Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 20
- Kernel Errors: 27
- Errors: 1
- Boot result: PASS
1 12:16:20.595857 lava-dispatcher, installed at version: 2023.08
2 12:16:20.596074 start: 0 validate
3 12:16:20.596218 Start time: 2023-10-27 12:16:20.596209+00:00 (UTC)
4 12:16:20.596337 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:16:20.596470 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:16:20.857046 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:16:20.857232 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:16:21.116597 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:16:21.117581 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:16:46.236415 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:16:46.237155 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:16:46.763177 validate duration: 26.17
14 12:16:46.763450 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:16:46.763549 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:16:46.763635 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:16:46.763763 Not decompressing ramdisk as can be used compressed.
18 12:16:46.763848 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 12:16:46.763912 saving as /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/ramdisk/rootfs.cpio.gz
20 12:16:46.763981 total size: 8181372 (7 MB)
21 12:16:49.805988 progress 0 % (0 MB)
22 12:16:49.811452 progress 5 % (0 MB)
23 12:16:49.813578 progress 10 % (0 MB)
24 12:16:49.815936 progress 15 % (1 MB)
25 12:16:49.818079 progress 20 % (1 MB)
26 12:16:49.820368 progress 25 % (1 MB)
27 12:16:49.822417 progress 30 % (2 MB)
28 12:16:49.824692 progress 35 % (2 MB)
29 12:16:49.826901 progress 40 % (3 MB)
30 12:16:49.829258 progress 45 % (3 MB)
31 12:16:49.831348 progress 50 % (3 MB)
32 12:16:49.833719 progress 55 % (4 MB)
33 12:16:49.835857 progress 60 % (4 MB)
34 12:16:49.838087 progress 65 % (5 MB)
35 12:16:49.840136 progress 70 % (5 MB)
36 12:16:49.842354 progress 75 % (5 MB)
37 12:16:49.844411 progress 80 % (6 MB)
38 12:16:49.846690 progress 85 % (6 MB)
39 12:16:49.848759 progress 90 % (7 MB)
40 12:16:49.850925 progress 95 % (7 MB)
41 12:16:49.853015 progress 100 % (7 MB)
42 12:16:49.853213 7 MB downloaded in 3.09 s (2.53 MB/s)
43 12:16:49.853364 end: 1.1.1 http-download (duration 00:00:03) [common]
45 12:16:49.853601 end: 1.1 download-retry (duration 00:00:03) [common]
46 12:16:49.853687 start: 1.2 download-retry (timeout 00:09:57) [common]
47 12:16:49.853770 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 12:16:49.853906 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:16:49.853983 saving as /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/kernel/Image
50 12:16:49.854043 total size: 49236480 (46 MB)
51 12:16:49.854105 No compression specified
52 12:16:49.855219 progress 0 % (0 MB)
53 12:16:49.867896 progress 5 % (2 MB)
54 12:16:49.880386 progress 10 % (4 MB)
55 12:16:49.892770 progress 15 % (7 MB)
56 12:16:49.905134 progress 20 % (9 MB)
57 12:16:49.917837 progress 25 % (11 MB)
58 12:16:49.930803 progress 30 % (14 MB)
59 12:16:49.943394 progress 35 % (16 MB)
60 12:16:49.956449 progress 40 % (18 MB)
61 12:16:49.969229 progress 45 % (21 MB)
62 12:16:49.981947 progress 50 % (23 MB)
63 12:16:49.994748 progress 55 % (25 MB)
64 12:16:50.007337 progress 60 % (28 MB)
65 12:16:50.020242 progress 65 % (30 MB)
66 12:16:50.033518 progress 70 % (32 MB)
67 12:16:50.046246 progress 75 % (35 MB)
68 12:16:50.059149 progress 80 % (37 MB)
69 12:16:50.071946 progress 85 % (39 MB)
70 12:16:50.084784 progress 90 % (42 MB)
71 12:16:50.097300 progress 95 % (44 MB)
72 12:16:50.109705 progress 100 % (46 MB)
73 12:16:50.109918 46 MB downloaded in 0.26 s (183.51 MB/s)
74 12:16:50.110071 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:16:50.110311 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:16:50.110403 start: 1.3 download-retry (timeout 00:09:57) [common]
78 12:16:50.110489 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 12:16:50.110635 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:16:50.110709 saving as /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/dtb/mt8192-asurada-spherion-r0.dtb
81 12:16:50.110775 total size: 47278 (0 MB)
82 12:16:50.110837 No compression specified
83 12:16:50.111967 progress 69 % (0 MB)
84 12:16:50.112249 progress 100 % (0 MB)
85 12:16:50.112408 0 MB downloaded in 0.00 s (27.65 MB/s)
86 12:16:50.112531 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:16:50.112756 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:16:50.112843 start: 1.4 download-retry (timeout 00:09:57) [common]
90 12:16:50.112927 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 12:16:50.113042 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:16:50.113114 saving as /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/modules/modules.tar
93 12:16:50.113176 total size: 8625084 (8 MB)
94 12:16:50.113239 Using unxz to decompress xz
95 12:16:50.117499 progress 0 % (0 MB)
96 12:16:50.139195 progress 5 % (0 MB)
97 12:16:50.161026 progress 10 % (0 MB)
98 12:16:50.187899 progress 15 % (1 MB)
99 12:16:50.213066 progress 20 % (1 MB)
100 12:16:50.238998 progress 25 % (2 MB)
101 12:16:50.265256 progress 30 % (2 MB)
102 12:16:50.292041 progress 35 % (2 MB)
103 12:16:50.317067 progress 40 % (3 MB)
104 12:16:50.341138 progress 45 % (3 MB)
105 12:16:50.367236 progress 50 % (4 MB)
106 12:16:50.392049 progress 55 % (4 MB)
107 12:16:50.416823 progress 60 % (4 MB)
108 12:16:50.441591 progress 65 % (5 MB)
109 12:16:50.466597 progress 70 % (5 MB)
110 12:16:50.490615 progress 75 % (6 MB)
111 12:16:50.516462 progress 80 % (6 MB)
112 12:16:50.546660 progress 85 % (7 MB)
113 12:16:50.573354 progress 90 % (7 MB)
114 12:16:50.598927 progress 95 % (7 MB)
115 12:16:50.622116 progress 100 % (8 MB)
116 12:16:50.626992 8 MB downloaded in 0.51 s (16.01 MB/s)
117 12:16:50.627332 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:16:50.627663 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:16:50.627762 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 12:16:50.627867 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 12:16:50.627949 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:16:50.628055 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 12:16:50.628304 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky
125 12:16:50.628444 makedir: /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin
126 12:16:50.628550 makedir: /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/tests
127 12:16:50.628649 makedir: /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/results
128 12:16:50.628764 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-add-keys
129 12:16:50.628915 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-add-sources
130 12:16:50.629043 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-background-process-start
131 12:16:50.629172 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-background-process-stop
132 12:16:50.629320 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-common-functions
133 12:16:50.629459 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-echo-ipv4
134 12:16:50.629586 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-install-packages
135 12:16:50.629709 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-installed-packages
136 12:16:50.629833 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-os-build
137 12:16:50.629957 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-probe-channel
138 12:16:50.630081 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-probe-ip
139 12:16:50.630206 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-target-ip
140 12:16:50.630330 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-target-mac
141 12:16:50.630451 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-target-storage
142 12:16:50.630580 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-test-case
143 12:16:50.630704 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-test-event
144 12:16:50.630827 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-test-feedback
145 12:16:50.630951 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-test-raise
146 12:16:50.631076 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-test-reference
147 12:16:50.631198 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-test-runner
148 12:16:50.631321 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-test-set
149 12:16:50.631447 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-test-shell
150 12:16:50.631574 Updating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-install-packages (oe)
151 12:16:50.631725 Updating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/bin/lava-installed-packages (oe)
152 12:16:50.631846 Creating /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/environment
153 12:16:50.631944 LAVA metadata
154 12:16:50.632019 - LAVA_JOB_ID=11893107
155 12:16:50.632084 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:16:50.632209 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 12:16:50.632290 skipped lava-vland-overlay
158 12:16:50.632363 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:16:50.632442 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 12:16:50.632505 skipped lava-multinode-overlay
161 12:16:50.632576 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:16:50.632658 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 12:16:50.632730 Loading test definitions
164 12:16:50.632817 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 12:16:50.632892 Using /lava-11893107 at stage 0
166 12:16:50.633204 uuid=11893107_1.5.2.3.1 testdef=None
167 12:16:50.633291 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:16:50.633376 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 12:16:50.633911 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:16:50.634127 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 12:16:50.634761 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:16:50.634990 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 12:16:50.635871 runner path: /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/0/tests/0_dmesg test_uuid 11893107_1.5.2.3.1
176 12:16:50.636029 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:16:50.636298 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:56) [common]
179 12:16:50.636369 Using /lava-11893107 at stage 1
180 12:16:50.636670 uuid=11893107_1.5.2.3.5 testdef=None
181 12:16:50.636759 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 12:16:50.636842 start: 1.5.2.3.6 test-overlay (timeout 00:09:56) [common]
183 12:16:50.637309 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 12:16:50.637526 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:56) [common]
186 12:16:50.638642 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 12:16:50.638870 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:56) [common]
189 12:16:50.639488 runner path: /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/1/tests/1_bootrr test_uuid 11893107_1.5.2.3.5
190 12:16:50.639643 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 12:16:50.639848 Creating lava-test-runner.conf files
193 12:16:50.639911 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/0 for stage 0
194 12:16:50.640001 - 0_dmesg
195 12:16:50.640081 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893107/lava-overlay-_hl74pky/lava-11893107/1 for stage 1
196 12:16:50.640171 - 1_bootrr
197 12:16:50.640273 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 12:16:50.640356 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
199 12:16:50.648327 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 12:16:50.648435 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
201 12:16:50.648522 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 12:16:50.648606 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 12:16:50.648689 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
204 12:16:50.897719 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 12:16:50.898109 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
206 12:16:50.898228 extracting modules file /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893107/extract-overlay-ramdisk-85u381zh/ramdisk
207 12:16:51.117744 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 12:16:51.117916 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
209 12:16:51.118012 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893107/compress-overlay-oar99q9b/overlay-1.5.2.4.tar.gz to ramdisk
210 12:16:51.118086 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893107/compress-overlay-oar99q9b/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893107/extract-overlay-ramdisk-85u381zh/ramdisk
211 12:16:51.126450 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 12:16:51.126563 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
213 12:16:51.126652 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 12:16:51.126740 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
215 12:16:51.126816 Building ramdisk /var/lib/lava/dispatcher/tmp/11893107/extract-overlay-ramdisk-85u381zh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893107/extract-overlay-ramdisk-85u381zh/ramdisk
216 12:16:51.538414 >> 145282 blocks
217 12:16:53.858647 rename /var/lib/lava/dispatcher/tmp/11893107/extract-overlay-ramdisk-85u381zh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/ramdisk/ramdisk.cpio.gz
218 12:16:53.859100 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 12:16:53.859222 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
220 12:16:53.859324 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
221 12:16:53.859433 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/kernel/Image'
222 12:17:06.216227 Returned 0 in 12 seconds
223 12:17:06.317237 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/kernel/image.itb
224 12:17:06.745979 output: FIT description: Kernel Image image with one or more FDT blobs
225 12:17:06.746403 output: Created: Fri Oct 27 13:17:06 2023
226 12:17:06.746481 output: Image 0 (kernel-1)
227 12:17:06.746546 output: Description:
228 12:17:06.746608 output: Created: Fri Oct 27 13:17:06 2023
229 12:17:06.746668 output: Type: Kernel Image
230 12:17:06.746728 output: Compression: lzma compressed
231 12:17:06.746786 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
232 12:17:06.746940 output: Architecture: AArch64
233 12:17:06.747050 output: OS: Linux
234 12:17:06.747112 output: Load Address: 0x00000000
235 12:17:06.747172 output: Entry Point: 0x00000000
236 12:17:06.747229 output: Hash algo: crc32
237 12:17:06.747288 output: Hash value: d33b93ae
238 12:17:06.747344 output: Image 1 (fdt-1)
239 12:17:06.747401 output: Description: mt8192-asurada-spherion-r0
240 12:17:06.747456 output: Created: Fri Oct 27 13:17:06 2023
241 12:17:06.747509 output: Type: Flat Device Tree
242 12:17:06.747561 output: Compression: uncompressed
243 12:17:06.747613 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 12:17:06.747666 output: Architecture: AArch64
245 12:17:06.747718 output: Hash algo: crc32
246 12:17:06.747769 output: Hash value: cc4352de
247 12:17:06.747821 output: Image 2 (ramdisk-1)
248 12:17:06.747873 output: Description: unavailable
249 12:17:06.747925 output: Created: Fri Oct 27 13:17:06 2023
250 12:17:06.747977 output: Type: RAMDisk Image
251 12:17:06.748029 output: Compression: Unknown Compression
252 12:17:06.748081 output: Data Size: 21385662 Bytes = 20884.44 KiB = 20.39 MiB
253 12:17:06.748133 output: Architecture: AArch64
254 12:17:06.748219 output: OS: Linux
255 12:17:06.748300 output: Load Address: unavailable
256 12:17:06.748352 output: Entry Point: unavailable
257 12:17:06.748405 output: Hash algo: crc32
258 12:17:06.748456 output: Hash value: ae557d89
259 12:17:06.748508 output: Default Configuration: 'conf-1'
260 12:17:06.748559 output: Configuration 0 (conf-1)
261 12:17:06.748611 output: Description: mt8192-asurada-spherion-r0
262 12:17:06.748663 output: Kernel: kernel-1
263 12:17:06.748758 output: Init Ramdisk: ramdisk-1
264 12:17:06.748824 output: FDT: fdt-1
265 12:17:06.748876 output: Loadables: kernel-1
266 12:17:06.748927 output:
267 12:17:06.749130 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 12:17:06.749226 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 12:17:06.749327 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 12:17:06.749417 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:40) [common]
271 12:17:06.749496 No LXC device requested
272 12:17:06.749577 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 12:17:06.749724 start: 1.7 deploy-device-env (timeout 00:09:40) [common]
274 12:17:06.749803 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 12:17:06.749873 Checking files for TFTP limit of 4294967296 bytes.
276 12:17:06.750430 end: 1 tftp-deploy (duration 00:00:20) [common]
277 12:17:06.750546 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 12:17:06.750666 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 12:17:06.750798 substitutions:
280 12:17:06.750863 - {DTB}: 11893107/tftp-deploy-_8h5mw6e/dtb/mt8192-asurada-spherion-r0.dtb
281 12:17:06.750942 - {INITRD}: 11893107/tftp-deploy-_8h5mw6e/ramdisk/ramdisk.cpio.gz
282 12:17:06.751012 - {KERNEL}: 11893107/tftp-deploy-_8h5mw6e/kernel/Image
283 12:17:06.751116 - {LAVA_MAC}: None
284 12:17:06.751193 - {PRESEED_CONFIG}: None
285 12:17:06.751251 - {PRESEED_LOCAL}: None
286 12:17:06.751307 - {RAMDISK}: 11893107/tftp-deploy-_8h5mw6e/ramdisk/ramdisk.cpio.gz
287 12:17:06.751362 - {ROOT_PART}: None
288 12:17:06.751416 - {ROOT}: None
289 12:17:06.751470 - {SERVER_IP}: 192.168.201.1
290 12:17:06.751523 - {TEE}: None
291 12:17:06.751576 Parsed boot commands:
292 12:17:06.751629 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 12:17:06.751804 Parsed boot commands: tftpboot 192.168.201.1 11893107/tftp-deploy-_8h5mw6e/kernel/image.itb 11893107/tftp-deploy-_8h5mw6e/kernel/cmdline
294 12:17:06.751890 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 12:17:06.751978 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 12:17:06.752066 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 12:17:06.752149 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 12:17:06.752275 Not connected, no need to disconnect.
299 12:17:06.752351 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 12:17:06.752437 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 12:17:06.752503 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
302 12:17:06.756627 Setting prompt string to ['lava-test: # ']
303 12:17:06.756998 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 12:17:06.757107 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 12:17:06.757207 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 12:17:06.757526 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 12:17:06.757747 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
308 12:17:11.893024 >> Command sent successfully.
309 12:17:11.895426 Returned 0 in 5 seconds
310 12:17:11.995835 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 12:17:11.996339 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 12:17:11.996488 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 12:17:11.996614 Setting prompt string to 'Starting depthcharge on Spherion...'
315 12:17:11.996711 Changing prompt to 'Starting depthcharge on Spherion...'
316 12:17:11.996815 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 12:17:11.997191 [Enter `^Ec?' for help]
318 12:17:12.174464
319 12:17:12.174659
320 12:17:12.174766 F0: 102B 0000
321 12:17:12.174867
322 12:17:12.174964 F3: 1001 0000 [0200]
323 12:17:12.175056
324 12:17:12.177822 F3: 1001 0000
325 12:17:12.177934
326 12:17:12.178031 F7: 102D 0000
327 12:17:12.178126
328 12:17:12.181491 F1: 0000 0000
329 12:17:12.181602
330 12:17:12.181701 V0: 0000 0000 [0001]
331 12:17:12.181795
332 12:17:12.181887 00: 0007 8000
333 12:17:12.184982
334 12:17:12.185091 01: 0000 0000
335 12:17:12.185189
336 12:17:12.185282 BP: 0C00 0209 [0000]
337 12:17:12.185374
338 12:17:12.188549 G0: 1182 0000
339 12:17:12.188657
340 12:17:12.188753 EC: 0000 0021 [4000]
341 12:17:12.188847
342 12:17:12.192257 S7: 0000 0000 [0000]
343 12:17:12.192346
344 12:17:12.192413 CC: 0000 0000 [0001]
345 12:17:12.192475
346 12:17:12.195074 T0: 0000 0040 [010F]
347 12:17:12.195184
348 12:17:12.195279 Jump to BL
349 12:17:12.195370
350 12:17:12.221475
351 12:17:12.221589
352 12:17:12.221686
353 12:17:12.229363 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 12:17:12.232874 ARM64: Exception handlers installed.
355 12:17:12.236571 ARM64: Testing exception
356 12:17:12.236683 ARM64: Done test exception
357 12:17:12.247484 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 12:17:12.254651 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 12:17:12.261474 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 12:17:12.272135 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 12:17:12.278563 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 12:17:12.288885 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 12:17:12.299856 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 12:17:12.306383 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 12:17:12.324121 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 12:17:12.327526 WDT: Last reset was cold boot
367 12:17:12.330810 SPI1(PAD0) initialized at 2873684 Hz
368 12:17:12.334316 SPI5(PAD0) initialized at 992727 Hz
369 12:17:12.337552 VBOOT: Loading verstage.
370 12:17:12.344420 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 12:17:12.347494 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 12:17:12.351163 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 12:17:12.354169 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 12:17:12.361539 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 12:17:12.368278 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 12:17:12.379038 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
377 12:17:12.379123
378 12:17:12.379190
379 12:17:12.389043 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 12:17:12.392488 ARM64: Exception handlers installed.
381 12:17:12.395661 ARM64: Testing exception
382 12:17:12.395748 ARM64: Done test exception
383 12:17:12.402249 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 12:17:12.405617 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 12:17:12.420381 Probing TPM: . done!
386 12:17:12.420465 TPM ready after 0 ms
387 12:17:12.427128 Connected to device vid:did:rid of 1ae0:0028:00
388 12:17:12.433937 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
389 12:17:12.482225 Initialized TPM device CR50 revision 0
390 12:17:12.497891 tlcl_send_startup: Startup return code is 0
391 12:17:12.498008 TPM: setup succeeded
392 12:17:12.508309 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 12:17:12.517458 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 12:17:12.527142 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 12:17:12.535941 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 12:17:12.539036 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 12:17:12.543414 in-header: 03 07 00 00 08 00 00 00
398 12:17:12.546663 in-data: aa e4 47 04 13 02 00 00
399 12:17:12.550043 Chrome EC: UHEPI supported
400 12:17:12.556632 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 12:17:12.569856 in-header: 03 95 00 00 08 00 00 00
402 12:17:12.573577 in-data: 18 20 20 08 00 00 00 00
403 12:17:12.573692 Phase 1
404 12:17:12.576845 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 12:17:12.584266 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 12:17:12.591880 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 12:17:12.591989 Recovery requested (1009000e)
408 12:17:12.602042 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 12:17:12.607661 tlcl_extend: response is 0
410 12:17:12.616715 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 12:17:12.622700 tlcl_extend: response is 0
412 12:17:12.629205 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 12:17:12.650134 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
414 12:17:12.657069 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 12:17:12.657183
416 12:17:12.657281
417 12:17:12.664578 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 12:17:12.668062 ARM64: Exception handlers installed.
419 12:17:12.671359 ARM64: Testing exception
420 12:17:12.674762 ARM64: Done test exception
421 12:17:12.694926 pmic_efuse_setting: Set efuses in 11 msecs
422 12:17:12.698117 pmwrap_interface_init: Select PMIF_VLD_RDY
423 12:17:12.704934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 12:17:12.708026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 12:17:12.714605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 12:17:12.717919 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 12:17:12.724678 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 12:17:12.728293 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 12:17:12.731254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 12:17:12.738054 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 12:17:12.741624 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 12:17:12.748000 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 12:17:12.751285 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 12:17:12.754808 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 12:17:12.762158 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 12:17:12.766107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 12:17:12.773191 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 12:17:12.776969 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 12:17:12.783995 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 12:17:12.791486 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 12:17:12.794967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 12:17:12.802202 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 12:17:12.805872 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 12:17:12.813149 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 12:17:12.816837 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 12:17:12.824211 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 12:17:12.828302 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 12:17:12.835700 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 12:17:12.839731 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 12:17:12.843153 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 12:17:12.850887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 12:17:12.854329 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 12:17:12.857989 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 12:17:12.865423 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 12:17:12.868970 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 12:17:12.872792 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 12:17:12.880055 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 12:17:12.883763 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 12:17:12.890794 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 12:17:12.894110 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 12:17:12.897859 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 12:17:12.901480 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 12:17:12.908743 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 12:17:12.912415 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 12:17:12.916157 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 12:17:12.920133 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 12:17:12.923482 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 12:17:12.930556 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 12:17:12.934397 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 12:17:12.937786 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 12:17:12.941288 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 12:17:12.945232 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 12:17:12.948837 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 12:17:12.956125 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 12:17:12.967059 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 12:17:12.970839 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 12:17:12.978060 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 12:17:12.988896 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 12:17:12.992629 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 12:17:12.995959 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 12:17:12.999247 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 12:17:13.008257 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
483 12:17:13.012028 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 12:17:13.019623 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 12:17:13.022757 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 12:17:13.031900 [RTC]rtc_get_frequency_meter,154: input=15, output=764
487 12:17:13.042038 [RTC]rtc_get_frequency_meter,154: input=23, output=949
488 12:17:13.051396 [RTC]rtc_get_frequency_meter,154: input=19, output=857
489 12:17:13.060470 [RTC]rtc_get_frequency_meter,154: input=17, output=810
490 12:17:13.070286 [RTC]rtc_get_frequency_meter,154: input=16, output=787
491 12:17:13.079849 [RTC]rtc_get_frequency_meter,154: input=16, output=788
492 12:17:13.089786 [RTC]rtc_get_frequency_meter,154: input=17, output=811
493 12:17:13.093372 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 12:17:13.097345 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 12:17:13.104296 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 12:17:13.107594 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 12:17:13.111388 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 12:17:13.115083 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 12:17:13.118670 ADC[4]: Raw value=669695 ID=5
500 12:17:13.122369 ADC[3]: Raw value=212917 ID=1
501 12:17:13.122453 RAM Code: 0x51
502 12:17:13.126280 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 12:17:13.133554 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 12:17:13.140461 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
505 12:17:13.144022 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
506 12:17:13.147620 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 12:17:13.151853 in-header: 03 07 00 00 08 00 00 00
508 12:17:13.155283 in-data: aa e4 47 04 13 02 00 00
509 12:17:13.158876 Chrome EC: UHEPI supported
510 12:17:13.165943 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 12:17:13.169603 in-header: 03 95 00 00 08 00 00 00
512 12:17:13.173210 in-data: 18 20 20 08 00 00 00 00
513 12:17:13.176832 MRC: failed to locate region type 0.
514 12:17:13.180226 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 12:17:13.183886 DRAM-K: Running full calibration
516 12:17:13.191038 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
517 12:17:13.191122 header.status = 0x0
518 12:17:13.194619 header.version = 0x6 (expected: 0x6)
519 12:17:13.198372 header.size = 0xd00 (expected: 0xd00)
520 12:17:13.201960 header.flags = 0x0
521 12:17:13.205486 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 12:17:13.225452 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
523 12:17:13.232775 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 12:17:13.236194 dram_init: ddr_geometry: 0
525 12:17:13.236278 [EMI] MDL number = 0
526 12:17:13.240054 [EMI] Get MDL freq = 0
527 12:17:13.240147 dram_init: ddr_type: 0
528 12:17:13.243750 is_discrete_lpddr4: 1
529 12:17:13.247743 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 12:17:13.247827
531 12:17:13.247893
532 12:17:13.247957 [Bian_co] ETT version 0.0.0.1
533 12:17:13.255230 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
534 12:17:13.255314
535 12:17:13.258642 dramc_set_vcore_voltage set vcore to 650000
536 12:17:13.258725 Read voltage for 800, 4
537 12:17:13.262456 Vio18 = 0
538 12:17:13.262539 Vcore = 650000
539 12:17:13.262607 Vdram = 0
540 12:17:13.262669 Vddq = 0
541 12:17:13.265922 Vmddr = 0
542 12:17:13.266005 dram_init: config_dvfs: 1
543 12:17:13.273139 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 12:17:13.276745 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 12:17:13.280600 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 12:17:13.283872 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 12:17:13.287897 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 12:17:13.291710 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 12:17:13.295243 MEM_TYPE=3, freq_sel=18
550 12:17:13.299150 sv_algorithm_assistance_LP4_1600
551 12:17:13.302642 ============ PULL DRAM RESETB DOWN ============
552 12:17:13.306281 ========== PULL DRAM RESETB DOWN end =========
553 12:17:13.310096 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 12:17:13.313526 ===================================
555 12:17:13.317408 LPDDR4 DRAM CONFIGURATION
556 12:17:13.321047 ===================================
557 12:17:13.321130 EX_ROW_EN[0] = 0x0
558 12:17:13.324817 EX_ROW_EN[1] = 0x0
559 12:17:13.324900 LP4Y_EN = 0x0
560 12:17:13.328398 WORK_FSP = 0x0
561 12:17:13.328482 WL = 0x2
562 12:17:13.332084 RL = 0x2
563 12:17:13.332167 BL = 0x2
564 12:17:13.335951 RPST = 0x0
565 12:17:13.336034 RD_PRE = 0x0
566 12:17:13.336100 WR_PRE = 0x1
567 12:17:13.340120 WR_PST = 0x0
568 12:17:13.340211 DBI_WR = 0x0
569 12:17:13.343092 DBI_RD = 0x0
570 12:17:13.343175 OTF = 0x1
571 12:17:13.346915 ===================================
572 12:17:13.349959 ===================================
573 12:17:13.353443 ANA top config
574 12:17:13.356680 ===================================
575 12:17:13.356796 DLL_ASYNC_EN = 0
576 12:17:13.360269 ALL_SLAVE_EN = 1
577 12:17:13.363306 NEW_RANK_MODE = 1
578 12:17:13.366681 DLL_IDLE_MODE = 1
579 12:17:13.366792 LP45_APHY_COMB_EN = 1
580 12:17:13.370225 TX_ODT_DIS = 1
581 12:17:13.374135 NEW_8X_MODE = 1
582 12:17:13.377758 ===================================
583 12:17:13.381376 ===================================
584 12:17:13.381460 data_rate = 1600
585 12:17:13.385080 CKR = 1
586 12:17:13.388615 DQ_P2S_RATIO = 8
587 12:17:13.391988 ===================================
588 12:17:13.395607 CA_P2S_RATIO = 8
589 12:17:13.398754 DQ_CA_OPEN = 0
590 12:17:13.398838 DQ_SEMI_OPEN = 0
591 12:17:13.401980 CA_SEMI_OPEN = 0
592 12:17:13.405273 CA_FULL_RATE = 0
593 12:17:13.408635 DQ_CKDIV4_EN = 1
594 12:17:13.412584 CA_CKDIV4_EN = 1
595 12:17:13.412667 CA_PREDIV_EN = 0
596 12:17:13.415994 PH8_DLY = 0
597 12:17:13.419718 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 12:17:13.423179 DQ_AAMCK_DIV = 4
599 12:17:13.423263 CA_AAMCK_DIV = 4
600 12:17:13.426892 CA_ADMCK_DIV = 4
601 12:17:13.429947 DQ_TRACK_CA_EN = 0
602 12:17:13.433353 CA_PICK = 800
603 12:17:13.436693 CA_MCKIO = 800
604 12:17:13.439953 MCKIO_SEMI = 0
605 12:17:13.443666 PLL_FREQ = 3068
606 12:17:13.443750 DQ_UI_PI_RATIO = 32
607 12:17:13.447639 CA_UI_PI_RATIO = 0
608 12:17:13.450987 ===================================
609 12:17:13.454883 ===================================
610 12:17:13.458623 memory_type:LPDDR4
611 12:17:13.458712 GP_NUM : 10
612 12:17:13.462380 SRAM_EN : 1
613 12:17:13.462464 MD32_EN : 0
614 12:17:13.465979 ===================================
615 12:17:13.469147 [ANA_INIT] >>>>>>>>>>>>>>
616 12:17:13.472938 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 12:17:13.476702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 12:17:13.476815 ===================================
619 12:17:13.479791 data_rate = 1600,PCW = 0X7600
620 12:17:13.483327 ===================================
621 12:17:13.486903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 12:17:13.493700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 12:17:13.499871 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 12:17:13.503171 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 12:17:13.506909 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 12:17:13.510088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 12:17:13.513249 [ANA_INIT] flow start
628 12:17:13.513360 [ANA_INIT] PLL >>>>>>>>
629 12:17:13.516612 [ANA_INIT] PLL <<<<<<<<
630 12:17:13.519896 [ANA_INIT] MIDPI >>>>>>>>
631 12:17:13.520012 [ANA_INIT] MIDPI <<<<<<<<
632 12:17:13.523650 [ANA_INIT] DLL >>>>>>>>
633 12:17:13.526556 [ANA_INIT] flow end
634 12:17:13.530207 ============ LP4 DIFF to SE enter ============
635 12:17:13.533417 ============ LP4 DIFF to SE exit ============
636 12:17:13.536648 [ANA_INIT] <<<<<<<<<<<<<
637 12:17:13.540051 [Flow] Enable top DCM control >>>>>
638 12:17:13.543546 [Flow] Enable top DCM control <<<<<
639 12:17:13.546670 Enable DLL master slave shuffle
640 12:17:13.550223 ==============================================================
641 12:17:13.553387 Gating Mode config
642 12:17:13.559852 ==============================================================
643 12:17:13.559937 Config description:
644 12:17:13.570032 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 12:17:13.576514 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 12:17:13.579850 SELPH_MODE 0: By rank 1: By Phase
647 12:17:13.586527 ==============================================================
648 12:17:13.589964 GAT_TRACK_EN = 1
649 12:17:13.593316 RX_GATING_MODE = 2
650 12:17:13.596488 RX_GATING_TRACK_MODE = 2
651 12:17:13.599903 SELPH_MODE = 1
652 12:17:13.603478 PICG_EARLY_EN = 1
653 12:17:13.603562 VALID_LAT_VALUE = 1
654 12:17:13.610040 ==============================================================
655 12:17:13.613373 Enter into Gating configuration >>>>
656 12:17:13.616708 Exit from Gating configuration <<<<
657 12:17:13.620017 Enter into DVFS_PRE_config >>>>>
658 12:17:13.629880 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 12:17:13.633352 Exit from DVFS_PRE_config <<<<<
660 12:17:13.636952 Enter into PICG configuration >>>>
661 12:17:13.640081 Exit from PICG configuration <<<<
662 12:17:13.643419 [RX_INPUT] configuration >>>>>
663 12:17:13.646715 [RX_INPUT] configuration <<<<<
664 12:17:13.650400 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 12:17:13.656658 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 12:17:13.663462 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 12:17:13.670138 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 12:17:13.676804 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 12:17:13.679919 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 12:17:13.686669 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 12:17:13.690282 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 12:17:13.693231 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 12:17:13.696689 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 12:17:13.703453 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 12:17:13.706613 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 12:17:13.710105 ===================================
677 12:17:13.713431 LPDDR4 DRAM CONFIGURATION
678 12:17:13.716675 ===================================
679 12:17:13.716784 EX_ROW_EN[0] = 0x0
680 12:17:13.720023 EX_ROW_EN[1] = 0x0
681 12:17:13.720129 LP4Y_EN = 0x0
682 12:17:13.723238 WORK_FSP = 0x0
683 12:17:13.723344 WL = 0x2
684 12:17:13.726609 RL = 0x2
685 12:17:13.726715 BL = 0x2
686 12:17:13.730039 RPST = 0x0
687 12:17:13.730145 RD_PRE = 0x0
688 12:17:13.733609 WR_PRE = 0x1
689 12:17:13.733719 WR_PST = 0x0
690 12:17:13.736774 DBI_WR = 0x0
691 12:17:13.736881 DBI_RD = 0x0
692 12:17:13.739875 OTF = 0x1
693 12:17:13.744027 ===================================
694 12:17:13.746775 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 12:17:13.750148 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 12:17:13.756671 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:17:13.759965 ===================================
698 12:17:13.760062 LPDDR4 DRAM CONFIGURATION
699 12:17:13.763551 ===================================
700 12:17:13.766711 EX_ROW_EN[0] = 0x10
701 12:17:13.769815 EX_ROW_EN[1] = 0x0
702 12:17:13.769896 LP4Y_EN = 0x0
703 12:17:13.773123 WORK_FSP = 0x0
704 12:17:13.773205 WL = 0x2
705 12:17:13.776703 RL = 0x2
706 12:17:13.776786 BL = 0x2
707 12:17:13.779940 RPST = 0x0
708 12:17:13.780022 RD_PRE = 0x0
709 12:17:13.783282 WR_PRE = 0x1
710 12:17:13.783379 WR_PST = 0x0
711 12:17:13.786563 DBI_WR = 0x0
712 12:17:13.786661 DBI_RD = 0x0
713 12:17:13.789884 OTF = 0x1
714 12:17:13.793254 ===================================
715 12:17:13.799983 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 12:17:13.803447 nWR fixed to 40
717 12:17:13.803530 [ModeRegInit_LP4] CH0 RK0
718 12:17:13.806571 [ModeRegInit_LP4] CH0 RK1
719 12:17:13.810147 [ModeRegInit_LP4] CH1 RK0
720 12:17:13.813753 [ModeRegInit_LP4] CH1 RK1
721 12:17:13.813836 match AC timing 12
722 12:17:13.820142 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
723 12:17:13.823629 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 12:17:13.826787 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 12:17:13.833427 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 12:17:13.836750 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 12:17:13.836833 [EMI DOE] emi_dcm 0
728 12:17:13.843686 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 12:17:13.843769 ==
730 12:17:13.846686 Dram Type= 6, Freq= 0, CH_0, rank 0
731 12:17:13.850107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
732 12:17:13.850191 ==
733 12:17:13.856772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 12:17:13.860116 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 12:17:13.870132 [CA 0] Center 37 (7~68) winsize 62
736 12:17:13.873459 [CA 1] Center 37 (7~68) winsize 62
737 12:17:13.877046 [CA 2] Center 35 (5~66) winsize 62
738 12:17:13.880118 [CA 3] Center 35 (5~66) winsize 62
739 12:17:13.883640 [CA 4] Center 34 (4~65) winsize 62
740 12:17:13.886876 [CA 5] Center 33 (3~64) winsize 62
741 12:17:13.886960
742 12:17:13.890102 [CmdBusTrainingLP45] Vref(ca) range 1: 32
743 12:17:13.890185
744 12:17:13.893615 [CATrainingPosCal] consider 1 rank data
745 12:17:13.896817 u2DelayCellTimex100 = 270/100 ps
746 12:17:13.900105 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
747 12:17:13.903432 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
748 12:17:13.910163 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
749 12:17:13.913531 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
750 12:17:13.916791 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
751 12:17:13.920210 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 12:17:13.920294
753 12:17:13.923600 CA PerBit enable=1, Macro0, CA PI delay=33
754 12:17:13.923683
755 12:17:13.926652 [CBTSetCACLKResult] CA Dly = 33
756 12:17:13.926736 CS Dly: 5 (0~36)
757 12:17:13.930045 ==
758 12:17:13.930129 Dram Type= 6, Freq= 0, CH_0, rank 1
759 12:17:13.936711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
760 12:17:13.936796 ==
761 12:17:13.940120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 12:17:13.946883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 12:17:13.956328 [CA 0] Center 37 (7~68) winsize 62
764 12:17:13.959496 [CA 1] Center 37 (6~68) winsize 63
765 12:17:13.962777 [CA 2] Center 35 (4~66) winsize 63
766 12:17:13.966019 [CA 3] Center 34 (4~65) winsize 62
767 12:17:13.969395 [CA 4] Center 33 (3~64) winsize 62
768 12:17:13.972730 [CA 5] Center 33 (3~64) winsize 62
769 12:17:13.972844
770 12:17:13.976044 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 12:17:13.976165
772 12:17:13.979626 [CATrainingPosCal] consider 2 rank data
773 12:17:13.982807 u2DelayCellTimex100 = 270/100 ps
774 12:17:13.985982 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 12:17:13.989497 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 12:17:13.996068 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
777 12:17:13.999416 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
778 12:17:14.002724 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
779 12:17:14.006051 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 12:17:14.006135
781 12:17:14.009725 CA PerBit enable=1, Macro0, CA PI delay=33
782 12:17:14.009809
783 12:17:14.012720 [CBTSetCACLKResult] CA Dly = 33
784 12:17:14.012804 CS Dly: 6 (0~38)
785 12:17:14.012871
786 12:17:14.016086 ----->DramcWriteLeveling(PI) begin...
787 12:17:14.019531 ==
788 12:17:14.023118 Dram Type= 6, Freq= 0, CH_0, rank 0
789 12:17:14.026573 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
790 12:17:14.026657 ==
791 12:17:14.030348 Write leveling (Byte 0): 29 => 29
792 12:17:14.030432 Write leveling (Byte 1): 30 => 30
793 12:17:14.033781 DramcWriteLeveling(PI) end<-----
794 12:17:14.033864
795 12:17:14.033930 ==
796 12:17:14.037425 Dram Type= 6, Freq= 0, CH_0, rank 0
797 12:17:14.041122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
798 12:17:14.044075 ==
799 12:17:14.044157 [Gating] SW mode calibration
800 12:17:14.051103 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 12:17:14.058355 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 12:17:14.061742 0 6 0 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 0)
803 12:17:14.065027 0 6 4 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
804 12:17:14.071402 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:17:14.074829 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:17:14.078081 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:17:14.084979 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:17:14.088043 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:17:14.091418 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:17:14.098379 0 7 0 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
811 12:17:14.101554 0 7 4 | B1->B0 | 3b3b 3f3f | 0 0 | (0 0) (0 0)
812 12:17:14.104796 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
813 12:17:14.111537 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
814 12:17:14.114956 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
815 12:17:14.118179 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
816 12:17:14.124638 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
817 12:17:14.128100 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
818 12:17:14.131618 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
819 12:17:14.137966 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
820 12:17:14.141466 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
821 12:17:14.144817 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
822 12:17:14.151685 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
823 12:17:14.154868 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
824 12:17:14.157942 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
825 12:17:14.161505 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
826 12:17:14.168390 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
827 12:17:14.171551 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
828 12:17:14.174792 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
829 12:17:14.181471 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
830 12:17:14.184709 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 12:17:14.188301 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 12:17:14.194805 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 12:17:14.198166 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 12:17:14.201584 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:17:14.204863 Total UI for P1: 0, mck2ui 16
836 12:17:14.208167 best dqsien dly found for B0: ( 0, 9, 30)
837 12:17:14.211653 Total UI for P1: 0, mck2ui 16
838 12:17:14.215057 best dqsien dly found for B1: ( 0, 9, 30)
839 12:17:14.218132 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
840 12:17:14.221604 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
841 12:17:14.221685
842 12:17:14.228274 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
843 12:17:14.231744 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
844 12:17:14.231826 [Gating] SW calibration Done
845 12:17:14.234913 ==
846 12:17:14.238498 Dram Type= 6, Freq= 0, CH_0, rank 0
847 12:17:14.241610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 12:17:14.241692 ==
849 12:17:14.241757 RX Vref Scan: 0
850 12:17:14.241818
851 12:17:14.245184 RX Vref 0 -> 0, step: 1
852 12:17:14.245266
853 12:17:14.248471 RX Delay -130 -> 252, step: 16
854 12:17:14.251756 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
855 12:17:14.255260 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
856 12:17:14.258380 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
857 12:17:14.265257 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
858 12:17:14.268444 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
859 12:17:14.271813 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
860 12:17:14.275054 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
861 12:17:14.278440 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
862 12:17:14.284983 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
863 12:17:14.288476 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
864 12:17:14.291899 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
865 12:17:14.295064 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
866 12:17:14.298543 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
867 12:17:14.305444 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
868 12:17:14.308701 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
869 12:17:14.311806 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
870 12:17:14.311889 ==
871 12:17:14.315314 Dram Type= 6, Freq= 0, CH_0, rank 0
872 12:17:14.318537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 12:17:14.321765 ==
874 12:17:14.321848 DQS Delay:
875 12:17:14.321914 DQS0 = 0, DQS1 = 0
876 12:17:14.325205 DQM Delay:
877 12:17:14.325288 DQM0 = 84, DQM1 = 74
878 12:17:14.325355 DQ Delay:
879 12:17:14.328665 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
880 12:17:14.332239 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
881 12:17:14.335422 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
882 12:17:14.338467 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
883 12:17:14.338550
884 12:17:14.341671
885 12:17:14.341754 ==
886 12:17:14.345040 Dram Type= 6, Freq= 0, CH_0, rank 0
887 12:17:14.348220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
888 12:17:14.348304 ==
889 12:17:14.348370
890 12:17:14.348431
891 12:17:14.351544 TX Vref Scan disable
892 12:17:14.351628 == TX Byte 0 ==
893 12:17:14.358266 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
894 12:17:14.361710 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
895 12:17:14.361794 == TX Byte 1 ==
896 12:17:14.368453 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
897 12:17:14.371793 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
898 12:17:14.371876 ==
899 12:17:14.375044 Dram Type= 6, Freq= 0, CH_0, rank 0
900 12:17:14.378237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 12:17:14.378321 ==
902 12:17:14.391598 TX Vref=22, minBit 0, minWin=27, winSum=443
903 12:17:14.394891 TX Vref=24, minBit 0, minWin=27, winSum=447
904 12:17:14.398320 TX Vref=26, minBit 4, minWin=27, winSum=450
905 12:17:14.401601 TX Vref=28, minBit 4, minWin=27, winSum=453
906 12:17:14.405295 TX Vref=30, minBit 0, minWin=28, winSum=456
907 12:17:14.408131 TX Vref=32, minBit 5, minWin=27, winSum=451
908 12:17:14.414970 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
909 12:17:14.415088
910 12:17:14.418391 Final TX Range 1 Vref 30
911 12:17:14.418502
912 12:17:14.418598 ==
913 12:17:14.422399 Dram Type= 6, Freq= 0, CH_0, rank 0
914 12:17:14.425749 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
915 12:17:14.425858 ==
916 12:17:14.425948
917 12:17:14.426041
918 12:17:14.429107 TX Vref Scan disable
919 12:17:14.432099 == TX Byte 0 ==
920 12:17:14.435458 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
921 12:17:14.439039 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
922 12:17:14.442098 == TX Byte 1 ==
923 12:17:14.445600 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
924 12:17:14.448846 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
925 12:17:14.448958
926 12:17:14.452222 [DATLAT]
927 12:17:14.452310 Freq=800, CH0 RK0
928 12:17:14.452376
929 12:17:14.455792 DATLAT Default: 0xa
930 12:17:14.455875 0, 0xFFFF, sum = 0
931 12:17:14.459140 1, 0xFFFF, sum = 0
932 12:17:14.459227 2, 0xFFFF, sum = 0
933 12:17:14.462316 3, 0xFFFF, sum = 0
934 12:17:14.462400 4, 0xFFFF, sum = 0
935 12:17:14.465599 5, 0xFFFF, sum = 0
936 12:17:14.465684 6, 0xFFFF, sum = 0
937 12:17:14.469053 7, 0xFFFF, sum = 0
938 12:17:14.469137 8, 0x0, sum = 1
939 12:17:14.472147 9, 0x0, sum = 2
940 12:17:14.472237 10, 0x0, sum = 3
941 12:17:14.475753 11, 0x0, sum = 4
942 12:17:14.475836 best_step = 9
943 12:17:14.475901
944 12:17:14.475965 ==
945 12:17:14.479135 Dram Type= 6, Freq= 0, CH_0, rank 0
946 12:17:14.482408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
947 12:17:14.482491 ==
948 12:17:14.486043 RX Vref Scan: 1
949 12:17:14.486126
950 12:17:14.489158 Set Vref Range= 32 -> 127
951 12:17:14.489239
952 12:17:14.489305 RX Vref 32 -> 127, step: 1
953 12:17:14.489366
954 12:17:14.492404 RX Delay -111 -> 252, step: 8
955 12:17:14.492487
956 12:17:14.495914 Set Vref, RX VrefLevel [Byte0]: 32
957 12:17:14.499113 [Byte1]: 32
958 12:17:14.502476
959 12:17:14.502559 Set Vref, RX VrefLevel [Byte0]: 33
960 12:17:14.505834 [Byte1]: 33
961 12:17:14.510248
962 12:17:14.510330 Set Vref, RX VrefLevel [Byte0]: 34
963 12:17:14.513459 [Byte1]: 34
964 12:17:14.517692
965 12:17:14.517774 Set Vref, RX VrefLevel [Byte0]: 35
966 12:17:14.521095 [Byte1]: 35
967 12:17:14.525320
968 12:17:14.525407 Set Vref, RX VrefLevel [Byte0]: 36
969 12:17:14.528774 [Byte1]: 36
970 12:17:14.532971
971 12:17:14.533092 Set Vref, RX VrefLevel [Byte0]: 37
972 12:17:14.536615 [Byte1]: 37
973 12:17:14.540674
974 12:17:14.540791 Set Vref, RX VrefLevel [Byte0]: 38
975 12:17:14.543912 [Byte1]: 38
976 12:17:14.548159
977 12:17:14.548253 Set Vref, RX VrefLevel [Byte0]: 39
978 12:17:14.551497 [Byte1]: 39
979 12:17:14.556352
980 12:17:14.556435 Set Vref, RX VrefLevel [Byte0]: 40
981 12:17:14.559245 [Byte1]: 40
982 12:17:14.563630
983 12:17:14.563716 Set Vref, RX VrefLevel [Byte0]: 41
984 12:17:14.567084 [Byte1]: 41
985 12:17:14.571304
986 12:17:14.571387 Set Vref, RX VrefLevel [Byte0]: 42
987 12:17:14.574860 [Byte1]: 42
988 12:17:14.579173
989 12:17:14.579256 Set Vref, RX VrefLevel [Byte0]: 43
990 12:17:14.582158 [Byte1]: 43
991 12:17:14.586494
992 12:17:14.586577 Set Vref, RX VrefLevel [Byte0]: 44
993 12:17:14.589743 [Byte1]: 44
994 12:17:14.594207
995 12:17:14.594290 Set Vref, RX VrefLevel [Byte0]: 45
996 12:17:14.597580 [Byte1]: 45
997 12:17:14.602024
998 12:17:14.602107 Set Vref, RX VrefLevel [Byte0]: 46
999 12:17:14.605152 [Byte1]: 46
1000 12:17:14.609423
1001 12:17:14.609506 Set Vref, RX VrefLevel [Byte0]: 47
1002 12:17:14.612995 [Byte1]: 47
1003 12:17:14.617314
1004 12:17:14.617397 Set Vref, RX VrefLevel [Byte0]: 48
1005 12:17:14.620460 [Byte1]: 48
1006 12:17:14.624863
1007 12:17:14.624946 Set Vref, RX VrefLevel [Byte0]: 49
1008 12:17:14.628293 [Byte1]: 49
1009 12:17:14.632377
1010 12:17:14.632460 Set Vref, RX VrefLevel [Byte0]: 50
1011 12:17:14.636025 [Byte1]: 50
1012 12:17:14.639990
1013 12:17:14.640072 Set Vref, RX VrefLevel [Byte0]: 51
1014 12:17:14.643361 [Byte1]: 51
1015 12:17:14.647838
1016 12:17:14.647921 Set Vref, RX VrefLevel [Byte0]: 52
1017 12:17:14.651119 [Byte1]: 52
1018 12:17:14.655356
1019 12:17:14.655468 Set Vref, RX VrefLevel [Byte0]: 53
1020 12:17:14.658600 [Byte1]: 53
1021 12:17:14.663119
1022 12:17:14.663231 Set Vref, RX VrefLevel [Byte0]: 54
1023 12:17:14.666696 [Byte1]: 54
1024 12:17:14.670632
1025 12:17:14.670717 Set Vref, RX VrefLevel [Byte0]: 55
1026 12:17:14.674089 [Byte1]: 55
1027 12:17:14.678394
1028 12:17:14.678477 Set Vref, RX VrefLevel [Byte0]: 56
1029 12:17:14.681530 [Byte1]: 56
1030 12:17:14.686463
1031 12:17:14.686544 Set Vref, RX VrefLevel [Byte0]: 57
1032 12:17:14.689800 [Byte1]: 57
1033 12:17:14.693478
1034 12:17:14.693559 Set Vref, RX VrefLevel [Byte0]: 58
1035 12:17:14.696864 [Byte1]: 58
1036 12:17:14.701624
1037 12:17:14.701705 Set Vref, RX VrefLevel [Byte0]: 59
1038 12:17:14.704655 [Byte1]: 59
1039 12:17:14.709189
1040 12:17:14.709271 Set Vref, RX VrefLevel [Byte0]: 60
1041 12:17:14.712478 [Byte1]: 60
1042 12:17:14.717100
1043 12:17:14.717181 Set Vref, RX VrefLevel [Byte0]: 61
1044 12:17:14.720359 [Byte1]: 61
1045 12:17:14.724509
1046 12:17:14.724591 Set Vref, RX VrefLevel [Byte0]: 62
1047 12:17:14.727664 [Byte1]: 62
1048 12:17:14.731744
1049 12:17:14.731826 Set Vref, RX VrefLevel [Byte0]: 63
1050 12:17:14.735393 [Byte1]: 63
1051 12:17:14.739640
1052 12:17:14.739721 Set Vref, RX VrefLevel [Byte0]: 64
1053 12:17:14.742682 [Byte1]: 64
1054 12:17:14.746878
1055 12:17:14.746958 Set Vref, RX VrefLevel [Byte0]: 65
1056 12:17:14.750361 [Byte1]: 65
1057 12:17:14.754803
1058 12:17:14.754884 Set Vref, RX VrefLevel [Byte0]: 66
1059 12:17:14.757915 [Byte1]: 66
1060 12:17:14.762210
1061 12:17:14.762292 Set Vref, RX VrefLevel [Byte0]: 67
1062 12:17:14.765661 [Byte1]: 67
1063 12:17:14.769903
1064 12:17:14.769984 Set Vref, RX VrefLevel [Byte0]: 68
1065 12:17:14.773369 [Byte1]: 68
1066 12:17:14.777765
1067 12:17:14.777847 Set Vref, RX VrefLevel [Byte0]: 69
1068 12:17:14.781036 [Byte1]: 69
1069 12:17:14.785599
1070 12:17:14.785681 Set Vref, RX VrefLevel [Byte0]: 70
1071 12:17:14.788566 [Byte1]: 70
1072 12:17:14.793214
1073 12:17:14.793295 Set Vref, RX VrefLevel [Byte0]: 71
1074 12:17:14.796449 [Byte1]: 71
1075 12:17:14.800643
1076 12:17:14.800724 Set Vref, RX VrefLevel [Byte0]: 72
1077 12:17:14.803956 [Byte1]: 72
1078 12:17:14.808195
1079 12:17:14.808277 Set Vref, RX VrefLevel [Byte0]: 73
1080 12:17:14.811597 [Byte1]: 73
1081 12:17:14.816182
1082 12:17:14.816264 Set Vref, RX VrefLevel [Byte0]: 74
1083 12:17:14.819331 [Byte1]: 74
1084 12:17:14.823500
1085 12:17:14.823581 Set Vref, RX VrefLevel [Byte0]: 75
1086 12:17:14.826873 [Byte1]: 75
1087 12:17:14.831328
1088 12:17:14.831441 Final RX Vref Byte 0 = 53 to rank0
1089 12:17:14.834859 Final RX Vref Byte 1 = 54 to rank0
1090 12:17:14.838045 Final RX Vref Byte 0 = 53 to rank1
1091 12:17:14.841172 Final RX Vref Byte 1 = 54 to rank1==
1092 12:17:14.844626 Dram Type= 6, Freq= 0, CH_0, rank 0
1093 12:17:14.848035 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1094 12:17:14.851181 ==
1095 12:17:14.851289 DQS Delay:
1096 12:17:14.851383 DQS0 = 0, DQS1 = 0
1097 12:17:14.854604 DQM Delay:
1098 12:17:14.854713 DQM0 = 83, DQM1 = 73
1099 12:17:14.858137 DQ Delay:
1100 12:17:14.861440 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1101 12:17:14.861551 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1102 12:17:14.864482 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1103 12:17:14.868106 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1104 12:17:14.871273
1105 12:17:14.871353
1106 12:17:14.877945 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1107 12:17:14.881313 CH0 RK0: MR19=606, MR18=3232
1108 12:17:14.888150 CH0_RK0: MR19=0x606, MR18=0x3232, DQSOSC=397, MR23=63, INC=93, DEC=62
1109 12:17:14.888274
1110 12:17:14.891556 ----->DramcWriteLeveling(PI) begin...
1111 12:17:14.891638 ==
1112 12:17:14.894811 Dram Type= 6, Freq= 0, CH_0, rank 1
1113 12:17:14.898037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1114 12:17:14.898120 ==
1115 12:17:14.901327 Write leveling (Byte 0): 29 => 29
1116 12:17:14.904766 Write leveling (Byte 1): 28 => 28
1117 12:17:14.908083 DramcWriteLeveling(PI) end<-----
1118 12:17:14.908164
1119 12:17:14.908273 ==
1120 12:17:14.911417 Dram Type= 6, Freq= 0, CH_0, rank 1
1121 12:17:14.914701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1122 12:17:14.914784 ==
1123 12:17:14.918147 [Gating] SW mode calibration
1124 12:17:14.924897 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1125 12:17:14.931367 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1126 12:17:14.934754 0 6 0 | B1->B0 | 2f2f 3030 | 1 0 | (1 1) (0 1)
1127 12:17:14.938533 0 6 4 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
1128 12:17:14.944919 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1129 12:17:14.947993 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1130 12:17:14.951396 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1131 12:17:14.958142 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1132 12:17:14.961543 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1133 12:17:14.964816 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1134 12:17:14.968047 0 7 0 | B1->B0 | 2f2f 3737 | 1 1 | (0 0) (0 0)
1135 12:17:14.974784 0 7 4 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
1136 12:17:14.978452 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1137 12:17:14.981481 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1138 12:17:14.988463 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1139 12:17:14.991487 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1140 12:17:14.995054 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1141 12:17:15.001653 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1142 12:17:15.005084 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1143 12:17:15.008265 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1144 12:17:15.015143 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1145 12:17:15.018690 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1146 12:17:15.021685 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1147 12:17:15.028451 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1148 12:17:15.031606 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1149 12:17:15.034867 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1150 12:17:15.041554 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1151 12:17:15.044987 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1152 12:17:15.048230 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1153 12:17:15.051894 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1154 12:17:15.058261 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1155 12:17:15.061703 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1156 12:17:15.064901 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1157 12:17:15.071573 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1158 12:17:15.075047 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1159 12:17:15.078358 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1160 12:17:15.081659 Total UI for P1: 0, mck2ui 16
1161 12:17:15.085184 best dqsien dly found for B0: ( 0, 10, 0)
1162 12:17:15.088456 Total UI for P1: 0, mck2ui 16
1163 12:17:15.091640 best dqsien dly found for B1: ( 0, 10, 0)
1164 12:17:15.095188 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1165 12:17:15.098402 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1166 12:17:15.098504
1167 12:17:15.145661 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1168 12:17:15.145801 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1169 12:17:15.146088 [Gating] SW calibration Done
1170 12:17:15.146187 ==
1171 12:17:15.146279 Dram Type= 6, Freq= 0, CH_0, rank 1
1172 12:17:15.146381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1173 12:17:15.146466 ==
1174 12:17:15.146550 RX Vref Scan: 0
1175 12:17:15.146664
1176 12:17:15.146792 RX Vref 0 -> 0, step: 1
1177 12:17:15.146925
1178 12:17:15.147027 RX Delay -130 -> 252, step: 16
1179 12:17:15.147141 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1180 12:17:15.147303 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1181 12:17:15.147429 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1182 12:17:15.147514 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1183 12:17:15.147612 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1184 12:17:15.185269 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1185 12:17:15.185385 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1186 12:17:15.185701 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1187 12:17:15.185831 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1188 12:17:15.185967 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1189 12:17:15.186091 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1190 12:17:15.186287 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1191 12:17:15.186455 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1192 12:17:15.186560 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1193 12:17:15.186665 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1194 12:17:15.189614 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1195 12:17:15.189743 ==
1196 12:17:15.192839 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 12:17:15.196114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1198 12:17:15.196234 ==
1199 12:17:15.196312 DQS Delay:
1200 12:17:15.199345 DQS0 = 0, DQS1 = 0
1201 12:17:15.199425 DQM Delay:
1202 12:17:15.202726 DQM0 = 81, DQM1 = 73
1203 12:17:15.202807 DQ Delay:
1204 12:17:15.206023 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1205 12:17:15.209564 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
1206 12:17:15.212942 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1207 12:17:15.216215 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1208 12:17:15.216297
1209 12:17:15.216361
1210 12:17:15.216421 ==
1211 12:17:15.219547 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 12:17:15.222702 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1213 12:17:15.226130 ==
1214 12:17:15.226211
1215 12:17:15.226276
1216 12:17:15.226336 TX Vref Scan disable
1217 12:17:15.229428 == TX Byte 0 ==
1218 12:17:15.232760 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1219 12:17:15.236198 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1220 12:17:15.239415 == TX Byte 1 ==
1221 12:17:15.242716 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1222 12:17:15.246243 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1223 12:17:15.246326 ==
1224 12:17:15.249364 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 12:17:15.256140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1226 12:17:15.256271 ==
1227 12:17:15.268371 TX Vref=22, minBit 0, minWin=27, winSum=443
1228 12:17:15.271818 TX Vref=24, minBit 14, minWin=27, winSum=449
1229 12:17:15.275840 TX Vref=26, minBit 2, minWin=28, winSum=456
1230 12:17:15.279402 TX Vref=28, minBit 2, minWin=28, winSum=457
1231 12:17:15.283326 TX Vref=30, minBit 2, minWin=28, winSum=458
1232 12:17:15.286333 TX Vref=32, minBit 2, minWin=28, winSum=456
1233 12:17:15.293112 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 30
1234 12:17:15.293195
1235 12:17:15.293260 Final TX Range 1 Vref 30
1236 12:17:15.293321
1237 12:17:15.297193 ==
1238 12:17:15.297302 Dram Type= 6, Freq= 0, CH_0, rank 1
1239 12:17:15.303914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1240 12:17:15.303998 ==
1241 12:17:15.304063
1242 12:17:15.304125
1243 12:17:15.304210 TX Vref Scan disable
1244 12:17:15.307959 == TX Byte 0 ==
1245 12:17:15.311338 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1246 12:17:15.314733 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1247 12:17:15.318085 == TX Byte 1 ==
1248 12:17:15.321697 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1249 12:17:15.324820 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1250 12:17:15.324902
1251 12:17:15.328108 [DATLAT]
1252 12:17:15.328195 Freq=800, CH0 RK1
1253 12:17:15.328263
1254 12:17:15.331635 DATLAT Default: 0x9
1255 12:17:15.331717 0, 0xFFFF, sum = 0
1256 12:17:15.334883 1, 0xFFFF, sum = 0
1257 12:17:15.334967 2, 0xFFFF, sum = 0
1258 12:17:15.338080 3, 0xFFFF, sum = 0
1259 12:17:15.338165 4, 0xFFFF, sum = 0
1260 12:17:15.341524 5, 0xFFFF, sum = 0
1261 12:17:15.341608 6, 0xFFFF, sum = 0
1262 12:17:15.344742 7, 0xFFFF, sum = 0
1263 12:17:15.344826 8, 0x0, sum = 1
1264 12:17:15.348335 9, 0x0, sum = 2
1265 12:17:15.348419 10, 0x0, sum = 3
1266 12:17:15.351469 11, 0x0, sum = 4
1267 12:17:15.351553 best_step = 9
1268 12:17:15.351619
1269 12:17:15.351680 ==
1270 12:17:15.355000 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 12:17:15.361607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1272 12:17:15.361876 ==
1273 12:17:15.361946 RX Vref Scan: 0
1274 12:17:15.362009
1275 12:17:15.364895 RX Vref 0 -> 0, step: 1
1276 12:17:15.364977
1277 12:17:15.368270 RX Delay -111 -> 252, step: 8
1278 12:17:15.371547 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1279 12:17:15.374711 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1280 12:17:15.378128 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1281 12:17:15.384587 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1282 12:17:15.388049 iDelay=217, Bit 4, Center 92 (-23 ~ 208) 232
1283 12:17:15.391462 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1284 12:17:15.394870 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1285 12:17:15.398212 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1286 12:17:15.405135 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1287 12:17:15.408605 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1288 12:17:15.411967 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1289 12:17:15.414821 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1290 12:17:15.418278 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1291 12:17:15.425044 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1292 12:17:15.428302 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1293 12:17:15.431546 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1294 12:17:15.431628 ==
1295 12:17:15.435240 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 12:17:15.438212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1297 12:17:15.438296 ==
1298 12:17:15.441772 DQS Delay:
1299 12:17:15.441855 DQS0 = 0, DQS1 = 0
1300 12:17:15.444927 DQM Delay:
1301 12:17:15.445010 DQM0 = 87, DQM1 = 74
1302 12:17:15.445077 DQ Delay:
1303 12:17:15.448403 DQ0 =80, DQ1 =88, DQ2 =88, DQ3 =84
1304 12:17:15.451483 DQ4 =92, DQ5 =76, DQ6 =92, DQ7 =96
1305 12:17:15.454951 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1306 12:17:15.458351 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1307 12:17:15.458434
1308 12:17:15.458499
1309 12:17:15.468148 [DQSOSCAuto] RK1, (LSB)MR18= 0x4444, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1310 12:17:15.471697 CH0 RK1: MR19=606, MR18=4444
1311 12:17:15.475025 CH0_RK1: MR19=0x606, MR18=0x4444, DQSOSC=392, MR23=63, INC=96, DEC=64
1312 12:17:15.478204 [RxdqsGatingPostProcess] freq 800
1313 12:17:15.484861 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1314 12:17:15.488462 Pre-setting of DQS Precalculation
1315 12:17:15.491552 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1316 12:17:15.491634 ==
1317 12:17:15.495136 Dram Type= 6, Freq= 0, CH_1, rank 0
1318 12:17:15.501511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1319 12:17:15.501610 ==
1320 12:17:15.504824 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1321 12:17:15.511583 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1322 12:17:15.520736 [CA 0] Center 36 (6~67) winsize 62
1323 12:17:15.524156 [CA 1] Center 36 (6~67) winsize 62
1324 12:17:15.527332 [CA 2] Center 34 (4~65) winsize 62
1325 12:17:15.530617 [CA 3] Center 34 (4~65) winsize 62
1326 12:17:15.534054 [CA 4] Center 33 (2~64) winsize 63
1327 12:17:15.537262 [CA 5] Center 33 (3~64) winsize 62
1328 12:17:15.537345
1329 12:17:15.540702 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1330 12:17:15.540784
1331 12:17:15.543938 [CATrainingPosCal] consider 1 rank data
1332 12:17:15.547368 u2DelayCellTimex100 = 270/100 ps
1333 12:17:15.550946 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1334 12:17:15.554008 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1335 12:17:15.560801 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1336 12:17:15.564057 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1337 12:17:15.567321 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
1338 12:17:15.570724 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1339 12:17:15.570806
1340 12:17:15.573880 CA PerBit enable=1, Macro0, CA PI delay=33
1341 12:17:15.573963
1342 12:17:15.577533 [CBTSetCACLKResult] CA Dly = 33
1343 12:17:15.577615 CS Dly: 4 (0~35)
1344 12:17:15.580570 ==
1345 12:17:15.580652 Dram Type= 6, Freq= 0, CH_1, rank 1
1346 12:17:15.587261 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1347 12:17:15.587345 ==
1348 12:17:15.590632 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1349 12:17:15.597098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1350 12:17:15.606420 [CA 0] Center 36 (6~67) winsize 62
1351 12:17:15.609823 [CA 1] Center 36 (5~67) winsize 63
1352 12:17:15.613127 [CA 2] Center 34 (4~65) winsize 62
1353 12:17:15.616441 [CA 3] Center 34 (4~65) winsize 62
1354 12:17:15.619903 [CA 4] Center 33 (3~63) winsize 61
1355 12:17:15.623145 [CA 5] Center 33 (3~63) winsize 61
1356 12:17:15.623227
1357 12:17:15.626349 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1358 12:17:15.626432
1359 12:17:15.629824 [CATrainingPosCal] consider 2 rank data
1360 12:17:15.633194 u2DelayCellTimex100 = 270/100 ps
1361 12:17:15.636565 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1362 12:17:15.639816 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1363 12:17:15.646346 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1364 12:17:15.649639 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1365 12:17:15.653308 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1366 12:17:15.656493 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1367 12:17:15.656575
1368 12:17:15.660009 CA PerBit enable=1, Macro0, CA PI delay=33
1369 12:17:15.660091
1370 12:17:15.663202 [CBTSetCACLKResult] CA Dly = 33
1371 12:17:15.663285 CS Dly: 4 (0~36)
1372 12:17:15.663350
1373 12:17:15.666346 ----->DramcWriteLeveling(PI) begin...
1374 12:17:15.669742 ==
1375 12:17:15.672973 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 12:17:15.676459 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1377 12:17:15.676541 ==
1378 12:17:15.679903 Write leveling (Byte 0): 25 => 25
1379 12:17:15.683290 Write leveling (Byte 1): 25 => 25
1380 12:17:15.686408 DramcWriteLeveling(PI) end<-----
1381 12:17:15.686491
1382 12:17:15.686555 ==
1383 12:17:15.690159 Dram Type= 6, Freq= 0, CH_1, rank 0
1384 12:17:15.693273 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1385 12:17:15.693356 ==
1386 12:17:15.696347 [Gating] SW mode calibration
1387 12:17:15.703147 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1388 12:17:15.706670 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1389 12:17:15.713052 0 6 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)
1390 12:17:15.716397 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1391 12:17:15.719608 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1392 12:17:15.726257 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1393 12:17:15.729663 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1394 12:17:15.733243 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1395 12:17:15.739667 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1396 12:17:15.743039 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1397 12:17:15.746239 0 7 0 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (1 1)
1398 12:17:15.752965 0 7 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1399 12:17:15.756265 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1400 12:17:15.759601 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1401 12:17:15.766243 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1402 12:17:15.769515 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1403 12:17:15.772990 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1404 12:17:15.779480 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1405 12:17:15.782813 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1406 12:17:15.786351 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 12:17:15.792951 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1408 12:17:15.796361 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1409 12:17:15.799599 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1410 12:17:15.806050 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1411 12:17:15.809412 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1412 12:17:15.812710 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1413 12:17:15.816095 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1414 12:17:15.823330 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1415 12:17:15.826109 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1416 12:17:15.829520 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1417 12:17:15.836133 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1418 12:17:15.839521 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1419 12:17:15.842626 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1420 12:17:15.849507 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1421 12:17:15.852892 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1422 12:17:15.856302 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1423 12:17:15.859442 Total UI for P1: 0, mck2ui 16
1424 12:17:15.862796 best dqsien dly found for B0: ( 0, 9, 30)
1425 12:17:15.865989 Total UI for P1: 0, mck2ui 16
1426 12:17:15.869372 best dqsien dly found for B1: ( 0, 10, 0)
1427 12:17:15.872761 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1428 12:17:15.876384 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1429 12:17:15.876466
1430 12:17:15.882821 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1431 12:17:15.886487 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1432 12:17:15.886599 [Gating] SW calibration Done
1433 12:17:15.889383 ==
1434 12:17:15.893074 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 12:17:15.896044 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1436 12:17:15.896126 ==
1437 12:17:15.896220 RX Vref Scan: 0
1438 12:17:15.896315
1439 12:17:15.899505 RX Vref 0 -> 0, step: 1
1440 12:17:15.899586
1441 12:17:15.902867 RX Delay -130 -> 252, step: 16
1442 12:17:15.906261 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1443 12:17:15.909478 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1444 12:17:15.916080 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1445 12:17:15.919321 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1446 12:17:15.922949 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1447 12:17:15.926012 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1448 12:17:15.929484 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1449 12:17:15.932948 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1450 12:17:15.936704 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1451 12:17:15.944098 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1452 12:17:15.947227 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1453 12:17:15.951128 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1454 12:17:15.954859 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1455 12:17:15.958456 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1456 12:17:15.961942 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1457 12:17:15.965123 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1458 12:17:15.965209 ==
1459 12:17:15.969126 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 12:17:15.975746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1461 12:17:15.975830 ==
1462 12:17:15.975897 DQS Delay:
1463 12:17:15.975960 DQS0 = 0, DQS1 = 0
1464 12:17:15.978846 DQM Delay:
1465 12:17:15.978929 DQM0 = 82, DQM1 = 74
1466 12:17:15.982359 DQ Delay:
1467 12:17:15.985641 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1468 12:17:15.985724 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1469 12:17:15.988984 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1470 12:17:15.995861 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1471 12:17:15.995944
1472 12:17:15.996010
1473 12:17:15.996071 ==
1474 12:17:15.998991 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 12:17:16.002644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1476 12:17:16.002726 ==
1477 12:17:16.002792
1478 12:17:16.002852
1479 12:17:16.005910 TX Vref Scan disable
1480 12:17:16.005992 == TX Byte 0 ==
1481 12:17:16.012069 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1482 12:17:16.015464 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1483 12:17:16.015547 == TX Byte 1 ==
1484 12:17:16.022112 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1485 12:17:16.025451 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1486 12:17:16.025534 ==
1487 12:17:16.028851 Dram Type= 6, Freq= 0, CH_1, rank 0
1488 12:17:16.032006 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1489 12:17:16.032089 ==
1490 12:17:16.045839 TX Vref=22, minBit 1, minWin=27, winSum=446
1491 12:17:16.049111 TX Vref=24, minBit 0, minWin=28, winSum=449
1492 12:17:16.052436 TX Vref=26, minBit 3, minWin=27, winSum=451
1493 12:17:16.055723 TX Vref=28, minBit 0, minWin=28, winSum=458
1494 12:17:16.059138 TX Vref=30, minBit 2, minWin=28, winSum=458
1495 12:17:16.062286 TX Vref=32, minBit 3, minWin=28, winSum=457
1496 12:17:16.069020 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1497 12:17:16.069103
1498 12:17:16.072442 Final TX Range 1 Vref 28
1499 12:17:16.072525
1500 12:17:16.072590 ==
1501 12:17:16.075572 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 12:17:16.079301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1503 12:17:16.079385 ==
1504 12:17:16.079451
1505 12:17:16.079513
1506 12:17:16.082331 TX Vref Scan disable
1507 12:17:16.085934 == TX Byte 0 ==
1508 12:17:16.089102 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1509 12:17:16.092418 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1510 12:17:16.095694 == TX Byte 1 ==
1511 12:17:16.099433 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1512 12:17:16.102382 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1513 12:17:16.102479
1514 12:17:16.106026 [DATLAT]
1515 12:17:16.106109 Freq=800, CH1 RK0
1516 12:17:16.106175
1517 12:17:16.109150 DATLAT Default: 0xa
1518 12:17:16.109232 0, 0xFFFF, sum = 0
1519 12:17:16.112333 1, 0xFFFF, sum = 0
1520 12:17:16.112417 2, 0xFFFF, sum = 0
1521 12:17:16.116038 3, 0xFFFF, sum = 0
1522 12:17:16.116121 4, 0xFFFF, sum = 0
1523 12:17:16.119307 5, 0xFFFF, sum = 0
1524 12:17:16.119391 6, 0xFFFF, sum = 0
1525 12:17:16.122623 7, 0xFFFF, sum = 0
1526 12:17:16.122707 8, 0x0, sum = 1
1527 12:17:16.125914 9, 0x0, sum = 2
1528 12:17:16.125998 10, 0x0, sum = 3
1529 12:17:16.129226 11, 0x0, sum = 4
1530 12:17:16.129309 best_step = 9
1531 12:17:16.129374
1532 12:17:16.129434 ==
1533 12:17:16.132629 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 12:17:16.135906 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1535 12:17:16.139074 ==
1536 12:17:16.139157 RX Vref Scan: 1
1537 12:17:16.139222
1538 12:17:16.142760 Set Vref Range= 32 -> 127
1539 12:17:16.142843
1540 12:17:16.146147 RX Vref 32 -> 127, step: 1
1541 12:17:16.146230
1542 12:17:16.146296 RX Delay -111 -> 252, step: 8
1543 12:17:16.146356
1544 12:17:16.149433 Set Vref, RX VrefLevel [Byte0]: 32
1545 12:17:16.152457 [Byte1]: 32
1546 12:17:16.156427
1547 12:17:16.156509 Set Vref, RX VrefLevel [Byte0]: 33
1548 12:17:16.159726 [Byte1]: 33
1549 12:17:16.163976
1550 12:17:16.164058 Set Vref, RX VrefLevel [Byte0]: 34
1551 12:17:16.167385 [Byte1]: 34
1552 12:17:16.171754
1553 12:17:16.171837 Set Vref, RX VrefLevel [Byte0]: 35
1554 12:17:16.175061 [Byte1]: 35
1555 12:17:16.179600
1556 12:17:16.179682 Set Vref, RX VrefLevel [Byte0]: 36
1557 12:17:16.182761 [Byte1]: 36
1558 12:17:16.187544
1559 12:17:16.187626 Set Vref, RX VrefLevel [Byte0]: 37
1560 12:17:16.190434 [Byte1]: 37
1561 12:17:16.195115
1562 12:17:16.195196 Set Vref, RX VrefLevel [Byte0]: 38
1563 12:17:16.198030 [Byte1]: 38
1564 12:17:16.202416
1565 12:17:16.202499 Set Vref, RX VrefLevel [Byte0]: 39
1566 12:17:16.205767 [Byte1]: 39
1567 12:17:16.209996
1568 12:17:16.210078 Set Vref, RX VrefLevel [Byte0]: 40
1569 12:17:16.213180 [Byte1]: 40
1570 12:17:16.217853
1571 12:17:16.217935 Set Vref, RX VrefLevel [Byte0]: 41
1572 12:17:16.220942 [Byte1]: 41
1573 12:17:16.225348
1574 12:17:16.225430 Set Vref, RX VrefLevel [Byte0]: 42
1575 12:17:16.228648 [Byte1]: 42
1576 12:17:16.233080
1577 12:17:16.233162 Set Vref, RX VrefLevel [Byte0]: 43
1578 12:17:16.236103 [Byte1]: 43
1579 12:17:16.240460
1580 12:17:16.240541 Set Vref, RX VrefLevel [Byte0]: 44
1581 12:17:16.243786 [Byte1]: 44
1582 12:17:16.248182
1583 12:17:16.248265 Set Vref, RX VrefLevel [Byte0]: 45
1584 12:17:16.251606 [Byte1]: 45
1585 12:17:16.255992
1586 12:17:16.256074 Set Vref, RX VrefLevel [Byte0]: 46
1587 12:17:16.259221 [Byte1]: 46
1588 12:17:16.263493
1589 12:17:16.263575 Set Vref, RX VrefLevel [Byte0]: 47
1590 12:17:16.266845 [Byte1]: 47
1591 12:17:16.271095
1592 12:17:16.271178 Set Vref, RX VrefLevel [Byte0]: 48
1593 12:17:16.274521 [Byte1]: 48
1594 12:17:16.279050
1595 12:17:16.279170 Set Vref, RX VrefLevel [Byte0]: 49
1596 12:17:16.282177 [Byte1]: 49
1597 12:17:16.286357
1598 12:17:16.286439 Set Vref, RX VrefLevel [Byte0]: 50
1599 12:17:16.290636 [Byte1]: 50
1600 12:17:16.294382
1601 12:17:16.294464 Set Vref, RX VrefLevel [Byte0]: 51
1602 12:17:16.297531 [Byte1]: 51
1603 12:17:16.301667
1604 12:17:16.301749 Set Vref, RX VrefLevel [Byte0]: 52
1605 12:17:16.305165 [Byte1]: 52
1606 12:17:16.309781
1607 12:17:16.309864 Set Vref, RX VrefLevel [Byte0]: 53
1608 12:17:16.312832 [Byte1]: 53
1609 12:17:16.317207
1610 12:17:16.317290 Set Vref, RX VrefLevel [Byte0]: 54
1611 12:17:16.320541 [Byte1]: 54
1612 12:17:16.325335
1613 12:17:16.325449 Set Vref, RX VrefLevel [Byte0]: 55
1614 12:17:16.327871 [Byte1]: 55
1615 12:17:16.332384
1616 12:17:16.332465 Set Vref, RX VrefLevel [Byte0]: 56
1617 12:17:16.335623 [Byte1]: 56
1618 12:17:16.339927
1619 12:17:16.340009 Set Vref, RX VrefLevel [Byte0]: 57
1620 12:17:16.343306 [Byte1]: 57
1621 12:17:16.347738
1622 12:17:16.347820 Set Vref, RX VrefLevel [Byte0]: 58
1623 12:17:16.351328 [Byte1]: 58
1624 12:17:16.355515
1625 12:17:16.355597 Set Vref, RX VrefLevel [Byte0]: 59
1626 12:17:16.358660 [Byte1]: 59
1627 12:17:16.363100
1628 12:17:16.363182 Set Vref, RX VrefLevel [Byte0]: 60
1629 12:17:16.366181 [Byte1]: 60
1630 12:17:16.370579
1631 12:17:16.370662 Set Vref, RX VrefLevel [Byte0]: 61
1632 12:17:16.373943 [Byte1]: 61
1633 12:17:16.378493
1634 12:17:16.378575 Set Vref, RX VrefLevel [Byte0]: 62
1635 12:17:16.381478 [Byte1]: 62
1636 12:17:16.385815
1637 12:17:16.385898 Set Vref, RX VrefLevel [Byte0]: 63
1638 12:17:16.389117 [Byte1]: 63
1639 12:17:16.393342
1640 12:17:16.393425 Set Vref, RX VrefLevel [Byte0]: 64
1641 12:17:16.396782 [Byte1]: 64
1642 12:17:16.401085
1643 12:17:16.401167 Set Vref, RX VrefLevel [Byte0]: 65
1644 12:17:16.404785 [Byte1]: 65
1645 12:17:16.408923
1646 12:17:16.409005 Set Vref, RX VrefLevel [Byte0]: 66
1647 12:17:16.412027 [Byte1]: 66
1648 12:17:16.416377
1649 12:17:16.416459 Set Vref, RX VrefLevel [Byte0]: 67
1650 12:17:16.419636 [Byte1]: 67
1651 12:17:16.423961
1652 12:17:16.424043 Set Vref, RX VrefLevel [Byte0]: 68
1653 12:17:16.427430 [Byte1]: 68
1654 12:17:16.431846
1655 12:17:16.431929 Set Vref, RX VrefLevel [Byte0]: 69
1656 12:17:16.434987 [Byte1]: 69
1657 12:17:16.439497
1658 12:17:16.439579 Set Vref, RX VrefLevel [Byte0]: 70
1659 12:17:16.442830 [Byte1]: 70
1660 12:17:16.447101
1661 12:17:16.447183 Set Vref, RX VrefLevel [Byte0]: 71
1662 12:17:16.450391 [Byte1]: 71
1663 12:17:16.454801
1664 12:17:16.454883 Set Vref, RX VrefLevel [Byte0]: 72
1665 12:17:16.458023 [Byte1]: 72
1666 12:17:16.462421
1667 12:17:16.462504 Set Vref, RX VrefLevel [Byte0]: 73
1668 12:17:16.465608 [Byte1]: 73
1669 12:17:16.470185
1670 12:17:16.470267 Set Vref, RX VrefLevel [Byte0]: 74
1671 12:17:16.473237 [Byte1]: 74
1672 12:17:16.477535
1673 12:17:16.477618 Final RX Vref Byte 0 = 59 to rank0
1674 12:17:16.480929 Final RX Vref Byte 1 = 53 to rank0
1675 12:17:16.484444 Final RX Vref Byte 0 = 59 to rank1
1676 12:17:16.487545 Final RX Vref Byte 1 = 53 to rank1==
1677 12:17:16.490932 Dram Type= 6, Freq= 0, CH_1, rank 0
1678 12:17:16.497760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1679 12:17:16.497843 ==
1680 12:17:16.497909 DQS Delay:
1681 12:17:16.497971 DQS0 = 0, DQS1 = 0
1682 12:17:16.500970 DQM Delay:
1683 12:17:16.501053 DQM0 = 79, DQM1 = 71
1684 12:17:16.504297 DQ Delay:
1685 12:17:16.507835 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1686 12:17:16.507915 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1687 12:17:16.511236 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1688 12:17:16.515404 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1689 12:17:16.515515
1690 12:17:16.515592
1691 12:17:16.525539 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e4e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1692 12:17:16.528434 CH1 RK0: MR19=606, MR18=4E4E
1693 12:17:16.532026 CH1_RK0: MR19=0x606, MR18=0x4E4E, DQSOSC=390, MR23=63, INC=97, DEC=64
1694 12:17:16.532108
1695 12:17:16.535159 ----->DramcWriteLeveling(PI) begin...
1696 12:17:16.538702 ==
1697 12:17:16.538783 Dram Type= 6, Freq= 0, CH_1, rank 1
1698 12:17:16.545165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1699 12:17:16.545247 ==
1700 12:17:16.548820 Write leveling (Byte 0): 24 => 24
1701 12:17:16.551860 Write leveling (Byte 1): 23 => 23
1702 12:17:16.555295 DramcWriteLeveling(PI) end<-----
1703 12:17:16.555376
1704 12:17:16.555440 ==
1705 12:17:16.558774 Dram Type= 6, Freq= 0, CH_1, rank 1
1706 12:17:16.561851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1707 12:17:16.561933 ==
1708 12:17:16.565351 [Gating] SW mode calibration
1709 12:17:16.571769 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1710 12:17:16.575297 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1711 12:17:16.581797 0 6 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
1712 12:17:16.585107 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1713 12:17:16.588517 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1714 12:17:16.595701 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1715 12:17:16.598598 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1716 12:17:16.601856 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1717 12:17:16.608296 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1718 12:17:16.611818 0 6 28 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
1719 12:17:16.615039 0 7 0 | B1->B0 | 3232 4545 | 1 0 | (0 0) (0 0)
1720 12:17:16.622045 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1721 12:17:16.625247 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1722 12:17:16.628338 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1723 12:17:16.635150 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1724 12:17:16.638397 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1725 12:17:16.641829 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1726 12:17:16.648457 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1727 12:17:16.652017 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 12:17:16.655231 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 12:17:16.658434 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 12:17:16.665022 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 12:17:16.668457 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 12:17:16.671932 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 12:17:16.678797 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 12:17:16.681689 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 12:17:16.684965 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 12:17:16.691666 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 12:17:16.695157 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 12:17:16.698270 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1739 12:17:16.705004 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1740 12:17:16.708425 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1741 12:17:16.711671 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1742 12:17:16.718289 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1743 12:17:16.721779 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1744 12:17:16.725203 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1745 12:17:16.728634 Total UI for P1: 0, mck2ui 16
1746 12:17:16.731754 best dqsien dly found for B0: ( 0, 9, 30)
1747 12:17:16.735011 Total UI for P1: 0, mck2ui 16
1748 12:17:16.738351 best dqsien dly found for B1: ( 0, 9, 30)
1749 12:17:16.741560 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1750 12:17:16.744916 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1751 12:17:16.744998
1752 12:17:16.748708 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1753 12:17:16.755048 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1754 12:17:16.755131 [Gating] SW calibration Done
1755 12:17:16.758327 ==
1756 12:17:16.762031 Dram Type= 6, Freq= 0, CH_1, rank 1
1757 12:17:16.765168 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1758 12:17:16.765251 ==
1759 12:17:16.765317 RX Vref Scan: 0
1760 12:17:16.765377
1761 12:17:16.768523 RX Vref 0 -> 0, step: 1
1762 12:17:16.768606
1763 12:17:16.771881 RX Delay -130 -> 252, step: 16
1764 12:17:16.775010 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1765 12:17:16.778427 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1766 12:17:16.781653 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1767 12:17:16.788390 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1768 12:17:16.791648 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1769 12:17:16.795193 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1770 12:17:16.798424 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1771 12:17:16.801745 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1772 12:17:16.808298 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1773 12:17:16.811950 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1774 12:17:16.814935 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1775 12:17:16.818383 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1776 12:17:16.821838 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1777 12:17:16.828531 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1778 12:17:16.831616 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1779 12:17:16.835280 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1780 12:17:16.835366 ==
1781 12:17:16.838435 Dram Type= 6, Freq= 0, CH_1, rank 1
1782 12:17:16.841712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1783 12:17:16.841795 ==
1784 12:17:16.845247 DQS Delay:
1785 12:17:16.845330 DQS0 = 0, DQS1 = 0
1786 12:17:16.848553 DQM Delay:
1787 12:17:16.848635 DQM0 = 82, DQM1 = 73
1788 12:17:16.848700 DQ Delay:
1789 12:17:16.851849 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1790 12:17:16.855527 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1791 12:17:16.858334 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1792 12:17:16.861798 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1793 12:17:16.861881
1794 12:17:16.861947
1795 12:17:16.865274 ==
1796 12:17:16.865357 Dram Type= 6, Freq= 0, CH_1, rank 1
1797 12:17:16.871697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1798 12:17:16.871780 ==
1799 12:17:16.871845
1800 12:17:16.871906
1801 12:17:16.875144 TX Vref Scan disable
1802 12:17:16.875225 == TX Byte 0 ==
1803 12:17:16.878139 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1804 12:17:16.884920 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1805 12:17:16.885004 == TX Byte 1 ==
1806 12:17:16.888157 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1807 12:17:16.894957 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1808 12:17:16.895039 ==
1809 12:17:16.898507 Dram Type= 6, Freq= 0, CH_1, rank 1
1810 12:17:16.901615 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1811 12:17:16.901698 ==
1812 12:17:16.914864 TX Vref=22, minBit 0, minWin=28, winSum=451
1813 12:17:16.918057 TX Vref=24, minBit 1, minWin=28, winSum=455
1814 12:17:16.921378 TX Vref=26, minBit 0, minWin=28, winSum=458
1815 12:17:16.924887 TX Vref=28, minBit 0, minWin=28, winSum=459
1816 12:17:16.928300 TX Vref=30, minBit 3, minWin=28, winSum=460
1817 12:17:16.931350 TX Vref=32, minBit 0, minWin=28, winSum=458
1818 12:17:16.938170 [TxChooseVref] Worse bit 3, Min win 28, Win sum 460, Final Vref 30
1819 12:17:16.938253
1820 12:17:16.941494 Final TX Range 1 Vref 30
1821 12:17:16.941577
1822 12:17:16.941643 ==
1823 12:17:16.944634 Dram Type= 6, Freq= 0, CH_1, rank 1
1824 12:17:16.947898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1825 12:17:16.947985 ==
1826 12:17:16.948051
1827 12:17:16.951682
1828 12:17:16.951764 TX Vref Scan disable
1829 12:17:16.954713 == TX Byte 0 ==
1830 12:17:16.958159 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1831 12:17:16.961267 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1832 12:17:16.964606 == TX Byte 1 ==
1833 12:17:16.967839 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
1834 12:17:16.974526 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
1835 12:17:16.974609
1836 12:17:16.974674 [DATLAT]
1837 12:17:16.974735 Freq=800, CH1 RK1
1838 12:17:16.974794
1839 12:17:16.978021 DATLAT Default: 0x9
1840 12:17:16.978103 0, 0xFFFF, sum = 0
1841 12:17:16.981277 1, 0xFFFF, sum = 0
1842 12:17:16.981457 2, 0xFFFF, sum = 0
1843 12:17:16.984402 3, 0xFFFF, sum = 0
1844 12:17:16.987831 4, 0xFFFF, sum = 0
1845 12:17:16.987914 5, 0xFFFF, sum = 0
1846 12:17:16.991133 6, 0xFFFF, sum = 0
1847 12:17:16.991216 7, 0xFFFF, sum = 0
1848 12:17:16.994490 8, 0x0, sum = 1
1849 12:17:16.994574 9, 0x0, sum = 2
1850 12:17:16.994641 10, 0x0, sum = 3
1851 12:17:16.997673 11, 0x0, sum = 4
1852 12:17:16.997757 best_step = 9
1853 12:17:16.997823
1854 12:17:16.997883 ==
1855 12:17:17.001206 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 12:17:17.007865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1857 12:17:17.007948 ==
1858 12:17:17.008014 RX Vref Scan: 0
1859 12:17:17.008075
1860 12:17:17.010900 RX Vref 0 -> 0, step: 1
1861 12:17:17.010983
1862 12:17:17.014832 RX Delay -111 -> 252, step: 8
1863 12:17:17.017727 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1864 12:17:17.021106 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1865 12:17:17.027573 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1866 12:17:17.030911 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1867 12:17:17.034345 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1868 12:17:17.037662 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1869 12:17:17.040817 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1870 12:17:17.047729 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1871 12:17:17.051193 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1872 12:17:17.054325 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1873 12:17:17.057501 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1874 12:17:17.061057 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1875 12:17:17.067618 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1876 12:17:17.070892 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1877 12:17:17.074540 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1878 12:17:17.077733 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1879 12:17:17.077816 ==
1880 12:17:17.081195 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 12:17:17.087529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1882 12:17:17.087613 ==
1883 12:17:17.087679 DQS Delay:
1884 12:17:17.087741 DQS0 = 0, DQS1 = 0
1885 12:17:17.091061 DQM Delay:
1886 12:17:17.091144 DQM0 = 82, DQM1 = 72
1887 12:17:17.094309 DQ Delay:
1888 12:17:17.097672 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1889 12:17:17.097755 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1890 12:17:17.101188 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1891 12:17:17.104161 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1892 12:17:17.107700
1893 12:17:17.107781
1894 12:17:17.114347 [DQSOSCAuto] RK1, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1895 12:17:17.117468 CH1 RK1: MR19=606, MR18=3838
1896 12:17:17.124393 CH1_RK1: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1897 12:17:17.127512 [RxdqsGatingPostProcess] freq 800
1898 12:17:17.131049 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1899 12:17:17.134476 Pre-setting of DQS Precalculation
1900 12:17:17.137668 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1901 12:17:17.147721 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1902 12:17:17.154415 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1903 12:17:17.154498
1904 12:17:17.154563
1905 12:17:17.158061 [Calibration Summary] 1600 Mbps
1906 12:17:17.158144 CH 0, Rank 0
1907 12:17:17.160848 SW Impedance : PASS
1908 12:17:17.160930 DUTY Scan : NO K
1909 12:17:17.164553 ZQ Calibration : PASS
1910 12:17:17.167504 Jitter Meter : NO K
1911 12:17:17.167586 CBT Training : PASS
1912 12:17:17.171101 Write leveling : PASS
1913 12:17:17.174263 RX DQS gating : PASS
1914 12:17:17.174346 RX DQ/DQS(RDDQC) : PASS
1915 12:17:17.177655 TX DQ/DQS : PASS
1916 12:17:17.181099 RX DATLAT : PASS
1917 12:17:17.181182 RX DQ/DQS(Engine): PASS
1918 12:17:17.184180 TX OE : NO K
1919 12:17:17.184265 All Pass.
1920 12:17:17.184331
1921 12:17:17.188061 CH 0, Rank 1
1922 12:17:17.188143 SW Impedance : PASS
1923 12:17:17.191052 DUTY Scan : NO K
1924 12:17:17.194148 ZQ Calibration : PASS
1925 12:17:17.194232 Jitter Meter : NO K
1926 12:17:17.197664 CBT Training : PASS
1927 12:17:17.197746 Write leveling : PASS
1928 12:17:17.200942 RX DQS gating : PASS
1929 12:17:17.204121 RX DQ/DQS(RDDQC) : PASS
1930 12:17:17.204257 TX DQ/DQS : PASS
1931 12:17:17.207465 RX DATLAT : PASS
1932 12:17:17.210900 RX DQ/DQS(Engine): PASS
1933 12:17:17.210983 TX OE : NO K
1934 12:17:17.214369 All Pass.
1935 12:17:17.214452
1936 12:17:17.214517 CH 1, Rank 0
1937 12:17:17.217854 SW Impedance : PASS
1938 12:17:17.217936 DUTY Scan : NO K
1939 12:17:17.220798 ZQ Calibration : PASS
1940 12:17:17.224060 Jitter Meter : NO K
1941 12:17:17.224143 CBT Training : PASS
1942 12:17:17.227397 Write leveling : PASS
1943 12:17:17.231008 RX DQS gating : PASS
1944 12:17:17.231091 RX DQ/DQS(RDDQC) : PASS
1945 12:17:17.234105 TX DQ/DQS : PASS
1946 12:17:17.237736 RX DATLAT : PASS
1947 12:17:17.237818 RX DQ/DQS(Engine): PASS
1948 12:17:17.240964 TX OE : NO K
1949 12:17:17.241047 All Pass.
1950 12:17:17.241113
1951 12:17:17.244107 CH 1, Rank 1
1952 12:17:17.244196 SW Impedance : PASS
1953 12:17:17.247621 DUTY Scan : NO K
1954 12:17:17.247703 ZQ Calibration : PASS
1955 12:17:17.250788 Jitter Meter : NO K
1956 12:17:17.254134 CBT Training : PASS
1957 12:17:17.254216 Write leveling : PASS
1958 12:17:17.257476 RX DQS gating : PASS
1959 12:17:17.260696 RX DQ/DQS(RDDQC) : PASS
1960 12:17:17.260778 TX DQ/DQS : PASS
1961 12:17:17.264045 RX DATLAT : PASS
1962 12:17:17.267346 RX DQ/DQS(Engine): PASS
1963 12:17:17.267428 TX OE : NO K
1964 12:17:17.270754 All Pass.
1965 12:17:17.270836
1966 12:17:17.270902 DramC Write-DBI off
1967 12:17:17.274108 PER_BANK_REFRESH: Hybrid Mode
1968 12:17:17.274191 TX_TRACKING: ON
1969 12:17:17.277952 [GetDramInforAfterCalByMRR] Vendor 6.
1970 12:17:17.284464 [GetDramInforAfterCalByMRR] Revision 606.
1971 12:17:17.287584 [GetDramInforAfterCalByMRR] Revision 2 0.
1972 12:17:17.287666 MR0 0x3939
1973 12:17:17.287732 MR8 0x1111
1974 12:17:17.290811 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1975 12:17:17.290894
1976 12:17:17.294171 MR0 0x3939
1977 12:17:17.294253 MR8 0x1111
1978 12:17:17.297716 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1979 12:17:17.297799
1980 12:17:17.307536 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1981 12:17:17.311163 [FAST_K] Save calibration result to emmc
1982 12:17:17.314202 [FAST_K] Save calibration result to emmc
1983 12:17:17.317627 dram_init: config_dvfs: 1
1984 12:17:17.320885 dramc_set_vcore_voltage set vcore to 662500
1985 12:17:17.324123 Read voltage for 1200, 2
1986 12:17:17.324211 Vio18 = 0
1987 12:17:17.324278 Vcore = 662500
1988 12:17:17.327762 Vdram = 0
1989 12:17:17.327844 Vddq = 0
1990 12:17:17.327908 Vmddr = 0
1991 12:17:17.334462 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1992 12:17:17.337708 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1993 12:17:17.341057 MEM_TYPE=3, freq_sel=15
1994 12:17:17.344523 sv_algorithm_assistance_LP4_1600
1995 12:17:17.347573 ============ PULL DRAM RESETB DOWN ============
1996 12:17:17.350939 ========== PULL DRAM RESETB DOWN end =========
1997 12:17:17.357633 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1998 12:17:17.360922 ===================================
1999 12:17:17.361005 LPDDR4 DRAM CONFIGURATION
2000 12:17:17.364178 ===================================
2001 12:17:17.367638 EX_ROW_EN[0] = 0x0
2002 12:17:17.371006 EX_ROW_EN[1] = 0x0
2003 12:17:17.371088 LP4Y_EN = 0x0
2004 12:17:17.374431 WORK_FSP = 0x0
2005 12:17:17.374513 WL = 0x4
2006 12:17:17.377607 RL = 0x4
2007 12:17:17.377689 BL = 0x2
2008 12:17:17.381057 RPST = 0x0
2009 12:17:17.381138 RD_PRE = 0x0
2010 12:17:17.384291 WR_PRE = 0x1
2011 12:17:17.384373 WR_PST = 0x0
2012 12:17:17.387635 DBI_WR = 0x0
2013 12:17:17.387717 DBI_RD = 0x0
2014 12:17:17.390960 OTF = 0x1
2015 12:17:17.394505 ===================================
2016 12:17:17.397747 ===================================
2017 12:17:17.397831 ANA top config
2018 12:17:17.401150 ===================================
2019 12:17:17.404551 DLL_ASYNC_EN = 0
2020 12:17:17.407945 ALL_SLAVE_EN = 0
2021 12:17:17.408027 NEW_RANK_MODE = 1
2022 12:17:17.411167 DLL_IDLE_MODE = 1
2023 12:17:17.414409 LP45_APHY_COMB_EN = 1
2024 12:17:17.417722 TX_ODT_DIS = 1
2025 12:17:17.417806 NEW_8X_MODE = 1
2026 12:17:17.420990 ===================================
2027 12:17:17.424381 ===================================
2028 12:17:17.427624 data_rate = 2400
2029 12:17:17.430890 CKR = 1
2030 12:17:17.434388 DQ_P2S_RATIO = 8
2031 12:17:17.437573 ===================================
2032 12:17:17.440991 CA_P2S_RATIO = 8
2033 12:17:17.444349 DQ_CA_OPEN = 0
2034 12:17:17.444432 DQ_SEMI_OPEN = 0
2035 12:17:17.447636 CA_SEMI_OPEN = 0
2036 12:17:17.451024 CA_FULL_RATE = 0
2037 12:17:17.454298 DQ_CKDIV4_EN = 0
2038 12:17:17.457674 CA_CKDIV4_EN = 0
2039 12:17:17.460945 CA_PREDIV_EN = 0
2040 12:17:17.461027 PH8_DLY = 17
2041 12:17:17.464232 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2042 12:17:17.467448 DQ_AAMCK_DIV = 4
2043 12:17:17.470807 CA_AAMCK_DIV = 4
2044 12:17:17.474159 CA_ADMCK_DIV = 4
2045 12:17:17.477501 DQ_TRACK_CA_EN = 0
2046 12:17:17.480686 CA_PICK = 1200
2047 12:17:17.480769 CA_MCKIO = 1200
2048 12:17:17.484300 MCKIO_SEMI = 0
2049 12:17:17.487331 PLL_FREQ = 2366
2050 12:17:17.490881 DQ_UI_PI_RATIO = 32
2051 12:17:17.494178 CA_UI_PI_RATIO = 0
2052 12:17:17.497499 ===================================
2053 12:17:17.500705 ===================================
2054 12:17:17.504036 memory_type:LPDDR4
2055 12:17:17.504119 GP_NUM : 10
2056 12:17:17.507362 SRAM_EN : 1
2057 12:17:17.507445 MD32_EN : 0
2058 12:17:17.510746 ===================================
2059 12:17:17.514414 [ANA_INIT] >>>>>>>>>>>>>>
2060 12:17:17.517402 <<<<<< [CONFIGURE PHASE]: ANA_TX
2061 12:17:17.520745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2062 12:17:17.524073 ===================================
2063 12:17:17.527376 data_rate = 2400,PCW = 0X5b00
2064 12:17:17.530685 ===================================
2065 12:17:17.533985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2066 12:17:17.540817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2067 12:17:17.544163 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2068 12:17:17.550702 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2069 12:17:17.554068 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2070 12:17:17.557400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2071 12:17:17.557483 [ANA_INIT] flow start
2072 12:17:17.560668 [ANA_INIT] PLL >>>>>>>>
2073 12:17:17.564041 [ANA_INIT] PLL <<<<<<<<
2074 12:17:17.564127 [ANA_INIT] MIDPI >>>>>>>>
2075 12:17:17.567444 [ANA_INIT] MIDPI <<<<<<<<
2076 12:17:17.570641 [ANA_INIT] DLL >>>>>>>>
2077 12:17:17.570723 [ANA_INIT] DLL <<<<<<<<
2078 12:17:17.574238 [ANA_INIT] flow end
2079 12:17:17.577597 ============ LP4 DIFF to SE enter ============
2080 12:17:17.580754 ============ LP4 DIFF to SE exit ============
2081 12:17:17.584099 [ANA_INIT] <<<<<<<<<<<<<
2082 12:17:17.587448 [Flow] Enable top DCM control >>>>>
2083 12:17:17.590778 [Flow] Enable top DCM control <<<<<
2084 12:17:17.594343 Enable DLL master slave shuffle
2085 12:17:17.600634 ==============================================================
2086 12:17:17.600717 Gating Mode config
2087 12:17:17.607410 ==============================================================
2088 12:17:17.607492 Config description:
2089 12:17:17.617171 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2090 12:17:17.624073 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2091 12:17:17.630586 SELPH_MODE 0: By rank 1: By Phase
2092 12:17:17.633832 ==============================================================
2093 12:17:17.637327 GAT_TRACK_EN = 1
2094 12:17:17.640752 RX_GATING_MODE = 2
2095 12:17:17.644134 RX_GATING_TRACK_MODE = 2
2096 12:17:17.647273 SELPH_MODE = 1
2097 12:17:17.650699 PICG_EARLY_EN = 1
2098 12:17:17.654137 VALID_LAT_VALUE = 1
2099 12:17:17.657229 ==============================================================
2100 12:17:17.664046 Enter into Gating configuration >>>>
2101 12:17:17.664129 Exit from Gating configuration <<<<
2102 12:17:17.667398 Enter into DVFS_PRE_config >>>>>
2103 12:17:17.680435 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2104 12:17:17.683963 Exit from DVFS_PRE_config <<<<<
2105 12:17:17.687230 Enter into PICG configuration >>>>
2106 12:17:17.690547 Exit from PICG configuration <<<<
2107 12:17:17.690630 [RX_INPUT] configuration >>>>>
2108 12:17:17.693688 [RX_INPUT] configuration <<<<<
2109 12:17:17.700464 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2110 12:17:17.703709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2111 12:17:17.710488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2112 12:17:17.717024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2113 12:17:17.723799 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2114 12:17:17.730359 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2115 12:17:17.733875 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2116 12:17:17.737182 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2117 12:17:17.740725 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2118 12:17:17.747514 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2119 12:17:17.750426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2120 12:17:17.753835 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 12:17:17.757284 ===================================
2122 12:17:17.760646 LPDDR4 DRAM CONFIGURATION
2123 12:17:17.763742 ===================================
2124 12:17:17.767091 EX_ROW_EN[0] = 0x0
2125 12:17:17.767174 EX_ROW_EN[1] = 0x0
2126 12:17:17.771011 LP4Y_EN = 0x0
2127 12:17:17.771104 WORK_FSP = 0x0
2128 12:17:17.774080 WL = 0x4
2129 12:17:17.774162 RL = 0x4
2130 12:17:17.777169 BL = 0x2
2131 12:17:17.777251 RPST = 0x0
2132 12:17:17.780390 RD_PRE = 0x0
2133 12:17:17.780487 WR_PRE = 0x1
2134 12:17:17.783888 WR_PST = 0x0
2135 12:17:17.783971 DBI_WR = 0x0
2136 12:17:17.787323 DBI_RD = 0x0
2137 12:17:17.787406 OTF = 0x1
2138 12:17:17.790683 ===================================
2139 12:17:17.793873 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2140 12:17:17.800624 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2141 12:17:17.804078 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 12:17:17.807293 ===================================
2143 12:17:17.810887 LPDDR4 DRAM CONFIGURATION
2144 12:17:17.813976 ===================================
2145 12:17:17.814057 EX_ROW_EN[0] = 0x10
2146 12:17:17.817253 EX_ROW_EN[1] = 0x0
2147 12:17:17.817332 LP4Y_EN = 0x0
2148 12:17:17.820802 WORK_FSP = 0x0
2149 12:17:17.824051 WL = 0x4
2150 12:17:17.824143 RL = 0x4
2151 12:17:17.827551 BL = 0x2
2152 12:17:17.827630 RPST = 0x0
2153 12:17:17.830650 RD_PRE = 0x0
2154 12:17:17.830729 WR_PRE = 0x1
2155 12:17:17.834071 WR_PST = 0x0
2156 12:17:17.834150 DBI_WR = 0x0
2157 12:17:17.837690 DBI_RD = 0x0
2158 12:17:17.837768 OTF = 0x1
2159 12:17:17.840752 ===================================
2160 12:17:17.847504 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2161 12:17:17.847584 ==
2162 12:17:17.850975 Dram Type= 6, Freq= 0, CH_0, rank 0
2163 12:17:17.854167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2164 12:17:17.854247 ==
2165 12:17:17.857793 [Duty_Offset_Calibration]
2166 12:17:17.860964 B0:0 B1:2 CA:1
2167 12:17:17.861043
2168 12:17:17.864073 [DutyScan_Calibration_Flow] k_type=0
2169 12:17:17.871985
2170 12:17:17.872067 ==CLK 0==
2171 12:17:17.875259 Final CLK duty delay cell = 0
2172 12:17:17.878667 [0] MAX Duty = 5093%(X100), DQS PI = 12
2173 12:17:17.881925 [0] MIN Duty = 4938%(X100), DQS PI = 52
2174 12:17:17.882005 [0] AVG Duty = 5015%(X100)
2175 12:17:17.885340
2176 12:17:17.888606 CH0 CLK Duty spec in!! Max-Min= 155%
2177 12:17:17.891963 [DutyScan_Calibration_Flow] ====Done====
2178 12:17:17.892067
2179 12:17:17.895209 [DutyScan_Calibration_Flow] k_type=1
2180 12:17:17.911362
2181 12:17:17.911443 ==DQS 0 ==
2182 12:17:17.914724 Final DQS duty delay cell = 0
2183 12:17:17.918041 [0] MAX Duty = 5125%(X100), DQS PI = 30
2184 12:17:17.921476 [0] MIN Duty = 5031%(X100), DQS PI = 6
2185 12:17:17.921558 [0] AVG Duty = 5078%(X100)
2186 12:17:17.924640
2187 12:17:17.924721 ==DQS 1 ==
2188 12:17:17.927847 Final DQS duty delay cell = 0
2189 12:17:17.931261 [0] MAX Duty = 5062%(X100), DQS PI = 56
2190 12:17:17.934510 [0] MIN Duty = 4906%(X100), DQS PI = 14
2191 12:17:17.934591 [0] AVG Duty = 4984%(X100)
2192 12:17:17.938007
2193 12:17:17.941354 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2194 12:17:17.941437
2195 12:17:17.944751 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2196 12:17:17.947965 [DutyScan_Calibration_Flow] ====Done====
2197 12:17:17.948047
2198 12:17:17.951331 [DutyScan_Calibration_Flow] k_type=3
2199 12:17:17.968435
2200 12:17:17.968520 ==DQM 0 ==
2201 12:17:17.971957 Final DQM duty delay cell = 0
2202 12:17:17.974940 [0] MAX Duty = 5156%(X100), DQS PI = 20
2203 12:17:17.978584 [0] MIN Duty = 4969%(X100), DQS PI = 54
2204 12:17:17.981939 [0] AVG Duty = 5062%(X100)
2205 12:17:17.982022
2206 12:17:17.982088 ==DQM 1 ==
2207 12:17:17.985305 Final DQM duty delay cell = 4
2208 12:17:17.988400 [4] MAX Duty = 5187%(X100), DQS PI = 52
2209 12:17:17.991932 [4] MIN Duty = 5000%(X100), DQS PI = 18
2210 12:17:17.992015 [4] AVG Duty = 5093%(X100)
2211 12:17:17.995153
2212 12:17:17.998583 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2213 12:17:17.998666
2214 12:17:18.002006 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2215 12:17:18.005159 [DutyScan_Calibration_Flow] ====Done====
2216 12:17:18.005242
2217 12:17:18.008539 [DutyScan_Calibration_Flow] k_type=2
2218 12:17:18.023517
2219 12:17:18.023599 ==DQ 0 ==
2220 12:17:18.026742 Final DQ duty delay cell = -4
2221 12:17:18.030171 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2222 12:17:18.033400 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2223 12:17:18.036670 [-4] AVG Duty = 4937%(X100)
2224 12:17:18.036752
2225 12:17:18.036818 ==DQ 1 ==
2226 12:17:18.040096 Final DQ duty delay cell = -4
2227 12:17:18.043565 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2228 12:17:18.046761 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2229 12:17:18.049927 [-4] AVG Duty = 4969%(X100)
2230 12:17:18.050009
2231 12:17:18.053384 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2232 12:17:18.053467
2233 12:17:18.056954 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2234 12:17:18.060091 [DutyScan_Calibration_Flow] ====Done====
2235 12:17:18.060181 ==
2236 12:17:18.063334 Dram Type= 6, Freq= 0, CH_1, rank 0
2237 12:17:18.066678 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2238 12:17:18.066762 ==
2239 12:17:18.070009 [Duty_Offset_Calibration]
2240 12:17:18.070091 B0:0 B1:5 CA:-5
2241 12:17:18.070157
2242 12:17:18.073324 [DutyScan_Calibration_Flow] k_type=0
2243 12:17:18.083889
2244 12:17:18.083972 ==CLK 0==
2245 12:17:18.087465 Final CLK duty delay cell = 0
2246 12:17:18.090644 [0] MAX Duty = 5094%(X100), DQS PI = 24
2247 12:17:18.094053 [0] MIN Duty = 4907%(X100), DQS PI = 44
2248 12:17:18.094136 [0] AVG Duty = 5000%(X100)
2249 12:17:18.097426
2250 12:17:18.100777 CH1 CLK Duty spec in!! Max-Min= 187%
2251 12:17:18.104297 [DutyScan_Calibration_Flow] ====Done====
2252 12:17:18.104379
2253 12:17:18.107566 [DutyScan_Calibration_Flow] k_type=1
2254 12:17:18.122527
2255 12:17:18.122609 ==DQS 0 ==
2256 12:17:18.125721 Final DQS duty delay cell = 0
2257 12:17:18.129103 [0] MAX Duty = 5125%(X100), DQS PI = 16
2258 12:17:18.132662 [0] MIN Duty = 4875%(X100), DQS PI = 42
2259 12:17:18.136037 [0] AVG Duty = 5000%(X100)
2260 12:17:18.136118
2261 12:17:18.136213 ==DQS 1 ==
2262 12:17:18.139076 Final DQS duty delay cell = -4
2263 12:17:18.142680 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2264 12:17:18.145710 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2265 12:17:18.149078 [-4] AVG Duty = 4969%(X100)
2266 12:17:18.149159
2267 12:17:18.152505 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2268 12:17:18.152587
2269 12:17:18.155716 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2270 12:17:18.159170 [DutyScan_Calibration_Flow] ====Done====
2271 12:17:18.159252
2272 12:17:18.162290 [DutyScan_Calibration_Flow] k_type=3
2273 12:17:18.177645
2274 12:17:18.177725 ==DQM 0 ==
2275 12:17:18.181028 Final DQM duty delay cell = -4
2276 12:17:18.184648 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2277 12:17:18.187863 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2278 12:17:18.191054 [-4] AVG Duty = 4969%(X100)
2279 12:17:18.191133
2280 12:17:18.191195 ==DQM 1 ==
2281 12:17:18.194336 Final DQM duty delay cell = -4
2282 12:17:18.197748 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2283 12:17:18.201001 [-4] MIN Duty = 4906%(X100), DQS PI = 56
2284 12:17:18.204295 [-4] AVG Duty = 5000%(X100)
2285 12:17:18.204375
2286 12:17:18.207598 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2287 12:17:18.207680
2288 12:17:18.211230 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2289 12:17:18.214309 [DutyScan_Calibration_Flow] ====Done====
2290 12:17:18.214390
2291 12:17:18.217452 [DutyScan_Calibration_Flow] k_type=2
2292 12:17:18.235107
2293 12:17:18.235196 ==DQ 0 ==
2294 12:17:18.238475 Final DQ duty delay cell = 0
2295 12:17:18.241760 [0] MAX Duty = 5062%(X100), DQS PI = 0
2296 12:17:18.245129 [0] MIN Duty = 4938%(X100), DQS PI = 44
2297 12:17:18.245211 [0] AVG Duty = 5000%(X100)
2298 12:17:18.245276
2299 12:17:18.248460 ==DQ 1 ==
2300 12:17:18.251681 Final DQ duty delay cell = 0
2301 12:17:18.254937 [0] MAX Duty = 5031%(X100), DQS PI = 8
2302 12:17:18.258312 [0] MIN Duty = 4907%(X100), DQS PI = 0
2303 12:17:18.258395 [0] AVG Duty = 4969%(X100)
2304 12:17:18.258459
2305 12:17:18.261677 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2306 12:17:18.261759
2307 12:17:18.265158 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2308 12:17:18.271755 [DutyScan_Calibration_Flow] ====Done====
2309 12:17:18.275151 nWR fixed to 30
2310 12:17:18.275233 [ModeRegInit_LP4] CH0 RK0
2311 12:17:18.278670 [ModeRegInit_LP4] CH0 RK1
2312 12:17:18.281625 [ModeRegInit_LP4] CH1 RK0
2313 12:17:18.281733 [ModeRegInit_LP4] CH1 RK1
2314 12:17:18.285241 match AC timing 6
2315 12:17:18.288424 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2316 12:17:18.291860 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2317 12:17:18.298408 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2318 12:17:18.301914 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2319 12:17:18.308284 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2320 12:17:18.308365 ==
2321 12:17:18.311771 Dram Type= 6, Freq= 0, CH_0, rank 0
2322 12:17:18.315193 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2323 12:17:18.315274 ==
2324 12:17:18.321730 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2325 12:17:18.324891 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2326 12:17:18.334843 [CA 0] Center 39 (9~70) winsize 62
2327 12:17:18.337867 [CA 1] Center 39 (9~70) winsize 62
2328 12:17:18.341281 [CA 2] Center 36 (5~67) winsize 63
2329 12:17:18.344601 [CA 3] Center 35 (4~66) winsize 63
2330 12:17:18.348097 [CA 4] Center 34 (3~65) winsize 63
2331 12:17:18.351238 [CA 5] Center 33 (3~64) winsize 62
2332 12:17:18.351345
2333 12:17:18.354715 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2334 12:17:18.354796
2335 12:17:18.358298 [CATrainingPosCal] consider 1 rank data
2336 12:17:18.361529 u2DelayCellTimex100 = 270/100 ps
2337 12:17:18.364663 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2338 12:17:18.368083 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2339 12:17:18.374598 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2340 12:17:18.377887 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2341 12:17:18.381161 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2342 12:17:18.384520 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2343 12:17:18.384602
2344 12:17:18.387713 CA PerBit enable=1, Macro0, CA PI delay=33
2345 12:17:18.387820
2346 12:17:18.391124 [CBTSetCACLKResult] CA Dly = 33
2347 12:17:18.391204 CS Dly: 7 (0~38)
2348 12:17:18.394479 ==
2349 12:17:18.397750 Dram Type= 6, Freq= 0, CH_0, rank 1
2350 12:17:18.401250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2351 12:17:18.401332 ==
2352 12:17:18.404516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2353 12:17:18.411235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2354 12:17:18.420115 [CA 0] Center 39 (8~70) winsize 63
2355 12:17:18.423658 [CA 1] Center 39 (8~70) winsize 63
2356 12:17:18.426714 [CA 2] Center 35 (5~66) winsize 62
2357 12:17:18.430238 [CA 3] Center 35 (4~66) winsize 63
2358 12:17:18.433604 [CA 4] Center 33 (3~64) winsize 62
2359 12:17:18.436892 [CA 5] Center 34 (3~65) winsize 63
2360 12:17:18.436971
2361 12:17:18.440033 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2362 12:17:18.440137
2363 12:17:18.443297 [CATrainingPosCal] consider 2 rank data
2364 12:17:18.446705 u2DelayCellTimex100 = 270/100 ps
2365 12:17:18.450225 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2366 12:17:18.453403 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2367 12:17:18.460161 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2368 12:17:18.463490 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2369 12:17:18.466882 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2370 12:17:18.470525 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2371 12:17:18.470605
2372 12:17:18.473503 CA PerBit enable=1, Macro0, CA PI delay=33
2373 12:17:18.473583
2374 12:17:18.476921 [CBTSetCACLKResult] CA Dly = 33
2375 12:17:18.477000 CS Dly: 7 (0~39)
2376 12:17:18.477063
2377 12:17:18.479972 ----->DramcWriteLeveling(PI) begin...
2378 12:17:18.483451 ==
2379 12:17:18.483552 Dram Type= 6, Freq= 0, CH_0, rank 0
2380 12:17:18.490100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2381 12:17:18.490181 ==
2382 12:17:18.493511 Write leveling (Byte 0): 27 => 27
2383 12:17:18.496755 Write leveling (Byte 1): 25 => 25
2384 12:17:18.500034 DramcWriteLeveling(PI) end<-----
2385 12:17:18.500114
2386 12:17:18.500201 ==
2387 12:17:18.503478 Dram Type= 6, Freq= 0, CH_0, rank 0
2388 12:17:18.506914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2389 12:17:18.507001 ==
2390 12:17:18.510376 [Gating] SW mode calibration
2391 12:17:18.516738 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2392 12:17:18.520130 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2393 12:17:18.526751 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2394 12:17:18.530179 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2395 12:17:18.533489 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2396 12:17:18.540073 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2397 12:17:18.543417 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2398 12:17:18.546609 0 11 20 | B1->B0 | 3131 2c2c | 1 1 | (1 0) (1 0)
2399 12:17:18.553417 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2400 12:17:18.556530 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2401 12:17:18.559857 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2402 12:17:18.566479 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2403 12:17:18.570147 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2404 12:17:18.573180 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2405 12:17:18.580059 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2406 12:17:18.583641 0 12 20 | B1->B0 | 3b3b 4343 | 1 0 | (0 0) (0 0)
2407 12:17:18.586850 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 12:17:18.593292 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2409 12:17:18.596738 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2410 12:17:18.599866 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2411 12:17:18.606568 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2412 12:17:18.610019 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2413 12:17:18.613367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2414 12:17:18.616724 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2415 12:17:18.623182 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2416 12:17:18.626698 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 12:17:18.630158 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 12:17:18.636792 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 12:17:18.639934 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 12:17:18.643430 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 12:17:18.650382 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 12:17:18.653360 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 12:17:18.656842 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 12:17:18.663385 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2425 12:17:18.666783 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2426 12:17:18.670181 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2427 12:17:18.676690 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2428 12:17:18.680068 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2429 12:17:18.683484 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2430 12:17:18.690031 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2431 12:17:18.693935 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2432 12:17:18.696665 Total UI for P1: 0, mck2ui 16
2433 12:17:18.700395 best dqsien dly found for B0: ( 0, 15, 18)
2434 12:17:18.703616 Total UI for P1: 0, mck2ui 16
2435 12:17:18.707203 best dqsien dly found for B1: ( 0, 15, 18)
2436 12:17:18.710006 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2437 12:17:18.713526 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2438 12:17:18.713609
2439 12:17:18.716895 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2440 12:17:18.720090 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2441 12:17:18.723540 [Gating] SW calibration Done
2442 12:17:18.723622 ==
2443 12:17:18.726870 Dram Type= 6, Freq= 0, CH_0, rank 0
2444 12:17:18.730196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2445 12:17:18.730283 ==
2446 12:17:18.733383 RX Vref Scan: 0
2447 12:17:18.733467
2448 12:17:18.736564 RX Vref 0 -> 0, step: 1
2449 12:17:18.736648
2450 12:17:18.736715 RX Delay -40 -> 252, step: 8
2451 12:17:18.743369 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2452 12:17:18.746720 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2453 12:17:18.749981 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2454 12:17:18.753147 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2455 12:17:18.756840 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2456 12:17:18.763289 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2457 12:17:18.766491 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2458 12:17:18.770240 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2459 12:17:18.773176 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2460 12:17:18.776695 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2461 12:17:18.783364 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2462 12:17:18.786510 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2463 12:17:18.789786 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2464 12:17:18.793254 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2465 12:17:18.796775 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2466 12:17:18.803325 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2467 12:17:18.803423 ==
2468 12:17:18.806585 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 12:17:18.810019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2470 12:17:18.810104 ==
2471 12:17:18.810170 DQS Delay:
2472 12:17:18.813294 DQS0 = 0, DQS1 = 0
2473 12:17:18.813376 DQM Delay:
2474 12:17:18.816532 DQM0 = 115, DQM1 = 106
2475 12:17:18.816616 DQ Delay:
2476 12:17:18.820042 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2477 12:17:18.823249 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2478 12:17:18.826478 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2479 12:17:18.830009 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2480 12:17:18.830094
2481 12:17:18.830160
2482 12:17:18.830220 ==
2483 12:17:18.833399 Dram Type= 6, Freq= 0, CH_0, rank 0
2484 12:17:18.840046 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2485 12:17:18.840158 ==
2486 12:17:18.840278
2487 12:17:18.840340
2488 12:17:18.840398 TX Vref Scan disable
2489 12:17:18.843593 == TX Byte 0 ==
2490 12:17:18.847231 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2491 12:17:18.853596 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2492 12:17:18.853678 == TX Byte 1 ==
2493 12:17:18.856875 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2494 12:17:18.863661 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2495 12:17:18.863743 ==
2496 12:17:18.867093 Dram Type= 6, Freq= 0, CH_0, rank 0
2497 12:17:18.870306 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2498 12:17:18.870388 ==
2499 12:17:18.881569 TX Vref=22, minBit 9, minWin=25, winSum=414
2500 12:17:18.884990 TX Vref=24, minBit 8, minWin=25, winSum=422
2501 12:17:18.888159 TX Vref=26, minBit 10, minWin=25, winSum=429
2502 12:17:18.891515 TX Vref=28, minBit 8, minWin=26, winSum=435
2503 12:17:18.894951 TX Vref=30, minBit 8, minWin=25, winSum=429
2504 12:17:18.898466 TX Vref=32, minBit 8, minWin=26, winSum=434
2505 12:17:18.904980 [TxChooseVref] Worse bit 8, Min win 26, Win sum 435, Final Vref 28
2506 12:17:18.905062
2507 12:17:18.908604 Final TX Range 1 Vref 28
2508 12:17:18.908685
2509 12:17:18.908750 ==
2510 12:17:18.911690 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 12:17:18.915163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2512 12:17:18.915244 ==
2513 12:17:18.915309
2514 12:17:18.918255
2515 12:17:18.918335 TX Vref Scan disable
2516 12:17:18.921892 == TX Byte 0 ==
2517 12:17:18.924801 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2518 12:17:18.928764 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2519 12:17:18.931967 == TX Byte 1 ==
2520 12:17:18.935009 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2521 12:17:18.938203 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2522 12:17:18.938284
2523 12:17:18.941822 [DATLAT]
2524 12:17:18.941902 Freq=1200, CH0 RK0
2525 12:17:18.941967
2526 12:17:18.944931 DATLAT Default: 0xd
2527 12:17:18.945012 0, 0xFFFF, sum = 0
2528 12:17:18.948575 1, 0xFFFF, sum = 0
2529 12:17:18.948658 2, 0xFFFF, sum = 0
2530 12:17:18.951799 3, 0xFFFF, sum = 0
2531 12:17:18.951881 4, 0xFFFF, sum = 0
2532 12:17:18.955126 5, 0xFFFF, sum = 0
2533 12:17:18.955208 6, 0xFFFF, sum = 0
2534 12:17:18.958600 7, 0xFFFF, sum = 0
2535 12:17:18.958715 8, 0xFFFF, sum = 0
2536 12:17:18.961517 9, 0xFFFF, sum = 0
2537 12:17:18.965020 10, 0xFFFF, sum = 0
2538 12:17:18.965132 11, 0x0, sum = 1
2539 12:17:18.965201 12, 0x0, sum = 2
2540 12:17:18.968373 13, 0x0, sum = 3
2541 12:17:18.968455 14, 0x0, sum = 4
2542 12:17:18.971568 best_step = 12
2543 12:17:18.971649
2544 12:17:18.971713 ==
2545 12:17:18.974883 Dram Type= 6, Freq= 0, CH_0, rank 0
2546 12:17:18.978204 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2547 12:17:18.978286 ==
2548 12:17:18.981670 RX Vref Scan: 1
2549 12:17:18.981750
2550 12:17:18.981814 Set Vref Range= 32 -> 127
2551 12:17:18.984913
2552 12:17:18.984994 RX Vref 32 -> 127, step: 1
2553 12:17:18.985058
2554 12:17:18.988357 RX Delay -21 -> 252, step: 4
2555 12:17:18.988438
2556 12:17:18.991733 Set Vref, RX VrefLevel [Byte0]: 32
2557 12:17:18.994760 [Byte1]: 32
2558 12:17:18.998119
2559 12:17:18.998199 Set Vref, RX VrefLevel [Byte0]: 33
2560 12:17:19.001383 [Byte1]: 33
2561 12:17:19.006186
2562 12:17:19.006267 Set Vref, RX VrefLevel [Byte0]: 34
2563 12:17:19.009328 [Byte1]: 34
2564 12:17:19.014063
2565 12:17:19.014142 Set Vref, RX VrefLevel [Byte0]: 35
2566 12:17:19.017115 [Byte1]: 35
2567 12:17:19.021945
2568 12:17:19.022023 Set Vref, RX VrefLevel [Byte0]: 36
2569 12:17:19.025221 [Byte1]: 36
2570 12:17:19.029964
2571 12:17:19.030043 Set Vref, RX VrefLevel [Byte0]: 37
2572 12:17:19.033062 [Byte1]: 37
2573 12:17:19.038012
2574 12:17:19.038091 Set Vref, RX VrefLevel [Byte0]: 38
2575 12:17:19.041022 [Byte1]: 38
2576 12:17:19.045634
2577 12:17:19.045713 Set Vref, RX VrefLevel [Byte0]: 39
2578 12:17:19.048924 [Byte1]: 39
2579 12:17:19.053488
2580 12:17:19.053567 Set Vref, RX VrefLevel [Byte0]: 40
2581 12:17:19.056886 [Byte1]: 40
2582 12:17:19.061624
2583 12:17:19.061703 Set Vref, RX VrefLevel [Byte0]: 41
2584 12:17:19.064722 [Byte1]: 41
2585 12:17:19.069680
2586 12:17:19.069764 Set Vref, RX VrefLevel [Byte0]: 42
2587 12:17:19.072714 [Byte1]: 42
2588 12:17:19.077255
2589 12:17:19.077334 Set Vref, RX VrefLevel [Byte0]: 43
2590 12:17:19.080611 [Byte1]: 43
2591 12:17:19.085114
2592 12:17:19.085194 Set Vref, RX VrefLevel [Byte0]: 44
2593 12:17:19.088521 [Byte1]: 44
2594 12:17:19.093114
2595 12:17:19.093193 Set Vref, RX VrefLevel [Byte0]: 45
2596 12:17:19.096517 [Byte1]: 45
2597 12:17:19.101288
2598 12:17:19.101366 Set Vref, RX VrefLevel [Byte0]: 46
2599 12:17:19.104340 [Byte1]: 46
2600 12:17:19.108856
2601 12:17:19.108935 Set Vref, RX VrefLevel [Byte0]: 47
2602 12:17:19.112595 [Byte1]: 47
2603 12:17:19.116985
2604 12:17:19.117064 Set Vref, RX VrefLevel [Byte0]: 48
2605 12:17:19.120063 [Byte1]: 48
2606 12:17:19.124963
2607 12:17:19.125042 Set Vref, RX VrefLevel [Byte0]: 49
2608 12:17:19.128076 [Byte1]: 49
2609 12:17:19.132944
2610 12:17:19.133023 Set Vref, RX VrefLevel [Byte0]: 50
2611 12:17:19.136223 [Byte1]: 50
2612 12:17:19.140673
2613 12:17:19.140751 Set Vref, RX VrefLevel [Byte0]: 51
2614 12:17:19.143896 [Byte1]: 51
2615 12:17:19.148826
2616 12:17:19.148904 Set Vref, RX VrefLevel [Byte0]: 52
2617 12:17:19.152001 [Byte1]: 52
2618 12:17:19.156986
2619 12:17:19.157065 Set Vref, RX VrefLevel [Byte0]: 53
2620 12:17:19.160064 [Byte1]: 53
2621 12:17:19.164307
2622 12:17:19.164412 Set Vref, RX VrefLevel [Byte0]: 54
2623 12:17:19.167770 [Byte1]: 54
2624 12:17:19.172496
2625 12:17:19.172575 Set Vref, RX VrefLevel [Byte0]: 55
2626 12:17:19.175692 [Byte1]: 55
2627 12:17:19.180424
2628 12:17:19.180522 Set Vref, RX VrefLevel [Byte0]: 56
2629 12:17:19.183567 [Byte1]: 56
2630 12:17:19.188305
2631 12:17:19.188386 Set Vref, RX VrefLevel [Byte0]: 57
2632 12:17:19.191657 [Byte1]: 57
2633 12:17:19.196116
2634 12:17:19.196248 Set Vref, RX VrefLevel [Byte0]: 58
2635 12:17:19.199427 [Byte1]: 58
2636 12:17:19.204015
2637 12:17:19.204109 Set Vref, RX VrefLevel [Byte0]: 59
2638 12:17:19.207555 [Byte1]: 59
2639 12:17:19.211857
2640 12:17:19.211940 Set Vref, RX VrefLevel [Byte0]: 60
2641 12:17:19.215239 [Byte1]: 60
2642 12:17:19.220041
2643 12:17:19.220123 Set Vref, RX VrefLevel [Byte0]: 61
2644 12:17:19.223702 [Byte1]: 61
2645 12:17:19.227831
2646 12:17:19.227913 Set Vref, RX VrefLevel [Byte0]: 62
2647 12:17:19.231072 [Byte1]: 62
2648 12:17:19.235834
2649 12:17:19.235916 Set Vref, RX VrefLevel [Byte0]: 63
2650 12:17:19.239119 [Byte1]: 63
2651 12:17:19.243757
2652 12:17:19.243840 Set Vref, RX VrefLevel [Byte0]: 64
2653 12:17:19.247211 [Byte1]: 64
2654 12:17:19.251616
2655 12:17:19.251699 Set Vref, RX VrefLevel [Byte0]: 65
2656 12:17:19.254952 [Byte1]: 65
2657 12:17:19.259374
2658 12:17:19.259456 Set Vref, RX VrefLevel [Byte0]: 66
2659 12:17:19.263025 [Byte1]: 66
2660 12:17:19.267206
2661 12:17:19.267305 Final RX Vref Byte 0 = 47 to rank0
2662 12:17:19.270778 Final RX Vref Byte 1 = 46 to rank0
2663 12:17:19.274184 Final RX Vref Byte 0 = 47 to rank1
2664 12:17:19.277438 Final RX Vref Byte 1 = 46 to rank1==
2665 12:17:19.280999 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 12:17:19.287394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2667 12:17:19.287486 ==
2668 12:17:19.287553 DQS Delay:
2669 12:17:19.287615 DQS0 = 0, DQS1 = 0
2670 12:17:19.291203 DQM Delay:
2671 12:17:19.291287 DQM0 = 114, DQM1 = 105
2672 12:17:19.294132 DQ Delay:
2673 12:17:19.297713 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2674 12:17:19.300890 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2675 12:17:19.304359 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2676 12:17:19.307595 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2677 12:17:19.307678
2678 12:17:19.307744
2679 12:17:19.314040 [DQSOSCAuto] RK0, (LSB)MR18= 0x505, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2680 12:17:19.317328 CH0 RK0: MR19=404, MR18=505
2681 12:17:19.324023 CH0_RK0: MR19=0x404, MR18=0x505, DQSOSC=408, MR23=63, INC=39, DEC=26
2682 12:17:19.324110
2683 12:17:19.327324 ----->DramcWriteLeveling(PI) begin...
2684 12:17:19.327409 ==
2685 12:17:19.330996 Dram Type= 6, Freq= 0, CH_0, rank 1
2686 12:17:19.334189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2687 12:17:19.334274 ==
2688 12:17:19.337589 Write leveling (Byte 0): 26 => 26
2689 12:17:19.340816 Write leveling (Byte 1): 24 => 24
2690 12:17:19.344388 DramcWriteLeveling(PI) end<-----
2691 12:17:19.344472
2692 12:17:19.344538 ==
2693 12:17:19.347412 Dram Type= 6, Freq= 0, CH_0, rank 1
2694 12:17:19.350790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2695 12:17:19.354269 ==
2696 12:17:19.354353 [Gating] SW mode calibration
2697 12:17:19.360905 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2698 12:17:19.367834 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2699 12:17:19.370786 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2700 12:17:19.377494 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2701 12:17:19.381170 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2702 12:17:19.384216 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2703 12:17:19.390901 0 11 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2704 12:17:19.394314 0 11 20 | B1->B0 | 2f2f 2727 | 1 0 | (1 0) (1 0)
2705 12:17:19.397460 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 12:17:19.404305 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2707 12:17:19.407679 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2708 12:17:19.410771 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2709 12:17:19.417492 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2710 12:17:19.420874 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2711 12:17:19.424158 0 12 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
2712 12:17:19.427737 0 12 20 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
2713 12:17:19.434211 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 12:17:19.437495 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 12:17:19.440877 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2716 12:17:19.447668 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2717 12:17:19.450698 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2718 12:17:19.454298 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2719 12:17:19.461094 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2720 12:17:19.464068 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2721 12:17:19.467513 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 12:17:19.474259 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 12:17:19.477497 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 12:17:19.480870 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 12:17:19.487537 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 12:17:19.490876 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 12:17:19.494137 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 12:17:19.500681 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 12:17:19.504294 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 12:17:19.507787 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 12:17:19.514314 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2732 12:17:19.517499 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2733 12:17:19.520757 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2734 12:17:19.524152 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2735 12:17:19.530864 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2736 12:17:19.534302 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2737 12:17:19.537654 Total UI for P1: 0, mck2ui 16
2738 12:17:19.540902 best dqsien dly found for B0: ( 0, 15, 16)
2739 12:17:19.544505 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2740 12:17:19.547441 Total UI for P1: 0, mck2ui 16
2741 12:17:19.550812 best dqsien dly found for B1: ( 0, 15, 18)
2742 12:17:19.554039 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2743 12:17:19.557577 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2744 12:17:19.560879
2745 12:17:19.564213 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2746 12:17:19.567404 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2747 12:17:19.570918 [Gating] SW calibration Done
2748 12:17:19.571000 ==
2749 12:17:19.574167 Dram Type= 6, Freq= 0, CH_0, rank 1
2750 12:17:19.577591 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2751 12:17:19.577673 ==
2752 12:17:19.577738 RX Vref Scan: 0
2753 12:17:19.577799
2754 12:17:19.581054 RX Vref 0 -> 0, step: 1
2755 12:17:19.581135
2756 12:17:19.584137 RX Delay -40 -> 252, step: 8
2757 12:17:19.587664 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2758 12:17:19.591284 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2759 12:17:19.597309 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2760 12:17:19.600898 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2761 12:17:19.604134 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2762 12:17:19.607837 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2763 12:17:19.610837 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2764 12:17:19.614623 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2765 12:17:19.621357 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2766 12:17:19.624202 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2767 12:17:19.627897 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2768 12:17:19.630964 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2769 12:17:19.634120 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2770 12:17:19.640705 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2771 12:17:19.644148 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2772 12:17:19.647475 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2773 12:17:19.647556 ==
2774 12:17:19.650774 Dram Type= 6, Freq= 0, CH_0, rank 1
2775 12:17:19.654245 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2776 12:17:19.654328 ==
2777 12:17:19.657467 DQS Delay:
2778 12:17:19.657548 DQS0 = 0, DQS1 = 0
2779 12:17:19.660692 DQM Delay:
2780 12:17:19.660773 DQM0 = 115, DQM1 = 107
2781 12:17:19.664164 DQ Delay:
2782 12:17:19.667425 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =111
2783 12:17:19.670919 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2784 12:17:19.674011 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2785 12:17:19.677729 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2786 12:17:19.677810
2787 12:17:19.677875
2788 12:17:19.677934 ==
2789 12:17:19.680940 Dram Type= 6, Freq= 0, CH_0, rank 1
2790 12:17:19.684133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2791 12:17:19.684241 ==
2792 12:17:19.684320
2793 12:17:19.684382
2794 12:17:19.687506 TX Vref Scan disable
2795 12:17:19.690915 == TX Byte 0 ==
2796 12:17:19.694362 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2797 12:17:19.697393 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2798 12:17:19.700782 == TX Byte 1 ==
2799 12:17:19.704235 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2800 12:17:19.707341 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2801 12:17:19.707424 ==
2802 12:17:19.710898 Dram Type= 6, Freq= 0, CH_0, rank 1
2803 12:17:19.714286 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2804 12:17:19.714369 ==
2805 12:17:19.727346 TX Vref=22, minBit 5, minWin=25, winSum=414
2806 12:17:19.730508 TX Vref=24, minBit 8, minWin=24, winSum=416
2807 12:17:19.733949 TX Vref=26, minBit 5, minWin=26, winSum=427
2808 12:17:19.737232 TX Vref=28, minBit 9, minWin=25, winSum=422
2809 12:17:19.740710 TX Vref=30, minBit 8, minWin=25, winSum=430
2810 12:17:19.744031 TX Vref=32, minBit 8, minWin=25, winSum=428
2811 12:17:19.750473 [TxChooseVref] Worse bit 5, Min win 26, Win sum 427, Final Vref 26
2812 12:17:19.750558
2813 12:17:19.754053 Final TX Range 1 Vref 26
2814 12:17:19.754137
2815 12:17:19.754202 ==
2816 12:17:19.757374 Dram Type= 6, Freq= 0, CH_0, rank 1
2817 12:17:19.760583 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2818 12:17:19.760668 ==
2819 12:17:19.760735
2820 12:17:19.763935
2821 12:17:19.764019 TX Vref Scan disable
2822 12:17:19.767424 == TX Byte 0 ==
2823 12:17:19.770611 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2824 12:17:19.773726 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2825 12:17:19.777232 == TX Byte 1 ==
2826 12:17:19.780456 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2827 12:17:19.784027 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2828 12:17:19.784111
2829 12:17:19.787296 [DATLAT]
2830 12:17:19.787380 Freq=1200, CH0 RK1
2831 12:17:19.787446
2832 12:17:19.790424 DATLAT Default: 0xc
2833 12:17:19.790507 0, 0xFFFF, sum = 0
2834 12:17:19.793767 1, 0xFFFF, sum = 0
2835 12:17:19.793852 2, 0xFFFF, sum = 0
2836 12:17:19.797372 3, 0xFFFF, sum = 0
2837 12:17:19.797456 4, 0xFFFF, sum = 0
2838 12:17:19.800661 5, 0xFFFF, sum = 0
2839 12:17:19.800745 6, 0xFFFF, sum = 0
2840 12:17:19.803875 7, 0xFFFF, sum = 0
2841 12:17:19.803958 8, 0xFFFF, sum = 0
2842 12:17:19.807236 9, 0xFFFF, sum = 0
2843 12:17:19.810552 10, 0xFFFF, sum = 0
2844 12:17:19.810635 11, 0x0, sum = 1
2845 12:17:19.810703 12, 0x0, sum = 2
2846 12:17:19.814022 13, 0x0, sum = 3
2847 12:17:19.814107 14, 0x0, sum = 4
2848 12:17:19.817267 best_step = 12
2849 12:17:19.817350
2850 12:17:19.817415 ==
2851 12:17:19.820837 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 12:17:19.823884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2853 12:17:19.823968 ==
2854 12:17:19.827383 RX Vref Scan: 0
2855 12:17:19.827467
2856 12:17:19.827532 RX Vref 0 -> 0, step: 1
2857 12:17:19.827593
2858 12:17:19.830500 RX Delay -21 -> 252, step: 4
2859 12:17:19.837601 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2860 12:17:19.840864 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2861 12:17:19.844122 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2862 12:17:19.847505 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2863 12:17:19.850841 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2864 12:17:19.857493 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2865 12:17:19.860838 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2866 12:17:19.864082 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2867 12:17:19.867397 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2868 12:17:19.870750 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2869 12:17:19.877598 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2870 12:17:19.880676 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2871 12:17:19.884091 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2872 12:17:19.887425 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2873 12:17:19.890957 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2874 12:17:19.897574 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2875 12:17:19.897658 ==
2876 12:17:19.900862 Dram Type= 6, Freq= 0, CH_0, rank 1
2877 12:17:19.904406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2878 12:17:19.904490 ==
2879 12:17:19.904557 DQS Delay:
2880 12:17:19.907547 DQS0 = 0, DQS1 = 0
2881 12:17:19.907631 DQM Delay:
2882 12:17:19.910931 DQM0 = 115, DQM1 = 105
2883 12:17:19.911013 DQ Delay:
2884 12:17:19.914155 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2885 12:17:19.917425 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2886 12:17:19.921053 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2887 12:17:19.924169 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2888 12:17:19.924292
2889 12:17:19.924359
2890 12:17:19.934299 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2891 12:17:19.934384 CH0 RK1: MR19=404, MR18=E0E
2892 12:17:19.941105 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2893 12:17:19.944475 [RxdqsGatingPostProcess] freq 1200
2894 12:17:19.951178 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2895 12:17:19.954718 Pre-setting of DQS Precalculation
2896 12:17:19.958054 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2897 12:17:19.958138 ==
2898 12:17:19.961161 Dram Type= 6, Freq= 0, CH_1, rank 0
2899 12:17:19.964517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2900 12:17:19.967651 ==
2901 12:17:19.971285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2902 12:17:19.977746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2903 12:17:19.985907 [CA 0] Center 37 (7~68) winsize 62
2904 12:17:19.989356 [CA 1] Center 37 (6~68) winsize 63
2905 12:17:19.992420 [CA 2] Center 34 (4~65) winsize 62
2906 12:17:19.995609 [CA 3] Center 33 (3~64) winsize 62
2907 12:17:19.999195 [CA 4] Center 32 (1~63) winsize 63
2908 12:17:20.002413 [CA 5] Center 32 (1~63) winsize 63
2909 12:17:20.002497
2910 12:17:20.005602 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2911 12:17:20.005687
2912 12:17:20.008989 [CATrainingPosCal] consider 1 rank data
2913 12:17:20.012408 u2DelayCellTimex100 = 270/100 ps
2914 12:17:20.015777 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2915 12:17:20.019176 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2916 12:17:20.025617 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2917 12:17:20.028995 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2918 12:17:20.032327 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2919 12:17:20.035527 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2920 12:17:20.035610
2921 12:17:20.039138 CA PerBit enable=1, Macro0, CA PI delay=32
2922 12:17:20.039222
2923 12:17:20.042300 [CBTSetCACLKResult] CA Dly = 32
2924 12:17:20.042383 CS Dly: 6 (0~37)
2925 12:17:20.045941 ==
2926 12:17:20.046025 Dram Type= 6, Freq= 0, CH_1, rank 1
2927 12:17:20.052521 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2928 12:17:20.052606 ==
2929 12:17:20.055587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2930 12:17:20.062509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2931 12:17:20.071084 [CA 0] Center 37 (7~68) winsize 62
2932 12:17:20.074633 [CA 1] Center 37 (6~68) winsize 63
2933 12:17:20.077701 [CA 2] Center 34 (3~65) winsize 63
2934 12:17:20.081469 [CA 3] Center 33 (3~64) winsize 62
2935 12:17:20.084385 [CA 4] Center 32 (2~63) winsize 62
2936 12:17:20.087879 [CA 5] Center 32 (2~63) winsize 62
2937 12:17:20.087963
2938 12:17:20.091389 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2939 12:17:20.091472
2940 12:17:20.094684 [CATrainingPosCal] consider 2 rank data
2941 12:17:20.097836 u2DelayCellTimex100 = 270/100 ps
2942 12:17:20.101052 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2943 12:17:20.104662 CA1 delay=37 (6~68),Diff = 5 PI (24 cell)
2944 12:17:20.107879 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2945 12:17:20.114610 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2946 12:17:20.117891 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2947 12:17:20.121253 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2948 12:17:20.121336
2949 12:17:20.124567 CA PerBit enable=1, Macro0, CA PI delay=32
2950 12:17:20.124650
2951 12:17:20.128017 [CBTSetCACLKResult] CA Dly = 32
2952 12:17:20.128102 CS Dly: 6 (0~38)
2953 12:17:20.128179
2954 12:17:20.131269 ----->DramcWriteLeveling(PI) begin...
2955 12:17:20.131354 ==
2956 12:17:20.134632 Dram Type= 6, Freq= 0, CH_1, rank 0
2957 12:17:20.141241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2958 12:17:20.141325 ==
2959 12:17:20.144469 Write leveling (Byte 0): 22 => 22
2960 12:17:20.147912 Write leveling (Byte 1): 24 => 24
2961 12:17:20.147995 DramcWriteLeveling(PI) end<-----
2962 12:17:20.151115
2963 12:17:20.151197 ==
2964 12:17:20.154613 Dram Type= 6, Freq= 0, CH_1, rank 0
2965 12:17:20.158170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2966 12:17:20.158253 ==
2967 12:17:20.161299 [Gating] SW mode calibration
2968 12:17:20.167976 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2969 12:17:20.171129 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2970 12:17:20.177904 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2971 12:17:20.181184 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2972 12:17:20.184610 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2973 12:17:20.191309 0 11 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2974 12:17:20.194419 0 11 16 | B1->B0 | 3030 2828 | 1 0 | (1 0) (1 0)
2975 12:17:20.198018 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2976 12:17:20.204582 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 12:17:20.207961 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2978 12:17:20.211174 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2979 12:17:20.218502 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2980 12:17:20.221043 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2981 12:17:20.224588 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2982 12:17:20.231278 0 12 16 | B1->B0 | 3939 4444 | 1 0 | (0 0) (0 0)
2983 12:17:20.234367 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 12:17:20.237771 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 12:17:20.241307 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 12:17:20.247954 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 12:17:20.251431 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 12:17:20.254767 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2989 12:17:20.261368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2990 12:17:20.264820 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2991 12:17:20.267989 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2992 12:17:20.274709 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 12:17:20.278070 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 12:17:20.281673 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 12:17:20.287972 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 12:17:20.291409 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 12:17:20.294695 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 12:17:20.301227 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 12:17:20.304849 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 12:17:20.307902 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 12:17:20.314693 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 12:17:20.317843 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 12:17:20.321292 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 12:17:20.328067 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 12:17:20.331249 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 12:17:20.334719 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3007 12:17:20.338053 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3008 12:17:20.341311 Total UI for P1: 0, mck2ui 16
3009 12:17:20.344460 best dqsien dly found for B0: ( 0, 15, 16)
3010 12:17:20.347717 Total UI for P1: 0, mck2ui 16
3011 12:17:20.351155 best dqsien dly found for B1: ( 0, 15, 16)
3012 12:17:20.354792 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3013 12:17:20.361212 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3014 12:17:20.361296
3015 12:17:20.364576 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3016 12:17:20.367928 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3017 12:17:20.371098 [Gating] SW calibration Done
3018 12:17:20.371184 ==
3019 12:17:20.374861 Dram Type= 6, Freq= 0, CH_1, rank 0
3020 12:17:20.378093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3021 12:17:20.378177 ==
3022 12:17:20.378243 RX Vref Scan: 0
3023 12:17:20.381251
3024 12:17:20.381333 RX Vref 0 -> 0, step: 1
3025 12:17:20.381400
3026 12:17:20.384542 RX Delay -40 -> 252, step: 8
3027 12:17:20.388039 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3028 12:17:20.391312 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3029 12:17:20.398181 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3030 12:17:20.401023 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3031 12:17:20.404445 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3032 12:17:20.407674 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3033 12:17:20.411084 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3034 12:17:20.417640 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3035 12:17:20.421253 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3036 12:17:20.424698 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3037 12:17:20.427886 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3038 12:17:20.431138 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3039 12:17:20.437742 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3040 12:17:20.441412 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3041 12:17:20.444567 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3042 12:17:20.448027 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3043 12:17:20.448109 ==
3044 12:17:20.451163 Dram Type= 6, Freq= 0, CH_1, rank 0
3045 12:17:20.454584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3046 12:17:20.457886 ==
3047 12:17:20.457968 DQS Delay:
3048 12:17:20.458033 DQS0 = 0, DQS1 = 0
3049 12:17:20.461138 DQM Delay:
3050 12:17:20.461219 DQM0 = 116, DQM1 = 108
3051 12:17:20.464716 DQ Delay:
3052 12:17:20.468111 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3053 12:17:20.471320 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3054 12:17:20.474617 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3055 12:17:20.478340 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3056 12:17:20.478422
3057 12:17:20.478487
3058 12:17:20.478547 ==
3059 12:17:20.481772 Dram Type= 6, Freq= 0, CH_1, rank 0
3060 12:17:20.484866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3061 12:17:20.484949 ==
3062 12:17:20.485015
3063 12:17:20.485077
3064 12:17:20.488008 TX Vref Scan disable
3065 12:17:20.491479 == TX Byte 0 ==
3066 12:17:20.494746 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3067 12:17:20.498209 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3068 12:17:20.501528 == TX Byte 1 ==
3069 12:17:20.504651 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3070 12:17:20.508087 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3071 12:17:20.508170 ==
3072 12:17:20.511626 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 12:17:20.514923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3074 12:17:20.518063 ==
3075 12:17:20.528057 TX Vref=22, minBit 8, minWin=25, winSum=411
3076 12:17:20.531397 TX Vref=24, minBit 8, minWin=25, winSum=422
3077 12:17:20.534702 TX Vref=26, minBit 15, minWin=25, winSum=427
3078 12:17:20.538084 TX Vref=28, minBit 8, minWin=26, winSum=432
3079 12:17:20.541267 TX Vref=30, minBit 8, minWin=26, winSum=432
3080 12:17:20.544515 TX Vref=32, minBit 9, minWin=26, winSum=432
3081 12:17:20.551309 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3082 12:17:20.551391
3083 12:17:20.555124 Final TX Range 1 Vref 28
3084 12:17:20.555205
3085 12:17:20.555269 ==
3086 12:17:20.557881 Dram Type= 6, Freq= 0, CH_1, rank 0
3087 12:17:20.561391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3088 12:17:20.561472 ==
3089 12:17:20.561537
3090 12:17:20.564846
3091 12:17:20.564929 TX Vref Scan disable
3092 12:17:20.567932 == TX Byte 0 ==
3093 12:17:20.571656 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3094 12:17:20.574792 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3095 12:17:20.577956 == TX Byte 1 ==
3096 12:17:20.581339 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3097 12:17:20.584568 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3098 12:17:20.584653
3099 12:17:20.587916 [DATLAT]
3100 12:17:20.587997 Freq=1200, CH1 RK0
3101 12:17:20.588062
3102 12:17:20.591195 DATLAT Default: 0xd
3103 12:17:20.591277 0, 0xFFFF, sum = 0
3104 12:17:20.594632 1, 0xFFFF, sum = 0
3105 12:17:20.594714 2, 0xFFFF, sum = 0
3106 12:17:20.597902 3, 0xFFFF, sum = 0
3107 12:17:20.597985 4, 0xFFFF, sum = 0
3108 12:17:20.601300 5, 0xFFFF, sum = 0
3109 12:17:20.601382 6, 0xFFFF, sum = 0
3110 12:17:20.604796 7, 0xFFFF, sum = 0
3111 12:17:20.604879 8, 0xFFFF, sum = 0
3112 12:17:20.608139 9, 0xFFFF, sum = 0
3113 12:17:20.611500 10, 0xFFFF, sum = 0
3114 12:17:20.611583 11, 0x0, sum = 1
3115 12:17:20.611650 12, 0x0, sum = 2
3116 12:17:20.614938 13, 0x0, sum = 3
3117 12:17:20.615022 14, 0x0, sum = 4
3118 12:17:20.618085 best_step = 12
3119 12:17:20.618168
3120 12:17:20.618233 ==
3121 12:17:20.621553 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 12:17:20.624759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3123 12:17:20.624842 ==
3124 12:17:20.628038 RX Vref Scan: 1
3125 12:17:20.628121
3126 12:17:20.628196 Set Vref Range= 32 -> 127
3127 12:17:20.628300
3128 12:17:20.631500 RX Vref 32 -> 127, step: 1
3129 12:17:20.631582
3130 12:17:20.634733 RX Delay -29 -> 252, step: 4
3131 12:17:20.634816
3132 12:17:20.638041 Set Vref, RX VrefLevel [Byte0]: 32
3133 12:17:20.641309 [Byte1]: 32
3134 12:17:20.644684
3135 12:17:20.644766 Set Vref, RX VrefLevel [Byte0]: 33
3136 12:17:20.647945 [Byte1]: 33
3137 12:17:20.652551
3138 12:17:20.652654 Set Vref, RX VrefLevel [Byte0]: 34
3139 12:17:20.655910 [Byte1]: 34
3140 12:17:20.660476
3141 12:17:20.660559 Set Vref, RX VrefLevel [Byte0]: 35
3142 12:17:20.663528 [Byte1]: 35
3143 12:17:20.668327
3144 12:17:20.668435 Set Vref, RX VrefLevel [Byte0]: 36
3145 12:17:20.671692 [Byte1]: 36
3146 12:17:20.676375
3147 12:17:20.676457 Set Vref, RX VrefLevel [Byte0]: 37
3148 12:17:20.679499 [Byte1]: 37
3149 12:17:20.684329
3150 12:17:20.684416 Set Vref, RX VrefLevel [Byte0]: 38
3151 12:17:20.687541 [Byte1]: 38
3152 12:17:20.692044
3153 12:17:20.692127 Set Vref, RX VrefLevel [Byte0]: 39
3154 12:17:20.695616 [Byte1]: 39
3155 12:17:20.700115
3156 12:17:20.700234 Set Vref, RX VrefLevel [Byte0]: 40
3157 12:17:20.703429 [Byte1]: 40
3158 12:17:20.708080
3159 12:17:20.708163 Set Vref, RX VrefLevel [Byte0]: 41
3160 12:17:20.711633 [Byte1]: 41
3161 12:17:20.716000
3162 12:17:20.716082 Set Vref, RX VrefLevel [Byte0]: 42
3163 12:17:20.719271 [Byte1]: 42
3164 12:17:20.724036
3165 12:17:20.724119 Set Vref, RX VrefLevel [Byte0]: 43
3166 12:17:20.727424 [Byte1]: 43
3167 12:17:20.732004
3168 12:17:20.732086 Set Vref, RX VrefLevel [Byte0]: 44
3169 12:17:20.735425 [Byte1]: 44
3170 12:17:20.739979
3171 12:17:20.740061 Set Vref, RX VrefLevel [Byte0]: 45
3172 12:17:20.743116 [Byte1]: 45
3173 12:17:20.747814
3174 12:17:20.747897 Set Vref, RX VrefLevel [Byte0]: 46
3175 12:17:20.751047 [Byte1]: 46
3176 12:17:20.755916
3177 12:17:20.755998 Set Vref, RX VrefLevel [Byte0]: 47
3178 12:17:20.759238 [Byte1]: 47
3179 12:17:20.763857
3180 12:17:20.763940 Set Vref, RX VrefLevel [Byte0]: 48
3181 12:17:20.767035 [Byte1]: 48
3182 12:17:20.771643
3183 12:17:20.771726 Set Vref, RX VrefLevel [Byte0]: 49
3184 12:17:20.774967 [Byte1]: 49
3185 12:17:20.779850
3186 12:17:20.779933 Set Vref, RX VrefLevel [Byte0]: 50
3187 12:17:20.783180 [Byte1]: 50
3188 12:17:20.787797
3189 12:17:20.787879 Set Vref, RX VrefLevel [Byte0]: 51
3190 12:17:20.791106 [Byte1]: 51
3191 12:17:20.795587
3192 12:17:20.795669 Set Vref, RX VrefLevel [Byte0]: 52
3193 12:17:20.798941 [Byte1]: 52
3194 12:17:20.803465
3195 12:17:20.806727 Set Vref, RX VrefLevel [Byte0]: 53
3196 12:17:20.806828 [Byte1]: 53
3197 12:17:20.811421
3198 12:17:20.811503 Set Vref, RX VrefLevel [Byte0]: 54
3199 12:17:20.814698 [Byte1]: 54
3200 12:17:20.819412
3201 12:17:20.819495 Set Vref, RX VrefLevel [Byte0]: 55
3202 12:17:20.822827 [Byte1]: 55
3203 12:17:20.827428
3204 12:17:20.827510 Set Vref, RX VrefLevel [Byte0]: 56
3205 12:17:20.830818 [Byte1]: 56
3206 12:17:20.835277
3207 12:17:20.835359 Set Vref, RX VrefLevel [Byte0]: 57
3208 12:17:20.838808 [Byte1]: 57
3209 12:17:20.843395
3210 12:17:20.843477 Set Vref, RX VrefLevel [Byte0]: 58
3211 12:17:20.846534 [Byte1]: 58
3212 12:17:20.851330
3213 12:17:20.851416 Set Vref, RX VrefLevel [Byte0]: 59
3214 12:17:20.854587 [Byte1]: 59
3215 12:17:20.859402
3216 12:17:20.859484 Set Vref, RX VrefLevel [Byte0]: 60
3217 12:17:20.862762 [Byte1]: 60
3218 12:17:20.867030
3219 12:17:20.867113 Set Vref, RX VrefLevel [Byte0]: 61
3220 12:17:20.870567 [Byte1]: 61
3221 12:17:20.875086
3222 12:17:20.875168 Set Vref, RX VrefLevel [Byte0]: 62
3223 12:17:20.878440 [Byte1]: 62
3224 12:17:20.883495
3225 12:17:20.883577 Set Vref, RX VrefLevel [Byte0]: 63
3226 12:17:20.886277 [Byte1]: 63
3227 12:17:20.890979
3228 12:17:20.891062 Set Vref, RX VrefLevel [Byte0]: 64
3229 12:17:20.894134 [Byte1]: 64
3230 12:17:20.899168
3231 12:17:20.899250 Set Vref, RX VrefLevel [Byte0]: 65
3232 12:17:20.902248 [Byte1]: 65
3233 12:17:20.906968
3234 12:17:20.907051 Final RX Vref Byte 0 = 53 to rank0
3235 12:17:20.910369 Final RX Vref Byte 1 = 48 to rank0
3236 12:17:20.913545 Final RX Vref Byte 0 = 53 to rank1
3237 12:17:20.916895 Final RX Vref Byte 1 = 48 to rank1==
3238 12:17:20.920340 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 12:17:20.927441 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3240 12:17:20.927525 ==
3241 12:17:20.927592 DQS Delay:
3242 12:17:20.927654 DQS0 = 0, DQS1 = 0
3243 12:17:20.930338 DQM Delay:
3244 12:17:20.930420 DQM0 = 115, DQM1 = 105
3245 12:17:20.933686 DQ Delay:
3246 12:17:20.936882 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3247 12:17:20.940285 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3248 12:17:20.943687 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3249 12:17:20.947142 DQ12 =112, DQ13 =116, DQ14 =112, DQ15 =116
3250 12:17:20.947225
3251 12:17:20.947290
3252 12:17:20.953892 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3253 12:17:20.957198 CH1 RK0: MR19=404, MR18=1818
3254 12:17:20.963769 CH1_RK0: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
3255 12:17:20.963853
3256 12:17:20.967086 ----->DramcWriteLeveling(PI) begin...
3257 12:17:20.967170 ==
3258 12:17:20.970344 Dram Type= 6, Freq= 0, CH_1, rank 1
3259 12:17:20.974050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3260 12:17:20.974133 ==
3261 12:17:20.976874 Write leveling (Byte 0): 21 => 21
3262 12:17:20.980296 Write leveling (Byte 1): 21 => 21
3263 12:17:20.983668 DramcWriteLeveling(PI) end<-----
3264 12:17:20.983750
3265 12:17:20.983817 ==
3266 12:17:20.987106 Dram Type= 6, Freq= 0, CH_1, rank 1
3267 12:17:20.993543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3268 12:17:20.993626 ==
3269 12:17:20.993692 [Gating] SW mode calibration
3270 12:17:21.003559 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3271 12:17:21.006999 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3272 12:17:21.010272 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3273 12:17:21.017097 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3274 12:17:21.020082 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3275 12:17:21.023796 0 11 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
3276 12:17:21.030201 0 11 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
3277 12:17:21.033730 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3278 12:17:21.037789 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3279 12:17:21.043626 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 12:17:21.047082 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3281 12:17:21.050618 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3282 12:17:21.057214 0 12 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3283 12:17:21.060424 0 12 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
3284 12:17:21.063479 0 12 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
3285 12:17:21.070234 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 12:17:21.073614 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3287 12:17:21.077145 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 12:17:21.080154 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3289 12:17:21.087063 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3290 12:17:21.090290 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3291 12:17:21.093622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3292 12:17:21.100634 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3293 12:17:21.103569 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3294 12:17:21.107153 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 12:17:21.113760 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 12:17:21.117183 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 12:17:21.120825 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 12:17:21.127250 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 12:17:21.130579 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 12:17:21.133564 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 12:17:21.140505 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 12:17:21.143702 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 12:17:21.147124 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 12:17:21.153725 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 12:17:21.157317 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 12:17:21.160344 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3307 12:17:21.164079 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3308 12:17:21.170335 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3309 12:17:21.173715 Total UI for P1: 0, mck2ui 16
3310 12:17:21.176968 best dqsien dly found for B0: ( 0, 15, 10)
3311 12:17:21.180383 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3312 12:17:21.183676 Total UI for P1: 0, mck2ui 16
3313 12:17:21.187383 best dqsien dly found for B1: ( 0, 15, 16)
3314 12:17:21.190596 best DQS0 dly(MCK, UI, PI) = (0, 15, 10)
3315 12:17:21.193652 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3316 12:17:21.193733
3317 12:17:21.197171 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 10)
3318 12:17:21.203803 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3319 12:17:21.203885 [Gating] SW calibration Done
3320 12:17:21.203950 ==
3321 12:17:21.207012 Dram Type= 6, Freq= 0, CH_1, rank 1
3322 12:17:21.213686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3323 12:17:21.213768 ==
3324 12:17:21.213833 RX Vref Scan: 0
3325 12:17:21.213894
3326 12:17:21.217003 RX Vref 0 -> 0, step: 1
3327 12:17:21.217084
3328 12:17:21.220611 RX Delay -40 -> 252, step: 8
3329 12:17:21.223845 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3330 12:17:21.227354 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3331 12:17:21.230531 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3332 12:17:21.233867 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3333 12:17:21.240564 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3334 12:17:21.244059 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3335 12:17:21.247317 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3336 12:17:21.250412 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3337 12:17:21.253791 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3338 12:17:21.260533 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3339 12:17:21.264031 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3340 12:17:21.267152 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3341 12:17:21.270500 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3342 12:17:21.274110 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3343 12:17:21.280470 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3344 12:17:21.284060 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3345 12:17:21.284169 ==
3346 12:17:21.286997 Dram Type= 6, Freq= 0, CH_1, rank 1
3347 12:17:21.290921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3348 12:17:21.291004 ==
3349 12:17:21.293759 DQS Delay:
3350 12:17:21.293840 DQS0 = 0, DQS1 = 0
3351 12:17:21.293906 DQM Delay:
3352 12:17:21.297176 DQM0 = 116, DQM1 = 105
3353 12:17:21.297259 DQ Delay:
3354 12:17:21.300610 DQ0 =119, DQ1 =111, DQ2 =111, DQ3 =115
3355 12:17:21.303816 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =115
3356 12:17:21.307269 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3357 12:17:21.310361 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3358 12:17:21.313649
3359 12:17:21.313733
3360 12:17:21.313798 ==
3361 12:17:21.317119 Dram Type= 6, Freq= 0, CH_1, rank 1
3362 12:17:21.320665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3363 12:17:21.320748 ==
3364 12:17:21.320813
3365 12:17:21.320873
3366 12:17:21.323717 TX Vref Scan disable
3367 12:17:21.323798 == TX Byte 0 ==
3368 12:17:21.330526 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3369 12:17:21.334113 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3370 12:17:21.334214 == TX Byte 1 ==
3371 12:17:21.337492 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3372 12:17:21.343999 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3373 12:17:21.344106 ==
3374 12:17:21.347398 Dram Type= 6, Freq= 0, CH_1, rank 1
3375 12:17:21.350452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3376 12:17:21.350536 ==
3377 12:17:21.362354 TX Vref=22, minBit 9, minWin=25, winSum=425
3378 12:17:21.365962 TX Vref=24, minBit 0, minWin=26, winSum=424
3379 12:17:21.369114 TX Vref=26, minBit 4, minWin=26, winSum=430
3380 12:17:21.372497 TX Vref=28, minBit 9, minWin=26, winSum=431
3381 12:17:21.375871 TX Vref=30, minBit 9, minWin=26, winSum=432
3382 12:17:21.379040 TX Vref=32, minBit 0, minWin=26, winSum=429
3383 12:17:21.385581 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 30
3384 12:17:21.385665
3385 12:17:21.389303 Final TX Range 1 Vref 30
3386 12:17:21.389386
3387 12:17:21.389452 ==
3388 12:17:21.392391 Dram Type= 6, Freq= 0, CH_1, rank 1
3389 12:17:21.395803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3390 12:17:21.395887 ==
3391 12:17:21.395953
3392 12:17:21.398968
3393 12:17:21.399050 TX Vref Scan disable
3394 12:17:21.402922 == TX Byte 0 ==
3395 12:17:21.405890 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3396 12:17:21.409207 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3397 12:17:21.412251 == TX Byte 1 ==
3398 12:17:21.415964 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3399 12:17:21.419175 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3400 12:17:21.419258
3401 12:17:21.422250 [DATLAT]
3402 12:17:21.422385 Freq=1200, CH1 RK1
3403 12:17:21.422490
3404 12:17:21.425680 DATLAT Default: 0xc
3405 12:17:21.425796 0, 0xFFFF, sum = 0
3406 12:17:21.429283 1, 0xFFFF, sum = 0
3407 12:17:21.429367 2, 0xFFFF, sum = 0
3408 12:17:21.432482 3, 0xFFFF, sum = 0
3409 12:17:21.432566 4, 0xFFFF, sum = 0
3410 12:17:21.435675 5, 0xFFFF, sum = 0
3411 12:17:21.435758 6, 0xFFFF, sum = 0
3412 12:17:21.438941 7, 0xFFFF, sum = 0
3413 12:17:21.439025 8, 0xFFFF, sum = 0
3414 12:17:21.442209 9, 0xFFFF, sum = 0
3415 12:17:21.445672 10, 0xFFFF, sum = 0
3416 12:17:21.445755 11, 0x0, sum = 1
3417 12:17:21.445823 12, 0x0, sum = 2
3418 12:17:21.448893 13, 0x0, sum = 3
3419 12:17:21.448976 14, 0x0, sum = 4
3420 12:17:21.452316 best_step = 12
3421 12:17:21.452398
3422 12:17:21.452463 ==
3423 12:17:21.455532 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 12:17:21.458923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3425 12:17:21.459006 ==
3426 12:17:21.462222 RX Vref Scan: 0
3427 12:17:21.462303
3428 12:17:21.462368 RX Vref 0 -> 0, step: 1
3429 12:17:21.462430
3430 12:17:21.465858 RX Delay -29 -> 252, step: 4
3431 12:17:21.472572 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3432 12:17:21.475915 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3433 12:17:21.479161 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3434 12:17:21.482622 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3435 12:17:21.485745 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3436 12:17:21.492572 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3437 12:17:21.496036 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3438 12:17:21.499284 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3439 12:17:21.502575 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3440 12:17:21.505948 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3441 12:17:21.512637 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3442 12:17:21.515932 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3443 12:17:21.519199 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3444 12:17:21.522435 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3445 12:17:21.525703 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3446 12:17:21.532421 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3447 12:17:21.532505 ==
3448 12:17:21.535722 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 12:17:21.539069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3450 12:17:21.539152 ==
3451 12:17:21.539218 DQS Delay:
3452 12:17:21.542712 DQS0 = 0, DQS1 = 0
3453 12:17:21.542794 DQM Delay:
3454 12:17:21.545607 DQM0 = 114, DQM1 = 103
3455 12:17:21.545689 DQ Delay:
3456 12:17:21.549032 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3457 12:17:21.552336 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3458 12:17:21.555734 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3459 12:17:21.559102 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3460 12:17:21.559184
3461 12:17:21.559250
3462 12:17:21.568885 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
3463 12:17:21.572254 CH1 RK1: MR19=404, MR18=E0E
3464 12:17:21.575455 CH1_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3465 12:17:21.578932 [RxdqsGatingPostProcess] freq 1200
3466 12:17:21.585862 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3467 12:17:21.589035 Pre-setting of DQS Precalculation
3468 12:17:21.592354 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3469 12:17:21.602165 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3470 12:17:21.608798 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3471 12:17:21.608924
3472 12:17:21.609043
3473 12:17:21.612351 [Calibration Summary] 2400 Mbps
3474 12:17:21.612477 CH 0, Rank 0
3475 12:17:21.615601 SW Impedance : PASS
3476 12:17:21.615703 DUTY Scan : NO K
3477 12:17:21.618762 ZQ Calibration : PASS
3478 12:17:21.622304 Jitter Meter : NO K
3479 12:17:21.622401 CBT Training : PASS
3480 12:17:21.625588 Write leveling : PASS
3481 12:17:21.628804 RX DQS gating : PASS
3482 12:17:21.628901 RX DQ/DQS(RDDQC) : PASS
3483 12:17:21.632186 TX DQ/DQS : PASS
3484 12:17:21.635419 RX DATLAT : PASS
3485 12:17:21.635542 RX DQ/DQS(Engine): PASS
3486 12:17:21.638724 TX OE : NO K
3487 12:17:21.638849 All Pass.
3488 12:17:21.638965
3489 12:17:21.642417 CH 0, Rank 1
3490 12:17:21.642499 SW Impedance : PASS
3491 12:17:21.645763 DUTY Scan : NO K
3492 12:17:21.645872 ZQ Calibration : PASS
3493 12:17:21.648880 Jitter Meter : NO K
3494 12:17:21.652094 CBT Training : PASS
3495 12:17:21.652228 Write leveling : PASS
3496 12:17:21.655821 RX DQS gating : PASS
3497 12:17:21.658921 RX DQ/DQS(RDDQC) : PASS
3498 12:17:21.659028 TX DQ/DQS : PASS
3499 12:17:21.662170 RX DATLAT : PASS
3500 12:17:21.665719 RX DQ/DQS(Engine): PASS
3501 12:17:21.665801 TX OE : NO K
3502 12:17:21.668896 All Pass.
3503 12:17:21.668977
3504 12:17:21.669042 CH 1, Rank 0
3505 12:17:21.672397 SW Impedance : PASS
3506 12:17:21.672479 DUTY Scan : NO K
3507 12:17:21.675706 ZQ Calibration : PASS
3508 12:17:21.679469 Jitter Meter : NO K
3509 12:17:21.679551 CBT Training : PASS
3510 12:17:21.682454 Write leveling : PASS
3511 12:17:21.682536 RX DQS gating : PASS
3512 12:17:21.685490 RX DQ/DQS(RDDQC) : PASS
3513 12:17:21.688828 TX DQ/DQS : PASS
3514 12:17:21.688921 RX DATLAT : PASS
3515 12:17:21.692306 RX DQ/DQS(Engine): PASS
3516 12:17:21.695619 TX OE : NO K
3517 12:17:21.695701 All Pass.
3518 12:17:21.695765
3519 12:17:21.695826 CH 1, Rank 1
3520 12:17:21.699109 SW Impedance : PASS
3521 12:17:21.702288 DUTY Scan : NO K
3522 12:17:21.702370 ZQ Calibration : PASS
3523 12:17:21.705725 Jitter Meter : NO K
3524 12:17:21.709001 CBT Training : PASS
3525 12:17:21.709083 Write leveling : PASS
3526 12:17:21.712343 RX DQS gating : PASS
3527 12:17:21.715777 RX DQ/DQS(RDDQC) : PASS
3528 12:17:21.715859 TX DQ/DQS : PASS
3529 12:17:21.719308 RX DATLAT : PASS
3530 12:17:21.722229 RX DQ/DQS(Engine): PASS
3531 12:17:21.722311 TX OE : NO K
3532 12:17:21.722377 All Pass.
3533 12:17:21.725457
3534 12:17:21.725538 DramC Write-DBI off
3535 12:17:21.729316 PER_BANK_REFRESH: Hybrid Mode
3536 12:17:21.729397 TX_TRACKING: ON
3537 12:17:21.739083 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3538 12:17:21.742345 [FAST_K] Save calibration result to emmc
3539 12:17:21.745523 dramc_set_vcore_voltage set vcore to 650000
3540 12:17:21.748971 Read voltage for 600, 5
3541 12:17:21.749055 Vio18 = 0
3542 12:17:21.752559 Vcore = 650000
3543 12:17:21.752642 Vdram = 0
3544 12:17:21.752708 Vddq = 0
3545 12:17:21.752769 Vmddr = 0
3546 12:17:21.759301 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3547 12:17:21.762355 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3548 12:17:21.766303 MEM_TYPE=3, freq_sel=19
3549 12:17:21.768951 sv_algorithm_assistance_LP4_1600
3550 12:17:21.772341 ============ PULL DRAM RESETB DOWN ============
3551 12:17:21.778985 ========== PULL DRAM RESETB DOWN end =========
3552 12:17:21.782335 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3553 12:17:21.785603 ===================================
3554 12:17:21.789144 LPDDR4 DRAM CONFIGURATION
3555 12:17:21.792579 ===================================
3556 12:17:21.792654 EX_ROW_EN[0] = 0x0
3557 12:17:21.795822 EX_ROW_EN[1] = 0x0
3558 12:17:21.795895 LP4Y_EN = 0x0
3559 12:17:21.799097 WORK_FSP = 0x0
3560 12:17:21.799166 WL = 0x2
3561 12:17:21.802527 RL = 0x2
3562 12:17:21.802600 BL = 0x2
3563 12:17:21.805883 RPST = 0x0
3564 12:17:21.805951 RD_PRE = 0x0
3565 12:17:21.809393 WR_PRE = 0x1
3566 12:17:21.809460 WR_PST = 0x0
3567 12:17:21.812322 DBI_WR = 0x0
3568 12:17:21.812390 DBI_RD = 0x0
3569 12:17:21.815567 OTF = 0x1
3570 12:17:21.819250 ===================================
3571 12:17:21.822514 ===================================
3572 12:17:21.822584 ANA top config
3573 12:17:21.825729 ===================================
3574 12:17:21.829140 DLL_ASYNC_EN = 0
3575 12:17:21.832325 ALL_SLAVE_EN = 1
3576 12:17:21.835887 NEW_RANK_MODE = 1
3577 12:17:21.835984 DLL_IDLE_MODE = 1
3578 12:17:21.838838 LP45_APHY_COMB_EN = 1
3579 12:17:21.842286 TX_ODT_DIS = 1
3580 12:17:21.845456 NEW_8X_MODE = 1
3581 12:17:21.849004 ===================================
3582 12:17:21.852322 ===================================
3583 12:17:21.855736 data_rate = 1200
3584 12:17:21.858898 CKR = 1
3585 12:17:21.858981 DQ_P2S_RATIO = 8
3586 12:17:21.862130 ===================================
3587 12:17:21.865519 CA_P2S_RATIO = 8
3588 12:17:21.868700 DQ_CA_OPEN = 0
3589 12:17:21.871946 DQ_SEMI_OPEN = 0
3590 12:17:21.875624 CA_SEMI_OPEN = 0
3591 12:17:21.875707 CA_FULL_RATE = 0
3592 12:17:21.878734 DQ_CKDIV4_EN = 1
3593 12:17:21.881976 CA_CKDIV4_EN = 1
3594 12:17:21.885405 CA_PREDIV_EN = 0
3595 12:17:21.888893 PH8_DLY = 0
3596 12:17:21.892047 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3597 12:17:21.892130 DQ_AAMCK_DIV = 4
3598 12:17:21.895305 CA_AAMCK_DIV = 4
3599 12:17:21.898664 CA_ADMCK_DIV = 4
3600 12:17:21.901918 DQ_TRACK_CA_EN = 0
3601 12:17:21.905328 CA_PICK = 600
3602 12:17:21.908626 CA_MCKIO = 600
3603 12:17:21.912352 MCKIO_SEMI = 0
3604 12:17:21.912435 PLL_FREQ = 2288
3605 12:17:21.915604 DQ_UI_PI_RATIO = 32
3606 12:17:21.918712 CA_UI_PI_RATIO = 0
3607 12:17:21.921906 ===================================
3608 12:17:21.925498 ===================================
3609 12:17:21.928693 memory_type:LPDDR4
3610 12:17:21.928775 GP_NUM : 10
3611 12:17:21.931902 SRAM_EN : 1
3612 12:17:21.935080 MD32_EN : 0
3613 12:17:21.938631 ===================================
3614 12:17:21.938714 [ANA_INIT] >>>>>>>>>>>>>>
3615 12:17:21.941787 <<<<<< [CONFIGURE PHASE]: ANA_TX
3616 12:17:21.945017 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3617 12:17:21.948431 ===================================
3618 12:17:21.951861 data_rate = 1200,PCW = 0X5800
3619 12:17:21.955203 ===================================
3620 12:17:21.958432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3621 12:17:21.965103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3622 12:17:21.968375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3623 12:17:21.975210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3624 12:17:21.978332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3625 12:17:21.981634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3626 12:17:21.985189 [ANA_INIT] flow start
3627 12:17:21.985271 [ANA_INIT] PLL >>>>>>>>
3628 12:17:21.988062 [ANA_INIT] PLL <<<<<<<<
3629 12:17:21.991612 [ANA_INIT] MIDPI >>>>>>>>
3630 12:17:21.991694 [ANA_INIT] MIDPI <<<<<<<<
3631 12:17:21.994740 [ANA_INIT] DLL >>>>>>>>
3632 12:17:21.998046 [ANA_INIT] flow end
3633 12:17:22.001392 ============ LP4 DIFF to SE enter ============
3634 12:17:22.004796 ============ LP4 DIFF to SE exit ============
3635 12:17:22.008116 [ANA_INIT] <<<<<<<<<<<<<
3636 12:17:22.011643 [Flow] Enable top DCM control >>>>>
3637 12:17:22.014782 [Flow] Enable top DCM control <<<<<
3638 12:17:22.017899 Enable DLL master slave shuffle
3639 12:17:22.021302 ==============================================================
3640 12:17:22.024994 Gating Mode config
3641 12:17:22.031350 ==============================================================
3642 12:17:22.031433 Config description:
3643 12:17:22.041298 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3644 12:17:22.047948 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3645 12:17:22.051525 SELPH_MODE 0: By rank 1: By Phase
3646 12:17:22.057981 ==============================================================
3647 12:17:22.061677 GAT_TRACK_EN = 1
3648 12:17:22.064692 RX_GATING_MODE = 2
3649 12:17:22.067864 RX_GATING_TRACK_MODE = 2
3650 12:17:22.071232 SELPH_MODE = 1
3651 12:17:22.074700 PICG_EARLY_EN = 1
3652 12:17:22.077845 VALID_LAT_VALUE = 1
3653 12:17:22.081068 ==============================================================
3654 12:17:22.084819 Enter into Gating configuration >>>>
3655 12:17:22.087915 Exit from Gating configuration <<<<
3656 12:17:22.091298 Enter into DVFS_PRE_config >>>>>
3657 12:17:22.104316 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3658 12:17:22.104401 Exit from DVFS_PRE_config <<<<<
3659 12:17:22.107561 Enter into PICG configuration >>>>
3660 12:17:22.111069 Exit from PICG configuration <<<<
3661 12:17:22.114335 [RX_INPUT] configuration >>>>>
3662 12:17:22.117680 [RX_INPUT] configuration <<<<<
3663 12:17:22.124162 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3664 12:17:22.127547 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3665 12:17:22.134268 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3666 12:17:22.140815 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3667 12:17:22.147248 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3668 12:17:22.153912 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3669 12:17:22.157334 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3670 12:17:22.160654 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3671 12:17:22.163909 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3672 12:17:22.170528 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3673 12:17:22.173937 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3674 12:17:22.177211 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3675 12:17:22.180368 ===================================
3676 12:17:22.183886 LPDDR4 DRAM CONFIGURATION
3677 12:17:22.187125 ===================================
3678 12:17:22.190402 EX_ROW_EN[0] = 0x0
3679 12:17:22.190490 EX_ROW_EN[1] = 0x0
3680 12:17:22.193702 LP4Y_EN = 0x0
3681 12:17:22.193785 WORK_FSP = 0x0
3682 12:17:22.196985 WL = 0x2
3683 12:17:22.197067 RL = 0x2
3684 12:17:22.200187 BL = 0x2
3685 12:17:22.200316 RPST = 0x0
3686 12:17:22.203674 RD_PRE = 0x0
3687 12:17:22.203756 WR_PRE = 0x1
3688 12:17:22.207278 WR_PST = 0x0
3689 12:17:22.207361 DBI_WR = 0x0
3690 12:17:22.210048 DBI_RD = 0x0
3691 12:17:22.210132 OTF = 0x1
3692 12:17:22.213454 ===================================
3693 12:17:22.220385 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3694 12:17:22.223313 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3695 12:17:22.226697 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3696 12:17:22.230112 ===================================
3697 12:17:22.233765 LPDDR4 DRAM CONFIGURATION
3698 12:17:22.236552 ===================================
3699 12:17:22.239909 EX_ROW_EN[0] = 0x10
3700 12:17:22.239993 EX_ROW_EN[1] = 0x0
3701 12:17:22.243153 LP4Y_EN = 0x0
3702 12:17:22.243236 WORK_FSP = 0x0
3703 12:17:22.246514 WL = 0x2
3704 12:17:22.246597 RL = 0x2
3705 12:17:22.249657 BL = 0x2
3706 12:17:22.249739 RPST = 0x0
3707 12:17:22.253025 RD_PRE = 0x0
3708 12:17:22.253115 WR_PRE = 0x1
3709 12:17:22.256707 WR_PST = 0x0
3710 12:17:22.256791 DBI_WR = 0x0
3711 12:17:22.259763 DBI_RD = 0x0
3712 12:17:22.259846 OTF = 0x1
3713 12:17:22.263296 ===================================
3714 12:17:22.269581 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3715 12:17:22.274266 nWR fixed to 30
3716 12:17:22.277516 [ModeRegInit_LP4] CH0 RK0
3717 12:17:22.277602 [ModeRegInit_LP4] CH0 RK1
3718 12:17:22.281367 [ModeRegInit_LP4] CH1 RK0
3719 12:17:22.284278 [ModeRegInit_LP4] CH1 RK1
3720 12:17:22.284363 match AC timing 16
3721 12:17:22.290839 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3722 12:17:22.294196 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3723 12:17:22.297363 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3724 12:17:22.303880 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3725 12:17:22.307731 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3726 12:17:22.307819 ==
3727 12:17:22.310939 Dram Type= 6, Freq= 0, CH_0, rank 0
3728 12:17:22.314081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3729 12:17:22.314174 ==
3730 12:17:22.320544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3731 12:17:22.327176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3732 12:17:22.330331 [CA 0] Center 35 (5~66) winsize 62
3733 12:17:22.333604 [CA 1] Center 35 (5~66) winsize 62
3734 12:17:22.337073 [CA 2] Center 34 (4~65) winsize 62
3735 12:17:22.340663 [CA 3] Center 34 (4~65) winsize 62
3736 12:17:22.343618 [CA 4] Center 33 (3~64) winsize 62
3737 12:17:22.347039 [CA 5] Center 33 (3~64) winsize 62
3738 12:17:22.347123
3739 12:17:22.350234 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3740 12:17:22.350316
3741 12:17:22.353484 [CATrainingPosCal] consider 1 rank data
3742 12:17:22.356824 u2DelayCellTimex100 = 270/100 ps
3743 12:17:22.360160 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3744 12:17:22.363569 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3745 12:17:22.366995 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3746 12:17:22.370234 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3747 12:17:22.376728 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3748 12:17:22.380284 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3749 12:17:22.380385
3750 12:17:22.383412 CA PerBit enable=1, Macro0, CA PI delay=33
3751 12:17:22.383495
3752 12:17:22.386724 [CBTSetCACLKResult] CA Dly = 33
3753 12:17:22.386807 CS Dly: 5 (0~36)
3754 12:17:22.386872 ==
3755 12:17:22.389989 Dram Type= 6, Freq= 0, CH_0, rank 1
3756 12:17:22.396603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3757 12:17:22.396708 ==
3758 12:17:22.400394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3759 12:17:22.406770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3760 12:17:22.410050 [CA 0] Center 35 (5~66) winsize 62
3761 12:17:22.412995 [CA 1] Center 35 (5~66) winsize 62
3762 12:17:22.416787 [CA 2] Center 34 (4~65) winsize 62
3763 12:17:22.419779 [CA 3] Center 34 (4~65) winsize 62
3764 12:17:22.423007 [CA 4] Center 33 (2~64) winsize 63
3765 12:17:22.426487 [CA 5] Center 33 (3~64) winsize 62
3766 12:17:22.426586
3767 12:17:22.429941 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3768 12:17:22.430030
3769 12:17:22.432999 [CATrainingPosCal] consider 2 rank data
3770 12:17:22.436343 u2DelayCellTimex100 = 270/100 ps
3771 12:17:22.439930 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3772 12:17:22.443017 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3773 12:17:22.446388 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3774 12:17:22.453339 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3775 12:17:22.456307 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3776 12:17:22.459815 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3777 12:17:22.459905
3778 12:17:22.462917 CA PerBit enable=1, Macro0, CA PI delay=33
3779 12:17:22.463003
3780 12:17:22.466462 [CBTSetCACLKResult] CA Dly = 33
3781 12:17:22.466547 CS Dly: 5 (0~37)
3782 12:17:22.466614
3783 12:17:22.469523 ----->DramcWriteLeveling(PI) begin...
3784 12:17:22.473108 ==
3785 12:17:22.473198 Dram Type= 6, Freq= 0, CH_0, rank 0
3786 12:17:22.479430 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3787 12:17:22.479525 ==
3788 12:17:22.483088 Write leveling (Byte 0): 30 => 30
3789 12:17:22.486110 Write leveling (Byte 1): 30 => 30
3790 12:17:22.489330 DramcWriteLeveling(PI) end<-----
3791 12:17:22.489420
3792 12:17:22.489487 ==
3793 12:17:22.492876 Dram Type= 6, Freq= 0, CH_0, rank 0
3794 12:17:22.496105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3795 12:17:22.496235 ==
3796 12:17:22.499304 [Gating] SW mode calibration
3797 12:17:22.505872 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3798 12:17:22.512587 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3799 12:17:22.516018 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3800 12:17:22.519182 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3801 12:17:22.525738 0 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3802 12:17:22.529057 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 12:17:22.532415 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 12:17:22.535701 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 12:17:22.542389 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 12:17:22.545661 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 12:17:22.548890 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3808 12:17:22.555777 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3809 12:17:22.558742 0 6 8 | B1->B0 | 2626 3434 | 0 1 | (0 0) (0 0)
3810 12:17:22.561991 0 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3811 12:17:22.568681 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 12:17:22.572195 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 12:17:22.575302 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 12:17:22.582092 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 12:17:22.585357 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3816 12:17:22.588590 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3817 12:17:22.595169 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3818 12:17:22.598503 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3819 12:17:22.601702 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 12:17:22.608474 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 12:17:22.611785 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 12:17:22.615020 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 12:17:22.621387 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 12:17:22.624729 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 12:17:22.628022 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 12:17:22.634750 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 12:17:22.638113 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 12:17:22.641391 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 12:17:22.648016 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 12:17:22.651228 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 12:17:22.654670 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 12:17:22.661636 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 12:17:22.664513 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3834 12:17:22.667680 Total UI for P1: 0, mck2ui 16
3835 12:17:22.671228 best dqsien dly found for B0: ( 0, 9, 6)
3836 12:17:22.674509 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3837 12:17:22.677946 Total UI for P1: 0, mck2ui 16
3838 12:17:22.681257 best dqsien dly found for B1: ( 0, 9, 8)
3839 12:17:22.684461 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3840 12:17:22.687807 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3841 12:17:22.687893
3842 12:17:22.694429 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3843 12:17:22.697763 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3844 12:17:22.697857 [Gating] SW calibration Done
3845 12:17:22.700947 ==
3846 12:17:22.704409 Dram Type= 6, Freq= 0, CH_0, rank 0
3847 12:17:22.707770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3848 12:17:22.707858 ==
3849 12:17:22.707924 RX Vref Scan: 0
3850 12:17:22.707985
3851 12:17:22.711076 RX Vref 0 -> 0, step: 1
3852 12:17:22.711160
3853 12:17:22.714606 RX Delay -230 -> 252, step: 16
3854 12:17:22.717874 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3855 12:17:22.720897 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3856 12:17:22.727509 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3857 12:17:22.730839 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3858 12:17:22.733861 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3859 12:17:22.737227 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3860 12:17:22.744031 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3861 12:17:22.747553 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3862 12:17:22.750640 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3863 12:17:22.753894 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
3864 12:17:22.757238 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3865 12:17:22.763725 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3866 12:17:22.766851 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3867 12:17:22.770325 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3868 12:17:22.776949 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3869 12:17:22.780539 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3870 12:17:22.780636 ==
3871 12:17:22.783516 Dram Type= 6, Freq= 0, CH_0, rank 0
3872 12:17:22.786751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3873 12:17:22.786838 ==
3874 12:17:22.790181 DQS Delay:
3875 12:17:22.790270 DQS0 = 0, DQS1 = 0
3876 12:17:22.790336 DQM Delay:
3877 12:17:22.793367 DQM0 = 38, DQM1 = 34
3878 12:17:22.793451 DQ Delay:
3879 12:17:22.796597 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3880 12:17:22.799911 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3881 12:17:22.803485 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
3882 12:17:22.806558 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3883 12:17:22.806647
3884 12:17:22.806713
3885 12:17:22.806775 ==
3886 12:17:22.809932 Dram Type= 6, Freq= 0, CH_0, rank 0
3887 12:17:22.816568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3888 12:17:22.816666 ==
3889 12:17:22.816733
3890 12:17:22.816794
3891 12:17:22.816854 TX Vref Scan disable
3892 12:17:22.819981 == TX Byte 0 ==
3893 12:17:22.823225 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3894 12:17:22.829871 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3895 12:17:22.829987 == TX Byte 1 ==
3896 12:17:22.833432 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3897 12:17:22.839853 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3898 12:17:22.839955 ==
3899 12:17:22.843057 Dram Type= 6, Freq= 0, CH_0, rank 0
3900 12:17:22.846483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3901 12:17:22.846571 ==
3902 12:17:22.846637
3903 12:17:22.846698
3904 12:17:22.849618 TX Vref Scan disable
3905 12:17:22.853058 == TX Byte 0 ==
3906 12:17:22.856159 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3907 12:17:22.859581 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3908 12:17:22.863057 == TX Byte 1 ==
3909 12:17:22.866429 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3910 12:17:22.869539 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3911 12:17:22.869630
3912 12:17:22.869697 [DATLAT]
3913 12:17:22.873090 Freq=600, CH0 RK0
3914 12:17:22.873179
3915 12:17:22.876469 DATLAT Default: 0x9
3916 12:17:22.876554 0, 0xFFFF, sum = 0
3917 12:17:22.879673 1, 0xFFFF, sum = 0
3918 12:17:22.879759 2, 0xFFFF, sum = 0
3919 12:17:22.882723 3, 0xFFFF, sum = 0
3920 12:17:22.882808 4, 0xFFFF, sum = 0
3921 12:17:22.886247 5, 0xFFFF, sum = 0
3922 12:17:22.886332 6, 0xFFFF, sum = 0
3923 12:17:22.889252 7, 0x0, sum = 1
3924 12:17:22.889337 8, 0x0, sum = 2
3925 12:17:22.892636 9, 0x0, sum = 3
3926 12:17:22.892726 10, 0x0, sum = 4
3927 12:17:22.892794 best_step = 8
3928 12:17:22.892854
3929 12:17:22.895860 ==
3930 12:17:22.895943 Dram Type= 6, Freq= 0, CH_0, rank 0
3931 12:17:22.902808 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3932 12:17:22.902905 ==
3933 12:17:22.902973 RX Vref Scan: 1
3934 12:17:22.903033
3935 12:17:22.906017 RX Vref 0 -> 0, step: 1
3936 12:17:22.906100
3937 12:17:22.909612 RX Delay -179 -> 252, step: 8
3938 12:17:22.909697
3939 12:17:22.912621 Set Vref, RX VrefLevel [Byte0]: 47
3940 12:17:22.915849 [Byte1]: 46
3941 12:17:22.915948
3942 12:17:22.919304 Final RX Vref Byte 0 = 47 to rank0
3943 12:17:22.922194 Final RX Vref Byte 1 = 46 to rank0
3944 12:17:22.925484 Final RX Vref Byte 0 = 47 to rank1
3945 12:17:22.928786 Final RX Vref Byte 1 = 46 to rank1==
3946 12:17:22.932260 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 12:17:22.935736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3948 12:17:22.939033 ==
3949 12:17:22.939121 DQS Delay:
3950 12:17:22.939187 DQS0 = 0, DQS1 = 0
3951 12:17:22.942243 DQM Delay:
3952 12:17:22.942326 DQM0 = 39, DQM1 = 30
3953 12:17:22.945512 DQ Delay:
3954 12:17:22.945596 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3955 12:17:22.948735 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
3956 12:17:22.951994 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3957 12:17:22.955278 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
3958 12:17:22.958538
3959 12:17:22.958626
3960 12:17:22.965303 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3961 12:17:22.968756 CH0 RK0: MR19=808, MR18=5959
3962 12:17:22.975419 CH0_RK0: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
3963 12:17:22.975543
3964 12:17:22.978304 ----->DramcWriteLeveling(PI) begin...
3965 12:17:22.978391 ==
3966 12:17:22.981661 Dram Type= 6, Freq= 0, CH_0, rank 1
3967 12:17:22.984999 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3968 12:17:22.985088 ==
3969 12:17:22.988390 Write leveling (Byte 0): 31 => 31
3970 12:17:22.991776 Write leveling (Byte 1): 28 => 28
3971 12:17:22.995134 DramcWriteLeveling(PI) end<-----
3972 12:17:22.995222
3973 12:17:22.995288 ==
3974 12:17:22.998323 Dram Type= 6, Freq= 0, CH_0, rank 1
3975 12:17:23.001542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3976 12:17:23.001631 ==
3977 12:17:23.005111 [Gating] SW mode calibration
3978 12:17:23.011505 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3979 12:17:23.018214 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3980 12:17:23.021422 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 12:17:23.027943 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 12:17:23.031273 0 5 8 | B1->B0 | 3232 3232 | 0 0 | (0 1) (0 0)
3983 12:17:23.034629 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3984 12:17:23.041349 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 12:17:23.044594 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 12:17:23.047820 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 12:17:23.054592 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 12:17:23.057794 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 12:17:23.060915 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 12:17:23.067697 0 6 8 | B1->B0 | 2929 3434 | 0 0 | (0 0) (0 0)
3991 12:17:23.070985 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3992 12:17:23.074336 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 12:17:23.080959 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 12:17:23.084248 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 12:17:23.087485 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 12:17:23.094164 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 12:17:23.097554 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3998 12:17:23.100759 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3999 12:17:23.103931 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:17:23.110762 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:17:23.113931 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:17:23.117496 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:17:23.123713 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:17:23.127091 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:17:23.130642 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:17:23.137351 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:17:23.140418 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:17:23.143628 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:17:23.150353 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:17:23.153742 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 12:17:23.156771 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:17:23.163643 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:17:23.166723 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:17:23.170255 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4015 12:17:23.176693 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 12:17:23.180074 Total UI for P1: 0, mck2ui 16
4017 12:17:23.183435 best dqsien dly found for B0: ( 0, 9, 8)
4018 12:17:23.186591 Total UI for P1: 0, mck2ui 16
4019 12:17:23.189843 best dqsien dly found for B1: ( 0, 9, 8)
4020 12:17:23.193350 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4021 12:17:23.196603 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4022 12:17:23.196694
4023 12:17:23.199875 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4024 12:17:23.203327 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4025 12:17:23.206509 [Gating] SW calibration Done
4026 12:17:23.206596 ==
4027 12:17:23.209849 Dram Type= 6, Freq= 0, CH_0, rank 1
4028 12:17:23.213295 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4029 12:17:23.213384 ==
4030 12:17:23.216240 RX Vref Scan: 0
4031 12:17:23.216324
4032 12:17:23.216390 RX Vref 0 -> 0, step: 1
4033 12:17:23.219623
4034 12:17:23.219706 RX Delay -230 -> 252, step: 16
4035 12:17:23.226305 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4036 12:17:23.229443 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4037 12:17:23.232745 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4038 12:17:23.236121 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4039 12:17:23.242782 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4040 12:17:23.246126 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4041 12:17:23.249580 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4042 12:17:23.252865 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4043 12:17:23.256058 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4044 12:17:23.262716 iDelay=218, Bit 9, Center 17 (-134 ~ 169) 304
4045 12:17:23.266491 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4046 12:17:23.269239 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4047 12:17:23.272479 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4048 12:17:23.279337 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4049 12:17:23.282491 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4050 12:17:23.285864 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4051 12:17:23.285952 ==
4052 12:17:23.289248 Dram Type= 6, Freq= 0, CH_0, rank 1
4053 12:17:23.292385 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4054 12:17:23.295674 ==
4055 12:17:23.295764 DQS Delay:
4056 12:17:23.295829 DQS0 = 0, DQS1 = 0
4057 12:17:23.299046 DQM Delay:
4058 12:17:23.299130 DQM0 = 44, DQM1 = 34
4059 12:17:23.302566 DQ Delay:
4060 12:17:23.302651 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4061 12:17:23.305706 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4062 12:17:23.308867 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4063 12:17:23.312276 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4064 12:17:23.316021
4065 12:17:23.316108
4066 12:17:23.316206 ==
4067 12:17:23.319003 Dram Type= 6, Freq= 0, CH_0, rank 1
4068 12:17:23.322342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4069 12:17:23.322429 ==
4070 12:17:23.322496
4071 12:17:23.322557
4072 12:17:23.325404 TX Vref Scan disable
4073 12:17:23.325489 == TX Byte 0 ==
4074 12:17:23.332180 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4075 12:17:23.335671 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4076 12:17:23.335760 == TX Byte 1 ==
4077 12:17:23.342077 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4078 12:17:23.345417 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4079 12:17:23.345507 ==
4080 12:17:23.348735 Dram Type= 6, Freq= 0, CH_0, rank 1
4081 12:17:23.352007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4082 12:17:23.352093 ==
4083 12:17:23.352160
4084 12:17:23.352230
4085 12:17:23.355202 TX Vref Scan disable
4086 12:17:23.358552 == TX Byte 0 ==
4087 12:17:23.361753 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4088 12:17:23.368644 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4089 12:17:23.368737 == TX Byte 1 ==
4090 12:17:23.371882 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4091 12:17:23.378497 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4092 12:17:23.378600
4093 12:17:23.378668 [DATLAT]
4094 12:17:23.378730 Freq=600, CH0 RK1
4095 12:17:23.378791
4096 12:17:23.381920 DATLAT Default: 0x8
4097 12:17:23.382004 0, 0xFFFF, sum = 0
4098 12:17:23.385111 1, 0xFFFF, sum = 0
4099 12:17:23.388554 2, 0xFFFF, sum = 0
4100 12:17:23.388641 3, 0xFFFF, sum = 0
4101 12:17:23.391792 4, 0xFFFF, sum = 0
4102 12:17:23.391927 5, 0xFFFF, sum = 0
4103 12:17:23.394985 6, 0xFFFF, sum = 0
4104 12:17:23.395072 7, 0x0, sum = 1
4105 12:17:23.395140 8, 0x0, sum = 2
4106 12:17:23.398799 9, 0x0, sum = 3
4107 12:17:23.398886 10, 0x0, sum = 4
4108 12:17:23.401536 best_step = 8
4109 12:17:23.401621
4110 12:17:23.401687 ==
4111 12:17:23.405018 Dram Type= 6, Freq= 0, CH_0, rank 1
4112 12:17:23.408381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4113 12:17:23.408469 ==
4114 12:17:23.411668 RX Vref Scan: 0
4115 12:17:23.411751
4116 12:17:23.411817 RX Vref 0 -> 0, step: 1
4117 12:17:23.411877
4118 12:17:23.414728 RX Delay -179 -> 252, step: 8
4119 12:17:23.422391 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4120 12:17:23.425789 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4121 12:17:23.428706 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4122 12:17:23.432526 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4123 12:17:23.438505 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4124 12:17:23.441993 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4125 12:17:23.445270 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4126 12:17:23.448467 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4127 12:17:23.455236 iDelay=205, Bit 8, Center 24 (-123 ~ 172) 296
4128 12:17:23.458498 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4129 12:17:23.461746 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4130 12:17:23.465223 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4131 12:17:23.471544 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4132 12:17:23.474910 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4133 12:17:23.478103 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4134 12:17:23.481730 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4135 12:17:23.481819 ==
4136 12:17:23.484956 Dram Type= 6, Freq= 0, CH_0, rank 1
4137 12:17:23.491525 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4138 12:17:23.491635 ==
4139 12:17:23.491705 DQS Delay:
4140 12:17:23.491767 DQS0 = 0, DQS1 = 0
4141 12:17:23.494968 DQM Delay:
4142 12:17:23.495052 DQM0 = 41, DQM1 = 32
4143 12:17:23.498255 DQ Delay:
4144 12:17:23.501647 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4145 12:17:23.504690 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4146 12:17:23.508169 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =24
4147 12:17:23.511359 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4148 12:17:23.511456
4149 12:17:23.511524
4150 12:17:23.518559 [DQSOSCAuto] RK1, (LSB)MR18= 0x6767, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
4151 12:17:23.521546 CH0 RK1: MR19=808, MR18=6767
4152 12:17:23.527868 CH0_RK1: MR19=0x808, MR18=0x6767, DQSOSC=390, MR23=63, INC=172, DEC=114
4153 12:17:23.531374 [RxdqsGatingPostProcess] freq 600
4154 12:17:23.534669 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4155 12:17:23.538137 Pre-setting of DQS Precalculation
4156 12:17:23.544495 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4157 12:17:23.544609 ==
4158 12:17:23.547809 Dram Type= 6, Freq= 0, CH_1, rank 0
4159 12:17:23.551398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4160 12:17:23.551489 ==
4161 12:17:23.557639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4162 12:17:23.564213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4163 12:17:23.567468 [CA 0] Center 35 (5~66) winsize 62
4164 12:17:23.570734 [CA 1] Center 35 (4~66) winsize 63
4165 12:17:23.574290 [CA 2] Center 33 (3~64) winsize 62
4166 12:17:23.577537 [CA 3] Center 33 (3~64) winsize 62
4167 12:17:23.581075 [CA 4] Center 33 (2~64) winsize 63
4168 12:17:23.583823 [CA 5] Center 33 (2~64) winsize 63
4169 12:17:23.583909
4170 12:17:23.587409 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4171 12:17:23.587496
4172 12:17:23.590783 [CATrainingPosCal] consider 1 rank data
4173 12:17:23.593906 u2DelayCellTimex100 = 270/100 ps
4174 12:17:23.597315 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4175 12:17:23.600827 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4176 12:17:23.603912 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4177 12:17:23.607174 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4178 12:17:23.610618 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4179 12:17:23.614017 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4180 12:17:23.614106
4181 12:17:23.620530 CA PerBit enable=1, Macro0, CA PI delay=33
4182 12:17:23.620629
4183 12:17:23.620698 [CBTSetCACLKResult] CA Dly = 33
4184 12:17:23.623986 CS Dly: 4 (0~35)
4185 12:17:23.624073 ==
4186 12:17:23.627052 Dram Type= 6, Freq= 0, CH_1, rank 1
4187 12:17:23.630549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4188 12:17:23.630638 ==
4189 12:17:23.636863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4190 12:17:23.643751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4191 12:17:23.647245 [CA 0] Center 35 (5~66) winsize 62
4192 12:17:23.650537 [CA 1] Center 34 (4~65) winsize 62
4193 12:17:23.654026 [CA 2] Center 33 (3~64) winsize 62
4194 12:17:23.656860 [CA 3] Center 33 (3~64) winsize 62
4195 12:17:23.660144 [CA 4] Center 32 (2~63) winsize 62
4196 12:17:23.663786 [CA 5] Center 32 (2~63) winsize 62
4197 12:17:23.663880
4198 12:17:23.666989 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4199 12:17:23.667077
4200 12:17:23.670276 [CATrainingPosCal] consider 2 rank data
4201 12:17:23.673573 u2DelayCellTimex100 = 270/100 ps
4202 12:17:23.676919 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4203 12:17:23.680128 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4204 12:17:23.683395 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4205 12:17:23.686727 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4206 12:17:23.690574 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4207 12:17:23.693477 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4208 12:17:23.696873
4209 12:17:23.700107 CA PerBit enable=1, Macro0, CA PI delay=32
4210 12:17:23.700237
4211 12:17:23.703300 [CBTSetCACLKResult] CA Dly = 32
4212 12:17:23.703385 CS Dly: 5 (0~37)
4213 12:17:23.703452
4214 12:17:23.706716 ----->DramcWriteLeveling(PI) begin...
4215 12:17:23.706801 ==
4216 12:17:23.709877 Dram Type= 6, Freq= 0, CH_1, rank 0
4217 12:17:23.713242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4218 12:17:23.716635 ==
4219 12:17:23.716720 Write leveling (Byte 0): 29 => 29
4220 12:17:23.719938 Write leveling (Byte 1): 28 => 28
4221 12:17:23.723214 DramcWriteLeveling(PI) end<-----
4222 12:17:23.723298
4223 12:17:23.723364 ==
4224 12:17:23.726423 Dram Type= 6, Freq= 0, CH_1, rank 0
4225 12:17:23.732981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4226 12:17:23.733097 ==
4227 12:17:23.733186 [Gating] SW mode calibration
4228 12:17:23.743147 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4229 12:17:23.746373 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4230 12:17:23.752942 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 12:17:23.756553 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4232 12:17:23.759679 0 5 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 1) (0 0)
4233 12:17:23.762948 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 12:17:23.769879 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 12:17:23.773079 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 12:17:23.776673 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 12:17:23.782857 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 12:17:23.786113 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 12:17:23.789519 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4240 12:17:23.796306 0 6 8 | B1->B0 | 3434 4040 | 0 0 | (0 0) (0 0)
4241 12:17:23.799357 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 12:17:23.803198 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 12:17:23.809704 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 12:17:23.812917 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 12:17:23.816096 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 12:17:23.822902 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 12:17:23.826287 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4248 12:17:23.829442 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4249 12:17:23.836025 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:17:23.839230 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:17:23.842504 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:17:23.849656 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:17:23.852665 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:17:23.856069 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:17:23.862689 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:17:23.865666 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:17:23.869084 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:17:23.875695 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:17:23.879064 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:17:23.882148 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:17:23.888949 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:17:23.892166 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:17:23.895965 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4264 12:17:23.902203 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 12:17:23.902312 Total UI for P1: 0, mck2ui 16
4266 12:17:23.908829 best dqsien dly found for B0: ( 0, 9, 4)
4267 12:17:23.908930 Total UI for P1: 0, mck2ui 16
4268 12:17:23.912106 best dqsien dly found for B1: ( 0, 9, 6)
4269 12:17:23.918627 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4270 12:17:23.922011 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4271 12:17:23.922106
4272 12:17:23.925336 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4273 12:17:23.928610 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4274 12:17:23.931891 [Gating] SW calibration Done
4275 12:17:23.931979 ==
4276 12:17:23.935304 Dram Type= 6, Freq= 0, CH_1, rank 0
4277 12:17:23.938543 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4278 12:17:23.938629 ==
4279 12:17:23.942069 RX Vref Scan: 0
4280 12:17:23.942166
4281 12:17:23.942230 RX Vref 0 -> 0, step: 1
4282 12:17:23.942289
4283 12:17:23.945018 RX Delay -230 -> 252, step: 16
4284 12:17:23.948507 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4285 12:17:23.955257 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4286 12:17:23.958564 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4287 12:17:23.961698 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4288 12:17:23.965205 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4289 12:17:23.971874 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4290 12:17:23.975447 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4291 12:17:23.978583 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4292 12:17:23.982196 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4293 12:17:23.984972 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4294 12:17:23.991550 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4295 12:17:23.994924 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4296 12:17:23.998092 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4297 12:17:24.001685 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4298 12:17:24.008242 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4299 12:17:24.011420 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4300 12:17:24.011520 ==
4301 12:17:24.014759 Dram Type= 6, Freq= 0, CH_1, rank 0
4302 12:17:24.018304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4303 12:17:24.018394 ==
4304 12:17:24.021421 DQS Delay:
4305 12:17:24.021504 DQS0 = 0, DQS1 = 0
4306 12:17:24.021568 DQM Delay:
4307 12:17:24.024701 DQM0 = 39, DQM1 = 32
4308 12:17:24.024784 DQ Delay:
4309 12:17:24.028362 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4310 12:17:24.031215 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4311 12:17:24.034694 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4312 12:17:24.038161 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4313 12:17:24.038250
4314 12:17:24.038331
4315 12:17:24.038401 ==
4316 12:17:24.041295 Dram Type= 6, Freq= 0, CH_1, rank 0
4317 12:17:24.047770 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4318 12:17:24.047864 ==
4319 12:17:24.047933
4320 12:17:24.047994
4321 12:17:24.048051 TX Vref Scan disable
4322 12:17:24.051667 == TX Byte 0 ==
4323 12:17:24.055243 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4324 12:17:24.061730 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4325 12:17:24.061831 == TX Byte 1 ==
4326 12:17:24.064878 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4327 12:17:24.071774 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4328 12:17:24.071876 ==
4329 12:17:24.074882 Dram Type= 6, Freq= 0, CH_1, rank 0
4330 12:17:24.078164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4331 12:17:24.078253 ==
4332 12:17:24.078317
4333 12:17:24.078377
4334 12:17:24.081572 TX Vref Scan disable
4335 12:17:24.084713 == TX Byte 0 ==
4336 12:17:24.088189 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4337 12:17:24.091232 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4338 12:17:24.094751 == TX Byte 1 ==
4339 12:17:24.098179 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4340 12:17:24.101192 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4341 12:17:24.101279
4342 12:17:24.101342 [DATLAT]
4343 12:17:24.104745 Freq=600, CH1 RK0
4344 12:17:24.104829
4345 12:17:24.104893 DATLAT Default: 0x9
4346 12:17:24.108045 0, 0xFFFF, sum = 0
4347 12:17:24.108126 1, 0xFFFF, sum = 0
4348 12:17:24.111542 2, 0xFFFF, sum = 0
4349 12:17:24.114612 3, 0xFFFF, sum = 0
4350 12:17:24.114751 4, 0xFFFF, sum = 0
4351 12:17:24.118047 5, 0xFFFF, sum = 0
4352 12:17:24.118133 6, 0xFFFF, sum = 0
4353 12:17:24.121267 7, 0x0, sum = 1
4354 12:17:24.121350 8, 0x0, sum = 2
4355 12:17:24.121416 9, 0x0, sum = 3
4356 12:17:24.124646 10, 0x0, sum = 4
4357 12:17:24.124730 best_step = 8
4358 12:17:24.124794
4359 12:17:24.124853 ==
4360 12:17:24.127827 Dram Type= 6, Freq= 0, CH_1, rank 0
4361 12:17:24.134789 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4362 12:17:24.134885 ==
4363 12:17:24.134951 RX Vref Scan: 1
4364 12:17:24.135010
4365 12:17:24.137920 RX Vref 0 -> 0, step: 1
4366 12:17:24.138001
4367 12:17:24.141204 RX Delay -195 -> 252, step: 8
4368 12:17:24.141285
4369 12:17:24.144442 Set Vref, RX VrefLevel [Byte0]: 53
4370 12:17:24.147853 [Byte1]: 48
4371 12:17:24.147937
4372 12:17:24.151271 Final RX Vref Byte 0 = 53 to rank0
4373 12:17:24.154314 Final RX Vref Byte 1 = 48 to rank0
4374 12:17:24.157884 Final RX Vref Byte 0 = 53 to rank1
4375 12:17:24.161212 Final RX Vref Byte 1 = 48 to rank1==
4376 12:17:24.164469 Dram Type= 6, Freq= 0, CH_1, rank 0
4377 12:17:24.167884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4378 12:17:24.167969 ==
4379 12:17:24.170966 DQS Delay:
4380 12:17:24.171049 DQS0 = 0, DQS1 = 0
4381 12:17:24.174149 DQM Delay:
4382 12:17:24.174230 DQM0 = 38, DQM1 = 31
4383 12:17:24.174294 DQ Delay:
4384 12:17:24.177577 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4385 12:17:24.180841 DQ4 =36, DQ5 =52, DQ6 =44, DQ7 =36
4386 12:17:24.184486 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4387 12:17:24.187631 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4388 12:17:24.187718
4389 12:17:24.187782
4390 12:17:24.197391 [DQSOSCAuto] RK0, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4391 12:17:24.201005 CH1 RK0: MR19=808, MR18=7272
4392 12:17:24.207241 CH1_RK0: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4393 12:17:24.207355
4394 12:17:24.210477 ----->DramcWriteLeveling(PI) begin...
4395 12:17:24.210565 ==
4396 12:17:24.213903 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 12:17:24.217467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4398 12:17:24.217556 ==
4399 12:17:24.220668 Write leveling (Byte 0): 30 => 30
4400 12:17:24.223789 Write leveling (Byte 1): 30 => 30
4401 12:17:24.227419 DramcWriteLeveling(PI) end<-----
4402 12:17:24.227507
4403 12:17:24.227571 ==
4404 12:17:24.230518 Dram Type= 6, Freq= 0, CH_1, rank 1
4405 12:17:24.233813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4406 12:17:24.233901 ==
4407 12:17:24.237177 [Gating] SW mode calibration
4408 12:17:24.243731 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4409 12:17:24.250291 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4410 12:17:24.253951 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 12:17:24.257152 0 5 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
4412 12:17:24.263395 0 5 8 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
4413 12:17:24.266752 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 12:17:24.270201 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 12:17:24.276671 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 12:17:24.280085 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 12:17:24.283396 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 12:17:24.290079 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 12:17:24.293349 0 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4420 12:17:24.296510 0 6 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4421 12:17:24.303258 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 12:17:24.306439 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 12:17:24.309773 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 12:17:24.316352 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 12:17:24.320169 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 12:17:24.323370 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 12:17:24.329993 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4428 12:17:24.333106 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:17:24.336357 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:17:24.342895 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:17:24.346147 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:17:24.349593 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:17:24.356223 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:17:24.359671 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:17:24.362879 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:17:24.369505 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:17:24.372742 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:17:24.375792 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:17:24.382524 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:17:24.385967 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:17:24.389047 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:17:24.395920 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 12:17:24.399486 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4444 12:17:24.402705 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 12:17:24.405934 Total UI for P1: 0, mck2ui 16
4446 12:17:24.409059 best dqsien dly found for B0: ( 0, 9, 4)
4447 12:17:24.412340 Total UI for P1: 0, mck2ui 16
4448 12:17:24.415823 best dqsien dly found for B1: ( 0, 9, 6)
4449 12:17:24.419185 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4450 12:17:24.422476 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4451 12:17:24.422562
4452 12:17:24.425892 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4453 12:17:24.432562 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4454 12:17:24.432657 [Gating] SW calibration Done
4455 12:17:24.432725 ==
4456 12:17:24.435457 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 12:17:24.441987 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4458 12:17:24.442085 ==
4459 12:17:24.442153 RX Vref Scan: 0
4460 12:17:24.442215
4461 12:17:24.445621 RX Vref 0 -> 0, step: 1
4462 12:17:24.445706
4463 12:17:24.448762 RX Delay -230 -> 252, step: 16
4464 12:17:24.452301 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4465 12:17:24.455415 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4466 12:17:24.462014 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4467 12:17:24.465298 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4468 12:17:24.468630 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4469 12:17:24.471626 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4470 12:17:24.475026 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4471 12:17:24.481646 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4472 12:17:24.484913 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4473 12:17:24.488438 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4474 12:17:24.491595 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4475 12:17:24.498176 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4476 12:17:24.501720 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4477 12:17:24.504855 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4478 12:17:24.508054 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4479 12:17:24.514574 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4480 12:17:24.514687 ==
4481 12:17:24.518663 Dram Type= 6, Freq= 0, CH_1, rank 1
4482 12:17:24.521319 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4483 12:17:24.521408 ==
4484 12:17:24.521516 DQS Delay:
4485 12:17:24.524801 DQS0 = 0, DQS1 = 0
4486 12:17:24.524887 DQM Delay:
4487 12:17:24.527911 DQM0 = 39, DQM1 = 34
4488 12:17:24.527997 DQ Delay:
4489 12:17:24.531359 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4490 12:17:24.534872 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4491 12:17:24.537748 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4492 12:17:24.540990 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4493 12:17:24.541081
4494 12:17:24.541148
4495 12:17:24.541210 ==
4496 12:17:24.544458 Dram Type= 6, Freq= 0, CH_1, rank 1
4497 12:17:24.547731 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4498 12:17:24.551328 ==
4499 12:17:24.551417
4500 12:17:24.551484
4501 12:17:24.551546 TX Vref Scan disable
4502 12:17:24.554197 == TX Byte 0 ==
4503 12:17:24.557509 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4504 12:17:24.561037 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4505 12:17:24.564344 == TX Byte 1 ==
4506 12:17:24.567701 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4507 12:17:24.570882 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4508 12:17:24.574139 ==
4509 12:17:24.577395 Dram Type= 6, Freq= 0, CH_1, rank 1
4510 12:17:24.580709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4511 12:17:24.580799 ==
4512 12:17:24.580866
4513 12:17:24.580928
4514 12:17:24.584319 TX Vref Scan disable
4515 12:17:24.584405 == TX Byte 0 ==
4516 12:17:24.590607 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4517 12:17:24.594204 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4518 12:17:24.597204 == TX Byte 1 ==
4519 12:17:24.600956 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4520 12:17:24.603920 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4521 12:17:24.604013
4522 12:17:24.604079 [DATLAT]
4523 12:17:24.607020 Freq=600, CH1 RK1
4524 12:17:24.607109
4525 12:17:24.607177 DATLAT Default: 0x8
4526 12:17:24.610517 0, 0xFFFF, sum = 0
4527 12:17:24.613857 1, 0xFFFF, sum = 0
4528 12:17:24.613945 2, 0xFFFF, sum = 0
4529 12:17:24.617087 3, 0xFFFF, sum = 0
4530 12:17:24.617173 4, 0xFFFF, sum = 0
4531 12:17:24.620782 5, 0xFFFF, sum = 0
4532 12:17:24.620871 6, 0xFFFF, sum = 0
4533 12:17:24.623595 7, 0x0, sum = 1
4534 12:17:24.623681 8, 0x0, sum = 2
4535 12:17:24.623749 9, 0x0, sum = 3
4536 12:17:24.627240 10, 0x0, sum = 4
4537 12:17:24.627327 best_step = 8
4538 12:17:24.627394
4539 12:17:24.627456 ==
4540 12:17:24.630400 Dram Type= 6, Freq= 0, CH_1, rank 1
4541 12:17:24.636876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4542 12:17:24.636976 ==
4543 12:17:24.637042 RX Vref Scan: 0
4544 12:17:24.637103
4545 12:17:24.640309 RX Vref 0 -> 0, step: 1
4546 12:17:24.640393
4547 12:17:24.643648 RX Delay -195 -> 252, step: 8
4548 12:17:24.646787 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4549 12:17:24.653483 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4550 12:17:24.657102 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4551 12:17:24.660200 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4552 12:17:24.663991 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4553 12:17:24.670135 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4554 12:17:24.673416 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4555 12:17:24.676931 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4556 12:17:24.680168 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4557 12:17:24.683487 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4558 12:17:24.690083 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4559 12:17:24.693566 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4560 12:17:24.696627 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4561 12:17:24.699785 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4562 12:17:24.706626 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4563 12:17:24.709674 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4564 12:17:24.709771 ==
4565 12:17:24.713088 Dram Type= 6, Freq= 0, CH_1, rank 1
4566 12:17:24.716225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4567 12:17:24.716316 ==
4568 12:17:24.719714 DQS Delay:
4569 12:17:24.719814 DQS0 = 0, DQS1 = 0
4570 12:17:24.722974 DQM Delay:
4571 12:17:24.723058 DQM0 = 37, DQM1 = 29
4572 12:17:24.723123 DQ Delay:
4573 12:17:24.726518 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4574 12:17:24.729521 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4575 12:17:24.733001 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4576 12:17:24.736331 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4577 12:17:24.736418
4578 12:17:24.736484
4579 12:17:24.746049 [DQSOSCAuto] RK1, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4580 12:17:24.749537 CH1 RK1: MR19=808, MR18=5858
4581 12:17:24.756142 CH1_RK1: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4582 12:17:24.756318 [RxdqsGatingPostProcess] freq 600
4583 12:17:24.762751 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4584 12:17:24.766036 Pre-setting of DQS Precalculation
4585 12:17:24.769392 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4586 12:17:24.779019 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4587 12:17:24.785594 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4588 12:17:24.785705
4589 12:17:24.785774
4590 12:17:24.788908 [Calibration Summary] 1200 Mbps
4591 12:17:24.788993 CH 0, Rank 0
4592 12:17:24.792406 SW Impedance : PASS
4593 12:17:24.792490 DUTY Scan : NO K
4594 12:17:24.795605 ZQ Calibration : PASS
4595 12:17:24.798866 Jitter Meter : NO K
4596 12:17:24.798954 CBT Training : PASS
4597 12:17:24.802378 Write leveling : PASS
4598 12:17:24.805779 RX DQS gating : PASS
4599 12:17:24.805865 RX DQ/DQS(RDDQC) : PASS
4600 12:17:24.808799 TX DQ/DQS : PASS
4601 12:17:24.812431 RX DATLAT : PASS
4602 12:17:24.812516 RX DQ/DQS(Engine): PASS
4603 12:17:24.815468 TX OE : NO K
4604 12:17:24.815555 All Pass.
4605 12:17:24.815621
4606 12:17:24.819011 CH 0, Rank 1
4607 12:17:24.819097 SW Impedance : PASS
4608 12:17:24.822087 DUTY Scan : NO K
4609 12:17:24.825577 ZQ Calibration : PASS
4610 12:17:24.825664 Jitter Meter : NO K
4611 12:17:24.828656 CBT Training : PASS
4612 12:17:24.831989 Write leveling : PASS
4613 12:17:24.832078 RX DQS gating : PASS
4614 12:17:24.835314 RX DQ/DQS(RDDQC) : PASS
4615 12:17:24.838603 TX DQ/DQS : PASS
4616 12:17:24.838688 RX DATLAT : PASS
4617 12:17:24.842087 RX DQ/DQS(Engine): PASS
4618 12:17:24.845373 TX OE : NO K
4619 12:17:24.845460 All Pass.
4620 12:17:24.845527
4621 12:17:24.845588 CH 1, Rank 0
4622 12:17:24.848458 SW Impedance : PASS
4623 12:17:24.852079 DUTY Scan : NO K
4624 12:17:24.852249 ZQ Calibration : PASS
4625 12:17:24.855161 Jitter Meter : NO K
4626 12:17:24.855245 CBT Training : PASS
4627 12:17:24.858450 Write leveling : PASS
4628 12:17:24.861973 RX DQS gating : PASS
4629 12:17:24.862060 RX DQ/DQS(RDDQC) : PASS
4630 12:17:24.864963 TX DQ/DQS : PASS
4631 12:17:24.868346 RX DATLAT : PASS
4632 12:17:24.868432 RX DQ/DQS(Engine): PASS
4633 12:17:24.871583 TX OE : NO K
4634 12:17:24.871669 All Pass.
4635 12:17:24.871736
4636 12:17:24.875005 CH 1, Rank 1
4637 12:17:24.875089 SW Impedance : PASS
4638 12:17:24.878341 DUTY Scan : NO K
4639 12:17:24.881584 ZQ Calibration : PASS
4640 12:17:24.881670 Jitter Meter : NO K
4641 12:17:24.885087 CBT Training : PASS
4642 12:17:24.888277 Write leveling : PASS
4643 12:17:24.888363 RX DQS gating : PASS
4644 12:17:24.891752 RX DQ/DQS(RDDQC) : PASS
4645 12:17:24.894981 TX DQ/DQS : PASS
4646 12:17:24.895072 RX DATLAT : PASS
4647 12:17:24.898204 RX DQ/DQS(Engine): PASS
4648 12:17:24.901683 TX OE : NO K
4649 12:17:24.901772 All Pass.
4650 12:17:24.901839
4651 12:17:24.901901 DramC Write-DBI off
4652 12:17:24.904824 PER_BANK_REFRESH: Hybrid Mode
4653 12:17:24.908431 TX_TRACKING: ON
4654 12:17:24.914640 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4655 12:17:24.918184 [FAST_K] Save calibration result to emmc
4656 12:17:24.924613 dramc_set_vcore_voltage set vcore to 662500
4657 12:17:24.924712 Read voltage for 933, 3
4658 12:17:24.928299 Vio18 = 0
4659 12:17:24.928446 Vcore = 662500
4660 12:17:24.928524 Vdram = 0
4661 12:17:24.928585 Vddq = 0
4662 12:17:24.931384 Vmddr = 0
4663 12:17:24.934392 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4664 12:17:24.941011 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4665 12:17:24.944609 MEM_TYPE=3, freq_sel=17
4666 12:17:24.947894 sv_algorithm_assistance_LP4_1600
4667 12:17:24.951201 ============ PULL DRAM RESETB DOWN ============
4668 12:17:24.954581 ========== PULL DRAM RESETB DOWN end =========
4669 12:17:24.957651 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4670 12:17:24.961026 ===================================
4671 12:17:24.964164 LPDDR4 DRAM CONFIGURATION
4672 12:17:24.967658 ===================================
4673 12:17:24.970894 EX_ROW_EN[0] = 0x0
4674 12:17:24.971036 EX_ROW_EN[1] = 0x0
4675 12:17:24.974222 LP4Y_EN = 0x0
4676 12:17:24.974305 WORK_FSP = 0x0
4677 12:17:24.977557 WL = 0x3
4678 12:17:24.977653 RL = 0x3
4679 12:17:24.981110 BL = 0x2
4680 12:17:24.981194 RPST = 0x0
4681 12:17:24.984341 RD_PRE = 0x0
4682 12:17:24.984425 WR_PRE = 0x1
4683 12:17:24.987731 WR_PST = 0x0
4684 12:17:24.990987 DBI_WR = 0x0
4685 12:17:24.991073 DBI_RD = 0x0
4686 12:17:24.994235 OTF = 0x1
4687 12:17:24.997594 ===================================
4688 12:17:25.000895 ===================================
4689 12:17:25.000984 ANA top config
4690 12:17:25.004080 ===================================
4691 12:17:25.007385 DLL_ASYNC_EN = 0
4692 12:17:25.010577 ALL_SLAVE_EN = 1
4693 12:17:25.010664 NEW_RANK_MODE = 1
4694 12:17:25.014081 DLL_IDLE_MODE = 1
4695 12:17:25.017435 LP45_APHY_COMB_EN = 1
4696 12:17:25.020597 TX_ODT_DIS = 1
4697 12:17:25.020683 NEW_8X_MODE = 1
4698 12:17:25.024124 ===================================
4699 12:17:25.027230 ===================================
4700 12:17:25.030649 data_rate = 1866
4701 12:17:25.033833 CKR = 1
4702 12:17:25.037056 DQ_P2S_RATIO = 8
4703 12:17:25.040406 ===================================
4704 12:17:25.043784 CA_P2S_RATIO = 8
4705 12:17:25.047154 DQ_CA_OPEN = 0
4706 12:17:25.047241 DQ_SEMI_OPEN = 0
4707 12:17:25.050484 CA_SEMI_OPEN = 0
4708 12:17:25.053743 CA_FULL_RATE = 0
4709 12:17:25.057032 DQ_CKDIV4_EN = 1
4710 12:17:25.060376 CA_CKDIV4_EN = 1
4711 12:17:25.063751 CA_PREDIV_EN = 0
4712 12:17:25.063840 PH8_DLY = 0
4713 12:17:25.066871 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4714 12:17:25.070741 DQ_AAMCK_DIV = 4
4715 12:17:25.073514 CA_AAMCK_DIV = 4
4716 12:17:25.076826 CA_ADMCK_DIV = 4
4717 12:17:25.080219 DQ_TRACK_CA_EN = 0
4718 12:17:25.080322 CA_PICK = 933
4719 12:17:25.083414 CA_MCKIO = 933
4720 12:17:25.086984 MCKIO_SEMI = 0
4721 12:17:25.090366 PLL_FREQ = 3732
4722 12:17:25.093611 DQ_UI_PI_RATIO = 32
4723 12:17:25.096844 CA_UI_PI_RATIO = 0
4724 12:17:25.100388 ===================================
4725 12:17:25.103472 ===================================
4726 12:17:25.106716 memory_type:LPDDR4
4727 12:17:25.106806 GP_NUM : 10
4728 12:17:25.110239 SRAM_EN : 1
4729 12:17:25.110325 MD32_EN : 0
4730 12:17:25.113334 ===================================
4731 12:17:25.116943 [ANA_INIT] >>>>>>>>>>>>>>
4732 12:17:25.120058 <<<<<< [CONFIGURE PHASE]: ANA_TX
4733 12:17:25.123176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4734 12:17:25.126748 ===================================
4735 12:17:25.129899 data_rate = 1866,PCW = 0X8f00
4736 12:17:25.133511 ===================================
4737 12:17:25.136511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4738 12:17:25.139910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4739 12:17:25.146834 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4740 12:17:25.153141 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4741 12:17:25.156432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4742 12:17:25.159845 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4743 12:17:25.159935 [ANA_INIT] flow start
4744 12:17:25.163249 [ANA_INIT] PLL >>>>>>>>
4745 12:17:25.166536 [ANA_INIT] PLL <<<<<<<<
4746 12:17:25.166624 [ANA_INIT] MIDPI >>>>>>>>
4747 12:17:25.169616 [ANA_INIT] MIDPI <<<<<<<<
4748 12:17:25.173095 [ANA_INIT] DLL >>>>>>>>
4749 12:17:25.173184 [ANA_INIT] flow end
4750 12:17:25.179974 ============ LP4 DIFF to SE enter ============
4751 12:17:25.182843 ============ LP4 DIFF to SE exit ============
4752 12:17:25.182933 [ANA_INIT] <<<<<<<<<<<<<
4753 12:17:25.186250 [Flow] Enable top DCM control >>>>>
4754 12:17:25.189481 [Flow] Enable top DCM control <<<<<
4755 12:17:25.193073 Enable DLL master slave shuffle
4756 12:17:25.199634 ==============================================================
4757 12:17:25.203023 Gating Mode config
4758 12:17:25.206140 ==============================================================
4759 12:17:25.209452 Config description:
4760 12:17:25.219576 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4761 12:17:25.226107 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4762 12:17:25.229339 SELPH_MODE 0: By rank 1: By Phase
4763 12:17:25.236071 ==============================================================
4764 12:17:25.239337 GAT_TRACK_EN = 1
4765 12:17:25.242678 RX_GATING_MODE = 2
4766 12:17:25.246110 RX_GATING_TRACK_MODE = 2
4767 12:17:25.246202 SELPH_MODE = 1
4768 12:17:25.249253 PICG_EARLY_EN = 1
4769 12:17:25.252611 VALID_LAT_VALUE = 1
4770 12:17:25.259306 ==============================================================
4771 12:17:25.263076 Enter into Gating configuration >>>>
4772 12:17:25.266062 Exit from Gating configuration <<<<
4773 12:17:25.269320 Enter into DVFS_PRE_config >>>>>
4774 12:17:25.279057 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4775 12:17:25.282575 Exit from DVFS_PRE_config <<<<<
4776 12:17:25.285669 Enter into PICG configuration >>>>
4777 12:17:25.289009 Exit from PICG configuration <<<<
4778 12:17:25.292527 [RX_INPUT] configuration >>>>>
4779 12:17:25.295709 [RX_INPUT] configuration <<<<<
4780 12:17:25.298913 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4781 12:17:25.305744 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4782 12:17:25.312336 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4783 12:17:25.318923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4784 12:17:25.325550 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4785 12:17:25.329023 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4786 12:17:25.335643 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4787 12:17:25.338994 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4788 12:17:25.342136 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4789 12:17:25.345400 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4790 12:17:25.351830 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4791 12:17:25.355551 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4792 12:17:25.358452 ===================================
4793 12:17:25.363066 LPDDR4 DRAM CONFIGURATION
4794 12:17:25.365184 ===================================
4795 12:17:25.365288 EX_ROW_EN[0] = 0x0
4796 12:17:25.368429 EX_ROW_EN[1] = 0x0
4797 12:17:25.368514 LP4Y_EN = 0x0
4798 12:17:25.371774 WORK_FSP = 0x0
4799 12:17:25.371858 WL = 0x3
4800 12:17:25.375321 RL = 0x3
4801 12:17:25.375406 BL = 0x2
4802 12:17:25.378315 RPST = 0x0
4803 12:17:25.378399 RD_PRE = 0x0
4804 12:17:25.381736 WR_PRE = 0x1
4805 12:17:25.381821 WR_PST = 0x0
4806 12:17:25.385085 DBI_WR = 0x0
4807 12:17:25.388552 DBI_RD = 0x0
4808 12:17:25.388637 OTF = 0x1
4809 12:17:25.391746 ===================================
4810 12:17:25.395044 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4811 12:17:25.398461 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4812 12:17:25.405170 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4813 12:17:25.408462 ===================================
4814 12:17:25.411816 LPDDR4 DRAM CONFIGURATION
4815 12:17:25.414939 ===================================
4816 12:17:25.415029 EX_ROW_EN[0] = 0x10
4817 12:17:25.418374 EX_ROW_EN[1] = 0x0
4818 12:17:25.418460 LP4Y_EN = 0x0
4819 12:17:25.421748 WORK_FSP = 0x0
4820 12:17:25.421833 WL = 0x3
4821 12:17:25.425110 RL = 0x3
4822 12:17:25.425195 BL = 0x2
4823 12:17:25.428206 RPST = 0x0
4824 12:17:25.428292 RD_PRE = 0x0
4825 12:17:25.431517 WR_PRE = 0x1
4826 12:17:25.431603 WR_PST = 0x0
4827 12:17:25.435039 DBI_WR = 0x0
4828 12:17:25.435124 DBI_RD = 0x0
4829 12:17:25.438152 OTF = 0x1
4830 12:17:25.441350 ===================================
4831 12:17:25.448030 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4832 12:17:25.451356 nWR fixed to 30
4833 12:17:25.454657 [ModeRegInit_LP4] CH0 RK0
4834 12:17:25.454749 [ModeRegInit_LP4] CH0 RK1
4835 12:17:25.458022 [ModeRegInit_LP4] CH1 RK0
4836 12:17:25.461413 [ModeRegInit_LP4] CH1 RK1
4837 12:17:25.461500 match AC timing 8
4838 12:17:25.467833 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4839 12:17:25.471381 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4840 12:17:25.474765 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4841 12:17:25.481405 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4842 12:17:25.484392 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4843 12:17:25.484490 ==
4844 12:17:25.488043 Dram Type= 6, Freq= 0, CH_0, rank 0
4845 12:17:25.490994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4846 12:17:25.491083 ==
4847 12:17:25.497666 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4848 12:17:25.504316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4849 12:17:25.507784 [CA 0] Center 38 (8~69) winsize 62
4850 12:17:25.511000 [CA 1] Center 38 (8~69) winsize 62
4851 12:17:25.514574 [CA 2] Center 36 (5~67) winsize 63
4852 12:17:25.517760 [CA 3] Center 36 (6~67) winsize 62
4853 12:17:25.520984 [CA 4] Center 34 (4~65) winsize 62
4854 12:17:25.524414 [CA 5] Center 34 (4~65) winsize 62
4855 12:17:25.524505
4856 12:17:25.527683 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4857 12:17:25.527769
4858 12:17:25.530992 [CATrainingPosCal] consider 1 rank data
4859 12:17:25.534345 u2DelayCellTimex100 = 270/100 ps
4860 12:17:25.537731 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4861 12:17:25.540887 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4862 12:17:25.544612 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4863 12:17:25.547561 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4864 12:17:25.551272 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4865 12:17:25.557754 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4866 12:17:25.557854
4867 12:17:25.560872 CA PerBit enable=1, Macro0, CA PI delay=34
4868 12:17:25.560958
4869 12:17:25.564377 [CBTSetCACLKResult] CA Dly = 34
4870 12:17:25.564463 CS Dly: 7 (0~38)
4871 12:17:25.564529 ==
4872 12:17:25.567659 Dram Type= 6, Freq= 0, CH_0, rank 1
4873 12:17:25.570874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4874 12:17:25.570959 ==
4875 12:17:25.577480 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4876 12:17:25.584341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4877 12:17:25.587607 [CA 0] Center 38 (8~69) winsize 62
4878 12:17:25.590695 [CA 1] Center 38 (7~69) winsize 63
4879 12:17:25.594298 [CA 2] Center 36 (6~67) winsize 62
4880 12:17:25.597602 [CA 3] Center 35 (5~66) winsize 62
4881 12:17:25.601193 [CA 4] Center 34 (4~65) winsize 62
4882 12:17:25.604268 [CA 5] Center 34 (4~65) winsize 62
4883 12:17:25.604364
4884 12:17:25.607637 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4885 12:17:25.607727
4886 12:17:25.610805 [CATrainingPosCal] consider 2 rank data
4887 12:17:25.613977 u2DelayCellTimex100 = 270/100 ps
4888 12:17:25.617472 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4889 12:17:25.620819 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4890 12:17:25.624058 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4891 12:17:25.627535 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4892 12:17:25.633967 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4893 12:17:25.637211 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4894 12:17:25.637310
4895 12:17:25.640621 CA PerBit enable=1, Macro0, CA PI delay=34
4896 12:17:25.640709
4897 12:17:25.643943 [CBTSetCACLKResult] CA Dly = 34
4898 12:17:25.644030 CS Dly: 7 (0~39)
4899 12:17:25.644098
4900 12:17:25.647430 ----->DramcWriteLeveling(PI) begin...
4901 12:17:25.647517 ==
4902 12:17:25.650874 Dram Type= 6, Freq= 0, CH_0, rank 0
4903 12:17:25.657177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4904 12:17:25.657277 ==
4905 12:17:25.660483 Write leveling (Byte 0): 31 => 31
4906 12:17:25.663780 Write leveling (Byte 1): 28 => 28
4907 12:17:25.663869 DramcWriteLeveling(PI) end<-----
4908 12:17:25.663936
4909 12:17:25.667456 ==
4910 12:17:25.667544 Dram Type= 6, Freq= 0, CH_0, rank 0
4911 12:17:25.673793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4912 12:17:25.673892 ==
4913 12:17:25.677126 [Gating] SW mode calibration
4914 12:17:25.683673 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4915 12:17:25.687054 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4916 12:17:25.693604 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4917 12:17:25.696872 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4918 12:17:25.700301 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4919 12:17:25.706948 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4920 12:17:25.710321 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4921 12:17:25.713801 0 10 20 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 1)
4922 12:17:25.720130 0 10 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4923 12:17:25.723682 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4924 12:17:25.726945 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 12:17:25.733414 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4926 12:17:25.736620 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4927 12:17:25.739970 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4928 12:17:25.746604 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 12:17:25.750343 0 11 20 | B1->B0 | 2525 3030 | 1 0 | (0 0) (0 0)
4930 12:17:25.753201 0 11 24 | B1->B0 | 3837 4646 | 1 0 | (0 0) (0 0)
4931 12:17:25.759858 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4932 12:17:25.763238 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 12:17:25.766682 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4934 12:17:25.773184 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4935 12:17:25.776508 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4936 12:17:25.779623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 12:17:25.786322 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4938 12:17:25.789676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 12:17:25.792955 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 12:17:25.799544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 12:17:25.802948 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 12:17:25.806307 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 12:17:25.812781 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 12:17:25.816061 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 12:17:25.819543 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 12:17:25.822972 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 12:17:25.829463 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 12:17:25.833082 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 12:17:25.836500 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 12:17:25.843074 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 12:17:25.846061 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 12:17:25.849418 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4953 12:17:25.856108 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 12:17:25.859293 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4955 12:17:25.862603 Total UI for P1: 0, mck2ui 16
4956 12:17:25.865907 best dqsien dly found for B0: ( 0, 14, 22)
4957 12:17:25.869062 Total UI for P1: 0, mck2ui 16
4958 12:17:25.872673 best dqsien dly found for B1: ( 0, 14, 22)
4959 12:17:25.875762 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4960 12:17:25.879314 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4961 12:17:25.879408
4962 12:17:25.882328 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4963 12:17:25.885855 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4964 12:17:25.889108 [Gating] SW calibration Done
4965 12:17:25.889197 ==
4966 12:17:25.892447 Dram Type= 6, Freq= 0, CH_0, rank 0
4967 12:17:25.898998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4968 12:17:25.899111 ==
4969 12:17:25.899179 RX Vref Scan: 0
4970 12:17:25.899241
4971 12:17:25.902373 RX Vref 0 -> 0, step: 1
4972 12:17:25.902456
4973 12:17:25.905943 RX Delay -80 -> 252, step: 8
4974 12:17:25.909256 iDelay=208, Bit 0, Center 87 (-16 ~ 191) 208
4975 12:17:25.912066 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
4976 12:17:25.915591 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4977 12:17:25.918785 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
4978 12:17:25.925463 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4979 12:17:25.928715 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4980 12:17:25.932070 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4981 12:17:25.935387 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4982 12:17:25.938663 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4983 12:17:25.945378 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
4984 12:17:25.948723 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4985 12:17:25.952232 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4986 12:17:25.955449 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4987 12:17:25.958446 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4988 12:17:25.961964 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4989 12:17:25.968616 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4990 12:17:25.968723 ==
4991 12:17:25.972005 Dram Type= 6, Freq= 0, CH_0, rank 0
4992 12:17:25.975763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4993 12:17:25.975853 ==
4994 12:17:25.975922 DQS Delay:
4995 12:17:25.978523 DQS0 = 0, DQS1 = 0
4996 12:17:25.978620 DQM Delay:
4997 12:17:25.981966 DQM0 = 95, DQM1 = 87
4998 12:17:25.982052 DQ Delay:
4999 12:17:25.985022 DQ0 =87, DQ1 =99, DQ2 =91, DQ3 =87
5000 12:17:25.988597 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5001 12:17:25.991697 DQ8 =79, DQ9 =75, DQ10 =83, DQ11 =79
5002 12:17:25.995107 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5003 12:17:25.995212
5004 12:17:25.995308
5005 12:17:25.995399 ==
5006 12:17:25.998256 Dram Type= 6, Freq= 0, CH_0, rank 0
5007 12:17:26.001646 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5008 12:17:26.004966 ==
5009 12:17:26.005055
5010 12:17:26.005121
5011 12:17:26.005182 TX Vref Scan disable
5012 12:17:26.008324 == TX Byte 0 ==
5013 12:17:26.011613 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5014 12:17:26.014992 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5015 12:17:26.018296 == TX Byte 1 ==
5016 12:17:26.021656 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5017 12:17:26.024992 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5018 12:17:26.028362 ==
5019 12:17:26.028453 Dram Type= 6, Freq= 0, CH_0, rank 0
5020 12:17:26.035089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5021 12:17:26.035193 ==
5022 12:17:26.035262
5023 12:17:26.035326
5024 12:17:26.035385 TX Vref Scan disable
5025 12:17:26.039380 == TX Byte 0 ==
5026 12:17:26.042997 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5027 12:17:26.049374 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5028 12:17:26.049477 == TX Byte 1 ==
5029 12:17:26.052595 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5030 12:17:26.059371 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5031 12:17:26.059474
5032 12:17:26.059544 [DATLAT]
5033 12:17:26.059606 Freq=933, CH0 RK0
5034 12:17:26.059667
5035 12:17:26.062822 DATLAT Default: 0xd
5036 12:17:26.062907 0, 0xFFFF, sum = 0
5037 12:17:26.065973 1, 0xFFFF, sum = 0
5038 12:17:26.066060 2, 0xFFFF, sum = 0
5039 12:17:26.069242 3, 0xFFFF, sum = 0
5040 12:17:26.069331 4, 0xFFFF, sum = 0
5041 12:17:26.072681 5, 0xFFFF, sum = 0
5042 12:17:26.072769 6, 0xFFFF, sum = 0
5043 12:17:26.076008 7, 0xFFFF, sum = 0
5044 12:17:26.079611 8, 0xFFFF, sum = 0
5045 12:17:26.079702 9, 0xFFFF, sum = 0
5046 12:17:26.082849 10, 0x0, sum = 1
5047 12:17:26.082937 11, 0x0, sum = 2
5048 12:17:26.083006 12, 0x0, sum = 3
5049 12:17:26.086132 13, 0x0, sum = 4
5050 12:17:26.086218 best_step = 11
5051 12:17:26.086284
5052 12:17:26.089244 ==
5053 12:17:26.089331 Dram Type= 6, Freq= 0, CH_0, rank 0
5054 12:17:26.096103 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5055 12:17:26.096236 ==
5056 12:17:26.096305 RX Vref Scan: 1
5057 12:17:26.096368
5058 12:17:26.099454 RX Vref 0 -> 0, step: 1
5059 12:17:26.099538
5060 12:17:26.102789 RX Delay -61 -> 252, step: 4
5061 12:17:26.102875
5062 12:17:26.106037 Set Vref, RX VrefLevel [Byte0]: 47
5063 12:17:26.109089 [Byte1]: 46
5064 12:17:26.109176
5065 12:17:26.112655 Final RX Vref Byte 0 = 47 to rank0
5066 12:17:26.116010 Final RX Vref Byte 1 = 46 to rank0
5067 12:17:26.119281 Final RX Vref Byte 0 = 47 to rank1
5068 12:17:26.122449 Final RX Vref Byte 1 = 46 to rank1==
5069 12:17:26.125785 Dram Type= 6, Freq= 0, CH_0, rank 0
5070 12:17:26.129143 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5071 12:17:26.129233 ==
5072 12:17:26.132420 DQS Delay:
5073 12:17:26.132505 DQS0 = 0, DQS1 = 0
5074 12:17:26.135739 DQM Delay:
5075 12:17:26.135823 DQM0 = 97, DQM1 = 87
5076 12:17:26.135888 DQ Delay:
5077 12:17:26.139102 DQ0 =92, DQ1 =100, DQ2 =96, DQ3 =94
5078 12:17:26.142236 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5079 12:17:26.145630 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5080 12:17:26.152190 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =96
5081 12:17:26.152311
5082 12:17:26.152379
5083 12:17:26.158785 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5084 12:17:26.162110 CH0 RK0: MR19=505, MR18=1E1E
5085 12:17:26.168733 CH0_RK0: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5086 12:17:26.168837
5087 12:17:26.172271 ----->DramcWriteLeveling(PI) begin...
5088 12:17:26.172377 ==
5089 12:17:26.175316 Dram Type= 6, Freq= 0, CH_0, rank 1
5090 12:17:26.178701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5091 12:17:26.178791 ==
5092 12:17:26.181959 Write leveling (Byte 0): 27 => 27
5093 12:17:26.185289 Write leveling (Byte 1): 27 => 27
5094 12:17:26.188796 DramcWriteLeveling(PI) end<-----
5095 12:17:26.188884
5096 12:17:26.188952 ==
5097 12:17:26.192140 Dram Type= 6, Freq= 0, CH_0, rank 1
5098 12:17:26.195266 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5099 12:17:26.195352 ==
5100 12:17:26.198696 [Gating] SW mode calibration
5101 12:17:26.205247 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5102 12:17:26.212131 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5103 12:17:26.215108 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 12:17:26.221980 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 12:17:26.225192 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 12:17:26.228616 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 12:17:26.231848 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 12:17:26.238268 0 10 20 | B1->B0 | 2f2f 2d2d | 1 0 | (1 0) (0 0)
5109 12:17:26.241805 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 12:17:26.244969 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 12:17:26.251703 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 12:17:26.255074 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 12:17:26.258282 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 12:17:26.264725 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 12:17:26.268006 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 12:17:26.271571 0 11 20 | B1->B0 | 2424 3030 | 0 0 | (1 1) (0 0)
5117 12:17:26.277953 0 11 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5118 12:17:26.281278 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 12:17:26.284561 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 12:17:26.291266 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 12:17:26.294526 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 12:17:26.297938 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 12:17:26.304497 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 12:17:26.307617 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5125 12:17:26.311002 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:17:26.317755 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:17:26.320986 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:17:26.324215 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:17:26.330925 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:17:26.334156 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:17:26.337697 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:17:26.344134 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:17:26.347323 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:17:26.350859 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:17:26.357549 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:17:26.361082 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:17:26.364098 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:17:26.370573 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:17:26.374155 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 12:17:26.377254 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 12:17:26.383963 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5142 12:17:26.387162 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 12:17:26.390830 Total UI for P1: 0, mck2ui 16
5144 12:17:26.393913 best dqsien dly found for B0: ( 0, 14, 24)
5145 12:17:26.397259 Total UI for P1: 0, mck2ui 16
5146 12:17:26.400645 best dqsien dly found for B1: ( 0, 14, 24)
5147 12:17:26.404083 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
5148 12:17:26.407307 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
5149 12:17:26.407401
5150 12:17:26.410379 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 24)
5151 12:17:26.413872 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 24)
5152 12:17:26.417116 [Gating] SW calibration Done
5153 12:17:26.417202 ==
5154 12:17:26.420516 Dram Type= 6, Freq= 0, CH_0, rank 1
5155 12:17:26.423774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5156 12:17:26.427854 ==
5157 12:17:26.427944 RX Vref Scan: 0
5158 12:17:26.428011
5159 12:17:26.430703 RX Vref 0 -> 0, step: 1
5160 12:17:26.430785
5161 12:17:26.433886 RX Delay -80 -> 252, step: 8
5162 12:17:26.437095 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5163 12:17:26.440334 iDelay=200, Bit 1, Center 95 (-8 ~ 199) 208
5164 12:17:26.443900 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5165 12:17:26.447060 iDelay=200, Bit 3, Center 87 (-8 ~ 183) 192
5166 12:17:26.450448 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5167 12:17:26.456965 iDelay=200, Bit 5, Center 87 (-16 ~ 191) 208
5168 12:17:26.460137 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5169 12:17:26.463552 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5170 12:17:26.466813 iDelay=200, Bit 8, Center 71 (-24 ~ 167) 192
5171 12:17:26.470163 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5172 12:17:26.476889 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5173 12:17:26.480117 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5174 12:17:26.483603 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5175 12:17:26.486632 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5176 12:17:26.489905 iDelay=200, Bit 14, Center 91 (-8 ~ 191) 200
5177 12:17:26.496733 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5178 12:17:26.496834 ==
5179 12:17:26.499963 Dram Type= 6, Freq= 0, CH_0, rank 1
5180 12:17:26.503379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5181 12:17:26.503466 ==
5182 12:17:26.503548 DQS Delay:
5183 12:17:26.506546 DQS0 = 0, DQS1 = 0
5184 12:17:26.506629 DQM Delay:
5185 12:17:26.510034 DQM0 = 96, DQM1 = 85
5186 12:17:26.510117 DQ Delay:
5187 12:17:26.513229 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =87
5188 12:17:26.516665 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5189 12:17:26.519712 DQ8 =71, DQ9 =71, DQ10 =87, DQ11 =79
5190 12:17:26.523109 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =95
5191 12:17:26.523196
5192 12:17:26.523263
5193 12:17:26.523324 ==
5194 12:17:26.526575 Dram Type= 6, Freq= 0, CH_0, rank 1
5195 12:17:26.529852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5196 12:17:26.529939 ==
5197 12:17:26.533201
5198 12:17:26.533286
5199 12:17:26.533351 TX Vref Scan disable
5200 12:17:26.536716 == TX Byte 0 ==
5201 12:17:26.539871 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5202 12:17:26.543305 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5203 12:17:26.546654 == TX Byte 1 ==
5204 12:17:26.549625 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5205 12:17:26.553119 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5206 12:17:26.553208 ==
5207 12:17:26.556534 Dram Type= 6, Freq= 0, CH_0, rank 1
5208 12:17:26.563508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5209 12:17:26.563608 ==
5210 12:17:26.563676
5211 12:17:26.563737
5212 12:17:26.563796 TX Vref Scan disable
5213 12:17:26.567029 == TX Byte 0 ==
5214 12:17:26.570485 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5215 12:17:26.577194 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5216 12:17:26.577303 == TX Byte 1 ==
5217 12:17:26.580612 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5218 12:17:26.587076 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5219 12:17:26.587181
5220 12:17:26.587272 [DATLAT]
5221 12:17:26.587355 Freq=933, CH0 RK1
5222 12:17:26.587436
5223 12:17:26.590330 DATLAT Default: 0xb
5224 12:17:26.590416 0, 0xFFFF, sum = 0
5225 12:17:26.593667 1, 0xFFFF, sum = 0
5226 12:17:26.596827 2, 0xFFFF, sum = 0
5227 12:17:26.596952 3, 0xFFFF, sum = 0
5228 12:17:26.600352 4, 0xFFFF, sum = 0
5229 12:17:26.600441 5, 0xFFFF, sum = 0
5230 12:17:26.603693 6, 0xFFFF, sum = 0
5231 12:17:26.603781 7, 0xFFFF, sum = 0
5232 12:17:26.606904 8, 0xFFFF, sum = 0
5233 12:17:26.606991 9, 0xFFFF, sum = 0
5234 12:17:26.610494 10, 0x0, sum = 1
5235 12:17:26.610582 11, 0x0, sum = 2
5236 12:17:26.613509 12, 0x0, sum = 3
5237 12:17:26.613595 13, 0x0, sum = 4
5238 12:17:26.613683 best_step = 11
5239 12:17:26.613766
5240 12:17:26.616906 ==
5241 12:17:26.620300 Dram Type= 6, Freq= 0, CH_0, rank 1
5242 12:17:26.623840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5243 12:17:26.623928 ==
5244 12:17:26.624014 RX Vref Scan: 0
5245 12:17:26.624162
5246 12:17:26.626993 RX Vref 0 -> 0, step: 1
5247 12:17:26.627075
5248 12:17:26.630336 RX Delay -69 -> 252, step: 4
5249 12:17:26.633606 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5250 12:17:26.640402 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5251 12:17:26.643477 iDelay=199, Bit 2, Center 96 (3 ~ 190) 188
5252 12:17:26.646798 iDelay=199, Bit 3, Center 90 (-1 ~ 182) 184
5253 12:17:26.650238 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5254 12:17:26.653525 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5255 12:17:26.656699 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5256 12:17:26.663345 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5257 12:17:26.666919 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5258 12:17:26.669951 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5259 12:17:26.673298 iDelay=199, Bit 10, Center 86 (-9 ~ 182) 192
5260 12:17:26.676638 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5261 12:17:26.683325 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5262 12:17:26.686839 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5263 12:17:26.689690 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5264 12:17:26.693100 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5265 12:17:26.693187 ==
5266 12:17:26.696538 Dram Type= 6, Freq= 0, CH_0, rank 1
5267 12:17:26.699857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5268 12:17:26.703141 ==
5269 12:17:26.703248 DQS Delay:
5270 12:17:26.703339 DQS0 = 0, DQS1 = 0
5271 12:17:26.706573 DQM Delay:
5272 12:17:26.706796 DQM0 = 96, DQM1 = 86
5273 12:17:26.709601 DQ Delay:
5274 12:17:26.712992 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =90
5275 12:17:26.716429 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =106
5276 12:17:26.720019 DQ8 =74, DQ9 =72, DQ10 =86, DQ11 =78
5277 12:17:26.723223 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5278 12:17:26.723311
5279 12:17:26.723378
5280 12:17:26.729922 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5281 12:17:26.733091 CH0 RK1: MR19=505, MR18=2A2A
5282 12:17:26.739575 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5283 12:17:26.742785 [RxdqsGatingPostProcess] freq 933
5284 12:17:26.746183 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5285 12:17:26.749611 Pre-setting of DQS Precalculation
5286 12:17:26.756167 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5287 12:17:26.756280 ==
5288 12:17:26.759343 Dram Type= 6, Freq= 0, CH_1, rank 0
5289 12:17:26.762658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5290 12:17:26.762760 ==
5291 12:17:26.769197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5292 12:17:26.776339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5293 12:17:26.779252 [CA 0] Center 37 (7~68) winsize 62
5294 12:17:26.782637 [CA 1] Center 37 (6~68) winsize 63
5295 12:17:26.786061 [CA 2] Center 34 (4~65) winsize 62
5296 12:17:26.789400 [CA 3] Center 34 (3~65) winsize 63
5297 12:17:26.792611 [CA 4] Center 33 (2~64) winsize 63
5298 12:17:26.792700 [CA 5] Center 33 (2~64) winsize 63
5299 12:17:26.792766
5300 12:17:26.799079 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5301 12:17:26.799181
5302 12:17:26.802457 [CATrainingPosCal] consider 1 rank data
5303 12:17:26.805911 u2DelayCellTimex100 = 270/100 ps
5304 12:17:26.809224 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5305 12:17:26.812411 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5306 12:17:26.815953 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5307 12:17:26.819365 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5308 12:17:26.822610 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5309 12:17:26.825759 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5310 12:17:26.825853
5311 12:17:26.829148 CA PerBit enable=1, Macro0, CA PI delay=33
5312 12:17:26.829233
5313 12:17:26.832471 [CBTSetCACLKResult] CA Dly = 33
5314 12:17:26.835654 CS Dly: 5 (0~36)
5315 12:17:26.835741 ==
5316 12:17:26.839202 Dram Type= 6, Freq= 0, CH_1, rank 1
5317 12:17:26.842556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5318 12:17:26.842643 ==
5319 12:17:26.848985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5320 12:17:26.855440 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5321 12:17:26.858845 [CA 0] Center 37 (6~68) winsize 63
5322 12:17:26.862085 [CA 1] Center 37 (6~68) winsize 63
5323 12:17:26.865479 [CA 2] Center 34 (4~65) winsize 62
5324 12:17:26.868675 [CA 3] Center 34 (4~65) winsize 62
5325 12:17:26.872295 [CA 4] Center 33 (2~64) winsize 63
5326 12:17:26.875600 [CA 5] Center 33 (2~64) winsize 63
5327 12:17:26.875688
5328 12:17:26.878671 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5329 12:17:26.878767
5330 12:17:26.881916 [CATrainingPosCal] consider 2 rank data
5331 12:17:26.885289 u2DelayCellTimex100 = 270/100 ps
5332 12:17:26.888540 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5333 12:17:26.891951 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5334 12:17:26.895217 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5335 12:17:26.898605 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5336 12:17:26.901955 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5337 12:17:26.905832 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5338 12:17:26.905924
5339 12:17:26.911846 CA PerBit enable=1, Macro0, CA PI delay=33
5340 12:17:26.911941
5341 12:17:26.912008 [CBTSetCACLKResult] CA Dly = 33
5342 12:17:26.915269 CS Dly: 5 (0~37)
5343 12:17:26.915353
5344 12:17:26.918405 ----->DramcWriteLeveling(PI) begin...
5345 12:17:26.918492 ==
5346 12:17:26.921678 Dram Type= 6, Freq= 0, CH_1, rank 0
5347 12:17:26.925051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5348 12:17:26.925137 ==
5349 12:17:26.928654 Write leveling (Byte 0): 23 => 23
5350 12:17:26.931640 Write leveling (Byte 1): 23 => 23
5351 12:17:26.935155 DramcWriteLeveling(PI) end<-----
5352 12:17:26.935242
5353 12:17:26.935308 ==
5354 12:17:26.938527 Dram Type= 6, Freq= 0, CH_1, rank 0
5355 12:17:26.941643 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5356 12:17:26.945038 ==
5357 12:17:26.945125 [Gating] SW mode calibration
5358 12:17:26.954998 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5359 12:17:26.958217 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5360 12:17:26.961641 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 12:17:26.968233 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 12:17:26.971739 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 12:17:26.974949 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 12:17:26.981341 0 10 16 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5365 12:17:26.984577 0 10 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
5366 12:17:26.988243 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5367 12:17:26.994991 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 12:17:26.998214 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 12:17:27.001274 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 12:17:27.008346 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 12:17:27.011353 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 12:17:27.014543 0 11 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5373 12:17:27.021157 0 11 20 | B1->B0 | 2828 4343 | 0 0 | (0 0) (0 0)
5374 12:17:27.024671 0 11 24 | B1->B0 | 3f3e 4646 | 1 0 | (0 0) (0 0)
5375 12:17:27.027821 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 12:17:27.034315 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 12:17:27.037663 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 12:17:27.040911 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 12:17:27.047830 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 12:17:27.051017 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5381 12:17:27.054442 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5382 12:17:27.061182 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 12:17:27.064151 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:17:27.067609 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:17:27.074186 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:17:27.077696 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:17:27.081003 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:17:27.087485 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:17:27.090782 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:17:27.094132 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:17:27.097517 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:17:27.103972 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:17:27.107370 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:17:27.113986 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:17:27.117073 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:17:27.120600 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5397 12:17:27.123806 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5398 12:17:27.127153 Total UI for P1: 0, mck2ui 16
5399 12:17:27.130430 best dqsien dly found for B0: ( 0, 14, 16)
5400 12:17:27.137286 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 12:17:27.140672 Total UI for P1: 0, mck2ui 16
5402 12:17:27.143644 best dqsien dly found for B1: ( 0, 14, 20)
5403 12:17:27.147197 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5404 12:17:27.150424 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5405 12:17:27.150513
5406 12:17:27.153842 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5407 12:17:27.157123 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5408 12:17:27.160144 [Gating] SW calibration Done
5409 12:17:27.160285 ==
5410 12:17:27.163538 Dram Type= 6, Freq= 0, CH_1, rank 0
5411 12:17:27.167100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5412 12:17:27.167188 ==
5413 12:17:27.170297 RX Vref Scan: 0
5414 12:17:27.170381
5415 12:17:27.173455 RX Vref 0 -> 0, step: 1
5416 12:17:27.173577
5417 12:17:27.173688 RX Delay -80 -> 252, step: 8
5418 12:17:27.180133 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5419 12:17:27.183842 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5420 12:17:27.186822 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5421 12:17:27.190016 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5422 12:17:27.193371 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5423 12:17:27.200157 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5424 12:17:27.203821 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5425 12:17:27.206602 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5426 12:17:27.210135 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5427 12:17:27.213366 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5428 12:17:27.216614 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5429 12:17:27.223469 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5430 12:17:27.226595 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5431 12:17:27.229808 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5432 12:17:27.233690 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5433 12:17:27.236576 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5434 12:17:27.236669 ==
5435 12:17:27.240047 Dram Type= 6, Freq= 0, CH_1, rank 0
5436 12:17:27.246498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5437 12:17:27.246603 ==
5438 12:17:27.246673 DQS Delay:
5439 12:17:27.249937 DQS0 = 0, DQS1 = 0
5440 12:17:27.250023 DQM Delay:
5441 12:17:27.250091 DQM0 = 94, DQM1 = 88
5442 12:17:27.253279 DQ Delay:
5443 12:17:27.256492 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5444 12:17:27.259849 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5445 12:17:27.263069 DQ8 =71, DQ9 =79, DQ10 =91, DQ11 =79
5446 12:17:27.266421 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5447 12:17:27.266511
5448 12:17:27.266578
5449 12:17:27.266639 ==
5450 12:17:27.269847 Dram Type= 6, Freq= 0, CH_1, rank 0
5451 12:17:27.273084 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5452 12:17:27.273172 ==
5453 12:17:27.273240
5454 12:17:27.273303
5455 12:17:27.276405 TX Vref Scan disable
5456 12:17:27.279946 == TX Byte 0 ==
5457 12:17:27.282902 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5458 12:17:27.286505 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5459 12:17:27.289477 == TX Byte 1 ==
5460 12:17:27.292869 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5461 12:17:27.296103 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5462 12:17:27.296234 ==
5463 12:17:27.299872 Dram Type= 6, Freq= 0, CH_1, rank 0
5464 12:17:27.302670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5465 12:17:27.305979 ==
5466 12:17:27.306066
5467 12:17:27.306133
5468 12:17:27.306194 TX Vref Scan disable
5469 12:17:27.309657 == TX Byte 0 ==
5470 12:17:27.313200 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5471 12:17:27.319609 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5472 12:17:27.319719 == TX Byte 1 ==
5473 12:17:27.322970 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5474 12:17:27.329776 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5475 12:17:27.329879
5476 12:17:27.329948 [DATLAT]
5477 12:17:27.330010 Freq=933, CH1 RK0
5478 12:17:27.330072
5479 12:17:27.332767 DATLAT Default: 0xd
5480 12:17:27.332852 0, 0xFFFF, sum = 0
5481 12:17:27.336087 1, 0xFFFF, sum = 0
5482 12:17:27.339374 2, 0xFFFF, sum = 0
5483 12:17:27.339464 3, 0xFFFF, sum = 0
5484 12:17:27.342866 4, 0xFFFF, sum = 0
5485 12:17:27.342955 5, 0xFFFF, sum = 0
5486 12:17:27.346210 6, 0xFFFF, sum = 0
5487 12:17:27.346298 7, 0xFFFF, sum = 0
5488 12:17:27.349488 8, 0xFFFF, sum = 0
5489 12:17:27.349575 9, 0xFFFF, sum = 0
5490 12:17:27.352917 10, 0x0, sum = 1
5491 12:17:27.353006 11, 0x0, sum = 2
5492 12:17:27.356095 12, 0x0, sum = 3
5493 12:17:27.356187 13, 0x0, sum = 4
5494 12:17:27.356255 best_step = 11
5495 12:17:27.356318
5496 12:17:27.359442 ==
5497 12:17:27.359526 Dram Type= 6, Freq= 0, CH_1, rank 0
5498 12:17:27.366063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5499 12:17:27.366156 ==
5500 12:17:27.366223 RX Vref Scan: 1
5501 12:17:27.366285
5502 12:17:27.369409 RX Vref 0 -> 0, step: 1
5503 12:17:27.369494
5504 12:17:27.372774 RX Delay -69 -> 252, step: 4
5505 12:17:27.372860
5506 12:17:27.376099 Set Vref, RX VrefLevel [Byte0]: 53
5507 12:17:27.379377 [Byte1]: 48
5508 12:17:27.379467
5509 12:17:27.382503 Final RX Vref Byte 0 = 53 to rank0
5510 12:17:27.386077 Final RX Vref Byte 1 = 48 to rank0
5511 12:17:27.389232 Final RX Vref Byte 0 = 53 to rank1
5512 12:17:27.392548 Final RX Vref Byte 1 = 48 to rank1==
5513 12:17:27.396101 Dram Type= 6, Freq= 0, CH_1, rank 0
5514 12:17:27.399321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5515 12:17:27.402755 ==
5516 12:17:27.402849 DQS Delay:
5517 12:17:27.402918 DQS0 = 0, DQS1 = 0
5518 12:17:27.405962 DQM Delay:
5519 12:17:27.406046 DQM0 = 94, DQM1 = 88
5520 12:17:27.409262 DQ Delay:
5521 12:17:27.409348 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5522 12:17:27.412496 DQ4 =94, DQ5 =104, DQ6 =100, DQ7 =92
5523 12:17:27.415724 DQ8 =70, DQ9 =76, DQ10 =90, DQ11 =80
5524 12:17:27.419119 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =98
5525 12:17:27.422330
5526 12:17:27.422418
5527 12:17:27.428974 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3b, (MSB)MR19= 0x505, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
5528 12:17:27.432496 CH1 RK0: MR19=505, MR18=3B3B
5529 12:17:27.439021 CH1_RK0: MR19=0x505, MR18=0x3B3B, DQSOSC=403, MR23=63, INC=66, DEC=44
5530 12:17:27.439144
5531 12:17:27.442298 ----->DramcWriteLeveling(PI) begin...
5532 12:17:27.442407 ==
5533 12:17:27.445534 Dram Type= 6, Freq= 0, CH_1, rank 1
5534 12:17:27.449007 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5535 12:17:27.449096 ==
5536 12:17:27.452276 Write leveling (Byte 0): 24 => 24
5537 12:17:27.455579 Write leveling (Byte 1): 24 => 24
5538 12:17:27.458690 DramcWriteLeveling(PI) end<-----
5539 12:17:27.458780
5540 12:17:27.458847 ==
5541 12:17:27.462285 Dram Type= 6, Freq= 0, CH_1, rank 1
5542 12:17:27.465559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5543 12:17:27.465648 ==
5544 12:17:27.468948 [Gating] SW mode calibration
5545 12:17:27.475325 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5546 12:17:27.482073 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5547 12:17:27.485258 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 12:17:27.491703 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 12:17:27.495257 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 12:17:27.498515 0 10 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5551 12:17:27.504870 0 10 16 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 1)
5552 12:17:27.508553 0 10 20 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5553 12:17:27.511736 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 12:17:27.518082 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 12:17:27.521510 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 12:17:27.524943 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 12:17:27.528159 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 12:17:27.535195 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 12:17:27.538071 0 11 16 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)
5560 12:17:27.541338 0 11 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5561 12:17:27.547995 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 12:17:27.551313 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 12:17:27.554627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 12:17:27.561419 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 12:17:27.564538 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 12:17:27.568090 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 12:17:27.574655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5568 12:17:27.578307 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5569 12:17:27.581531 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 12:17:27.588067 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 12:17:27.591335 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 12:17:27.594794 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 12:17:27.601211 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 12:17:27.604465 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 12:17:27.607884 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 12:17:27.614629 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 12:17:27.617840 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 12:17:27.621013 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:17:27.627839 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:17:27.630981 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:17:27.634352 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:17:27.640784 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:17:27.644308 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5584 12:17:27.647660 Total UI for P1: 0, mck2ui 16
5585 12:17:27.650815 best dqsien dly found for B0: ( 0, 14, 14)
5586 12:17:27.654210 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5587 12:17:27.660844 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 12:17:27.660950 Total UI for P1: 0, mck2ui 16
5589 12:17:27.664149 best dqsien dly found for B1: ( 0, 14, 20)
5590 12:17:27.670978 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5591 12:17:27.674333 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5592 12:17:27.674433
5593 12:17:27.677457 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5594 12:17:27.680642 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5595 12:17:27.683937 [Gating] SW calibration Done
5596 12:17:27.684029 ==
5597 12:17:27.687221 Dram Type= 6, Freq= 0, CH_1, rank 1
5598 12:17:27.691292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5599 12:17:27.691381 ==
5600 12:17:27.693712 RX Vref Scan: 0
5601 12:17:27.693797
5602 12:17:27.693864 RX Vref 0 -> 0, step: 1
5603 12:17:27.693926
5604 12:17:27.697100 RX Delay -80 -> 252, step: 8
5605 12:17:27.700391 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5606 12:17:27.707017 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5607 12:17:27.710862 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5608 12:17:27.713944 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5609 12:17:27.717159 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5610 12:17:27.720534 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5611 12:17:27.723826 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5612 12:17:27.730529 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5613 12:17:27.733611 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5614 12:17:27.736978 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5615 12:17:27.740284 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5616 12:17:27.743756 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5617 12:17:27.750191 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5618 12:17:27.753594 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5619 12:17:27.757069 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5620 12:17:27.760614 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5621 12:17:27.760715 ==
5622 12:17:27.763545 Dram Type= 6, Freq= 0, CH_1, rank 1
5623 12:17:27.766854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5624 12:17:27.766985 ==
5625 12:17:27.770081 DQS Delay:
5626 12:17:27.770212 DQS0 = 0, DQS1 = 0
5627 12:17:27.773494 DQM Delay:
5628 12:17:27.773587 DQM0 = 94, DQM1 = 85
5629 12:17:27.777050 DQ Delay:
5630 12:17:27.777144 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =91
5631 12:17:27.780152 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =91
5632 12:17:27.783757 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =75
5633 12:17:27.786845 DQ12 =91, DQ13 =95, DQ14 =91, DQ15 =95
5634 12:17:27.786935
5635 12:17:27.790424
5636 12:17:27.790510 ==
5637 12:17:27.793367 Dram Type= 6, Freq= 0, CH_1, rank 1
5638 12:17:27.796687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5639 12:17:27.796777 ==
5640 12:17:27.796844
5641 12:17:27.796906
5642 12:17:27.800092 TX Vref Scan disable
5643 12:17:27.800206 == TX Byte 0 ==
5644 12:17:27.806429 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5645 12:17:27.810281 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5646 12:17:27.810376 == TX Byte 1 ==
5647 12:17:27.816578 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5648 12:17:27.819898 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5649 12:17:27.820018 ==
5650 12:17:27.822995 Dram Type= 6, Freq= 0, CH_1, rank 1
5651 12:17:27.826437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5652 12:17:27.826524 ==
5653 12:17:27.826592
5654 12:17:27.826652
5655 12:17:27.829644 TX Vref Scan disable
5656 12:17:27.833075 == TX Byte 0 ==
5657 12:17:27.836374 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5658 12:17:27.839498 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5659 12:17:27.842867 == TX Byte 1 ==
5660 12:17:27.846362 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5661 12:17:27.849674 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5662 12:17:27.849762
5663 12:17:27.852667 [DATLAT]
5664 12:17:27.852751 Freq=933, CH1 RK1
5665 12:17:27.852818
5666 12:17:27.856310 DATLAT Default: 0xb
5667 12:17:27.856394 0, 0xFFFF, sum = 0
5668 12:17:27.859637 1, 0xFFFF, sum = 0
5669 12:17:27.859723 2, 0xFFFF, sum = 0
5670 12:17:27.862668 3, 0xFFFF, sum = 0
5671 12:17:27.862754 4, 0xFFFF, sum = 0
5672 12:17:27.866130 5, 0xFFFF, sum = 0
5673 12:17:27.866217 6, 0xFFFF, sum = 0
5674 12:17:27.869455 7, 0xFFFF, sum = 0
5675 12:17:27.872828 8, 0xFFFF, sum = 0
5676 12:17:27.872915 9, 0xFFFF, sum = 0
5677 12:17:27.872983 10, 0x0, sum = 1
5678 12:17:27.876052 11, 0x0, sum = 2
5679 12:17:27.876138 12, 0x0, sum = 3
5680 12:17:27.879345 13, 0x0, sum = 4
5681 12:17:27.879430 best_step = 11
5682 12:17:27.879496
5683 12:17:27.879558 ==
5684 12:17:27.882724 Dram Type= 6, Freq= 0, CH_1, rank 1
5685 12:17:27.889074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5686 12:17:27.889170 ==
5687 12:17:27.889238 RX Vref Scan: 0
5688 12:17:27.889300
5689 12:17:27.892488 RX Vref 0 -> 0, step: 1
5690 12:17:27.892576
5691 12:17:27.895797 RX Delay -69 -> 252, step: 4
5692 12:17:27.899108 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5693 12:17:27.905879 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5694 12:17:27.909230 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5695 12:17:27.912459 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5696 12:17:27.915630 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5697 12:17:27.919122 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5698 12:17:27.922265 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5699 12:17:27.929057 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5700 12:17:27.932140 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5701 12:17:27.935534 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5702 12:17:27.938993 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5703 12:17:27.942238 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5704 12:17:27.948949 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5705 12:17:27.952054 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5706 12:17:27.955417 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5707 12:17:27.958788 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5708 12:17:27.958875 ==
5709 12:17:27.961986 Dram Type= 6, Freq= 0, CH_1, rank 1
5710 12:17:27.965522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5711 12:17:27.965609 ==
5712 12:17:27.968651 DQS Delay:
5713 12:17:27.968735 DQS0 = 0, DQS1 = 0
5714 12:17:27.972219 DQM Delay:
5715 12:17:27.972305 DQM0 = 96, DQM1 = 87
5716 12:17:27.972372 DQ Delay:
5717 12:17:27.975420 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =94
5718 12:17:27.978745 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5719 12:17:27.981937 DQ8 =74, DQ9 =74, DQ10 =86, DQ11 =80
5720 12:17:27.985334 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5721 12:17:27.985424
5722 12:17:27.988608
5723 12:17:27.995247 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5724 12:17:27.998565 CH1 RK1: MR19=505, MR18=2A2A
5725 12:17:28.005440 CH1_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5726 12:17:28.005562 [RxdqsGatingPostProcess] freq 933
5727 12:17:28.012071 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5728 12:17:28.015231 Pre-setting of DQS Precalculation
5729 12:17:28.021855 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5730 12:17:28.028315 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5731 12:17:28.035179 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5732 12:17:28.035289
5733 12:17:28.035357
5734 12:17:28.038354 [Calibration Summary] 1866 Mbps
5735 12:17:28.038441 CH 0, Rank 0
5736 12:17:28.041560 SW Impedance : PASS
5737 12:17:28.045123 DUTY Scan : NO K
5738 12:17:28.045210 ZQ Calibration : PASS
5739 12:17:28.048515 Jitter Meter : NO K
5740 12:17:28.048601 CBT Training : PASS
5741 12:17:28.051504 Write leveling : PASS
5742 12:17:28.054820 RX DQS gating : PASS
5743 12:17:28.054908 RX DQ/DQS(RDDQC) : PASS
5744 12:17:28.058382 TX DQ/DQS : PASS
5745 12:17:28.061754 RX DATLAT : PASS
5746 12:17:28.061842 RX DQ/DQS(Engine): PASS
5747 12:17:28.065107 TX OE : NO K
5748 12:17:28.065192 All Pass.
5749 12:17:28.065260
5750 12:17:28.068308 CH 0, Rank 1
5751 12:17:28.068393 SW Impedance : PASS
5752 12:17:28.071751 DUTY Scan : NO K
5753 12:17:28.075007 ZQ Calibration : PASS
5754 12:17:28.075094 Jitter Meter : NO K
5755 12:17:28.078276 CBT Training : PASS
5756 12:17:28.081596 Write leveling : PASS
5757 12:17:28.081685 RX DQS gating : PASS
5758 12:17:28.084881 RX DQ/DQS(RDDQC) : PASS
5759 12:17:28.088154 TX DQ/DQS : PASS
5760 12:17:28.088279 RX DATLAT : PASS
5761 12:17:28.091461 RX DQ/DQS(Engine): PASS
5762 12:17:28.091547 TX OE : NO K
5763 12:17:28.094804 All Pass.
5764 12:17:28.094890
5765 12:17:28.094957 CH 1, Rank 0
5766 12:17:28.097975 SW Impedance : PASS
5767 12:17:28.098061 DUTY Scan : NO K
5768 12:17:28.101541 ZQ Calibration : PASS
5769 12:17:28.104729 Jitter Meter : NO K
5770 12:17:28.104818 CBT Training : PASS
5771 12:17:28.108112 Write leveling : PASS
5772 12:17:28.111440 RX DQS gating : PASS
5773 12:17:28.111528 RX DQ/DQS(RDDQC) : PASS
5774 12:17:28.114529 TX DQ/DQS : PASS
5775 12:17:28.118102 RX DATLAT : PASS
5776 12:17:28.118188 RX DQ/DQS(Engine): PASS
5777 12:17:28.121079 TX OE : NO K
5778 12:17:28.121163 All Pass.
5779 12:17:28.121231
5780 12:17:28.124552 CH 1, Rank 1
5781 12:17:28.124638 SW Impedance : PASS
5782 12:17:28.128001 DUTY Scan : NO K
5783 12:17:28.131350 ZQ Calibration : PASS
5784 12:17:28.131436 Jitter Meter : NO K
5785 12:17:28.134440 CBT Training : PASS
5786 12:17:28.138160 Write leveling : PASS
5787 12:17:28.138252 RX DQS gating : PASS
5788 12:17:28.141381 RX DQ/DQS(RDDQC) : PASS
5789 12:17:28.144652 TX DQ/DQS : PASS
5790 12:17:28.144739 RX DATLAT : PASS
5791 12:17:28.147877 RX DQ/DQS(Engine): PASS
5792 12:17:28.147961 TX OE : NO K
5793 12:17:28.151295 All Pass.
5794 12:17:28.151380
5795 12:17:28.151447 DramC Write-DBI off
5796 12:17:28.155185 PER_BANK_REFRESH: Hybrid Mode
5797 12:17:28.157776 TX_TRACKING: ON
5798 12:17:28.164562 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5799 12:17:28.167941 [FAST_K] Save calibration result to emmc
5800 12:17:28.174471 dramc_set_vcore_voltage set vcore to 650000
5801 12:17:28.174583 Read voltage for 400, 6
5802 12:17:28.174652 Vio18 = 0
5803 12:17:28.177606 Vcore = 650000
5804 12:17:28.177692 Vdram = 0
5805 12:17:28.177760 Vddq = 0
5806 12:17:28.181079 Vmddr = 0
5807 12:17:28.184107 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5808 12:17:28.191233 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5809 12:17:28.194242 MEM_TYPE=3, freq_sel=20
5810 12:17:28.194336 sv_algorithm_assistance_LP4_800
5811 12:17:28.201032 ============ PULL DRAM RESETB DOWN ============
5812 12:17:28.204095 ========== PULL DRAM RESETB DOWN end =========
5813 12:17:28.207445 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5814 12:17:28.210672 ===================================
5815 12:17:28.214368 LPDDR4 DRAM CONFIGURATION
5816 12:17:28.217713 ===================================
5817 12:17:28.220767 EX_ROW_EN[0] = 0x0
5818 12:17:28.220854 EX_ROW_EN[1] = 0x0
5819 12:17:28.223827 LP4Y_EN = 0x0
5820 12:17:28.223913 WORK_FSP = 0x0
5821 12:17:28.227357 WL = 0x2
5822 12:17:28.227442 RL = 0x2
5823 12:17:28.230708 BL = 0x2
5824 12:17:28.230793 RPST = 0x0
5825 12:17:28.233902 RD_PRE = 0x0
5826 12:17:28.233986 WR_PRE = 0x1
5827 12:17:28.237280 WR_PST = 0x0
5828 12:17:28.237373 DBI_WR = 0x0
5829 12:17:28.240608 DBI_RD = 0x0
5830 12:17:28.240693 OTF = 0x1
5831 12:17:28.243770 ===================================
5832 12:17:28.247451 ===================================
5833 12:17:28.250585 ANA top config
5834 12:17:28.253693 ===================================
5835 12:17:28.257074 DLL_ASYNC_EN = 0
5836 12:17:28.257163 ALL_SLAVE_EN = 1
5837 12:17:28.260394 NEW_RANK_MODE = 1
5838 12:17:28.263665 DLL_IDLE_MODE = 1
5839 12:17:28.267221 LP45_APHY_COMB_EN = 1
5840 12:17:28.270459 TX_ODT_DIS = 1
5841 12:17:28.270551 NEW_8X_MODE = 1
5842 12:17:28.273832 ===================================
5843 12:17:28.277555 ===================================
5844 12:17:28.280330 data_rate = 800
5845 12:17:28.283579 CKR = 1
5846 12:17:28.286954 DQ_P2S_RATIO = 4
5847 12:17:28.290285 ===================================
5848 12:17:28.293806 CA_P2S_RATIO = 4
5849 12:17:28.296838 DQ_CA_OPEN = 0
5850 12:17:28.296926 DQ_SEMI_OPEN = 1
5851 12:17:28.300410 CA_SEMI_OPEN = 1
5852 12:17:28.303559 CA_FULL_RATE = 0
5853 12:17:28.306775 DQ_CKDIV4_EN = 0
5854 12:17:28.310156 CA_CKDIV4_EN = 1
5855 12:17:28.310245 CA_PREDIV_EN = 0
5856 12:17:28.313538 PH8_DLY = 0
5857 12:17:28.316681 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5858 12:17:28.319960 DQ_AAMCK_DIV = 0
5859 12:17:28.323394 CA_AAMCK_DIV = 0
5860 12:17:28.326793 CA_ADMCK_DIV = 4
5861 12:17:28.326880 DQ_TRACK_CA_EN = 0
5862 12:17:28.330126 CA_PICK = 800
5863 12:17:28.333407 CA_MCKIO = 400
5864 12:17:28.336743 MCKIO_SEMI = 400
5865 12:17:28.340184 PLL_FREQ = 3016
5866 12:17:28.343317 DQ_UI_PI_RATIO = 32
5867 12:17:28.346672 CA_UI_PI_RATIO = 32
5868 12:17:28.349758 ===================================
5869 12:17:28.353305 ===================================
5870 12:17:28.356356 memory_type:LPDDR4
5871 12:17:28.356445 GP_NUM : 10
5872 12:17:28.359897 SRAM_EN : 1
5873 12:17:28.359984 MD32_EN : 0
5874 12:17:28.363285 ===================================
5875 12:17:28.366307 [ANA_INIT] >>>>>>>>>>>>>>
5876 12:17:28.369698 <<<<<< [CONFIGURE PHASE]: ANA_TX
5877 12:17:28.372942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5878 12:17:28.376320 ===================================
5879 12:17:28.379487 data_rate = 800,PCW = 0X7400
5880 12:17:28.382937 ===================================
5881 12:17:28.386268 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5882 12:17:28.389734 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5883 12:17:28.402969 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5884 12:17:28.406146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5885 12:17:28.409559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5886 12:17:28.413228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5887 12:17:28.416320 [ANA_INIT] flow start
5888 12:17:28.419363 [ANA_INIT] PLL >>>>>>>>
5889 12:17:28.419451 [ANA_INIT] PLL <<<<<<<<
5890 12:17:28.422653 [ANA_INIT] MIDPI >>>>>>>>
5891 12:17:28.425973 [ANA_INIT] MIDPI <<<<<<<<
5892 12:17:28.426060 [ANA_INIT] DLL >>>>>>>>
5893 12:17:28.429414 [ANA_INIT] flow end
5894 12:17:28.432669 ============ LP4 DIFF to SE enter ============
5895 12:17:28.439346 ============ LP4 DIFF to SE exit ============
5896 12:17:28.439453 [ANA_INIT] <<<<<<<<<<<<<
5897 12:17:28.442529 [Flow] Enable top DCM control >>>>>
5898 12:17:28.446124 [Flow] Enable top DCM control <<<<<
5899 12:17:28.449357 Enable DLL master slave shuffle
5900 12:17:28.455918 ==============================================================
5901 12:17:28.456018 Gating Mode config
5902 12:17:28.462549 ==============================================================
5903 12:17:28.465979 Config description:
5904 12:17:28.472652 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5905 12:17:28.479783 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5906 12:17:28.486081 SELPH_MODE 0: By rank 1: By Phase
5907 12:17:28.489508 ==============================================================
5908 12:17:28.492764 GAT_TRACK_EN = 0
5909 12:17:28.495945 RX_GATING_MODE = 2
5910 12:17:28.499228 RX_GATING_TRACK_MODE = 2
5911 12:17:28.502723 SELPH_MODE = 1
5912 12:17:28.506478 PICG_EARLY_EN = 1
5913 12:17:28.509283 VALID_LAT_VALUE = 1
5914 12:17:28.515865 ==============================================================
5915 12:17:28.519146 Enter into Gating configuration >>>>
5916 12:17:28.522642 Exit from Gating configuration <<<<
5917 12:17:28.526117 Enter into DVFS_PRE_config >>>>>
5918 12:17:28.535600 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5919 12:17:28.539019 Exit from DVFS_PRE_config <<<<<
5920 12:17:28.542509 Enter into PICG configuration >>>>
5921 12:17:28.545423 Exit from PICG configuration <<<<
5922 12:17:28.548724 [RX_INPUT] configuration >>>>>
5923 12:17:28.548813 [RX_INPUT] configuration <<<<<
5924 12:17:28.555541 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5925 12:17:28.562130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5926 12:17:28.565530 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5927 12:17:28.571987 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5928 12:17:28.578564 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5929 12:17:28.585300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5930 12:17:28.588718 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5931 12:17:28.592048 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5932 12:17:28.598607 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5933 12:17:28.601929 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5934 12:17:28.605165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5935 12:17:28.611852 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5936 12:17:28.615203 ===================================
5937 12:17:28.615303 LPDDR4 DRAM CONFIGURATION
5938 12:17:28.618381 ===================================
5939 12:17:28.621663 EX_ROW_EN[0] = 0x0
5940 12:17:28.624981 EX_ROW_EN[1] = 0x0
5941 12:17:28.625072 LP4Y_EN = 0x0
5942 12:17:28.628307 WORK_FSP = 0x0
5943 12:17:28.628393 WL = 0x2
5944 12:17:28.631447 RL = 0x2
5945 12:17:28.631531 BL = 0x2
5946 12:17:28.634782 RPST = 0x0
5947 12:17:28.634866 RD_PRE = 0x0
5948 12:17:28.638077 WR_PRE = 0x1
5949 12:17:28.638162 WR_PST = 0x0
5950 12:17:28.641244 DBI_WR = 0x0
5951 12:17:28.641329 DBI_RD = 0x0
5952 12:17:28.644644 OTF = 0x1
5953 12:17:28.648228 ===================================
5954 12:17:28.651562 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5955 12:17:28.654440 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5956 12:17:28.661006 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5957 12:17:28.664607 ===================================
5958 12:17:28.664698 LPDDR4 DRAM CONFIGURATION
5959 12:17:28.667990 ===================================
5960 12:17:28.671096 EX_ROW_EN[0] = 0x10
5961 12:17:28.674344 EX_ROW_EN[1] = 0x0
5962 12:17:28.674434 LP4Y_EN = 0x0
5963 12:17:28.677776 WORK_FSP = 0x0
5964 12:17:28.677862 WL = 0x2
5965 12:17:28.680949 RL = 0x2
5966 12:17:28.681033 BL = 0x2
5967 12:17:28.684346 RPST = 0x0
5968 12:17:28.684431 RD_PRE = 0x0
5969 12:17:28.687932 WR_PRE = 0x1
5970 12:17:28.688015 WR_PST = 0x0
5971 12:17:28.690807 DBI_WR = 0x0
5972 12:17:28.690891 DBI_RD = 0x0
5973 12:17:28.694287 OTF = 0x1
5974 12:17:28.697478 ===================================
5975 12:17:28.704496 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5976 12:17:28.707208 nWR fixed to 30
5977 12:17:28.710558 [ModeRegInit_LP4] CH0 RK0
5978 12:17:28.710644 [ModeRegInit_LP4] CH0 RK1
5979 12:17:28.713865 [ModeRegInit_LP4] CH1 RK0
5980 12:17:28.717203 [ModeRegInit_LP4] CH1 RK1
5981 12:17:28.717290 match AC timing 18
5982 12:17:28.723768 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5983 12:17:28.727511 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5984 12:17:28.730813 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5985 12:17:28.737196 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5986 12:17:28.740703 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5987 12:17:28.740801 ==
5988 12:17:28.743764 Dram Type= 6, Freq= 0, CH_0, rank 0
5989 12:17:28.747189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5990 12:17:28.747275 ==
5991 12:17:28.753750 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5992 12:17:28.760376 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5993 12:17:28.763796 [CA 0] Center 36 (8~64) winsize 57
5994 12:17:28.763888 [CA 1] Center 36 (8~64) winsize 57
5995 12:17:28.767106 [CA 2] Center 36 (8~64) winsize 57
5996 12:17:28.770508 [CA 3] Center 36 (8~64) winsize 57
5997 12:17:28.773650 [CA 4] Center 36 (8~64) winsize 57
5998 12:17:28.777334 [CA 5] Center 36 (8~64) winsize 57
5999 12:17:28.777422
6000 12:17:28.780444 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6001 12:17:28.780528
6002 12:17:28.787152 [CATrainingPosCal] consider 1 rank data
6003 12:17:28.787254 u2DelayCellTimex100 = 270/100 ps
6004 12:17:28.793614 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 12:17:28.797021 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 12:17:28.800235 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 12:17:28.803547 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 12:17:28.806858 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 12:17:28.810129 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 12:17:28.810217
6011 12:17:28.813354 CA PerBit enable=1, Macro0, CA PI delay=36
6012 12:17:28.813438
6013 12:17:28.816799 [CBTSetCACLKResult] CA Dly = 36
6014 12:17:28.819975 CS Dly: 1 (0~32)
6015 12:17:28.820062 ==
6016 12:17:28.823217 Dram Type= 6, Freq= 0, CH_0, rank 1
6017 12:17:28.826515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6018 12:17:28.826601 ==
6019 12:17:28.833617 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6020 12:17:28.836744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6021 12:17:28.840132 [CA 0] Center 36 (8~64) winsize 57
6022 12:17:28.843740 [CA 1] Center 36 (8~64) winsize 57
6023 12:17:28.846604 [CA 2] Center 36 (8~64) winsize 57
6024 12:17:28.849963 [CA 3] Center 36 (8~64) winsize 57
6025 12:17:28.853485 [CA 4] Center 36 (8~64) winsize 57
6026 12:17:28.856863 [CA 5] Center 36 (8~64) winsize 57
6027 12:17:28.856956
6028 12:17:28.859928 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6029 12:17:28.860015
6030 12:17:28.863271 [CATrainingPosCal] consider 2 rank data
6031 12:17:28.866631 u2DelayCellTimex100 = 270/100 ps
6032 12:17:28.869939 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 12:17:28.873459 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 12:17:28.876801 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 12:17:28.883190 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 12:17:28.886731 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 12:17:28.889763 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 12:17:28.889847
6039 12:17:28.893176 CA PerBit enable=1, Macro0, CA PI delay=36
6040 12:17:28.893259
6041 12:17:28.896378 [CBTSetCACLKResult] CA Dly = 36
6042 12:17:28.896462 CS Dly: 1 (0~32)
6043 12:17:28.896529
6044 12:17:28.899727 ----->DramcWriteLeveling(PI) begin...
6045 12:17:28.899811 ==
6046 12:17:28.903113 Dram Type= 6, Freq= 0, CH_0, rank 0
6047 12:17:28.909753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6048 12:17:28.909841 ==
6049 12:17:28.912892 Write leveling (Byte 0): 32 => 0
6050 12:17:28.916136 Write leveling (Byte 1): 32 => 0
6051 12:17:28.916259 DramcWriteLeveling(PI) end<-----
6052 12:17:28.916326
6053 12:17:28.919411 ==
6054 12:17:28.922805 Dram Type= 6, Freq= 0, CH_0, rank 0
6055 12:17:28.926092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6056 12:17:28.926176 ==
6057 12:17:28.929401 [Gating] SW mode calibration
6058 12:17:28.936197 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6059 12:17:28.939484 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6060 12:17:28.946626 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6061 12:17:28.949461 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6062 12:17:28.952798 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6063 12:17:28.959602 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6064 12:17:28.962984 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6065 12:17:28.966059 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6066 12:17:28.973094 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6067 12:17:28.976061 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6068 12:17:28.979407 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6069 12:17:28.982882 Total UI for P1: 0, mck2ui 16
6070 12:17:28.985979 best dqsien dly found for B0: ( 0, 10, 16)
6071 12:17:28.989521 Total UI for P1: 0, mck2ui 16
6072 12:17:28.992566 best dqsien dly found for B1: ( 0, 10, 24)
6073 12:17:28.996331 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6074 12:17:28.999257 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6075 12:17:28.999340
6076 12:17:29.005847 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6077 12:17:29.009334 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6078 12:17:29.012489 [Gating] SW calibration Done
6079 12:17:29.012572 ==
6080 12:17:29.015827 Dram Type= 6, Freq= 0, CH_0, rank 0
6081 12:17:29.019009 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6082 12:17:29.019092 ==
6083 12:17:29.019159 RX Vref Scan: 0
6084 12:17:29.019220
6085 12:17:29.022511 RX Vref 0 -> 0, step: 1
6086 12:17:29.022595
6087 12:17:29.025817 RX Delay -410 -> 252, step: 16
6088 12:17:29.029078 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6089 12:17:29.035687 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6090 12:17:29.038989 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6091 12:17:29.042341 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6092 12:17:29.045923 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6093 12:17:29.052411 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6094 12:17:29.056057 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6095 12:17:29.058938 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6096 12:17:29.062463 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6097 12:17:29.065605 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6098 12:17:29.072452 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6099 12:17:29.075421 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6100 12:17:29.078874 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6101 12:17:29.085566 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6102 12:17:29.088740 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6103 12:17:29.092502 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6104 12:17:29.092585 ==
6105 12:17:29.095331 Dram Type= 6, Freq= 0, CH_0, rank 0
6106 12:17:29.098729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6107 12:17:29.101952 ==
6108 12:17:29.102034 DQS Delay:
6109 12:17:29.102100 DQS0 = 51, DQS1 = 59
6110 12:17:29.105190 DQM Delay:
6111 12:17:29.105274 DQM0 = 12, DQM1 = 12
6112 12:17:29.108758 DQ Delay:
6113 12:17:29.108841 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6114 12:17:29.112336 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6115 12:17:29.115364 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6116 12:17:29.118545 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6117 12:17:29.118628
6118 12:17:29.118693
6119 12:17:29.122047 ==
6120 12:17:29.122130 Dram Type= 6, Freq= 0, CH_0, rank 0
6121 12:17:29.128503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6122 12:17:29.128587 ==
6123 12:17:29.128653
6124 12:17:29.128714
6125 12:17:29.131963 TX Vref Scan disable
6126 12:17:29.132045 == TX Byte 0 ==
6127 12:17:29.135283 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6128 12:17:29.141976 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6129 12:17:29.142061 == TX Byte 1 ==
6130 12:17:29.145433 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6131 12:17:29.151770 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6132 12:17:29.151854 ==
6133 12:17:29.155349 Dram Type= 6, Freq= 0, CH_0, rank 0
6134 12:17:29.158336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6135 12:17:29.158420 ==
6136 12:17:29.158485
6137 12:17:29.158545
6138 12:17:29.161514 TX Vref Scan disable
6139 12:17:29.161596 == TX Byte 0 ==
6140 12:17:29.165085 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6141 12:17:29.171617 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6142 12:17:29.171701 == TX Byte 1 ==
6143 12:17:29.178076 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6144 12:17:29.181713 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6145 12:17:29.181796
6146 12:17:29.181862 [DATLAT]
6147 12:17:29.184667 Freq=400, CH0 RK0
6148 12:17:29.184755
6149 12:17:29.184821 DATLAT Default: 0xf
6150 12:17:29.188315 0, 0xFFFF, sum = 0
6151 12:17:29.188400 1, 0xFFFF, sum = 0
6152 12:17:29.191592 2, 0xFFFF, sum = 0
6153 12:17:29.191676 3, 0xFFFF, sum = 0
6154 12:17:29.194792 4, 0xFFFF, sum = 0
6155 12:17:29.194877 5, 0xFFFF, sum = 0
6156 12:17:29.197938 6, 0xFFFF, sum = 0
6157 12:17:29.198023 7, 0xFFFF, sum = 0
6158 12:17:29.201381 8, 0xFFFF, sum = 0
6159 12:17:29.201466 9, 0xFFFF, sum = 0
6160 12:17:29.204673 10, 0xFFFF, sum = 0
6161 12:17:29.204758 11, 0xFFFF, sum = 0
6162 12:17:29.208387 12, 0x0, sum = 1
6163 12:17:29.208474 13, 0x0, sum = 2
6164 12:17:29.211679 14, 0x0, sum = 3
6165 12:17:29.211763 15, 0x0, sum = 4
6166 12:17:29.214812 best_step = 13
6167 12:17:29.214895
6168 12:17:29.214961 ==
6169 12:17:29.218303 Dram Type= 6, Freq= 0, CH_0, rank 0
6170 12:17:29.221772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6171 12:17:29.221856 ==
6172 12:17:29.224783 RX Vref Scan: 1
6173 12:17:29.224866
6174 12:17:29.224932 RX Vref 0 -> 0, step: 1
6175 12:17:29.224995
6176 12:17:29.228004 RX Delay -359 -> 252, step: 8
6177 12:17:29.228087
6178 12:17:29.231273 Set Vref, RX VrefLevel [Byte0]: 47
6179 12:17:29.234619 [Byte1]: 46
6180 12:17:29.239566
6181 12:17:29.239649 Final RX Vref Byte 0 = 47 to rank0
6182 12:17:29.242762 Final RX Vref Byte 1 = 46 to rank0
6183 12:17:29.246023 Final RX Vref Byte 0 = 47 to rank1
6184 12:17:29.249430 Final RX Vref Byte 1 = 46 to rank1==
6185 12:17:29.252561 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 12:17:29.259060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6187 12:17:29.259143 ==
6188 12:17:29.259209 DQS Delay:
6189 12:17:29.262704 DQS0 = 52, DQS1 = 68
6190 12:17:29.262787 DQM Delay:
6191 12:17:29.262853 DQM0 = 9, DQM1 = 17
6192 12:17:29.265957 DQ Delay:
6193 12:17:29.269181 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6194 12:17:29.269264 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6195 12:17:29.272346 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6196 12:17:29.275730 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6197 12:17:29.275813
6198 12:17:29.279017
6199 12:17:29.285556 [DQSOSCAuto] RK0, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6200 12:17:29.289031 CH0 RK0: MR19=C0C, MR18=A4A4
6201 12:17:29.295648 CH0_RK0: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6202 12:17:29.295731 ==
6203 12:17:29.298926 Dram Type= 6, Freq= 0, CH_0, rank 1
6204 12:17:29.302047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6205 12:17:29.302134 ==
6206 12:17:29.305759 [Gating] SW mode calibration
6207 12:17:29.312112 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6208 12:17:29.318863 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6209 12:17:29.322139 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6210 12:17:29.325332 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6211 12:17:29.332103 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6212 12:17:29.335344 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6213 12:17:29.338581 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6214 12:17:29.341949 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6215 12:17:29.348599 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6216 12:17:29.351914 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6217 12:17:29.355123 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6218 12:17:29.358509 Total UI for P1: 0, mck2ui 16
6219 12:17:29.361972 best dqsien dly found for B0: ( 0, 10, 16)
6220 12:17:29.365232 Total UI for P1: 0, mck2ui 16
6221 12:17:29.368395 best dqsien dly found for B1: ( 0, 10, 16)
6222 12:17:29.371755 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6223 12:17:29.378320 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6224 12:17:29.378428
6225 12:17:29.381586 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6226 12:17:29.385092 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6227 12:17:29.388385 [Gating] SW calibration Done
6228 12:17:29.388467 ==
6229 12:17:29.391630 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 12:17:29.394852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6231 12:17:29.394936 ==
6232 12:17:29.398331 RX Vref Scan: 0
6233 12:17:29.398414
6234 12:17:29.398480 RX Vref 0 -> 0, step: 1
6235 12:17:29.398543
6236 12:17:29.401567 RX Delay -410 -> 252, step: 16
6237 12:17:29.408107 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6238 12:17:29.411259 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6239 12:17:29.414660 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6240 12:17:29.418339 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6241 12:17:29.424722 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6242 12:17:29.427989 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6243 12:17:29.431133 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6244 12:17:29.434431 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6245 12:17:29.441096 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6246 12:17:29.444278 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6247 12:17:29.447471 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6248 12:17:29.450898 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6249 12:17:29.457578 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6250 12:17:29.460892 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6251 12:17:29.464160 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6252 12:17:29.467611 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6253 12:17:29.471078 ==
6254 12:17:29.474119 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 12:17:29.477377 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6256 12:17:29.477461 ==
6257 12:17:29.477528 DQS Delay:
6258 12:17:29.480769 DQS0 = 43, DQS1 = 59
6259 12:17:29.480852 DQM Delay:
6260 12:17:29.484099 DQM0 = 7, DQM1 = 15
6261 12:17:29.484206 DQ Delay:
6262 12:17:29.487488 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6263 12:17:29.490760 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6264 12:17:29.493874 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6265 12:17:29.497271 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6266 12:17:29.497354
6267 12:17:29.497420
6268 12:17:29.497481 ==
6269 12:17:29.500626 Dram Type= 6, Freq= 0, CH_0, rank 1
6270 12:17:29.503838 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6271 12:17:29.503925 ==
6272 12:17:29.503991
6273 12:17:29.504053
6274 12:17:29.507285 TX Vref Scan disable
6275 12:17:29.507369 == TX Byte 0 ==
6276 12:17:29.513845 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6277 12:17:29.517228 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6278 12:17:29.517312 == TX Byte 1 ==
6279 12:17:29.523956 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6280 12:17:29.526972 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6281 12:17:29.527056 ==
6282 12:17:29.530108 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 12:17:29.533408 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6284 12:17:29.533493 ==
6285 12:17:29.533568
6286 12:17:29.533632
6287 12:17:29.536741 TX Vref Scan disable
6288 12:17:29.536824 == TX Byte 0 ==
6289 12:17:29.543371 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6290 12:17:29.546578 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6291 12:17:29.546663 == TX Byte 1 ==
6292 12:17:29.553261 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6293 12:17:29.556513 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6294 12:17:29.556598
6295 12:17:29.556665 [DATLAT]
6296 12:17:29.559982 Freq=400, CH0 RK1
6297 12:17:29.560067
6298 12:17:29.560133 DATLAT Default: 0xd
6299 12:17:29.563019 0, 0xFFFF, sum = 0
6300 12:17:29.563104 1, 0xFFFF, sum = 0
6301 12:17:29.566503 2, 0xFFFF, sum = 0
6302 12:17:29.566588 3, 0xFFFF, sum = 0
6303 12:17:29.570069 4, 0xFFFF, sum = 0
6304 12:17:29.570154 5, 0xFFFF, sum = 0
6305 12:17:29.573412 6, 0xFFFF, sum = 0
6306 12:17:29.576294 7, 0xFFFF, sum = 0
6307 12:17:29.576378 8, 0xFFFF, sum = 0
6308 12:17:29.579912 9, 0xFFFF, sum = 0
6309 12:17:29.579998 10, 0xFFFF, sum = 0
6310 12:17:29.583155 11, 0xFFFF, sum = 0
6311 12:17:29.583243 12, 0x0, sum = 1
6312 12:17:29.586362 13, 0x0, sum = 2
6313 12:17:29.586447 14, 0x0, sum = 3
6314 12:17:29.589663 15, 0x0, sum = 4
6315 12:17:29.589747 best_step = 13
6316 12:17:29.589813
6317 12:17:29.589874 ==
6318 12:17:29.593002 Dram Type= 6, Freq= 0, CH_0, rank 1
6319 12:17:29.596112 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6320 12:17:29.596204 ==
6321 12:17:29.599370 RX Vref Scan: 0
6322 12:17:29.599452
6323 12:17:29.602828 RX Vref 0 -> 0, step: 1
6324 12:17:29.602942
6325 12:17:29.603037 RX Delay -359 -> 252, step: 8
6326 12:17:29.611694 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6327 12:17:29.615047 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6328 12:17:29.618314 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6329 12:17:29.621627 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6330 12:17:29.628038 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6331 12:17:29.631461 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6332 12:17:29.634807 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6333 12:17:29.638105 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6334 12:17:29.645037 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6335 12:17:29.648687 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6336 12:17:29.651579 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6337 12:17:29.654990 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6338 12:17:29.661587 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6339 12:17:29.664834 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6340 12:17:29.668074 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6341 12:17:29.674767 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6342 12:17:29.674854 ==
6343 12:17:29.678219 Dram Type= 6, Freq= 0, CH_0, rank 1
6344 12:17:29.681413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6345 12:17:29.681498 ==
6346 12:17:29.681564 DQS Delay:
6347 12:17:29.684828 DQS0 = 52, DQS1 = 68
6348 12:17:29.684911 DQM Delay:
6349 12:17:29.688083 DQM0 = 10, DQM1 = 16
6350 12:17:29.688166 DQ Delay:
6351 12:17:29.691368 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6352 12:17:29.694776 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6353 12:17:29.698079 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6354 12:17:29.701458 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6355 12:17:29.701542
6356 12:17:29.701608
6357 12:17:29.708083 [DQSOSCAuto] RK1, (LSB)MR18= 0xcfcf, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6358 12:17:29.711514 CH0 RK1: MR19=C0C, MR18=CFCF
6359 12:17:29.717874 CH0_RK1: MR19=0xC0C, MR18=0xCFCF, DQSOSC=384, MR23=63, INC=400, DEC=267
6360 12:17:29.721172 [RxdqsGatingPostProcess] freq 400
6361 12:17:29.727857 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6362 12:17:29.727945 Pre-setting of DQS Precalculation
6363 12:17:29.734725 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6364 12:17:29.734818 ==
6365 12:17:29.737847 Dram Type= 6, Freq= 0, CH_1, rank 0
6366 12:17:29.741300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6367 12:17:29.741405 ==
6368 12:17:29.748123 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6369 12:17:29.754510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6370 12:17:29.757689 [CA 0] Center 36 (8~64) winsize 57
6371 12:17:29.761132 [CA 1] Center 36 (8~64) winsize 57
6372 12:17:29.764488 [CA 2] Center 36 (8~64) winsize 57
6373 12:17:29.767796 [CA 3] Center 36 (8~64) winsize 57
6374 12:17:29.767893 [CA 4] Center 36 (8~64) winsize 57
6375 12:17:29.771000 [CA 5] Center 36 (8~64) winsize 57
6376 12:17:29.771091
6377 12:17:29.777801 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6378 12:17:29.777920
6379 12:17:29.780896 [CATrainingPosCal] consider 1 rank data
6380 12:17:29.784256 u2DelayCellTimex100 = 270/100 ps
6381 12:17:29.787638 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 12:17:29.791205 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 12:17:29.794367 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 12:17:29.797643 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 12:17:29.800977 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 12:17:29.804300 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 12:17:29.804405
6388 12:17:29.807542 CA PerBit enable=1, Macro0, CA PI delay=36
6389 12:17:29.807629
6390 12:17:29.810947 [CBTSetCACLKResult] CA Dly = 36
6391 12:17:29.814314 CS Dly: 1 (0~32)
6392 12:17:29.814413 ==
6393 12:17:29.817660 Dram Type= 6, Freq= 0, CH_1, rank 1
6394 12:17:29.820790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6395 12:17:29.820880 ==
6396 12:17:29.827310 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6397 12:17:29.830564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6398 12:17:29.833887 [CA 0] Center 36 (8~64) winsize 57
6399 12:17:29.837273 [CA 1] Center 36 (8~64) winsize 57
6400 12:17:29.840855 [CA 2] Center 36 (8~64) winsize 57
6401 12:17:29.843990 [CA 3] Center 36 (8~64) winsize 57
6402 12:17:29.847241 [CA 4] Center 36 (8~64) winsize 57
6403 12:17:29.850808 [CA 5] Center 36 (8~64) winsize 57
6404 12:17:29.850892
6405 12:17:29.853933 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6406 12:17:29.854016
6407 12:17:29.857061 [CATrainingPosCal] consider 2 rank data
6408 12:17:29.860580 u2DelayCellTimex100 = 270/100 ps
6409 12:17:29.863757 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 12:17:29.867025 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 12:17:29.873772 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 12:17:29.877297 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 12:17:29.880681 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 12:17:29.883706 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 12:17:29.883790
6416 12:17:29.887085 CA PerBit enable=1, Macro0, CA PI delay=36
6417 12:17:29.887169
6418 12:17:29.890207 [CBTSetCACLKResult] CA Dly = 36
6419 12:17:29.890291 CS Dly: 1 (0~32)
6420 12:17:29.890357
6421 12:17:29.893644 ----->DramcWriteLeveling(PI) begin...
6422 12:17:29.897058 ==
6423 12:17:29.900247 Dram Type= 6, Freq= 0, CH_1, rank 0
6424 12:17:29.903631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6425 12:17:29.903722 ==
6426 12:17:29.906836 Write leveling (Byte 0): 32 => 0
6427 12:17:29.910102 Write leveling (Byte 1): 32 => 0
6428 12:17:29.913544 DramcWriteLeveling(PI) end<-----
6429 12:17:29.913627
6430 12:17:29.913692 ==
6431 12:17:29.916861 Dram Type= 6, Freq= 0, CH_1, rank 0
6432 12:17:29.920079 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6433 12:17:29.920162 ==
6434 12:17:29.923484 [Gating] SW mode calibration
6435 12:17:29.929918 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6436 12:17:29.933266 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6437 12:17:29.939925 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 12:17:29.943263 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6439 12:17:29.946674 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 12:17:29.953259 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6441 12:17:29.956431 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 12:17:29.959631 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 12:17:29.966436 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6444 12:17:29.969615 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6445 12:17:29.973169 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6446 12:17:29.976217 Total UI for P1: 0, mck2ui 16
6447 12:17:29.979716 best dqsien dly found for B0: ( 0, 10, 16)
6448 12:17:29.983043 Total UI for P1: 0, mck2ui 16
6449 12:17:29.986211 best dqsien dly found for B1: ( 0, 10, 16)
6450 12:17:29.989451 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6451 12:17:29.995931 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6452 12:17:29.996014
6453 12:17:29.999640 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6454 12:17:30.002800 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6455 12:17:30.005954 [Gating] SW calibration Done
6456 12:17:30.006039 ==
6457 12:17:30.009270 Dram Type= 6, Freq= 0, CH_1, rank 0
6458 12:17:30.012697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6459 12:17:30.012780 ==
6460 12:17:30.015848 RX Vref Scan: 0
6461 12:17:30.015931
6462 12:17:30.015997 RX Vref 0 -> 0, step: 1
6463 12:17:30.016060
6464 12:17:30.019411 RX Delay -410 -> 252, step: 16
6465 12:17:30.025959 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6466 12:17:30.029065 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6467 12:17:30.032518 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6468 12:17:30.035738 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6469 12:17:30.042346 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6470 12:17:30.045568 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6471 12:17:30.048880 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6472 12:17:30.052323 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6473 12:17:30.058730 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6474 12:17:30.061986 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6475 12:17:30.065272 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6476 12:17:30.068843 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6477 12:17:30.075405 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6478 12:17:30.078728 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6479 12:17:30.081810 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6480 12:17:30.088464 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6481 12:17:30.088548 ==
6482 12:17:30.091707 Dram Type= 6, Freq= 0, CH_1, rank 0
6483 12:17:30.095203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6484 12:17:30.095287 ==
6485 12:17:30.095353 DQS Delay:
6486 12:17:30.098587 DQS0 = 43, DQS1 = 59
6487 12:17:30.098669 DQM Delay:
6488 12:17:30.101888 DQM0 = 6, DQM1 = 14
6489 12:17:30.101970 DQ Delay:
6490 12:17:30.105534 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6491 12:17:30.108475 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6492 12:17:30.111727 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6493 12:17:30.115039 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6494 12:17:30.115120
6495 12:17:30.115185
6496 12:17:30.115244 ==
6497 12:17:30.118545 Dram Type= 6, Freq= 0, CH_1, rank 0
6498 12:17:30.122052 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6499 12:17:30.122134 ==
6500 12:17:30.122198
6501 12:17:30.122257
6502 12:17:30.124786 TX Vref Scan disable
6503 12:17:30.124866 == TX Byte 0 ==
6504 12:17:30.131742 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6505 12:17:30.135058 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6506 12:17:30.135138 == TX Byte 1 ==
6507 12:17:30.141579 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6508 12:17:30.144731 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6509 12:17:30.144812 ==
6510 12:17:30.148191 Dram Type= 6, Freq= 0, CH_1, rank 0
6511 12:17:30.151329 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6512 12:17:30.151424 ==
6513 12:17:30.151502
6514 12:17:30.151561
6515 12:17:30.154734 TX Vref Scan disable
6516 12:17:30.157921 == TX Byte 0 ==
6517 12:17:30.161541 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6518 12:17:30.164817 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6519 12:17:30.168342 == TX Byte 1 ==
6520 12:17:30.171350 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6521 12:17:30.174476 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6522 12:17:30.174556
6523 12:17:30.174621 [DATLAT]
6524 12:17:30.177734 Freq=400, CH1 RK0
6525 12:17:30.177815
6526 12:17:30.181223 DATLAT Default: 0xf
6527 12:17:30.181304 0, 0xFFFF, sum = 0
6528 12:17:30.184374 1, 0xFFFF, sum = 0
6529 12:17:30.184456 2, 0xFFFF, sum = 0
6530 12:17:30.187569 3, 0xFFFF, sum = 0
6531 12:17:30.187650 4, 0xFFFF, sum = 0
6532 12:17:30.191354 5, 0xFFFF, sum = 0
6533 12:17:30.191436 6, 0xFFFF, sum = 0
6534 12:17:30.194373 7, 0xFFFF, sum = 0
6535 12:17:30.194455 8, 0xFFFF, sum = 0
6536 12:17:30.197743 9, 0xFFFF, sum = 0
6537 12:17:30.197825 10, 0xFFFF, sum = 0
6538 12:17:30.201262 11, 0xFFFF, sum = 0
6539 12:17:30.201343 12, 0x0, sum = 1
6540 12:17:30.204295 13, 0x0, sum = 2
6541 12:17:30.204391 14, 0x0, sum = 3
6542 12:17:30.207509 15, 0x0, sum = 4
6543 12:17:30.207623 best_step = 13
6544 12:17:30.207717
6545 12:17:30.207807 ==
6546 12:17:30.211001 Dram Type= 6, Freq= 0, CH_1, rank 0
6547 12:17:30.217632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6548 12:17:30.217715 ==
6549 12:17:30.217779 RX Vref Scan: 1
6550 12:17:30.217839
6551 12:17:30.220843 RX Vref 0 -> 0, step: 1
6552 12:17:30.220924
6553 12:17:30.223939 RX Delay -359 -> 252, step: 8
6554 12:17:30.224046
6555 12:17:30.227359 Set Vref, RX VrefLevel [Byte0]: 53
6556 12:17:30.230596 [Byte1]: 48
6557 12:17:30.230677
6558 12:17:30.234344 Final RX Vref Byte 0 = 53 to rank0
6559 12:17:30.237304 Final RX Vref Byte 1 = 48 to rank0
6560 12:17:30.240638 Final RX Vref Byte 0 = 53 to rank1
6561 12:17:30.244071 Final RX Vref Byte 1 = 48 to rank1==
6562 12:17:30.247372 Dram Type= 6, Freq= 0, CH_1, rank 0
6563 12:17:30.250642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6564 12:17:30.254037 ==
6565 12:17:30.254118 DQS Delay:
6566 12:17:30.254183 DQS0 = 48, DQS1 = 64
6567 12:17:30.257227 DQM Delay:
6568 12:17:30.257308 DQM0 = 8, DQM1 = 16
6569 12:17:30.260428 DQ Delay:
6570 12:17:30.260509 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6571 12:17:30.263893 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6572 12:17:30.267090 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6573 12:17:30.270727 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6574 12:17:30.270809
6575 12:17:30.270874
6576 12:17:30.280377 [DQSOSCAuto] RK0, (LSB)MR18= 0xe1e1, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6577 12:17:30.283672 CH1 RK0: MR19=C0C, MR18=E1E1
6578 12:17:30.290206 CH1_RK0: MR19=0xC0C, MR18=0xE1E1, DQSOSC=382, MR23=63, INC=404, DEC=269
6579 12:17:30.290293 ==
6580 12:17:30.293567 Dram Type= 6, Freq= 0, CH_1, rank 1
6581 12:17:30.296614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6582 12:17:30.296697 ==
6583 12:17:30.300050 [Gating] SW mode calibration
6584 12:17:30.306853 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6585 12:17:30.310176 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6586 12:17:30.316531 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6587 12:17:30.319909 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6588 12:17:30.323325 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6589 12:17:30.329830 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6590 12:17:30.333598 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6591 12:17:30.336671 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6592 12:17:30.343228 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6593 12:17:30.346550 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6594 12:17:30.349896 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6595 12:17:30.353078 Total UI for P1: 0, mck2ui 16
6596 12:17:30.356556 best dqsien dly found for B0: ( 0, 10, 16)
6597 12:17:30.359791 Total UI for P1: 0, mck2ui 16
6598 12:17:30.366162 best dqsien dly found for B1: ( 0, 10, 16)
6599 12:17:30.366455 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6600 12:17:30.369445 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6601 12:17:30.373043
6602 12:17:30.376385 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6603 12:17:30.379622 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6604 12:17:30.382814 [Gating] SW calibration Done
6605 12:17:30.382898 ==
6606 12:17:30.386454 Dram Type= 6, Freq= 0, CH_1, rank 1
6607 12:17:30.389801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6608 12:17:30.389884 ==
6609 12:17:30.389951 RX Vref Scan: 0
6610 12:17:30.392676
6611 12:17:30.392759 RX Vref 0 -> 0, step: 1
6612 12:17:30.392824
6613 12:17:30.396084 RX Delay -410 -> 252, step: 16
6614 12:17:30.399419 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6615 12:17:30.406016 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6616 12:17:30.409386 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6617 12:17:30.412844 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6618 12:17:30.416039 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6619 12:17:30.422626 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6620 12:17:30.425954 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6621 12:17:30.429418 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6622 12:17:30.432588 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6623 12:17:30.439363 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6624 12:17:30.442667 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6625 12:17:30.446105 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6626 12:17:30.449145 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6627 12:17:30.455883 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6628 12:17:30.459009 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6629 12:17:30.462628 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6630 12:17:30.462712 ==
6631 12:17:30.465617 Dram Type= 6, Freq= 0, CH_1, rank 1
6632 12:17:30.472217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6633 12:17:30.472303 ==
6634 12:17:30.472370 DQS Delay:
6635 12:17:30.475539 DQS0 = 43, DQS1 = 59
6636 12:17:30.475622 DQM Delay:
6637 12:17:30.475688 DQM0 = 9, DQM1 = 17
6638 12:17:30.479203 DQ Delay:
6639 12:17:30.482496 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6640 12:17:30.482579 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6641 12:17:30.485426 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6642 12:17:30.488964 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6643 12:17:30.489048
6644 12:17:30.492212
6645 12:17:30.492309 ==
6646 12:17:30.495473 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 12:17:30.498720 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6648 12:17:30.498805 ==
6649 12:17:30.498870
6650 12:17:30.498931
6651 12:17:30.502282 TX Vref Scan disable
6652 12:17:30.502365 == TX Byte 0 ==
6653 12:17:30.505379 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6654 12:17:30.511952 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6655 12:17:30.512055 == TX Byte 1 ==
6656 12:17:30.515535 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6657 12:17:30.521971 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6658 12:17:30.522060 ==
6659 12:17:30.525249 Dram Type= 6, Freq= 0, CH_1, rank 1
6660 12:17:30.528593 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6661 12:17:30.528678 ==
6662 12:17:30.528744
6663 12:17:30.528805
6664 12:17:30.531997 TX Vref Scan disable
6665 12:17:30.532080 == TX Byte 0 ==
6666 12:17:30.535273 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6667 12:17:30.541873 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6668 12:17:30.541958 == TX Byte 1 ==
6669 12:17:30.545125 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6670 12:17:30.551958 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6671 12:17:30.552043
6672 12:17:30.552108 [DATLAT]
6673 12:17:30.552170 Freq=400, CH1 RK1
6674 12:17:30.554894
6675 12:17:30.554977 DATLAT Default: 0xd
6676 12:17:30.558200 0, 0xFFFF, sum = 0
6677 12:17:30.558285 1, 0xFFFF, sum = 0
6678 12:17:30.561556 2, 0xFFFF, sum = 0
6679 12:17:30.561640 3, 0xFFFF, sum = 0
6680 12:17:30.564972 4, 0xFFFF, sum = 0
6681 12:17:30.565057 5, 0xFFFF, sum = 0
6682 12:17:30.568064 6, 0xFFFF, sum = 0
6683 12:17:30.568148 7, 0xFFFF, sum = 0
6684 12:17:30.571593 8, 0xFFFF, sum = 0
6685 12:17:30.571678 9, 0xFFFF, sum = 0
6686 12:17:30.574748 10, 0xFFFF, sum = 0
6687 12:17:30.574832 11, 0xFFFF, sum = 0
6688 12:17:30.577906 12, 0x0, sum = 1
6689 12:17:30.578034 13, 0x0, sum = 2
6690 12:17:30.581278 14, 0x0, sum = 3
6691 12:17:30.581362 15, 0x0, sum = 4
6692 12:17:30.584657 best_step = 13
6693 12:17:30.584741
6694 12:17:30.584805 ==
6695 12:17:30.588148 Dram Type= 6, Freq= 0, CH_1, rank 1
6696 12:17:30.591253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6697 12:17:30.591336 ==
6698 12:17:30.594466 RX Vref Scan: 0
6699 12:17:30.594548
6700 12:17:30.594614 RX Vref 0 -> 0, step: 1
6701 12:17:30.594675
6702 12:17:30.597987 RX Delay -359 -> 252, step: 8
6703 12:17:30.606013 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6704 12:17:30.609131 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6705 12:17:30.612514 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6706 12:17:30.615754 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6707 12:17:30.622929 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6708 12:17:30.625950 iDelay=225, Bit 5, Center -28 (-279 ~ 224) 504
6709 12:17:30.629077 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6710 12:17:30.632218 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6711 12:17:30.638985 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6712 12:17:30.642677 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6713 12:17:30.645666 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6714 12:17:30.652168 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6715 12:17:30.655534 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6716 12:17:30.659093 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6717 12:17:30.662338 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6718 12:17:30.668724 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6719 12:17:30.668810 ==
6720 12:17:30.671989 Dram Type= 6, Freq= 0, CH_1, rank 1
6721 12:17:30.675659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6722 12:17:30.675744 ==
6723 12:17:30.675811 DQS Delay:
6724 12:17:30.678802 DQS0 = 48, DQS1 = 64
6725 12:17:30.678887 DQM Delay:
6726 12:17:30.682011 DQM0 = 9, DQM1 = 15
6727 12:17:30.682095 DQ Delay:
6728 12:17:30.685510 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6729 12:17:30.688591 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6730 12:17:30.691997 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6731 12:17:30.695212 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6732 12:17:30.695295
6733 12:17:30.695361
6734 12:17:30.701863 [DQSOSCAuto] RK1, (LSB)MR18= 0xacac, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6735 12:17:30.705198 CH1 RK1: MR19=C0C, MR18=ACAC
6736 12:17:30.711703 CH1_RK1: MR19=0xC0C, MR18=0xACAC, DQSOSC=388, MR23=63, INC=392, DEC=261
6737 12:17:30.715139 [RxdqsGatingPostProcess] freq 400
6738 12:17:30.721719 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6739 12:17:30.725131 Pre-setting of DQS Precalculation
6740 12:17:30.728426 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6741 12:17:30.735007 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6742 12:17:30.741549 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6743 12:17:30.741637
6744 12:17:30.741703
6745 12:17:30.744931 [Calibration Summary] 800 Mbps
6746 12:17:30.748530 CH 0, Rank 0
6747 12:17:30.748654 SW Impedance : PASS
6748 12:17:30.751641 DUTY Scan : NO K
6749 12:17:30.754951 ZQ Calibration : PASS
6750 12:17:30.755034 Jitter Meter : NO K
6751 12:17:30.758483 CBT Training : PASS
6752 12:17:30.761464 Write leveling : PASS
6753 12:17:30.761546 RX DQS gating : PASS
6754 12:17:30.764842 RX DQ/DQS(RDDQC) : PASS
6755 12:17:30.764925 TX DQ/DQS : PASS
6756 12:17:30.768199 RX DATLAT : PASS
6757 12:17:30.771380 RX DQ/DQS(Engine): PASS
6758 12:17:30.771460 TX OE : NO K
6759 12:17:30.774996 All Pass.
6760 12:17:30.775077
6761 12:17:30.775142 CH 0, Rank 1
6762 12:17:30.778132 SW Impedance : PASS
6763 12:17:30.778257 DUTY Scan : NO K
6764 12:17:30.781556 ZQ Calibration : PASS
6765 12:17:30.784921 Jitter Meter : NO K
6766 12:17:30.785005 CBT Training : PASS
6767 12:17:30.788323 Write leveling : NO K
6768 12:17:30.791461 RX DQS gating : PASS
6769 12:17:30.791567 RX DQ/DQS(RDDQC) : PASS
6770 12:17:30.795006 TX DQ/DQS : PASS
6771 12:17:30.798118 RX DATLAT : PASS
6772 12:17:30.798199 RX DQ/DQS(Engine): PASS
6773 12:17:30.801390 TX OE : NO K
6774 12:17:30.801473 All Pass.
6775 12:17:30.801538
6776 12:17:30.804870 CH 1, Rank 0
6777 12:17:30.804952 SW Impedance : PASS
6778 12:17:30.807814 DUTY Scan : NO K
6779 12:17:30.811269 ZQ Calibration : PASS
6780 12:17:30.811353 Jitter Meter : NO K
6781 12:17:30.814596 CBT Training : PASS
6782 12:17:30.817761 Write leveling : PASS
6783 12:17:30.817843 RX DQS gating : PASS
6784 12:17:30.821243 RX DQ/DQS(RDDQC) : PASS
6785 12:17:30.821325 TX DQ/DQS : PASS
6786 12:17:30.824625 RX DATLAT : PASS
6787 12:17:30.827698 RX DQ/DQS(Engine): PASS
6788 12:17:30.827780 TX OE : NO K
6789 12:17:30.831014 All Pass.
6790 12:17:30.831095
6791 12:17:30.831161 CH 1, Rank 1
6792 12:17:30.834467 SW Impedance : PASS
6793 12:17:30.834548 DUTY Scan : NO K
6794 12:17:30.837803 ZQ Calibration : PASS
6795 12:17:30.841171 Jitter Meter : NO K
6796 12:17:30.841254 CBT Training : PASS
6797 12:17:30.844398 Write leveling : NO K
6798 12:17:30.847802 RX DQS gating : PASS
6799 12:17:30.847883 RX DQ/DQS(RDDQC) : PASS
6800 12:17:30.851132 TX DQ/DQS : PASS
6801 12:17:30.854335 RX DATLAT : PASS
6802 12:17:30.854416 RX DQ/DQS(Engine): PASS
6803 12:17:30.857582 TX OE : NO K
6804 12:17:30.857665 All Pass.
6805 12:17:30.857731
6806 12:17:30.860918 DramC Write-DBI off
6807 12:17:30.864153 PER_BANK_REFRESH: Hybrid Mode
6808 12:17:30.864272 TX_TRACKING: ON
6809 12:17:30.874441 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6810 12:17:30.877446 [FAST_K] Save calibration result to emmc
6811 12:17:30.880828 dramc_set_vcore_voltage set vcore to 725000
6812 12:17:30.884375 Read voltage for 1600, 0
6813 12:17:30.884461 Vio18 = 0
6814 12:17:30.884527 Vcore = 725000
6815 12:17:30.887959 Vdram = 0
6816 12:17:30.888041 Vddq = 0
6817 12:17:30.888128 Vmddr = 0
6818 12:17:30.894078 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6819 12:17:30.897574 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6820 12:17:30.900810 MEM_TYPE=3, freq_sel=13
6821 12:17:30.904157 sv_algorithm_assistance_LP4_3733
6822 12:17:30.907291 ============ PULL DRAM RESETB DOWN ============
6823 12:17:30.910824 ========== PULL DRAM RESETB DOWN end =========
6824 12:17:30.917369 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6825 12:17:30.920553 ===================================
6826 12:17:30.923994 LPDDR4 DRAM CONFIGURATION
6827 12:17:30.927440 ===================================
6828 12:17:30.927524 EX_ROW_EN[0] = 0x0
6829 12:17:30.930666 EX_ROW_EN[1] = 0x0
6830 12:17:30.930750 LP4Y_EN = 0x0
6831 12:17:30.934045 WORK_FSP = 0x1
6832 12:17:30.934127 WL = 0x5
6833 12:17:30.937326 RL = 0x5
6834 12:17:30.937410 BL = 0x2
6835 12:17:30.940391 RPST = 0x0
6836 12:17:30.940474 RD_PRE = 0x0
6837 12:17:30.943953 WR_PRE = 0x1
6838 12:17:30.944036 WR_PST = 0x1
6839 12:17:30.947082 DBI_WR = 0x0
6840 12:17:30.947164 DBI_RD = 0x0
6841 12:17:30.950530 OTF = 0x1
6842 12:17:30.954056 ===================================
6843 12:17:30.957125 ===================================
6844 12:17:30.957207 ANA top config
6845 12:17:30.960497 ===================================
6846 12:17:30.963783 DLL_ASYNC_EN = 0
6847 12:17:30.967157 ALL_SLAVE_EN = 0
6848 12:17:30.970672 NEW_RANK_MODE = 1
6849 12:17:30.970758 DLL_IDLE_MODE = 1
6850 12:17:30.973825 LP45_APHY_COMB_EN = 1
6851 12:17:30.977163 TX_ODT_DIS = 0
6852 12:17:30.980421 NEW_8X_MODE = 1
6853 12:17:30.983610 ===================================
6854 12:17:30.987124 ===================================
6855 12:17:30.990675 data_rate = 3200
6856 12:17:30.990759 CKR = 1
6857 12:17:30.993917 DQ_P2S_RATIO = 8
6858 12:17:30.996929 ===================================
6859 12:17:31.000597 CA_P2S_RATIO = 8
6860 12:17:31.003569 DQ_CA_OPEN = 0
6861 12:17:31.006942 DQ_SEMI_OPEN = 0
6862 12:17:31.010350 CA_SEMI_OPEN = 0
6863 12:17:31.010435 CA_FULL_RATE = 0
6864 12:17:31.013714 DQ_CKDIV4_EN = 0
6865 12:17:31.016811 CA_CKDIV4_EN = 0
6866 12:17:31.020161 CA_PREDIV_EN = 0
6867 12:17:31.023465 PH8_DLY = 12
6868 12:17:31.026791 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6869 12:17:31.026875 DQ_AAMCK_DIV = 4
6870 12:17:31.030295 CA_AAMCK_DIV = 4
6871 12:17:31.033483 CA_ADMCK_DIV = 4
6872 12:17:31.036833 DQ_TRACK_CA_EN = 0
6873 12:17:31.040063 CA_PICK = 1600
6874 12:17:31.043507 CA_MCKIO = 1600
6875 12:17:31.046853 MCKIO_SEMI = 0
6876 12:17:31.046938 PLL_FREQ = 3068
6877 12:17:31.050194 DQ_UI_PI_RATIO = 32
6878 12:17:31.053430 CA_UI_PI_RATIO = 0
6879 12:17:31.056869 ===================================
6880 12:17:31.060109 ===================================
6881 12:17:31.063481 memory_type:LPDDR4
6882 12:17:31.066797 GP_NUM : 10
6883 12:17:31.066880 SRAM_EN : 1
6884 12:17:31.070242 MD32_EN : 0
6885 12:17:31.073443 ===================================
6886 12:17:31.073526 [ANA_INIT] >>>>>>>>>>>>>>
6887 12:17:31.076695 <<<<<< [CONFIGURE PHASE]: ANA_TX
6888 12:17:31.079842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6889 12:17:31.083364 ===================================
6890 12:17:31.086855 data_rate = 3200,PCW = 0X7600
6891 12:17:31.090123 ===================================
6892 12:17:31.093402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6893 12:17:31.099972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6894 12:17:31.103250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6895 12:17:31.110719 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6896 12:17:31.112944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6897 12:17:31.116609 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6898 12:17:31.119832 [ANA_INIT] flow start
6899 12:17:31.119920 [ANA_INIT] PLL >>>>>>>>
6900 12:17:31.122971 [ANA_INIT] PLL <<<<<<<<
6901 12:17:31.126313 [ANA_INIT] MIDPI >>>>>>>>
6902 12:17:31.126399 [ANA_INIT] MIDPI <<<<<<<<
6903 12:17:31.129906 [ANA_INIT] DLL >>>>>>>>
6904 12:17:31.132967 [ANA_INIT] DLL <<<<<<<<
6905 12:17:31.133051 [ANA_INIT] flow end
6906 12:17:31.139448 ============ LP4 DIFF to SE enter ============
6907 12:17:31.142974 ============ LP4 DIFF to SE exit ============
6908 12:17:31.146102 [ANA_INIT] <<<<<<<<<<<<<
6909 12:17:31.149524 [Flow] Enable top DCM control >>>>>
6910 12:17:31.152571 [Flow] Enable top DCM control <<<<<
6911 12:17:31.152656 Enable DLL master slave shuffle
6912 12:17:31.159362 ==============================================================
6913 12:17:31.162913 Gating Mode config
6914 12:17:31.165902 ==============================================================
6915 12:17:31.169031 Config description:
6916 12:17:31.179078 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6917 12:17:31.185484 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6918 12:17:31.189022 SELPH_MODE 0: By rank 1: By Phase
6919 12:17:31.195595 ==============================================================
6920 12:17:31.199045 GAT_TRACK_EN = 1
6921 12:17:31.202301 RX_GATING_MODE = 2
6922 12:17:31.205671 RX_GATING_TRACK_MODE = 2
6923 12:17:31.208887 SELPH_MODE = 1
6924 12:17:31.212042 PICG_EARLY_EN = 1
6925 12:17:31.212133 VALID_LAT_VALUE = 1
6926 12:17:31.218685 ==============================================================
6927 12:17:31.222017 Enter into Gating configuration >>>>
6928 12:17:31.225413 Exit from Gating configuration <<<<
6929 12:17:31.228488 Enter into DVFS_PRE_config >>>>>
6930 12:17:31.238457 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6931 12:17:31.241960 Exit from DVFS_PRE_config <<<<<
6932 12:17:31.245219 Enter into PICG configuration >>>>
6933 12:17:31.248405 Exit from PICG configuration <<<<
6934 12:17:31.251677 [RX_INPUT] configuration >>>>>
6935 12:17:31.255069 [RX_INPUT] configuration <<<<<
6936 12:17:31.261775 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6937 12:17:31.265587 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6938 12:17:31.271905 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6939 12:17:31.278331 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6940 12:17:31.284827 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6941 12:17:31.291748 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6942 12:17:31.295419 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6943 12:17:31.298374 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6944 12:17:31.301451 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6945 12:17:31.308418 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6946 12:17:31.311493 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6947 12:17:31.314692 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6948 12:17:31.318095 ===================================
6949 12:17:31.321372 LPDDR4 DRAM CONFIGURATION
6950 12:17:31.324612 ===================================
6951 12:17:31.324698 EX_ROW_EN[0] = 0x0
6952 12:17:31.328036 EX_ROW_EN[1] = 0x0
6953 12:17:31.331520 LP4Y_EN = 0x0
6954 12:17:31.331603 WORK_FSP = 0x1
6955 12:17:31.334627 WL = 0x5
6956 12:17:31.334708 RL = 0x5
6957 12:17:31.337950 BL = 0x2
6958 12:17:31.338032 RPST = 0x0
6959 12:17:31.341203 RD_PRE = 0x0
6960 12:17:31.341285 WR_PRE = 0x1
6961 12:17:31.344406 WR_PST = 0x1
6962 12:17:31.344490 DBI_WR = 0x0
6963 12:17:31.347830 DBI_RD = 0x0
6964 12:17:31.347926 OTF = 0x1
6965 12:17:31.350998 ===================================
6966 12:17:31.354859 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6967 12:17:31.361197 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6968 12:17:31.364459 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6969 12:17:31.368011 ===================================
6970 12:17:31.371296 LPDDR4 DRAM CONFIGURATION
6971 12:17:31.374562 ===================================
6972 12:17:31.374646 EX_ROW_EN[0] = 0x10
6973 12:17:31.378086 EX_ROW_EN[1] = 0x0
6974 12:17:31.378168 LP4Y_EN = 0x0
6975 12:17:31.381087 WORK_FSP = 0x1
6976 12:17:31.381169 WL = 0x5
6977 12:17:31.384457 RL = 0x5
6978 12:17:31.387667 BL = 0x2
6979 12:17:31.387749 RPST = 0x0
6980 12:17:31.390842 RD_PRE = 0x0
6981 12:17:31.390924 WR_PRE = 0x1
6982 12:17:31.394386 WR_PST = 0x1
6983 12:17:31.394468 DBI_WR = 0x0
6984 12:17:31.397649 DBI_RD = 0x0
6985 12:17:31.397732 OTF = 0x1
6986 12:17:31.400941 ===================================
6987 12:17:31.407577 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6988 12:17:31.407684 ==
6989 12:17:31.410686 Dram Type= 6, Freq= 0, CH_0, rank 0
6990 12:17:31.414167 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6991 12:17:31.414253 ==
6992 12:17:31.417324 [Duty_Offset_Calibration]
6993 12:17:31.420616 B0:0 B1:2 CA:1
6994 12:17:31.420700
6995 12:17:31.423917 [DutyScan_Calibration_Flow] k_type=0
6996 12:17:31.432538
6997 12:17:31.432630 ==CLK 0==
6998 12:17:31.436029 Final CLK duty delay cell = 0
6999 12:17:31.439376 [0] MAX Duty = 5187%(X100), DQS PI = 24
7000 12:17:31.442510 [0] MIN Duty = 4938%(X100), DQS PI = 52
7001 12:17:31.445838 [0] AVG Duty = 5062%(X100)
7002 12:17:31.445922
7003 12:17:31.449038 CH0 CLK Duty spec in!! Max-Min= 249%
7004 12:17:31.452363 [DutyScan_Calibration_Flow] ====Done====
7005 12:17:31.452447
7006 12:17:31.455772 [DutyScan_Calibration_Flow] k_type=1
7007 12:17:31.472848
7008 12:17:31.472973 ==DQS 0 ==
7009 12:17:31.475826 Final DQS duty delay cell = 0
7010 12:17:31.479220 [0] MAX Duty = 5156%(X100), DQS PI = 32
7011 12:17:31.482665 [0] MIN Duty = 5031%(X100), DQS PI = 8
7012 12:17:31.482749 [0] AVG Duty = 5093%(X100)
7013 12:17:31.485788
7014 12:17:31.485878 ==DQS 1 ==
7015 12:17:31.489177 Final DQS duty delay cell = 0
7016 12:17:31.492390 [0] MAX Duty = 5031%(X100), DQS PI = 2
7017 12:17:31.495639 [0] MIN Duty = 4876%(X100), DQS PI = 16
7018 12:17:31.495722 [0] AVG Duty = 4953%(X100)
7019 12:17:31.499104
7020 12:17:31.502489 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7021 12:17:31.502573
7022 12:17:31.505874 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7023 12:17:31.509004 [DutyScan_Calibration_Flow] ====Done====
7024 12:17:31.509093
7025 12:17:31.512325 [DutyScan_Calibration_Flow] k_type=3
7026 12:17:31.529730
7027 12:17:31.529921 ==DQM 0 ==
7028 12:17:31.532875 Final DQM duty delay cell = 0
7029 12:17:31.536201 [0] MAX Duty = 5187%(X100), DQS PI = 24
7030 12:17:31.539532 [0] MIN Duty = 4907%(X100), DQS PI = 56
7031 12:17:31.542796 [0] AVG Duty = 5047%(X100)
7032 12:17:31.542878
7033 12:17:31.542942 ==DQM 1 ==
7034 12:17:31.546292 Final DQM duty delay cell = 0
7035 12:17:31.549811 [0] MAX Duty = 5062%(X100), DQS PI = 52
7036 12:17:31.552849 [0] MIN Duty = 4782%(X100), DQS PI = 14
7037 12:17:31.556010 [0] AVG Duty = 4922%(X100)
7038 12:17:31.556092
7039 12:17:31.559467 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7040 12:17:31.559549
7041 12:17:31.562856 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7042 12:17:31.566014 [DutyScan_Calibration_Flow] ====Done====
7043 12:17:31.566095
7044 12:17:31.569224 [DutyScan_Calibration_Flow] k_type=2
7045 12:17:31.586184
7046 12:17:31.586299 ==DQ 0 ==
7047 12:17:31.589218 Final DQ duty delay cell = 0
7048 12:17:31.592623 [0] MAX Duty = 5218%(X100), DQS PI = 18
7049 12:17:31.596008 [0] MIN Duty = 4938%(X100), DQS PI = 56
7050 12:17:31.596090 [0] AVG Duty = 5078%(X100)
7051 12:17:31.596186
7052 12:17:31.599319 ==DQ 1 ==
7053 12:17:31.602643 Final DQ duty delay cell = -4
7054 12:17:31.606027 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7055 12:17:31.609282 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7056 12:17:31.612476 [-4] AVG Duty = 4953%(X100)
7057 12:17:31.612563
7058 12:17:31.615939 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7059 12:17:31.616023
7060 12:17:31.619442 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7061 12:17:31.622581 [DutyScan_Calibration_Flow] ====Done====
7062 12:17:31.622664 ==
7063 12:17:31.626254 Dram Type= 6, Freq= 0, CH_1, rank 0
7064 12:17:31.629138 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7065 12:17:31.629223 ==
7066 12:17:31.632944 [Duty_Offset_Calibration]
7067 12:17:31.633027 B0:0 B1:4 CA:-5
7068 12:17:31.633094
7069 12:17:31.635819 [DutyScan_Calibration_Flow] k_type=0
7070 12:17:31.646659
7071 12:17:31.646765 ==CLK 0==
7072 12:17:31.649801 Final CLK duty delay cell = 0
7073 12:17:31.653143 [0] MAX Duty = 5156%(X100), DQS PI = 24
7074 12:17:31.656644 [0] MIN Duty = 4906%(X100), DQS PI = 52
7075 12:17:31.656729 [0] AVG Duty = 5031%(X100)
7076 12:17:31.660141
7077 12:17:31.663273 CH1 CLK Duty spec in!! Max-Min= 250%
7078 12:17:31.666578 [DutyScan_Calibration_Flow] ====Done====
7079 12:17:31.666662
7080 12:17:31.669679 [DutyScan_Calibration_Flow] k_type=1
7081 12:17:31.685680
7082 12:17:31.685782 ==DQS 0 ==
7083 12:17:31.689028 Final DQS duty delay cell = 0
7084 12:17:31.691972 [0] MAX Duty = 5156%(X100), DQS PI = 18
7085 12:17:31.695197 [0] MIN Duty = 4844%(X100), DQS PI = 44
7086 12:17:31.698517 [0] AVG Duty = 5000%(X100)
7087 12:17:31.698612
7088 12:17:31.698679 ==DQS 1 ==
7089 12:17:31.702019 Final DQS duty delay cell = -4
7090 12:17:31.705125 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7091 12:17:31.708609 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7092 12:17:31.711698 [-4] AVG Duty = 4922%(X100)
7093 12:17:31.711782
7094 12:17:31.715198 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7095 12:17:31.715282
7096 12:17:31.718540 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7097 12:17:31.722034 [DutyScan_Calibration_Flow] ====Done====
7098 12:17:31.722117
7099 12:17:31.725017 [DutyScan_Calibration_Flow] k_type=3
7100 12:17:31.741487
7101 12:17:31.741593 ==DQM 0 ==
7102 12:17:31.744533 Final DQM duty delay cell = -4
7103 12:17:31.748164 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7104 12:17:31.751315 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7105 12:17:31.754385 [-4] AVG Duty = 4922%(X100)
7106 12:17:31.754468
7107 12:17:31.754535 ==DQM 1 ==
7108 12:17:31.758009 Final DQM duty delay cell = -4
7109 12:17:31.761169 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7110 12:17:31.764539 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7111 12:17:31.767734 [-4] AVG Duty = 5000%(X100)
7112 12:17:31.767816
7113 12:17:31.771038 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7114 12:17:31.771120
7115 12:17:31.774415 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7116 12:17:31.777627 [DutyScan_Calibration_Flow] ====Done====
7117 12:17:31.777709
7118 12:17:31.780996 [DutyScan_Calibration_Flow] k_type=2
7119 12:17:31.798797
7120 12:17:31.798882 ==DQ 0 ==
7121 12:17:31.801953 Final DQ duty delay cell = 0
7122 12:17:31.805337 [0] MAX Duty = 5093%(X100), DQS PI = 18
7123 12:17:31.809036 [0] MIN Duty = 4938%(X100), DQS PI = 46
7124 12:17:31.809121 [0] AVG Duty = 5015%(X100)
7125 12:17:31.812071
7126 12:17:31.812153 ==DQ 1 ==
7127 12:17:31.815438 Final DQ duty delay cell = 0
7128 12:17:31.818729 [0] MAX Duty = 5031%(X100), DQS PI = 4
7129 12:17:31.822079 [0] MIN Duty = 4876%(X100), DQS PI = 28
7130 12:17:31.822161 [0] AVG Duty = 4953%(X100)
7131 12:17:31.822227
7132 12:17:31.825446 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7133 12:17:31.828805
7134 12:17:31.832197 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7135 12:17:31.835206 [DutyScan_Calibration_Flow] ====Done====
7136 12:17:31.838568 nWR fixed to 30
7137 12:17:31.838651 [ModeRegInit_LP4] CH0 RK0
7138 12:17:31.842215 [ModeRegInit_LP4] CH0 RK1
7139 12:17:31.845314 [ModeRegInit_LP4] CH1 RK0
7140 12:17:31.845396 [ModeRegInit_LP4] CH1 RK1
7141 12:17:31.848560 match AC timing 4
7142 12:17:31.851831 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7143 12:17:31.858763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7144 12:17:31.862017 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7145 12:17:31.868590 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7146 12:17:31.871770 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7147 12:17:31.871853 [MiockJmeterHQA]
7148 12:17:31.871918
7149 12:17:31.875228 [DramcMiockJmeter] u1RxGatingPI = 0
7150 12:17:31.878568 0 : 4258, 4029
7151 12:17:31.878652 4 : 4252, 4027
7152 12:17:31.878719 8 : 4252, 4027
7153 12:17:31.881917 12 : 4253, 4026
7154 12:17:31.882001 16 : 4368, 4142
7155 12:17:31.885105 20 : 4253, 4026
7156 12:17:31.885188 24 : 4252, 4027
7157 12:17:31.888646 28 : 4363, 4138
7158 12:17:31.888730 32 : 4253, 4026
7159 12:17:31.892086 36 : 4363, 4138
7160 12:17:31.892170 40 : 4253, 4026
7161 12:17:31.892248 44 : 4252, 4027
7162 12:17:31.895027 48 : 4364, 4137
7163 12:17:31.895110 52 : 4255, 4029
7164 12:17:31.898571 56 : 4363, 4137
7165 12:17:31.898654 60 : 4252, 4027
7166 12:17:31.901874 64 : 4252, 4027
7167 12:17:31.901957 68 : 4366, 4140
7168 12:17:31.902024 72 : 4360, 4137
7169 12:17:31.905386 76 : 4365, 4140
7170 12:17:31.905469 80 : 4253, 4030
7171 12:17:31.908608 84 : 4252, 4029
7172 12:17:31.908691 88 : 4253, 4029
7173 12:17:31.912349 92 : 4250, 4026
7174 12:17:31.912431 96 : 4250, 4027
7175 12:17:31.915254 100 : 4363, 2259
7176 12:17:31.915335 104 : 4252, 0
7177 12:17:31.915400 108 : 4250, 0
7178 12:17:31.918624 112 : 4252, 0
7179 12:17:31.918706 116 : 4255, 0
7180 12:17:31.922209 120 : 4249, 0
7181 12:17:31.922290 124 : 4253, 0
7182 12:17:31.922355 128 : 4360, 0
7183 12:17:31.925316 132 : 4361, 0
7184 12:17:31.925398 136 : 4365, 0
7185 12:17:31.925464 140 : 4252, 0
7186 12:17:31.928635 144 : 4360, 0
7187 12:17:31.928716 148 : 4250, 0
7188 12:17:31.932012 152 : 4252, 0
7189 12:17:31.932094 156 : 4250, 0
7190 12:17:31.932159 160 : 4249, 0
7191 12:17:31.935305 164 : 4252, 0
7192 12:17:31.935386 168 : 4250, 0
7193 12:17:31.938387 172 : 4250, 0
7194 12:17:31.938468 176 : 4366, 0
7195 12:17:31.938534 180 : 4250, 0
7196 12:17:31.941731 184 : 4250, 0
7197 12:17:31.941813 188 : 4363, 0
7198 12:17:31.944971 192 : 4363, 0
7199 12:17:31.945053 196 : 4360, 0
7200 12:17:31.945118 200 : 4250, 0
7201 12:17:31.948369 204 : 4250, 0
7202 12:17:31.948451 208 : 4250, 0
7203 12:17:31.948516 212 : 4250, 0
7204 12:17:31.951644 216 : 4250, 0
7205 12:17:31.951726 220 : 4363, 598
7206 12:17:31.954799 224 : 4250, 3984
7207 12:17:31.954880 228 : 4255, 4029
7208 12:17:31.958365 232 : 4360, 4137
7209 12:17:31.958446 236 : 4250, 4027
7210 12:17:31.961568 240 : 4250, 4027
7211 12:17:31.961649 244 : 4250, 4027
7212 12:17:31.964807 248 : 4250, 4027
7213 12:17:31.964889 252 : 4250, 4027
7214 12:17:31.967993 256 : 4250, 4027
7215 12:17:31.968092 260 : 4250, 4027
7216 12:17:31.971704 264 : 4361, 4137
7217 12:17:31.971785 268 : 4250, 4026
7218 12:17:31.971851 272 : 4250, 4026
7219 12:17:31.974626 276 : 4250, 4027
7220 12:17:31.974707 280 : 4250, 4026
7221 12:17:31.977923 284 : 4361, 4137
7222 12:17:31.978004 288 : 4363, 4137
7223 12:17:31.981452 292 : 4247, 4024
7224 12:17:31.981535 296 : 4250, 4027
7225 12:17:31.984679 300 : 4251, 4027
7226 12:17:31.984761 304 : 4360, 4137
7227 12:17:31.988132 308 : 4250, 4027
7228 12:17:31.988271 312 : 4363, 4137
7229 12:17:31.991555 316 : 4361, 4138
7230 12:17:31.991637 320 : 4250, 4027
7231 12:17:31.994717 324 : 4250, 4026
7232 12:17:31.994800 328 : 4250, 4027
7233 12:17:31.994906 332 : 4249, 4027
7234 12:17:31.998355 336 : 4250, 3939
7235 12:17:31.998438 340 : 4360, 2116
7236 12:17:31.998503
7237 12:17:32.001669 MIOCK jitter meter ch=0
7238 12:17:32.001764
7239 12:17:32.004732 1T = (340-104) = 236 dly cells
7240 12:17:32.011210 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7241 12:17:32.011306 ==
7242 12:17:32.014858 Dram Type= 6, Freq= 0, CH_0, rank 0
7243 12:17:32.017965 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7244 12:17:32.018050 ==
7245 12:17:32.024770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7246 12:17:32.028126 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7247 12:17:32.031214 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7248 12:17:32.038087 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7249 12:17:32.045909 [CA 0] Center 41 (11~72) winsize 62
7250 12:17:32.049309 [CA 1] Center 41 (11~72) winsize 62
7251 12:17:32.052518 [CA 2] Center 37 (7~67) winsize 61
7252 12:17:32.056059 [CA 3] Center 37 (7~67) winsize 61
7253 12:17:32.059196 [CA 4] Center 35 (5~66) winsize 62
7254 12:17:32.062698 [CA 5] Center 35 (5~65) winsize 61
7255 12:17:32.062782
7256 12:17:32.065800 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7257 12:17:32.065944
7258 12:17:32.069331 [CATrainingPosCal] consider 1 rank data
7259 12:17:32.072534 u2DelayCellTimex100 = 275/100 ps
7260 12:17:32.075874 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7261 12:17:32.082568 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7262 12:17:32.086063 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7263 12:17:32.089417 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7264 12:17:32.092507 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7265 12:17:32.095686 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7266 12:17:32.095788
7267 12:17:32.099401 CA PerBit enable=1, Macro0, CA PI delay=35
7268 12:17:32.099501
7269 12:17:32.102356 [CBTSetCACLKResult] CA Dly = 35
7270 12:17:32.105798 CS Dly: 11 (0~42)
7271 12:17:32.109023 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7272 12:17:32.112197 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7273 12:17:32.112350 ==
7274 12:17:32.115682 Dram Type= 6, Freq= 0, CH_0, rank 1
7275 12:17:32.118887 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7276 12:17:32.122424 ==
7277 12:17:32.125634 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7278 12:17:32.128879 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7279 12:17:32.135817 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7280 12:17:32.138683 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7281 12:17:32.148475 [CA 0] Center 42 (12~73) winsize 62
7282 12:17:32.151677 [CA 1] Center 41 (11~72) winsize 62
7283 12:17:32.155167 [CA 2] Center 38 (9~68) winsize 60
7284 12:17:32.158325 [CA 3] Center 37 (8~67) winsize 60
7285 12:17:32.161740 [CA 4] Center 35 (5~65) winsize 61
7286 12:17:32.164946 [CA 5] Center 35 (5~66) winsize 62
7287 12:17:32.165032
7288 12:17:32.168401 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7289 12:17:32.168486
7290 12:17:32.171678 [CATrainingPosCal] consider 2 rank data
7291 12:17:32.175146 u2DelayCellTimex100 = 275/100 ps
7292 12:17:32.178319 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7293 12:17:32.184724 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7294 12:17:32.188332 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7295 12:17:32.191521 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7296 12:17:32.194826 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7297 12:17:32.198382 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7298 12:17:32.198475
7299 12:17:32.201384 CA PerBit enable=1, Macro0, CA PI delay=35
7300 12:17:32.201469
7301 12:17:32.204868 [CBTSetCACLKResult] CA Dly = 35
7302 12:17:32.208277 CS Dly: 11 (0~43)
7303 12:17:32.211524 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7304 12:17:32.215055 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7305 12:17:32.215166
7306 12:17:32.217906 ----->DramcWriteLeveling(PI) begin...
7307 12:17:32.217992 ==
7308 12:17:32.221569 Dram Type= 6, Freq= 0, CH_0, rank 0
7309 12:17:32.227960 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7310 12:17:32.228077 ==
7311 12:17:32.231486 Write leveling (Byte 0): 29 => 29
7312 12:17:32.231605 Write leveling (Byte 1): 25 => 25
7313 12:17:32.234552 DramcWriteLeveling(PI) end<-----
7314 12:17:32.234637
7315 12:17:32.237986 ==
7316 12:17:32.238071 Dram Type= 6, Freq= 0, CH_0, rank 0
7317 12:17:32.244770 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7318 12:17:32.244923 ==
7319 12:17:32.248020 [Gating] SW mode calibration
7320 12:17:32.254728 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7321 12:17:32.257841 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7322 12:17:32.264479 0 12 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7323 12:17:32.267835 0 12 4 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7324 12:17:32.271284 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7325 12:17:32.277924 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7326 12:17:32.281366 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7327 12:17:32.284658 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7328 12:17:32.291225 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7329 12:17:32.294486 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7330 12:17:32.297999 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
7331 12:17:32.304296 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
7332 12:17:32.307667 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7333 12:17:32.311016 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7334 12:17:32.317531 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7335 12:17:32.320890 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7336 12:17:32.324364 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 12:17:32.330771 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7338 12:17:32.334335 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7339 12:17:32.337494 0 14 4 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
7340 12:17:32.343968 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7341 12:17:32.347416 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7342 12:17:32.350643 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7343 12:17:32.357515 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7344 12:17:32.360547 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7345 12:17:32.363878 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7346 12:17:32.367436 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7347 12:17:32.374223 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7348 12:17:32.377418 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7349 12:17:32.380506 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 12:17:32.387185 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 12:17:32.390723 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 12:17:32.393910 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 12:17:32.400572 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 12:17:32.403775 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 12:17:32.407341 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 12:17:32.413991 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 12:17:32.417096 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 12:17:32.420705 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 12:17:32.427002 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 12:17:32.430261 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 12:17:32.433658 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7362 12:17:32.440213 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7363 12:17:32.443595 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7364 12:17:32.447643 Total UI for P1: 0, mck2ui 16
7365 12:17:32.450342 best dqsien dly found for B0: ( 1, 0, 30)
7366 12:17:32.453592 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7367 12:17:32.456706 Total UI for P1: 0, mck2ui 16
7368 12:17:32.460093 best dqsien dly found for B1: ( 1, 1, 4)
7369 12:17:32.463369 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7370 12:17:32.466669 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7371 12:17:32.466753
7372 12:17:32.473315 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7373 12:17:32.476738 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7374 12:17:32.476821 [Gating] SW calibration Done
7375 12:17:32.480207 ==
7376 12:17:32.480305 Dram Type= 6, Freq= 0, CH_0, rank 0
7377 12:17:32.486587 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7378 12:17:32.486671 ==
7379 12:17:32.486737 RX Vref Scan: 0
7380 12:17:32.486799
7381 12:17:32.489963 RX Vref 0 -> 0, step: 1
7382 12:17:32.490047
7383 12:17:32.493343 RX Delay 0 -> 252, step: 8
7384 12:17:32.496700 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7385 12:17:32.500059 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7386 12:17:32.503661 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7387 12:17:32.510224 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7388 12:17:32.513315 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7389 12:17:32.516520 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7390 12:17:32.520065 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7391 12:17:32.523184 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7392 12:17:32.529674 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7393 12:17:32.532932 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7394 12:17:32.536440 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7395 12:17:32.539758 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7396 12:17:32.543348 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7397 12:17:32.549880 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7398 12:17:32.553047 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7399 12:17:32.556160 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7400 12:17:32.556281 ==
7401 12:17:32.559430 Dram Type= 6, Freq= 0, CH_0, rank 0
7402 12:17:32.562903 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7403 12:17:32.562986 ==
7404 12:17:32.566245 DQS Delay:
7405 12:17:32.566327 DQS0 = 0, DQS1 = 0
7406 12:17:32.569524 DQM Delay:
7407 12:17:32.569607 DQM0 = 130, DQM1 = 124
7408 12:17:32.572911 DQ Delay:
7409 12:17:32.576128 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7410 12:17:32.579670 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7411 12:17:32.582851 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7412 12:17:32.586109 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7413 12:17:32.586223
7414 12:17:32.586290
7415 12:17:32.586355 ==
7416 12:17:32.589411 Dram Type= 6, Freq= 0, CH_0, rank 0
7417 12:17:32.592760 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7418 12:17:32.592842 ==
7419 12:17:32.592908
7420 12:17:32.592969
7421 12:17:32.596554 TX Vref Scan disable
7422 12:17:32.599248 == TX Byte 0 ==
7423 12:17:32.602549 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7424 12:17:32.605944 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7425 12:17:32.609668 == TX Byte 1 ==
7426 12:17:32.612715 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7427 12:17:32.615933 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7428 12:17:32.616015 ==
7429 12:17:32.619168 Dram Type= 6, Freq= 0, CH_0, rank 0
7430 12:17:32.626138 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7431 12:17:32.626221 ==
7432 12:17:32.637346
7433 12:17:32.640657 TX Vref early break, caculate TX vref
7434 12:17:32.644341 TX Vref=16, minBit 10, minWin=21, winSum=366
7435 12:17:32.647496 TX Vref=18, minBit 8, minWin=22, winSum=379
7436 12:17:32.651281 TX Vref=20, minBit 8, minWin=23, winSum=387
7437 12:17:32.654022 TX Vref=22, minBit 9, minWin=23, winSum=394
7438 12:17:32.657716 TX Vref=24, minBit 11, minWin=24, winSum=403
7439 12:17:32.664030 TX Vref=26, minBit 8, minWin=25, winSum=415
7440 12:17:32.667503 TX Vref=28, minBit 3, minWin=25, winSum=415
7441 12:17:32.670776 TX Vref=30, minBit 0, minWin=25, winSum=411
7442 12:17:32.674086 TX Vref=32, minBit 8, minWin=24, winSum=400
7443 12:17:32.677159 TX Vref=34, minBit 1, minWin=24, winSum=393
7444 12:17:32.683777 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 26
7445 12:17:32.683861
7446 12:17:32.687039 Final TX Range 0 Vref 26
7447 12:17:32.687122
7448 12:17:32.687186 ==
7449 12:17:32.690435 Dram Type= 6, Freq= 0, CH_0, rank 0
7450 12:17:32.693956 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7451 12:17:32.694039 ==
7452 12:17:32.694104
7453 12:17:32.694164
7454 12:17:32.697304 TX Vref Scan disable
7455 12:17:32.703871 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7456 12:17:32.703954 == TX Byte 0 ==
7457 12:17:32.707096 u2DelayCellOfst[0]=10 cells (3 PI)
7458 12:17:32.710295 u2DelayCellOfst[1]=17 cells (5 PI)
7459 12:17:32.713691 u2DelayCellOfst[2]=10 cells (3 PI)
7460 12:17:32.716805 u2DelayCellOfst[3]=10 cells (3 PI)
7461 12:17:32.720321 u2DelayCellOfst[4]=7 cells (2 PI)
7462 12:17:32.723529 u2DelayCellOfst[5]=0 cells (0 PI)
7463 12:17:32.726990 u2DelayCellOfst[6]=17 cells (5 PI)
7464 12:17:32.730229 u2DelayCellOfst[7]=14 cells (4 PI)
7465 12:17:32.733724 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7466 12:17:32.737195 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7467 12:17:32.739933 == TX Byte 1 ==
7468 12:17:32.743652 u2DelayCellOfst[8]=3 cells (1 PI)
7469 12:17:32.743735 u2DelayCellOfst[9]=0 cells (0 PI)
7470 12:17:32.746693 u2DelayCellOfst[10]=10 cells (3 PI)
7471 12:17:32.750300 u2DelayCellOfst[11]=3 cells (1 PI)
7472 12:17:32.753454 u2DelayCellOfst[12]=14 cells (4 PI)
7473 12:17:32.756696 u2DelayCellOfst[13]=14 cells (4 PI)
7474 12:17:32.759980 u2DelayCellOfst[14]=17 cells (5 PI)
7475 12:17:32.763231 u2DelayCellOfst[15]=14 cells (4 PI)
7476 12:17:32.766561 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
7477 12:17:32.773400 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7478 12:17:32.773498 DramC Write-DBI on
7479 12:17:32.773566 ==
7480 12:17:32.776616 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 12:17:32.783129 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7482 12:17:32.783212 ==
7483 12:17:32.783278
7484 12:17:32.783339
7485 12:17:32.783397 TX Vref Scan disable
7486 12:17:32.787234 == TX Byte 0 ==
7487 12:17:32.790499 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7488 12:17:32.793792 == TX Byte 1 ==
7489 12:17:32.797272 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7490 12:17:32.797355 DramC Write-DBI off
7491 12:17:32.800578
7492 12:17:32.800660 [DATLAT]
7493 12:17:32.800725 Freq=1600, CH0 RK0
7494 12:17:32.800786
7495 12:17:32.803846 DATLAT Default: 0xf
7496 12:17:32.803927 0, 0xFFFF, sum = 0
7497 12:17:32.807176 1, 0xFFFF, sum = 0
7498 12:17:32.807260 2, 0xFFFF, sum = 0
7499 12:17:32.810544 3, 0xFFFF, sum = 0
7500 12:17:32.810630 4, 0xFFFF, sum = 0
7501 12:17:32.813867 5, 0xFFFF, sum = 0
7502 12:17:32.817094 6, 0xFFFF, sum = 0
7503 12:17:32.817177 7, 0xFFFF, sum = 0
7504 12:17:32.820476 8, 0xFFFF, sum = 0
7505 12:17:32.820559 9, 0xFFFF, sum = 0
7506 12:17:32.823945 10, 0xFFFF, sum = 0
7507 12:17:32.824027 11, 0xFFFF, sum = 0
7508 12:17:32.826918 12, 0xBFF, sum = 0
7509 12:17:32.827002 13, 0x0, sum = 1
7510 12:17:32.830183 14, 0x0, sum = 2
7511 12:17:32.830267 15, 0x0, sum = 3
7512 12:17:32.833832 16, 0x0, sum = 4
7513 12:17:32.833966 best_step = 14
7514 12:17:32.834061
7515 12:17:32.834137 ==
7516 12:17:32.836927 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 12:17:32.840161 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7518 12:17:32.843447 ==
7519 12:17:32.843529 RX Vref Scan: 1
7520 12:17:32.843594
7521 12:17:32.846738 Set Vref Range= 24 -> 127
7522 12:17:32.846820
7523 12:17:32.846886 RX Vref 24 -> 127, step: 1
7524 12:17:32.850213
7525 12:17:32.850295 RX Delay 11 -> 252, step: 4
7526 12:17:32.850360
7527 12:17:32.853348 Set Vref, RX VrefLevel [Byte0]: 24
7528 12:17:32.856742 [Byte1]: 24
7529 12:17:32.860458
7530 12:17:32.860540 Set Vref, RX VrefLevel [Byte0]: 25
7531 12:17:32.863656 [Byte1]: 25
7532 12:17:32.867983
7533 12:17:32.868065 Set Vref, RX VrefLevel [Byte0]: 26
7534 12:17:32.871777 [Byte1]: 26
7535 12:17:32.875600
7536 12:17:32.875681 Set Vref, RX VrefLevel [Byte0]: 27
7537 12:17:32.878837 [Byte1]: 27
7538 12:17:32.883301
7539 12:17:32.883382 Set Vref, RX VrefLevel [Byte0]: 28
7540 12:17:32.886489 [Byte1]: 28
7541 12:17:32.890899
7542 12:17:32.890981 Set Vref, RX VrefLevel [Byte0]: 29
7543 12:17:32.894137 [Byte1]: 29
7544 12:17:32.898440
7545 12:17:32.898522 Set Vref, RX VrefLevel [Byte0]: 30
7546 12:17:32.901609 [Byte1]: 30
7547 12:17:32.906028
7548 12:17:32.906109 Set Vref, RX VrefLevel [Byte0]: 31
7549 12:17:32.909217 [Byte1]: 31
7550 12:17:32.913798
7551 12:17:32.913883 Set Vref, RX VrefLevel [Byte0]: 32
7552 12:17:32.916940 [Byte1]: 32
7553 12:17:32.921384
7554 12:17:32.921466 Set Vref, RX VrefLevel [Byte0]: 33
7555 12:17:32.924537 [Byte1]: 33
7556 12:17:32.929036
7557 12:17:32.929119 Set Vref, RX VrefLevel [Byte0]: 34
7558 12:17:32.932054 [Byte1]: 34
7559 12:17:32.936572
7560 12:17:32.936653 Set Vref, RX VrefLevel [Byte0]: 35
7561 12:17:32.939661 [Byte1]: 35
7562 12:17:32.944296
7563 12:17:32.944377 Set Vref, RX VrefLevel [Byte0]: 36
7564 12:17:32.947436 [Byte1]: 36
7565 12:17:32.951927
7566 12:17:32.952008 Set Vref, RX VrefLevel [Byte0]: 37
7567 12:17:32.955159 [Byte1]: 37
7568 12:17:32.959324
7569 12:17:32.959421 Set Vref, RX VrefLevel [Byte0]: 38
7570 12:17:32.965728 [Byte1]: 38
7571 12:17:32.965811
7572 12:17:32.969058 Set Vref, RX VrefLevel [Byte0]: 39
7573 12:17:32.972337 [Byte1]: 39
7574 12:17:32.972419
7575 12:17:32.976328 Set Vref, RX VrefLevel [Byte0]: 40
7576 12:17:32.978955 [Byte1]: 40
7577 12:17:32.982163
7578 12:17:32.982249 Set Vref, RX VrefLevel [Byte0]: 41
7579 12:17:32.985839 [Byte1]: 41
7580 12:17:32.989700
7581 12:17:32.989782 Set Vref, RX VrefLevel [Byte0]: 42
7582 12:17:32.992912 [Byte1]: 42
7583 12:17:32.997397
7584 12:17:32.997478 Set Vref, RX VrefLevel [Byte0]: 43
7585 12:17:33.000577 [Byte1]: 43
7586 12:17:33.004959
7587 12:17:33.005041 Set Vref, RX VrefLevel [Byte0]: 44
7588 12:17:33.008360 [Byte1]: 44
7589 12:17:33.012618
7590 12:17:33.012702 Set Vref, RX VrefLevel [Byte0]: 45
7591 12:17:33.015955 [Byte1]: 45
7592 12:17:33.020151
7593 12:17:33.020282 Set Vref, RX VrefLevel [Byte0]: 46
7594 12:17:33.023952 [Byte1]: 46
7595 12:17:33.028060
7596 12:17:33.028171 Set Vref, RX VrefLevel [Byte0]: 47
7597 12:17:33.031007 [Byte1]: 47
7598 12:17:33.035542
7599 12:17:33.035625 Set Vref, RX VrefLevel [Byte0]: 48
7600 12:17:33.038967 [Byte1]: 48
7601 12:17:33.043315
7602 12:17:33.043398 Set Vref, RX VrefLevel [Byte0]: 49
7603 12:17:33.046502 [Byte1]: 49
7604 12:17:33.051012
7605 12:17:33.051095 Set Vref, RX VrefLevel [Byte0]: 50
7606 12:17:33.053875 [Byte1]: 50
7607 12:17:33.058343
7608 12:17:33.058426 Set Vref, RX VrefLevel [Byte0]: 51
7609 12:17:33.061616 [Byte1]: 51
7610 12:17:33.066048
7611 12:17:33.066131 Set Vref, RX VrefLevel [Byte0]: 52
7612 12:17:33.069153 [Byte1]: 52
7613 12:17:33.073739
7614 12:17:33.073823 Set Vref, RX VrefLevel [Byte0]: 53
7615 12:17:33.076658 [Byte1]: 53
7616 12:17:33.081012
7617 12:17:33.081095 Set Vref, RX VrefLevel [Byte0]: 54
7618 12:17:33.084423 [Byte1]: 54
7619 12:17:33.088778
7620 12:17:33.088861 Set Vref, RX VrefLevel [Byte0]: 55
7621 12:17:33.091976 [Byte1]: 55
7622 12:17:33.096628
7623 12:17:33.096711 Set Vref, RX VrefLevel [Byte0]: 56
7624 12:17:33.099567 [Byte1]: 56
7625 12:17:33.104094
7626 12:17:33.104186 Set Vref, RX VrefLevel [Byte0]: 57
7627 12:17:33.107260 [Byte1]: 57
7628 12:17:33.111631
7629 12:17:33.111714 Set Vref, RX VrefLevel [Byte0]: 58
7630 12:17:33.114878 [Byte1]: 58
7631 12:17:33.119177
7632 12:17:33.119258 Set Vref, RX VrefLevel [Byte0]: 59
7633 12:17:33.122834 [Byte1]: 59
7634 12:17:33.126883
7635 12:17:33.126965 Set Vref, RX VrefLevel [Byte0]: 60
7636 12:17:33.130319 [Byte1]: 60
7637 12:17:33.134302
7638 12:17:33.134384 Set Vref, RX VrefLevel [Byte0]: 61
7639 12:17:33.137618 [Byte1]: 61
7640 12:17:33.142258
7641 12:17:33.142339 Set Vref, RX VrefLevel [Byte0]: 62
7642 12:17:33.145429 [Byte1]: 62
7643 12:17:33.149875
7644 12:17:33.149956 Set Vref, RX VrefLevel [Byte0]: 63
7645 12:17:33.153197 [Byte1]: 63
7646 12:17:33.157134
7647 12:17:33.157215 Set Vref, RX VrefLevel [Byte0]: 64
7648 12:17:33.163920 [Byte1]: 64
7649 12:17:33.164003
7650 12:17:33.166987 Set Vref, RX VrefLevel [Byte0]: 65
7651 12:17:33.170371 [Byte1]: 65
7652 12:17:33.170452
7653 12:17:33.173546 Set Vref, RX VrefLevel [Byte0]: 66
7654 12:17:33.177047 [Byte1]: 66
7655 12:17:33.177130
7656 12:17:33.180303 Set Vref, RX VrefLevel [Byte0]: 67
7657 12:17:33.183619 [Byte1]: 67
7658 12:17:33.187853
7659 12:17:33.187936 Set Vref, RX VrefLevel [Byte0]: 68
7660 12:17:33.191194 [Byte1]: 68
7661 12:17:33.195456
7662 12:17:33.195538 Set Vref, RX VrefLevel [Byte0]: 69
7663 12:17:33.198441 [Byte1]: 69
7664 12:17:33.202887
7665 12:17:33.203013 Final RX Vref Byte 0 = 50 to rank0
7666 12:17:33.206158 Final RX Vref Byte 1 = 55 to rank0
7667 12:17:33.209632 Final RX Vref Byte 0 = 50 to rank1
7668 12:17:33.212956 Final RX Vref Byte 1 = 55 to rank1==
7669 12:17:33.216118 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 12:17:33.222719 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7671 12:17:33.222805 ==
7672 12:17:33.222872 DQS Delay:
7673 12:17:33.226053 DQS0 = 0, DQS1 = 0
7674 12:17:33.226137 DQM Delay:
7675 12:17:33.226204 DQM0 = 127, DQM1 = 121
7676 12:17:33.229295 DQ Delay:
7677 12:17:33.232705 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7678 12:17:33.235924 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7679 12:17:33.239401 DQ8 =110, DQ9 =106, DQ10 =122, DQ11 =112
7680 12:17:33.242608 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7681 12:17:33.242691
7682 12:17:33.242757
7683 12:17:33.242820
7684 12:17:33.245860 [DramC_TX_OE_Calibration] TA2
7685 12:17:33.249402 Original DQ_B0 (3 6) =30, OEN = 27
7686 12:17:33.252651 Original DQ_B1 (3 6) =30, OEN = 27
7687 12:17:33.256033 24, 0x0, End_B0=24 End_B1=24
7688 12:17:33.256117 25, 0x0, End_B0=25 End_B1=25
7689 12:17:33.259116 26, 0x0, End_B0=26 End_B1=26
7690 12:17:33.262672 27, 0x0, End_B0=27 End_B1=27
7691 12:17:33.266221 28, 0x0, End_B0=28 End_B1=28
7692 12:17:33.269199 29, 0x0, End_B0=29 End_B1=29
7693 12:17:33.269284 30, 0x0, End_B0=30 End_B1=30
7694 12:17:33.272687 31, 0x4141, End_B0=30 End_B1=30
7695 12:17:33.276238 Byte0 end_step=30 best_step=27
7696 12:17:33.279257 Byte1 end_step=30 best_step=27
7697 12:17:33.282528 Byte0 TX OE(2T, 0.5T) = (3, 3)
7698 12:17:33.285828 Byte1 TX OE(2T, 0.5T) = (3, 3)
7699 12:17:33.285911
7700 12:17:33.285976
7701 12:17:33.292524 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7702 12:17:33.295760 CH0 RK0: MR19=303, MR18=1A1A
7703 12:17:33.302618 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7704 12:17:33.302703
7705 12:17:33.305733 ----->DramcWriteLeveling(PI) begin...
7706 12:17:33.305818 ==
7707 12:17:33.308912 Dram Type= 6, Freq= 0, CH_0, rank 1
7708 12:17:33.312487 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7709 12:17:33.312572 ==
7710 12:17:33.315589 Write leveling (Byte 0): 30 => 30
7711 12:17:33.319043 Write leveling (Byte 1): 26 => 26
7712 12:17:33.322273 DramcWriteLeveling(PI) end<-----
7713 12:17:33.322355
7714 12:17:33.322420 ==
7715 12:17:33.325608 Dram Type= 6, Freq= 0, CH_0, rank 1
7716 12:17:33.328942 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7717 12:17:33.329024 ==
7718 12:17:33.332211 [Gating] SW mode calibration
7719 12:17:33.338692 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7720 12:17:33.345513 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7721 12:17:33.348835 0 12 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7722 12:17:33.355536 0 12 4 | B1->B0 | 2424 3434 | 1 1 | (0 0) (1 1)
7723 12:17:33.358899 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7724 12:17:33.362128 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7725 12:17:33.368631 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7726 12:17:33.371703 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7727 12:17:33.375097 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7728 12:17:33.382003 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7729 12:17:33.385018 0 13 0 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
7730 12:17:33.388302 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
7731 12:17:33.394769 0 13 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7732 12:17:33.398112 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7733 12:17:33.401397 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7734 12:17:33.408366 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7735 12:17:33.411343 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7736 12:17:33.414849 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7737 12:17:33.421436 0 14 0 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (1 1)
7738 12:17:33.424692 0 14 4 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
7739 12:17:33.428104 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7740 12:17:33.434509 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7741 12:17:33.437747 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7742 12:17:33.441177 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7743 12:17:33.444395 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7744 12:17:33.451088 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7745 12:17:33.454556 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7746 12:17:33.461071 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7747 12:17:33.464208 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7748 12:17:33.467490 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 12:17:33.473961 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 12:17:33.477582 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 12:17:33.480688 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 12:17:33.484247 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 12:17:33.490515 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 12:17:33.494116 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 12:17:33.497254 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 12:17:33.504017 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 12:17:33.507108 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 12:17:33.510632 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 12:17:33.517191 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 12:17:33.520428 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7761 12:17:33.523544 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7762 12:17:33.531034 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7763 12:17:33.533517 Total UI for P1: 0, mck2ui 16
7764 12:17:33.536855 best dqsien dly found for B0: ( 1, 0, 30)
7765 12:17:33.540622 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7766 12:17:33.543744 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7767 12:17:33.546747 Total UI for P1: 0, mck2ui 16
7768 12:17:33.550096 best dqsien dly found for B1: ( 1, 1, 6)
7769 12:17:33.553514 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7770 12:17:33.556793 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7771 12:17:33.559988
7772 12:17:33.563386 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7773 12:17:33.566749 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7774 12:17:33.570035 [Gating] SW calibration Done
7775 12:17:33.570119 ==
7776 12:17:33.573333 Dram Type= 6, Freq= 0, CH_0, rank 1
7777 12:17:33.576510 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7778 12:17:33.576593 ==
7779 12:17:33.576659 RX Vref Scan: 0
7780 12:17:33.576720
7781 12:17:33.580179 RX Vref 0 -> 0, step: 1
7782 12:17:33.580293
7783 12:17:33.583241 RX Delay 0 -> 252, step: 8
7784 12:17:33.586601 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7785 12:17:33.589824 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7786 12:17:33.596371 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7787 12:17:33.600044 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7788 12:17:33.603118 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7789 12:17:33.606339 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7790 12:17:33.609844 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7791 12:17:33.616387 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7792 12:17:33.619727 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7793 12:17:33.622791 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7794 12:17:33.626160 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7795 12:17:33.629525 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7796 12:17:33.636121 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7797 12:17:33.639390 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7798 12:17:33.642839 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7799 12:17:33.646095 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7800 12:17:33.646176 ==
7801 12:17:33.649444 Dram Type= 6, Freq= 0, CH_0, rank 1
7802 12:17:33.655827 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7803 12:17:33.655912 ==
7804 12:17:33.655977 DQS Delay:
7805 12:17:33.659231 DQS0 = 0, DQS1 = 0
7806 12:17:33.659313 DQM Delay:
7807 12:17:33.659379 DQM0 = 131, DQM1 = 124
7808 12:17:33.662445 DQ Delay:
7809 12:17:33.666085 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7810 12:17:33.669277 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7811 12:17:33.672426 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7812 12:17:33.675996 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7813 12:17:33.676078
7814 12:17:33.676142
7815 12:17:33.676262 ==
7816 12:17:33.679224 Dram Type= 6, Freq= 0, CH_0, rank 1
7817 12:17:33.685634 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7818 12:17:33.685716 ==
7819 12:17:33.685781
7820 12:17:33.685841
7821 12:17:33.685900 TX Vref Scan disable
7822 12:17:33.688939 == TX Byte 0 ==
7823 12:17:33.692185 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7824 12:17:33.698802 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7825 12:17:33.698885 == TX Byte 1 ==
7826 12:17:33.702292 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7827 12:17:33.708725 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7828 12:17:33.708808 ==
7829 12:17:33.712398 Dram Type= 6, Freq= 0, CH_0, rank 1
7830 12:17:33.715210 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7831 12:17:33.715295 ==
7832 12:17:33.729397
7833 12:17:33.732496 TX Vref early break, caculate TX vref
7834 12:17:33.735807 TX Vref=16, minBit 9, minWin=21, winSum=374
7835 12:17:33.739002 TX Vref=18, minBit 1, minWin=23, winSum=381
7836 12:17:33.742363 TX Vref=20, minBit 1, minWin=23, winSum=387
7837 12:17:33.745796 TX Vref=22, minBit 9, minWin=23, winSum=395
7838 12:17:33.749109 TX Vref=24, minBit 1, minWin=24, winSum=403
7839 12:17:33.755931 TX Vref=26, minBit 8, minWin=24, winSum=405
7840 12:17:33.758865 TX Vref=28, minBit 8, minWin=24, winSum=413
7841 12:17:33.762381 TX Vref=30, minBit 8, minWin=24, winSum=407
7842 12:17:33.765751 TX Vref=32, minBit 0, minWin=24, winSum=401
7843 12:17:33.768839 TX Vref=34, minBit 1, minWin=24, winSum=395
7844 12:17:33.772405 TX Vref=36, minBit 8, minWin=23, winSum=388
7845 12:17:33.778848 [TxChooseVref] Worse bit 8, Min win 24, Win sum 413, Final Vref 28
7846 12:17:33.778934
7847 12:17:33.782357 Final TX Range 0 Vref 28
7848 12:17:33.782441
7849 12:17:33.782507 ==
7850 12:17:33.785407 Dram Type= 6, Freq= 0, CH_0, rank 1
7851 12:17:33.788873 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7852 12:17:33.788958 ==
7853 12:17:33.789025
7854 12:17:33.789087
7855 12:17:33.791972 TX Vref Scan disable
7856 12:17:33.798596 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7857 12:17:33.798681 == TX Byte 0 ==
7858 12:17:33.801994 u2DelayCellOfst[0]=10 cells (3 PI)
7859 12:17:33.805497 u2DelayCellOfst[1]=17 cells (5 PI)
7860 12:17:33.808961 u2DelayCellOfst[2]=10 cells (3 PI)
7861 12:17:33.811980 u2DelayCellOfst[3]=10 cells (3 PI)
7862 12:17:33.815437 u2DelayCellOfst[4]=7 cells (2 PI)
7863 12:17:33.818639 u2DelayCellOfst[5]=0 cells (0 PI)
7864 12:17:33.822056 u2DelayCellOfst[6]=14 cells (4 PI)
7865 12:17:33.825335 u2DelayCellOfst[7]=17 cells (5 PI)
7866 12:17:33.828394 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7867 12:17:33.831740 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7868 12:17:33.835113 == TX Byte 1 ==
7869 12:17:33.838479 u2DelayCellOfst[8]=3 cells (1 PI)
7870 12:17:33.841945 u2DelayCellOfst[9]=0 cells (0 PI)
7871 12:17:33.845576 u2DelayCellOfst[10]=10 cells (3 PI)
7872 12:17:33.845661 u2DelayCellOfst[11]=7 cells (2 PI)
7873 12:17:33.848485 u2DelayCellOfst[12]=14 cells (4 PI)
7874 12:17:33.852019 u2DelayCellOfst[13]=14 cells (4 PI)
7875 12:17:33.855205 u2DelayCellOfst[14]=21 cells (6 PI)
7876 12:17:33.858626 u2DelayCellOfst[15]=17 cells (5 PI)
7877 12:17:33.864974 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7878 12:17:33.868465 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7879 12:17:33.868556 DramC Write-DBI on
7880 12:17:33.868622 ==
7881 12:17:33.871866 Dram Type= 6, Freq= 0, CH_0, rank 1
7882 12:17:33.878179 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7883 12:17:33.878266 ==
7884 12:17:33.878333
7885 12:17:33.878395
7886 12:17:33.878454 TX Vref Scan disable
7887 12:17:33.882654 == TX Byte 0 ==
7888 12:17:33.885798 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7889 12:17:33.889089 == TX Byte 1 ==
7890 12:17:33.892358 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7891 12:17:33.895925 DramC Write-DBI off
7892 12:17:33.896009
7893 12:17:33.896076 [DATLAT]
7894 12:17:33.896138 Freq=1600, CH0 RK1
7895 12:17:33.896216
7896 12:17:33.899200 DATLAT Default: 0xe
7897 12:17:33.899283 0, 0xFFFF, sum = 0
7898 12:17:33.902375 1, 0xFFFF, sum = 0
7899 12:17:33.905682 2, 0xFFFF, sum = 0
7900 12:17:33.905766 3, 0xFFFF, sum = 0
7901 12:17:33.908993 4, 0xFFFF, sum = 0
7902 12:17:33.909078 5, 0xFFFF, sum = 0
7903 12:17:33.912492 6, 0xFFFF, sum = 0
7904 12:17:33.912578 7, 0xFFFF, sum = 0
7905 12:17:33.915505 8, 0xFFFF, sum = 0
7906 12:17:33.915590 9, 0xFFFF, sum = 0
7907 12:17:33.919118 10, 0xFFFF, sum = 0
7908 12:17:33.919202 11, 0xFFFF, sum = 0
7909 12:17:33.922428 12, 0xCFFF, sum = 0
7910 12:17:33.922512 13, 0x0, sum = 1
7911 12:17:33.925782 14, 0x0, sum = 2
7912 12:17:33.925866 15, 0x0, sum = 3
7913 12:17:33.928818 16, 0x0, sum = 4
7914 12:17:33.928903 best_step = 14
7915 12:17:33.928970
7916 12:17:33.929032 ==
7917 12:17:33.932163 Dram Type= 6, Freq= 0, CH_0, rank 1
7918 12:17:33.935533 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7919 12:17:33.938950 ==
7920 12:17:33.939032 RX Vref Scan: 0
7921 12:17:33.939099
7922 12:17:33.942239 RX Vref 0 -> 0, step: 1
7923 12:17:33.942323
7924 12:17:33.945458 RX Delay 11 -> 252, step: 4
7925 12:17:33.948818 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7926 12:17:33.952577 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7927 12:17:33.955575 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7928 12:17:33.962128 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7929 12:17:33.965192 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
7930 12:17:33.968660 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7931 12:17:33.971965 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
7932 12:17:33.975217 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7933 12:17:33.981729 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7934 12:17:33.985025 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7935 12:17:33.988389 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7936 12:17:33.991675 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7937 12:17:33.995316 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7938 12:17:34.001887 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7939 12:17:34.005046 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
7940 12:17:34.008433 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7941 12:17:34.008516 ==
7942 12:17:34.011573 Dram Type= 6, Freq= 0, CH_0, rank 1
7943 12:17:34.015335 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7944 12:17:34.015423 ==
7945 12:17:34.018346 DQS Delay:
7946 12:17:34.018429 DQS0 = 0, DQS1 = 0
7947 12:17:34.021903 DQM Delay:
7948 12:17:34.021985 DQM0 = 128, DQM1 = 120
7949 12:17:34.025103 DQ Delay:
7950 12:17:34.028309 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
7951 12:17:34.031789 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7952 12:17:34.034976 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7953 12:17:34.038343 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
7954 12:17:34.038426
7955 12:17:34.038493
7956 12:17:34.038554
7957 12:17:34.041631 [DramC_TX_OE_Calibration] TA2
7958 12:17:34.044938 Original DQ_B0 (3 6) =30, OEN = 27
7959 12:17:34.048494 Original DQ_B1 (3 6) =30, OEN = 27
7960 12:17:34.048578 24, 0x0, End_B0=24 End_B1=24
7961 12:17:34.051592 25, 0x0, End_B0=25 End_B1=25
7962 12:17:34.054909 26, 0x0, End_B0=26 End_B1=26
7963 12:17:34.058166 27, 0x0, End_B0=27 End_B1=27
7964 12:17:34.061515 28, 0x0, End_B0=28 End_B1=28
7965 12:17:34.061599 29, 0x0, End_B0=29 End_B1=29
7966 12:17:34.064930 30, 0x0, End_B0=30 End_B1=30
7967 12:17:34.067995 31, 0x4545, End_B0=30 End_B1=30
7968 12:17:34.071349 Byte0 end_step=30 best_step=27
7969 12:17:34.074926 Byte1 end_step=30 best_step=27
7970 12:17:34.078146 Byte0 TX OE(2T, 0.5T) = (3, 3)
7971 12:17:34.078230 Byte1 TX OE(2T, 0.5T) = (3, 3)
7972 12:17:34.078296
7973 12:17:34.078358
7974 12:17:34.087939 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
7975 12:17:34.091319 CH0 RK1: MR19=303, MR18=2525
7976 12:17:34.098182 CH0_RK1: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
7977 12:17:34.098267 [RxdqsGatingPostProcess] freq 1600
7978 12:17:34.104497 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7979 12:17:34.107706 Pre-setting of DQS Precalculation
7980 12:17:34.114462 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7981 12:17:34.114554 ==
7982 12:17:34.117953 Dram Type= 6, Freq= 0, CH_1, rank 0
7983 12:17:34.121300 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7984 12:17:34.121383 ==
7985 12:17:34.127605 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7986 12:17:34.131188 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7987 12:17:34.134209 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7988 12:17:34.140698 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7989 12:17:34.148538 [CA 0] Center 41 (11~72) winsize 62
7990 12:17:34.151772 [CA 1] Center 41 (10~72) winsize 63
7991 12:17:34.155132 [CA 2] Center 37 (8~67) winsize 60
7992 12:17:34.158505 [CA 3] Center 36 (7~66) winsize 60
7993 12:17:34.161796 [CA 4] Center 34 (4~64) winsize 61
7994 12:17:34.165183 [CA 5] Center 34 (5~64) winsize 60
7995 12:17:34.165265
7996 12:17:34.168691 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7997 12:17:34.168773
7998 12:17:34.172009 [CATrainingPosCal] consider 1 rank data
7999 12:17:34.175064 u2DelayCellTimex100 = 275/100 ps
8000 12:17:34.178370 CA0 delay=41 (11~72),Diff = 7 PI (24 cell)
8001 12:17:34.185435 CA1 delay=41 (10~72),Diff = 7 PI (24 cell)
8002 12:17:34.188458 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8003 12:17:34.191848 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8004 12:17:34.194934 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8005 12:17:34.198438 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8006 12:17:34.198520
8007 12:17:34.202279 CA PerBit enable=1, Macro0, CA PI delay=34
8008 12:17:34.202361
8009 12:17:34.205173 [CBTSetCACLKResult] CA Dly = 34
8010 12:17:34.208670 CS Dly: 8 (0~39)
8011 12:17:34.211624 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8012 12:17:34.214906 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8013 12:17:34.214990 ==
8014 12:17:34.218277 Dram Type= 6, Freq= 0, CH_1, rank 1
8015 12:17:34.221588 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8016 12:17:34.225326 ==
8017 12:17:34.228512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8018 12:17:34.231436 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8019 12:17:34.238381 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8020 12:17:34.241374 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8021 12:17:34.251285 [CA 0] Center 41 (11~71) winsize 61
8022 12:17:34.254217 [CA 1] Center 41 (11~71) winsize 61
8023 12:17:34.257504 [CA 2] Center 36 (7~66) winsize 60
8024 12:17:34.260804 [CA 3] Center 36 (7~65) winsize 59
8025 12:17:34.264302 [CA 4] Center 34 (5~64) winsize 60
8026 12:17:34.267581 [CA 5] Center 34 (4~64) winsize 61
8027 12:17:34.267692
8028 12:17:34.270695 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8029 12:17:34.270776
8030 12:17:34.274085 [CATrainingPosCal] consider 2 rank data
8031 12:17:34.277306 u2DelayCellTimex100 = 275/100 ps
8032 12:17:34.284170 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8033 12:17:34.287324 CA1 delay=41 (11~71),Diff = 7 PI (24 cell)
8034 12:17:34.290714 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8035 12:17:34.294054 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8036 12:17:34.297236 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8037 12:17:34.300490 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8038 12:17:34.300572
8039 12:17:34.303933 CA PerBit enable=1, Macro0, CA PI delay=34
8040 12:17:34.304015
8041 12:17:34.307162 [CBTSetCACLKResult] CA Dly = 34
8042 12:17:34.310659 CS Dly: 9 (0~41)
8043 12:17:34.313720 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8044 12:17:34.317212 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8045 12:17:34.317295
8046 12:17:34.320466 ----->DramcWriteLeveling(PI) begin...
8047 12:17:34.320551 ==
8048 12:17:34.323931 Dram Type= 6, Freq= 0, CH_1, rank 0
8049 12:17:34.330313 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8050 12:17:34.330397 ==
8051 12:17:34.333910 Write leveling (Byte 0): 23 => 23
8052 12:17:34.333993 Write leveling (Byte 1): 21 => 21
8053 12:17:34.337109 DramcWriteLeveling(PI) end<-----
8054 12:17:34.337192
8055 12:17:34.337258 ==
8056 12:17:34.340444 Dram Type= 6, Freq= 0, CH_1, rank 0
8057 12:17:34.347180 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8058 12:17:34.347264 ==
8059 12:17:34.351125 [Gating] SW mode calibration
8060 12:17:34.357280 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8061 12:17:34.360565 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8062 12:17:34.367052 0 12 0 | B1->B0 | 2424 3434 | 1 0 | (1 1) (0 0)
8063 12:17:34.370373 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 12:17:34.373629 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 12:17:34.380308 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 12:17:34.383721 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 12:17:34.386929 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 12:17:34.393640 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8069 12:17:34.396987 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8070 12:17:34.400060 0 13 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
8071 12:17:34.407406 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8072 12:17:34.410252 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 12:17:34.413642 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 12:17:34.420365 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 12:17:34.423576 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 12:17:34.427041 0 13 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8077 12:17:34.433376 0 13 28 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8078 12:17:34.436664 0 14 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8079 12:17:34.439887 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 12:17:34.446634 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 12:17:34.449875 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 12:17:34.453358 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 12:17:34.459895 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 12:17:34.463917 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 12:17:34.466653 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 12:17:34.473306 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8087 12:17:34.476679 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8088 12:17:34.480301 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 12:17:34.483297 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 12:17:34.489657 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 12:17:34.493184 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 12:17:34.496448 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 12:17:34.502666 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:17:34.506163 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 12:17:34.509376 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 12:17:34.515974 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 12:17:34.519392 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:17:34.522597 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:17:34.529485 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:17:34.533215 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 12:17:34.536078 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8102 12:17:34.542738 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8103 12:17:34.542865 Total UI for P1: 0, mck2ui 16
8104 12:17:34.549330 best dqsien dly found for B0: ( 1, 0, 26)
8105 12:17:34.552580 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8106 12:17:34.555737 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 12:17:34.559400 Total UI for P1: 0, mck2ui 16
8108 12:17:34.562708 best dqsien dly found for B1: ( 1, 1, 0)
8109 12:17:34.566165 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8110 12:17:34.569376 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8111 12:17:34.569459
8112 12:17:34.575845 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8113 12:17:34.579053 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8114 12:17:34.579135 [Gating] SW calibration Done
8115 12:17:34.582338 ==
8116 12:17:34.582435 Dram Type= 6, Freq= 0, CH_1, rank 0
8117 12:17:34.589126 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8118 12:17:34.589209 ==
8119 12:17:34.589276 RX Vref Scan: 0
8120 12:17:34.589338
8121 12:17:34.592543 RX Vref 0 -> 0, step: 1
8122 12:17:34.592650
8123 12:17:34.595816 RX Delay 0 -> 252, step: 8
8124 12:17:34.599077 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8125 12:17:34.602314 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8126 12:17:34.605631 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8127 12:17:34.612259 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8128 12:17:34.615722 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8129 12:17:34.618928 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8130 12:17:34.622198 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8131 12:17:34.625786 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8132 12:17:34.632141 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8133 12:17:34.635712 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8134 12:17:34.638676 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8135 12:17:34.641963 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8136 12:17:34.645247 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8137 12:17:34.651842 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8138 12:17:34.655391 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8139 12:17:34.658652 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8140 12:17:34.658736 ==
8141 12:17:34.661868 Dram Type= 6, Freq= 0, CH_1, rank 0
8142 12:17:34.665235 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8143 12:17:34.668529 ==
8144 12:17:34.668613 DQS Delay:
8145 12:17:34.668680 DQS0 = 0, DQS1 = 0
8146 12:17:34.672064 DQM Delay:
8147 12:17:34.672179 DQM0 = 130, DQM1 = 125
8148 12:17:34.675116 DQ Delay:
8149 12:17:34.678254 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8150 12:17:34.681963 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8151 12:17:34.684979 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =115
8152 12:17:34.688368 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8153 12:17:34.688451
8154 12:17:34.688518
8155 12:17:34.688579 ==
8156 12:17:34.691555 Dram Type= 6, Freq= 0, CH_1, rank 0
8157 12:17:34.694908 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8158 12:17:34.694992 ==
8159 12:17:34.698454
8160 12:17:34.698537
8161 12:17:34.698603 TX Vref Scan disable
8162 12:17:34.701442 == TX Byte 0 ==
8163 12:17:34.704665 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8164 12:17:34.707957 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8165 12:17:34.711641 == TX Byte 1 ==
8166 12:17:34.714749 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8167 12:17:34.718277 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8168 12:17:34.718361 ==
8169 12:17:34.721315 Dram Type= 6, Freq= 0, CH_1, rank 0
8170 12:17:34.728046 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8171 12:17:34.728156 ==
8172 12:17:34.738147
8173 12:17:34.741793 TX Vref early break, caculate TX vref
8174 12:17:34.744752 TX Vref=16, minBit 0, minWin=21, winSum=369
8175 12:17:34.748296 TX Vref=18, minBit 3, minWin=22, winSum=381
8176 12:17:34.751479 TX Vref=20, minBit 2, minWin=23, winSum=387
8177 12:17:34.754824 TX Vref=22, minBit 3, minWin=23, winSum=397
8178 12:17:34.758405 TX Vref=24, minBit 3, minWin=23, winSum=406
8179 12:17:34.764973 TX Vref=26, minBit 0, minWin=25, winSum=418
8180 12:17:34.768281 TX Vref=28, minBit 0, minWin=25, winSum=416
8181 12:17:34.771331 TX Vref=30, minBit 3, minWin=23, winSum=406
8182 12:17:34.774929 TX Vref=32, minBit 0, minWin=23, winSum=395
8183 12:17:34.781337 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8184 12:17:34.781424
8185 12:17:34.784591 Final TX Range 0 Vref 26
8186 12:17:34.784675
8187 12:17:34.784742 ==
8188 12:17:34.788047 Dram Type= 6, Freq= 0, CH_1, rank 0
8189 12:17:34.791410 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8190 12:17:34.791494 ==
8191 12:17:34.791561
8192 12:17:34.791623
8193 12:17:34.794830 TX Vref Scan disable
8194 12:17:34.798173 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8195 12:17:34.801374 == TX Byte 0 ==
8196 12:17:34.804481 u2DelayCellOfst[0]=17 cells (5 PI)
8197 12:17:34.808295 u2DelayCellOfst[1]=14 cells (4 PI)
8198 12:17:34.811168 u2DelayCellOfst[2]=0 cells (0 PI)
8199 12:17:34.814616 u2DelayCellOfst[3]=7 cells (2 PI)
8200 12:17:34.817831 u2DelayCellOfst[4]=10 cells (3 PI)
8201 12:17:34.817913 u2DelayCellOfst[5]=17 cells (5 PI)
8202 12:17:34.821071 u2DelayCellOfst[6]=17 cells (5 PI)
8203 12:17:34.824519 u2DelayCellOfst[7]=7 cells (2 PI)
8204 12:17:34.831009 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8205 12:17:34.834360 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8206 12:17:34.834441 == TX Byte 1 ==
8207 12:17:34.837511 u2DelayCellOfst[8]=0 cells (0 PI)
8208 12:17:34.840997 u2DelayCellOfst[9]=7 cells (2 PI)
8209 12:17:34.844341 u2DelayCellOfst[10]=10 cells (3 PI)
8210 12:17:34.847889 u2DelayCellOfst[11]=7 cells (2 PI)
8211 12:17:34.851105 u2DelayCellOfst[12]=17 cells (5 PI)
8212 12:17:34.854147 u2DelayCellOfst[13]=17 cells (5 PI)
8213 12:17:34.857951 u2DelayCellOfst[14]=21 cells (6 PI)
8214 12:17:34.861041 u2DelayCellOfst[15]=17 cells (5 PI)
8215 12:17:34.864362 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8216 12:17:34.867600 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8217 12:17:34.870971 DramC Write-DBI on
8218 12:17:34.871057 ==
8219 12:17:34.874481 Dram Type= 6, Freq= 0, CH_1, rank 0
8220 12:17:34.877428 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8221 12:17:34.877553 ==
8222 12:17:34.877647
8223 12:17:34.877736
8224 12:17:34.881149 TX Vref Scan disable
8225 12:17:34.884507 == TX Byte 0 ==
8226 12:17:34.887947 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8227 12:17:34.890784 == TX Byte 1 ==
8228 12:17:34.894166 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8229 12:17:34.894254 DramC Write-DBI off
8230 12:17:34.894323
8231 12:17:34.897758 [DATLAT]
8232 12:17:34.897926 Freq=1600, CH1 RK0
8233 12:17:34.898016
8234 12:17:34.901199 DATLAT Default: 0xf
8235 12:17:34.901331 0, 0xFFFF, sum = 0
8236 12:17:34.904220 1, 0xFFFF, sum = 0
8237 12:17:34.904323 2, 0xFFFF, sum = 0
8238 12:17:34.907756 3, 0xFFFF, sum = 0
8239 12:17:34.907935 4, 0xFFFF, sum = 0
8240 12:17:34.910873 5, 0xFFFF, sum = 0
8241 12:17:34.911009 6, 0xFFFF, sum = 0
8242 12:17:34.913744 7, 0xFFFF, sum = 0
8243 12:17:34.917274 8, 0xFFFF, sum = 0
8244 12:17:34.917396 9, 0xFFFF, sum = 0
8245 12:17:34.920550 10, 0xFFFF, sum = 0
8246 12:17:34.920685 11, 0xFFFF, sum = 0
8247 12:17:34.924074 12, 0xF7F, sum = 0
8248 12:17:34.924268 13, 0x0, sum = 1
8249 12:17:34.927379 14, 0x0, sum = 2
8250 12:17:34.927529 15, 0x0, sum = 3
8251 12:17:34.930507 16, 0x0, sum = 4
8252 12:17:34.930678 best_step = 14
8253 12:17:34.930852
8254 12:17:34.930983 ==
8255 12:17:34.933971 Dram Type= 6, Freq= 0, CH_1, rank 0
8256 12:17:34.937774 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8257 12:17:34.938059 ==
8258 12:17:34.940724 RX Vref Scan: 1
8259 12:17:34.940963
8260 12:17:34.944047 Set Vref Range= 24 -> 127
8261 12:17:34.944356
8262 12:17:34.944584 RX Vref 24 -> 127, step: 1
8263 12:17:34.944795
8264 12:17:34.947332 RX Delay 11 -> 252, step: 4
8265 12:17:34.947611
8266 12:17:34.951178 Set Vref, RX VrefLevel [Byte0]: 24
8267 12:17:34.954540 [Byte1]: 24
8268 12:17:34.955037
8269 12:17:34.957915 Set Vref, RX VrefLevel [Byte0]: 25
8270 12:17:34.960925 [Byte1]: 25
8271 12:17:34.965561
8272 12:17:34.966058 Set Vref, RX VrefLevel [Byte0]: 26
8273 12:17:34.968425 [Byte1]: 26
8274 12:17:34.972907
8275 12:17:34.973438 Set Vref, RX VrefLevel [Byte0]: 27
8276 12:17:34.975760 [Byte1]: 27
8277 12:17:34.980845
8278 12:17:34.981375 Set Vref, RX VrefLevel [Byte0]: 28
8279 12:17:34.983290 [Byte1]: 28
8280 12:17:34.988339
8281 12:17:34.988864 Set Vref, RX VrefLevel [Byte0]: 29
8282 12:17:34.991269 [Byte1]: 29
8283 12:17:34.996141
8284 12:17:34.996722 Set Vref, RX VrefLevel [Byte0]: 30
8285 12:17:34.999346 [Byte1]: 30
8286 12:17:35.003487
8287 12:17:35.004022 Set Vref, RX VrefLevel [Byte0]: 31
8288 12:17:35.006468 [Byte1]: 31
8289 12:17:35.010761
8290 12:17:35.014284 Set Vref, RX VrefLevel [Byte0]: 32
8291 12:17:35.014812 [Byte1]: 32
8292 12:17:35.018049
8293 12:17:35.018468 Set Vref, RX VrefLevel [Byte0]: 33
8294 12:17:35.021320 [Byte1]: 33
8295 12:17:35.025828
8296 12:17:35.026244 Set Vref, RX VrefLevel [Byte0]: 34
8297 12:17:35.029376 [Byte1]: 34
8298 12:17:35.033838
8299 12:17:35.034380 Set Vref, RX VrefLevel [Byte0]: 35
8300 12:17:35.036837 [Byte1]: 35
8301 12:17:35.041294
8302 12:17:35.041811 Set Vref, RX VrefLevel [Byte0]: 36
8303 12:17:35.044496 [Byte1]: 36
8304 12:17:35.049019
8305 12:17:35.049538 Set Vref, RX VrefLevel [Byte0]: 37
8306 12:17:35.051974 [Byte1]: 37
8307 12:17:35.056879
8308 12:17:35.057408 Set Vref, RX VrefLevel [Byte0]: 38
8309 12:17:35.059861 [Byte1]: 38
8310 12:17:35.063913
8311 12:17:35.064364 Set Vref, RX VrefLevel [Byte0]: 39
8312 12:17:35.067360 [Byte1]: 39
8313 12:17:35.071432
8314 12:17:35.071818 Set Vref, RX VrefLevel [Byte0]: 40
8315 12:17:35.074712 [Byte1]: 40
8316 12:17:35.079381
8317 12:17:35.079862 Set Vref, RX VrefLevel [Byte0]: 41
8318 12:17:35.083017 [Byte1]: 41
8319 12:17:35.087341
8320 12:17:35.087840 Set Vref, RX VrefLevel [Byte0]: 42
8321 12:17:35.090062 [Byte1]: 42
8322 12:17:35.094334
8323 12:17:35.094746 Set Vref, RX VrefLevel [Byte0]: 43
8324 12:17:35.097831 [Byte1]: 43
8325 12:17:35.102159
8326 12:17:35.102668 Set Vref, RX VrefLevel [Byte0]: 44
8327 12:17:35.105596 [Byte1]: 44
8328 12:17:35.109685
8329 12:17:35.112726 Set Vref, RX VrefLevel [Byte0]: 45
8330 12:17:35.115871 [Byte1]: 45
8331 12:17:35.116333
8332 12:17:35.119284 Set Vref, RX VrefLevel [Byte0]: 46
8333 12:17:35.122627 [Byte1]: 46
8334 12:17:35.123044
8335 12:17:35.126086 Set Vref, RX VrefLevel [Byte0]: 47
8336 12:17:35.129517 [Byte1]: 47
8337 12:17:35.130040
8338 12:17:35.133159 Set Vref, RX VrefLevel [Byte0]: 48
8339 12:17:35.135915 [Byte1]: 48
8340 12:17:35.140247
8341 12:17:35.140760 Set Vref, RX VrefLevel [Byte0]: 49
8342 12:17:35.143306 [Byte1]: 49
8343 12:17:35.148224
8344 12:17:35.148735 Set Vref, RX VrefLevel [Byte0]: 50
8345 12:17:35.151532 [Byte1]: 50
8346 12:17:35.155632
8347 12:17:35.156149 Set Vref, RX VrefLevel [Byte0]: 51
8348 12:17:35.158784 [Byte1]: 51
8349 12:17:35.163329
8350 12:17:35.163842 Set Vref, RX VrefLevel [Byte0]: 52
8351 12:17:35.166089 [Byte1]: 52
8352 12:17:35.171024
8353 12:17:35.171539 Set Vref, RX VrefLevel [Byte0]: 53
8354 12:17:35.173995 [Byte1]: 53
8355 12:17:35.178214
8356 12:17:35.178728 Set Vref, RX VrefLevel [Byte0]: 54
8357 12:17:35.181866 [Byte1]: 54
8358 12:17:35.186259
8359 12:17:35.186774 Set Vref, RX VrefLevel [Byte0]: 55
8360 12:17:35.188862 [Byte1]: 55
8361 12:17:35.193201
8362 12:17:35.193614 Set Vref, RX VrefLevel [Byte0]: 56
8363 12:17:35.196814 [Byte1]: 56
8364 12:17:35.201541
8365 12:17:35.202061 Set Vref, RX VrefLevel [Byte0]: 57
8366 12:17:35.204542 [Byte1]: 57
8367 12:17:35.208971
8368 12:17:35.209487 Set Vref, RX VrefLevel [Byte0]: 58
8369 12:17:35.212279 [Byte1]: 58
8370 12:17:35.216399
8371 12:17:35.216816 Set Vref, RX VrefLevel [Byte0]: 59
8372 12:17:35.219320 [Byte1]: 59
8373 12:17:35.224046
8374 12:17:35.224646 Set Vref, RX VrefLevel [Byte0]: 60
8375 12:17:35.227242 [Byte1]: 60
8376 12:17:35.231315
8377 12:17:35.231732 Set Vref, RX VrefLevel [Byte0]: 61
8378 12:17:35.235257 [Byte1]: 61
8379 12:17:35.239406
8380 12:17:35.239918 Set Vref, RX VrefLevel [Byte0]: 62
8381 12:17:35.242343 [Byte1]: 62
8382 12:17:35.247052
8383 12:17:35.247568 Set Vref, RX VrefLevel [Byte0]: 63
8384 12:17:35.249831 [Byte1]: 63
8385 12:17:35.254228
8386 12:17:35.254387 Set Vref, RX VrefLevel [Byte0]: 64
8387 12:17:35.257306 [Byte1]: 64
8388 12:17:35.261885
8389 12:17:35.262045 Set Vref, RX VrefLevel [Byte0]: 65
8390 12:17:35.264810 [Byte1]: 65
8391 12:17:35.269332
8392 12:17:35.269495 Set Vref, RX VrefLevel [Byte0]: 66
8393 12:17:35.272682 [Byte1]: 66
8394 12:17:35.276806
8395 12:17:35.276978 Set Vref, RX VrefLevel [Byte0]: 67
8396 12:17:35.280043 [Byte1]: 67
8397 12:17:35.284449
8398 12:17:35.284637 Set Vref, RX VrefLevel [Byte0]: 68
8399 12:17:35.287689 [Byte1]: 68
8400 12:17:35.291932
8401 12:17:35.292166 Set Vref, RX VrefLevel [Byte0]: 69
8402 12:17:35.295581 [Byte1]: 69
8403 12:17:35.300062
8404 12:17:35.300689 Set Vref, RX VrefLevel [Byte0]: 70
8405 12:17:35.303193 [Byte1]: 70
8406 12:17:35.307779
8407 12:17:35.308305 Set Vref, RX VrefLevel [Byte0]: 71
8408 12:17:35.311330 [Byte1]: 71
8409 12:17:35.315968
8410 12:17:35.316611 Set Vref, RX VrefLevel [Byte0]: 72
8411 12:17:35.318549 [Byte1]: 72
8412 12:17:35.322932
8413 12:17:35.323495 Set Vref, RX VrefLevel [Byte0]: 73
8414 12:17:35.326591 [Byte1]: 73
8415 12:17:35.330730
8416 12:17:35.331255 Set Vref, RX VrefLevel [Byte0]: 74
8417 12:17:35.333932 [Byte1]: 74
8418 12:17:35.338602
8419 12:17:35.339149 Final RX Vref Byte 0 = 59 to rank0
8420 12:17:35.341262 Final RX Vref Byte 1 = 56 to rank0
8421 12:17:35.344790 Final RX Vref Byte 0 = 59 to rank1
8422 12:17:35.347823 Final RX Vref Byte 1 = 56 to rank1==
8423 12:17:35.351206 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 12:17:35.358105 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8425 12:17:35.358646 ==
8426 12:17:35.359031 DQS Delay:
8427 12:17:35.359541 DQS0 = 0, DQS1 = 0
8428 12:17:35.361317 DQM Delay:
8429 12:17:35.361738 DQM0 = 128, DQM1 = 123
8430 12:17:35.365360 DQ Delay:
8431 12:17:35.367799 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8432 12:17:35.371102 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8433 12:17:35.374413 DQ8 =104, DQ9 =112, DQ10 =126, DQ11 =110
8434 12:17:35.377907 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =132
8435 12:17:35.378425
8436 12:17:35.378758
8437 12:17:35.379069
8438 12:17:35.380999 [DramC_TX_OE_Calibration] TA2
8439 12:17:35.384855 Original DQ_B0 (3 6) =30, OEN = 27
8440 12:17:35.388047 Original DQ_B1 (3 6) =30, OEN = 27
8441 12:17:35.391341 24, 0x0, End_B0=24 End_B1=24
8442 12:17:35.391873 25, 0x0, End_B0=25 End_B1=25
8443 12:17:35.394512 26, 0x0, End_B0=26 End_B1=26
8444 12:17:35.398134 27, 0x0, End_B0=27 End_B1=27
8445 12:17:35.401241 28, 0x0, End_B0=28 End_B1=28
8446 12:17:35.404634 29, 0x0, End_B0=29 End_B1=29
8447 12:17:35.405196 30, 0x0, End_B0=30 End_B1=30
8448 12:17:35.407842 31, 0x4141, End_B0=30 End_B1=30
8449 12:17:35.411132 Byte0 end_step=30 best_step=27
8450 12:17:35.414364 Byte1 end_step=30 best_step=27
8451 12:17:35.417581 Byte0 TX OE(2T, 0.5T) = (3, 3)
8452 12:17:35.420726 Byte1 TX OE(2T, 0.5T) = (3, 3)
8453 12:17:35.421147
8454 12:17:35.421481
8455 12:17:35.427522 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x303, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
8456 12:17:35.430944 CH1 RK0: MR19=303, MR18=2B2B
8457 12:17:35.437611 CH1_RK0: MR19=0x303, MR18=0x2B2B, DQSOSC=388, MR23=63, INC=24, DEC=16
8458 12:17:35.438134
8459 12:17:35.440885 ----->DramcWriteLeveling(PI) begin...
8460 12:17:35.441329 ==
8461 12:17:35.444135 Dram Type= 6, Freq= 0, CH_1, rank 1
8462 12:17:35.447619 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8463 12:17:35.448313 ==
8464 12:17:35.450860 Write leveling (Byte 0): 23 => 23
8465 12:17:35.454237 Write leveling (Byte 1): 20 => 20
8466 12:17:35.457662 DramcWriteLeveling(PI) end<-----
8467 12:17:35.458187
8468 12:17:35.458526 ==
8469 12:17:35.460877 Dram Type= 6, Freq= 0, CH_1, rank 1
8470 12:17:35.464338 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8471 12:17:35.464863 ==
8472 12:17:35.467401 [Gating] SW mode calibration
8473 12:17:35.474443 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8474 12:17:35.480607 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8475 12:17:35.484239 0 12 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8476 12:17:35.490933 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 12:17:35.493753 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 12:17:35.496878 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 12:17:35.504120 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 12:17:35.507063 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8481 12:17:35.510405 0 12 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8482 12:17:35.516971 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8483 12:17:35.520402 0 13 0 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
8484 12:17:35.523579 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 12:17:35.526961 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 12:17:35.533712 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 12:17:35.536697 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 12:17:35.540348 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 12:17:35.546990 0 13 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
8490 12:17:35.550070 0 13 28 | B1->B0 | 2323 4646 | 1 0 | (0 0) (0 0)
8491 12:17:35.553354 0 14 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8492 12:17:35.559885 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 12:17:35.563193 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 12:17:35.566834 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 12:17:35.573455 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 12:17:35.576706 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 12:17:35.580042 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8498 12:17:35.586519 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8499 12:17:35.590133 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8500 12:17:35.593183 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 12:17:35.600230 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 12:17:35.603287 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 12:17:35.606675 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 12:17:35.613553 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 12:17:35.616648 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 12:17:35.620347 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 12:17:35.626448 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 12:17:35.629914 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 12:17:35.632972 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 12:17:35.639871 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 12:17:35.643243 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 12:17:35.646477 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8513 12:17:35.653014 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 12:17:35.656408 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8515 12:17:35.659920 Total UI for P1: 0, mck2ui 16
8516 12:17:35.663177 best dqsien dly found for B0: ( 1, 0, 26)
8517 12:17:35.666600 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8518 12:17:35.669736 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8519 12:17:35.673229 Total UI for P1: 0, mck2ui 16
8520 12:17:35.676423 best dqsien dly found for B1: ( 1, 0, 30)
8521 12:17:35.682819 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8522 12:17:35.686593 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8523 12:17:35.687132
8524 12:17:35.689193 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8525 12:17:35.692508 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8526 12:17:35.696091 [Gating] SW calibration Done
8527 12:17:35.696653 ==
8528 12:17:35.699849 Dram Type= 6, Freq= 0, CH_1, rank 1
8529 12:17:35.702879 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8530 12:17:35.703396 ==
8531 12:17:35.706204 RX Vref Scan: 0
8532 12:17:35.706724
8533 12:17:35.707065 RX Vref 0 -> 0, step: 1
8534 12:17:35.707383
8535 12:17:35.709386 RX Delay 0 -> 252, step: 8
8536 12:17:35.713046 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8537 12:17:35.716426 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8538 12:17:35.722515 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8539 12:17:35.726144 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8540 12:17:35.729543 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8541 12:17:35.732528 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8542 12:17:35.736066 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8543 12:17:35.742678 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8544 12:17:35.746021 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8545 12:17:35.748977 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8546 12:17:35.752645 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8547 12:17:35.755846 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8548 12:17:35.762549 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8549 12:17:35.765696 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8550 12:17:35.769004 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8551 12:17:35.772288 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8552 12:17:35.775700 ==
8553 12:17:35.776319 Dram Type= 6, Freq= 0, CH_1, rank 1
8554 12:17:35.782125 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8555 12:17:35.782651 ==
8556 12:17:35.782992 DQS Delay:
8557 12:17:35.785480 DQS0 = 0, DQS1 = 0
8558 12:17:35.785898 DQM Delay:
8559 12:17:35.789039 DQM0 = 131, DQM1 = 124
8560 12:17:35.789553 DQ Delay:
8561 12:17:35.792004 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8562 12:17:35.795322 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8563 12:17:35.798843 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8564 12:17:35.802108 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8565 12:17:35.802648
8566 12:17:35.802989
8567 12:17:35.803303 ==
8568 12:17:35.805480 Dram Type= 6, Freq= 0, CH_1, rank 1
8569 12:17:35.812111 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8570 12:17:35.812683 ==
8571 12:17:35.813029
8572 12:17:35.813347
8573 12:17:35.813648 TX Vref Scan disable
8574 12:17:35.815272 == TX Byte 0 ==
8575 12:17:35.818598 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8576 12:17:35.825516 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8577 12:17:35.826038 == TX Byte 1 ==
8578 12:17:35.828810 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8579 12:17:35.835532 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8580 12:17:35.836049 ==
8581 12:17:35.838759 Dram Type= 6, Freq= 0, CH_1, rank 1
8582 12:17:35.842232 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8583 12:17:35.842756 ==
8584 12:17:35.855458
8585 12:17:35.858816 TX Vref early break, caculate TX vref
8586 12:17:35.861777 TX Vref=16, minBit 1, minWin=22, winSum=383
8587 12:17:35.865232 TX Vref=18, minBit 0, minWin=22, winSum=386
8588 12:17:35.869035 TX Vref=20, minBit 0, minWin=23, winSum=395
8589 12:17:35.871899 TX Vref=22, minBit 5, minWin=23, winSum=403
8590 12:17:35.875248 TX Vref=24, minBit 0, minWin=23, winSum=410
8591 12:17:35.882254 TX Vref=26, minBit 0, minWin=24, winSum=418
8592 12:17:35.885065 TX Vref=28, minBit 0, minWin=24, winSum=418
8593 12:17:35.888335 TX Vref=30, minBit 0, minWin=23, winSum=414
8594 12:17:35.891641 TX Vref=32, minBit 0, minWin=23, winSum=404
8595 12:17:35.894997 TX Vref=34, minBit 0, minWin=22, winSum=398
8596 12:17:35.898599 TX Vref=36, minBit 0, minWin=22, winSum=395
8597 12:17:35.905137 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 26
8598 12:17:35.905657
8599 12:17:35.908512 Final TX Range 0 Vref 26
8600 12:17:35.909028
8601 12:17:35.909369 ==
8602 12:17:35.912292 Dram Type= 6, Freq= 0, CH_1, rank 1
8603 12:17:35.915196 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8604 12:17:35.915727 ==
8605 12:17:35.916069
8606 12:17:35.916442
8607 12:17:35.918050 TX Vref Scan disable
8608 12:17:35.924709 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8609 12:17:35.925226 == TX Byte 0 ==
8610 12:17:35.928488 u2DelayCellOfst[0]=14 cells (4 PI)
8611 12:17:35.931650 u2DelayCellOfst[1]=7 cells (2 PI)
8612 12:17:35.935537 u2DelayCellOfst[2]=0 cells (0 PI)
8613 12:17:35.938225 u2DelayCellOfst[3]=7 cells (2 PI)
8614 12:17:35.941379 u2DelayCellOfst[4]=7 cells (2 PI)
8615 12:17:35.944801 u2DelayCellOfst[5]=14 cells (4 PI)
8616 12:17:35.948522 u2DelayCellOfst[6]=14 cells (4 PI)
8617 12:17:35.951529 u2DelayCellOfst[7]=3 cells (1 PI)
8618 12:17:35.954857 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8619 12:17:35.958082 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8620 12:17:35.961381 == TX Byte 1 ==
8621 12:17:35.964736 u2DelayCellOfst[8]=0 cells (0 PI)
8622 12:17:35.965256 u2DelayCellOfst[9]=3 cells (1 PI)
8623 12:17:35.968024 u2DelayCellOfst[10]=10 cells (3 PI)
8624 12:17:35.971450 u2DelayCellOfst[11]=3 cells (1 PI)
8625 12:17:35.974500 u2DelayCellOfst[12]=14 cells (4 PI)
8626 12:17:35.977865 u2DelayCellOfst[13]=17 cells (5 PI)
8627 12:17:35.981321 u2DelayCellOfst[14]=17 cells (5 PI)
8628 12:17:35.984610 u2DelayCellOfst[15]=14 cells (4 PI)
8629 12:17:35.987760 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8630 12:17:35.994476 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8631 12:17:35.994989 DramC Write-DBI on
8632 12:17:35.995330 ==
8633 12:17:35.997858 Dram Type= 6, Freq= 0, CH_1, rank 1
8634 12:17:36.004581 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8635 12:17:36.005114 ==
8636 12:17:36.005456
8637 12:17:36.005767
8638 12:17:36.006065 TX Vref Scan disable
8639 12:17:36.008409 == TX Byte 0 ==
8640 12:17:36.011724 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8641 12:17:36.015181 == TX Byte 1 ==
8642 12:17:36.018420 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8643 12:17:36.021693 DramC Write-DBI off
8644 12:17:36.022115
8645 12:17:36.022450 [DATLAT]
8646 12:17:36.022764 Freq=1600, CH1 RK1
8647 12:17:36.023067
8648 12:17:36.024856 DATLAT Default: 0xe
8649 12:17:36.028477 0, 0xFFFF, sum = 0
8650 12:17:36.029009 1, 0xFFFF, sum = 0
8651 12:17:36.031514 2, 0xFFFF, sum = 0
8652 12:17:36.032043 3, 0xFFFF, sum = 0
8653 12:17:36.034931 4, 0xFFFF, sum = 0
8654 12:17:36.035458 5, 0xFFFF, sum = 0
8655 12:17:36.038204 6, 0xFFFF, sum = 0
8656 12:17:36.038735 7, 0xFFFF, sum = 0
8657 12:17:36.041757 8, 0xFFFF, sum = 0
8658 12:17:36.042286 9, 0xFFFF, sum = 0
8659 12:17:36.044558 10, 0xFFFF, sum = 0
8660 12:17:36.044982 11, 0xFFFF, sum = 0
8661 12:17:36.047985 12, 0xF7F, sum = 0
8662 12:17:36.048554 13, 0x0, sum = 1
8663 12:17:36.051137 14, 0x0, sum = 2
8664 12:17:36.051559 15, 0x0, sum = 3
8665 12:17:36.054784 16, 0x0, sum = 4
8666 12:17:36.055334 best_step = 14
8667 12:17:36.055673
8668 12:17:36.055984 ==
8669 12:17:36.058071 Dram Type= 6, Freq= 0, CH_1, rank 1
8670 12:17:36.061103 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8671 12:17:36.064495 ==
8672 12:17:36.065015 RX Vref Scan: 0
8673 12:17:36.065401
8674 12:17:36.068079 RX Vref 0 -> 0, step: 1
8675 12:17:36.068541
8676 12:17:36.068876 RX Delay 3 -> 252, step: 4
8677 12:17:36.075554 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8678 12:17:36.078345 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8679 12:17:36.081876 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8680 12:17:36.084918 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8681 12:17:36.091334 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8682 12:17:36.094971 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8683 12:17:36.098274 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8684 12:17:36.101397 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8685 12:17:36.105133 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8686 12:17:36.111585 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8687 12:17:36.115018 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8688 12:17:36.118368 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8689 12:17:36.121466 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8690 12:17:36.124912 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8691 12:17:36.131540 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8692 12:17:36.134427 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8693 12:17:36.134819 ==
8694 12:17:36.138225 Dram Type= 6, Freq= 0, CH_1, rank 1
8695 12:17:36.141537 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8696 12:17:36.142062 ==
8697 12:17:36.144681 DQS Delay:
8698 12:17:36.145201 DQS0 = 0, DQS1 = 0
8699 12:17:36.145541 DQM Delay:
8700 12:17:36.148046 DQM0 = 127, DQM1 = 122
8701 12:17:36.148641 DQ Delay:
8702 12:17:36.151708 DQ0 =128, DQ1 =122, DQ2 =118, DQ3 =124
8703 12:17:36.154785 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8704 12:17:36.158455 DQ8 =104, DQ9 =108, DQ10 =124, DQ11 =114
8705 12:17:36.164634 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8706 12:17:36.165161
8707 12:17:36.165498
8708 12:17:36.165823
8709 12:17:36.168335 [DramC_TX_OE_Calibration] TA2
8710 12:17:36.168855 Original DQ_B0 (3 6) =30, OEN = 27
8711 12:17:36.172012 Original DQ_B1 (3 6) =30, OEN = 27
8712 12:17:36.174869 24, 0x0, End_B0=24 End_B1=24
8713 12:17:36.178242 25, 0x0, End_B0=25 End_B1=25
8714 12:17:36.181027 26, 0x0, End_B0=26 End_B1=26
8715 12:17:36.184843 27, 0x0, End_B0=27 End_B1=27
8716 12:17:36.185371 28, 0x0, End_B0=28 End_B1=28
8717 12:17:36.188316 29, 0x0, End_B0=29 End_B1=29
8718 12:17:36.191551 30, 0x0, End_B0=30 End_B1=30
8719 12:17:36.194512 31, 0x4141, End_B0=30 End_B1=30
8720 12:17:36.197659 Byte0 end_step=30 best_step=27
8721 12:17:36.198079 Byte1 end_step=30 best_step=27
8722 12:17:36.201084 Byte0 TX OE(2T, 0.5T) = (3, 3)
8723 12:17:36.204653 Byte1 TX OE(2T, 0.5T) = (3, 3)
8724 12:17:36.205182
8725 12:17:36.205540
8726 12:17:36.214612 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8727 12:17:36.215137 CH1 RK1: MR19=303, MR18=2020
8728 12:17:36.221126 CH1_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8729 12:17:36.224396 [RxdqsGatingPostProcess] freq 1600
8730 12:17:36.231426 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8731 12:17:36.234884 Pre-setting of DQS Precalculation
8732 12:17:36.237673 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8733 12:17:36.244281 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8734 12:17:36.254476 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8735 12:17:36.255005
8736 12:17:36.255353
8737 12:17:36.257965 [Calibration Summary] 3200 Mbps
8738 12:17:36.258487 CH 0, Rank 0
8739 12:17:36.260615 SW Impedance : PASS
8740 12:17:36.261045 DUTY Scan : NO K
8741 12:17:36.264662 ZQ Calibration : PASS
8742 12:17:36.267809 Jitter Meter : NO K
8743 12:17:36.268373 CBT Training : PASS
8744 12:17:36.271113 Write leveling : PASS
8745 12:17:36.274359 RX DQS gating : PASS
8746 12:17:36.274880 RX DQ/DQS(RDDQC) : PASS
8747 12:17:36.277530 TX DQ/DQS : PASS
8748 12:17:36.278057 RX DATLAT : PASS
8749 12:17:36.280761 RX DQ/DQS(Engine): PASS
8750 12:17:36.284572 TX OE : PASS
8751 12:17:36.285136 All Pass.
8752 12:17:36.285485
8753 12:17:36.285804 CH 0, Rank 1
8754 12:17:36.287172 SW Impedance : PASS
8755 12:17:36.291033 DUTY Scan : NO K
8756 12:17:36.291551 ZQ Calibration : PASS
8757 12:17:36.293808 Jitter Meter : NO K
8758 12:17:36.297176 CBT Training : PASS
8759 12:17:36.297604 Write leveling : PASS
8760 12:17:36.300683 RX DQS gating : PASS
8761 12:17:36.304044 RX DQ/DQS(RDDQC) : PASS
8762 12:17:36.304603 TX DQ/DQS : PASS
8763 12:17:36.307261 RX DATLAT : PASS
8764 12:17:36.310549 RX DQ/DQS(Engine): PASS
8765 12:17:36.311076 TX OE : PASS
8766 12:17:36.313880 All Pass.
8767 12:17:36.314305
8768 12:17:36.314646 CH 1, Rank 0
8769 12:17:36.317664 SW Impedance : PASS
8770 12:17:36.318193 DUTY Scan : NO K
8771 12:17:36.320496 ZQ Calibration : PASS
8772 12:17:36.324046 Jitter Meter : NO K
8773 12:17:36.324560 CBT Training : PASS
8774 12:17:36.327620 Write leveling : PASS
8775 12:17:36.330666 RX DQS gating : PASS
8776 12:17:36.331192 RX DQ/DQS(RDDQC) : PASS
8777 12:17:36.333968 TX DQ/DQS : PASS
8778 12:17:36.334506 RX DATLAT : PASS
8779 12:17:36.337339 RX DQ/DQS(Engine): PASS
8780 12:17:36.340660 TX OE : PASS
8781 12:17:36.341086 All Pass.
8782 12:17:36.341423
8783 12:17:36.341737 CH 1, Rank 1
8784 12:17:36.344062 SW Impedance : PASS
8785 12:17:36.347030 DUTY Scan : NO K
8786 12:17:36.347464 ZQ Calibration : PASS
8787 12:17:36.350606 Jitter Meter : NO K
8788 12:17:36.354161 CBT Training : PASS
8789 12:17:36.354690 Write leveling : PASS
8790 12:17:36.357302 RX DQS gating : PASS
8791 12:17:36.360648 RX DQ/DQS(RDDQC) : PASS
8792 12:17:36.361168 TX DQ/DQS : PASS
8793 12:17:36.363912 RX DATLAT : PASS
8794 12:17:36.367569 RX DQ/DQS(Engine): PASS
8795 12:17:36.368092 TX OE : PASS
8796 12:17:36.368506 All Pass.
8797 12:17:36.370461
8798 12:17:36.371086 DramC Write-DBI on
8799 12:17:36.374115 PER_BANK_REFRESH: Hybrid Mode
8800 12:17:36.374736 TX_TRACKING: ON
8801 12:17:36.384461 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8802 12:17:36.390772 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8803 12:17:36.400558 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8804 12:17:36.404163 [FAST_K] Save calibration result to emmc
8805 12:17:36.407356 sync common calibartion params.
8806 12:17:36.407875 sync cbt_mode0:0, 1:0
8807 12:17:36.411067 dram_init: ddr_geometry: 0
8808 12:17:36.414164 dram_init: ddr_geometry: 0
8809 12:17:36.414685 dram_init: ddr_geometry: 0
8810 12:17:36.417332 0:dram_rank_size:80000000
8811 12:17:36.420254 1:dram_rank_size:80000000
8812 12:17:36.423430 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8813 12:17:36.426944 DFS_SHUFFLE_HW_MODE: ON
8814 12:17:36.430491 dramc_set_vcore_voltage set vcore to 725000
8815 12:17:36.433830 Read voltage for 1600, 0
8816 12:17:36.434357 Vio18 = 0
8817 12:17:36.436881 Vcore = 725000
8818 12:17:36.437296 Vdram = 0
8819 12:17:36.437629 Vddq = 0
8820 12:17:36.437937 Vmddr = 0
8821 12:17:36.440136 switch to 3200 Mbps bootup
8822 12:17:36.443251 [DramcRunTimeConfig]
8823 12:17:36.443670 PHYPLL
8824 12:17:36.444002 DPM_CONTROL_AFTERK: ON
8825 12:17:36.446744 PER_BANK_REFRESH: ON
8826 12:17:36.450443 REFRESH_OVERHEAD_REDUCTION: ON
8827 12:17:36.453502 CMD_PICG_NEW_MODE: OFF
8828 12:17:36.454019 XRTWTW_NEW_MODE: ON
8829 12:17:36.456930 XRTRTR_NEW_MODE: ON
8830 12:17:36.457353 TX_TRACKING: ON
8831 12:17:36.459989 RDSEL_TRACKING: OFF
8832 12:17:36.460457 DQS Precalculation for DVFS: ON
8833 12:17:36.463573 RX_TRACKING: OFF
8834 12:17:36.463987 HW_GATING DBG: ON
8835 12:17:36.466946 ZQCS_ENABLE_LP4: ON
8836 12:17:36.470583 RX_PICG_NEW_MODE: ON
8837 12:17:36.471100 TX_PICG_NEW_MODE: ON
8838 12:17:36.473509 ENABLE_RX_DCM_DPHY: ON
8839 12:17:36.476767 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8840 12:17:36.477186 DUMMY_READ_FOR_TRACKING: OFF
8841 12:17:36.479843 !!! SPM_CONTROL_AFTERK: OFF
8842 12:17:36.483428 !!! SPM could not control APHY
8843 12:17:36.486582 IMPEDANCE_TRACKING: ON
8844 12:17:36.487004 TEMP_SENSOR: ON
8845 12:17:36.489947 HW_SAVE_FOR_SR: OFF
8846 12:17:36.493390 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8847 12:17:36.496702 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8848 12:17:36.497127 Read ODT Tracking: ON
8849 12:17:36.500115 Refresh Rate DeBounce: ON
8850 12:17:36.503435 DFS_NO_QUEUE_FLUSH: ON
8851 12:17:36.506848 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8852 12:17:36.507373 ENABLE_DFS_RUNTIME_MRW: OFF
8853 12:17:36.510032 DDR_RESERVE_NEW_MODE: ON
8854 12:17:36.513091 MR_CBT_SWITCH_FREQ: ON
8855 12:17:36.513611 =========================
8856 12:17:36.533014 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8857 12:17:36.536211 dram_init: ddr_geometry: 0
8858 12:17:36.554298 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8859 12:17:36.557721 dram_init: dram init end (result: 0)
8860 12:17:36.564266 DRAM-K: Full calibration passed in 23367 msecs
8861 12:17:36.567922 MRC: failed to locate region type 0.
8862 12:17:36.568491 DRAM rank0 size:0x80000000,
8863 12:17:36.570921 DRAM rank1 size=0x80000000
8864 12:17:36.580764 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8865 12:17:36.587232 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8866 12:17:36.594197 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8867 12:17:36.601022 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8868 12:17:36.604144 DRAM rank0 size:0x80000000,
8869 12:17:36.607314 DRAM rank1 size=0x80000000
8870 12:17:36.607732 CBMEM:
8871 12:17:36.611142 IMD: root @ 0xfffff000 254 entries.
8872 12:17:36.614427 IMD: root @ 0xffffec00 62 entries.
8873 12:17:36.617431 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8874 12:17:36.620943 WARNING: RO_VPD is uninitialized or empty.
8875 12:17:36.627594 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8876 12:17:36.633906 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8877 12:17:36.647022 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8878 12:17:36.658150 BS: romstage times (exec / console): total (unknown) / 22915 ms
8879 12:17:36.658693
8880 12:17:36.659030
8881 12:17:36.667851 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8882 12:17:36.672111 ARM64: Exception handlers installed.
8883 12:17:36.674720 ARM64: Testing exception
8884 12:17:36.678120 ARM64: Done test exception
8885 12:17:36.678645 Enumerating buses...
8886 12:17:36.681252 Show all devs... Before device enumeration.
8887 12:17:36.684530 Root Device: enabled 1
8888 12:17:36.687435 CPU_CLUSTER: 0: enabled 1
8889 12:17:36.687855 CPU: 00: enabled 1
8890 12:17:36.690768 Compare with tree...
8891 12:17:36.691186 Root Device: enabled 1
8892 12:17:36.694182 CPU_CLUSTER: 0: enabled 1
8893 12:17:36.697719 CPU: 00: enabled 1
8894 12:17:36.698136 Root Device scanning...
8895 12:17:36.701188 scan_static_bus for Root Device
8896 12:17:36.704406 CPU_CLUSTER: 0 enabled
8897 12:17:36.707530 scan_static_bus for Root Device done
8898 12:17:36.710805 scan_bus: bus Root Device finished in 8 msecs
8899 12:17:36.711228 done
8900 12:17:36.717602 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8901 12:17:36.720863 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8902 12:17:36.727501 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8903 12:17:36.730846 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8904 12:17:36.734623 Allocating resources...
8905 12:17:36.737474 Reading resources...
8906 12:17:36.740867 Root Device read_resources bus 0 link: 0
8907 12:17:36.741388 DRAM rank0 size:0x80000000,
8908 12:17:36.743812 DRAM rank1 size=0x80000000
8909 12:17:36.747417 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8910 12:17:36.751070 CPU: 00 missing read_resources
8911 12:17:36.754555 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8912 12:17:36.760453 Root Device read_resources bus 0 link: 0 done
8913 12:17:36.760928 Done reading resources.
8914 12:17:36.767361 Show resources in subtree (Root Device)...After reading.
8915 12:17:36.770396 Root Device child on link 0 CPU_CLUSTER: 0
8916 12:17:36.773888 CPU_CLUSTER: 0 child on link 0 CPU: 00
8917 12:17:36.784101 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8918 12:17:36.784671 CPU: 00
8919 12:17:36.787187 Root Device assign_resources, bus 0 link: 0
8920 12:17:36.790555 CPU_CLUSTER: 0 missing set_resources
8921 12:17:36.797062 Root Device assign_resources, bus 0 link: 0 done
8922 12:17:36.797490 Done setting resources.
8923 12:17:36.803563 Show resources in subtree (Root Device)...After assigning values.
8924 12:17:36.807290 Root Device child on link 0 CPU_CLUSTER: 0
8925 12:17:36.810456 CPU_CLUSTER: 0 child on link 0 CPU: 00
8926 12:17:36.820498 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8927 12:17:36.821033 CPU: 00
8928 12:17:36.823640 Done allocating resources.
8929 12:17:36.827260 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8930 12:17:36.830284 Enabling resources...
8931 12:17:36.830824 done.
8932 12:17:36.836668 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8933 12:17:36.837100 Initializing devices...
8934 12:17:36.840002 Root Device init
8935 12:17:36.840477 init hardware done!
8936 12:17:36.843494 0x00000018: ctrlr->caps
8937 12:17:36.846836 52.000 MHz: ctrlr->f_max
8938 12:17:36.847379 0.400 MHz: ctrlr->f_min
8939 12:17:36.850057 0x40ff8080: ctrlr->voltages
8940 12:17:36.850493 sclk: 390625
8941 12:17:36.853298 Bus Width = 1
8942 12:17:36.853842 sclk: 390625
8943 12:17:36.856536 Bus Width = 1
8944 12:17:36.856963 Early init status = 3
8945 12:17:36.863125 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8946 12:17:36.866311 in-header: 03 fc 00 00 01 00 00 00
8947 12:17:36.869829 in-data: 00
8948 12:17:36.873021 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8949 12:17:36.877859 in-header: 03 fd 00 00 00 00 00 00
8950 12:17:36.881029 in-data:
8951 12:17:36.884593 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8952 12:17:36.888593 in-header: 03 fc 00 00 01 00 00 00
8953 12:17:36.892319 in-data: 00
8954 12:17:36.895225 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8955 12:17:36.901506 in-header: 03 fd 00 00 00 00 00 00
8956 12:17:36.904646 in-data:
8957 12:17:36.908160 [SSUSB] Setting up USB HOST controller...
8958 12:17:36.911193 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8959 12:17:36.914608 [SSUSB] phy power-on done.
8960 12:17:36.917470 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8961 12:17:36.924641 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8962 12:17:36.927687 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8963 12:17:36.934506 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8964 12:17:36.941300 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8965 12:17:36.947690 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8966 12:17:36.954261 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8967 12:17:36.960661 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8968 12:17:36.964143 SPM: binary array size = 0x9dc
8969 12:17:36.967509 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8970 12:17:36.974181 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8971 12:17:36.980707 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8972 12:17:36.984635 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8973 12:17:36.990648 configure_display: Starting display init
8974 12:17:37.024474 anx7625_power_on_init: Init interface.
8975 12:17:37.027591 anx7625_disable_pd_protocol: Disabled PD feature.
8976 12:17:37.031285 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8977 12:17:37.058979 anx7625_start_dp_work: Secure OCM version=00
8978 12:17:37.062090 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8979 12:17:37.077224 sp_tx_get_edid_block: EDID Block = 1
8980 12:17:37.179593 Extracted contents:
8981 12:17:37.182744 header: 00 ff ff ff ff ff ff 00
8982 12:17:37.186194 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8983 12:17:37.189206 version: 01 04
8984 12:17:37.192671 basic params: 95 1f 11 78 0a
8985 12:17:37.195848 chroma info: 76 90 94 55 54 90 27 21 50 54
8986 12:17:37.199115 established: 00 00 00
8987 12:17:37.205885 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8988 12:17:37.209433 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8989 12:17:37.215835 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8990 12:17:37.222653 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8991 12:17:37.228886 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8992 12:17:37.232425 extensions: 00
8993 12:17:37.232989 checksum: fb
8994 12:17:37.233364
8995 12:17:37.235669 Manufacturer: IVO Model 57d Serial Number 0
8996 12:17:37.239115 Made week 0 of 2020
8997 12:17:37.239685 EDID version: 1.4
8998 12:17:37.242338 Digital display
8999 12:17:37.245811 6 bits per primary color channel
9000 12:17:37.246290 DisplayPort interface
9001 12:17:37.248671 Maximum image size: 31 cm x 17 cm
9002 12:17:37.252416 Gamma: 220%
9003 12:17:37.252985 Check DPMS levels
9004 12:17:37.255651 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9005 12:17:37.262178 First detailed timing is preferred timing
9006 12:17:37.262773 Established timings supported:
9007 12:17:37.265561 Standard timings supported:
9008 12:17:37.269163 Detailed timings
9009 12:17:37.272417 Hex of detail: 383680a07038204018303c0035ae10000019
9010 12:17:37.275769 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9011 12:17:37.282281 0780 0798 07c8 0820 hborder 0
9012 12:17:37.285618 0438 043b 0447 0458 vborder 0
9013 12:17:37.288705 -hsync -vsync
9014 12:17:37.289281 Did detailed timing
9015 12:17:37.295289 Hex of detail: 000000000000000000000000000000000000
9016 12:17:37.298606 Manufacturer-specified data, tag 0
9017 12:17:37.301928 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9018 12:17:37.305331 ASCII string: InfoVision
9019 12:17:37.308620 Hex of detail: 000000fe00523134304e574635205248200a
9020 12:17:37.311971 ASCII string: R140NWF5 RH
9021 12:17:37.312593 Checksum
9022 12:17:37.320686 Checksum: 0xfb (valid)
9023 12:17:37.321295 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9024 12:17:37.322015 DSI data_rate: 832800000 bps
9025 12:17:37.328275 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9026 12:17:37.332052 anx7625_parse_edid: pixelclock(138800).
9027 12:17:37.335105 hactive(1920), hsync(48), hfp(24), hbp(88)
9028 12:17:37.338777 vactive(1080), vsync(12), vfp(3), vbp(17)
9029 12:17:37.341741 anx7625_dsi_config: config dsi.
9030 12:17:37.348284 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9031 12:17:37.361566 anx7625_dsi_config: success to config DSI
9032 12:17:37.364679 anx7625_dp_start: MIPI phy setup OK.
9033 12:17:37.368302 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9034 12:17:37.371808 mtk_ddp_mode_set invalid vrefresh 60
9035 12:17:37.375312 main_disp_path_setup
9036 12:17:37.375880 ovl_layer_smi_id_en
9037 12:17:37.378071 ovl_layer_smi_id_en
9038 12:17:37.378539 ccorr_config
9039 12:17:37.378916 aal_config
9040 12:17:37.381410 gamma_config
9041 12:17:37.381879 postmask_config
9042 12:17:37.384870 dither_config
9043 12:17:37.387875 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9044 12:17:37.394767 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9045 12:17:37.397853 Root Device init finished in 554 msecs
9046 12:17:37.398395 CPU_CLUSTER: 0 init
9047 12:17:37.407463 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9048 12:17:37.411025 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9049 12:17:37.414565 APU_MBOX 0x190000b0 = 0x10001
9050 12:17:37.417455 APU_MBOX 0x190001b0 = 0x10001
9051 12:17:37.420972 APU_MBOX 0x190005b0 = 0x10001
9052 12:17:37.424011 APU_MBOX 0x190006b0 = 0x10001
9053 12:17:37.427234 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9054 12:17:37.440023 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9055 12:17:37.452590 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9056 12:17:37.458905 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9057 12:17:37.470799 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9058 12:17:37.479571 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9059 12:17:37.483105 CPU_CLUSTER: 0 init finished in 81 msecs
9060 12:17:37.486264 Devices initialized
9061 12:17:37.489661 Show all devs... After init.
9062 12:17:37.489745 Root Device: enabled 1
9063 12:17:37.492840 CPU_CLUSTER: 0: enabled 1
9064 12:17:37.496117 CPU: 00: enabled 1
9065 12:17:37.499529 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9066 12:17:37.502957 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9067 12:17:37.506178 ELOG: NV offset 0x57f000 size 0x1000
9068 12:17:37.513241 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9069 12:17:37.519689 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9070 12:17:37.523070 ELOG: Event(17) added with size 13 at 2023-10-27 12:17:38 UTC
9071 12:17:37.526497 out: cmd=0x121: 03 db 21 01 00 00 00 00
9072 12:17:37.530333 in-header: 03 1e 00 00 2c 00 00 00
9073 12:17:37.543474 in-data: 45 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9074 12:17:37.550218 ELOG: Event(A1) added with size 10 at 2023-10-27 12:17:38 UTC
9075 12:17:37.556809 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9076 12:17:37.563332 ELOG: Event(A0) added with size 9 at 2023-10-27 12:17:38 UTC
9077 12:17:37.566393 elog_add_boot_reason: Logged dev mode boot
9078 12:17:37.569895 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9079 12:17:37.573187 Finalize devices...
9080 12:17:37.573371 Devices finalized
9081 12:17:37.579863 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9082 12:17:37.582931 Writing coreboot table at 0xffe64000
9083 12:17:37.586341 0. 000000000010a000-0000000000113fff: RAMSTAGE
9084 12:17:37.589430 1. 0000000040000000-00000000400fffff: RAM
9085 12:17:37.596259 2. 0000000040100000-000000004032afff: RAMSTAGE
9086 12:17:37.599717 3. 000000004032b000-00000000545fffff: RAM
9087 12:17:37.602522 4. 0000000054600000-000000005465ffff: BL31
9088 12:17:37.605988 5. 0000000054660000-00000000ffe63fff: RAM
9089 12:17:37.612806 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9090 12:17:37.616480 7. 0000000100000000-000000013fffffff: RAM
9091 12:17:37.619658 Passing 5 GPIOs to payload:
9092 12:17:37.622962 NAME | PORT | POLARITY | VALUE
9093 12:17:37.626155 EC in RW | 0x000000aa | low | undefined
9094 12:17:37.632747 EC interrupt | 0x00000005 | low | undefined
9095 12:17:37.636272 TPM interrupt | 0x000000ab | high | undefined
9096 12:17:37.642890 SD card detect | 0x00000011 | high | undefined
9097 12:17:37.646086 speaker enable | 0x00000093 | high | undefined
9098 12:17:37.649597 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9099 12:17:37.652646 in-header: 03 f4 00 00 02 00 00 00
9100 12:17:37.655953 in-data: 07 00
9101 12:17:37.656428 ADC[4]: Raw value=668958 ID=5
9102 12:17:37.659192 ADC[3]: Raw value=212549 ID=1
9103 12:17:37.663037 RAM Code: 0x51
9104 12:17:37.663339 ADC[6]: Raw value=74410 ID=0
9105 12:17:37.665903 ADC[5]: Raw value=211812 ID=1
9106 12:17:37.669125 SKU Code: 0x1
9107 12:17:37.672415 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3567
9108 12:17:37.676313 coreboot table: 964 bytes.
9109 12:17:37.679326 IMD ROOT 0. 0xfffff000 0x00001000
9110 12:17:37.682551 IMD SMALL 1. 0xffffe000 0x00001000
9111 12:17:37.686074 RO MCACHE 2. 0xffffc000 0x00001104
9112 12:17:37.688893 CONSOLE 3. 0xfff7c000 0x00080000
9113 12:17:37.692419 FMAP 4. 0xfff7b000 0x00000452
9114 12:17:37.695746 TIME STAMP 5. 0xfff7a000 0x00000910
9115 12:17:37.698874 VBOOT WORK 6. 0xfff66000 0x00014000
9116 12:17:37.702666 RAMOOPS 7. 0xffe66000 0x00100000
9117 12:17:37.706423 COREBOOT 8. 0xffe64000 0x00002000
9118 12:17:37.706882 IMD small region:
9119 12:17:37.709473 IMD ROOT 0. 0xffffec00 0x00000400
9120 12:17:37.712804 VPD 1. 0xffffeb80 0x0000006c
9121 12:17:37.719317 MMC STATUS 2. 0xffffeb60 0x00000004
9122 12:17:37.722822 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9123 12:17:37.725878 Probing TPM: done!
9124 12:17:37.729427 Connected to device vid:did:rid of 1ae0:0028:00
9125 12:17:37.739441 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9126 12:17:37.742426 Initialized TPM device CR50 revision 0
9127 12:17:37.746389 Checking cr50 for pending updates
9128 12:17:37.749955 Reading cr50 TPM mode
9129 12:17:37.758440 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9130 12:17:37.765173 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9131 12:17:37.805206 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9132 12:17:37.808727 Checking segment from ROM address 0x40100000
9133 12:17:37.812049 Checking segment from ROM address 0x4010001c
9134 12:17:37.818589 Loading segment from ROM address 0x40100000
9135 12:17:37.819154 code (compression=0)
9136 12:17:37.828666 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9137 12:17:37.835315 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9138 12:17:37.835883 it's not compressed!
9139 12:17:37.841883 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9140 12:17:37.848581 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9141 12:17:37.865870 Loading segment from ROM address 0x4010001c
9142 12:17:37.866430 Entry Point 0x80000000
9143 12:17:37.868988 Loaded segments
9144 12:17:37.872388 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9145 12:17:37.878932 Jumping to boot code at 0x80000000(0xffe64000)
9146 12:17:37.886064 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9147 12:17:37.892278 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9148 12:17:37.900300 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9149 12:17:37.903726 Checking segment from ROM address 0x40100000
9150 12:17:37.906711 Checking segment from ROM address 0x4010001c
9151 12:17:37.913595 Loading segment from ROM address 0x40100000
9152 12:17:37.914178 code (compression=1)
9153 12:17:37.920036 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9154 12:17:37.929914 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9155 12:17:37.930551 using LZMA
9156 12:17:37.938478 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9157 12:17:37.944997 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9158 12:17:37.948644 Loading segment from ROM address 0x4010001c
9159 12:17:37.949228 Entry Point 0x54601000
9160 12:17:37.951674 Loaded segments
9161 12:17:37.955113 NOTICE: MT8192 bl31_setup
9162 12:17:37.962318 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9163 12:17:37.965553 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9164 12:17:37.968851 WARNING: region 0:
9165 12:17:37.971961 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9166 12:17:37.972593 WARNING: region 1:
9167 12:17:37.978996 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9168 12:17:37.981844 WARNING: region 2:
9169 12:17:37.985147 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9170 12:17:37.988545 WARNING: region 3:
9171 12:17:37.991815 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9172 12:17:37.995558 WARNING: region 4:
9173 12:17:38.002123 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9174 12:17:38.002687 WARNING: region 5:
9175 12:17:38.005162 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9176 12:17:38.008712 WARNING: region 6:
9177 12:17:38.012128 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9178 12:17:38.015488 WARNING: region 7:
9179 12:17:38.018653 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 12:17:38.025475 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9181 12:17:38.028830 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9182 12:17:38.031720 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9183 12:17:38.038711 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9184 12:17:38.042272 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9185 12:17:38.045241 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9186 12:17:38.051970 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9187 12:17:38.055553 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9188 12:17:38.062263 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9189 12:17:38.065184 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9190 12:17:38.068772 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9191 12:17:38.075194 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9192 12:17:38.078333 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9193 12:17:38.081498 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9194 12:17:38.088363 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9195 12:17:38.091757 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9196 12:17:38.098329 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9197 12:17:38.101556 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9198 12:17:38.104865 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9199 12:17:38.111924 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9200 12:17:38.115013 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9201 12:17:38.118772 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9202 12:17:38.125215 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9203 12:17:38.128867 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9204 12:17:38.135240 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9205 12:17:38.138159 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9206 12:17:38.141666 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9207 12:17:38.148565 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9208 12:17:38.152085 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9209 12:17:38.158744 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9210 12:17:38.161829 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9211 12:17:38.165346 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9212 12:17:38.172288 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9213 12:17:38.175304 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9214 12:17:38.178648 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9215 12:17:38.182154 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9216 12:17:38.188711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9217 12:17:38.191963 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9218 12:17:38.195443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9219 12:17:38.198600 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9220 12:17:38.201773 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9221 12:17:38.208772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9222 12:17:38.212132 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9223 12:17:38.215340 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9224 12:17:38.222375 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9225 12:17:38.225138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9226 12:17:38.228826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9227 12:17:38.232146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9228 12:17:38.238780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9229 12:17:38.242095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9230 12:17:38.248384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9231 12:17:38.252284 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9232 12:17:38.255347 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9233 12:17:38.262308 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9234 12:17:38.265288 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9235 12:17:38.272381 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9236 12:17:38.275180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9237 12:17:38.282008 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9238 12:17:38.284903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9239 12:17:38.288666 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9240 12:17:38.295348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9241 12:17:38.298220 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9242 12:17:38.305116 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9243 12:17:38.308244 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9244 12:17:38.315343 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9245 12:17:38.318444 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9246 12:17:38.325141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9247 12:17:38.328438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9248 12:17:38.332002 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9249 12:17:38.338581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9250 12:17:38.341685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9251 12:17:38.348423 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9252 12:17:38.351677 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9253 12:17:38.358386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9254 12:17:38.361940 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9255 12:17:38.365627 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9256 12:17:38.371953 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9257 12:17:38.375439 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9258 12:17:38.381982 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9259 12:17:38.385348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9260 12:17:38.391896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9261 12:17:38.395021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9262 12:17:38.398438 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9263 12:17:38.405410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9264 12:17:38.408790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9265 12:17:38.414880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9266 12:17:38.418453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9267 12:17:38.425069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9268 12:17:38.428304 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9269 12:17:38.431619 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9270 12:17:38.438724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9271 12:17:38.441786 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9272 12:17:38.448570 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9273 12:17:38.451596 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9274 12:17:38.458378 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9275 12:17:38.461968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9276 12:17:38.465121 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9277 12:17:38.471869 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9278 12:17:38.474840 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9279 12:17:38.478053 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9280 12:17:38.481584 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9281 12:17:38.488539 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9282 12:17:38.491384 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9283 12:17:38.498115 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9284 12:17:38.501285 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9285 12:17:38.504847 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9286 12:17:38.511603 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9287 12:17:38.514569 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9288 12:17:38.521819 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9289 12:17:38.525127 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9290 12:17:38.528227 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9291 12:17:38.534946 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9292 12:17:38.538260 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9293 12:17:38.544764 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9294 12:17:38.548329 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9295 12:17:38.551533 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9296 12:17:38.554919 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9297 12:17:38.561625 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9298 12:17:38.564811 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9299 12:17:38.568142 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9300 12:17:38.575033 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9301 12:17:38.578044 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9302 12:17:38.581718 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9303 12:17:38.584689 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9304 12:17:38.591440 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9305 12:17:38.594914 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9306 12:17:38.601472 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9307 12:17:38.604873 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9308 12:17:38.608257 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9309 12:17:38.614606 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9310 12:17:38.617901 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9311 12:17:38.624675 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9312 12:17:38.627816 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9313 12:17:38.631661 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9314 12:17:38.638417 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9315 12:17:38.641233 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9316 12:17:38.648348 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9317 12:17:38.651190 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9318 12:17:38.654670 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9319 12:17:38.661698 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9320 12:17:38.664374 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9321 12:17:38.668030 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9322 12:17:38.674676 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9323 12:17:38.677731 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9324 12:17:38.684715 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9325 12:17:38.687956 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9326 12:17:38.691036 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9327 12:17:38.697515 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9328 12:17:38.701089 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9329 12:17:38.708021 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9330 12:17:38.711014 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9331 12:17:38.714309 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9332 12:17:38.721192 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9333 12:17:38.724640 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9334 12:17:38.730967 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9335 12:17:38.734672 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9336 12:17:38.737716 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9337 12:17:38.744778 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9338 12:17:38.748316 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9339 12:17:38.751309 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9340 12:17:38.757986 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9341 12:17:38.761089 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9342 12:17:38.768018 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9343 12:17:38.771192 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9344 12:17:38.774428 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9345 12:17:38.780858 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9346 12:17:38.784408 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9347 12:17:38.791028 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9348 12:17:38.793929 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9349 12:17:38.797204 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9350 12:17:38.804245 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9351 12:17:38.807941 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9352 12:17:38.814463 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9353 12:17:38.817413 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9354 12:17:38.820590 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9355 12:17:38.827141 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9356 12:17:38.830377 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9357 12:17:38.837325 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9358 12:17:38.840233 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9359 12:17:38.844018 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9360 12:17:38.850629 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9361 12:17:38.853889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9362 12:17:38.857211 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9363 12:17:38.863915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9364 12:17:38.866759 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9365 12:17:38.874033 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9366 12:17:38.877468 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9367 12:17:38.880364 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9368 12:17:38.887296 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9369 12:17:38.890537 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9370 12:17:38.896863 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9371 12:17:38.900429 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9372 12:17:38.906959 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9373 12:17:38.910365 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9374 12:17:38.913555 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9375 12:17:38.920254 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9376 12:17:38.923605 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9377 12:17:38.930170 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9378 12:17:38.933165 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9379 12:17:38.939641 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9380 12:17:38.943235 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9381 12:17:38.946448 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9382 12:17:38.953046 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9383 12:17:38.956780 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9384 12:17:38.963365 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9385 12:17:38.966463 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9386 12:17:38.969872 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9387 12:17:38.976552 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9388 12:17:38.979916 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9389 12:17:38.986459 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9390 12:17:38.989808 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9391 12:17:38.996356 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9392 12:17:38.999714 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9393 12:17:39.002940 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9394 12:17:39.009704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9395 12:17:39.013075 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9396 12:17:39.019490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9397 12:17:39.022736 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9398 12:17:39.029143 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9399 12:17:39.032289 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9400 12:17:39.036376 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9401 12:17:39.042466 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9402 12:17:39.045783 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9403 12:17:39.052367 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9404 12:17:39.056043 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9405 12:17:39.059185 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9406 12:17:39.065739 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9407 12:17:39.069169 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9408 12:17:39.075827 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9409 12:17:39.079183 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9410 12:17:39.082077 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9411 12:17:39.085702 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9412 12:17:39.092346 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9413 12:17:39.095788 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9414 12:17:39.098740 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9415 12:17:39.105467 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9416 12:17:39.108831 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9417 12:17:39.111952 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9418 12:17:39.118995 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9419 12:17:39.122260 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9420 12:17:39.125142 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9421 12:17:39.132043 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9422 12:17:39.135428 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9423 12:17:39.138639 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9424 12:17:39.145302 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9425 12:17:39.148589 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9426 12:17:39.155619 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9427 12:17:39.158646 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9428 12:17:39.162197 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9429 12:17:39.168569 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9430 12:17:39.172004 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9431 12:17:39.175466 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9432 12:17:39.181662 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9433 12:17:39.184834 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9434 12:17:39.188503 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9435 12:17:39.195310 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9436 12:17:39.198426 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9437 12:17:39.204661 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9438 12:17:39.208151 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9439 12:17:39.211776 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9440 12:17:39.218357 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9441 12:17:39.221699 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9442 12:17:39.228532 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9443 12:17:39.231489 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9444 12:17:39.234970 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9445 12:17:39.241387 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9446 12:17:39.244561 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9447 12:17:39.248535 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9448 12:17:39.255192 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9449 12:17:39.258210 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9450 12:17:39.261361 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9451 12:17:39.264798 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9452 12:17:39.271184 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9453 12:17:39.275342 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9454 12:17:39.277613 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9455 12:17:39.281117 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9456 12:17:39.287947 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9457 12:17:39.291123 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9458 12:17:39.294295 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9459 12:17:39.297587 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9460 12:17:39.304339 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9461 12:17:39.307509 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9462 12:17:39.310981 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9463 12:17:39.317543 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9464 12:17:39.321056 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9465 12:17:39.327475 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9466 12:17:39.330946 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9467 12:17:39.334087 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9468 12:17:39.340751 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9469 12:17:39.344294 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9470 12:17:39.350778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9471 12:17:39.354057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9472 12:17:39.357405 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9473 12:17:39.364427 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9474 12:17:39.367605 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9475 12:17:39.374030 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9476 12:17:39.377261 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9477 12:17:39.380744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9478 12:17:39.387223 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9479 12:17:39.390749 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9480 12:17:39.396902 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9481 12:17:39.400409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9482 12:17:39.407183 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9483 12:17:39.410800 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9484 12:17:39.413725 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9485 12:17:39.420540 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9486 12:17:39.423745 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9487 12:17:39.430280 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9488 12:17:39.433662 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9489 12:17:39.436883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9490 12:17:39.443664 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9491 12:17:39.447158 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9492 12:17:39.453577 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9493 12:17:39.456926 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9494 12:17:39.460235 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9495 12:17:39.467265 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9496 12:17:39.470566 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9497 12:17:39.476926 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9498 12:17:39.480290 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9499 12:17:39.487092 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9500 12:17:39.490234 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9501 12:17:39.493507 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9502 12:17:39.500286 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9503 12:17:39.503658 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9504 12:17:39.510588 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9505 12:17:39.513328 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9506 12:17:39.516876 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9507 12:17:39.523047 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9508 12:17:39.526695 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9509 12:17:39.533165 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9510 12:17:39.536522 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9511 12:17:39.539549 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9512 12:17:39.546545 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9513 12:17:39.549554 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9514 12:17:39.556142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9515 12:17:39.559748 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9516 12:17:39.566266 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9517 12:17:39.569660 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9518 12:17:39.573093 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9519 12:17:39.579652 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9520 12:17:39.582922 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9521 12:17:39.589409 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9522 12:17:39.592895 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9523 12:17:39.596106 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9524 12:17:39.602595 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9525 12:17:39.606167 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9526 12:17:39.612593 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9527 12:17:39.615687 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9528 12:17:39.619142 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9529 12:17:39.625578 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9530 12:17:39.628823 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9531 12:17:39.635885 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9532 12:17:39.639292 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9533 12:17:39.642054 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9534 12:17:39.648901 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9535 12:17:39.652264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9536 12:17:39.659081 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9537 12:17:39.662294 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9538 12:17:39.669559 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9539 12:17:39.672105 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9540 12:17:39.678957 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9541 12:17:39.682239 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9542 12:17:39.685506 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9543 12:17:39.692117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9544 12:17:39.695576 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9545 12:17:39.701976 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9546 12:17:39.705114 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9547 12:17:39.712345 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9548 12:17:39.715372 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9549 12:17:39.718579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9550 12:17:39.725175 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9551 12:17:39.728144 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9552 12:17:39.735140 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9553 12:17:39.738065 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9554 12:17:39.744725 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9555 12:17:39.747881 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9556 12:17:39.754885 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9557 12:17:39.758397 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9558 12:17:39.761405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9559 12:17:39.767727 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9560 12:17:39.771325 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9561 12:17:39.778276 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9562 12:17:39.781280 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9563 12:17:39.787712 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9564 12:17:39.791154 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9565 12:17:39.794463 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9566 12:17:39.800785 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9567 12:17:39.804271 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9568 12:17:39.811271 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9569 12:17:39.814493 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9570 12:17:39.821132 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9571 12:17:39.824437 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9572 12:17:39.831460 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9573 12:17:39.834462 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9574 12:17:39.837344 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9575 12:17:39.844605 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9576 12:17:39.847578 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9577 12:17:39.854350 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9578 12:17:39.857360 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9579 12:17:39.864334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9580 12:17:39.867780 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9581 12:17:39.870639 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9582 12:17:39.877942 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9583 12:17:39.880871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9584 12:17:39.887556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9585 12:17:39.890613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9586 12:17:39.897567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9587 12:17:39.900565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9588 12:17:39.907501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9589 12:17:39.910923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9590 12:17:39.917153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9591 12:17:39.920624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9592 12:17:39.927228 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9593 12:17:39.930312 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9594 12:17:39.937032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9595 12:17:39.940475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9596 12:17:39.947446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9597 12:17:39.950407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9598 12:17:39.953445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9599 12:17:39.959995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9600 12:17:39.963381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9601 12:17:39.970651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9602 12:17:39.973840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9603 12:17:39.980329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9604 12:17:39.983135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9605 12:17:39.990072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9606 12:17:39.993291 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9607 12:17:39.999915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9608 12:17:40.003321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9609 12:17:40.010088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9610 12:17:40.013130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9611 12:17:40.019915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9612 12:17:40.023627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9613 12:17:40.029873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9614 12:17:40.033482 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9615 12:17:40.036331 INFO: [APUAPC] vio 0
9616 12:17:40.039877 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9617 12:17:40.046260 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9618 12:17:40.049484 INFO: [APUAPC] D0_APC_0: 0x400510
9619 12:17:40.052838 INFO: [APUAPC] D0_APC_1: 0x0
9620 12:17:40.056017 INFO: [APUAPC] D0_APC_2: 0x1540
9621 12:17:40.056526 INFO: [APUAPC] D0_APC_3: 0x0
9622 12:17:40.059949 INFO: [APUAPC] D1_APC_0: 0xffffffff
9623 12:17:40.066387 INFO: [APUAPC] D1_APC_1: 0xffffffff
9624 12:17:40.069670 INFO: [APUAPC] D1_APC_2: 0x3fffff
9625 12:17:40.070240 INFO: [APUAPC] D1_APC_3: 0x0
9626 12:17:40.072701 INFO: [APUAPC] D2_APC_0: 0xffffffff
9627 12:17:40.076016 INFO: [APUAPC] D2_APC_1: 0xffffffff
9628 12:17:40.079403 INFO: [APUAPC] D2_APC_2: 0x3fffff
9629 12:17:40.082821 INFO: [APUAPC] D2_APC_3: 0x0
9630 12:17:40.086416 INFO: [APUAPC] D3_APC_0: 0xffffffff
9631 12:17:40.089466 INFO: [APUAPC] D3_APC_1: 0xffffffff
9632 12:17:40.092648 INFO: [APUAPC] D3_APC_2: 0x3fffff
9633 12:17:40.096303 INFO: [APUAPC] D3_APC_3: 0x0
9634 12:17:40.099057 INFO: [APUAPC] D4_APC_0: 0xffffffff
9635 12:17:40.102449 INFO: [APUAPC] D4_APC_1: 0xffffffff
9636 12:17:40.105924 INFO: [APUAPC] D4_APC_2: 0x3fffff
9637 12:17:40.109249 INFO: [APUAPC] D4_APC_3: 0x0
9638 12:17:40.112899 INFO: [APUAPC] D5_APC_0: 0xffffffff
9639 12:17:40.116456 INFO: [APUAPC] D5_APC_1: 0xffffffff
9640 12:17:40.119444 INFO: [APUAPC] D5_APC_2: 0x3fffff
9641 12:17:40.122573 INFO: [APUAPC] D5_APC_3: 0x0
9642 12:17:40.126015 INFO: [APUAPC] D6_APC_0: 0xffffffff
9643 12:17:40.129206 INFO: [APUAPC] D6_APC_1: 0xffffffff
9644 12:17:40.132733 INFO: [APUAPC] D6_APC_2: 0x3fffff
9645 12:17:40.136246 INFO: [APUAPC] D6_APC_3: 0x0
9646 12:17:40.139631 INFO: [APUAPC] D7_APC_0: 0xffffffff
9647 12:17:40.142322 INFO: [APUAPC] D7_APC_1: 0xffffffff
9648 12:17:40.145694 INFO: [APUAPC] D7_APC_2: 0x3fffff
9649 12:17:40.148816 INFO: [APUAPC] D7_APC_3: 0x0
9650 12:17:40.152744 INFO: [APUAPC] D8_APC_0: 0xffffffff
9651 12:17:40.155803 INFO: [APUAPC] D8_APC_1: 0xffffffff
9652 12:17:40.158844 INFO: [APUAPC] D8_APC_2: 0x3fffff
9653 12:17:40.162331 INFO: [APUAPC] D8_APC_3: 0x0
9654 12:17:40.165678 INFO: [APUAPC] D9_APC_0: 0xffffffff
9655 12:17:40.169206 INFO: [APUAPC] D9_APC_1: 0xffffffff
9656 12:17:40.172869 INFO: [APUAPC] D9_APC_2: 0x3fffff
9657 12:17:40.175381 INFO: [APUAPC] D9_APC_3: 0x0
9658 12:17:40.178809 INFO: [APUAPC] D10_APC_0: 0xffffffff
9659 12:17:40.182101 INFO: [APUAPC] D10_APC_1: 0xffffffff
9660 12:17:40.185376 INFO: [APUAPC] D10_APC_2: 0x3fffff
9661 12:17:40.188689 INFO: [APUAPC] D10_APC_3: 0x0
9662 12:17:40.191914 INFO: [APUAPC] D11_APC_0: 0xffffffff
9663 12:17:40.195111 INFO: [APUAPC] D11_APC_1: 0xffffffff
9664 12:17:40.198772 INFO: [APUAPC] D11_APC_2: 0x3fffff
9665 12:17:40.202099 INFO: [APUAPC] D11_APC_3: 0x0
9666 12:17:40.205168 INFO: [APUAPC] D12_APC_0: 0xffffffff
9667 12:17:40.208661 INFO: [APUAPC] D12_APC_1: 0xffffffff
9668 12:17:40.211658 INFO: [APUAPC] D12_APC_2: 0x3fffff
9669 12:17:40.214952 INFO: [APUAPC] D12_APC_3: 0x0
9670 12:17:40.218782 INFO: [APUAPC] D13_APC_0: 0xffffffff
9671 12:17:40.221568 INFO: [APUAPC] D13_APC_1: 0xffffffff
9672 12:17:40.224944 INFO: [APUAPC] D13_APC_2: 0x3fffff
9673 12:17:40.228435 INFO: [APUAPC] D13_APC_3: 0x0
9674 12:17:40.231360 INFO: [APUAPC] D14_APC_0: 0xffffffff
9675 12:17:40.234704 INFO: [APUAPC] D14_APC_1: 0xffffffff
9676 12:17:40.237948 INFO: [APUAPC] D14_APC_2: 0x3fffff
9677 12:17:40.241411 INFO: [APUAPC] D14_APC_3: 0x0
9678 12:17:40.244713 INFO: [APUAPC] D15_APC_0: 0xffffffff
9679 12:17:40.248355 INFO: [APUAPC] D15_APC_1: 0xffffffff
9680 12:17:40.251459 INFO: [APUAPC] D15_APC_2: 0x3fffff
9681 12:17:40.254705 INFO: [APUAPC] D15_APC_3: 0x0
9682 12:17:40.258356 INFO: [APUAPC] APC_CON: 0x4
9683 12:17:40.261471 INFO: [NOCDAPC] D0_APC_0: 0x0
9684 12:17:40.264509 INFO: [NOCDAPC] D0_APC_1: 0x0
9685 12:17:40.267925 INFO: [NOCDAPC] D1_APC_0: 0x0
9686 12:17:40.268540 INFO: [NOCDAPC] D1_APC_1: 0xfff
9687 12:17:40.271965 INFO: [NOCDAPC] D2_APC_0: 0x0
9688 12:17:40.274906 INFO: [NOCDAPC] D2_APC_1: 0xfff
9689 12:17:40.278194 INFO: [NOCDAPC] D3_APC_0: 0x0
9690 12:17:40.281562 INFO: [NOCDAPC] D3_APC_1: 0xfff
9691 12:17:40.284771 INFO: [NOCDAPC] D4_APC_0: 0x0
9692 12:17:40.287962 INFO: [NOCDAPC] D4_APC_1: 0xfff
9693 12:17:40.291542 INFO: [NOCDAPC] D5_APC_0: 0x0
9694 12:17:40.294642 INFO: [NOCDAPC] D5_APC_1: 0xfff
9695 12:17:40.298000 INFO: [NOCDAPC] D6_APC_0: 0x0
9696 12:17:40.301631 INFO: [NOCDAPC] D6_APC_1: 0xfff
9697 12:17:40.302200 INFO: [NOCDAPC] D7_APC_0: 0x0
9698 12:17:40.304587 INFO: [NOCDAPC] D7_APC_1: 0xfff
9699 12:17:40.308303 INFO: [NOCDAPC] D8_APC_0: 0x0
9700 12:17:40.311422 INFO: [NOCDAPC] D8_APC_1: 0xfff
9701 12:17:40.314567 INFO: [NOCDAPC] D9_APC_0: 0x0
9702 12:17:40.317615 INFO: [NOCDAPC] D9_APC_1: 0xfff
9703 12:17:40.321665 INFO: [NOCDAPC] D10_APC_0: 0x0
9704 12:17:40.324822 INFO: [NOCDAPC] D10_APC_1: 0xfff
9705 12:17:40.327962 INFO: [NOCDAPC] D11_APC_0: 0x0
9706 12:17:40.331252 INFO: [NOCDAPC] D11_APC_1: 0xfff
9707 12:17:40.334778 INFO: [NOCDAPC] D12_APC_0: 0x0
9708 12:17:40.337944 INFO: [NOCDAPC] D12_APC_1: 0xfff
9709 12:17:40.338513 INFO: [NOCDAPC] D13_APC_0: 0x0
9710 12:17:40.341128 INFO: [NOCDAPC] D13_APC_1: 0xfff
9711 12:17:40.344922 INFO: [NOCDAPC] D14_APC_0: 0x0
9712 12:17:40.348024 INFO: [NOCDAPC] D14_APC_1: 0xfff
9713 12:17:40.350967 INFO: [NOCDAPC] D15_APC_0: 0x0
9714 12:17:40.354467 INFO: [NOCDAPC] D15_APC_1: 0xfff
9715 12:17:40.358348 INFO: [NOCDAPC] APC_CON: 0x4
9716 12:17:40.361026 INFO: [APUAPC] set_apusys_apc done
9717 12:17:40.364894 INFO: [DEVAPC] devapc_init done
9718 12:17:40.368009 INFO: GICv3 without legacy support detected.
9719 12:17:40.370896 INFO: ARM GICv3 driver initialized in EL3
9720 12:17:40.377403 INFO: Maximum SPI INTID supported: 639
9721 12:17:40.380747 INFO: BL31: Initializing runtime services
9722 12:17:40.387317 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9723 12:17:40.387908 INFO: SPM: enable CPC mode
9724 12:17:40.394004 INFO: mcdi ready for mcusys-off-idle and system suspend
9725 12:17:40.397619 INFO: BL31: Preparing for EL3 exit to normal world
9726 12:17:40.400721 INFO: Entry point address = 0x80000000
9727 12:17:40.404074 INFO: SPSR = 0x8
9728 12:17:40.410058
9729 12:17:40.410615
9730 12:17:40.410984
9731 12:17:40.413333 Starting depthcharge on Spherion...
9732 12:17:40.413895
9733 12:17:40.414271 Wipe memory regions:
9734 12:17:40.414616
9735 12:17:40.417373 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9736 12:17:40.417932 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9737 12:17:40.418398 Setting prompt string to ['asurada:']
9738 12:17:40.418828 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9739 12:17:40.419538 [0x00000040000000, 0x00000054600000)
9740 12:17:40.538824
9741 12:17:40.539349 [0x00000054660000, 0x00000080000000)
9742 12:17:40.799740
9743 12:17:40.800336 [0x000000821a7280, 0x000000ffe64000)
9744 12:17:41.544416
9745 12:17:41.545155 [0x00000100000000, 0x00000140000000)
9746 12:17:41.925383
9747 12:17:41.928817 Initializing XHCI USB controller at 0x11200000.
9748 12:17:42.967142
9749 12:17:42.970206 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9750 12:17:42.970768
9751 12:17:42.971132
9752 12:17:42.971473
9753 12:17:42.972343 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9755 12:17:43.073704 asurada: tftpboot 192.168.201.1 11893107/tftp-deploy-_8h5mw6e/kernel/image.itb 11893107/tftp-deploy-_8h5mw6e/kernel/cmdline
9756 12:17:43.074354 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9757 12:17:43.074833 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9758 12:17:43.079609 tftpboot 192.168.201.1 11893107/tftp-deploy-_8h5mw6e/kernel/image.ittp-deploy-_8h5mw6e/kernel/cmdline
9759 12:17:43.080223
9760 12:17:43.080605 Waiting for link
9761 12:17:43.240049
9762 12:17:43.240667 R8152: Initializing
9763 12:17:43.241039
9764 12:17:43.243548 Version 9 (ocp_data = 6010)
9765 12:17:43.244111
9766 12:17:43.246615 R8152: Done initializing
9767 12:17:43.247177
9768 12:17:43.247556 Adding net device
9769 12:17:45.309727
9770 12:17:45.309875 done.
9771 12:17:45.309943
9772 12:17:45.310005 MAC: 00:e0:4c:68:03:bd
9773 12:17:45.310065
9774 12:17:45.313123 Sending DHCP discover... done.
9775 12:17:45.313209
9776 12:17:45.316532 Waiting for reply... done.
9777 12:17:45.316616
9778 12:17:45.319712 Sending DHCP request... done.
9779 12:17:45.319817
9780 12:17:45.319910 Waiting for reply... done.
9781 12:17:45.320009
9782 12:17:45.322911 My ip is 192.168.201.16
9783 12:17:45.323014
9784 12:17:45.326449 The DHCP server ip is 192.168.201.1
9785 12:17:45.326570
9786 12:17:45.329469 TFTP server IP predefined by user: 192.168.201.1
9787 12:17:45.329566
9788 12:17:45.335974 Bootfile predefined by user: 11893107/tftp-deploy-_8h5mw6e/kernel/image.itb
9789 12:17:45.336073
9790 12:17:45.339894 Sending tftp read request... done.
9791 12:17:45.339992
9792 12:17:45.342638 Waiting for the transfer...
9793 12:17:45.342742
9794 12:17:45.642303 00000000 ################################################################
9795 12:17:45.642448
9796 12:17:45.940640 00080000 ################################################################
9797 12:17:45.940783
9798 12:17:46.237202 00100000 ################################################################
9799 12:17:46.237345
9800 12:17:46.531125 00180000 ################################################################
9801 12:17:46.531269
9802 12:17:46.821886 00200000 ################################################################
9803 12:17:46.822033
9804 12:17:47.118156 00280000 ################################################################
9805 12:17:47.118323
9806 12:17:47.403130 00300000 ################################################################
9807 12:17:47.403288
9808 12:17:47.675475 00380000 ################################################################
9809 12:17:47.675655
9810 12:17:47.971867 00400000 ################################################################
9811 12:17:47.972007
9812 12:17:48.250986 00480000 ################################################################
9813 12:17:48.251127
9814 12:17:48.520421 00500000 ################################################################
9815 12:17:48.520579
9816 12:17:48.771518 00580000 ################################################################
9817 12:17:48.771657
9818 12:17:49.022003 00600000 ################################################################
9819 12:17:49.022143
9820 12:17:49.284386 00680000 ################################################################
9821 12:17:49.284529
9822 12:17:49.548285 00700000 ################################################################
9823 12:17:49.548428
9824 12:17:49.806945 00780000 ################################################################
9825 12:17:49.807117
9826 12:17:50.067092 00800000 ################################################################
9827 12:17:50.067228
9828 12:17:50.322710 00880000 ################################################################
9829 12:17:50.322850
9830 12:17:50.577973 00900000 ################################################################
9831 12:17:50.578121
9832 12:17:50.845160 00980000 ################################################################
9833 12:17:50.845299
9834 12:17:51.100869 00a00000 ################################################################
9835 12:17:51.100993
9836 12:17:51.350996 00a80000 ################################################################
9837 12:17:51.351132
9838 12:17:51.607730 00b00000 ################################################################
9839 12:17:51.607872
9840 12:17:51.902490 00b80000 ################################################################
9841 12:17:51.902636
9842 12:17:52.176698 00c00000 ################################################################
9843 12:17:52.176839
9844 12:17:52.434641 00c80000 ################################################################
9845 12:17:52.434781
9846 12:17:52.689807 00d00000 ################################################################
9847 12:17:52.689946
9848 12:17:52.941627 00d80000 ################################################################
9849 12:17:52.941769
9850 12:17:53.184357 00e00000 ################################################################
9851 12:17:53.184508
9852 12:17:53.452050 00e80000 ################################################################
9853 12:17:53.452252
9854 12:17:53.725940 00f00000 ################################################################
9855 12:17:53.726077
9856 12:17:53.979971 00f80000 ################################################################
9857 12:17:53.980142
9858 12:17:54.234153 01000000 ################################################################
9859 12:17:54.234308
9860 12:17:54.512299 01080000 ################################################################
9861 12:17:54.512428
9862 12:17:54.783012 01100000 ################################################################
9863 12:17:54.783138
9864 12:17:55.039563 01180000 ################################################################
9865 12:17:55.039691
9866 12:17:55.291627 01200000 ################################################################
9867 12:17:55.291761
9868 12:17:55.547327 01280000 ################################################################
9869 12:17:55.547460
9870 12:17:55.802532 01300000 ################################################################
9871 12:17:55.802658
9872 12:17:56.065567 01380000 ################################################################
9873 12:17:56.065725
9874 12:17:56.324756 01400000 ################################################################
9875 12:17:56.324886
9876 12:17:56.580382 01480000 ################################################################
9877 12:17:56.580533
9878 12:17:56.834345 01500000 ################################################################
9879 12:17:56.834479
9880 12:17:57.088623 01580000 ################################################################
9881 12:17:57.088758
9882 12:17:57.347692 01600000 ################################################################
9883 12:17:57.347832
9884 12:17:57.611214 01680000 ################################################################
9885 12:17:57.611353
9886 12:17:57.873192 01700000 ################################################################
9887 12:17:57.873329
9888 12:17:58.125512 01780000 ################################################################
9889 12:17:58.125646
9890 12:17:58.379620 01800000 ################################################################
9891 12:17:58.379757
9892 12:17:58.650436 01880000 ################################################################
9893 12:17:58.650568
9894 12:17:58.916172 01900000 ################################################################
9895 12:17:58.916327
9896 12:17:59.176866 01980000 ################################################################
9897 12:17:59.177004
9898 12:17:59.430970 01a00000 ################################################################
9899 12:17:59.431132
9900 12:17:59.690275 01a80000 ################################################################
9901 12:17:59.690434
9902 12:17:59.968237 01b00000 ################################################################
9903 12:17:59.968373
9904 12:18:00.247143 01b80000 ################################################################
9905 12:18:00.247280
9906 12:18:00.538371 01c00000 ################################################################
9907 12:18:00.538516
9908 12:18:00.837095 01c80000 ################################################################
9909 12:18:00.837229
9910 12:18:01.139079 01d00000 ################################################################
9911 12:18:01.139219
9912 12:18:01.442197 01d80000 ################################################################
9913 12:18:01.442341
9914 12:18:01.706323 01e00000 ################################################################
9915 12:18:01.706456
9916 12:18:01.955269 01e80000 ############################################################## done.
9917 12:18:01.955395
9918 12:18:01.958207 The bootfile was 32482970 bytes long.
9919 12:18:01.958296
9920 12:18:01.961635 Sending tftp read request... done.
9921 12:18:01.961762
9922 12:18:01.964772 Waiting for the transfer...
9923 12:18:01.964890
9924 12:18:01.964969 00000000 # done.
9925 12:18:01.965043
9926 12:18:01.975130 Command line loaded dynamically from TFTP file: 11893107/tftp-deploy-_8h5mw6e/kernel/cmdline
9927 12:18:01.975325
9928 12:18:01.988256 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
9929 12:18:01.988491
9930 12:18:01.988626 Loading FIT.
9931 12:18:01.988752
9932 12:18:01.991155 Image ramdisk-1 has 21385662 bytes.
9933 12:18:01.991315
9934 12:18:01.994718 Image fdt-1 has 47278 bytes.
9935 12:18:01.994893
9936 12:18:01.998327 Image kernel-1 has 11047994 bytes.
9937 12:18:01.998535
9938 12:18:02.004670 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
9939 12:18:02.005004
9940 12:18:02.024817 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
9941 12:18:02.025434
9942 12:18:02.027682 Choosing best match conf-1 for compat google,spherion.
9943 12:18:02.033016
9944 12:18:02.037536 Connected to device vid:did:rid of 1ae0:0028:00
9945 12:18:02.044338
9946 12:18:02.047658 tpm_get_response: command 0x17b, return code 0x0
9947 12:18:02.048257
9948 12:18:02.050903 ec_init: CrosEC protocol v3 supported (256, 248)
9949 12:18:02.056431
9950 12:18:02.059454 tpm_cleanup: add release locality here.
9951 12:18:02.059927
9952 12:18:02.060334 Shutting down all USB controllers.
9953 12:18:02.063035
9954 12:18:02.063498 Removing current net device
9955 12:18:02.063870
9956 12:18:02.069572 Exiting depthcharge with code 4 at timestamp: 49844245
9957 12:18:02.070161
9958 12:18:02.072769 LZMA decompressing kernel-1 to 0x821a6718
9959 12:18:02.073243
9960 12:18:02.076091 LZMA decompressing kernel-1 to 0x40000000
9961 12:18:03.463681
9962 12:18:03.464292 jumping to kernel
9963 12:18:03.466056 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
9964 12:18:03.466596 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
9965 12:18:03.467021 Setting prompt string to ['Linux version [0-9]']
9966 12:18:03.467404 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9967 12:18:03.467783 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
9968 12:18:03.514754
9969 12:18:03.518081 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
9970 12:18:03.521867 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
9971 12:18:03.522388 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
9972 12:18:03.522790 Setting prompt string to []
9973 12:18:03.523226 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
9974 12:18:03.523636 Using line separator: #'\n'#
9975 12:18:03.524025 No login prompt set.
9976 12:18:03.524523 Parsing kernel messages
9977 12:18:03.524855 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
9978 12:18:03.525425 [login-action] Waiting for messages, (timeout 00:04:03)
9979 12:18:03.540830 [ 0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023
9980 12:18:03.544419 [ 0.000000] random: crng init done
9981 12:18:03.550874 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
9982 12:18:03.554257 [ 0.000000] efi: UEFI not found.
9983 12:18:03.560972 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
9984 12:18:03.567624 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
9985 12:18:03.577728 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
9986 12:18:03.587593 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
9987 12:18:03.594233 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
9988 12:18:03.600401 [ 0.000000] printk: bootconsole [mtk8250] enabled
9989 12:18:03.606886 [ 0.000000] NUMA: No NUMA configuration found
9990 12:18:03.613576 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
9991 12:18:03.617042 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
9992 12:18:03.620289 [ 0.000000] Zone ranges:
9993 12:18:03.626850 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
9994 12:18:03.629944 [ 0.000000] DMA32 empty
9995 12:18:03.636624 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
9996 12:18:03.640084 [ 0.000000] Movable zone start for each node
9997 12:18:03.643303 [ 0.000000] Early memory node ranges
9998 12:18:03.649987 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
9999 12:18:03.656830 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10000 12:18:03.663191 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10001 12:18:03.669950 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10002 12:18:03.676454 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10003 12:18:03.683530 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10004 12:18:03.713157 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10005 12:18:03.719913 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10006 12:18:03.726540 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10007 12:18:03.729934 [ 0.000000] psci: probing for conduit method from DT.
10008 12:18:03.737146 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10009 12:18:03.740016 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10010 12:18:03.746756 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10011 12:18:03.749924 [ 0.000000] psci: SMC Calling Convention v1.2
10012 12:18:03.756723 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10013 12:18:03.760024 [ 0.000000] Detected VIPT I-cache on CPU0
10014 12:18:03.766424 [ 0.000000] CPU features: detected: GIC system register CPU interface
10015 12:18:03.772829 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10016 12:18:03.779663 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10017 12:18:03.786330 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10018 12:18:03.792704 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10019 12:18:03.802673 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10020 12:18:03.806383 [ 0.000000] alternatives: applying boot alternatives
10021 12:18:03.812815 [ 0.000000] Fallback order for Node 0: 0
10022 12:18:03.819246 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10023 12:18:03.822604 [ 0.000000] Policy zone: Normal
10024 12:18:03.835868 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10025 12:18:03.845560 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10026 12:18:03.856074 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10027 12:18:03.866059 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10028 12:18:03.872734 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10029 12:18:03.875929 <6>[ 0.000000] software IO TLB: area num 8.
10030 12:18:03.932280 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10031 12:18:04.011942 <6>[ 0.000000] Memory: 3834192K/4191232K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 324272K reserved, 32768K cma-reserved)
10032 12:18:04.018674 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10033 12:18:04.025127 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10034 12:18:04.028251 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10035 12:18:04.035123 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10036 12:18:04.041715 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10037 12:18:04.044828 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10038 12:18:04.054931 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10039 12:18:04.061979 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10040 12:18:04.068222 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10041 12:18:04.075148 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10042 12:18:04.078132 <6>[ 0.000000] GICv3: 608 SPIs implemented
10043 12:18:04.081177 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10044 12:18:04.088061 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10045 12:18:04.091301 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10046 12:18:04.098091 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10047 12:18:04.111297 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10048 12:18:04.121141 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10049 12:18:04.131602 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10050 12:18:04.138381 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10051 12:18:04.151855 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10052 12:18:04.158424 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10053 12:18:04.164884 <6>[ 0.009175] Console: colour dummy device 80x25
10054 12:18:04.174883 <6>[ 0.013899] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10055 12:18:04.181639 <6>[ 0.024340] pid_max: default: 32768 minimum: 301
10056 12:18:04.184808 <6>[ 0.029212] LSM: Security Framework initializing
10057 12:18:04.191312 <6>[ 0.034126] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10058 12:18:04.200964 <6>[ 0.041781] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10059 12:18:04.207818 <6>[ 0.051061] cblist_init_generic: Setting adjustable number of callback queues.
10060 12:18:04.214434 <6>[ 0.058503] cblist_init_generic: Setting shift to 3 and lim to 1.
10061 12:18:04.224116 <6>[ 0.064841] cblist_init_generic: Setting adjustable number of callback queues.
10062 12:18:04.230861 <6>[ 0.072268] cblist_init_generic: Setting shift to 3 and lim to 1.
10063 12:18:04.234519 <6>[ 0.078668] rcu: Hierarchical SRCU implementation.
10064 12:18:04.240710 <6>[ 0.083683] rcu: Max phase no-delay instances is 1000.
10065 12:18:04.247569 <6>[ 0.090739] EFI services will not be available.
10066 12:18:04.250686 <6>[ 0.095692] smp: Bringing up secondary CPUs ...
10067 12:18:04.258807 <6>[ 0.100738] Detected VIPT I-cache on CPU1
10068 12:18:04.265384 <6>[ 0.100804] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10069 12:18:04.272207 <6>[ 0.100835] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10070 12:18:04.275832 <6>[ 0.101167] Detected VIPT I-cache on CPU2
10071 12:18:04.282162 <6>[ 0.101216] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10072 12:18:04.292440 <6>[ 0.101232] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10073 12:18:04.295262 <6>[ 0.101491] Detected VIPT I-cache on CPU3
10074 12:18:04.301622 <6>[ 0.101536] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10075 12:18:04.308244 <6>[ 0.101550] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10076 12:18:04.311890 <6>[ 0.101853] CPU features: detected: Spectre-v4
10077 12:18:04.318004 <6>[ 0.101859] CPU features: detected: Spectre-BHB
10078 12:18:04.321308 <6>[ 0.101864] Detected PIPT I-cache on CPU4
10079 12:18:04.328294 <6>[ 0.101922] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10080 12:18:04.335059 <6>[ 0.101939] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10081 12:18:04.341150 <6>[ 0.102228] Detected PIPT I-cache on CPU5
10082 12:18:04.348168 <6>[ 0.102292] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10083 12:18:04.354838 <6>[ 0.102309] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10084 12:18:04.357810 <6>[ 0.102590] Detected PIPT I-cache on CPU6
10085 12:18:04.364530 <6>[ 0.102653] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10086 12:18:04.370867 <6>[ 0.102669] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10087 12:18:04.377676 <6>[ 0.102970] Detected PIPT I-cache on CPU7
10088 12:18:04.384541 <6>[ 0.103038] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10089 12:18:04.390899 <6>[ 0.103055] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10090 12:18:04.394158 <6>[ 0.103102] smp: Brought up 1 node, 8 CPUs
10091 12:18:04.400710 <6>[ 0.244344] SMP: Total of 8 processors activated.
10092 12:18:04.404122 <6>[ 0.249296] CPU features: detected: 32-bit EL0 Support
10093 12:18:04.413710 <6>[ 0.254659] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10094 12:18:04.420394 <6>[ 0.263514] CPU features: detected: Common not Private translations
10095 12:18:04.426998 <6>[ 0.269990] CPU features: detected: CRC32 instructions
10096 12:18:04.430189 <6>[ 0.275341] CPU features: detected: RCpc load-acquire (LDAPR)
10097 12:18:04.437278 <6>[ 0.281338] CPU features: detected: LSE atomic instructions
10098 12:18:04.443899 <6>[ 0.287121] CPU features: detected: Privileged Access Never
10099 12:18:04.450072 <6>[ 0.292901] CPU features: detected: RAS Extension Support
10100 12:18:04.457087 <6>[ 0.298544] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10101 12:18:04.460004 <6>[ 0.305807] CPU: All CPU(s) started at EL2
10102 12:18:04.466989 <6>[ 0.310123] alternatives: applying system-wide alternatives
10103 12:18:04.475815 <6>[ 0.319981] devtmpfs: initialized
10104 12:18:04.490145 <6>[ 0.328222] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10105 12:18:04.497009 <6>[ 0.338181] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10106 12:18:04.503585 <6>[ 0.346359] pinctrl core: initialized pinctrl subsystem
10107 12:18:04.507226 <6>[ 0.353169] DMI not present or invalid.
10108 12:18:04.513450 <6>[ 0.357575] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10109 12:18:04.523530 <6>[ 0.364436] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10110 12:18:04.529976 <6>[ 0.371889] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10111 12:18:04.539706 <6>[ 0.379981] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10112 12:18:04.543296 <6>[ 0.388135] audit: initializing netlink subsys (disabled)
10113 12:18:04.553027 <5>[ 0.393833] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10114 12:18:04.559572 <6>[ 0.394573] thermal_sys: Registered thermal governor 'step_wise'
10115 12:18:04.565972 <6>[ 0.401800] thermal_sys: Registered thermal governor 'power_allocator'
10116 12:18:04.569486 <6>[ 0.408056] cpuidle: using governor menu
10117 12:18:04.576520 <6>[ 0.419019] NET: Registered PF_QIPCRTR protocol family
10118 12:18:04.583072 <6>[ 0.424499] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10119 12:18:04.589040 <6>[ 0.431605] ASID allocator initialised with 32768 entries
10120 12:18:04.592418 <6>[ 0.438219] Serial: AMBA PL011 UART driver
10121 12:18:04.602954 <4>[ 0.447371] Trying to register duplicate clock ID: 134
10122 12:18:04.659459 <6>[ 0.507163] KASLR enabled
10123 12:18:04.673960 <6>[ 0.514876] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10124 12:18:04.680584 <6>[ 0.521890] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10125 12:18:04.687403 <6>[ 0.528382] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10126 12:18:04.693860 <6>[ 0.535389] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10127 12:18:04.700155 <6>[ 0.541878] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10128 12:18:04.706936 <6>[ 0.548883] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10129 12:18:04.713260 <6>[ 0.555373] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10130 12:18:04.719845 <6>[ 0.562378] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10131 12:18:04.723059 <6>[ 0.569809] ACPI: Interpreter disabled.
10132 12:18:04.732145 <6>[ 0.576315] iommu: Default domain type: Translated
10133 12:18:04.739008 <6>[ 0.581472] iommu: DMA domain TLB invalidation policy: strict mode
10134 12:18:04.741736 <5>[ 0.588138] SCSI subsystem initialized
10135 12:18:04.748410 <6>[ 0.592402] usbcore: registered new interface driver usbfs
10136 12:18:04.755213 <6>[ 0.598134] usbcore: registered new interface driver hub
10137 12:18:04.758252 <6>[ 0.603689] usbcore: registered new device driver usb
10138 12:18:04.765664 <6>[ 0.609860] pps_core: LinuxPPS API ver. 1 registered
10139 12:18:04.775867 <6>[ 0.615052] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10140 12:18:04.778933 <6>[ 0.624398] PTP clock support registered
10141 12:18:04.782511 <6>[ 0.628640] EDAC MC: Ver: 3.0.0
10142 12:18:04.789778 <6>[ 0.633854] FPGA manager framework
10143 12:18:04.796000 <6>[ 0.637531] Advanced Linux Sound Architecture Driver Initialized.
10144 12:18:04.799571 <6>[ 0.644308] vgaarb: loaded
10145 12:18:04.806276 <6>[ 0.647480] clocksource: Switched to clocksource arch_sys_counter
10146 12:18:04.809312 <5>[ 0.653937] VFS: Disk quotas dquot_6.6.0
10147 12:18:04.816522 <6>[ 0.658121] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10148 12:18:04.819159 <6>[ 0.665316] pnp: PnP ACPI: disabled
10149 12:18:04.827891 <6>[ 0.672005] NET: Registered PF_INET protocol family
10150 12:18:04.834022 <6>[ 0.677391] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10151 12:18:04.846369 <6>[ 0.687413] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10152 12:18:04.856760 <6>[ 0.696200] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10153 12:18:04.863110 <6>[ 0.704167] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10154 12:18:04.869811 <6>[ 0.712572] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10155 12:18:04.880410 <6>[ 0.721230] TCP: Hash tables configured (established 32768 bind 32768)
10156 12:18:04.887325 <6>[ 0.728087] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10157 12:18:04.893560 <6>[ 0.735106] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10158 12:18:04.900066 <6>[ 0.742623] NET: Registered PF_UNIX/PF_LOCAL protocol family
10159 12:18:04.906739 <6>[ 0.748773] RPC: Registered named UNIX socket transport module.
10160 12:18:04.910022 <6>[ 0.754928] RPC: Registered udp transport module.
10161 12:18:04.916678 <6>[ 0.759863] RPC: Registered tcp transport module.
10162 12:18:04.923261 <6>[ 0.764794] RPC: Registered tcp NFSv4.1 backchannel transport module.
10163 12:18:04.926544 <6>[ 0.771463] PCI: CLS 0 bytes, default 64
10164 12:18:04.929749 <6>[ 0.775814] Unpacking initramfs...
10165 12:18:04.946618 <6>[ 0.787599] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10166 12:18:04.956530 <6>[ 0.796262] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10167 12:18:04.959988 <6>[ 0.805140] kvm [1]: IPA Size Limit: 40 bits
10168 12:18:04.966523 <6>[ 0.809673] kvm [1]: GICv3: no GICV resource entry
10169 12:18:04.969526 <6>[ 0.814697] kvm [1]: disabling GICv2 emulation
10170 12:18:04.976356 <6>[ 0.819385] kvm [1]: GIC system register CPU interface enabled
10171 12:18:04.979744 <6>[ 0.825575] kvm [1]: vgic interrupt IRQ18
10172 12:18:04.986366 <6>[ 0.829955] kvm [1]: VHE mode initialized successfully
10173 12:18:04.993131 <5>[ 0.836366] Initialise system trusted keyrings
10174 12:18:04.999707 <6>[ 0.841158] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10175 12:18:05.006756 <6>[ 0.851095] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10176 12:18:05.013209 <5>[ 0.857480] NFS: Registering the id_resolver key type
10177 12:18:05.016624 <5>[ 0.862776] Key type id_resolver registered
10178 12:18:05.023542 <5>[ 0.867192] Key type id_legacy registered
10179 12:18:05.029735 <6>[ 0.871477] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10180 12:18:05.036730 <6>[ 0.878398] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10181 12:18:05.043364 <6>[ 0.886101] 9p: Installing v9fs 9p2000 file system support
10182 12:18:05.079815 <5>[ 0.924031] Key type asymmetric registered
10183 12:18:05.083005 <5>[ 0.928361] Asymmetric key parser 'x509' registered
10184 12:18:05.092925 <6>[ 0.933494] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10185 12:18:05.096306 <6>[ 0.941108] io scheduler mq-deadline registered
10186 12:18:05.099537 <6>[ 0.945870] io scheduler kyber registered
10187 12:18:05.119178 <6>[ 0.963414] EINJ: ACPI disabled.
10188 12:18:05.151656 <4>[ 0.989184] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10189 12:18:05.161390 <4>[ 0.999798] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10190 12:18:05.176444 <6>[ 1.020710] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10191 12:18:05.184763 <6>[ 1.028755] printk: console [ttyS0] disabled
10192 12:18:05.212522 <6>[ 1.053420] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10193 12:18:05.218885 <6>[ 1.062890] printk: console [ttyS0] enabled
10194 12:18:05.222494 <6>[ 1.062890] printk: console [ttyS0] enabled
10195 12:18:05.228847 <6>[ 1.071784] printk: bootconsole [mtk8250] disabled
10196 12:18:05.232084 <6>[ 1.071784] printk: bootconsole [mtk8250] disabled
10197 12:18:05.239125 <6>[ 1.082858] SuperH (H)SCI(F) driver initialized
10198 12:18:05.241899 <6>[ 1.088144] msm_serial: driver initialized
10199 12:18:05.256410 <6>[ 1.097202] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10200 12:18:05.266461 <6>[ 1.105749] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10201 12:18:05.273065 <6>[ 1.114292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10202 12:18:05.282669 <6>[ 1.122920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10203 12:18:05.292530 <6>[ 1.131626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10204 12:18:05.299186 <6>[ 1.140344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10205 12:18:05.309360 <6>[ 1.148884] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10206 12:18:05.315555 <6>[ 1.157679] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10207 12:18:05.327790 <6>[ 1.166222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10208 12:18:05.337578 <6>[ 1.181819] loop: module loaded
10209 12:18:05.343967 <6>[ 1.187838] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10210 12:18:05.367235 <4>[ 1.211162] mtk-pmic-keys: Failed to locate of_node [id: -1]
10211 12:18:05.373982 <6>[ 1.217960] megasas: 07.719.03.00-rc1
10212 12:18:05.383595 <6>[ 1.227660] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10213 12:18:05.391050 <6>[ 1.234865] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10214 12:18:05.407210 <6>[ 1.251419] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10215 12:18:05.463018 <6>[ 1.300784] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10216 12:18:05.828007 <6>[ 1.672305] Freeing initrd memory: 20884K
10217 12:18:05.843632 <6>[ 1.687979] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10218 12:18:05.854501 <6>[ 1.699106] tun: Universal TUN/TAP device driver, 1.6
10219 12:18:05.858261 <6>[ 1.705215] thunder_xcv, ver 1.0
10220 12:18:05.861441 <6>[ 1.708722] thunder_bgx, ver 1.0
10221 12:18:05.864928 <6>[ 1.712219] nicpf, ver 1.0
10222 12:18:05.875612 <6>[ 1.716294] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10223 12:18:05.878776 <6>[ 1.723769] hns3: Copyright (c) 2017 Huawei Corporation.
10224 12:18:05.881923 <6>[ 1.729381] hclge is initializing
10225 12:18:05.888863 <6>[ 1.732961] e1000: Intel(R) PRO/1000 Network Driver
10226 12:18:05.895616 <6>[ 1.738091] e1000: Copyright (c) 1999-2006 Intel Corporation.
10227 12:18:05.898741 <6>[ 1.744106] e1000e: Intel(R) PRO/1000 Network Driver
10228 12:18:05.905328 <6>[ 1.749321] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10229 12:18:05.912268 <6>[ 1.755507] igb: Intel(R) Gigabit Ethernet Network Driver
10230 12:18:05.918340 <6>[ 1.761157] igb: Copyright (c) 2007-2014 Intel Corporation.
10231 12:18:05.925039 <6>[ 1.766992] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10232 12:18:05.931775 <6>[ 1.773511] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10233 12:18:05.935201 <6>[ 1.779984] sky2: driver version 1.30
10234 12:18:05.941580 <6>[ 1.785035] VFIO - User Level meta-driver version: 0.3
10235 12:18:05.948725 <6>[ 1.793375] usbcore: registered new interface driver usb-storage
10236 12:18:05.955782 <6>[ 1.799822] usbcore: registered new device driver onboard-usb-hub
10237 12:18:05.964767 <6>[ 1.809015] mt6397-rtc mt6359-rtc: registered as rtc0
10238 12:18:05.974585 <6>[ 1.814480] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:18:06 UTC (1698409086)
10239 12:18:05.978280 <6>[ 1.824118] i2c_dev: i2c /dev entries driver
10240 12:18:05.995211 <6>[ 1.836263] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10241 12:18:06.016047 <6>[ 1.860252] cpu cpu0: EM: created perf domain
10242 12:18:06.019053 <6>[ 1.865142] cpu cpu4: EM: created perf domain
10243 12:18:06.026371 <6>[ 1.870678] sdhci: Secure Digital Host Controller Interface driver
10244 12:18:06.032874 <6>[ 1.877113] sdhci: Copyright(c) Pierre Ossman
10245 12:18:06.039389 <6>[ 1.882075] Synopsys Designware Multimedia Card Interface Driver
10246 12:18:06.046135 <6>[ 1.888694] sdhci-pltfm: SDHCI platform and OF driver helper
10247 12:18:06.049471 <6>[ 1.888836] mmc0: CQHCI version 5.10
10248 12:18:06.056335 <6>[ 1.898871] ledtrig-cpu: registered to indicate activity on CPUs
10249 12:18:06.062820 <6>[ 1.905845] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10250 12:18:06.069400 <6>[ 1.912880] usbcore: registered new interface driver usbhid
10251 12:18:06.072788 <6>[ 1.918706] usbhid: USB HID core driver
10252 12:18:06.079417 <6>[ 1.922906] spi_master spi0: will run message pump with realtime priority
10253 12:18:06.124047 <6>[ 1.961836] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10254 12:18:06.143661 <6>[ 1.977783] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10255 12:18:06.150337 <6>[ 1.992503] cros-ec-spi spi0.0: Chrome EC device registered
10256 12:18:06.154004 <6>[ 1.998560] mmc0: Command Queue Engine enabled
10257 12:18:06.160559 <6>[ 2.003318] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10258 12:18:06.167063 <6>[ 2.010381] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10259 12:18:06.177100 <6>[ 2.016523] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10260 12:18:06.184011 <6>[ 2.025039] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10261 12:18:06.187492 <6>[ 2.026709] NET: Registered PF_PACKET protocol family
10262 12:18:06.193821 <6>[ 2.032598] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10263 12:18:06.197601 <6>[ 2.037143] 9pnet: Installing 9P2000 support
10264 12:18:06.204071 <6>[ 2.042883] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10265 12:18:06.207321 <5>[ 2.046850] Key type dns_resolver registered
10266 12:18:06.213985 <6>[ 2.052598] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10267 12:18:06.216849 <6>[ 2.057049] registered taskstats version 1
10268 12:18:06.223453 <5>[ 2.067493] Loading compiled-in X.509 certificates
10269 12:18:06.251201 <4>[ 2.089065] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10270 12:18:06.261239 <4>[ 2.099845] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10271 12:18:06.267776 <3>[ 2.110373] debugfs: File 'uA_load' in directory '/' already present!
10272 12:18:06.274742 <3>[ 2.117074] debugfs: File 'min_uV' in directory '/' already present!
10273 12:18:06.281170 <3>[ 2.123778] debugfs: File 'max_uV' in directory '/' already present!
10274 12:18:06.287624 <3>[ 2.130395] debugfs: File 'constraint_flags' in directory '/' already present!
10275 12:18:06.298795 <3>[ 2.139825] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10276 12:18:06.308006 <6>[ 2.152119] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10277 12:18:06.314804 <6>[ 2.158810] xhci-mtk 11200000.usb: xHCI Host Controller
10278 12:18:06.321115 <6>[ 2.164307] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10279 12:18:06.331266 <6>[ 2.172268] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10280 12:18:06.337849 <6>[ 2.181719] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10281 12:18:06.344567 <6>[ 2.187776] xhci-mtk 11200000.usb: xHCI Host Controller
10282 12:18:06.351070 <6>[ 2.193256] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10283 12:18:06.358186 <6>[ 2.200905] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10284 12:18:06.364537 <6>[ 2.208748] hub 1-0:1.0: USB hub found
10285 12:18:06.367568 <6>[ 2.212787] hub 1-0:1.0: 1 port detected
10286 12:18:06.374884 <6>[ 2.217057] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10287 12:18:06.381506 <6>[ 2.225832] hub 2-0:1.0: USB hub found
10288 12:18:06.384693 <6>[ 2.229868] hub 2-0:1.0: 1 port detected
10289 12:18:06.393920 <6>[ 2.237866] mtk-msdc 11f70000.mmc: Got CD GPIO
10290 12:18:06.400856 <6>[ 2.243034] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10291 12:18:06.410443 <6>[ 2.251080] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10292 12:18:06.419859 <4>[ 2.258980] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10293 12:18:06.426771 <6>[ 2.268508] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10294 12:18:06.436760 <6>[ 2.276587] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10295 12:18:06.443323 <6>[ 2.284735] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10296 12:18:06.449905 <6>[ 2.292667] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10297 12:18:06.460289 <6>[ 2.300485] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10298 12:18:06.466254 <6>[ 2.308302] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10299 12:18:06.477392 <6>[ 2.318810] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10300 12:18:06.488003 <6>[ 2.327204] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10301 12:18:06.494629 <6>[ 2.335545] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10302 12:18:06.504650 <6>[ 2.343886] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10303 12:18:06.510949 <6>[ 2.352227] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10304 12:18:06.520455 <6>[ 2.360565] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10305 12:18:06.527125 <6>[ 2.368904] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10306 12:18:06.537140 <6>[ 2.377242] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10307 12:18:06.543857 <6>[ 2.385580] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10308 12:18:06.553880 <6>[ 2.393918] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10309 12:18:06.560708 <6>[ 2.402256] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10310 12:18:06.570113 <6>[ 2.410608] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10311 12:18:06.576717 <6>[ 2.418946] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10312 12:18:06.586680 <6>[ 2.427283] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10313 12:18:06.593461 <6>[ 2.435620] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10314 12:18:06.600041 <6>[ 2.444455] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10315 12:18:06.607323 <6>[ 2.451647] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10316 12:18:06.614499 <6>[ 2.458390] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10317 12:18:06.624348 <6>[ 2.465124] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10318 12:18:06.630982 <6>[ 2.472032] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10319 12:18:06.637275 <6>[ 2.478890] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10320 12:18:06.647654 <6>[ 2.488020] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10321 12:18:06.657229 <6>[ 2.497139] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10322 12:18:06.667244 <6>[ 2.506451] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10323 12:18:06.676996 <6>[ 2.515921] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10324 12:18:06.684118 <6>[ 2.525390] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10325 12:18:06.693786 <6>[ 2.534510] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10326 12:18:06.703725 <6>[ 2.543976] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10327 12:18:06.713172 <6>[ 2.553094] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10328 12:18:06.723012 <6>[ 2.562389] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10329 12:18:06.732878 <6>[ 2.572548] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10330 12:18:06.742986 <6>[ 2.584058] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10331 12:18:06.774811 <6>[ 2.615810] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10332 12:18:06.802136 <6>[ 2.646492] hub 2-1:1.0: USB hub found
10333 12:18:06.805328 <6>[ 2.650896] hub 2-1:1.0: 3 ports detected
10334 12:18:06.926788 <6>[ 2.767739] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10335 12:18:07.081760 <6>[ 2.925820] hub 1-1:1.0: USB hub found
10336 12:18:07.084786 <6>[ 2.930260] hub 1-1:1.0: 4 ports detected
10337 12:18:07.162841 <6>[ 3.003892] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10338 12:18:07.406556 <6>[ 3.247790] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10339 12:18:07.539349 <6>[ 3.383552] hub 1-1.4:1.0: USB hub found
10340 12:18:07.542721 <6>[ 3.388213] hub 1-1.4:1.0: 2 ports detected
10341 12:18:07.838272 <6>[ 3.679759] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10342 12:18:08.030780 <6>[ 3.871760] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10343 12:18:19.019640 <6>[ 14.868779] ALSA device list:
10344 12:18:19.025775 <6>[ 14.872064] No soundcards found.
10345 12:18:19.034350 <6>[ 14.879852] Freeing unused kernel memory: 8384K
10346 12:18:19.037237 <6>[ 14.884835] Run /init as init process
10347 12:18:19.067999 Starting syslogd: OK
10348 12:18:19.072423 Starting klogd: OK
10349 12:18:19.080823 Running sysctl: OK
10350 12:18:19.087804 Populating /dev using udev: <30>[ 14.934428] udevd[186]: starting version 3.2.9
10351 12:18:19.095388 <27>[ 14.940970] udevd[186]: specified user 'tss' unknown
10352 12:18:19.101617 <27>[ 14.946314] udevd[186]: specified group 'tss' unknown
10353 12:18:19.104904 <30>[ 14.952680] udevd[187]: starting eudev-3.2.9
10354 12:18:19.127657 <27>[ 14.973691] udevd[187]: specified user 'tss' unknown
10355 12:18:19.134190 <27>[ 14.979211] udevd[187]: specified group 'tss' unknown
10356 12:18:19.286926 <6>[ 15.129806] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10357 12:18:19.297162 <6>[ 15.143045] remoteproc remoteproc0: scp is available
10358 12:18:19.303758 <6>[ 15.148472] remoteproc remoteproc0: powering up scp
10359 12:18:19.310802 <6>[ 15.153793] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10360 12:18:19.320056 <6>[ 15.154905] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10361 12:18:19.323434 <6>[ 15.162590] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10362 12:18:19.333751 <6>[ 15.169946] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10363 12:18:19.339974 <4>[ 15.179793] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10364 12:18:19.350442 <6>[ 15.184270] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10365 12:18:19.356546 <4>[ 15.191790] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10366 12:18:19.363273 <6>[ 15.209412] mc: Linux media interface: v0.10
10367 12:18:19.370394 <6>[ 15.216311] usbcore: registered new interface driver r8152
10368 12:18:19.380220 <3>[ 15.219945] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10369 12:18:19.387244 <6>[ 15.223616] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10370 12:18:19.393571 <3>[ 15.230361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10371 12:18:19.403964 <3>[ 15.246063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10372 12:18:19.413855 <4>[ 15.252030] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10373 12:18:19.416707 <4>[ 15.252030] Fallback method does not support PEC.
10374 12:18:19.423856 <3>[ 15.254286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10375 12:18:19.434301 <3>[ 15.276058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10376 12:18:19.440957 <3>[ 15.284171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10377 12:18:19.450616 <3>[ 15.286258] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10378 12:18:19.457215 <3>[ 15.292260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10379 12:18:19.467394 <3>[ 15.292266] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10380 12:18:19.474434 <3>[ 15.292363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10381 12:18:19.484586 <6>[ 15.300241] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10382 12:18:19.494258 <6>[ 15.300582] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10383 12:18:19.500808 <6>[ 15.300763] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10384 12:18:19.507433 <6>[ 15.300772] remoteproc remoteproc0: remote processor scp is now up
10385 12:18:19.514646 <6>[ 15.300772] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10386 12:18:19.524529 <6>[ 15.307704] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10387 12:18:19.531140 <3>[ 15.309204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10388 12:18:19.537224 <6>[ 15.313211] videodev: Linux video capture interface: v2.00
10389 12:18:19.547218 <6>[ 15.321194] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10390 12:18:19.553717 <3>[ 15.325303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10391 12:18:19.560589 <3>[ 15.325307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10392 12:18:19.570131 <3>[ 15.325346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10393 12:18:19.580356 <3>[ 15.325568] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10394 12:18:19.587199 <6>[ 15.328901] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10395 12:18:19.590698 <6>[ 15.328908] pci_bus 0000:00: root bus resource [bus 00-ff]
10396 12:18:19.600276 <6>[ 15.328916] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10397 12:18:19.610393 <6>[ 15.328921] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10398 12:18:19.613391 <6>[ 15.328960] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10399 12:18:19.623565 <6>[ 15.328981] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10400 12:18:19.626457 <6>[ 15.329089] pci 0000:00:00.0: supports D1 D2
10401 12:18:19.633374 <6>[ 15.329097] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10402 12:18:19.643372 <6>[ 15.331033] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10403 12:18:19.649853 <6>[ 15.331463] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10404 12:18:19.656637 <6>[ 15.331526] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10405 12:18:19.662950 <6>[ 15.331550] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10406 12:18:19.669690 <6>[ 15.331568] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10407 12:18:19.676535 <6>[ 15.331717] pci 0000:01:00.0: supports D1 D2
10408 12:18:19.683001 <6>[ 15.331720] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10409 12:18:19.689393 <4>[ 15.342474] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10410 12:18:19.696101 <6>[ 15.343564] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10411 12:18:19.706320 <6>[ 15.343592] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10412 12:18:19.712757 <6>[ 15.343595] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10413 12:18:19.723467 <6>[ 15.343603] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10414 12:18:19.729021 <6>[ 15.343616] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10415 12:18:19.739179 <6>[ 15.343628] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10416 12:18:19.742632 <6>[ 15.343640] pci 0000:00:00.0: PCI bridge to [bus 01]
10417 12:18:19.752631 <6>[ 15.343645] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10418 12:18:19.755763 <6>[ 15.343771] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10419 12:18:19.762405 <6>[ 15.344220] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10420 12:18:19.769586 <6>[ 15.344379] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10421 12:18:19.778900 <3>[ 15.344446] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10422 12:18:19.785873 <4>[ 15.352958] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10423 12:18:19.792548 <3>[ 15.359425] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10424 12:18:19.798763 <6>[ 15.360386] usbcore: registered new interface driver cdc_ether
10425 12:18:19.808427 <6>[ 15.361774] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10426 12:18:19.815414 <6>[ 15.369222] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10427 12:18:19.825033 <3>[ 15.373579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10428 12:18:19.831683 <3>[ 15.373584] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10429 12:18:19.841567 <3>[ 15.373610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10430 12:18:19.845052 <6>[ 15.374168] Bluetooth: Core ver 2.22
10431 12:18:19.848113 <6>[ 15.374280] NET: Registered PF_BLUETOOTH protocol family
10432 12:18:19.854555 <6>[ 15.374283] usbcore: registered new interface driver r8153_ecm
10433 12:18:19.861466 <6>[ 15.374285] Bluetooth: HCI device and connection manager initialized
10434 12:18:19.868138 <6>[ 15.374314] Bluetooth: HCI socket layer initialized
10435 12:18:19.871204 <6>[ 15.374321] Bluetooth: L2CAP socket layer initialized
10436 12:18:19.877862 <6>[ 15.374330] Bluetooth: SCO socket layer initialized
10437 12:18:19.884393 <5>[ 15.383755] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10438 12:18:19.894125 <6>[ 15.397900] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10439 12:18:19.901134 <5>[ 15.428323] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10440 12:18:19.904148 <6>[ 15.430806] usbcore: registered new interface driver btusb
10441 12:18:19.911029 <6>[ 15.430978] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10442 12:18:19.924344 <4>[ 15.431440] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10443 12:18:19.927717 <3>[ 15.431483] Bluetooth: hci0: Failed to load firmware file (-2)
10444 12:18:19.933996 <3>[ 15.431497] Bluetooth: hci0: Failed to set up firmware (-2)
10445 12:18:19.944006 <4>[ 15.431506] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10446 12:18:19.957106 <6>[ 15.431866] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10447 12:18:19.963779 <6>[ 15.432006] usbcore: registered new interface driver uvcvideo
10448 12:18:19.970664 <4>[ 15.436778] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10449 12:18:19.977202 <6>[ 15.449615] r8152 2-1.3:1.0 eth0: v1.12.13
10450 12:18:19.980244 <6>[ 15.459455] cfg80211: failed to load regulatory.db
10451 12:18:19.990333 <6>[ 15.540693] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10452 12:18:19.996614 <6>[ 15.840184] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10453 12:18:20.017778 <6>[ 15.863727] mt7921e 0000:01:00.0: ASIC revision: 79610010
10454 12:18:20.123649 <4>[ 15.963047] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10455 12:18:20.124291 done
10456 12:18:20.144358 Saving random seed: OK
10457 12:18:20.160323 Starting network: OK
10458 12:18:20.199073 Starting dropbear sshd: <6>[ 16.045046] NET: Registered PF_INET6 protocol family
10459 12:18:20.205739 <6>[ 16.051792] Segment Routing with IPv6
10460 12:18:20.208855 <6>[ 16.055737] In-situ OAM (IOAM) with IPv6
10461 12:18:20.212920 OK
10462 12:18:20.225573 /bin/sh: can't access tty; job control turned off
10463 12:18:20.226884 Matched prompt #10: / #
10465 12:18:20.227992 Setting prompt string to ['/ #']
10466 12:18:20.228518 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10468 12:18:20.229619 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10469 12:18:20.230100 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
10470 12:18:20.230494 Setting prompt string to ['/ #']
10471 12:18:20.230835 Forcing a shell prompt, looking for ['/ #']
10473 12:18:20.281701 / #
10474 12:18:20.282361 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10475 12:18:20.282941 Waiting using forced prompt support (timeout 00:02:30)
10476 12:18:20.283466 <4>[ 16.081983] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10477 12:18:20.288460
10478 12:18:20.289543 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10479 12:18:20.290095 start: 2.2.7 export-device-env (timeout 00:03:46) [common]
10480 12:18:20.290662 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10481 12:18:20.291181 end: 2.2 depthcharge-retry (duration 00:01:14) [common]
10482 12:18:20.291665 end: 2 depthcharge-action (duration 00:01:14) [common]
10483 12:18:20.292147 start: 3 lava-test-retry (timeout 00:01:00) [common]
10484 12:18:20.292665 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10485 12:18:20.293084 Using namespace: common
10487 12:18:20.394424 / # #
10488 12:18:20.395100 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10489 12:18:20.395732 <4>[ 16.197776] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10490 12:18:20.401241 #
10491 12:18:20.402131 Using /lava-11893107
10493 12:18:20.503493 / # export SHELL=/bin/sh
10494 12:18:20.504336 export SHELL=/bin/sh<4>[ 16.314218] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10495 12:18:20.510039
10497 12:18:20.611787 / # . /lava-11893107/environment
10498 12:18:20.612640 . /lava-11893107/environment<4>[ 16.433687] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10499 12:18:20.618359
10501 12:18:20.720144 / # /lava-11893107/bin/lava-test-runner /lava-11893107/0
10502 12:18:20.720777 Test shell timeout: 10s (minimum of the action and connection timeout)
10503 12:18:20.722403 /lava-11893107/bin/lava-test-runner /lava-11893107/0<4>[ 16.550090] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10504 12:18:20.726496
10505 12:18:20.768401 + export 'TESTRUN_ID=0_dmesg'
10506 12:18:20.768544 + c<8>[ 16.595993] <LAVA_SIGNAL_STARTRUN 0_dmesg 11893107_1.5.2.3.1>
10507 12:18:20.768635 d /lava-11893107/0/tests/0_dmesg
10508 12:18:20.768714 + cat uuid
10509 12:18:20.768791 + UUID=11893107_1.5.2.3.1
10510 12:18:20.768864 + set +x
10511 12:18:20.768936 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10512 12:18:20.769199 Received signal: <STARTRUN> 0_dmesg 11893107_1.5.2.3.1
10513 12:18:20.769287 Starting test lava.0_dmesg (11893107_1.5.2.3.1)
10514 12:18:20.769389 Skipping test definition patterns.
10515 12:18:20.774710 <8>[ 16.617688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10516 12:18:20.774969 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10518 12:18:20.794890 <8>[ 16.638011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10519 12:18:20.795233 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10521 12:18:20.821478 <8>[ 16.664724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10522 12:18:20.821839 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10524 12:18:20.834733 <4>[ 16.670307] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10525 12:18:20.834942 + set +x
10526 12:18:20.841540 <8>[ 16.685022] <LAVA_SIGNAL_ENDRUN 0_dmesg 11893107_1.5.2.3.1>
10527 12:18:20.841964 Received signal: <ENDRUN> 0_dmesg 11893107_1.5.2.3.1
10528 12:18:20.842120 Ending use of test pattern.
10529 12:18:20.842237 Ending test lava.0_dmesg (11893107_1.5.2.3.1), duration 0.07
10531 12:18:20.844525 <LAVA_TEST_RUNNER EXIT>
10532 12:18:20.844876 ok: lava_test_shell seems to have completed
10533 12:18:20.845072 alert: pass
crit: pass
emerg: pass
10534 12:18:20.845230 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10535 12:18:20.845386 end: 3 lava-test-retry (duration 00:00:01) [common]
10536 12:18:20.845537 start: 4 lava-test-retry (timeout 00:01:00) [common]
10537 12:18:20.845685 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10538 12:18:20.845803 Using namespace: common
10540 12:18:20.946591 / # #
10541 12:18:20.947271 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10542 12:18:20.947952 Using /lava-11893107
10544 12:18:21.049084 export SHELL=/bin/sh
10545 12:18:21.049732 #<4>[ 16.789714] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10546 12:18:21.050178
10548 12:18:21.151436 / # export SHELL=/bin/sh. /lava-11893107/environment
10549 12:18:21.152130
10550 12:18:21.152523 / # <4>[ 16.910320] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10552 12:18:21.253850 . /lava-11893107/environment/lava-11893107/bin/lava-test-runner /lava-11893107/1
10553 12:18:21.254343 Test shell timeout: 10s (minimum of the action and connection timeout)
10554 12:18:21.254864
10555 12:18:21.255209 / # <4>[ 17.029953] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10556 12:18:21.259882 /lava-11893107/bin/lava-test-runner /lava-11893107/1
10557 12:18:21.300537 + export 'TESTRUN_ID=1_bootrr'
10558 12:18:21.300968 <8>[ 17.131063] <LAVA_SIGNAL_STARTRUN 1_bootrr 11893107_1.5.2.3.5>
10559 12:18:21.301311 + cd /lava-11893107/1/tests/1_bootrr
10560 12:18:21.301632 + cat uuid
10561 12:18:21.302195 Received signal: <STARTRUN> 1_bootrr 11893107_1.5.2.3.5
10562 12:18:21.302529 Starting test lava.1_bootrr (11893107_1.5.2.3.5)
10563 12:18:21.302903 Skipping test definition patterns.
10564 12:18:21.303370 + UUID=11893107_1.5.2.3.5
10565 12:18:21.303703 + set +x
10566 12:18:21.306453 + export 'PATH=/<3>[ 17.149971] mt7921e 0000:01:00.0: hardware init failed
10567 12:18:21.313107 opt/bootrr/libexec/bootrr/helpers:/lava-11893107/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10568 12:18:21.316434 + cd /opt/bootrr/libexec/bootrr
10569 12:18:21.323693 + sh <8>[ 17.166202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10570 12:18:21.324385 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10572 12:18:21.326397 helpers/bootrr-auto
10573 12:18:21.329830 /lava-11893107/1/../bin/lava-test-case
10574 12:18:21.332987 /lava-11893107/1/../bin/lava-test-case
10575 12:18:21.343611 <8>[ 17.186485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10576 12:18:21.344292 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10578 12:18:21.348241 /usr/bin/tpm2_getcap
10579 12:18:21.381769 /lava-11893107/1/../bin/lava-test-case
10580 12:18:21.388349 <8>[ 17.233124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10581 12:18:21.389026 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10583 12:18:21.406670 /lava-11893107/1/../bin/lava-test-case
10584 12:18:21.413191 <8>[ 17.255867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10585 12:18:21.413869 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10587 12:18:21.425035 /lava-11893107/1/../bin/lava-test-case
10588 12:18:21.431695 <8>[ 17.274949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10589 12:18:21.432374 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10591 12:18:21.444008 /lava-11893107/1/../bin/lava-test-case
10592 12:18:21.450718 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10594 12:18:21.453598 <8>[ 17.295401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10595 12:18:21.462655 /lava-11893107/1/../bin/lava-test-case
10596 12:18:21.469526 <8>[ 17.312590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10597 12:18:21.470202 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10599 12:18:21.480443 /lava-11893107/1/../bin/lava-test-case
10600 12:18:21.487731 <8>[ 17.330564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10601 12:18:21.488406 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10603 12:18:21.496394 /lava-11893107/1/../bin/lava-test-case
10604 12:18:21.503036 <8>[ 17.345793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10605 12:18:21.503714 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10607 12:18:21.514609 /lava-11893107/1/../bin/lava-test-case
10608 12:18:21.521150 <8>[ 17.364296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10609 12:18:21.521826 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10611 12:18:21.537996 /lava-11893107/1/../bin/lava-tes<8>[ 17.380459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10612 12:18:21.538425 t-case
10613 12:18:21.539009 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10615 12:18:21.550438 /lava-11893107/1/../bin/lava-test-case
10616 12:18:21.557302 <8>[ 17.399722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10617 12:18:21.558097 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10619 12:18:21.569723 /lava-11893107/1/../bin/lava-test-case
10620 12:18:21.575914 <8>[ 17.419944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10621 12:18:21.576709 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10623 12:18:21.588797 /lava-11893107/1/../bin/lava-test-case
10624 12:18:21.598675 <8>[ 17.441824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10625 12:18:21.599352 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10627 12:18:21.610059 /lava-11893107/1/../bin/lava-test-case
10628 12:18:21.616828 <8>[ 17.460742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10629 12:18:21.617506 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10631 12:18:21.626860 /lava-11893107/1/../bin/lava-test-case
10632 12:18:21.633227 <8>[ 17.477266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10633 12:18:21.633903 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10635 12:18:21.645268 /lava-11893107/1/../bin/lava-test-case
10636 12:18:21.651687 <8>[ 17.494277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10637 12:18:21.652367 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10639 12:18:21.660463 /lava-11893107/1/../bin/lava-test-case
10640 12:18:21.666871 <8>[ 17.510092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10641 12:18:21.667549 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10643 12:18:21.678299 /lava-11893107/1/../bin/lava-test-case
10644 12:18:21.684655 <8>[ 17.527683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10645 12:18:21.685332 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10647 12:18:21.692509 /lava-11893107/1/../bin/lava-test-case
10648 12:18:21.699186 <8>[ 17.543270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10649 12:18:21.699865 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10651 12:18:21.710155 /lava-11893107/1/../bin/lava-test-case
10652 12:18:21.716461 <8>[ 17.560706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10653 12:18:21.717146 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10655 12:18:21.725033 /lava-11893107/1/../bin/lava-test-case
10656 12:18:21.731777 <8>[ 17.576031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10657 12:18:21.732520 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10659 12:18:21.742970 /lava-11893107/1/../bin/lava-test-case
10660 12:18:21.749555 <8>[ 17.593647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10661 12:18:21.750288 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10663 12:18:21.766195 /lava-11893107/1/../bin/lava-tes<8>[ 17.608565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10664 12:18:21.766803 t-case
10665 12:18:21.767572 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10667 12:18:21.777908 /lava-11893107/1/../bin/lava-test-case
10668 12:18:21.788051 <8>[ 17.629957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10669 12:18:21.788815 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10671 12:18:21.797122 /lava-11893107/1/../bin/lava-test-case
10672 12:18:21.803495 <8>[ 17.647282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10673 12:18:21.804207 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10675 12:18:21.812371 /lava-11893107/1/../bin/lava-test-case
10676 12:18:21.818708 <8>[ 17.662907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10677 12:18:21.819529 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10679 12:18:21.838375 /lava-11893107/1/../bin/lava-tes<8>[ 17.680936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10680 12:18:21.838939 t-case
10681 12:18:21.839688 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10683 12:18:21.845961 /lava-11893107/1/../bin/lava-test-case
10684 12:18:21.852691 <8>[ 17.695703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10685 12:18:21.853377 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10687 12:18:21.872768 /lava-11893107/1/../bin/lava-tes<8>[ 17.715183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10688 12:18:21.873378 t-case
10689 12:18:21.873992 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10691 12:18:21.883931 /lava-11893107/1/../bin/lava-test-case
10692 12:18:21.890351 <8>[ 17.733982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10693 12:18:21.891120 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10695 12:18:21.908836 /lava-11893107/1/../bin/lava-tes<8>[ 17.750895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10696 12:18:21.909271 t-case
10697 12:18:21.909862 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10699 12:18:21.919012 /lava-11893107/1/../bin/lava-test-case
10700 12:18:21.925540 <8>[ 17.769219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10701 12:18:21.926219 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10703 12:18:21.935612 /lava-11893107/1/../bin/lava-test-case
10704 12:18:21.942273 <8>[ 17.785437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10705 12:18:21.942951 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10707 12:18:21.952453 /lava-11893107/1/../bin/lava-test-case
10708 12:18:21.959152 <8>[ 17.803202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10709 12:18:21.959830 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10711 12:18:21.971061 /lava-11893107/1/../bin/lava-test-case
10712 12:18:21.977693 <8>[ 17.820751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10713 12:18:21.978434 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10715 12:18:21.986771 /lava-11893107/1/../bin/lava-test-case
10716 12:18:21.993372 <8>[ 17.837240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10717 12:18:21.994208 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10719 12:18:22.014174 /lava-11893107/1/../bin/lava-tes<8>[ 17.856090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10720 12:18:22.014760 t-case
10721 12:18:22.015538 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10723 12:18:22.022558 /lava-11893107/1/../bin/lava-test-case
10724 12:18:22.029517 <8>[ 17.872572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10725 12:18:22.030257 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10727 12:18:22.042417 /lava-11893107/1/../bin/lava-test-case
10728 12:18:22.048908 <8>[ 17.891865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10729 12:18:22.049596 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10731 12:18:22.058391 /lava-11893107/1/../bin/lava-test-case
10732 12:18:22.065129 <8>[ 17.909005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10733 12:18:22.065847 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10735 12:18:22.080918 /lava-11893107/1/../bin/lava-test-case
10736 12:18:22.087565 <8>[ 17.932792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10737 12:18:22.088294 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10739 12:18:22.097742 /lava-11893107/1/../bin/lava-test-case
10740 12:18:22.104272 <8>[ 17.947312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10741 12:18:22.104967 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10743 12:18:22.118054 /lava-11893107/1/../bin/lava-test-case
10744 12:18:22.124845 <8>[ 17.968893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10745 12:18:22.125530 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10747 12:18:22.133985 /lava-11893107/1/../bin/lava-test-case
10748 12:18:22.140820 <8>[ 17.983754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10749 12:18:22.141497 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10751 12:18:22.154938 /lava-11893107/1/../bin/lava-test-case
10752 12:18:22.160939 <8>[ 18.004891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10753 12:18:22.161706 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10755 12:18:22.171792 /lava-11893107/1/../bin/lava-test-case
10756 12:18:22.178269 <8>[ 18.021479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10757 12:18:22.179177 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10759 12:18:22.190305 /lava-11893107/1/../bin/lava-test-case
10760 12:18:22.196887 <8>[ 18.040207] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10761 12:18:22.197679 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
10763 12:18:22.204716 /lava-11893107/1/../bin/lava-test-case
10764 12:18:22.210996 <8>[ 18.054224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
10765 12:18:22.211901 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
10767 12:18:22.230366 /lava-11893107/1/../bin/lava-tes<8>[ 18.072363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
10768 12:18:22.230844 t-case
10769 12:18:22.231475 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
10771 12:18:22.240489 /lava-11893107/1/../bin/lava-test-case
10772 12:18:22.246583 <8>[ 18.090257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
10773 12:18:22.247323 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
10775 12:18:22.262571 /lava-11893107/1/../bin/lava-tes<8>[ 18.105046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
10776 12:18:22.263040 t-case
10777 12:18:22.263660 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
10779 12:18:22.274515 /lava-11893107/1/../bin/lava-test-case
10780 12:18:22.280586 <8>[ 18.123849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
10781 12:18:22.281444 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
10783 12:18:22.296153 /lava-11893107/1/../bin/lava-tes<8>[ 18.138713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
10784 12:18:22.296683 t-case
10785 12:18:22.297321 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
10787 12:18:22.306407 /lava-11893107/1/../bin/lava-test-case
10788 12:18:22.313293 <8>[ 18.156662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
10789 12:18:22.313976 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
10791 12:18:22.324563 /lava-11893107/1/../bin/lava-test-case
10792 12:18:22.331091 <8>[ 18.173858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
10793 12:18:22.331829 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
10795 12:18:22.340240 /lava-11893107/1/../bin/lava-test-case
10796 12:18:22.346899 <8>[ 18.190929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
10797 12:18:22.347614 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
10799 12:18:22.359050 /lava-11893107/1/../bin/lava-test-case
10800 12:18:22.365477 <8>[ 18.208381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
10801 12:18:22.366328 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
10803 12:18:22.374515 /lava-11893107/1/../bin/lava-test-case
10804 12:18:22.380849 <8>[ 18.225051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
10805 12:18:22.381676 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
10807 12:18:22.398888 /lava-11893107/1/../bin/lava-tes<8>[ 18.241082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
10808 12:18:22.399485 t-case
10809 12:18:22.400146 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
10811 12:18:22.407851 /lava-11893107/1/../bin/lava-test-case
10812 12:18:22.414610 <8>[ 18.257438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
10813 12:18:22.415458 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
10815 12:18:22.425711 /lava-11893107/1/../bin/lava-test-case
10816 12:18:22.432305 <8>[ 18.274970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
10817 12:18:22.433043 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
10819 12:18:22.439782 /lava-11893107/1/../bin/lava-test-case
10820 12:18:22.446614 <8>[ 18.290354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
10821 12:18:22.447474 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
10823 12:18:22.459927 /lava-11893107/1/../bin/lava-test-case
10824 12:18:22.466507 <8>[ 18.309808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
10825 12:18:22.467245 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
10827 12:18:22.474288 /lava-11893107/1/../bin/lava-test-case
10828 12:18:22.480781 <8>[ 18.324404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
10829 12:18:22.481515 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
10831 12:18:22.495043 /lava-11893107/1/../bin/lava-test-case
10832 12:18:22.501737 <8>[ 18.345357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
10833 12:18:22.502409 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
10835 12:18:22.513739 /lava-11893107/1/../bin/lava-test-case
10836 12:18:22.519729 <8>[ 18.363129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
10837 12:18:22.520497 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
10839 12:18:22.532560 /lava-11893107/1/../bin/lava-test-case
10840 12:18:22.539070 <8>[ 18.381975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
10841 12:18:22.539924 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
10843 12:18:22.550156 /lava-11893107/1/../bin/lava-test-case
10844 12:18:22.557020 <8>[ 18.401947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
10845 12:18:22.557870 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
10847 12:18:22.571011 /lava-11893107/1/../bin/lava-test-case
10848 12:18:22.577491 <8>[ 18.420977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
10849 12:18:22.578394 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
10851 12:18:22.590135 /lava-11893107/1/../bin/lava-test-case
10852 12:18:22.596606 <8>[ 18.440210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
10853 12:18:22.597339 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
10855 12:18:22.614391 /lava-11893107/1/../bin/lava-tes<8>[ 18.456839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
10856 12:18:22.614866 t-case
10857 12:18:22.615495 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
10859 12:18:22.625335 /lava-11893107/1/../bin/lava-test-case
10860 12:18:22.632158 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
10862 12:18:22.635073 <8>[ 18.477387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
10863 12:18:22.645182 /lava-11893107/1/../bin/lava-test-case
10864 12:18:22.651861 <8>[ 18.494634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
10865 12:18:22.652593 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
10867 12:18:22.662826 /lava-11893107/1/../bin/lava-test-case
10868 12:18:22.669059 <8>[ 18.512972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
10869 12:18:22.669830 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
10871 12:18:22.687942 /lava-11893107/1/../bin/lava-tes<8>[ 18.530660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
10872 12:18:22.688124 t-case
10873 12:18:22.688413 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
10875 12:18:22.705847 /lava-11893107/1/../bin/lava-tes<8>[ 18.548438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
10876 12:18:22.705974 t-case
10877 12:18:22.706253 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
10879 12:18:22.716123 /lava-11893107/1/../bin/lava-test-case
10880 12:18:22.722732 <8>[ 18.567339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
10881 12:18:22.723104 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
10883 12:18:22.735680 /lava-11893107/1/../bin/lava-test-case
10884 12:18:22.742186 <8>[ 18.585780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
10885 12:18:22.742824 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
10887 12:18:22.751839 /lava-11893107/1/../bin/lava-test-case
10888 12:18:22.759108 <8>[ 18.602702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
10889 12:18:22.759935 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
10891 12:18:22.770448 /lava-11893107/1/../bin/lava-test-case
10892 12:18:22.776972 <8>[ 18.619649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
10893 12:18:22.777806 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
10895 12:18:22.788076 /lava-11893107/1/../bin/lava-test-case
10896 12:18:22.794261 <8>[ 18.638149] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
10897 12:18:22.795104 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
10899 12:18:22.803729 /lava-11893107/1/../bin/lava-test-case
10900 12:18:22.810276 <8>[ 18.653755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
10901 12:18:22.811023 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
10903 12:18:22.825119 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
10905 12:18:22.827870 /lava-11893107/1/../bin/lava-tes<8>[ 18.670328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
10906 12:18:22.828386 t-case
10907 12:18:22.836539 /lava-11893107/1/../bin/lava-test-case
10908 12:18:22.842848 <8>[ 18.686485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
10909 12:18:22.843589 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
10911 12:18:22.854347 /lava-11893107/1/../bin/lava-test-case
10912 12:18:22.860885 <8>[ 18.704014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
10913 12:18:22.861750 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
10915 12:18:22.876856 /lava-11893107/1/../bin/lava-tes<8>[ 18.719052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
10916 12:18:22.877434 t-case
10917 12:18:22.878093 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
10919 12:18:22.888739 /lava-11893107/1/../bin/lava-test-case
10920 12:18:22.895423 <8>[ 18.739707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
10921 12:18:22.896242 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
10923 12:18:22.913335 /lava-11893107/1/../bin/lava-tes<8>[ 18.755962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
10924 12:18:22.913818 t-case
10925 12:18:22.914455 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
10927 12:18:22.924103 /lava-11893107/1/../bin/lava-test-case
10928 12:18:22.930813 <8>[ 18.774770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
10929 12:18:22.931490 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
10931 12:18:22.948275 /lava-11893107/1/../bin/lava-tes<8>[ 18.790501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
10932 12:18:22.948843 t-case
10933 12:18:22.949502 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
10935 12:18:22.967796 /lava-11893107/1/../bin/lava-tes<8>[ 18.810101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
10936 12:18:22.968307 t-case
10937 12:18:22.968946 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
10939 12:18:22.983231 /lava-11893107/1/../bin/lava-tes<8>[ 18.825341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
10940 12:18:22.983809 t-case
10941 12:18:22.984509 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
10943 12:18:22.995816 /lava-11893107/1/../bin/lava-test-case
10944 12:18:23.002480 <8>[ 18.845595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
10945 12:18:23.003490 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
10947 12:18:23.014977 /lava-11893107/1/../bin/lava-test-case
10948 12:18:23.022458 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
10950 12:18:23.024773 <8>[ 18.867007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
10951 12:18:23.040972 /lava-11893107/1/../bin/lava-tes<8>[ 18.882982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
10952 12:18:23.041539 t-case
10953 12:18:23.042183 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
10955 12:18:23.058661 /lava-11893107/1/../bin/lava-tes<8>[ 18.900388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
10956 12:18:23.059277 t-case
10957 12:18:23.060137 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
10959 12:18:23.067371 /lava-11893107/1/../bin/lava-test-case
10960 12:18:23.074013 <8>[ 18.916387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
10961 12:18:23.074874 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
10963 12:18:23.086805 /lava-11893107/1/../bin/lava-test-case
10964 12:18:23.093352 <8>[ 18.937035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
10965 12:18:23.094189 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
10967 12:18:23.108651 /lava-11893107/1/../bin/lava-tes<8>[ 18.951249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
10968 12:18:23.109216 t-case
10969 12:18:23.109861 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
10971 12:18:24.121524 /lava-11893107/1/../bin/lava-test-case
10972 12:18:24.127725 <8>[ 19.970819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
10973 12:18:24.128532 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
10975 12:18:24.140090 /lava-11893107/1/../bin/lava-test-case
10976 12:18:24.146538 <8>[ 19.990303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
10977 12:18:24.147276 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
10979 12:18:25.161673 /lava-11893107/1/../bin/lava-test-case
10980 12:18:25.167710 <8>[ 21.011090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
10981 12:18:25.168472 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
10983 12:18:25.186000 /lava-11893107/1/../bin/lava-tes<8>[ 21.028769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
10984 12:18:25.186547 t-case
10985 12:18:25.187230 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
10987 12:18:26.200735 /lava-11893107/1/../bin/lava-test-case
10988 12:18:26.207261 <8>[ 22.051167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
10989 12:18:26.207533 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
10991 12:18:26.219422 /lava-11893107/1/../bin/lava-test-case
10992 12:18:26.226278 <8>[ 22.070887] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
10993 12:18:26.226531 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
10995 12:18:27.239568 /lava-11893107/1/../bin/lava-test-case
10996 12:18:27.246538 <8>[ 23.089812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
10997 12:18:27.247435 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
10999 12:18:27.265463 /lava-11893107/1/../bin/lava-tes<8>[ 23.108459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11000 12:18:27.266139 t-case
11001 12:18:27.266964 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11003 12:18:28.278785 /lava-11893107/1/../bin/lava-test-case
11004 12:18:28.285747 <8>[ 24.129652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11005 12:18:28.286202 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11007 12:18:28.303903 /lava-11893107/1/../bin/lava-tes<8>[ 24.146731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11008 12:18:28.304153 t-case
11009 12:18:28.304610 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11011 12:18:29.316107 /lava-11893107/1/../bin/lava-test-case
11012 12:18:29.323083 <8>[ 25.168498] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11013 12:18:29.323844 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11015 12:18:29.334385 /lava-11893107/1/../bin/lava-test-case
11016 12:18:29.340758 <8>[ 25.185302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11017 12:18:29.341433 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11019 12:18:30.354207 /lava-11893107/1/../bin/lava-test-case
11020 12:18:30.360572 <8>[ 26.204744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11021 12:18:30.361270 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11023 12:18:30.380065 /lava-11893107/1/../bin/lava-tes<8>[ 26.223406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11024 12:18:30.380630 t-case
11025 12:18:30.381229 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11027 12:18:30.390039 /lava-11893107/1/../bin/lava-test-case
11028 12:18:30.396535 <8>[ 26.240943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11029 12:18:30.397266 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11031 12:18:31.410301 /lava-11893107/1/../bin/lava-test-case
11032 12:18:31.417103 <8>[ 27.261247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11033 12:18:31.417853 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11035 12:18:31.437336 /lava-11893107/1/../bin/lava-tes<8>[ 27.280481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11036 12:18:31.437767 t-case
11037 12:18:31.438354 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11039 12:18:31.455904 /lava-11893107/1/../bin/lava-tes<8>[ 27.298964] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11040 12:18:31.456487 t-case
11041 12:18:31.457337 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11043 12:18:31.471667 /lava-11893107/1/../bin/lava-tes<8>[ 27.314895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11044 12:18:31.472094 t-case
11045 12:18:31.472736 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11047 12:18:31.491773 /lava-11893107/1/../bin/lava-tes<8>[ 27.334910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11048 12:18:31.492239 t-case
11049 12:18:31.492837 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11051 12:18:31.509504 /lava-11893107/1/../bin/lava-tes<8>[ 27.352840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11052 12:18:31.510189 t-case
11053 12:18:31.510848 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11055 12:18:31.519007 /lava-11893107/1/../bin/lava-test-case
11056 12:18:31.525642 <8>[ 27.370014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11057 12:18:31.526378 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11059 12:18:31.535551 /lava-11893107/1/../bin/lava-test-case
11060 12:18:31.541901 <8>[ 27.386072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11061 12:18:31.542636 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11063 12:18:31.561753 /lava-11893107/1/../bin/lava-tes<8>[ 27.405326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11064 12:18:31.562356 t-case
11065 12:18:31.563001 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11067 12:18:31.576626 /lava-11893107/1/../bin/lava-test-case
11068 12:18:31.583034 <8>[ 27.427479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11069 12:18:31.583766 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11071 12:18:31.600120 /lava-11893107/1/../bin/lava-tes<8>[ 27.443025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11072 12:18:31.600592 t-case
11073 12:18:31.601180 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11075 12:18:31.609187 /lava-11893107/1/../bin/lava-test-case
11076 12:18:31.616275 <8>[ 27.460933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11077 12:18:31.616957 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11079 12:18:31.633562 /lava-11893107/1/../bin/lava-tes<8>[ 27.477035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11080 12:18:31.633988 t-case
11081 12:18:31.634572 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11083 12:18:31.643825 /lava-11893107/1/../bin/lava-test-case
11084 12:18:31.650089 <8>[ 27.495175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11085 12:18:31.650915 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11087 12:18:31.660618 /lava-11893107/1/../bin/lava-test-case
11088 12:18:31.667677 <8>[ 27.511315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11089 12:18:31.668624 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11091 12:18:31.680994 /lava-11893107/1/../bin/lava-test-case
11092 12:18:31.687504 <8>[ 27.532613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11093 12:18:31.688309 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11095 12:18:31.696906 /lava-11893107/1/../bin/lava-test-case
11096 12:18:31.703750 <8>[ 27.548143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11097 12:18:31.704649 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11099 12:18:31.716674 /lava-11893107/1/../bin/lava-test-case
11100 12:18:31.722914 <8>[ 27.567683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11101 12:18:31.723645 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11103 12:18:31.738531 /lava-11893107/1/../bin/lava-tes<8>[ 27.581837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11104 12:18:31.739109 t-case
11105 12:18:31.739762 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11107 12:18:31.751627 /lava-11893107/1/../bin/lava-test-case
11108 12:18:31.757928 <8>[ 27.604137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11109 12:18:31.758765 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11111 12:18:31.769827 /lava-11893107/1/../bin/lava-test-case
11112 12:18:31.776644 <8>[ 27.620635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11113 12:18:31.777500 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11115 12:18:32.789385 /lava-11893107/1/../bin/lava-test-case
11116 12:18:32.796312 <8>[ 28.641490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11117 12:18:32.797064 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11119 12:18:33.809314 /lava-11893107/1/../bin/lava-test-case
11120 12:18:33.815757 <8>[ 29.659976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11121 12:18:33.816643 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11123 12:18:33.827703 /lava-11893107/1/../bin/lava-test-case
11124 12:18:33.834609 <8>[ 29.680598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11125 12:18:33.835471 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11127 12:18:33.846044 /lava-11893107/1/../bin/lava-test-case
11128 12:18:33.852549 <8>[ 29.696901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11129 12:18:33.853410 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11131 12:18:33.864913 /lava-11893107/1/../bin/lava-test-case
11132 12:18:33.871145 <8>[ 29.714953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11133 12:18:33.872325 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11135 12:18:33.881449 /lava-11893107/1/../bin/lava-test-case
11136 12:18:33.891652 <8>[ 29.736212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11137 12:18:33.892531 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11139 12:18:33.908543 /lava-11893107/1/../bin/lava-tes<8>[ 29.752096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11140 12:18:33.909133 t-case
11141 12:18:33.909794 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11143 12:18:33.919063 /lava-11893107/1/../bin/lava-test-case
11144 12:18:33.925558 <8>[ 29.770492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11145 12:18:33.926420 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11147 12:18:33.934624 /lava-11893107/1/../bin/lava-test-case
11148 12:18:33.940954 <8>[ 29.785712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11149 12:18:33.941809 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11151 12:18:33.950917 /lava-11893107/1/../bin/lava-test-case
11152 12:18:33.957942 <8>[ 29.802877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11153 12:18:33.958820 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11155 12:18:33.966127 /lava-11893107/1/../bin/lava-test-case
11156 12:18:33.973059 <8>[ 29.818062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11157 12:18:33.973928 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11159 12:18:33.985426 /lava-11893107/1/../bin/lava-test-case
11160 12:18:33.991639 <8>[ 29.835736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11161 12:18:33.992513 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11163 12:18:34.005740 /lava-11893107/1/../bin/lava-tes<8>[ 29.849160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11164 12:18:34.006319 t-case
11165 12:18:34.006975 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11167 12:18:34.024812 /lava-11893107/1/../bin/lava-tes<8>[ 29.868362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11168 12:18:34.025410 t-case
11169 12:18:34.026068 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11171 12:18:34.032772 /lava-11893107/1/../bin/lava-test-case
11172 12:18:34.039379 <8>[ 29.885411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11173 12:18:34.040112 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11175 12:18:34.056562 /lava-11893107/1/../bin/lava-test-case
11176 12:18:34.062960 <8>[ 29.907520] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11177 12:18:34.063791 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11179 12:18:34.071598 /lava-11893107/1/../bin/lava-test-case
11180 12:18:34.077976 <8>[ 29.922678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11181 12:18:34.078829 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11183 12:18:34.089365 /lava-11893107/1/../bin/lava-test-case
11184 12:18:34.096342 <8>[ 29.940242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11185 12:18:34.097188 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11187 12:18:34.111588 /lava-11893107/1/../bin/lava-tes<8>[ 29.954979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11188 12:18:34.112163 t-case
11189 12:18:34.112884 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11191 12:18:34.121486 /lava-11893107/1/../bin/lava-test-case
11192 12:18:34.128222 <8>[ 29.973017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11193 12:18:34.129075 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11195 12:18:34.136279 /lava-11893107/1/../bin/lava-test-case
11196 12:18:34.145873 <8>[ 29.989756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11197 12:18:34.146726 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11199 12:18:34.164001 /lava-11893107/1/../bin/lava-tes<8>[ 30.007291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11200 12:18:34.164617 t-case
11201 12:18:34.165268 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11203 12:18:35.174076 /lava-11893107/1/../bin/lava-test-case
11204 12:18:35.180368 <8>[ 31.025364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11205 12:18:35.180648 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11207 12:18:36.193554 /lava-11893107/1/../bin/lava-test-case
11208 12:18:36.200150 <8>[ 32.046016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11209 12:18:36.200947 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11210 12:18:36.201418 Bad test result: blocked
11211 12:18:36.209453 /lava-11893107/1/../bin/lava-test-case
11212 12:18:36.215947 <8>[ 32.060674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11213 12:18:36.216714 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11215 12:18:37.233204 /lava-11893107/1/../bin/lava-test-case
11216 12:18:37.239740 <8>[ 33.086151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11217 12:18:37.240004 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11219 12:18:37.248351 /lava-11893107/1/../bin/lava-test-case
11220 12:18:37.255069 <8>[ 33.100197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11221 12:18:37.255342 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11223 12:18:37.267508 /lava-11893107/1/../bin/lava-test-case
11224 12:18:37.273907 <8>[ 33.119400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11225 12:18:37.274173 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11227 12:18:37.284406 /lava-11893107/1/../bin/lava-test-case
11228 12:18:37.291502 <8>[ 33.136490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11229 12:18:37.291767 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11231 12:18:37.302036 /lava-11893107/1/../bin/lava-test-case
11232 12:18:37.308374 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11234 12:18:37.311503 <8>[ 33.155269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11235 12:18:37.320499 /lava-11893107/1/../bin/lava-test-case
11236 12:18:37.327007 <8>[ 33.172309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11237 12:18:37.327261 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11239 12:18:37.344406 /lava-11893107/1/../bin/lava-tes<8>[ 33.189178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11240 12:18:37.344489 t-case
11241 12:18:37.344723 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11243 12:18:38.355748 /lava-11893107/1/../bin/lava-test-case
11244 12:18:38.362075 <8>[ 34.207567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11245 12:18:38.362340 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11247 12:18:38.372439 /lava-11893107/1/../bin/lava-test-case
11248 12:18:38.379018 <8>[ 34.224378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11249 12:18:38.379261 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11251 12:18:39.395023 /lava-11893107/1/../bin/lava-test-case
11252 12:18:39.401456 <8>[ 35.246768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11253 12:18:39.401763 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11255 12:18:39.418302 /lava-11893107/1/../bin/lava-tes<8>[ 35.262579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11256 12:18:39.418484 t-case
11257 12:18:39.418763 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11259 12:18:40.431459 /lava-11893107/1/../bin/lava-test-case
11260 12:18:40.438250 <8>[ 36.283008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11261 12:18:40.439029 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11263 12:18:40.455000 /lava-11893107/1/../bin/lava-tes<8>[ 36.299052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11264 12:18:40.455575 t-case
11265 12:18:40.456260 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11267 12:18:41.465723 /lava-11893107/1/../bin/lava-test-case
11268 12:18:41.472306 <8>[ 37.317750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11269 12:18:41.472571 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11271 12:18:41.485469 /lava-11893107/1/../bin/lava-test-case
11272 12:18:41.492134 <8>[ 37.337955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11273 12:18:41.492435 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11275 12:18:41.506679 /lava-11893107/1/../bin/lava-tes<8>[ 37.354893] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11276 12:18:41.506933 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11278 12:18:41.509785 t-case
11279 12:18:41.524871 /lava-11893107/1/../bin/lava-tes<8>[ 37.373260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11280 12:18:41.525123 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11282 12:18:41.528312 t-case
11283 12:18:41.534740 /lava-11893107/1/../bin/lava-test-case
11284 12:18:41.541288 <8>[ 37.387297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11285 12:18:41.541541 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11287 12:18:41.552246 /lava-11893107/1/../bin/lava-test-case
11288 12:18:41.558620 <8>[ 37.405691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11289 12:18:41.558872 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11291 12:18:41.569543 /lava-11893107/1/../bin/lava-test-case
11292 12:18:41.576114 <8>[ 37.421445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11293 12:18:41.576435 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11295 12:18:41.588487 /lava-11893107/1/../bin/lava-test-case
11296 12:18:41.595025 <8>[ 37.441951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11297 12:18:41.595345 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11299 12:18:41.605414 /lava-11893107/1/../bin/lava-test-case
11300 12:18:41.611901 <8>[ 37.457220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11301 12:18:41.612471 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11303 12:18:41.622443 /lava-11893107/1/../bin/lava-test-case
11304 12:18:41.628844 <8>[ 37.475766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11305 12:18:41.629097 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11307 12:18:41.633402 + set +x
11308 12:18:41.637404 Received signal: <ENDRUN> 1_bootrr 11893107_1.5.2.3.5
11309 12:18:41.637495 Ending use of test pattern.
11310 12:18:41.637561 Ending test lava.1_bootrr (11893107_1.5.2.3.5), duration 20.34
11312 12:18:41.640160 <8>[ 37.486105] <LAVA_SIGNAL_ENDRUN 1_bootrr 11893107_1.5.2.3.5>
11313 12:18:41.640255 <LAVA_TEST_RUNNER EXIT>
11314 12:18:41.640489 ok: lava_test_shell seems to have completed
11315 12:18:41.641454 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11316 12:18:41.641598 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11317 12:18:41.641685 end: 4 lava-test-retry (duration 00:00:21) [common]
11318 12:18:41.641774 start: 5 finalize (timeout 00:08:05) [common]
11319 12:18:41.641861 start: 5.1 power-off (timeout 00:00:30) [common]
11320 12:18:41.642012 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11321 12:18:41.717514 >> Command sent successfully.
11322 12:18:41.719929 Returned 0 in 0 seconds
11323 12:18:41.820421 end: 5.1 power-off (duration 00:00:00) [common]
11325 12:18:41.821073 start: 5.2 read-feedback (timeout 00:08:05) [common]
11326 12:18:41.821490 Listened to connection for namespace 'common' for up to 1s
11327 12:18:41.821857 Listened to connection for namespace 'common' for up to 1s
11328 12:18:42.822505 Finalising connection for namespace 'common'
11329 12:18:42.823166 Disconnecting from shell: Finalise
11330 12:18:42.823593 / #
11331 12:18:42.924700 end: 5.2 read-feedback (duration 00:00:01) [common]
11332 12:18:42.925389 end: 5 finalize (duration 00:00:01) [common]
11333 12:18:42.926059 Cleaning after the job
11334 12:18:42.926635 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/ramdisk
11335 12:18:42.942138 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/kernel
11336 12:18:42.969134 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/dtb
11337 12:18:42.969461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893107/tftp-deploy-_8h5mw6e/modules
11338 12:18:42.980698 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893107
11339 12:18:43.030055 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893107
11340 12:18:43.030214 Job finished correctly