Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 37
- Errors: 1
- Boot result: PASS
1 12:16:41.684610 lava-dispatcher, installed at version: 2023.08
2 12:16:41.684817 start: 0 validate
3 12:16:41.684971 Start time: 2023-10-27 12:16:41.684938+00:00 (UTC)
4 12:16:41.685116 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:16:41.685242 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:16:41.947070 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:16:41.947823 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:17:06.728870 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:17:06.729060 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:17:06.993870 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:17:06.994046 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:17:07.541194 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:17:07.541366 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:17:10.548791 validate duration: 28.86
16 12:17:10.549140 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:17:10.549269 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:17:10.549385 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:17:10.549550 Not decompressing ramdisk as can be used compressed.
20 12:17:10.549649 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 12:17:10.549741 saving as /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/ramdisk/initrd.cpio.gz
22 12:17:10.549805 total size: 4665412 (4 MB)
23 12:17:10.816842 progress 0 % (0 MB)
24 12:17:10.818236 progress 5 % (0 MB)
25 12:17:10.819446 progress 10 % (0 MB)
26 12:17:10.823822 progress 15 % (0 MB)
27 12:17:10.826012 progress 20 % (0 MB)
28 12:17:10.827227 progress 25 % (1 MB)
29 12:17:10.828431 progress 30 % (1 MB)
30 12:17:10.829681 progress 35 % (1 MB)
31 12:17:10.831215 progress 40 % (1 MB)
32 12:17:10.832819 progress 45 % (2 MB)
33 12:17:10.834401 progress 50 % (2 MB)
34 12:17:10.836546 progress 55 % (2 MB)
35 12:17:10.838071 progress 60 % (2 MB)
36 12:17:10.839776 progress 65 % (2 MB)
37 12:17:10.841700 progress 70 % (3 MB)
38 12:17:10.843412 progress 75 % (3 MB)
39 12:17:10.845429 progress 80 % (3 MB)
40 12:17:10.847176 progress 85 % (3 MB)
41 12:17:10.848796 progress 90 % (4 MB)
42 12:17:10.851227 progress 95 % (4 MB)
43 12:17:10.852466 progress 100 % (4 MB)
44 12:17:10.852629 4 MB downloaded in 0.30 s (14.69 MB/s)
45 12:17:10.852777 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:17:10.853061 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:17:10.853149 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:17:10.853234 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:17:10.853351 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:17:10.853420 saving as /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/kernel/Image
52 12:17:10.853480 total size: 49236480 (46 MB)
53 12:17:10.853541 No compression specified
54 12:17:10.854668 progress 0 % (0 MB)
55 12:17:10.867222 progress 5 % (2 MB)
56 12:17:10.879671 progress 10 % (4 MB)
57 12:17:10.892110 progress 15 % (7 MB)
58 12:17:10.904808 progress 20 % (9 MB)
59 12:17:10.921933 progress 25 % (11 MB)
60 12:17:10.935025 progress 30 % (14 MB)
61 12:17:10.948030 progress 35 % (16 MB)
62 12:17:10.960662 progress 40 % (18 MB)
63 12:17:10.973188 progress 45 % (21 MB)
64 12:17:10.985554 progress 50 % (23 MB)
65 12:17:10.998300 progress 55 % (25 MB)
66 12:17:11.010923 progress 60 % (28 MB)
67 12:17:11.023791 progress 65 % (30 MB)
68 12:17:11.036579 progress 70 % (32 MB)
69 12:17:11.049185 progress 75 % (35 MB)
70 12:17:11.061782 progress 80 % (37 MB)
71 12:17:11.074075 progress 85 % (39 MB)
72 12:17:11.086387 progress 90 % (42 MB)
73 12:17:11.098693 progress 95 % (44 MB)
74 12:17:11.111067 progress 100 % (46 MB)
75 12:17:11.111287 46 MB downloaded in 0.26 s (182.14 MB/s)
76 12:17:11.111441 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:17:11.111702 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:17:11.111827 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:17:11.111945 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:17:11.112087 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:17:11.112158 saving as /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/dtb/mt8192-asurada-spherion-r0.dtb
83 12:17:11.112224 total size: 47278 (0 MB)
84 12:17:11.112286 No compression specified
85 12:17:11.113576 progress 69 % (0 MB)
86 12:17:11.113854 progress 100 % (0 MB)
87 12:17:11.114010 0 MB downloaded in 0.00 s (25.27 MB/s)
88 12:17:11.114133 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:17:11.114354 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:17:11.114438 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:17:11.114521 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:17:11.114633 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 12:17:11.114704 saving as /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/nfsrootfs/full.rootfs.tar
95 12:17:11.114766 total size: 125290964 (119 MB)
96 12:17:11.114829 Using unxz to decompress xz
97 12:17:11.120556 progress 0 % (0 MB)
98 12:17:11.445838 progress 5 % (6 MB)
99 12:17:11.782565 progress 10 % (11 MB)
100 12:17:12.119182 progress 15 % (17 MB)
101 12:17:12.310954 progress 20 % (23 MB)
102 12:17:12.486768 progress 25 % (29 MB)
103 12:17:12.845164 progress 30 % (35 MB)
104 12:17:13.203843 progress 35 % (41 MB)
105 12:17:13.598425 progress 40 % (47 MB)
106 12:17:13.975559 progress 45 % (53 MB)
107 12:17:14.361615 progress 50 % (59 MB)
108 12:17:14.714054 progress 55 % (65 MB)
109 12:17:15.091090 progress 60 % (71 MB)
110 12:17:15.429520 progress 65 % (77 MB)
111 12:17:15.789432 progress 70 % (83 MB)
112 12:17:16.179211 progress 75 % (89 MB)
113 12:17:16.608454 progress 80 % (95 MB)
114 12:17:17.024204 progress 85 % (101 MB)
115 12:17:17.276159 progress 90 % (107 MB)
116 12:17:17.624655 progress 95 % (113 MB)
117 12:17:17.992682 progress 100 % (119 MB)
118 12:17:17.998440 119 MB downloaded in 6.88 s (17.36 MB/s)
119 12:17:17.998701 end: 1.4.1 http-download (duration 00:00:07) [common]
121 12:17:17.998962 end: 1.4 download-retry (duration 00:00:07) [common]
122 12:17:17.999054 start: 1.5 download-retry (timeout 00:09:53) [common]
123 12:17:17.999170 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 12:17:17.999323 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:17:17.999399 saving as /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/modules/modules.tar
126 12:17:17.999462 total size: 8625084 (8 MB)
127 12:17:17.999528 Using unxz to decompress xz
128 12:17:18.280932 progress 0 % (0 MB)
129 12:17:18.302415 progress 5 % (0 MB)
130 12:17:18.325479 progress 10 % (0 MB)
131 12:17:18.351616 progress 15 % (1 MB)
132 12:17:18.376772 progress 20 % (1 MB)
133 12:17:18.401703 progress 25 % (2 MB)
134 12:17:18.427528 progress 30 % (2 MB)
135 12:17:18.454218 progress 35 % (2 MB)
136 12:17:18.478833 progress 40 % (3 MB)
137 12:17:18.502435 progress 45 % (3 MB)
138 12:17:18.528455 progress 50 % (4 MB)
139 12:17:18.553222 progress 55 % (4 MB)
140 12:17:18.577617 progress 60 % (4 MB)
141 12:17:18.601762 progress 65 % (5 MB)
142 12:17:18.626143 progress 70 % (5 MB)
143 12:17:18.650064 progress 75 % (6 MB)
144 12:17:18.675827 progress 80 % (6 MB)
145 12:17:18.704280 progress 85 % (7 MB)
146 12:17:18.730530 progress 90 % (7 MB)
147 12:17:18.756030 progress 95 % (7 MB)
148 12:17:18.778938 progress 100 % (8 MB)
149 12:17:18.783765 8 MB downloaded in 0.78 s (10.49 MB/s)
150 12:17:18.784077 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:17:18.784471 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:17:18.784607 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 12:17:18.784750 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 12:17:20.739821 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11893118/extract-nfsrootfs-o9tlk6ze
156 12:17:20.740035 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:17:20.740158 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 12:17:20.740335 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s
159 12:17:20.740482 makedir: /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin
160 12:17:20.740599 makedir: /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/tests
161 12:17:20.740741 makedir: /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/results
162 12:17:20.740884 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-add-keys
163 12:17:20.741111 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-add-sources
164 12:17:20.741282 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-background-process-start
165 12:17:20.741451 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-background-process-stop
166 12:17:20.741618 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-common-functions
167 12:17:20.741757 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-echo-ipv4
168 12:17:20.741898 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-install-packages
169 12:17:20.742041 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-installed-packages
170 12:17:20.742181 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-os-build
171 12:17:20.742321 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-probe-channel
172 12:17:20.742466 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-probe-ip
173 12:17:20.742634 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-target-ip
174 12:17:20.742801 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-target-mac
175 12:17:20.742964 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-target-storage
176 12:17:20.743105 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-test-case
177 12:17:20.743245 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-test-event
178 12:17:20.743388 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-test-feedback
179 12:17:20.743555 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-test-raise
180 12:17:20.743723 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-test-reference
181 12:17:20.743897 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-test-runner
182 12:17:20.744065 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-test-set
183 12:17:20.744232 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-test-shell
184 12:17:20.744401 Updating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-install-packages (oe)
185 12:17:20.744606 Updating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/bin/lava-installed-packages (oe)
186 12:17:20.744776 Creating /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/environment
187 12:17:20.744911 LAVA metadata
188 12:17:20.745039 - LAVA_JOB_ID=11893118
189 12:17:20.745119 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:17:20.745248 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 12:17:20.745324 skipped lava-vland-overlay
192 12:17:20.745445 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:17:20.745570 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 12:17:20.745666 skipped lava-multinode-overlay
195 12:17:20.745785 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:17:20.745907 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 12:17:20.746021 Loading test definitions
198 12:17:20.746155 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 12:17:20.746263 Using /lava-11893118 at stage 0
200 12:17:20.746686 uuid=11893118_1.6.2.3.1 testdef=None
201 12:17:20.746812 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:17:20.746938 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 12:17:20.747665 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:17:20.748034 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 12:17:20.748677 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:17:20.749335 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 12:17:20.749960 runner path: /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/0/tests/0_dmesg test_uuid 11893118_1.6.2.3.1
210 12:17:20.750127 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:17:20.750382 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 12:17:20.750491 Using /lava-11893118 at stage 1
214 12:17:20.750912 uuid=11893118_1.6.2.3.5 testdef=None
215 12:17:20.751036 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 12:17:20.751163 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 12:17:20.751857 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 12:17:20.752220 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 12:17:20.752863 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 12:17:20.753162 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 12:17:20.753792 runner path: /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/1/tests/1_bootrr test_uuid 11893118_1.6.2.3.5
224 12:17:20.753955 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 12:17:20.754182 Creating lava-test-runner.conf files
227 12:17:20.754263 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/0 for stage 0
228 12:17:20.754376 - 0_dmesg
229 12:17:20.754492 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893118/lava-overlay-r9931e7s/lava-11893118/1 for stage 1
230 12:17:20.754625 - 1_bootrr
231 12:17:20.754761 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 12:17:20.754886 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 12:17:20.762656 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 12:17:20.762771 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 12:17:20.762871 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 12:17:20.762973 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 12:17:20.763075 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 12:17:20.884185 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 12:17:20.884570 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 12:17:20.884706 extracting modules file /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893118/extract-nfsrootfs-o9tlk6ze
241 12:17:21.206138 extracting modules file /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893118/extract-overlay-ramdisk-yvqrg_yt/ramdisk
242 12:17:21.421222 end: 1.6.4 extract-modules (duration 00:00:01) [common]
243 12:17:21.421401 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 12:17:21.421502 [common] Applying overlay to NFS
245 12:17:21.421596 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893118/compress-overlay-xlps5j64/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893118/extract-nfsrootfs-o9tlk6ze
246 12:17:22.416050 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
247 12:17:22.416219 start: 1.6.6 configure-preseed-file (timeout 00:09:48) [common]
248 12:17:22.416324 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 12:17:22.416420 start: 1.6.7 compress-ramdisk (timeout 00:09:48) [common]
250 12:17:22.416504 Building ramdisk /var/lib/lava/dispatcher/tmp/11893118/extract-overlay-ramdisk-yvqrg_yt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893118/extract-overlay-ramdisk-yvqrg_yt/ramdisk
251 12:17:24.206834 >> 119370 blocks
252 12:17:26.150999 rename /var/lib/lava/dispatcher/tmp/11893118/extract-overlay-ramdisk-yvqrg_yt/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/ramdisk/ramdisk.cpio.gz
253 12:17:26.151408 end: 1.6.7 compress-ramdisk (duration 00:00:04) [common]
254 12:17:26.151540 start: 1.6.8 prepare-kernel (timeout 00:09:44) [common]
255 12:17:26.151646 start: 1.6.8.1 prepare-fit (timeout 00:09:44) [common]
256 12:17:26.151768 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/kernel/Image'
257 12:17:40.320078 Returned 0 in 14 seconds
258 12:17:40.420659 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/kernel/image.itb
259 12:17:40.893501 output: FIT description: Kernel Image image with one or more FDT blobs
260 12:17:40.893852 output: Created: Fri Oct 27 13:17:40 2023
261 12:17:40.893946 output: Image 0 (kernel-1)
262 12:17:40.894050 output: Description:
263 12:17:40.894140 output: Created: Fri Oct 27 13:17:40 2023
264 12:17:40.894206 output: Type: Kernel Image
265 12:17:40.894269 output: Compression: lzma compressed
266 12:17:40.894332 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
267 12:17:40.894394 output: Architecture: AArch64
268 12:17:40.894485 output: OS: Linux
269 12:17:40.894546 output: Load Address: 0x00000000
270 12:17:40.894602 output: Entry Point: 0x00000000
271 12:17:40.894662 output: Hash algo: crc32
272 12:17:40.894719 output: Hash value: d33b93ae
273 12:17:40.894775 output: Image 1 (fdt-1)
274 12:17:40.894833 output: Description: mt8192-asurada-spherion-r0
275 12:17:40.894888 output: Created: Fri Oct 27 13:17:40 2023
276 12:17:40.894943 output: Type: Flat Device Tree
277 12:17:40.894997 output: Compression: uncompressed
278 12:17:40.895051 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 12:17:40.895104 output: Architecture: AArch64
280 12:17:40.895158 output: Hash algo: crc32
281 12:17:40.895211 output: Hash value: cc4352de
282 12:17:40.895264 output: Image 2 (ramdisk-1)
283 12:17:40.895317 output: Description: unavailable
284 12:17:40.895371 output: Created: Fri Oct 27 13:17:40 2023
285 12:17:40.895424 output: Type: RAMDisk Image
286 12:17:40.895478 output: Compression: Unknown Compression
287 12:17:40.895532 output: Data Size: 17797451 Bytes = 17380.32 KiB = 16.97 MiB
288 12:17:40.895586 output: Architecture: AArch64
289 12:17:40.895639 output: OS: Linux
290 12:17:40.895693 output: Load Address: unavailable
291 12:17:40.895747 output: Entry Point: unavailable
292 12:17:40.895800 output: Hash algo: crc32
293 12:17:40.895853 output: Hash value: c8f06527
294 12:17:40.895923 output: Default Configuration: 'conf-1'
295 12:17:40.896008 output: Configuration 0 (conf-1)
296 12:17:40.896110 output: Description: mt8192-asurada-spherion-r0
297 12:17:40.896164 output: Kernel: kernel-1
298 12:17:40.896217 output: Init Ramdisk: ramdisk-1
299 12:17:40.896270 output: FDT: fdt-1
300 12:17:40.896323 output: Loadables: kernel-1
301 12:17:40.896377 output:
302 12:17:40.896564 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
303 12:17:40.896661 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
304 12:17:40.896800 end: 1.6 prepare-tftp-overlay (duration 00:00:22) [common]
305 12:17:40.896900 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:30) [common]
306 12:17:40.897021 No LXC device requested
307 12:17:40.897103 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 12:17:40.897190 start: 1.8 deploy-device-env (timeout 00:09:30) [common]
309 12:17:40.897272 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 12:17:40.897342 Checking files for TFTP limit of 4294967296 bytes.
311 12:17:40.897833 end: 1 tftp-deploy (duration 00:00:30) [common]
312 12:17:40.897940 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 12:17:40.898034 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 12:17:40.898160 substitutions:
315 12:17:40.898231 - {DTB}: 11893118/tftp-deploy-wopfvvj9/dtb/mt8192-asurada-spherion-r0.dtb
316 12:17:40.898311 - {INITRD}: 11893118/tftp-deploy-wopfvvj9/ramdisk/ramdisk.cpio.gz
317 12:17:40.898404 - {KERNEL}: 11893118/tftp-deploy-wopfvvj9/kernel/Image
318 12:17:40.898533 - {LAVA_MAC}: None
319 12:17:40.898611 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11893118/extract-nfsrootfs-o9tlk6ze
320 12:17:40.898672 - {NFS_SERVER_IP}: 192.168.201.1
321 12:17:40.898730 - {PRESEED_CONFIG}: None
322 12:17:40.898789 - {PRESEED_LOCAL}: None
323 12:17:40.898846 - {RAMDISK}: 11893118/tftp-deploy-wopfvvj9/ramdisk/ramdisk.cpio.gz
324 12:17:40.898902 - {ROOT_PART}: None
325 12:17:40.898958 - {ROOT}: None
326 12:17:40.899013 - {SERVER_IP}: 192.168.201.1
327 12:17:40.899098 - {TEE}: None
328 12:17:40.899153 Parsed boot commands:
329 12:17:40.899209 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 12:17:40.899387 Parsed boot commands: tftpboot 192.168.201.1 11893118/tftp-deploy-wopfvvj9/kernel/image.itb 11893118/tftp-deploy-wopfvvj9/kernel/cmdline
331 12:17:40.899477 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 12:17:40.899564 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 12:17:40.899688 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 12:17:40.899775 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 12:17:40.899846 Not connected, no need to disconnect.
336 12:17:40.899920 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 12:17:40.900002 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 12:17:40.900069 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
339 12:17:40.903465 Setting prompt string to ['lava-test: # ']
340 12:17:40.903836 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 12:17:40.903948 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 12:17:40.904062 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 12:17:40.904169 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 12:17:40.904370 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
345 12:17:46.035866 >> Command sent successfully.
346 12:17:46.039010 Returned 0 in 5 seconds
347 12:17:46.139413 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 12:17:46.139838 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 12:17:46.139941 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 12:17:46.140031 Setting prompt string to 'Starting depthcharge on Spherion...'
352 12:17:46.140102 Changing prompt to 'Starting depthcharge on Spherion...'
353 12:17:46.140172 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 12:17:46.140446 [Enter `^Ec?' for help]
355 12:17:46.313422
356 12:17:46.313587
357 12:17:46.313668 F0: 102B 0000
358 12:17:46.313738
359 12:17:46.313804 F3: 1001 0000 [0200]
360 12:17:46.316493
361 12:17:46.316582 F3: 1001 0000
362 12:17:46.316652
363 12:17:46.316716 F7: 102D 0000
364 12:17:46.316778
365 12:17:46.319689 F1: 0000 0000
366 12:17:46.319778
367 12:17:46.319847 V0: 0000 0000 [0001]
368 12:17:46.319911
369 12:17:46.323235 00: 0007 8000
370 12:17:46.323328
371 12:17:46.323398 01: 0000 0000
372 12:17:46.323463
373 12:17:46.326475 BP: 0C00 0209 [0000]
374 12:17:46.326562
375 12:17:46.326632 G0: 1182 0000
376 12:17:46.326696
377 12:17:46.329975 EC: 0000 0021 [4000]
378 12:17:46.330063
379 12:17:46.330132 S7: 0000 0000 [0000]
380 12:17:46.330196
381 12:17:46.333549 CC: 0000 0000 [0001]
382 12:17:46.333642
383 12:17:46.333712 T0: 0000 0040 [010F]
384 12:17:46.333777
385 12:17:46.333839 Jump to BL
386 12:17:46.333901
387 12:17:46.360328
388 12:17:46.360482
389 12:17:46.360555
390 12:17:46.367748 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 12:17:46.371836 ARM64: Exception handlers installed.
392 12:17:46.375318 ARM64: Testing exception
393 12:17:46.378590 ARM64: Done test exception
394 12:17:46.385152 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 12:17:46.395585 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 12:17:46.401967 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 12:17:46.411952 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 12:17:46.418742 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 12:17:46.425347 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 12:17:46.437130 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 12:17:46.443843 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 12:17:46.462939 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 12:17:46.466154 WDT: Last reset was cold boot
404 12:17:46.469596 SPI1(PAD0) initialized at 2873684 Hz
405 12:17:46.473114 SPI5(PAD0) initialized at 992727 Hz
406 12:17:46.476566 VBOOT: Loading verstage.
407 12:17:46.482887 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 12:17:46.486456 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 12:17:46.489927 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 12:17:46.493143 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 12:17:46.500479 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 12:17:46.507350 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 12:17:46.517689 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 12:17:46.517823
415 12:17:46.517897
416 12:17:46.527710 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 12:17:46.531328 ARM64: Exception handlers installed.
418 12:17:46.535137 ARM64: Testing exception
419 12:17:46.535287 ARM64: Done test exception
420 12:17:46.541275 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 12:17:46.544692 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:17:46.558813 Probing TPM: . done!
423 12:17:46.558971 TPM ready after 0 ms
424 12:17:46.565385 Connected to device vid:did:rid of 1ae0:0028:00
425 12:17:46.572666 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 12:17:46.576568 Initialized TPM device CR50 revision 0
427 12:17:46.641968 tlcl_send_startup: Startup return code is 0
428 12:17:46.642130 TPM: setup succeeded
429 12:17:46.653511 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 12:17:46.661932 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 12:17:46.672567 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 12:17:46.681882 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 12:17:46.684528 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 12:17:46.693370 in-header: 03 07 00 00 08 00 00 00
435 12:17:46.697042 in-data: aa e4 47 04 13 02 00 00
436 12:17:46.700417 Chrome EC: UHEPI supported
437 12:17:46.708198 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 12:17:46.711745 in-header: 03 ad 00 00 08 00 00 00
439 12:17:46.715531 in-data: 00 20 20 08 00 00 00 00
440 12:17:46.715635 Phase 1
441 12:17:46.719321 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 12:17:46.726887 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 12:17:46.730785 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 12:17:46.734452 Recovery requested (1009000e)
445 12:17:46.742615 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 12:17:46.748011 tlcl_extend: response is 0
447 12:17:46.757109 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 12:17:46.763221 tlcl_extend: response is 0
449 12:17:46.769939 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 12:17:46.790483 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 12:17:46.797153 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 12:17:46.797290
453 12:17:46.797366
454 12:17:46.807569 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 12:17:46.810687 ARM64: Exception handlers installed.
456 12:17:46.810787 ARM64: Testing exception
457 12:17:46.814267 ARM64: Done test exception
458 12:17:46.835302 pmic_efuse_setting: Set efuses in 11 msecs
459 12:17:46.838630 pmwrap_interface_init: Select PMIF_VLD_RDY
460 12:17:46.845752 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 12:17:46.849061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 12:17:46.852719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 12:17:46.859316 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 12:17:46.862696 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 12:17:46.869925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 12:17:46.873692 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 12:17:46.878091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 12:17:46.881591 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 12:17:46.888729 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 12:17:46.892752 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 12:17:46.896701 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 12:17:46.899948 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 12:17:46.906672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 12:17:46.913778 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 12:17:46.920696 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 12:17:46.924268 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 12:17:46.932288 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 12:17:46.935767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 12:17:46.942551 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 12:17:46.946325 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 12:17:46.953167 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 12:17:46.959809 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 12:17:46.962987 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 12:17:46.969767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 12:17:46.973398 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 12:17:46.980226 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 12:17:46.983150 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 12:17:46.990410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 12:17:46.993546 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 12:17:47.000488 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 12:17:47.003509 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 12:17:47.010169 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 12:17:47.013337 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 12:17:47.020110 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 12:17:47.023482 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 12:17:47.029960 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 12:17:47.033301 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 12:17:47.040122 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 12:17:47.044049 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 12:17:47.047882 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 12:17:47.051101 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 12:17:47.057765 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 12:17:47.061014 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 12:17:47.064590 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 12:17:47.067658 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 12:17:47.074309 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 12:17:47.077860 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 12:17:47.081289 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 12:17:47.084766 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 12:17:47.091268 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 12:17:47.098043 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 12:17:47.107842 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 12:17:47.111337 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 12:17:47.118105 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 12:17:47.128179 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 12:17:47.131808 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 12:17:47.138126 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 12:17:47.141410 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 12:17:47.148121 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xa
520 12:17:47.155045 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 12:17:47.158205 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 12:17:47.161584 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 12:17:47.173117 [RTC]rtc_get_frequency_meter,154: input=15, output=772
524 12:17:47.182170 [RTC]rtc_get_frequency_meter,154: input=23, output=957
525 12:17:47.191344 [RTC]rtc_get_frequency_meter,154: input=19, output=864
526 12:17:47.201306 [RTC]rtc_get_frequency_meter,154: input=17, output=818
527 12:17:47.210295 [RTC]rtc_get_frequency_meter,154: input=16, output=794
528 12:17:47.214104 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
529 12:17:47.220588 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
530 12:17:47.223903 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
531 12:17:47.227017 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
532 12:17:47.230517 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
533 12:17:47.233770 ADC[4]: Raw value=902139 ID=7
534 12:17:47.237371 ADC[3]: Raw value=212810 ID=1
535 12:17:47.240499 RAM Code: 0x71
536 12:17:47.244118 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
537 12:17:47.247315 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
538 12:17:47.257367 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
539 12:17:47.263698 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
540 12:17:47.267361 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
541 12:17:47.270622 in-header: 03 07 00 00 08 00 00 00
542 12:17:47.273794 in-data: aa e4 47 04 13 02 00 00
543 12:17:47.277055 Chrome EC: UHEPI supported
544 12:17:47.283649 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
545 12:17:47.287382 in-header: 03 ed 00 00 08 00 00 00
546 12:17:47.290447 in-data: 80 20 60 08 00 00 00 00
547 12:17:47.293729 MRC: failed to locate region type 0.
548 12:17:47.300739 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
549 12:17:47.304567 DRAM-K: Running full calibration
550 12:17:47.308198 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
551 12:17:47.312111 header.status = 0x0
552 12:17:47.315574 header.version = 0x6 (expected: 0x6)
553 12:17:47.319940 header.size = 0xd00 (expected: 0xd00)
554 12:17:47.320076 header.flags = 0x0
555 12:17:47.326724 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
556 12:17:47.343793 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
557 12:17:47.351360 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
558 12:17:47.351509 dram_init: ddr_geometry: 2
559 12:17:47.355112 [EMI] MDL number = 2
560 12:17:47.359193 [EMI] Get MDL freq = 0
561 12:17:47.359298 dram_init: ddr_type: 0
562 12:17:47.362580 is_discrete_lpddr4: 1
563 12:17:47.365779 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
564 12:17:47.365878
565 12:17:47.365948
566 12:17:47.369069 [Bian_co] ETT version 0.0.0.1
567 12:17:47.372480 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
568 12:17:47.372582
569 12:17:47.375569 dramc_set_vcore_voltage set vcore to 650000
570 12:17:47.378998 Read voltage for 800, 4
571 12:17:47.379095 Vio18 = 0
572 12:17:47.379165 Vcore = 650000
573 12:17:47.382239 Vdram = 0
574 12:17:47.382329 Vddq = 0
575 12:17:47.382396 Vmddr = 0
576 12:17:47.385599 dram_init: config_dvfs: 1
577 12:17:47.389212 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
578 12:17:47.395786 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
579 12:17:47.398994 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
580 12:17:47.402681 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
581 12:17:47.405843 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
582 12:17:47.412830 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
583 12:17:47.412974 MEM_TYPE=3, freq_sel=18
584 12:17:47.416232 sv_algorithm_assistance_LP4_1600
585 12:17:47.419692 ============ PULL DRAM RESETB DOWN ============
586 12:17:47.423635 ========== PULL DRAM RESETB DOWN end =========
587 12:17:47.431236 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
588 12:17:47.431365 ===================================
589 12:17:47.435208 LPDDR4 DRAM CONFIGURATION
590 12:17:47.438608 ===================================
591 12:17:47.438715 EX_ROW_EN[0] = 0x0
592 12:17:47.442344 EX_ROW_EN[1] = 0x0
593 12:17:47.442440 LP4Y_EN = 0x0
594 12:17:47.445689 WORK_FSP = 0x0
595 12:17:47.445784 WL = 0x2
596 12:17:47.448920 RL = 0x2
597 12:17:47.449025 BL = 0x2
598 12:17:47.452861 RPST = 0x0
599 12:17:47.455580 RD_PRE = 0x0
600 12:17:47.455673 WR_PRE = 0x1
601 12:17:47.459040 WR_PST = 0x0
602 12:17:47.459133 DBI_WR = 0x0
603 12:17:47.462486 DBI_RD = 0x0
604 12:17:47.462576 OTF = 0x1
605 12:17:47.466091 ===================================
606 12:17:47.469222 ===================================
607 12:17:47.469315 ANA top config
608 12:17:47.472215 ===================================
609 12:17:47.475705 DLL_ASYNC_EN = 0
610 12:17:47.479281 ALL_SLAVE_EN = 1
611 12:17:47.482526 NEW_RANK_MODE = 1
612 12:17:47.485606 DLL_IDLE_MODE = 1
613 12:17:47.485703 LP45_APHY_COMB_EN = 1
614 12:17:47.489288 TX_ODT_DIS = 1
615 12:17:47.492445 NEW_8X_MODE = 1
616 12:17:47.495657 ===================================
617 12:17:47.499142 ===================================
618 12:17:47.502782 data_rate = 1600
619 12:17:47.505946 CKR = 1
620 12:17:47.506044 DQ_P2S_RATIO = 8
621 12:17:47.509120 ===================================
622 12:17:47.512633 CA_P2S_RATIO = 8
623 12:17:47.515975 DQ_CA_OPEN = 0
624 12:17:47.519217 DQ_SEMI_OPEN = 0
625 12:17:47.522492 CA_SEMI_OPEN = 0
626 12:17:47.522589 CA_FULL_RATE = 0
627 12:17:47.525989 DQ_CKDIV4_EN = 1
628 12:17:47.529242 CA_CKDIV4_EN = 1
629 12:17:47.533079 CA_PREDIV_EN = 0
630 12:17:47.536106 PH8_DLY = 0
631 12:17:47.539432 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
632 12:17:47.539532 DQ_AAMCK_DIV = 4
633 12:17:47.542779 CA_AAMCK_DIV = 4
634 12:17:47.546220 CA_ADMCK_DIV = 4
635 12:17:47.549457 DQ_TRACK_CA_EN = 0
636 12:17:47.552852 CA_PICK = 800
637 12:17:47.556081 CA_MCKIO = 800
638 12:17:47.556179 MCKIO_SEMI = 0
639 12:17:47.559802 PLL_FREQ = 3068
640 12:17:47.563018 DQ_UI_PI_RATIO = 32
641 12:17:47.566120 CA_UI_PI_RATIO = 0
642 12:17:47.569519 ===================================
643 12:17:47.573066 ===================================
644 12:17:47.576416 memory_type:LPDDR4
645 12:17:47.576511 GP_NUM : 10
646 12:17:47.579754 SRAM_EN : 1
647 12:17:47.579846 MD32_EN : 0
648 12:17:47.583472 ===================================
649 12:17:47.587081 [ANA_INIT] >>>>>>>>>>>>>>
650 12:17:47.590968 <<<<<< [CONFIGURE PHASE]: ANA_TX
651 12:17:47.594544 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
652 12:17:47.598222 ===================================
653 12:17:47.598325 data_rate = 1600,PCW = 0X7600
654 12:17:47.601825 ===================================
655 12:17:47.606006 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
656 12:17:47.613388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
657 12:17:47.616890 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
658 12:17:47.620704 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
659 12:17:47.623867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
660 12:17:47.626959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
661 12:17:47.630449 [ANA_INIT] flow start
662 12:17:47.634225 [ANA_INIT] PLL >>>>>>>>
663 12:17:47.634345 [ANA_INIT] PLL <<<<<<<<
664 12:17:47.637206 [ANA_INIT] MIDPI >>>>>>>>
665 12:17:47.640751 [ANA_INIT] MIDPI <<<<<<<<
666 12:17:47.640841 [ANA_INIT] DLL >>>>>>>>
667 12:17:47.644089 [ANA_INIT] flow end
668 12:17:47.647367 ============ LP4 DIFF to SE enter ============
669 12:17:47.650727 ============ LP4 DIFF to SE exit ============
670 12:17:47.653983 [ANA_INIT] <<<<<<<<<<<<<
671 12:17:47.657428 [Flow] Enable top DCM control >>>>>
672 12:17:47.660800 [Flow] Enable top DCM control <<<<<
673 12:17:47.664373 Enable DLL master slave shuffle
674 12:17:47.670500 ==============================================================
675 12:17:47.670597 Gating Mode config
676 12:17:47.677103 ==============================================================
677 12:17:47.677199 Config description:
678 12:17:47.687494 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
679 12:17:47.694215 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
680 12:17:47.700859 SELPH_MODE 0: By rank 1: By Phase
681 12:17:47.704012 ==============================================================
682 12:17:47.707463 GAT_TRACK_EN = 1
683 12:17:47.711051 RX_GATING_MODE = 2
684 12:17:47.714920 RX_GATING_TRACK_MODE = 2
685 12:17:47.718131 SELPH_MODE = 1
686 12:17:47.721630 PICG_EARLY_EN = 1
687 12:17:47.725119 VALID_LAT_VALUE = 1
688 12:17:47.728487 ==============================================================
689 12:17:47.732296 Enter into Gating configuration >>>>
690 12:17:47.736304 Exit from Gating configuration <<<<
691 12:17:47.739723 Enter into DVFS_PRE_config >>>>>
692 12:17:47.750718 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
693 12:17:47.754272 Exit from DVFS_PRE_config <<<<<
694 12:17:47.757896 Enter into PICG configuration >>>>
695 12:17:47.757993 Exit from PICG configuration <<<<
696 12:17:47.761998 [RX_INPUT] configuration >>>>>
697 12:17:47.765725 [RX_INPUT] configuration <<<<<
698 12:17:47.769058 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
699 12:17:47.776362 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
700 12:17:47.780177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
701 12:17:47.788177 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
702 12:17:47.795552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
703 12:17:47.799183 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
704 12:17:47.802719 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
705 12:17:47.806380 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
706 12:17:47.813440 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
707 12:17:47.817547 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
708 12:17:47.821362 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
709 12:17:47.825134 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
710 12:17:47.828654 ===================================
711 12:17:47.832247 LPDDR4 DRAM CONFIGURATION
712 12:17:47.836403 ===================================
713 12:17:47.836513 EX_ROW_EN[0] = 0x0
714 12:17:47.839570 EX_ROW_EN[1] = 0x0
715 12:17:47.839736 LP4Y_EN = 0x0
716 12:17:47.843300 WORK_FSP = 0x0
717 12:17:47.843420 WL = 0x2
718 12:17:47.843518 RL = 0x2
719 12:17:47.846919 BL = 0x2
720 12:17:47.847012 RPST = 0x0
721 12:17:47.850684 RD_PRE = 0x0
722 12:17:47.850803 WR_PRE = 0x1
723 12:17:47.854727 WR_PST = 0x0
724 12:17:47.854841 DBI_WR = 0x0
725 12:17:47.858835 DBI_RD = 0x0
726 12:17:47.858933 OTF = 0x1
727 12:17:47.862235 ===================================
728 12:17:47.866078 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
729 12:17:47.869603 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
730 12:17:47.873768 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
731 12:17:47.877279 ===================================
732 12:17:47.880734 LPDDR4 DRAM CONFIGURATION
733 12:17:47.884097 ===================================
734 12:17:47.884221 EX_ROW_EN[0] = 0x10
735 12:17:47.887876 EX_ROW_EN[1] = 0x0
736 12:17:47.887996 LP4Y_EN = 0x0
737 12:17:47.891987 WORK_FSP = 0x0
738 12:17:47.892099 WL = 0x2
739 12:17:47.895361 RL = 0x2
740 12:17:47.895472 BL = 0x2
741 12:17:47.899209 RPST = 0x0
742 12:17:47.899320 RD_PRE = 0x0
743 12:17:47.902993 WR_PRE = 0x1
744 12:17:47.903111 WR_PST = 0x0
745 12:17:47.906986 DBI_WR = 0x0
746 12:17:47.907080 DBI_RD = 0x0
747 12:17:47.907150 OTF = 0x1
748 12:17:47.910586 ===================================
749 12:17:47.917793 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
750 12:17:47.921844 nWR fixed to 40
751 12:17:47.921950 [ModeRegInit_LP4] CH0 RK0
752 12:17:47.925322 [ModeRegInit_LP4] CH0 RK1
753 12:17:47.929317 [ModeRegInit_LP4] CH1 RK0
754 12:17:47.929416 [ModeRegInit_LP4] CH1 RK1
755 12:17:47.932424 match AC timing 13
756 12:17:47.936349 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
757 12:17:47.940176 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
758 12:17:47.943798 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
759 12:17:47.950953 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
760 12:17:47.954700 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
761 12:17:47.958484 [EMI DOE] emi_dcm 0
762 12:17:47.962650 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
763 12:17:47.962783 ==
764 12:17:47.962880 Dram Type= 6, Freq= 0, CH_0, rank 0
765 12:17:47.969956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 12:17:47.970116 ==
767 12:17:47.973834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
768 12:17:47.980898 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
769 12:17:47.989702 [CA 0] Center 38 (7~69) winsize 63
770 12:17:47.993140 [CA 1] Center 38 (7~69) winsize 63
771 12:17:47.997017 [CA 2] Center 35 (5~66) winsize 62
772 12:17:48.000537 [CA 3] Center 35 (5~66) winsize 62
773 12:17:48.004136 [CA 4] Center 34 (4~65) winsize 62
774 12:17:48.007911 [CA 5] Center 33 (3~64) winsize 62
775 12:17:48.008046
776 12:17:48.011874 [CmdBusTrainingLP45] Vref(ca) range 1: 34
777 12:17:48.011965
778 12:17:48.012032 [CATrainingPosCal] consider 1 rank data
779 12:17:48.016210 u2DelayCellTimex100 = 270/100 ps
780 12:17:48.019610 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
781 12:17:48.022955 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
782 12:17:48.026433 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
783 12:17:48.033253 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
784 12:17:48.036457 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
785 12:17:48.039579 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
786 12:17:48.039666
787 12:17:48.043279 CA PerBit enable=1, Macro0, CA PI delay=33
788 12:17:48.043359
789 12:17:48.046270 [CBTSetCACLKResult] CA Dly = 33
790 12:17:48.046362 CS Dly: 5 (0~36)
791 12:17:48.046453 ==
792 12:17:48.049668 Dram Type= 6, Freq= 0, CH_0, rank 1
793 12:17:48.056436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
794 12:17:48.056564 ==
795 12:17:48.059484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
796 12:17:48.066185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
797 12:17:48.075459 [CA 0] Center 38 (7~69) winsize 63
798 12:17:48.078903 [CA 1] Center 38 (7~69) winsize 63
799 12:17:48.082287 [CA 2] Center 35 (5~66) winsize 62
800 12:17:48.085535 [CA 3] Center 35 (5~66) winsize 62
801 12:17:48.088952 [CA 4] Center 35 (4~66) winsize 63
802 12:17:48.092164 [CA 5] Center 34 (4~65) winsize 62
803 12:17:48.092264
804 12:17:48.095743 [CmdBusTrainingLP45] Vref(ca) range 1: 32
805 12:17:48.095840
806 12:17:48.098765 [CATrainingPosCal] consider 2 rank data
807 12:17:48.102232 u2DelayCellTimex100 = 270/100 ps
808 12:17:48.105564 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
809 12:17:48.108861 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
810 12:17:48.115966 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
811 12:17:48.118981 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
812 12:17:48.122513 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
813 12:17:48.125916 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
814 12:17:48.126006
815 12:17:48.129339 CA PerBit enable=1, Macro0, CA PI delay=34
816 12:17:48.129433
817 12:17:48.132804 [CBTSetCACLKResult] CA Dly = 34
818 12:17:48.132895 CS Dly: 6 (0~38)
819 12:17:48.133006
820 12:17:48.135653 ----->DramcWriteLeveling(PI) begin...
821 12:17:48.135742 ==
822 12:17:48.138959 Dram Type= 6, Freq= 0, CH_0, rank 0
823 12:17:48.145899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
824 12:17:48.145997 ==
825 12:17:48.149114 Write leveling (Byte 0): 27 => 27
826 12:17:48.152801 Write leveling (Byte 1): 27 => 27
827 12:17:48.152888 DramcWriteLeveling(PI) end<-----
828 12:17:48.153001
829 12:17:48.155948 ==
830 12:17:48.159301 Dram Type= 6, Freq= 0, CH_0, rank 0
831 12:17:48.162661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
832 12:17:48.162767 ==
833 12:17:48.165707 [Gating] SW mode calibration
834 12:17:48.173253 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
835 12:17:48.176863 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
836 12:17:48.180675 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
837 12:17:48.184384 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
838 12:17:48.190901 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:17:48.194594 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:17:48.197846 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 12:17:48.204601 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 12:17:48.208236 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:17:48.211231 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:17:48.218068 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 12:17:48.221577 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 12:17:48.224703 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 12:17:48.227937 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 12:17:48.234783 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 12:17:48.238060 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 12:17:48.241329 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:17:48.248054 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:17:48.251698 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:17:48.254963 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
854 12:17:48.261673 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
855 12:17:48.265152 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:17:48.267968 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:17:48.274790 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:17:48.278003 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:17:48.281700 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:17:48.288305 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:17:48.291313 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
862 12:17:48.294957 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
863 12:17:48.301831 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
864 12:17:48.304751 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 12:17:48.308350 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 12:17:48.311376 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
867 12:17:48.318318 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 12:17:48.321990 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
869 12:17:48.325270 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
870 12:17:48.331741 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
871 12:17:48.335179 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
872 12:17:48.338177 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:17:48.344665 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:17:48.348505 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:17:48.351900 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:17:48.358573 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:17:48.361829 0 11 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
878 12:17:48.365501 0 11 8 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
879 12:17:48.371747 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
880 12:17:48.375022 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 12:17:48.378361 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 12:17:48.381888 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
883 12:17:48.388516 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 12:17:48.391665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 12:17:48.395301 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
886 12:17:48.401856 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
887 12:17:48.405220 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 12:17:48.408549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 12:17:48.415183 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 12:17:48.418923 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 12:17:48.421993 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 12:17:48.428484 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 12:17:48.431985 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 12:17:48.435620 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 12:17:48.442157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 12:17:48.445540 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 12:17:48.448749 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 12:17:48.455442 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:17:48.458697 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:17:48.461990 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:17:48.465420 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
902 12:17:48.468710 Total UI for P1: 0, mck2ui 16
903 12:17:48.471820 best dqsien dly found for B0: ( 0, 14, 2)
904 12:17:48.478804 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
905 12:17:48.482030 Total UI for P1: 0, mck2ui 16
906 12:17:48.485405 best dqsien dly found for B1: ( 0, 14, 6)
907 12:17:48.488627 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
908 12:17:48.492317 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
909 12:17:48.492433
910 12:17:48.495349 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
911 12:17:48.498851 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
912 12:17:48.502598 [Gating] SW calibration Done
913 12:17:48.502758 ==
914 12:17:48.505582 Dram Type= 6, Freq= 0, CH_0, rank 0
915 12:17:48.509244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
916 12:17:48.509346 ==
917 12:17:48.512367 RX Vref Scan: 0
918 12:17:48.512462
919 12:17:48.512552 RX Vref 0 -> 0, step: 1
920 12:17:48.512636
921 12:17:48.515637 RX Delay -130 -> 252, step: 16
922 12:17:48.519452 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
923 12:17:48.525829 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
924 12:17:48.529244 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
925 12:17:48.532194 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
926 12:17:48.535500 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
927 12:17:48.539190 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
928 12:17:48.545635 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
929 12:17:48.548685 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
930 12:17:48.552442 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
931 12:17:48.555332 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
932 12:17:48.558710 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
933 12:17:48.565811 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
934 12:17:48.569098 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
935 12:17:48.572176 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
936 12:17:48.575725 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
937 12:17:48.579055 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
938 12:17:48.582196 ==
939 12:17:48.582296 Dram Type= 6, Freq= 0, CH_0, rank 0
940 12:17:48.588902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 12:17:48.589052 ==
942 12:17:48.589162 DQS Delay:
943 12:17:48.592267 DQS0 = 0, DQS1 = 0
944 12:17:48.592362 DQM Delay:
945 12:17:48.595858 DQM0 = 89, DQM1 = 79
946 12:17:48.595976 DQ Delay:
947 12:17:48.598944 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
948 12:17:48.602646 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
949 12:17:48.606192 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
950 12:17:48.609107 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
951 12:17:48.609208
952 12:17:48.609279
953 12:17:48.609343 ==
954 12:17:48.612334 Dram Type= 6, Freq= 0, CH_0, rank 0
955 12:17:48.616391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 12:17:48.616490 ==
957 12:17:48.616560
958 12:17:48.616623
959 12:17:48.619100 TX Vref Scan disable
960 12:17:48.619189 == TX Byte 0 ==
961 12:17:48.626320 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
962 12:17:48.629172 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
963 12:17:48.632508 == TX Byte 1 ==
964 12:17:48.635823 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
965 12:17:48.639436 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
966 12:17:48.639536 ==
967 12:17:48.642822 Dram Type= 6, Freq= 0, CH_0, rank 0
968 12:17:48.646021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
969 12:17:48.646114 ==
970 12:17:48.660111 TX Vref=22, minBit 8, minWin=26, winSum=440
971 12:17:48.663159 TX Vref=24, minBit 5, minWin=27, winSum=447
972 12:17:48.666814 TX Vref=26, minBit 5, minWin=27, winSum=448
973 12:17:48.670053 TX Vref=28, minBit 5, minWin=27, winSum=450
974 12:17:48.672971 TX Vref=30, minBit 8, minWin=28, winSum=456
975 12:17:48.679741 TX Vref=32, minBit 11, minWin=27, winSum=453
976 12:17:48.683457 [TxChooseVref] Worse bit 8, Min win 28, Win sum 456, Final Vref 30
977 12:17:48.683567
978 12:17:48.686501 Final TX Range 1 Vref 30
979 12:17:48.686595
980 12:17:48.686681 ==
981 12:17:48.690160 Dram Type= 6, Freq= 0, CH_0, rank 0
982 12:17:48.693048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 12:17:48.693148 ==
984 12:17:48.693217
985 12:17:48.696303
986 12:17:48.696397 TX Vref Scan disable
987 12:17:48.700115 == TX Byte 0 ==
988 12:17:48.703065 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
989 12:17:48.706603 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
990 12:17:48.710153 == TX Byte 1 ==
991 12:17:48.713376 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
992 12:17:48.716480 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
993 12:17:48.720203
994 12:17:48.720308 [DATLAT]
995 12:17:48.720378 Freq=800, CH0 RK0
996 12:17:48.720443
997 12:17:48.723253 DATLAT Default: 0xa
998 12:17:48.723342 0, 0xFFFF, sum = 0
999 12:17:48.726872 1, 0xFFFF, sum = 0
1000 12:17:48.726968 2, 0xFFFF, sum = 0
1001 12:17:48.729925 3, 0xFFFF, sum = 0
1002 12:17:48.730021 4, 0xFFFF, sum = 0
1003 12:17:48.733544 5, 0xFFFF, sum = 0
1004 12:17:48.733638 6, 0xFFFF, sum = 0
1005 12:17:48.736629 7, 0xFFFF, sum = 0
1006 12:17:48.736718 8, 0xFFFF, sum = 0
1007 12:17:48.739955 9, 0x0, sum = 1
1008 12:17:48.740047 10, 0x0, sum = 2
1009 12:17:48.743445 11, 0x0, sum = 3
1010 12:17:48.743539 12, 0x0, sum = 4
1011 12:17:48.746726 best_step = 10
1012 12:17:48.746817
1013 12:17:48.746887 ==
1014 12:17:48.750510 Dram Type= 6, Freq= 0, CH_0, rank 0
1015 12:17:48.753535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1016 12:17:48.753627 ==
1017 12:17:48.756957 RX Vref Scan: 1
1018 12:17:48.757060
1019 12:17:48.757128 Set Vref Range= 32 -> 127
1020 12:17:48.757191
1021 12:17:48.760007 RX Vref 32 -> 127, step: 1
1022 12:17:48.760094
1023 12:17:48.763293 RX Delay -95 -> 252, step: 8
1024 12:17:48.763382
1025 12:17:48.766798 Set Vref, RX VrefLevel [Byte0]: 32
1026 12:17:48.770156 [Byte1]: 32
1027 12:17:48.770251
1028 12:17:48.773460 Set Vref, RX VrefLevel [Byte0]: 33
1029 12:17:48.776748 [Byte1]: 33
1030 12:17:48.779972
1031 12:17:48.780060 Set Vref, RX VrefLevel [Byte0]: 34
1032 12:17:48.783404 [Byte1]: 34
1033 12:17:48.787969
1034 12:17:48.788073 Set Vref, RX VrefLevel [Byte0]: 35
1035 12:17:48.791089 [Byte1]: 35
1036 12:17:48.795195
1037 12:17:48.795292 Set Vref, RX VrefLevel [Byte0]: 36
1038 12:17:48.798774 [Byte1]: 36
1039 12:17:48.802958
1040 12:17:48.803066 Set Vref, RX VrefLevel [Byte0]: 37
1041 12:17:48.806108 [Byte1]: 37
1042 12:17:48.810360
1043 12:17:48.810460 Set Vref, RX VrefLevel [Byte0]: 38
1044 12:17:48.814126 [Byte1]: 38
1045 12:17:48.818853
1046 12:17:48.818955 Set Vref, RX VrefLevel [Byte0]: 39
1047 12:17:48.821894 [Byte1]: 39
1048 12:17:48.825840
1049 12:17:48.825940 Set Vref, RX VrefLevel [Byte0]: 40
1050 12:17:48.829689 [Byte1]: 40
1051 12:17:48.833286
1052 12:17:48.833383 Set Vref, RX VrefLevel [Byte0]: 41
1053 12:17:48.836708 [Byte1]: 41
1054 12:17:48.841397
1055 12:17:48.841499 Set Vref, RX VrefLevel [Byte0]: 42
1056 12:17:48.844685 [Byte1]: 42
1057 12:17:48.848637
1058 12:17:48.848758 Set Vref, RX VrefLevel [Byte0]: 43
1059 12:17:48.852130 [Byte1]: 43
1060 12:17:48.856151
1061 12:17:48.856247 Set Vref, RX VrefLevel [Byte0]: 44
1062 12:17:48.859491 [Byte1]: 44
1063 12:17:48.863779
1064 12:17:48.863904 Set Vref, RX VrefLevel [Byte0]: 45
1065 12:17:48.867076 [Byte1]: 45
1066 12:17:48.871570
1067 12:17:48.871694 Set Vref, RX VrefLevel [Byte0]: 46
1068 12:17:48.874827 [Byte1]: 46
1069 12:17:48.878944
1070 12:17:48.879042 Set Vref, RX VrefLevel [Byte0]: 47
1071 12:17:48.882349 [Byte1]: 47
1072 12:17:48.886484
1073 12:17:48.886602 Set Vref, RX VrefLevel [Byte0]: 48
1074 12:17:48.889937 [Byte1]: 48
1075 12:17:48.893952
1076 12:17:48.894100 Set Vref, RX VrefLevel [Byte0]: 49
1077 12:17:48.897169 [Byte1]: 49
1078 12:17:48.901552
1079 12:17:48.901671 Set Vref, RX VrefLevel [Byte0]: 50
1080 12:17:48.904768 [Byte1]: 50
1081 12:17:48.909525
1082 12:17:48.909623 Set Vref, RX VrefLevel [Byte0]: 51
1083 12:17:48.912362 [Byte1]: 51
1084 12:17:48.916893
1085 12:17:48.917026 Set Vref, RX VrefLevel [Byte0]: 52
1086 12:17:48.920059 [Byte1]: 52
1087 12:17:48.924503
1088 12:17:48.924602 Set Vref, RX VrefLevel [Byte0]: 53
1089 12:17:48.928072 [Byte1]: 53
1090 12:17:48.932138
1091 12:17:48.932232 Set Vref, RX VrefLevel [Byte0]: 54
1092 12:17:48.935256 [Byte1]: 54
1093 12:17:48.939836
1094 12:17:48.939932 Set Vref, RX VrefLevel [Byte0]: 55
1095 12:17:48.942977 [Byte1]: 55
1096 12:17:48.947183
1097 12:17:48.947275 Set Vref, RX VrefLevel [Byte0]: 56
1098 12:17:48.950588 [Byte1]: 56
1099 12:17:48.954946
1100 12:17:48.955041 Set Vref, RX VrefLevel [Byte0]: 57
1101 12:17:48.958000 [Byte1]: 57
1102 12:17:48.962452
1103 12:17:48.962548 Set Vref, RX VrefLevel [Byte0]: 58
1104 12:17:48.966081 [Byte1]: 58
1105 12:17:48.970207
1106 12:17:48.970300 Set Vref, RX VrefLevel [Byte0]: 59
1107 12:17:48.973545 [Byte1]: 59
1108 12:17:48.977858
1109 12:17:48.977953 Set Vref, RX VrefLevel [Byte0]: 60
1110 12:17:48.980758 [Byte1]: 60
1111 12:17:48.985390
1112 12:17:48.985509 Set Vref, RX VrefLevel [Byte0]: 61
1113 12:17:48.988392 [Byte1]: 61
1114 12:17:48.992902
1115 12:17:48.993046 Set Vref, RX VrefLevel [Byte0]: 62
1116 12:17:48.996213 [Byte1]: 62
1117 12:17:49.000500
1118 12:17:49.000695 Set Vref, RX VrefLevel [Byte0]: 63
1119 12:17:49.003830 [Byte1]: 63
1120 12:17:49.007970
1121 12:17:49.008092 Set Vref, RX VrefLevel [Byte0]: 64
1122 12:17:49.011238 [Byte1]: 64
1123 12:17:49.015498
1124 12:17:49.015606 Set Vref, RX VrefLevel [Byte0]: 65
1125 12:17:49.019125 [Byte1]: 65
1126 12:17:49.023137
1127 12:17:49.023255 Set Vref, RX VrefLevel [Byte0]: 66
1128 12:17:49.026347 [Byte1]: 66
1129 12:17:49.030702
1130 12:17:49.030833 Set Vref, RX VrefLevel [Byte0]: 67
1131 12:17:49.033973 [Byte1]: 67
1132 12:17:49.038471
1133 12:17:49.038594 Set Vref, RX VrefLevel [Byte0]: 68
1134 12:17:49.041731 [Byte1]: 68
1135 12:17:49.045943
1136 12:17:49.046042 Set Vref, RX VrefLevel [Byte0]: 69
1137 12:17:49.049342 [Byte1]: 69
1138 12:17:49.053559
1139 12:17:49.053654 Set Vref, RX VrefLevel [Byte0]: 70
1140 12:17:49.056934 [Byte1]: 70
1141 12:17:49.061306
1142 12:17:49.061400 Set Vref, RX VrefLevel [Byte0]: 71
1143 12:17:49.064809 [Byte1]: 71
1144 12:17:49.068919
1145 12:17:49.069048 Set Vref, RX VrefLevel [Byte0]: 72
1146 12:17:49.072096 [Byte1]: 72
1147 12:17:49.076821
1148 12:17:49.076918 Set Vref, RX VrefLevel [Byte0]: 73
1149 12:17:49.079739 [Byte1]: 73
1150 12:17:49.084005
1151 12:17:49.084099 Set Vref, RX VrefLevel [Byte0]: 74
1152 12:17:49.087410 [Byte1]: 74
1153 12:17:49.091435
1154 12:17:49.091560 Set Vref, RX VrefLevel [Byte0]: 75
1155 12:17:49.095056 [Byte1]: 75
1156 12:17:49.099530
1157 12:17:49.099672 Set Vref, RX VrefLevel [Byte0]: 76
1158 12:17:49.102369 [Byte1]: 76
1159 12:17:49.106806
1160 12:17:49.106956 Set Vref, RX VrefLevel [Byte0]: 77
1161 12:17:49.109977 [Byte1]: 77
1162 12:17:49.114504
1163 12:17:49.114625 Final RX Vref Byte 0 = 61 to rank0
1164 12:17:49.117588 Final RX Vref Byte 1 = 52 to rank0
1165 12:17:49.120894 Final RX Vref Byte 0 = 61 to rank1
1166 12:17:49.124455 Final RX Vref Byte 1 = 52 to rank1==
1167 12:17:49.127703 Dram Type= 6, Freq= 0, CH_0, rank 0
1168 12:17:49.131136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1169 12:17:49.134521 ==
1170 12:17:49.134618 DQS Delay:
1171 12:17:49.134686 DQS0 = 0, DQS1 = 0
1172 12:17:49.137762 DQM Delay:
1173 12:17:49.137890 DQM0 = 93, DQM1 = 82
1174 12:17:49.141078 DQ Delay:
1175 12:17:49.144414 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1176 12:17:49.144550 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1177 12:17:49.148127 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1178 12:17:49.151016 DQ12 =88, DQ13 =84, DQ14 =96, DQ15 =88
1179 12:17:49.154440
1180 12:17:49.154550
1181 12:17:49.161240 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1182 12:17:49.164426 CH0 RK0: MR19=606, MR18=3E39
1183 12:17:49.171481 CH0_RK0: MR19=0x606, MR18=0x3E39, DQSOSC=394, MR23=63, INC=95, DEC=63
1184 12:17:49.171616
1185 12:17:49.175077 ----->DramcWriteLeveling(PI) begin...
1186 12:17:49.175169 ==
1187 12:17:49.177902 Dram Type= 6, Freq= 0, CH_0, rank 1
1188 12:17:49.181351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 12:17:49.181441 ==
1190 12:17:49.184789 Write leveling (Byte 0): 34 => 34
1191 12:17:49.187761 Write leveling (Byte 1): 29 => 29
1192 12:17:49.191460 DramcWriteLeveling(PI) end<-----
1193 12:17:49.191583
1194 12:17:49.191678 ==
1195 12:17:49.194644 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 12:17:49.198168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1197 12:17:49.198259 ==
1198 12:17:49.201545 [Gating] SW mode calibration
1199 12:17:49.208091 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1200 12:17:49.214493 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1201 12:17:49.217844 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1202 12:17:49.221286 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1203 12:17:49.227975 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:17:49.231291 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:17:49.234750 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:17:49.282436 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:17:49.282595 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:17:49.282860 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 12:17:49.282930 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:17:49.283003 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:17:49.283576 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:17:49.283726 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:17:49.284007 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:17:49.284104 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:17:49.284206 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:17:49.284296 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:17:49.288429 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:17:49.291484 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1219 12:17:49.298095 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1220 12:17:49.301760 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:17:49.305132 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:17:49.311693 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:17:49.315102 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:17:49.318317 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:17:49.324969 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:17:49.328354 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1227 12:17:49.331927 0 9 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
1228 12:17:49.334955 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 12:17:49.341533 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 12:17:49.345185 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 12:17:49.348211 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 12:17:49.354814 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 12:17:49.358434 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 12:17:49.361394 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
1235 12:17:49.368220 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1236 12:17:49.371732 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:17:49.375154 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:17:49.381922 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:17:49.385038 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:17:49.388368 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:17:49.395123 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:17:49.398390 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1243 12:17:49.401817 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
1244 12:17:49.408488 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 12:17:49.411668 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 12:17:49.415283 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 12:17:49.418629 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 12:17:49.426538 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 12:17:49.430755 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 12:17:49.434447 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1251 12:17:49.437646 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1252 12:17:49.440752 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 12:17:49.447879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 12:17:49.451622 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 12:17:49.455120 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 12:17:49.458515 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 12:17:49.464962 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 12:17:49.468111 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 12:17:49.471538 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:17:49.478741 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:17:49.498470 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:17:49.498897 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:17:49.499169 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:17:49.499424 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:17:49.499954 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:17:49.505201 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:17:49.508328 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 12:17:49.511716 Total UI for P1: 0, mck2ui 16
1269 12:17:49.515576 best dqsien dly found for B0: ( 0, 14, 6)
1270 12:17:49.518361 Total UI for P1: 0, mck2ui 16
1271 12:17:49.521793 best dqsien dly found for B1: ( 0, 14, 6)
1272 12:17:49.524951 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1273 12:17:49.528609 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1274 12:17:49.528724
1275 12:17:49.531587 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1276 12:17:49.534940 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1277 12:17:49.538233 [Gating] SW calibration Done
1278 12:17:49.538345 ==
1279 12:17:49.542123 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 12:17:49.545309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 12:17:49.545400 ==
1282 12:17:49.548768 RX Vref Scan: 0
1283 12:17:49.548856
1284 12:17:49.548924 RX Vref 0 -> 0, step: 1
1285 12:17:49.549031
1286 12:17:49.551922 RX Delay -130 -> 252, step: 16
1287 12:17:49.558599 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1288 12:17:49.561669 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1289 12:17:49.564876 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1290 12:17:49.568241 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1291 12:17:49.571507 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1292 12:17:49.574840 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1293 12:17:49.581641 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1294 12:17:49.585073 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1295 12:17:49.588111 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1296 12:17:49.591711 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1297 12:17:49.598253 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1298 12:17:49.601629 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1299 12:17:49.604796 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1300 12:17:49.608173 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1301 12:17:49.611622 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1302 12:17:49.618054 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1303 12:17:49.618170 ==
1304 12:17:49.621533 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 12:17:49.624853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 12:17:49.625004 ==
1307 12:17:49.625091 DQS Delay:
1308 12:17:49.628237 DQS0 = 0, DQS1 = 0
1309 12:17:49.628327 DQM Delay:
1310 12:17:49.631737 DQM0 = 90, DQM1 = 79
1311 12:17:49.631824 DQ Delay:
1312 12:17:49.635031 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1313 12:17:49.638319 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1314 12:17:49.641393 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1315 12:17:49.645018 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1316 12:17:49.645105
1317 12:17:49.645192
1318 12:17:49.645272 ==
1319 12:17:49.648454 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 12:17:49.651586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 12:17:49.651673 ==
1322 12:17:49.651759
1323 12:17:49.654888
1324 12:17:49.654974 TX Vref Scan disable
1325 12:17:49.658192 == TX Byte 0 ==
1326 12:17:49.661516 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1327 12:17:49.665147 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1328 12:17:49.668374 == TX Byte 1 ==
1329 12:17:49.671470 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1330 12:17:49.674825 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1331 12:17:49.674940 ==
1332 12:17:49.678386 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 12:17:49.684902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 12:17:49.685022 ==
1335 12:17:49.697321 TX Vref=22, minBit 1, minWin=27, winSum=440
1336 12:17:49.700735 TX Vref=24, minBit 8, minWin=27, winSum=447
1337 12:17:49.704275 TX Vref=26, minBit 6, minWin=27, winSum=448
1338 12:17:49.707427 TX Vref=28, minBit 8, minWin=27, winSum=451
1339 12:17:49.710633 TX Vref=30, minBit 8, minWin=27, winSum=453
1340 12:17:49.717220 TX Vref=32, minBit 10, minWin=27, winSum=454
1341 12:17:49.720701 [TxChooseVref] Worse bit 10, Min win 27, Win sum 454, Final Vref 32
1342 12:17:49.720788
1343 12:17:49.723923 Final TX Range 1 Vref 32
1344 12:17:49.724008
1345 12:17:49.724075 ==
1346 12:17:49.727614 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 12:17:49.730989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 12:17:49.731076 ==
1349 12:17:49.734145
1350 12:17:49.734228
1351 12:17:49.734293 TX Vref Scan disable
1352 12:17:49.737553 == TX Byte 0 ==
1353 12:17:49.741182 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1354 12:17:49.744334 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1355 12:17:49.747497 == TX Byte 1 ==
1356 12:17:49.751160 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1357 12:17:49.754305 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1358 12:17:49.754388
1359 12:17:49.757891 [DATLAT]
1360 12:17:49.757973 Freq=800, CH0 RK1
1361 12:17:49.758039
1362 12:17:49.761226 DATLAT Default: 0xa
1363 12:17:49.761309 0, 0xFFFF, sum = 0
1364 12:17:49.764362 1, 0xFFFF, sum = 0
1365 12:17:49.764453 2, 0xFFFF, sum = 0
1366 12:17:49.767974 3, 0xFFFF, sum = 0
1367 12:17:49.768060 4, 0xFFFF, sum = 0
1368 12:17:49.771124 5, 0xFFFF, sum = 0
1369 12:17:49.771209 6, 0xFFFF, sum = 0
1370 12:17:49.774714 7, 0xFFFF, sum = 0
1371 12:17:49.774818 8, 0xFFFF, sum = 0
1372 12:17:49.777732 9, 0x0, sum = 1
1373 12:17:49.777817 10, 0x0, sum = 2
1374 12:17:49.781148 11, 0x0, sum = 3
1375 12:17:49.781233 12, 0x0, sum = 4
1376 12:17:49.784642 best_step = 10
1377 12:17:49.784739
1378 12:17:49.784804 ==
1379 12:17:49.787705 Dram Type= 6, Freq= 0, CH_0, rank 1
1380 12:17:49.791118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 12:17:49.791244 ==
1382 12:17:49.794337 RX Vref Scan: 0
1383 12:17:49.794421
1384 12:17:49.794485 RX Vref 0 -> 0, step: 1
1385 12:17:49.794545
1386 12:17:49.797862 RX Delay -95 -> 252, step: 8
1387 12:17:49.804543 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1388 12:17:49.807900 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1389 12:17:49.811685 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1390 12:17:49.814764 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1391 12:17:49.817904 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1392 12:17:49.821381 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1393 12:17:49.827921 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1394 12:17:49.831627 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1395 12:17:49.834752 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1396 12:17:49.838275 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1397 12:17:49.841533 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1398 12:17:49.848011 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1399 12:17:49.851309 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1400 12:17:49.854919 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1401 12:17:49.858210 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1402 12:17:49.865246 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1403 12:17:49.865332 ==
1404 12:17:49.867888 Dram Type= 6, Freq= 0, CH_0, rank 1
1405 12:17:49.871500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 12:17:49.871583 ==
1407 12:17:49.871648 DQS Delay:
1408 12:17:49.874525 DQS0 = 0, DQS1 = 0
1409 12:17:49.874606 DQM Delay:
1410 12:17:49.878050 DQM0 = 91, DQM1 = 82
1411 12:17:49.878131 DQ Delay:
1412 12:17:49.881686 DQ0 =88, DQ1 =92, DQ2 =92, DQ3 =84
1413 12:17:49.884860 DQ4 =88, DQ5 =84, DQ6 =100, DQ7 =100
1414 12:17:49.888571 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
1415 12:17:49.891523 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1416 12:17:49.891608
1417 12:17:49.891672
1418 12:17:49.898087 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
1419 12:17:49.901335 CH0 RK1: MR19=606, MR18=3E19
1420 12:17:49.907993 CH0_RK1: MR19=0x606, MR18=0x3E19, DQSOSC=394, MR23=63, INC=95, DEC=63
1421 12:17:49.911444 [RxdqsGatingPostProcess] freq 800
1422 12:17:49.914710 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1423 12:17:49.918470 Pre-setting of DQS Precalculation
1424 12:17:49.924818 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1425 12:17:49.924926 ==
1426 12:17:49.928114 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 12:17:49.931448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 12:17:49.931532 ==
1429 12:17:49.938307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1430 12:17:49.945182 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1431 12:17:49.952729 [CA 0] Center 36 (6~67) winsize 62
1432 12:17:49.956175 [CA 1] Center 36 (6~67) winsize 62
1433 12:17:49.959411 [CA 2] Center 35 (5~65) winsize 61
1434 12:17:49.962680 [CA 3] Center 34 (3~65) winsize 63
1435 12:17:49.966286 [CA 4] Center 34 (4~64) winsize 61
1436 12:17:49.969390 [CA 5] Center 33 (3~64) winsize 62
1437 12:17:49.969473
1438 12:17:49.972669 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1439 12:17:49.972776
1440 12:17:49.975925 [CATrainingPosCal] consider 1 rank data
1441 12:17:49.979571 u2DelayCellTimex100 = 270/100 ps
1442 12:17:49.982800 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1443 12:17:49.986088 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1444 12:17:49.992613 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1445 12:17:49.996018 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1446 12:17:49.999319 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1447 12:17:50.002733 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1448 12:17:50.002817
1449 12:17:50.006351 CA PerBit enable=1, Macro0, CA PI delay=33
1450 12:17:50.006438
1451 12:17:50.009555 [CBTSetCACLKResult] CA Dly = 33
1452 12:17:50.009639 CS Dly: 5 (0~36)
1453 12:17:50.009706 ==
1454 12:17:50.013046 Dram Type= 6, Freq= 0, CH_1, rank 1
1455 12:17:50.019710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 12:17:50.019798 ==
1457 12:17:50.022951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1458 12:17:50.029535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1459 12:17:50.038921 [CA 0] Center 37 (7~67) winsize 61
1460 12:17:50.042697 [CA 1] Center 37 (6~68) winsize 63
1461 12:17:50.046052 [CA 2] Center 35 (5~66) winsize 62
1462 12:17:50.048961 [CA 3] Center 34 (4~65) winsize 62
1463 12:17:50.052386 [CA 4] Center 34 (4~65) winsize 62
1464 12:17:50.055772 [CA 5] Center 34 (4~64) winsize 61
1465 12:17:50.055855
1466 12:17:50.059125 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1467 12:17:50.059208
1468 12:17:50.062759 [CATrainingPosCal] consider 2 rank data
1469 12:17:50.065953 u2DelayCellTimex100 = 270/100 ps
1470 12:17:50.069069 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1471 12:17:50.072803 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 12:17:50.075759 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1473 12:17:50.083083 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1474 12:17:50.086118 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
1475 12:17:50.089463 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1476 12:17:50.089551
1477 12:17:50.093665 CA PerBit enable=1, Macro0, CA PI delay=34
1478 12:17:50.093753
1479 12:17:50.097684 [CBTSetCACLKResult] CA Dly = 34
1480 12:17:50.097771 CS Dly: 6 (0~38)
1481 12:17:50.097838
1482 12:17:50.101323 ----->DramcWriteLeveling(PI) begin...
1483 12:17:50.101410 ==
1484 12:17:50.104821 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 12:17:50.108586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1486 12:17:50.108675 ==
1487 12:17:50.112336 Write leveling (Byte 0): 28 => 28
1488 12:17:50.115897 Write leveling (Byte 1): 29 => 29
1489 12:17:50.115986 DramcWriteLeveling(PI) end<-----
1490 12:17:50.116102
1491 12:17:50.119804 ==
1492 12:17:50.119890 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 12:17:50.126539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 12:17:50.126663 ==
1495 12:17:50.129650 [Gating] SW mode calibration
1496 12:17:50.136899 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1497 12:17:50.140110 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1498 12:17:50.146313 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1499 12:17:50.149761 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1500 12:17:50.153123 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:17:50.156437 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:17:50.163092 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:17:50.166853 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:17:50.169965 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 12:17:50.176748 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:17:50.179940 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 12:17:50.183315 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:17:50.189915 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:17:50.193714 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:17:50.196692 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:17:50.203491 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:17:50.206771 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:17:50.209737 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:17:50.216867 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:17:50.219844 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:17:50.223062 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:17:50.226692 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:17:50.233251 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:17:50.236600 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:17:50.239749 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:17:50.246988 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:17:50.250242 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:17:50.253407 0 9 4 | B1->B0 | 2322 2424 | 1 0 | (0 0) (1 1)
1524 12:17:50.260028 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 12:17:50.263625 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 12:17:50.266892 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 12:17:50.273153 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 12:17:50.276838 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 12:17:50.280078 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 12:17:50.286806 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 12:17:50.290008 0 10 4 | B1->B0 | 3030 2d2d | 0 1 | (1 0) (1 0)
1532 12:17:50.293860 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:17:50.296881 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:17:50.303596 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:17:50.306919 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:17:50.310442 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:17:50.316734 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:17:50.320123 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:17:50.323812 0 11 4 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
1540 12:17:50.330952 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 12:17:50.333905 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 12:17:50.336966 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 12:17:50.344045 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 12:17:50.347065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 12:17:50.350804 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 12:17:50.357099 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 12:17:50.360345 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1548 12:17:50.363779 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1549 12:17:50.367534 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 12:17:50.373997 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 12:17:50.377324 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 12:17:50.380609 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 12:17:50.387455 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 12:17:50.390739 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 12:17:50.393688 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 12:17:50.400468 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:17:50.404246 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:17:50.407304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:17:50.413724 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:17:50.416958 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:17:50.420547 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:17:50.426964 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1563 12:17:50.430353 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1564 12:17:50.433799 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:17:50.437456 Total UI for P1: 0, mck2ui 16
1566 12:17:50.440429 best dqsien dly found for B0: ( 0, 14, 2)
1567 12:17:50.443720 Total UI for P1: 0, mck2ui 16
1568 12:17:50.447211 best dqsien dly found for B1: ( 0, 14, 4)
1569 12:17:50.450402 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1570 12:17:50.453751 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1571 12:17:50.453861
1572 12:17:50.456858 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1573 12:17:50.463645 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1574 12:17:50.463761 [Gating] SW calibration Done
1575 12:17:50.463836 ==
1576 12:17:50.466920 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 12:17:50.473649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 12:17:50.473764 ==
1579 12:17:50.473835 RX Vref Scan: 0
1580 12:17:50.473897
1581 12:17:50.476951 RX Vref 0 -> 0, step: 1
1582 12:17:50.477059
1583 12:17:50.480202 RX Delay -130 -> 252, step: 16
1584 12:17:50.483557 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1585 12:17:50.487331 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1586 12:17:50.490262 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1587 12:17:50.496807 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1588 12:17:50.500371 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1589 12:17:50.503552 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1590 12:17:50.507055 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1591 12:17:50.510241 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1592 12:17:50.516880 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1593 12:17:50.520574 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1594 12:17:50.523536 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1595 12:17:50.527317 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1596 12:17:50.530636 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1597 12:17:50.537087 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1598 12:17:50.540524 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1599 12:17:50.543715 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1600 12:17:50.543805 ==
1601 12:17:50.547096 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 12:17:50.550563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 12:17:50.550650 ==
1604 12:17:50.553765 DQS Delay:
1605 12:17:50.553850 DQS0 = 0, DQS1 = 0
1606 12:17:50.553917 DQM Delay:
1607 12:17:50.556905 DQM0 = 90, DQM1 = 82
1608 12:17:50.557032 DQ Delay:
1609 12:17:50.560751 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1610 12:17:50.563627 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =93
1611 12:17:50.567295 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1612 12:17:50.570610 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1613 12:17:50.570697
1614 12:17:50.570764
1615 12:17:50.570825 ==
1616 12:17:50.574285 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 12:17:50.580566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 12:17:50.580658 ==
1619 12:17:50.580726
1620 12:17:50.580787
1621 12:17:50.580846 TX Vref Scan disable
1622 12:17:50.584177 == TX Byte 0 ==
1623 12:17:50.587438 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1624 12:17:50.594037 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1625 12:17:50.594135 == TX Byte 1 ==
1626 12:17:50.597358 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1627 12:17:50.600694 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1628 12:17:50.604461 ==
1629 12:17:50.607724 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 12:17:50.611106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 12:17:50.611199 ==
1632 12:17:50.623108 TX Vref=22, minBit 11, minWin=26, winSum=446
1633 12:17:50.626649 TX Vref=24, minBit 8, minWin=27, winSum=450
1634 12:17:50.629858 TX Vref=26, minBit 8, minWin=27, winSum=452
1635 12:17:50.632882 TX Vref=28, minBit 9, minWin=27, winSum=454
1636 12:17:50.636505 TX Vref=30, minBit 8, minWin=27, winSum=457
1637 12:17:50.642962 TX Vref=32, minBit 8, minWin=27, winSum=452
1638 12:17:50.646509 [TxChooseVref] Worse bit 8, Min win 27, Win sum 457, Final Vref 30
1639 12:17:50.646596
1640 12:17:50.649804 Final TX Range 1 Vref 30
1641 12:17:50.649882
1642 12:17:50.649947 ==
1643 12:17:50.653044 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 12:17:50.656676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 12:17:50.656767 ==
1646 12:17:50.656836
1647 12:17:50.659610
1648 12:17:50.659695 TX Vref Scan disable
1649 12:17:50.663127 == TX Byte 0 ==
1650 12:17:50.666550 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1651 12:17:50.670295 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1652 12:17:50.673245 == TX Byte 1 ==
1653 12:17:50.676724 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1654 12:17:50.680050 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1655 12:17:50.680141
1656 12:17:50.683227 [DATLAT]
1657 12:17:50.683312 Freq=800, CH1 RK0
1658 12:17:50.683379
1659 12:17:50.686947 DATLAT Default: 0xa
1660 12:17:50.687030 0, 0xFFFF, sum = 0
1661 12:17:50.690086 1, 0xFFFF, sum = 0
1662 12:17:50.690199 2, 0xFFFF, sum = 0
1663 12:17:50.693436 3, 0xFFFF, sum = 0
1664 12:17:50.693524 4, 0xFFFF, sum = 0
1665 12:17:50.697176 5, 0xFFFF, sum = 0
1666 12:17:50.697262 6, 0xFFFF, sum = 0
1667 12:17:50.700329 7, 0xFFFF, sum = 0
1668 12:17:50.700415 8, 0xFFFF, sum = 0
1669 12:17:50.703685 9, 0x0, sum = 1
1670 12:17:50.703798 10, 0x0, sum = 2
1671 12:17:50.706727 11, 0x0, sum = 3
1672 12:17:50.706833 12, 0x0, sum = 4
1673 12:17:50.710249 best_step = 10
1674 12:17:50.710386
1675 12:17:50.710510 ==
1676 12:17:50.713389 Dram Type= 6, Freq= 0, CH_1, rank 0
1677 12:17:50.716898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1678 12:17:50.717019 ==
1679 12:17:50.720464 RX Vref Scan: 1
1680 12:17:50.720548
1681 12:17:50.720614 Set Vref Range= 32 -> 127
1682 12:17:50.720676
1683 12:17:50.723961 RX Vref 32 -> 127, step: 1
1684 12:17:50.724045
1685 12:17:50.727102 RX Delay -95 -> 252, step: 8
1686 12:17:50.727186
1687 12:17:50.730496 Set Vref, RX VrefLevel [Byte0]: 32
1688 12:17:50.733749 [Byte1]: 32
1689 12:17:50.733833
1690 12:17:50.736868 Set Vref, RX VrefLevel [Byte0]: 33
1691 12:17:50.740345 [Byte1]: 33
1692 12:17:50.740455
1693 12:17:50.743596 Set Vref, RX VrefLevel [Byte0]: 34
1694 12:17:50.746992 [Byte1]: 34
1695 12:17:50.751388
1696 12:17:50.751498 Set Vref, RX VrefLevel [Byte0]: 35
1697 12:17:50.754506 [Byte1]: 35
1698 12:17:50.758365
1699 12:17:50.758535 Set Vref, RX VrefLevel [Byte0]: 36
1700 12:17:50.762059 [Byte1]: 36
1701 12:17:50.766009
1702 12:17:50.766094 Set Vref, RX VrefLevel [Byte0]: 37
1703 12:17:50.769475 [Byte1]: 37
1704 12:17:50.773634
1705 12:17:50.773719 Set Vref, RX VrefLevel [Byte0]: 38
1706 12:17:50.777183 [Byte1]: 38
1707 12:17:50.781430
1708 12:17:50.781515 Set Vref, RX VrefLevel [Byte0]: 39
1709 12:17:50.784780 [Byte1]: 39
1710 12:17:50.789157
1711 12:17:50.789241 Set Vref, RX VrefLevel [Byte0]: 40
1712 12:17:50.792238 [Byte1]: 40
1713 12:17:50.796446
1714 12:17:50.796532 Set Vref, RX VrefLevel [Byte0]: 41
1715 12:17:50.799978 [Byte1]: 41
1716 12:17:50.804316
1717 12:17:50.804428 Set Vref, RX VrefLevel [Byte0]: 42
1718 12:17:50.807432 [Byte1]: 42
1719 12:17:50.811704
1720 12:17:50.811788 Set Vref, RX VrefLevel [Byte0]: 43
1721 12:17:50.814939 [Byte1]: 43
1722 12:17:50.819834
1723 12:17:50.819919 Set Vref, RX VrefLevel [Byte0]: 44
1724 12:17:50.822930 [Byte1]: 44
1725 12:17:50.826954
1726 12:17:50.827039 Set Vref, RX VrefLevel [Byte0]: 45
1727 12:17:50.830344 [Byte1]: 45
1728 12:17:50.834665
1729 12:17:50.834748 Set Vref, RX VrefLevel [Byte0]: 46
1730 12:17:50.837758 [Byte1]: 46
1731 12:17:50.842204
1732 12:17:50.842288 Set Vref, RX VrefLevel [Byte0]: 47
1733 12:17:50.845352 [Byte1]: 47
1734 12:17:50.849661
1735 12:17:50.849744 Set Vref, RX VrefLevel [Byte0]: 48
1736 12:17:50.853121 [Byte1]: 48
1737 12:17:50.857233
1738 12:17:50.857316 Set Vref, RX VrefLevel [Byte0]: 49
1739 12:17:50.860631 [Byte1]: 49
1740 12:17:50.864969
1741 12:17:50.865071 Set Vref, RX VrefLevel [Byte0]: 50
1742 12:17:50.868226 [Byte1]: 50
1743 12:17:50.872637
1744 12:17:50.872723 Set Vref, RX VrefLevel [Byte0]: 51
1745 12:17:50.875594 [Byte1]: 51
1746 12:17:50.880195
1747 12:17:50.880280 Set Vref, RX VrefLevel [Byte0]: 52
1748 12:17:50.883609 [Byte1]: 52
1749 12:17:50.887734
1750 12:17:50.887818 Set Vref, RX VrefLevel [Byte0]: 53
1751 12:17:50.891233 [Byte1]: 53
1752 12:17:50.895294
1753 12:17:50.895384 Set Vref, RX VrefLevel [Byte0]: 54
1754 12:17:50.898610 [Byte1]: 54
1755 12:17:50.903112
1756 12:17:50.903197 Set Vref, RX VrefLevel [Byte0]: 55
1757 12:17:50.909357 [Byte1]: 55
1758 12:17:50.909445
1759 12:17:50.912873 Set Vref, RX VrefLevel [Byte0]: 56
1760 12:17:50.916200 [Byte1]: 56
1761 12:17:50.916284
1762 12:17:50.919561 Set Vref, RX VrefLevel [Byte0]: 57
1763 12:17:50.922926 [Byte1]: 57
1764 12:17:50.923011
1765 12:17:50.925985 Set Vref, RX VrefLevel [Byte0]: 58
1766 12:17:50.929322 [Byte1]: 58
1767 12:17:50.933235
1768 12:17:50.933320 Set Vref, RX VrefLevel [Byte0]: 59
1769 12:17:50.936494 [Byte1]: 59
1770 12:17:50.940718
1771 12:17:50.940802 Set Vref, RX VrefLevel [Byte0]: 60
1772 12:17:50.944426 [Byte1]: 60
1773 12:17:50.948397
1774 12:17:50.948482 Set Vref, RX VrefLevel [Byte0]: 61
1775 12:17:50.952049 [Byte1]: 61
1776 12:17:50.956077
1777 12:17:50.956162 Set Vref, RX VrefLevel [Byte0]: 62
1778 12:17:50.959208 [Byte1]: 62
1779 12:17:50.963756
1780 12:17:50.963841 Set Vref, RX VrefLevel [Byte0]: 63
1781 12:17:50.966966 [Byte1]: 63
1782 12:17:50.971137
1783 12:17:50.971230 Set Vref, RX VrefLevel [Byte0]: 64
1784 12:17:50.974792 [Byte1]: 64
1785 12:17:50.979008
1786 12:17:50.979127 Set Vref, RX VrefLevel [Byte0]: 65
1787 12:17:50.982284 [Byte1]: 65
1788 12:17:50.986712
1789 12:17:50.986845 Set Vref, RX VrefLevel [Byte0]: 66
1790 12:17:50.989726 [Byte1]: 66
1791 12:17:50.993986
1792 12:17:50.994077 Set Vref, RX VrefLevel [Byte0]: 67
1793 12:17:50.997338 [Byte1]: 67
1794 12:17:51.001907
1795 12:17:51.001994 Set Vref, RX VrefLevel [Byte0]: 68
1796 12:17:51.005265 [Byte1]: 68
1797 12:17:51.009296
1798 12:17:51.009383 Set Vref, RX VrefLevel [Byte0]: 69
1799 12:17:51.012457 [Byte1]: 69
1800 12:17:51.016773
1801 12:17:51.016856 Set Vref, RX VrefLevel [Byte0]: 70
1802 12:17:51.020188 [Byte1]: 70
1803 12:17:51.024474
1804 12:17:51.024559 Set Vref, RX VrefLevel [Byte0]: 71
1805 12:17:51.027972 [Byte1]: 71
1806 12:17:51.031960
1807 12:17:51.032045 Set Vref, RX VrefLevel [Byte0]: 72
1808 12:17:51.035128 [Byte1]: 72
1809 12:17:51.039620
1810 12:17:51.039706 Set Vref, RX VrefLevel [Byte0]: 73
1811 12:17:51.042919 [Byte1]: 73
1812 12:17:51.047417
1813 12:17:51.047504 Set Vref, RX VrefLevel [Byte0]: 74
1814 12:17:51.050450 [Byte1]: 74
1815 12:17:51.054703
1816 12:17:51.054789 Set Vref, RX VrefLevel [Byte0]: 75
1817 12:17:51.058099 [Byte1]: 75
1818 12:17:51.062264
1819 12:17:51.062353 Set Vref, RX VrefLevel [Byte0]: 76
1820 12:17:51.065944 [Byte1]: 76
1821 12:17:51.070125
1822 12:17:51.070210 Final RX Vref Byte 0 = 51 to rank0
1823 12:17:51.073461 Final RX Vref Byte 1 = 61 to rank0
1824 12:17:51.076851 Final RX Vref Byte 0 = 51 to rank1
1825 12:17:51.079957 Final RX Vref Byte 1 = 61 to rank1==
1826 12:17:51.083518 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 12:17:51.090129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 12:17:51.090220 ==
1829 12:17:51.090288 DQS Delay:
1830 12:17:51.090349 DQS0 = 0, DQS1 = 0
1831 12:17:51.093286 DQM Delay:
1832 12:17:51.093375 DQM0 = 92, DQM1 = 83
1833 12:17:51.096645 DQ Delay:
1834 12:17:51.099880 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1835 12:17:51.103324 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1836 12:17:51.103410 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1837 12:17:51.110013 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
1838 12:17:51.110105
1839 12:17:51.110172
1840 12:17:51.116919 [DQSOSCAuto] RK0, (LSB)MR18= 0x314e, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1841 12:17:51.119960 CH1 RK0: MR19=606, MR18=314E
1842 12:17:51.126602 CH1_RK0: MR19=0x606, MR18=0x314E, DQSOSC=390, MR23=63, INC=97, DEC=64
1843 12:17:51.126693
1844 12:17:51.130068 ----->DramcWriteLeveling(PI) begin...
1845 12:17:51.130154 ==
1846 12:17:51.133393 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 12:17:51.136885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 12:17:51.137005 ==
1849 12:17:51.139911 Write leveling (Byte 0): 25 => 25
1850 12:17:51.143222 Write leveling (Byte 1): 32 => 32
1851 12:17:51.146664 DramcWriteLeveling(PI) end<-----
1852 12:17:51.146750
1853 12:17:51.146817 ==
1854 12:17:51.150440 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 12:17:51.153797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 12:17:51.153884 ==
1857 12:17:51.157082 [Gating] SW mode calibration
1858 12:17:51.163562 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 12:17:51.170158 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 12:17:51.173848 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1861 12:17:51.176969 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1862 12:17:51.183718 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:17:51.186858 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:17:51.190091 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:17:51.197159 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:17:51.200275 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:17:51.203372 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:17:51.210371 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:17:51.213669 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:17:51.216897 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:17:51.223267 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:17:51.227096 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:17:51.230009 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:17:51.233511 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:17:51.240190 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:17:51.243479 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1877 12:17:51.247026 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1878 12:17:51.253546 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:17:51.256926 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:17:51.260275 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:17:51.266670 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:17:51.270318 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:17:51.273489 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:17:51.280022 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:17:51.283546 0 9 4 | B1->B0 | 2626 2323 | 1 0 | (1 1) (0 0)
1886 12:17:51.287013 0 9 8 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 0)
1887 12:17:51.293672 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 12:17:51.297169 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 12:17:51.300178 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 12:17:51.307250 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 12:17:51.310325 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 12:17:51.313456 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 12:17:51.316828 0 10 4 | B1->B0 | 2f2f 3232 | 0 1 | (1 0) (1 0)
1894 12:17:51.323586 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1895 12:17:51.327051 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:17:51.330281 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:17:51.337043 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:17:51.340198 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:17:51.343710 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:17:51.350642 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:17:51.353945 0 11 4 | B1->B0 | 3333 2929 | 0 0 | (0 0) (0 0)
1902 12:17:51.356869 0 11 8 | B1->B0 | 4646 3c3c | 0 1 | (0 0) (0 0)
1903 12:17:51.363933 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 12:17:51.366942 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 12:17:51.370427 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 12:17:51.377213 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 12:17:51.380284 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 12:17:51.383997 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 12:17:51.390344 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1910 12:17:51.393762 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 12:17:51.396988 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 12:17:51.400557 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 12:17:51.406999 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:17:51.410497 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:17:51.413801 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 12:17:51.420489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:17:51.424048 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 12:17:51.427493 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 12:17:51.433791 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:17:51.437056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:17:51.440484 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:17:51.447061 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:17:51.450442 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:17:51.453955 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:17:51.460499 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 12:17:51.460594 Total UI for P1: 0, mck2ui 16
1927 12:17:51.467154 best dqsien dly found for B0: ( 0, 14, 2)
1928 12:17:51.467251 Total UI for P1: 0, mck2ui 16
1929 12:17:51.470509 best dqsien dly found for B1: ( 0, 14, 2)
1930 12:17:51.477032 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1931 12:17:51.480394 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1932 12:17:51.480489
1933 12:17:51.484156 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1934 12:17:51.487200 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1935 12:17:51.490819 [Gating] SW calibration Done
1936 12:17:51.490910 ==
1937 12:17:51.493892 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 12:17:51.497068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 12:17:51.497161 ==
1940 12:17:51.497248 RX Vref Scan: 0
1941 12:17:51.500653
1942 12:17:51.500740 RX Vref 0 -> 0, step: 1
1943 12:17:51.500844
1944 12:17:51.503943 RX Delay -130 -> 252, step: 16
1945 12:17:51.507169 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1946 12:17:51.510834 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1947 12:17:51.517275 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1948 12:17:51.520617 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1949 12:17:51.523821 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1950 12:17:51.527320 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1951 12:17:51.530610 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1952 12:17:51.537267 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1953 12:17:51.540490 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1954 12:17:51.544175 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1955 12:17:51.547526 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1956 12:17:51.550528 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1957 12:17:51.557284 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1958 12:17:51.560941 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1959 12:17:51.564129 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1960 12:17:51.567348 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1961 12:17:51.567436 ==
1962 12:17:51.570785 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 12:17:51.577354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 12:17:51.577470 ==
1965 12:17:51.577549 DQS Delay:
1966 12:17:51.577614 DQS0 = 0, DQS1 = 0
1967 12:17:51.580523 DQM Delay:
1968 12:17:51.580608 DQM0 = 89, DQM1 = 85
1969 12:17:51.583990 DQ Delay:
1970 12:17:51.587145 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1971 12:17:51.590322 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1972 12:17:51.594024 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1973 12:17:51.597415 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1974 12:17:51.597529
1975 12:17:51.597618
1976 12:17:51.597682 ==
1977 12:17:51.600646 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 12:17:51.603946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 12:17:51.604065 ==
1980 12:17:51.604167
1981 12:17:51.604266
1982 12:17:51.607350 TX Vref Scan disable
1983 12:17:51.607497 == TX Byte 0 ==
1984 12:17:51.614346 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1985 12:17:51.617201 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1986 12:17:51.617292 == TX Byte 1 ==
1987 12:17:51.623969 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1988 12:17:51.627409 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1989 12:17:51.627505 ==
1990 12:17:51.631106 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 12:17:51.633893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 12:17:51.633982 ==
1993 12:17:51.648387 TX Vref=22, minBit 13, minWin=27, winSum=449
1994 12:17:51.651917 TX Vref=24, minBit 8, minWin=27, winSum=453
1995 12:17:51.655430 TX Vref=26, minBit 9, minWin=27, winSum=451
1996 12:17:51.658479 TX Vref=28, minBit 8, minWin=27, winSum=460
1997 12:17:51.661741 TX Vref=30, minBit 8, minWin=28, winSum=461
1998 12:17:51.665422 TX Vref=32, minBit 8, minWin=27, winSum=457
1999 12:17:51.672114 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
2000 12:17:51.672223
2001 12:17:51.675361 Final TX Range 1 Vref 30
2002 12:17:51.675450
2003 12:17:51.675517 ==
2004 12:17:51.678414 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 12:17:51.681808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 12:17:51.681897 ==
2007 12:17:51.681966
2008 12:17:51.685208
2009 12:17:51.685296 TX Vref Scan disable
2010 12:17:51.688539 == TX Byte 0 ==
2011 12:17:51.692242 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2012 12:17:51.695195 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2013 12:17:51.698509 == TX Byte 1 ==
2014 12:17:51.702289 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2015 12:17:51.705880 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2016 12:17:51.705969
2017 12:17:51.708878 [DATLAT]
2018 12:17:51.709002 Freq=800, CH1 RK1
2019 12:17:51.709069
2020 12:17:51.712156 DATLAT Default: 0xa
2021 12:17:51.712239 0, 0xFFFF, sum = 0
2022 12:17:51.715282 1, 0xFFFF, sum = 0
2023 12:17:51.715367 2, 0xFFFF, sum = 0
2024 12:17:51.718968 3, 0xFFFF, sum = 0
2025 12:17:51.719052 4, 0xFFFF, sum = 0
2026 12:17:51.722292 5, 0xFFFF, sum = 0
2027 12:17:51.722376 6, 0xFFFF, sum = 0
2028 12:17:51.725737 7, 0xFFFF, sum = 0
2029 12:17:51.725822 8, 0xFFFF, sum = 0
2030 12:17:51.728877 9, 0x0, sum = 1
2031 12:17:51.728981 10, 0x0, sum = 2
2032 12:17:51.732147 11, 0x0, sum = 3
2033 12:17:51.732232 12, 0x0, sum = 4
2034 12:17:51.735624 best_step = 10
2035 12:17:51.735722
2036 12:17:51.735789 ==
2037 12:17:51.738667 Dram Type= 6, Freq= 0, CH_1, rank 1
2038 12:17:51.742143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2039 12:17:51.742232 ==
2040 12:17:51.745317 RX Vref Scan: 0
2041 12:17:51.745425
2042 12:17:51.745520 RX Vref 0 -> 0, step: 1
2043 12:17:51.745612
2044 12:17:51.749138 RX Delay -79 -> 252, step: 8
2045 12:17:51.755598 iDelay=209, Bit 0, Center 100 (9 ~ 192) 184
2046 12:17:51.758636 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2047 12:17:51.762072 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2048 12:17:51.765272 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2049 12:17:51.768542 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2050 12:17:51.775300 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2051 12:17:51.778692 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2052 12:17:51.781885 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2053 12:17:51.785359 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2054 12:17:51.788915 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2055 12:17:51.792128 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2056 12:17:51.798792 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2057 12:17:51.802044 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2058 12:17:51.805357 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2059 12:17:51.808572 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2060 12:17:51.815359 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2061 12:17:51.815454 ==
2062 12:17:51.819257 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 12:17:51.822255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 12:17:51.822369 ==
2065 12:17:51.822465 DQS Delay:
2066 12:17:51.825482 DQS0 = 0, DQS1 = 0
2067 12:17:51.825594 DQM Delay:
2068 12:17:51.828924 DQM0 = 92, DQM1 = 84
2069 12:17:51.829026 DQ Delay:
2070 12:17:51.832041 DQ0 =100, DQ1 =84, DQ2 =84, DQ3 =88
2071 12:17:51.835571 DQ4 =96, DQ5 =100, DQ6 =96, DQ7 =88
2072 12:17:51.838767 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2073 12:17:51.842307 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2074 12:17:51.842397
2075 12:17:51.842467
2076 12:17:51.848875 [DQSOSCAuto] RK1, (LSB)MR18= 0x390f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2077 12:17:51.851992 CH1 RK1: MR19=606, MR18=390F
2078 12:17:51.859177 CH1_RK1: MR19=0x606, MR18=0x390F, DQSOSC=395, MR23=63, INC=94, DEC=63
2079 12:17:51.862153 [RxdqsGatingPostProcess] freq 800
2080 12:17:51.865518 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2081 12:17:51.869067 Pre-setting of DQS Precalculation
2082 12:17:51.875344 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2083 12:17:51.882284 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2084 12:17:51.889134 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2085 12:17:51.889251
2086 12:17:51.889323
2087 12:17:51.892178 [Calibration Summary] 1600 Mbps
2088 12:17:51.895951 CH 0, Rank 0
2089 12:17:51.896048 SW Impedance : PASS
2090 12:17:51.898969 DUTY Scan : NO K
2091 12:17:51.899056 ZQ Calibration : PASS
2092 12:17:51.902493 Jitter Meter : NO K
2093 12:17:51.905703 CBT Training : PASS
2094 12:17:51.905791 Write leveling : PASS
2095 12:17:51.908864 RX DQS gating : PASS
2096 12:17:51.912320 RX DQ/DQS(RDDQC) : PASS
2097 12:17:51.912410 TX DQ/DQS : PASS
2098 12:17:51.915565 RX DATLAT : PASS
2099 12:17:51.918895 RX DQ/DQS(Engine): PASS
2100 12:17:51.918984 TX OE : NO K
2101 12:17:51.922272 All Pass.
2102 12:17:51.922362
2103 12:17:51.922429 CH 0, Rank 1
2104 12:17:51.925439 SW Impedance : PASS
2105 12:17:51.925525 DUTY Scan : NO K
2106 12:17:51.929340 ZQ Calibration : PASS
2107 12:17:51.932173 Jitter Meter : NO K
2108 12:17:51.932261 CBT Training : PASS
2109 12:17:51.935439 Write leveling : PASS
2110 12:17:51.935526 RX DQS gating : PASS
2111 12:17:51.938974 RX DQ/DQS(RDDQC) : PASS
2112 12:17:51.942163 TX DQ/DQS : PASS
2113 12:17:51.942269 RX DATLAT : PASS
2114 12:17:51.945614 RX DQ/DQS(Engine): PASS
2115 12:17:51.948852 TX OE : NO K
2116 12:17:51.949005 All Pass.
2117 12:17:51.949075
2118 12:17:51.949135 CH 1, Rank 0
2119 12:17:51.952581 SW Impedance : PASS
2120 12:17:51.955522 DUTY Scan : NO K
2121 12:17:51.955611 ZQ Calibration : PASS
2122 12:17:51.958916 Jitter Meter : NO K
2123 12:17:51.962333 CBT Training : PASS
2124 12:17:51.962423 Write leveling : PASS
2125 12:17:51.965561 RX DQS gating : PASS
2126 12:17:51.969397 RX DQ/DQS(RDDQC) : PASS
2127 12:17:51.969488 TX DQ/DQS : PASS
2128 12:17:51.972370 RX DATLAT : PASS
2129 12:17:51.972457 RX DQ/DQS(Engine): PASS
2130 12:17:51.975662 TX OE : NO K
2131 12:17:51.975751 All Pass.
2132 12:17:51.975819
2133 12:17:51.979043 CH 1, Rank 1
2134 12:17:51.979130 SW Impedance : PASS
2135 12:17:51.982568 DUTY Scan : NO K
2136 12:17:51.985872 ZQ Calibration : PASS
2137 12:17:51.985961 Jitter Meter : NO K
2138 12:17:51.989094 CBT Training : PASS
2139 12:17:51.992251 Write leveling : PASS
2140 12:17:51.992355 RX DQS gating : PASS
2141 12:17:51.995720 RX DQ/DQS(RDDQC) : PASS
2142 12:17:51.999277 TX DQ/DQS : PASS
2143 12:17:51.999394 RX DATLAT : PASS
2144 12:17:52.002398 RX DQ/DQS(Engine): PASS
2145 12:17:52.005691 TX OE : NO K
2146 12:17:52.005778 All Pass.
2147 12:17:52.005846
2148 12:17:52.005908 DramC Write-DBI off
2149 12:17:52.009116 PER_BANK_REFRESH: Hybrid Mode
2150 12:17:52.012385 TX_TRACKING: ON
2151 12:17:52.015894 [GetDramInforAfterCalByMRR] Vendor 6.
2152 12:17:52.019260 [GetDramInforAfterCalByMRR] Revision 606.
2153 12:17:52.022757 [GetDramInforAfterCalByMRR] Revision 2 0.
2154 12:17:52.022853 MR0 0x3b3b
2155 12:17:52.026116 MR8 0x5151
2156 12:17:52.029079 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 12:17:52.029167
2158 12:17:52.029235 MR0 0x3b3b
2159 12:17:52.029297 MR8 0x5151
2160 12:17:52.032707 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 12:17:52.035657
2162 12:17:52.042515 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2163 12:17:52.045692 [FAST_K] Save calibration result to emmc
2164 12:17:52.049157 [FAST_K] Save calibration result to emmc
2165 12:17:52.052324 dram_init: config_dvfs: 1
2166 12:17:52.056152 dramc_set_vcore_voltage set vcore to 662500
2167 12:17:52.059402 Read voltage for 1200, 2
2168 12:17:52.059498 Vio18 = 0
2169 12:17:52.062694 Vcore = 662500
2170 12:17:52.062782 Vdram = 0
2171 12:17:52.062850 Vddq = 0
2172 12:17:52.062912 Vmddr = 0
2173 12:17:52.069278 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2174 12:17:52.072553 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2175 12:17:52.075968 MEM_TYPE=3, freq_sel=15
2176 12:17:52.079063 sv_algorithm_assistance_LP4_1600
2177 12:17:52.082453 ============ PULL DRAM RESETB DOWN ============
2178 12:17:52.089555 ========== PULL DRAM RESETB DOWN end =========
2179 12:17:52.092685 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2180 12:17:52.095900 ===================================
2181 12:17:52.099299 LPDDR4 DRAM CONFIGURATION
2182 12:17:52.102436 ===================================
2183 12:17:52.102526 EX_ROW_EN[0] = 0x0
2184 12:17:52.106032 EX_ROW_EN[1] = 0x0
2185 12:17:52.106145 LP4Y_EN = 0x0
2186 12:17:52.109126 WORK_FSP = 0x0
2187 12:17:52.109285 WL = 0x4
2188 12:17:52.112528 RL = 0x4
2189 12:17:52.112635 BL = 0x2
2190 12:17:52.116234 RPST = 0x0
2191 12:17:52.116325 RD_PRE = 0x0
2192 12:17:52.119388 WR_PRE = 0x1
2193 12:17:52.119485 WR_PST = 0x0
2194 12:17:52.122579 DBI_WR = 0x0
2195 12:17:52.122671 DBI_RD = 0x0
2196 12:17:52.125900 OTF = 0x1
2197 12:17:52.129157 ===================================
2198 12:17:52.132511 ===================================
2199 12:17:52.132621 ANA top config
2200 12:17:52.135909 ===================================
2201 12:17:52.139096 DLL_ASYNC_EN = 0
2202 12:17:52.142316 ALL_SLAVE_EN = 0
2203 12:17:52.145875 NEW_RANK_MODE = 1
2204 12:17:52.145969 DLL_IDLE_MODE = 1
2205 12:17:52.149214 LP45_APHY_COMB_EN = 1
2206 12:17:52.152852 TX_ODT_DIS = 1
2207 12:17:52.155812 NEW_8X_MODE = 1
2208 12:17:52.159500 ===================================
2209 12:17:52.162587 ===================================
2210 12:17:52.165876 data_rate = 2400
2211 12:17:52.165970 CKR = 1
2212 12:17:52.169209 DQ_P2S_RATIO = 8
2213 12:17:52.172415 ===================================
2214 12:17:52.175799 CA_P2S_RATIO = 8
2215 12:17:52.179418 DQ_CA_OPEN = 0
2216 12:17:52.182523 DQ_SEMI_OPEN = 0
2217 12:17:52.185815 CA_SEMI_OPEN = 0
2218 12:17:52.185902 CA_FULL_RATE = 0
2219 12:17:52.189617 DQ_CKDIV4_EN = 0
2220 12:17:52.192674 CA_CKDIV4_EN = 0
2221 12:17:52.195934 CA_PREDIV_EN = 0
2222 12:17:52.199312 PH8_DLY = 17
2223 12:17:52.202795 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2224 12:17:52.202895 DQ_AAMCK_DIV = 4
2225 12:17:52.206018 CA_AAMCK_DIV = 4
2226 12:17:52.209486 CA_ADMCK_DIV = 4
2227 12:17:52.212690 DQ_TRACK_CA_EN = 0
2228 12:17:52.216143 CA_PICK = 1200
2229 12:17:52.219621 CA_MCKIO = 1200
2230 12:17:52.219717 MCKIO_SEMI = 0
2231 12:17:52.222793 PLL_FREQ = 2366
2232 12:17:52.226188 DQ_UI_PI_RATIO = 32
2233 12:17:52.229190 CA_UI_PI_RATIO = 0
2234 12:17:52.232626 ===================================
2235 12:17:52.236105 ===================================
2236 12:17:52.239371 memory_type:LPDDR4
2237 12:17:52.239473 GP_NUM : 10
2238 12:17:52.242795 SRAM_EN : 1
2239 12:17:52.245809 MD32_EN : 0
2240 12:17:52.249645 ===================================
2241 12:17:52.249782 [ANA_INIT] >>>>>>>>>>>>>>
2242 12:17:52.252925 <<<<<< [CONFIGURE PHASE]: ANA_TX
2243 12:17:52.256028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2244 12:17:52.259537 ===================================
2245 12:17:52.262953 data_rate = 2400,PCW = 0X5b00
2246 12:17:52.266107 ===================================
2247 12:17:52.269469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2248 12:17:52.276233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2249 12:17:52.279798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 12:17:52.286283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2251 12:17:52.289593 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2252 12:17:52.292869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2253 12:17:52.292981 [ANA_INIT] flow start
2254 12:17:52.296162 [ANA_INIT] PLL >>>>>>>>
2255 12:17:52.299479 [ANA_INIT] PLL <<<<<<<<
2256 12:17:52.299567 [ANA_INIT] MIDPI >>>>>>>>
2257 12:17:52.303176 [ANA_INIT] MIDPI <<<<<<<<
2258 12:17:52.306169 [ANA_INIT] DLL >>>>>>>>
2259 12:17:52.306254 [ANA_INIT] DLL <<<<<<<<
2260 12:17:52.309729 [ANA_INIT] flow end
2261 12:17:52.312941 ============ LP4 DIFF to SE enter ============
2262 12:17:52.316393 ============ LP4 DIFF to SE exit ============
2263 12:17:52.319771 [ANA_INIT] <<<<<<<<<<<<<
2264 12:17:52.322757 [Flow] Enable top DCM control >>>>>
2265 12:17:52.326074 [Flow] Enable top DCM control <<<<<
2266 12:17:52.329659 Enable DLL master slave shuffle
2267 12:17:52.336294 ==============================================================
2268 12:17:52.336410 Gating Mode config
2269 12:17:52.342861 ==============================================================
2270 12:17:52.342958 Config description:
2271 12:17:52.352669 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2272 12:17:52.359651 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2273 12:17:52.366444 SELPH_MODE 0: By rank 1: By Phase
2274 12:17:52.369975 ==============================================================
2275 12:17:52.373165 GAT_TRACK_EN = 1
2276 12:17:52.376091 RX_GATING_MODE = 2
2277 12:17:52.379669 RX_GATING_TRACK_MODE = 2
2278 12:17:52.382973 SELPH_MODE = 1
2279 12:17:52.386550 PICG_EARLY_EN = 1
2280 12:17:52.389410 VALID_LAT_VALUE = 1
2281 12:17:52.396403 ==============================================================
2282 12:17:52.399769 Enter into Gating configuration >>>>
2283 12:17:52.402913 Exit from Gating configuration <<<<
2284 12:17:52.403005 Enter into DVFS_PRE_config >>>>>
2285 12:17:52.416304 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2286 12:17:52.419446 Exit from DVFS_PRE_config <<<<<
2287 12:17:52.423310 Enter into PICG configuration >>>>
2288 12:17:52.426168 Exit from PICG configuration <<<<
2289 12:17:52.426256 [RX_INPUT] configuration >>>>>
2290 12:17:52.429619 [RX_INPUT] configuration <<<<<
2291 12:17:52.436259 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2292 12:17:52.439567 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2293 12:17:52.446339 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 12:17:52.453224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 12:17:52.459540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 12:17:52.466383 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 12:17:52.469858 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2298 12:17:52.473261 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2299 12:17:52.476334 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2300 12:17:52.482932 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2301 12:17:52.486263 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2302 12:17:52.489827 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2303 12:17:52.492927 ===================================
2304 12:17:52.496123 LPDDR4 DRAM CONFIGURATION
2305 12:17:52.499644 ===================================
2306 12:17:52.502739 EX_ROW_EN[0] = 0x0
2307 12:17:52.502826 EX_ROW_EN[1] = 0x0
2308 12:17:52.506416 LP4Y_EN = 0x0
2309 12:17:52.506528 WORK_FSP = 0x0
2310 12:17:52.509575 WL = 0x4
2311 12:17:52.509662 RL = 0x4
2312 12:17:52.513238 BL = 0x2
2313 12:17:52.513323 RPST = 0x0
2314 12:17:52.516583 RD_PRE = 0x0
2315 12:17:52.516693 WR_PRE = 0x1
2316 12:17:52.519519 WR_PST = 0x0
2317 12:17:52.519604 DBI_WR = 0x0
2318 12:17:52.523039 DBI_RD = 0x0
2319 12:17:52.523124 OTF = 0x1
2320 12:17:52.526413 ===================================
2321 12:17:52.529875 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2322 12:17:52.536322 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2323 12:17:52.540071 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 12:17:52.543342 ===================================
2325 12:17:52.546658 LPDDR4 DRAM CONFIGURATION
2326 12:17:52.549844 ===================================
2327 12:17:52.549932 EX_ROW_EN[0] = 0x10
2328 12:17:52.553312 EX_ROW_EN[1] = 0x0
2329 12:17:52.553399 LP4Y_EN = 0x0
2330 12:17:52.556864 WORK_FSP = 0x0
2331 12:17:52.556968 WL = 0x4
2332 12:17:52.559951 RL = 0x4
2333 12:17:52.563290 BL = 0x2
2334 12:17:52.563374 RPST = 0x0
2335 12:17:52.566773 RD_PRE = 0x0
2336 12:17:52.566858 WR_PRE = 0x1
2337 12:17:52.570169 WR_PST = 0x0
2338 12:17:52.570263 DBI_WR = 0x0
2339 12:17:52.573456 DBI_RD = 0x0
2340 12:17:52.573562 OTF = 0x1
2341 12:17:52.576791 ===================================
2342 12:17:52.583206 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2343 12:17:52.583292 ==
2344 12:17:52.586778 Dram Type= 6, Freq= 0, CH_0, rank 0
2345 12:17:52.590025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2346 12:17:52.590108 ==
2347 12:17:52.593171 [Duty_Offset_Calibration]
2348 12:17:52.596555 B0:2 B1:0 CA:1
2349 12:17:52.596641
2350 12:17:52.599994 [DutyScan_Calibration_Flow] k_type=0
2351 12:17:52.607010
2352 12:17:52.607096 ==CLK 0==
2353 12:17:52.610045 Final CLK duty delay cell = -4
2354 12:17:52.613674 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2355 12:17:52.616804 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2356 12:17:52.620269 [-4] AVG Duty = 4953%(X100)
2357 12:17:52.620378
2358 12:17:52.623594 CH0 CLK Duty spec in!! Max-Min= 156%
2359 12:17:52.627185 [DutyScan_Calibration_Flow] ====Done====
2360 12:17:52.627276
2361 12:17:52.630232 [DutyScan_Calibration_Flow] k_type=1
2362 12:17:52.645690
2363 12:17:52.645789 ==DQS 0 ==
2364 12:17:52.648891 Final DQS duty delay cell = 0
2365 12:17:52.652467 [0] MAX Duty = 5187%(X100), DQS PI = 30
2366 12:17:52.656027 [0] MIN Duty = 4938%(X100), DQS PI = 0
2367 12:17:52.656120 [0] AVG Duty = 5062%(X100)
2368 12:17:52.659457
2369 12:17:52.659550 ==DQS 1 ==
2370 12:17:52.662542 Final DQS duty delay cell = -4
2371 12:17:52.665817 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2372 12:17:52.669196 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2373 12:17:52.672478 [-4] AVG Duty = 5031%(X100)
2374 12:17:52.672561
2375 12:17:52.675804 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2376 12:17:52.675886
2377 12:17:52.679268 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2378 12:17:52.682667 [DutyScan_Calibration_Flow] ====Done====
2379 12:17:52.682750
2380 12:17:52.685794 [DutyScan_Calibration_Flow] k_type=3
2381 12:17:52.702503
2382 12:17:52.702604 ==DQM 0 ==
2383 12:17:52.705975 Final DQM duty delay cell = 0
2384 12:17:52.709086 [0] MAX Duty = 5062%(X100), DQS PI = 24
2385 12:17:52.712755 [0] MIN Duty = 4875%(X100), DQS PI = 0
2386 12:17:52.712871 [0] AVG Duty = 4968%(X100)
2387 12:17:52.715950
2388 12:17:52.716033 ==DQM 1 ==
2389 12:17:52.719258 Final DQM duty delay cell = 0
2390 12:17:52.722612 [0] MAX Duty = 5187%(X100), DQS PI = 48
2391 12:17:52.725922 [0] MIN Duty = 5000%(X100), DQS PI = 14
2392 12:17:52.726006 [0] AVG Duty = 5093%(X100)
2393 12:17:52.726072
2394 12:17:52.732621 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2395 12:17:52.732705
2396 12:17:52.736117 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2397 12:17:52.739290 [DutyScan_Calibration_Flow] ====Done====
2398 12:17:52.739375
2399 12:17:52.742722 [DutyScan_Calibration_Flow] k_type=2
2400 12:17:52.758184
2401 12:17:52.758305 ==DQ 0 ==
2402 12:17:52.762097 Final DQ duty delay cell = -4
2403 12:17:52.764972 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2404 12:17:52.768454 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2405 12:17:52.771863 [-4] AVG Duty = 4953%(X100)
2406 12:17:52.771946
2407 12:17:52.772012 ==DQ 1 ==
2408 12:17:52.774940 Final DQ duty delay cell = 0
2409 12:17:52.778425 [0] MAX Duty = 4938%(X100), DQS PI = 6
2410 12:17:52.781974 [0] MIN Duty = 4907%(X100), DQS PI = 0
2411 12:17:52.782057 [0] AVG Duty = 4922%(X100)
2412 12:17:52.782122
2413 12:17:52.785051 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2414 12:17:52.788318
2415 12:17:52.791959 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2416 12:17:52.794917 [DutyScan_Calibration_Flow] ====Done====
2417 12:17:52.795007 ==
2418 12:17:52.798417 Dram Type= 6, Freq= 0, CH_1, rank 0
2419 12:17:52.801956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2420 12:17:52.802040 ==
2421 12:17:52.805134 [Duty_Offset_Calibration]
2422 12:17:52.805216 B0:0 B1:-1 CA:2
2423 12:17:52.805282
2424 12:17:52.808482 [DutyScan_Calibration_Flow] k_type=0
2425 12:17:52.818477
2426 12:17:52.818567 ==CLK 0==
2427 12:17:52.821938 Final CLK duty delay cell = 0
2428 12:17:52.824941 [0] MAX Duty = 5156%(X100), DQS PI = 16
2429 12:17:52.828242 [0] MIN Duty = 4938%(X100), DQS PI = 44
2430 12:17:52.828326 [0] AVG Duty = 5047%(X100)
2431 12:17:52.831760
2432 12:17:52.834978 CH1 CLK Duty spec in!! Max-Min= 218%
2433 12:17:52.838493 [DutyScan_Calibration_Flow] ====Done====
2434 12:17:52.838576
2435 12:17:52.841743 [DutyScan_Calibration_Flow] k_type=1
2436 12:17:52.858094
2437 12:17:52.858188 ==DQS 0 ==
2438 12:17:52.861206 Final DQS duty delay cell = 0
2439 12:17:52.864429 [0] MAX Duty = 5093%(X100), DQS PI = 24
2440 12:17:52.867950 [0] MIN Duty = 4969%(X100), DQS PI = 0
2441 12:17:52.868035 [0] AVG Duty = 5031%(X100)
2442 12:17:52.871080
2443 12:17:52.871162 ==DQS 1 ==
2444 12:17:52.874652 Final DQS duty delay cell = 0
2445 12:17:52.877800 [0] MAX Duty = 5156%(X100), DQS PI = 0
2446 12:17:52.881223 [0] MIN Duty = 4844%(X100), DQS PI = 36
2447 12:17:52.881307 [0] AVG Duty = 5000%(X100)
2448 12:17:52.881373
2449 12:17:52.887727 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2450 12:17:52.887812
2451 12:17:52.891490 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2452 12:17:52.894571 [DutyScan_Calibration_Flow] ====Done====
2453 12:17:52.894656
2454 12:17:52.897940 [DutyScan_Calibration_Flow] k_type=3
2455 12:17:52.914321
2456 12:17:52.914419 ==DQM 0 ==
2457 12:17:52.917571 Final DQM duty delay cell = 4
2458 12:17:52.920965 [4] MAX Duty = 5093%(X100), DQS PI = 6
2459 12:17:52.924192 [4] MIN Duty = 4938%(X100), DQS PI = 48
2460 12:17:52.924279 [4] AVG Duty = 5015%(X100)
2461 12:17:52.927823
2462 12:17:52.927907 ==DQM 1 ==
2463 12:17:52.931041 Final DQM duty delay cell = -4
2464 12:17:52.934114 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2465 12:17:52.938111 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2466 12:17:52.941119 [-4] AVG Duty = 4875%(X100)
2467 12:17:52.941203
2468 12:17:52.944446 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2469 12:17:52.944531
2470 12:17:52.947515 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2471 12:17:52.950829 [DutyScan_Calibration_Flow] ====Done====
2472 12:17:52.950913
2473 12:17:52.954124 [DutyScan_Calibration_Flow] k_type=2
2474 12:17:52.971034
2475 12:17:52.971151 ==DQ 0 ==
2476 12:17:52.974532 Final DQ duty delay cell = 0
2477 12:17:52.977638 [0] MAX Duty = 5062%(X100), DQS PI = 22
2478 12:17:52.981096 [0] MIN Duty = 4938%(X100), DQS PI = 30
2479 12:17:52.981181 [0] AVG Duty = 5000%(X100)
2480 12:17:52.981250
2481 12:17:52.984294 ==DQ 1 ==
2482 12:17:52.987641 Final DQ duty delay cell = 0
2483 12:17:52.990990 [0] MAX Duty = 5031%(X100), DQS PI = 0
2484 12:17:52.994574 [0] MIN Duty = 4813%(X100), DQS PI = 36
2485 12:17:52.994659 [0] AVG Duty = 4922%(X100)
2486 12:17:52.994727
2487 12:17:52.998117 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2488 12:17:52.998207
2489 12:17:53.001294 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2490 12:17:53.007724 [DutyScan_Calibration_Flow] ====Done====
2491 12:17:53.011576 nWR fixed to 30
2492 12:17:53.011671 [ModeRegInit_LP4] CH0 RK0
2493 12:17:53.014646 [ModeRegInit_LP4] CH0 RK1
2494 12:17:53.018142 [ModeRegInit_LP4] CH1 RK0
2495 12:17:53.018227 [ModeRegInit_LP4] CH1 RK1
2496 12:17:53.021249 match AC timing 7
2497 12:17:53.024820 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2498 12:17:53.027936 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2499 12:17:53.034482 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2500 12:17:53.037926 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2501 12:17:53.044721 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2502 12:17:53.044809 ==
2503 12:17:53.047806 Dram Type= 6, Freq= 0, CH_0, rank 0
2504 12:17:53.051409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2505 12:17:53.051495 ==
2506 12:17:53.057821 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2507 12:17:53.061221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2508 12:17:53.070926 [CA 0] Center 38 (7~69) winsize 63
2509 12:17:53.074384 [CA 1] Center 38 (7~69) winsize 63
2510 12:17:53.077532 [CA 2] Center 34 (4~65) winsize 62
2511 12:17:53.080797 [CA 3] Center 34 (4~65) winsize 62
2512 12:17:53.084255 [CA 4] Center 33 (3~64) winsize 62
2513 12:17:53.087609 [CA 5] Center 33 (3~63) winsize 61
2514 12:17:53.087692
2515 12:17:53.091108 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2516 12:17:53.091193
2517 12:17:53.094250 [CATrainingPosCal] consider 1 rank data
2518 12:17:53.097623 u2DelayCellTimex100 = 270/100 ps
2519 12:17:53.100701 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2520 12:17:53.104469 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2521 12:17:53.110797 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
2522 12:17:53.114554 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2523 12:17:53.117722 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2524 12:17:53.121334 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2525 12:17:53.121417
2526 12:17:53.124445 CA PerBit enable=1, Macro0, CA PI delay=33
2527 12:17:53.124528
2528 12:17:53.127493 [CBTSetCACLKResult] CA Dly = 33
2529 12:17:53.127577 CS Dly: 6 (0~37)
2530 12:17:53.127643 ==
2531 12:17:53.131309 Dram Type= 6, Freq= 0, CH_0, rank 1
2532 12:17:53.137564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 12:17:53.137653 ==
2534 12:17:53.140955 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2535 12:17:53.147637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2536 12:17:53.156713 [CA 0] Center 38 (7~69) winsize 63
2537 12:17:53.160007 [CA 1] Center 38 (8~69) winsize 62
2538 12:17:53.163152 [CA 2] Center 35 (5~66) winsize 62
2539 12:17:53.166512 [CA 3] Center 35 (5~66) winsize 62
2540 12:17:53.170020 [CA 4] Center 34 (3~65) winsize 63
2541 12:17:53.173126 [CA 5] Center 33 (3~64) winsize 62
2542 12:17:53.173209
2543 12:17:53.176668 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2544 12:17:53.176751
2545 12:17:53.180017 [CATrainingPosCal] consider 2 rank data
2546 12:17:53.183360 u2DelayCellTimex100 = 270/100 ps
2547 12:17:53.186385 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2548 12:17:53.189788 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2549 12:17:53.196612 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2550 12:17:53.199927 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2551 12:17:53.203300 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2552 12:17:53.206804 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2553 12:17:53.206887
2554 12:17:53.209681 CA PerBit enable=1, Macro0, CA PI delay=33
2555 12:17:53.209765
2556 12:17:53.213288 [CBTSetCACLKResult] CA Dly = 33
2557 12:17:53.213372 CS Dly: 7 (0~39)
2558 12:17:53.213438
2559 12:17:53.216786 ----->DramcWriteLeveling(PI) begin...
2560 12:17:53.219765 ==
2561 12:17:53.219849 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 12:17:53.226605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 12:17:53.226689 ==
2564 12:17:53.229967 Write leveling (Byte 0): 33 => 33
2565 12:17:53.233226 Write leveling (Byte 1): 33 => 33
2566 12:17:53.233326 DramcWriteLeveling(PI) end<-----
2567 12:17:53.236586
2568 12:17:53.236668 ==
2569 12:17:53.240240 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 12:17:53.243604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 12:17:53.243688 ==
2572 12:17:53.246928 [Gating] SW mode calibration
2573 12:17:53.253240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2574 12:17:53.256674 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2575 12:17:53.263322 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2576 12:17:53.266559 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2577 12:17:53.269907 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 12:17:53.276674 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 12:17:53.279726 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 12:17:53.283474 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 12:17:53.290034 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2582 12:17:53.293455 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2583 12:17:53.296696 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2584 12:17:53.303391 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 12:17:53.306628 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 12:17:53.309892 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 12:17:53.316479 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 12:17:53.320216 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 12:17:53.323396 1 0 24 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2590 12:17:53.326603 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2591 12:17:53.333289 1 1 0 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
2592 12:17:53.336684 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 12:17:53.340101 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 12:17:53.346864 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 12:17:53.350252 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 12:17:53.353313 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 12:17:53.359972 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 12:17:53.363405 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2599 12:17:53.366863 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2600 12:17:53.373376 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 12:17:53.377210 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 12:17:53.380643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 12:17:53.387098 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 12:17:53.390347 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 12:17:53.393999 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 12:17:53.396939 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 12:17:53.403774 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 12:17:53.407224 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 12:17:53.410770 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:17:53.417458 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:17:53.420525 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:17:53.423981 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:17:53.430613 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:17:53.434088 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2615 12:17:53.437193 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2616 12:17:53.440433 Total UI for P1: 0, mck2ui 16
2617 12:17:53.443999 best dqsien dly found for B0: ( 1, 3, 28)
2618 12:17:53.450502 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 12:17:53.450618 Total UI for P1: 0, mck2ui 16
2620 12:17:53.454046 best dqsien dly found for B1: ( 1, 3, 30)
2621 12:17:53.460592 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2622 12:17:53.463699 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2623 12:17:53.463784
2624 12:17:53.467257 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2625 12:17:53.470351 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2626 12:17:53.473837 [Gating] SW calibration Done
2627 12:17:53.473922 ==
2628 12:17:53.477356 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 12:17:53.480835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 12:17:53.480985 ==
2631 12:17:53.483706 RX Vref Scan: 0
2632 12:17:53.483791
2633 12:17:53.483864 RX Vref 0 -> 0, step: 1
2634 12:17:53.483928
2635 12:17:53.487242 RX Delay -40 -> 252, step: 8
2636 12:17:53.490582 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2637 12:17:53.494056 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2638 12:17:53.500894 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2639 12:17:53.503991 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2640 12:17:53.507117 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2641 12:17:53.510477 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2642 12:17:53.513769 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2643 12:17:53.520538 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2644 12:17:53.523924 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2645 12:17:53.527181 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2646 12:17:53.531001 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2647 12:17:53.534086 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2648 12:17:53.540514 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2649 12:17:53.544058 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2650 12:17:53.547400 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2651 12:17:53.551017 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2652 12:17:53.551103 ==
2653 12:17:53.554182 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 12:17:53.560610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 12:17:53.560696 ==
2656 12:17:53.560764 DQS Delay:
2657 12:17:53.560826 DQS0 = 0, DQS1 = 0
2658 12:17:53.564062 DQM Delay:
2659 12:17:53.564147 DQM0 = 123, DQM1 = 110
2660 12:17:53.567525 DQ Delay:
2661 12:17:53.570574 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2662 12:17:53.573928 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2663 12:17:53.577264 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2664 12:17:53.581048 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2665 12:17:53.581135
2666 12:17:53.581202
2667 12:17:53.581263 ==
2668 12:17:53.584164 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 12:17:53.587529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 12:17:53.587615 ==
2671 12:17:53.587683
2672 12:17:53.587744
2673 12:17:53.590595 TX Vref Scan disable
2674 12:17:53.594185 == TX Byte 0 ==
2675 12:17:53.597730 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2676 12:17:53.600653 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2677 12:17:53.604134 == TX Byte 1 ==
2678 12:17:53.607395 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2679 12:17:53.610897 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2680 12:17:53.611010 ==
2681 12:17:53.614339 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 12:17:53.617831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 12:17:53.620702 ==
2684 12:17:53.630751 TX Vref=22, minBit 6, minWin=23, winSum=392
2685 12:17:53.634038 TX Vref=24, minBit 4, minWin=24, winSum=401
2686 12:17:53.637517 TX Vref=26, minBit 0, minWin=24, winSum=398
2687 12:17:53.640935 TX Vref=28, minBit 1, minWin=25, winSum=415
2688 12:17:53.644024 TX Vref=30, minBit 1, minWin=25, winSum=412
2689 12:17:53.647500 TX Vref=32, minBit 1, minWin=25, winSum=411
2690 12:17:53.654065 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 28
2691 12:17:53.654153
2692 12:17:53.657219 Final TX Range 1 Vref 28
2693 12:17:53.657306
2694 12:17:53.657391 ==
2695 12:17:53.661112 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 12:17:53.664243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 12:17:53.664330 ==
2698 12:17:53.664416
2699 12:17:53.667381
2700 12:17:53.667468 TX Vref Scan disable
2701 12:17:53.670635 == TX Byte 0 ==
2702 12:17:53.674092 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2703 12:17:53.677632 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2704 12:17:53.681031 == TX Byte 1 ==
2705 12:17:53.684287 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2706 12:17:53.687417 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2707 12:17:53.687505
2708 12:17:53.691153 [DATLAT]
2709 12:17:53.691238 Freq=1200, CH0 RK0
2710 12:17:53.691324
2711 12:17:53.694182 DATLAT Default: 0xd
2712 12:17:53.694268 0, 0xFFFF, sum = 0
2713 12:17:53.697796 1, 0xFFFF, sum = 0
2714 12:17:53.697887 2, 0xFFFF, sum = 0
2715 12:17:53.701366 3, 0xFFFF, sum = 0
2716 12:17:53.701454 4, 0xFFFF, sum = 0
2717 12:17:53.704513 5, 0xFFFF, sum = 0
2718 12:17:53.704600 6, 0xFFFF, sum = 0
2719 12:17:53.707568 7, 0xFFFF, sum = 0
2720 12:17:53.707656 8, 0xFFFF, sum = 0
2721 12:17:53.711102 9, 0xFFFF, sum = 0
2722 12:17:53.711221 10, 0xFFFF, sum = 0
2723 12:17:53.714439 11, 0xFFFF, sum = 0
2724 12:17:53.714524 12, 0x0, sum = 1
2725 12:17:53.717925 13, 0x0, sum = 2
2726 12:17:53.718011 14, 0x0, sum = 3
2727 12:17:53.721364 15, 0x0, sum = 4
2728 12:17:53.721448 best_step = 13
2729 12:17:53.721514
2730 12:17:53.721576 ==
2731 12:17:53.724418 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 12:17:53.731446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2733 12:17:53.731532 ==
2734 12:17:53.731598 RX Vref Scan: 1
2735 12:17:53.731659
2736 12:17:53.734688 Set Vref Range= 32 -> 127
2737 12:17:53.734772
2738 12:17:53.737819 RX Vref 32 -> 127, step: 1
2739 12:17:53.737902
2740 12:17:53.737968 RX Delay -13 -> 252, step: 4
2741 12:17:53.741249
2742 12:17:53.741333 Set Vref, RX VrefLevel [Byte0]: 32
2743 12:17:53.744290 [Byte1]: 32
2744 12:17:53.748875
2745 12:17:53.748996 Set Vref, RX VrefLevel [Byte0]: 33
2746 12:17:53.752096 [Byte1]: 33
2747 12:17:53.756897
2748 12:17:53.756986 Set Vref, RX VrefLevel [Byte0]: 34
2749 12:17:53.760028 [Byte1]: 34
2750 12:17:53.764509
2751 12:17:53.764593 Set Vref, RX VrefLevel [Byte0]: 35
2752 12:17:53.767983 [Byte1]: 35
2753 12:17:53.772774
2754 12:17:53.772860 Set Vref, RX VrefLevel [Byte0]: 36
2755 12:17:53.776001 [Byte1]: 36
2756 12:17:53.780728
2757 12:17:53.780812 Set Vref, RX VrefLevel [Byte0]: 37
2758 12:17:53.783740 [Byte1]: 37
2759 12:17:53.788150
2760 12:17:53.788236 Set Vref, RX VrefLevel [Byte0]: 38
2761 12:17:53.791850 [Byte1]: 38
2762 12:17:53.796298
2763 12:17:53.796387 Set Vref, RX VrefLevel [Byte0]: 39
2764 12:17:53.799818 [Byte1]: 39
2765 12:17:53.804068
2766 12:17:53.804156 Set Vref, RX VrefLevel [Byte0]: 40
2767 12:17:53.807398 [Byte1]: 40
2768 12:17:53.811942
2769 12:17:53.812029 Set Vref, RX VrefLevel [Byte0]: 41
2770 12:17:53.815095 [Byte1]: 41
2771 12:17:53.820119
2772 12:17:53.820204 Set Vref, RX VrefLevel [Byte0]: 42
2773 12:17:53.823278 [Byte1]: 42
2774 12:17:53.827894
2775 12:17:53.827978 Set Vref, RX VrefLevel [Byte0]: 43
2776 12:17:53.831059 [Byte1]: 43
2777 12:17:53.835710
2778 12:17:53.835795 Set Vref, RX VrefLevel [Byte0]: 44
2779 12:17:53.839149 [Byte1]: 44
2780 12:17:53.843548
2781 12:17:53.843632 Set Vref, RX VrefLevel [Byte0]: 45
2782 12:17:53.850058 [Byte1]: 45
2783 12:17:53.850143
2784 12:17:53.853150 Set Vref, RX VrefLevel [Byte0]: 46
2785 12:17:53.856709 [Byte1]: 46
2786 12:17:53.856794
2787 12:17:53.859945 Set Vref, RX VrefLevel [Byte0]: 47
2788 12:17:53.862935 [Byte1]: 47
2789 12:17:53.867079
2790 12:17:53.867163 Set Vref, RX VrefLevel [Byte0]: 48
2791 12:17:53.870454 [Byte1]: 48
2792 12:17:53.875004
2793 12:17:53.875088 Set Vref, RX VrefLevel [Byte0]: 49
2794 12:17:53.878241 [Byte1]: 49
2795 12:17:53.882991
2796 12:17:53.883075 Set Vref, RX VrefLevel [Byte0]: 50
2797 12:17:53.886355 [Byte1]: 50
2798 12:17:53.890993
2799 12:17:53.891080 Set Vref, RX VrefLevel [Byte0]: 51
2800 12:17:53.894538 [Byte1]: 51
2801 12:17:53.898954
2802 12:17:53.899041 Set Vref, RX VrefLevel [Byte0]: 52
2803 12:17:53.902359 [Byte1]: 52
2804 12:17:53.906672
2805 12:17:53.906755 Set Vref, RX VrefLevel [Byte0]: 53
2806 12:17:53.909844 [Byte1]: 53
2807 12:17:53.914625
2808 12:17:53.914709 Set Vref, RX VrefLevel [Byte0]: 54
2809 12:17:53.917807 [Byte1]: 54
2810 12:17:53.922436
2811 12:17:53.922523 Set Vref, RX VrefLevel [Byte0]: 55
2812 12:17:53.925640 [Byte1]: 55
2813 12:17:53.930230
2814 12:17:53.930314 Set Vref, RX VrefLevel [Byte0]: 56
2815 12:17:53.933716 [Byte1]: 56
2816 12:17:53.938437
2817 12:17:53.938521 Set Vref, RX VrefLevel [Byte0]: 57
2818 12:17:53.941647 [Byte1]: 57
2819 12:17:53.946261
2820 12:17:53.946344 Set Vref, RX VrefLevel [Byte0]: 58
2821 12:17:53.949377 [Byte1]: 58
2822 12:17:53.954043
2823 12:17:53.954128 Set Vref, RX VrefLevel [Byte0]: 59
2824 12:17:53.957302 [Byte1]: 59
2825 12:17:53.961738
2826 12:17:53.961823 Set Vref, RX VrefLevel [Byte0]: 60
2827 12:17:53.965364 [Byte1]: 60
2828 12:17:53.969700
2829 12:17:53.969784 Set Vref, RX VrefLevel [Byte0]: 61
2830 12:17:53.972909 [Byte1]: 61
2831 12:17:53.977571
2832 12:17:53.977655 Set Vref, RX VrefLevel [Byte0]: 62
2833 12:17:53.981153 [Byte1]: 62
2834 12:17:53.985463
2835 12:17:53.985548 Set Vref, RX VrefLevel [Byte0]: 63
2836 12:17:53.988876 [Byte1]: 63
2837 12:17:53.993383
2838 12:17:53.993468 Set Vref, RX VrefLevel [Byte0]: 64
2839 12:17:53.997019 [Byte1]: 64
2840 12:17:54.001256
2841 12:17:54.001343 Set Vref, RX VrefLevel [Byte0]: 65
2842 12:17:54.004874 [Byte1]: 65
2843 12:17:54.009304
2844 12:17:54.009389 Set Vref, RX VrefLevel [Byte0]: 66
2845 12:17:54.015695 [Byte1]: 66
2846 12:17:54.015780
2847 12:17:54.019188 Set Vref, RX VrefLevel [Byte0]: 67
2848 12:17:54.022425 [Byte1]: 67
2849 12:17:54.022509
2850 12:17:54.025766 Set Vref, RX VrefLevel [Byte0]: 68
2851 12:17:54.029275 [Byte1]: 68
2852 12:17:54.033088
2853 12:17:54.033172 Set Vref, RX VrefLevel [Byte0]: 69
2854 12:17:54.036248 [Byte1]: 69
2855 12:17:54.040873
2856 12:17:54.041012 Final RX Vref Byte 0 = 57 to rank0
2857 12:17:54.044427 Final RX Vref Byte 1 = 48 to rank0
2858 12:17:54.047481 Final RX Vref Byte 0 = 57 to rank1
2859 12:17:54.050884 Final RX Vref Byte 1 = 48 to rank1==
2860 12:17:54.054422 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 12:17:54.061024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 12:17:54.061109 ==
2863 12:17:54.061176 DQS Delay:
2864 12:17:54.061238 DQS0 = 0, DQS1 = 0
2865 12:17:54.064179 DQM Delay:
2866 12:17:54.064262 DQM0 = 122, DQM1 = 109
2867 12:17:54.067347 DQ Delay:
2868 12:17:54.070947 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2869 12:17:54.074177 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2870 12:17:54.077531 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2871 12:17:54.080949 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2872 12:17:54.081048
2873 12:17:54.081114
2874 12:17:54.087697 [DQSOSCAuto] RK0, (LSB)MR18= 0xa07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2875 12:17:54.090957 CH0 RK0: MR19=404, MR18=A07
2876 12:17:54.097604 CH0_RK0: MR19=0x404, MR18=0xA07, DQSOSC=406, MR23=63, INC=39, DEC=26
2877 12:17:54.097694
2878 12:17:54.101107 ----->DramcWriteLeveling(PI) begin...
2879 12:17:54.101193 ==
2880 12:17:54.104322 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 12:17:54.108365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 12:17:54.108450 ==
2883 12:17:54.110993 Write leveling (Byte 0): 34 => 34
2884 12:17:54.114600 Write leveling (Byte 1): 31 => 31
2885 12:17:54.117851 DramcWriteLeveling(PI) end<-----
2886 12:17:54.117936
2887 12:17:54.118001 ==
2888 12:17:54.121505 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 12:17:54.124315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 12:17:54.127649 ==
2891 12:17:54.127733 [Gating] SW mode calibration
2892 12:17:54.134351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 12:17:54.141058 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 12:17:54.144330 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2895 12:17:54.151022 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 12:17:54.154273 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 12:17:54.157741 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 12:17:54.164342 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 12:17:54.167686 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 12:17:54.171326 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 12:17:54.177546 0 15 28 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 1)
2902 12:17:54.181104 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2903 12:17:54.184032 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 12:17:54.191244 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 12:17:54.194333 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 12:17:54.197759 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 12:17:54.200902 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 12:17:54.207592 1 0 24 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
2909 12:17:54.211300 1 0 28 | B1->B0 | 3f3f 4545 | 1 0 | (0 0) (0 0)
2910 12:17:54.214637 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 12:17:54.221094 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 12:17:54.224438 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 12:17:54.228090 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 12:17:54.234689 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 12:17:54.237817 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 12:17:54.241247 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 12:17:54.247790 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2918 12:17:54.251594 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 12:17:54.254673 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 12:17:54.261232 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 12:17:54.264510 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 12:17:54.267814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 12:17:54.271274 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 12:17:54.277982 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 12:17:54.281382 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 12:17:54.284950 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 12:17:54.291203 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 12:17:54.294671 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 12:17:54.298237 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:17:54.304723 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:17:54.307966 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:17:54.311506 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2933 12:17:54.318399 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2934 12:17:54.321552 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 12:17:54.324969 Total UI for P1: 0, mck2ui 16
2936 12:17:54.328458 best dqsien dly found for B0: ( 1, 3, 26)
2937 12:17:54.331441 Total UI for P1: 0, mck2ui 16
2938 12:17:54.334950 best dqsien dly found for B1: ( 1, 3, 28)
2939 12:17:54.338366 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2940 12:17:54.341517 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2941 12:17:54.341602
2942 12:17:54.344884 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2943 12:17:54.348017 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2944 12:17:54.351404 [Gating] SW calibration Done
2945 12:17:54.351515 ==
2946 12:17:54.355045 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 12:17:54.358003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 12:17:54.358087 ==
2949 12:17:54.361441 RX Vref Scan: 0
2950 12:17:54.361526
2951 12:17:54.364849 RX Vref 0 -> 0, step: 1
2952 12:17:54.364938
2953 12:17:54.365005 RX Delay -40 -> 252, step: 8
2954 12:17:54.371787 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2955 12:17:54.375077 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2956 12:17:54.378072 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2957 12:17:54.381409 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2958 12:17:54.384673 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2959 12:17:54.391646 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2960 12:17:54.395101 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2961 12:17:54.398005 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2962 12:17:54.401641 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2963 12:17:54.404849 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2964 12:17:54.408354 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2965 12:17:54.414739 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2966 12:17:54.417919 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2967 12:17:54.421691 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2968 12:17:54.424593 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2969 12:17:54.431464 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2970 12:17:54.431551 ==
2971 12:17:54.434868 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 12:17:54.438110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 12:17:54.438195 ==
2974 12:17:54.438262 DQS Delay:
2975 12:17:54.441583 DQS0 = 0, DQS1 = 0
2976 12:17:54.441667 DQM Delay:
2977 12:17:54.445072 DQM0 = 120, DQM1 = 108
2978 12:17:54.445156 DQ Delay:
2979 12:17:54.448282 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2980 12:17:54.451281 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2981 12:17:54.454889 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2982 12:17:54.457894 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2983 12:17:54.457978
2984 12:17:54.458044
2985 12:17:54.458105 ==
2986 12:17:54.461516 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 12:17:54.468105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 12:17:54.468190 ==
2989 12:17:54.468258
2990 12:17:54.468319
2991 12:17:54.468378 TX Vref Scan disable
2992 12:17:54.471665 == TX Byte 0 ==
2993 12:17:54.474989 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2994 12:17:54.481662 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2995 12:17:54.481748 == TX Byte 1 ==
2996 12:17:54.485109 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2997 12:17:54.492015 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2998 12:17:54.492101 ==
2999 12:17:54.494939 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 12:17:54.501410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 12:17:54.501506 ==
3002 12:17:54.510064 TX Vref=22, minBit 2, minWin=23, winSum=394
3003 12:17:54.513131 TX Vref=24, minBit 0, minWin=25, winSum=412
3004 12:17:54.516651 TX Vref=26, minBit 7, minWin=24, winSum=408
3005 12:17:54.519784 TX Vref=28, minBit 1, minWin=24, winSum=413
3006 12:17:54.522995 TX Vref=30, minBit 1, minWin=25, winSum=411
3007 12:17:54.526669 TX Vref=32, minBit 1, minWin=25, winSum=412
3008 12:17:54.533208 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 24
3009 12:17:54.533294
3010 12:17:54.536651 Final TX Range 1 Vref 24
3011 12:17:54.536736
3012 12:17:54.536803 ==
3013 12:17:54.539977 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 12:17:54.543301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 12:17:54.543385 ==
3016 12:17:54.543452
3017 12:17:54.543512
3018 12:17:54.546519 TX Vref Scan disable
3019 12:17:54.549786 == TX Byte 0 ==
3020 12:17:54.553008 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3021 12:17:54.556451 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3022 12:17:54.559880 == TX Byte 1 ==
3023 12:17:54.563338 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3024 12:17:54.567012 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3025 12:17:54.567098
3026 12:17:54.570295 [DATLAT]
3027 12:17:54.570380 Freq=1200, CH0 RK1
3028 12:17:54.570448
3029 12:17:54.573288 DATLAT Default: 0xd
3030 12:17:54.573372 0, 0xFFFF, sum = 0
3031 12:17:54.576682 1, 0xFFFF, sum = 0
3032 12:17:54.576768 2, 0xFFFF, sum = 0
3033 12:17:54.580068 3, 0xFFFF, sum = 0
3034 12:17:54.580153 4, 0xFFFF, sum = 0
3035 12:17:54.583362 5, 0xFFFF, sum = 0
3036 12:17:54.583447 6, 0xFFFF, sum = 0
3037 12:17:54.586739 7, 0xFFFF, sum = 0
3038 12:17:54.586825 8, 0xFFFF, sum = 0
3039 12:17:54.590008 9, 0xFFFF, sum = 0
3040 12:17:54.590094 10, 0xFFFF, sum = 0
3041 12:17:54.593232 11, 0xFFFF, sum = 0
3042 12:17:54.593317 12, 0x0, sum = 1
3043 12:17:54.596832 13, 0x0, sum = 2
3044 12:17:54.596917 14, 0x0, sum = 3
3045 12:17:54.600090 15, 0x0, sum = 4
3046 12:17:54.600176 best_step = 13
3047 12:17:54.600243
3048 12:17:54.600304 ==
3049 12:17:54.603648 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 12:17:54.609915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 12:17:54.610003 ==
3052 12:17:54.610071 RX Vref Scan: 0
3053 12:17:54.610135
3054 12:17:54.613378 RX Vref 0 -> 0, step: 1
3055 12:17:54.613463
3056 12:17:54.616596 RX Delay -21 -> 252, step: 4
3057 12:17:54.620259 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3058 12:17:54.623239 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3059 12:17:54.630072 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3060 12:17:54.633103 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3061 12:17:54.636450 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3062 12:17:54.639743 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3063 12:17:54.643328 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3064 12:17:54.650109 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3065 12:17:54.653293 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3066 12:17:54.656451 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3067 12:17:54.660025 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3068 12:17:54.663343 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3069 12:17:54.670015 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3070 12:17:54.673374 iDelay=195, Bit 13, Center 112 (51 ~ 174) 124
3071 12:17:54.676502 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3072 12:17:54.679926 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3073 12:17:54.680011 ==
3074 12:17:54.683017 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 12:17:54.686505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 12:17:54.689755 ==
3077 12:17:54.689840 DQS Delay:
3078 12:17:54.689907 DQS0 = 0, DQS1 = 0
3079 12:17:54.693327 DQM Delay:
3080 12:17:54.693411 DQM0 = 119, DQM1 = 108
3081 12:17:54.696417 DQ Delay:
3082 12:17:54.699820 DQ0 =116, DQ1 =122, DQ2 =116, DQ3 =114
3083 12:17:54.703481 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3084 12:17:54.706723 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3085 12:17:54.709912 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3086 12:17:54.709997
3087 12:17:54.710063
3088 12:17:54.716724 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 405 ps
3089 12:17:54.720334 CH0 RK1: MR19=403, MR18=DF5
3090 12:17:54.726612 CH0_RK1: MR19=0x403, MR18=0xDF5, DQSOSC=405, MR23=63, INC=39, DEC=26
3091 12:17:54.729913 [RxdqsGatingPostProcess] freq 1200
3092 12:17:54.736596 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 12:17:54.736683 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 12:17:54.740310 best DQS1 dly(2T, 0.5T) = (0, 11)
3095 12:17:54.743327 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 12:17:54.746701 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3097 12:17:54.750053 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 12:17:54.753821 best DQS1 dly(2T, 0.5T) = (0, 11)
3099 12:17:54.756656 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 12:17:54.760228 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3101 12:17:54.763522 Pre-setting of DQS Precalculation
3102 12:17:54.766765 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 12:17:54.770146 ==
3104 12:17:54.770230 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 12:17:54.777043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 12:17:54.777127 ==
3107 12:17:54.779979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 12:17:54.786801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3109 12:17:54.795641 [CA 0] Center 37 (7~67) winsize 61
3110 12:17:54.798958 [CA 1] Center 37 (7~68) winsize 62
3111 12:17:54.802460 [CA 2] Center 34 (4~65) winsize 62
3112 12:17:54.805849 [CA 3] Center 33 (3~64) winsize 62
3113 12:17:54.809043 [CA 4] Center 33 (3~64) winsize 62
3114 12:17:54.812521 [CA 5] Center 33 (3~63) winsize 61
3115 12:17:54.812606
3116 12:17:54.815608 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3117 12:17:54.815692
3118 12:17:54.819389 [CATrainingPosCal] consider 1 rank data
3119 12:17:54.822245 u2DelayCellTimex100 = 270/100 ps
3120 12:17:54.825877 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3121 12:17:54.828936 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 12:17:54.835706 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3123 12:17:54.839148 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3124 12:17:54.842372 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3125 12:17:54.845813 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3126 12:17:54.845898
3127 12:17:54.849267 CA PerBit enable=1, Macro0, CA PI delay=33
3128 12:17:54.849367
3129 12:17:54.852716 [CBTSetCACLKResult] CA Dly = 33
3130 12:17:54.852800 CS Dly: 5 (0~36)
3131 12:17:54.852866 ==
3132 12:17:54.855709 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 12:17:54.862714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 12:17:54.862798 ==
3135 12:17:54.865789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 12:17:54.872447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3137 12:17:54.881659 [CA 0] Center 38 (8~68) winsize 61
3138 12:17:54.884808 [CA 1] Center 37 (7~68) winsize 62
3139 12:17:54.888204 [CA 2] Center 35 (5~66) winsize 62
3140 12:17:54.891375 [CA 3] Center 34 (4~65) winsize 62
3141 12:17:54.894568 [CA 4] Center 34 (4~64) winsize 61
3142 12:17:54.898016 [CA 5] Center 33 (3~63) winsize 61
3143 12:17:54.898153
3144 12:17:54.901728 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3145 12:17:54.901813
3146 12:17:54.904479 [CATrainingPosCal] consider 2 rank data
3147 12:17:54.908150 u2DelayCellTimex100 = 270/100 ps
3148 12:17:54.911064 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3149 12:17:54.914667 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3150 12:17:54.921162 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3151 12:17:54.924632 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 12:17:54.927893 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 12:17:54.931113 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3154 12:17:54.931202
3155 12:17:54.934925 CA PerBit enable=1, Macro0, CA PI delay=33
3156 12:17:54.935034
3157 12:17:54.938102 [CBTSetCACLKResult] CA Dly = 33
3158 12:17:54.938187 CS Dly: 6 (0~38)
3159 12:17:54.938261
3160 12:17:54.941210 ----->DramcWriteLeveling(PI) begin...
3161 12:17:54.945031 ==
3162 12:17:54.945119 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 12:17:54.951380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 12:17:54.951492 ==
3165 12:17:54.954824 Write leveling (Byte 0): 25 => 25
3166 12:17:54.957996 Write leveling (Byte 1): 28 => 28
3167 12:17:54.958082 DramcWriteLeveling(PI) end<-----
3168 12:17:54.961472
3169 12:17:54.961555 ==
3170 12:17:54.964659 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 12:17:54.968018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 12:17:54.968102 ==
3173 12:17:54.971705 [Gating] SW mode calibration
3174 12:17:54.978084 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 12:17:54.981388 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 12:17:54.988785 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 12:17:54.991370 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 12:17:54.994681 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 12:17:55.001919 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 12:17:55.004859 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 12:17:55.008294 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3182 12:17:55.015040 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (1 0)
3183 12:17:55.018214 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3184 12:17:55.021588 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 12:17:55.028075 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 12:17:55.031406 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 12:17:55.034902 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 12:17:55.038255 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 12:17:55.044881 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3190 12:17:55.048410 1 0 24 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)
3191 12:17:55.051619 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 12:17:55.058193 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 12:17:55.061920 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 12:17:55.065164 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 12:17:55.071675 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 12:17:55.075102 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 12:17:55.078731 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3198 12:17:55.085070 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3199 12:17:55.088411 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3200 12:17:55.091838 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 12:17:55.098616 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 12:17:55.101746 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 12:17:55.104909 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 12:17:55.111855 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 12:17:55.115225 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 12:17:55.118216 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 12:17:55.125273 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 12:17:55.128242 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 12:17:55.131666 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 12:17:55.135263 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:17:55.141740 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:17:55.145063 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:17:55.148364 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3214 12:17:55.155354 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 12:17:55.158725 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 12:17:55.162126 Total UI for P1: 0, mck2ui 16
3217 12:17:55.165466 best dqsien dly found for B0: ( 1, 3, 22)
3218 12:17:55.168835 Total UI for P1: 0, mck2ui 16
3219 12:17:55.171878 best dqsien dly found for B1: ( 1, 3, 24)
3220 12:17:55.175297 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3221 12:17:55.179333 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3222 12:17:55.179798
3223 12:17:55.182519 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3224 12:17:55.185749 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3225 12:17:55.189349 [Gating] SW calibration Done
3226 12:17:55.189707 ==
3227 12:17:55.192387 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 12:17:55.195739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 12:17:55.196097 ==
3230 12:17:55.198997 RX Vref Scan: 0
3231 12:17:55.199521
3232 12:17:55.202815 RX Vref 0 -> 0, step: 1
3233 12:17:55.203329
3234 12:17:55.203659 RX Delay -40 -> 252, step: 8
3235 12:17:55.209515 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3236 12:17:55.212312 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3237 12:17:55.216001 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3238 12:17:55.219344 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3239 12:17:55.222746 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3240 12:17:55.229253 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3241 12:17:55.232896 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3242 12:17:55.235812 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3243 12:17:55.239125 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3244 12:17:55.242484 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3245 12:17:55.245613 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3246 12:17:55.252458 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3247 12:17:55.255780 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3248 12:17:55.259634 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3249 12:17:55.262917 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3250 12:17:55.269311 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3251 12:17:55.269822 ==
3252 12:17:55.272643 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 12:17:55.276192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 12:17:55.276627 ==
3255 12:17:55.276864 DQS Delay:
3256 12:17:55.279241 DQS0 = 0, DQS1 = 0
3257 12:17:55.279527 DQM Delay:
3258 12:17:55.282377 DQM0 = 120, DQM1 = 112
3259 12:17:55.282598 DQ Delay:
3260 12:17:55.285826 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3261 12:17:55.289121 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3262 12:17:55.292597 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3263 12:17:55.295877 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3264 12:17:55.296034
3265 12:17:55.296157
3266 12:17:55.296270 ==
3267 12:17:55.299162 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 12:17:55.305590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 12:17:55.305754 ==
3270 12:17:55.305851
3271 12:17:55.305936
3272 12:17:55.306018 TX Vref Scan disable
3273 12:17:55.308951 == TX Byte 0 ==
3274 12:17:55.312331 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3275 12:17:55.319058 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3276 12:17:55.319210 == TX Byte 1 ==
3277 12:17:55.322345 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3278 12:17:55.325981 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3279 12:17:55.329327 ==
3280 12:17:55.332698 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 12:17:55.335654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 12:17:55.335739 ==
3283 12:17:55.347129 TX Vref=22, minBit 3, minWin=24, winSum=395
3284 12:17:55.350283 TX Vref=24, minBit 11, minWin=23, winSum=403
3285 12:17:55.353882 TX Vref=26, minBit 11, minWin=24, winSum=407
3286 12:17:55.357350 TX Vref=28, minBit 8, minWin=25, winSum=412
3287 12:17:55.360871 TX Vref=30, minBit 8, minWin=25, winSum=417
3288 12:17:55.367470 TX Vref=32, minBit 10, minWin=24, winSum=417
3289 12:17:55.370789 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 30
3290 12:17:55.371237
3291 12:17:55.373940 Final TX Range 1 Vref 30
3292 12:17:55.374312
3293 12:17:55.374584 ==
3294 12:17:55.377261 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 12:17:55.380879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 12:17:55.384260 ==
3297 12:17:55.384771
3298 12:17:55.385197
3299 12:17:55.385506 TX Vref Scan disable
3300 12:17:55.387360 == TX Byte 0 ==
3301 12:17:55.390266 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3302 12:17:55.397347 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3303 12:17:55.397890 == TX Byte 1 ==
3304 12:17:55.400604 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3305 12:17:55.406861 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3306 12:17:55.407304
3307 12:17:55.407743 [DATLAT]
3308 12:17:55.408158 Freq=1200, CH1 RK0
3309 12:17:55.408586
3310 12:17:55.410408 DATLAT Default: 0xd
3311 12:17:55.410817 0, 0xFFFF, sum = 0
3312 12:17:55.413614 1, 0xFFFF, sum = 0
3313 12:17:55.416850 2, 0xFFFF, sum = 0
3314 12:17:55.417368 3, 0xFFFF, sum = 0
3315 12:17:55.420293 4, 0xFFFF, sum = 0
3316 12:17:55.420820 5, 0xFFFF, sum = 0
3317 12:17:55.423551 6, 0xFFFF, sum = 0
3318 12:17:55.423980 7, 0xFFFF, sum = 0
3319 12:17:55.427076 8, 0xFFFF, sum = 0
3320 12:17:55.427476 9, 0xFFFF, sum = 0
3321 12:17:55.430142 10, 0xFFFF, sum = 0
3322 12:17:55.430540 11, 0xFFFF, sum = 0
3323 12:17:55.433436 12, 0x0, sum = 1
3324 12:17:55.433832 13, 0x0, sum = 2
3325 12:17:55.437090 14, 0x0, sum = 3
3326 12:17:55.437488 15, 0x0, sum = 4
3327 12:17:55.437806 best_step = 13
3328 12:17:55.440244
3329 12:17:55.440633 ==
3330 12:17:55.443461 Dram Type= 6, Freq= 0, CH_1, rank 0
3331 12:17:55.447377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3332 12:17:55.447770 ==
3333 12:17:55.448097 RX Vref Scan: 1
3334 12:17:55.448390
3335 12:17:55.450470 Set Vref Range= 32 -> 127
3336 12:17:55.450861
3337 12:17:55.453650 RX Vref 32 -> 127, step: 1
3338 12:17:55.453932
3339 12:17:55.456751 RX Delay -13 -> 252, step: 4
3340 12:17:55.456987
3341 12:17:55.460108 Set Vref, RX VrefLevel [Byte0]: 32
3342 12:17:55.463655 [Byte1]: 32
3343 12:17:55.463831
3344 12:17:55.466789 Set Vref, RX VrefLevel [Byte0]: 33
3345 12:17:55.469993 [Byte1]: 33
3346 12:17:55.470139
3347 12:17:55.473435 Set Vref, RX VrefLevel [Byte0]: 34
3348 12:17:55.476857 [Byte1]: 34
3349 12:17:55.481295
3350 12:17:55.481404 Set Vref, RX VrefLevel [Byte0]: 35
3351 12:17:55.484552 [Byte1]: 35
3352 12:17:55.489134
3353 12:17:55.489224 Set Vref, RX VrefLevel [Byte0]: 36
3354 12:17:55.492339 [Byte1]: 36
3355 12:17:55.496899
3356 12:17:55.497035 Set Vref, RX VrefLevel [Byte0]: 37
3357 12:17:55.499996 [Byte1]: 37
3358 12:17:55.504725
3359 12:17:55.504808 Set Vref, RX VrefLevel [Byte0]: 38
3360 12:17:55.508012 [Byte1]: 38
3361 12:17:55.512354
3362 12:17:55.512469 Set Vref, RX VrefLevel [Byte0]: 39
3363 12:17:55.515763 [Byte1]: 39
3364 12:17:55.520520
3365 12:17:55.520602 Set Vref, RX VrefLevel [Byte0]: 40
3366 12:17:55.524198 [Byte1]: 40
3367 12:17:55.528342
3368 12:17:55.528424 Set Vref, RX VrefLevel [Byte0]: 41
3369 12:17:55.531650 [Byte1]: 41
3370 12:17:55.536171
3371 12:17:55.536253 Set Vref, RX VrefLevel [Byte0]: 42
3372 12:17:55.539670 [Byte1]: 42
3373 12:17:55.544113
3374 12:17:55.544195 Set Vref, RX VrefLevel [Byte0]: 43
3375 12:17:55.547546 [Byte1]: 43
3376 12:17:55.552252
3377 12:17:55.552337 Set Vref, RX VrefLevel [Byte0]: 44
3378 12:17:55.555283 [Byte1]: 44
3379 12:17:55.560020
3380 12:17:55.560102 Set Vref, RX VrefLevel [Byte0]: 45
3381 12:17:55.563268 [Byte1]: 45
3382 12:17:55.567656
3383 12:17:55.567738 Set Vref, RX VrefLevel [Byte0]: 46
3384 12:17:55.571459 [Byte1]: 46
3385 12:17:55.575555
3386 12:17:55.575637 Set Vref, RX VrefLevel [Byte0]: 47
3387 12:17:55.579104 [Byte1]: 47
3388 12:17:55.583592
3389 12:17:55.583673 Set Vref, RX VrefLevel [Byte0]: 48
3390 12:17:55.587097 [Byte1]: 48
3391 12:17:55.591723
3392 12:17:55.591804 Set Vref, RX VrefLevel [Byte0]: 49
3393 12:17:55.594989 [Byte1]: 49
3394 12:17:55.599568
3395 12:17:55.599650 Set Vref, RX VrefLevel [Byte0]: 50
3396 12:17:55.602672 [Byte1]: 50
3397 12:17:55.607080
3398 12:17:55.607162 Set Vref, RX VrefLevel [Byte0]: 51
3399 12:17:55.610754 [Byte1]: 51
3400 12:17:55.615055
3401 12:17:55.615137 Set Vref, RX VrefLevel [Byte0]: 52
3402 12:17:55.618527 [Byte1]: 52
3403 12:17:55.623264
3404 12:17:55.623345 Set Vref, RX VrefLevel [Byte0]: 53
3405 12:17:55.626475 [Byte1]: 53
3406 12:17:55.631017
3407 12:17:55.631099 Set Vref, RX VrefLevel [Byte0]: 54
3408 12:17:55.634260 [Byte1]: 54
3409 12:17:55.638947
3410 12:17:55.639029 Set Vref, RX VrefLevel [Byte0]: 55
3411 12:17:55.642495 [Byte1]: 55
3412 12:17:55.646978
3413 12:17:55.647061 Set Vref, RX VrefLevel [Byte0]: 56
3414 12:17:55.649877 [Byte1]: 56
3415 12:17:55.654500
3416 12:17:55.654581 Set Vref, RX VrefLevel [Byte0]: 57
3417 12:17:55.657742 [Byte1]: 57
3418 12:17:55.662644
3419 12:17:55.662728 Set Vref, RX VrefLevel [Byte0]: 58
3420 12:17:55.665851 [Byte1]: 58
3421 12:17:55.670197
3422 12:17:55.670281 Set Vref, RX VrefLevel [Byte0]: 59
3423 12:17:55.673672 [Byte1]: 59
3424 12:17:55.678365
3425 12:17:55.678449 Set Vref, RX VrefLevel [Byte0]: 60
3426 12:17:55.681540 [Byte1]: 60
3427 12:17:55.686161
3428 12:17:55.686245 Set Vref, RX VrefLevel [Byte0]: 61
3429 12:17:55.689721 [Byte1]: 61
3430 12:17:55.694175
3431 12:17:55.694272 Set Vref, RX VrefLevel [Byte0]: 62
3432 12:17:55.700519 [Byte1]: 62
3433 12:17:55.700604
3434 12:17:55.703928 Set Vref, RX VrefLevel [Byte0]: 63
3435 12:17:55.706916 [Byte1]: 63
3436 12:17:55.707001
3437 12:17:55.710512 Set Vref, RX VrefLevel [Byte0]: 64
3438 12:17:55.713733 [Byte1]: 64
3439 12:17:55.717506
3440 12:17:55.717589 Set Vref, RX VrefLevel [Byte0]: 65
3441 12:17:55.720854 [Byte1]: 65
3442 12:17:55.725472
3443 12:17:55.725565 Set Vref, RX VrefLevel [Byte0]: 66
3444 12:17:55.729144 [Byte1]: 66
3445 12:17:55.733370
3446 12:17:55.733480 Set Vref, RX VrefLevel [Byte0]: 67
3447 12:17:55.737095 [Byte1]: 67
3448 12:17:55.741221
3449 12:17:55.741348 Final RX Vref Byte 0 = 52 to rank0
3450 12:17:55.745080 Final RX Vref Byte 1 = 50 to rank0
3451 12:17:55.748410 Final RX Vref Byte 0 = 52 to rank1
3452 12:17:55.751627 Final RX Vref Byte 1 = 50 to rank1==
3453 12:17:55.754854 Dram Type= 6, Freq= 0, CH_1, rank 0
3454 12:17:55.758228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3455 12:17:55.761658 ==
3456 12:17:55.761747 DQS Delay:
3457 12:17:55.761818 DQS0 = 0, DQS1 = 0
3458 12:17:55.764880 DQM Delay:
3459 12:17:55.765011 DQM0 = 119, DQM1 = 111
3460 12:17:55.768292 DQ Delay:
3461 12:17:55.771921 DQ0 =122, DQ1 =112, DQ2 =112, DQ3 =118
3462 12:17:55.775139 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3463 12:17:55.778227 DQ8 =100, DQ9 =98, DQ10 =114, DQ11 =104
3464 12:17:55.781975 DQ12 =122, DQ13 =116, DQ14 =120, DQ15 =118
3465 12:17:55.782157
3466 12:17:55.782248
3467 12:17:55.788525 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3468 12:17:55.791923 CH1 RK0: MR19=404, MR18=518
3469 12:17:55.798413 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3470 12:17:55.798887
3471 12:17:55.801885 ----->DramcWriteLeveling(PI) begin...
3472 12:17:55.802314 ==
3473 12:17:55.805085 Dram Type= 6, Freq= 0, CH_1, rank 1
3474 12:17:55.808383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 12:17:55.808777 ==
3476 12:17:55.811559 Write leveling (Byte 0): 25 => 25
3477 12:17:55.814978 Write leveling (Byte 1): 29 => 29
3478 12:17:55.818771 DramcWriteLeveling(PI) end<-----
3479 12:17:55.819158
3480 12:17:55.819464 ==
3481 12:17:55.822094 Dram Type= 6, Freq= 0, CH_1, rank 1
3482 12:17:55.825356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 12:17:55.828595 ==
3484 12:17:55.829019 [Gating] SW mode calibration
3485 12:17:55.835542 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3486 12:17:55.842017 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3487 12:17:55.845287 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3488 12:17:55.852534 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 12:17:55.855420 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 12:17:55.859212 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 12:17:55.865231 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 12:17:55.868857 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 12:17:55.872196 0 15 24 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
3494 12:17:55.875482 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3495 12:17:55.882166 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 12:17:55.885274 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 12:17:55.888801 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 12:17:55.895937 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 12:17:55.899127 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 12:17:55.902418 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3501 12:17:55.908717 1 0 24 | B1->B0 | 3e3e 3030 | 0 0 | (0 0) (1 1)
3502 12:17:55.912518 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 12:17:55.915752 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 12:17:55.922998 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 12:17:55.925651 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 12:17:55.929090 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 12:17:55.935837 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 12:17:55.939140 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 12:17:55.942232 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3510 12:17:55.948897 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3511 12:17:55.952217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 12:17:55.955420 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 12:17:55.962276 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 12:17:55.965665 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 12:17:55.969024 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 12:17:55.975400 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 12:17:55.979139 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 12:17:55.982109 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 12:17:55.985370 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 12:17:55.991955 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 12:17:55.995554 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 12:17:55.998489 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 12:17:56.005354 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 12:17:56.008604 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 12:17:56.012021 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3526 12:17:56.018652 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 12:17:56.019157 Total UI for P1: 0, mck2ui 16
3528 12:17:56.025549 best dqsien dly found for B0: ( 1, 3, 24)
3529 12:17:56.026062 Total UI for P1: 0, mck2ui 16
3530 12:17:56.032546 best dqsien dly found for B1: ( 1, 3, 24)
3531 12:17:56.035603 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3532 12:17:56.038945 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3533 12:17:56.039368
3534 12:17:56.042006 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3535 12:17:56.045456 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3536 12:17:56.048485 [Gating] SW calibration Done
3537 12:17:56.049016 ==
3538 12:17:56.052428 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 12:17:56.055569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 12:17:56.056097 ==
3541 12:17:56.058640 RX Vref Scan: 0
3542 12:17:56.059156
3543 12:17:56.059568 RX Vref 0 -> 0, step: 1
3544 12:17:56.059923
3545 12:17:56.061934 RX Delay -40 -> 252, step: 8
3546 12:17:56.065209 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3547 12:17:56.071631 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3548 12:17:56.075295 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3549 12:17:56.078766 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3550 12:17:56.081628 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3551 12:17:56.085288 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3552 12:17:56.091714 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3553 12:17:56.095087 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3554 12:17:56.098421 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3555 12:17:56.101700 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3556 12:17:56.104989 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3557 12:17:56.112277 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3558 12:17:56.115326 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3559 12:17:56.118585 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3560 12:17:56.121917 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3561 12:17:56.125083 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3562 12:17:56.128604 ==
3563 12:17:56.129159 Dram Type= 6, Freq= 0, CH_1, rank 1
3564 12:17:56.135523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3565 12:17:56.136052 ==
3566 12:17:56.136396 DQS Delay:
3567 12:17:56.138944 DQS0 = 0, DQS1 = 0
3568 12:17:56.139469 DQM Delay:
3569 12:17:56.141924 DQM0 = 120, DQM1 = 112
3570 12:17:56.142346 DQ Delay:
3571 12:17:56.145029 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3572 12:17:56.148839 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3573 12:17:56.152047 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3574 12:17:56.155749 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3575 12:17:56.156326
3576 12:17:56.156660
3577 12:17:56.157009 ==
3578 12:17:56.158379 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 12:17:56.165238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 12:17:56.165750 ==
3581 12:17:56.166088
3582 12:17:56.166398
3583 12:17:56.166691 TX Vref Scan disable
3584 12:17:56.168602 == TX Byte 0 ==
3585 12:17:56.171951 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3586 12:17:56.178434 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3587 12:17:56.178992 == TX Byte 1 ==
3588 12:17:56.181413 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3589 12:17:56.188624 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3590 12:17:56.189147 ==
3591 12:17:56.191537 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 12:17:56.194836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 12:17:56.195268 ==
3594 12:17:56.206394 TX Vref=22, minBit 1, minWin=25, winSum=409
3595 12:17:56.209441 TX Vref=24, minBit 1, minWin=25, winSum=414
3596 12:17:56.212751 TX Vref=26, minBit 1, minWin=25, winSum=421
3597 12:17:56.216372 TX Vref=28, minBit 9, minWin=25, winSum=426
3598 12:17:56.219468 TX Vref=30, minBit 3, minWin=26, winSum=426
3599 12:17:56.226110 TX Vref=32, minBit 9, minWin=25, winSum=423
3600 12:17:56.229290 [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 30
3601 12:17:56.229517
3602 12:17:56.233160 Final TX Range 1 Vref 30
3603 12:17:56.233432
3604 12:17:56.233579 ==
3605 12:17:56.235950 Dram Type= 6, Freq= 0, CH_1, rank 1
3606 12:17:56.239489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3607 12:17:56.239762 ==
3608 12:17:56.239925
3609 12:17:56.242554
3610 12:17:56.242746 TX Vref Scan disable
3611 12:17:56.246303 == TX Byte 0 ==
3612 12:17:56.249389 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3613 12:17:56.253035 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3614 12:17:56.256272 == TX Byte 1 ==
3615 12:17:56.259504 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3616 12:17:56.263223 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3617 12:17:56.266120
3618 12:17:56.266551 [DATLAT]
3619 12:17:56.266895 Freq=1200, CH1 RK1
3620 12:17:56.267217
3621 12:17:56.269450 DATLAT Default: 0xd
3622 12:17:56.269882 0, 0xFFFF, sum = 0
3623 12:17:56.273264 1, 0xFFFF, sum = 0
3624 12:17:56.273809 2, 0xFFFF, sum = 0
3625 12:17:56.276281 3, 0xFFFF, sum = 0
3626 12:17:56.276715 4, 0xFFFF, sum = 0
3627 12:17:56.279368 5, 0xFFFF, sum = 0
3628 12:17:56.282689 6, 0xFFFF, sum = 0
3629 12:17:56.283135 7, 0xFFFF, sum = 0
3630 12:17:56.285957 8, 0xFFFF, sum = 0
3631 12:17:56.286395 9, 0xFFFF, sum = 0
3632 12:17:56.289430 10, 0xFFFF, sum = 0
3633 12:17:56.289867 11, 0xFFFF, sum = 0
3634 12:17:56.292445 12, 0x0, sum = 1
3635 12:17:56.292882 13, 0x0, sum = 2
3636 12:17:56.295907 14, 0x0, sum = 3
3637 12:17:56.296342 15, 0x0, sum = 4
3638 12:17:56.296691 best_step = 13
3639 12:17:56.299527
3640 12:17:56.299962 ==
3641 12:17:56.302459 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 12:17:56.305944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 12:17:56.306380 ==
3644 12:17:56.306783 RX Vref Scan: 0
3645 12:17:56.307257
3646 12:17:56.309398 RX Vref 0 -> 0, step: 1
3647 12:17:56.309848
3648 12:17:56.312338 RX Delay -13 -> 252, step: 4
3649 12:17:56.315822 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3650 12:17:56.322653 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3651 12:17:56.325461 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3652 12:17:56.328824 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3653 12:17:56.332264 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3654 12:17:56.335724 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3655 12:17:56.342422 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3656 12:17:56.345843 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3657 12:17:56.349142 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3658 12:17:56.352261 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3659 12:17:56.355527 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3660 12:17:56.362065 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3661 12:17:56.365623 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3662 12:17:56.368665 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3663 12:17:56.372190 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3664 12:17:56.375695 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3665 12:17:56.378645 ==
3666 12:17:56.381915 Dram Type= 6, Freq= 0, CH_1, rank 1
3667 12:17:56.385188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3668 12:17:56.385373 ==
3669 12:17:56.385521 DQS Delay:
3670 12:17:56.388540 DQS0 = 0, DQS1 = 0
3671 12:17:56.388695 DQM Delay:
3672 12:17:56.391858 DQM0 = 119, DQM1 = 113
3673 12:17:56.391991 DQ Delay:
3674 12:17:56.395188 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3675 12:17:56.398394 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3676 12:17:56.401929 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3677 12:17:56.404843 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3678 12:17:56.404996
3679 12:17:56.405081
3680 12:17:56.415569 [DQSOSCAuto] RK1, (LSB)MR18= 0x6eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3681 12:17:56.415690 CH1 RK1: MR19=403, MR18=6EB
3682 12:17:56.422043 CH1_RK1: MR19=0x403, MR18=0x6EB, DQSOSC=407, MR23=63, INC=39, DEC=26
3683 12:17:56.425467 [RxdqsGatingPostProcess] freq 1200
3684 12:17:56.431581 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3685 12:17:56.435104 best DQS0 dly(2T, 0.5T) = (0, 11)
3686 12:17:56.438328 best DQS1 dly(2T, 0.5T) = (0, 11)
3687 12:17:56.442194 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3688 12:17:56.445215 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3689 12:17:56.448318 best DQS0 dly(2T, 0.5T) = (0, 11)
3690 12:17:56.451639 best DQS1 dly(2T, 0.5T) = (0, 11)
3691 12:17:56.454916 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3692 12:17:56.455034 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3693 12:17:56.458683 Pre-setting of DQS Precalculation
3694 12:17:56.465314 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3695 12:17:56.471668 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3696 12:17:56.478586 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3697 12:17:56.478814
3698 12:17:56.478937
3699 12:17:56.482327 [Calibration Summary] 2400 Mbps
3700 12:17:56.484908 CH 0, Rank 0
3701 12:17:56.485152 SW Impedance : PASS
3702 12:17:56.488792 DUTY Scan : NO K
3703 12:17:56.491841 ZQ Calibration : PASS
3704 12:17:56.492175 Jitter Meter : NO K
3705 12:17:56.495279 CBT Training : PASS
3706 12:17:56.498625 Write leveling : PASS
3707 12:17:56.499059 RX DQS gating : PASS
3708 12:17:56.501845 RX DQ/DQS(RDDQC) : PASS
3709 12:17:56.502238 TX DQ/DQS : PASS
3710 12:17:56.505255 RX DATLAT : PASS
3711 12:17:56.508497 RX DQ/DQS(Engine): PASS
3712 12:17:56.508959 TX OE : NO K
3713 12:17:56.511843 All Pass.
3714 12:17:56.512275
3715 12:17:56.512705 CH 0, Rank 1
3716 12:17:56.515053 SW Impedance : PASS
3717 12:17:56.515483 DUTY Scan : NO K
3718 12:17:56.518342 ZQ Calibration : PASS
3719 12:17:56.521822 Jitter Meter : NO K
3720 12:17:56.522258 CBT Training : PASS
3721 12:17:56.525218 Write leveling : PASS
3722 12:17:56.528902 RX DQS gating : PASS
3723 12:17:56.529469 RX DQ/DQS(RDDQC) : PASS
3724 12:17:56.531869 TX DQ/DQS : PASS
3725 12:17:56.535171 RX DATLAT : PASS
3726 12:17:56.535706 RX DQ/DQS(Engine): PASS
3727 12:17:56.538608 TX OE : NO K
3728 12:17:56.539146 All Pass.
3729 12:17:56.539590
3730 12:17:56.541701 CH 1, Rank 0
3731 12:17:56.542134 SW Impedance : PASS
3732 12:17:56.545176 DUTY Scan : NO K
3733 12:17:56.545707 ZQ Calibration : PASS
3734 12:17:56.548489 Jitter Meter : NO K
3735 12:17:56.552122 CBT Training : PASS
3736 12:17:56.552658 Write leveling : PASS
3737 12:17:56.555251 RX DQS gating : PASS
3738 12:17:56.558519 RX DQ/DQS(RDDQC) : PASS
3739 12:17:56.559051 TX DQ/DQS : PASS
3740 12:17:56.562105 RX DATLAT : PASS
3741 12:17:56.565171 RX DQ/DQS(Engine): PASS
3742 12:17:56.565606 TX OE : NO K
3743 12:17:56.568548 All Pass.
3744 12:17:56.569011
3745 12:17:56.569371 CH 1, Rank 1
3746 12:17:56.571787 SW Impedance : PASS
3747 12:17:56.572219 DUTY Scan : NO K
3748 12:17:56.575216 ZQ Calibration : PASS
3749 12:17:56.578952 Jitter Meter : NO K
3750 12:17:56.579505 CBT Training : PASS
3751 12:17:56.581866 Write leveling : PASS
3752 12:17:56.585107 RX DQS gating : PASS
3753 12:17:56.585543 RX DQ/DQS(RDDQC) : PASS
3754 12:17:56.588517 TX DQ/DQS : PASS
3755 12:17:56.588988 RX DATLAT : PASS
3756 12:17:56.591942 RX DQ/DQS(Engine): PASS
3757 12:17:56.595325 TX OE : NO K
3758 12:17:56.595928 All Pass.
3759 12:17:56.596286
3760 12:17:56.598811 DramC Write-DBI off
3761 12:17:56.599352 PER_BANK_REFRESH: Hybrid Mode
3762 12:17:56.602276 TX_TRACKING: ON
3763 12:17:56.611669 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3764 12:17:56.614922 [FAST_K] Save calibration result to emmc
3765 12:17:56.618004 dramc_set_vcore_voltage set vcore to 650000
3766 12:17:56.618440 Read voltage for 600, 5
3767 12:17:56.621335 Vio18 = 0
3768 12:17:56.621763 Vcore = 650000
3769 12:17:56.622100 Vdram = 0
3770 12:17:56.624815 Vddq = 0
3771 12:17:56.625401 Vmddr = 0
3772 12:17:56.631910 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3773 12:17:56.634700 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3774 12:17:56.638135 MEM_TYPE=3, freq_sel=19
3775 12:17:56.641415 sv_algorithm_assistance_LP4_1600
3776 12:17:56.644705 ============ PULL DRAM RESETB DOWN ============
3777 12:17:56.648206 ========== PULL DRAM RESETB DOWN end =========
3778 12:17:56.655423 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3779 12:17:56.658479 ===================================
3780 12:17:56.659004 LPDDR4 DRAM CONFIGURATION
3781 12:17:56.661227 ===================================
3782 12:17:56.664626 EX_ROW_EN[0] = 0x0
3783 12:17:56.665071 EX_ROW_EN[1] = 0x0
3784 12:17:56.668048 LP4Y_EN = 0x0
3785 12:17:56.671912 WORK_FSP = 0x0
3786 12:17:56.672432 WL = 0x2
3787 12:17:56.674975 RL = 0x2
3788 12:17:56.675401 BL = 0x2
3789 12:17:56.677969 RPST = 0x0
3790 12:17:56.678395 RD_PRE = 0x0
3791 12:17:56.681155 WR_PRE = 0x1
3792 12:17:56.681583 WR_PST = 0x0
3793 12:17:56.684635 DBI_WR = 0x0
3794 12:17:56.685197 DBI_RD = 0x0
3795 12:17:56.687962 OTF = 0x1
3796 12:17:56.691828 ===================================
3797 12:17:56.694697 ===================================
3798 12:17:56.695125 ANA top config
3799 12:17:56.698538 ===================================
3800 12:17:56.701684 DLL_ASYNC_EN = 0
3801 12:17:56.704753 ALL_SLAVE_EN = 1
3802 12:17:56.705381 NEW_RANK_MODE = 1
3803 12:17:56.708130 DLL_IDLE_MODE = 1
3804 12:17:56.711510 LP45_APHY_COMB_EN = 1
3805 12:17:56.714249 TX_ODT_DIS = 1
3806 12:17:56.718039 NEW_8X_MODE = 1
3807 12:17:56.721770 ===================================
3808 12:17:56.722214 ===================================
3809 12:17:56.724418 data_rate = 1200
3810 12:17:56.728030 CKR = 1
3811 12:17:56.731407 DQ_P2S_RATIO = 8
3812 12:17:56.734506 ===================================
3813 12:17:56.737999 CA_P2S_RATIO = 8
3814 12:17:56.741569 DQ_CA_OPEN = 0
3815 12:17:56.741999 DQ_SEMI_OPEN = 0
3816 12:17:56.744988 CA_SEMI_OPEN = 0
3817 12:17:56.748006 CA_FULL_RATE = 0
3818 12:17:56.751455 DQ_CKDIV4_EN = 1
3819 12:17:56.755134 CA_CKDIV4_EN = 1
3820 12:17:56.758423 CA_PREDIV_EN = 0
3821 12:17:56.758949 PH8_DLY = 0
3822 12:17:56.761053 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3823 12:17:56.764898 DQ_AAMCK_DIV = 4
3824 12:17:56.767757 CA_AAMCK_DIV = 4
3825 12:17:56.771159 CA_ADMCK_DIV = 4
3826 12:17:56.774807 DQ_TRACK_CA_EN = 0
3827 12:17:56.775338 CA_PICK = 600
3828 12:17:56.778388 CA_MCKIO = 600
3829 12:17:56.781324 MCKIO_SEMI = 0
3830 12:17:56.784991 PLL_FREQ = 2288
3831 12:17:56.787592 DQ_UI_PI_RATIO = 32
3832 12:17:56.791418 CA_UI_PI_RATIO = 0
3833 12:17:56.794632 ===================================
3834 12:17:56.797830 ===================================
3835 12:17:56.800900 memory_type:LPDDR4
3836 12:17:56.801344 GP_NUM : 10
3837 12:17:56.804603 SRAM_EN : 1
3838 12:17:56.805057 MD32_EN : 0
3839 12:17:56.807787 ===================================
3840 12:17:56.811337 [ANA_INIT] >>>>>>>>>>>>>>
3841 12:17:56.814246 <<<<<< [CONFIGURE PHASE]: ANA_TX
3842 12:17:56.817355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3843 12:17:56.821205 ===================================
3844 12:17:56.824300 data_rate = 1200,PCW = 0X5800
3845 12:17:56.827700 ===================================
3846 12:17:56.830954 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3847 12:17:56.834166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3848 12:17:56.840868 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3849 12:17:56.844231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3850 12:17:56.851088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3851 12:17:56.854245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3852 12:17:56.854683 [ANA_INIT] flow start
3853 12:17:56.858034 [ANA_INIT] PLL >>>>>>>>
3854 12:17:56.858565 [ANA_INIT] PLL <<<<<<<<
3855 12:17:56.861286 [ANA_INIT] MIDPI >>>>>>>>
3856 12:17:56.864553 [ANA_INIT] MIDPI <<<<<<<<
3857 12:17:56.867652 [ANA_INIT] DLL >>>>>>>>
3858 12:17:56.868087 [ANA_INIT] flow end
3859 12:17:56.871059 ============ LP4 DIFF to SE enter ============
3860 12:17:56.877733 ============ LP4 DIFF to SE exit ============
3861 12:17:56.878465 [ANA_INIT] <<<<<<<<<<<<<
3862 12:17:56.881280 [Flow] Enable top DCM control >>>>>
3863 12:17:56.884507 [Flow] Enable top DCM control <<<<<
3864 12:17:56.887666 Enable DLL master slave shuffle
3865 12:17:56.894690 ==============================================================
3866 12:17:56.895224 Gating Mode config
3867 12:17:56.901191 ==============================================================
3868 12:17:56.904737 Config description:
3869 12:17:56.937000 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3870 12:17:56.937535 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3871 12:17:56.937893 SELPH_MODE 0: By rank 1: By Phase
3872 12:17:56.938239 ==============================================================
3873 12:17:56.938559 GAT_TRACK_EN = 1
3874 12:17:56.938866 RX_GATING_MODE = 2
3875 12:17:56.939493 RX_GATING_TRACK_MODE = 2
3876 12:17:56.940663 SELPH_MODE = 1
3877 12:17:56.944266 PICG_EARLY_EN = 1
3878 12:17:56.947316 VALID_LAT_VALUE = 1
3879 12:17:56.954364 ==============================================================
3880 12:17:56.957394 Enter into Gating configuration >>>>
3881 12:17:56.960472 Exit from Gating configuration <<<<
3882 12:17:56.964034 Enter into DVFS_PRE_config >>>>>
3883 12:17:56.974316 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3884 12:17:56.977404 Exit from DVFS_PRE_config <<<<<
3885 12:17:56.980330 Enter into PICG configuration >>>>
3886 12:17:56.984186 Exit from PICG configuration <<<<
3887 12:17:56.987398 [RX_INPUT] configuration >>>>>
3888 12:17:56.990922 [RX_INPUT] configuration <<<<<
3889 12:17:56.994137 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3890 12:17:57.000486 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3891 12:17:57.007457 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 12:17:57.010896 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 12:17:57.017285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3894 12:17:57.023684 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3895 12:17:57.027102 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3896 12:17:57.030876 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3897 12:17:57.037467 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3898 12:17:57.040634 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3899 12:17:57.044000 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3900 12:17:57.050795 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 12:17:57.053781 ===================================
3902 12:17:57.054221 LPDDR4 DRAM CONFIGURATION
3903 12:17:57.057151 ===================================
3904 12:17:57.060660 EX_ROW_EN[0] = 0x0
3905 12:17:57.063793 EX_ROW_EN[1] = 0x0
3906 12:17:57.064214 LP4Y_EN = 0x0
3907 12:17:57.067425 WORK_FSP = 0x0
3908 12:17:57.068124 WL = 0x2
3909 12:17:57.070476 RL = 0x2
3910 12:17:57.070909 BL = 0x2
3911 12:17:57.073959 RPST = 0x0
3912 12:17:57.074536 RD_PRE = 0x0
3913 12:17:57.077265 WR_PRE = 0x1
3914 12:17:57.077770 WR_PST = 0x0
3915 12:17:57.080599 DBI_WR = 0x0
3916 12:17:57.081059 DBI_RD = 0x0
3917 12:17:57.083939 OTF = 0x1
3918 12:17:57.087449 ===================================
3919 12:17:57.091015 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3920 12:17:57.093997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3921 12:17:57.097392 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 12:17:57.100662 ===================================
3923 12:17:57.103850 LPDDR4 DRAM CONFIGURATION
3924 12:17:57.107272 ===================================
3925 12:17:57.110623 EX_ROW_EN[0] = 0x10
3926 12:17:57.111089 EX_ROW_EN[1] = 0x0
3927 12:17:57.113762 LP4Y_EN = 0x0
3928 12:17:57.114297 WORK_FSP = 0x0
3929 12:17:57.117076 WL = 0x2
3930 12:17:57.117511 RL = 0x2
3931 12:17:57.120814 BL = 0x2
3932 12:17:57.121304 RPST = 0x0
3933 12:17:57.123913 RD_PRE = 0x0
3934 12:17:57.127576 WR_PRE = 0x1
3935 12:17:57.128105 WR_PST = 0x0
3936 12:17:57.130689 DBI_WR = 0x0
3937 12:17:57.131135 DBI_RD = 0x0
3938 12:17:57.133730 OTF = 0x1
3939 12:17:57.137217 ===================================
3940 12:17:57.140503 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3941 12:17:57.145491 nWR fixed to 30
3942 12:17:57.149346 [ModeRegInit_LP4] CH0 RK0
3943 12:17:57.149774 [ModeRegInit_LP4] CH0 RK1
3944 12:17:57.152289 [ModeRegInit_LP4] CH1 RK0
3945 12:17:57.155653 [ModeRegInit_LP4] CH1 RK1
3946 12:17:57.155991 match AC timing 17
3947 12:17:57.162253 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3948 12:17:57.165831 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3949 12:17:57.168782 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3950 12:17:57.175489 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3951 12:17:57.179055 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3952 12:17:57.179192 ==
3953 12:17:57.182375 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 12:17:57.185801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3955 12:17:57.185993 ==
3956 12:17:57.192046 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3957 12:17:57.199288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3958 12:17:57.202278 [CA 0] Center 36 (6~67) winsize 62
3959 12:17:57.205647 [CA 1] Center 36 (6~67) winsize 62
3960 12:17:57.208700 [CA 2] Center 34 (4~65) winsize 62
3961 12:17:57.212333 [CA 3] Center 34 (4~65) winsize 62
3962 12:17:57.215974 [CA 4] Center 34 (3~65) winsize 63
3963 12:17:57.219560 [CA 5] Center 33 (3~64) winsize 62
3964 12:17:57.219985
3965 12:17:57.222590 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3966 12:17:57.223065
3967 12:17:57.225875 [CATrainingPosCal] consider 1 rank data
3968 12:17:57.229294 u2DelayCellTimex100 = 270/100 ps
3969 12:17:57.232596 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3970 12:17:57.235801 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3971 12:17:57.239197 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3972 12:17:57.242175 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3973 12:17:57.245844 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3974 12:17:57.248772 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3975 12:17:57.249036
3976 12:17:57.255656 CA PerBit enable=1, Macro0, CA PI delay=33
3977 12:17:57.255810
3978 12:17:57.255918 [CBTSetCACLKResult] CA Dly = 33
3979 12:17:57.258657 CS Dly: 4 (0~35)
3980 12:17:57.258790 ==
3981 12:17:57.262018 Dram Type= 6, Freq= 0, CH_0, rank 1
3982 12:17:57.265207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 12:17:57.265342 ==
3984 12:17:57.272112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3985 12:17:57.279076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3986 12:17:57.281849 [CA 0] Center 36 (6~67) winsize 62
3987 12:17:57.285052 [CA 1] Center 37 (7~67) winsize 61
3988 12:17:57.288385 [CA 2] Center 35 (5~66) winsize 62
3989 12:17:57.292108 [CA 3] Center 35 (4~66) winsize 63
3990 12:17:57.295254 [CA 4] Center 34 (3~65) winsize 63
3991 12:17:57.298450 [CA 5] Center 34 (3~65) winsize 63
3992 12:17:57.298534
3993 12:17:57.302015 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3994 12:17:57.302448
3995 12:17:57.305372 [CATrainingPosCal] consider 2 rank data
3996 12:17:57.308759 u2DelayCellTimex100 = 270/100 ps
3997 12:17:57.312418 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3998 12:17:57.315502 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3999 12:17:57.318666 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4000 12:17:57.324049 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4001 12:17:57.325722 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4002 12:17:57.328994 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4003 12:17:57.332532
4004 12:17:57.335713 CA PerBit enable=1, Macro0, CA PI delay=33
4005 12:17:57.336174
4006 12:17:57.339028 [CBTSetCACLKResult] CA Dly = 33
4007 12:17:57.339563 CS Dly: 5 (0~37)
4008 12:17:57.339907
4009 12:17:57.342399 ----->DramcWriteLeveling(PI) begin...
4010 12:17:57.342832 ==
4011 12:17:57.345555 Dram Type= 6, Freq= 0, CH_0, rank 0
4012 12:17:57.348766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 12:17:57.351981 ==
4014 12:17:57.352403 Write leveling (Byte 0): 33 => 33
4015 12:17:57.355205 Write leveling (Byte 1): 31 => 31
4016 12:17:57.358641 DramcWriteLeveling(PI) end<-----
4017 12:17:57.359069
4018 12:17:57.359408 ==
4019 12:17:57.361970 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 12:17:57.368629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 12:17:57.369099 ==
4022 12:17:57.371833 [Gating] SW mode calibration
4023 12:17:57.378778 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4024 12:17:57.381516 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4025 12:17:57.388252 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 12:17:57.391654 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4027 12:17:57.395161 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4028 12:17:57.401472 0 9 12 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
4029 12:17:57.404572 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4030 12:17:57.407771 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 12:17:57.411511 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 12:17:57.417708 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 12:17:57.420938 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 12:17:57.427599 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 12:17:57.431064 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4036 12:17:57.434308 0 10 12 | B1->B0 | 2d2d 3838 | 0 0 | (0 0) (0 0)
4037 12:17:57.437732 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4038 12:17:57.444480 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 12:17:57.447525 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 12:17:57.450790 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 12:17:57.457644 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 12:17:57.461096 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 12:17:57.464072 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 12:17:57.471037 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 12:17:57.474296 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4046 12:17:57.477328 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:17:57.484105 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 12:17:57.487382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 12:17:57.491224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 12:17:57.497488 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 12:17:57.501144 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 12:17:57.504176 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 12:17:57.510875 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 12:17:57.514187 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 12:17:57.517364 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 12:17:57.523952 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 12:17:57.527575 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:17:57.530947 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:17:57.537299 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:17:57.540678 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4061 12:17:57.543945 Total UI for P1: 0, mck2ui 16
4062 12:17:57.547447 best dqsien dly found for B0: ( 0, 13, 10)
4063 12:17:57.550902 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4064 12:17:57.554517 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 12:17:57.557543 Total UI for P1: 0, mck2ui 16
4066 12:17:57.560783 best dqsien dly found for B1: ( 0, 13, 16)
4067 12:17:57.567366 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4068 12:17:57.570613 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4069 12:17:57.570712
4070 12:17:57.574373 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4071 12:17:57.577381 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4072 12:17:57.580681 [Gating] SW calibration Done
4073 12:17:57.580784 ==
4074 12:17:57.584071 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 12:17:57.587234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 12:17:57.587383 ==
4077 12:17:57.591092 RX Vref Scan: 0
4078 12:17:57.591683
4079 12:17:57.592210 RX Vref 0 -> 0, step: 1
4080 12:17:57.592711
4081 12:17:57.594000 RX Delay -230 -> 252, step: 16
4082 12:17:57.597337 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4083 12:17:57.604322 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4084 12:17:57.607579 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4085 12:17:57.610914 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4086 12:17:57.614024 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4087 12:17:57.620545 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4088 12:17:57.624046 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4089 12:17:57.627354 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4090 12:17:57.630572 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4091 12:17:57.634088 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4092 12:17:57.640403 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4093 12:17:57.643726 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4094 12:17:57.647202 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4095 12:17:57.650355 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4096 12:17:57.657156 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4097 12:17:57.660315 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4098 12:17:57.660707 ==
4099 12:17:57.663606 Dram Type= 6, Freq= 0, CH_0, rank 0
4100 12:17:57.667243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4101 12:17:57.667661 ==
4102 12:17:57.670404 DQS Delay:
4103 12:17:57.670818 DQS0 = 0, DQS1 = 0
4104 12:17:57.671198 DQM Delay:
4105 12:17:57.673751 DQM0 = 50, DQM1 = 40
4106 12:17:57.674150 DQ Delay:
4107 12:17:57.677046 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4108 12:17:57.680558 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4109 12:17:57.683986 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4110 12:17:57.687365 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4111 12:17:57.687832
4112 12:17:57.688142
4113 12:17:57.688526 ==
4114 12:17:57.690782 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 12:17:57.697057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 12:17:57.697395 ==
4117 12:17:57.697779
4118 12:17:57.698045
4119 12:17:57.698358 TX Vref Scan disable
4120 12:17:57.700511 == TX Byte 0 ==
4121 12:17:57.703839 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4122 12:17:57.707684 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4123 12:17:57.710673 == TX Byte 1 ==
4124 12:17:57.713818 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4125 12:17:57.717264 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4126 12:17:57.720831 ==
4127 12:17:57.723940 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 12:17:57.727455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 12:17:57.727708 ==
4130 12:17:57.727936
4131 12:17:57.728142
4132 12:17:57.730444 TX Vref Scan disable
4133 12:17:57.730690 == TX Byte 0 ==
4134 12:17:57.738610 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4135 12:17:57.740366 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4136 12:17:57.740540 == TX Byte 1 ==
4137 12:17:57.747174 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4138 12:17:57.750451 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4139 12:17:57.750621
4140 12:17:57.750779 [DATLAT]
4141 12:17:57.753560 Freq=600, CH0 RK0
4142 12:17:57.753728
4143 12:17:57.753882 DATLAT Default: 0x9
4144 12:17:57.757109 0, 0xFFFF, sum = 0
4145 12:17:57.757274 1, 0xFFFF, sum = 0
4146 12:17:57.760498 2, 0xFFFF, sum = 0
4147 12:17:57.763937 3, 0xFFFF, sum = 0
4148 12:17:57.764074 4, 0xFFFF, sum = 0
4149 12:17:57.767202 5, 0xFFFF, sum = 0
4150 12:17:57.767391 6, 0xFFFF, sum = 0
4151 12:17:57.770430 7, 0xFFFF, sum = 0
4152 12:17:57.770641 8, 0x0, sum = 1
4153 12:17:57.770840 9, 0x0, sum = 2
4154 12:17:57.773799 10, 0x0, sum = 3
4155 12:17:57.774011 11, 0x0, sum = 4
4156 12:17:57.777173 best_step = 9
4157 12:17:57.777388
4158 12:17:57.777584 ==
4159 12:17:57.780186 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 12:17:57.783758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 12:17:57.784032 ==
4162 12:17:57.787070 RX Vref Scan: 1
4163 12:17:57.787272
4164 12:17:57.787455 RX Vref 0 -> 0, step: 1
4165 12:17:57.787632
4166 12:17:57.790652 RX Delay -179 -> 252, step: 8
4167 12:17:57.790793
4168 12:17:57.793729 Set Vref, RX VrefLevel [Byte0]: 57
4169 12:17:57.796908 [Byte1]: 48
4170 12:17:57.801601
4171 12:17:57.801741 Final RX Vref Byte 0 = 57 to rank0
4172 12:17:57.804222 Final RX Vref Byte 1 = 48 to rank0
4173 12:17:57.807656 Final RX Vref Byte 0 = 57 to rank1
4174 12:17:57.811281 Final RX Vref Byte 1 = 48 to rank1==
4175 12:17:57.814492 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 12:17:57.817858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 12:17:57.821133 ==
4178 12:17:57.821410 DQS Delay:
4179 12:17:57.821609 DQS0 = 0, DQS1 = 0
4180 12:17:57.824466 DQM Delay:
4181 12:17:57.824795 DQM0 = 50, DQM1 = 39
4182 12:17:57.828036 DQ Delay:
4183 12:17:57.831179 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =48
4184 12:17:57.831389 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4185 12:17:57.834365 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4186 12:17:57.838032 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4187 12:17:57.841383
4188 12:17:57.841739
4189 12:17:57.848000 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4190 12:17:57.851483 CH0 RK0: MR19=808, MR18=5D57
4191 12:17:57.857835 CH0_RK0: MR19=0x808, MR18=0x5D57, DQSOSC=392, MR23=63, INC=170, DEC=113
4192 12:17:57.858312
4193 12:17:57.861198 ----->DramcWriteLeveling(PI) begin...
4194 12:17:57.861685 ==
4195 12:17:57.864422 Dram Type= 6, Freq= 0, CH_0, rank 1
4196 12:17:57.867892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 12:17:57.868389 ==
4198 12:17:57.871223 Write leveling (Byte 0): 33 => 33
4199 12:17:57.874745 Write leveling (Byte 1): 31 => 31
4200 12:17:57.877566 DramcWriteLeveling(PI) end<-----
4201 12:17:57.877989
4202 12:17:57.878388 ==
4203 12:17:57.881147 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 12:17:57.884591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 12:17:57.885136 ==
4206 12:17:57.887586 [Gating] SW mode calibration
4207 12:17:57.894262 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4208 12:17:57.900976 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4209 12:17:57.904369 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4210 12:17:57.907730 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4211 12:17:57.914402 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4212 12:17:57.917949 0 9 12 | B1->B0 | 3030 3232 | 1 1 | (1 0) (1 0)
4213 12:17:57.920669 0 9 16 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
4214 12:17:57.927315 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 12:17:57.930679 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 12:17:57.934133 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 12:17:57.940690 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 12:17:57.944568 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 12:17:57.947435 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 12:17:57.954410 0 10 12 | B1->B0 | 2f2f 3535 | 0 0 | (0 0) (0 0)
4221 12:17:57.957513 0 10 16 | B1->B0 | 4242 4545 | 0 0 | (0 0) (0 0)
4222 12:17:57.960718 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 12:17:57.967434 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 12:17:57.970820 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 12:17:57.973927 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 12:17:57.980604 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 12:17:57.983866 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 12:17:57.987714 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 12:17:57.993953 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 12:17:57.997081 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 12:17:58.000965 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 12:17:58.007420 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 12:17:58.011118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 12:17:58.014010 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 12:17:58.020593 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 12:17:58.024093 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 12:17:58.027142 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 12:17:58.030846 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 12:17:58.037161 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 12:17:58.040699 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 12:17:58.044201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 12:17:58.050871 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 12:17:58.054071 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 12:17:58.057364 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4245 12:17:58.063810 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4246 12:17:58.064345 Total UI for P1: 0, mck2ui 16
4247 12:17:58.070561 best dqsien dly found for B1: ( 0, 13, 12)
4248 12:17:58.073994 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 12:17:58.077145 Total UI for P1: 0, mck2ui 16
4250 12:17:58.080242 best dqsien dly found for B0: ( 0, 13, 14)
4251 12:17:58.083660 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4252 12:17:58.087205 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4253 12:17:58.087669
4254 12:17:58.090744 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4255 12:17:58.093967 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4256 12:17:58.097001 [Gating] SW calibration Done
4257 12:17:58.097336 ==
4258 12:17:58.100419 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 12:17:58.106651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 12:17:58.106853 ==
4261 12:17:58.107003 RX Vref Scan: 0
4262 12:17:58.107142
4263 12:17:58.109966 RX Vref 0 -> 0, step: 1
4264 12:17:58.110149
4265 12:17:58.113384 RX Delay -230 -> 252, step: 16
4266 12:17:58.116496 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4267 12:17:58.120013 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4268 12:17:58.124063 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4269 12:17:58.130005 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4270 12:17:58.133084 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4271 12:17:58.136722 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4272 12:17:58.139969 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4273 12:17:58.143351 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4274 12:17:58.149867 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4275 12:17:58.153204 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4276 12:17:58.156424 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4277 12:17:58.159700 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4278 12:17:58.166530 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4279 12:17:58.169940 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4280 12:17:58.173090 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4281 12:17:58.176361 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4282 12:17:58.179921 ==
4283 12:17:58.180005 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 12:17:58.186393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 12:17:58.186477 ==
4286 12:17:58.186555 DQS Delay:
4287 12:17:58.189501 DQS0 = 0, DQS1 = 0
4288 12:17:58.189584 DQM Delay:
4289 12:17:58.193218 DQM0 = 47, DQM1 = 42
4290 12:17:58.193301 DQ Delay:
4291 12:17:58.196762 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4292 12:17:58.199946 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4293 12:17:58.203477 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4294 12:17:58.206517 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4295 12:17:58.206613
4296 12:17:58.206689
4297 12:17:58.206759 ==
4298 12:17:58.209748 Dram Type= 6, Freq= 0, CH_0, rank 1
4299 12:17:58.213057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4300 12:17:58.213161 ==
4301 12:17:58.213244
4302 12:17:58.213319
4303 12:17:58.216504 TX Vref Scan disable
4304 12:17:58.219923 == TX Byte 0 ==
4305 12:17:58.223140 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4306 12:17:58.226504 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4307 12:17:58.229975 == TX Byte 1 ==
4308 12:17:58.232948 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4309 12:17:58.236699 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4310 12:17:58.236875 ==
4311 12:17:58.239791 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 12:17:58.243225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 12:17:58.243430 ==
4314 12:17:58.246558
4315 12:17:58.246823
4316 12:17:58.247017 TX Vref Scan disable
4317 12:17:58.250195 == TX Byte 0 ==
4318 12:17:58.253727 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4319 12:17:58.260017 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4320 12:17:58.260448 == TX Byte 1 ==
4321 12:17:58.263793 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4322 12:17:58.270046 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4323 12:17:58.270521
4324 12:17:58.270859 [DATLAT]
4325 12:17:58.271210 Freq=600, CH0 RK1
4326 12:17:58.271515
4327 12:17:58.273532 DATLAT Default: 0x9
4328 12:17:58.274001 0, 0xFFFF, sum = 0
4329 12:17:58.277334 1, 0xFFFF, sum = 0
4330 12:17:58.277812 2, 0xFFFF, sum = 0
4331 12:17:58.280416 3, 0xFFFF, sum = 0
4332 12:17:58.280848 4, 0xFFFF, sum = 0
4333 12:17:58.283686 5, 0xFFFF, sum = 0
4334 12:17:58.287134 6, 0xFFFF, sum = 0
4335 12:17:58.287578 7, 0xFFFF, sum = 0
4336 12:17:58.290110 8, 0x0, sum = 1
4337 12:17:58.290540 9, 0x0, sum = 2
4338 12:17:58.290884 10, 0x0, sum = 3
4339 12:17:58.293499 11, 0x0, sum = 4
4340 12:17:58.293940 best_step = 9
4341 12:17:58.294487
4342 12:17:58.294835 ==
4343 12:17:58.297075 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 12:17:58.303542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 12:17:58.304022 ==
4346 12:17:58.304549 RX Vref Scan: 0
4347 12:17:58.304878
4348 12:17:58.306966 RX Vref 0 -> 0, step: 1
4349 12:17:58.307381
4350 12:17:58.310052 RX Delay -179 -> 252, step: 8
4351 12:17:58.313235 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4352 12:17:58.319978 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4353 12:17:58.323342 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4354 12:17:58.327020 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4355 12:17:58.330050 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4356 12:17:58.333320 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4357 12:17:58.339883 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4358 12:17:58.343348 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4359 12:17:58.346775 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4360 12:17:58.350248 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4361 12:17:58.353241 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4362 12:17:58.359643 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4363 12:17:58.363345 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4364 12:17:58.366570 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4365 12:17:58.369763 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4366 12:17:58.376631 iDelay=205, Bit 15, Center 44 (-99 ~ 188) 288
4367 12:17:58.377114 ==
4368 12:17:58.380026 Dram Type= 6, Freq= 0, CH_0, rank 1
4369 12:17:58.382953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 12:17:58.383411 ==
4371 12:17:58.383770 DQS Delay:
4372 12:17:58.386936 DQS0 = 0, DQS1 = 0
4373 12:17:58.387605 DQM Delay:
4374 12:17:58.389773 DQM0 = 47, DQM1 = 39
4375 12:17:58.390465 DQ Delay:
4376 12:17:58.393068 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4377 12:17:58.396400 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4378 12:17:58.399926 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4379 12:17:58.403048 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =44
4380 12:17:58.403617
4381 12:17:58.404104
4382 12:17:58.409741 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4383 12:17:58.412909 CH0 RK1: MR19=808, MR18=5F2D
4384 12:17:58.419653 CH0_RK1: MR19=0x808, MR18=0x5F2D, DQSOSC=391, MR23=63, INC=171, DEC=114
4385 12:17:58.423270 [RxdqsGatingPostProcess] freq 600
4386 12:17:58.429865 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4387 12:17:58.432878 Pre-setting of DQS Precalculation
4388 12:17:58.436087 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4389 12:17:58.436529 ==
4390 12:17:58.439729 Dram Type= 6, Freq= 0, CH_1, rank 0
4391 12:17:58.442900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 12:17:58.443344 ==
4393 12:17:58.449790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 12:17:58.456253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4395 12:17:58.459564 [CA 0] Center 35 (5~66) winsize 62
4396 12:17:58.462833 [CA 1] Center 35 (5~66) winsize 62
4397 12:17:58.466124 [CA 2] Center 34 (4~65) winsize 62
4398 12:17:58.469574 [CA 3] Center 34 (3~65) winsize 63
4399 12:17:58.472725 [CA 4] Center 34 (3~65) winsize 63
4400 12:17:58.475930 [CA 5] Center 33 (3~64) winsize 62
4401 12:17:58.476370
4402 12:17:58.479237 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4403 12:17:58.479697
4404 12:17:58.482447 [CATrainingPosCal] consider 1 rank data
4405 12:17:58.485905 u2DelayCellTimex100 = 270/100 ps
4406 12:17:58.489677 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4407 12:17:58.492874 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4408 12:17:58.496377 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 12:17:58.499257 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4410 12:17:58.502718 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4411 12:17:58.505898 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 12:17:58.509437
4413 12:17:58.512656 CA PerBit enable=1, Macro0, CA PI delay=33
4414 12:17:58.513283
4415 12:17:58.515700 [CBTSetCACLKResult] CA Dly = 33
4416 12:17:58.516148 CS Dly: 4 (0~35)
4417 12:17:58.516530 ==
4418 12:17:58.519272 Dram Type= 6, Freq= 0, CH_1, rank 1
4419 12:17:58.522710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 12:17:58.523185 ==
4421 12:17:58.529465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 12:17:58.536061 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4423 12:17:58.539500 [CA 0] Center 35 (5~66) winsize 62
4424 12:17:58.542570 [CA 1] Center 35 (5~66) winsize 62
4425 12:17:58.546305 [CA 2] Center 34 (4~65) winsize 62
4426 12:17:58.549379 [CA 3] Center 34 (4~64) winsize 61
4427 12:17:58.552683 [CA 4] Center 34 (4~65) winsize 62
4428 12:17:58.556053 [CA 5] Center 33 (3~64) winsize 62
4429 12:17:58.556535
4430 12:17:58.559041 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4431 12:17:58.559465
4432 12:17:58.562394 [CATrainingPosCal] consider 2 rank data
4433 12:17:58.565950 u2DelayCellTimex100 = 270/100 ps
4434 12:17:58.569229 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4435 12:17:58.572740 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4436 12:17:58.576225 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 12:17:58.579386 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4438 12:17:58.583126 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 12:17:58.589141 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4440 12:17:58.589680
4441 12:17:58.592474 CA PerBit enable=1, Macro0, CA PI delay=33
4442 12:17:58.592903
4443 12:17:58.595871 [CBTSetCACLKResult] CA Dly = 33
4444 12:17:58.596304 CS Dly: 4 (0~36)
4445 12:17:58.596647
4446 12:17:58.599307 ----->DramcWriteLeveling(PI) begin...
4447 12:17:58.599741 ==
4448 12:17:58.602559 Dram Type= 6, Freq= 0, CH_1, rank 0
4449 12:17:58.609223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4450 12:17:58.609744 ==
4451 12:17:58.612523 Write leveling (Byte 0): 29 => 29
4452 12:17:58.612989 Write leveling (Byte 1): 32 => 32
4453 12:17:58.615702 DramcWriteLeveling(PI) end<-----
4454 12:17:58.616131
4455 12:17:58.616520 ==
4456 12:17:58.618956 Dram Type= 6, Freq= 0, CH_1, rank 0
4457 12:17:58.625883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 12:17:58.626490 ==
4459 12:17:58.629005 [Gating] SW mode calibration
4460 12:17:58.635995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4461 12:17:58.638904 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4462 12:17:58.645665 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4463 12:17:58.648844 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4464 12:17:58.652104 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4465 12:17:58.658930 0 9 12 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (1 0)
4466 12:17:58.662252 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 12:17:58.665784 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 12:17:58.668953 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 12:17:58.675552 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 12:17:58.678862 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 12:17:58.682205 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 12:17:58.688847 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 12:17:58.692450 0 10 12 | B1->B0 | 3b3b 3b3b | 0 0 | (0 0) (0 0)
4474 12:17:58.695662 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 12:17:58.702218 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 12:17:58.705385 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 12:17:58.709042 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 12:17:58.715805 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 12:17:58.718918 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 12:17:58.722456 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 12:17:58.728738 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4482 12:17:58.732025 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4483 12:17:58.735608 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 12:17:58.742106 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 12:17:58.745785 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 12:17:58.749050 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 12:17:58.755639 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:17:58.759041 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:17:58.761976 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:17:58.768785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 12:17:58.772365 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 12:17:58.775542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:17:58.779068 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 12:17:58.785577 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 12:17:58.788881 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:17:58.792225 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:17:58.799006 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4498 12:17:58.801954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 12:17:58.805335 Total UI for P1: 0, mck2ui 16
4500 12:17:58.808730 best dqsien dly found for B0: ( 0, 13, 12)
4501 12:17:58.812068 Total UI for P1: 0, mck2ui 16
4502 12:17:58.815332 best dqsien dly found for B1: ( 0, 13, 12)
4503 12:17:58.818762 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4504 12:17:58.821984 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4505 12:17:58.822408
4506 12:17:58.825283 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4507 12:17:58.831957 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4508 12:17:58.832382 [Gating] SW calibration Done
4509 12:17:58.832720 ==
4510 12:17:58.835422 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 12:17:58.841923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 12:17:58.842349 ==
4513 12:17:58.842686 RX Vref Scan: 0
4514 12:17:58.842999
4515 12:17:58.845120 RX Vref 0 -> 0, step: 1
4516 12:17:58.845541
4517 12:17:58.848560 RX Delay -230 -> 252, step: 16
4518 12:17:58.851831 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4519 12:17:58.855381 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4520 12:17:58.858547 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4521 12:17:58.865328 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4522 12:17:58.868507 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4523 12:17:58.871837 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4524 12:17:58.875176 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4525 12:17:58.878298 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4526 12:17:58.885517 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4527 12:17:58.888531 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4528 12:17:58.891564 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4529 12:17:58.895110 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4530 12:17:58.901932 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4531 12:17:58.905387 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4532 12:17:58.908268 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4533 12:17:58.911717 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4534 12:17:58.912142 ==
4535 12:17:58.914817 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 12:17:58.921868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 12:17:58.922300 ==
4538 12:17:58.922638 DQS Delay:
4539 12:17:58.924735 DQS0 = 0, DQS1 = 0
4540 12:17:58.925258 DQM Delay:
4541 12:17:58.925602 DQM0 = 53, DQM1 = 44
4542 12:17:58.928153 DQ Delay:
4543 12:17:58.931895 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4544 12:17:58.934841 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4545 12:17:58.938414 DQ8 =25, DQ9 =25, DQ10 =49, DQ11 =41
4546 12:17:58.941566 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4547 12:17:58.941991
4548 12:17:58.942326
4549 12:17:58.942637 ==
4550 12:17:58.944860 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 12:17:58.948187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 12:17:58.948614 ==
4553 12:17:58.948994
4554 12:17:58.949325
4555 12:17:58.951483 TX Vref Scan disable
4556 12:17:58.955010 == TX Byte 0 ==
4557 12:17:58.958049 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4558 12:17:58.961774 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4559 12:17:58.964437 == TX Byte 1 ==
4560 12:17:58.968389 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4561 12:17:58.971697 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4562 12:17:58.972017 ==
4563 12:17:58.974762 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 12:17:58.978079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 12:17:58.978363 ==
4566 12:17:58.981548
4567 12:17:58.981789
4568 12:17:58.981982 TX Vref Scan disable
4569 12:17:58.985100 == TX Byte 0 ==
4570 12:17:58.988453 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4571 12:17:58.991530 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4572 12:17:58.995086 == TX Byte 1 ==
4573 12:17:58.998115 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4574 12:17:59.004905 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4575 12:17:59.005173
4576 12:17:59.005362 [DATLAT]
4577 12:17:59.005539 Freq=600, CH1 RK0
4578 12:17:59.005711
4579 12:17:59.008147 DATLAT Default: 0x9
4580 12:17:59.008494 0, 0xFFFF, sum = 0
4581 12:17:59.011517 1, 0xFFFF, sum = 0
4582 12:17:59.011762 2, 0xFFFF, sum = 0
4583 12:17:59.014954 3, 0xFFFF, sum = 0
4584 12:17:59.015215 4, 0xFFFF, sum = 0
4585 12:17:59.018306 5, 0xFFFF, sum = 0
4586 12:17:59.021573 6, 0xFFFF, sum = 0
4587 12:17:59.021826 7, 0xFFFF, sum = 0
4588 12:17:59.022025 8, 0x0, sum = 1
4589 12:17:59.024758 9, 0x0, sum = 2
4590 12:17:59.025075 10, 0x0, sum = 3
4591 12:17:59.028097 11, 0x0, sum = 4
4592 12:17:59.028346 best_step = 9
4593 12:17:59.028542
4594 12:17:59.028725 ==
4595 12:17:59.031370 Dram Type= 6, Freq= 0, CH_1, rank 0
4596 12:17:59.038314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 12:17:59.038726 ==
4598 12:17:59.039063 RX Vref Scan: 1
4599 12:17:59.039385
4600 12:17:59.041445 RX Vref 0 -> 0, step: 1
4601 12:17:59.041877
4602 12:17:59.044786 RX Delay -179 -> 252, step: 8
4603 12:17:59.045293
4604 12:17:59.048108 Set Vref, RX VrefLevel [Byte0]: 52
4605 12:17:59.051431 [Byte1]: 50
4606 12:17:59.052042
4607 12:17:59.054597 Final RX Vref Byte 0 = 52 to rank0
4608 12:17:59.058030 Final RX Vref Byte 1 = 50 to rank0
4609 12:17:59.061670 Final RX Vref Byte 0 = 52 to rank1
4610 12:17:59.064913 Final RX Vref Byte 1 = 50 to rank1==
4611 12:17:59.068130 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 12:17:59.071348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 12:17:59.071775 ==
4614 12:17:59.074970 DQS Delay:
4615 12:17:59.075457 DQS0 = 0, DQS1 = 0
4616 12:17:59.075819 DQM Delay:
4617 12:17:59.078162 DQM0 = 49, DQM1 = 41
4618 12:17:59.078647 DQ Delay:
4619 12:17:59.081768 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4620 12:17:59.084762 DQ4 =52, DQ5 =60, DQ6 =56, DQ7 =44
4621 12:17:59.088003 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4622 12:17:59.091331 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4623 12:17:59.091918
4624 12:17:59.092362
4625 12:17:59.101348 [DQSOSCAuto] RK0, (LSB)MR18= 0x486f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4626 12:17:59.104239 CH1 RK0: MR19=808, MR18=486F
4627 12:17:59.107571 CH1_RK0: MR19=0x808, MR18=0x486F, DQSOSC=389, MR23=63, INC=173, DEC=115
4628 12:17:59.107649
4629 12:17:59.114085 ----->DramcWriteLeveling(PI) begin...
4630 12:17:59.114173 ==
4631 12:17:59.117502 Dram Type= 6, Freq= 0, CH_1, rank 1
4632 12:17:59.121195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 12:17:59.121288 ==
4634 12:17:59.124431 Write leveling (Byte 0): 30 => 30
4635 12:17:59.127612 Write leveling (Byte 1): 30 => 30
4636 12:17:59.130898 DramcWriteLeveling(PI) end<-----
4637 12:17:59.131002
4638 12:17:59.131094 ==
4639 12:17:59.134110 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 12:17:59.137284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 12:17:59.137366 ==
4642 12:17:59.141106 [Gating] SW mode calibration
4643 12:17:59.147408 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4644 12:17:59.154243 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4645 12:17:59.157529 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4646 12:17:59.160686 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 12:17:59.167524 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
4648 12:17:59.170674 0 9 12 | B1->B0 | 2a2a 3232 | 0 0 | (0 0) (1 1)
4649 12:17:59.174030 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4650 12:17:59.177455 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 12:17:59.184132 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 12:17:59.187441 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 12:17:59.190911 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 12:17:59.197521 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 12:17:59.200472 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4656 12:17:59.204167 0 10 12 | B1->B0 | 4141 3030 | 0 0 | (0 0) (0 0)
4657 12:17:59.210784 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 12:17:59.213830 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 12:17:59.217078 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 12:17:59.223864 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 12:17:59.227201 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 12:17:59.230655 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 12:17:59.236908 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 12:17:59.240246 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 12:17:59.244055 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 12:17:59.250446 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 12:17:59.253828 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 12:17:59.257123 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 12:17:59.263949 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 12:17:59.267232 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 12:17:59.270681 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 12:17:59.277263 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:17:59.280397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 12:17:59.283896 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 12:17:59.290528 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 12:17:59.293934 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 12:17:59.297331 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 12:17:59.300605 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 12:17:59.307316 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:17:59.310555 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4681 12:17:59.314192 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 12:17:59.317158 Total UI for P1: 0, mck2ui 16
4683 12:17:59.320527 best dqsien dly found for B0: ( 0, 13, 12)
4684 12:17:59.323962 Total UI for P1: 0, mck2ui 16
4685 12:17:59.327174 best dqsien dly found for B1: ( 0, 13, 12)
4686 12:17:59.330326 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4687 12:17:59.337184 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4688 12:17:59.337268
4689 12:17:59.340321 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4690 12:17:59.343857 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4691 12:17:59.346954 [Gating] SW calibration Done
4692 12:17:59.347063 ==
4693 12:17:59.350429 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 12:17:59.353946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 12:17:59.354026 ==
4696 12:17:59.354094 RX Vref Scan: 0
4697 12:17:59.357343
4698 12:17:59.357740 RX Vref 0 -> 0, step: 1
4699 12:17:59.358052
4700 12:17:59.361125 RX Delay -230 -> 252, step: 16
4701 12:17:59.363911 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4702 12:17:59.367728 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4703 12:17:59.374491 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4704 12:17:59.377599 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4705 12:17:59.380699 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4706 12:17:59.384123 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4707 12:17:59.390660 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4708 12:17:59.394497 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4709 12:17:59.397431 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4710 12:17:59.400577 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4711 12:17:59.404116 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4712 12:17:59.410425 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4713 12:17:59.413739 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4714 12:17:59.417156 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4715 12:17:59.420506 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4716 12:17:59.427054 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4717 12:17:59.427613 ==
4718 12:17:59.430249 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 12:17:59.433467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 12:17:59.433895 ==
4721 12:17:59.434233 DQS Delay:
4722 12:17:59.436668 DQS0 = 0, DQS1 = 0
4723 12:17:59.437123 DQM Delay:
4724 12:17:59.440169 DQM0 = 51, DQM1 = 44
4725 12:17:59.440621 DQ Delay:
4726 12:17:59.443632 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4727 12:17:59.446828 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4728 12:17:59.450022 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4729 12:17:59.453562 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =57
4730 12:17:59.453994
4731 12:17:59.454363
4732 12:17:59.454678 ==
4733 12:17:59.457200 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 12:17:59.460273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 12:17:59.463502 ==
4736 12:17:59.464305
4737 12:17:59.464921
4738 12:17:59.465519 TX Vref Scan disable
4739 12:17:59.467000 == TX Byte 0 ==
4740 12:17:59.469927 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4741 12:17:59.473355 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4742 12:17:59.476586 == TX Byte 1 ==
4743 12:17:59.480045 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4744 12:17:59.483232 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4745 12:17:59.486702 ==
4746 12:17:59.487125 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 12:17:59.493726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 12:17:59.494164 ==
4749 12:17:59.494585
4750 12:17:59.495012
4751 12:17:59.496681 TX Vref Scan disable
4752 12:17:59.497093 == TX Byte 0 ==
4753 12:17:59.503105 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4754 12:17:59.506692 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4755 12:17:59.507133 == TX Byte 1 ==
4756 12:17:59.513537 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4757 12:17:59.516689 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4758 12:17:59.517170
4759 12:17:59.517709 [DATLAT]
4760 12:17:59.520100 Freq=600, CH1 RK1
4761 12:17:59.520524
4762 12:17:59.520857 DATLAT Default: 0x9
4763 12:17:59.523356 0, 0xFFFF, sum = 0
4764 12:17:59.523783 1, 0xFFFF, sum = 0
4765 12:17:59.526628 2, 0xFFFF, sum = 0
4766 12:17:59.527054 3, 0xFFFF, sum = 0
4767 12:17:59.529887 4, 0xFFFF, sum = 0
4768 12:17:59.530315 5, 0xFFFF, sum = 0
4769 12:17:59.533676 6, 0xFFFF, sum = 0
4770 12:17:59.534146 7, 0xFFFF, sum = 0
4771 12:17:59.536815 8, 0x0, sum = 1
4772 12:17:59.537276 9, 0x0, sum = 2
4773 12:17:59.539952 10, 0x0, sum = 3
4774 12:17:59.540377 11, 0x0, sum = 4
4775 12:17:59.543253 best_step = 9
4776 12:17:59.543673
4777 12:17:59.544002 ==
4778 12:17:59.546659 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 12:17:59.550195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 12:17:59.550622 ==
4781 12:17:59.553523 RX Vref Scan: 0
4782 12:17:59.553963
4783 12:17:59.554315 RX Vref 0 -> 0, step: 1
4784 12:17:59.554668
4785 12:17:59.556741 RX Delay -163 -> 252, step: 8
4786 12:17:59.563608 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4787 12:17:59.566956 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4788 12:17:59.570192 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4789 12:17:59.573392 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4790 12:17:59.576956 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4791 12:17:59.583729 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4792 12:17:59.586980 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4793 12:17:59.590268 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4794 12:17:59.593700 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4795 12:17:59.596791 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4796 12:17:59.603278 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4797 12:17:59.606848 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4798 12:17:59.609864 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4799 12:17:59.613622 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4800 12:17:59.620098 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4801 12:17:59.623587 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4802 12:17:59.624010 ==
4803 12:17:59.627084 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 12:17:59.630092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 12:17:59.630504 ==
4806 12:17:59.630848 DQS Delay:
4807 12:17:59.633709 DQS0 = 0, DQS1 = 0
4808 12:17:59.634242 DQM Delay:
4809 12:17:59.637047 DQM0 = 49, DQM1 = 44
4810 12:17:59.637478 DQ Delay:
4811 12:17:59.640066 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4812 12:17:59.643446 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4813 12:17:59.646566 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4814 12:17:59.650422 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =56
4815 12:17:59.650875
4816 12:17:59.651363
4817 12:17:59.659859 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4818 12:17:59.660306 CH1 RK1: MR19=808, MR18=5A20
4819 12:17:59.666744 CH1_RK1: MR19=0x808, MR18=0x5A20, DQSOSC=392, MR23=63, INC=170, DEC=113
4820 12:17:59.670084 [RxdqsGatingPostProcess] freq 600
4821 12:17:59.676738 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4822 12:17:59.680114 Pre-setting of DQS Precalculation
4823 12:17:59.683808 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4824 12:17:59.689844 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4825 12:17:59.696740 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4826 12:17:59.699906
4827 12:17:59.700351
4828 12:17:59.700705 [Calibration Summary] 1200 Mbps
4829 12:17:59.703367 CH 0, Rank 0
4830 12:17:59.703906 SW Impedance : PASS
4831 12:17:59.706549 DUTY Scan : NO K
4832 12:17:59.709886 ZQ Calibration : PASS
4833 12:17:59.710319 Jitter Meter : NO K
4834 12:17:59.713474 CBT Training : PASS
4835 12:17:59.716633 Write leveling : PASS
4836 12:17:59.717258 RX DQS gating : PASS
4837 12:17:59.719876 RX DQ/DQS(RDDQC) : PASS
4838 12:17:59.722959 TX DQ/DQS : PASS
4839 12:17:59.723415 RX DATLAT : PASS
4840 12:17:59.726420 RX DQ/DQS(Engine): PASS
4841 12:17:59.729752 TX OE : NO K
4842 12:17:59.730195 All Pass.
4843 12:17:59.730568
4844 12:17:59.730893 CH 0, Rank 1
4845 12:17:59.732804 SW Impedance : PASS
4846 12:17:59.736284 DUTY Scan : NO K
4847 12:17:59.736879 ZQ Calibration : PASS
4848 12:17:59.739604 Jitter Meter : NO K
4849 12:17:59.743133 CBT Training : PASS
4850 12:17:59.743564 Write leveling : PASS
4851 12:17:59.746162 RX DQS gating : PASS
4852 12:17:59.749659 RX DQ/DQS(RDDQC) : PASS
4853 12:17:59.750103 TX DQ/DQS : PASS
4854 12:17:59.752777 RX DATLAT : PASS
4855 12:17:59.753244 RX DQ/DQS(Engine): PASS
4856 12:17:59.756067 TX OE : NO K
4857 12:17:59.756620 All Pass.
4858 12:17:59.757027
4859 12:17:59.759512 CH 1, Rank 0
4860 12:17:59.760011 SW Impedance : PASS
4861 12:17:59.763390 DUTY Scan : NO K
4862 12:17:59.766322 ZQ Calibration : PASS
4863 12:17:59.766766 Jitter Meter : NO K
4864 12:17:59.769623 CBT Training : PASS
4865 12:17:59.772750 Write leveling : PASS
4866 12:17:59.773307 RX DQS gating : PASS
4867 12:17:59.776301 RX DQ/DQS(RDDQC) : PASS
4868 12:17:59.779470 TX DQ/DQS : PASS
4869 12:17:59.779903 RX DATLAT : PASS
4870 12:17:59.782735 RX DQ/DQS(Engine): PASS
4871 12:17:59.786024 TX OE : NO K
4872 12:17:59.786508 All Pass.
4873 12:17:59.786890
4874 12:17:59.787221 CH 1, Rank 1
4875 12:17:59.789263 SW Impedance : PASS
4876 12:17:59.792703 DUTY Scan : NO K
4877 12:17:59.793269 ZQ Calibration : PASS
4878 12:17:59.796458 Jitter Meter : NO K
4879 12:17:59.799601 CBT Training : PASS
4880 12:17:59.800074 Write leveling : PASS
4881 12:17:59.802933 RX DQS gating : PASS
4882 12:17:59.803572 RX DQ/DQS(RDDQC) : PASS
4883 12:17:59.806382 TX DQ/DQS : PASS
4884 12:17:59.809583 RX DATLAT : PASS
4885 12:17:59.810066 RX DQ/DQS(Engine): PASS
4886 12:17:59.812966 TX OE : NO K
4887 12:17:59.813405 All Pass.
4888 12:17:59.813828
4889 12:17:59.815910 DramC Write-DBI off
4890 12:17:59.819231 PER_BANK_REFRESH: Hybrid Mode
4891 12:17:59.819622 TX_TRACKING: ON
4892 12:17:59.829390 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4893 12:17:59.832493 [FAST_K] Save calibration result to emmc
4894 12:17:59.835687 dramc_set_vcore_voltage set vcore to 662500
4895 12:17:59.839213 Read voltage for 933, 3
4896 12:17:59.839453 Vio18 = 0
4897 12:17:59.839634 Vcore = 662500
4898 12:17:59.842383 Vdram = 0
4899 12:17:59.842612 Vddq = 0
4900 12:17:59.842795 Vmddr = 0
4901 12:17:59.848897 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4902 12:17:59.852346 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4903 12:17:59.855555 MEM_TYPE=3, freq_sel=17
4904 12:17:59.859159 sv_algorithm_assistance_LP4_1600
4905 12:17:59.862542 ============ PULL DRAM RESETB DOWN ============
4906 12:17:59.869042 ========== PULL DRAM RESETB DOWN end =========
4907 12:17:59.872726 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4908 12:17:59.875850 ===================================
4909 12:17:59.879007 LPDDR4 DRAM CONFIGURATION
4910 12:17:59.882208 ===================================
4911 12:17:59.882777 EX_ROW_EN[0] = 0x0
4912 12:17:59.885941 EX_ROW_EN[1] = 0x0
4913 12:17:59.886510 LP4Y_EN = 0x0
4914 12:17:59.889229 WORK_FSP = 0x0
4915 12:17:59.889720 WL = 0x3
4916 12:17:59.892623 RL = 0x3
4917 12:17:59.893091 BL = 0x2
4918 12:17:59.895703 RPST = 0x0
4919 12:17:59.896248 RD_PRE = 0x0
4920 12:17:59.899339 WR_PRE = 0x1
4921 12:17:59.899943 WR_PST = 0x0
4922 12:17:59.902478 DBI_WR = 0x0
4923 12:17:59.902973 DBI_RD = 0x0
4924 12:17:59.905843 OTF = 0x1
4925 12:17:59.909050 ===================================
4926 12:17:59.912131 ===================================
4927 12:17:59.912554 ANA top config
4928 12:17:59.915418 ===================================
4929 12:17:59.918921 DLL_ASYNC_EN = 0
4930 12:17:59.922297 ALL_SLAVE_EN = 1
4931 12:17:59.925754 NEW_RANK_MODE = 1
4932 12:17:59.926205 DLL_IDLE_MODE = 1
4933 12:17:59.929033 LP45_APHY_COMB_EN = 1
4934 12:17:59.932549 TX_ODT_DIS = 1
4935 12:17:59.935684 NEW_8X_MODE = 1
4936 12:17:59.939114 ===================================
4937 12:17:59.942446 ===================================
4938 12:17:59.945830 data_rate = 1866
4939 12:17:59.946348 CKR = 1
4940 12:17:59.949078 DQ_P2S_RATIO = 8
4941 12:17:59.952258 ===================================
4942 12:17:59.955567 CA_P2S_RATIO = 8
4943 12:17:59.959059 DQ_CA_OPEN = 0
4944 12:17:59.962186 DQ_SEMI_OPEN = 0
4945 12:17:59.965495 CA_SEMI_OPEN = 0
4946 12:17:59.966018 CA_FULL_RATE = 0
4947 12:17:59.968922 DQ_CKDIV4_EN = 1
4948 12:17:59.972199 CA_CKDIV4_EN = 1
4949 12:17:59.975360 CA_PREDIV_EN = 0
4950 12:17:59.978908 PH8_DLY = 0
4951 12:17:59.982394 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4952 12:17:59.982927 DQ_AAMCK_DIV = 4
4953 12:17:59.985535 CA_AAMCK_DIV = 4
4954 12:17:59.988723 CA_ADMCK_DIV = 4
4955 12:17:59.992233 DQ_TRACK_CA_EN = 0
4956 12:17:59.995429 CA_PICK = 933
4957 12:17:59.998612 CA_MCKIO = 933
4958 12:18:00.002019 MCKIO_SEMI = 0
4959 12:18:00.002103 PLL_FREQ = 3732
4960 12:18:00.004883 DQ_UI_PI_RATIO = 32
4961 12:18:00.008320 CA_UI_PI_RATIO = 0
4962 12:18:00.011691 ===================================
4963 12:18:00.014924 ===================================
4964 12:18:00.018137 memory_type:LPDDR4
4965 12:18:00.018221 GP_NUM : 10
4966 12:18:00.021597 SRAM_EN : 1
4967 12:18:00.025235 MD32_EN : 0
4968 12:18:00.028316 ===================================
4969 12:18:00.028400 [ANA_INIT] >>>>>>>>>>>>>>
4970 12:18:00.031763 <<<<<< [CONFIGURE PHASE]: ANA_TX
4971 12:18:00.035140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4972 12:18:00.038417 ===================================
4973 12:18:00.041539 data_rate = 1866,PCW = 0X8f00
4974 12:18:00.045085 ===================================
4975 12:18:00.048317 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4976 12:18:00.054916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4977 12:18:00.058466 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4978 12:18:00.065064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4979 12:18:00.068289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4980 12:18:00.071706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4981 12:18:00.071779 [ANA_INIT] flow start
4982 12:18:00.074810 [ANA_INIT] PLL >>>>>>>>
4983 12:18:00.078076 [ANA_INIT] PLL <<<<<<<<
4984 12:18:00.081858 [ANA_INIT] MIDPI >>>>>>>>
4985 12:18:00.081943 [ANA_INIT] MIDPI <<<<<<<<
4986 12:18:00.084876 [ANA_INIT] DLL >>>>>>>>
4987 12:18:00.088336 [ANA_INIT] flow end
4988 12:18:00.091546 ============ LP4 DIFF to SE enter ============
4989 12:18:00.095086 ============ LP4 DIFF to SE exit ============
4990 12:18:00.098428 [ANA_INIT] <<<<<<<<<<<<<
4991 12:18:00.101358 [Flow] Enable top DCM control >>>>>
4992 12:18:00.104727 [Flow] Enable top DCM control <<<<<
4993 12:18:00.108335 Enable DLL master slave shuffle
4994 12:18:00.111588 ==============================================================
4995 12:18:00.114678 Gating Mode config
4996 12:18:00.118238 ==============================================================
4997 12:18:00.121247 Config description:
4998 12:18:00.131559 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4999 12:18:00.138153 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5000 12:18:00.141321 SELPH_MODE 0: By rank 1: By Phase
5001 12:18:00.147756 ==============================================================
5002 12:18:00.151481 GAT_TRACK_EN = 1
5003 12:18:00.154611 RX_GATING_MODE = 2
5004 12:18:00.158063 RX_GATING_TRACK_MODE = 2
5005 12:18:00.161260 SELPH_MODE = 1
5006 12:18:00.164541 PICG_EARLY_EN = 1
5007 12:18:00.164643 VALID_LAT_VALUE = 1
5008 12:18:00.171157 ==============================================================
5009 12:18:00.174769 Enter into Gating configuration >>>>
5010 12:18:00.178069 Exit from Gating configuration <<<<
5011 12:18:00.181260 Enter into DVFS_PRE_config >>>>>
5012 12:18:00.191401 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5013 12:18:00.194672 Exit from DVFS_PRE_config <<<<<
5014 12:18:00.198194 Enter into PICG configuration >>>>
5015 12:18:00.200897 Exit from PICG configuration <<<<
5016 12:18:00.204640 [RX_INPUT] configuration >>>>>
5017 12:18:00.207853 [RX_INPUT] configuration <<<<<
5018 12:18:00.211435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5019 12:18:00.217826 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5020 12:18:00.224236 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5021 12:18:00.230840 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5022 12:18:00.237486 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5023 12:18:00.244334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5024 12:18:00.247877 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5025 12:18:00.250865 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5026 12:18:00.254208 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5027 12:18:00.261180 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5028 12:18:00.264535 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5029 12:18:00.267469 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5030 12:18:00.271124 ===================================
5031 12:18:00.274575 LPDDR4 DRAM CONFIGURATION
5032 12:18:00.277309 ===================================
5033 12:18:00.277393 EX_ROW_EN[0] = 0x0
5034 12:18:00.281278 EX_ROW_EN[1] = 0x0
5035 12:18:00.281365 LP4Y_EN = 0x0
5036 12:18:00.284220 WORK_FSP = 0x0
5037 12:18:00.284309 WL = 0x3
5038 12:18:00.287523 RL = 0x3
5039 12:18:00.287606 BL = 0x2
5040 12:18:00.290877 RPST = 0x0
5041 12:18:00.294178 RD_PRE = 0x0
5042 12:18:00.294261 WR_PRE = 0x1
5043 12:18:00.297494 WR_PST = 0x0
5044 12:18:00.297577 DBI_WR = 0x0
5045 12:18:00.300817 DBI_RD = 0x0
5046 12:18:00.300926 OTF = 0x1
5047 12:18:00.303942 ===================================
5048 12:18:00.307525 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5049 12:18:00.314060 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5050 12:18:00.317286 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5051 12:18:00.320854 ===================================
5052 12:18:00.323988 LPDDR4 DRAM CONFIGURATION
5053 12:18:00.327569 ===================================
5054 12:18:00.327653 EX_ROW_EN[0] = 0x10
5055 12:18:00.330587 EX_ROW_EN[1] = 0x0
5056 12:18:00.330670 LP4Y_EN = 0x0
5057 12:18:00.333802 WORK_FSP = 0x0
5058 12:18:00.333889 WL = 0x3
5059 12:18:00.337136 RL = 0x3
5060 12:18:00.337220 BL = 0x2
5061 12:18:00.340748 RPST = 0x0
5062 12:18:00.340832 RD_PRE = 0x0
5063 12:18:00.344015 WR_PRE = 0x1
5064 12:18:00.344099 WR_PST = 0x0
5065 12:18:00.347767 DBI_WR = 0x0
5066 12:18:00.350752 DBI_RD = 0x0
5067 12:18:00.350836 OTF = 0x1
5068 12:18:00.354147 ===================================
5069 12:18:00.360673 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5070 12:18:00.364083 nWR fixed to 30
5071 12:18:00.367247 [ModeRegInit_LP4] CH0 RK0
5072 12:18:00.367331 [ModeRegInit_LP4] CH0 RK1
5073 12:18:00.370881 [ModeRegInit_LP4] CH1 RK0
5074 12:18:00.373861 [ModeRegInit_LP4] CH1 RK1
5075 12:18:00.373944 match AC timing 9
5076 12:18:00.380741 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5077 12:18:00.384201 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5078 12:18:00.387401 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5079 12:18:00.394324 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5080 12:18:00.397574 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5081 12:18:00.397662 ==
5082 12:18:00.400825 Dram Type= 6, Freq= 0, CH_0, rank 0
5083 12:18:00.404208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 12:18:00.404292 ==
5085 12:18:00.410718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 12:18:00.417298 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5087 12:18:00.420341 [CA 0] Center 37 (7~68) winsize 62
5088 12:18:00.423953 [CA 1] Center 38 (8~68) winsize 61
5089 12:18:00.427061 [CA 2] Center 35 (5~65) winsize 61
5090 12:18:00.430659 [CA 3] Center 34 (4~65) winsize 62
5091 12:18:00.433867 [CA 4] Center 34 (4~64) winsize 61
5092 12:18:00.437378 [CA 5] Center 33 (3~64) winsize 62
5093 12:18:00.437462
5094 12:18:00.440591 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5095 12:18:00.440674
5096 12:18:00.443462 [CATrainingPosCal] consider 1 rank data
5097 12:18:00.447016 u2DelayCellTimex100 = 270/100 ps
5098 12:18:00.450470 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5099 12:18:00.453635 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5100 12:18:00.457167 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5101 12:18:00.460271 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5102 12:18:00.463662 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5103 12:18:00.470104 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5104 12:18:00.470218
5105 12:18:00.473416 CA PerBit enable=1, Macro0, CA PI delay=33
5106 12:18:00.473499
5107 12:18:00.476844 [CBTSetCACLKResult] CA Dly = 33
5108 12:18:00.476985 CS Dly: 6 (0~37)
5109 12:18:00.477053 ==
5110 12:18:00.480083 Dram Type= 6, Freq= 0, CH_0, rank 1
5111 12:18:00.483420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 12:18:00.486838 ==
5113 12:18:00.490121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5114 12:18:00.496863 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5115 12:18:00.499676 [CA 0] Center 38 (8~69) winsize 62
5116 12:18:00.503338 [CA 1] Center 38 (8~69) winsize 62
5117 12:18:00.506482 [CA 2] Center 36 (6~66) winsize 61
5118 12:18:00.509745 [CA 3] Center 35 (5~66) winsize 62
5119 12:18:00.513145 [CA 4] Center 34 (4~65) winsize 62
5120 12:18:00.516384 [CA 5] Center 34 (4~64) winsize 61
5121 12:18:00.516467
5122 12:18:00.519670 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5123 12:18:00.519755
5124 12:18:00.522880 [CATrainingPosCal] consider 2 rank data
5125 12:18:00.526134 u2DelayCellTimex100 = 270/100 ps
5126 12:18:00.529877 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5127 12:18:00.533087 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5128 12:18:00.536098 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5129 12:18:00.539611 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5130 12:18:00.546030 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5131 12:18:00.549424 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5132 12:18:00.549503
5133 12:18:00.552833 CA PerBit enable=1, Macro0, CA PI delay=34
5134 12:18:00.552910
5135 12:18:00.556274 [CBTSetCACLKResult] CA Dly = 34
5136 12:18:00.556347 CS Dly: 7 (0~39)
5137 12:18:00.556426
5138 12:18:00.559576 ----->DramcWriteLeveling(PI) begin...
5139 12:18:00.559665 ==
5140 12:18:00.562769 Dram Type= 6, Freq= 0, CH_0, rank 0
5141 12:18:00.569331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 12:18:00.569409 ==
5143 12:18:00.572890 Write leveling (Byte 0): 29 => 29
5144 12:18:00.576025 Write leveling (Byte 1): 28 => 28
5145 12:18:00.576108 DramcWriteLeveling(PI) end<-----
5146 12:18:00.579329
5147 12:18:00.579402 ==
5148 12:18:00.582730 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 12:18:00.585764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 12:18:00.585840 ==
5151 12:18:00.589303 [Gating] SW mode calibration
5152 12:18:00.596068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5153 12:18:00.599149 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5154 12:18:00.605924 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5155 12:18:00.608866 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 12:18:00.612291 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 12:18:00.619031 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 12:18:00.622415 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 12:18:00.625530 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 12:18:00.632141 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
5161 12:18:00.635442 0 14 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5162 12:18:00.638822 0 15 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5163 12:18:00.645553 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 12:18:00.648925 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 12:18:00.652023 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 12:18:00.658759 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 12:18:00.662081 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 12:18:00.665437 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5169 12:18:00.672019 0 15 28 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
5170 12:18:00.675493 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5171 12:18:00.678790 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 12:18:00.685362 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 12:18:00.688830 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 12:18:00.692020 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 12:18:00.698601 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 12:18:00.702052 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 12:18:00.705094 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5178 12:18:00.711972 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5179 12:18:00.715442 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 12:18:00.718487 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 12:18:00.725285 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 12:18:00.728725 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 12:18:00.731810 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 12:18:00.738477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:18:00.741745 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 12:18:00.745038 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:18:00.748637 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 12:18:00.754966 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:18:00.758306 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 12:18:00.762026 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 12:18:00.768811 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:18:00.771638 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5193 12:18:00.774971 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5194 12:18:00.778666 Total UI for P1: 0, mck2ui 16
5195 12:18:00.781571 best dqsien dly found for B0: ( 1, 2, 24)
5196 12:18:00.788081 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 12:18:00.788174 Total UI for P1: 0, mck2ui 16
5198 12:18:00.794787 best dqsien dly found for B1: ( 1, 2, 28)
5199 12:18:00.798576 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5200 12:18:00.801526 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5201 12:18:00.801646
5202 12:18:00.805163 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5203 12:18:00.808578 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5204 12:18:00.811704 [Gating] SW calibration Done
5205 12:18:00.811794 ==
5206 12:18:00.814820 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 12:18:00.818457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 12:18:00.818553 ==
5209 12:18:00.821358 RX Vref Scan: 0
5210 12:18:00.821467
5211 12:18:00.821568 RX Vref 0 -> 0, step: 1
5212 12:18:00.821650
5213 12:18:00.824952 RX Delay -80 -> 252, step: 8
5214 12:18:00.831908 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5215 12:18:00.834784 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5216 12:18:00.838206 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5217 12:18:00.841262 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5218 12:18:00.844514 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5219 12:18:00.848102 iDelay=208, Bit 5, Center 103 (16 ~ 191) 176
5220 12:18:00.854632 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5221 12:18:00.857893 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5222 12:18:00.861181 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5223 12:18:00.864421 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5224 12:18:00.867801 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5225 12:18:00.874236 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5226 12:18:00.877677 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5227 12:18:00.880912 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5228 12:18:00.884194 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5229 12:18:00.887723 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5230 12:18:00.887827 ==
5231 12:18:00.890945 Dram Type= 6, Freq= 0, CH_0, rank 0
5232 12:18:00.897606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5233 12:18:00.897713 ==
5234 12:18:00.897809 DQS Delay:
5235 12:18:00.900734 DQS0 = 0, DQS1 = 0
5236 12:18:00.900839 DQM Delay:
5237 12:18:00.904112 DQM0 = 107, DQM1 = 91
5238 12:18:00.904214 DQ Delay:
5239 12:18:00.907581 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5240 12:18:00.910777 DQ4 =107, DQ5 =103, DQ6 =115, DQ7 =115
5241 12:18:00.914179 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5242 12:18:00.917868 DQ12 =91, DQ13 =91, DQ14 =103, DQ15 =103
5243 12:18:00.917973
5244 12:18:00.918069
5245 12:18:00.918158 ==
5246 12:18:00.920878 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 12:18:00.924140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 12:18:00.924252 ==
5249 12:18:00.927260
5250 12:18:00.927340
5251 12:18:00.927412 TX Vref Scan disable
5252 12:18:00.930500 == TX Byte 0 ==
5253 12:18:00.934359 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5254 12:18:00.937636 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5255 12:18:00.940654 == TX Byte 1 ==
5256 12:18:00.944029 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5257 12:18:00.947279 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5258 12:18:00.947387 ==
5259 12:18:00.950927 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 12:18:00.957527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 12:18:00.957609 ==
5262 12:18:00.957704
5263 12:18:00.957795
5264 12:18:00.957859 TX Vref Scan disable
5265 12:18:00.961652 == TX Byte 0 ==
5266 12:18:00.964832 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5267 12:18:00.968484 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5268 12:18:00.971557 == TX Byte 1 ==
5269 12:18:00.974882 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5270 12:18:00.978232 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5271 12:18:00.981584
5272 12:18:00.981680 [DATLAT]
5273 12:18:00.981749 Freq=933, CH0 RK0
5274 12:18:00.981812
5275 12:18:00.984801 DATLAT Default: 0xd
5276 12:18:00.984919 0, 0xFFFF, sum = 0
5277 12:18:00.988134 1, 0xFFFF, sum = 0
5278 12:18:00.988235 2, 0xFFFF, sum = 0
5279 12:18:00.991549 3, 0xFFFF, sum = 0
5280 12:18:00.991635 4, 0xFFFF, sum = 0
5281 12:18:00.995184 5, 0xFFFF, sum = 0
5282 12:18:00.998316 6, 0xFFFF, sum = 0
5283 12:18:00.998402 7, 0xFFFF, sum = 0
5284 12:18:01.001551 8, 0xFFFF, sum = 0
5285 12:18:01.001637 9, 0xFFFF, sum = 0
5286 12:18:01.004923 10, 0x0, sum = 1
5287 12:18:01.005018 11, 0x0, sum = 2
5288 12:18:01.005088 12, 0x0, sum = 3
5289 12:18:01.008113 13, 0x0, sum = 4
5290 12:18:01.008217 best_step = 11
5291 12:18:01.008287
5292 12:18:01.011785 ==
5293 12:18:01.011902 Dram Type= 6, Freq= 0, CH_0, rank 0
5294 12:18:01.018404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5295 12:18:01.018487 ==
5296 12:18:01.018554 RX Vref Scan: 1
5297 12:18:01.018617
5298 12:18:01.021450 RX Vref 0 -> 0, step: 1
5299 12:18:01.021561
5300 12:18:01.024826 RX Delay -53 -> 252, step: 4
5301 12:18:01.024946
5302 12:18:01.028348 Set Vref, RX VrefLevel [Byte0]: 57
5303 12:18:01.031642 [Byte1]: 48
5304 12:18:01.031728
5305 12:18:01.035079 Final RX Vref Byte 0 = 57 to rank0
5306 12:18:01.038405 Final RX Vref Byte 1 = 48 to rank0
5307 12:18:01.041371 Final RX Vref Byte 0 = 57 to rank1
5308 12:18:01.044892 Final RX Vref Byte 1 = 48 to rank1==
5309 12:18:01.048001 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 12:18:01.051683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 12:18:01.051776 ==
5312 12:18:01.055152 DQS Delay:
5313 12:18:01.055272 DQS0 = 0, DQS1 = 0
5314 12:18:01.058351 DQM Delay:
5315 12:18:01.058435 DQM0 = 108, DQM1 = 92
5316 12:18:01.058503 DQ Delay:
5317 12:18:01.061584 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5318 12:18:01.064700 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =116
5319 12:18:01.068317 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =90
5320 12:18:01.074712 DQ12 =94, DQ13 =96, DQ14 =102, DQ15 =100
5321 12:18:01.074815
5322 12:18:01.074884
5323 12:18:01.081284 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5324 12:18:01.084677 CH0 RK0: MR19=505, MR18=2723
5325 12:18:01.091331 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5326 12:18:01.091472
5327 12:18:01.094633 ----->DramcWriteLeveling(PI) begin...
5328 12:18:01.094718 ==
5329 12:18:01.097760 Dram Type= 6, Freq= 0, CH_0, rank 1
5330 12:18:01.101433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5331 12:18:01.101517 ==
5332 12:18:01.104926 Write leveling (Byte 0): 32 => 32
5333 12:18:01.108161 Write leveling (Byte 1): 31 => 31
5334 12:18:01.111313 DramcWriteLeveling(PI) end<-----
5335 12:18:01.111460
5336 12:18:01.111595 ==
5337 12:18:01.114434 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 12:18:01.118050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 12:18:01.118156 ==
5340 12:18:01.121758 [Gating] SW mode calibration
5341 12:18:01.128061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5342 12:18:01.134772 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5343 12:18:01.137692 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 12:18:01.141707 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 12:18:01.148086 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 12:18:01.151220 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 12:18:01.154805 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 12:18:01.161303 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 12:18:01.164570 0 14 24 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
5350 12:18:01.167959 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5351 12:18:01.174962 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5352 12:18:01.178277 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 12:18:01.181084 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 12:18:01.188196 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 12:18:01.191482 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 12:18:01.194922 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 12:18:01.201727 0 15 24 | B1->B0 | 2727 2f2f | 0 1 | (0 0) (0 0)
5358 12:18:01.205115 0 15 28 | B1->B0 | 3a3a 4040 | 1 0 | (0 0) (0 0)
5359 12:18:01.208260 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 12:18:01.215270 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 12:18:01.218026 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 12:18:01.221308 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 12:18:01.227931 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 12:18:01.231591 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 12:18:01.234855 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 12:18:01.241511 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5367 12:18:01.244814 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 12:18:01.247925 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 12:18:01.255080 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 12:18:01.258094 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 12:18:01.261169 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 12:18:01.267828 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 12:18:01.271067 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 12:18:01.274567 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 12:18:01.277744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 12:18:01.284250 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 12:18:01.287402 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 12:18:01.290916 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 12:18:01.297495 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 12:18:01.301191 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 12:18:01.304299 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5382 12:18:01.310994 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5383 12:18:01.314575 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 12:18:01.317532 Total UI for P1: 0, mck2ui 16
5385 12:18:01.320863 best dqsien dly found for B0: ( 1, 2, 26)
5386 12:18:01.324130 Total UI for P1: 0, mck2ui 16
5387 12:18:01.327516 best dqsien dly found for B1: ( 1, 2, 26)
5388 12:18:01.330818 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5389 12:18:01.334462 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5390 12:18:01.334727
5391 12:18:01.337327 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5392 12:18:01.340657 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5393 12:18:01.343994 [Gating] SW calibration Done
5394 12:18:01.344236 ==
5395 12:18:01.347425 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 12:18:01.350765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 12:18:01.354127 ==
5398 12:18:01.354393 RX Vref Scan: 0
5399 12:18:01.354606
5400 12:18:01.357480 RX Vref 0 -> 0, step: 1
5401 12:18:01.357723
5402 12:18:01.360637 RX Delay -80 -> 252, step: 8
5403 12:18:01.363978 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5404 12:18:01.367427 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5405 12:18:01.370959 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5406 12:18:01.374217 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5407 12:18:01.377515 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5408 12:18:01.383972 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5409 12:18:01.387173 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5410 12:18:01.390542 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5411 12:18:01.393919 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5412 12:18:01.397402 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5413 12:18:01.400576 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5414 12:18:01.407511 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5415 12:18:01.410668 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5416 12:18:01.413936 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5417 12:18:01.417327 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5418 12:18:01.420681 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5419 12:18:01.421047 ==
5420 12:18:01.423777 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 12:18:01.430874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 12:18:01.431328 ==
5423 12:18:01.431673 DQS Delay:
5424 12:18:01.434351 DQS0 = 0, DQS1 = 0
5425 12:18:01.434827 DQM Delay:
5426 12:18:01.435204 DQM0 = 105, DQM1 = 90
5427 12:18:01.437612 DQ Delay:
5428 12:18:01.440778 DQ0 =103, DQ1 =111, DQ2 =99, DQ3 =99
5429 12:18:01.444037 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5430 12:18:01.447246 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5431 12:18:01.450566 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5432 12:18:01.451027
5433 12:18:01.451371
5434 12:18:01.451713 ==
5435 12:18:01.454170 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 12:18:01.457295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 12:18:01.457729 ==
5438 12:18:01.458067
5439 12:18:01.458402
5440 12:18:01.460692 TX Vref Scan disable
5441 12:18:01.463908 == TX Byte 0 ==
5442 12:18:01.467469 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5443 12:18:01.470467 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5444 12:18:01.473882 == TX Byte 1 ==
5445 12:18:01.477761 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5446 12:18:01.480502 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5447 12:18:01.481139 ==
5448 12:18:01.483663 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 12:18:01.487145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 12:18:01.490720 ==
5451 12:18:01.491316
5452 12:18:01.491872
5453 12:18:01.492429 TX Vref Scan disable
5454 12:18:01.493837 == TX Byte 0 ==
5455 12:18:01.497316 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5456 12:18:01.500532 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5457 12:18:01.503837 == TX Byte 1 ==
5458 12:18:01.507478 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5459 12:18:01.513974 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5460 12:18:01.514554
5461 12:18:01.515168 [DATLAT]
5462 12:18:01.515733 Freq=933, CH0 RK1
5463 12:18:01.516317
5464 12:18:01.517391 DATLAT Default: 0xb
5465 12:18:01.517943 0, 0xFFFF, sum = 0
5466 12:18:01.520965 1, 0xFFFF, sum = 0
5467 12:18:01.521617 2, 0xFFFF, sum = 0
5468 12:18:01.523890 3, 0xFFFF, sum = 0
5469 12:18:01.524428 4, 0xFFFF, sum = 0
5470 12:18:01.527563 5, 0xFFFF, sum = 0
5471 12:18:01.531106 6, 0xFFFF, sum = 0
5472 12:18:01.531534 7, 0xFFFF, sum = 0
5473 12:18:01.534259 8, 0xFFFF, sum = 0
5474 12:18:01.534711 9, 0xFFFF, sum = 0
5475 12:18:01.537629 10, 0x0, sum = 1
5476 12:18:01.538057 11, 0x0, sum = 2
5477 12:18:01.538402 12, 0x0, sum = 3
5478 12:18:01.540459 13, 0x0, sum = 4
5479 12:18:01.541056 best_step = 11
5480 12:18:01.541506
5481 12:18:01.543852 ==
5482 12:18:01.544481 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 12:18:01.550788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 12:18:01.551222 ==
5485 12:18:01.551571 RX Vref Scan: 0
5486 12:18:01.551892
5487 12:18:01.553861 RX Vref 0 -> 0, step: 1
5488 12:18:01.554294
5489 12:18:01.557342 RX Delay -53 -> 252, step: 4
5490 12:18:01.560490 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5491 12:18:01.567219 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5492 12:18:01.570937 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5493 12:18:01.573755 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5494 12:18:01.577658 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5495 12:18:01.580792 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5496 12:18:01.584174 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5497 12:18:01.591149 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5498 12:18:01.594019 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5499 12:18:01.597522 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5500 12:18:01.600767 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5501 12:18:01.604012 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5502 12:18:01.610582 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5503 12:18:01.613803 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5504 12:18:01.617421 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5505 12:18:01.620469 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5506 12:18:01.620856 ==
5507 12:18:01.623796 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 12:18:01.627582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 12:18:01.630592 ==
5510 12:18:01.631114 DQS Delay:
5511 12:18:01.631492 DQS0 = 0, DQS1 = 0
5512 12:18:01.634056 DQM Delay:
5513 12:18:01.634537 DQM0 = 104, DQM1 = 92
5514 12:18:01.637474 DQ Delay:
5515 12:18:01.640558 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =100
5516 12:18:01.643949 DQ4 =104, DQ5 =98, DQ6 =114, DQ7 =110
5517 12:18:01.647407 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =90
5518 12:18:01.650334 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5519 12:18:01.650803
5520 12:18:01.651177
5521 12:18:01.657223 [DQSOSCAuto] RK1, (LSB)MR18= 0x2608, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5522 12:18:01.660623 CH0 RK1: MR19=505, MR18=2608
5523 12:18:01.666838 CH0_RK1: MR19=0x505, MR18=0x2608, DQSOSC=409, MR23=63, INC=64, DEC=43
5524 12:18:01.670545 [RxdqsGatingPostProcess] freq 933
5525 12:18:01.676817 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5526 12:18:01.677361 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 12:18:01.679983 best DQS1 dly(2T, 0.5T) = (0, 10)
5528 12:18:01.683267 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 12:18:01.686785 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5530 12:18:01.690321 best DQS0 dly(2T, 0.5T) = (0, 10)
5531 12:18:01.693509 best DQS1 dly(2T, 0.5T) = (0, 10)
5532 12:18:01.696624 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5533 12:18:01.699705 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5534 12:18:01.703061 Pre-setting of DQS Precalculation
5535 12:18:01.706366 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5536 12:18:01.709798 ==
5537 12:18:01.713073 Dram Type= 6, Freq= 0, CH_1, rank 0
5538 12:18:01.716242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5539 12:18:01.716317 ==
5540 12:18:01.719652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5541 12:18:01.726447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5542 12:18:01.730251 [CA 0] Center 37 (7~67) winsize 61
5543 12:18:01.733652 [CA 1] Center 37 (7~68) winsize 62
5544 12:18:01.736625 [CA 2] Center 35 (5~65) winsize 61
5545 12:18:01.740018 [CA 3] Center 34 (4~65) winsize 62
5546 12:18:01.743166 [CA 4] Center 34 (4~65) winsize 62
5547 12:18:01.746619 [CA 5] Center 34 (4~64) winsize 61
5548 12:18:01.746720
5549 12:18:01.750014 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5550 12:18:01.750086
5551 12:18:01.753166 [CATrainingPosCal] consider 1 rank data
5552 12:18:01.756828 u2DelayCellTimex100 = 270/100 ps
5553 12:18:01.759835 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5554 12:18:01.766859 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5555 12:18:01.770056 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5556 12:18:01.773404 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5557 12:18:01.776606 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5558 12:18:01.779824 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5559 12:18:01.779907
5560 12:18:01.783799 CA PerBit enable=1, Macro0, CA PI delay=34
5561 12:18:01.783882
5562 12:18:01.786702 [CBTSetCACLKResult] CA Dly = 34
5563 12:18:01.786785 CS Dly: 6 (0~37)
5564 12:18:01.790057 ==
5565 12:18:01.792847 Dram Type= 6, Freq= 0, CH_1, rank 1
5566 12:18:01.796708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 12:18:01.796791 ==
5568 12:18:01.800080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 12:18:01.806516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5570 12:18:01.809870 [CA 0] Center 37 (7~68) winsize 62
5571 12:18:01.813223 [CA 1] Center 37 (7~68) winsize 62
5572 12:18:01.817057 [CA 2] Center 35 (5~66) winsize 62
5573 12:18:01.819765 [CA 3] Center 35 (5~65) winsize 61
5574 12:18:01.823045 [CA 4] Center 35 (5~65) winsize 61
5575 12:18:01.826541 [CA 5] Center 34 (4~64) winsize 61
5576 12:18:01.826625
5577 12:18:01.829908 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5578 12:18:01.830016
5579 12:18:01.833275 [CATrainingPosCal] consider 2 rank data
5580 12:18:01.836486 u2DelayCellTimex100 = 270/100 ps
5581 12:18:01.839763 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5582 12:18:01.846823 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5583 12:18:01.849701 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5584 12:18:01.853052 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5585 12:18:01.856619 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5586 12:18:01.859884 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5587 12:18:01.859966
5588 12:18:01.863591 CA PerBit enable=1, Macro0, CA PI delay=34
5589 12:18:01.863675
5590 12:18:01.866619 [CBTSetCACLKResult] CA Dly = 34
5591 12:18:01.866702 CS Dly: 7 (0~39)
5592 12:18:01.866767
5593 12:18:01.869631 ----->DramcWriteLeveling(PI) begin...
5594 12:18:01.873427 ==
5595 12:18:01.876325 Dram Type= 6, Freq= 0, CH_1, rank 0
5596 12:18:01.879717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5597 12:18:01.879843 ==
5598 12:18:01.883317 Write leveling (Byte 0): 26 => 26
5599 12:18:01.886411 Write leveling (Byte 1): 27 => 27
5600 12:18:01.890286 DramcWriteLeveling(PI) end<-----
5601 12:18:01.890419
5602 12:18:01.890492 ==
5603 12:18:01.892860 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 12:18:01.896370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 12:18:01.896510 ==
5606 12:18:01.899718 [Gating] SW mode calibration
5607 12:18:01.906299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5608 12:18:01.912639 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5609 12:18:01.916207 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 12:18:01.919887 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 12:18:01.922998 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 12:18:01.929931 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 12:18:01.933077 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 12:18:01.936258 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5615 12:18:01.942695 0 14 24 | B1->B0 | 3131 3131 | 0 0 | (0 1) (0 1)
5616 12:18:01.946600 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5617 12:18:01.949830 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 12:18:01.956428 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 12:18:01.959832 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 12:18:01.963078 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 12:18:01.969689 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 12:18:01.972863 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 12:18:01.976211 0 15 24 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
5624 12:18:01.982763 0 15 28 | B1->B0 | 4444 4545 | 0 0 | (0 0) (0 0)
5625 12:18:01.986301 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 12:18:01.989652 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 12:18:01.996249 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 12:18:01.999507 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 12:18:02.002702 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 12:18:02.009361 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 12:18:02.013225 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5632 12:18:02.016055 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5633 12:18:02.022798 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:18:02.025880 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 12:18:02.029118 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:18:02.035924 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:18:02.039477 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:18:02.042583 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:18:02.049148 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:18:02.052625 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:18:02.055998 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:18:02.059249 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:18:02.065936 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 12:18:02.069384 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 12:18:02.072710 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:18:02.079272 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:18:02.082974 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5648 12:18:02.086023 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 12:18:02.089529 Total UI for P1: 0, mck2ui 16
5650 12:18:02.092628 best dqsien dly found for B0: ( 1, 2, 24)
5651 12:18:02.096054 Total UI for P1: 0, mck2ui 16
5652 12:18:02.099397 best dqsien dly found for B1: ( 1, 2, 24)
5653 12:18:02.102766 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5654 12:18:02.106337 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5655 12:18:02.106432
5656 12:18:02.112803 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5657 12:18:02.116098 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5658 12:18:02.116209 [Gating] SW calibration Done
5659 12:18:02.119114 ==
5660 12:18:02.122786 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 12:18:02.126139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 12:18:02.126278 ==
5663 12:18:02.126389 RX Vref Scan: 0
5664 12:18:02.126502
5665 12:18:02.129237 RX Vref 0 -> 0, step: 1
5666 12:18:02.129460
5667 12:18:02.132515 RX Delay -80 -> 252, step: 8
5668 12:18:02.136076 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5669 12:18:02.139067 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5670 12:18:02.142457 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5671 12:18:02.149272 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5672 12:18:02.152577 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5673 12:18:02.155859 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5674 12:18:02.159271 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5675 12:18:02.162877 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5676 12:18:02.165848 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5677 12:18:02.172380 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5678 12:18:02.175873 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5679 12:18:02.179253 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5680 12:18:02.182345 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5681 12:18:02.185691 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5682 12:18:02.188887 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5683 12:18:02.195850 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5684 12:18:02.195930 ==
5685 12:18:02.199095 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 12:18:02.202689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 12:18:02.202772 ==
5688 12:18:02.202835 DQS Delay:
5689 12:18:02.205818 DQS0 = 0, DQS1 = 0
5690 12:18:02.205889 DQM Delay:
5691 12:18:02.209119 DQM0 = 102, DQM1 = 94
5692 12:18:02.209202 DQ Delay:
5693 12:18:02.212252 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5694 12:18:02.215527 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5695 12:18:02.219566 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5696 12:18:02.222437 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5697 12:18:02.222572
5698 12:18:02.222639
5699 12:18:02.222700 ==
5700 12:18:02.225628 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:18:02.228842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:18:02.232337 ==
5703 12:18:02.232464
5704 12:18:02.232567
5705 12:18:02.232664 TX Vref Scan disable
5706 12:18:02.235420 == TX Byte 0 ==
5707 12:18:02.238665 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5708 12:18:02.242331 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5709 12:18:02.245688 == TX Byte 1 ==
5710 12:18:02.248830 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5711 12:18:02.252416 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5712 12:18:02.252522 ==
5713 12:18:02.255501 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 12:18:02.261989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 12:18:02.262075 ==
5716 12:18:02.262158
5717 12:18:02.262238
5718 12:18:02.262315 TX Vref Scan disable
5719 12:18:02.266303 == TX Byte 0 ==
5720 12:18:02.269693 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5721 12:18:02.276331 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5722 12:18:02.276431 == TX Byte 1 ==
5723 12:18:02.279760 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 12:18:02.286463 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 12:18:02.286549
5726 12:18:02.286633 [DATLAT]
5727 12:18:02.286722 Freq=933, CH1 RK0
5728 12:18:02.286801
5729 12:18:02.289947 DATLAT Default: 0xd
5730 12:18:02.290032 0, 0xFFFF, sum = 0
5731 12:18:02.293385 1, 0xFFFF, sum = 0
5732 12:18:02.293503 2, 0xFFFF, sum = 0
5733 12:18:02.296209 3, 0xFFFF, sum = 0
5734 12:18:02.299562 4, 0xFFFF, sum = 0
5735 12:18:02.299649 5, 0xFFFF, sum = 0
5736 12:18:02.303197 6, 0xFFFF, sum = 0
5737 12:18:02.303283 7, 0xFFFF, sum = 0
5738 12:18:02.306555 8, 0xFFFF, sum = 0
5739 12:18:02.306649 9, 0xFFFF, sum = 0
5740 12:18:02.309952 10, 0x0, sum = 1
5741 12:18:02.310039 11, 0x0, sum = 2
5742 12:18:02.310134 12, 0x0, sum = 3
5743 12:18:02.312685 13, 0x0, sum = 4
5744 12:18:02.312762 best_step = 11
5745 12:18:02.312861
5746 12:18:02.316299 ==
5747 12:18:02.319794 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 12:18:02.323216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 12:18:02.323303 ==
5750 12:18:02.323388 RX Vref Scan: 1
5751 12:18:02.323496
5752 12:18:02.326298 RX Vref 0 -> 0, step: 1
5753 12:18:02.326399
5754 12:18:02.329547 RX Delay -53 -> 252, step: 4
5755 12:18:02.329633
5756 12:18:02.332851 Set Vref, RX VrefLevel [Byte0]: 52
5757 12:18:02.336254 [Byte1]: 50
5758 12:18:02.336340
5759 12:18:02.339678 Final RX Vref Byte 0 = 52 to rank0
5760 12:18:02.343233 Final RX Vref Byte 1 = 50 to rank0
5761 12:18:02.346577 Final RX Vref Byte 0 = 52 to rank1
5762 12:18:02.349919 Final RX Vref Byte 1 = 50 to rank1==
5763 12:18:02.353237 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 12:18:02.356388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 12:18:02.356484 ==
5766 12:18:02.360037 DQS Delay:
5767 12:18:02.360122 DQS0 = 0, DQS1 = 0
5768 12:18:02.362824 DQM Delay:
5769 12:18:02.362909 DQM0 = 104, DQM1 = 96
5770 12:18:02.362995 DQ Delay:
5771 12:18:02.366509 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =102
5772 12:18:02.369922 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =100
5773 12:18:02.373228 DQ8 =88, DQ9 =84, DQ10 =102, DQ11 =90
5774 12:18:02.379726 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =102
5775 12:18:02.379837
5776 12:18:02.379942
5777 12:18:02.386427 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5778 12:18:02.389546 CH1 RK0: MR19=505, MR18=1B33
5779 12:18:02.396392 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5780 12:18:02.396486
5781 12:18:02.399745 ----->DramcWriteLeveling(PI) begin...
5782 12:18:02.399840 ==
5783 12:18:02.402834 Dram Type= 6, Freq= 0, CH_1, rank 1
5784 12:18:02.406101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 12:18:02.406211 ==
5786 12:18:02.409351 Write leveling (Byte 0): 26 => 26
5787 12:18:02.412816 Write leveling (Byte 1): 29 => 29
5788 12:18:02.416391 DramcWriteLeveling(PI) end<-----
5789 12:18:02.416830
5790 12:18:02.417319 ==
5791 12:18:02.419552 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 12:18:02.423043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 12:18:02.423482 ==
5794 12:18:02.426408 [Gating] SW mode calibration
5795 12:18:02.433121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5796 12:18:02.439804 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5797 12:18:02.443369 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5798 12:18:02.449592 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 12:18:02.453051 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 12:18:02.456299 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 12:18:02.462977 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 12:18:02.466661 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 12:18:02.469557 0 14 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 0)
5804 12:18:02.476358 0 14 28 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 0)
5805 12:18:02.479581 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 12:18:02.482968 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 12:18:02.486525 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 12:18:02.492737 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 12:18:02.496020 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 12:18:02.499356 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 12:18:02.506248 0 15 24 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
5812 12:18:02.509567 0 15 28 | B1->B0 | 4444 4141 | 0 0 | (0 0) (0 0)
5813 12:18:02.512836 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5814 12:18:02.519419 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 12:18:02.522810 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 12:18:02.525956 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 12:18:02.532899 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 12:18:02.536293 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 12:18:02.539117 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5820 12:18:02.546048 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 12:18:02.549037 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 12:18:02.552690 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 12:18:02.559467 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 12:18:02.562694 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 12:18:02.566417 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 12:18:02.572766 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:18:02.576099 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 12:18:02.579348 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 12:18:02.585740 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 12:18:02.589019 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 12:18:02.592702 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 12:18:02.599385 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 12:18:02.602298 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 12:18:02.605839 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 12:18:02.612396 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5836 12:18:02.615637 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5837 12:18:02.618979 Total UI for P1: 0, mck2ui 16
5838 12:18:02.622243 best dqsien dly found for B1: ( 1, 2, 24)
5839 12:18:02.625742 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 12:18:02.629385 Total UI for P1: 0, mck2ui 16
5841 12:18:02.632587 best dqsien dly found for B0: ( 1, 2, 28)
5842 12:18:02.635740 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5843 12:18:02.638868 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5844 12:18:02.639289
5845 12:18:02.642141 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5846 12:18:02.649234 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5847 12:18:02.649853 [Gating] SW calibration Done
5848 12:18:02.650360 ==
5849 12:18:02.652272 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 12:18:02.658574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 12:18:02.659060 ==
5852 12:18:02.659574 RX Vref Scan: 0
5853 12:18:02.660063
5854 12:18:02.662066 RX Vref 0 -> 0, step: 1
5855 12:18:02.662682
5856 12:18:02.665176 RX Delay -80 -> 252, step: 8
5857 12:18:02.668437 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5858 12:18:02.672295 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5859 12:18:02.675349 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5860 12:18:02.678560 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5861 12:18:02.685265 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5862 12:18:02.688400 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5863 12:18:02.692015 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5864 12:18:02.695312 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5865 12:18:02.698582 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5866 12:18:02.701995 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5867 12:18:02.708827 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5868 12:18:02.712006 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5869 12:18:02.714997 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5870 12:18:02.718460 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5871 12:18:02.721719 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5872 12:18:02.724896 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5873 12:18:02.728160 ==
5874 12:18:02.731586 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 12:18:02.734903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 12:18:02.734989 ==
5877 12:18:02.735058 DQS Delay:
5878 12:18:02.738139 DQS0 = 0, DQS1 = 0
5879 12:18:02.738231 DQM Delay:
5880 12:18:02.741526 DQM0 = 102, DQM1 = 95
5881 12:18:02.741625 DQ Delay:
5882 12:18:02.744715 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5883 12:18:02.748349 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =99
5884 12:18:02.751636 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5885 12:18:02.755002 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5886 12:18:02.755119
5887 12:18:02.755212
5888 12:18:02.755297 ==
5889 12:18:02.758259 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 12:18:02.761619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 12:18:02.761763 ==
5892 12:18:02.761885
5893 12:18:02.764756
5894 12:18:02.764897 TX Vref Scan disable
5895 12:18:02.768236 == TX Byte 0 ==
5896 12:18:02.771623 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5897 12:18:02.774882 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5898 12:18:02.778506 == TX Byte 1 ==
5899 12:18:02.781858 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5900 12:18:02.785241 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5901 12:18:02.785328 ==
5902 12:18:02.788453 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 12:18:02.794578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 12:18:02.794663 ==
5905 12:18:02.794731
5906 12:18:02.794793
5907 12:18:02.794852 TX Vref Scan disable
5908 12:18:02.799003 == TX Byte 0 ==
5909 12:18:02.802303 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5910 12:18:02.805603 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5911 12:18:02.808938 == TX Byte 1 ==
5912 12:18:02.812093 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5913 12:18:02.815505 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5914 12:18:02.819018
5915 12:18:02.819102 [DATLAT]
5916 12:18:02.819169 Freq=933, CH1 RK1
5917 12:18:02.819231
5918 12:18:02.822285 DATLAT Default: 0xb
5919 12:18:02.822372 0, 0xFFFF, sum = 0
5920 12:18:02.825335 1, 0xFFFF, sum = 0
5921 12:18:02.825475 2, 0xFFFF, sum = 0
5922 12:18:02.828600 3, 0xFFFF, sum = 0
5923 12:18:02.832165 4, 0xFFFF, sum = 0
5924 12:18:02.832277 5, 0xFFFF, sum = 0
5925 12:18:02.835483 6, 0xFFFF, sum = 0
5926 12:18:02.835599 7, 0xFFFF, sum = 0
5927 12:18:02.839038 8, 0xFFFF, sum = 0
5928 12:18:02.839148 9, 0xFFFF, sum = 0
5929 12:18:02.842030 10, 0x0, sum = 1
5930 12:18:02.842155 11, 0x0, sum = 2
5931 12:18:02.845340 12, 0x0, sum = 3
5932 12:18:02.845426 13, 0x0, sum = 4
5933 12:18:02.845495 best_step = 11
5934 12:18:02.845557
5935 12:18:02.848897 ==
5936 12:18:02.849028 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 12:18:02.855298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 12:18:02.855385 ==
5939 12:18:02.855513 RX Vref Scan: 0
5940 12:18:02.855611
5941 12:18:02.858876 RX Vref 0 -> 0, step: 1
5942 12:18:02.858961
5943 12:18:02.862020 RX Delay -53 -> 252, step: 4
5944 12:18:02.865223 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5945 12:18:02.871925 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5946 12:18:02.875045 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5947 12:18:02.878541 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5948 12:18:02.881848 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5949 12:18:02.885625 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5950 12:18:02.892016 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5951 12:18:02.895218 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5952 12:18:02.898361 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5953 12:18:02.901551 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5954 12:18:02.904999 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5955 12:18:02.908322 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5956 12:18:02.915011 iDelay=199, Bit 12, Center 110 (27 ~ 194) 168
5957 12:18:02.918190 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5958 12:18:02.921637 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5959 12:18:02.925177 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5960 12:18:02.925287 ==
5961 12:18:02.928375 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 12:18:02.935328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 12:18:02.935444 ==
5964 12:18:02.935542 DQS Delay:
5965 12:18:02.938289 DQS0 = 0, DQS1 = 0
5966 12:18:02.938403 DQM Delay:
5967 12:18:02.938507 DQM0 = 106, DQM1 = 98
5968 12:18:02.941654 DQ Delay:
5969 12:18:02.945168 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =104
5970 12:18:02.948303 DQ4 =108, DQ5 =116, DQ6 =114, DQ7 =102
5971 12:18:02.951593 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5972 12:18:02.955130 DQ12 =110, DQ13 =104, DQ14 =106, DQ15 =106
5973 12:18:02.955244
5974 12:18:02.955340
5975 12:18:02.962096 [DQSOSCAuto] RK1, (LSB)MR18= 0x2300, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5976 12:18:02.965010 CH1 RK1: MR19=505, MR18=2300
5977 12:18:02.972011 CH1_RK1: MR19=0x505, MR18=0x2300, DQSOSC=410, MR23=63, INC=64, DEC=42
5978 12:18:02.975004 [RxdqsGatingPostProcess] freq 933
5979 12:18:02.981532 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5980 12:18:02.985080 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 12:18:02.985165 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 12:18:02.988375 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 12:18:02.991409 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 12:18:02.995111 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 12:18:02.998556 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 12:18:03.001991 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 12:18:03.004843 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 12:18:03.008426 Pre-setting of DQS Precalculation
5989 12:18:03.015391 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5990 12:18:03.021733 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5991 12:18:03.028105 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5992 12:18:03.028232
5993 12:18:03.028331
5994 12:18:03.031362 [Calibration Summary] 1866 Mbps
5995 12:18:03.031501 CH 0, Rank 0
5996 12:18:03.035005 SW Impedance : PASS
5997 12:18:03.037988 DUTY Scan : NO K
5998 12:18:03.038148 ZQ Calibration : PASS
5999 12:18:03.041654 Jitter Meter : NO K
6000 12:18:03.044750 CBT Training : PASS
6001 12:18:03.044940 Write leveling : PASS
6002 12:18:03.048074 RX DQS gating : PASS
6003 12:18:03.051770 RX DQ/DQS(RDDQC) : PASS
6004 12:18:03.052156 TX DQ/DQS : PASS
6005 12:18:03.054711 RX DATLAT : PASS
6006 12:18:03.055025 RX DQ/DQS(Engine): PASS
6007 12:18:03.058513 TX OE : NO K
6008 12:18:03.058742 All Pass.
6009 12:18:03.058931
6010 12:18:03.061446 CH 0, Rank 1
6011 12:18:03.061694 SW Impedance : PASS
6012 12:18:03.064693 DUTY Scan : NO K
6013 12:18:03.067993 ZQ Calibration : PASS
6014 12:18:03.068303 Jitter Meter : NO K
6015 12:18:03.071371 CBT Training : PASS
6016 12:18:03.074626 Write leveling : PASS
6017 12:18:03.075028 RX DQS gating : PASS
6018 12:18:03.077720 RX DQ/DQS(RDDQC) : PASS
6019 12:18:03.081332 TX DQ/DQS : PASS
6020 12:18:03.081416 RX DATLAT : PASS
6021 12:18:03.084492 RX DQ/DQS(Engine): PASS
6022 12:18:03.087913 TX OE : NO K
6023 12:18:03.087998 All Pass.
6024 12:18:03.088065
6025 12:18:03.088127 CH 1, Rank 0
6026 12:18:03.091592 SW Impedance : PASS
6027 12:18:03.094494 DUTY Scan : NO K
6028 12:18:03.094578 ZQ Calibration : PASS
6029 12:18:03.097967 Jitter Meter : NO K
6030 12:18:03.101042 CBT Training : PASS
6031 12:18:03.101139 Write leveling : PASS
6032 12:18:03.104459 RX DQS gating : PASS
6033 12:18:03.104556 RX DQ/DQS(RDDQC) : PASS
6034 12:18:03.108168 TX DQ/DQS : PASS
6035 12:18:03.111351 RX DATLAT : PASS
6036 12:18:03.111466 RX DQ/DQS(Engine): PASS
6037 12:18:03.114464 TX OE : NO K
6038 12:18:03.114579 All Pass.
6039 12:18:03.114671
6040 12:18:03.118164 CH 1, Rank 1
6041 12:18:03.118330 SW Impedance : PASS
6042 12:18:03.121348 DUTY Scan : NO K
6043 12:18:03.124640 ZQ Calibration : PASS
6044 12:18:03.124742 Jitter Meter : NO K
6045 12:18:03.127623 CBT Training : PASS
6046 12:18:03.130889 Write leveling : PASS
6047 12:18:03.130974 RX DQS gating : PASS
6048 12:18:03.134279 RX DQ/DQS(RDDQC) : PASS
6049 12:18:03.137623 TX DQ/DQS : PASS
6050 12:18:03.137708 RX DATLAT : PASS
6051 12:18:03.141054 RX DQ/DQS(Engine): PASS
6052 12:18:03.144299 TX OE : NO K
6053 12:18:03.144384 All Pass.
6054 12:18:03.144451
6055 12:18:03.144514 DramC Write-DBI off
6056 12:18:03.147885 PER_BANK_REFRESH: Hybrid Mode
6057 12:18:03.151096 TX_TRACKING: ON
6058 12:18:03.157811 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6059 12:18:03.160824 [FAST_K] Save calibration result to emmc
6060 12:18:03.167663 dramc_set_vcore_voltage set vcore to 650000
6061 12:18:03.167748 Read voltage for 400, 6
6062 12:18:03.170982 Vio18 = 0
6063 12:18:03.171068 Vcore = 650000
6064 12:18:03.171134 Vdram = 0
6065 12:18:03.173934 Vddq = 0
6066 12:18:03.174019 Vmddr = 0
6067 12:18:03.177578 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6068 12:18:03.184424 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6069 12:18:03.187654 MEM_TYPE=3, freq_sel=20
6070 12:18:03.187736 sv_algorithm_assistance_LP4_800
6071 12:18:03.194061 ============ PULL DRAM RESETB DOWN ============
6072 12:18:03.197337 ========== PULL DRAM RESETB DOWN end =========
6073 12:18:03.200632 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6074 12:18:03.204374 ===================================
6075 12:18:03.207768 LPDDR4 DRAM CONFIGURATION
6076 12:18:03.211371 ===================================
6077 12:18:03.214556 EX_ROW_EN[0] = 0x0
6078 12:18:03.214967 EX_ROW_EN[1] = 0x0
6079 12:18:03.218040 LP4Y_EN = 0x0
6080 12:18:03.218615 WORK_FSP = 0x0
6081 12:18:03.221084 WL = 0x2
6082 12:18:03.221562 RL = 0x2
6083 12:18:03.224215 BL = 0x2
6084 12:18:03.224702 RPST = 0x0
6085 12:18:03.228082 RD_PRE = 0x0
6086 12:18:03.228558 WR_PRE = 0x1
6087 12:18:03.231205 WR_PST = 0x0
6088 12:18:03.231677 DBI_WR = 0x0
6089 12:18:03.234695 DBI_RD = 0x0
6090 12:18:03.235184 OTF = 0x1
6091 12:18:03.237867 ===================================
6092 12:18:03.241203 ===================================
6093 12:18:03.244561 ANA top config
6094 12:18:03.247401 ===================================
6095 12:18:03.251107 DLL_ASYNC_EN = 0
6096 12:18:03.251592 ALL_SLAVE_EN = 1
6097 12:18:03.254277 NEW_RANK_MODE = 1
6098 12:18:03.257537 DLL_IDLE_MODE = 1
6099 12:18:03.260601 LP45_APHY_COMB_EN = 1
6100 12:18:03.264280 TX_ODT_DIS = 1
6101 12:18:03.264849 NEW_8X_MODE = 1
6102 12:18:03.267593 ===================================
6103 12:18:03.271243 ===================================
6104 12:18:03.274109 data_rate = 800
6105 12:18:03.277506 CKR = 1
6106 12:18:03.280564 DQ_P2S_RATIO = 4
6107 12:18:03.284116 ===================================
6108 12:18:03.287273 CA_P2S_RATIO = 4
6109 12:18:03.290716 DQ_CA_OPEN = 0
6110 12:18:03.291140 DQ_SEMI_OPEN = 1
6111 12:18:03.294133 CA_SEMI_OPEN = 1
6112 12:18:03.297584 CA_FULL_RATE = 0
6113 12:18:03.300708 DQ_CKDIV4_EN = 0
6114 12:18:03.304031 CA_CKDIV4_EN = 1
6115 12:18:03.307323 CA_PREDIV_EN = 0
6116 12:18:03.307803 PH8_DLY = 0
6117 12:18:03.310825 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6118 12:18:03.314062 DQ_AAMCK_DIV = 0
6119 12:18:03.317321 CA_AAMCK_DIV = 0
6120 12:18:03.320889 CA_ADMCK_DIV = 4
6121 12:18:03.323925 DQ_TRACK_CA_EN = 0
6122 12:18:03.324552 CA_PICK = 800
6123 12:18:03.327099 CA_MCKIO = 400
6124 12:18:03.330463 MCKIO_SEMI = 400
6125 12:18:03.333734 PLL_FREQ = 3016
6126 12:18:03.337139 DQ_UI_PI_RATIO = 32
6127 12:18:03.340594 CA_UI_PI_RATIO = 32
6128 12:18:03.344123 ===================================
6129 12:18:03.347204 ===================================
6130 12:18:03.347681 memory_type:LPDDR4
6131 12:18:03.350790 GP_NUM : 10
6132 12:18:03.353680 SRAM_EN : 1
6133 12:18:03.354202 MD32_EN : 0
6134 12:18:03.357316 ===================================
6135 12:18:03.360511 [ANA_INIT] >>>>>>>>>>>>>>
6136 12:18:03.364221 <<<<<< [CONFIGURE PHASE]: ANA_TX
6137 12:18:03.367000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6138 12:18:03.370358 ===================================
6139 12:18:03.373755 data_rate = 800,PCW = 0X7400
6140 12:18:03.377373 ===================================
6141 12:18:03.380460 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6142 12:18:03.384172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 12:18:03.397020 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 12:18:03.400604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6145 12:18:03.404299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6146 12:18:03.407141 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6147 12:18:03.410426 [ANA_INIT] flow start
6148 12:18:03.410850 [ANA_INIT] PLL >>>>>>>>
6149 12:18:03.413720 [ANA_INIT] PLL <<<<<<<<
6150 12:18:03.417197 [ANA_INIT] MIDPI >>>>>>>>
6151 12:18:03.420649 [ANA_INIT] MIDPI <<<<<<<<
6152 12:18:03.421281 [ANA_INIT] DLL >>>>>>>>
6153 12:18:03.423795 [ANA_INIT] flow end
6154 12:18:03.427056 ============ LP4 DIFF to SE enter ============
6155 12:18:03.430494 ============ LP4 DIFF to SE exit ============
6156 12:18:03.433637 [ANA_INIT] <<<<<<<<<<<<<
6157 12:18:03.437028 [Flow] Enable top DCM control >>>>>
6158 12:18:03.440564 [Flow] Enable top DCM control <<<<<
6159 12:18:03.443714 Enable DLL master slave shuffle
6160 12:18:03.450380 ==============================================================
6161 12:18:03.450810 Gating Mode config
6162 12:18:03.457254 ==============================================================
6163 12:18:03.457685 Config description:
6164 12:18:03.467358 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6165 12:18:03.473766 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6166 12:18:03.480402 SELPH_MODE 0: By rank 1: By Phase
6167 12:18:03.483576 ==============================================================
6168 12:18:03.486862 GAT_TRACK_EN = 0
6169 12:18:03.490135 RX_GATING_MODE = 2
6170 12:18:03.493743 RX_GATING_TRACK_MODE = 2
6171 12:18:03.496726 SELPH_MODE = 1
6172 12:18:03.500033 PICG_EARLY_EN = 1
6173 12:18:03.503865 VALID_LAT_VALUE = 1
6174 12:18:03.506884 ==============================================================
6175 12:18:03.513515 Enter into Gating configuration >>>>
6176 12:18:03.514086 Exit from Gating configuration <<<<
6177 12:18:03.516915 Enter into DVFS_PRE_config >>>>>
6178 12:18:03.530148 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6179 12:18:03.533866 Exit from DVFS_PRE_config <<<<<
6180 12:18:03.536901 Enter into PICG configuration >>>>
6181 12:18:03.540383 Exit from PICG configuration <<<<
6182 12:18:03.540882 [RX_INPUT] configuration >>>>>
6183 12:18:03.543963 [RX_INPUT] configuration <<<<<
6184 12:18:03.550302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6185 12:18:03.553961 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6186 12:18:03.560235 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 12:18:03.566753 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 12:18:03.573603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6189 12:18:03.580496 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6190 12:18:03.583614 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6191 12:18:03.587048 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6192 12:18:03.590215 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6193 12:18:03.596908 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6194 12:18:03.600165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6195 12:18:03.603660 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 12:18:03.607142 ===================================
6197 12:18:03.610099 LPDDR4 DRAM CONFIGURATION
6198 12:18:03.613051 ===================================
6199 12:18:03.616689 EX_ROW_EN[0] = 0x0
6200 12:18:03.617213 EX_ROW_EN[1] = 0x0
6201 12:18:03.620048 LP4Y_EN = 0x0
6202 12:18:03.620653 WORK_FSP = 0x0
6203 12:18:03.623139 WL = 0x2
6204 12:18:03.623656 RL = 0x2
6205 12:18:03.626412 BL = 0x2
6206 12:18:03.627195 RPST = 0x0
6207 12:18:03.629998 RD_PRE = 0x0
6208 12:18:03.630487 WR_PRE = 0x1
6209 12:18:03.633259 WR_PST = 0x0
6210 12:18:03.633752 DBI_WR = 0x0
6211 12:18:03.636845 DBI_RD = 0x0
6212 12:18:03.637373 OTF = 0x1
6213 12:18:03.640009 ===================================
6214 12:18:03.646621 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6215 12:18:03.649906 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6216 12:18:03.653380 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6217 12:18:03.656098 ===================================
6218 12:18:03.659928 LPDDR4 DRAM CONFIGURATION
6219 12:18:03.663130 ===================================
6220 12:18:03.666501 EX_ROW_EN[0] = 0x10
6221 12:18:03.666951 EX_ROW_EN[1] = 0x0
6222 12:18:03.669793 LP4Y_EN = 0x0
6223 12:18:03.670251 WORK_FSP = 0x0
6224 12:18:03.673030 WL = 0x2
6225 12:18:03.673512 RL = 0x2
6226 12:18:03.676623 BL = 0x2
6227 12:18:03.677097 RPST = 0x0
6228 12:18:03.679727 RD_PRE = 0x0
6229 12:18:03.680204 WR_PRE = 0x1
6230 12:18:03.683022 WR_PST = 0x0
6231 12:18:03.683506 DBI_WR = 0x0
6232 12:18:03.686332 DBI_RD = 0x0
6233 12:18:03.686769 OTF = 0x1
6234 12:18:03.689595 ===================================
6235 12:18:03.696354 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6236 12:18:03.700730 nWR fixed to 30
6237 12:18:03.704159 [ModeRegInit_LP4] CH0 RK0
6238 12:18:03.704643 [ModeRegInit_LP4] CH0 RK1
6239 12:18:03.707292 [ModeRegInit_LP4] CH1 RK0
6240 12:18:03.710840 [ModeRegInit_LP4] CH1 RK1
6241 12:18:03.711274 match AC timing 19
6242 12:18:03.717421 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6243 12:18:03.720699 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6244 12:18:03.723996 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6245 12:18:03.730666 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6246 12:18:03.734177 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6247 12:18:03.734655 ==
6248 12:18:03.737486 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 12:18:03.740571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 12:18:03.741105 ==
6251 12:18:03.747449 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 12:18:03.754020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 12:18:03.757408 [CA 0] Center 36 (8~64) winsize 57
6254 12:18:03.760477 [CA 1] Center 36 (8~64) winsize 57
6255 12:18:03.763897 [CA 2] Center 36 (8~64) winsize 57
6256 12:18:03.764337 [CA 3] Center 36 (8~64) winsize 57
6257 12:18:03.767428 [CA 4] Center 36 (8~64) winsize 57
6258 12:18:03.770866 [CA 5] Center 36 (8~64) winsize 57
6259 12:18:03.771343
6260 12:18:03.773819 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 12:18:03.777151
6262 12:18:03.780820 [CATrainingPosCal] consider 1 rank data
6263 12:18:03.781275 u2DelayCellTimex100 = 270/100 ps
6264 12:18:03.787718 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 12:18:03.790515 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 12:18:03.793703 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 12:18:03.797008 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 12:18:03.800554 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 12:18:03.803630 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:18:03.804061
6271 12:18:03.807243 CA PerBit enable=1, Macro0, CA PI delay=36
6272 12:18:03.807713
6273 12:18:03.810583 [CBTSetCACLKResult] CA Dly = 36
6274 12:18:03.813940 CS Dly: 1 (0~32)
6275 12:18:03.814393 ==
6276 12:18:03.817304 Dram Type= 6, Freq= 0, CH_0, rank 1
6277 12:18:03.820397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 12:18:03.820849 ==
6279 12:18:03.826872 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 12:18:03.830673 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6281 12:18:03.833842 [CA 0] Center 36 (8~64) winsize 57
6282 12:18:03.837280 [CA 1] Center 36 (8~64) winsize 57
6283 12:18:03.840413 [CA 2] Center 36 (8~64) winsize 57
6284 12:18:03.843879 [CA 3] Center 36 (8~64) winsize 57
6285 12:18:03.846983 [CA 4] Center 36 (8~64) winsize 57
6286 12:18:03.850449 [CA 5] Center 36 (8~64) winsize 57
6287 12:18:03.850879
6288 12:18:03.853673 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6289 12:18:03.854124
6290 12:18:03.856894 [CATrainingPosCal] consider 2 rank data
6291 12:18:03.860754 u2DelayCellTimex100 = 270/100 ps
6292 12:18:03.863856 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 12:18:03.867227 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 12:18:03.870197 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 12:18:03.877216 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 12:18:03.880334 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 12:18:03.883603 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 12:18:03.884035
6299 12:18:03.886809 CA PerBit enable=1, Macro0, CA PI delay=36
6300 12:18:03.887281
6301 12:18:03.890491 [CBTSetCACLKResult] CA Dly = 36
6302 12:18:03.891015 CS Dly: 1 (0~32)
6303 12:18:03.891353
6304 12:18:03.893697 ----->DramcWriteLeveling(PI) begin...
6305 12:18:03.894128 ==
6306 12:18:03.896895 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 12:18:03.903773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 12:18:03.904200 ==
6309 12:18:03.906946 Write leveling (Byte 0): 40 => 8
6310 12:18:03.907371 Write leveling (Byte 1): 32 => 0
6311 12:18:03.910240 DramcWriteLeveling(PI) end<-----
6312 12:18:03.910667
6313 12:18:03.913487 ==
6314 12:18:03.913914 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 12:18:03.920380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 12:18:03.920847 ==
6317 12:18:03.923478 [Gating] SW mode calibration
6318 12:18:03.930200 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6319 12:18:03.933819 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6320 12:18:03.940192 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 12:18:03.943736 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 12:18:03.946970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 12:18:03.953418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 12:18:03.956736 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 12:18:03.960047 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 12:18:03.966905 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 12:18:03.970296 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 12:18:03.973713 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 12:18:03.976868 Total UI for P1: 0, mck2ui 16
6330 12:18:03.980278 best dqsien dly found for B0: ( 0, 14, 24)
6331 12:18:03.983658 Total UI for P1: 0, mck2ui 16
6332 12:18:03.986838 best dqsien dly found for B1: ( 0, 14, 24)
6333 12:18:03.990317 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6334 12:18:03.993470 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6335 12:18:03.993958
6336 12:18:03.997160 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 12:18:04.003998 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 12:18:04.004599 [Gating] SW calibration Done
6339 12:18:04.005058 ==
6340 12:18:04.006882 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 12:18:04.013652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 12:18:04.014176 ==
6343 12:18:04.014729 RX Vref Scan: 0
6344 12:18:04.015244
6345 12:18:04.016544 RX Vref 0 -> 0, step: 1
6346 12:18:04.017168
6347 12:18:04.020015 RX Delay -410 -> 252, step: 16
6348 12:18:04.023214 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6349 12:18:04.026841 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6350 12:18:04.032981 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6351 12:18:04.036519 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6352 12:18:04.039825 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6353 12:18:04.043324 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6354 12:18:04.049826 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6355 12:18:04.053524 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6356 12:18:04.056439 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6357 12:18:04.059744 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6358 12:18:04.066338 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6359 12:18:04.069470 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6360 12:18:04.072827 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6361 12:18:04.076146 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6362 12:18:04.082879 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6363 12:18:04.086276 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6364 12:18:04.086656 ==
6365 12:18:04.090098 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 12:18:04.093152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 12:18:04.093600 ==
6368 12:18:04.096150 DQS Delay:
6369 12:18:04.096565 DQS0 = 19, DQS1 = 35
6370 12:18:04.099736 DQM Delay:
6371 12:18:04.100154 DQM0 = 5, DQM1 = 8
6372 12:18:04.100512 DQ Delay:
6373 12:18:04.102829 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6374 12:18:04.106479 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6375 12:18:04.109652 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6376 12:18:04.113135 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6377 12:18:04.113571
6378 12:18:04.113904
6379 12:18:04.114248 ==
6380 12:18:04.116065 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 12:18:04.119577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 12:18:04.120116 ==
6383 12:18:04.122695
6384 12:18:04.123120
6385 12:18:04.123467 TX Vref Scan disable
6386 12:18:04.126306 == TX Byte 0 ==
6387 12:18:04.129467 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 12:18:04.132807 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 12:18:04.136403 == TX Byte 1 ==
6390 12:18:04.139539 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6391 12:18:04.142963 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6392 12:18:04.143398 ==
6393 12:18:04.146349 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 12:18:04.149570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 12:18:04.152632 ==
6396 12:18:04.153110
6397 12:18:04.153472
6398 12:18:04.153786 TX Vref Scan disable
6399 12:18:04.156036 == TX Byte 0 ==
6400 12:18:04.159372 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 12:18:04.162601 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 12:18:04.166105 == TX Byte 1 ==
6403 12:18:04.169381 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6404 12:18:04.172473 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6405 12:18:04.173098
6406 12:18:04.176087 [DATLAT]
6407 12:18:04.176605 Freq=400, CH0 RK0
6408 12:18:04.177006
6409 12:18:04.179668 DATLAT Default: 0xf
6410 12:18:04.180107 0, 0xFFFF, sum = 0
6411 12:18:04.182891 1, 0xFFFF, sum = 0
6412 12:18:04.183403 2, 0xFFFF, sum = 0
6413 12:18:04.186101 3, 0xFFFF, sum = 0
6414 12:18:04.186560 4, 0xFFFF, sum = 0
6415 12:18:04.189234 5, 0xFFFF, sum = 0
6416 12:18:04.189654 6, 0xFFFF, sum = 0
6417 12:18:04.192832 7, 0xFFFF, sum = 0
6418 12:18:04.193335 8, 0xFFFF, sum = 0
6419 12:18:04.195873 9, 0xFFFF, sum = 0
6420 12:18:04.196268 10, 0xFFFF, sum = 0
6421 12:18:04.199391 11, 0xFFFF, sum = 0
6422 12:18:04.199762 12, 0xFFFF, sum = 0
6423 12:18:04.202743 13, 0x0, sum = 1
6424 12:18:04.203132 14, 0x0, sum = 2
6425 12:18:04.205818 15, 0x0, sum = 3
6426 12:18:04.206323 16, 0x0, sum = 4
6427 12:18:04.209444 best_step = 14
6428 12:18:04.209807
6429 12:18:04.210141 ==
6430 12:18:04.212578 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 12:18:04.216004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 12:18:04.216445 ==
6433 12:18:04.219680 RX Vref Scan: 1
6434 12:18:04.220162
6435 12:18:04.220631 RX Vref 0 -> 0, step: 1
6436 12:18:04.221182
6437 12:18:04.222744 RX Delay -311 -> 252, step: 8
6438 12:18:04.223323
6439 12:18:04.226068 Set Vref, RX VrefLevel [Byte0]: 57
6440 12:18:04.229226 [Byte1]: 48
6441 12:18:04.233976
6442 12:18:04.234427 Final RX Vref Byte 0 = 57 to rank0
6443 12:18:04.237280 Final RX Vref Byte 1 = 48 to rank0
6444 12:18:04.240573 Final RX Vref Byte 0 = 57 to rank1
6445 12:18:04.243729 Final RX Vref Byte 1 = 48 to rank1==
6446 12:18:04.247020 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 12:18:04.253823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 12:18:04.254316 ==
6449 12:18:04.254763 DQS Delay:
6450 12:18:04.257347 DQS0 = 28, DQS1 = 48
6451 12:18:04.257822 DQM Delay:
6452 12:18:04.258301 DQM0 = 12, DQM1 = 15
6453 12:18:04.260489 DQ Delay:
6454 12:18:04.264073 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6455 12:18:04.264557 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6456 12:18:04.267256 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6457 12:18:04.270570 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6458 12:18:04.271053
6459 12:18:04.273884
6460 12:18:04.280680 [DQSOSCAuto] RK0, (LSB)MR18= 0xa8a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6461 12:18:04.283771 CH0 RK0: MR19=C0C, MR18=A8A0
6462 12:18:04.290497 CH0_RK0: MR19=0xC0C, MR18=0xA8A0, DQSOSC=388, MR23=63, INC=392, DEC=261
6463 12:18:04.290924 ==
6464 12:18:04.293938 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 12:18:04.297380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 12:18:04.297806 ==
6467 12:18:04.300781 [Gating] SW mode calibration
6468 12:18:04.307167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6469 12:18:04.313690 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6470 12:18:04.317399 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 12:18:04.320229 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 12:18:04.323622 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 12:18:04.330150 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 12:18:04.333710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 12:18:04.336883 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 12:18:04.343677 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 12:18:04.347141 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 12:18:04.350682 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 12:18:04.353917 Total UI for P1: 0, mck2ui 16
6480 12:18:04.357266 best dqsien dly found for B0: ( 0, 14, 24)
6481 12:18:04.360516 Total UI for P1: 0, mck2ui 16
6482 12:18:04.363697 best dqsien dly found for B1: ( 0, 14, 24)
6483 12:18:04.367027 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6484 12:18:04.370285 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6485 12:18:04.370709
6486 12:18:04.377133 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 12:18:04.380590 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 12:18:04.384137 [Gating] SW calibration Done
6489 12:18:04.384677 ==
6490 12:18:04.387232 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 12:18:04.390578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 12:18:04.391176 ==
6493 12:18:04.391563 RX Vref Scan: 0
6494 12:18:04.391911
6495 12:18:04.393678 RX Vref 0 -> 0, step: 1
6496 12:18:04.394169
6497 12:18:04.397237 RX Delay -410 -> 252, step: 16
6498 12:18:04.400344 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6499 12:18:04.407238 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6500 12:18:04.410588 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6501 12:18:04.414008 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6502 12:18:04.417203 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6503 12:18:04.423606 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6504 12:18:04.426940 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6505 12:18:04.430168 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6506 12:18:04.433694 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6507 12:18:04.440286 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6508 12:18:04.443420 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6509 12:18:04.446773 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6510 12:18:04.450506 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6511 12:18:04.456984 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6512 12:18:04.460368 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6513 12:18:04.463340 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6514 12:18:04.463822 ==
6515 12:18:04.466795 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 12:18:04.470083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 12:18:04.473240 ==
6518 12:18:04.473681 DQS Delay:
6519 12:18:04.474144 DQS0 = 27, DQS1 = 43
6520 12:18:04.477015 DQM Delay:
6521 12:18:04.477495 DQM0 = 9, DQM1 = 16
6522 12:18:04.480035 DQ Delay:
6523 12:18:04.480510 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6524 12:18:04.483298 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6525 12:18:04.486759 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6526 12:18:04.490234 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6527 12:18:04.490671
6528 12:18:04.491125
6529 12:18:04.491565 ==
6530 12:18:04.493439 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 12:18:04.499900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 12:18:04.500328 ==
6533 12:18:04.500662
6534 12:18:04.501007
6535 12:18:04.501317 TX Vref Scan disable
6536 12:18:04.503514 == TX Byte 0 ==
6537 12:18:04.506472 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6538 12:18:04.510096 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6539 12:18:04.513222 == TX Byte 1 ==
6540 12:18:04.516556 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6541 12:18:04.519738 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6542 12:18:04.523275 ==
6543 12:18:04.523701 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 12:18:04.529661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 12:18:04.530085 ==
6546 12:18:04.530420
6547 12:18:04.530729
6548 12:18:04.533016 TX Vref Scan disable
6549 12:18:04.533579 == TX Byte 0 ==
6550 12:18:04.536291 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6551 12:18:04.543091 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6552 12:18:04.543651 == TX Byte 1 ==
6553 12:18:04.546593 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6554 12:18:04.549719 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6555 12:18:04.550281
6556 12:18:04.552983 [DATLAT]
6557 12:18:04.553495 Freq=400, CH0 RK1
6558 12:18:04.553920
6559 12:18:04.556322 DATLAT Default: 0xe
6560 12:18:04.556885 0, 0xFFFF, sum = 0
6561 12:18:04.560165 1, 0xFFFF, sum = 0
6562 12:18:04.560625 2, 0xFFFF, sum = 0
6563 12:18:04.563432 3, 0xFFFF, sum = 0
6564 12:18:04.563867 4, 0xFFFF, sum = 0
6565 12:18:04.566658 5, 0xFFFF, sum = 0
6566 12:18:04.567095 6, 0xFFFF, sum = 0
6567 12:18:04.569910 7, 0xFFFF, sum = 0
6568 12:18:04.570347 8, 0xFFFF, sum = 0
6569 12:18:04.572951 9, 0xFFFF, sum = 0
6570 12:18:04.576383 10, 0xFFFF, sum = 0
6571 12:18:04.576819 11, 0xFFFF, sum = 0
6572 12:18:04.579823 12, 0xFFFF, sum = 0
6573 12:18:04.580260 13, 0x0, sum = 1
6574 12:18:04.582805 14, 0x0, sum = 2
6575 12:18:04.583359 15, 0x0, sum = 3
6576 12:18:04.586443 16, 0x0, sum = 4
6577 12:18:04.586877 best_step = 14
6578 12:18:04.587221
6579 12:18:04.587539 ==
6580 12:18:04.589832 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 12:18:04.593216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 12:18:04.593657 ==
6583 12:18:04.596111 RX Vref Scan: 0
6584 12:18:04.596540
6585 12:18:04.599302 RX Vref 0 -> 0, step: 1
6586 12:18:04.599822
6587 12:18:04.600195 RX Delay -327 -> 252, step: 8
6588 12:18:04.608254 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6589 12:18:04.611405 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6590 12:18:04.614964 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6591 12:18:04.618530 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6592 12:18:04.625000 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6593 12:18:04.628159 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6594 12:18:04.631323 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6595 12:18:04.634793 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6596 12:18:04.641114 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6597 12:18:04.644428 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6598 12:18:04.647936 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6599 12:18:04.651174 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6600 12:18:04.657732 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6601 12:18:04.661322 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6602 12:18:04.664536 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6603 12:18:04.671213 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6604 12:18:04.671639 ==
6605 12:18:04.674475 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 12:18:04.677721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 12:18:04.678148 ==
6608 12:18:04.678483 DQS Delay:
6609 12:18:04.681095 DQS0 = 28, DQS1 = 40
6610 12:18:04.681515 DQM Delay:
6611 12:18:04.684839 DQM0 = 9, DQM1 = 13
6612 12:18:04.685295 DQ Delay:
6613 12:18:04.687916 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6614 12:18:04.691099 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6615 12:18:04.694700 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6616 12:18:04.697953 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6617 12:18:04.698381
6618 12:18:04.698723
6619 12:18:04.704303 [DQSOSCAuto] RK1, (LSB)MR18= 0xb76b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6620 12:18:04.707589 CH0 RK1: MR19=C0C, MR18=B76B
6621 12:18:04.714307 CH0_RK1: MR19=0xC0C, MR18=0xB76B, DQSOSC=387, MR23=63, INC=394, DEC=262
6622 12:18:04.717466 [RxdqsGatingPostProcess] freq 400
6623 12:18:04.724077 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6624 12:18:04.724502 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 12:18:04.727667 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 12:18:04.731015 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 12:18:04.733975 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 12:18:04.737411 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 12:18:04.740907 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 12:18:04.743946 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 12:18:04.747598 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 12:18:04.751031 Pre-setting of DQS Precalculation
6633 12:18:04.757255 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6634 12:18:04.757680 ==
6635 12:18:04.760701 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 12:18:04.764143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 12:18:04.764585 ==
6638 12:18:04.770939 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 12:18:04.773875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6640 12:18:04.777198 [CA 0] Center 36 (8~64) winsize 57
6641 12:18:04.780861 [CA 1] Center 36 (8~64) winsize 57
6642 12:18:04.784182 [CA 2] Center 36 (8~64) winsize 57
6643 12:18:04.787062 [CA 3] Center 36 (8~64) winsize 57
6644 12:18:04.790559 [CA 4] Center 36 (8~64) winsize 57
6645 12:18:04.793760 [CA 5] Center 36 (8~64) winsize 57
6646 12:18:04.794181
6647 12:18:04.796857 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6648 12:18:04.797335
6649 12:18:04.800488 [CATrainingPosCal] consider 1 rank data
6650 12:18:04.803544 u2DelayCellTimex100 = 270/100 ps
6651 12:18:04.807026 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 12:18:04.810660 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 12:18:04.817076 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 12:18:04.820412 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 12:18:04.823834 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 12:18:04.826705 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:18:04.827128
6658 12:18:04.830193 CA PerBit enable=1, Macro0, CA PI delay=36
6659 12:18:04.830617
6660 12:18:04.833652 [CBTSetCACLKResult] CA Dly = 36
6661 12:18:04.834077 CS Dly: 1 (0~32)
6662 12:18:04.834415 ==
6663 12:18:04.836845 Dram Type= 6, Freq= 0, CH_1, rank 1
6664 12:18:04.843740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 12:18:04.844217 ==
6666 12:18:04.846721 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 12:18:04.853206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6668 12:18:04.856468 [CA 0] Center 36 (8~64) winsize 57
6669 12:18:04.859933 [CA 1] Center 36 (8~64) winsize 57
6670 12:18:04.863659 [CA 2] Center 36 (8~64) winsize 57
6671 12:18:04.866951 [CA 3] Center 36 (8~64) winsize 57
6672 12:18:04.869835 [CA 4] Center 36 (8~64) winsize 57
6673 12:18:04.873462 [CA 5] Center 36 (8~64) winsize 57
6674 12:18:04.873886
6675 12:18:04.877002 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6676 12:18:04.877524
6677 12:18:04.880351 [CATrainingPosCal] consider 2 rank data
6678 12:18:04.883498 u2DelayCellTimex100 = 270/100 ps
6679 12:18:04.886416 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 12:18:04.890479 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 12:18:04.893319 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 12:18:04.896780 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 12:18:04.900128 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 12:18:04.903271 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 12:18:04.906656
6686 12:18:04.909810 CA PerBit enable=1, Macro0, CA PI delay=36
6687 12:18:04.910252
6688 12:18:04.913304 [CBTSetCACLKResult] CA Dly = 36
6689 12:18:04.913744 CS Dly: 1 (0~32)
6690 12:18:04.914182
6691 12:18:04.916579 ----->DramcWriteLeveling(PI) begin...
6692 12:18:04.917051 ==
6693 12:18:04.919556 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 12:18:04.922909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 12:18:04.926081 ==
6696 12:18:04.926536 Write leveling (Byte 0): 40 => 8
6697 12:18:04.929712 Write leveling (Byte 1): 32 => 0
6698 12:18:04.932925 DramcWriteLeveling(PI) end<-----
6699 12:18:04.933385
6700 12:18:04.933721 ==
6701 12:18:04.936138 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 12:18:04.942780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 12:18:04.943319 ==
6704 12:18:04.943798 [Gating] SW mode calibration
6705 12:18:04.952963 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6706 12:18:04.956004 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6707 12:18:04.959361 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 12:18:04.966083 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 12:18:04.969863 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 12:18:04.972872 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 12:18:04.979199 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 12:18:04.982650 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 12:18:04.985791 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 12:18:04.992586 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 12:18:04.995871 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 12:18:04.999514 Total UI for P1: 0, mck2ui 16
6717 12:18:05.002852 best dqsien dly found for B0: ( 0, 14, 24)
6718 12:18:05.005878 Total UI for P1: 0, mck2ui 16
6719 12:18:05.009662 best dqsien dly found for B1: ( 0, 14, 24)
6720 12:18:05.012987 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6721 12:18:05.016194 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6722 12:18:05.016633
6723 12:18:05.019363 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 12:18:05.023045 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 12:18:05.025977 [Gating] SW calibration Done
6726 12:18:05.026419 ==
6727 12:18:05.029823 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 12:18:05.036144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 12:18:05.036683 ==
6730 12:18:05.037222 RX Vref Scan: 0
6731 12:18:05.037595
6732 12:18:05.038995 RX Vref 0 -> 0, step: 1
6733 12:18:05.039486
6734 12:18:05.042594 RX Delay -410 -> 252, step: 16
6735 12:18:05.046052 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6736 12:18:05.049092 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6737 12:18:05.056003 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6738 12:18:05.059141 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6739 12:18:05.062240 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6740 12:18:05.066181 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6741 12:18:05.072462 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6742 12:18:05.075790 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6743 12:18:05.078996 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6744 12:18:05.082558 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6745 12:18:05.089192 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6746 12:18:05.092173 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6747 12:18:05.095417 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6748 12:18:05.099093 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6749 12:18:05.105727 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6750 12:18:05.108836 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6751 12:18:05.109283 ==
6752 12:18:05.112242 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 12:18:05.115502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 12:18:05.116027 ==
6755 12:18:05.119013 DQS Delay:
6756 12:18:05.119542 DQS0 = 27, DQS1 = 43
6757 12:18:05.119885 DQM Delay:
6758 12:18:05.122242 DQM0 = 7, DQM1 = 17
6759 12:18:05.122715 DQ Delay:
6760 12:18:05.125500 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6761 12:18:05.128634 DQ4 =8, DQ5 =8, DQ6 =16, DQ7 =0
6762 12:18:05.132370 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6763 12:18:05.135307 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =24
6764 12:18:05.135783
6765 12:18:05.136248
6766 12:18:05.136604 ==
6767 12:18:05.138757 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 12:18:05.142056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 12:18:05.142488 ==
6770 12:18:05.145359
6771 12:18:05.145824
6772 12:18:05.146192 TX Vref Scan disable
6773 12:18:05.148513 == TX Byte 0 ==
6774 12:18:05.151898 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 12:18:05.155211 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 12:18:05.158706 == TX Byte 1 ==
6777 12:18:05.161812 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6778 12:18:05.165396 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6779 12:18:05.165825 ==
6780 12:18:05.169101 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 12:18:05.172084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 12:18:05.175395 ==
6783 12:18:05.175841
6784 12:18:05.176208
6785 12:18:05.176543 TX Vref Scan disable
6786 12:18:05.179034 == TX Byte 0 ==
6787 12:18:05.182136 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 12:18:05.185441 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 12:18:05.188735 == TX Byte 1 ==
6790 12:18:05.192462 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6791 12:18:05.195668 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6792 12:18:05.196092
6793 12:18:05.199011 [DATLAT]
6794 12:18:05.199433 Freq=400, CH1 RK0
6795 12:18:05.199770
6796 12:18:05.202332 DATLAT Default: 0xf
6797 12:18:05.202754 0, 0xFFFF, sum = 0
6798 12:18:05.205495 1, 0xFFFF, sum = 0
6799 12:18:05.205926 2, 0xFFFF, sum = 0
6800 12:18:05.208810 3, 0xFFFF, sum = 0
6801 12:18:05.209274 4, 0xFFFF, sum = 0
6802 12:18:05.212228 5, 0xFFFF, sum = 0
6803 12:18:05.212657 6, 0xFFFF, sum = 0
6804 12:18:05.215475 7, 0xFFFF, sum = 0
6805 12:18:05.215905 8, 0xFFFF, sum = 0
6806 12:18:05.218989 9, 0xFFFF, sum = 0
6807 12:18:05.219529 10, 0xFFFF, sum = 0
6808 12:18:05.222514 11, 0xFFFF, sum = 0
6809 12:18:05.223045 12, 0xFFFF, sum = 0
6810 12:18:05.225749 13, 0x0, sum = 1
6811 12:18:05.226178 14, 0x0, sum = 2
6812 12:18:05.229248 15, 0x0, sum = 3
6813 12:18:05.229682 16, 0x0, sum = 4
6814 12:18:05.232016 best_step = 14
6815 12:18:05.232440
6816 12:18:05.232775 ==
6817 12:18:05.235438 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 12:18:05.238937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 12:18:05.239365 ==
6820 12:18:05.242322 RX Vref Scan: 1
6821 12:18:05.242767
6822 12:18:05.243110 RX Vref 0 -> 0, step: 1
6823 12:18:05.243426
6824 12:18:05.245455 RX Delay -327 -> 252, step: 8
6825 12:18:05.246015
6826 12:18:05.248704 Set Vref, RX VrefLevel [Byte0]: 52
6827 12:18:05.251980 [Byte1]: 50
6828 12:18:05.256579
6829 12:18:05.257097 Final RX Vref Byte 0 = 52 to rank0
6830 12:18:05.259956 Final RX Vref Byte 1 = 50 to rank0
6831 12:18:05.263284 Final RX Vref Byte 0 = 52 to rank1
6832 12:18:05.266533 Final RX Vref Byte 1 = 50 to rank1==
6833 12:18:05.269843 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 12:18:05.276528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 12:18:05.276995 ==
6836 12:18:05.277346 DQS Delay:
6837 12:18:05.279892 DQS0 = 32, DQS1 = 40
6838 12:18:05.280318 DQM Delay:
6839 12:18:05.280660 DQM0 = 11, DQM1 = 12
6840 12:18:05.283396 DQ Delay:
6841 12:18:05.286397 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6842 12:18:05.286825 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6843 12:18:05.290155 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6844 12:18:05.293024 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6845 12:18:05.293459
6846 12:18:05.293796
6847 12:18:05.302954 [DQSOSCAuto] RK0, (LSB)MR18= 0x94ce, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6848 12:18:05.306389 CH1 RK0: MR19=C0C, MR18=94CE
6849 12:18:05.312873 CH1_RK0: MR19=0xC0C, MR18=0x94CE, DQSOSC=384, MR23=63, INC=400, DEC=267
6850 12:18:05.313337 ==
6851 12:18:05.316278 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 12:18:05.319483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 12:18:05.319912 ==
6854 12:18:05.322916 [Gating] SW mode calibration
6855 12:18:05.329426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6856 12:18:05.336057 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6857 12:18:05.339203 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 12:18:05.342745 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 12:18:05.349154 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 12:18:05.352305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 12:18:05.356066 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 12:18:05.359576 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 12:18:05.366253 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 12:18:05.369307 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 12:18:05.372750 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 12:18:05.375886 Total UI for P1: 0, mck2ui 16
6867 12:18:05.379350 best dqsien dly found for B0: ( 0, 14, 24)
6868 12:18:05.382441 Total UI for P1: 0, mck2ui 16
6869 12:18:05.385761 best dqsien dly found for B1: ( 0, 14, 24)
6870 12:18:05.389285 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6871 12:18:05.396006 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6872 12:18:05.396586
6873 12:18:05.399343 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 12:18:05.402733 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 12:18:05.405836 [Gating] SW calibration Done
6876 12:18:05.406358 ==
6877 12:18:05.409076 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 12:18:05.412430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 12:18:05.412997 ==
6880 12:18:05.415933 RX Vref Scan: 0
6881 12:18:05.416449
6882 12:18:05.416845 RX Vref 0 -> 0, step: 1
6883 12:18:05.417214
6884 12:18:05.418823 RX Delay -410 -> 252, step: 16
6885 12:18:05.422251 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6886 12:18:05.428771 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6887 12:18:05.432024 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6888 12:18:05.435393 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6889 12:18:05.438822 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6890 12:18:05.445426 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6891 12:18:05.448669 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6892 12:18:05.452206 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6893 12:18:05.455675 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6894 12:18:05.462195 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6895 12:18:05.465753 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6896 12:18:05.468958 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6897 12:18:05.472277 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6898 12:18:05.478866 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6899 12:18:05.482277 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6900 12:18:05.485359 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6901 12:18:05.485829 ==
6902 12:18:05.488887 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 12:18:05.495569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 12:18:05.496042 ==
6905 12:18:05.496414 DQS Delay:
6906 12:18:05.498881 DQS0 = 35, DQS1 = 35
6907 12:18:05.499350 DQM Delay:
6908 12:18:05.499718 DQM0 = 18, DQM1 = 12
6909 12:18:05.502511 DQ Delay:
6910 12:18:05.505635 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6911 12:18:05.506109 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6912 12:18:05.508997 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6913 12:18:05.512467 DQ12 =24, DQ13 =16, DQ14 =8, DQ15 =24
6914 12:18:05.513033
6915 12:18:05.515473
6916 12:18:05.515893 ==
6917 12:18:05.519587 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 12:18:05.522556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 12:18:05.522988 ==
6920 12:18:05.523326
6921 12:18:05.523638
6922 12:18:05.525302 TX Vref Scan disable
6923 12:18:05.525658 == TX Byte 0 ==
6924 12:18:05.528692 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6925 12:18:05.535707 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6926 12:18:05.536238 == TX Byte 1 ==
6927 12:18:05.538637 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6928 12:18:05.545430 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6929 12:18:05.545886 ==
6930 12:18:05.548530 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 12:18:05.551737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 12:18:05.552177 ==
6933 12:18:05.552575
6934 12:18:05.552955
6935 12:18:05.555080 TX Vref Scan disable
6936 12:18:05.555520 == TX Byte 0 ==
6937 12:18:05.558380 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6938 12:18:05.565418 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6939 12:18:05.565866 == TX Byte 1 ==
6940 12:18:05.568808 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6941 12:18:05.575161 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6942 12:18:05.575604
6943 12:18:05.575965 [DATLAT]
6944 12:18:05.576284 Freq=400, CH1 RK1
6945 12:18:05.576615
6946 12:18:05.578631 DATLAT Default: 0xe
6947 12:18:05.581598 0, 0xFFFF, sum = 0
6948 12:18:05.582156 1, 0xFFFF, sum = 0
6949 12:18:05.585280 2, 0xFFFF, sum = 0
6950 12:18:05.585751 3, 0xFFFF, sum = 0
6951 12:18:05.588599 4, 0xFFFF, sum = 0
6952 12:18:05.589075 5, 0xFFFF, sum = 0
6953 12:18:05.591851 6, 0xFFFF, sum = 0
6954 12:18:05.592286 7, 0xFFFF, sum = 0
6955 12:18:05.594965 8, 0xFFFF, sum = 0
6956 12:18:05.595409 9, 0xFFFF, sum = 0
6957 12:18:05.598145 10, 0xFFFF, sum = 0
6958 12:18:05.598615 11, 0xFFFF, sum = 0
6959 12:18:05.601606 12, 0xFFFF, sum = 0
6960 12:18:05.602077 13, 0x0, sum = 1
6961 12:18:05.605353 14, 0x0, sum = 2
6962 12:18:05.605869 15, 0x0, sum = 3
6963 12:18:05.608453 16, 0x0, sum = 4
6964 12:18:05.609124 best_step = 14
6965 12:18:05.609503
6966 12:18:05.609827 ==
6967 12:18:05.611701 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 12:18:05.614911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 12:18:05.618390 ==
6970 12:18:05.618929 RX Vref Scan: 0
6971 12:18:05.619302
6972 12:18:05.621979 RX Vref 0 -> 0, step: 1
6973 12:18:05.622408
6974 12:18:05.624864 RX Delay -311 -> 252, step: 8
6975 12:18:05.628515 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6976 12:18:05.634765 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6977 12:18:05.638702 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6978 12:18:05.641860 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6979 12:18:05.644872 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6980 12:18:05.651712 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6981 12:18:05.654888 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6982 12:18:05.658300 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6983 12:18:05.661555 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6984 12:18:05.668083 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6985 12:18:05.671994 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6986 12:18:05.675382 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6987 12:18:05.678174 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6988 12:18:05.685009 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6989 12:18:05.688112 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6990 12:18:05.691634 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6991 12:18:05.692258 ==
6992 12:18:05.695062 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 12:18:05.701595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 12:18:05.702025 ==
6995 12:18:05.702397 DQS Delay:
6996 12:18:05.704719 DQS0 = 28, DQS1 = 36
6997 12:18:05.705243 DQM Delay:
6998 12:18:05.705620 DQM0 = 10, DQM1 = 11
6999 12:18:05.708038 DQ Delay:
7000 12:18:05.711467 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7001 12:18:05.711907 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
7002 12:18:05.714562 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7003 12:18:05.718324 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
7004 12:18:05.718783
7005 12:18:05.721607
7006 12:18:05.727846 [DQSOSCAuto] RK1, (LSB)MR18= 0xa851, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7007 12:18:05.731521 CH1 RK1: MR19=C0C, MR18=A851
7008 12:18:05.737986 CH1_RK1: MR19=0xC0C, MR18=0xA851, DQSOSC=388, MR23=63, INC=392, DEC=261
7009 12:18:05.741351 [RxdqsGatingPostProcess] freq 400
7010 12:18:05.744569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7011 12:18:05.748019 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 12:18:05.751345 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 12:18:05.754591 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 12:18:05.757778 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 12:18:05.761029 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 12:18:05.764628 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 12:18:05.767989 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 12:18:05.771270 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 12:18:05.774270 Pre-setting of DQS Precalculation
7020 12:18:05.777912 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7021 12:18:05.784419 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7022 12:18:05.794362 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7023 12:18:05.794788
7024 12:18:05.795121
7025 12:18:05.795462 [Calibration Summary] 800 Mbps
7026 12:18:05.797833 CH 0, Rank 0
7027 12:18:05.801022 SW Impedance : PASS
7028 12:18:05.801444 DUTY Scan : NO K
7029 12:18:05.804374 ZQ Calibration : PASS
7030 12:18:05.804795 Jitter Meter : NO K
7031 12:18:05.807534 CBT Training : PASS
7032 12:18:05.811171 Write leveling : PASS
7033 12:18:05.811592 RX DQS gating : PASS
7034 12:18:05.814650 RX DQ/DQS(RDDQC) : PASS
7035 12:18:05.817812 TX DQ/DQS : PASS
7036 12:18:05.818276 RX DATLAT : PASS
7037 12:18:05.820845 RX DQ/DQS(Engine): PASS
7038 12:18:05.824225 TX OE : NO K
7039 12:18:05.824648 All Pass.
7040 12:18:05.825015
7041 12:18:05.825333 CH 0, Rank 1
7042 12:18:05.827680 SW Impedance : PASS
7043 12:18:05.831071 DUTY Scan : NO K
7044 12:18:05.831494 ZQ Calibration : PASS
7045 12:18:05.834347 Jitter Meter : NO K
7046 12:18:05.837494 CBT Training : PASS
7047 12:18:05.837916 Write leveling : NO K
7048 12:18:05.840837 RX DQS gating : PASS
7049 12:18:05.844498 RX DQ/DQS(RDDQC) : PASS
7050 12:18:05.844919 TX DQ/DQS : PASS
7051 12:18:05.847720 RX DATLAT : PASS
7052 12:18:05.848286 RX DQ/DQS(Engine): PASS
7053 12:18:05.850929 TX OE : NO K
7054 12:18:05.851492 All Pass.
7055 12:18:05.851963
7056 12:18:05.854306 CH 1, Rank 0
7057 12:18:05.854731 SW Impedance : PASS
7058 12:18:05.857622 DUTY Scan : NO K
7059 12:18:05.860577 ZQ Calibration : PASS
7060 12:18:05.861062 Jitter Meter : NO K
7061 12:18:05.864311 CBT Training : PASS
7062 12:18:05.867355 Write leveling : PASS
7063 12:18:05.867780 RX DQS gating : PASS
7064 12:18:05.870610 RX DQ/DQS(RDDQC) : PASS
7065 12:18:05.873979 TX DQ/DQS : PASS
7066 12:18:05.874402 RX DATLAT : PASS
7067 12:18:05.877432 RX DQ/DQS(Engine): PASS
7068 12:18:05.880747 TX OE : NO K
7069 12:18:05.881234 All Pass.
7070 12:18:05.881577
7071 12:18:05.881887 CH 1, Rank 1
7072 12:18:05.884166 SW Impedance : PASS
7073 12:18:05.887101 DUTY Scan : NO K
7074 12:18:05.887525 ZQ Calibration : PASS
7075 12:18:05.890596 Jitter Meter : NO K
7076 12:18:05.893976 CBT Training : PASS
7077 12:18:05.894397 Write leveling : NO K
7078 12:18:05.897337 RX DQS gating : PASS
7079 12:18:05.900693 RX DQ/DQS(RDDQC) : PASS
7080 12:18:05.901150 TX DQ/DQS : PASS
7081 12:18:05.903968 RX DATLAT : PASS
7082 12:18:05.904391 RX DQ/DQS(Engine): PASS
7083 12:18:05.907578 TX OE : NO K
7084 12:18:05.908003 All Pass.
7085 12:18:05.908338
7086 12:18:05.911002 DramC Write-DBI off
7087 12:18:05.913983 PER_BANK_REFRESH: Hybrid Mode
7088 12:18:05.914456 TX_TRACKING: ON
7089 12:18:05.923870 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7090 12:18:05.927176 [FAST_K] Save calibration result to emmc
7091 12:18:05.930446 dramc_set_vcore_voltage set vcore to 725000
7092 12:18:05.934393 Read voltage for 1600, 0
7093 12:18:05.934815 Vio18 = 0
7094 12:18:05.935164 Vcore = 725000
7095 12:18:05.937710 Vdram = 0
7096 12:18:05.938131 Vddq = 0
7097 12:18:05.938470 Vmddr = 0
7098 12:18:05.944218 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7099 12:18:05.947480 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7100 12:18:05.950705 MEM_TYPE=3, freq_sel=13
7101 12:18:05.954133 sv_algorithm_assistance_LP4_3733
7102 12:18:05.957310 ============ PULL DRAM RESETB DOWN ============
7103 12:18:05.960799 ========== PULL DRAM RESETB DOWN end =========
7104 12:18:05.967184 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7105 12:18:05.970408 ===================================
7106 12:18:05.973972 LPDDR4 DRAM CONFIGURATION
7107 12:18:05.977272 ===================================
7108 12:18:05.977705 EX_ROW_EN[0] = 0x0
7109 12:18:05.981024 EX_ROW_EN[1] = 0x0
7110 12:18:05.981456 LP4Y_EN = 0x0
7111 12:18:05.983929 WORK_FSP = 0x1
7112 12:18:05.984359 WL = 0x5
7113 12:18:05.987654 RL = 0x5
7114 12:18:05.988083 BL = 0x2
7115 12:18:05.990979 RPST = 0x0
7116 12:18:05.991349 RD_PRE = 0x0
7117 12:18:05.993939 WR_PRE = 0x1
7118 12:18:05.994299 WR_PST = 0x1
7119 12:18:05.997368 DBI_WR = 0x0
7120 12:18:05.997728 DBI_RD = 0x0
7121 12:18:06.000531 OTF = 0x1
7122 12:18:06.003854 ===================================
7123 12:18:06.007112 ===================================
7124 12:18:06.007539 ANA top config
7125 12:18:06.010679 ===================================
7126 12:18:06.013955 DLL_ASYNC_EN = 0
7127 12:18:06.017617 ALL_SLAVE_EN = 0
7128 12:18:06.020445 NEW_RANK_MODE = 1
7129 12:18:06.020874 DLL_IDLE_MODE = 1
7130 12:18:06.023882 LP45_APHY_COMB_EN = 1
7131 12:18:06.027018 TX_ODT_DIS = 0
7132 12:18:06.030380 NEW_8X_MODE = 1
7133 12:18:06.033998 ===================================
7134 12:18:06.037413 ===================================
7135 12:18:06.040650 data_rate = 3200
7136 12:18:06.041075 CKR = 1
7137 12:18:06.043894 DQ_P2S_RATIO = 8
7138 12:18:06.047637 ===================================
7139 12:18:06.051082 CA_P2S_RATIO = 8
7140 12:18:06.053649 DQ_CA_OPEN = 0
7141 12:18:06.057322 DQ_SEMI_OPEN = 0
7142 12:18:06.060607 CA_SEMI_OPEN = 0
7143 12:18:06.061068 CA_FULL_RATE = 0
7144 12:18:06.063886 DQ_CKDIV4_EN = 0
7145 12:18:06.067360 CA_CKDIV4_EN = 0
7146 12:18:06.070711 CA_PREDIV_EN = 0
7147 12:18:06.074288 PH8_DLY = 12
7148 12:18:06.077417 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7149 12:18:06.077845 DQ_AAMCK_DIV = 4
7150 12:18:06.080742 CA_AAMCK_DIV = 4
7151 12:18:06.084133 CA_ADMCK_DIV = 4
7152 12:18:06.087096 DQ_TRACK_CA_EN = 0
7153 12:18:06.090366 CA_PICK = 1600
7154 12:18:06.094074 CA_MCKIO = 1600
7155 12:18:06.097208 MCKIO_SEMI = 0
7156 12:18:06.097631 PLL_FREQ = 3068
7157 12:18:06.100424 DQ_UI_PI_RATIO = 32
7158 12:18:06.103736 CA_UI_PI_RATIO = 0
7159 12:18:06.107545 ===================================
7160 12:18:06.110460 ===================================
7161 12:18:06.113905 memory_type:LPDDR4
7162 12:18:06.114329 GP_NUM : 10
7163 12:18:06.117033 SRAM_EN : 1
7164 12:18:06.120299 MD32_EN : 0
7165 12:18:06.123707 ===================================
7166 12:18:06.124131 [ANA_INIT] >>>>>>>>>>>>>>
7167 12:18:06.126942 <<<<<< [CONFIGURE PHASE]: ANA_TX
7168 12:18:06.130277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7169 12:18:06.133433 ===================================
7170 12:18:06.137019 data_rate = 3200,PCW = 0X7600
7171 12:18:06.140433 ===================================
7172 12:18:06.143587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7173 12:18:06.150180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 12:18:06.153849 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 12:18:06.160104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7176 12:18:06.163418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7177 12:18:06.166616 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7178 12:18:06.170419 [ANA_INIT] flow start
7179 12:18:06.170853 [ANA_INIT] PLL >>>>>>>>
7180 12:18:06.173451 [ANA_INIT] PLL <<<<<<<<
7181 12:18:06.176795 [ANA_INIT] MIDPI >>>>>>>>
7182 12:18:06.177310 [ANA_INIT] MIDPI <<<<<<<<
7183 12:18:06.179991 [ANA_INIT] DLL >>>>>>>>
7184 12:18:06.183580 [ANA_INIT] DLL <<<<<<<<
7185 12:18:06.184013 [ANA_INIT] flow end
7186 12:18:06.189999 ============ LP4 DIFF to SE enter ============
7187 12:18:06.193577 ============ LP4 DIFF to SE exit ============
7188 12:18:06.194012 [ANA_INIT] <<<<<<<<<<<<<
7189 12:18:06.196434 [Flow] Enable top DCM control >>>>>
7190 12:18:06.200116 [Flow] Enable top DCM control <<<<<
7191 12:18:06.203779 Enable DLL master slave shuffle
7192 12:18:06.210110 ==============================================================
7193 12:18:06.213405 Gating Mode config
7194 12:18:06.216414 ==============================================================
7195 12:18:06.219874 Config description:
7196 12:18:06.229580 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7197 12:18:06.236428 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7198 12:18:06.239767 SELPH_MODE 0: By rank 1: By Phase
7199 12:18:06.246654 ==============================================================
7200 12:18:06.250006 GAT_TRACK_EN = 1
7201 12:18:06.253208 RX_GATING_MODE = 2
7202 12:18:06.253647 RX_GATING_TRACK_MODE = 2
7203 12:18:06.256187 SELPH_MODE = 1
7204 12:18:06.259560 PICG_EARLY_EN = 1
7205 12:18:06.262995 VALID_LAT_VALUE = 1
7206 12:18:06.269758 ==============================================================
7207 12:18:06.272985 Enter into Gating configuration >>>>
7208 12:18:06.276749 Exit from Gating configuration <<<<
7209 12:18:06.280099 Enter into DVFS_PRE_config >>>>>
7210 12:18:06.290211 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7211 12:18:06.293078 Exit from DVFS_PRE_config <<<<<
7212 12:18:06.296479 Enter into PICG configuration >>>>
7213 12:18:06.299654 Exit from PICG configuration <<<<
7214 12:18:06.303298 [RX_INPUT] configuration >>>>>
7215 12:18:06.306769 [RX_INPUT] configuration <<<<<
7216 12:18:06.310083 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7217 12:18:06.316693 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7218 12:18:06.323368 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 12:18:06.329899 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 12:18:06.332925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7221 12:18:06.339797 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7222 12:18:06.342973 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7223 12:18:06.349746 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7224 12:18:06.353047 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7225 12:18:06.356102 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7226 12:18:06.359941 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7227 12:18:06.366263 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 12:18:06.369673 ===================================
7229 12:18:06.370117 LPDDR4 DRAM CONFIGURATION
7230 12:18:06.373044 ===================================
7231 12:18:06.376320 EX_ROW_EN[0] = 0x0
7232 12:18:06.379754 EX_ROW_EN[1] = 0x0
7233 12:18:06.380192 LP4Y_EN = 0x0
7234 12:18:06.383130 WORK_FSP = 0x1
7235 12:18:06.383674 WL = 0x5
7236 12:18:06.386594 RL = 0x5
7237 12:18:06.387038 BL = 0x2
7238 12:18:06.389904 RPST = 0x0
7239 12:18:06.390503 RD_PRE = 0x0
7240 12:18:06.393207 WR_PRE = 0x1
7241 12:18:06.393663 WR_PST = 0x1
7242 12:18:06.396090 DBI_WR = 0x0
7243 12:18:06.396544 DBI_RD = 0x0
7244 12:18:06.399666 OTF = 0x1
7245 12:18:06.403246 ===================================
7246 12:18:06.406532 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7247 12:18:06.409685 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7248 12:18:06.416479 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7249 12:18:06.419567 ===================================
7250 12:18:06.420000 LPDDR4 DRAM CONFIGURATION
7251 12:18:06.422878 ===================================
7252 12:18:06.426390 EX_ROW_EN[0] = 0x10
7253 12:18:06.426843 EX_ROW_EN[1] = 0x0
7254 12:18:06.429521 LP4Y_EN = 0x0
7255 12:18:06.432469 WORK_FSP = 0x1
7256 12:18:06.433002 WL = 0x5
7257 12:18:06.435834 RL = 0x5
7258 12:18:06.436263 BL = 0x2
7259 12:18:06.439121 RPST = 0x0
7260 12:18:06.439574 RD_PRE = 0x0
7261 12:18:06.442553 WR_PRE = 0x1
7262 12:18:06.443254 WR_PST = 0x1
7263 12:18:06.446062 DBI_WR = 0x0
7264 12:18:06.446553 DBI_RD = 0x0
7265 12:18:06.449541 OTF = 0x1
7266 12:18:06.452749 ===================================
7267 12:18:06.459052 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7268 12:18:06.459486 ==
7269 12:18:06.462546 Dram Type= 6, Freq= 0, CH_0, rank 0
7270 12:18:06.465968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7271 12:18:06.466403 ==
7272 12:18:06.469333 [Duty_Offset_Calibration]
7273 12:18:06.469764 B0:2 B1:0 CA:1
7274 12:18:06.470120
7275 12:18:06.472533 [DutyScan_Calibration_Flow] k_type=0
7276 12:18:06.482527
7277 12:18:06.483074 ==CLK 0==
7278 12:18:06.485476 Final CLK duty delay cell = -4
7279 12:18:06.488739 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7280 12:18:06.491787 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7281 12:18:06.495278 [-4] AVG Duty = 4906%(X100)
7282 12:18:06.495729
7283 12:18:06.498529 CH0 CLK Duty spec in!! Max-Min= 187%
7284 12:18:06.501968 [DutyScan_Calibration_Flow] ====Done====
7285 12:18:06.502556
7286 12:18:06.505123 [DutyScan_Calibration_Flow] k_type=1
7287 12:18:06.521650
7288 12:18:06.522165 ==DQS 0 ==
7289 12:18:06.524763 Final DQS duty delay cell = 0
7290 12:18:06.528022 [0] MAX Duty = 5249%(X100), DQS PI = 32
7291 12:18:06.531311 [0] MIN Duty = 4969%(X100), DQS PI = 0
7292 12:18:06.531841 [0] AVG Duty = 5109%(X100)
7293 12:18:06.534626
7294 12:18:06.535056 ==DQS 1 ==
7295 12:18:06.538015 Final DQS duty delay cell = -4
7296 12:18:06.541279 [-4] MAX Duty = 5156%(X100), DQS PI = 46
7297 12:18:06.544992 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7298 12:18:06.547838 [-4] AVG Duty = 5015%(X100)
7299 12:18:06.548288
7300 12:18:06.551711 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7301 12:18:06.552263
7302 12:18:06.554742 CH0 DQS 1 Duty spec in!! Max-Min= 281%
7303 12:18:06.558111 [DutyScan_Calibration_Flow] ====Done====
7304 12:18:06.558556
7305 12:18:06.561191 [DutyScan_Calibration_Flow] k_type=3
7306 12:18:06.578927
7307 12:18:06.579515 ==DQM 0 ==
7308 12:18:06.582393 Final DQM duty delay cell = 0
7309 12:18:06.585541 [0] MAX Duty = 5093%(X100), DQS PI = 26
7310 12:18:06.589009 [0] MIN Duty = 4813%(X100), DQS PI = 50
7311 12:18:06.591920 [0] AVG Duty = 4953%(X100)
7312 12:18:06.592407
7313 12:18:06.592780 ==DQM 1 ==
7314 12:18:06.595514 Final DQM duty delay cell = 0
7315 12:18:06.598498 [0] MAX Duty = 5249%(X100), DQS PI = 28
7316 12:18:06.602194 [0] MIN Duty = 5000%(X100), DQS PI = 20
7317 12:18:06.605511 [0] AVG Duty = 5124%(X100)
7318 12:18:06.605968
7319 12:18:06.608563 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7320 12:18:06.609088
7321 12:18:06.612122 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7322 12:18:06.615237 [DutyScan_Calibration_Flow] ====Done====
7323 12:18:06.615679
7324 12:18:06.618412 [DutyScan_Calibration_Flow] k_type=2
7325 12:18:06.636310
7326 12:18:06.636881 ==DQ 0 ==
7327 12:18:06.639202 Final DQ duty delay cell = 0
7328 12:18:06.642859 [0] MAX Duty = 5124%(X100), DQS PI = 34
7329 12:18:06.646355 [0] MIN Duty = 5000%(X100), DQS PI = 0
7330 12:18:06.646863 [0] AVG Duty = 5062%(X100)
7331 12:18:06.647258
7332 12:18:06.649582 ==DQ 1 ==
7333 12:18:06.652433 Final DQ duty delay cell = 0
7334 12:18:06.656014 [0] MAX Duty = 4969%(X100), DQS PI = 44
7335 12:18:06.659261 [0] MIN Duty = 4875%(X100), DQS PI = 10
7336 12:18:06.659693 [0] AVG Duty = 4922%(X100)
7337 12:18:06.660060
7338 12:18:06.662790 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7339 12:18:06.666022
7340 12:18:06.669171 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7341 12:18:06.672608 [DutyScan_Calibration_Flow] ====Done====
7342 12:18:06.673098 ==
7343 12:18:06.675864 Dram Type= 6, Freq= 0, CH_1, rank 0
7344 12:18:06.679289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7345 12:18:06.679722 ==
7346 12:18:06.682635 [Duty_Offset_Calibration]
7347 12:18:06.683063 B0:0 B1:-1 CA:2
7348 12:18:06.683413
7349 12:18:06.685426 [DutyScan_Calibration_Flow] k_type=0
7350 12:18:06.695930
7351 12:18:06.696347 ==CLK 0==
7352 12:18:06.699557 Final CLK duty delay cell = 0
7353 12:18:06.702790 [0] MAX Duty = 5156%(X100), DQS PI = 10
7354 12:18:06.706084 [0] MIN Duty = 4906%(X100), DQS PI = 46
7355 12:18:06.709446 [0] AVG Duty = 5031%(X100)
7356 12:18:06.709962
7357 12:18:06.712838 CH1 CLK Duty spec in!! Max-Min= 250%
7358 12:18:06.716226 [DutyScan_Calibration_Flow] ====Done====
7359 12:18:06.716648
7360 12:18:06.719192 [DutyScan_Calibration_Flow] k_type=1
7361 12:18:06.735985
7362 12:18:06.736420 ==DQS 0 ==
7363 12:18:06.739255 Final DQS duty delay cell = 0
7364 12:18:06.742530 [0] MAX Duty = 5124%(X100), DQS PI = 26
7365 12:18:06.745763 [0] MIN Duty = 5000%(X100), DQS PI = 0
7366 12:18:06.746185 [0] AVG Duty = 5062%(X100)
7367 12:18:06.749105
7368 12:18:06.749526 ==DQS 1 ==
7369 12:18:06.752236 Final DQS duty delay cell = 0
7370 12:18:06.755639 [0] MAX Duty = 5187%(X100), DQS PI = 0
7371 12:18:06.758944 [0] MIN Duty = 4844%(X100), DQS PI = 34
7372 12:18:06.759361 [0] AVG Duty = 5015%(X100)
7373 12:18:06.762498
7374 12:18:06.766001 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7375 12:18:06.766441
7376 12:18:06.768871 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7377 12:18:06.772423 [DutyScan_Calibration_Flow] ====Done====
7378 12:18:06.773012
7379 12:18:06.775742 [DutyScan_Calibration_Flow] k_type=3
7380 12:18:06.793501
7381 12:18:06.793919 ==DQM 0 ==
7382 12:18:06.797062 Final DQM duty delay cell = 4
7383 12:18:06.800193 [4] MAX Duty = 5125%(X100), DQS PI = 8
7384 12:18:06.803750 [4] MIN Duty = 5000%(X100), DQS PI = 30
7385 12:18:06.804350 [4] AVG Duty = 5062%(X100)
7386 12:18:06.807060
7387 12:18:06.807482 ==DQM 1 ==
7388 12:18:06.810269 Final DQM duty delay cell = 0
7389 12:18:06.813558 [0] MAX Duty = 5281%(X100), DQS PI = 58
7390 12:18:06.816775 [0] MIN Duty = 4907%(X100), DQS PI = 34
7391 12:18:06.817283 [0] AVG Duty = 5094%(X100)
7392 12:18:06.820179
7393 12:18:06.823590 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7394 12:18:06.824099
7395 12:18:06.826962 CH1 DQM 1 Duty spec in!! Max-Min= 374%
7396 12:18:06.830196 [DutyScan_Calibration_Flow] ====Done====
7397 12:18:06.830637
7398 12:18:06.833482 [DutyScan_Calibration_Flow] k_type=2
7399 12:18:06.850341
7400 12:18:06.850854 ==DQ 0 ==
7401 12:18:06.854028 Final DQ duty delay cell = 0
7402 12:18:06.856972 [0] MAX Duty = 5093%(X100), DQS PI = 20
7403 12:18:06.860415 [0] MIN Duty = 4969%(X100), DQS PI = 48
7404 12:18:06.860859 [0] AVG Duty = 5031%(X100)
7405 12:18:06.861269
7406 12:18:06.863539 ==DQ 1 ==
7407 12:18:06.867302 Final DQ duty delay cell = 0
7408 12:18:06.870346 [0] MAX Duty = 5062%(X100), DQS PI = 4
7409 12:18:06.873473 [0] MIN Duty = 4813%(X100), DQS PI = 34
7410 12:18:06.873910 [0] AVG Duty = 4937%(X100)
7411 12:18:06.874279
7412 12:18:06.876779 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7413 12:18:06.880633
7414 12:18:06.883612 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7415 12:18:06.886583 [DutyScan_Calibration_Flow] ====Done====
7416 12:18:06.890550 nWR fixed to 30
7417 12:18:06.890987 [ModeRegInit_LP4] CH0 RK0
7418 12:18:06.893576 [ModeRegInit_LP4] CH0 RK1
7419 12:18:06.896806 [ModeRegInit_LP4] CH1 RK0
7420 12:18:06.897279 [ModeRegInit_LP4] CH1 RK1
7421 12:18:06.900186 match AC timing 5
7422 12:18:06.903591 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7423 12:18:06.906958 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7424 12:18:06.913449 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7425 12:18:06.916766 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7426 12:18:06.923367 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7427 12:18:06.923861 [MiockJmeterHQA]
7428 12:18:06.924207
7429 12:18:06.926862 [DramcMiockJmeter] u1RxGatingPI = 0
7430 12:18:06.930067 0 : 4257, 4027
7431 12:18:06.930529 4 : 4367, 4142
7432 12:18:06.930899 8 : 4252, 4027
7433 12:18:06.933525 12 : 4252, 4026
7434 12:18:06.933893 16 : 4368, 4142
7435 12:18:06.936813 20 : 4252, 4027
7436 12:18:06.937284 24 : 4255, 4030
7437 12:18:06.939981 28 : 4254, 4029
7438 12:18:06.940484 32 : 4363, 4137
7439 12:18:06.943287 36 : 4363, 4137
7440 12:18:06.943784 40 : 4252, 4027
7441 12:18:06.944182 44 : 4255, 4029
7442 12:18:06.946781 48 : 4254, 4029
7443 12:18:06.947229 52 : 4252, 4027
7444 12:18:06.950118 56 : 4254, 4029
7445 12:18:06.950551 60 : 4252, 4029
7446 12:18:06.953502 64 : 4250, 4027
7447 12:18:06.953931 68 : 4252, 4030
7448 12:18:06.956517 72 : 4250, 4027
7449 12:18:06.956924 76 : 4252, 4029
7450 12:18:06.957350 80 : 4252, 4029
7451 12:18:06.960119 84 : 4361, 4137
7452 12:18:06.960673 88 : 4360, 3766
7453 12:18:06.963624 92 : 4361, 0
7454 12:18:06.964063 96 : 4250, 0
7455 12:18:06.964430 100 : 4361, 0
7456 12:18:06.966574 104 : 4250, 0
7457 12:18:06.967032 108 : 4250, 0
7458 12:18:06.970122 112 : 4252, 0
7459 12:18:06.970581 116 : 4250, 0
7460 12:18:06.970933 120 : 4250, 0
7461 12:18:06.973216 124 : 4361, 0
7462 12:18:06.973671 128 : 4249, 0
7463 12:18:06.974027 132 : 4250, 0
7464 12:18:06.976658 136 : 4250, 0
7465 12:18:06.977155 140 : 4254, 0
7466 12:18:06.979808 144 : 4360, 0
7467 12:18:06.980245 148 : 4250, 0
7468 12:18:06.980609 152 : 4360, 0
7469 12:18:06.983050 156 : 4250, 0
7470 12:18:06.983508 160 : 4250, 0
7471 12:18:06.986675 164 : 4250, 0
7472 12:18:06.987112 168 : 4250, 0
7473 12:18:06.987478 172 : 4252, 0
7474 12:18:06.990030 176 : 4361, 0
7475 12:18:06.990468 180 : 4360, 0
7476 12:18:06.993317 184 : 4250, 0
7477 12:18:06.993879 188 : 4250, 0
7478 12:18:06.994368 192 : 4254, 0
7479 12:18:06.996533 196 : 4250, 0
7480 12:18:06.996992 200 : 4361, 6
7481 12:18:06.999949 204 : 4250, 2462
7482 12:18:07.000379 208 : 4360, 4137
7483 12:18:07.000716 212 : 4250, 4027
7484 12:18:07.003124 216 : 4250, 4027
7485 12:18:07.003566 220 : 4363, 4140
7486 12:18:07.006877 224 : 4250, 4026
7487 12:18:07.007306 228 : 4250, 4027
7488 12:18:07.010310 232 : 4250, 4027
7489 12:18:07.010740 236 : 4252, 4030
7490 12:18:07.013389 240 : 4249, 4027
7491 12:18:07.013927 244 : 4361, 4137
7492 12:18:07.016639 248 : 4361, 4137
7493 12:18:07.017244 252 : 4250, 4027
7494 12:18:07.019879 256 : 4250, 4027
7495 12:18:07.020305 260 : 4250, 4026
7496 12:18:07.023275 264 : 4250, 4027
7497 12:18:07.023705 268 : 4250, 4027
7498 12:18:07.024046 272 : 4363, 4140
7499 12:18:07.026811 276 : 4250, 4026
7500 12:18:07.027402 280 : 4250, 4027
7501 12:18:07.029629 284 : 4250, 4027
7502 12:18:07.030032 288 : 4252, 4030
7503 12:18:07.032843 292 : 4250, 4027
7504 12:18:07.033436 296 : 4361, 4137
7505 12:18:07.036611 300 : 4361, 4137
7506 12:18:07.037145 304 : 4250, 4027
7507 12:18:07.039936 308 : 4249, 4027
7508 12:18:07.040500 312 : 4250, 3961
7509 12:18:07.043348 316 : 4250, 2274
7510 12:18:07.043913 320 : 4250, 12
7511 12:18:07.044401
7512 12:18:07.046284 MIOCK jitter meter ch=0
7513 12:18:07.046743
7514 12:18:07.049559 1T = (320-92) = 228 dly cells
7515 12:18:07.052873 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7516 12:18:07.053493 ==
7517 12:18:07.056531 Dram Type= 6, Freq= 0, CH_0, rank 0
7518 12:18:07.062830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7519 12:18:07.063346 ==
7520 12:18:07.066265 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7521 12:18:07.072729 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7522 12:18:07.075913 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7523 12:18:07.082929 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7524 12:18:07.090745 [CA 0] Center 42 (12~73) winsize 62
7525 12:18:07.094044 [CA 1] Center 43 (13~73) winsize 61
7526 12:18:07.097192 [CA 2] Center 38 (8~68) winsize 61
7527 12:18:07.100296 [CA 3] Center 37 (8~67) winsize 60
7528 12:18:07.104212 [CA 4] Center 36 (6~66) winsize 61
7529 12:18:07.107426 [CA 5] Center 35 (5~65) winsize 61
7530 12:18:07.107868
7531 12:18:07.110804 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7532 12:18:07.111321
7533 12:18:07.113923 [CATrainingPosCal] consider 1 rank data
7534 12:18:07.117141 u2DelayCellTimex100 = 285/100 ps
7535 12:18:07.120786 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7536 12:18:07.127751 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7537 12:18:07.130539 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7538 12:18:07.133965 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7539 12:18:07.137177 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7540 12:18:07.140676 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7541 12:18:07.141137
7542 12:18:07.143996 CA PerBit enable=1, Macro0, CA PI delay=35
7543 12:18:07.144418
7544 12:18:07.147009 [CBTSetCACLKResult] CA Dly = 35
7545 12:18:07.150341 CS Dly: 9 (0~40)
7546 12:18:07.153512 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7547 12:18:07.157355 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7548 12:18:07.157925 ==
7549 12:18:07.160070 Dram Type= 6, Freq= 0, CH_0, rank 1
7550 12:18:07.163952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 12:18:07.164376 ==
7552 12:18:07.170308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7553 12:18:07.173518 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7554 12:18:07.180187 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7555 12:18:07.183511 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7556 12:18:07.194042 [CA 0] Center 43 (13~74) winsize 62
7557 12:18:07.197051 [CA 1] Center 43 (13~73) winsize 61
7558 12:18:07.200563 [CA 2] Center 38 (9~68) winsize 60
7559 12:18:07.203610 [CA 3] Center 38 (9~68) winsize 60
7560 12:18:07.207252 [CA 4] Center 36 (7~66) winsize 60
7561 12:18:07.210744 [CA 5] Center 36 (6~66) winsize 61
7562 12:18:07.211307
7563 12:18:07.213981 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7564 12:18:07.214448
7565 12:18:07.217244 [CATrainingPosCal] consider 2 rank data
7566 12:18:07.220422 u2DelayCellTimex100 = 285/100 ps
7567 12:18:07.223509 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7568 12:18:07.230254 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7569 12:18:07.233584 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7570 12:18:07.236807 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7571 12:18:07.240503 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7572 12:18:07.243831 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7573 12:18:07.244294
7574 12:18:07.246933 CA PerBit enable=1, Macro0, CA PI delay=35
7575 12:18:07.247386
7576 12:18:07.250426 [CBTSetCACLKResult] CA Dly = 35
7577 12:18:07.253900 CS Dly: 10 (0~43)
7578 12:18:07.256772 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7579 12:18:07.260208 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7580 12:18:07.260673
7581 12:18:07.263554 ----->DramcWriteLeveling(PI) begin...
7582 12:18:07.264057 ==
7583 12:18:07.266849 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 12:18:07.273801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7585 12:18:07.274351 ==
7586 12:18:07.276687 Write leveling (Byte 0): 36 => 36
7587 12:18:07.277148 Write leveling (Byte 1): 32 => 32
7588 12:18:07.280217 DramcWriteLeveling(PI) end<-----
7589 12:18:07.280698
7590 12:18:07.281139 ==
7591 12:18:07.283450 Dram Type= 6, Freq= 0, CH_0, rank 0
7592 12:18:07.290644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7593 12:18:07.291072 ==
7594 12:18:07.293738 [Gating] SW mode calibration
7595 12:18:07.300244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7596 12:18:07.303535 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7597 12:18:07.310385 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 12:18:07.313458 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 12:18:07.316780 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7600 12:18:07.655761 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7601 12:18:07.656854 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7602 12:18:07.657327 1 4 20 | B1->B0 | 3231 3434 | 1 1 | (0 0) (1 1)
7603 12:18:07.657711 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7604 12:18:07.658027 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 12:18:07.658349 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 12:18:07.658685 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 12:18:07.659025 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
7608 12:18:07.659348 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7609 12:18:07.659686 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7610 12:18:07.659975 1 5 20 | B1->B0 | 2d2d 2323 | 1 0 | (0 1) (0 0)
7611 12:18:07.660393 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7612 12:18:07.660849 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 12:18:07.661268 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 12:18:07.661851 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7615 12:18:07.662438 1 6 8 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7616 12:18:07.663039 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7617 12:18:07.663624 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
7618 12:18:07.664232 1 6 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7619 12:18:07.664840 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7620 12:18:07.665483 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 12:18:07.666104 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 12:18:07.666716 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 12:18:07.667326 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7624 12:18:07.667938 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7625 12:18:07.668550 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7626 12:18:07.669162 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7627 12:18:07.669779 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:18:07.670387 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:18:07.670999 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 12:18:07.671604 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 12:18:07.672220 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 12:18:07.672820 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 12:18:07.673424 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 12:18:07.674036 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 12:18:07.674647 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:18:07.675248 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:18:07.675772 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:18:07.676247 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:18:07.676716 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:18:07.677254 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7641 12:18:07.677731 Total UI for P1: 0, mck2ui 16
7642 12:18:07.678278 best dqsien dly found for B0: ( 1, 9, 10)
7643 12:18:07.678726 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 12:18:07.679175 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7645 12:18:07.679666 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 12:18:07.680136 Total UI for P1: 0, mck2ui 16
7647 12:18:07.680576 best dqsien dly found for B1: ( 1, 9, 20)
7648 12:18:07.681047 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7649 12:18:07.681355 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7650 12:18:07.681690
7651 12:18:07.681980 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7652 12:18:07.682301 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7653 12:18:07.682588 [Gating] SW calibration Done
7654 12:18:07.682914 ==
7655 12:18:07.683361 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 12:18:07.683811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 12:18:07.684256 ==
7658 12:18:07.684695 RX Vref Scan: 0
7659 12:18:07.685154
7660 12:18:07.685476 RX Vref 0 -> 0, step: 1
7661 12:18:07.685708
7662 12:18:07.685914 RX Delay 0 -> 252, step: 8
7663 12:18:07.686138 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7664 12:18:07.686451 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7665 12:18:07.686766 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7666 12:18:07.687070 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7667 12:18:07.687374 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7668 12:18:07.687687 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7669 12:18:07.688006 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7670 12:18:07.688363 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7671 12:18:07.688698 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7672 12:18:07.689015 iDelay=200, Bit 9, Center 111 (64 ~ 159) 96
7673 12:18:07.689231 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7674 12:18:07.689444 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7675 12:18:07.689664 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7676 12:18:07.689868 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7677 12:18:07.690081 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7678 12:18:07.690282 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7679 12:18:07.690484 ==
7680 12:18:07.690696 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 12:18:07.690929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 12:18:07.691159 ==
7683 12:18:07.691395 DQS Delay:
7684 12:18:07.691630 DQS0 = 0, DQS1 = 0
7685 12:18:07.691865 DQM Delay:
7686 12:18:07.692100 DQM0 = 138, DQM1 = 125
7687 12:18:07.692328 DQ Delay:
7688 12:18:07.692564 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7689 12:18:07.692795 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7690 12:18:07.693033 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
7691 12:18:07.693210 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7692 12:18:07.693367
7693 12:18:07.693519
7694 12:18:07.693670 ==
7695 12:18:07.693831 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 12:18:07.693984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 12:18:07.694135 ==
7698 12:18:07.694342
7699 12:18:07.694511
7700 12:18:07.694663 TX Vref Scan disable
7701 12:18:07.694814 == TX Byte 0 ==
7702 12:18:07.694966 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7703 12:18:07.695127 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7704 12:18:07.695279 == TX Byte 1 ==
7705 12:18:07.710386 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7706 12:18:07.710857 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7707 12:18:07.710996 ==
7708 12:18:07.711157 Dram Type= 6, Freq= 0, CH_0, rank 0
7709 12:18:07.711275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7710 12:18:07.711385 ==
7711 12:18:07.711491
7712 12:18:07.711629 TX Vref early break, caculate TX vref
7713 12:18:07.711741 TX Vref=16, minBit 7, minWin=22, winSum=376
7714 12:18:07.711848 TX Vref=18, minBit 6, minWin=23, winSum=390
7715 12:18:07.713235 TX Vref=20, minBit 5, minWin=24, winSum=398
7716 12:18:07.716608 TX Vref=22, minBit 8, minWin=24, winSum=409
7717 12:18:07.719913 TX Vref=24, minBit 2, minWin=25, winSum=415
7718 12:18:07.726410 TX Vref=26, minBit 0, minWin=26, winSum=425
7719 12:18:07.729557 TX Vref=28, minBit 0, minWin=25, winSum=425
7720 12:18:07.733455 TX Vref=30, minBit 0, minWin=26, winSum=419
7721 12:18:07.736578 TX Vref=32, minBit 2, minWin=24, winSum=407
7722 12:18:07.739862 TX Vref=34, minBit 7, minWin=24, winSum=397
7723 12:18:07.746223 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 26
7724 12:18:07.746681
7725 12:18:07.749677 Final TX Range 0 Vref 26
7726 12:18:07.750300
7727 12:18:07.750837 ==
7728 12:18:07.753399 Dram Type= 6, Freq= 0, CH_0, rank 0
7729 12:18:07.756750 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7730 12:18:07.757221 ==
7731 12:18:07.757561
7732 12:18:07.757872
7733 12:18:07.759929 TX Vref Scan disable
7734 12:18:07.766702 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7735 12:18:07.767131 == TX Byte 0 ==
7736 12:18:07.769972 u2DelayCellOfst[0]=17 cells (5 PI)
7737 12:18:07.773027 u2DelayCellOfst[1]=17 cells (5 PI)
7738 12:18:07.776469 u2DelayCellOfst[2]=13 cells (4 PI)
7739 12:18:07.779861 u2DelayCellOfst[3]=17 cells (5 PI)
7740 12:18:07.783230 u2DelayCellOfst[4]=10 cells (3 PI)
7741 12:18:07.786243 u2DelayCellOfst[5]=0 cells (0 PI)
7742 12:18:07.789590 u2DelayCellOfst[6]=20 cells (6 PI)
7743 12:18:07.792782 u2DelayCellOfst[7]=17 cells (5 PI)
7744 12:18:07.796139 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7745 12:18:07.799148 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7746 12:18:07.802808 == TX Byte 1 ==
7747 12:18:07.806112 u2DelayCellOfst[8]=3 cells (1 PI)
7748 12:18:07.806817 u2DelayCellOfst[9]=0 cells (0 PI)
7749 12:18:07.809375 u2DelayCellOfst[10]=10 cells (3 PI)
7750 12:18:07.812753 u2DelayCellOfst[11]=3 cells (1 PI)
7751 12:18:07.815865 u2DelayCellOfst[12]=13 cells (4 PI)
7752 12:18:07.819109 u2DelayCellOfst[13]=10 cells (3 PI)
7753 12:18:07.822765 u2DelayCellOfst[14]=13 cells (4 PI)
7754 12:18:07.826009 u2DelayCellOfst[15]=10 cells (3 PI)
7755 12:18:07.829063 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7756 12:18:07.835759 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7757 12:18:07.836266 DramC Write-DBI on
7758 12:18:07.836817 ==
7759 12:18:07.839509 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 12:18:07.846020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 12:18:07.846537 ==
7762 12:18:07.846722
7763 12:18:07.846854
7764 12:18:07.846957 TX Vref Scan disable
7765 12:18:07.849553 == TX Byte 0 ==
7766 12:18:07.852802 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7767 12:18:07.856387 == TX Byte 1 ==
7768 12:18:07.859676 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7769 12:18:07.859786 DramC Write-DBI off
7770 12:18:07.862701
7771 12:18:07.862791 [DATLAT]
7772 12:18:07.862859 Freq=1600, CH0 RK0
7773 12:18:07.862926
7774 12:18:07.866441 DATLAT Default: 0xf
7775 12:18:07.866538 0, 0xFFFF, sum = 0
7776 12:18:07.869375 1, 0xFFFF, sum = 0
7777 12:18:07.869461 2, 0xFFFF, sum = 0
7778 12:18:07.873147 3, 0xFFFF, sum = 0
7779 12:18:07.875862 4, 0xFFFF, sum = 0
7780 12:18:07.875936 5, 0xFFFF, sum = 0
7781 12:18:07.879825 6, 0xFFFF, sum = 0
7782 12:18:07.879926 7, 0xFFFF, sum = 0
7783 12:18:07.882507 8, 0xFFFF, sum = 0
7784 12:18:07.882607 9, 0xFFFF, sum = 0
7785 12:18:07.886305 10, 0xFFFF, sum = 0
7786 12:18:07.886405 11, 0xFFFF, sum = 0
7787 12:18:07.889258 12, 0xFFFF, sum = 0
7788 12:18:07.889339 13, 0xFFFF, sum = 0
7789 12:18:07.892579 14, 0x0, sum = 1
7790 12:18:07.892685 15, 0x0, sum = 2
7791 12:18:07.896048 16, 0x0, sum = 3
7792 12:18:07.896127 17, 0x0, sum = 4
7793 12:18:07.899264 best_step = 15
7794 12:18:07.899347
7795 12:18:07.899409 ==
7796 12:18:07.902695 Dram Type= 6, Freq= 0, CH_0, rank 0
7797 12:18:07.905943 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7798 12:18:07.906043 ==
7799 12:18:07.906141 RX Vref Scan: 1
7800 12:18:07.909302
7801 12:18:07.909376 Set Vref Range= 24 -> 127
7802 12:18:07.909439
7803 12:18:07.912788 RX Vref 24 -> 127, step: 1
7804 12:18:07.912891
7805 12:18:07.916017 RX Delay 19 -> 252, step: 4
7806 12:18:07.916124
7807 12:18:07.919682 Set Vref, RX VrefLevel [Byte0]: 24
7808 12:18:07.922726 [Byte1]: 24
7809 12:18:07.922834
7810 12:18:07.926491 Set Vref, RX VrefLevel [Byte0]: 25
7811 12:18:07.929295 [Byte1]: 25
7812 12:18:07.929367
7813 12:18:07.932802 Set Vref, RX VrefLevel [Byte0]: 26
7814 12:18:07.935820 [Byte1]: 26
7815 12:18:07.939796
7816 12:18:07.939891 Set Vref, RX VrefLevel [Byte0]: 27
7817 12:18:07.943120 [Byte1]: 27
7818 12:18:07.947251
7819 12:18:07.947325 Set Vref, RX VrefLevel [Byte0]: 28
7820 12:18:07.950781 [Byte1]: 28
7821 12:18:07.954839
7822 12:18:07.954909 Set Vref, RX VrefLevel [Byte0]: 29
7823 12:18:07.957993 [Byte1]: 29
7824 12:18:07.962245
7825 12:18:07.962316 Set Vref, RX VrefLevel [Byte0]: 30
7826 12:18:07.965573 [Byte1]: 30
7827 12:18:07.970145
7828 12:18:07.970216 Set Vref, RX VrefLevel [Byte0]: 31
7829 12:18:07.973377 [Byte1]: 31
7830 12:18:07.977858
7831 12:18:07.977928 Set Vref, RX VrefLevel [Byte0]: 32
7832 12:18:07.980981 [Byte1]: 32
7833 12:18:07.985229
7834 12:18:07.985303 Set Vref, RX VrefLevel [Byte0]: 33
7835 12:18:07.988419 [Byte1]: 33
7836 12:18:07.992591
7837 12:18:07.992664 Set Vref, RX VrefLevel [Byte0]: 34
7838 12:18:07.996028 [Byte1]: 34
7839 12:18:08.000344
7840 12:18:08.000413 Set Vref, RX VrefLevel [Byte0]: 35
7841 12:18:08.003432 [Byte1]: 35
7842 12:18:08.007857
7843 12:18:08.007925 Set Vref, RX VrefLevel [Byte0]: 36
7844 12:18:08.011256 [Byte1]: 36
7845 12:18:08.015343
7846 12:18:08.015416 Set Vref, RX VrefLevel [Byte0]: 37
7847 12:18:08.019047 [Byte1]: 37
7848 12:18:08.022742
7849 12:18:08.022811 Set Vref, RX VrefLevel [Byte0]: 38
7850 12:18:08.026067 [Byte1]: 38
7851 12:18:08.030373
7852 12:18:08.030448 Set Vref, RX VrefLevel [Byte0]: 39
7853 12:18:08.033828 [Byte1]: 39
7854 12:18:08.038354
7855 12:18:08.038433 Set Vref, RX VrefLevel [Byte0]: 40
7856 12:18:08.041458 [Byte1]: 40
7857 12:18:08.046042
7858 12:18:08.046185 Set Vref, RX VrefLevel [Byte0]: 41
7859 12:18:08.049100 [Byte1]: 41
7860 12:18:08.053323
7861 12:18:08.053470 Set Vref, RX VrefLevel [Byte0]: 42
7862 12:18:08.056557 [Byte1]: 42
7863 12:18:08.061037
7864 12:18:08.061181 Set Vref, RX VrefLevel [Byte0]: 43
7865 12:18:08.063973 [Byte1]: 43
7866 12:18:08.068516
7867 12:18:08.068602 Set Vref, RX VrefLevel [Byte0]: 44
7868 12:18:08.071675 [Byte1]: 44
7869 12:18:08.075869
7870 12:18:08.075966 Set Vref, RX VrefLevel [Byte0]: 45
7871 12:18:08.079283 [Byte1]: 45
7872 12:18:08.083671
7873 12:18:08.083763 Set Vref, RX VrefLevel [Byte0]: 46
7874 12:18:08.086885 [Byte1]: 46
7875 12:18:08.091355
7876 12:18:08.091432 Set Vref, RX VrefLevel [Byte0]: 47
7877 12:18:08.094204 [Byte1]: 47
7878 12:18:08.098984
7879 12:18:08.099073 Set Vref, RX VrefLevel [Byte0]: 48
7880 12:18:08.101905 [Byte1]: 48
7881 12:18:08.106147
7882 12:18:08.106222 Set Vref, RX VrefLevel [Byte0]: 49
7883 12:18:08.109631 [Byte1]: 49
7884 12:18:08.114038
7885 12:18:08.114114 Set Vref, RX VrefLevel [Byte0]: 50
7886 12:18:08.117139 [Byte1]: 50
7887 12:18:08.121329
7888 12:18:08.121437 Set Vref, RX VrefLevel [Byte0]: 51
7889 12:18:08.124597 [Byte1]: 51
7890 12:18:08.129092
7891 12:18:08.129174 Set Vref, RX VrefLevel [Byte0]: 52
7892 12:18:08.132262 [Byte1]: 52
7893 12:18:08.136523
7894 12:18:08.136606 Set Vref, RX VrefLevel [Byte0]: 53
7895 12:18:08.139605 [Byte1]: 53
7896 12:18:08.144002
7897 12:18:08.144084 Set Vref, RX VrefLevel [Byte0]: 54
7898 12:18:08.147363 [Byte1]: 54
7899 12:18:08.151979
7900 12:18:08.152066 Set Vref, RX VrefLevel [Byte0]: 55
7901 12:18:08.155307 [Byte1]: 55
7902 12:18:08.159561
7903 12:18:08.159637 Set Vref, RX VrefLevel [Byte0]: 56
7904 12:18:08.162461 [Byte1]: 56
7905 12:18:08.166739
7906 12:18:08.166842 Set Vref, RX VrefLevel [Byte0]: 57
7907 12:18:08.170186 [Byte1]: 57
7908 12:18:08.174337
7909 12:18:08.174410 Set Vref, RX VrefLevel [Byte0]: 58
7910 12:18:08.178034 [Byte1]: 58
7911 12:18:08.181743
7912 12:18:08.185480 Set Vref, RX VrefLevel [Byte0]: 59
7913 12:18:08.185553 [Byte1]: 59
7914 12:18:08.189740
7915 12:18:08.189813 Set Vref, RX VrefLevel [Byte0]: 60
7916 12:18:08.192934 [Byte1]: 60
7917 12:18:08.197116
7918 12:18:08.197188 Set Vref, RX VrefLevel [Byte0]: 61
7919 12:18:08.200737 [Byte1]: 61
7920 12:18:08.204813
7921 12:18:08.204913 Set Vref, RX VrefLevel [Byte0]: 62
7922 12:18:08.208176 [Byte1]: 62
7923 12:18:08.212462
7924 12:18:08.212534 Set Vref, RX VrefLevel [Byte0]: 63
7925 12:18:08.215737 [Byte1]: 63
7926 12:18:08.219652
7927 12:18:08.219751 Set Vref, RX VrefLevel [Byte0]: 64
7928 12:18:08.222935 [Byte1]: 64
7929 12:18:08.227334
7930 12:18:08.227411 Set Vref, RX VrefLevel [Byte0]: 65
7931 12:18:08.230500 [Byte1]: 65
7932 12:18:08.234982
7933 12:18:08.235056 Set Vref, RX VrefLevel [Byte0]: 66
7934 12:18:08.238167 [Byte1]: 66
7935 12:18:08.242404
7936 12:18:08.242515 Set Vref, RX VrefLevel [Byte0]: 67
7937 12:18:08.245986 [Byte1]: 67
7938 12:18:08.250082
7939 12:18:08.250186 Set Vref, RX VrefLevel [Byte0]: 68
7940 12:18:08.253611 [Byte1]: 68
7941 12:18:08.257992
7942 12:18:08.258075 Set Vref, RX VrefLevel [Byte0]: 69
7943 12:18:08.260851 [Byte1]: 69
7944 12:18:08.265115
7945 12:18:08.265191 Set Vref, RX VrefLevel [Byte0]: 70
7946 12:18:08.268694 [Byte1]: 70
7947 12:18:08.272959
7948 12:18:08.273051 Set Vref, RX VrefLevel [Byte0]: 71
7949 12:18:08.275960 [Byte1]: 71
7950 12:18:08.280468
7951 12:18:08.280545 Set Vref, RX VrefLevel [Byte0]: 72
7952 12:18:08.283669 [Byte1]: 72
7953 12:18:08.287985
7954 12:18:08.288067 Set Vref, RX VrefLevel [Byte0]: 73
7955 12:18:08.291463 [Byte1]: 73
7956 12:18:08.295931
7957 12:18:08.296006 Set Vref, RX VrefLevel [Byte0]: 74
7958 12:18:08.298611 [Byte1]: 74
7959 12:18:08.303035
7960 12:18:08.303111 Set Vref, RX VrefLevel [Byte0]: 75
7961 12:18:08.306896 [Byte1]: 75
7962 12:18:08.310803
7963 12:18:08.310882 Set Vref, RX VrefLevel [Byte0]: 76
7964 12:18:08.314077 [Byte1]: 76
7965 12:18:08.318607
7966 12:18:08.318683 Set Vref, RX VrefLevel [Byte0]: 77
7967 12:18:08.321560 [Byte1]: 77
7968 12:18:08.325659
7969 12:18:08.325735 Set Vref, RX VrefLevel [Byte0]: 78
7970 12:18:08.329105 [Byte1]: 78
7971 12:18:08.333563
7972 12:18:08.333638 Final RX Vref Byte 0 = 62 to rank0
7973 12:18:08.336719 Final RX Vref Byte 1 = 61 to rank0
7974 12:18:08.339998 Final RX Vref Byte 0 = 62 to rank1
7975 12:18:08.343635 Final RX Vref Byte 1 = 61 to rank1==
7976 12:18:08.346714 Dram Type= 6, Freq= 0, CH_0, rank 0
7977 12:18:08.353280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 12:18:08.353365 ==
7979 12:18:08.353450 DQS Delay:
7980 12:18:08.356762 DQS0 = 0, DQS1 = 0
7981 12:18:08.356839 DQM Delay:
7982 12:18:08.356960 DQM0 = 136, DQM1 = 124
7983 12:18:08.359821 DQ Delay:
7984 12:18:08.363148 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7985 12:18:08.366406 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
7986 12:18:08.369535 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7987 12:18:08.373176 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7988 12:18:08.373270
7989 12:18:08.373356
7990 12:18:08.373438
7991 12:18:08.376476 [DramC_TX_OE_Calibration] TA2
7992 12:18:08.379827 Original DQ_B0 (3 6) =30, OEN = 27
7993 12:18:08.383050 Original DQ_B1 (3 6) =30, OEN = 27
7994 12:18:08.386327 24, 0x0, End_B0=24 End_B1=24
7995 12:18:08.386414 25, 0x0, End_B0=25 End_B1=25
7996 12:18:08.389643 26, 0x0, End_B0=26 End_B1=26
7997 12:18:08.393111 27, 0x0, End_B0=27 End_B1=27
7998 12:18:08.396607 28, 0x0, End_B0=28 End_B1=28
7999 12:18:08.399783 29, 0x0, End_B0=29 End_B1=29
8000 12:18:08.399870 30, 0x0, End_B0=30 End_B1=30
8001 12:18:08.403025 31, 0x4141, End_B0=30 End_B1=30
8002 12:18:08.406543 Byte0 end_step=30 best_step=27
8003 12:18:08.409738 Byte1 end_step=30 best_step=27
8004 12:18:08.412776 Byte0 TX OE(2T, 0.5T) = (3, 3)
8005 12:18:08.416485 Byte1 TX OE(2T, 0.5T) = (3, 3)
8006 12:18:08.416580
8007 12:18:08.416683
8008 12:18:08.422635 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8009 12:18:08.426167 CH0 RK0: MR19=303, MR18=1C1B
8010 12:18:08.432759 CH0_RK0: MR19=0x303, MR18=0x1C1B, DQSOSC=395, MR23=63, INC=23, DEC=15
8011 12:18:08.432841
8012 12:18:08.436049 ----->DramcWriteLeveling(PI) begin...
8013 12:18:08.436138 ==
8014 12:18:08.439258 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 12:18:08.443145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8016 12:18:08.443220 ==
8017 12:18:08.446243 Write leveling (Byte 0): 37 => 37
8018 12:18:08.449228 Write leveling (Byte 1): 29 => 29
8019 12:18:08.452430 DramcWriteLeveling(PI) end<-----
8020 12:18:08.452511
8021 12:18:08.452631 ==
8022 12:18:08.456149 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 12:18:08.459219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 12:18:08.459290 ==
8025 12:18:08.462996 [Gating] SW mode calibration
8026 12:18:08.469262 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8027 12:18:08.476096 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8028 12:18:08.478926 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 12:18:08.485998 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 12:18:08.489058 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 12:18:08.492529 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8032 12:18:08.499483 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8033 12:18:08.502850 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8034 12:18:08.505649 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 12:18:08.509115 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 12:18:08.515563 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 12:18:08.519372 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 12:18:08.522338 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8039 12:18:08.528934 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
8040 12:18:08.532320 1 5 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8041 12:18:08.535536 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 12:18:08.542500 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 12:18:08.545764 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 12:18:08.548692 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 12:18:08.555566 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 12:18:08.559156 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8047 12:18:08.562141 1 6 12 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
8048 12:18:08.568702 1 6 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8049 12:18:08.571917 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 12:18:08.575254 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 12:18:08.582357 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 12:18:08.585349 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 12:18:08.588601 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 12:18:08.595523 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 12:18:08.598959 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 12:18:08.602136 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8057 12:18:08.608565 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:18:08.612098 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:18:08.615517 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:18:08.622287 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:18:08.625190 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 12:18:08.628792 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 12:18:08.631971 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 12:18:08.638609 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 12:18:08.642044 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 12:18:08.645647 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 12:18:08.651890 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 12:18:08.655587 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 12:18:08.658712 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 12:18:08.665203 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8071 12:18:08.668640 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8072 12:18:08.671856 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8073 12:18:08.678922 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 12:18:08.681824 Total UI for P1: 0, mck2ui 16
8075 12:18:08.685493 best dqsien dly found for B0: ( 1, 9, 12)
8076 12:18:08.685569 Total UI for P1: 0, mck2ui 16
8077 12:18:08.691920 best dqsien dly found for B1: ( 1, 9, 14)
8078 12:18:08.695113 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8079 12:18:08.698329 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8080 12:18:08.698400
8081 12:18:08.701980 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8082 12:18:08.705119 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8083 12:18:08.708305 [Gating] SW calibration Done
8084 12:18:08.708399 ==
8085 12:18:08.712265 Dram Type= 6, Freq= 0, CH_0, rank 1
8086 12:18:08.715242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8087 12:18:08.715314 ==
8088 12:18:08.718656 RX Vref Scan: 0
8089 12:18:08.718729
8090 12:18:08.718791 RX Vref 0 -> 0, step: 1
8091 12:18:08.721965
8092 12:18:08.722034 RX Delay 0 -> 252, step: 8
8093 12:18:08.724934 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8094 12:18:08.731855 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8095 12:18:08.735113 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8096 12:18:08.738249 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8097 12:18:08.741907 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8098 12:18:08.745077 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8099 12:18:08.751882 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8100 12:18:08.755084 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8101 12:18:08.758237 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8102 12:18:08.761602 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8103 12:18:08.764828 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8104 12:18:08.771680 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8105 12:18:08.774726 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8106 12:18:08.778566 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8107 12:18:08.781514 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8108 12:18:08.784763 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8109 12:18:08.788149 ==
8110 12:18:08.791421 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 12:18:08.794962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 12:18:08.795040 ==
8113 12:18:08.795105 DQS Delay:
8114 12:18:08.798285 DQS0 = 0, DQS1 = 0
8115 12:18:08.798362 DQM Delay:
8116 12:18:08.801715 DQM0 = 136, DQM1 = 125
8117 12:18:08.801790 DQ Delay:
8118 12:18:08.804882 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8119 12:18:08.808222 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8120 12:18:08.811493 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8121 12:18:08.814880 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8122 12:18:08.814955
8123 12:18:08.815017
8124 12:18:08.815075 ==
8125 12:18:08.818268 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 12:18:08.824920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 12:18:08.825035 ==
8128 12:18:08.825099
8129 12:18:08.825160
8130 12:18:08.825217 TX Vref Scan disable
8131 12:18:08.828461 == TX Byte 0 ==
8132 12:18:08.831971 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8133 12:18:08.838511 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8134 12:18:08.838599 == TX Byte 1 ==
8135 12:18:08.841994 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8136 12:18:08.848576 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8137 12:18:08.848728 ==
8138 12:18:08.851652 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 12:18:08.855295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 12:18:08.855379 ==
8141 12:18:08.868325
8142 12:18:08.871892 TX Vref early break, caculate TX vref
8143 12:18:08.874980 TX Vref=16, minBit 0, minWin=23, winSum=391
8144 12:18:08.878356 TX Vref=18, minBit 0, minWin=23, winSum=398
8145 12:18:08.881841 TX Vref=20, minBit 0, minWin=25, winSum=408
8146 12:18:08.885031 TX Vref=22, minBit 0, minWin=25, winSum=416
8147 12:18:08.888887 TX Vref=24, minBit 2, minWin=25, winSum=425
8148 12:18:08.895252 TX Vref=26, minBit 0, minWin=26, winSum=431
8149 12:18:08.898453 TX Vref=28, minBit 2, minWin=26, winSum=431
8150 12:18:08.901873 TX Vref=30, minBit 0, minWin=25, winSum=422
8151 12:18:08.905185 TX Vref=32, minBit 0, minWin=25, winSum=416
8152 12:18:08.908195 TX Vref=34, minBit 2, minWin=24, winSum=405
8153 12:18:08.914798 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 26
8154 12:18:08.914881
8155 12:18:08.918242 Final TX Range 0 Vref 26
8156 12:18:08.918326
8157 12:18:08.918391 ==
8158 12:18:08.921391 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 12:18:08.924796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 12:18:08.924880 ==
8161 12:18:08.924985
8162 12:18:08.925067
8163 12:18:08.928321 TX Vref Scan disable
8164 12:18:08.935146 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8165 12:18:08.935260 == TX Byte 0 ==
8166 12:18:08.938361 u2DelayCellOfst[0]=13 cells (4 PI)
8167 12:18:08.941706 u2DelayCellOfst[1]=20 cells (6 PI)
8168 12:18:08.944831 u2DelayCellOfst[2]=13 cells (4 PI)
8169 12:18:08.948335 u2DelayCellOfst[3]=13 cells (4 PI)
8170 12:18:08.951534 u2DelayCellOfst[4]=10 cells (3 PI)
8171 12:18:08.954882 u2DelayCellOfst[5]=0 cells (0 PI)
8172 12:18:08.958101 u2DelayCellOfst[6]=20 cells (6 PI)
8173 12:18:08.961211 u2DelayCellOfst[7]=17 cells (5 PI)
8174 12:18:08.964816 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8175 12:18:08.968128 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8176 12:18:08.971352 == TX Byte 1 ==
8177 12:18:08.971428 u2DelayCellOfst[8]=0 cells (0 PI)
8178 12:18:08.974379 u2DelayCellOfst[9]=3 cells (1 PI)
8179 12:18:08.977878 u2DelayCellOfst[10]=6 cells (2 PI)
8180 12:18:08.981039 u2DelayCellOfst[11]=3 cells (1 PI)
8181 12:18:08.984712 u2DelayCellOfst[12]=13 cells (4 PI)
8182 12:18:08.987726 u2DelayCellOfst[13]=13 cells (4 PI)
8183 12:18:08.991184 u2DelayCellOfst[14]=13 cells (4 PI)
8184 12:18:08.994490 u2DelayCellOfst[15]=10 cells (3 PI)
8185 12:18:08.997710 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8186 12:18:09.004248 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8187 12:18:09.004331 DramC Write-DBI on
8188 12:18:09.004413 ==
8189 12:18:09.007848 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 12:18:09.011038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 12:18:09.014831 ==
8192 12:18:09.014909
8193 12:18:09.014993
8194 12:18:09.015068 TX Vref Scan disable
8195 12:18:09.017967 == TX Byte 0 ==
8196 12:18:09.021189 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8197 12:18:09.024973 == TX Byte 1 ==
8198 12:18:09.027974 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8199 12:18:09.031510 DramC Write-DBI off
8200 12:18:09.031588
8201 12:18:09.031667 [DATLAT]
8202 12:18:09.031744 Freq=1600, CH0 RK1
8203 12:18:09.031820
8204 12:18:09.034594 DATLAT Default: 0xf
8205 12:18:09.034671 0, 0xFFFF, sum = 0
8206 12:18:09.037766 1, 0xFFFF, sum = 0
8207 12:18:09.037847 2, 0xFFFF, sum = 0
8208 12:18:09.041570 3, 0xFFFF, sum = 0
8209 12:18:09.044639 4, 0xFFFF, sum = 0
8210 12:18:09.044720 5, 0xFFFF, sum = 0
8211 12:18:09.047934 6, 0xFFFF, sum = 0
8212 12:18:09.048008 7, 0xFFFF, sum = 0
8213 12:18:09.051543 8, 0xFFFF, sum = 0
8214 12:18:09.051629 9, 0xFFFF, sum = 0
8215 12:18:09.054717 10, 0xFFFF, sum = 0
8216 12:18:09.054796 11, 0xFFFF, sum = 0
8217 12:18:09.058167 12, 0xFFFF, sum = 0
8218 12:18:09.058246 13, 0xFFFF, sum = 0
8219 12:18:09.061227 14, 0x0, sum = 1
8220 12:18:09.061305 15, 0x0, sum = 2
8221 12:18:09.064810 16, 0x0, sum = 3
8222 12:18:09.064884 17, 0x0, sum = 4
8223 12:18:09.067908 best_step = 15
8224 12:18:09.067980
8225 12:18:09.068058 ==
8226 12:18:09.071135 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 12:18:09.074589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 12:18:09.074666 ==
8229 12:18:09.074746 RX Vref Scan: 0
8230 12:18:09.077693
8231 12:18:09.077769 RX Vref 0 -> 0, step: 1
8232 12:18:09.077847
8233 12:18:09.081266 RX Delay 11 -> 252, step: 4
8234 12:18:09.084400 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8235 12:18:09.091431 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8236 12:18:09.094500 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8237 12:18:09.097750 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8238 12:18:09.101390 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8239 12:18:09.104752 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8240 12:18:09.110931 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8241 12:18:09.114761 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8242 12:18:09.118073 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8243 12:18:09.121232 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8244 12:18:09.124589 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8245 12:18:09.130871 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8246 12:18:09.134432 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8247 12:18:09.137451 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8248 12:18:09.141161 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8249 12:18:09.144343 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8250 12:18:09.147754 ==
8251 12:18:09.147838 Dram Type= 6, Freq= 0, CH_0, rank 1
8252 12:18:09.154390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8253 12:18:09.154476 ==
8254 12:18:09.154544 DQS Delay:
8255 12:18:09.157759 DQS0 = 0, DQS1 = 0
8256 12:18:09.157842 DQM Delay:
8257 12:18:09.160988 DQM0 = 133, DQM1 = 123
8258 12:18:09.161075 DQ Delay:
8259 12:18:09.164180 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =128
8260 12:18:09.167689 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8261 12:18:09.170993 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8262 12:18:09.174276 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8263 12:18:09.174364
8264 12:18:09.174432
8265 12:18:09.174493
8266 12:18:09.177514 [DramC_TX_OE_Calibration] TA2
8267 12:18:09.180691 Original DQ_B0 (3 6) =30, OEN = 27
8268 12:18:09.184321 Original DQ_B1 (3 6) =30, OEN = 27
8269 12:18:09.187382 24, 0x0, End_B0=24 End_B1=24
8270 12:18:09.191171 25, 0x0, End_B0=25 End_B1=25
8271 12:18:09.191257 26, 0x0, End_B0=26 End_B1=26
8272 12:18:09.194276 27, 0x0, End_B0=27 End_B1=27
8273 12:18:09.197605 28, 0x0, End_B0=28 End_B1=28
8274 12:18:09.201015 29, 0x0, End_B0=29 End_B1=29
8275 12:18:09.201101 30, 0x0, End_B0=30 End_B1=30
8276 12:18:09.204084 31, 0x4545, End_B0=30 End_B1=30
8277 12:18:09.207460 Byte0 end_step=30 best_step=27
8278 12:18:09.210757 Byte1 end_step=30 best_step=27
8279 12:18:09.214134 Byte0 TX OE(2T, 0.5T) = (3, 3)
8280 12:18:09.217440 Byte1 TX OE(2T, 0.5T) = (3, 3)
8281 12:18:09.217524
8282 12:18:09.217591
8283 12:18:09.224189 [DQSOSCAuto] RK1, (LSB)MR18= 0x200d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8284 12:18:09.227414 CH0 RK1: MR19=303, MR18=200D
8285 12:18:09.233898 CH0_RK1: MR19=0x303, MR18=0x200D, DQSOSC=393, MR23=63, INC=23, DEC=15
8286 12:18:09.237706 [RxdqsGatingPostProcess] freq 1600
8287 12:18:09.240810 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8288 12:18:09.244404 best DQS0 dly(2T, 0.5T) = (1, 1)
8289 12:18:09.247199 best DQS1 dly(2T, 0.5T) = (1, 1)
8290 12:18:09.250650 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8291 12:18:09.253694 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8292 12:18:09.257378 best DQS0 dly(2T, 0.5T) = (1, 1)
8293 12:18:09.260620 best DQS1 dly(2T, 0.5T) = (1, 1)
8294 12:18:09.263972 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8295 12:18:09.267247 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8296 12:18:09.270812 Pre-setting of DQS Precalculation
8297 12:18:09.273898 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8298 12:18:09.273983 ==
8299 12:18:09.277200 Dram Type= 6, Freq= 0, CH_1, rank 0
8300 12:18:09.284131 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 12:18:09.284216 ==
8302 12:18:09.286910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 12:18:09.293597 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 12:18:09.297174 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 12:18:09.303960 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 12:18:09.311172 [CA 0] Center 41 (12~71) winsize 60
8307 12:18:09.314468 [CA 1] Center 42 (12~72) winsize 61
8308 12:18:09.317938 [CA 2] Center 38 (9~67) winsize 59
8309 12:18:09.321354 [CA 3] Center 36 (7~66) winsize 60
8310 12:18:09.324515 [CA 4] Center 37 (7~68) winsize 62
8311 12:18:09.327517 [CA 5] Center 36 (7~66) winsize 60
8312 12:18:09.327602
8313 12:18:09.331218 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8314 12:18:09.331303
8315 12:18:09.334181 [CATrainingPosCal] consider 1 rank data
8316 12:18:09.337842 u2DelayCellTimex100 = 285/100 ps
8317 12:18:09.341312 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8318 12:18:09.347570 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8319 12:18:09.350735 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8320 12:18:09.354451 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8321 12:18:09.357740 CA4 delay=37 (7~68),Diff = 1 PI (3 cell)
8322 12:18:09.361130 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8323 12:18:09.361215
8324 12:18:09.364327 CA PerBit enable=1, Macro0, CA PI delay=36
8325 12:18:09.364412
8326 12:18:09.367617 [CBTSetCACLKResult] CA Dly = 36
8327 12:18:09.370960 CS Dly: 9 (0~40)
8328 12:18:09.374112 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 12:18:09.377447 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 12:18:09.377532 ==
8331 12:18:09.380819 Dram Type= 6, Freq= 0, CH_1, rank 1
8332 12:18:09.384610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8333 12:18:09.384695 ==
8334 12:18:09.390729 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8335 12:18:09.394102 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8336 12:18:09.400897 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8337 12:18:09.404356 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8338 12:18:09.414311 [CA 0] Center 43 (14~73) winsize 60
8339 12:18:09.417688 [CA 1] Center 43 (13~73) winsize 61
8340 12:18:09.421150 [CA 2] Center 38 (9~68) winsize 60
8341 12:18:09.423988 [CA 3] Center 38 (9~67) winsize 59
8342 12:18:09.427652 [CA 4] Center 38 (9~68) winsize 60
8343 12:18:09.430778 [CA 5] Center 37 (8~67) winsize 60
8344 12:18:09.430862
8345 12:18:09.434081 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8346 12:18:09.434163
8347 12:18:09.437403 [CATrainingPosCal] consider 2 rank data
8348 12:18:09.440705 u2DelayCellTimex100 = 285/100 ps
8349 12:18:09.444390 CA0 delay=42 (14~71),Diff = 5 PI (17 cell)
8350 12:18:09.450950 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8351 12:18:09.454211 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8352 12:18:09.457462 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8353 12:18:09.460712 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8354 12:18:09.463937 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8355 12:18:09.464020
8356 12:18:09.466997 CA PerBit enable=1, Macro0, CA PI delay=37
8357 12:18:09.467079
8358 12:18:09.470411 [CBTSetCACLKResult] CA Dly = 37
8359 12:18:09.473822 CS Dly: 10 (0~43)
8360 12:18:09.477373 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8361 12:18:09.480760 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8362 12:18:09.480832
8363 12:18:09.484063 ----->DramcWriteLeveling(PI) begin...
8364 12:18:09.484162 ==
8365 12:18:09.487088 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 12:18:09.490532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 12:18:09.494034 ==
8368 12:18:09.497128 Write leveling (Byte 0): 25 => 25
8369 12:18:09.497203 Write leveling (Byte 1): 28 => 28
8370 12:18:09.500578 DramcWriteLeveling(PI) end<-----
8371 12:18:09.500680
8372 12:18:09.500741 ==
8373 12:18:09.503734 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 12:18:09.510574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 12:18:09.510660 ==
8376 12:18:09.513920 [Gating] SW mode calibration
8377 12:18:09.520370 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8378 12:18:09.523682 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8379 12:18:09.530582 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 12:18:09.533425 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 12:18:09.536860 1 4 8 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
8382 12:18:09.543705 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 12:18:09.546918 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 12:18:09.550102 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 12:18:09.556715 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 12:18:09.560021 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 12:18:09.563737 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 12:18:09.566831 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8389 12:18:09.573436 1 5 8 | B1->B0 | 2c2c 2929 | 0 1 | (0 1) (1 0)
8390 12:18:09.577193 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8391 12:18:09.580420 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 12:18:09.586758 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 12:18:09.590015 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 12:18:09.593423 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 12:18:09.599996 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 12:18:09.603619 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 12:18:09.606783 1 6 8 | B1->B0 | 3d3d 4242 | 0 0 | (0 0) (0 0)
8398 12:18:09.613322 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 12:18:09.616541 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 12:18:09.620149 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 12:18:09.626722 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 12:18:09.630170 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 12:18:09.633346 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 12:18:09.640033 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8405 12:18:09.643278 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8406 12:18:09.646596 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8407 12:18:09.653189 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:18:09.656759 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:18:09.659827 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:18:09.666407 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:18:09.669773 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:18:09.673458 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:18:09.679865 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:18:09.683297 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:18:09.686474 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 12:18:09.693089 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 12:18:09.696511 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 12:18:09.699708 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 12:18:09.702911 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 12:18:09.709714 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8421 12:18:09.713264 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 12:18:09.716552 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 12:18:09.720018 Total UI for P1: 0, mck2ui 16
8424 12:18:09.723111 best dqsien dly found for B0: ( 1, 9, 6)
8425 12:18:09.726305 Total UI for P1: 0, mck2ui 16
8426 12:18:09.729964 best dqsien dly found for B1: ( 1, 9, 8)
8427 12:18:09.732793 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8428 12:18:09.736501 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8429 12:18:09.736603
8430 12:18:09.742975 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8431 12:18:09.746212 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8432 12:18:09.749370 [Gating] SW calibration Done
8433 12:18:09.749444 ==
8434 12:18:09.752972 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 12:18:09.756230 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 12:18:09.756328 ==
8437 12:18:09.756423 RX Vref Scan: 0
8438 12:18:09.756513
8439 12:18:09.759535 RX Vref 0 -> 0, step: 1
8440 12:18:09.759632
8441 12:18:09.762972 RX Delay 0 -> 252, step: 8
8442 12:18:09.766418 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8443 12:18:09.769807 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8444 12:18:09.772918 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8445 12:18:09.779812 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8446 12:18:09.783204 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8447 12:18:09.786123 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8448 12:18:09.789628 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8449 12:18:09.792694 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8450 12:18:09.799595 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8451 12:18:09.802788 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8452 12:18:09.806072 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8453 12:18:09.809132 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8454 12:18:09.812784 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8455 12:18:09.819247 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8456 12:18:09.822709 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8457 12:18:09.825912 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8458 12:18:09.826011 ==
8459 12:18:09.829347 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 12:18:09.832917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 12:18:09.833051 ==
8462 12:18:09.835857 DQS Delay:
8463 12:18:09.835954 DQS0 = 0, DQS1 = 0
8464 12:18:09.839355 DQM Delay:
8465 12:18:09.839453 DQM0 = 137, DQM1 = 129
8466 12:18:09.839543 DQ Delay:
8467 12:18:09.845909 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8468 12:18:09.849240 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8469 12:18:09.853071 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8470 12:18:09.856322 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8471 12:18:09.856422
8472 12:18:09.856516
8473 12:18:09.856605 ==
8474 12:18:09.859795 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 12:18:09.862857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 12:18:09.862951 ==
8477 12:18:09.863039
8478 12:18:09.863125
8479 12:18:09.866373 TX Vref Scan disable
8480 12:18:09.869206 == TX Byte 0 ==
8481 12:18:09.872842 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8482 12:18:09.876333 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8483 12:18:09.879133 == TX Byte 1 ==
8484 12:18:09.882873 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8485 12:18:09.886283 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8486 12:18:09.886351 ==
8487 12:18:09.889252 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 12:18:09.892652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 12:18:09.895947 ==
8490 12:18:09.905811
8491 12:18:09.908899 TX Vref early break, caculate TX vref
8492 12:18:09.912471 TX Vref=16, minBit 10, minWin=21, winSum=370
8493 12:18:09.915835 TX Vref=18, minBit 10, minWin=22, winSum=380
8494 12:18:09.918940 TX Vref=20, minBit 10, minWin=23, winSum=390
8495 12:18:09.922229 TX Vref=22, minBit 10, minWin=23, winSum=397
8496 12:18:09.925589 TX Vref=24, minBit 10, minWin=24, winSum=407
8497 12:18:09.932627 TX Vref=26, minBit 10, minWin=25, winSum=417
8498 12:18:09.935744 TX Vref=28, minBit 8, minWin=25, winSum=415
8499 12:18:09.939182 TX Vref=30, minBit 9, minWin=24, winSum=409
8500 12:18:09.942514 TX Vref=32, minBit 9, minWin=23, winSum=395
8501 12:18:09.948850 [TxChooseVref] Worse bit 10, Min win 25, Win sum 417, Final Vref 26
8502 12:18:09.948944
8503 12:18:09.952402 Final TX Range 0 Vref 26
8504 12:18:09.952487
8505 12:18:09.952553 ==
8506 12:18:09.955874 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 12:18:09.959109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 12:18:09.959194 ==
8509 12:18:09.959261
8510 12:18:09.959323
8511 12:18:09.962225 TX Vref Scan disable
8512 12:18:09.968805 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8513 12:18:09.968892 == TX Byte 0 ==
8514 12:18:09.972409 u2DelayCellOfst[0]=13 cells (4 PI)
8515 12:18:09.975748 u2DelayCellOfst[1]=10 cells (3 PI)
8516 12:18:09.979117 u2DelayCellOfst[2]=0 cells (0 PI)
8517 12:18:09.982613 u2DelayCellOfst[3]=3 cells (1 PI)
8518 12:18:09.985420 u2DelayCellOfst[4]=6 cells (2 PI)
8519 12:18:09.988946 u2DelayCellOfst[5]=17 cells (5 PI)
8520 12:18:09.989045 u2DelayCellOfst[6]=17 cells (5 PI)
8521 12:18:09.992519 u2DelayCellOfst[7]=6 cells (2 PI)
8522 12:18:09.998840 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8523 12:18:10.002277 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8524 12:18:10.002359 == TX Byte 1 ==
8525 12:18:10.005595 u2DelayCellOfst[8]=0 cells (0 PI)
8526 12:18:10.009062 u2DelayCellOfst[9]=3 cells (1 PI)
8527 12:18:10.011927 u2DelayCellOfst[10]=10 cells (3 PI)
8528 12:18:10.015364 u2DelayCellOfst[11]=3 cells (1 PI)
8529 12:18:10.018907 u2DelayCellOfst[12]=17 cells (5 PI)
8530 12:18:10.021929 u2DelayCellOfst[13]=17 cells (5 PI)
8531 12:18:10.025213 u2DelayCellOfst[14]=20 cells (6 PI)
8532 12:18:10.028452 u2DelayCellOfst[15]=17 cells (5 PI)
8533 12:18:10.031697 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8534 12:18:10.038836 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8535 12:18:10.038920 DramC Write-DBI on
8536 12:18:10.038986 ==
8537 12:18:10.041943 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 12:18:10.045187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 12:18:10.045272 ==
8540 12:18:10.048638
8541 12:18:10.048721
8542 12:18:10.048797 TX Vref Scan disable
8543 12:18:10.051989 == TX Byte 0 ==
8544 12:18:10.055123 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8545 12:18:10.058634 == TX Byte 1 ==
8546 12:18:10.061834 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8547 12:18:10.061918 DramC Write-DBI off
8548 12:18:10.065222
8549 12:18:10.065305 [DATLAT]
8550 12:18:10.065371 Freq=1600, CH1 RK0
8551 12:18:10.065451
8552 12:18:10.068439 DATLAT Default: 0xf
8553 12:18:10.068548 0, 0xFFFF, sum = 0
8554 12:18:10.071888 1, 0xFFFF, sum = 0
8555 12:18:10.071999 2, 0xFFFF, sum = 0
8556 12:18:10.075072 3, 0xFFFF, sum = 0
8557 12:18:10.078283 4, 0xFFFF, sum = 0
8558 12:18:10.078369 5, 0xFFFF, sum = 0
8559 12:18:10.081808 6, 0xFFFF, sum = 0
8560 12:18:10.081893 7, 0xFFFF, sum = 0
8561 12:18:10.084982 8, 0xFFFF, sum = 0
8562 12:18:10.085104 9, 0xFFFF, sum = 0
8563 12:18:10.088261 10, 0xFFFF, sum = 0
8564 12:18:10.088353 11, 0xFFFF, sum = 0
8565 12:18:10.091417 12, 0xFFFF, sum = 0
8566 12:18:10.091528 13, 0xFFFF, sum = 0
8567 12:18:10.095138 14, 0x0, sum = 1
8568 12:18:10.095214 15, 0x0, sum = 2
8569 12:18:10.098114 16, 0x0, sum = 3
8570 12:18:10.098198 17, 0x0, sum = 4
8571 12:18:10.101648 best_step = 15
8572 12:18:10.101760
8573 12:18:10.101845 ==
8574 12:18:10.104819 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 12:18:10.108068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 12:18:10.108178 ==
8577 12:18:10.108273 RX Vref Scan: 1
8578 12:18:10.111691
8579 12:18:10.111800 Set Vref Range= 24 -> 127
8580 12:18:10.111902
8581 12:18:10.115105 RX Vref 24 -> 127, step: 1
8582 12:18:10.115188
8583 12:18:10.118258 RX Delay 19 -> 252, step: 4
8584 12:18:10.118341
8585 12:18:10.121426 Set Vref, RX VrefLevel [Byte0]: 24
8586 12:18:10.124813 [Byte1]: 24
8587 12:18:10.124918
8588 12:18:10.128047 Set Vref, RX VrefLevel [Byte0]: 25
8589 12:18:10.131313 [Byte1]: 25
8590 12:18:10.131390
8591 12:18:10.134554 Set Vref, RX VrefLevel [Byte0]: 26
8592 12:18:10.138033 [Byte1]: 26
8593 12:18:10.142027
8594 12:18:10.142111 Set Vref, RX VrefLevel [Byte0]: 27
8595 12:18:10.145172 [Byte1]: 27
8596 12:18:10.149508
8597 12:18:10.149591 Set Vref, RX VrefLevel [Byte0]: 28
8598 12:18:10.152862 [Byte1]: 28
8599 12:18:10.157037
8600 12:18:10.157117 Set Vref, RX VrefLevel [Byte0]: 29
8601 12:18:10.160115 [Byte1]: 29
8602 12:18:10.164627
8603 12:18:10.164735 Set Vref, RX VrefLevel [Byte0]: 30
8604 12:18:10.167921 [Byte1]: 30
8605 12:18:10.172381
8606 12:18:10.172458 Set Vref, RX VrefLevel [Byte0]: 31
8607 12:18:10.175472 [Byte1]: 31
8608 12:18:10.179638
8609 12:18:10.179747 Set Vref, RX VrefLevel [Byte0]: 32
8610 12:18:10.182983 [Byte1]: 32
8611 12:18:10.187685
8612 12:18:10.187768 Set Vref, RX VrefLevel [Byte0]: 33
8613 12:18:10.190783 [Byte1]: 33
8614 12:18:10.194998
8615 12:18:10.195081 Set Vref, RX VrefLevel [Byte0]: 34
8616 12:18:10.198092 [Byte1]: 34
8617 12:18:10.202671
8618 12:18:10.202754 Set Vref, RX VrefLevel [Byte0]: 35
8619 12:18:10.205895 [Byte1]: 35
8620 12:18:10.210058
8621 12:18:10.210142 Set Vref, RX VrefLevel [Byte0]: 36
8622 12:18:10.213261 [Byte1]: 36
8623 12:18:10.217707
8624 12:18:10.217791 Set Vref, RX VrefLevel [Byte0]: 37
8625 12:18:10.221049 [Byte1]: 37
8626 12:18:10.225282
8627 12:18:10.225373 Set Vref, RX VrefLevel [Byte0]: 38
8628 12:18:10.228630 [Byte1]: 38
8629 12:18:10.232806
8630 12:18:10.232910 Set Vref, RX VrefLevel [Byte0]: 39
8631 12:18:10.236134 [Byte1]: 39
8632 12:18:10.240355
8633 12:18:10.240464 Set Vref, RX VrefLevel [Byte0]: 40
8634 12:18:10.243535 [Byte1]: 40
8635 12:18:10.247980
8636 12:18:10.248063 Set Vref, RX VrefLevel [Byte0]: 41
8637 12:18:10.251062 [Byte1]: 41
8638 12:18:10.255696
8639 12:18:10.255805 Set Vref, RX VrefLevel [Byte0]: 42
8640 12:18:10.258838 [Byte1]: 42
8641 12:18:10.262927
8642 12:18:10.263037 Set Vref, RX VrefLevel [Byte0]: 43
8643 12:18:10.266844 [Byte1]: 43
8644 12:18:10.270578
8645 12:18:10.270689 Set Vref, RX VrefLevel [Byte0]: 44
8646 12:18:10.274006 [Byte1]: 44
8647 12:18:10.278283
8648 12:18:10.278367 Set Vref, RX VrefLevel [Byte0]: 45
8649 12:18:10.281867 [Byte1]: 45
8650 12:18:10.286136
8651 12:18:10.286228 Set Vref, RX VrefLevel [Byte0]: 46
8652 12:18:10.288899 [Byte1]: 46
8653 12:18:10.293450
8654 12:18:10.293563 Set Vref, RX VrefLevel [Byte0]: 47
8655 12:18:10.296865 [Byte1]: 47
8656 12:18:10.300947
8657 12:18:10.301051 Set Vref, RX VrefLevel [Byte0]: 48
8658 12:18:10.304123 [Byte1]: 48
8659 12:18:10.308346
8660 12:18:10.308456 Set Vref, RX VrefLevel [Byte0]: 49
8661 12:18:10.311726 [Byte1]: 49
8662 12:18:10.315964
8663 12:18:10.316047 Set Vref, RX VrefLevel [Byte0]: 50
8664 12:18:10.319171 [Byte1]: 50
8665 12:18:10.323494
8666 12:18:10.323600 Set Vref, RX VrefLevel [Byte0]: 51
8667 12:18:10.326991 [Byte1]: 51
8668 12:18:10.331005
8669 12:18:10.331107 Set Vref, RX VrefLevel [Byte0]: 52
8670 12:18:10.334386 [Byte1]: 52
8671 12:18:10.338628
8672 12:18:10.338713 Set Vref, RX VrefLevel [Byte0]: 53
8673 12:18:10.342243 [Byte1]: 53
8674 12:18:10.346555
8675 12:18:10.346630 Set Vref, RX VrefLevel [Byte0]: 54
8676 12:18:10.349608 [Byte1]: 54
8677 12:18:10.353988
8678 12:18:10.354082 Set Vref, RX VrefLevel [Byte0]: 55
8679 12:18:10.357361 [Byte1]: 55
8680 12:18:10.361433
8681 12:18:10.364499 Set Vref, RX VrefLevel [Byte0]: 56
8682 12:18:10.367876 [Byte1]: 56
8683 12:18:10.367945
8684 12:18:10.371460 Set Vref, RX VrefLevel [Byte0]: 57
8685 12:18:10.374673 [Byte1]: 57
8686 12:18:10.374745
8687 12:18:10.377939 Set Vref, RX VrefLevel [Byte0]: 58
8688 12:18:10.381367 [Byte1]: 58
8689 12:18:10.381442
8690 12:18:10.384334 Set Vref, RX VrefLevel [Byte0]: 59
8691 12:18:10.388032 [Byte1]: 59
8692 12:18:10.391934
8693 12:18:10.392010 Set Vref, RX VrefLevel [Byte0]: 60
8694 12:18:10.395432 [Byte1]: 60
8695 12:18:10.399505
8696 12:18:10.399577 Set Vref, RX VrefLevel [Byte0]: 61
8697 12:18:10.402911 [Byte1]: 61
8698 12:18:10.406935
8699 12:18:10.407006 Set Vref, RX VrefLevel [Byte0]: 62
8700 12:18:10.410205 [Byte1]: 62
8701 12:18:10.414419
8702 12:18:10.414488 Set Vref, RX VrefLevel [Byte0]: 63
8703 12:18:10.417671 [Byte1]: 63
8704 12:18:10.422176
8705 12:18:10.422243 Set Vref, RX VrefLevel [Byte0]: 64
8706 12:18:10.425342 [Byte1]: 64
8707 12:18:10.429372
8708 12:18:10.429440 Set Vref, RX VrefLevel [Byte0]: 65
8709 12:18:10.433111 [Byte1]: 65
8710 12:18:10.437226
8711 12:18:10.437347 Set Vref, RX VrefLevel [Byte0]: 66
8712 12:18:10.440832 [Byte1]: 66
8713 12:18:10.444850
8714 12:18:10.444965 Set Vref, RX VrefLevel [Byte0]: 67
8715 12:18:10.447919 [Byte1]: 67
8716 12:18:10.452552
8717 12:18:10.452733 Set Vref, RX VrefLevel [Byte0]: 68
8718 12:18:10.455729 [Byte1]: 68
8719 12:18:10.460248
8720 12:18:10.460321 Set Vref, RX VrefLevel [Byte0]: 69
8721 12:18:10.463579 [Byte1]: 69
8722 12:18:10.467403
8723 12:18:10.467511 Set Vref, RX VrefLevel [Byte0]: 70
8724 12:18:10.470883 [Byte1]: 70
8725 12:18:10.475161
8726 12:18:10.475243 Set Vref, RX VrefLevel [Byte0]: 71
8727 12:18:10.478524 [Byte1]: 71
8728 12:18:10.482622
8729 12:18:10.482704 Set Vref, RX VrefLevel [Byte0]: 72
8730 12:18:10.485857 [Byte1]: 72
8731 12:18:10.490034
8732 12:18:10.490116 Set Vref, RX VrefLevel [Byte0]: 73
8733 12:18:10.493571 [Byte1]: 73
8734 12:18:10.497681
8735 12:18:10.497763 Set Vref, RX VrefLevel [Byte0]: 74
8736 12:18:10.501288 [Byte1]: 74
8737 12:18:10.505617
8738 12:18:10.505701 Set Vref, RX VrefLevel [Byte0]: 75
8739 12:18:10.508789 [Byte1]: 75
8740 12:18:10.512851
8741 12:18:10.512933 Final RX Vref Byte 0 = 58 to rank0
8742 12:18:10.516179 Final RX Vref Byte 1 = 61 to rank0
8743 12:18:10.519427 Final RX Vref Byte 0 = 58 to rank1
8744 12:18:10.523013 Final RX Vref Byte 1 = 61 to rank1==
8745 12:18:10.526489 Dram Type= 6, Freq= 0, CH_1, rank 0
8746 12:18:10.533075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8747 12:18:10.533151 ==
8748 12:18:10.533215 DQS Delay:
8749 12:18:10.533275 DQS0 = 0, DQS1 = 0
8750 12:18:10.536610 DQM Delay:
8751 12:18:10.536707 DQM0 = 134, DQM1 = 129
8752 12:18:10.539610 DQ Delay:
8753 12:18:10.543307 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8754 12:18:10.546651 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8755 12:18:10.549772 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8756 12:18:10.552831 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8757 12:18:10.552933
8758 12:18:10.553030
8759 12:18:10.553089
8760 12:18:10.556024 [DramC_TX_OE_Calibration] TA2
8761 12:18:10.559318 Original DQ_B0 (3 6) =30, OEN = 27
8762 12:18:10.562718 Original DQ_B1 (3 6) =30, OEN = 27
8763 12:18:10.566364 24, 0x0, End_B0=24 End_B1=24
8764 12:18:10.566450 25, 0x0, End_B0=25 End_B1=25
8765 12:18:10.569536 26, 0x0, End_B0=26 End_B1=26
8766 12:18:10.572891 27, 0x0, End_B0=27 End_B1=27
8767 12:18:10.575981 28, 0x0, End_B0=28 End_B1=28
8768 12:18:10.576056 29, 0x0, End_B0=29 End_B1=29
8769 12:18:10.579611 30, 0x0, End_B0=30 End_B1=30
8770 12:18:10.582955 31, 0x4141, End_B0=30 End_B1=30
8771 12:18:10.586144 Byte0 end_step=30 best_step=27
8772 12:18:10.589438 Byte1 end_step=30 best_step=27
8773 12:18:10.592900 Byte0 TX OE(2T, 0.5T) = (3, 3)
8774 12:18:10.593029 Byte1 TX OE(2T, 0.5T) = (3, 3)
8775 12:18:10.596009
8776 12:18:10.596099
8777 12:18:10.602739 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8778 12:18:10.605972 CH1 RK0: MR19=303, MR18=1927
8779 12:18:10.612745 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8780 12:18:10.612859
8781 12:18:10.616058 ----->DramcWriteLeveling(PI) begin...
8782 12:18:10.616167 ==
8783 12:18:10.619360 Dram Type= 6, Freq= 0, CH_1, rank 1
8784 12:18:10.622715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 12:18:10.622798 ==
8786 12:18:10.625913 Write leveling (Byte 0): 25 => 25
8787 12:18:10.629200 Write leveling (Byte 1): 29 => 29
8788 12:18:10.632567 DramcWriteLeveling(PI) end<-----
8789 12:18:10.632651
8790 12:18:10.632716 ==
8791 12:18:10.635863 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 12:18:10.639115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 12:18:10.639238 ==
8794 12:18:10.642486 [Gating] SW mode calibration
8795 12:18:10.649094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8796 12:18:10.655817 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8797 12:18:10.659261 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 12:18:10.662600 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 12:18:10.668770 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8800 12:18:10.672085 1 4 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 1)
8801 12:18:10.675604 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 12:18:10.682088 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 12:18:10.685327 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 12:18:10.688739 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 12:18:10.695499 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 12:18:10.698739 1 5 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8807 12:18:10.701957 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (1 0) (1 0)
8808 12:18:10.708790 1 5 12 | B1->B0 | 2323 3333 | 0 1 | (1 0) (1 0)
8809 12:18:10.712288 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 12:18:10.715590 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 12:18:10.722021 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 12:18:10.725331 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 12:18:10.728852 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 12:18:10.735257 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 12:18:10.738824 1 6 8 | B1->B0 | 4040 2424 | 0 0 | (0 0) (0 0)
8816 12:18:10.742202 1 6 12 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
8817 12:18:10.748636 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 12:18:10.752071 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 12:18:10.755490 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 12:18:10.762161 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 12:18:10.765215 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 12:18:10.768736 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 12:18:10.771900 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8824 12:18:10.778595 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8825 12:18:10.781808 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 12:18:10.785287 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 12:18:10.791953 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 12:18:10.795185 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 12:18:10.799020 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 12:18:10.805372 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 12:18:10.808650 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 12:18:10.812151 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 12:18:10.818694 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 12:18:10.821774 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 12:18:10.825334 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 12:18:10.832069 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 12:18:10.835198 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 12:18:10.838220 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 12:18:10.845003 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8840 12:18:10.848594 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8841 12:18:10.851739 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8842 12:18:10.855222 Total UI for P1: 0, mck2ui 16
8843 12:18:10.858491 best dqsien dly found for B0: ( 1, 9, 10)
8844 12:18:10.861617 Total UI for P1: 0, mck2ui 16
8845 12:18:10.864826 best dqsien dly found for B1: ( 1, 9, 10)
8846 12:18:10.868109 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8847 12:18:10.871790 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8848 12:18:10.871891
8849 12:18:10.878411 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8850 12:18:10.882111 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8851 12:18:10.882194 [Gating] SW calibration Done
8852 12:18:10.885065 ==
8853 12:18:10.888500 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 12:18:10.891599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 12:18:10.891683 ==
8856 12:18:10.891749 RX Vref Scan: 0
8857 12:18:10.891811
8858 12:18:10.894784 RX Vref 0 -> 0, step: 1
8859 12:18:10.894867
8860 12:18:10.898226 RX Delay 0 -> 252, step: 8
8861 12:18:10.901419 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8862 12:18:10.904857 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8863 12:18:10.908036 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8864 12:18:10.914720 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8865 12:18:10.917974 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8866 12:18:10.921656 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8867 12:18:10.924913 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8868 12:18:10.928175 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8869 12:18:10.934605 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8870 12:18:10.937983 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8871 12:18:10.941474 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8872 12:18:10.944700 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8873 12:18:10.947985 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8874 12:18:10.954481 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8875 12:18:10.957861 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8876 12:18:10.961607 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8877 12:18:10.961692 ==
8878 12:18:10.964636 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 12:18:10.967831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 12:18:10.971307 ==
8881 12:18:10.971405 DQS Delay:
8882 12:18:10.971518 DQS0 = 0, DQS1 = 0
8883 12:18:10.974582 DQM Delay:
8884 12:18:10.974667 DQM0 = 136, DQM1 = 132
8885 12:18:10.978131 DQ Delay:
8886 12:18:10.981514 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8887 12:18:10.984548 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8888 12:18:10.987835 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8889 12:18:10.991465 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =143
8890 12:18:10.991549
8891 12:18:10.991615
8892 12:18:10.991676 ==
8893 12:18:10.994463 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 12:18:10.997805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 12:18:10.997891 ==
8896 12:18:10.997957
8897 12:18:11.001242
8898 12:18:11.001326 TX Vref Scan disable
8899 12:18:11.004760 == TX Byte 0 ==
8900 12:18:11.007914 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8901 12:18:11.011258 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8902 12:18:11.014570 == TX Byte 1 ==
8903 12:18:11.017767 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8904 12:18:11.021109 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8905 12:18:11.021194 ==
8906 12:18:11.024540 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 12:18:11.031098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 12:18:11.031182 ==
8909 12:18:11.043812
8910 12:18:11.046826 TX Vref early break, caculate TX vref
8911 12:18:11.050421 TX Vref=16, minBit 9, minWin=21, winSum=378
8912 12:18:11.053366 TX Vref=18, minBit 8, minWin=22, winSum=389
8913 12:18:11.056905 TX Vref=20, minBit 8, minWin=23, winSum=394
8914 12:18:11.060325 TX Vref=22, minBit 8, minWin=24, winSum=406
8915 12:18:11.063864 TX Vref=24, minBit 9, minWin=24, winSum=413
8916 12:18:11.070193 TX Vref=26, minBit 9, minWin=24, winSum=414
8917 12:18:11.073653 TX Vref=28, minBit 8, minWin=24, winSum=413
8918 12:18:11.077202 TX Vref=30, minBit 9, minWin=24, winSum=404
8919 12:18:11.080167 TX Vref=32, minBit 10, minWin=23, winSum=398
8920 12:18:11.083776 TX Vref=34, minBit 8, minWin=22, winSum=394
8921 12:18:11.087480 TX Vref=36, minBit 10, minWin=22, winSum=379
8922 12:18:11.093696 [TxChooseVref] Worse bit 9, Min win 24, Win sum 414, Final Vref 26
8923 12:18:11.093777
8924 12:18:11.097012 Final TX Range 0 Vref 26
8925 12:18:11.097085
8926 12:18:11.097152 ==
8927 12:18:11.100555 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 12:18:11.103761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 12:18:11.103863 ==
8930 12:18:11.103954
8931 12:18:11.104042
8932 12:18:11.106965 TX Vref Scan disable
8933 12:18:11.113457 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8934 12:18:11.113535 == TX Byte 0 ==
8935 12:18:11.117151 u2DelayCellOfst[0]=17 cells (5 PI)
8936 12:18:11.120528 u2DelayCellOfst[1]=13 cells (4 PI)
8937 12:18:11.123653 u2DelayCellOfst[2]=0 cells (0 PI)
8938 12:18:11.126923 u2DelayCellOfst[3]=6 cells (2 PI)
8939 12:18:11.130232 u2DelayCellOfst[4]=10 cells (3 PI)
8940 12:18:11.133829 u2DelayCellOfst[5]=20 cells (6 PI)
8941 12:18:11.137105 u2DelayCellOfst[6]=17 cells (5 PI)
8942 12:18:11.140236 u2DelayCellOfst[7]=6 cells (2 PI)
8943 12:18:11.143319 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8944 12:18:11.147236 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8945 12:18:11.150436 == TX Byte 1 ==
8946 12:18:11.153427 u2DelayCellOfst[8]=0 cells (0 PI)
8947 12:18:11.153517 u2DelayCellOfst[9]=3 cells (1 PI)
8948 12:18:11.156854 u2DelayCellOfst[10]=6 cells (2 PI)
8949 12:18:11.160181 u2DelayCellOfst[11]=0 cells (0 PI)
8950 12:18:11.163635 u2DelayCellOfst[12]=13 cells (4 PI)
8951 12:18:11.166769 u2DelayCellOfst[13]=17 cells (5 PI)
8952 12:18:11.170019 u2DelayCellOfst[14]=17 cells (5 PI)
8953 12:18:11.173163 u2DelayCellOfst[15]=17 cells (5 PI)
8954 12:18:11.176547 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8955 12:18:11.183548 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8956 12:18:11.183629 DramC Write-DBI on
8957 12:18:11.183712 ==
8958 12:18:11.186776 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 12:18:11.193240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 12:18:11.193365 ==
8961 12:18:11.193468
8962 12:18:11.193559
8963 12:18:11.193648 TX Vref Scan disable
8964 12:18:11.197056 == TX Byte 0 ==
8965 12:18:11.200347 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8966 12:18:11.203409 == TX Byte 1 ==
8967 12:18:11.206989 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8968 12:18:11.210060 DramC Write-DBI off
8969 12:18:11.210136
8970 12:18:11.210207 [DATLAT]
8971 12:18:11.210267 Freq=1600, CH1 RK1
8972 12:18:11.210326
8973 12:18:11.213951 DATLAT Default: 0xf
8974 12:18:11.214060 0, 0xFFFF, sum = 0
8975 12:18:11.216690 1, 0xFFFF, sum = 0
8976 12:18:11.216795 2, 0xFFFF, sum = 0
8977 12:18:11.220056 3, 0xFFFF, sum = 0
8978 12:18:11.223760 4, 0xFFFF, sum = 0
8979 12:18:11.223845 5, 0xFFFF, sum = 0
8980 12:18:11.227047 6, 0xFFFF, sum = 0
8981 12:18:11.227131 7, 0xFFFF, sum = 0
8982 12:18:11.230404 8, 0xFFFF, sum = 0
8983 12:18:11.230492 9, 0xFFFF, sum = 0
8984 12:18:11.233860 10, 0xFFFF, sum = 0
8985 12:18:11.233971 11, 0xFFFF, sum = 0
8986 12:18:11.236805 12, 0xFFFF, sum = 0
8987 12:18:11.236906 13, 0xFFFF, sum = 0
8988 12:18:11.240273 14, 0x0, sum = 1
8989 12:18:11.240357 15, 0x0, sum = 2
8990 12:18:11.243488 16, 0x0, sum = 3
8991 12:18:11.243572 17, 0x0, sum = 4
8992 12:18:11.247036 best_step = 15
8993 12:18:11.247119
8994 12:18:11.247184 ==
8995 12:18:11.250273 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 12:18:11.253233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 12:18:11.253319 ==
8998 12:18:11.256639 RX Vref Scan: 0
8999 12:18:11.256723
9000 12:18:11.256788 RX Vref 0 -> 0, step: 1
9001 12:18:11.256864
9002 12:18:11.259947 RX Delay 19 -> 252, step: 4
9003 12:18:11.263577 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9004 12:18:11.269986 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9005 12:18:11.273495 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9006 12:18:11.276855 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9007 12:18:11.280132 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9008 12:18:11.283486 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9009 12:18:11.286557 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9010 12:18:11.293539 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9011 12:18:11.296537 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9012 12:18:11.300173 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9013 12:18:11.303615 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9014 12:18:11.306597 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9015 12:18:11.313067 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9016 12:18:11.316565 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9017 12:18:11.319514 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9018 12:18:11.322830 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9019 12:18:11.322934 ==
9020 12:18:11.326597 Dram Type= 6, Freq= 0, CH_1, rank 1
9021 12:18:11.332789 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9022 12:18:11.332895 ==
9023 12:18:11.333012 DQS Delay:
9024 12:18:11.336366 DQS0 = 0, DQS1 = 0
9025 12:18:11.336453 DQM Delay:
9026 12:18:11.339664 DQM0 = 133, DQM1 = 130
9027 12:18:11.339780 DQ Delay:
9028 12:18:11.342965 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9029 12:18:11.346321 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
9030 12:18:11.349460 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
9031 12:18:11.353093 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =142
9032 12:18:11.353175
9033 12:18:11.353238
9034 12:18:11.353297
9035 12:18:11.356493 [DramC_TX_OE_Calibration] TA2
9036 12:18:11.359733 Original DQ_B0 (3 6) =30, OEN = 27
9037 12:18:11.362931 Original DQ_B1 (3 6) =30, OEN = 27
9038 12:18:11.366131 24, 0x0, End_B0=24 End_B1=24
9039 12:18:11.366241 25, 0x0, End_B0=25 End_B1=25
9040 12:18:11.369829 26, 0x0, End_B0=26 End_B1=26
9041 12:18:11.373225 27, 0x0, End_B0=27 End_B1=27
9042 12:18:11.376451 28, 0x0, End_B0=28 End_B1=28
9043 12:18:11.379648 29, 0x0, End_B0=29 End_B1=29
9044 12:18:11.379752 30, 0x0, End_B0=30 End_B1=30
9045 12:18:11.382986 31, 0x5151, End_B0=30 End_B1=30
9046 12:18:11.386394 Byte0 end_step=30 best_step=27
9047 12:18:11.389854 Byte1 end_step=30 best_step=27
9048 12:18:11.393072 Byte0 TX OE(2T, 0.5T) = (3, 3)
9049 12:18:11.396157 Byte1 TX OE(2T, 0.5T) = (3, 3)
9050 12:18:11.396241
9051 12:18:11.396308
9052 12:18:11.402856 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9053 12:18:11.406181 CH1 RK1: MR19=303, MR18=1E09
9054 12:18:11.413113 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9055 12:18:11.416481 [RxdqsGatingPostProcess] freq 1600
9056 12:18:11.419341 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9057 12:18:11.422931 best DQS0 dly(2T, 0.5T) = (1, 1)
9058 12:18:11.426005 best DQS1 dly(2T, 0.5T) = (1, 1)
9059 12:18:11.429832 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9060 12:18:11.432557 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9061 12:18:11.435856 best DQS0 dly(2T, 0.5T) = (1, 1)
9062 12:18:11.439224 best DQS1 dly(2T, 0.5T) = (1, 1)
9063 12:18:11.442595 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9064 12:18:11.445777 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9065 12:18:11.449208 Pre-setting of DQS Precalculation
9066 12:18:11.452633 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9067 12:18:11.459215 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9068 12:18:11.469455 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9069 12:18:11.469541
9070 12:18:11.469606
9071 12:18:11.472780 [Calibration Summary] 3200 Mbps
9072 12:18:11.472890 CH 0, Rank 0
9073 12:18:11.475985 SW Impedance : PASS
9074 12:18:11.476068 DUTY Scan : NO K
9075 12:18:11.479558 ZQ Calibration : PASS
9076 12:18:11.479641 Jitter Meter : NO K
9077 12:18:11.482303 CBT Training : PASS
9078 12:18:11.485655 Write leveling : PASS
9079 12:18:11.485779 RX DQS gating : PASS
9080 12:18:11.489030 RX DQ/DQS(RDDQC) : PASS
9081 12:18:11.492352 TX DQ/DQS : PASS
9082 12:18:11.492461 RX DATLAT : PASS
9083 12:18:11.495685 RX DQ/DQS(Engine): PASS
9084 12:18:11.499090 TX OE : PASS
9085 12:18:11.499174 All Pass.
9086 12:18:11.499239
9087 12:18:11.499300 CH 0, Rank 1
9088 12:18:11.502481 SW Impedance : PASS
9089 12:18:11.505881 DUTY Scan : NO K
9090 12:18:11.505964 ZQ Calibration : PASS
9091 12:18:11.508895 Jitter Meter : NO K
9092 12:18:11.512296 CBT Training : PASS
9093 12:18:11.512378 Write leveling : PASS
9094 12:18:11.515544 RX DQS gating : PASS
9095 12:18:11.519068 RX DQ/DQS(RDDQC) : PASS
9096 12:18:11.519152 TX DQ/DQS : PASS
9097 12:18:11.522425 RX DATLAT : PASS
9098 12:18:11.522508 RX DQ/DQS(Engine): PASS
9099 12:18:11.525969 TX OE : PASS
9100 12:18:11.526052 All Pass.
9101 12:18:11.526119
9102 12:18:11.528826 CH 1, Rank 0
9103 12:18:11.528940 SW Impedance : PASS
9104 12:18:11.532161 DUTY Scan : NO K
9105 12:18:11.535728 ZQ Calibration : PASS
9106 12:18:11.535811 Jitter Meter : NO K
9107 12:18:11.539180 CBT Training : PASS
9108 12:18:11.542336 Write leveling : PASS
9109 12:18:11.542470 RX DQS gating : PASS
9110 12:18:11.545451 RX DQ/DQS(RDDQC) : PASS
9111 12:18:11.549065 TX DQ/DQS : PASS
9112 12:18:11.549154 RX DATLAT : PASS
9113 12:18:11.552384 RX DQ/DQS(Engine): PASS
9114 12:18:11.555457 TX OE : PASS
9115 12:18:11.555604 All Pass.
9116 12:18:11.555705
9117 12:18:11.555801 CH 1, Rank 1
9118 12:18:11.558798 SW Impedance : PASS
9119 12:18:11.562127 DUTY Scan : NO K
9120 12:18:11.562279 ZQ Calibration : PASS
9121 12:18:11.565346 Jitter Meter : NO K
9122 12:18:11.568728 CBT Training : PASS
9123 12:18:11.568841 Write leveling : PASS
9124 12:18:11.572065 RX DQS gating : PASS
9125 12:18:11.572160 RX DQ/DQS(RDDQC) : PASS
9126 12:18:11.575328 TX DQ/DQS : PASS
9127 12:18:11.578855 RX DATLAT : PASS
9128 12:18:11.578986 RX DQ/DQS(Engine): PASS
9129 12:18:11.582243 TX OE : PASS
9130 12:18:11.582425 All Pass.
9131 12:18:11.582524
9132 12:18:11.585928 DramC Write-DBI on
9133 12:18:11.588875 PER_BANK_REFRESH: Hybrid Mode
9134 12:18:11.589131 TX_TRACKING: ON
9135 12:18:11.598571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9136 12:18:11.605269 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9137 12:18:11.612196 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9138 12:18:11.618655 [FAST_K] Save calibration result to emmc
9139 12:18:11.618765 sync common calibartion params.
9140 12:18:11.622343 sync cbt_mode0:1, 1:1
9141 12:18:11.625111 dram_init: ddr_geometry: 2
9142 12:18:11.625210 dram_init: ddr_geometry: 2
9143 12:18:11.628677 dram_init: ddr_geometry: 2
9144 12:18:11.631880 0:dram_rank_size:100000000
9145 12:18:11.635318 1:dram_rank_size:100000000
9146 12:18:11.638688 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9147 12:18:11.641926 DFS_SHUFFLE_HW_MODE: ON
9148 12:18:11.644944 dramc_set_vcore_voltage set vcore to 725000
9149 12:18:11.648720 Read voltage for 1600, 0
9150 12:18:11.648822 Vio18 = 0
9151 12:18:11.651774 Vcore = 725000
9152 12:18:11.651875 Vdram = 0
9153 12:18:11.651975 Vddq = 0
9154 12:18:11.652064 Vmddr = 0
9155 12:18:11.655153 switch to 3200 Mbps bootup
9156 12:18:11.658472 [DramcRunTimeConfig]
9157 12:18:11.658576 PHYPLL
9158 12:18:11.658672 DPM_CONTROL_AFTERK: ON
9159 12:18:11.662028 PER_BANK_REFRESH: ON
9160 12:18:11.665029 REFRESH_OVERHEAD_REDUCTION: ON
9161 12:18:11.668514 CMD_PICG_NEW_MODE: OFF
9162 12:18:11.668614 XRTWTW_NEW_MODE: ON
9163 12:18:11.672013 XRTRTR_NEW_MODE: ON
9164 12:18:11.672115 TX_TRACKING: ON
9165 12:18:11.675208 RDSEL_TRACKING: OFF
9166 12:18:11.675315 DQS Precalculation for DVFS: ON
9167 12:18:11.678514 RX_TRACKING: OFF
9168 12:18:11.678620 HW_GATING DBG: ON
9169 12:18:11.681818 ZQCS_ENABLE_LP4: ON
9170 12:18:11.685177 RX_PICG_NEW_MODE: ON
9171 12:18:11.685259 TX_PICG_NEW_MODE: ON
9172 12:18:11.688293 ENABLE_RX_DCM_DPHY: ON
9173 12:18:11.691830 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9174 12:18:11.691903 DUMMY_READ_FOR_TRACKING: OFF
9175 12:18:11.695036 !!! SPM_CONTROL_AFTERK: OFF
9176 12:18:11.698057 !!! SPM could not control APHY
9177 12:18:11.701574 IMPEDANCE_TRACKING: ON
9178 12:18:11.701650 TEMP_SENSOR: ON
9179 12:18:11.704867 HW_SAVE_FOR_SR: OFF
9180 12:18:11.708148 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9181 12:18:11.711828 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9182 12:18:11.711930 Read ODT Tracking: ON
9183 12:18:11.714931 Refresh Rate DeBounce: ON
9184 12:18:11.718426 DFS_NO_QUEUE_FLUSH: ON
9185 12:18:11.718508 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9186 12:18:11.721586 ENABLE_DFS_RUNTIME_MRW: OFF
9187 12:18:11.724772 DDR_RESERVE_NEW_MODE: ON
9188 12:18:11.728008 MR_CBT_SWITCH_FREQ: ON
9189 12:18:11.728112 =========================
9190 12:18:11.747838 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9191 12:18:11.751059 dram_init: ddr_geometry: 2
9192 12:18:11.769375 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9193 12:18:11.772836 dram_init: dram init end (result: 0)
9194 12:18:11.779524 DRAM-K: Full calibration passed in 24464 msecs
9195 12:18:11.782798 MRC: failed to locate region type 0.
9196 12:18:11.782908 DRAM rank0 size:0x100000000,
9197 12:18:11.786125 DRAM rank1 size=0x100000000
9198 12:18:11.796170 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9199 12:18:11.802733 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9200 12:18:11.809566 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9201 12:18:11.816010 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9202 12:18:11.819555 DRAM rank0 size:0x100000000,
9203 12:18:11.822621 DRAM rank1 size=0x100000000
9204 12:18:11.822723 CBMEM:
9205 12:18:11.825877 IMD: root @ 0xfffff000 254 entries.
9206 12:18:11.829253 IMD: root @ 0xffffec00 62 entries.
9207 12:18:11.832746 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9208 12:18:11.835884 WARNING: RO_VPD is uninitialized or empty.
9209 12:18:11.842565 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9210 12:18:11.849589 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9211 12:18:11.862390 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9212 12:18:11.873635 BS: romstage times (exec / console): total (unknown) / 23968 ms
9213 12:18:11.873734
9214 12:18:11.873801
9215 12:18:11.883636 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9216 12:18:11.886826 ARM64: Exception handlers installed.
9217 12:18:11.890599 ARM64: Testing exception
9218 12:18:11.893439 ARM64: Done test exception
9219 12:18:11.893524 Enumerating buses...
9220 12:18:11.896969 Show all devs... Before device enumeration.
9221 12:18:11.900120 Root Device: enabled 1
9222 12:18:11.903489 CPU_CLUSTER: 0: enabled 1
9223 12:18:11.903573 CPU: 00: enabled 1
9224 12:18:11.907137 Compare with tree...
9225 12:18:11.907220 Root Device: enabled 1
9226 12:18:11.910168 CPU_CLUSTER: 0: enabled 1
9227 12:18:11.913772 CPU: 00: enabled 1
9228 12:18:11.913856 Root Device scanning...
9229 12:18:11.917139 scan_static_bus for Root Device
9230 12:18:11.920365 CPU_CLUSTER: 0 enabled
9231 12:18:11.923907 scan_static_bus for Root Device done
9232 12:18:11.927066 scan_bus: bus Root Device finished in 8 msecs
9233 12:18:11.927150 done
9234 12:18:11.933578 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9235 12:18:11.936852 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9236 12:18:11.943630 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9237 12:18:11.946713 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9238 12:18:11.950037 Allocating resources...
9239 12:18:11.950121 Reading resources...
9240 12:18:11.956732 Root Device read_resources bus 0 link: 0
9241 12:18:11.956817 DRAM rank0 size:0x100000000,
9242 12:18:11.960171 DRAM rank1 size=0x100000000
9243 12:18:11.963560 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9244 12:18:11.966655 CPU: 00 missing read_resources
9245 12:18:11.970159 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9246 12:18:11.976620 Root Device read_resources bus 0 link: 0 done
9247 12:18:11.976704 Done reading resources.
9248 12:18:11.983409 Show resources in subtree (Root Device)...After reading.
9249 12:18:11.986529 Root Device child on link 0 CPU_CLUSTER: 0
9250 12:18:11.990035 CPU_CLUSTER: 0 child on link 0 CPU: 00
9251 12:18:12.000142 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9252 12:18:12.000229 CPU: 00
9253 12:18:12.003505 Root Device assign_resources, bus 0 link: 0
9254 12:18:12.006789 CPU_CLUSTER: 0 missing set_resources
9255 12:18:12.010028 Root Device assign_resources, bus 0 link: 0 done
9256 12:18:12.012855 Done setting resources.
9257 12:18:12.019863 Show resources in subtree (Root Device)...After assigning values.
9258 12:18:12.023170 Root Device child on link 0 CPU_CLUSTER: 0
9259 12:18:12.026352 CPU_CLUSTER: 0 child on link 0 CPU: 00
9260 12:18:12.036208 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9261 12:18:12.036295 CPU: 00
9262 12:18:12.039488 Done allocating resources.
9263 12:18:12.042817 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9264 12:18:12.046033 Enabling resources...
9265 12:18:12.046113 done.
9266 12:18:12.052804 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9267 12:18:12.052892 Initializing devices...
9268 12:18:12.056126 Root Device init
9269 12:18:12.056210 init hardware done!
9270 12:18:12.059207 0x00000018: ctrlr->caps
9271 12:18:12.062565 52.000 MHz: ctrlr->f_max
9272 12:18:12.062650 0.400 MHz: ctrlr->f_min
9273 12:18:12.065934 0x40ff8080: ctrlr->voltages
9274 12:18:12.069400 sclk: 390625
9275 12:18:12.069483 Bus Width = 1
9276 12:18:12.069548 sclk: 390625
9277 12:18:12.072651 Bus Width = 1
9278 12:18:12.072748 Early init status = 3
9279 12:18:12.078891 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9280 12:18:12.082636 in-header: 03 fc 00 00 01 00 00 00
9281 12:18:12.085751 in-data: 00
9282 12:18:12.088864 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9283 12:18:12.094460 in-header: 03 fd 00 00 00 00 00 00
9284 12:18:12.097404 in-data:
9285 12:18:12.100908 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9286 12:18:12.105220 in-header: 03 fc 00 00 01 00 00 00
9287 12:18:12.108389 in-data: 00
9288 12:18:12.112081 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9289 12:18:12.117650 in-header: 03 fd 00 00 00 00 00 00
9290 12:18:12.120863 in-data:
9291 12:18:12.124138 [SSUSB] Setting up USB HOST controller...
9292 12:18:12.127463 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9293 12:18:12.130734 [SSUSB] phy power-on done.
9294 12:18:12.134019 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9295 12:18:12.141235 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9296 12:18:12.144064 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9297 12:18:12.150476 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9298 12:18:12.157268 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9299 12:18:12.163932 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9300 12:18:12.170967 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9301 12:18:12.177536 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9302 12:18:12.181184 SPM: binary array size = 0x9dc
9303 12:18:12.183745 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9304 12:18:12.190626 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9305 12:18:12.197195 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9306 12:18:12.200362 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9307 12:18:12.207017 configure_display: Starting display init
9308 12:18:12.240767 anx7625_power_on_init: Init interface.
9309 12:18:12.243939 anx7625_disable_pd_protocol: Disabled PD feature.
9310 12:18:12.247489 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9311 12:18:12.275205 anx7625_start_dp_work: Secure OCM version=00
9312 12:18:12.278356 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9313 12:18:12.293346 sp_tx_get_edid_block: EDID Block = 1
9314 12:18:12.395952 Extracted contents:
9315 12:18:12.399157 header: 00 ff ff ff ff ff ff 00
9316 12:18:12.402378 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9317 12:18:12.405810 version: 01 04
9318 12:18:12.409292 basic params: 95 1f 11 78 0a
9319 12:18:12.412311 chroma info: 76 90 94 55 54 90 27 21 50 54
9320 12:18:12.415780 established: 00 00 00
9321 12:18:12.422271 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9322 12:18:12.425645 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9323 12:18:12.432722 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9324 12:18:12.438982 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9325 12:18:12.445646 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9326 12:18:12.449124 extensions: 00
9327 12:18:12.449209 checksum: fb
9328 12:18:12.449276
9329 12:18:12.452246 Manufacturer: IVO Model 57d Serial Number 0
9330 12:18:12.455741 Made week 0 of 2020
9331 12:18:12.455849 EDID version: 1.4
9332 12:18:12.459037 Digital display
9333 12:18:12.462497 6 bits per primary color channel
9334 12:18:12.462583 DisplayPort interface
9335 12:18:12.465864 Maximum image size: 31 cm x 17 cm
9336 12:18:12.468726 Gamma: 220%
9337 12:18:12.468811 Check DPMS levels
9338 12:18:12.472066 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9339 12:18:12.475522 First detailed timing is preferred timing
9340 12:18:12.478800 Established timings supported:
9341 12:18:12.482126 Standard timings supported:
9342 12:18:12.485410 Detailed timings
9343 12:18:12.488612 Hex of detail: 383680a07038204018303c0035ae10000019
9344 12:18:12.491779 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9345 12:18:12.498741 0780 0798 07c8 0820 hborder 0
9346 12:18:12.502217 0438 043b 0447 0458 vborder 0
9347 12:18:12.505021 -hsync -vsync
9348 12:18:12.505114 Did detailed timing
9349 12:18:12.511918 Hex of detail: 000000000000000000000000000000000000
9350 12:18:12.511999 Manufacturer-specified data, tag 0
9351 12:18:12.518433 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9352 12:18:12.521671 ASCII string: InfoVision
9353 12:18:12.524890 Hex of detail: 000000fe00523134304e574635205248200a
9354 12:18:12.528703 ASCII string: R140NWF5 RH
9355 12:18:12.528783 Checksum
9356 12:18:12.531760 Checksum: 0xfb (valid)
9357 12:18:12.535279 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9358 12:18:12.538404 DSI data_rate: 832800000 bps
9359 12:18:12.542113 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9360 12:18:12.548780 anx7625_parse_edid: pixelclock(138800).
9361 12:18:12.551808 hactive(1920), hsync(48), hfp(24), hbp(88)
9362 12:18:12.555222 vactive(1080), vsync(12), vfp(3), vbp(17)
9363 12:18:12.558556 anx7625_dsi_config: config dsi.
9364 12:18:12.565209 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9365 12:18:12.577815 anx7625_dsi_config: success to config DSI
9366 12:18:12.581580 anx7625_dp_start: MIPI phy setup OK.
9367 12:18:12.584247 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9368 12:18:12.588258 mtk_ddp_mode_set invalid vrefresh 60
9369 12:18:12.591118 main_disp_path_setup
9370 12:18:12.591225 ovl_layer_smi_id_en
9371 12:18:12.594511 ovl_layer_smi_id_en
9372 12:18:12.594587 ccorr_config
9373 12:18:12.594650 aal_config
9374 12:18:12.597775 gamma_config
9375 12:18:12.597848 postmask_config
9376 12:18:12.601618 dither_config
9377 12:18:12.604412 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9378 12:18:12.611526 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9379 12:18:12.614602 Root Device init finished in 555 msecs
9380 12:18:12.614709 CPU_CLUSTER: 0 init
9381 12:18:12.624438 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9382 12:18:12.627679 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9383 12:18:12.631078 APU_MBOX 0x190000b0 = 0x10001
9384 12:18:12.634341 APU_MBOX 0x190001b0 = 0x10001
9385 12:18:12.638260 APU_MBOX 0x190005b0 = 0x10001
9386 12:18:12.641202 APU_MBOX 0x190006b0 = 0x10001
9387 12:18:12.644643 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9388 12:18:12.657172 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9389 12:18:12.669167 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9390 12:18:12.684663 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9391 12:18:12.687392 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9392 12:18:12.696904 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9393 12:18:12.699790 CPU_CLUSTER: 0 init finished in 81 msecs
9394 12:18:12.703065 Devices initialized
9395 12:18:12.706817 Show all devs... After init.
9396 12:18:12.706898 Root Device: enabled 1
9397 12:18:12.710145 CPU_CLUSTER: 0: enabled 1
9398 12:18:12.713143 CPU: 00: enabled 1
9399 12:18:12.716437 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9400 12:18:12.719732 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9401 12:18:12.723027 ELOG: NV offset 0x57f000 size 0x1000
9402 12:18:12.729876 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9403 12:18:12.736513 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9404 12:18:12.739749 ELOG: Event(17) added with size 13 at 2023-10-27 12:17:51 UTC
9405 12:18:12.746409 out: cmd=0x121: 03 db 21 01 00 00 00 00
9406 12:18:12.749889 in-header: 03 57 00 00 2c 00 00 00
9407 12:18:12.759725 in-data: 08 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9408 12:18:12.766195 ELOG: Event(A1) added with size 10 at 2023-10-27 12:17:51 UTC
9409 12:18:12.772906 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9410 12:18:12.779687 ELOG: Event(A0) added with size 9 at 2023-10-27 12:17:51 UTC
9411 12:18:12.782996 elog_add_boot_reason: Logged dev mode boot
9412 12:18:12.786447 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9413 12:18:12.789627 Finalize devices...
9414 12:18:12.789709 Devices finalized
9415 12:18:12.796061 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9416 12:18:12.799317 Writing coreboot table at 0xffe64000
9417 12:18:12.803032 0. 000000000010a000-0000000000113fff: RAMSTAGE
9418 12:18:12.806327 1. 0000000040000000-00000000400fffff: RAM
9419 12:18:12.813190 2. 0000000040100000-000000004032afff: RAMSTAGE
9420 12:18:12.816144 3. 000000004032b000-00000000545fffff: RAM
9421 12:18:12.819410 4. 0000000054600000-000000005465ffff: BL31
9422 12:18:12.822786 5. 0000000054660000-00000000ffe63fff: RAM
9423 12:18:12.829453 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9424 12:18:12.832815 7. 0000000100000000-000000023fffffff: RAM
9425 12:18:12.835834 Passing 5 GPIOs to payload:
9426 12:18:12.839505 NAME | PORT | POLARITY | VALUE
9427 12:18:12.842757 EC in RW | 0x000000aa | low | undefined
9428 12:18:12.849431 EC interrupt | 0x00000005 | low | undefined
9429 12:18:12.852562 TPM interrupt | 0x000000ab | high | undefined
9430 12:18:12.859082 SD card detect | 0x00000011 | high | undefined
9431 12:18:12.862376 speaker enable | 0x00000093 | high | undefined
9432 12:18:12.866006 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9433 12:18:12.869331 in-header: 03 f9 00 00 02 00 00 00
9434 12:18:12.872855 in-data: 02 00
9435 12:18:12.872980 ADC[4]: Raw value=901401 ID=7
9436 12:18:12.875834 ADC[3]: Raw value=213179 ID=1
9437 12:18:12.879004 RAM Code: 0x71
9438 12:18:12.879083 ADC[6]: Raw value=74502 ID=0
9439 12:18:12.882366 ADC[5]: Raw value=212810 ID=1
9440 12:18:12.885724 SKU Code: 0x1
9441 12:18:12.889022 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7bf0
9442 12:18:12.892342 coreboot table: 964 bytes.
9443 12:18:12.895894 IMD ROOT 0. 0xfffff000 0x00001000
9444 12:18:12.898876 IMD SMALL 1. 0xffffe000 0x00001000
9445 12:18:12.902216 RO MCACHE 2. 0xffffc000 0x00001104
9446 12:18:12.905614 CONSOLE 3. 0xfff7c000 0x00080000
9447 12:18:12.908788 FMAP 4. 0xfff7b000 0x00000452
9448 12:18:12.912178 TIME STAMP 5. 0xfff7a000 0x00000910
9449 12:18:12.915521 VBOOT WORK 6. 0xfff66000 0x00014000
9450 12:18:12.918902 RAMOOPS 7. 0xffe66000 0x00100000
9451 12:18:12.922428 COREBOOT 8. 0xffe64000 0x00002000
9452 12:18:12.922514 IMD small region:
9453 12:18:12.925466 IMD ROOT 0. 0xffffec00 0x00000400
9454 12:18:12.931970 VPD 1. 0xffffeb80 0x0000006c
9455 12:18:12.935298 MMC STATUS 2. 0xffffeb60 0x00000004
9456 12:18:12.938583 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9457 12:18:12.942266 Probing TPM: done!
9458 12:18:12.945585 Connected to device vid:did:rid of 1ae0:0028:00
9459 12:18:12.955948 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9460 12:18:12.959204 Initialized TPM device CR50 revision 0
9461 12:18:12.962620 Checking cr50 for pending updates
9462 12:18:12.966660 Reading cr50 TPM mode
9463 12:18:12.975093 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9464 12:18:12.982088 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9465 12:18:13.021645 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9466 12:18:13.025350 Checking segment from ROM address 0x40100000
9467 12:18:13.028651 Checking segment from ROM address 0x4010001c
9468 12:18:13.035229 Loading segment from ROM address 0x40100000
9469 12:18:13.035316 code (compression=0)
9470 12:18:13.041872 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9471 12:18:13.051715 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9472 12:18:13.051823 it's not compressed!
9473 12:18:13.058811 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9474 12:18:13.061886 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9475 12:18:13.082112 Loading segment from ROM address 0x4010001c
9476 12:18:13.082222 Entry Point 0x80000000
9477 12:18:13.085569 Loaded segments
9478 12:18:13.088731 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9479 12:18:13.095540 Jumping to boot code at 0x80000000(0xffe64000)
9480 12:18:13.102243 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9481 12:18:13.108921 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9482 12:18:13.116737 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9483 12:18:13.120133 Checking segment from ROM address 0x40100000
9484 12:18:13.123322 Checking segment from ROM address 0x4010001c
9485 12:18:13.130283 Loading segment from ROM address 0x40100000
9486 12:18:13.130363 code (compression=1)
9487 12:18:13.136548 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9488 12:18:13.146449 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9489 12:18:13.146555 using LZMA
9490 12:18:13.154842 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9491 12:18:13.161922 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9492 12:18:13.164935 Loading segment from ROM address 0x4010001c
9493 12:18:13.165015 Entry Point 0x54601000
9494 12:18:13.168450 Loaded segments
9495 12:18:13.171719 NOTICE: MT8192 bl31_setup
9496 12:18:13.178427 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9497 12:18:13.181883 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9498 12:18:13.185370 WARNING: region 0:
9499 12:18:13.188440 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 12:18:13.188541 WARNING: region 1:
9501 12:18:13.195087 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9502 12:18:13.198531 WARNING: region 2:
9503 12:18:13.201801 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9504 12:18:13.205317 WARNING: region 3:
9505 12:18:13.208546 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9506 12:18:13.211787 WARNING: region 4:
9507 12:18:13.218797 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9508 12:18:13.218881 WARNING: region 5:
9509 12:18:13.221899 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 12:18:13.225583 WARNING: region 6:
9511 12:18:13.228634 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9512 12:18:13.228718 WARNING: region 7:
9513 12:18:13.235241 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 12:18:13.242263 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9515 12:18:13.245557 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9516 12:18:13.248640 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9517 12:18:13.255589 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9518 12:18:13.258944 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9519 12:18:13.262015 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9520 12:18:13.268817 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9521 12:18:13.272165 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9522 12:18:13.275690 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9523 12:18:13.282109 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9524 12:18:13.285791 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9525 12:18:13.289123 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9526 12:18:13.295845 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9527 12:18:13.298950 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9528 12:18:13.305831 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9529 12:18:13.309062 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9530 12:18:13.312743 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9531 12:18:13.319276 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9532 12:18:13.322629 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9533 12:18:13.325782 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9534 12:18:13.332472 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9535 12:18:13.335886 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9536 12:18:13.342528 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9537 12:18:13.345635 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9538 12:18:13.349399 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9539 12:18:13.355783 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9540 12:18:13.359248 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9541 12:18:13.366126 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9542 12:18:13.369317 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9543 12:18:13.372531 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9544 12:18:13.379003 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9545 12:18:13.382524 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9546 12:18:13.385801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9547 12:18:13.392849 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9548 12:18:13.396246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9549 12:18:13.399421 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9550 12:18:13.402806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9551 12:18:13.409234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9552 12:18:13.412772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9553 12:18:13.415837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9554 12:18:13.419655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9555 12:18:13.422946 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9556 12:18:13.429649 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9557 12:18:13.432729 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9558 12:18:13.435932 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9559 12:18:13.442966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9560 12:18:13.446146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9561 12:18:13.449316 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9562 12:18:13.453059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9563 12:18:13.459503 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9564 12:18:13.463112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9565 12:18:13.469843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9566 12:18:13.473022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9567 12:18:13.479475 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9568 12:18:13.482729 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9569 12:18:13.486262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9570 12:18:13.492749 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9571 12:18:13.496583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9572 12:18:13.503177 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9573 12:18:13.506501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9574 12:18:13.513078 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9575 12:18:13.516499 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9576 12:18:13.519867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9577 12:18:13.526504 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9578 12:18:13.529910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9579 12:18:13.536232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9580 12:18:13.539823 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9581 12:18:13.546398 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9582 12:18:13.549593 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9583 12:18:13.553048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9584 12:18:13.560001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9585 12:18:13.563056 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9586 12:18:13.570025 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9587 12:18:13.573232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9588 12:18:13.579978 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9589 12:18:13.583263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9590 12:18:13.586438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9591 12:18:13.593192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9592 12:18:13.596477 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9593 12:18:13.603325 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9594 12:18:13.606712 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9595 12:18:13.613132 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9596 12:18:13.616430 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9597 12:18:13.619895 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9598 12:18:13.626737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9599 12:18:13.629956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9600 12:18:13.636876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9601 12:18:13.639834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9602 12:18:13.646508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9603 12:18:13.650160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9604 12:18:13.653041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9605 12:18:13.659910 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9606 12:18:13.663321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9607 12:18:13.669699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9608 12:18:13.673320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9609 12:18:13.679956 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9610 12:18:13.683482 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9611 12:18:13.686521 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9612 12:18:13.690009 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9613 12:18:13.696415 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9614 12:18:13.699853 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9615 12:18:13.702956 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9616 12:18:13.709864 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9617 12:18:13.713063 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9618 12:18:13.719815 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9619 12:18:13.723198 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9620 12:18:13.726357 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9621 12:18:13.733126 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9622 12:18:13.736457 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9623 12:18:13.739869 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9624 12:18:13.746795 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9625 12:18:13.749856 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9626 12:18:13.757223 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9627 12:18:13.759974 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9628 12:18:13.763213 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9629 12:18:13.770077 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9630 12:18:13.773586 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9631 12:18:13.776850 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9632 12:18:13.783399 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9633 12:18:13.786561 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9634 12:18:13.789911 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9635 12:18:13.793347 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9636 12:18:13.800079 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9637 12:18:13.803286 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9638 12:18:13.806862 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9639 12:18:13.813253 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9640 12:18:13.816547 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9641 12:18:13.820402 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9642 12:18:13.826765 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9643 12:18:13.830144 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9644 12:18:13.833476 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9645 12:18:13.840077 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9646 12:18:13.843476 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9647 12:18:13.850237 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9648 12:18:13.853319 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9649 12:18:13.857250 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9650 12:18:13.863622 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9651 12:18:13.866907 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9652 12:18:13.873603 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9653 12:18:13.876802 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9654 12:18:13.880317 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9655 12:18:13.886944 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9656 12:18:13.890403 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9657 12:18:13.896762 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9658 12:18:13.900498 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9659 12:18:13.903526 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9660 12:18:13.910432 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9661 12:18:13.913449 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9662 12:18:13.916744 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9663 12:18:13.923477 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9664 12:18:13.926806 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9665 12:18:13.933635 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9666 12:18:13.937121 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9667 12:18:13.940412 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9668 12:18:13.946714 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9669 12:18:13.950486 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9670 12:18:13.953704 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9671 12:18:13.960547 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9672 12:18:13.963712 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9673 12:18:13.970337 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9674 12:18:13.973626 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9675 12:18:13.977496 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9676 12:18:13.983617 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9677 12:18:13.987310 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9678 12:18:13.994005 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9679 12:18:13.997101 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9680 12:18:13.999975 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9681 12:18:14.006694 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9682 12:18:14.010522 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9683 12:18:14.013373 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9684 12:18:14.020386 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9685 12:18:14.023712 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9686 12:18:14.030232 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9687 12:18:14.033489 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9688 12:18:14.036832 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9689 12:18:14.043678 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9690 12:18:14.046957 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9691 12:18:14.053437 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9692 12:18:14.056784 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9693 12:18:14.059976 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9694 12:18:14.066751 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9695 12:18:14.069955 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9696 12:18:14.076593 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9697 12:18:14.080021 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9698 12:18:14.083481 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9699 12:18:14.089972 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9700 12:18:14.093009 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9701 12:18:14.099777 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9702 12:18:14.103030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9703 12:18:14.106699 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9704 12:18:14.113064 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9705 12:18:14.116688 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9706 12:18:14.122994 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9707 12:18:14.126351 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9708 12:18:14.129666 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9709 12:18:14.136290 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9710 12:18:14.139628 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9711 12:18:14.146589 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9712 12:18:14.149404 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9713 12:18:14.156188 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9714 12:18:14.159603 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9715 12:18:14.162792 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9716 12:18:14.169037 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9717 12:18:14.172601 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9718 12:18:14.179508 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9719 12:18:14.182759 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9720 12:18:14.189197 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9721 12:18:14.192280 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9722 12:18:14.195796 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9723 12:18:14.202385 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9724 12:18:14.205663 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9725 12:18:14.212269 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9726 12:18:14.215576 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9727 12:18:14.222152 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9728 12:18:14.225327 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9729 12:18:14.228748 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9730 12:18:14.235431 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9731 12:18:14.238766 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9732 12:18:14.245302 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9733 12:18:14.248606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9734 12:18:14.252379 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9735 12:18:14.258576 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9736 12:18:14.262119 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9737 12:18:14.268301 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9738 12:18:14.272218 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9739 12:18:14.278621 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9740 12:18:14.282158 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9741 12:18:14.285247 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9742 12:18:14.292100 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9743 12:18:14.295207 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9744 12:18:14.298621 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9745 12:18:14.301818 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9746 12:18:14.308454 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9747 12:18:14.311805 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9748 12:18:14.315232 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9749 12:18:14.321646 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9750 12:18:14.325384 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9751 12:18:14.328772 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9752 12:18:14.335166 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9753 12:18:14.338408 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9754 12:18:14.341888 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9755 12:18:14.348486 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9756 12:18:14.351891 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9757 12:18:14.355097 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9758 12:18:14.361964 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9759 12:18:14.365077 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9760 12:18:14.371588 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9761 12:18:14.374829 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9762 12:18:14.378683 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9763 12:18:14.385190 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9764 12:18:14.388668 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9765 12:18:14.391584 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9766 12:18:14.398471 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9767 12:18:14.401797 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9768 12:18:14.405095 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9769 12:18:14.411413 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9770 12:18:14.415099 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9771 12:18:14.421342 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9772 12:18:14.424874 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9773 12:18:14.428467 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9774 12:18:14.434655 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9775 12:18:14.437990 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9776 12:18:14.444645 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9777 12:18:14.448252 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9778 12:18:14.451848 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9779 12:18:14.457926 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9780 12:18:14.461376 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9781 12:18:14.464729 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9782 12:18:14.470944 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9783 12:18:14.474791 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9784 12:18:14.477640 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9785 12:18:14.480954 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9786 12:18:14.487488 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9787 12:18:14.490813 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9788 12:18:14.494483 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9789 12:18:14.497424 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9790 12:18:14.504038 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9791 12:18:14.507284 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9792 12:18:14.511185 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9793 12:18:14.514421 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9794 12:18:14.520725 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9795 12:18:14.524224 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9796 12:18:14.527106 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9797 12:18:14.533842 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9798 12:18:14.537585 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9799 12:18:14.543668 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9800 12:18:14.547036 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9801 12:18:14.553881 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9802 12:18:14.557141 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9803 12:18:14.560620 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9804 12:18:14.567276 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9805 12:18:14.570465 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9806 12:18:14.574147 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9807 12:18:14.580410 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9808 12:18:14.583744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9809 12:18:14.590657 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9810 12:18:14.594070 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9811 12:18:14.597320 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9812 12:18:14.603971 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9813 12:18:14.607008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9814 12:18:14.613450 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9815 12:18:14.617264 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9816 12:18:14.623667 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9817 12:18:14.627172 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9818 12:18:14.630620 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9819 12:18:14.637075 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9820 12:18:14.640512 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9821 12:18:14.647087 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9822 12:18:14.650553 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9823 12:18:14.653650 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9824 12:18:14.660556 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9825 12:18:14.663842 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9826 12:18:14.670314 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9827 12:18:14.673842 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9828 12:18:14.676788 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9829 12:18:14.683941 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9830 12:18:14.687143 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9831 12:18:14.693532 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9832 12:18:14.696836 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9833 12:18:14.700379 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9834 12:18:14.707056 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9835 12:18:14.710181 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9836 12:18:14.717051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9837 12:18:14.720801 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9838 12:18:14.723659 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9839 12:18:14.730431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9840 12:18:14.733626 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9841 12:18:14.740534 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9842 12:18:14.743730 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9843 12:18:14.746646 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9844 12:18:14.753493 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9845 12:18:14.756503 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9846 12:18:14.763533 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9847 12:18:14.766711 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9848 12:18:14.773391 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9849 12:18:14.776588 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9850 12:18:14.780088 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9851 12:18:14.786618 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9852 12:18:14.789880 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9853 12:18:14.796825 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9854 12:18:14.800550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9855 12:18:14.803243 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9856 12:18:14.810122 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9857 12:18:14.813148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9858 12:18:14.819785 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9859 12:18:14.823172 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9860 12:18:14.829530 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9861 12:18:14.832927 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9862 12:18:14.836165 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9863 12:18:14.843133 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9864 12:18:14.846391 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9865 12:18:14.853117 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9866 12:18:14.856250 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9867 12:18:14.859561 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9868 12:18:14.866118 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9869 12:18:14.869374 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9870 12:18:14.876010 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9871 12:18:14.879360 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9872 12:18:14.886004 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9873 12:18:14.889117 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9874 12:18:14.895925 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9875 12:18:14.899231 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9876 12:18:14.902939 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9877 12:18:14.909056 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9878 12:18:14.912669 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9879 12:18:14.919156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9880 12:18:14.922289 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9881 12:18:14.929336 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9882 12:18:14.932557 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9883 12:18:14.936105 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9884 12:18:14.942540 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9885 12:18:14.946086 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9886 12:18:14.952625 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9887 12:18:14.955688 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9888 12:18:14.962285 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9889 12:18:14.965531 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9890 12:18:14.969108 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9891 12:18:14.975963 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9892 12:18:14.978837 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9893 12:18:14.985635 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9894 12:18:14.989118 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9895 12:18:14.995633 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9896 12:18:14.998632 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9897 12:18:15.001886 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9898 12:18:15.008630 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9899 12:18:15.011925 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9900 12:18:15.018789 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9901 12:18:15.021954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9902 12:18:15.028781 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9903 12:18:15.031935 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9904 12:18:15.035128 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9905 12:18:15.041962 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9906 12:18:15.045120 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9907 12:18:15.051864 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9908 12:18:15.055334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9909 12:18:15.061931 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9910 12:18:15.065137 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9911 12:18:15.068458 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9912 12:18:15.075230 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9913 12:18:15.078761 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9914 12:18:15.085362 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9915 12:18:15.088459 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9916 12:18:15.091838 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9917 12:18:15.098427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9918 12:18:15.101887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9919 12:18:15.108399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9920 12:18:15.111854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9921 12:18:15.118234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9922 12:18:15.121880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9923 12:18:15.128624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9924 12:18:15.131886 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9925 12:18:15.138368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9926 12:18:15.141994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9927 12:18:15.148151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9928 12:18:15.151859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9929 12:18:15.158404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9930 12:18:15.161405 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9931 12:18:15.168174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9932 12:18:15.171352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9933 12:18:15.174763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9934 12:18:15.181676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9935 12:18:15.184720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9936 12:18:15.191279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9937 12:18:15.194887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9938 12:18:15.201597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9939 12:18:15.204782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9940 12:18:15.211200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9941 12:18:15.214873 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9942 12:18:15.221688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9943 12:18:15.224633 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9944 12:18:15.231540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9945 12:18:15.234511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9946 12:18:15.241490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9947 12:18:15.245069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9948 12:18:15.251371 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9949 12:18:15.251471 INFO: [APUAPC] vio 0
9950 12:18:15.258249 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9951 12:18:15.261560 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9952 12:18:15.265169 INFO: [APUAPC] D0_APC_0: 0x400510
9953 12:18:15.268400 INFO: [APUAPC] D0_APC_1: 0x0
9954 12:18:15.271753 INFO: [APUAPC] D0_APC_2: 0x1540
9955 12:18:15.274715 INFO: [APUAPC] D0_APC_3: 0x0
9956 12:18:15.278447 INFO: [APUAPC] D1_APC_0: 0xffffffff
9957 12:18:15.281876 INFO: [APUAPC] D1_APC_1: 0xffffffff
9958 12:18:15.285384 INFO: [APUAPC] D1_APC_2: 0x3fffff
9959 12:18:15.288224 INFO: [APUAPC] D1_APC_3: 0x0
9960 12:18:15.291344 INFO: [APUAPC] D2_APC_0: 0xffffffff
9961 12:18:15.294775 INFO: [APUAPC] D2_APC_1: 0xffffffff
9962 12:18:15.298154 INFO: [APUAPC] D2_APC_2: 0x3fffff
9963 12:18:15.301567 INFO: [APUAPC] D2_APC_3: 0x0
9964 12:18:15.304757 INFO: [APUAPC] D3_APC_0: 0xffffffff
9965 12:18:15.307882 INFO: [APUAPC] D3_APC_1: 0xffffffff
9966 12:18:15.311485 INFO: [APUAPC] D3_APC_2: 0x3fffff
9967 12:18:15.314732 INFO: [APUAPC] D3_APC_3: 0x0
9968 12:18:15.318133 INFO: [APUAPC] D4_APC_0: 0xffffffff
9969 12:18:15.321350 INFO: [APUAPC] D4_APC_1: 0xffffffff
9970 12:18:15.324924 INFO: [APUAPC] D4_APC_2: 0x3fffff
9971 12:18:15.325029 INFO: [APUAPC] D4_APC_3: 0x0
9972 12:18:15.328108 INFO: [APUAPC] D5_APC_0: 0xffffffff
9973 12:18:15.331704 INFO: [APUAPC] D5_APC_1: 0xffffffff
9974 12:18:15.334969 INFO: [APUAPC] D5_APC_2: 0x3fffff
9975 12:18:15.338349 INFO: [APUAPC] D5_APC_3: 0x0
9976 12:18:15.341567 INFO: [APUAPC] D6_APC_0: 0xffffffff
9977 12:18:15.344790 INFO: [APUAPC] D6_APC_1: 0xffffffff
9978 12:18:15.347865 INFO: [APUAPC] D6_APC_2: 0x3fffff
9979 12:18:15.351266 INFO: [APUAPC] D6_APC_3: 0x0
9980 12:18:15.354848 INFO: [APUAPC] D7_APC_0: 0xffffffff
9981 12:18:15.358041 INFO: [APUAPC] D7_APC_1: 0xffffffff
9982 12:18:15.361220 INFO: [APUAPC] D7_APC_2: 0x3fffff
9983 12:18:15.364475 INFO: [APUAPC] D7_APC_3: 0x0
9984 12:18:15.368095 INFO: [APUAPC] D8_APC_0: 0xffffffff
9985 12:18:15.371214 INFO: [APUAPC] D8_APC_1: 0xffffffff
9986 12:18:15.375063 INFO: [APUAPC] D8_APC_2: 0x3fffff
9987 12:18:15.378138 INFO: [APUAPC] D8_APC_3: 0x0
9988 12:18:15.381136 INFO: [APUAPC] D9_APC_0: 0xffffffff
9989 12:18:15.384609 INFO: [APUAPC] D9_APC_1: 0xffffffff
9990 12:18:15.388065 INFO: [APUAPC] D9_APC_2: 0x3fffff
9991 12:18:15.391250 INFO: [APUAPC] D9_APC_3: 0x0
9992 12:18:15.394302 INFO: [APUAPC] D10_APC_0: 0xffffffff
9993 12:18:15.397604 INFO: [APUAPC] D10_APC_1: 0xffffffff
9994 12:18:15.401101 INFO: [APUAPC] D10_APC_2: 0x3fffff
9995 12:18:15.404849 INFO: [APUAPC] D10_APC_3: 0x0
9996 12:18:15.407899 INFO: [APUAPC] D11_APC_0: 0xffffffff
9997 12:18:15.411302 INFO: [APUAPC] D11_APC_1: 0xffffffff
9998 12:18:15.414336 INFO: [APUAPC] D11_APC_2: 0x3fffff
9999 12:18:15.417631 INFO: [APUAPC] D11_APC_3: 0x0
10000 12:18:15.420939 INFO: [APUAPC] D12_APC_0: 0xffffffff
10001 12:18:15.424308 INFO: [APUAPC] D12_APC_1: 0xffffffff
10002 12:18:15.427724 INFO: [APUAPC] D12_APC_2: 0x3fffff
10003 12:18:15.430620 INFO: [APUAPC] D12_APC_3: 0x0
10004 12:18:15.433989 INFO: [APUAPC] D13_APC_0: 0xffffffff
10005 12:18:15.437468 INFO: [APUAPC] D13_APC_1: 0xffffffff
10006 12:18:15.440682 INFO: [APUAPC] D13_APC_2: 0x3fffff
10007 12:18:15.444245 INFO: [APUAPC] D13_APC_3: 0x0
10008 12:18:15.447450 INFO: [APUAPC] D14_APC_0: 0xffffffff
10009 12:18:15.450393 INFO: [APUAPC] D14_APC_1: 0xffffffff
10010 12:18:15.454140 INFO: [APUAPC] D14_APC_2: 0x3fffff
10011 12:18:15.457140 INFO: [APUAPC] D14_APC_3: 0x0
10012 12:18:15.460536 INFO: [APUAPC] D15_APC_0: 0xffffffff
10013 12:18:15.463792 INFO: [APUAPC] D15_APC_1: 0xffffffff
10014 12:18:15.467347 INFO: [APUAPC] D15_APC_2: 0x3fffff
10015 12:18:15.470635 INFO: [APUAPC] D15_APC_3: 0x0
10016 12:18:15.473710 INFO: [APUAPC] APC_CON: 0x4
10017 12:18:15.476914 INFO: [NOCDAPC] D0_APC_0: 0x0
10018 12:18:15.480593 INFO: [NOCDAPC] D0_APC_1: 0x0
10019 12:18:15.483798 INFO: [NOCDAPC] D1_APC_0: 0x0
10020 12:18:15.486993 INFO: [NOCDAPC] D1_APC_1: 0xfff
10021 12:18:15.490157 INFO: [NOCDAPC] D2_APC_0: 0x0
10022 12:18:15.493443 INFO: [NOCDAPC] D2_APC_1: 0xfff
10023 12:18:15.493527 INFO: [NOCDAPC] D3_APC_0: 0x0
10024 12:18:15.496858 INFO: [NOCDAPC] D3_APC_1: 0xfff
10025 12:18:15.500181 INFO: [NOCDAPC] D4_APC_0: 0x0
10026 12:18:15.503636 INFO: [NOCDAPC] D4_APC_1: 0xfff
10027 12:18:15.506920 INFO: [NOCDAPC] D5_APC_0: 0x0
10028 12:18:15.510158 INFO: [NOCDAPC] D5_APC_1: 0xfff
10029 12:18:15.513354 INFO: [NOCDAPC] D6_APC_0: 0x0
10030 12:18:15.516653 INFO: [NOCDAPC] D6_APC_1: 0xfff
10031 12:18:15.520043 INFO: [NOCDAPC] D7_APC_0: 0x0
10032 12:18:15.523322 INFO: [NOCDAPC] D7_APC_1: 0xfff
10033 12:18:15.526562 INFO: [NOCDAPC] D8_APC_0: 0x0
10034 12:18:15.530066 INFO: [NOCDAPC] D8_APC_1: 0xfff
10035 12:18:15.530150 INFO: [NOCDAPC] D9_APC_0: 0x0
10036 12:18:15.533625 INFO: [NOCDAPC] D9_APC_1: 0xfff
10037 12:18:15.536555 INFO: [NOCDAPC] D10_APC_0: 0x0
10038 12:18:15.539874 INFO: [NOCDAPC] D10_APC_1: 0xfff
10039 12:18:15.543173 INFO: [NOCDAPC] D11_APC_0: 0x0
10040 12:18:15.546635 INFO: [NOCDAPC] D11_APC_1: 0xfff
10041 12:18:15.549801 INFO: [NOCDAPC] D12_APC_0: 0x0
10042 12:18:15.552874 INFO: [NOCDAPC] D12_APC_1: 0xfff
10043 12:18:15.556335 INFO: [NOCDAPC] D13_APC_0: 0x0
10044 12:18:15.559744 INFO: [NOCDAPC] D13_APC_1: 0xfff
10045 12:18:15.562910 INFO: [NOCDAPC] D14_APC_0: 0x0
10046 12:18:15.566142 INFO: [NOCDAPC] D14_APC_1: 0xfff
10047 12:18:15.569628 INFO: [NOCDAPC] D15_APC_0: 0x0
10048 12:18:15.572808 INFO: [NOCDAPC] D15_APC_1: 0xfff
10049 12:18:15.572893 INFO: [NOCDAPC] APC_CON: 0x4
10050 12:18:15.576464 INFO: [APUAPC] set_apusys_apc done
10051 12:18:15.579723 INFO: [DEVAPC] devapc_init done
10052 12:18:15.586062 INFO: GICv3 without legacy support detected.
10053 12:18:15.589542 INFO: ARM GICv3 driver initialized in EL3
10054 12:18:15.592760 INFO: Maximum SPI INTID supported: 639
10055 12:18:15.596081 INFO: BL31: Initializing runtime services
10056 12:18:15.602746 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10057 12:18:15.606051 INFO: SPM: enable CPC mode
10058 12:18:15.609559 INFO: mcdi ready for mcusys-off-idle and system suspend
10059 12:18:15.616515 INFO: BL31: Preparing for EL3 exit to normal world
10060 12:18:15.619583 INFO: Entry point address = 0x80000000
10061 12:18:15.619667 INFO: SPSR = 0x8
10062 12:18:15.626578
10063 12:18:15.626662
10064 12:18:15.626728
10065 12:18:15.629749 Starting depthcharge on Spherion...
10066 12:18:15.629832
10067 12:18:15.629899 Wipe memory regions:
10068 12:18:15.629959
10069 12:18:15.630568 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10070 12:18:15.630668 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10071 12:18:15.630983 Setting prompt string to ['asurada:']
10072 12:18:15.631068 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10073 12:18:15.632926 [0x00000040000000, 0x00000054600000)
10074 12:18:15.755402
10075 12:18:15.755537 [0x00000054660000, 0x00000080000000)
10076 12:18:16.016404
10077 12:18:16.016620 [0x000000821a7280, 0x000000ffe64000)
10078 12:18:16.760842
10079 12:18:16.760990 [0x00000100000000, 0x00000240000000)
10080 12:18:18.651065
10081 12:18:18.654267 Initializing XHCI USB controller at 0x11200000.
10082 12:18:19.691755
10083 12:18:19.695236 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10084 12:18:19.695353
10085 12:18:19.695448
10086 12:18:19.695547
10087 12:18:19.695862 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10089 12:18:19.796231 asurada: tftpboot 192.168.201.1 11893118/tftp-deploy-wopfvvj9/kernel/image.itb 11893118/tftp-deploy-wopfvvj9/kernel/cmdline
10090 12:18:19.796376 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 12:18:19.796474 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10092 12:18:19.800839 tftpboot 192.168.201.1 11893118/tftp-deploy-wopfvvj9/kernel/image.itp-deploy-wopfvvj9/kernel/cmdline
10093 12:18:19.800983
10094 12:18:19.801084 Waiting for link
10095 12:18:19.961161
10096 12:18:19.961281 R8152: Initializing
10097 12:18:19.961357
10098 12:18:19.964349 Version 9 (ocp_data = 6010)
10099 12:18:19.964420
10100 12:18:19.967681 R8152: Done initializing
10101 12:18:19.967753
10102 12:18:19.967815 Adding net device
10103 12:18:21.913655
10104 12:18:21.913790 done.
10105 12:18:21.913868
10106 12:18:21.913940 MAC: 00:e0:4c:72:2d:d6
10107 12:18:21.914005
10108 12:18:21.916669 Sending DHCP discover... done.
10109 12:18:21.916770
10110 12:18:21.919738 Waiting for reply... done.
10111 12:18:21.919844
10112 12:18:21.923130 Sending DHCP request... done.
10113 12:18:21.923234
10114 12:18:21.930797 Waiting for reply... done.
10115 12:18:21.930909
10116 12:18:21.931004 My ip is 192.168.201.21
10117 12:18:21.931094
10118 12:18:21.933846 The DHCP server ip is 192.168.201.1
10119 12:18:21.933945
10120 12:18:21.940867 TFTP server IP predefined by user: 192.168.201.1
10121 12:18:21.940976
10122 12:18:21.947061 Bootfile predefined by user: 11893118/tftp-deploy-wopfvvj9/kernel/image.itb
10123 12:18:21.947172
10124 12:18:21.950495 Sending tftp read request... done.
10125 12:18:21.950598
10126 12:18:21.950697 Waiting for the transfer...
10127 12:18:21.953561
10128 12:18:22.209271 00000000 ################################################################
10129 12:18:22.209423
10130 12:18:22.473389 00080000 ################################################################
10131 12:18:22.473523
10132 12:18:22.730329 00100000 ################################################################
10133 12:18:22.730461
10134 12:18:22.979536 00180000 ################################################################
10135 12:18:22.979672
10136 12:18:23.248088 00200000 ################################################################
10137 12:18:23.248253
10138 12:18:23.525795 00280000 ################################################################
10139 12:18:23.525958
10140 12:18:23.790518 00300000 ################################################################
10141 12:18:23.790674
10142 12:18:24.057883 00380000 ################################################################
10143 12:18:24.058041
10144 12:18:24.333516 00400000 ################################################################
10145 12:18:24.333658
10146 12:18:24.607203 00480000 ################################################################
10147 12:18:24.607363
10148 12:18:24.863813 00500000 ################################################################
10149 12:18:24.863953
10150 12:18:25.140142 00580000 ################################################################
10151 12:18:25.140307
10152 12:18:25.395217 00600000 ################################################################
10153 12:18:25.395353
10154 12:18:25.643637 00680000 ################################################################
10155 12:18:25.643807
10156 12:18:25.888109 00700000 ################################################################
10157 12:18:25.888246
10158 12:18:26.145919 00780000 ################################################################
10159 12:18:26.146060
10160 12:18:26.391734 00800000 ################################################################
10161 12:18:26.391895
10162 12:18:26.661443 00880000 ################################################################
10163 12:18:26.661609
10164 12:18:26.912248 00900000 ################################################################
10165 12:18:26.912390
10166 12:18:27.159369 00980000 ################################################################
10167 12:18:27.159551
10168 12:18:27.424256 00a00000 ################################################################
10169 12:18:27.424433
10170 12:18:27.686812 00a80000 ################################################################
10171 12:18:27.686988
10172 12:18:27.933911 00b00000 ################################################################
10173 12:18:27.934057
10174 12:18:28.182497 00b80000 ################################################################
10175 12:18:28.182654
10176 12:18:28.439057 00c00000 ################################################################
10177 12:18:28.439194
10178 12:18:28.688634 00c80000 ################################################################
10179 12:18:28.688780
10180 12:18:28.941832 00d00000 ################################################################
10181 12:18:28.941975
10182 12:18:29.195549 00d80000 ################################################################
10183 12:18:29.195686
10184 12:18:29.443989 00e00000 ################################################################
10185 12:18:29.444128
10186 12:18:29.693162 00e80000 ################################################################
10187 12:18:29.693304
10188 12:18:29.942683 00f00000 ################################################################
10189 12:18:29.942837
10190 12:18:30.191395 00f80000 ################################################################
10191 12:18:30.191545
10192 12:18:30.464903 01000000 ################################################################
10193 12:18:30.465070
10194 12:18:30.728242 01080000 ################################################################
10195 12:18:30.728387
10196 12:18:30.982821 01100000 ################################################################
10197 12:18:30.982962
10198 12:18:31.231723 01180000 ################################################################
10199 12:18:31.231864
10200 12:18:31.480088 01200000 ################################################################
10201 12:18:31.480244
10202 12:18:31.771340 01280000 ################################################################
10203 12:18:31.771484
10204 12:18:32.060644 01300000 ################################################################
10205 12:18:32.060801
10206 12:18:32.353402 01380000 ################################################################
10207 12:18:32.353556
10208 12:18:32.642466 01400000 ################################################################
10209 12:18:32.642610
10210 12:18:32.931358 01480000 ################################################################
10211 12:18:32.931494
10212 12:18:33.230650 01500000 ################################################################
10213 12:18:33.230806
10214 12:18:33.519501 01580000 ################################################################
10215 12:18:33.519652
10216 12:18:33.774476 01600000 ################################################################
10217 12:18:33.774622
10218 12:18:34.023251 01680000 ################################################################
10219 12:18:34.023413
10220 12:18:34.279589 01700000 ################################################################
10221 12:18:34.279754
10222 12:18:34.527409 01780000 ################################################################
10223 12:18:34.527562
10224 12:18:34.799095 01800000 ################################################################
10225 12:18:34.799275
10226 12:18:35.049237 01880000 ################################################################
10227 12:18:35.049390
10228 12:18:35.307883 01900000 ################################################################
10229 12:18:35.308069
10230 12:18:35.564735 01980000 ################################################################
10231 12:18:35.564917
10232 12:18:35.815649 01a00000 ################################################################
10233 12:18:35.815833
10234 12:18:36.056961 01a80000 ################################################################
10235 12:18:36.057130
10236 12:18:36.304109 01b00000 ################################################################
10237 12:18:36.304265
10238 12:18:36.330845 01b80000 ######## done.
10239 12:18:36.330944
10240 12:18:36.334220 The bootfile was 28894758 bytes long.
10241 12:18:36.334308
10242 12:18:36.337662 Sending tftp read request... done.
10243 12:18:36.337769
10244 12:18:36.340903 Waiting for the transfer...
10245 12:18:36.340996
10246 12:18:36.341066 00000000 # done.
10247 12:18:36.341132
10248 12:18:36.347605 Command line loaded dynamically from TFTP file: 11893118/tftp-deploy-wopfvvj9/kernel/cmdline
10249 12:18:36.350865
10250 12:18:36.371100 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893118/extract-nfsrootfs-o9tlk6ze,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10251 12:18:36.371193
10252 12:18:36.371262 Loading FIT.
10253 12:18:36.371327
10254 12:18:36.374237 Image ramdisk-1 has 17797451 bytes.
10255 12:18:36.374324
10256 12:18:36.377597 Image fdt-1 has 47278 bytes.
10257 12:18:36.377684
10258 12:18:36.380806 Image kernel-1 has 11047994 bytes.
10259 12:18:36.380892
10260 12:18:36.391130 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10261 12:18:36.391218
10262 12:18:36.407706 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10263 12:18:36.407805
10264 12:18:36.414365 Choosing best match conf-1 for compat google,spherion-rev2.
10265 12:18:36.414476
10266 12:18:36.421880 Connected to device vid:did:rid of 1ae0:0028:00
10267 12:18:36.430010
10268 12:18:36.433218 tpm_get_response: command 0x17b, return code 0x0
10269 12:18:36.433304
10270 12:18:36.436547 ec_init: CrosEC protocol v3 supported (256, 248)
10271 12:18:36.441680
10272 12:18:36.444783 tpm_cleanup: add release locality here.
10273 12:18:36.444894
10274 12:18:36.444985 Shutting down all USB controllers.
10275 12:18:36.448229
10276 12:18:36.448313 Removing current net device
10277 12:18:36.448381
10278 12:18:36.455073 Exiting depthcharge with code 4 at timestamp: 50091336
10279 12:18:36.455158
10280 12:18:36.458558 LZMA decompressing kernel-1 to 0x821a6718
10281 12:18:36.458643
10282 12:18:36.461936 LZMA decompressing kernel-1 to 0x40000000
10283 12:18:37.851025
10284 12:18:37.851187 jumping to kernel
10285 12:18:37.851653 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10286 12:18:37.851759 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10287 12:18:37.851840 Setting prompt string to ['Linux version [0-9]']
10288 12:18:37.851923 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10289 12:18:37.851996 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10290 12:18:37.932601
10291 12:18:37.936064 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10292 12:18:37.939375 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10293 12:18:37.939497 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10294 12:18:37.939601 Setting prompt string to []
10295 12:18:37.939708 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10296 12:18:37.939814 Using line separator: #'\n'#
10297 12:18:37.939910 No login prompt set.
10298 12:18:37.940005 Parsing kernel messages
10299 12:18:37.940092 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10300 12:18:37.940202 [login-action] Waiting for messages, (timeout 00:04:03)
10301 12:18:37.959264 [ 0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023
10302 12:18:37.962699 [ 0.000000] random: crng init done
10303 12:18:37.965743 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10304 12:18:37.969305 [ 0.000000] efi: UEFI not found.
10305 12:18:37.979424 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10306 12:18:37.986279 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10307 12:18:37.995548 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10308 12:18:38.005564 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10309 12:18:38.012509 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10310 12:18:38.015554 [ 0.000000] printk: bootconsole [mtk8250] enabled
10311 12:18:38.024262 [ 0.000000] NUMA: No NUMA configuration found
10312 12:18:38.031315 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10313 12:18:38.037674 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10314 12:18:38.037783 [ 0.000000] Zone ranges:
10315 12:18:38.044310 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10316 12:18:38.047587 [ 0.000000] DMA32 empty
10317 12:18:38.054476 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10318 12:18:38.057713 [ 0.000000] Movable zone start for each node
10319 12:18:38.061076 [ 0.000000] Early memory node ranges
10320 12:18:38.067713 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10321 12:18:38.074354 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10322 12:18:38.080913 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10323 12:18:38.087539 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10324 12:18:38.094069 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10325 12:18:38.100687 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10326 12:18:38.157051 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10327 12:18:38.163399 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10328 12:18:38.170060 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10329 12:18:38.173249 [ 0.000000] psci: probing for conduit method from DT.
10330 12:18:38.180174 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10331 12:18:38.183381 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10332 12:18:38.190189 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10333 12:18:38.193491 [ 0.000000] psci: SMC Calling Convention v1.2
10334 12:18:38.200200 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10335 12:18:38.203382 [ 0.000000] Detected VIPT I-cache on CPU0
10336 12:18:38.209964 [ 0.000000] CPU features: detected: GIC system register CPU interface
10337 12:18:38.216834 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10338 12:18:38.223483 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10339 12:18:38.230176 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10340 12:18:38.236918 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10341 12:18:38.243164 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10342 12:18:38.249868 [ 0.000000] alternatives: applying boot alternatives
10343 12:18:38.253515 [ 0.000000] Fallback order for Node 0: 0
10344 12:18:38.260007 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10345 12:18:38.263376 [ 0.000000] Policy zone: Normal
10346 12:18:38.286202 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893118/extract-nfsrootfs-o9tlk6ze,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10347 12:18:38.299765 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10348 12:18:38.309923 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10349 12:18:38.319720 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10350 12:18:38.326285 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10351 12:18:38.329612 <6>[ 0.000000] software IO TLB: area num 8.
10352 12:18:38.385806 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10353 12:18:38.535457 <6>[ 0.000000] Memory: 7952108K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 400660K reserved, 32768K cma-reserved)
10354 12:18:38.541865 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10355 12:18:38.548529 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10356 12:18:38.551877 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10357 12:18:38.558204 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10358 12:18:38.564916 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10359 12:18:38.568685 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10360 12:18:38.578480 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10361 12:18:38.584894 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10362 12:18:38.588382 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10363 12:18:38.596047 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10364 12:18:38.599638 <6>[ 0.000000] GICv3: 608 SPIs implemented
10365 12:18:38.606048 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10366 12:18:38.609664 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10367 12:18:38.612837 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10368 12:18:38.622814 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10369 12:18:38.632999 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10370 12:18:38.646146 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10371 12:18:38.652872 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10372 12:18:38.661606 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10373 12:18:38.674978 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10374 12:18:38.681568 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10375 12:18:38.688362 <6>[ 0.009229] Console: colour dummy device 80x25
10376 12:18:38.698088 <6>[ 0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10377 12:18:38.704707 <6>[ 0.024397] pid_max: default: 32768 minimum: 301
10378 12:18:38.708314 <6>[ 0.029299] LSM: Security Framework initializing
10379 12:18:38.714712 <6>[ 0.034237] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10380 12:18:38.724685 <6>[ 0.042052] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10381 12:18:38.731222 <6>[ 0.051466] cblist_init_generic: Setting adjustable number of callback queues.
10382 12:18:38.737866 <6>[ 0.058908] cblist_init_generic: Setting shift to 3 and lim to 1.
10383 12:18:38.747961 <6>[ 0.065247] cblist_init_generic: Setting adjustable number of callback queues.
10384 12:18:38.751263 <6>[ 0.072673] cblist_init_generic: Setting shift to 3 and lim to 1.
10385 12:18:38.758019 <6>[ 0.079074] rcu: Hierarchical SRCU implementation.
10386 12:18:38.764539 <6>[ 0.084090] rcu: Max phase no-delay instances is 1000.
10387 12:18:38.771232 <6>[ 0.091112] EFI services will not be available.
10388 12:18:38.774599 <6>[ 0.096067] smp: Bringing up secondary CPUs ...
10389 12:18:38.782594 <6>[ 0.101118] Detected VIPT I-cache on CPU1
10390 12:18:38.789450 <6>[ 0.101189] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10391 12:18:38.795921 <6>[ 0.101219] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10392 12:18:38.799019 <6>[ 0.101558] Detected VIPT I-cache on CPU2
10393 12:18:38.805736 <6>[ 0.101610] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10394 12:18:38.812526 <6>[ 0.101628] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10395 12:18:38.819174 <6>[ 0.101888] Detected VIPT I-cache on CPU3
10396 12:18:38.825668 <6>[ 0.101934] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10397 12:18:38.832357 <6>[ 0.101948] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10398 12:18:38.835521 <6>[ 0.102253] CPU features: detected: Spectre-v4
10399 12:18:38.842048 <6>[ 0.102259] CPU features: detected: Spectre-BHB
10400 12:18:38.845437 <6>[ 0.102264] Detected PIPT I-cache on CPU4
10401 12:18:38.852774 <6>[ 0.102320] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10402 12:18:38.858849 <6>[ 0.102337] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10403 12:18:38.865443 <6>[ 0.102632] Detected PIPT I-cache on CPU5
10404 12:18:38.872260 <6>[ 0.102695] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10405 12:18:38.878870 <6>[ 0.102711] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10406 12:18:38.882230 <6>[ 0.102995] Detected PIPT I-cache on CPU6
10407 12:18:38.888843 <6>[ 0.103060] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10408 12:18:38.895191 <6>[ 0.103076] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10409 12:18:38.902272 <6>[ 0.103375] Detected PIPT I-cache on CPU7
10410 12:18:38.908957 <6>[ 0.103441] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10411 12:18:38.915590 <6>[ 0.103457] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10412 12:18:38.919022 <6>[ 0.103503] smp: Brought up 1 node, 8 CPUs
10413 12:18:38.925638 <6>[ 0.244859] SMP: Total of 8 processors activated.
10414 12:18:38.928534 <6>[ 0.249780] CPU features: detected: 32-bit EL0 Support
10415 12:18:38.938469 <6>[ 0.255143] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10416 12:18:38.945322 <6>[ 0.263961] CPU features: detected: Common not Private translations
10417 12:18:38.948710 <6>[ 0.270436] CPU features: detected: CRC32 instructions
10418 12:18:38.955275 <6>[ 0.275821] CPU features: detected: RCpc load-acquire (LDAPR)
10419 12:18:38.962057 <6>[ 0.281781] CPU features: detected: LSE atomic instructions
10420 12:18:38.968613 <6>[ 0.287562] CPU features: detected: Privileged Access Never
10421 12:18:38.971779 <6>[ 0.293342] CPU features: detected: RAS Extension Support
10422 12:18:38.978565 <6>[ 0.298986] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10423 12:18:38.985616 <6>[ 0.306250] CPU: All CPU(s) started at EL2
10424 12:18:38.991872 <6>[ 0.310567] alternatives: applying system-wide alternatives
10425 12:18:39.000605 <6>[ 0.321277] devtmpfs: initialized
10426 12:18:39.012913 <6>[ 0.330207] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10427 12:18:39.022737 <6>[ 0.340168] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10428 12:18:39.029565 <6>[ 0.348187] pinctrl core: initialized pinctrl subsystem
10429 12:18:39.032457 <6>[ 0.354877] DMI not present or invalid.
10430 12:18:39.039390 <6>[ 0.359287] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10431 12:18:39.049087 <6>[ 0.366155] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10432 12:18:39.055928 <6>[ 0.373726] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10433 12:18:39.065818 <6>[ 0.381939] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10434 12:18:39.068671 <6>[ 0.390183] audit: initializing netlink subsys (disabled)
10435 12:18:39.078896 <5>[ 0.395882] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10436 12:18:39.085689 <6>[ 0.396590] thermal_sys: Registered thermal governor 'step_wise'
10437 12:18:39.091991 <6>[ 0.403853] thermal_sys: Registered thermal governor 'power_allocator'
10438 12:18:39.095387 <6>[ 0.410110] cpuidle: using governor menu
10439 12:18:39.102565 <6>[ 0.421075] NET: Registered PF_QIPCRTR protocol family
10440 12:18:39.108768 <6>[ 0.426568] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10441 12:18:39.112094 <6>[ 0.433673] ASID allocator initialised with 32768 entries
10442 12:18:39.119406 <6>[ 0.440258] Serial: AMBA PL011 UART driver
10443 12:18:39.128255 <4>[ 0.449049] Trying to register duplicate clock ID: 134
10444 12:18:39.184001 <6>[ 0.508299] KASLR enabled
10445 12:18:39.198564 <6>[ 0.515977] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10446 12:18:39.204805 <6>[ 0.522992] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10447 12:18:39.211319 <6>[ 0.529484] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10448 12:18:39.218194 <6>[ 0.536493] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10449 12:18:39.224792 <6>[ 0.542983] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10450 12:18:39.231425 <6>[ 0.549991] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10451 12:18:39.237924 <6>[ 0.556482] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10452 12:18:39.244580 <6>[ 0.563487] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10453 12:18:39.248051 <6>[ 0.570961] ACPI: Interpreter disabled.
10454 12:18:39.256127 <6>[ 0.577371] iommu: Default domain type: Translated
10455 12:18:39.262927 <6>[ 0.582520] iommu: DMA domain TLB invalidation policy: strict mode
10456 12:18:39.266552 <5>[ 0.589182] SCSI subsystem initialized
10457 12:18:39.273107 <6>[ 0.593433] usbcore: registered new interface driver usbfs
10458 12:18:39.279859 <6>[ 0.599166] usbcore: registered new interface driver hub
10459 12:18:39.282915 <6>[ 0.604721] usbcore: registered new device driver usb
10460 12:18:39.289988 <6>[ 0.610836] pps_core: LinuxPPS API ver. 1 registered
10461 12:18:39.299765 <6>[ 0.616031] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10462 12:18:39.303041 <6>[ 0.625376] PTP clock support registered
10463 12:18:39.306347 <6>[ 0.629622] EDAC MC: Ver: 3.0.0
10464 12:18:39.313971 <6>[ 0.634828] FPGA manager framework
10465 12:18:39.320323 <6>[ 0.638505] Advanced Linux Sound Architecture Driver Initialized.
10466 12:18:39.323832 <6>[ 0.645283] vgaarb: loaded
10467 12:18:39.330328 <6>[ 0.648455] clocksource: Switched to clocksource arch_sys_counter
10468 12:18:39.333695 <5>[ 0.654902] VFS: Disk quotas dquot_6.6.0
10469 12:18:39.339989 <6>[ 0.659088] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10470 12:18:39.343279 <6>[ 0.666283] pnp: PnP ACPI: disabled
10471 12:18:39.352090 <6>[ 0.672967] NET: Registered PF_INET protocol family
10472 12:18:39.361692 <6>[ 0.678553] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10473 12:18:39.373406 <6>[ 0.690867] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10474 12:18:39.383442 <6>[ 0.699687] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10475 12:18:39.389682 <6>[ 0.707660] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10476 12:18:39.396490 <6>[ 0.716367] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10477 12:18:39.408556 <6>[ 0.726078] TCP: Hash tables configured (established 65536 bind 65536)
10478 12:18:39.415265 <6>[ 0.732940] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10479 12:18:39.421936 <6>[ 0.740141] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10480 12:18:39.428439 <6>[ 0.747843] NET: Registered PF_UNIX/PF_LOCAL protocol family
10481 12:18:39.435138 <6>[ 0.754014] RPC: Registered named UNIX socket transport module.
10482 12:18:39.438449 <6>[ 0.760173] RPC: Registered udp transport module.
10483 12:18:39.445243 <6>[ 0.765107] RPC: Registered tcp transport module.
10484 12:18:39.452076 <6>[ 0.770040] RPC: Registered tcp NFSv4.1 backchannel transport module.
10485 12:18:39.454827 <6>[ 0.776709] PCI: CLS 0 bytes, default 64
10486 12:18:39.458316 <6>[ 0.781144] Unpacking initramfs...
10487 12:18:39.468348 <6>[ 0.785350] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10488 12:18:39.474623 <6>[ 0.794002] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10489 12:18:39.482184 <6>[ 0.802853] kvm [1]: IPA Size Limit: 40 bits
10490 12:18:39.485189 <6>[ 0.807384] kvm [1]: GICv3: no GICV resource entry
10491 12:18:39.491940 <6>[ 0.812409] kvm [1]: disabling GICv2 emulation
10492 12:18:39.498381 <6>[ 0.817096] kvm [1]: GIC system register CPU interface enabled
10493 12:18:39.501961 <6>[ 0.823279] kvm [1]: vgic interrupt IRQ18
10494 12:18:39.508303 <6>[ 0.828508] kvm [1]: VHE mode initialized successfully
10495 12:18:39.515069 <5>[ 0.834992] Initialise system trusted keyrings
10496 12:18:39.521389 <6>[ 0.839790] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10497 12:18:39.528749 <6>[ 0.849800] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10498 12:18:39.535552 <5>[ 0.856169] NFS: Registering the id_resolver key type
10499 12:18:39.538663 <5>[ 0.861491] Key type id_resolver registered
10500 12:18:39.545170 <5>[ 0.865908] Key type id_legacy registered
10501 12:18:39.552240 <6>[ 0.870187] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10502 12:18:39.558734 <6>[ 0.877112] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10503 12:18:39.565031 <6>[ 0.884862] 9p: Installing v9fs 9p2000 file system support
10504 12:18:39.602021 <5>[ 0.922964] Key type asymmetric registered
10505 12:18:39.605312 <5>[ 0.927298] Asymmetric key parser 'x509' registered
10506 12:18:39.614931 <6>[ 0.932438] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10507 12:18:39.618673 <6>[ 0.940059] io scheduler mq-deadline registered
10508 12:18:39.621535 <6>[ 0.944824] io scheduler kyber registered
10509 12:18:39.641053 <6>[ 0.962046] EINJ: ACPI disabled.
10510 12:18:39.674301 <4>[ 0.988663] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10511 12:18:39.684019 <4>[ 0.999298] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10512 12:18:39.699128 <6>[ 1.020357] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10513 12:18:39.707062 <6>[ 1.028343] printk: console [ttyS0] disabled
10514 12:18:39.735048 <6>[ 1.052997] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10515 12:18:39.741983 <6>[ 1.062474] printk: console [ttyS0] enabled
10516 12:18:39.745556 <6>[ 1.062474] printk: console [ttyS0] enabled
10517 12:18:39.752287 <6>[ 1.071368] printk: bootconsole [mtk8250] disabled
10518 12:18:39.755108 <6>[ 1.071368] printk: bootconsole [mtk8250] disabled
10519 12:18:39.761694 <6>[ 1.082684] SuperH (H)SCI(F) driver initialized
10520 12:18:39.764970 <6>[ 1.087971] msm_serial: driver initialized
10521 12:18:39.779021 <6>[ 1.097008] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10522 12:18:39.789161 <6>[ 1.105554] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10523 12:18:39.795954 <6>[ 1.114097] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10524 12:18:39.805662 <6>[ 1.122724] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10525 12:18:39.815493 <6>[ 1.131432] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10526 12:18:39.822786 <6>[ 1.140145] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10527 12:18:39.832144 <6>[ 1.148685] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10528 12:18:39.838803 <6>[ 1.157507] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10529 12:18:39.848536 <6>[ 1.166050] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10530 12:18:39.860524 <6>[ 1.181833] loop: module loaded
10531 12:18:39.867494 <6>[ 1.187847] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10532 12:18:39.890258 <4>[ 1.211238] mtk-pmic-keys: Failed to locate of_node [id: -1]
10533 12:18:39.897097 <6>[ 1.218159] megasas: 07.719.03.00-rc1
10534 12:18:39.906910 <6>[ 1.227714] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10535 12:18:39.915250 <6>[ 1.235881] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10536 12:18:39.931671 <6>[ 1.252627] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10537 12:18:39.988075 <6>[ 1.302565] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10538 12:18:40.201076 <6>[ 1.522240] Freeing initrd memory: 17380K
10539 12:18:40.211367 <6>[ 1.532508] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10540 12:18:40.222512 <6>[ 1.543401] tun: Universal TUN/TAP device driver, 1.6
10541 12:18:40.226000 <6>[ 1.549460] thunder_xcv, ver 1.0
10542 12:18:40.229322 <6>[ 1.552968] thunder_bgx, ver 1.0
10543 12:18:40.232225 <6>[ 1.556463] nicpf, ver 1.0
10544 12:18:40.243010 <6>[ 1.560482] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10545 12:18:40.246254 <6>[ 1.567957] hns3: Copyright (c) 2017 Huawei Corporation.
10546 12:18:40.249211 <6>[ 1.573545] hclge is initializing
10547 12:18:40.256284 <6>[ 1.577127] e1000: Intel(R) PRO/1000 Network Driver
10548 12:18:40.262803 <6>[ 1.582256] e1000: Copyright (c) 1999-2006 Intel Corporation.
10549 12:18:40.266038 <6>[ 1.588269] e1000e: Intel(R) PRO/1000 Network Driver
10550 12:18:40.272731 <6>[ 1.593484] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10551 12:18:40.279554 <6>[ 1.599669] igb: Intel(R) Gigabit Ethernet Network Driver
10552 12:18:40.285959 <6>[ 1.605319] igb: Copyright (c) 2007-2014 Intel Corporation.
10553 12:18:40.292813 <6>[ 1.611158] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10554 12:18:40.299233 <6>[ 1.617676] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10555 12:18:40.302591 <6>[ 1.624139] sky2: driver version 1.30
10556 12:18:40.309277 <6>[ 1.629147] VFIO - User Level meta-driver version: 0.3
10557 12:18:40.316384 <6>[ 1.637413] usbcore: registered new interface driver usb-storage
10558 12:18:40.322922 <6>[ 1.643864] usbcore: registered new device driver onboard-usb-hub
10559 12:18:40.332051 <6>[ 1.653005] mt6397-rtc mt6359-rtc: registered as rtc0
10560 12:18:40.342023 <6>[ 1.658474] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:18:18 UTC (1698409098)
10561 12:18:40.345128 <6>[ 1.668042] i2c_dev: i2c /dev entries driver
10562 12:18:40.362123 <6>[ 1.679821] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10563 12:18:40.381921 <6>[ 1.702813] cpu cpu0: EM: created perf domain
10564 12:18:40.385190 <6>[ 1.707745] cpu cpu4: EM: created perf domain
10565 12:18:40.392019 <6>[ 1.713325] sdhci: Secure Digital Host Controller Interface driver
10566 12:18:40.399022 <6>[ 1.719756] sdhci: Copyright(c) Pierre Ossman
10567 12:18:40.405555 <6>[ 1.724711] Synopsys Designware Multimedia Card Interface Driver
10568 12:18:40.408925 <6>[ 1.731300] mmc0: CQHCI version 5.10
10569 12:18:40.415524 <6>[ 1.731329] sdhci-pltfm: SDHCI platform and OF driver helper
10570 12:18:40.421960 <6>[ 1.742171] ledtrig-cpu: registered to indicate activity on CPUs
10571 12:18:40.428676 <6>[ 1.749148] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10572 12:18:40.435341 <6>[ 1.756214] usbcore: registered new interface driver usbhid
10573 12:18:40.438749 <6>[ 1.762038] usbhid: USB HID core driver
10574 12:18:40.445731 <6>[ 1.766231] spi_master spi0: will run message pump with realtime priority
10575 12:18:40.491706 <6>[ 1.806057] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10576 12:18:40.506943 <6>[ 1.821374] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10577 12:18:40.514009 <6>[ 1.834953] mmc0: Command Queue Engine enabled
10578 12:18:40.520873 <6>[ 1.836869] cros-ec-spi spi0.0: Chrome EC device registered
10579 12:18:40.524523 <6>[ 1.839682] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10580 12:18:40.531432 <6>[ 1.852784] mmcblk0: mmc0:0001 DA4128 116 GiB
10581 12:18:40.541752 <6>[ 1.859631] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10582 12:18:40.548767 <6>[ 1.863091] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10583 12:18:40.555523 <6>[ 1.870051] NET: Registered PF_PACKET protocol family
10584 12:18:40.558695 <6>[ 1.876146] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10585 12:18:40.565477 <6>[ 1.880244] 9pnet: Installing 9P2000 support
10586 12:18:40.568718 <6>[ 1.886091] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10587 12:18:40.571929 <5>[ 1.889950] Key type dns_resolver registered
10588 12:18:40.578630 <6>[ 1.895825] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10589 12:18:40.585366 <6>[ 1.900169] registered taskstats version 1
10590 12:18:40.588853 <5>[ 1.910559] Loading compiled-in X.509 certificates
10591 12:18:40.617590 <4>[ 1.931882] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 12:18:40.627588 <4>[ 1.942615] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 12:18:40.634225 <3>[ 1.953143] debugfs: File 'uA_load' in directory '/' already present!
10594 12:18:40.640576 <3>[ 1.959841] debugfs: File 'min_uV' in directory '/' already present!
10595 12:18:40.647373 <3>[ 1.966447] debugfs: File 'max_uV' in directory '/' already present!
10596 12:18:40.653937 <3>[ 1.973115] debugfs: File 'constraint_flags' in directory '/' already present!
10597 12:18:40.664545 <3>[ 1.982503] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10598 12:18:40.673534 <6>[ 1.994811] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10599 12:18:40.680614 <6>[ 2.001719] xhci-mtk 11200000.usb: xHCI Host Controller
10600 12:18:40.687104 <6>[ 2.007229] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10601 12:18:40.697531 <6>[ 2.015093] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10602 12:18:40.703895 <6>[ 2.024529] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10603 12:18:40.710552 <6>[ 2.030605] xhci-mtk 11200000.usb: xHCI Host Controller
10604 12:18:40.717378 <6>[ 2.036087] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10605 12:18:40.723929 <6>[ 2.043740] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10606 12:18:40.730676 <6>[ 2.051419] hub 1-0:1.0: USB hub found
10607 12:18:40.733995 <6>[ 2.055428] hub 1-0:1.0: 1 port detected
10608 12:18:40.740634 <6>[ 2.059700] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10609 12:18:40.747144 <6>[ 2.068324] hub 2-0:1.0: USB hub found
10610 12:18:40.750581 <6>[ 2.072341] hub 2-0:1.0: 1 port detected
10611 12:18:40.759823 <6>[ 2.080533] mtk-msdc 11f70000.mmc: Got CD GPIO
10612 12:18:40.769591 <6>[ 2.086909] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10613 12:18:40.776251 <6>[ 2.094932] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10614 12:18:40.786575 <4>[ 2.102833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10615 12:18:40.792843 <6>[ 2.112356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10616 12:18:40.803157 <6>[ 2.120435] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10617 12:18:40.809682 <6>[ 2.128525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10618 12:18:40.819704 <6>[ 2.136437] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10619 12:18:40.826245 <6>[ 2.144255] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10620 12:18:40.836240 <6>[ 2.152073] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10621 12:18:40.846656 <6>[ 2.162560] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10622 12:18:40.853383 <6>[ 2.170919] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10623 12:18:40.863234 <6>[ 2.179262] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10624 12:18:40.869710 <6>[ 2.187600] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10625 12:18:40.876365 <6>[ 2.195947] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10626 12:18:40.886615 <6>[ 2.204286] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10627 12:18:40.896137 <6>[ 2.212624] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10628 12:18:40.902894 <6>[ 2.220964] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10629 12:18:40.909675 <6>[ 2.229301] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10630 12:18:40.919839 <6>[ 2.237639] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10631 12:18:40.926448 <6>[ 2.245978] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10632 12:18:40.936595 <6>[ 2.254316] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10633 12:18:40.943416 <6>[ 2.262665] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10634 12:18:40.953218 <6>[ 2.271003] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10635 12:18:40.963292 <6>[ 2.279341] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10636 12:18:40.969515 <6>[ 2.288090] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10637 12:18:40.976327 <6>[ 2.295238] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10638 12:18:40.982895 <6>[ 2.302019] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10639 12:18:40.989801 <6>[ 2.308786] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10640 12:18:40.996237 <6>[ 2.315721] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10641 12:18:41.006338 <6>[ 2.322571] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10642 12:18:41.016351 <6>[ 2.331702] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10643 12:18:41.022809 <6>[ 2.340854] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10644 12:18:41.032938 <6>[ 2.350150] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10645 12:18:41.042704 <6>[ 2.359620] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10646 12:18:41.052511 <6>[ 2.369087] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10647 12:18:41.062468 <6>[ 2.378207] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10648 12:18:41.068952 <6>[ 2.387673] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10649 12:18:41.079046 <6>[ 2.396793] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10650 12:18:41.089070 <6>[ 2.406088] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10651 12:18:41.098721 <6>[ 2.416249] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10652 12:18:41.109943 <6>[ 2.427836] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10653 12:18:41.116591 <6>[ 2.437459] Trying to probe devices needed for running init ...
10654 12:18:41.150557 <6>[ 2.468601] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10655 12:18:41.305501 <6>[ 2.626837] hub 1-1:1.0: USB hub found
10656 12:18:41.308836 <6>[ 2.631390] hub 1-1:1.0: 4 ports detected
10657 12:18:41.431210 <6>[ 2.749002] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10658 12:18:41.456799 <6>[ 2.778220] hub 2-1:1.0: USB hub found
10659 12:18:41.460092 <6>[ 2.782688] hub 2-1:1.0: 3 ports detected
10660 12:18:41.630862 <6>[ 2.948798] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10661 12:18:41.763097 <6>[ 3.084177] hub 1-1.4:1.0: USB hub found
10662 12:18:41.766299 <6>[ 3.088840] hub 1-1.4:1.0: 2 ports detected
10663 12:18:41.842678 <6>[ 3.160899] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10664 12:18:42.062792 <6>[ 3.380773] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10665 12:18:42.254822 <6>[ 3.572738] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10666 12:18:53.415984 <6>[ 14.741741] ALSA device list:
10667 12:18:53.422533 <6>[ 14.745034] No soundcards found.
10668 12:18:53.430791 <6>[ 14.752996] Freeing unused kernel memory: 8384K
10669 12:18:53.433819 <6>[ 14.757984] Run /init as init process
10670 12:18:53.445157 Loading, please wait...
10671 12:18:53.465699 Starting version 247.3-7+deb11u2
10672 12:18:53.698113 <6>[ 15.017235] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10673 12:18:53.704712 <6>[ 15.024923] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10674 12:18:53.714755 <3>[ 15.027478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 12:18:53.721042 <6>[ 15.033626] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10676 12:18:53.727465 <6>[ 15.042153] usbcore: registered new interface driver r8152
10677 12:18:53.737817 <3>[ 15.050431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 12:18:53.744538 <3>[ 15.064257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 12:18:53.750789 <6>[ 15.065133] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10680 12:18:53.760764 <4>[ 15.071103] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10681 12:18:53.767424 <4>[ 15.075485] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10682 12:18:53.774003 <3>[ 15.075550] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 12:18:53.783822 <3>[ 15.075566] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 12:18:53.790414 <3>[ 15.075569] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 12:18:53.800720 <3>[ 15.075575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 12:18:53.807310 <3>[ 15.075578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 12:18:53.810586 <6>[ 15.082008] mc: Linux media interface: v0.10
10688 12:18:53.816821 <6>[ 15.083022] remoteproc remoteproc0: scp is available
10689 12:18:53.823744 <6>[ 15.083071] remoteproc remoteproc0: powering up scp
10690 12:18:53.830488 <6>[ 15.083074] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10691 12:18:53.837167 <6>[ 15.083090] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10692 12:18:53.844017 <3>[ 15.101619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 12:18:53.853735 <6>[ 15.106317] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10694 12:18:53.860423 <3>[ 15.110764] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 12:18:53.870166 <4>[ 15.131708] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10696 12:18:53.873658 <4>[ 15.131708] Fallback method does not support PEC.
10697 12:18:53.883613 <3>[ 15.134858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 12:18:53.890111 <6>[ 15.154080] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10699 12:18:53.897258 <3>[ 15.158170] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 12:18:53.906706 <3>[ 15.158941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 12:18:53.909876 <6>[ 15.164206] pci_bus 0000:00: root bus resource [bus 00-ff]
10702 12:18:53.920582 <6>[ 15.172236] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10703 12:18:53.926637 <3>[ 15.172249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 12:18:53.933490 <3>[ 15.172252] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10705 12:18:53.943122 <3>[ 15.172258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 12:18:53.949876 <3>[ 15.172260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 12:18:53.960102 <3>[ 15.172288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 12:18:53.966384 <3>[ 15.172370] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10709 12:18:53.976483 <6>[ 15.270947] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10710 12:18:53.983283 <6>[ 15.278796] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10711 12:18:53.989604 <6>[ 15.278798] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10712 12:18:53.999800 <6>[ 15.278812] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10713 12:18:54.009637 <6>[ 15.278878] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10714 12:18:54.016270 <6>[ 15.278891] remoteproc remoteproc0: remote processor scp is now up
10715 12:18:54.023171 <6>[ 15.278921] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10716 12:18:54.029617 <6>[ 15.278943] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10717 12:18:54.036254 <6>[ 15.279044] pci 0000:00:00.0: supports D1 D2
10718 12:18:54.042996 <6>[ 15.279047] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10719 12:18:54.049460 <6>[ 15.280751] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10720 12:18:54.055912 <6>[ 15.280850] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10721 12:18:54.062491 <6>[ 15.280878] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10722 12:18:54.069199 <6>[ 15.280895] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10723 12:18:54.079250 <6>[ 15.280912] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10724 12:18:54.082769 <6>[ 15.281023] pci 0000:01:00.0: supports D1 D2
10725 12:18:54.089035 <6>[ 15.281026] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10726 12:18:54.095876 <6>[ 15.292648] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10727 12:18:54.105712 <6>[ 15.296616] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10728 12:18:54.115639 <4>[ 15.298206] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10729 12:18:54.122314 <4>[ 15.298212] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10730 12:18:54.132386 <6>[ 15.304974] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10731 12:18:54.142524 <6>[ 15.312588] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10732 12:18:54.148606 <6>[ 15.319078] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10733 12:18:54.155374 <6>[ 15.344418] videodev: Linux video capture interface: v2.00
10734 12:18:54.161803 <6>[ 15.350268] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10735 12:18:54.171812 <6>[ 15.350291] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10736 12:18:54.175661 <6>[ 15.350456] r8152 2-1.3:1.0 eth0: v1.12.13
10737 12:18:54.182075 <6>[ 15.358223] usbcore: registered new interface driver cdc_ether
10738 12:18:54.188668 <6>[ 15.362190] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10739 12:18:54.199088 <6>[ 15.363950] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10740 12:18:54.202503 <6>[ 15.377666] usbcore: registered new interface driver r8153_ecm
10741 12:18:54.208891 <6>[ 15.378067] Bluetooth: Core ver 2.22
10742 12:18:54.212546 <6>[ 15.378120] NET: Registered PF_BLUETOOTH protocol family
10743 12:18:54.219129 <6>[ 15.378122] Bluetooth: HCI device and connection manager initialized
10744 12:18:54.225426 <6>[ 15.378136] Bluetooth: HCI socket layer initialized
10745 12:18:54.228784 <6>[ 15.378140] Bluetooth: L2CAP socket layer initialized
10746 12:18:54.235674 <6>[ 15.378151] Bluetooth: SCO socket layer initialized
10747 12:18:54.242322 <6>[ 15.383603] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10748 12:18:54.248699 <6>[ 15.402441] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10749 12:18:54.255433 <6>[ 15.406000] pci 0000:00:00.0: PCI bridge to [bus 01]
10750 12:18:54.262201 <6>[ 15.419391] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10751 12:18:54.268720 <6>[ 15.424260] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10752 12:18:54.275207 <6>[ 15.425107] usbcore: registered new interface driver btusb
10753 12:18:54.285309 <4>[ 15.434800] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10754 12:18:54.298686 <6>[ 15.435673] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10755 12:18:54.305252 <6>[ 15.435818] usbcore: registered new interface driver uvcvideo
10756 12:18:54.311783 <6>[ 15.443677] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10757 12:18:54.315172 <3>[ 15.451524] Bluetooth: hci0: Failed to load firmware file (-2)
10758 12:18:54.321592 <6>[ 15.452182] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10759 12:18:54.328443 <6>[ 15.460126] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10760 12:18:54.334869 <3>[ 15.468631] Bluetooth: hci0: Failed to set up firmware (-2)
10761 12:18:54.341603 <6>[ 15.477469] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10762 12:18:54.351270 <4>[ 15.482436] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10763 12:18:54.358170 <5>[ 15.513212] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10764 12:18:54.367872 <3>[ 15.522929] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10765 12:18:54.374686 <5>[ 15.538365] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10766 12:18:54.384514 <4>[ 15.702905] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10767 12:18:54.387908 <6>[ 15.711786] cfg80211: failed to load regulatory.db
10768 12:18:54.435566 <6>[ 15.755186] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10769 12:18:54.442106 <6>[ 15.762691] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10770 12:18:54.466464 <6>[ 15.789323] mt7921e 0000:01:00.0: ASIC revision: 79610010
10771 12:18:54.571826 <4>[ 15.887958] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 12:18:54.574937 Begin: Loading essential drivers ... done.
10773 12:18:54.581835 Begin: Running /scripts/init-premount ... done.
10774 12:18:54.588312 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10775 12:18:54.598728 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10776 12:18:54.601694 Device /sys/class/net/enx00e04c722dd6 found
10777 12:18:54.601774 done.
10778 12:18:54.648961 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10779 12:18:54.690792 <4>[ 16.006763] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 12:18:54.809722 <4>[ 16.125800] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 12:18:54.925785 <4>[ 16.241768] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 12:18:55.041518 <4>[ 16.357684] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 12:18:55.157387 <4>[ 16.473624] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 12:18:55.273521 <4>[ 16.589618] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 12:18:55.389138 <4>[ 16.705520] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 12:18:55.504903 <4>[ 16.821471] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 12:18:55.620916 <4>[ 16.937337] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 12:18:55.678172 <6>[ 17.001014] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10789 12:18:55.728295 <3>[ 17.051372] mt7921e 0000:01:00.0: hardware init failed
10790 12:18:55.835830 IP-Config: no response after 2 secs - giving up
10791 12:18:55.884987 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10792 12:18:55.888337 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10793 12:18:55.894803 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10794 12:18:55.904617 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10795 12:18:55.911316 host : mt8192-asurada-spherion-r0-cbg-1
10796 12:18:55.917959 domain : lava-rack
10797 12:18:55.921087 rootserver: 192.168.201.1 rootpath:
10798 12:18:55.921174 filename :
10799 12:18:55.969738 done.
10800 12:18:55.976611 Begin: Running /scripts/nfs-bottom ... done.
10801 12:18:55.992843 Begin: Running /scripts/init-bottom ... done.
10802 12:18:57.167184 <6>[ 18.490414] NET: Registered PF_INET6 protocol family
10803 12:18:57.174762 <6>[ 18.497816] Segment Routing with IPv6
10804 12:18:57.178019 <6>[ 18.501843] In-situ OAM (IOAM) with IPv6
10805 12:18:57.293939 <30>[ 18.597096] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10806 12:18:57.297080 <30>[ 18.621498] systemd[1]: Detected architecture arm64.
10807 12:18:57.317172
10808 12:18:57.320229 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10809 12:18:57.320346
10810 12:18:57.335639 <30>[ 18.658622] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10811 12:18:58.077185 <30>[ 19.396736] systemd[1]: Queued start job for default target Graphical Interface.
10812 12:18:58.100350 <30>[ 19.423167] systemd[1]: Created slice system-getty.slice.
10813 12:18:58.106545 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10814 12:18:58.123009 <30>[ 19.446268] systemd[1]: Created slice system-modprobe.slice.
10815 12:18:58.129770 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10816 12:18:58.146759 <30>[ 19.470005] systemd[1]: Created slice system-serial\x2dgetty.slice.
10817 12:18:58.157232 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10818 12:18:58.170508 <30>[ 19.493834] systemd[1]: Created slice User and Session Slice.
10819 12:18:58.177319 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10820 12:18:58.197869 <30>[ 19.517598] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10821 12:18:58.207332 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10822 12:18:58.225815 <30>[ 19.545498] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10823 12:18:58.232223 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10824 12:18:58.256233 <30>[ 19.572900] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10825 12:18:58.263109 <30>[ 19.585047] systemd[1]: Reached target Local Encrypted Volumes.
10826 12:18:58.269590 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10827 12:18:58.285636 <30>[ 19.608890] systemd[1]: Reached target Paths.
10828 12:18:58.288955 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10829 12:18:58.305351 <30>[ 19.628790] systemd[1]: Reached target Remote File Systems.
10830 12:18:58.312277 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10831 12:18:58.329701 <30>[ 19.653110] systemd[1]: Reached target Slices.
10832 12:18:58.336408 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10833 12:18:58.349598 <30>[ 19.672764] systemd[1]: Reached target Swap.
10834 12:18:58.352647 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10835 12:18:58.373275 <30>[ 19.693253] systemd[1]: Listening on initctl Compatibility Named Pipe.
10836 12:18:58.380120 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10837 12:18:58.386836 <30>[ 19.709262] systemd[1]: Listening on Journal Audit Socket.
10838 12:18:58.393296 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10839 12:18:58.410777 <30>[ 19.733836] systemd[1]: Listening on Journal Socket (/dev/log).
10840 12:18:58.417303 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10841 12:18:58.434887 <30>[ 19.758007] systemd[1]: Listening on Journal Socket.
10842 12:18:58.441647 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10843 12:18:58.458410 <30>[ 19.778340] systemd[1]: Listening on Network Service Netlink Socket.
10844 12:18:58.465187 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10845 12:18:58.479915 <30>[ 19.803129] systemd[1]: Listening on udev Control Socket.
10846 12:18:58.486311 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10847 12:18:58.501880 <30>[ 19.825183] systemd[1]: Listening on udev Kernel Socket.
10848 12:18:58.508612 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10849 12:18:58.561649 <30>[ 19.884963] systemd[1]: Mounting Huge Pages File System...
10850 12:18:58.568243 Mounting [0;1;39mHuge Pages File System[0m...
10851 12:18:58.586260 <30>[ 19.909119] systemd[1]: Mounting POSIX Message Queue File System...
10852 12:18:58.592811 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10853 12:18:58.616783 <30>[ 19.940056] systemd[1]: Mounting Kernel Debug File System...
10854 12:18:58.623509 Mounting [0;1;39mKernel Debug File System[0m...
10855 12:18:58.640893 <30>[ 19.960966] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10856 12:18:58.655471 <30>[ 19.975470] systemd[1]: Starting Create list of static device nodes for the current kernel...
10857 12:18:58.665404 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10858 12:18:58.680443 <30>[ 20.003827] systemd[1]: Starting Load Kernel Module configfs...
10859 12:18:58.687014 Starting [0;1;39mLoad Kernel Module configfs[0m...
10860 12:18:58.706273 <30>[ 20.029608] systemd[1]: Starting Load Kernel Module drm...
10861 12:18:58.713077 Starting [0;1;39mLoad Kernel Module drm[0m...
10862 12:18:58.730196 <30>[ 20.053649] systemd[1]: Starting Load Kernel Module fuse...
10863 12:18:58.737071 Starting [0;1;39mLoad Kernel Module fuse[0m...
10864 12:18:58.762343 <6>[ 20.085105] fuse: init (API version 7.37)
10865 12:18:58.771652 <30>[ 20.086464] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10866 12:18:58.806541 <30>[ 20.129625] systemd[1]: Starting Journal Service...
10867 12:18:58.809905 Starting [0;1;39mJournal Service[0m...
10868 12:18:58.834654 <30>[ 20.157732] systemd[1]: Starting Load Kernel Modules...
10869 12:18:58.841174 Starting [0;1;39mLoad Kernel Modules[0m...
10870 12:18:58.862995 <30>[ 20.182946] systemd[1]: Starting Remount Root and Kernel File Systems...
10871 12:18:58.869487 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10872 12:18:58.887009 <30>[ 20.210359] systemd[1]: Starting Coldplug All udev Devices...
10873 12:18:58.893787 Starting [0;1;39mColdplug All udev Devices[0m...
10874 12:18:58.916346 <30>[ 20.239441] systemd[1]: Mounted Huge Pages File System.
10875 12:18:58.923671 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10876 12:18:58.930428 <3>[ 20.251180] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 12:18:58.938088 <30>[ 20.261530] systemd[1]: Mounted POSIX Message Queue File System.
10878 12:18:58.944846 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10879 12:18:58.961986 <30>[ 20.285112] systemd[1]: Mounted Kernel Debug File System.
10880 12:18:58.975614 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<3>[ 20.294025] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 12:18:58.975719 g File System[0m.
10882 12:18:58.997752 <30>[ 20.317521] systemd[1]: Finished Create list of static device nodes for the current kernel.
10883 12:18:59.004693 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10884 12:18:59.015070 <3>[ 20.334836] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 12:18:59.023030 <30>[ 20.346067] systemd[1]: modprobe@configfs.service: Succeeded.
10886 12:18:59.030116 <30>[ 20.353161] systemd[1]: Finished Load Kernel Module configfs.
10887 12:18:59.036874 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10888 12:18:59.048851 <3>[ 20.368759] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 12:18:59.055323 <30>[ 20.378468] systemd[1]: modprobe@drm.service: Succeeded.
10890 12:18:59.062297 <30>[ 20.385341] systemd[1]: Finished Load Kernel Module drm.
10891 12:18:59.068834 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10892 12:18:59.083770 <3>[ 20.403962] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 12:18:59.091443 <30>[ 20.414444] systemd[1]: modprobe@fuse.service: Succeeded.
10894 12:18:59.099527 <30>[ 20.422531] systemd[1]: Finished Load Kernel Module fuse.
10895 12:18:59.105906 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10896 12:18:59.119292 <3>[ 20.439055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:18:59.127141 <30>[ 20.450555] systemd[1]: Finished Load Kernel Modules.
10898 12:18:59.133840 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10899 12:18:59.147698 <30>[ 20.470830] systemd[1]: Finished Remount Root and Kernel File Systems.
10900 12:18:59.157597 <3>[ 20.474398] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 12:18:59.164096 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10902 12:18:59.191361 <3>[ 20.511492] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 12:18:59.206969 <30>[ 20.530403] systemd[1]: Mounting FUSE Control File System...
10904 12:18:59.214143 Mounting [0;1;39mFUSE Control File System[0m...
10905 12:18:59.224694 <3>[ 20.544701] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 12:18:59.238320 <30>[ 20.558527] systemd[1]: Mounting Kernel Configuration File System...
10907 12:18:59.241872 Mounting [0;1;39mKernel Configuration File System[0m...
10908 12:18:59.259990 <3>[ 20.580167] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 12:18:59.274007 <30>[ 20.593621] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10910 12:18:59.283628 <30>[ 20.602814] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10911 12:18:59.314760 <30>[ 20.637980] systemd[1]: Starting Load/Save Random Seed...
10912 12:18:59.321334 Starting [0;1;39mLoad/Save Random Seed[0m...
10913 12:18:59.343138 <30>[ 20.665728] systemd[1]: Starting Apply Kernel Variables...
10914 12:18:59.360015 <4>[ 20.671770] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10915 12:18:59.369954 Startin<3>[ 20.687478] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10916 12:18:59.372829 g [0;1;39mApply Kernel Variables[0m...
10917 12:18:59.394569 <30>[ 20.717906] systemd[1]: Starting Create System Users...
10918 12:18:59.401190 Starting [0;1;39mCreate System Users[0m...
10919 12:18:59.416507 <30>[ 20.739860] systemd[1]: Started Journal Service.
10920 12:18:59.423343 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10921 12:18:59.447045 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10922 12:18:59.461662 See 'systemctl status systemd-udev-trigger.service' for details.
10923 12:18:59.482334 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10924 12:18:59.498414 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10925 12:18:59.515429 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10926 12:18:59.531516 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10927 12:18:59.551075 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10928 12:18:59.602425 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10929 12:18:59.622183 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10930 12:18:59.668848 <46>[ 20.988943] systemd-journald[295]: Received client request to flush runtime journal.
10931 12:18:59.696744 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10932 12:18:59.710924 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10933 12:18:59.729699 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10934 12:18:59.790020 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10935 12:19:01.071457 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10936 12:19:01.125913 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10937 12:19:01.145499 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10938 12:19:01.174443 Starting [0;1;39mNetwork Service[0m...
10939 12:19:01.509351 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10940 12:19:01.540979 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10941 12:19:01.615365 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10942 12:19:01.821933 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10943 12:19:01.841514 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10944 12:19:01.898244 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10945 12:19:01.913941 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10946 12:19:01.934057 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10947 12:19:01.958501 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10948 12:19:01.998120 Starting [0;1;39mNetwork Name Resolution[0m...
10949 12:19:02.024144 Starting [0;1;39mNetwork Time Synchronization[0m...
10950 12:19:02.042752 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10951 12:19:02.058930 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10952 12:19:02.101980 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10953 12:19:02.201590 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10954 12:19:02.222421 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10955 12:19:02.240569 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10956 12:19:02.253073 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10957 12:19:02.269495 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10958 12:19:02.354538 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10959 12:19:02.458439 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10960 12:19:02.489959 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10961 12:19:02.519908 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10962 12:19:02.537371 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10963 12:19:02.566705 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10964 12:19:02.585345 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10965 12:19:02.601194 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10966 12:19:02.642297 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10967 12:19:02.695261 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10968 12:19:02.810662 Starting [0;1;39mUser Login Management[0m...
10969 12:19:02.829252 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10970 12:19:02.847349 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10971 12:19:02.865052 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10972 12:19:02.919399 Starting [0;1;39mPermit User Sessions[0m...
10973 12:19:03.013394 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10974 12:19:03.036484 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10975 12:19:03.068576 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10976 12:19:03.110877 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10977 12:19:03.127595 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10978 12:19:03.147439 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10979 12:19:03.166049 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10980 12:19:03.184790 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10981 12:19:03.234750 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10982 12:19:03.279306 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10983 12:19:03.358517
10984 12:19:03.358683
10985 12:19:03.361867 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10986 12:19:03.361952
10987 12:19:03.365067 debian-bullseye-arm64 login: root (automatic login)
10988 12:19:03.365168
10989 12:19:03.365263
10990 12:19:03.629946 Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64
10991 12:19:03.630112
10992 12:19:03.636907 The programs included with the Debian GNU/Linux system are free software;
10993 12:19:03.643308 the exact distribution terms for each program are described in the
10994 12:19:03.646525 individual files in /usr/share/doc/*/copyright.
10995 12:19:03.646604
10996 12:19:03.653396 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10997 12:19:03.656575 permitted by applicable law.
10998 12:19:03.706918 Matched prompt #10: / #
11000 12:19:03.707295 Setting prompt string to ['/ #']
11001 12:19:03.707444 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11003 12:19:03.707713 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11004 12:19:03.707828 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11005 12:19:03.707957 Setting prompt string to ['/ #']
11006 12:19:03.708060 Forcing a shell prompt, looking for ['/ #']
11008 12:19:03.758334 / #
11009 12:19:03.758507 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11010 12:19:03.758615 Waiting using forced prompt support (timeout 00:02:30)
11011 12:19:03.763368
11012 12:19:03.763659 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11013 12:19:03.763782 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11015 12:19:03.864131 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893118/extract-nfsrootfs-o9tlk6ze'
11016 12:19:03.868822 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893118/extract-nfsrootfs-o9tlk6ze'
11018 12:19:03.969409 / # export NFS_SERVER_IP='192.168.201.1'
11019 12:19:03.974430 export NFS_SERVER_IP='192.168.201.1'
11020 12:19:03.974738 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11021 12:19:03.974851 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11022 12:19:03.974972 end: 2 depthcharge-action (duration 00:01:23) [common]
11023 12:19:03.975087 start: 3 lava-test-retry (timeout 00:01:00) [common]
11024 12:19:03.975209 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11025 12:19:03.975302 Using namespace: common
11027 12:19:04.075637 / # #
11028 12:19:04.075835 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11029 12:19:04.080688 #
11030 12:19:04.080978 Using /lava-11893118
11032 12:19:04.181306 / # export SHELL=/bin/sh
11033 12:19:04.186198 export SHELL=/bin/sh
11035 12:19:04.286689 / # . /lava-11893118/environment
11036 12:19:04.292606 . /lava-11893118/environment
11038 12:19:04.397555 / # /lava-11893118/bin/lava-test-runner /lava-11893118/0
11039 12:19:04.397716 Test shell timeout: 10s (minimum of the action and connection timeout)
11040 12:19:04.402375 /lava-11893118/bin/lava-test-runner /lava-11893118/0
11041 12:19:04.584649 + export TESTRUN_ID=0_dmesg
11042 12:19:04.587942 + cd /lava-11893118/0/tests/0_dmesg
11043 12:19:04.591158 + cat uuid
11044 12:19:04.597815 + UUID=11893118_1.<8>[ 25.920123] <LAVA_SIGNAL_STARTRUN 0_dmesg 11893118_1.6.2.3.1>
11045 12:19:04.598077 Received signal: <STARTRUN> 0_dmesg 11893118_1.6.2.3.1
11046 12:19:04.598164 Starting test lava.0_dmesg (11893118_1.6.2.3.1)
11047 12:19:04.598273 Skipping test definition patterns.
11048 12:19:04.601177 6.2.3.1
11049 12:19:04.601287 + set +x
11050 12:19:04.604562 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11051 12:19:04.673913 <8>[ 25.994507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11052 12:19:04.674216 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11054 12:19:04.723469 <8>[ 26.044144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11055 12:19:04.723751 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11057 12:19:04.778465 <8>[ 26.099206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11058 12:19:04.778753 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11060 12:19:04.781949 + set +x
11061 12:19:04.785358 <8>[ 26.108895] <LAVA_SIGNAL_ENDRUN 0_dmesg 11893118_1.6.2.3.1>
11062 12:19:04.785610 Received signal: <ENDRUN> 0_dmesg 11893118_1.6.2.3.1
11063 12:19:04.785705 Ending use of test pattern.
11064 12:19:04.785779 Ending test lava.0_dmesg (11893118_1.6.2.3.1), duration 0.19
11066 12:19:04.790499 <LAVA_TEST_RUNNER EXIT>
11067 12:19:04.790754 ok: lava_test_shell seems to have completed
11068 12:19:04.790876 alert: pass
crit: pass
emerg: pass
11069 12:19:04.790984 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11070 12:19:04.791088 end: 3 lava-test-retry (duration 00:00:01) [common]
11071 12:19:04.791189 start: 4 lava-test-retry (timeout 00:01:00) [common]
11072 12:19:04.791290 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11073 12:19:04.791368 Using namespace: common
11075 12:19:04.891701 / # #
11076 12:19:04.891856 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11077 12:19:04.891999 Using /lava-11893118
11079 12:19:04.992305 export SHELL=/bin/sh
11080 12:19:04.992518 #
11082 12:19:05.093007 / # export SHELL=/bin/sh. /lava-11893118/environment
11083 12:19:05.093214
11085 12:19:05.193722 / # . /lava-11893118/environment/lava-11893118/bin/lava-test-runner /lava-11893118/1
11086 12:19:05.193878 Test shell timeout: 10s (minimum of the action and connection timeout)
11087 12:19:05.194038
11088 12:19:05.199193 / # /lava-11893118/bin/lava-test-runner /lava-11893118/1
11089 12:19:05.281256 + export TESTRUN_ID=1_bootrr
11090 12:19:05.284330 + cd /lava-11893118/1/tests/1_bootrr
11091 12:19:05.287601 + cat uuid
11092 12:19:05.294446 + UUID=11893118_<8>[ 26.615807] <LAVA_SIGNAL_STARTRUN 1_bootrr 11893118_1.6.2.3.5>
11093 12:19:05.294601 1.6.2.3.5
11094 12:19:05.294871 Received signal: <STARTRUN> 1_bootrr 11893118_1.6.2.3.5
11095 12:19:05.294958 Starting test lava.1_bootrr (11893118_1.6.2.3.5)
11096 12:19:05.295043 Skipping test definition patterns.
11097 12:19:05.297538 + set +x
11098 12:19:05.307576 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-11893118/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11099 12:19:05.310777 + cd /opt/bootrr/libexec/bootrr
11100 12:19:05.313924 + sh helpers/bootrr-auto
11101 12:19:05.354922 /lava-11893118/1/../bin/lava-test-case
11102 12:19:05.375002 <8>[ 26.695821] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11103 12:19:05.375282 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11105 12:19:05.407660 /lava-11893118/1/../bin/lava-test-case
11106 12:19:05.429121 <8>[ 26.749599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11107 12:19:05.429394 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11109 12:19:05.448252 /lava-11893118/1/../bin/lava-test-case
11110 12:19:05.464633 <8>[ 26.785363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11111 12:19:05.464895 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11113 12:19:05.512885 /lava-11893118/1/../bin/lava-test-case
11114 12:19:05.532615 <8>[ 26.853136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11115 12:19:05.532890 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11117 12:19:05.558171 /lava-11893118/1/../bin/lava-test-case
11118 12:19:05.580229 <8>[ 26.901061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11119 12:19:05.580526 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11121 12:19:05.610677 /lava-11893118/1/../bin/lava-test-case
11122 12:19:05.630637 <8>[ 26.951173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11123 12:19:05.630909 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11125 12:19:05.659057 /lava-11893118/1/../bin/lava-test-case
11126 12:19:05.679296 <8>[ 27.000042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11127 12:19:05.679567 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11129 12:19:05.704132 /lava-11893118/1/../bin/lava-test-case
11130 12:19:05.722792 <8>[ 27.043696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11131 12:19:05.723055 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11133 12:19:05.740621 /lava-11893118/1/../bin/lava-test-case
11134 12:19:05.759819 <8>[ 27.080804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11135 12:19:05.760085 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11137 12:19:05.785108 /lava-11893118/1/../bin/lava-test-case
11138 12:19:05.802907 <8>[ 27.123667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11139 12:19:05.803168 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11141 12:19:05.818340 /lava-11893118/1/../bin/lava-test-case
11142 12:19:05.840152 <8>[ 27.160895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11143 12:19:05.840449 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11145 12:19:05.865977 /lava-11893118/1/../bin/lava-test-case
11146 12:19:05.885542 <8>[ 27.206309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11147 12:19:05.885807 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11149 12:19:05.920186 /lava-11893118/1/../bin/lava-test-case
11150 12:19:05.937980 <8>[ 27.258687] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11151 12:19:05.938355 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11153 12:19:05.965213 /lava-11893118/1/../bin/lava-test-case
11154 12:19:05.985913 <8>[ 27.306760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11155 12:19:05.986203 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11157 12:19:06.011468 /lava-11893118/1/../bin/lava-test-case
11158 12:19:06.029656 <8>[ 27.350668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11159 12:19:06.029947 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11161 12:19:06.047723 /lava-11893118/1/../bin/lava-test-case
11162 12:19:06.068345 <8>[ 27.388995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11163 12:19:06.068637 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11165 12:19:06.095488 /lava-11893118/1/../bin/lava-test-case
11166 12:19:06.114965 <8>[ 27.435958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11167 12:19:06.115256 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11169 12:19:06.133469 /lava-11893118/1/../bin/lava-test-case
11170 12:19:06.153612 <8>[ 27.474475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11171 12:19:06.153881 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11173 12:19:06.181199 /lava-11893118/1/../bin/lava-test-case
11174 12:19:06.198430 <8>[ 27.519105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11175 12:19:06.198692 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11177 12:19:06.222205 /lava-11893118/1/../bin/lava-test-case
11178 12:19:06.241603 <8>[ 27.562360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11179 12:19:06.241878 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11181 12:19:06.267491 /lava-11893118/1/../bin/lava-test-case
11182 12:19:06.289285 <8>[ 27.610226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11183 12:19:06.289596 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11185 12:19:06.307457 /lava-11893118/1/../bin/lava-test-case
11186 12:19:06.328486 <8>[ 27.649542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11187 12:19:06.328775 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11189 12:19:06.353617 /lava-11893118/1/../bin/lava-test-case
11190 12:19:06.374912 <8>[ 27.695649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11191 12:19:06.375183 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11193 12:19:06.394984 /lava-11893118/1/../bin/lava-test-case
11194 12:19:06.415019 <8>[ 27.735947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11195 12:19:06.415315 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11197 12:19:06.441799 /lava-11893118/1/../bin/lava-test-case
11198 12:19:06.463284 <8>[ 27.784138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11199 12:19:06.463578 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11201 12:19:06.488994 /lava-11893118/1/../bin/lava-test-case
11202 12:19:06.510095 <8>[ 27.831087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11203 12:19:06.510370 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11205 12:19:06.535039 /lava-11893118/1/../bin/lava-test-case
11206 12:19:06.553821 <8>[ 27.874872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11207 12:19:06.554098 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11209 12:19:06.580959 /lava-11893118/1/../bin/lava-test-case
11210 12:19:06.602050 <8>[ 27.922984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11211 12:19:06.602325 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11213 12:19:06.620113 /lava-11893118/1/../bin/lava-test-case
11214 12:19:06.640790 <8>[ 27.961869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11215 12:19:06.641082 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11217 12:19:06.667873 /lava-11893118/1/../bin/lava-test-case
11218 12:19:06.692920 <8>[ 28.013876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11219 12:19:06.693198 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11221 12:19:06.722233 /lava-11893118/1/../bin/lava-test-case
11222 12:19:06.743059 <8>[ 28.063892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11223 12:19:06.743347 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11225 12:19:06.768503 /lava-11893118/1/../bin/lava-test-case
11226 12:19:06.790279 <8>[ 28.111113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11227 12:19:06.790556 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11229 12:19:06.816530 /lava-11893118/1/../bin/lava-test-case
11230 12:19:06.837208 <8>[ 28.158132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11231 12:19:06.837481 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11233 12:19:06.861768 /lava-11893118/1/../bin/lava-test-case
11234 12:19:06.880301 <8>[ 28.201283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11235 12:19:06.880568 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11237 12:19:06.903383 /lava-11893118/1/../bin/lava-test-case
11238 12:19:06.924897 <8>[ 28.245826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11239 12:19:06.925218 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11241 12:19:06.949245 /lava-11893118/1/../bin/lava-test-case
11242 12:19:06.970338 <8>[ 28.291364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11243 12:19:06.970604 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11245 12:19:06.987234 /lava-11893118/1/../bin/lava-test-case
11246 12:19:07.005690 <8>[ 28.326593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11247 12:19:07.005957 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11249 12:19:07.030802 /lava-11893118/1/../bin/lava-test-case
11250 12:19:07.055848 <8>[ 28.376927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11251 12:19:07.056122 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11253 12:19:07.073912 /lava-11893118/1/../bin/lava-test-case
11254 12:19:07.092740 <8>[ 28.413763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11255 12:19:07.093018 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11257 12:19:07.117817 /lava-11893118/1/../bin/lava-test-case
11258 12:19:07.134904 <8>[ 28.456121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11259 12:19:07.135182 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11261 12:19:07.152009 /lava-11893118/1/../bin/lava-test-case
11262 12:19:07.171422 <8>[ 28.492507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11263 12:19:07.171717 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11265 12:19:07.212592 /lava-11893118/1/../bin/lava-test-case
11266 12:19:07.233872 <8>[ 28.554859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11267 12:19:07.234152 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11269 12:19:07.251394 /lava-11893118/1/../bin/lava-test-case
11270 12:19:07.269170 <8>[ 28.589898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11271 12:19:07.269430 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11273 12:19:07.295741 /lava-11893118/1/../bin/lava-test-case
11274 12:19:07.316678 <8>[ 28.637705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11275 12:19:07.317019 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11277 12:19:07.335220 /lava-11893118/1/../bin/lava-test-case
11278 12:19:07.356507 <8>[ 28.677637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11279 12:19:07.356805 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11281 12:19:07.383749 /lava-11893118/1/../bin/lava-test-case
11282 12:19:07.403038 <8>[ 28.723802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11283 12:19:07.403335 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11285 12:19:07.418408 /lava-11893118/1/../bin/lava-test-case
11286 12:19:07.436368 <8>[ 28.757088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11287 12:19:07.436688 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11289 12:19:07.462604 /lava-11893118/1/../bin/lava-test-case
11290 12:19:07.481524 <8>[ 28.802456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11291 12:19:07.481815 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11293 12:19:07.498065 /lava-11893118/1/../bin/lava-test-case
11294 12:19:07.524891 <8>[ 28.846019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11295 12:19:07.525241 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11297 12:19:07.551378 /lava-11893118/1/../bin/lava-test-case
11298 12:19:07.569448 <8>[ 28.890642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11299 12:19:07.569713 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11301 12:19:07.593142 /lava-11893118/1/../bin/lava-test-case
11302 12:19:07.611690 <8>[ 28.932789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11303 12:19:07.611980 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11305 12:19:07.629231 /lava-11893118/1/../bin/lava-test-case
11306 12:19:07.647057 <8>[ 28.968266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11307 12:19:07.647329 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11309 12:19:07.674026 /lava-11893118/1/../bin/lava-test-case
11310 12:19:07.692642 <8>[ 29.013208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11311 12:19:07.692952 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11313 12:19:07.707657 /lava-11893118/1/../bin/lava-test-case
11314 12:19:07.727548 <8>[ 29.048419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11315 12:19:07.727840 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11317 12:19:07.765533 /lava-11893118/1/../bin/lava-test-case
11318 12:19:07.791676 <8>[ 29.112796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11319 12:19:07.791942 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11321 12:19:07.825203 /lava-11893118/1/../bin/lava-test-case
11322 12:19:07.843584 <8>[ 29.164545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11323 12:19:07.843897 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11325 12:19:07.867638 /lava-11893118/1/../bin/lava-test-case
11326 12:19:07.888697 <8>[ 29.209517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11327 12:19:07.888952 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11329 12:19:07.912614 /lava-11893118/1/../bin/lava-test-case
11330 12:19:07.933125 <8>[ 29.254282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11331 12:19:07.933419 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11333 12:19:07.957955 /lava-11893118/1/../bin/lava-test-case
11334 12:19:07.977979 <8>[ 29.299192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11335 12:19:07.978282 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11337 12:19:07.996809 /lava-11893118/1/../bin/lava-test-case
11338 12:19:08.014127 <8>[ 29.335243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11339 12:19:08.014416 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11341 12:19:08.038362 /lava-11893118/1/../bin/lava-test-case
11342 12:19:08.054451 <8>[ 29.375743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11343 12:19:08.054747 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11345 12:19:08.079798 /lava-11893118/1/../bin/lava-test-case
11346 12:19:08.102929 <8>[ 29.423915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11347 12:19:08.103213 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11349 12:19:08.127050 /lava-11893118/1/../bin/lava-test-case
11350 12:19:08.146146 <8>[ 29.467016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11351 12:19:08.146451 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11353 12:19:08.171483 /lava-11893118/1/../bin/lava-test-case
11354 12:19:08.190509 <8>[ 29.511365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11355 12:19:08.190808 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11357 12:19:08.207281 /lava-11893118/1/../bin/lava-test-case
11358 12:19:08.225838 <8>[ 29.546939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11359 12:19:08.226128 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11361 12:19:08.252942 /lava-11893118/1/../bin/lava-test-case
11362 12:19:08.274952 <8>[ 29.596190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11363 12:19:08.275243 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11365 12:19:08.293771 /lava-11893118/1/../bin/lava-test-case
11366 12:19:08.313111 <8>[ 29.634303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11367 12:19:08.313371 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11369 12:19:08.339809 /lava-11893118/1/../bin/lava-test-case
11370 12:19:08.361171 <8>[ 29.682096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11371 12:19:08.361446 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11373 12:19:08.385382 /lava-11893118/1/../bin/lava-test-case
11374 12:19:08.405117 <8>[ 29.726041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11375 12:19:08.405381 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11377 12:19:08.439204 /lava-11893118/1/../bin/lava-test-case
11378 12:19:08.459054 <8>[ 29.779906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11379 12:19:08.459329 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11381 12:19:08.487574 /lava-11893118/1/../bin/lava-test-case
11382 12:19:08.509976 <8>[ 29.831176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11383 12:19:08.510256 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11385 12:19:08.536823 /lava-11893118/1/../bin/lava-test-case
11386 12:19:08.555188 <8>[ 29.876354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11387 12:19:08.555476 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11389 12:19:08.580807 /lava-11893118/1/../bin/lava-test-case
11390 12:19:08.599916 <8>[ 29.921018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11391 12:19:08.600222 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11393 12:19:08.622651 /lava-11893118/1/../bin/lava-test-case
11394 12:19:08.640267 <8>[ 29.961164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11395 12:19:08.640551 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11397 12:19:08.665899 /lava-11893118/1/../bin/lava-test-case
11398 12:19:08.687014 <8>[ 30.008361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11399 12:19:08.687308 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11401 12:19:08.712798 /lava-11893118/1/../bin/lava-test-case
11402 12:19:08.732466 <8>[ 30.053550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11403 12:19:08.732756 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11405 12:19:08.765047 /lava-11893118/1/../bin/lava-test-case
11406 12:19:08.785943 <8>[ 30.106659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11407 12:19:08.786209 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11409 12:19:08.810118 /lava-11893118/1/../bin/lava-test-case
11410 12:19:08.831635 <8>[ 30.152939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11411 12:19:08.831903 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11413 12:19:08.861427 /lava-11893118/1/../bin/lava-test-case
11414 12:19:08.880347 <8>[ 30.201276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11415 12:19:08.880640 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11417 12:19:08.911369 /lava-11893118/1/../bin/lava-test-case
11418 12:19:08.934013 <8>[ 30.255151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11419 12:19:08.934295 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11421 12:19:08.960289 /lava-11893118/1/../bin/lava-test-case
11422 12:19:08.977853 <8>[ 30.299137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11423 12:19:08.978119 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11425 12:19:09.002814 /lava-11893118/1/../bin/lava-test-case
11426 12:19:09.023046 <8>[ 30.344204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11427 12:19:09.023307 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11429 12:19:09.041728 /lava-11893118/1/../bin/lava-test-case
11430 12:19:09.059551 <8>[ 30.380628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11431 12:19:09.059865 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11433 12:19:09.092293 /lava-11893118/1/../bin/lava-test-case
11434 12:19:09.111757 <8>[ 30.433170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11435 12:19:09.112043 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11437 12:19:09.129183 /lava-11893118/1/../bin/lava-test-case
11438 12:19:09.150522 <8>[ 30.471786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11439 12:19:09.150838 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11441 12:19:09.174927 /lava-11893118/1/../bin/lava-test-case
11442 12:19:09.196130 <8>[ 30.517397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11443 12:19:09.196392 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11445 12:19:09.213586 /lava-11893118/1/../bin/lava-test-case
11446 12:19:09.231351 <8>[ 30.552713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11447 12:19:09.231633 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11449 12:19:09.259335 /lava-11893118/1/../bin/lava-test-case
11450 12:19:09.279883 <8>[ 30.601278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11451 12:19:09.280174 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11453 12:19:09.301176 /lava-11893118/1/../bin/lava-test-case
11454 12:19:09.321830 <8>[ 30.643196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11455 12:19:09.322092 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11457 12:19:09.352645 /lava-11893118/1/../bin/lava-test-case
11458 12:19:09.373884 <8>[ 30.694920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11459 12:19:09.374180 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11461 12:19:09.398466 /lava-11893118/1/../bin/lava-test-case
11462 12:19:09.418833 <8>[ 30.740065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11463 12:19:09.419131 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11465 12:19:09.443240 /lava-11893118/1/../bin/lava-test-case
11466 12:19:09.460302 <8>[ 30.781611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11467 12:19:09.460572 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11469 12:19:09.476053 /lava-11893118/1/../bin/lava-test-case
11470 12:19:09.494018 <8>[ 30.814912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11471 12:19:09.494281 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11473 12:19:09.518350 /lava-11893118/1/../bin/lava-test-case
11474 12:19:09.536462 <8>[ 30.857904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11475 12:19:09.536740 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11477 12:19:09.560895 /lava-11893118/1/../bin/lava-test-case
11478 12:19:09.579387 <8>[ 30.900635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11479 12:19:09.579683 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11481 12:19:09.597134 /lava-11893118/1/../bin/lava-test-case
11482 12:19:09.616572 <8>[ 30.937724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11483 12:19:09.616851 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11485 12:19:09.644674 /lava-11893118/1/../bin/lava-test-case
11486 12:19:09.667107 <8>[ 30.988385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11487 12:19:09.667443 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11489 12:19:09.683969 /lava-11893118/1/../bin/lava-test-case
11490 12:19:09.702886 <8>[ 31.024228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11491 12:19:09.703157 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11493 12:19:09.736667 /lava-11893118/1/../bin/lava-test-case
11494 12:19:09.756674 <8>[ 31.078041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11495 12:19:09.756990 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11497 12:19:09.776347 /lava-11893118/1/../bin/lava-test-case
11498 12:19:09.795865 <8>[ 31.117245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11499 12:19:09.796194 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11501 12:19:10.844555 /lava-11893118/1/../bin/lava-test-case
11502 12:19:10.866525 <8>[ 32.187813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11503 12:19:10.866812 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11505 12:19:10.882581 /lava-11893118/1/../bin/lava-test-case
11506 12:19:10.904749 <8>[ 32.226211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11507 12:19:10.905038 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11509 12:19:11.940253 /lava-11893118/1/../bin/lava-test-case
11510 12:19:11.963530 <8>[ 33.285111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11511 12:19:11.963811 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11513 12:19:11.979898 /lava-11893118/1/../bin/lava-test-case
11514 12:19:12.000622 <8>[ 33.322314] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11515 12:19:12.000884 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11517 12:19:13.041067 /lava-11893118/1/../bin/lava-test-case
11518 12:19:13.063099 <8>[ 34.384679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11519 12:19:13.063404 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11521 12:19:13.079131 /lava-11893118/1/../bin/lava-test-case
11522 12:19:13.101400 <8>[ 34.423067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11523 12:19:13.101771 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11525 12:19:14.138333 /lava-11893118/1/../bin/lava-test-case
11526 12:19:14.162200 <8>[ 35.483663] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11527 12:19:14.162495 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11529 12:19:14.177437 /lava-11893118/1/../bin/lava-test-case
11530 12:19:14.199546 <8>[ 35.521276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11531 12:19:14.199805 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11533 12:19:15.235186 /lava-11893118/1/../bin/lava-test-case
11534 12:19:15.257872 <8>[ 36.579718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11535 12:19:15.258159 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11537 12:19:15.272800 /lava-11893118/1/../bin/lava-test-case
11538 12:19:15.295034 <8>[ 36.616669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11539 12:19:15.295299 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11541 12:19:16.329787 /lava-11893118/1/../bin/lava-test-case
11542 12:19:16.352841 <8>[ 37.675111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11543 12:19:16.353137 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11545 12:19:16.368252 /lava-11893118/1/../bin/lava-test-case
11546 12:19:16.387002 <8>[ 37.709152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11547 12:19:16.387267 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11549 12:19:17.424878 /lava-11893118/1/../bin/lava-test-case
11550 12:19:17.448090 <8>[ 38.770147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11551 12:19:17.448392 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11553 12:19:17.463537 /lava-11893118/1/../bin/lava-test-case
11554 12:19:17.483680 <8>[ 38.805680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11555 12:19:17.484030 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11557 12:19:17.501228 /lava-11893118/1/../bin/lava-test-case
11558 12:19:17.519212 <8>[ 38.841708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11559 12:19:17.519585 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11561 12:19:18.553902 /lava-11893118/1/../bin/lava-test-case
11562 12:19:18.580368 <8>[ 39.902554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11563 12:19:18.580712 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11565 12:19:18.598636 /lava-11893118/1/../bin/lava-test-case
11566 12:19:18.619176 <8>[ 39.941401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11567 12:19:18.619448 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11569 12:19:18.646428 /lava-11893118/1/../bin/lava-test-case
11570 12:19:18.667730 <8>[ 39.990002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11571 12:19:18.668004 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11573 12:19:18.684989 /lava-11893118/1/../bin/lava-test-case
11574 12:19:18.704820 <8>[ 40.027001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11575 12:19:18.705076 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11577 12:19:18.731638 /lava-11893118/1/../bin/lava-test-case
11578 12:19:18.753137 <8>[ 40.075446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11579 12:19:18.753430 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11581 12:19:18.778589 /lava-11893118/1/../bin/lava-test-case
11582 12:19:18.799006 <8>[ 40.121348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11583 12:19:18.799265 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11585 12:19:18.825817 /lava-11893118/1/../bin/lava-test-case
11586 12:19:18.846058 <8>[ 40.168183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11587 12:19:18.846320 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11589 12:19:18.872195 /lava-11893118/1/../bin/lava-test-case
11590 12:19:18.890668 <8>[ 40.213112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11591 12:19:18.890924 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11593 12:19:18.915381 /lava-11893118/1/../bin/lava-test-case
11594 12:19:18.935857 <8>[ 40.258074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11595 12:19:18.936116 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11597 12:19:18.959845 /lava-11893118/1/../bin/lava-test-case
11598 12:19:18.980637 <8>[ 40.303236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11599 12:19:18.980969 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11601 12:19:18.999390 /lava-11893118/1/../bin/lava-test-case
11602 12:19:19.020532 <8>[ 40.342773] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11603 12:19:19.020789 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11605 12:19:19.046577 /lava-11893118/1/../bin/lava-test-case
11606 12:19:19.067819 <8>[ 40.389993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11607 12:19:19.068092 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11609 12:19:19.086419 /lava-11893118/1/../bin/lava-test-case
11610 12:19:19.105619 <8>[ 40.427831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11611 12:19:19.105887 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11613 12:19:19.131746 /lava-11893118/1/../bin/lava-test-case
11614 12:19:19.151459 <8>[ 40.473593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11615 12:19:19.151733 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11617 12:19:19.179971 /lava-11893118/1/../bin/lava-test-case
11618 12:19:19.198411 <8>[ 40.520835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11619 12:19:19.198678 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11621 12:19:19.225089 /lava-11893118/1/../bin/lava-test-case
11622 12:19:19.246311 <8>[ 40.568870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11623 12:19:19.246577 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11625 12:19:19.264604 /lava-11893118/1/../bin/lava-test-case
11626 12:19:19.283535 <8>[ 40.605722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11627 12:19:19.283794 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11629 12:19:19.309210 /lava-11893118/1/../bin/lava-test-case
11630 12:19:19.328828 <8>[ 40.651469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11631 12:19:19.329114 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11633 12:19:19.345920 /lava-11893118/1/../bin/lava-test-case
11634 12:19:19.367392 <8>[ 40.689595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11635 12:19:19.367659 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11637 12:19:19.394775 /lava-11893118/1/../bin/lava-test-case
11638 12:19:19.416327 <8>[ 40.738230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11639 12:19:19.416607 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11641 12:19:19.433294 /lava-11893118/1/../bin/lava-test-case
11642 12:19:19.452915 <8>[ 40.775201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11643 12:19:19.453199 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11645 12:19:20.497990 /lava-11893118/1/../bin/lava-test-case
11646 12:19:20.520857 <8>[ 41.843080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11647 12:19:20.521186 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11649 12:19:21.557243 /lava-11893118/1/../bin/lava-test-case
11650 12:19:21.579314 <8>[ 42.901937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11651 12:19:21.579596 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11653 12:19:21.597234 /lava-11893118/1/../bin/lava-test-case
11654 12:19:21.620463 <8>[ 42.943179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11655 12:19:21.620763 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11657 12:19:21.647985 /lava-11893118/1/../bin/lava-test-case
11658 12:19:21.665353 <8>[ 42.987966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11659 12:19:21.665617 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11661 12:19:21.682497 /lava-11893118/1/../bin/lava-test-case
11662 12:19:21.703969 <8>[ 43.026546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11663 12:19:21.704222 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11665 12:19:21.730842 /lava-11893118/1/../bin/lava-test-case
11666 12:19:21.751124 <8>[ 43.073524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11667 12:19:21.751390 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11669 12:19:21.769204 /lava-11893118/1/../bin/lava-test-case
11670 12:19:21.787698 <8>[ 43.110689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11671 12:19:21.788075 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11673 12:19:21.815018 /lava-11893118/1/../bin/lava-test-case
11674 12:19:21.835436 <8>[ 43.158313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11675 12:19:21.835703 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11677 12:19:21.859589 /lava-11893118/1/../bin/lava-test-case
11678 12:19:21.879388 <8>[ 43.201982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11679 12:19:21.879660 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11681 12:19:21.905581 /lava-11893118/1/../bin/lava-test-case
11682 12:19:21.926087 <8>[ 43.248927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11683 12:19:21.926347 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11685 12:19:21.944069 /lava-11893118/1/../bin/lava-test-case
11686 12:19:21.965868 <8>[ 43.288482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11687 12:19:21.966130 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11689 12:19:21.992089 /lava-11893118/1/../bin/lava-test-case
11690 12:19:22.013581 <8>[ 43.336200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11691 12:19:22.013850 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11693 12:19:22.030895 /lava-11893118/1/../bin/lava-test-case
11694 12:19:22.049289 <8>[ 43.371957] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11695 12:19:22.049550 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11697 12:19:22.075791 /lava-11893118/1/../bin/lava-test-case
11698 12:19:22.096153 <8>[ 43.418621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11699 12:19:22.096437 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11701 12:19:22.114003 /lava-11893118/1/../bin/lava-test-case
11702 12:19:22.133860 <8>[ 43.456739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11703 12:19:22.134117 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11705 12:19:22.167364 /lava-11893118/1/../bin/lava-test-case
11706 12:19:22.187167 <8>[ 43.509941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11707 12:19:22.187423 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11709 12:19:22.202620 /lava-11893118/1/../bin/lava-test-case
11710 12:19:22.224538 <8>[ 43.547152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11711 12:19:22.224825 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11713 12:19:22.254480 /lava-11893118/1/../bin/lava-test-case
11714 12:19:22.275002 <8>[ 43.597868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11715 12:19:22.275290 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11717 12:19:22.291568 /lava-11893118/1/../bin/lava-test-case
11718 12:19:22.313296 <8>[ 43.636181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11719 12:19:22.313552 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11721 12:19:22.339379 /lava-11893118/1/../bin/lava-test-case
11722 12:19:22.358687 <8>[ 43.681590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11723 12:19:22.358978 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11725 12:19:22.375487 /lava-11893118/1/../bin/lava-test-case
11726 12:19:22.393320 <8>[ 43.716284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11727 12:19:22.393592 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11729 12:19:22.419965 /lava-11893118/1/../bin/lava-test-case
11730 12:19:22.438555 <8>[ 43.761319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11731 12:19:22.438842 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11733 12:19:23.477711 /lava-11893118/1/../bin/lava-test-case
11734 12:19:23.501075 <8>[ 44.824232] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11735 12:19:23.501343 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11737 12:19:24.527963 /lava-11893118/1/../bin/lava-test-case
11738 12:19:24.555418 <8>[ 45.878187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11739 12:19:24.555733 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11740 12:19:24.555853 Bad test result: blocked
11741 12:19:24.573458 /lava-11893118/1/../bin/lava-test-case
11742 12:19:24.594264 <8>[ 45.917200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11743 12:19:24.594549 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11745 12:19:24.956758 <6>[ 46.286329] vpu: disabling
11746 12:19:24.959983 <6>[ 46.289440] vproc2: disabling
11747 12:19:24.963273 <6>[ 46.292765] vproc1: disabling
11748 12:19:24.966808 <6>[ 46.296492] vaud18: disabling
11749 12:19:24.974328 <6>[ 46.300732] vsram_others: disabling
11750 12:19:24.977435 <6>[ 46.305388] va09: disabling
11751 12:19:24.981128 <6>[ 46.308932] vsram_md: disabling
11752 12:19:24.984032 <6>[ 46.312601] Vgpu: disabling
11753 12:19:25.630242 /lava-11893118/1/../bin/lava-test-case
11754 12:19:25.654148 <8>[ 46.977237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11755 12:19:25.654454 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11757 12:19:25.672436 /lava-11893118/1/../bin/lava-test-case
11758 12:19:25.692230 <8>[ 47.015282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11759 12:19:25.692521 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11761 12:19:25.718055 /lava-11893118/1/../bin/lava-test-case
11762 12:19:25.738130 <8>[ 47.061337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11763 12:19:25.738387 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11765 12:19:25.763924 /lava-11893118/1/../bin/lava-test-case
11766 12:19:25.785894 <8>[ 47.109244] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11767 12:19:25.786253 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11769 12:19:25.802356 /lava-11893118/1/../bin/lava-test-case
11770 12:19:25.822297 <8>[ 47.145394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11771 12:19:25.822576 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11773 12:19:25.846276 /lava-11893118/1/../bin/lava-test-case
11774 12:19:25.866345 <8>[ 47.189362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11775 12:19:25.866631 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11777 12:19:25.883328 /lava-11893118/1/../bin/lava-test-case
11778 12:19:25.904147 <8>[ 47.227073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11779 12:19:25.904433 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11781 12:19:26.943701 /lava-11893118/1/../bin/lava-test-case
11782 12:19:26.966110 <8>[ 48.289305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11783 12:19:26.966454 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11785 12:19:26.983592 /lava-11893118/1/../bin/lava-test-case
11786 12:19:27.005231 <8>[ 48.328425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11787 12:19:27.005495 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11789 12:19:28.040865 /lava-11893118/1/../bin/lava-test-case
11790 12:19:28.064367 <8>[ 49.387786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11791 12:19:28.064667 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11793 12:19:28.080663 /lava-11893118/1/../bin/lava-test-case
11794 12:19:28.098995 <8>[ 49.422442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11795 12:19:28.099280 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11797 12:19:29.134084 /lava-11893118/1/../bin/lava-test-case
11798 12:19:29.159885 <8>[ 50.483652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11799 12:19:29.160214 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11801 12:19:29.180391 /lava-11893118/1/../bin/lava-test-case
11802 12:19:29.204369 <8>[ 50.527918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11803 12:19:29.204630 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11805 12:19:30.244379 /lava-11893118/1/../bin/lava-test-case
11806 12:19:30.266087 <8>[ 51.589508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11807 12:19:30.266374 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11809 12:19:30.283961 /lava-11893118/1/../bin/lava-test-case
11810 12:19:30.304237 <8>[ 51.627920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11811 12:19:30.304521 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11813 12:19:30.329827 /lava-11893118/1/../bin/lava-test-case
11814 12:19:30.349327 <8>[ 51.673188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11815 12:19:30.349584 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11817 12:19:30.373379 /lava-11893118/1/../bin/lava-test-case
11818 12:19:30.389843 <8>[ 51.713627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11819 12:19:30.390155 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11821 12:19:30.406736 /lava-11893118/1/../bin/lava-test-case
11822 12:19:30.425449 <8>[ 51.748912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11823 12:19:30.425706 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11825 12:19:30.453276 /lava-11893118/1/../bin/lava-test-case
11826 12:19:30.473914 <8>[ 51.797233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11827 12:19:30.474317 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11829 12:19:30.489996 /lava-11893118/1/../bin/lava-test-case
11830 12:19:30.509231 <8>[ 51.832949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11831 12:19:30.509494 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11833 12:19:30.534828 /lava-11893118/1/../bin/lava-test-case
11834 12:19:30.553318 <8>[ 51.876827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11835 12:19:30.553578 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11837 12:19:30.579859 /lava-11893118/1/../bin/lava-test-case
11838 12:19:30.599283 <8>[ 51.922952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11839 12:19:30.599548 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11841 12:19:30.624851 /lava-11893118/1/../bin/lava-test-case
11842 12:19:30.642470 <8>[ 51.966009] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11843 12:19:30.642763 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11845 12:19:30.647780 + set +x
11846 12:19:30.651305 Received signal: <ENDRUN> 1_bootrr 11893118_1.6.2.3.5
11847 12:19:30.651393 Ending use of test pattern.
11848 12:19:30.651470 Ending test lava.1_bootrr (11893118_1.6.2.3.5), duration 25.36
11850 12:19:30.654798 <8>[ 51.978072] <LAVA_SIGNAL_ENDRUN 1_bootrr 11893118_1.6.2.3.5>
11851 12:19:30.658628 <LAVA_TEST_RUNNER EXIT>
11852 12:19:30.658909 ok: lava_test_shell seems to have completed
11853 12:19:30.661053 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11854 12:19:30.661210 end: 4.1 lava-test-shell (duration 00:00:26) [common]
11855 12:19:30.661302 end: 4 lava-test-retry (duration 00:00:26) [common]
11856 12:19:30.661403 start: 5 finalize (timeout 00:07:40) [common]
11857 12:19:30.661494 start: 5.1 power-off (timeout 00:00:30) [common]
11858 12:19:30.661664 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11859 12:19:30.736793 >> Command sent successfully.
11860 12:19:30.739029 Returned 0 in 0 seconds
11861 12:19:30.839434 end: 5.1 power-off (duration 00:00:00) [common]
11863 12:19:30.839780 start: 5.2 read-feedback (timeout 00:07:40) [common]
11864 12:19:30.840048 Listened to connection for namespace 'common' for up to 1s
11865 12:19:31.841022 Finalising connection for namespace 'common'
11866 12:19:31.841248 Disconnecting from shell: Finalise
11867 12:19:31.841365 / #
11868 12:19:31.941701 end: 5.2 read-feedback (duration 00:00:01) [common]
11869 12:19:31.941881 end: 5 finalize (duration 00:00:01) [common]
11870 12:19:31.941995 Cleaning after the job
11871 12:19:31.942109 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/ramdisk
11872 12:19:31.944151 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/kernel
11873 12:19:31.953719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/dtb
11874 12:19:31.953957 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/nfsrootfs
11875 12:19:32.009784 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893118/tftp-deploy-wopfvvj9/modules
11876 12:19:32.015289 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893118
11877 12:19:32.337674 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893118
11878 12:19:32.337851 Job finished correctly