Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 26
- Kernel Errors: 29
- Errors: 1
- Boot result: PASS
1 12:19:14.504450 lava-dispatcher, installed at version: 2023.08
2 12:19:14.504669 start: 0 validate
3 12:19:14.504803 Start time: 2023-10-27 12:19:14.504796+00:00 (UTC)
4 12:19:14.504930 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:19:14.505068 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:19:14.774923 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:19:14.775126 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:19:15.041556 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:19:15.041743 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:19:15.310257 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:19:15.310432 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:19:15.841787 validate duration: 1.34
14 12:19:15.842105 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:19:15.842205 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:19:15.842297 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:19:15.842426 Not decompressing ramdisk as can be used compressed.
18 12:19:15.842517 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 12:19:15.842583 saving as /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/ramdisk/rootfs.cpio.gz
20 12:19:15.842648 total size: 34390042 (32 MB)
21 12:19:15.848107 progress 0 % (0 MB)
22 12:19:15.857278 progress 5 % (1 MB)
23 12:19:15.866119 progress 10 % (3 MB)
24 12:19:15.875497 progress 15 % (4 MB)
25 12:19:15.884403 progress 20 % (6 MB)
26 12:19:15.893474 progress 25 % (8 MB)
27 12:19:15.902604 progress 30 % (9 MB)
28 12:19:15.911922 progress 35 % (11 MB)
29 12:19:15.921625 progress 40 % (13 MB)
30 12:19:15.930861 progress 45 % (14 MB)
31 12:19:15.939897 progress 50 % (16 MB)
32 12:19:15.949190 progress 55 % (18 MB)
33 12:19:15.958247 progress 60 % (19 MB)
34 12:19:15.967796 progress 65 % (21 MB)
35 12:19:15.976879 progress 70 % (22 MB)
36 12:19:15.985973 progress 75 % (24 MB)
37 12:19:15.994979 progress 80 % (26 MB)
38 12:19:16.004087 progress 85 % (27 MB)
39 12:19:16.013294 progress 90 % (29 MB)
40 12:19:16.022248 progress 95 % (31 MB)
41 12:19:16.031185 progress 100 % (32 MB)
42 12:19:16.031366 32 MB downloaded in 0.19 s (173.79 MB/s)
43 12:19:16.031529 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:19:16.031907 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:19:16.032107 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:19:16.032270 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:19:16.032481 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:19:16.032592 saving as /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/kernel/Image
50 12:19:16.032684 total size: 49236480 (46 MB)
51 12:19:16.032773 No compression specified
52 12:19:16.033869 progress 0 % (0 MB)
53 12:19:16.046969 progress 5 % (2 MB)
54 12:19:16.060122 progress 10 % (4 MB)
55 12:19:16.073039 progress 15 % (7 MB)
56 12:19:16.086259 progress 20 % (9 MB)
57 12:19:16.099562 progress 25 % (11 MB)
58 12:19:16.112631 progress 30 % (14 MB)
59 12:19:16.125556 progress 35 % (16 MB)
60 12:19:16.138798 progress 40 % (18 MB)
61 12:19:16.152170 progress 45 % (21 MB)
62 12:19:16.165040 progress 50 % (23 MB)
63 12:19:16.178322 progress 55 % (25 MB)
64 12:19:16.191210 progress 60 % (28 MB)
65 12:19:16.204367 progress 65 % (30 MB)
66 12:19:16.217657 progress 70 % (32 MB)
67 12:19:16.230564 progress 75 % (35 MB)
68 12:19:16.244023 progress 80 % (37 MB)
69 12:19:16.257026 progress 85 % (39 MB)
70 12:19:16.270366 progress 90 % (42 MB)
71 12:19:16.283319 progress 95 % (44 MB)
72 12:19:16.296309 progress 100 % (46 MB)
73 12:19:16.296512 46 MB downloaded in 0.26 s (177.98 MB/s)
74 12:19:16.296667 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:19:16.296902 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:19:16.296989 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:19:16.297079 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:19:16.297219 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:19:16.297288 saving as /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/dtb/mt8192-asurada-spherion-r0.dtb
81 12:19:16.297351 total size: 47278 (0 MB)
82 12:19:16.297412 No compression specified
83 12:19:16.298545 progress 69 % (0 MB)
84 12:19:16.298828 progress 100 % (0 MB)
85 12:19:16.298987 0 MB downloaded in 0.00 s (27.61 MB/s)
86 12:19:16.299151 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:19:16.299372 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:19:16.299457 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:19:16.299541 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:19:16.299655 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:19:16.299729 saving as /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/modules/modules.tar
93 12:19:16.299787 total size: 8625084 (8 MB)
94 12:19:16.299846 Using unxz to decompress xz
95 12:19:16.303762 progress 0 % (0 MB)
96 12:19:16.325329 progress 5 % (0 MB)
97 12:19:16.347841 progress 10 % (0 MB)
98 12:19:16.373857 progress 15 % (1 MB)
99 12:19:16.399350 progress 20 % (1 MB)
100 12:19:16.424850 progress 25 % (2 MB)
101 12:19:16.450935 progress 30 % (2 MB)
102 12:19:16.478614 progress 35 % (2 MB)
103 12:19:16.503948 progress 40 % (3 MB)
104 12:19:16.528191 progress 45 % (3 MB)
105 12:19:16.555700 progress 50 % (4 MB)
106 12:19:16.581366 progress 55 % (4 MB)
107 12:19:16.607182 progress 60 % (4 MB)
108 12:19:16.632044 progress 65 % (5 MB)
109 12:19:16.657446 progress 70 % (5 MB)
110 12:19:16.681914 progress 75 % (6 MB)
111 12:19:16.708605 progress 80 % (6 MB)
112 12:19:16.738837 progress 85 % (7 MB)
113 12:19:16.766758 progress 90 % (7 MB)
114 12:19:16.794271 progress 95 % (7 MB)
115 12:19:16.818458 progress 100 % (8 MB)
116 12:19:16.823390 8 MB downloaded in 0.52 s (15.71 MB/s)
117 12:19:16.823644 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:19:16.823921 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:19:16.824017 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:19:16.824114 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:19:16.824192 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:19:16.824278 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:19:16.824509 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep
125 12:19:16.824647 makedir: /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin
126 12:19:16.824755 makedir: /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/tests
127 12:19:16.824854 makedir: /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/results
128 12:19:16.824974 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-add-keys
129 12:19:16.825121 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-add-sources
130 12:19:16.825250 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-background-process-start
131 12:19:16.825380 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-background-process-stop
132 12:19:16.825506 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-common-functions
133 12:19:16.825632 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-echo-ipv4
134 12:19:16.825765 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-install-packages
135 12:19:16.825893 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-installed-packages
136 12:19:16.826017 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-os-build
137 12:19:16.826141 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-probe-channel
138 12:19:16.826264 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-probe-ip
139 12:19:16.826387 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-target-ip
140 12:19:16.826509 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-target-mac
141 12:19:16.826631 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-target-storage
142 12:19:16.826758 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-test-case
143 12:19:16.826885 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-test-event
144 12:19:16.827009 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-test-feedback
145 12:19:16.827145 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-test-raise
146 12:19:16.827273 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-test-reference
147 12:19:16.827397 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-test-runner
148 12:19:16.827521 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-test-set
149 12:19:16.827648 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-test-shell
150 12:19:16.827775 Updating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-install-packages (oe)
151 12:19:16.827926 Updating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/bin/lava-installed-packages (oe)
152 12:19:16.828048 Creating /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/environment
153 12:19:16.828146 LAVA metadata
154 12:19:16.828218 - LAVA_JOB_ID=11893130
155 12:19:16.828280 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:19:16.828378 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:19:16.828443 skipped lava-vland-overlay
158 12:19:16.828514 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:19:16.828594 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:19:16.828655 skipped lava-multinode-overlay
161 12:19:16.828727 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:19:16.828810 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:19:16.828883 Loading test definitions
164 12:19:16.828972 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:19:16.829046 Using /lava-11893130 at stage 0
166 12:19:16.829360 uuid=11893130_1.5.2.3.1 testdef=None
167 12:19:16.829447 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:19:16.829535 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:19:16.830055 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:19:16.830278 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:19:16.830901 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:19:16.831139 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:19:16.831737 runner path: /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/0/tests/0_cros-ec test_uuid 11893130_1.5.2.3.1
176 12:19:16.831891 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:19:16.832095 Creating lava-test-runner.conf files
179 12:19:16.832158 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893130/lava-overlay-udzjegep/lava-11893130/0 for stage 0
180 12:19:16.832247 - 0_cros-ec
181 12:19:16.832344 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:19:16.832426 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:19:16.839143 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:19:16.839250 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:19:16.839339 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:19:16.839422 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:19:16.839507 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:19:17.843489 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:19:17.843881 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:19:17.843993 extracting modules file /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893130/extract-overlay-ramdisk-qx5o22_x/ramdisk
191 12:19:18.079385 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:19:18.079557 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:19:18.079648 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893130/compress-overlay-_a2xwk0t/overlay-1.5.2.4.tar.gz to ramdisk
194 12:19:18.079717 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893130/compress-overlay-_a2xwk0t/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893130/extract-overlay-ramdisk-qx5o22_x/ramdisk
195 12:19:18.086157 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:19:18.086264 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:19:18.086350 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:19:18.086432 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:19:18.086505 Building ramdisk /var/lib/lava/dispatcher/tmp/11893130/extract-overlay-ramdisk-qx5o22_x/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893130/extract-overlay-ramdisk-qx5o22_x/ramdisk
200 12:19:18.864905 >> 271038 blocks
201 12:19:23.596664 rename /var/lib/lava/dispatcher/tmp/11893130/extract-overlay-ramdisk-qx5o22_x/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/ramdisk/ramdisk.cpio.gz
202 12:19:23.597099 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 12:19:23.597237 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 12:19:23.597342 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 12:19:23.597445 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/kernel/Image'
206 12:19:36.979509 Returned 0 in 13 seconds
207 12:19:37.080140 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/kernel/image.itb
208 12:19:37.805765 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:19:37.806146 output: Created: Fri Oct 27 13:19:37 2023
210 12:19:37.806223 output: Image 0 (kernel-1)
211 12:19:37.806287 output: Description:
212 12:19:37.806345 output: Created: Fri Oct 27 13:19:37 2023
213 12:19:37.806405 output: Type: Kernel Image
214 12:19:37.806462 output: Compression: lzma compressed
215 12:19:37.806518 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
216 12:19:37.806576 output: Architecture: AArch64
217 12:19:37.806633 output: OS: Linux
218 12:19:37.806690 output: Load Address: 0x00000000
219 12:19:37.806746 output: Entry Point: 0x00000000
220 12:19:37.806802 output: Hash algo: crc32
221 12:19:37.806857 output: Hash value: d33b93ae
222 12:19:37.806912 output: Image 1 (fdt-1)
223 12:19:37.806965 output: Description: mt8192-asurada-spherion-r0
224 12:19:37.807015 output: Created: Fri Oct 27 13:19:37 2023
225 12:19:37.807066 output: Type: Flat Device Tree
226 12:19:37.807164 output: Compression: uncompressed
227 12:19:37.807215 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:19:37.807266 output: Architecture: AArch64
229 12:19:37.807316 output: Hash algo: crc32
230 12:19:37.807366 output: Hash value: cc4352de
231 12:19:37.807417 output: Image 2 (ramdisk-1)
232 12:19:37.807467 output: Description: unavailable
233 12:19:37.807518 output: Created: Fri Oct 27 13:19:37 2023
234 12:19:37.807568 output: Type: RAMDisk Image
235 12:19:37.807618 output: Compression: Unknown Compression
236 12:19:37.807668 output: Data Size: 47524695 Bytes = 46410.83 KiB = 45.32 MiB
237 12:19:37.807719 output: Architecture: AArch64
238 12:19:37.807768 output: OS: Linux
239 12:19:37.807819 output: Load Address: unavailable
240 12:19:37.807868 output: Entry Point: unavailable
241 12:19:37.807918 output: Hash algo: crc32
242 12:19:37.807968 output: Hash value: 44acf54a
243 12:19:37.808018 output: Default Configuration: 'conf-1'
244 12:19:37.808067 output: Configuration 0 (conf-1)
245 12:19:37.808117 output: Description: mt8192-asurada-spherion-r0
246 12:19:37.808167 output: Kernel: kernel-1
247 12:19:37.808217 output: Init Ramdisk: ramdisk-1
248 12:19:37.808267 output: FDT: fdt-1
249 12:19:37.808317 output: Loadables: kernel-1
250 12:19:37.808367 output:
251 12:19:37.808566 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:19:37.808660 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:19:37.808760 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 12:19:37.808853 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 12:19:37.808933 No LXC device requested
256 12:19:37.809010 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:19:37.809095 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 12:19:37.809170 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:19:37.809239 Checking files for TFTP limit of 4294967296 bytes.
260 12:19:37.809727 end: 1 tftp-deploy (duration 00:00:22) [common]
261 12:19:37.809829 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:19:37.809918 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:19:37.810035 substitutions:
264 12:19:37.810103 - {DTB}: 11893130/tftp-deploy-ggesbx_0/dtb/mt8192-asurada-spherion-r0.dtb
265 12:19:37.810166 - {INITRD}: 11893130/tftp-deploy-ggesbx_0/ramdisk/ramdisk.cpio.gz
266 12:19:37.810223 - {KERNEL}: 11893130/tftp-deploy-ggesbx_0/kernel/Image
267 12:19:37.810279 - {LAVA_MAC}: None
268 12:19:37.810332 - {PRESEED_CONFIG}: None
269 12:19:37.810385 - {PRESEED_LOCAL}: None
270 12:19:37.810437 - {RAMDISK}: 11893130/tftp-deploy-ggesbx_0/ramdisk/ramdisk.cpio.gz
271 12:19:37.810490 - {ROOT_PART}: None
272 12:19:37.810542 - {ROOT}: None
273 12:19:37.810595 - {SERVER_IP}: 192.168.201.1
274 12:19:37.810646 - {TEE}: None
275 12:19:37.810698 Parsed boot commands:
276 12:19:37.810749 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:19:37.810922 Parsed boot commands: tftpboot 192.168.201.1 11893130/tftp-deploy-ggesbx_0/kernel/image.itb 11893130/tftp-deploy-ggesbx_0/kernel/cmdline
278 12:19:37.811007 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:19:37.811115 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:19:37.811225 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:19:37.811311 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:19:37.811381 Not connected, no need to disconnect.
283 12:19:37.811452 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:19:37.811532 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:19:37.811598 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
286 12:19:37.815669 Setting prompt string to ['lava-test: # ']
287 12:19:37.816043 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:19:37.816148 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:19:37.816249 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:19:37.816344 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:19:37.816575 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 12:19:42.963091 >> Command sent successfully.
293 12:19:42.966150 Returned 0 in 5 seconds
294 12:19:43.066979 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:19:43.069028 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:19:43.069826 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:19:43.070415 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:19:43.070910 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:19:43.071366 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:19:43.072586 [Enter `^Ec?' for help]
302 12:19:43.242918 639.733735] init: imageloader
303 12:19:43.243064 F0: 102B 0000
304 12:19:43.243172
305 12:19:43.246891 F3: 1001 0000 [0200]
306 12:19:43.247026
307 12:19:43.247157 F3: 1001 0000
308 12:19:43.247268
309 12:19:43.247365 F7: 102D 0000
310 12:19:43.247456
311 12:19:43.249557 F1: 0000 0000
312 12:19:43.249646
313 12:19:43.249710 V0: 0000 0000 [0001]
314 12:19:43.249773
315 12:19:43.253230 00: 0007 8000
316 12:19:43.253316
317 12:19:43.253381 01: 0000 0000
318 12:19:43.253442
319 12:19:43.256648 BP: 0C00 0209 [0000]
320 12:19:43.256730
321 12:19:43.256794 G0: 1182 0000
322 12:19:43.256867
323 12:19:43.260305 EC: 0000 0021 [4000]
324 12:19:43.260393
325 12:19:43.260461 S7: 0000 0000 [0000]
326 12:19:43.260525
327 12:19:43.263745 CC: 0000 0000 [0001]
328 12:19:43.263840
329 12:19:43.263915 T0: 0000 0040 [010F]
330 12:19:43.263984
331 12:19:43.266643 Jump to BL
332 12:19:43.266737
333 12:19:43.290537
334 12:19:43.290952
335 12:19:43.291310
336 12:19:43.297872 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 12:19:43.301727 ARM64: Exception handlers installed.
338 12:19:43.304886 ARM64: Testing exception
339 12:19:43.308488 ARM64: Done test exception
340 12:19:43.314589 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 12:19:43.325440 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 12:19:43.332444 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 12:19:43.341530 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 12:19:43.348615 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 12:19:43.358110 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 12:19:43.368584 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 12:19:43.375359 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 12:19:43.393328 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 12:19:43.397100 WDT: Last reset was cold boot
350 12:19:43.400059 SPI1(PAD0) initialized at 2873684 Hz
351 12:19:43.403239 SPI5(PAD0) initialized at 992727 Hz
352 12:19:43.406876 VBOOT: Loading verstage.
353 12:19:43.413040 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 12:19:43.416790 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 12:19:43.419711 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 12:19:43.423299 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 12:19:43.430400 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 12:19:43.437114 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 12:19:43.448657 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 12:19:43.448978
361 12:19:43.449278
362 12:19:43.457933 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 12:19:43.461181 ARM64: Exception handlers installed.
364 12:19:43.464643 ARM64: Testing exception
365 12:19:43.464942 ARM64: Done test exception
366 12:19:43.472456 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 12:19:43.475569 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 12:19:43.489202 Probing TPM: . done!
369 12:19:43.489552 TPM ready after 0 ms
370 12:19:43.496954 Connected to device vid:did:rid of 1ae0:0028:00
371 12:19:43.504058 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
372 12:19:43.561824 Initialized TPM device CR50 revision 0
373 12:19:43.573616 tlcl_send_startup: Startup return code is 0
374 12:19:43.573927 TPM: setup succeeded
375 12:19:43.584709 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 12:19:43.593614 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 12:19:43.605924 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 12:19:43.615968 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 12:19:43.618699 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 12:19:43.623548 in-header: 03 07 00 00 08 00 00 00
381 12:19:43.627467 in-data: aa e4 47 04 13 02 00 00
382 12:19:43.631171 Chrome EC: UHEPI supported
383 12:19:43.638226 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 12:19:43.641690 in-header: 03 95 00 00 08 00 00 00
385 12:19:43.645287 in-data: 18 20 20 08 00 00 00 00
386 12:19:43.645374 Phase 1
387 12:19:43.648818 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 12:19:43.656130 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 12:19:43.659941 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 12:19:43.663810 Recovery requested (1009000e)
391 12:19:43.672558 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 12:19:43.677123 tlcl_extend: response is 0
393 12:19:43.686795 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 12:19:43.692329 tlcl_extend: response is 0
395 12:19:43.698935 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 12:19:43.719064 read SPI 0x210d4 0x2173b: 15141 us, 9049 KB/s, 72.392 Mbps
397 12:19:43.725660 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 12:19:43.725740
399 12:19:43.725804
400 12:19:43.736192 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 12:19:43.739459 ARM64: Exception handlers installed.
402 12:19:43.742895 ARM64: Testing exception
403 12:19:43.743108 ARM64: Done test exception
404 12:19:43.764762 pmic_efuse_setting: Set efuses in 11 msecs
405 12:19:43.768468 pmwrap_interface_init: Select PMIF_VLD_RDY
406 12:19:43.774863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 12:19:43.779106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 12:19:43.784761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 12:19:43.788187 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 12:19:43.791894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 12:19:43.799192 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 12:19:43.803362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 12:19:43.807189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 12:19:43.813897 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 12:19:43.818203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 12:19:43.821334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 12:19:43.825439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 12:19:43.832242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 12:19:43.836169 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 12:19:43.843691 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 12:19:43.850422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 12:19:43.853965 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 12:19:43.861608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 12:19:43.865214 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 12:19:43.872119 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 12:19:43.876152 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 12:19:43.883070 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 12:19:43.886898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 12:19:43.893985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 12:19:43.898054 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 12:19:43.905316 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 12:19:43.908381 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 12:19:43.915952 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 12:19:43.919428 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 12:19:43.922845 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 12:19:43.930572 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 12:19:43.934161 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 12:19:43.937556 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 12:19:43.945283 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 12:19:43.948686 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 12:19:43.955715 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 12:19:43.959868 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 12:19:43.962948 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 12:19:43.966513 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 12:19:43.974254 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 12:19:43.978541 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 12:19:43.981702 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 12:19:43.984817 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 12:19:43.993077 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 12:19:43.996359 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 12:19:43.999584 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 12:19:44.003683 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 12:19:44.007183 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 12:19:44.011178 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 12:19:44.014047 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 12:19:44.021361 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 12:19:44.029271 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 12:19:44.036110 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 12:19:44.039525 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 12:19:44.050515 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 12:19:44.057782 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 12:19:44.061204 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 12:19:44.065103 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 12:19:44.072301 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:19:44.079253 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x27
466 12:19:44.082866 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 12:19:44.086589 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
468 12:19:44.093720 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 12:19:44.102760 [RTC]rtc_get_frequency_meter,154: input=15, output=851
470 12:19:44.111579 [RTC]rtc_get_frequency_meter,154: input=7, output=722
471 12:19:44.121658 [RTC]rtc_get_frequency_meter,154: input=11, output=786
472 12:19:44.131039 [RTC]rtc_get_frequency_meter,154: input=13, output=820
473 12:19:44.140386 [RTC]rtc_get_frequency_meter,154: input=12, output=803
474 12:19:44.149618 [RTC]rtc_get_frequency_meter,154: input=11, output=787
475 12:19:44.159554 [RTC]rtc_get_frequency_meter,154: input=12, output=802
476 12:19:44.163385 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
477 12:19:44.166541 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
478 12:19:44.174104 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 12:19:44.177728 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
480 12:19:44.181511 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 12:19:44.185339 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
482 12:19:44.189064 ADC[4]: Raw value=905541 ID=7
483 12:19:44.192192 ADC[3]: Raw value=213916 ID=1
484 12:19:44.192275 RAM Code: 0x71
485 12:19:44.196232 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 12:19:44.203513 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 12:19:44.210393 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 12:19:44.218301 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 12:19:44.221030 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 12:19:44.225472 in-header: 03 07 00 00 08 00 00 00
491 12:19:44.228392 in-data: aa e4 47 04 13 02 00 00
492 12:19:44.228474 Chrome EC: UHEPI supported
493 12:19:44.235255 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 12:19:44.239116 in-header: 03 95 00 00 08 00 00 00
495 12:19:44.243306 in-data: 18 20 20 08 00 00 00 00
496 12:19:44.246875 MRC: failed to locate region type 0.
497 12:19:44.254434 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 12:19:44.257652 DRAM-K: Running full calibration
499 12:19:44.261574 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 12:19:44.265025 header.status = 0x0
501 12:19:44.268497 header.version = 0x6 (expected: 0x6)
502 12:19:44.272865 header.size = 0xd00 (expected: 0xd00)
503 12:19:44.272951 header.flags = 0x0
504 12:19:44.279329 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 12:19:44.297041 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 12:19:44.304467 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 12:19:44.308156 dram_init: ddr_geometry: 2
508 12:19:44.308281 [EMI] MDL number = 2
509 12:19:44.311418 [EMI] Get MDL freq = 0
510 12:19:44.311544 dram_init: ddr_type: 0
511 12:19:44.315106 is_discrete_lpddr4: 1
512 12:19:44.318959 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 12:19:44.319164
514 12:19:44.319332
515 12:19:44.322878 [Bian_co] ETT version 0.0.0.1
516 12:19:44.326826 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 12:19:44.327016
518 12:19:44.329993 dramc_set_vcore_voltage set vcore to 650000
519 12:19:44.333025 Read voltage for 800, 4
520 12:19:44.333306 Vio18 = 0
521 12:19:44.333543 Vcore = 650000
522 12:19:44.333744 Vdram = 0
523 12:19:44.336307 Vddq = 0
524 12:19:44.336539 Vmddr = 0
525 12:19:44.339614 dram_init: config_dvfs: 1
526 12:19:44.343037 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 12:19:44.350154 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 12:19:44.354354 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
529 12:19:44.357662 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
530 12:19:44.361191 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
531 12:19:44.364714 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
532 12:19:44.368266 MEM_TYPE=3, freq_sel=18
533 12:19:44.368517 sv_algorithm_assistance_LP4_1600
534 12:19:44.375482 ============ PULL DRAM RESETB DOWN ============
535 12:19:44.378536 ========== PULL DRAM RESETB DOWN end =========
536 12:19:44.382331 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 12:19:44.384761 ===================================
538 12:19:44.388261 LPDDR4 DRAM CONFIGURATION
539 12:19:44.391704 ===================================
540 12:19:44.395177 EX_ROW_EN[0] = 0x0
541 12:19:44.395383 EX_ROW_EN[1] = 0x0
542 12:19:44.397916 LP4Y_EN = 0x0
543 12:19:44.398130 WORK_FSP = 0x0
544 12:19:44.401447 WL = 0x2
545 12:19:44.401597 RL = 0x2
546 12:19:44.404930 BL = 0x2
547 12:19:44.405100 RPST = 0x0
548 12:19:44.408389 RD_PRE = 0x0
549 12:19:44.408593 WR_PRE = 0x1
550 12:19:44.411680 WR_PST = 0x0
551 12:19:44.411940 DBI_WR = 0x0
552 12:19:44.415258 DBI_RD = 0x0
553 12:19:44.415549 OTF = 0x1
554 12:19:44.419432 ===================================
555 12:19:44.421677 ===================================
556 12:19:44.425556 ANA top config
557 12:19:44.428473 ===================================
558 12:19:44.431846 DLL_ASYNC_EN = 0
559 12:19:44.432262 ALL_SLAVE_EN = 1
560 12:19:44.434563 NEW_RANK_MODE = 1
561 12:19:44.438393 DLL_IDLE_MODE = 1
562 12:19:44.442041 LP45_APHY_COMB_EN = 1
563 12:19:44.444575 TX_ODT_DIS = 1
564 12:19:44.445045 NEW_8X_MODE = 1
565 12:19:44.448279 ===================================
566 12:19:44.451271 ===================================
567 12:19:44.454643 data_rate = 1600
568 12:19:44.458305 CKR = 1
569 12:19:44.461411 DQ_P2S_RATIO = 8
570 12:19:44.464685 ===================================
571 12:19:44.468071 CA_P2S_RATIO = 8
572 12:19:44.468689 DQ_CA_OPEN = 0
573 12:19:44.471935 DQ_SEMI_OPEN = 0
574 12:19:44.475354 CA_SEMI_OPEN = 0
575 12:19:44.478386 CA_FULL_RATE = 0
576 12:19:44.481633 DQ_CKDIV4_EN = 1
577 12:19:44.485210 CA_CKDIV4_EN = 1
578 12:19:44.485808 CA_PREDIV_EN = 0
579 12:19:44.488920 PH8_DLY = 0
580 12:19:44.491773 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 12:19:44.495165 DQ_AAMCK_DIV = 4
582 12:19:44.498192 CA_AAMCK_DIV = 4
583 12:19:44.501925 CA_ADMCK_DIV = 4
584 12:19:44.502435 DQ_TRACK_CA_EN = 0
585 12:19:44.504861 CA_PICK = 800
586 12:19:44.508439 CA_MCKIO = 800
587 12:19:44.512119 MCKIO_SEMI = 0
588 12:19:44.515535 PLL_FREQ = 3068
589 12:19:44.515984 DQ_UI_PI_RATIO = 32
590 12:19:44.519377 CA_UI_PI_RATIO = 0
591 12:19:44.523378 ===================================
592 12:19:44.526513 ===================================
593 12:19:44.530378 memory_type:LPDDR4
594 12:19:44.530894 GP_NUM : 10
595 12:19:44.533714 SRAM_EN : 1
596 12:19:44.534321 MD32_EN : 0
597 12:19:44.537816 ===================================
598 12:19:44.541337 [ANA_INIT] >>>>>>>>>>>>>>
599 12:19:44.545628 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 12:19:44.548930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 12:19:44.549681 ===================================
602 12:19:44.552222 data_rate = 1600,PCW = 0X7600
603 12:19:44.555152 ===================================
604 12:19:44.558557 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 12:19:44.565827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 12:19:44.571975 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:19:44.575177 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 12:19:44.578363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 12:19:44.581556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:19:44.585000 [ANA_INIT] flow start
611 12:19:44.585556 [ANA_INIT] PLL >>>>>>>>
612 12:19:44.588657 [ANA_INIT] PLL <<<<<<<<
613 12:19:44.591890 [ANA_INIT] MIDPI >>>>>>>>
614 12:19:44.595264 [ANA_INIT] MIDPI <<<<<<<<
615 12:19:44.595537 [ANA_INIT] DLL >>>>>>>>
616 12:19:44.598690 [ANA_INIT] flow end
617 12:19:44.601849 ============ LP4 DIFF to SE enter ============
618 12:19:44.604953 ============ LP4 DIFF to SE exit ============
619 12:19:44.608178 [ANA_INIT] <<<<<<<<<<<<<
620 12:19:44.611845 [Flow] Enable top DCM control >>>>>
621 12:19:44.614643 [Flow] Enable top DCM control <<<<<
622 12:19:44.618119 Enable DLL master slave shuffle
623 12:19:44.624741 ==============================================================
624 12:19:44.624819 Gating Mode config
625 12:19:44.631349 ==============================================================
626 12:19:44.631451 Config description:
627 12:19:44.641599 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 12:19:44.648239 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 12:19:44.654765 SELPH_MODE 0: By rank 1: By Phase
630 12:19:44.658238 ==============================================================
631 12:19:44.661521 GAT_TRACK_EN = 1
632 12:19:44.664764 RX_GATING_MODE = 2
633 12:19:44.667855 RX_GATING_TRACK_MODE = 2
634 12:19:44.671392 SELPH_MODE = 1
635 12:19:44.674971 PICG_EARLY_EN = 1
636 12:19:44.678031 VALID_LAT_VALUE = 1
637 12:19:44.681431 ==============================================================
638 12:19:44.684362 Enter into Gating configuration >>>>
639 12:19:44.687972 Exit from Gating configuration <<<<
640 12:19:44.691041 Enter into DVFS_PRE_config >>>>>
641 12:19:44.704210 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 12:19:44.707452 Exit from DVFS_PRE_config <<<<<
643 12:19:44.711034 Enter into PICG configuration >>>>
644 12:19:44.714293 Exit from PICG configuration <<<<
645 12:19:44.714374 [RX_INPUT] configuration >>>>>
646 12:19:44.717635 [RX_INPUT] configuration <<<<<
647 12:19:44.724170 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 12:19:44.727649 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 12:19:44.734107 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 12:19:44.740573 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 12:19:44.747280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 12:19:44.753851 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 12:19:44.757689 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 12:19:44.760678 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 12:19:44.767020 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 12:19:44.770760 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 12:19:44.774244 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 12:19:44.777034 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 12:19:44.780638 ===================================
660 12:19:44.783741 LPDDR4 DRAM CONFIGURATION
661 12:19:44.787209 ===================================
662 12:19:44.790557 EX_ROW_EN[0] = 0x0
663 12:19:44.790690 EX_ROW_EN[1] = 0x0
664 12:19:44.794122 LP4Y_EN = 0x0
665 12:19:44.794358 WORK_FSP = 0x0
666 12:19:44.797619 WL = 0x2
667 12:19:44.797874 RL = 0x2
668 12:19:44.801005 BL = 0x2
669 12:19:44.801200 RPST = 0x0
670 12:19:44.803807 RD_PRE = 0x0
671 12:19:44.804007 WR_PRE = 0x1
672 12:19:44.807251 WR_PST = 0x0
673 12:19:44.810982 DBI_WR = 0x0
674 12:19:44.811112 DBI_RD = 0x0
675 12:19:44.813842 OTF = 0x1
676 12:19:44.817496 ===================================
677 12:19:44.822182 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 12:19:44.823596 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 12:19:44.826923 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 12:19:44.830372 ===================================
681 12:19:44.833841 LPDDR4 DRAM CONFIGURATION
682 12:19:44.837279 ===================================
683 12:19:44.840213 EX_ROW_EN[0] = 0x10
684 12:19:44.840375 EX_ROW_EN[1] = 0x0
685 12:19:44.843734 LP4Y_EN = 0x0
686 12:19:44.843865 WORK_FSP = 0x0
687 12:19:44.846919 WL = 0x2
688 12:19:44.847018 RL = 0x2
689 12:19:44.850364 BL = 0x2
690 12:19:44.850446 RPST = 0x0
691 12:19:44.853471 RD_PRE = 0x0
692 12:19:44.853558 WR_PRE = 0x1
693 12:19:44.857030 WR_PST = 0x0
694 12:19:44.857117 DBI_WR = 0x0
695 12:19:44.860599 DBI_RD = 0x0
696 12:19:44.860692 OTF = 0x1
697 12:19:44.863797 ===================================
698 12:19:44.870251 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 12:19:44.874966 nWR fixed to 40
700 12:19:44.878629 [ModeRegInit_LP4] CH0 RK0
701 12:19:44.878902 [ModeRegInit_LP4] CH0 RK1
702 12:19:44.881873 [ModeRegInit_LP4] CH1 RK0
703 12:19:44.885113 [ModeRegInit_LP4] CH1 RK1
704 12:19:44.885342 match AC timing 13
705 12:19:44.891911 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 12:19:44.894999 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 12:19:44.898042 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 12:19:44.904457 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 12:19:44.908207 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 12:19:44.911646 [EMI DOE] emi_dcm 0
711 12:19:44.914978 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 12:19:44.915109 ==
713 12:19:44.918117 Dram Type= 6, Freq= 0, CH_0, rank 0
714 12:19:44.921188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 12:19:44.921276 ==
716 12:19:44.927614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 12:19:44.934752 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 12:19:44.942375 [CA 0] Center 37 (7~68) winsize 62
719 12:19:44.946360 [CA 1] Center 37 (7~68) winsize 62
720 12:19:44.949078 [CA 2] Center 34 (4~65) winsize 62
721 12:19:44.952987 [CA 3] Center 35 (4~66) winsize 63
722 12:19:44.955435 [CA 4] Center 33 (3~64) winsize 62
723 12:19:44.959008 [CA 5] Center 33 (3~64) winsize 62
724 12:19:44.959220
725 12:19:44.962739 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 12:19:44.962940
727 12:19:44.965740 [CATrainingPosCal] consider 1 rank data
728 12:19:44.969537 u2DelayCellTimex100 = 270/100 ps
729 12:19:44.972079 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 12:19:44.979013 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
731 12:19:44.982198 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
732 12:19:44.985404 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
733 12:19:44.988783 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
734 12:19:44.992185 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 12:19:44.992502
736 12:19:44.995711 CA PerBit enable=1, Macro0, CA PI delay=33
737 12:19:44.996098
738 12:19:44.999237 [CBTSetCACLKResult] CA Dly = 33
739 12:19:45.002153 CS Dly: 5 (0~36)
740 12:19:45.002686 ==
741 12:19:45.005815 Dram Type= 6, Freq= 0, CH_0, rank 1
742 12:19:45.009066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 12:19:45.009619 ==
744 12:19:45.012221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 12:19:45.019548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 12:19:45.029283 [CA 0] Center 38 (7~69) winsize 63
747 12:19:45.032350 [CA 1] Center 37 (7~68) winsize 62
748 12:19:45.035697 [CA 2] Center 35 (4~66) winsize 63
749 12:19:45.038970 [CA 3] Center 35 (4~66) winsize 63
750 12:19:45.042365 [CA 4] Center 34 (3~65) winsize 63
751 12:19:45.045808 [CA 5] Center 33 (3~64) winsize 62
752 12:19:45.046450
753 12:19:45.049115 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 12:19:45.049743
755 12:19:45.052440 [CATrainingPosCal] consider 2 rank data
756 12:19:45.055816 u2DelayCellTimex100 = 270/100 ps
757 12:19:45.058811 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 12:19:45.065681 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
759 12:19:45.068952 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
760 12:19:45.072188 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
761 12:19:45.075672 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
762 12:19:45.079141 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 12:19:45.079562
764 12:19:45.082242 CA PerBit enable=1, Macro0, CA PI delay=33
765 12:19:45.082790
766 12:19:45.085511 [CBTSetCACLKResult] CA Dly = 33
767 12:19:45.088359 CS Dly: 6 (0~38)
768 12:19:45.088783
769 12:19:45.092728 ----->DramcWriteLeveling(PI) begin...
770 12:19:45.093169 ==
771 12:19:45.095842 Dram Type= 6, Freq= 0, CH_0, rank 0
772 12:19:45.099888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 12:19:45.100311 ==
774 12:19:45.103316 Write leveling (Byte 0): 31 => 31
775 12:19:45.103736 Write leveling (Byte 1): 25 => 25
776 12:19:45.106656 DramcWriteLeveling(PI) end<-----
777 12:19:45.107102
778 12:19:45.107461 ==
779 12:19:45.110507 Dram Type= 6, Freq= 0, CH_0, rank 0
780 12:19:45.116950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 12:19:45.117590 ==
782 12:19:45.118156 [Gating] SW mode calibration
783 12:19:45.123799 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 12:19:45.130928 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 12:19:45.133835 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 12:19:45.140677 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 12:19:45.144563 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 12:19:45.147636 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:19:45.154058 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:19:45.157405 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:19:45.160846 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:19:45.167028 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:19:45.170858 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:19:45.174312 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:19:45.177300 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:19:45.184404 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:19:45.187405 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:19:45.190470 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:19:45.197256 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:19:45.201007 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:19:45.204090 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:19:45.210889 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 12:19:45.213881 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
804 12:19:45.217420 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:19:45.224427 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:19:45.227861 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:19:45.231127 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:19:45.237311 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:19:45.240431 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:19:45.243624 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:19:45.250444 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
812 12:19:45.254452 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
813 12:19:45.257272 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 12:19:45.263831 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:19:45.266706 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:19:45.270485 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:19:45.277203 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:19:45.280060 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
819 12:19:45.283501 0 10 8 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
820 12:19:45.289635 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
821 12:19:45.293115 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:19:45.296669 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:19:45.303276 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:19:45.306292 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:19:45.310594 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:19:45.316562 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
827 12:19:45.319768 0 11 8 | B1->B0 | 2c2c 3f3f | 0 0 | (0 0) (0 0)
828 12:19:45.323011 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
829 12:19:45.329920 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 12:19:45.333370 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:19:45.336342 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:19:45.342729 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:19:45.346259 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:19:45.349652 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
835 12:19:45.356648 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 12:19:45.359196 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:19:45.363306 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:19:45.370021 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:19:45.372951 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:19:45.375959 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:19:45.383238 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:19:45.385931 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:19:45.388907 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:19:45.395429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:19:45.398824 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:19:45.402198 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:19:45.409208 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:19:45.412602 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:19:45.415823 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:19:45.422236 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 12:19:45.425440 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 12:19:45.429344 Total UI for P1: 0, mck2ui 16
853 12:19:45.432472 best dqsien dly found for B0: ( 0, 14, 4)
854 12:19:45.435239 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 12:19:45.438209 Total UI for P1: 0, mck2ui 16
856 12:19:45.442018 best dqsien dly found for B1: ( 0, 14, 8)
857 12:19:45.444959 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
858 12:19:45.448571 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 12:19:45.449031
860 12:19:45.452168 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
861 12:19:45.458797 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 12:19:45.459410 [Gating] SW calibration Done
863 12:19:45.459777 ==
864 12:19:45.462400 Dram Type= 6, Freq= 0, CH_0, rank 0
865 12:19:45.469344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 12:19:45.469895 ==
867 12:19:45.470258 RX Vref Scan: 0
868 12:19:45.470639
869 12:19:45.472258 RX Vref 0 -> 0, step: 1
870 12:19:45.472920
871 12:19:45.475509 RX Delay -130 -> 252, step: 16
872 12:19:45.478906 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
873 12:19:45.482499 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 12:19:45.485950 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 12:19:50.046441 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 12:19:50.046605 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
877 12:19:50.046671 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
878 12:19:50.046731 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 12:19:50.046790 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
880 12:19:50.046936 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 12:19:50.047035 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
882 12:19:50.047143 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
883 12:19:50.047208 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 12:19:50.047328 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 12:19:50.047399 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
886 12:19:50.047461 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 12:19:50.047547 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 12:19:50.047633 ==
889 12:19:50.047686 Dram Type= 6, Freq= 0, CH_0, rank 0
890 12:19:50.047739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 12:19:50.047792 ==
892 12:19:50.047843 DQS Delay:
893 12:19:50.047898 DQS0 = 0, DQS1 = 0
894 12:19:50.047950 DQM Delay:
895 12:19:50.048001 DQM0 = 89, DQM1 = 75
896 12:19:50.048052 DQ Delay:
897 12:19:50.048106 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
898 12:19:50.048158 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
899 12:19:50.048209 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
900 12:19:50.048260 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
901 12:19:50.048311
902 12:19:50.048365
903 12:19:50.048416 ==
904 12:19:50.048467 Dram Type= 6, Freq= 0, CH_0, rank 0
905 12:19:50.048517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 12:19:50.048569 ==
907 12:19:50.048624
908 12:19:50.048675
909 12:19:50.048725 TX Vref Scan disable
910 12:19:50.048776 == TX Byte 0 ==
911 12:19:50.048827 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
912 12:19:50.048881 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
913 12:19:50.048934 == TX Byte 1 ==
914 12:19:50.049001 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
915 12:19:50.049066 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
916 12:19:50.049122 ==
917 12:19:50.049184 Dram Type= 6, Freq= 0, CH_0, rank 0
918 12:19:50.049234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 12:19:50.049285 ==
920 12:19:50.049338 TX Vref=22, minBit 0, minWin=27, winSum=438
921 12:19:50.049388 TX Vref=24, minBit 1, minWin=27, winSum=442
922 12:19:50.049438 TX Vref=26, minBit 1, minWin=27, winSum=445
923 12:19:50.049489 TX Vref=28, minBit 1, minWin=27, winSum=448
924 12:19:50.049539 TX Vref=30, minBit 1, minWin=27, winSum=448
925 12:19:50.049591 TX Vref=32, minBit 4, minWin=27, winSum=449
926 12:19:50.049642 [TxChooseVref] Worse bit 4, Min win 27, Win sum 449, Final Vref 32
927 12:19:50.049693
928 12:19:50.049743 Final TX Range 1 Vref 32
929 12:19:50.049792
930 12:19:50.049845 ==
931 12:19:50.049896 Dram Type= 6, Freq= 0, CH_0, rank 0
932 12:19:50.049990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 12:19:50.050074 ==
934 12:19:50.050165
935 12:19:50.050218
936 12:19:50.050282 TX Vref Scan disable
937 12:19:50.050333 == TX Byte 0 ==
938 12:19:50.050399 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
939 12:19:50.050467 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
940 12:19:50.050517 == TX Byte 1 ==
941 12:19:50.050567 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
942 12:19:50.050618 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
943 12:19:50.050688
944 12:19:50.050755 [DATLAT]
945 12:19:50.050805 Freq=800, CH0 RK0
946 12:19:50.050856
947 12:19:50.050921 DATLAT Default: 0xa
948 12:19:50.050971 0, 0xFFFF, sum = 0
949 12:19:50.051090 1, 0xFFFF, sum = 0
950 12:19:50.051165 2, 0xFFFF, sum = 0
951 12:19:50.051232 3, 0xFFFF, sum = 0
952 12:19:50.051299 4, 0xFFFF, sum = 0
953 12:19:50.051368 5, 0xFFFF, sum = 0
954 12:19:50.051419 6, 0xFFFF, sum = 0
955 12:19:50.051470 7, 0xFFFF, sum = 0
956 12:19:50.051521 8, 0xFFFF, sum = 0
957 12:19:50.051587 9, 0x0, sum = 1
958 12:19:50.051681 10, 0x0, sum = 2
959 12:19:50.051766 11, 0x0, sum = 3
960 12:19:50.051820 12, 0x0, sum = 4
961 12:19:50.051887 best_step = 10
962 12:19:50.051943
963 12:19:50.051994 ==
964 12:19:50.052046 Dram Type= 6, Freq= 0, CH_0, rank 0
965 12:19:50.052097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 12:19:50.052149 ==
967 12:19:50.052216 RX Vref Scan: 1
968 12:19:50.052266
969 12:19:50.052315 Set Vref Range= 32 -> 127
970 12:19:50.052365
971 12:19:50.052431 RX Vref 32 -> 127, step: 1
972 12:19:50.052497
973 12:19:50.052546 RX Delay -111 -> 252, step: 8
974 12:19:50.052596
975 12:19:50.052646 Set Vref, RX VrefLevel [Byte0]: 32
976 12:19:50.052711 [Byte1]: 32
977 12:19:50.052777
978 12:19:50.052827 Set Vref, RX VrefLevel [Byte0]: 33
979 12:19:50.052877 [Byte1]: 33
980 12:19:50.052927
981 12:19:50.052992 Set Vref, RX VrefLevel [Byte0]: 34
982 12:19:50.053057 [Byte1]: 34
983 12:19:50.053136
984 12:19:50.053186 Set Vref, RX VrefLevel [Byte0]: 35
985 12:19:50.053235 [Byte1]: 35
986 12:19:50.053300
987 12:19:50.053366 Set Vref, RX VrefLevel [Byte0]: 36
988 12:19:50.053416 [Byte1]: 36
989 12:19:50.053466
990 12:19:50.053515 Set Vref, RX VrefLevel [Byte0]: 37
991 12:19:50.053564 [Byte1]: 37
992 12:19:50.053642
993 12:19:50.053694 Set Vref, RX VrefLevel [Byte0]: 38
994 12:19:50.053744 [Byte1]: 38
995 12:19:50.053793
996 12:19:50.053843 Set Vref, RX VrefLevel [Byte0]: 39
997 12:19:50.053922 [Byte1]: 39
998 12:19:50.053989
999 12:19:50.054038 Set Vref, RX VrefLevel [Byte0]: 40
1000 12:19:50.054088 [Byte1]: 40
1001 12:19:50.054138
1002 12:19:50.054217 Set Vref, RX VrefLevel [Byte0]: 41
1003 12:19:50.054269 [Byte1]: 41
1004 12:19:50.054318
1005 12:19:50.054368 Set Vref, RX VrefLevel [Byte0]: 42
1006 12:19:50.054417 [Byte1]: 42
1007 12:19:50.054483
1008 12:19:50.054548 Set Vref, RX VrefLevel [Byte0]: 43
1009 12:19:50.054599 [Byte1]: 43
1010 12:19:50.054650
1011 12:19:50.054700 Set Vref, RX VrefLevel [Byte0]: 44
1012 12:19:50.054763 [Byte1]: 44
1013 12:19:50.054831
1014 12:19:50.054907 Set Vref, RX VrefLevel [Byte0]: 45
1015 12:19:50.054956 [Byte1]: 45
1016 12:19:50.055006
1017 12:19:50.055070 Set Vref, RX VrefLevel [Byte0]: 46
1018 12:19:50.055208 [Byte1]: 46
1019 12:19:50.055286
1020 12:19:50.055373 Set Vref, RX VrefLevel [Byte0]: 47
1021 12:19:50.055424 [Byte1]: 47
1022 12:19:50.055475
1023 12:19:50.055525 Set Vref, RX VrefLevel [Byte0]: 48
1024 12:19:50.055591 [Byte1]: 48
1025 12:19:50.055664
1026 12:19:50.055717 Set Vref, RX VrefLevel [Byte0]: 49
1027 12:19:50.055769 [Byte1]: 49
1028 12:19:50.055820
1029 12:19:50.055870 Set Vref, RX VrefLevel [Byte0]: 50
1030 12:19:50.055951 [Byte1]: 50
1031 12:19:50.056002
1032 12:19:50.056278 Set Vref, RX VrefLevel [Byte0]: 51
1033 12:19:50.056349 [Byte1]: 51
1034 12:19:50.056401
1035 12:19:50.056451 Set Vref, RX VrefLevel [Byte0]: 52
1036 12:19:50.056515 [Byte1]: 52
1037 12:19:50.056582
1038 12:19:50.056632 Set Vref, RX VrefLevel [Byte0]: 53
1039 12:19:50.056681 [Byte1]: 53
1040 12:19:50.056731
1041 12:19:50.056794 Set Vref, RX VrefLevel [Byte0]: 54
1042 12:19:50.056860 [Byte1]: 54
1043 12:19:50.056910
1044 12:19:50.056960 Set Vref, RX VrefLevel [Byte0]: 55
1045 12:19:50.057009 [Byte1]: 55
1046 12:19:50.057072
1047 12:19:50.057152 Set Vref, RX VrefLevel [Byte0]: 56
1048 12:19:50.057245 [Byte1]: 56
1049 12:19:50.057296
1050 12:19:50.057376 Set Vref, RX VrefLevel [Byte0]: 57
1051 12:19:50.057427 [Byte1]: 57
1052 12:19:50.057502
1053 12:19:50.057565 Set Vref, RX VrefLevel [Byte0]: 58
1054 12:19:50.057628 [Byte1]: 58
1055 12:19:50.057696
1056 12:19:50.057745 Set Vref, RX VrefLevel [Byte0]: 59
1057 12:19:50.057794 [Byte1]: 59
1058 12:19:50.057843
1059 12:19:50.057905 Set Vref, RX VrefLevel [Byte0]: 60
1060 12:19:50.057971 [Byte1]: 60
1061 12:19:50.058020
1062 12:19:50.058069 Set Vref, RX VrefLevel [Byte0]: 61
1063 12:19:50.058118 [Byte1]: 61
1064 12:19:50.058181
1065 12:19:50.058246 Set Vref, RX VrefLevel [Byte0]: 62
1066 12:19:50.058296 [Byte1]: 62
1067 12:19:50.058344
1068 12:19:50.058393 Set Vref, RX VrefLevel [Byte0]: 63
1069 12:19:50.058456 [Byte1]: 63
1070 12:19:50.058521
1071 12:19:50.058570 Set Vref, RX VrefLevel [Byte0]: 64
1072 12:19:50.058619 [Byte1]: 64
1073 12:19:50.058668
1074 12:19:50.058731 Set Vref, RX VrefLevel [Byte0]: 65
1075 12:19:50.058796 [Byte1]: 65
1076 12:19:50.058845
1077 12:19:50.058894 Set Vref, RX VrefLevel [Byte0]: 66
1078 12:19:50.058943 [Byte1]: 66
1079 12:19:50.059007
1080 12:19:50.059060 Set Vref, RX VrefLevel [Byte0]: 67
1081 12:19:50.059173 [Byte1]: 67
1082 12:19:50.059317
1083 12:19:50.059378 Set Vref, RX VrefLevel [Byte0]: 68
1084 12:19:50.059443 [Byte1]: 68
1085 12:19:50.059493
1086 12:19:50.059570 Set Vref, RX VrefLevel [Byte0]: 69
1087 12:19:50.059624 [Byte1]: 69
1088 12:19:50.059692
1089 12:19:50.059744 Set Vref, RX VrefLevel [Byte0]: 70
1090 12:19:50.059841 [Byte1]: 70
1091 12:19:50.059908
1092 12:19:50.059958 Set Vref, RX VrefLevel [Byte0]: 71
1093 12:19:50.060008 [Byte1]: 71
1094 12:19:50.060078
1095 12:19:50.060130 Set Vref, RX VrefLevel [Byte0]: 72
1096 12:19:50.060183 [Byte1]: 72
1097 12:19:50.060235
1098 12:19:50.060285 Set Vref, RX VrefLevel [Byte0]: 73
1099 12:19:50.060348 [Byte1]: 73
1100 12:19:50.060397
1101 12:19:50.060476 Set Vref, RX VrefLevel [Byte0]: 74
1102 12:19:50.060526 [Byte1]: 74
1103 12:19:50.060576
1104 12:19:50.060625 Final RX Vref Byte 0 = 55 to rank0
1105 12:19:50.060675 Final RX Vref Byte 1 = 60 to rank0
1106 12:19:50.060754 Final RX Vref Byte 0 = 55 to rank1
1107 12:19:50.060804 Final RX Vref Byte 1 = 60 to rank1==
1108 12:19:50.060853 Dram Type= 6, Freq= 0, CH_0, rank 0
1109 12:19:50.060902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1110 12:19:50.060952 ==
1111 12:19:50.061029 DQS Delay:
1112 12:19:50.061082 DQS0 = 0, DQS1 = 0
1113 12:19:50.061137 DQM Delay:
1114 12:19:50.061209 DQM0 = 87, DQM1 = 77
1115 12:19:50.061288 DQ Delay:
1116 12:19:50.061354 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1117 12:19:50.061404 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1118 12:19:50.061453 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =72
1119 12:19:50.061503 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1120 12:19:50.061566
1121 12:19:50.061632
1122 12:19:50.061681 [DQSOSCAuto] RK0, (LSB)MR18= 0x241e, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
1123 12:19:50.061732 CH0 RK0: MR19=606, MR18=241E
1124 12:19:50.061782 CH0_RK0: MR19=0x606, MR18=0x241E, DQSOSC=400, MR23=63, INC=92, DEC=61
1125 12:19:50.061846
1126 12:19:50.061911 ----->DramcWriteLeveling(PI) begin...
1127 12:19:50.061962 ==
1128 12:19:50.062011 Dram Type= 6, Freq= 0, CH_0, rank 1
1129 12:19:50.062061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 12:19:50.062140 ==
1131 12:19:50.062190 Write leveling (Byte 0): 34 => 34
1132 12:19:50.062240 Write leveling (Byte 1): 27 => 27
1133 12:19:50.062289 DramcWriteLeveling(PI) end<-----
1134 12:19:50.062339
1135 12:19:50.062414 ==
1136 12:19:50.062466 Dram Type= 6, Freq= 0, CH_0, rank 1
1137 12:19:50.062517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1138 12:19:50.062567 ==
1139 12:19:50.062617 [Gating] SW mode calibration
1140 12:19:50.062680 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1141 12:19:50.062746 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1142 12:19:50.062796 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1143 12:19:50.062846 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1144 12:19:50.062895 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1145 12:19:50.062959 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 12:19:50.063012 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 12:19:50.063063 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 12:19:50.063205 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 12:19:50.063283 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 12:19:50.063335 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 12:19:50.063385 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 12:19:50.063434 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 12:19:50.063497 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:19:50.063564 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:19:50.063614 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:19:50.063663 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:19:50.063713 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:19:50.063798 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:19:50.063863 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1160 12:19:50.063927 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1161 12:19:50.063976 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:19:50.064039 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:19:50.064124 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:19:50.064403 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:19:50.064463 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:19:50.064517 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:19:50.064568 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1168 12:19:50.064622 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
1169 12:19:50.064674 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1170 12:19:50.064725 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 12:19:50.064776 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 12:19:50.064826 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 12:19:50.064880 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 12:19:50.064930 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 12:19:50.064981 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1176 12:19:50.065031 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
1177 12:19:50.065082 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1178 12:19:50.065135 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:19:50.065186 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:19:50.065240 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:19:50.065332 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:19:50.065398 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:19:50.065453 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1184 12:19:50.065504 0 11 8 | B1->B0 | 2e2e 4040 | 0 0 | (0 0) (0 0)
1185 12:19:50.065555 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1186 12:19:50.065606 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 12:19:50.065659 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 12:19:50.065710 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 12:19:50.065760 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 12:19:50.065811 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 12:19:50.065861 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1192 12:19:50.065914 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1193 12:19:50.065965 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1194 12:19:50.066015 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 12:19:50.066065 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 12:19:50.066116 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 12:19:50.066169 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 12:19:50.066220 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:19:50.066270 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:19:50.066321 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:19:50.066374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:19:50.066425 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:19:50.066476 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:19:50.066526 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:19:50.066576 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:19:50.066629 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:19:50.066680 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1208 12:19:50.066738 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1209 12:19:50.066789 Total UI for P1: 0, mck2ui 16
1210 12:19:50.066840 best dqsien dly found for B0: ( 0, 14, 4)
1211 12:19:50.066895 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 12:19:50.066945 Total UI for P1: 0, mck2ui 16
1213 12:19:50.066995 best dqsien dly found for B1: ( 0, 14, 8)
1214 12:19:50.067046 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1215 12:19:50.067144 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1216 12:19:50.067200
1217 12:19:50.067256 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1218 12:19:50.067362 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1219 12:19:50.067433 [Gating] SW calibration Done
1220 12:19:50.067485 ==
1221 12:19:50.067536 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 12:19:50.067587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1223 12:19:50.067638 ==
1224 12:19:50.067692 RX Vref Scan: 0
1225 12:19:50.067743
1226 12:19:50.067794 RX Vref 0 -> 0, step: 1
1227 12:19:50.067844
1228 12:19:50.067894 RX Delay -130 -> 252, step: 16
1229 12:19:50.067949 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1230 12:19:50.068000 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1231 12:19:50.068050 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1232 12:19:50.068100 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1233 12:19:50.068150 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1234 12:19:50.068204 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1235 12:19:50.068253 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1236 12:19:50.068304 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1237 12:19:50.068363 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1238 12:19:50.068437 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1239 12:19:50.068490 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1240 12:19:50.068541 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1241 12:19:50.068592 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1242 12:19:50.068643 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1243 12:19:50.068698 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1244 12:19:50.068748 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1245 12:19:50.068799 ==
1246 12:19:50.068850 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 12:19:50.068903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 12:19:50.068955 ==
1249 12:19:50.069006 DQS Delay:
1250 12:19:50.069056 DQS0 = 0, DQS1 = 0
1251 12:19:50.069107 DQM Delay:
1252 12:19:50.069162 DQM0 = 86, DQM1 = 76
1253 12:19:50.069213 DQ Delay:
1254 12:19:50.069274 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1255 12:19:50.069326 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1256 12:19:50.069377 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
1257 12:19:50.069430 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1258 12:19:50.069481
1259 12:19:50.069531
1260 12:19:50.069581 ==
1261 12:19:50.069635 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 12:19:50.069686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 12:19:50.069736 ==
1264 12:19:50.069787
1265 12:19:50.069837
1266 12:19:50.069890 TX Vref Scan disable
1267 12:19:50.069941 == TX Byte 0 ==
1268 12:19:50.070248 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1269 12:19:50.070346 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1270 12:19:50.070429 == TX Byte 1 ==
1271 12:19:50.070508 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1272 12:19:50.070587 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1273 12:19:50.070668 ==
1274 12:19:50.070746 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 12:19:50.070825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 12:19:50.070907 ==
1277 12:19:50.070986 TX Vref=22, minBit 3, minWin=26, winSum=439
1278 12:19:50.071066 TX Vref=24, minBit 5, minWin=27, winSum=447
1279 12:19:50.071178 TX Vref=26, minBit 4, minWin=27, winSum=448
1280 12:19:50.071232 TX Vref=28, minBit 9, minWin=27, winSum=451
1281 12:19:50.071316 TX Vref=30, minBit 5, minWin=27, winSum=453
1282 12:19:50.071453 TX Vref=32, minBit 5, minWin=27, winSum=450
1283 12:19:50.071509 [TxChooseVref] Worse bit 5, Min win 27, Win sum 453, Final Vref 30
1284 12:19:50.071561
1285 12:19:50.071611 Final TX Range 1 Vref 30
1286 12:19:50.071664
1287 12:19:50.071714 ==
1288 12:19:50.071764 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 12:19:50.071814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 12:19:50.071865 ==
1291 12:19:50.071917
1292 12:19:50.071966
1293 12:19:50.072015 TX Vref Scan disable
1294 12:19:50.072065 == TX Byte 0 ==
1295 12:19:50.072113 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1296 12:19:50.072166 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1297 12:19:50.072217 == TX Byte 1 ==
1298 12:19:50.072266 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1299 12:19:50.072315 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1300 12:19:50.072383
1301 12:19:50.072437 [DATLAT]
1302 12:19:50.072550 Freq=800, CH0 RK1
1303 12:19:50.072601
1304 12:19:50.072650 DATLAT Default: 0xa
1305 12:19:50.072702 0, 0xFFFF, sum = 0
1306 12:19:50.072753 1, 0xFFFF, sum = 0
1307 12:19:50.072804 2, 0xFFFF, sum = 0
1308 12:19:50.072854 3, 0xFFFF, sum = 0
1309 12:19:50.072905 4, 0xFFFF, sum = 0
1310 12:19:50.072958 5, 0xFFFF, sum = 0
1311 12:19:50.073008 6, 0xFFFF, sum = 0
1312 12:19:50.073057 7, 0xFFFF, sum = 0
1313 12:19:50.073107 8, 0xFFFF, sum = 0
1314 12:19:50.073173 9, 0x0, sum = 1
1315 12:19:50.073239 10, 0x0, sum = 2
1316 12:19:50.073289 11, 0x0, sum = 3
1317 12:19:50.073339 12, 0x0, sum = 4
1318 12:19:50.073414 best_step = 10
1319 12:19:50.073479
1320 12:19:50.073569 ==
1321 12:19:50.073676 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 12:19:50.073761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 12:19:50.073840 ==
1324 12:19:50.073918 RX Vref Scan: 0
1325 12:19:50.073998
1326 12:19:50.074076 RX Vref 0 -> 0, step: 1
1327 12:19:50.074154
1328 12:19:50.074235 RX Delay -111 -> 252, step: 8
1329 12:19:50.074313 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1330 12:19:50.074424 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1331 12:19:50.074504 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1332 12:19:50.074582 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1333 12:19:50.074663 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1334 12:19:50.074741 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1335 12:19:50.074819 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1336 12:19:50.074897 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1337 12:19:50.074980 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1338 12:19:50.075059 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1339 12:19:50.075197 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1340 12:19:50.075276 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1341 12:19:50.075354 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1342 12:19:50.075435 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1343 12:19:50.075513 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1344 12:19:50.075591 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1345 12:19:50.075671 ==
1346 12:19:50.075749 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 12:19:50.075827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 12:19:50.075905 ==
1349 12:19:50.075985 DQS Delay:
1350 12:19:50.076062 DQS0 = 0, DQS1 = 0
1351 12:19:50.076140 DQM Delay:
1352 12:19:50.076220 DQM0 = 86, DQM1 = 77
1353 12:19:50.076297 DQ Delay:
1354 12:19:50.076374 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1355 12:19:50.076455 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1356 12:19:50.076533 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1357 12:19:50.076611 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1358 12:19:50.076707
1359 12:19:50.076817
1360 12:19:50.076872 [DQSOSCAuto] RK1, (LSB)MR18= 0x211d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
1361 12:19:50.077001 CH0 RK1: MR19=606, MR18=211D
1362 12:19:50.077082 CH0_RK1: MR19=0x606, MR18=0x211D, DQSOSC=401, MR23=63, INC=91, DEC=61
1363 12:19:50.077179 [RxdqsGatingPostProcess] freq 800
1364 12:19:50.077258 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1365 12:19:50.077336 Pre-setting of DQS Precalculation
1366 12:19:50.077418 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1367 12:19:50.077496 ==
1368 12:19:50.077574 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 12:19:50.077655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 12:19:50.077748 ==
1371 12:19:50.077828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1372 12:19:50.077912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1373 12:19:50.077992 [CA 0] Center 37 (6~68) winsize 63
1374 12:19:50.078071 [CA 1] Center 37 (6~68) winsize 63
1375 12:19:50.078154 [CA 2] Center 35 (5~65) winsize 61
1376 12:19:50.078234 [CA 3] Center 34 (4~64) winsize 61
1377 12:19:50.078313 [CA 4] Center 34 (4~65) winsize 62
1378 12:19:50.078395 [CA 5] Center 33 (3~64) winsize 62
1379 12:19:50.078474
1380 12:19:50.078553 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1381 12:19:50.078634
1382 12:19:50.078714 [CATrainingPosCal] consider 1 rank data
1383 12:19:50.078793 u2DelayCellTimex100 = 270/100 ps
1384 12:19:50.078875 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1385 12:19:50.078955 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1386 12:19:50.079035 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1387 12:19:50.079134 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1388 12:19:50.079204 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1389 12:19:50.079255 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1390 12:19:50.079305
1391 12:19:50.079355 CA PerBit enable=1, Macro0, CA PI delay=33
1392 12:19:50.079408
1393 12:19:50.079462 [CBTSetCACLKResult] CA Dly = 33
1394 12:19:50.079512 CS Dly: 5 (0~36)
1395 12:19:50.079562 ==
1396 12:19:50.079611 Dram Type= 6, Freq= 0, CH_1, rank 1
1397 12:19:50.079664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 12:19:50.079715 ==
1399 12:19:50.079764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 12:19:50.079815 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 12:19:50.080067 [CA 0] Center 36 (6~67) winsize 62
1402 12:19:50.080153 [CA 1] Center 36 (6~67) winsize 62
1403 12:19:50.080257 [CA 2] Center 34 (4~65) winsize 62
1404 12:19:50.080359 [CA 3] Center 33 (3~64) winsize 62
1405 12:19:50.080463 [CA 4] Center 34 (4~65) winsize 62
1406 12:19:50.080555 [CA 5] Center 34 (3~65) winsize 63
1407 12:19:50.080639
1408 12:19:50.080719 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1409 12:19:50.080799
1410 12:19:50.080878 [CATrainingPosCal] consider 2 rank data
1411 12:19:50.080961 u2DelayCellTimex100 = 270/100 ps
1412 12:19:50.081040 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1413 12:19:50.081120 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 12:19:50.081204 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1415 12:19:50.081283 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1416 12:19:50.081363 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 12:19:50.081445 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1418 12:19:50.081523
1419 12:19:50.081602 CA PerBit enable=1, Macro0, CA PI delay=33
1420 12:19:50.081684
1421 12:19:50.081763 [CBTSetCACLKResult] CA Dly = 33
1422 12:19:50.081841 CS Dly: 5 (0~37)
1423 12:19:50.081923
1424 12:19:50.082002 ----->DramcWriteLeveling(PI) begin...
1425 12:19:50.082082 ==
1426 12:19:50.082164 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 12:19:50.082244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 12:19:50.082323 ==
1429 12:19:50.082406 Write leveling (Byte 0): 26 => 26
1430 12:19:50.082485 Write leveling (Byte 1): 27 => 27
1431 12:19:50.082564 DramcWriteLeveling(PI) end<-----
1432 12:19:50.082645
1433 12:19:50.082724 ==
1434 12:19:50.082803 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 12:19:50.082885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 12:19:50.082964 ==
1437 12:19:50.083043 [Gating] SW mode calibration
1438 12:19:50.083174 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1439 12:19:50.083256 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1440 12:19:50.083339 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1441 12:19:50.083412 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1442 12:19:50.083464 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1443 12:19:50.083515 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 12:19:50.083569 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 12:19:50.083620 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 12:19:50.083670 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 12:19:50.083720 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 12:19:50.083770 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 12:19:50.083823 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 12:19:50.083874 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:19:50.083925 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:19:50.083976 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:19:50.084034 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:19:50.084089 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:19:50.084161 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:19:50.084213 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:19:50.084264 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1458 12:19:50.084317 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:19:50.084367 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:19:50.084417 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:19:50.084468 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:19:50.084518 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:19:50.084571 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:19:50.084621 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:19:50.084671 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:19:50.084722 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1467 12:19:50.084772 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 12:19:50.084826 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 12:19:50.084876 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 12:19:50.084926 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 12:19:50.084976 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 12:19:50.085026 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 12:19:50.085080 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
1474 12:19:50.085130 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1475 12:19:50.085180 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:19:50.085230 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:19:50.085283 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:19:50.085333 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:19:50.085383 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:19:50.085432 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:19:50.085482 0 11 4 | B1->B0 | 2828 3131 | 0 0 | (0 0) (1 1)
1482 12:19:50.085536 0 11 8 | B1->B0 | 3e3e 4343 | 0 0 | (1 1) (0 0)
1483 12:19:50.085586 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 12:19:50.085636 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 12:19:50.085687 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 12:19:50.085738 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 12:19:50.085790 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 12:19:50.085841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 12:19:50.085890 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 12:19:50.085940 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1491 12:19:50.085990 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1492 12:19:50.086043 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 12:19:50.086093 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 12:19:50.086142 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 12:19:50.086192 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 12:19:50.086242 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 12:19:50.086487 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 12:19:50.086547 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:19:50.086599 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:19:50.086649 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:19:50.086699 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:19:50.086752 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:19:50.086802 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:19:50.086853 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:19:50.086902 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1506 12:19:50.086970 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1507 12:19:50.087053 Total UI for P1: 0, mck2ui 16
1508 12:19:50.087122 best dqsien dly found for B0: ( 0, 14, 4)
1509 12:19:50.087174 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 12:19:50.087225 Total UI for P1: 0, mck2ui 16
1511 12:19:50.087279 best dqsien dly found for B1: ( 0, 14, 8)
1512 12:19:50.087330 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1513 12:19:50.087380 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1514 12:19:50.087431
1515 12:19:50.087483 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1516 12:19:50.087534 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1517 12:19:50.087584 [Gating] SW calibration Done
1518 12:19:50.087634 ==
1519 12:19:50.087685 Dram Type= 6, Freq= 0, CH_1, rank 0
1520 12:19:50.087739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1521 12:19:50.087790 ==
1522 12:19:50.087840 RX Vref Scan: 0
1523 12:19:50.087890
1524 12:19:50.087940 RX Vref 0 -> 0, step: 1
1525 12:19:50.087993
1526 12:19:50.088043 RX Delay -130 -> 252, step: 16
1527 12:19:50.088094 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1528 12:19:50.088144 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1529 12:19:50.088194 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1530 12:19:50.088254 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1531 12:19:50.088306 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1532 12:19:50.088375 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1533 12:19:50.088428 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1534 12:19:50.088482 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1535 12:19:50.088533 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1536 12:19:50.088584 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1537 12:19:50.088634 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1538 12:19:50.088684 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1539 12:19:50.088738 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1540 12:19:50.088788 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1541 12:19:50.088839 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1542 12:19:50.088889 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1543 12:19:50.088939 ==
1544 12:19:50.088992 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 12:19:50.089042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 12:19:50.089093 ==
1547 12:19:50.089142 DQS Delay:
1548 12:19:50.089192 DQS0 = 0, DQS1 = 0
1549 12:19:50.089245 DQM Delay:
1550 12:19:50.089295 DQM0 = 89, DQM1 = 78
1551 12:19:50.089344 DQ Delay:
1552 12:19:50.089394 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1553 12:19:50.089446 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1554 12:19:50.089496 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1555 12:19:50.089546 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1556 12:19:50.089596
1557 12:19:50.089645
1558 12:19:50.089697 ==
1559 12:19:50.089747 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 12:19:50.089799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 12:19:50.089849 ==
1562 12:19:50.089899
1563 12:19:50.089951
1564 12:19:50.090001 TX Vref Scan disable
1565 12:19:50.090050 == TX Byte 0 ==
1566 12:19:50.090100 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1567 12:19:50.090159 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1568 12:19:50.090213 == TX Byte 1 ==
1569 12:19:50.090262 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1570 12:19:50.090312 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1571 12:19:50.090362 ==
1572 12:19:50.090415 Dram Type= 6, Freq= 0, CH_1, rank 0
1573 12:19:50.090465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1574 12:19:50.090516 ==
1575 12:19:50.090566 TX Vref=22, minBit 0, minWin=27, winSum=444
1576 12:19:50.090617 TX Vref=24, minBit 2, minWin=27, winSum=447
1577 12:19:50.090669 TX Vref=26, minBit 4, minWin=27, winSum=452
1578 12:19:50.090719 TX Vref=28, minBit 2, minWin=27, winSum=454
1579 12:19:50.090769 TX Vref=30, minBit 1, minWin=28, winSum=457
1580 12:19:50.090820 TX Vref=32, minBit 0, minWin=28, winSum=457
1581 12:19:50.090882 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30
1582 12:19:50.090977
1583 12:19:50.091064 Final TX Range 1 Vref 30
1584 12:19:50.091155
1585 12:19:50.091235 ==
1586 12:19:50.091318 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 12:19:50.091373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 12:19:50.091428 ==
1589 12:19:50.091479
1590 12:19:50.091530
1591 12:19:50.091580 TX Vref Scan disable
1592 12:19:50.091630 == TX Byte 0 ==
1593 12:19:50.091680 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1594 12:19:50.091731 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1595 12:19:50.091781 == TX Byte 1 ==
1596 12:19:50.091831 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1597 12:19:50.091881 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1598 12:19:50.091931
1599 12:19:50.091981 [DATLAT]
1600 12:19:50.092030 Freq=800, CH1 RK0
1601 12:19:50.092082
1602 12:19:50.092131 DATLAT Default: 0xa
1603 12:19:50.092181 0, 0xFFFF, sum = 0
1604 12:19:50.092232 1, 0xFFFF, sum = 0
1605 12:19:50.092282 2, 0xFFFF, sum = 0
1606 12:19:50.092332 3, 0xFFFF, sum = 0
1607 12:19:50.092394 4, 0xFFFF, sum = 0
1608 12:19:50.092446 5, 0xFFFF, sum = 0
1609 12:19:50.092519 6, 0xFFFF, sum = 0
1610 12:19:50.092573 7, 0xFFFF, sum = 0
1611 12:19:50.092624 8, 0xFFFF, sum = 0
1612 12:19:50.092686 9, 0x0, sum = 1
1613 12:19:50.092746 10, 0x0, sum = 2
1614 12:19:50.092807 11, 0x0, sum = 3
1615 12:19:50.092859 12, 0x0, sum = 4
1616 12:19:50.092922 best_step = 10
1617 12:19:50.093019
1618 12:19:50.093106 ==
1619 12:19:50.093187 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 12:19:50.093271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 12:19:50.093350 ==
1622 12:19:50.093429 RX Vref Scan: 1
1623 12:19:50.093511
1624 12:19:50.093590 Set Vref Range= 32 -> 127
1625 12:19:50.093668
1626 12:19:50.093750 RX Vref 32 -> 127, step: 1
1627 12:19:50.093828
1628 12:19:50.093907 RX Delay -95 -> 252, step: 8
1629 12:19:50.093988
1630 12:19:50.094068 Set Vref, RX VrefLevel [Byte0]: 32
1631 12:19:50.094153 [Byte1]: 32
1632 12:19:50.094240
1633 12:19:50.094320 Set Vref, RX VrefLevel [Byte0]: 33
1634 12:19:50.094399 [Byte1]: 33
1635 12:19:50.094481
1636 12:19:50.094560 Set Vref, RX VrefLevel [Byte0]: 34
1637 12:19:50.094640 [Byte1]: 34
1638 12:19:50.094721
1639 12:19:50.094995 Set Vref, RX VrefLevel [Byte0]: 35
1640 12:19:50.095105 [Byte1]: 35
1641 12:19:50.095176
1642 12:19:50.095230 Set Vref, RX VrefLevel [Byte0]: 36
1643 12:19:50.095282 [Byte1]: 36
1644 12:19:50.095332
1645 12:19:50.095383 Set Vref, RX VrefLevel [Byte0]: 37
1646 12:19:50.095435 [Byte1]: 37
1647 12:19:50.095488
1648 12:19:50.095539 Set Vref, RX VrefLevel [Byte0]: 38
1649 12:19:50.095590 [Byte1]: 38
1650 12:19:50.095640
1651 12:19:50.095693 Set Vref, RX VrefLevel [Byte0]: 39
1652 12:19:50.095760 [Byte1]: 39
1653 12:19:50.095812
1654 12:19:50.095862 Set Vref, RX VrefLevel [Byte0]: 40
1655 12:19:50.095912 [Byte1]: 40
1656 12:19:50.095965
1657 12:19:50.096015 Set Vref, RX VrefLevel [Byte0]: 41
1658 12:19:50.096065 [Byte1]: 41
1659 12:19:50.096115
1660 12:19:50.096164 Set Vref, RX VrefLevel [Byte0]: 42
1661 12:19:50.096216 [Byte1]: 42
1662 12:19:50.096267
1663 12:19:50.096316 Set Vref, RX VrefLevel [Byte0]: 43
1664 12:19:50.096365 [Byte1]: 43
1665 12:19:50.096414
1666 12:19:50.096467 Set Vref, RX VrefLevel [Byte0]: 44
1667 12:19:50.096517 [Byte1]: 44
1668 12:19:50.096567
1669 12:19:50.096616 Set Vref, RX VrefLevel [Byte0]: 45
1670 12:19:50.096666 [Byte1]: 45
1671 12:19:50.096719
1672 12:19:50.096768 Set Vref, RX VrefLevel [Byte0]: 46
1673 12:19:50.096818 [Byte1]: 46
1674 12:19:50.096879
1675 12:19:50.096929 Set Vref, RX VrefLevel [Byte0]: 47
1676 12:19:50.096991 [Byte1]: 47
1677 12:19:50.097045
1678 12:19:50.097109 Set Vref, RX VrefLevel [Byte0]: 48
1679 12:19:50.097161 [Byte1]: 48
1680 12:19:50.097215
1681 12:19:50.097265 Set Vref, RX VrefLevel [Byte0]: 49
1682 12:19:50.097314 [Byte1]: 49
1683 12:19:50.097364
1684 12:19:50.097414 Set Vref, RX VrefLevel [Byte0]: 50
1685 12:19:50.097467 [Byte1]: 50
1686 12:19:50.097517
1687 12:19:50.097567 Set Vref, RX VrefLevel [Byte0]: 51
1688 12:19:50.097619 [Byte1]: 51
1689 12:19:50.097669
1690 12:19:50.097721 Set Vref, RX VrefLevel [Byte0]: 52
1691 12:19:50.097774 [Byte1]: 52
1692 12:19:50.097824
1693 12:19:50.097874 Set Vref, RX VrefLevel [Byte0]: 53
1694 12:19:50.097924 [Byte1]: 53
1695 12:19:50.097977
1696 12:19:50.098027 Set Vref, RX VrefLevel [Byte0]: 54
1697 12:19:50.098078 [Byte1]: 54
1698 12:19:50.098127
1699 12:19:50.098177 Set Vref, RX VrefLevel [Byte0]: 55
1700 12:19:50.098230 [Byte1]: 55
1701 12:19:50.098280
1702 12:19:50.098329 Set Vref, RX VrefLevel [Byte0]: 56
1703 12:19:50.098379 [Byte1]: 56
1704 12:19:50.098429
1705 12:19:50.098482 Set Vref, RX VrefLevel [Byte0]: 57
1706 12:19:50.098532 [Byte1]: 57
1707 12:19:50.098582
1708 12:19:50.098631 Set Vref, RX VrefLevel [Byte0]: 58
1709 12:19:50.098683 [Byte1]: 58
1710 12:19:50.098734
1711 12:19:50.098783 Set Vref, RX VrefLevel [Byte0]: 59
1712 12:19:50.098833 [Byte1]: 59
1713 12:19:50.098883
1714 12:19:50.098932 Set Vref, RX VrefLevel [Byte0]: 60
1715 12:19:50.098985 [Byte1]: 60
1716 12:19:50.099035
1717 12:19:50.099133 Set Vref, RX VrefLevel [Byte0]: 61
1718 12:19:50.099184 [Byte1]: 61
1719 12:19:50.099238
1720 12:19:50.099288 Set Vref, RX VrefLevel [Byte0]: 62
1721 12:19:50.099338 [Byte1]: 62
1722 12:19:50.099387
1723 12:19:50.099437 Set Vref, RX VrefLevel [Byte0]: 63
1724 12:19:50.099491 [Byte1]: 63
1725 12:19:50.099541
1726 12:19:50.099590 Set Vref, RX VrefLevel [Byte0]: 64
1727 12:19:50.099640 [Byte1]: 64
1728 12:19:50.099692
1729 12:19:50.099742 Set Vref, RX VrefLevel [Byte0]: 65
1730 12:19:50.099793 [Byte1]: 65
1731 12:19:50.099843
1732 12:19:50.099903 Set Vref, RX VrefLevel [Byte0]: 66
1733 12:19:50.099956 [Byte1]: 66
1734 12:19:50.100006
1735 12:19:50.100056 Set Vref, RX VrefLevel [Byte0]: 67
1736 12:19:50.100105 [Byte1]: 67
1737 12:19:50.100155
1738 12:19:50.100207 Set Vref, RX VrefLevel [Byte0]: 68
1739 12:19:50.100257 [Byte1]: 68
1740 12:19:50.100307
1741 12:19:50.100356 Set Vref, RX VrefLevel [Byte0]: 69
1742 12:19:50.100406 [Byte1]: 69
1743 12:19:50.100462
1744 12:19:50.100512 Set Vref, RX VrefLevel [Byte0]: 70
1745 12:19:50.100561 [Byte1]: 70
1746 12:19:50.100611
1747 12:19:50.100660 Set Vref, RX VrefLevel [Byte0]: 71
1748 12:19:50.100713 [Byte1]: 71
1749 12:19:50.100762
1750 12:19:50.100811 Set Vref, RX VrefLevel [Byte0]: 72
1751 12:19:50.100861 [Byte1]: 72
1752 12:19:50.100910
1753 12:19:50.100963 Set Vref, RX VrefLevel [Byte0]: 73
1754 12:19:50.101012 [Byte1]: 73
1755 12:19:50.101062
1756 12:19:50.101111 Set Vref, RX VrefLevel [Byte0]: 74
1757 12:19:50.101161 [Byte1]: 74
1758 12:19:50.101220
1759 12:19:50.101271 Set Vref, RX VrefLevel [Byte0]: 75
1760 12:19:50.101341 [Byte1]: 75
1761 12:19:50.101394
1762 12:19:50.101447 Set Vref, RX VrefLevel [Byte0]: 76
1763 12:19:50.101498 [Byte1]: 76
1764 12:19:50.101548
1765 12:19:50.101598 Set Vref, RX VrefLevel [Byte0]: 77
1766 12:19:50.101648 [Byte1]: 77
1767 12:19:50.101702
1768 12:19:50.101752 Final RX Vref Byte 0 = 61 to rank0
1769 12:19:50.101802 Final RX Vref Byte 1 = 61 to rank0
1770 12:19:50.101853 Final RX Vref Byte 0 = 61 to rank1
1771 12:19:50.101903 Final RX Vref Byte 1 = 61 to rank1==
1772 12:19:50.101957 Dram Type= 6, Freq= 0, CH_1, rank 0
1773 12:19:50.102007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1774 12:19:50.102058 ==
1775 12:19:50.102108 DQS Delay:
1776 12:19:50.102160 DQS0 = 0, DQS1 = 0
1777 12:19:50.102211 DQM Delay:
1778 12:19:50.102260 DQM0 = 86, DQM1 = 80
1779 12:19:50.102310 DQ Delay:
1780 12:19:50.102360 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1781 12:19:50.102413 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1782 12:19:50.102463 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1783 12:19:50.102512 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1784 12:19:50.102562
1785 12:19:50.102612
1786 12:19:50.102664 [DQSOSCAuto] RK0, (LSB)MR18= 0x1124, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
1787 12:19:50.102716 CH1 RK0: MR19=606, MR18=1124
1788 12:19:50.102766 CH1_RK0: MR19=0x606, MR18=0x1124, DQSOSC=400, MR23=63, INC=92, DEC=61
1789 12:19:50.102815
1790 12:19:50.102865 ----->DramcWriteLeveling(PI) begin...
1791 12:19:50.102919 ==
1792 12:19:50.102970 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 12:19:50.103020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 12:19:50.103070 ==
1795 12:19:50.103171 Write leveling (Byte 0): 26 => 26
1796 12:19:50.103429 Write leveling (Byte 1): 28 => 28
1797 12:19:50.103489 DramcWriteLeveling(PI) end<-----
1798 12:19:50.103541
1799 12:19:50.103591 ==
1800 12:19:50.103641 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 12:19:50.103694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 12:19:50.103745 ==
1803 12:19:50.103794 [Gating] SW mode calibration
1804 12:19:50.103845 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1805 12:19:50.103895 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1806 12:19:50.103949 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1807 12:19:50.104000 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1808 12:19:50.104050 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:19:50.104100 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:19:50.104152 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:19:50.104204 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:19:50.104254 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:19:50.104304 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:19:50.104354 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:19:50.104407 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:19:50.104458 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:19:50.104508 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:19:50.104558 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:19:50.104607 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:19:50.104660 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:19:50.104711 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:19:50.104760 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1823 12:19:50.104814 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1824 12:19:50.104869 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1825 12:19:50.104938 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:19:50.104991 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:19:50.105042 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:19:50.105092 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:19:50.105146 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:19:50.105196 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:19:50.105246 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1832 12:19:50.105295 0 9 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
1833 12:19:50.105345 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:19:50.105398 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 12:19:50.105448 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 12:19:50.105498 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 12:19:50.105548 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 12:19:50.105598 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1839 12:19:50.105650 0 10 4 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
1840 12:19:50.105700 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
1841 12:19:50.105750 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:19:50.105800 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:19:50.105850 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:19:50.105904 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:19:50.105954 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:19:50.106003 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:19:50.106054 0 11 4 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
1848 12:19:50.106106 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1849 12:19:50.106156 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:19:50.106206 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 12:19:50.106256 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 12:19:50.106306 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 12:19:50.106358 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 12:19:50.106408 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:19:50.106458 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1856 12:19:50.106507 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1857 12:19:50.106557 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:19:50.106609 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:19:50.106660 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:19:50.106710 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:19:50.106759 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:19:50.106809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:19:50.106866 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:19:50.106915 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:19:50.106965 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:19:50.107050 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:19:50.107157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:19:50.107209 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:19:50.107260 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:19:50.107310 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1871 12:19:50.107364 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1872 12:19:50.107413 Total UI for P1: 0, mck2ui 16
1873 12:19:50.107464 best dqsien dly found for B0: ( 0, 14, 0)
1874 12:19:50.107515 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 12:19:50.107565 Total UI for P1: 0, mck2ui 16
1876 12:19:50.107619 best dqsien dly found for B1: ( 0, 14, 4)
1877 12:19:50.107670 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1878 12:19:50.107721 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1879 12:19:50.107772
1880 12:19:50.107824 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1881 12:19:50.107875 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 12:19:50.107925 [Gating] SW calibration Done
1883 12:19:50.107975 ==
1884 12:19:50.108217 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 12:19:50.108275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 12:19:50.108330 ==
1887 12:19:50.108381 RX Vref Scan: 0
1888 12:19:50.108431
1889 12:19:50.108480 RX Vref 0 -> 0, step: 1
1890 12:19:50.108530
1891 12:19:50.108582 RX Delay -130 -> 252, step: 16
1892 12:19:50.108633 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1893 12:19:50.108683 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1894 12:19:50.108734 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1895 12:19:50.108797 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1896 12:19:50.108869 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1897 12:19:50.108922 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1898 12:19:50.108972 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1899 12:19:50.109034 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1900 12:19:50.109118 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1901 12:19:50.109202 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1902 12:19:50.109281 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1903 12:19:50.109360 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1904 12:19:50.109440 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1905 12:19:50.109522 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1906 12:19:50.109602 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1907 12:19:50.109682 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1908 12:19:50.109763 ==
1909 12:19:50.109843 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 12:19:50.109922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 12:19:50.110001 ==
1912 12:19:50.110083 DQS Delay:
1913 12:19:50.110162 DQS0 = 0, DQS1 = 0
1914 12:19:50.110240 DQM Delay:
1915 12:19:50.110319 DQM0 = 85, DQM1 = 84
1916 12:19:50.110400 DQ Delay:
1917 12:19:50.110479 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =77
1918 12:19:51.731809 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1919 12:19:51.731949 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1920 12:19:51.732013 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1921 12:19:51.732073
1922 12:19:51.732129
1923 12:19:51.732187 ==
1924 12:19:51.732243 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 12:19:51.732296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 12:19:51.732350 ==
1927 12:19:51.732403
1928 12:19:51.732457
1929 12:19:51.732508 TX Vref Scan disable
1930 12:19:51.732560 == TX Byte 0 ==
1931 12:19:51.732611 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1932 12:19:51.732663 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1933 12:19:51.732719 == TX Byte 1 ==
1934 12:19:51.732772 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1935 12:19:51.732823 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1936 12:19:51.732874 ==
1937 12:19:51.732925 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 12:19:51.732979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 12:19:51.733031 ==
1940 12:19:51.733082 TX Vref=22, minBit 1, minWin=27, winSum=447
1941 12:19:51.733133 TX Vref=24, minBit 0, minWin=27, winSum=447
1942 12:19:51.733184 TX Vref=26, minBit 5, minWin=27, winSum=452
1943 12:19:51.733239 TX Vref=28, minBit 6, minWin=27, winSum=455
1944 12:19:51.733327 TX Vref=30, minBit 0, minWin=27, winSum=452
1945 12:19:51.733381 TX Vref=32, minBit 2, minWin=27, winSum=455
1946 12:19:51.733433 [TxChooseVref] Worse bit 6, Min win 27, Win sum 455, Final Vref 28
1947 12:19:51.733485
1948 12:19:51.733538 Final TX Range 1 Vref 28
1949 12:19:51.733590
1950 12:19:51.733640 ==
1951 12:19:51.733690 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 12:19:51.733740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 12:19:51.733791 ==
1954 12:19:51.733844
1955 12:19:51.733896
1956 12:19:51.733946 TX Vref Scan disable
1957 12:19:51.733995 == TX Byte 0 ==
1958 12:19:51.734046 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1959 12:19:51.734100 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1960 12:19:51.734159 == TX Byte 1 ==
1961 12:19:51.734211 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1962 12:19:51.734282 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1963 12:19:51.734370
1964 12:19:51.734451 [DATLAT]
1965 12:19:51.734531 Freq=800, CH1 RK1
1966 12:19:51.734611
1967 12:19:51.734693 DATLAT Default: 0xa
1968 12:19:51.734772 0, 0xFFFF, sum = 0
1969 12:19:51.734854 1, 0xFFFF, sum = 0
1970 12:19:51.734938 2, 0xFFFF, sum = 0
1971 12:19:51.735021 3, 0xFFFF, sum = 0
1972 12:19:51.735106 4, 0xFFFF, sum = 0
1973 12:19:51.735160 5, 0xFFFF, sum = 0
1974 12:19:51.735217 6, 0xFFFF, sum = 0
1975 12:19:51.735276 7, 0xFFFF, sum = 0
1976 12:19:51.735353 8, 0xFFFF, sum = 0
1977 12:19:51.735407 9, 0x0, sum = 1
1978 12:19:51.735459 10, 0x0, sum = 2
1979 12:19:51.735515 11, 0x0, sum = 3
1980 12:19:51.735568 12, 0x0, sum = 4
1981 12:19:51.735619 best_step = 10
1982 12:19:51.735669
1983 12:19:51.735720 ==
1984 12:19:51.735773 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 12:19:51.735823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 12:19:51.735874 ==
1987 12:19:51.735924 RX Vref Scan: 0
1988 12:19:51.735974
1989 12:19:51.736024 RX Vref 0 -> 0, step: 1
1990 12:19:51.736078
1991 12:19:51.736129 RX Delay -95 -> 252, step: 8
1992 12:19:51.736180 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1993 12:19:51.736231 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1994 12:19:51.736282 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1995 12:19:51.736335 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1996 12:19:51.736386 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1997 12:19:51.736436 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1998 12:19:51.736487 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1999 12:19:51.736537 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2000 12:19:51.736587 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2001 12:19:51.736641 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2002 12:19:51.736693 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2003 12:19:51.736744 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2004 12:19:51.736793 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2005 12:19:51.736843 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2006 12:19:51.736897 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2007 12:19:51.736948 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2008 12:19:51.736998 ==
2009 12:19:51.737048 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 12:19:51.737099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 12:19:51.737152 ==
2012 12:19:51.737204 DQS Delay:
2013 12:19:51.737264 DQS0 = 0, DQS1 = 0
2014 12:19:51.737353 DQM Delay:
2015 12:19:51.737452 DQM0 = 86, DQM1 = 83
2016 12:19:51.737535 DQ Delay:
2017 12:19:51.737589 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2018 12:19:51.737644 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2019 12:19:51.737696 DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76
2020 12:19:51.737747 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2021 12:19:51.737798
2022 12:19:51.737848
2023 12:19:51.737899 [DQSOSCAuto] RK1, (LSB)MR18= 0x1531, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 404 ps
2024 12:19:51.737953 CH1 RK1: MR19=606, MR18=1531
2025 12:19:51.738212 CH1_RK1: MR19=0x606, MR18=0x1531, DQSOSC=397, MR23=63, INC=93, DEC=62
2026 12:19:51.738271 [RxdqsGatingPostProcess] freq 800
2027 12:19:51.738330 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 12:19:51.738434 Pre-setting of DQS Precalculation
2029 12:19:51.738537 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 12:19:51.738645 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 12:19:51.738801 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 12:19:51.738926
2033 12:19:51.739011
2034 12:19:51.739116 [Calibration Summary] 1600 Mbps
2035 12:19:51.739172 CH 0, Rank 0
2036 12:19:51.739224 SW Impedance : PASS
2037 12:19:51.739275 DUTY Scan : NO K
2038 12:19:51.739339 ZQ Calibration : PASS
2039 12:19:51.739410 Jitter Meter : NO K
2040 12:19:51.739462 CBT Training : PASS
2041 12:19:51.739513 Write leveling : PASS
2042 12:19:51.739563 RX DQS gating : PASS
2043 12:19:51.739618 RX DQ/DQS(RDDQC) : PASS
2044 12:19:51.739670 TX DQ/DQS : PASS
2045 12:19:51.739721 RX DATLAT : PASS
2046 12:19:51.739772 RX DQ/DQS(Engine): PASS
2047 12:19:51.739822 TX OE : NO K
2048 12:19:51.739873 All Pass.
2049 12:19:51.739927
2050 12:19:51.739978 CH 0, Rank 1
2051 12:19:51.740040 SW Impedance : PASS
2052 12:19:51.740094 DUTY Scan : NO K
2053 12:19:51.740159 ZQ Calibration : PASS
2054 12:19:51.740210 Jitter Meter : NO K
2055 12:19:51.740265 CBT Training : PASS
2056 12:19:51.740318 Write leveling : PASS
2057 12:19:51.740369 RX DQS gating : PASS
2058 12:19:51.740420 RX DQ/DQS(RDDQC) : PASS
2059 12:19:51.740470 TX DQ/DQS : PASS
2060 12:19:51.740521 RX DATLAT : PASS
2061 12:19:51.740574 RX DQ/DQS(Engine): PASS
2062 12:19:51.740625 TX OE : NO K
2063 12:19:51.740675 All Pass.
2064 12:19:51.740726
2065 12:19:51.740776 CH 1, Rank 0
2066 12:19:51.740830 SW Impedance : PASS
2067 12:19:51.740892 DUTY Scan : NO K
2068 12:19:51.740943 ZQ Calibration : PASS
2069 12:19:51.740994 Jitter Meter : NO K
2070 12:19:51.741044 CBT Training : PASS
2071 12:19:51.741098 Write leveling : PASS
2072 12:19:51.741147 RX DQS gating : PASS
2073 12:19:51.741198 RX DQ/DQS(RDDQC) : PASS
2074 12:19:51.741248 TX DQ/DQS : PASS
2075 12:19:51.741298 RX DATLAT : PASS
2076 12:19:51.741348 RX DQ/DQS(Engine): PASS
2077 12:19:51.741402 TX OE : NO K
2078 12:19:51.741455 All Pass.
2079 12:19:51.741505
2080 12:19:51.741555 CH 1, Rank 1
2081 12:19:51.741605 SW Impedance : PASS
2082 12:19:51.741658 DUTY Scan : NO K
2083 12:19:51.741709 ZQ Calibration : PASS
2084 12:19:51.741759 Jitter Meter : NO K
2085 12:19:51.741809 CBT Training : PASS
2086 12:19:51.741859 Write leveling : PASS
2087 12:19:51.741910 RX DQS gating : PASS
2088 12:19:51.741963 RX DQ/DQS(RDDQC) : PASS
2089 12:19:51.742016 TX DQ/DQS : PASS
2090 12:19:51.742066 RX DATLAT : PASS
2091 12:19:51.742116 RX DQ/DQS(Engine): PASS
2092 12:19:51.742166 TX OE : NO K
2093 12:19:51.742219 All Pass.
2094 12:19:51.742269
2095 12:19:51.742319 DramC Write-DBI off
2096 12:19:51.742369 PER_BANK_REFRESH: Hybrid Mode
2097 12:19:51.742419 TX_TRACKING: ON
2098 12:19:51.742474 [GetDramInforAfterCalByMRR] Vendor 6.
2099 12:19:51.742526 [GetDramInforAfterCalByMRR] Revision 606.
2100 12:19:51.742577 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 12:19:51.742628 MR0 0x3b3b
2102 12:19:51.742678 MR8 0x5151
2103 12:19:51.742731 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 12:19:51.742782
2105 12:19:51.742832 MR0 0x3b3b
2106 12:19:51.742882 MR8 0x5151
2107 12:19:51.742932 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 12:19:51.742982
2109 12:19:51.743035 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 12:19:51.743099 [FAST_K] Save calibration result to emmc
2111 12:19:51.743151 [FAST_K] Save calibration result to emmc
2112 12:19:51.743202 dram_init: config_dvfs: 1
2113 12:19:51.743253 dramc_set_vcore_voltage set vcore to 662500
2114 12:19:51.743308 Read voltage for 1200, 2
2115 12:19:51.743359 Vio18 = 0
2116 12:19:51.743409 Vcore = 662500
2117 12:19:51.743460 Vdram = 0
2118 12:19:51.743510 Vddq = 0
2119 12:19:51.743563 Vmddr = 0
2120 12:19:51.743614 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 12:19:51.743667 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 12:19:51.743718 MEM_TYPE=3, freq_sel=15
2123 12:19:51.743768 sv_algorithm_assistance_LP4_1600
2124 12:19:51.743819 ============ PULL DRAM RESETB DOWN ============
2125 12:19:51.743873 ========== PULL DRAM RESETB DOWN end =========
2126 12:19:51.743932 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 12:19:51.743984 ===================================
2128 12:19:51.744035 LPDDR4 DRAM CONFIGURATION
2129 12:19:51.744086 ===================================
2130 12:19:51.744140 EX_ROW_EN[0] = 0x0
2131 12:19:51.744193 EX_ROW_EN[1] = 0x0
2132 12:19:51.744243 LP4Y_EN = 0x0
2133 12:19:51.744293 WORK_FSP = 0x0
2134 12:19:51.744354 WL = 0x4
2135 12:19:51.744425 RL = 0x4
2136 12:19:51.744480 BL = 0x2
2137 12:19:51.744531 RPST = 0x0
2138 12:19:51.744581 RD_PRE = 0x0
2139 12:19:51.744631 WR_PRE = 0x1
2140 12:19:51.744685 WR_PST = 0x0
2141 12:19:51.744736 DBI_WR = 0x0
2142 12:19:51.744788 DBI_RD = 0x0
2143 12:19:51.744838 OTF = 0x1
2144 12:19:51.744890 ===================================
2145 12:19:51.744941 ===================================
2146 12:19:51.744995 ANA top config
2147 12:19:51.745045 ===================================
2148 12:19:51.745096 DLL_ASYNC_EN = 0
2149 12:19:51.745147 ALL_SLAVE_EN = 0
2150 12:19:51.745198 NEW_RANK_MODE = 1
2151 12:19:51.745252 DLL_IDLE_MODE = 1
2152 12:19:51.745304 LP45_APHY_COMB_EN = 1
2153 12:19:51.745355 TX_ODT_DIS = 1
2154 12:19:51.745406 NEW_8X_MODE = 1
2155 12:19:51.745456 ===================================
2156 12:19:51.745507 ===================================
2157 12:19:51.745561 data_rate = 2400
2158 12:19:51.745611 CKR = 1
2159 12:19:51.745662 DQ_P2S_RATIO = 8
2160 12:19:51.745712 ===================================
2161 12:19:51.745762 CA_P2S_RATIO = 8
2162 12:19:51.745815 DQ_CA_OPEN = 0
2163 12:19:51.745868 DQ_SEMI_OPEN = 0
2164 12:19:51.745918 CA_SEMI_OPEN = 0
2165 12:19:51.745969 CA_FULL_RATE = 0
2166 12:19:51.746020 DQ_CKDIV4_EN = 0
2167 12:19:51.746073 CA_CKDIV4_EN = 0
2168 12:19:51.746124 CA_PREDIV_EN = 0
2169 12:19:51.746173 PH8_DLY = 17
2170 12:19:51.746223 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 12:19:51.746274 DQ_AAMCK_DIV = 4
2172 12:19:51.746521 CA_AAMCK_DIV = 4
2173 12:19:51.746579 CA_ADMCK_DIV = 4
2174 12:19:51.746635 DQ_TRACK_CA_EN = 0
2175 12:19:51.746687 CA_PICK = 1200
2176 12:19:51.746739 CA_MCKIO = 1200
2177 12:19:51.746790 MCKIO_SEMI = 0
2178 12:19:51.746841 PLL_FREQ = 2366
2179 12:19:51.746895 DQ_UI_PI_RATIO = 32
2180 12:19:51.746948 CA_UI_PI_RATIO = 0
2181 12:19:51.746999 ===================================
2182 12:19:51.747050 ===================================
2183 12:19:51.747164 memory_type:LPDDR4
2184 12:19:51.747259 GP_NUM : 10
2185 12:19:51.747318 SRAM_EN : 1
2186 12:19:51.747370 MD32_EN : 0
2187 12:19:51.747425 ===================================
2188 12:19:51.747477 [ANA_INIT] >>>>>>>>>>>>>>
2189 12:19:51.747528 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 12:19:51.747579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 12:19:51.747636 ===================================
2192 12:19:51.747692 data_rate = 2400,PCW = 0X5b00
2193 12:19:51.747743 ===================================
2194 12:19:51.747794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 12:19:51.747845 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 12:19:51.747896 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 12:19:51.747951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 12:19:51.748002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 12:19:51.748055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 12:19:51.748105 [ANA_INIT] flow start
2201 12:19:51.748156 [ANA_INIT] PLL >>>>>>>>
2202 12:19:51.748212 [ANA_INIT] PLL <<<<<<<<
2203 12:19:51.748280 [ANA_INIT] MIDPI >>>>>>>>
2204 12:19:51.748336 [ANA_INIT] MIDPI <<<<<<<<
2205 12:19:51.748386 [ANA_INIT] DLL >>>>>>>>
2206 12:19:51.748436 [ANA_INIT] DLL <<<<<<<<
2207 12:19:51.748487 [ANA_INIT] flow end
2208 12:19:51.748541 ============ LP4 DIFF to SE enter ============
2209 12:19:51.748595 ============ LP4 DIFF to SE exit ============
2210 12:19:51.748646 [ANA_INIT] <<<<<<<<<<<<<
2211 12:19:51.748696 [Flow] Enable top DCM control >>>>>
2212 12:19:51.748747 [Flow] Enable top DCM control <<<<<
2213 12:19:51.748801 Enable DLL master slave shuffle
2214 12:19:51.748851 ==============================================================
2215 12:19:51.748902 Gating Mode config
2216 12:19:51.748953 ==============================================================
2217 12:19:51.749004 Config description:
2218 12:19:51.749057 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 12:19:51.749109 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 12:19:51.749162 SELPH_MODE 0: By rank 1: By Phase
2221 12:19:51.749213 ==============================================================
2222 12:19:51.749273 GAT_TRACK_EN = 1
2223 12:19:51.749328 RX_GATING_MODE = 2
2224 12:19:51.749379 RX_GATING_TRACK_MODE = 2
2225 12:19:51.749430 SELPH_MODE = 1
2226 12:19:51.749481 PICG_EARLY_EN = 1
2227 12:19:51.749531 VALID_LAT_VALUE = 1
2228 12:19:51.749582 ==============================================================
2229 12:19:51.749636 Enter into Gating configuration >>>>
2230 12:19:51.749689 Exit from Gating configuration <<<<
2231 12:19:51.749740 Enter into DVFS_PRE_config >>>>>
2232 12:19:51.749791 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 12:19:51.749843 Exit from DVFS_PRE_config <<<<<
2234 12:19:51.749897 Enter into PICG configuration >>>>
2235 12:19:51.749948 Exit from PICG configuration <<<<
2236 12:19:51.749998 [RX_INPUT] configuration >>>>>
2237 12:19:51.750049 [RX_INPUT] configuration <<<<<
2238 12:19:51.750100 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 12:19:51.750151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 12:19:51.750205 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 12:19:51.750259 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 12:19:51.750310 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 12:19:51.750361 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 12:19:51.750411 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 12:19:51.750465 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 12:19:51.750516 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 12:19:51.750567 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 12:19:51.750617 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 12:19:51.750668 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 12:19:51.750731 ===================================
2251 12:19:51.750785 LPDDR4 DRAM CONFIGURATION
2252 12:19:51.750836 ===================================
2253 12:19:51.750887 EX_ROW_EN[0] = 0x0
2254 12:19:51.750938 EX_ROW_EN[1] = 0x0
2255 12:19:51.750991 LP4Y_EN = 0x0
2256 12:19:51.751042 WORK_FSP = 0x0
2257 12:19:51.751119 WL = 0x4
2258 12:19:51.751185 RL = 0x4
2259 12:19:51.751245 BL = 0x2
2260 12:19:51.751332 RPST = 0x0
2261 12:19:51.751386 RD_PRE = 0x0
2262 12:19:51.751437 WR_PRE = 0x1
2263 12:19:51.751491 WR_PST = 0x0
2264 12:19:51.751542 DBI_WR = 0x0
2265 12:19:51.751592 DBI_RD = 0x0
2266 12:19:51.751642 OTF = 0x1
2267 12:19:51.751693 ===================================
2268 12:19:51.751744 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 12:19:51.751798 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 12:19:51.751851 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 12:19:51.751902 ===================================
2272 12:19:51.751953 LPDDR4 DRAM CONFIGURATION
2273 12:19:51.752004 ===================================
2274 12:19:51.752058 EX_ROW_EN[0] = 0x10
2275 12:19:51.752108 EX_ROW_EN[1] = 0x0
2276 12:19:51.752158 LP4Y_EN = 0x0
2277 12:19:51.752208 WORK_FSP = 0x0
2278 12:19:51.752259 WL = 0x4
2279 12:19:51.752518 RL = 0x4
2280 12:19:51.752583 BL = 0x2
2281 12:19:51.752642 RPST = 0x0
2282 12:19:51.752695 RD_PRE = 0x0
2283 12:19:51.752746 WR_PRE = 0x1
2284 12:19:51.752797 WR_PST = 0x0
2285 12:19:51.752848 DBI_WR = 0x0
2286 12:19:51.752905 DBI_RD = 0x0
2287 12:19:51.752992 OTF = 0x1
2288 12:19:51.753057 ===================================
2289 12:19:51.753110 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 12:19:51.753166 ==
2291 12:19:51.753221 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 12:19:51.753278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 12:19:51.753345 ==
2294 12:19:51.753398 [Duty_Offset_Calibration]
2295 12:19:51.753452 B0:2 B1:0 CA:4
2296 12:19:51.753505
2297 12:19:51.753556 [DutyScan_Calibration_Flow] k_type=0
2298 12:19:51.753606
2299 12:19:51.753656 ==CLK 0==
2300 12:19:51.753706 Final CLK duty delay cell = 0
2301 12:19:51.753761 [0] MAX Duty = 5156%(X100), DQS PI = 14
2302 12:19:51.753811 [0] MIN Duty = 4969%(X100), DQS PI = 8
2303 12:19:51.753861 [0] AVG Duty = 5062%(X100)
2304 12:19:51.753911
2305 12:19:51.754000 CH0 CLK Duty spec in!! Max-Min= 187%
2306 12:19:51.754094 [DutyScan_Calibration_Flow] ====Done====
2307 12:19:51.754175
2308 12:19:51.754257 [DutyScan_Calibration_Flow] k_type=1
2309 12:19:51.754336
2310 12:19:51.754415 ==DQS 0 ==
2311 12:19:51.754494 Final DQS duty delay cell = -4
2312 12:19:51.754577 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2313 12:19:51.754659 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2314 12:19:51.754738 [-4] AVG Duty = 4922%(X100)
2315 12:19:51.754819
2316 12:19:51.754898 ==DQS 1 ==
2317 12:19:51.754978 Final DQS duty delay cell = 0
2318 12:19:51.755057 [0] MAX Duty = 5125%(X100), DQS PI = 6
2319 12:19:51.755190 [0] MIN Duty = 5000%(X100), DQS PI = 0
2320 12:19:51.755251 [0] AVG Duty = 5062%(X100)
2321 12:19:51.755307
2322 12:19:51.755361 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2323 12:19:51.755412
2324 12:19:51.755462 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2325 12:19:51.755512 [DutyScan_Calibration_Flow] ====Done====
2326 12:19:51.755562
2327 12:19:51.755616 [DutyScan_Calibration_Flow] k_type=3
2328 12:19:51.755666
2329 12:19:51.755718 ==DQM 0 ==
2330 12:19:51.755769 Final DQM duty delay cell = 0
2331 12:19:51.755819 [0] MAX Duty = 5125%(X100), DQS PI = 20
2332 12:19:51.755870 [0] MIN Duty = 4844%(X100), DQS PI = 52
2333 12:19:51.755923 [0] AVG Duty = 4984%(X100)
2334 12:19:51.755974
2335 12:19:51.756023 ==DQM 1 ==
2336 12:19:51.756073 Final DQM duty delay cell = 0
2337 12:19:51.756126 [0] MAX Duty = 4969%(X100), DQS PI = 2
2338 12:19:51.756179 [0] MIN Duty = 4907%(X100), DQS PI = 12
2339 12:19:51.756232 [0] AVG Duty = 4938%(X100)
2340 12:19:51.756281
2341 12:19:51.756331 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2342 12:19:51.756381
2343 12:19:51.756434 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2344 12:19:51.756485 [DutyScan_Calibration_Flow] ====Done====
2345 12:19:51.756535
2346 12:19:51.756585 [DutyScan_Calibration_Flow] k_type=2
2347 12:19:51.756635
2348 12:19:51.756685 ==DQ 0 ==
2349 12:19:51.756738 Final DQ duty delay cell = 0
2350 12:19:51.756791 [0] MAX Duty = 5125%(X100), DQS PI = 18
2351 12:19:51.756841 [0] MIN Duty = 4969%(X100), DQS PI = 52
2352 12:19:51.756891 [0] AVG Duty = 5047%(X100)
2353 12:19:51.756941
2354 12:19:51.756993 ==DQ 1 ==
2355 12:19:51.757050 Final DQ duty delay cell = 0
2356 12:19:51.757102 [0] MAX Duty = 5156%(X100), DQS PI = 4
2357 12:19:51.757173 [0] MIN Duty = 4938%(X100), DQS PI = 14
2358 12:19:51.757229 [0] AVG Duty = 5047%(X100)
2359 12:19:51.757295
2360 12:19:51.757464 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2361 12:19:51.757547
2362 12:19:51.757626 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2363 12:19:51.757706 [DutyScan_Calibration_Flow] ====Done====
2364 12:19:51.757785 ==
2365 12:19:51.757868 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 12:19:51.757948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 12:19:51.758028 ==
2368 12:19:51.758110 [Duty_Offset_Calibration]
2369 12:19:51.758189 B0:0 B1:-1 CA:3
2370 12:19:51.758267
2371 12:19:51.758350 [DutyScan_Calibration_Flow] k_type=0
2372 12:19:51.758430
2373 12:19:51.758508 ==CLK 0==
2374 12:19:51.758590 Final CLK duty delay cell = -4
2375 12:19:51.758670 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2376 12:19:51.758750 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2377 12:19:51.758829 [-4] AVG Duty = 4938%(X100)
2378 12:19:51.758916
2379 12:19:51.758996 CH1 CLK Duty spec in!! Max-Min= 124%
2380 12:19:51.759082 [DutyScan_Calibration_Flow] ====Done====
2381 12:19:51.759171
2382 12:19:51.759225 [DutyScan_Calibration_Flow] k_type=1
2383 12:19:51.759285
2384 12:19:51.759373 ==DQS 0 ==
2385 12:19:51.759468 Final DQS duty delay cell = 0
2386 12:19:51.759550 [0] MAX Duty = 5187%(X100), DQS PI = 18
2387 12:19:51.759631 [0] MIN Duty = 4938%(X100), DQS PI = 38
2388 12:19:51.759713 [0] AVG Duty = 5062%(X100)
2389 12:19:51.759792
2390 12:19:51.759871 ==DQS 1 ==
2391 12:19:51.759954 Final DQS duty delay cell = -4
2392 12:19:51.760036 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2393 12:19:51.760116 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2394 12:19:51.760195 [-4] AVG Duty = 4953%(X100)
2395 12:19:51.760277
2396 12:19:51.760356 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2397 12:19:51.760435
2398 12:19:51.760517 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2399 12:19:51.760598 [DutyScan_Calibration_Flow] ====Done====
2400 12:19:51.760676
2401 12:19:51.760755 [DutyScan_Calibration_Flow] k_type=3
2402 12:19:51.760836
2403 12:19:51.760914 ==DQM 0 ==
2404 12:19:51.760994 Final DQM duty delay cell = 0
2405 12:19:51.761077 [0] MAX Duty = 5031%(X100), DQS PI = 28
2406 12:19:51.761158 [0] MIN Duty = 4813%(X100), DQS PI = 38
2407 12:19:51.761237 [0] AVG Duty = 4922%(X100)
2408 12:19:51.761319
2409 12:19:51.761397 ==DQM 1 ==
2410 12:19:51.761476 Final DQM duty delay cell = 0
2411 12:19:51.761557 [0] MAX Duty = 5000%(X100), DQS PI = 34
2412 12:19:51.761621 [0] MIN Duty = 4844%(X100), DQS PI = 0
2413 12:19:51.761693 [0] AVG Duty = 4922%(X100)
2414 12:19:51.761746
2415 12:19:51.761796 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2416 12:19:51.761851
2417 12:19:51.761902 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2418 12:19:51.761952 [DutyScan_Calibration_Flow] ====Done====
2419 12:19:51.762003
2420 12:19:51.762052 [DutyScan_Calibration_Flow] k_type=2
2421 12:19:51.762102
2422 12:19:51.762154 ==DQ 0 ==
2423 12:19:51.762207 Final DQ duty delay cell = -4
2424 12:19:51.762258 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2425 12:19:51.762309 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2426 12:19:51.762359 [-4] AVG Duty = 4937%(X100)
2427 12:19:51.762412
2428 12:19:51.762462 ==DQ 1 ==
2429 12:19:51.762513 Final DQ duty delay cell = 0
2430 12:19:51.762563 [0] MAX Duty = 5031%(X100), DQS PI = 34
2431 12:19:51.762613 [0] MIN Duty = 4844%(X100), DQS PI = 0
2432 12:19:51.762667 [0] AVG Duty = 4937%(X100)
2433 12:19:51.762719
2434 12:19:51.762768 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2435 12:19:51.762819
2436 12:19:51.762869 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2437 12:19:51.762927 [DutyScan_Calibration_Flow] ====Done====
2438 12:19:51.763008 nWR fixed to 30
2439 12:19:51.763098 [ModeRegInit_LP4] CH0 RK0
2440 12:19:51.763153 [ModeRegInit_LP4] CH0 RK1
2441 12:19:51.763207 [ModeRegInit_LP4] CH1 RK0
2442 12:19:51.763259 [ModeRegInit_LP4] CH1 RK1
2443 12:19:51.763507 match AC timing 7
2444 12:19:51.763564 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 12:19:51.763616 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 12:19:51.763667 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 12:19:51.763717 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 12:19:51.763771 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 12:19:51.763824 ==
2450 12:19:51.763874 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 12:19:51.763925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 12:19:51.763976 ==
2453 12:19:51.764029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 12:19:51.764080 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2455 12:19:51.764131 [CA 0] Center 39 (9~70) winsize 62
2456 12:19:51.764182 [CA 1] Center 39 (9~70) winsize 62
2457 12:19:51.764232 [CA 2] Center 35 (5~66) winsize 62
2458 12:19:51.764282 [CA 3] Center 35 (5~66) winsize 62
2459 12:19:51.764336 [CA 4] Center 33 (3~64) winsize 62
2460 12:19:51.764388 [CA 5] Center 33 (3~63) winsize 61
2461 12:19:51.764437
2462 12:19:51.764487 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2463 12:19:51.764538
2464 12:19:51.764591 [CATrainingPosCal] consider 1 rank data
2465 12:19:51.764642 u2DelayCellTimex100 = 270/100 ps
2466 12:19:51.764691 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2467 12:19:51.764742 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2468 12:19:51.764792 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2469 12:19:51.764844 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2470 12:19:51.764894 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2471 12:19:51.764946 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2472 12:19:51.764996
2473 12:19:51.765046 CA PerBit enable=1, Macro0, CA PI delay=33
2474 12:19:51.765096
2475 12:19:51.765149 [CBTSetCACLKResult] CA Dly = 33
2476 12:19:51.765199 CS Dly: 7 (0~38)
2477 12:19:51.765248 ==
2478 12:19:51.765298 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 12:19:51.765348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 12:19:51.765398 ==
2481 12:19:51.765451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 12:19:51.765501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 12:19:51.765554 [CA 0] Center 39 (9~70) winsize 62
2484 12:19:51.765614 [CA 1] Center 39 (9~70) winsize 62
2485 12:19:51.765672 [CA 2] Center 35 (5~66) winsize 62
2486 12:19:51.765738 [CA 3] Center 35 (5~66) winsize 62
2487 12:19:51.765793 [CA 4] Center 34 (3~65) winsize 63
2488 12:19:51.765844 [CA 5] Center 33 (3~63) winsize 61
2489 12:19:51.765894
2490 12:19:51.765944 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 12:19:51.765997
2492 12:19:51.766049 [CATrainingPosCal] consider 2 rank data
2493 12:19:51.766099 u2DelayCellTimex100 = 270/100 ps
2494 12:19:51.766149 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2495 12:19:51.766199 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2496 12:19:51.766252 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 12:19:51.766302 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 12:19:51.766352 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2499 12:19:51.766402 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 12:19:51.766452
2501 12:19:51.766504 CA PerBit enable=1, Macro0, CA PI delay=33
2502 12:19:51.766558
2503 12:19:51.766607 [CBTSetCACLKResult] CA Dly = 33
2504 12:19:51.766657 CS Dly: 8 (0~41)
2505 12:19:51.766707
2506 12:19:51.766759 ----->DramcWriteLeveling(PI) begin...
2507 12:19:51.766811 ==
2508 12:19:51.766861 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 12:19:51.766912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 12:19:51.766962 ==
2511 12:19:51.767014 Write leveling (Byte 0): 31 => 31
2512 12:19:51.767065 Write leveling (Byte 1): 27 => 27
2513 12:19:51.767128 DramcWriteLeveling(PI) end<-----
2514 12:19:51.767178
2515 12:19:51.767228 ==
2516 12:19:51.767279 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 12:19:51.767333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 12:19:51.767384 ==
2519 12:19:51.767435 [Gating] SW mode calibration
2520 12:19:51.767485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 12:19:51.767537 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 12:19:51.767590 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2523 12:19:51.767640 0 15 4 | B1->B0 | 2d2c 3434 | 1 1 | (0 0) (1 1)
2524 12:19:51.767692 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 12:19:51.767743 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 12:19:51.767793 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 12:19:51.767843 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 12:19:51.767896 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2529 12:19:51.767946 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2530 12:19:51.767996 1 0 0 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
2531 12:19:51.768046 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2532 12:19:51.768096 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 12:19:51.768149 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 12:19:51.768202 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 12:19:51.768252 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 12:19:51.768302 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2537 12:19:51.768353 1 0 28 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
2538 12:19:51.768403 1 1 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2539 12:19:51.768457 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2540 12:19:51.768507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 12:19:51.768557 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 12:19:51.768608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 12:19:51.768658 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 12:19:51.768711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 12:19:51.768762 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 12:19:51.768814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 12:19:51.768865 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:19:51.768914 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:19:51.768964 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:19:51.769017 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:19:51.769272 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:19:51.769331 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:19:51.769383 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:19:51.769435 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:19:51.769486 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:19:51.769539 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:19:51.769590 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:19:51.769641 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:19:51.769691 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:19:51.769741 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:19:51.769791 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 12:19:51.769844 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2563 12:19:51.769896 Total UI for P1: 0, mck2ui 16
2564 12:19:51.769947 best dqsien dly found for B0: ( 1, 3, 28)
2565 12:19:51.769997 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 12:19:51.770048 Total UI for P1: 0, mck2ui 16
2567 12:19:51.770099 best dqsien dly found for B1: ( 1, 4, 0)
2568 12:19:51.770160 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2569 12:19:51.770230 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2570 12:19:51.770284
2571 12:19:51.770334 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2572 12:19:51.770387 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2573 12:19:51.770437 [Gating] SW calibration Done
2574 12:19:51.770491 ==
2575 12:19:51.770541 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 12:19:51.770592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 12:19:51.770643 ==
2578 12:19:51.770696 RX Vref Scan: 0
2579 12:19:51.770747
2580 12:19:51.770797 RX Vref 0 -> 0, step: 1
2581 12:19:51.770847
2582 12:19:51.770897 RX Delay -40 -> 252, step: 8
2583 12:19:51.770947 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2584 12:19:51.771001 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2585 12:19:51.771053 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2586 12:19:51.771156 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2587 12:19:51.771209 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2588 12:19:51.771263 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2589 12:19:51.771314 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2590 12:19:51.771364 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2591 12:19:51.771414 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2592 12:19:51.771464 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2593 12:19:51.771517 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2594 12:19:51.771569 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2595 12:19:51.771620 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2596 12:19:51.771670 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2597 12:19:51.771720 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2598 12:19:51.771773 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2599 12:19:51.771823 ==
2600 12:19:51.771873 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 12:19:51.771923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 12:19:51.771974 ==
2603 12:19:51.772023 DQS Delay:
2604 12:19:51.772076 DQS0 = 0, DQS1 = 0
2605 12:19:51.772128 DQM Delay:
2606 12:19:51.772178 DQM0 = 120, DQM1 = 107
2607 12:19:51.772228 DQ Delay:
2608 12:19:51.772288 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2609 12:19:51.772343 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2610 12:19:51.772394 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2611 12:19:51.772445 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2612 12:19:51.772495
2613 12:19:51.772545
2614 12:19:51.772599 ==
2615 12:19:51.772650 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 12:19:51.772702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 12:19:51.772753 ==
2618 12:19:51.772804
2619 12:19:51.772853
2620 12:19:51.772906 TX Vref Scan disable
2621 12:19:51.772956 == TX Byte 0 ==
2622 12:19:51.773006 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2623 12:19:51.773057 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2624 12:19:51.773107 == TX Byte 1 ==
2625 12:19:51.773160 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2626 12:19:51.773212 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2627 12:19:51.773263 ==
2628 12:19:51.773313 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 12:19:51.773363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 12:19:51.773414 ==
2631 12:19:51.773467 TX Vref=22, minBit 1, minWin=25, winSum=411
2632 12:19:51.773517 TX Vref=24, minBit 3, minWin=25, winSum=418
2633 12:19:51.773568 TX Vref=26, minBit 1, minWin=26, winSum=427
2634 12:19:51.773618 TX Vref=28, minBit 5, minWin=26, winSum=427
2635 12:19:51.773668 TX Vref=30, minBit 8, minWin=26, winSum=428
2636 12:19:51.773722 TX Vref=32, minBit 5, minWin=26, winSum=425
2637 12:19:51.773774 [TxChooseVref] Worse bit 8, Min win 26, Win sum 428, Final Vref 30
2638 12:19:51.773824
2639 12:19:51.773873 Final TX Range 1 Vref 30
2640 12:19:51.773923
2641 12:19:51.773976 ==
2642 12:19:51.774026 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 12:19:51.774075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 12:19:51.774126 ==
2645 12:19:51.774175
2646 12:19:51.774225
2647 12:19:51.774279 TX Vref Scan disable
2648 12:19:51.774329 == TX Byte 0 ==
2649 12:19:51.774379 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2650 12:19:51.774430 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2651 12:19:51.774480 == TX Byte 1 ==
2652 12:19:51.774532 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2653 12:19:51.774583 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2654 12:19:51.774633
2655 12:19:51.774683 [DATLAT]
2656 12:19:51.774734 Freq=1200, CH0 RK0
2657 12:19:51.774786
2658 12:19:51.774836 DATLAT Default: 0xd
2659 12:19:51.774888 0, 0xFFFF, sum = 0
2660 12:19:51.774945 1, 0xFFFF, sum = 0
2661 12:19:51.775035 2, 0xFFFF, sum = 0
2662 12:19:51.775130 3, 0xFFFF, sum = 0
2663 12:19:51.775216 4, 0xFFFF, sum = 0
2664 12:19:51.775271 5, 0xFFFF, sum = 0
2665 12:19:51.775326 6, 0xFFFF, sum = 0
2666 12:19:51.775380 7, 0xFFFF, sum = 0
2667 12:19:51.775431 8, 0xFFFF, sum = 0
2668 12:19:51.775482 9, 0xFFFF, sum = 0
2669 12:19:51.775533 10, 0xFFFF, sum = 0
2670 12:19:51.775584 11, 0xFFFF, sum = 0
2671 12:19:51.775638 12, 0x0, sum = 1
2672 12:19:51.775689 13, 0x0, sum = 2
2673 12:19:51.775740 14, 0x0, sum = 3
2674 12:19:51.775791 15, 0x0, sum = 4
2675 12:19:51.775851 best_step = 13
2676 12:19:51.775902
2677 12:19:51.775955 ==
2678 12:19:51.776008 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 12:19:51.776058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 12:19:51.776108 ==
2681 12:19:51.776158 RX Vref Scan: 1
2682 12:19:51.776208
2683 12:19:51.776261 Set Vref Range= 32 -> 127
2684 12:19:51.776311
2685 12:19:51.776361 RX Vref 32 -> 127, step: 1
2686 12:19:51.776411
2687 12:19:51.776461 RX Delay -21 -> 252, step: 4
2688 12:19:51.776511
2689 12:19:51.776561 Set Vref, RX VrefLevel [Byte0]: 32
2690 12:19:51.776615 [Byte1]: 32
2691 12:19:51.776667
2692 12:19:51.776910 Set Vref, RX VrefLevel [Byte0]: 33
2693 12:19:51.776967 [Byte1]: 33
2694 12:19:51.777019
2695 12:19:51.777069 Set Vref, RX VrefLevel [Byte0]: 34
2696 12:19:51.777120 [Byte1]: 34
2697 12:19:51.777170
2698 12:19:51.777223 Set Vref, RX VrefLevel [Byte0]: 35
2699 12:19:51.777276 [Byte1]: 35
2700 12:19:51.777327
2701 12:19:51.777378 Set Vref, RX VrefLevel [Byte0]: 36
2702 12:19:51.777428 [Byte1]: 36
2703 12:19:51.777478
2704 12:19:51.777530 Set Vref, RX VrefLevel [Byte0]: 37
2705 12:19:51.777580 [Byte1]: 37
2706 12:19:51.777630
2707 12:19:51.777680 Set Vref, RX VrefLevel [Byte0]: 38
2708 12:19:51.777730 [Byte1]: 38
2709 12:19:51.777783
2710 12:19:51.777833 Set Vref, RX VrefLevel [Byte0]: 39
2711 12:19:51.777885 [Byte1]: 39
2712 12:19:51.777935
2713 12:19:51.777985 Set Vref, RX VrefLevel [Byte0]: 40
2714 12:19:51.778035 [Byte1]: 40
2715 12:19:51.778087
2716 12:19:51.778136 Set Vref, RX VrefLevel [Byte0]: 41
2717 12:19:51.778187 [Byte1]: 41
2718 12:19:51.778236
2719 12:19:51.778286 Set Vref, RX VrefLevel [Byte0]: 42
2720 12:19:51.778335 [Byte1]: 42
2721 12:19:51.778388
2722 12:19:51.778439 Set Vref, RX VrefLevel [Byte0]: 43
2723 12:19:51.778490 [Byte1]: 43
2724 12:19:51.778539
2725 12:19:51.778589 Set Vref, RX VrefLevel [Byte0]: 44
2726 12:19:51.778639 [Byte1]: 44
2727 12:19:51.778691
2728 12:19:51.778741 Set Vref, RX VrefLevel [Byte0]: 45
2729 12:19:51.778790 [Byte1]: 45
2730 12:19:51.778840
2731 12:19:51.778890 Set Vref, RX VrefLevel [Byte0]: 46
2732 12:19:51.778939 [Byte1]: 46
2733 12:19:51.778989
2734 12:19:51.779049 Set Vref, RX VrefLevel [Byte0]: 47
2735 12:19:51.779156 [Byte1]: 47
2736 12:19:51.779222
2737 12:19:51.779280 Set Vref, RX VrefLevel [Byte0]: 48
2738 12:19:51.779331 [Byte1]: 48
2739 12:19:51.779382
2740 12:19:51.779432 Set Vref, RX VrefLevel [Byte0]: 49
2741 12:19:51.779487 [Byte1]: 49
2742 12:19:51.779547
2743 12:19:51.779601 Set Vref, RX VrefLevel [Byte0]: 50
2744 12:19:51.779654 [Byte1]: 50
2745 12:19:51.779704
2746 12:19:51.779754 Set Vref, RX VrefLevel [Byte0]: 51
2747 12:19:51.779804 [Byte1]: 51
2748 12:19:51.779857
2749 12:19:51.779906 Set Vref, RX VrefLevel [Byte0]: 52
2750 12:19:51.779957 [Byte1]: 52
2751 12:19:51.780006
2752 12:19:51.780056 Set Vref, RX VrefLevel [Byte0]: 53
2753 12:19:51.780106 [Byte1]: 53
2754 12:19:51.780159
2755 12:19:51.780209 Set Vref, RX VrefLevel [Byte0]: 54
2756 12:19:51.780261 [Byte1]: 54
2757 12:19:51.780312
2758 12:19:51.780362 Set Vref, RX VrefLevel [Byte0]: 55
2759 12:19:51.780412 [Byte1]: 55
2760 12:19:51.780464
2761 12:19:51.780514 Set Vref, RX VrefLevel [Byte0]: 56
2762 12:19:51.780564 [Byte1]: 56
2763 12:19:51.780614
2764 12:19:51.780664 Set Vref, RX VrefLevel [Byte0]: 57
2765 12:19:51.780714 [Byte1]: 57
2766 12:19:51.780764
2767 12:19:51.780817 Set Vref, RX VrefLevel [Byte0]: 58
2768 12:19:51.780869 [Byte1]: 58
2769 12:19:51.780919
2770 12:19:51.780968 Set Vref, RX VrefLevel [Byte0]: 59
2771 12:19:51.781019 [Byte1]: 59
2772 12:19:51.781068
2773 12:19:51.781121 Set Vref, RX VrefLevel [Byte0]: 60
2774 12:19:51.781171 [Byte1]: 60
2775 12:19:51.781220
2776 12:19:51.781270 Set Vref, RX VrefLevel [Byte0]: 61
2777 12:19:51.781322 [Byte1]: 61
2778 12:19:51.781372
2779 12:19:51.781422 Set Vref, RX VrefLevel [Byte0]: 62
2780 12:19:51.781479 [Byte1]: 62
2781 12:19:51.781538
2782 12:19:51.781595 Set Vref, RX VrefLevel [Byte0]: 63
2783 12:19:51.781645 [Byte1]: 63
2784 12:19:51.781697
2785 12:19:51.781749 Set Vref, RX VrefLevel [Byte0]: 64
2786 12:19:51.781800 [Byte1]: 64
2787 12:19:51.781850
2788 12:19:51.781900 Set Vref, RX VrefLevel [Byte0]: 65
2789 12:19:51.781950 [Byte1]: 65
2790 12:19:51.781999
2791 12:19:51.782059 Set Vref, RX VrefLevel [Byte0]: 66
2792 12:19:51.782111 [Byte1]: 66
2793 12:19:51.782163
2794 12:19:51.782213 Set Vref, RX VrefLevel [Byte0]: 67
2795 12:19:51.782263 [Byte1]: 67
2796 12:19:51.782312
2797 12:19:51.782364 Set Vref, RX VrefLevel [Byte0]: 68
2798 12:19:51.782414 [Byte1]: 68
2799 12:19:51.782464
2800 12:19:51.782514 Set Vref, RX VrefLevel [Byte0]: 69
2801 12:19:51.782563 [Byte1]: 69
2802 12:19:51.782612
2803 12:19:51.782662 Final RX Vref Byte 0 = 59 to rank0
2804 12:19:51.782715 Final RX Vref Byte 1 = 49 to rank0
2805 12:19:51.782767 Final RX Vref Byte 0 = 59 to rank1
2806 12:19:51.782817 Final RX Vref Byte 1 = 49 to rank1==
2807 12:19:51.782867 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 12:19:51.782917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 12:19:51.782967 ==
2810 12:19:51.783020 DQS Delay:
2811 12:19:51.783069 DQS0 = 0, DQS1 = 0
2812 12:19:51.783169 DQM Delay:
2813 12:19:51.783219 DQM0 = 119, DQM1 = 106
2814 12:19:51.783268 DQ Delay:
2815 12:19:51.783322 DQ0 =118, DQ1 =116, DQ2 =116, DQ3 =116
2816 12:19:51.783375 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2817 12:19:51.783425 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =100
2818 12:19:51.783476 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =114
2819 12:19:51.783525
2820 12:19:51.783575
2821 12:19:51.783627 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcf7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 411 ps
2822 12:19:51.783678 CH0 RK0: MR19=303, MR18=FCF7
2823 12:19:51.783728 CH0_RK0: MR19=0x303, MR18=0xFCF7, DQSOSC=411, MR23=63, INC=38, DEC=25
2824 12:19:51.783779
2825 12:19:51.783829 ----->DramcWriteLeveling(PI) begin...
2826 12:19:51.783880 ==
2827 12:19:51.783933 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 12:19:51.783985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 12:19:51.784036 ==
2830 12:19:51.784087 Write leveling (Byte 0): 33 => 33
2831 12:19:51.784137 Write leveling (Byte 1): 27 => 27
2832 12:19:51.784186 DramcWriteLeveling(PI) end<-----
2833 12:19:51.784235
2834 12:19:51.784288 ==
2835 12:19:51.784339 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 12:19:51.784389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 12:19:51.784439 ==
2838 12:19:51.784497 [Gating] SW mode calibration
2839 12:19:51.784551 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 12:19:51.784625 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 12:19:51.784677 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2842 12:19:51.784729 0 15 4 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
2843 12:19:51.784972 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 12:19:51.785029 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 12:19:51.785080 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 12:19:51.785134 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 12:19:51.785187 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2848 12:19:51.785239 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
2849 12:19:51.785290 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2850 12:19:51.785341 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 12:19:51.785391 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 12:19:51.785445 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 12:19:51.785495 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 12:19:51.785546 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 12:19:51.785597 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2856 12:19:51.785647 1 0 28 | B1->B0 | 2727 4141 | 0 0 | (0 0) (0 0)
2857 12:19:51.785697 1 1 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
2858 12:19:51.785760 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 12:19:51.785813 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 12:19:51.785863 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 12:19:51.785914 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 12:19:51.785965 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2863 12:19:51.786015 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2864 12:19:51.786069 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2865 12:19:51.786119 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2866 12:19:51.786169 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:19:51.786219 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:19:51.786269 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:19:51.786321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:19:51.786372 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:19:51.786424 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:19:51.786474 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:19:51.786524 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:19:51.786574 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:19:51.786627 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:19:51.786677 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:19:51.786728 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:19:51.786778 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:19:51.786828 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2880 12:19:51.786878 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2881 12:19:51.786930 Total UI for P1: 0, mck2ui 16
2882 12:19:51.786983 best dqsien dly found for B0: ( 1, 3, 24)
2883 12:19:51.787033 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2884 12:19:51.787091 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 12:19:51.787144 Total UI for P1: 0, mck2ui 16
2886 12:19:51.787195 best dqsien dly found for B1: ( 1, 3, 30)
2887 12:19:51.787249 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2888 12:19:51.787299 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2889 12:19:51.787349
2890 12:19:51.787399 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2891 12:19:51.787450 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2892 12:19:51.787503 [Gating] SW calibration Done
2893 12:19:51.787553 ==
2894 12:19:51.787605 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 12:19:51.787655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 12:19:51.787706 ==
2897 12:19:51.787757 RX Vref Scan: 0
2898 12:19:51.787809
2899 12:19:51.787859 RX Vref 0 -> 0, step: 1
2900 12:19:51.787909
2901 12:19:51.787959 RX Delay -40 -> 252, step: 8
2902 12:19:51.788009 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2903 12:19:51.788059 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2904 12:19:51.788112 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2905 12:19:51.788164 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2906 12:19:51.788214 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2907 12:19:51.788264 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2908 12:19:51.788314 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
2909 12:19:51.788364 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2910 12:19:51.788417 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2911 12:19:51.788467 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2912 12:19:51.788517 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2913 12:19:51.788567 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2914 12:19:51.788617 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2915 12:19:51.788667 iDelay=200, Bit 13, Center 111 (48 ~ 175) 128
2916 12:19:51.788720 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2917 12:19:51.788772 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2918 12:19:51.788822 ==
2919 12:19:51.788872 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 12:19:51.788923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 12:19:51.788989 ==
2922 12:19:51.789045 DQS Delay:
2923 12:19:51.789114 DQS0 = 0, DQS1 = 0
2924 12:19:51.789166 DQM Delay:
2925 12:19:51.789215 DQM0 = 119, DQM1 = 106
2926 12:19:51.789268 DQ Delay:
2927 12:19:51.789319 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2928 12:19:51.789371 DQ4 =123, DQ5 =111, DQ6 =131, DQ7 =123
2929 12:19:51.789421 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
2930 12:19:51.789471 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =115
2931 12:19:51.789521
2932 12:19:51.789573
2933 12:19:51.789623 ==
2934 12:19:51.789672 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 12:19:51.789723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 12:19:52.737989 ==
2937 12:19:52.738122
2938 12:19:52.738187
2939 12:19:52.738253 TX Vref Scan disable
2940 12:19:52.738312 == TX Byte 0 ==
2941 12:19:52.738368 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2942 12:19:52.738424 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2943 12:19:52.738484 == TX Byte 1 ==
2944 12:19:52.738539 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2945 12:19:52.738593 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2946 12:19:52.738646 ==
2947 12:19:52.738699 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 12:19:52.738759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 12:19:52.738813 ==
2950 12:19:52.739079 TX Vref=22, minBit 14, minWin=25, winSum=421
2951 12:19:52.739184 TX Vref=24, minBit 1, minWin=26, winSum=423
2952 12:19:52.739245 TX Vref=26, minBit 3, minWin=26, winSum=428
2953 12:19:52.739299 TX Vref=28, minBit 4, minWin=26, winSum=430
2954 12:19:52.739352 TX Vref=30, minBit 4, minWin=26, winSum=430
2955 12:19:52.739404 TX Vref=32, minBit 13, minWin=25, winSum=426
2956 12:19:52.739462 [TxChooseVref] Worse bit 4, Min win 26, Win sum 430, Final Vref 28
2957 12:19:52.739516
2958 12:19:52.739567 Final TX Range 1 Vref 28
2959 12:19:52.739619
2960 12:19:52.739677 ==
2961 12:19:52.739747 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 12:19:52.739801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 12:19:52.739853 ==
2964 12:19:52.739904
2965 12:19:52.739961
2966 12:19:52.740013 TX Vref Scan disable
2967 12:19:52.740064 == TX Byte 0 ==
2968 12:19:52.740115 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2969 12:19:52.740168 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2970 12:19:52.740227 == TX Byte 1 ==
2971 12:19:52.740279 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2972 12:19:52.740331 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2973 12:19:52.740383
2974 12:19:52.740434 [DATLAT]
2975 12:19:52.740492 Freq=1200, CH0 RK1
2976 12:19:52.740543
2977 12:19:52.740595 DATLAT Default: 0xd
2978 12:19:52.740646 0, 0xFFFF, sum = 0
2979 12:19:52.740704 1, 0xFFFF, sum = 0
2980 12:19:52.740758 2, 0xFFFF, sum = 0
2981 12:19:52.740810 3, 0xFFFF, sum = 0
2982 12:19:52.740863 4, 0xFFFF, sum = 0
2983 12:19:52.740915 5, 0xFFFF, sum = 0
2984 12:19:52.740974 6, 0xFFFF, sum = 0
2985 12:19:52.741026 7, 0xFFFF, sum = 0
2986 12:19:52.741078 8, 0xFFFF, sum = 0
2987 12:19:52.741130 9, 0xFFFF, sum = 0
2988 12:19:52.741186 10, 0xFFFF, sum = 0
2989 12:19:52.741239 11, 0xFFFF, sum = 0
2990 12:19:52.741291 12, 0x0, sum = 1
2991 12:19:52.741343 13, 0x0, sum = 2
2992 12:19:52.741395 14, 0x0, sum = 3
2993 12:19:52.741453 15, 0x0, sum = 4
2994 12:19:52.741505 best_step = 13
2995 12:19:52.741556
2996 12:19:52.741607 ==
2997 12:19:52.741659 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 12:19:52.741716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 12:19:52.741768 ==
3000 12:19:52.741819 RX Vref Scan: 0
3001 12:19:52.741869
3002 12:19:52.741925 RX Vref 0 -> 0, step: 1
3003 12:19:52.741977
3004 12:19:52.742028 RX Delay -21 -> 252, step: 4
3005 12:19:52.742079 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3006 12:19:52.742131 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3007 12:19:52.742188 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3008 12:19:52.742240 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3009 12:19:52.742291 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
3010 12:19:52.742342 iDelay=195, Bit 5, Center 112 (51 ~ 174) 124
3011 12:19:52.742399 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3012 12:19:52.742453 iDelay=195, Bit 7, Center 122 (59 ~ 186) 128
3013 12:19:52.742503 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3014 12:19:52.742555 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3015 12:19:52.742606 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3016 12:19:52.742663 iDelay=195, Bit 11, Center 98 (35 ~ 162) 128
3017 12:19:52.742715 iDelay=195, Bit 12, Center 112 (51 ~ 174) 124
3018 12:19:52.742766 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3019 12:19:52.742817 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3020 12:19:52.742868 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3021 12:19:52.742935 ==
3022 12:19:52.743021 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 12:19:52.743145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 12:19:52.743202 ==
3025 12:19:52.743254 DQS Delay:
3026 12:19:52.743306 DQS0 = 0, DQS1 = 0
3027 12:19:52.743357 DQM Delay:
3028 12:19:52.743415 DQM0 = 118, DQM1 = 106
3029 12:19:52.743467 DQ Delay:
3030 12:19:52.743517 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =114
3031 12:19:52.743568 DQ4 =122, DQ5 =112, DQ6 =128, DQ7 =122
3032 12:19:52.743624 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3033 12:19:52.743677 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3034 12:19:52.743728
3035 12:19:52.743778
3036 12:19:52.743830 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5f3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
3037 12:19:52.743887 CH0 RK1: MR19=303, MR18=F5F3
3038 12:19:52.743939 CH0_RK1: MR19=0x303, MR18=0xF5F3, DQSOSC=414, MR23=63, INC=38, DEC=25
3039 12:19:52.743991 [RxdqsGatingPostProcess] freq 1200
3040 12:19:52.744041 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3041 12:19:52.744092 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 12:19:52.744149 best DQS1 dly(2T, 0.5T) = (0, 12)
3043 12:19:52.744201 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 12:19:52.744252 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3045 12:19:52.744303 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 12:19:52.744355 best DQS1 dly(2T, 0.5T) = (0, 11)
3047 12:19:52.744413 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 12:19:52.744464 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3049 12:19:52.744515 Pre-setting of DQS Precalculation
3050 12:19:52.744567 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3051 12:19:52.744623 ==
3052 12:19:52.744675 Dram Type= 6, Freq= 0, CH_1, rank 0
3053 12:19:52.744726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 12:19:52.744778 ==
3055 12:19:52.744830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3056 12:19:52.744888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3057 12:19:52.744940 [CA 0] Center 38 (8~68) winsize 61
3058 12:19:52.744992 [CA 1] Center 37 (7~68) winsize 62
3059 12:19:52.745043 [CA 2] Center 35 (5~65) winsize 61
3060 12:19:52.745095 [CA 3] Center 34 (4~64) winsize 61
3061 12:19:52.745152 [CA 4] Center 35 (5~65) winsize 61
3062 12:19:52.745203 [CA 5] Center 34 (4~64) winsize 61
3063 12:19:52.745255
3064 12:19:52.745306 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3065 12:19:52.745363
3066 12:19:52.745415 [CATrainingPosCal] consider 1 rank data
3067 12:19:52.745467 u2DelayCellTimex100 = 270/100 ps
3068 12:19:52.745519 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3069 12:19:52.745570 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3070 12:19:52.745628 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3071 12:19:52.745679 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3072 12:19:52.745731 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3073 12:19:52.745782 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3074 12:19:52.745834
3075 12:19:52.745890 CA PerBit enable=1, Macro0, CA PI delay=34
3076 12:19:52.745942
3077 12:19:52.745994 [CBTSetCACLKResult] CA Dly = 34
3078 12:19:52.746045 CS Dly: 5 (0~36)
3079 12:19:52.746102 ==
3080 12:19:52.746154 Dram Type= 6, Freq= 0, CH_1, rank 1
3081 12:19:52.746220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 12:19:52.746276 ==
3083 12:19:52.746530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3084 12:19:52.746698 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3085 12:19:52.746751 [CA 0] Center 37 (7~68) winsize 62
3086 12:19:52.746804 [CA 1] Center 38 (8~68) winsize 61
3087 12:19:52.746856 [CA 2] Center 35 (5~65) winsize 61
3088 12:19:52.746915 [CA 3] Center 34 (4~64) winsize 61
3089 12:19:52.746966 [CA 4] Center 34 (4~64) winsize 61
3090 12:19:52.747017 [CA 5] Center 33 (3~63) winsize 61
3091 12:19:52.747069
3092 12:19:52.747169 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3093 12:19:52.747222
3094 12:19:52.747273 [CATrainingPosCal] consider 2 rank data
3095 12:19:52.747325 u2DelayCellTimex100 = 270/100 ps
3096 12:19:52.747381 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3097 12:19:52.747435 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3098 12:19:52.747486 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3099 12:19:52.747538 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 12:19:52.747589 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3101 12:19:52.747647 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3102 12:19:52.747699
3103 12:19:52.747750 CA PerBit enable=1, Macro0, CA PI delay=33
3104 12:19:52.747802
3105 12:19:52.747853 [CBTSetCACLKResult] CA Dly = 33
3106 12:19:52.747911 CS Dly: 6 (0~39)
3107 12:19:52.747962
3108 12:19:52.748013 ----->DramcWriteLeveling(PI) begin...
3109 12:19:52.748066 ==
3110 12:19:52.748123 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 12:19:52.748175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 12:19:52.748227 ==
3113 12:19:52.748278 Write leveling (Byte 0): 27 => 27
3114 12:19:52.748330 Write leveling (Byte 1): 29 => 29
3115 12:19:52.748388 DramcWriteLeveling(PI) end<-----
3116 12:19:52.748439
3117 12:19:52.748490 ==
3118 12:19:52.748542 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 12:19:52.748598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 12:19:52.748651 ==
3121 12:19:52.748702 [Gating] SW mode calibration
3122 12:19:52.748777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3123 12:19:52.748871 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3124 12:19:52.748929 0 15 0 | B1->B0 | 3131 3434 | 1 0 | (1 1) (0 0)
3125 12:19:52.749003 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 12:19:52.749058 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 12:19:52.749118 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 12:19:52.749171 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 12:19:52.749224 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 12:19:52.749277 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
3131 12:19:52.749328 0 15 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (1 0)
3132 12:19:52.749386 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 12:19:52.749438 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 12:19:52.749490 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 12:19:52.749542 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 12:19:52.749599 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 12:19:52.749651 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 12:19:52.749703 1 0 24 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
3139 12:19:52.749754 1 0 28 | B1->B0 | 3636 4545 | 1 0 | (0 0) (0 0)
3140 12:19:52.749807 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 12:19:52.749864 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 12:19:52.749916 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 12:19:52.749968 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 12:19:52.750019 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 12:19:52.750071 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 12:19:52.750129 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 12:19:52.750180 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3148 12:19:52.750232 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3149 12:19:52.750284 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:19:52.750340 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:19:52.750393 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:19:52.750445 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:19:52.750496 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:19:52.750548 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:19:52.750606 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:19:52.750658 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:19:52.750710 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:19:52.750762 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:19:52.750818 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:19:52.750870 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:19:52.750922 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 12:19:52.750974 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 12:19:52.751025 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3164 12:19:52.751115 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 12:19:52.751183 Total UI for P1: 0, mck2ui 16
3166 12:19:52.751235 best dqsien dly found for B0: ( 1, 3, 28)
3167 12:19:52.751287 Total UI for P1: 0, mck2ui 16
3168 12:19:52.751346 best dqsien dly found for B1: ( 1, 3, 28)
3169 12:19:52.751398 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3170 12:19:52.751450 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3171 12:19:52.751502
3172 12:19:52.751559 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3173 12:19:52.751612 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3174 12:19:52.751664 [Gating] SW calibration Done
3175 12:19:52.751716 ==
3176 12:19:52.751768 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 12:19:52.751825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 12:19:52.751878 ==
3179 12:19:52.751929 RX Vref Scan: 0
3180 12:19:52.751980
3181 12:19:52.752035 RX Vref 0 -> 0, step: 1
3182 12:19:52.752087
3183 12:19:52.752139 RX Delay -40 -> 252, step: 8
3184 12:19:52.752191 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3185 12:19:52.752242 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3186 12:19:52.752299 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3187 12:19:52.752352 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3188 12:19:52.752598 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3189 12:19:52.752657 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3190 12:19:52.752710 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3191 12:19:52.752763 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3192 12:19:52.752823 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3193 12:19:52.752875 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3194 12:19:52.752927 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3195 12:19:52.752980 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3196 12:19:52.753037 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3197 12:19:52.753090 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3198 12:19:52.753158 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3199 12:19:52.753214 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3200 12:19:52.753272 ==
3201 12:19:52.753326 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 12:19:52.753377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 12:19:52.753430 ==
3204 12:19:52.753482 DQS Delay:
3205 12:19:52.753540 DQS0 = 0, DQS1 = 0
3206 12:19:52.753592 DQM Delay:
3207 12:19:52.753644 DQM0 = 115, DQM1 = 113
3208 12:19:52.753696 DQ Delay:
3209 12:19:52.753747 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3210 12:19:52.753808 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3211 12:19:52.753860 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3212 12:19:52.753912 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3213 12:19:52.753964
3214 12:19:52.754020
3215 12:19:52.754072 ==
3216 12:19:52.754123 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 12:19:52.754175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 12:19:52.754227 ==
3219 12:19:52.754284
3220 12:19:52.754336
3221 12:19:52.754386 TX Vref Scan disable
3222 12:19:52.754438 == TX Byte 0 ==
3223 12:19:52.754490 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3224 12:19:52.754549 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3225 12:19:52.754601 == TX Byte 1 ==
3226 12:19:52.754652 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3227 12:19:52.754704 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3228 12:19:52.754760 ==
3229 12:19:52.754813 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 12:19:52.754865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 12:19:52.754916 ==
3232 12:19:52.754968 TX Vref=22, minBit 1, minWin=25, winSum=410
3233 12:19:52.755025 TX Vref=24, minBit 7, minWin=25, winSum=417
3234 12:19:52.755110 TX Vref=26, minBit 1, minWin=26, winSum=421
3235 12:19:52.755222 TX Vref=28, minBit 1, minWin=26, winSum=423
3236 12:19:52.755291 TX Vref=30, minBit 4, minWin=26, winSum=427
3237 12:19:52.755345 TX Vref=32, minBit 10, minWin=25, winSum=423
3238 12:19:52.755398 [TxChooseVref] Worse bit 4, Min win 26, Win sum 427, Final Vref 30
3239 12:19:52.755450
3240 12:19:52.755509 Final TX Range 1 Vref 30
3241 12:19:52.755562
3242 12:19:52.755614 ==
3243 12:19:52.755665 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 12:19:52.755717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 12:19:52.755775 ==
3246 12:19:52.755827
3247 12:19:52.755882
3248 12:19:52.755948 TX Vref Scan disable
3249 12:19:52.756008 == TX Byte 0 ==
3250 12:19:52.756061 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3251 12:19:52.756113 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3252 12:19:52.756165 == TX Byte 1 ==
3253 12:19:52.756217 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3254 12:19:52.756276 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3255 12:19:52.756328
3256 12:19:52.756379 [DATLAT]
3257 12:19:52.756431 Freq=1200, CH1 RK0
3258 12:19:52.756488
3259 12:19:52.756539 DATLAT Default: 0xd
3260 12:19:52.756591 0, 0xFFFF, sum = 0
3261 12:19:52.756643 1, 0xFFFF, sum = 0
3262 12:19:52.756695 2, 0xFFFF, sum = 0
3263 12:19:52.756754 3, 0xFFFF, sum = 0
3264 12:19:52.756807 4, 0xFFFF, sum = 0
3265 12:19:52.756859 5, 0xFFFF, sum = 0
3266 12:19:52.756911 6, 0xFFFF, sum = 0
3267 12:19:52.756963 7, 0xFFFF, sum = 0
3268 12:19:52.757021 8, 0xFFFF, sum = 0
3269 12:19:52.757074 9, 0xFFFF, sum = 0
3270 12:19:52.757126 10, 0xFFFF, sum = 0
3271 12:19:52.757178 11, 0xFFFF, sum = 0
3272 12:19:52.757236 12, 0x0, sum = 1
3273 12:19:52.757289 13, 0x0, sum = 2
3274 12:19:52.757341 14, 0x0, sum = 3
3275 12:19:52.757393 15, 0x0, sum = 4
3276 12:19:52.757446 best_step = 13
3277 12:19:52.757503
3278 12:19:52.757555 ==
3279 12:19:52.757606 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 12:19:52.757658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 12:19:52.757710 ==
3282 12:19:52.757768 RX Vref Scan: 1
3283 12:19:52.757819
3284 12:19:52.757871 Set Vref Range= 32 -> 127
3285 12:19:52.757922
3286 12:19:52.757978 RX Vref 32 -> 127, step: 1
3287 12:19:52.758030
3288 12:19:52.758082 RX Delay -13 -> 252, step: 4
3289 12:19:52.758133
3290 12:19:52.758184 Set Vref, RX VrefLevel [Byte0]: 32
3291 12:19:52.758242 [Byte1]: 32
3292 12:19:52.758294
3293 12:19:52.758345 Set Vref, RX VrefLevel [Byte0]: 33
3294 12:19:52.758396 [Byte1]: 33
3295 12:19:52.758447
3296 12:19:52.758504 Set Vref, RX VrefLevel [Byte0]: 34
3297 12:19:52.758555 [Byte1]: 34
3298 12:19:52.758606
3299 12:19:52.758656 Set Vref, RX VrefLevel [Byte0]: 35
3300 12:19:52.758712 [Byte1]: 35
3301 12:19:52.758764
3302 12:19:52.758814 Set Vref, RX VrefLevel [Byte0]: 36
3303 12:19:52.758864 [Byte1]: 36
3304 12:19:52.758915
3305 12:19:52.758972 Set Vref, RX VrefLevel [Byte0]: 37
3306 12:19:52.759023 [Byte1]: 37
3307 12:19:52.759143
3308 12:19:52.759204 Set Vref, RX VrefLevel [Byte0]: 38
3309 12:19:52.759258 [Byte1]: 38
3310 12:19:52.759310
3311 12:19:52.759362 Set Vref, RX VrefLevel [Byte0]: 39
3312 12:19:52.759413 [Byte1]: 39
3313 12:19:52.759471
3314 12:19:52.759522 Set Vref, RX VrefLevel [Byte0]: 40
3315 12:19:52.759574 [Byte1]: 40
3316 12:19:52.759624
3317 12:19:52.759680 Set Vref, RX VrefLevel [Byte0]: 41
3318 12:19:52.759733 [Byte1]: 41
3319 12:19:52.759784
3320 12:19:52.759835 Set Vref, RX VrefLevel [Byte0]: 42
3321 12:19:52.759886 [Byte1]: 42
3322 12:19:52.759942
3323 12:19:52.759993 Set Vref, RX VrefLevel [Byte0]: 43
3324 12:19:52.760044 [Byte1]: 43
3325 12:19:52.760094
3326 12:19:52.760145 Set Vref, RX VrefLevel [Byte0]: 44
3327 12:19:52.760203 [Byte1]: 44
3328 12:19:52.760255
3329 12:19:52.760305 Set Vref, RX VrefLevel [Byte0]: 45
3330 12:19:52.760356 [Byte1]: 45
3331 12:19:52.760412
3332 12:19:52.760464 Set Vref, RX VrefLevel [Byte0]: 46
3333 12:19:52.760516 [Byte1]: 46
3334 12:19:52.760566
3335 12:19:52.760617 Set Vref, RX VrefLevel [Byte0]: 47
3336 12:19:52.760675 [Byte1]: 47
3337 12:19:52.760728
3338 12:19:52.760778 Set Vref, RX VrefLevel [Byte0]: 48
3339 12:19:52.760829 [Byte1]: 48
3340 12:19:52.760880
3341 12:19:52.760937 Set Vref, RX VrefLevel [Byte0]: 49
3342 12:19:52.760989 [Byte1]: 49
3343 12:19:52.761039
3344 12:19:52.761089 Set Vref, RX VrefLevel [Byte0]: 50
3345 12:19:52.761146 [Byte1]: 50
3346 12:19:52.761199
3347 12:19:52.761443 Set Vref, RX VrefLevel [Byte0]: 51
3348 12:19:52.761503 [Byte1]: 51
3349 12:19:52.761556
3350 12:19:52.761608 Set Vref, RX VrefLevel [Byte0]: 52
3351 12:19:52.761668 [Byte1]: 52
3352 12:19:52.761720
3353 12:19:52.761771 Set Vref, RX VrefLevel [Byte0]: 53
3354 12:19:52.761823 [Byte1]: 53
3355 12:19:52.761879
3356 12:19:52.761932 Set Vref, RX VrefLevel [Byte0]: 54
3357 12:19:52.761983 [Byte1]: 54
3358 12:19:52.762035
3359 12:19:52.762085 Set Vref, RX VrefLevel [Byte0]: 55
3360 12:19:52.762141 [Byte1]: 55
3361 12:19:52.762193
3362 12:19:52.762244 Set Vref, RX VrefLevel [Byte0]: 56
3363 12:19:52.762295 [Byte1]: 56
3364 12:19:52.762345
3365 12:19:52.762402 Set Vref, RX VrefLevel [Byte0]: 57
3366 12:19:52.762453 [Byte1]: 57
3367 12:19:52.762504
3368 12:19:52.762555 Set Vref, RX VrefLevel [Byte0]: 58
3369 12:19:52.762606 [Byte1]: 58
3370 12:19:52.762664
3371 12:19:52.762715 Set Vref, RX VrefLevel [Byte0]: 59
3372 12:19:52.762767 [Byte1]: 59
3373 12:19:52.762818
3374 12:19:52.762875 Set Vref, RX VrefLevel [Byte0]: 60
3375 12:19:52.762926 [Byte1]: 60
3376 12:19:52.762977
3377 12:19:52.763027 Set Vref, RX VrefLevel [Byte0]: 61
3378 12:19:52.763116 [Byte1]: 61
3379 12:19:52.763208
3380 12:19:52.763263 Set Vref, RX VrefLevel [Byte0]: 62
3381 12:19:52.763315 [Byte1]: 62
3382 12:19:52.763366
3383 12:19:52.763424 Set Vref, RX VrefLevel [Byte0]: 63
3384 12:19:52.763476 [Byte1]: 63
3385 12:19:52.763527
3386 12:19:52.763578 Set Vref, RX VrefLevel [Byte0]: 64
3387 12:19:52.763630 [Byte1]: 64
3388 12:19:52.763687
3389 12:19:52.763738 Set Vref, RX VrefLevel [Byte0]: 65
3390 12:19:52.763790 [Byte1]: 65
3391 12:19:52.763841
3392 12:19:52.763897 Final RX Vref Byte 0 = 51 to rank0
3393 12:19:52.763949 Final RX Vref Byte 1 = 53 to rank0
3394 12:19:52.764001 Final RX Vref Byte 0 = 51 to rank1
3395 12:19:52.764051 Final RX Vref Byte 1 = 53 to rank1==
3396 12:19:52.764103 Dram Type= 6, Freq= 0, CH_1, rank 0
3397 12:19:52.764161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3398 12:19:52.764213 ==
3399 12:19:52.764263 DQS Delay:
3400 12:19:52.764315 DQS0 = 0, DQS1 = 0
3401 12:19:52.764366 DQM Delay:
3402 12:19:52.764423 DQM0 = 115, DQM1 = 113
3403 12:19:52.764474 DQ Delay:
3404 12:19:52.764525 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3405 12:19:52.764576 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3406 12:19:52.764633 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =108
3407 12:19:52.764685 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =122
3408 12:19:52.764736
3409 12:19:52.764787
3410 12:19:52.764838 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 416 ps
3411 12:19:52.764897 CH1 RK0: MR19=303, MR18=F0FD
3412 12:19:52.764948 CH1_RK0: MR19=0x303, MR18=0xF0FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3413 12:19:52.765001
3414 12:19:52.765052 ----->DramcWriteLeveling(PI) begin...
3415 12:19:52.765110 ==
3416 12:19:52.765162 Dram Type= 6, Freq= 0, CH_1, rank 1
3417 12:19:52.765227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3418 12:19:52.765283 ==
3419 12:19:52.765996 Write leveling (Byte 0): 26 => 26
3420 12:19:52.769414 Write leveling (Byte 1): 28 => 28
3421 12:19:52.769501 DramcWriteLeveling(PI) end<-----
3422 12:19:52.769564
3423 12:19:52.772797 ==
3424 12:19:52.776248 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 12:19:52.779297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 12:19:52.779377 ==
3427 12:19:52.782976 [Gating] SW mode calibration
3428 12:19:52.789475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3429 12:19:52.793532 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3430 12:19:52.799023 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3431 12:19:52.802559 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3432 12:19:52.805701 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 12:19:52.812238 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 12:19:52.815796 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 12:19:52.818498 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3436 12:19:52.824981 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 1)
3437 12:19:52.828907 0 15 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
3438 12:19:52.831687 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3439 12:19:52.838198 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 12:19:52.841817 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 12:19:52.844716 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 12:19:52.852262 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 12:19:52.855221 1 0 20 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
3444 12:19:52.862115 1 0 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
3445 12:19:52.864695 1 0 28 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
3446 12:19:52.868002 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3447 12:19:52.874434 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 12:19:52.877895 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 12:19:52.881145 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 12:19:52.887622 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 12:19:52.890934 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 12:19:52.894243 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3453 12:19:52.900739 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3454 12:19:52.904542 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 12:19:52.907472 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 12:19:52.914218 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 12:19:52.917245 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 12:19:52.920724 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 12:19:52.926933 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 12:19:52.930233 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 12:19:52.933721 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:19:52.940560 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:19:52.943640 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:19:52.947011 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:19:52.953056 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:19:52.956729 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:19:52.959754 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3468 12:19:52.966911 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3469 12:19:52.969602 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3470 12:19:52.972983 Total UI for P1: 0, mck2ui 16
3471 12:19:52.976259 best dqsien dly found for B0: ( 1, 3, 22)
3472 12:19:52.979260 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 12:19:52.982963 Total UI for P1: 0, mck2ui 16
3474 12:19:52.986154 best dqsien dly found for B1: ( 1, 3, 26)
3475 12:19:52.989414 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3476 12:19:52.992656 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3477 12:19:52.992736
3478 12:19:52.999042 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3479 12:19:53.002703 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3480 12:19:53.005877 [Gating] SW calibration Done
3481 12:19:53.005957 ==
3482 12:19:53.009113 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 12:19:53.012166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 12:19:53.012246 ==
3485 12:19:53.012321 RX Vref Scan: 0
3486 12:19:53.012381
3487 12:19:53.015683 RX Vref 0 -> 0, step: 1
3488 12:19:53.015762
3489 12:19:53.018819 RX Delay -40 -> 252, step: 8
3490 12:19:53.022171 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3491 12:19:53.025425 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3492 12:19:53.032569 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3493 12:19:53.036253 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3494 12:19:53.038666 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3495 12:19:53.041652 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3496 12:19:53.045150 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3497 12:19:53.051873 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3498 12:19:53.054991 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3499 12:19:53.058175 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3500 12:19:53.061887 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3501 12:19:53.068726 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3502 12:19:53.072070 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3503 12:19:53.075039 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3504 12:19:53.078218 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3505 12:19:53.081778 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3506 12:19:53.084976 ==
3507 12:19:53.088177 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 12:19:53.091645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 12:19:53.091725 ==
3510 12:19:53.091787 DQS Delay:
3511 12:19:53.094765 DQS0 = 0, DQS1 = 0
3512 12:19:53.094844 DQM Delay:
3513 12:19:53.097947 DQM0 = 115, DQM1 = 113
3514 12:19:53.098026 DQ Delay:
3515 12:19:53.101318 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3516 12:19:53.104166 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3517 12:19:53.108024 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
3518 12:19:53.111049 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3519 12:19:53.111137
3520 12:19:53.111199
3521 12:19:53.114449 ==
3522 12:19:53.117861 Dram Type= 6, Freq= 0, CH_1, rank 1
3523 12:19:53.120935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3524 12:19:53.121014 ==
3525 12:19:53.121076
3526 12:19:53.121134
3527 12:19:53.124012 TX Vref Scan disable
3528 12:19:53.124091 == TX Byte 0 ==
3529 12:19:53.127301 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3530 12:19:53.134101 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3531 12:19:53.134181 == TX Byte 1 ==
3532 12:19:53.140765 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3533 12:19:53.143966 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3534 12:19:53.144041 ==
3535 12:19:53.147191 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 12:19:53.150182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 12:19:53.150260 ==
3538 12:19:53.162665 TX Vref=22, minBit 3, minWin=25, winSum=417
3539 12:19:53.165813 TX Vref=24, minBit 1, minWin=25, winSum=422
3540 12:19:53.169330 TX Vref=26, minBit 1, minWin=26, winSum=425
3541 12:19:53.172459 TX Vref=28, minBit 1, minWin=26, winSum=431
3542 12:19:53.175538 TX Vref=30, minBit 1, minWin=26, winSum=432
3543 12:19:53.182420 TX Vref=32, minBit 9, minWin=26, winSum=431
3544 12:19:53.185349 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3545 12:19:53.185424
3546 12:19:53.189067 Final TX Range 1 Vref 30
3547 12:19:53.189135
3548 12:19:53.189193 ==
3549 12:19:53.192045 Dram Type= 6, Freq= 0, CH_1, rank 1
3550 12:19:53.195684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3551 12:19:53.199601 ==
3552 12:19:53.199672
3553 12:19:53.199731
3554 12:19:53.199787 TX Vref Scan disable
3555 12:19:53.202483 == TX Byte 0 ==
3556 12:19:53.205776 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3557 12:19:53.212331 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3558 12:19:53.212408 == TX Byte 1 ==
3559 12:19:53.215235 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3560 12:19:53.222159 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3561 12:19:53.222234
3562 12:19:53.222304 [DATLAT]
3563 12:19:53.222362 Freq=1200, CH1 RK1
3564 12:19:53.222419
3565 12:19:53.225074 DATLAT Default: 0xd
3566 12:19:53.228895 0, 0xFFFF, sum = 0
3567 12:19:53.228968 1, 0xFFFF, sum = 0
3568 12:19:53.231779 2, 0xFFFF, sum = 0
3569 12:19:53.231857 3, 0xFFFF, sum = 0
3570 12:19:53.235252 4, 0xFFFF, sum = 0
3571 12:19:53.235323 5, 0xFFFF, sum = 0
3572 12:19:53.238307 6, 0xFFFF, sum = 0
3573 12:19:53.238378 7, 0xFFFF, sum = 0
3574 12:19:53.241504 8, 0xFFFF, sum = 0
3575 12:19:53.241579 9, 0xFFFF, sum = 0
3576 12:19:53.244681 10, 0xFFFF, sum = 0
3577 12:19:53.244753 11, 0xFFFF, sum = 0
3578 12:19:53.248813 12, 0x0, sum = 1
3579 12:19:53.248890 13, 0x0, sum = 2
3580 12:19:53.251937 14, 0x0, sum = 3
3581 12:19:53.252010 15, 0x0, sum = 4
3582 12:19:53.254717 best_step = 13
3583 12:19:53.254793
3584 12:19:53.254852 ==
3585 12:19:53.258407 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 12:19:53.261668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 12:19:53.261745 ==
3588 12:19:53.264755 RX Vref Scan: 0
3589 12:19:53.264826
3590 12:19:53.264894 RX Vref 0 -> 0, step: 1
3591 12:19:53.264951
3592 12:19:53.268286 RX Delay -13 -> 252, step: 4
3593 12:19:53.274413 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3594 12:19:53.278333 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3595 12:19:53.281500 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3596 12:19:53.284124 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3597 12:19:53.291433 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3598 12:19:53.293995 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3599 12:19:53.298084 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3600 12:19:53.300891 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3601 12:19:53.303781 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3602 12:19:53.310323 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3603 12:19:53.313483 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3604 12:19:53.316778 iDelay=195, Bit 11, Center 108 (47 ~ 170) 124
3605 12:19:53.320416 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3606 12:19:53.326947 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3607 12:19:53.329932 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3608 12:19:53.333629 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3609 12:19:53.333698 ==
3610 12:19:53.336423 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 12:19:53.339785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 12:19:53.339854 ==
3613 12:19:53.343161 DQS Delay:
3614 12:19:53.343232 DQS0 = 0, DQS1 = 0
3615 12:19:53.346404 DQM Delay:
3616 12:19:53.346469 DQM0 = 115, DQM1 = 113
3617 12:19:53.349953 DQ Delay:
3618 12:19:53.352949 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =114
3619 12:19:53.356097 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3620 12:19:53.359578 DQ8 =100, DQ9 =104, DQ10 =116, DQ11 =108
3621 12:19:53.362643 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3622 12:19:53.362715
3623 12:19:53.362774
3624 12:19:53.373033 [DQSOSCAuto] RK1, (LSB)MR18= 0xf003, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 416 ps
3625 12:19:53.373110 CH1 RK1: MR19=304, MR18=F003
3626 12:19:53.379461 CH1_RK1: MR19=0x304, MR18=0xF003, DQSOSC=408, MR23=63, INC=39, DEC=26
3627 12:19:53.382634 [RxdqsGatingPostProcess] freq 1200
3628 12:19:53.389689 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3629 12:19:53.392546 best DQS0 dly(2T, 0.5T) = (0, 11)
3630 12:19:53.395644 best DQS1 dly(2T, 0.5T) = (0, 11)
3631 12:19:53.399009 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3632 12:19:53.402822 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3633 12:19:53.405344 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 12:19:53.405429 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 12:19:53.408904 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 12:19:53.412532 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 12:19:53.415387 Pre-setting of DQS Precalculation
3638 12:19:53.421695 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3639 12:19:53.428437 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3640 12:19:53.434781 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3641 12:19:53.434864
3642 12:19:53.434927
3643 12:19:53.438639 [Calibration Summary] 2400 Mbps
3644 12:19:53.441380 CH 0, Rank 0
3645 12:19:53.441484 SW Impedance : PASS
3646 12:19:53.445171 DUTY Scan : NO K
3647 12:19:53.448268 ZQ Calibration : PASS
3648 12:19:53.448403 Jitter Meter : NO K
3649 12:19:53.451300 CBT Training : PASS
3650 12:19:53.454951 Write leveling : PASS
3651 12:19:53.455092 RX DQS gating : PASS
3652 12:19:53.457966 RX DQ/DQS(RDDQC) : PASS
3653 12:19:53.461136 TX DQ/DQS : PASS
3654 12:19:53.461210 RX DATLAT : PASS
3655 12:19:53.464825 RX DQ/DQS(Engine): PASS
3656 12:19:53.468206 TX OE : NO K
3657 12:19:53.468339 All Pass.
3658 12:19:53.468457
3659 12:19:53.468549 CH 0, Rank 1
3660 12:19:53.471500 SW Impedance : PASS
3661 12:19:53.474963 DUTY Scan : NO K
3662 12:19:53.475078 ZQ Calibration : PASS
3663 12:19:53.477699 Jitter Meter : NO K
3664 12:19:53.477807 CBT Training : PASS
3665 12:19:53.481160 Write leveling : PASS
3666 12:19:53.484048 RX DQS gating : PASS
3667 12:19:53.484165 RX DQ/DQS(RDDQC) : PASS
3668 12:19:53.487608 TX DQ/DQS : PASS
3669 12:19:53.490692 RX DATLAT : PASS
3670 12:19:53.490794 RX DQ/DQS(Engine): PASS
3671 12:19:53.494342 TX OE : NO K
3672 12:19:53.494418 All Pass.
3673 12:19:53.494479
3674 12:19:53.497174 CH 1, Rank 0
3675 12:19:53.497248 SW Impedance : PASS
3676 12:19:53.500819 DUTY Scan : NO K
3677 12:19:53.504241 ZQ Calibration : PASS
3678 12:19:53.504315 Jitter Meter : NO K
3679 12:19:53.507485 CBT Training : PASS
3680 12:19:53.510424 Write leveling : PASS
3681 12:19:53.510530 RX DQS gating : PASS
3682 12:19:53.513642 RX DQ/DQS(RDDQC) : PASS
3683 12:19:53.517157 TX DQ/DQS : PASS
3684 12:19:53.517297 RX DATLAT : PASS
3685 12:19:53.520222 RX DQ/DQS(Engine): PASS
3686 12:19:53.523786 TX OE : NO K
3687 12:19:53.523862 All Pass.
3688 12:19:53.523927
3689 12:19:53.523983 CH 1, Rank 1
3690 12:19:53.527212 SW Impedance : PASS
3691 12:19:53.529971 DUTY Scan : NO K
3692 12:19:53.530044 ZQ Calibration : PASS
3693 12:19:53.533486 Jitter Meter : NO K
3694 12:19:53.537118 CBT Training : PASS
3695 12:19:53.537194 Write leveling : PASS
3696 12:19:53.539947 RX DQS gating : PASS
3697 12:19:53.543432 RX DQ/DQS(RDDQC) : PASS
3698 12:19:53.543501 TX DQ/DQS : PASS
3699 12:19:53.546659 RX DATLAT : PASS
3700 12:19:53.549967 RX DQ/DQS(Engine): PASS
3701 12:19:53.550037 TX OE : NO K
3702 12:19:53.553002 All Pass.
3703 12:19:53.553077
3704 12:19:53.553138 DramC Write-DBI off
3705 12:19:53.556385 PER_BANK_REFRESH: Hybrid Mode
3706 12:19:53.556488 TX_TRACKING: ON
3707 12:19:53.566178 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3708 12:19:53.569809 [FAST_K] Save calibration result to emmc
3709 12:19:53.572908 dramc_set_vcore_voltage set vcore to 650000
3710 12:19:53.576369 Read voltage for 600, 5
3711 12:19:53.576442 Vio18 = 0
3712 12:19:53.580001 Vcore = 650000
3713 12:19:53.580077 Vdram = 0
3714 12:19:53.580137 Vddq = 0
3715 12:19:53.582824 Vmddr = 0
3716 12:19:53.586018 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3717 12:19:53.592811 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3718 12:19:53.592890 MEM_TYPE=3, freq_sel=19
3719 12:19:53.596059 sv_algorithm_assistance_LP4_1600
3720 12:19:53.602490 ============ PULL DRAM RESETB DOWN ============
3721 12:19:53.605795 ========== PULL DRAM RESETB DOWN end =========
3722 12:19:53.609375 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3723 12:19:53.612368 ===================================
3724 12:19:53.615964 LPDDR4 DRAM CONFIGURATION
3725 12:19:53.618859 ===================================
3726 12:19:53.622611 EX_ROW_EN[0] = 0x0
3727 12:19:53.622683 EX_ROW_EN[1] = 0x0
3728 12:19:53.625215 LP4Y_EN = 0x0
3729 12:19:53.625284 WORK_FSP = 0x0
3730 12:19:53.629143 WL = 0x2
3731 12:19:53.629214 RL = 0x2
3732 12:19:53.632112 BL = 0x2
3733 12:19:53.632181 RPST = 0x0
3734 12:19:53.635683 RD_PRE = 0x0
3735 12:19:53.635754 WR_PRE = 0x1
3736 12:19:53.638834 WR_PST = 0x0
3737 12:19:53.638903 DBI_WR = 0x0
3738 12:19:53.641874 DBI_RD = 0x0
3739 12:19:53.645524 OTF = 0x1
3740 12:19:53.648719 ===================================
3741 12:19:53.651553 ===================================
3742 12:19:53.651629 ANA top config
3743 12:19:53.654968 ===================================
3744 12:19:53.658537 DLL_ASYNC_EN = 0
3745 12:19:53.661305 ALL_SLAVE_EN = 1
3746 12:19:53.661386 NEW_RANK_MODE = 1
3747 12:19:53.664911 DLL_IDLE_MODE = 1
3748 12:19:53.668169 LP45_APHY_COMB_EN = 1
3749 12:19:53.671877 TX_ODT_DIS = 1
3750 12:19:53.671949 NEW_8X_MODE = 1
3751 12:19:53.675314 ===================================
3752 12:19:53.678430 ===================================
3753 12:19:53.681164 data_rate = 1200
3754 12:19:53.684408 CKR = 1
3755 12:19:53.687772 DQ_P2S_RATIO = 8
3756 12:19:53.691441 ===================================
3757 12:19:53.694706 CA_P2S_RATIO = 8
3758 12:19:53.698204 DQ_CA_OPEN = 0
3759 12:19:53.701522 DQ_SEMI_OPEN = 0
3760 12:19:53.701621 CA_SEMI_OPEN = 0
3761 12:19:53.704705 CA_FULL_RATE = 0
3762 12:19:53.707669 DQ_CKDIV4_EN = 1
3763 12:19:53.711005 CA_CKDIV4_EN = 1
3764 12:19:53.714217 CA_PREDIV_EN = 0
3765 12:19:53.717368 PH8_DLY = 0
3766 12:19:53.717439 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3767 12:19:53.721364 DQ_AAMCK_DIV = 4
3768 12:19:53.724475 CA_AAMCK_DIV = 4
3769 12:19:53.727894 CA_ADMCK_DIV = 4
3770 12:19:53.730426 DQ_TRACK_CA_EN = 0
3771 12:19:53.733962 CA_PICK = 600
3772 12:19:53.736887 CA_MCKIO = 600
3773 12:19:53.736967 MCKIO_SEMI = 0
3774 12:19:53.740401 PLL_FREQ = 2288
3775 12:19:53.743692 DQ_UI_PI_RATIO = 32
3776 12:19:53.747038 CA_UI_PI_RATIO = 0
3777 12:19:53.750467 ===================================
3778 12:19:53.753607 ===================================
3779 12:19:53.756637 memory_type:LPDDR4
3780 12:19:53.756740 GP_NUM : 10
3781 12:19:53.760312 SRAM_EN : 1
3782 12:19:53.763581 MD32_EN : 0
3783 12:19:53.766550 ===================================
3784 12:19:53.766632 [ANA_INIT] >>>>>>>>>>>>>>
3785 12:19:53.770010 <<<<<< [CONFIGURE PHASE]: ANA_TX
3786 12:19:53.773233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3787 12:19:53.776578 ===================================
3788 12:19:53.779744 data_rate = 1200,PCW = 0X5800
3789 12:19:53.783111 ===================================
3790 12:19:53.786602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3791 12:19:53.793410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3792 12:19:53.799384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 12:19:53.803438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3794 12:19:53.806357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3795 12:19:53.809469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3796 12:19:53.813289 [ANA_INIT] flow start
3797 12:19:53.813369 [ANA_INIT] PLL >>>>>>>>
3798 12:19:53.816279 [ANA_INIT] PLL <<<<<<<<
3799 12:19:53.819201 [ANA_INIT] MIDPI >>>>>>>>
3800 12:19:53.819281 [ANA_INIT] MIDPI <<<<<<<<
3801 12:19:53.822486 [ANA_INIT] DLL >>>>>>>>
3802 12:19:53.825723 [ANA_INIT] flow end
3803 12:19:53.829141 ============ LP4 DIFF to SE enter ============
3804 12:19:53.832314 ============ LP4 DIFF to SE exit ============
3805 12:19:53.835486 [ANA_INIT] <<<<<<<<<<<<<
3806 12:19:53.839230 [Flow] Enable top DCM control >>>>>
3807 12:19:53.842219 [Flow] Enable top DCM control <<<<<
3808 12:19:53.845132 Enable DLL master slave shuffle
3809 12:19:53.851906 ==============================================================
3810 12:19:53.852029 Gating Mode config
3811 12:19:53.858805 ==============================================================
3812 12:19:53.858886 Config description:
3813 12:19:53.868754 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3814 12:19:53.875022 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3815 12:19:53.881661 SELPH_MODE 0: By rank 1: By Phase
3816 12:19:53.885274 ==============================================================
3817 12:19:53.888270 GAT_TRACK_EN = 1
3818 12:19:53.892152 RX_GATING_MODE = 2
3819 12:19:53.895128 RX_GATING_TRACK_MODE = 2
3820 12:19:53.898010 SELPH_MODE = 1
3821 12:19:53.902269 PICG_EARLY_EN = 1
3822 12:19:53.905147 VALID_LAT_VALUE = 1
3823 12:19:53.911545 ==============================================================
3824 12:19:53.914386 Enter into Gating configuration >>>>
3825 12:19:53.918075 Exit from Gating configuration <<<<
3826 12:19:53.921630 Enter into DVFS_PRE_config >>>>>
3827 12:19:53.930864 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3828 12:19:53.934678 Exit from DVFS_PRE_config <<<<<
3829 12:19:53.937746 Enter into PICG configuration >>>>
3830 12:19:53.940821 Exit from PICG configuration <<<<
3831 12:19:53.943927 [RX_INPUT] configuration >>>>>
3832 12:19:53.947522 [RX_INPUT] configuration <<<<<
3833 12:19:53.950302 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3834 12:19:53.957050 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3835 12:19:53.963922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3836 12:19:53.970410 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3837 12:19:53.973865 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3838 12:19:53.980263 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3839 12:19:53.983441 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3840 12:19:53.989873 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3841 12:19:53.993505 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3842 12:19:53.996382 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3843 12:19:54.000108 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3844 12:19:54.006249 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3845 12:19:54.009829 ===================================
3846 12:19:54.013504 LPDDR4 DRAM CONFIGURATION
3847 12:19:54.016454 ===================================
3848 12:19:54.016534 EX_ROW_EN[0] = 0x0
3849 12:19:54.019487 EX_ROW_EN[1] = 0x0
3850 12:19:54.019567 LP4Y_EN = 0x0
3851 12:19:54.023238 WORK_FSP = 0x0
3852 12:19:54.023318 WL = 0x2
3853 12:19:54.026400 RL = 0x2
3854 12:19:54.026479 BL = 0x2
3855 12:19:54.030227 RPST = 0x0
3856 12:19:54.030307 RD_PRE = 0x0
3857 12:19:54.033086 WR_PRE = 0x1
3858 12:19:54.033165 WR_PST = 0x0
3859 12:19:54.036339 DBI_WR = 0x0
3860 12:19:54.036419 DBI_RD = 0x0
3861 12:19:54.039357 OTF = 0x1
3862 12:19:54.042614 ===================================
3863 12:19:54.046494 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3864 12:19:54.049487 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3865 12:19:54.055597 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 12:19:54.058991 ===================================
3867 12:19:54.062287 LPDDR4 DRAM CONFIGURATION
3868 12:19:54.065430 ===================================
3869 12:19:54.065544 EX_ROW_EN[0] = 0x10
3870 12:19:54.068733 EX_ROW_EN[1] = 0x0
3871 12:19:54.068813 LP4Y_EN = 0x0
3872 12:19:54.072344 WORK_FSP = 0x0
3873 12:19:54.072424 WL = 0x2
3874 12:19:54.075461 RL = 0x2
3875 12:19:54.075541 BL = 0x2
3876 12:19:54.078641 RPST = 0x0
3877 12:19:54.082232 RD_PRE = 0x0
3878 12:19:54.082337 WR_PRE = 0x1
3879 12:19:54.085739 WR_PST = 0x0
3880 12:19:54.085819 DBI_WR = 0x0
3881 12:19:54.088353 DBI_RD = 0x0
3882 12:19:54.088432 OTF = 0x1
3883 12:19:54.091792 ===================================
3884 12:19:54.098173 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3885 12:19:54.102958 nWR fixed to 30
3886 12:19:54.106165 [ModeRegInit_LP4] CH0 RK0
3887 12:19:54.106282 [ModeRegInit_LP4] CH0 RK1
3888 12:19:54.108726 [ModeRegInit_LP4] CH1 RK0
3889 12:19:54.112752 [ModeRegInit_LP4] CH1 RK1
3890 12:19:54.112828 match AC timing 17
3891 12:19:54.118700 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3892 12:19:54.121902 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3893 12:19:54.125778 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3894 12:19:54.131974 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3895 12:19:54.135387 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3896 12:19:54.135473 ==
3897 12:19:54.138640 Dram Type= 6, Freq= 0, CH_0, rank 0
3898 12:19:54.141748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3899 12:19:54.145226 ==
3900 12:19:54.148077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3901 12:19:54.155214 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3902 12:19:54.158272 [CA 0] Center 36 (6~67) winsize 62
3903 12:19:54.161388 [CA 1] Center 36 (6~66) winsize 61
3904 12:19:54.164897 [CA 2] Center 34 (4~65) winsize 62
3905 12:19:54.168341 [CA 3] Center 34 (4~65) winsize 62
3906 12:19:54.171725 [CA 4] Center 33 (3~64) winsize 62
3907 12:19:54.174927 [CA 5] Center 33 (3~64) winsize 62
3908 12:19:54.175033
3909 12:19:54.177787 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3910 12:19:54.177884
3911 12:19:54.181193 [CATrainingPosCal] consider 1 rank data
3912 12:19:54.184370 u2DelayCellTimex100 = 270/100 ps
3913 12:19:54.188173 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3914 12:19:54.191168 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3915 12:19:54.194417 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3916 12:19:54.201343 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3917 12:19:54.204460 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3918 12:19:54.208003 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3919 12:19:54.208078
3920 12:19:54.211068 CA PerBit enable=1, Macro0, CA PI delay=33
3921 12:19:54.211181
3922 12:19:54.214449 [CBTSetCACLKResult] CA Dly = 33
3923 12:19:54.214522 CS Dly: 4 (0~35)
3924 12:19:54.214583 ==
3925 12:19:54.218264 Dram Type= 6, Freq= 0, CH_0, rank 1
3926 12:19:54.224276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3927 12:19:54.224371 ==
3928 12:19:54.227630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3929 12:19:54.233997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3930 12:19:54.237648 [CA 0] Center 36 (6~67) winsize 62
3931 12:19:54.241103 [CA 1] Center 36 (6~67) winsize 62
3932 12:19:54.244627 [CA 2] Center 35 (4~66) winsize 63
3933 12:19:54.247636 [CA 3] Center 35 (4~66) winsize 63
3934 12:19:54.250681 [CA 4] Center 34 (4~65) winsize 62
3935 12:19:54.253903 [CA 5] Center 34 (3~65) winsize 63
3936 12:19:54.253983
3937 12:19:54.257275 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3938 12:19:54.257355
3939 12:19:54.261019 [CATrainingPosCal] consider 2 rank data
3940 12:19:54.264128 u2DelayCellTimex100 = 270/100 ps
3941 12:19:54.267048 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3942 12:19:54.274050 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3943 12:19:54.277039 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3944 12:19:54.280460 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3945 12:19:54.284076 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3946 12:19:54.287463 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3947 12:19:54.287543
3948 12:19:54.290487 CA PerBit enable=1, Macro0, CA PI delay=33
3949 12:19:54.290567
3950 12:19:54.293656 [CBTSetCACLKResult] CA Dly = 33
3951 12:19:54.297484 CS Dly: 5 (0~37)
3952 12:19:54.297563
3953 12:19:54.300040 ----->DramcWriteLeveling(PI) begin...
3954 12:19:54.300121 ==
3955 12:19:54.303708 Dram Type= 6, Freq= 0, CH_0, rank 0
3956 12:19:54.307064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3957 12:19:54.307180 ==
3958 12:19:54.309969 Write leveling (Byte 0): 32 => 32
3959 12:19:54.313779 Write leveling (Byte 1): 28 => 28
3960 12:19:54.316540 DramcWriteLeveling(PI) end<-----
3961 12:19:54.316619
3962 12:19:54.316681 ==
3963 12:19:54.320100 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 12:19:54.322937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 12:19:54.323018 ==
3966 12:19:54.326918 [Gating] SW mode calibration
3967 12:19:54.333195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3968 12:19:54.340053 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3969 12:19:54.343258 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3970 12:19:54.346331 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 12:19:54.353052 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 12:19:54.356058 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
3973 12:19:54.359326 0 9 16 | B1->B0 | 2e2e 2929 | 0 0 | (0 0) (0 0)
3974 12:19:54.366240 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3975 12:19:54.369356 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 12:19:54.373011 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 12:19:54.379098 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 12:19:54.382652 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 12:19:54.389031 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 12:19:54.392243 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3981 12:19:54.395760 0 10 16 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
3982 12:19:54.402110 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3983 12:19:54.406131 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 12:19:54.409043 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 12:19:54.415650 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 12:19:54.418769 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 12:19:54.422098 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 12:19:54.428219 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 12:19:54.431609 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3990 12:19:54.435029 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 12:19:54.441228 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 12:19:54.445034 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 12:19:54.447980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:19:54.454599 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 12:19:54.457819 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:19:54.461201 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:19:54.467976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:19:54.471360 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:19:54.474729 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:19:54.481253 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:19:54.484656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:19:54.487956 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:19:54.494059 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:19:54.497239 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4005 12:19:54.500399 Total UI for P1: 0, mck2ui 16
4006 12:19:54.504102 best dqsien dly found for B0: ( 0, 13, 10)
4007 12:19:54.507338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4008 12:19:54.514005 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 12:19:54.514086 Total UI for P1: 0, mck2ui 16
4010 12:19:54.520648 best dqsien dly found for B1: ( 0, 13, 16)
4011 12:19:54.523847 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4012 12:19:54.526977 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4013 12:19:54.527057
4014 12:19:54.530419 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4015 12:19:54.533849 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4016 12:19:54.536956 [Gating] SW calibration Done
4017 12:19:54.537036 ==
4018 12:19:54.540173 Dram Type= 6, Freq= 0, CH_0, rank 0
4019 12:19:54.543051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4020 12:19:54.543140 ==
4021 12:19:54.546297 RX Vref Scan: 0
4022 12:19:54.546377
4023 12:19:54.549763 RX Vref 0 -> 0, step: 1
4024 12:19:54.549842
4025 12:19:54.549904 RX Delay -230 -> 252, step: 16
4026 12:19:54.556931 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4027 12:19:54.560237 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4028 12:19:54.563009 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4029 12:19:54.566099 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4030 12:19:54.572608 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4031 12:19:54.575947 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4032 12:19:54.579349 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4033 12:19:54.582712 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4034 12:19:54.588999 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4035 12:19:54.592911 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4036 12:19:54.596317 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4037 12:19:54.599378 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4038 12:19:54.605865 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4039 12:19:54.608934 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4040 12:19:54.612393 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4041 12:19:54.615606 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4042 12:19:54.615680 ==
4043 12:19:54.619402 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 12:19:54.625723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 12:19:54.625805 ==
4046 12:19:54.625866 DQS Delay:
4047 12:19:54.629091 DQS0 = 0, DQS1 = 0
4048 12:19:54.629157 DQM Delay:
4049 12:19:54.632314 DQM0 = 46, DQM1 = 36
4050 12:19:54.632382 DQ Delay:
4051 12:19:54.635444 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4052 12:19:54.638663 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4053 12:19:54.642177 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4054 12:19:54.645736 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4055 12:19:54.645807
4056 12:19:54.645869
4057 12:19:54.645926 ==
4058 12:19:54.648480 Dram Type= 6, Freq= 0, CH_0, rank 0
4059 12:19:54.651958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4060 12:19:54.652024 ==
4061 12:19:54.652081
4062 12:19:54.652134
4063 12:19:54.655328 TX Vref Scan disable
4064 12:19:54.658447 == TX Byte 0 ==
4065 12:19:54.662012 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4066 12:19:54.664895 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4067 12:19:54.668183 == TX Byte 1 ==
4068 12:19:54.671430 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4069 12:19:54.674667 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4070 12:19:54.674747 ==
4071 12:19:54.678578 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 12:19:54.684988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 12:19:54.685069 ==
4074 12:19:54.685131
4075 12:19:54.685189
4076 12:19:54.685246 TX Vref Scan disable
4077 12:19:54.689353 == TX Byte 0 ==
4078 12:19:54.692901 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4079 12:19:54.698875 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4080 12:19:54.698956 == TX Byte 1 ==
4081 12:19:54.702250 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4082 12:19:54.708759 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4083 12:19:54.708838
4084 12:19:54.708901 [DATLAT]
4085 12:19:54.708965 Freq=600, CH0 RK0
4086 12:19:54.709031
4087 12:19:54.712550 DATLAT Default: 0x9
4088 12:19:54.712627 0, 0xFFFF, sum = 0
4089 12:19:54.715615 1, 0xFFFF, sum = 0
4090 12:19:54.718756 2, 0xFFFF, sum = 0
4091 12:19:54.718855 3, 0xFFFF, sum = 0
4092 12:19:54.722212 4, 0xFFFF, sum = 0
4093 12:19:54.722296 5, 0xFFFF, sum = 0
4094 12:19:54.725383 6, 0xFFFF, sum = 0
4095 12:19:54.725455 7, 0xFFFF, sum = 0
4096 12:19:54.728811 8, 0x0, sum = 1
4097 12:19:54.728881 9, 0x0, sum = 2
4098 12:19:54.731982 10, 0x0, sum = 3
4099 12:19:54.732049 11, 0x0, sum = 4
4100 12:19:54.732112 best_step = 9
4101 12:19:54.732169
4102 12:19:54.734990 ==
4103 12:19:54.739029 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 12:19:54.741661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 12:19:54.741730 ==
4106 12:19:54.741788 RX Vref Scan: 1
4107 12:19:54.741844
4108 12:19:54.745356 RX Vref 0 -> 0, step: 1
4109 12:19:54.745462
4110 12:19:54.748397 RX Delay -179 -> 252, step: 8
4111 12:19:54.748469
4112 12:19:54.751515 Set Vref, RX VrefLevel [Byte0]: 59
4113 12:19:54.754776 [Byte1]: 49
4114 12:19:54.754881
4115 12:19:54.758750 Final RX Vref Byte 0 = 59 to rank0
4116 12:19:54.761688 Final RX Vref Byte 1 = 49 to rank0
4117 12:19:54.764715 Final RX Vref Byte 0 = 59 to rank1
4118 12:19:54.768194 Final RX Vref Byte 1 = 49 to rank1==
4119 12:19:54.771401 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 12:19:54.778433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 12:19:54.778534 ==
4122 12:19:54.778597 DQS Delay:
4123 12:19:54.778655 DQS0 = 0, DQS1 = 0
4124 12:19:54.781025 DQM Delay:
4125 12:19:54.781096 DQM0 = 44, DQM1 = 36
4126 12:19:54.784756 DQ Delay:
4127 12:19:54.787829 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4128 12:19:54.791391 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4129 12:19:54.794483 DQ8 =28, DQ9 =20, DQ10 =36, DQ11 =32
4130 12:19:54.797730 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4131 12:19:54.797832
4132 12:19:54.797913
4133 12:19:54.804379 [DQSOSCAuto] RK0, (LSB)MR18= 0x463d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4134 12:19:54.807612 CH0 RK0: MR19=808, MR18=463D
4135 12:19:54.814484 CH0_RK0: MR19=0x808, MR18=0x463D, DQSOSC=396, MR23=63, INC=167, DEC=111
4136 12:19:54.814577
4137 12:19:54.817617 ----->DramcWriteLeveling(PI) begin...
4138 12:19:54.817692 ==
4139 12:19:54.820827 Dram Type= 6, Freq= 0, CH_0, rank 1
4140 12:19:54.824045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 12:19:54.824120 ==
4142 12:19:54.827231 Write leveling (Byte 0): 34 => 34
4143 12:19:54.830763 Write leveling (Byte 1): 30 => 30
4144 12:19:54.834301 DramcWriteLeveling(PI) end<-----
4145 12:19:54.834375
4146 12:19:54.834437 ==
4147 12:19:54.836997 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 12:19:54.840878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 12:19:54.844428 ==
4150 12:19:54.844504 [Gating] SW mode calibration
4151 12:19:54.850616 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4152 12:19:54.856815 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4153 12:19:54.860624 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4154 12:19:54.866813 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 12:19:54.870260 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4156 12:19:54.873941 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 0)
4157 12:19:54.880151 0 9 16 | B1->B0 | 3030 2525 | 0 0 | (1 1) (1 1)
4158 12:19:54.883289 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4159 12:19:54.886700 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 12:19:54.893527 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 12:19:54.896720 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 12:19:54.900178 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 12:19:54.906426 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 12:19:54.909498 0 10 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
4165 12:19:54.913636 0 10 16 | B1->B0 | 3939 4343 | 0 0 | (1 1) (0 0)
4166 12:19:54.919622 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4167 12:19:54.922888 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 12:19:54.926418 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 12:19:54.932699 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 12:19:54.936205 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 12:19:54.939798 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 12:19:54.946222 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4173 12:19:54.949398 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4174 12:19:54.952507 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 12:19:54.959661 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:19:54.962782 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:19:54.966173 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:19:54.972374 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 12:19:54.976222 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 12:19:54.979056 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:19:54.985698 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:19:54.989306 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:19:54.992224 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:19:54.998640 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:19:55.001961 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:19:55.005275 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:19:55.011728 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:19:55.014863 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4189 12:19:55.018451 Total UI for P1: 0, mck2ui 16
4190 12:19:55.022012 best dqsien dly found for B0: ( 0, 13, 10)
4191 12:19:55.025308 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4192 12:19:55.031859 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 12:19:55.034899 Total UI for P1: 0, mck2ui 16
4194 12:19:55.037998 best dqsien dly found for B1: ( 0, 13, 14)
4195 12:19:55.041510 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4196 12:19:55.045162 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4197 12:19:55.045269
4198 12:19:55.048190 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4199 12:19:55.051342 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4200 12:19:55.054728 [Gating] SW calibration Done
4201 12:19:55.054801 ==
4202 12:19:55.057499 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 12:19:55.061100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 12:19:55.061175 ==
4205 12:19:55.064079 RX Vref Scan: 0
4206 12:19:55.064147
4207 12:19:55.068110 RX Vref 0 -> 0, step: 1
4208 12:19:55.068180
4209 12:19:55.071181 RX Delay -230 -> 252, step: 16
4210 12:19:55.074274 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4211 12:19:55.077455 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4212 12:19:55.080516 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4213 12:19:55.087320 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4214 12:19:55.090858 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4215 12:19:55.094137 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4216 12:19:55.097219 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4217 12:19:55.100316 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4218 12:19:55.107089 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4219 12:19:55.110692 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4220 12:19:55.113800 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4221 12:19:55.116768 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4222 12:19:55.123273 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4223 12:19:55.126882 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4224 12:19:55.129976 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4225 12:19:55.133323 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4226 12:19:55.136813 ==
4227 12:19:55.136883 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 12:19:55.143398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 12:19:55.143470 ==
4230 12:19:55.143534 DQS Delay:
4231 12:19:55.146543 DQS0 = 0, DQS1 = 0
4232 12:19:55.146609 DQM Delay:
4233 12:19:55.150160 DQM0 = 45, DQM1 = 36
4234 12:19:55.150230 DQ Delay:
4235 12:19:55.153271 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4236 12:19:55.156518 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4237 12:19:55.159790 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4238 12:19:55.162990 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4239 12:19:55.163112
4240 12:19:55.163189
4241 12:19:55.163257 ==
4242 12:19:55.166520 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 12:19:55.169325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 12:19:55.169396 ==
4245 12:19:55.169459
4246 12:19:55.169514
4247 12:19:55.172776 TX Vref Scan disable
4248 12:19:55.176533 == TX Byte 0 ==
4249 12:19:55.179738 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4250 12:19:55.182555 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4251 12:19:55.186357 == TX Byte 1 ==
4252 12:19:55.189115 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4253 12:19:55.192387 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4254 12:19:55.192489 ==
4255 12:19:55.196843 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 12:19:55.202119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 12:19:55.202198 ==
4258 12:19:55.202259
4259 12:19:55.202316
4260 12:19:55.205622 TX Vref Scan disable
4261 12:19:55.205692 == TX Byte 0 ==
4262 12:19:55.211886 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4263 12:19:55.215524 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4264 12:19:55.215626 == TX Byte 1 ==
4265 12:19:55.221938 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4266 12:19:55.225633 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4267 12:19:55.225703
4268 12:19:55.225763 [DATLAT]
4269 12:19:55.228807 Freq=600, CH0 RK1
4270 12:19:55.228878
4271 12:19:55.228935 DATLAT Default: 0x9
4272 12:19:55.231876 0, 0xFFFF, sum = 0
4273 12:19:55.235541 1, 0xFFFF, sum = 0
4274 12:19:55.235644 2, 0xFFFF, sum = 0
4275 12:19:55.238365 3, 0xFFFF, sum = 0
4276 12:19:55.238459 4, 0xFFFF, sum = 0
4277 12:19:55.242195 5, 0xFFFF, sum = 0
4278 12:19:55.242267 6, 0xFFFF, sum = 0
4279 12:19:55.245221 7, 0xFFFF, sum = 0
4280 12:19:55.245290 8, 0x0, sum = 1
4281 12:19:55.248389 9, 0x0, sum = 2
4282 12:19:55.248456 10, 0x0, sum = 3
4283 12:19:55.251766 11, 0x0, sum = 4
4284 12:19:55.251835 best_step = 9
4285 12:19:55.251892
4286 12:19:55.251946 ==
4287 12:19:55.254587 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 12:19:55.258215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 12:19:55.258287 ==
4290 12:19:55.261448 RX Vref Scan: 0
4291 12:19:55.261535
4292 12:19:55.264909 RX Vref 0 -> 0, step: 1
4293 12:19:55.264981
4294 12:19:55.265040 RX Delay -179 -> 252, step: 8
4295 12:19:55.272380 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4296 12:19:55.275443 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4297 12:19:55.279640 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4298 12:19:55.282362 iDelay=205, Bit 3, Center 44 (-107 ~ 196) 304
4299 12:19:55.289115 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4300 12:19:55.292052 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4301 12:19:55.295378 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4302 12:19:55.299031 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4303 12:19:55.302371 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4304 12:19:55.308463 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4305 12:19:55.311830 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4306 12:19:55.314999 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4307 12:19:55.321847 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4308 12:19:55.325102 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4309 12:19:55.328506 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4310 12:19:55.331700 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4311 12:19:55.331781 ==
4312 12:19:55.335065 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 12:19:55.341318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 12:19:55.341389 ==
4315 12:19:55.341454 DQS Delay:
4316 12:19:55.344723 DQS0 = 0, DQS1 = 0
4317 12:19:55.344787 DQM Delay:
4318 12:19:55.344843 DQM0 = 45, DQM1 = 36
4319 12:19:55.348180 DQ Delay:
4320 12:19:55.351493 DQ0 =40, DQ1 =48, DQ2 =40, DQ3 =44
4321 12:19:55.354939 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =52
4322 12:19:55.357991 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =28
4323 12:19:55.361215 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4324 12:19:55.361288
4325 12:19:55.361351
4326 12:19:55.367738 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4327 12:19:55.371220 CH0 RK1: MR19=808, MR18=3D3A
4328 12:19:55.377453 CH0_RK1: MR19=0x808, MR18=0x3D3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4329 12:19:55.380861 [RxdqsGatingPostProcess] freq 600
4330 12:19:55.387510 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4331 12:19:55.387580 Pre-setting of DQS Precalculation
4332 12:19:55.394070 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4333 12:19:55.394138 ==
4334 12:19:55.397330 Dram Type= 6, Freq= 0, CH_1, rank 0
4335 12:19:55.400621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 12:19:55.400692 ==
4337 12:19:55.407041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4338 12:19:55.413897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4339 12:19:55.417091 [CA 0] Center 36 (6~66) winsize 61
4340 12:19:55.420227 [CA 1] Center 35 (5~66) winsize 62
4341 12:19:55.423918 [CA 2] Center 35 (5~65) winsize 61
4342 12:19:55.426653 [CA 3] Center 34 (3~65) winsize 63
4343 12:19:55.430439 [CA 4] Center 34 (4~65) winsize 62
4344 12:19:55.433512 [CA 5] Center 33 (3~64) winsize 62
4345 12:19:55.433577
4346 12:19:55.436814 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4347 12:19:55.436879
4348 12:19:55.439966 [CATrainingPosCal] consider 1 rank data
4349 12:19:55.443071 u2DelayCellTimex100 = 270/100 ps
4350 12:19:55.446461 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4351 12:19:55.449986 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4352 12:19:55.453217 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4353 12:19:55.456432 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4354 12:19:55.463007 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4355 12:19:55.466053 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4356 12:19:55.466121
4357 12:19:55.469980 CA PerBit enable=1, Macro0, CA PI delay=33
4358 12:19:55.470047
4359 12:19:55.472799 [CBTSetCACLKResult] CA Dly = 33
4360 12:19:55.472865 CS Dly: 5 (0~36)
4361 12:19:55.472921 ==
4362 12:19:55.476216 Dram Type= 6, Freq= 0, CH_1, rank 1
4363 12:19:55.483192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 12:19:55.483262 ==
4365 12:19:55.486161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 12:19:55.493468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4367 12:19:55.495941 [CA 0] Center 35 (5~66) winsize 62
4368 12:19:55.499801 [CA 1] Center 36 (6~66) winsize 61
4369 12:19:55.502748 [CA 2] Center 34 (4~65) winsize 62
4370 12:19:55.505837 [CA 3] Center 34 (4~65) winsize 62
4371 12:19:55.509026 [CA 4] Center 34 (3~65) winsize 63
4372 12:19:55.512441 [CA 5] Center 34 (3~65) winsize 63
4373 12:19:55.512506
4374 12:19:55.515721 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4375 12:19:55.515792
4376 12:19:55.519214 [CATrainingPosCal] consider 2 rank data
4377 12:19:55.522630 u2DelayCellTimex100 = 270/100 ps
4378 12:19:55.525712 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4379 12:19:55.532565 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4380 12:19:55.535502 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4381 12:19:55.539002 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 12:19:55.542151 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 12:19:55.545213 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 12:19:55.545281
4385 12:19:55.548438 CA PerBit enable=1, Macro0, CA PI delay=33
4386 12:19:55.548508
4387 12:19:55.551994 [CBTSetCACLKResult] CA Dly = 33
4388 12:19:55.555251 CS Dly: 5 (0~36)
4389 12:19:55.555316
4390 12:19:55.558392 ----->DramcWriteLeveling(PI) begin...
4391 12:19:55.558464 ==
4392 12:19:55.562321 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 12:19:55.565473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 12:19:55.565545 ==
4395 12:19:55.569162 Write leveling (Byte 0): 29 => 29
4396 12:19:55.571678 Write leveling (Byte 1): 32 => 32
4397 12:19:55.574942 DramcWriteLeveling(PI) end<-----
4398 12:19:55.575032
4399 12:19:55.575152 ==
4400 12:19:55.578487 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 12:19:55.581464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 12:19:55.581529 ==
4403 12:19:55.584724 [Gating] SW mode calibration
4404 12:19:55.591428 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4405 12:19:55.598388 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4406 12:19:55.601028 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 12:19:55.604294 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 12:19:55.611077 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4409 12:19:55.614481 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (0 1) (1 1)
4410 12:19:55.620681 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 12:19:55.623981 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 12:19:55.627516 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 12:19:55.634115 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 12:19:55.637424 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 12:19:55.641375 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 12:19:55.647581 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 12:19:55.650729 0 10 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
4418 12:19:55.653773 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4419 12:19:55.660811 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 12:19:55.663574 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 12:19:55.667189 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 12:19:55.673972 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 12:19:55.676780 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 12:19:55.679896 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 12:19:55.686582 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4426 12:19:55.690112 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 12:19:55.693252 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:19:55.700088 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:19:55.703302 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:19:55.706162 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:19:55.713203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:19:55.715990 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:19:55.719551 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:19:55.725979 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:19:55.729265 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:19:55.732960 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:19:55.739037 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:19:55.742299 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:19:55.746252 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:19:55.752125 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:19:55.755581 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4442 12:19:55.759067 Total UI for P1: 0, mck2ui 16
4443 12:19:55.762304 best dqsien dly found for B0: ( 0, 13, 10)
4444 12:19:55.765465 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 12:19:55.768670 Total UI for P1: 0, mck2ui 16
4446 12:19:55.772423 best dqsien dly found for B1: ( 0, 13, 12)
4447 12:19:55.775659 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4448 12:19:55.779342 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4449 12:19:55.779437
4450 12:19:55.785031 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4451 12:19:55.788776 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4452 12:19:55.792164 [Gating] SW calibration Done
4453 12:19:55.792232 ==
4454 12:19:55.795069 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 12:19:55.798099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4456 12:19:55.798171 ==
4457 12:19:55.798229 RX Vref Scan: 0
4458 12:19:55.801713
4459 12:19:55.801785 RX Vref 0 -> 0, step: 1
4460 12:19:55.801845
4461 12:19:55.805033 RX Delay -230 -> 252, step: 16
4462 12:19:55.807953 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4463 12:19:55.814828 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4464 12:19:55.818187 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4465 12:19:55.821333 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4466 12:19:55.824671 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4467 12:19:55.831163 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4468 12:19:55.834246 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4469 12:19:55.837837 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4470 12:19:55.841298 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4471 12:19:55.844493 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4472 12:19:55.850915 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4473 12:19:55.854024 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4474 12:19:55.857119 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4475 12:19:55.863678 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4476 12:19:55.867733 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4477 12:19:55.870435 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4478 12:19:55.870589 ==
4479 12:19:55.873621 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 12:19:55.876709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 12:19:55.880156 ==
4482 12:19:55.880322 DQS Delay:
4483 12:19:55.880406 DQS0 = 0, DQS1 = 0
4484 12:19:55.883850 DQM Delay:
4485 12:19:55.884017 DQM0 = 43, DQM1 = 39
4486 12:19:55.887101 DQ Delay:
4487 12:19:55.887236 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4488 12:19:55.890187 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4489 12:19:55.893283 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4490 12:19:55.897021 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4491 12:19:55.899930
4492 12:19:55.900114
4493 12:19:55.900251 ==
4494 12:19:55.903100 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 12:19:55.906545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 12:19:55.906734 ==
4497 12:19:55.906871
4498 12:19:55.907000
4499 12:19:55.909584 TX Vref Scan disable
4500 12:19:55.909772 == TX Byte 0 ==
4501 12:19:55.916897 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4502 12:19:55.919945 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4503 12:19:55.920094 == TX Byte 1 ==
4504 12:19:55.926527 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4505 12:19:55.929803 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4506 12:19:55.929923 ==
4507 12:19:55.933361 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 12:19:55.936169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 12:19:55.936289 ==
4510 12:19:55.936381
4511 12:19:55.939346
4512 12:19:55.939466 TX Vref Scan disable
4513 12:19:55.942992 == TX Byte 0 ==
4514 12:19:55.946413 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4515 12:19:55.953027 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4516 12:19:55.953195 == TX Byte 1 ==
4517 12:19:55.956364 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4518 12:19:55.962523 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4519 12:19:55.962721
4520 12:19:55.962912 [DATLAT]
4521 12:19:55.963109 Freq=600, CH1 RK0
4522 12:19:55.963285
4523 12:19:55.966172 DATLAT Default: 0x9
4524 12:19:55.969284 0, 0xFFFF, sum = 0
4525 12:19:55.969579 1, 0xFFFF, sum = 0
4526 12:19:55.973199 2, 0xFFFF, sum = 0
4527 12:19:55.973582 3, 0xFFFF, sum = 0
4528 12:19:55.976422 4, 0xFFFF, sum = 0
4529 12:19:55.976803 5, 0xFFFF, sum = 0
4530 12:19:55.979418 6, 0xFFFF, sum = 0
4531 12:19:55.979832 7, 0xFFFF, sum = 0
4532 12:19:55.982938 8, 0x0, sum = 1
4533 12:19:55.983441 9, 0x0, sum = 2
4534 12:19:55.986022 10, 0x0, sum = 3
4535 12:19:55.986436 11, 0x0, sum = 4
4536 12:19:55.986764 best_step = 9
4537 12:19:55.987111
4538 12:19:55.989055 ==
4539 12:19:55.992292 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 12:19:55.995655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 12:19:55.996066 ==
4542 12:19:55.996387 RX Vref Scan: 1
4543 12:19:55.996685
4544 12:19:55.998900 RX Vref 0 -> 0, step: 1
4545 12:19:55.999403
4546 12:19:56.002446 RX Delay -179 -> 252, step: 8
4547 12:19:56.002853
4548 12:19:56.005801 Set Vref, RX VrefLevel [Byte0]: 51
4549 12:19:56.008989 [Byte1]: 53
4550 12:19:56.009401
4551 12:19:56.012962 Final RX Vref Byte 0 = 51 to rank0
4552 12:19:56.015711 Final RX Vref Byte 1 = 53 to rank0
4553 12:19:56.019026 Final RX Vref Byte 0 = 51 to rank1
4554 12:19:56.022501 Final RX Vref Byte 1 = 53 to rank1==
4555 12:19:56.025485 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 12:19:56.032115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 12:19:56.032197 ==
4558 12:19:56.032262 DQS Delay:
4559 12:19:56.032321 DQS0 = 0, DQS1 = 0
4560 12:19:56.034990 DQM Delay:
4561 12:19:56.035075 DQM0 = 41, DQM1 = 34
4562 12:19:56.038104 DQ Delay:
4563 12:19:56.041759 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4564 12:19:56.044901 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4565 12:19:56.048360 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4566 12:19:56.051160 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4567 12:19:56.051248
4568 12:19:56.051313
4569 12:19:56.057731 [DQSOSCAuto] RK0, (LSB)MR18= 0x2740, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4570 12:19:56.061234 CH1 RK0: MR19=808, MR18=2740
4571 12:19:56.067981 CH1_RK0: MR19=0x808, MR18=0x2740, DQSOSC=397, MR23=63, INC=166, DEC=110
4572 12:19:56.068056
4573 12:19:56.070847 ----->DramcWriteLeveling(PI) begin...
4574 12:19:56.070945 ==
4575 12:19:56.074413 Dram Type= 6, Freq= 0, CH_1, rank 1
4576 12:19:56.077511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 12:19:56.077580 ==
4578 12:19:56.080859 Write leveling (Byte 0): 28 => 28
4579 12:19:56.084157 Write leveling (Byte 1): 28 => 28
4580 12:19:56.087311 DramcWriteLeveling(PI) end<-----
4581 12:19:56.087381
4582 12:19:56.087438 ==
4583 12:19:56.091077 Dram Type= 6, Freq= 0, CH_1, rank 1
4584 12:19:56.093938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 12:19:56.097392 ==
4586 12:19:56.097460 [Gating] SW mode calibration
4587 12:19:56.107027 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4588 12:19:56.110810 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4589 12:19:56.113802 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4590 12:19:56.120198 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 12:19:56.123901 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4592 12:19:56.126836 0 9 12 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
4593 12:19:56.133556 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4594 12:19:56.137037 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 12:19:56.139871 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 12:19:56.146684 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 12:19:56.150612 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 12:19:56.153630 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 12:19:56.159614 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4600 12:19:56.162924 0 10 12 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (1 1)
4601 12:19:56.166240 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4602 12:19:56.173957 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 12:19:56.176283 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 12:19:56.182838 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 12:19:56.185731 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 12:19:56.189297 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 12:19:56.196478 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 12:19:56.199604 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4609 12:19:56.202339 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 12:19:56.209435 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:19:56.212580 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:19:56.215552 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:19:56.222165 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:19:56.225461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 12:19:56.228841 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:19:56.235428 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:19:56.238341 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:19:56.241810 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:19:56.248071 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:19:56.251452 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:19:56.254707 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:19:56.261545 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:19:56.265071 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4624 12:19:56.268020 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4625 12:19:56.274965 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4626 12:19:56.275071 Total UI for P1: 0, mck2ui 16
4627 12:19:56.281541 best dqsien dly found for B0: ( 0, 13, 10)
4628 12:19:56.284480 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 12:19:56.287727 Total UI for P1: 0, mck2ui 16
4630 12:19:56.291378 best dqsien dly found for B1: ( 0, 13, 16)
4631 12:19:56.294462 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4632 12:19:56.297762 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4633 12:19:56.297841
4634 12:19:56.301344 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4635 12:19:56.304750 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4636 12:19:56.307659 [Gating] SW calibration Done
4637 12:19:56.307740 ==
4638 12:19:56.311106 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 12:19:56.317317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 12:19:56.317398 ==
4641 12:19:56.317460 RX Vref Scan: 0
4642 12:19:56.317518
4643 12:19:56.320702 RX Vref 0 -> 0, step: 1
4644 12:19:56.320782
4645 12:19:56.324668 RX Delay -230 -> 252, step: 16
4646 12:19:56.327387 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4647 12:19:56.330446 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4648 12:19:56.333855 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4649 12:19:56.340411 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4650 12:19:56.344001 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4651 12:19:56.347276 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4652 12:19:56.350384 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4653 12:19:56.357119 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4654 12:19:56.360168 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4655 12:19:56.363270 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4656 12:19:56.366902 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4657 12:19:56.373104 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4658 12:19:56.376482 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4659 12:19:56.379946 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4660 12:19:56.383125 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4661 12:19:56.389834 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4662 12:19:56.389914 ==
4663 12:19:56.393377 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 12:19:56.396326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 12:19:56.396406 ==
4666 12:19:56.396468 DQS Delay:
4667 12:19:56.399964 DQS0 = 0, DQS1 = 0
4668 12:19:56.400043 DQM Delay:
4669 12:19:56.402944 DQM0 = 40, DQM1 = 38
4670 12:19:56.403081 DQ Delay:
4671 12:19:56.406674 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4672 12:19:56.409593 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4673 12:19:56.412561 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4674 12:19:56.415795 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4675 12:19:56.415876
4676 12:19:56.415938
4677 12:19:56.415996 ==
4678 12:19:56.419482 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 12:19:56.422461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 12:19:56.425945 ==
4681 12:19:56.426050
4682 12:19:56.426142
4683 12:19:56.426209 TX Vref Scan disable
4684 12:19:56.429685 == TX Byte 0 ==
4685 12:19:56.432614 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4686 12:19:56.439269 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4687 12:19:56.439349 == TX Byte 1 ==
4688 12:19:56.442524 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4689 12:19:56.449328 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4690 12:19:56.449408 ==
4691 12:19:56.452132 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 12:19:56.455444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 12:19:56.455525 ==
4694 12:19:56.455587
4695 12:19:56.455645
4696 12:19:56.458740 TX Vref Scan disable
4697 12:19:56.461940 == TX Byte 0 ==
4698 12:19:56.465045 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4699 12:19:56.468741 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4700 12:19:56.471945 == TX Byte 1 ==
4701 12:19:56.475384 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4702 12:19:56.478319 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4703 12:19:56.478399
4704 12:19:56.478461 [DATLAT]
4705 12:19:56.481435 Freq=600, CH1 RK1
4706 12:19:56.481515
4707 12:19:56.484938 DATLAT Default: 0x9
4708 12:19:56.485018 0, 0xFFFF, sum = 0
4709 12:19:56.488357 1, 0xFFFF, sum = 0
4710 12:19:56.488438 2, 0xFFFF, sum = 0
4711 12:19:56.491433 3, 0xFFFF, sum = 0
4712 12:19:56.491513 4, 0xFFFF, sum = 0
4713 12:19:56.494735 5, 0xFFFF, sum = 0
4714 12:19:56.494816 6, 0xFFFF, sum = 0
4715 12:19:56.498770 7, 0xFFFF, sum = 0
4716 12:19:56.498851 8, 0x0, sum = 1
4717 12:19:56.501297 9, 0x0, sum = 2
4718 12:19:56.501379 10, 0x0, sum = 3
4719 12:19:56.504782 11, 0x0, sum = 4
4720 12:19:56.504863 best_step = 9
4721 12:19:56.504925
4722 12:19:56.504982 ==
4723 12:19:56.507992 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 12:19:56.511497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 12:19:56.515136 ==
4726 12:19:56.515229 RX Vref Scan: 0
4727 12:19:56.515332
4728 12:19:56.517854 RX Vref 0 -> 0, step: 1
4729 12:19:56.517933
4730 12:19:56.521262 RX Delay -179 -> 252, step: 8
4731 12:19:56.524046 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4732 12:19:56.527475 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4733 12:19:56.533987 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4734 12:19:56.537698 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4735 12:19:56.541057 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4736 12:19:56.543902 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4737 12:19:56.550880 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4738 12:19:56.554023 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4739 12:19:56.557191 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4740 12:19:56.560584 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4741 12:19:56.566959 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4742 12:19:56.570765 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4743 12:19:56.573979 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4744 12:19:56.577811 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4745 12:19:56.583640 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4746 12:19:56.587619 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4747 12:19:56.587699 ==
4748 12:19:56.590662 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 12:19:56.593442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 12:19:56.593522 ==
4751 12:19:56.596941 DQS Delay:
4752 12:19:56.597020 DQS0 = 0, DQS1 = 0
4753 12:19:56.597083 DQM Delay:
4754 12:19:56.600286 DQM0 = 38, DQM1 = 35
4755 12:19:56.600365 DQ Delay:
4756 12:19:56.603443 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4757 12:19:56.606399 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4758 12:19:56.610317 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4759 12:19:56.613118 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4760 12:19:56.613197
4761 12:19:56.613259
4762 12:19:56.623380 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f54, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4763 12:19:56.626380 CH1 RK1: MR19=808, MR18=2F54
4764 12:19:56.629622 CH1_RK1: MR19=0x808, MR18=0x2F54, DQSOSC=393, MR23=63, INC=169, DEC=113
4765 12:19:56.632990 [RxdqsGatingPostProcess] freq 600
4766 12:19:56.639566 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4767 12:19:56.643104 Pre-setting of DQS Precalculation
4768 12:19:56.646148 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4769 12:19:56.655995 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4770 12:19:56.662356 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4771 12:19:56.662437
4772 12:19:56.662499
4773 12:19:56.665640 [Calibration Summary] 1200 Mbps
4774 12:19:56.665719 CH 0, Rank 0
4775 12:19:56.668923 SW Impedance : PASS
4776 12:19:56.669003 DUTY Scan : NO K
4777 12:19:56.672718 ZQ Calibration : PASS
4778 12:19:56.675478 Jitter Meter : NO K
4779 12:19:56.675558 CBT Training : PASS
4780 12:19:56.679030 Write leveling : PASS
4781 12:19:56.682669 RX DQS gating : PASS
4782 12:19:56.682800 RX DQ/DQS(RDDQC) : PASS
4783 12:19:56.685538 TX DQ/DQS : PASS
4784 12:19:56.689414 RX DATLAT : PASS
4785 12:19:56.689493 RX DQ/DQS(Engine): PASS
4786 12:19:56.692040 TX OE : NO K
4787 12:19:56.692119 All Pass.
4788 12:19:56.692181
4789 12:19:56.695692 CH 0, Rank 1
4790 12:19:56.695771 SW Impedance : PASS
4791 12:19:56.699186 DUTY Scan : NO K
4792 12:19:56.702632 ZQ Calibration : PASS
4793 12:19:56.702711 Jitter Meter : NO K
4794 12:19:56.705372 CBT Training : PASS
4795 12:19:56.708306 Write leveling : PASS
4796 12:19:56.708385 RX DQS gating : PASS
4797 12:19:56.712140 RX DQ/DQS(RDDQC) : PASS
4798 12:19:56.715327 TX DQ/DQS : PASS
4799 12:19:56.715407 RX DATLAT : PASS
4800 12:19:56.718242 RX DQ/DQS(Engine): PASS
4801 12:19:56.721375 TX OE : NO K
4802 12:19:56.721455 All Pass.
4803 12:19:56.721517
4804 12:19:56.721574 CH 1, Rank 0
4805 12:19:56.725592 SW Impedance : PASS
4806 12:19:56.728300 DUTY Scan : NO K
4807 12:19:56.728379 ZQ Calibration : PASS
4808 12:19:56.731645 Jitter Meter : NO K
4809 12:19:56.735838 CBT Training : PASS
4810 12:19:56.735917 Write leveling : PASS
4811 12:19:56.738230 RX DQS gating : PASS
4812 12:19:56.741604 RX DQ/DQS(RDDQC) : PASS
4813 12:19:56.741742 TX DQ/DQS : PASS
4814 12:19:56.744606 RX DATLAT : PASS
4815 12:19:56.744705 RX DQ/DQS(Engine): PASS
4816 12:19:56.747982 TX OE : NO K
4817 12:19:56.748062 All Pass.
4818 12:19:56.748124
4819 12:19:56.751670 CH 1, Rank 1
4820 12:19:56.751750 SW Impedance : PASS
4821 12:19:56.754726 DUTY Scan : NO K
4822 12:19:56.757889 ZQ Calibration : PASS
4823 12:19:56.757969 Jitter Meter : NO K
4824 12:19:56.761124 CBT Training : PASS
4825 12:19:56.764880 Write leveling : PASS
4826 12:19:56.764959 RX DQS gating : PASS
4827 12:19:56.767811 RX DQ/DQS(RDDQC) : PASS
4828 12:19:56.771069 TX DQ/DQS : PASS
4829 12:19:56.771171 RX DATLAT : PASS
4830 12:19:56.774159 RX DQ/DQS(Engine): PASS
4831 12:19:56.777544 TX OE : NO K
4832 12:19:56.777624 All Pass.
4833 12:19:56.777686
4834 12:19:56.780792 DramC Write-DBI off
4835 12:19:56.780872 PER_BANK_REFRESH: Hybrid Mode
4836 12:19:56.784050 TX_TRACKING: ON
4837 12:19:56.794390 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4838 12:19:56.797379 [FAST_K] Save calibration result to emmc
4839 12:19:56.800831 dramc_set_vcore_voltage set vcore to 662500
4840 12:19:56.800911 Read voltage for 933, 3
4841 12:19:56.804049 Vio18 = 0
4842 12:19:56.804128 Vcore = 662500
4843 12:19:56.804190 Vdram = 0
4844 12:19:56.807474 Vddq = 0
4845 12:19:56.807554 Vmddr = 0
4846 12:19:56.814471 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4847 12:19:56.817482 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4848 12:19:56.820312 MEM_TYPE=3, freq_sel=17
4849 12:19:56.823954 sv_algorithm_assistance_LP4_1600
4850 12:19:56.827105 ============ PULL DRAM RESETB DOWN ============
4851 12:19:56.830121 ========== PULL DRAM RESETB DOWN end =========
4852 12:19:56.836600 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 12:19:56.840236 ===================================
4854 12:19:56.840315 LPDDR4 DRAM CONFIGURATION
4855 12:19:56.843187 ===================================
4856 12:19:56.847194 EX_ROW_EN[0] = 0x0
4857 12:19:56.849750 EX_ROW_EN[1] = 0x0
4858 12:19:56.849850 LP4Y_EN = 0x0
4859 12:19:56.852976 WORK_FSP = 0x0
4860 12:19:56.853056 WL = 0x3
4861 12:19:56.856226 RL = 0x3
4862 12:19:56.856305 BL = 0x2
4863 12:19:56.859629 RPST = 0x0
4864 12:19:56.859707 RD_PRE = 0x0
4865 12:19:56.863117 WR_PRE = 0x1
4866 12:19:56.863197 WR_PST = 0x0
4867 12:19:56.866740 DBI_WR = 0x0
4868 12:19:56.866819 DBI_RD = 0x0
4869 12:19:56.869905 OTF = 0x1
4870 12:19:56.872786 ===================================
4871 12:19:56.876359 ===================================
4872 12:19:56.876439 ANA top config
4873 12:19:56.879580 ===================================
4874 12:19:56.883514 DLL_ASYNC_EN = 0
4875 12:19:56.886068 ALL_SLAVE_EN = 1
4876 12:19:56.889357 NEW_RANK_MODE = 1
4877 12:19:56.889437 DLL_IDLE_MODE = 1
4878 12:19:56.892682 LP45_APHY_COMB_EN = 1
4879 12:19:56.895985 TX_ODT_DIS = 1
4880 12:19:56.899261 NEW_8X_MODE = 1
4881 12:19:56.902330 ===================================
4882 12:19:56.905716 ===================================
4883 12:19:56.909349 data_rate = 1866
4884 12:19:56.912610 CKR = 1
4885 12:19:56.912690 DQ_P2S_RATIO = 8
4886 12:19:56.916421 ===================================
4887 12:19:56.919122 CA_P2S_RATIO = 8
4888 12:19:56.922622 DQ_CA_OPEN = 0
4889 12:19:56.925535 DQ_SEMI_OPEN = 0
4890 12:19:56.928993 CA_SEMI_OPEN = 0
4891 12:19:56.932227 CA_FULL_RATE = 0
4892 12:19:56.932307 DQ_CKDIV4_EN = 1
4893 12:19:56.935446 CA_CKDIV4_EN = 1
4894 12:19:56.938930 CA_PREDIV_EN = 0
4895 12:19:56.941851 PH8_DLY = 0
4896 12:19:56.945623 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4897 12:19:56.948454 DQ_AAMCK_DIV = 4
4898 12:19:56.948537 CA_AAMCK_DIV = 4
4899 12:19:56.951722 CA_ADMCK_DIV = 4
4900 12:19:56.955056 DQ_TRACK_CA_EN = 0
4901 12:19:56.958212 CA_PICK = 933
4902 12:19:56.961536 CA_MCKIO = 933
4903 12:19:56.965046 MCKIO_SEMI = 0
4904 12:19:56.968220 PLL_FREQ = 3732
4905 12:19:56.971407 DQ_UI_PI_RATIO = 32
4906 12:19:56.971488 CA_UI_PI_RATIO = 0
4907 12:19:56.975047 ===================================
4908 12:19:56.978135 ===================================
4909 12:19:56.981123 memory_type:LPDDR4
4910 12:19:56.984720 GP_NUM : 10
4911 12:19:56.984801 SRAM_EN : 1
4912 12:19:56.988095 MD32_EN : 0
4913 12:19:56.991254 ===================================
4914 12:19:56.994517 [ANA_INIT] >>>>>>>>>>>>>>
4915 12:19:56.997902 <<<<<< [CONFIGURE PHASE]: ANA_TX
4916 12:19:57.001710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4917 12:19:57.004153 ===================================
4918 12:19:57.004234 data_rate = 1866,PCW = 0X8f00
4919 12:19:57.007749 ===================================
4920 12:19:57.014443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4921 12:19:57.018192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 12:19:57.024090 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 12:19:57.027772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4924 12:19:57.031219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4925 12:19:57.034320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4926 12:19:57.037451 [ANA_INIT] flow start
4927 12:19:57.040625 [ANA_INIT] PLL >>>>>>>>
4928 12:19:57.040705 [ANA_INIT] PLL <<<<<<<<
4929 12:19:57.043548 [ANA_INIT] MIDPI >>>>>>>>
4930 12:19:57.047045 [ANA_INIT] MIDPI <<<<<<<<
4931 12:19:57.050196 [ANA_INIT] DLL >>>>>>>>
4932 12:19:57.050275 [ANA_INIT] flow end
4933 12:19:57.053364 ============ LP4 DIFF to SE enter ============
4934 12:19:57.060073 ============ LP4 DIFF to SE exit ============
4935 12:19:57.060154 [ANA_INIT] <<<<<<<<<<<<<
4936 12:19:57.063263 [Flow] Enable top DCM control >>>>>
4937 12:19:57.066723 [Flow] Enable top DCM control <<<<<
4938 12:19:57.069966 Enable DLL master slave shuffle
4939 12:19:57.076714 ==============================================================
4940 12:19:57.076794 Gating Mode config
4941 12:19:57.083078 ==============================================================
4942 12:19:57.086722 Config description:
4943 12:19:57.096876 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4944 12:19:57.103133 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4945 12:19:57.105990 SELPH_MODE 0: By rank 1: By Phase
4946 12:19:57.112616 ==============================================================
4947 12:19:57.115867 GAT_TRACK_EN = 1
4948 12:19:57.119139 RX_GATING_MODE = 2
4949 12:19:57.122401 RX_GATING_TRACK_MODE = 2
4950 12:19:57.122481 SELPH_MODE = 1
4951 12:19:57.125784 PICG_EARLY_EN = 1
4952 12:19:57.129367 VALID_LAT_VALUE = 1
4953 12:19:57.135468 ==============================================================
4954 12:19:57.138704 Enter into Gating configuration >>>>
4955 12:19:57.141943 Exit from Gating configuration <<<<
4956 12:19:57.145244 Enter into DVFS_PRE_config >>>>>
4957 12:19:57.155272 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4958 12:19:57.158753 Exit from DVFS_PRE_config <<<<<
4959 12:19:57.161879 Enter into PICG configuration >>>>
4960 12:19:57.165382 Exit from PICG configuration <<<<
4961 12:19:57.168530 [RX_INPUT] configuration >>>>>
4962 12:19:57.171485 [RX_INPUT] configuration <<<<<
4963 12:19:57.178084 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4964 12:19:57.181646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4965 12:19:57.188250 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 12:19:57.194957 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 12:19:57.201470 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 12:19:57.208007 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 12:19:57.211085 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4970 12:19:57.214836 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4971 12:19:57.218093 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4972 12:19:57.224640 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4973 12:19:57.227574 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4974 12:19:57.230919 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 12:19:57.234153 ===================================
4976 12:19:57.237753 LPDDR4 DRAM CONFIGURATION
4977 12:19:57.240722 ===================================
4978 12:19:57.244358 EX_ROW_EN[0] = 0x0
4979 12:19:57.244437 EX_ROW_EN[1] = 0x0
4980 12:19:57.247834 LP4Y_EN = 0x0
4981 12:19:57.247913 WORK_FSP = 0x0
4982 12:19:57.250862 WL = 0x3
4983 12:19:57.250941 RL = 0x3
4984 12:19:57.254136 BL = 0x2
4985 12:19:57.254216 RPST = 0x0
4986 12:19:57.257379 RD_PRE = 0x0
4987 12:19:57.257458 WR_PRE = 0x1
4988 12:19:57.260446 WR_PST = 0x0
4989 12:19:57.260526 DBI_WR = 0x0
4990 12:19:57.263562 DBI_RD = 0x0
4991 12:19:57.263641 OTF = 0x1
4992 12:19:57.266935 ===================================
4993 12:19:57.273877 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4994 12:19:57.276769 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4995 12:19:57.280021 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 12:19:57.283506 ===================================
4997 12:19:57.286876 LPDDR4 DRAM CONFIGURATION
4998 12:19:57.290452 ===================================
4999 12:19:57.293375 EX_ROW_EN[0] = 0x10
5000 12:19:57.293455 EX_ROW_EN[1] = 0x0
5001 12:19:57.297072 LP4Y_EN = 0x0
5002 12:19:57.297151 WORK_FSP = 0x0
5003 12:19:57.300363 WL = 0x3
5004 12:19:57.300443 RL = 0x3
5005 12:19:57.303214 BL = 0x2
5006 12:19:57.303293 RPST = 0x0
5007 12:19:57.306671 RD_PRE = 0x0
5008 12:19:57.306751 WR_PRE = 0x1
5009 12:19:57.310152 WR_PST = 0x0
5010 12:19:57.310231 DBI_WR = 0x0
5011 12:19:57.313461 DBI_RD = 0x0
5012 12:19:57.313543 OTF = 0x1
5013 12:19:57.316516 ===================================
5014 12:19:57.323120 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5015 12:19:57.328124 nWR fixed to 30
5016 12:19:57.331775 [ModeRegInit_LP4] CH0 RK0
5017 12:19:57.331855 [ModeRegInit_LP4] CH0 RK1
5018 12:19:57.334858 [ModeRegInit_LP4] CH1 RK0
5019 12:19:57.338060 [ModeRegInit_LP4] CH1 RK1
5020 12:19:57.338161 match AC timing 9
5021 12:19:57.344394 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5022 12:19:57.347754 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5023 12:19:57.350980 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5024 12:19:57.357645 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5025 12:19:57.361038 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5026 12:19:57.361123 ==
5027 12:19:57.364131 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 12:19:57.367357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5029 12:19:57.370560 ==
5030 12:19:57.373775 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5031 12:19:57.380986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5032 12:19:57.383975 [CA 0] Center 38 (7~69) winsize 63
5033 12:19:57.387416 [CA 1] Center 37 (7~68) winsize 62
5034 12:19:57.390514 [CA 2] Center 34 (4~65) winsize 62
5035 12:19:57.393673 [CA 3] Center 34 (4~65) winsize 62
5036 12:19:57.396919 [CA 4] Center 33 (3~64) winsize 62
5037 12:19:57.400394 [CA 5] Center 33 (3~63) winsize 61
5038 12:19:57.400496
5039 12:19:57.403887 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5040 12:19:57.403960
5041 12:19:57.406878 [CATrainingPosCal] consider 1 rank data
5042 12:19:57.410297 u2DelayCellTimex100 = 270/100 ps
5043 12:19:57.413722 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5044 12:19:57.417172 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5045 12:19:57.420032 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5046 12:19:57.426784 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5047 12:19:57.430447 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5048 12:19:57.433387 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5049 12:19:57.433457
5050 12:19:57.436620 CA PerBit enable=1, Macro0, CA PI delay=33
5051 12:19:57.436693
5052 12:19:57.440049 [CBTSetCACLKResult] CA Dly = 33
5053 12:19:57.440119 CS Dly: 6 (0~37)
5054 12:19:57.440183 ==
5055 12:19:57.443107 Dram Type= 6, Freq= 0, CH_0, rank 1
5056 12:19:57.449486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 12:19:57.449561 ==
5058 12:19:57.452828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 12:19:57.459478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5060 12:19:57.463272 [CA 0] Center 38 (8~69) winsize 62
5061 12:19:57.466408 [CA 1] Center 38 (7~69) winsize 63
5062 12:19:57.469484 [CA 2] Center 34 (4~65) winsize 62
5063 12:19:57.472641 [CA 3] Center 34 (4~65) winsize 62
5064 12:19:57.476288 [CA 4] Center 33 (3~64) winsize 62
5065 12:19:57.479318 [CA 5] Center 33 (3~64) winsize 62
5066 12:19:57.479417
5067 12:19:57.482689 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5068 12:19:57.482786
5069 12:19:57.486012 [CATrainingPosCal] consider 2 rank data
5070 12:19:57.489124 u2DelayCellTimex100 = 270/100 ps
5071 12:19:57.492687 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5072 12:19:57.499171 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5073 12:19:57.502476 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5074 12:19:57.505978 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5075 12:19:57.509568 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5076 12:19:57.512337 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5077 12:19:57.512408
5078 12:19:57.515721 CA PerBit enable=1, Macro0, CA PI delay=33
5079 12:19:57.515794
5080 12:19:57.519127 [CBTSetCACLKResult] CA Dly = 33
5081 12:19:57.522175 CS Dly: 7 (0~39)
5082 12:19:57.522272
5083 12:19:57.526501 ----->DramcWriteLeveling(PI) begin...
5084 12:19:57.526575 ==
5085 12:19:57.528738 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 12:19:57.532232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 12:19:57.532304 ==
5088 12:19:57.535675 Write leveling (Byte 0): 30 => 30
5089 12:19:57.538847 Write leveling (Byte 1): 30 => 30
5090 12:19:57.542421 DramcWriteLeveling(PI) end<-----
5091 12:19:57.542518
5092 12:19:57.542620 ==
5093 12:19:57.545784 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 12:19:57.549241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 12:19:57.549313 ==
5096 12:19:57.552062 [Gating] SW mode calibration
5097 12:19:57.558321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 12:19:57.564967 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5099 12:19:57.568821 0 14 0 | B1->B0 | 2323 3131 | 1 1 | (1 1) (1 1)
5100 12:19:57.574938 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5101 12:19:57.578448 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 12:19:57.581808 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 12:19:57.588131 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 12:19:57.591341 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 12:19:57.594454 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5106 12:19:57.601677 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5107 12:19:57.604495 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
5108 12:19:57.607903 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 12:19:57.614630 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 12:19:57.617681 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 12:19:57.621361 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 12:19:57.627674 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 12:19:57.630958 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 12:19:57.634145 0 15 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5115 12:19:57.640827 1 0 0 | B1->B0 | 3434 4545 | 1 0 | (0 0) (0 0)
5116 12:19:57.643766 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 12:19:57.647206 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 12:19:57.653609 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 12:19:57.657415 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 12:19:57.660456 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 12:19:57.667498 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 12:19:57.670364 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5123 12:19:57.674397 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5124 12:19:57.680126 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 12:19:57.683198 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:19:57.686529 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:19:57.693488 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:19:57.696617 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:19:57.699846 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:19:57.706708 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:19:57.709925 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:19:57.712866 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:19:57.719939 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:19:57.722939 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:19:57.726341 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:19:57.733229 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:19:57.736235 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5138 12:19:57.739391 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 12:19:57.746701 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5140 12:19:57.746781 Total UI for P1: 0, mck2ui 16
5141 12:19:57.752520 best dqsien dly found for B0: ( 1, 2, 30)
5142 12:19:57.756217 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5143 12:19:57.759119 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 12:19:57.762505 Total UI for P1: 0, mck2ui 16
5145 12:19:57.765628 best dqsien dly found for B1: ( 1, 3, 2)
5146 12:19:57.768669 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5147 12:19:57.771920 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5148 12:19:57.772000
5149 12:19:57.778685 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5150 12:19:57.782142 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5151 12:19:57.784923 [Gating] SW calibration Done
5152 12:19:57.785002 ==
5153 12:19:57.788623 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 12:19:57.791527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 12:19:57.791608 ==
5156 12:19:57.791669 RX Vref Scan: 0
5157 12:19:57.791727
5158 12:19:57.795895 RX Vref 0 -> 0, step: 1
5159 12:19:57.795974
5160 12:19:57.798599 RX Delay -80 -> 252, step: 8
5161 12:19:57.802156 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5162 12:19:57.805204 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5163 12:19:57.811681 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5164 12:19:57.814794 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5165 12:19:57.818180 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5166 12:19:57.821055 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5167 12:19:57.824898 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5168 12:19:57.831363 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5169 12:19:57.834886 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5170 12:19:57.837934 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5171 12:19:57.841031 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5172 12:19:57.844242 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5173 12:19:57.850682 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5174 12:19:57.854106 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5175 12:19:57.857598 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5176 12:19:57.861093 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5177 12:19:57.861190 ==
5178 12:19:57.864280 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 12:19:57.867328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 12:19:57.867409 ==
5181 12:19:57.870571 DQS Delay:
5182 12:19:57.870650 DQS0 = 0, DQS1 = 0
5183 12:19:57.873905 DQM Delay:
5184 12:19:57.873985 DQM0 = 103, DQM1 = 89
5185 12:19:57.877356 DQ Delay:
5186 12:19:57.880594 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5187 12:19:57.883623 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =107
5188 12:19:57.887279 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5189 12:19:57.890412 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5190 12:19:57.890492
5191 12:19:57.890554
5192 12:19:57.890612 ==
5193 12:19:57.893653 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 12:19:57.897062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 12:19:57.897142 ==
5196 12:19:57.897204
5197 12:19:57.897261
5198 12:19:57.900508 TX Vref Scan disable
5199 12:19:57.900587 == TX Byte 0 ==
5200 12:19:57.907239 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5201 12:19:57.910210 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5202 12:19:57.910289 == TX Byte 1 ==
5203 12:19:57.916919 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5204 12:19:57.920041 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5205 12:19:57.920121 ==
5206 12:19:57.923282 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 12:19:57.926754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 12:19:57.926834 ==
5209 12:19:57.930394
5210 12:19:57.930472
5211 12:19:57.930534 TX Vref Scan disable
5212 12:19:57.933748 == TX Byte 0 ==
5213 12:19:57.936803 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5214 12:19:57.943113 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5215 12:19:57.943206 == TX Byte 1 ==
5216 12:19:57.946505 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5217 12:19:57.953454 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5218 12:19:57.953534
5219 12:19:57.953596 [DATLAT]
5220 12:19:57.953653 Freq=933, CH0 RK0
5221 12:19:57.953709
5222 12:19:57.956651 DATLAT Default: 0xd
5223 12:19:57.959721 0, 0xFFFF, sum = 0
5224 12:19:57.959802 1, 0xFFFF, sum = 0
5225 12:19:57.962912 2, 0xFFFF, sum = 0
5226 12:19:57.962993 3, 0xFFFF, sum = 0
5227 12:19:57.966330 4, 0xFFFF, sum = 0
5228 12:19:57.966412 5, 0xFFFF, sum = 0
5229 12:19:57.969943 6, 0xFFFF, sum = 0
5230 12:19:57.970024 7, 0xFFFF, sum = 0
5231 12:19:57.972772 8, 0xFFFF, sum = 0
5232 12:19:57.972853 9, 0xFFFF, sum = 0
5233 12:19:57.976085 10, 0x0, sum = 1
5234 12:19:57.976165 11, 0x0, sum = 2
5235 12:19:57.979527 12, 0x0, sum = 3
5236 12:19:57.979608 13, 0x0, sum = 4
5237 12:19:57.982920 best_step = 11
5238 12:19:57.982999
5239 12:19:57.983061 ==
5240 12:19:57.985920 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 12:19:57.989510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 12:19:57.989590 ==
5243 12:19:57.989670 RX Vref Scan: 1
5244 12:19:57.992762
5245 12:19:57.992841 RX Vref 0 -> 0, step: 1
5246 12:19:57.992903
5247 12:19:57.996388 RX Delay -69 -> 252, step: 4
5248 12:19:57.996468
5249 12:19:57.998932 Set Vref, RX VrefLevel [Byte0]: 59
5250 12:19:58.003007 [Byte1]: 49
5251 12:19:58.005707
5252 12:19:58.005786 Final RX Vref Byte 0 = 59 to rank0
5253 12:19:58.009312 Final RX Vref Byte 1 = 49 to rank0
5254 12:19:58.012982 Final RX Vref Byte 0 = 59 to rank1
5255 12:19:58.015657 Final RX Vref Byte 1 = 49 to rank1==
5256 12:19:58.018985 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 12:19:58.025539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 12:19:58.025619 ==
5259 12:19:58.025682 DQS Delay:
5260 12:19:58.028718 DQS0 = 0, DQS1 = 0
5261 12:19:58.028797 DQM Delay:
5262 12:19:58.028859 DQM0 = 103, DQM1 = 89
5263 12:19:58.032490 DQ Delay:
5264 12:19:58.035718 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =98
5265 12:19:58.039059 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5266 12:19:58.042062 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =86
5267 12:19:58.045390 DQ12 =98, DQ13 =92, DQ14 =96, DQ15 =98
5268 12:19:58.045470
5269 12:19:58.045533
5270 12:19:58.052360 [DQSOSCAuto] RK0, (LSB)MR18= 0x110b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 416 ps
5271 12:19:58.055358 CH0 RK0: MR19=505, MR18=110B
5272 12:19:58.061960 CH0_RK0: MR19=0x505, MR18=0x110B, DQSOSC=416, MR23=63, INC=62, DEC=41
5273 12:19:58.062040
5274 12:19:58.065239 ----->DramcWriteLeveling(PI) begin...
5275 12:19:58.065320 ==
5276 12:19:58.068757 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 12:19:58.071725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 12:19:58.075394 ==
5279 12:19:58.075474 Write leveling (Byte 0): 32 => 32
5280 12:19:58.078102 Write leveling (Byte 1): 26 => 26
5281 12:19:58.081547 DramcWriteLeveling(PI) end<-----
5282 12:19:58.081626
5283 12:19:58.081687 ==
5284 12:19:58.084870 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 12:19:58.091734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 12:19:58.091813 ==
5287 12:19:58.094534 [Gating] SW mode calibration
5288 12:19:58.101149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5289 12:19:58.104753 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5290 12:19:58.111444 0 14 0 | B1->B0 | 2828 3333 | 0 1 | (0 0) (1 1)
5291 12:19:58.114747 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 12:19:58.117749 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 12:19:58.124285 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 12:19:58.127373 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 12:19:58.130972 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 12:19:58.137143 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 12:19:58.140709 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5298 12:19:58.143815 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
5299 12:19:58.150467 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5300 12:19:58.154249 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 12:19:58.157219 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 12:19:58.163635 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 12:19:58.167308 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 12:19:58.170324 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 12:19:58.176673 0 15 28 | B1->B0 | 2727 3b3b | 0 0 | (0 0) (0 0)
5306 12:19:58.180209 1 0 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5307 12:19:58.183388 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 12:19:58.189852 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 12:19:58.193926 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 12:19:58.196475 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 12:19:58.202964 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 12:19:58.206595 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5313 12:19:58.210147 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5314 12:19:58.216271 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:19:58.219467 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 12:19:58.222753 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 12:19:58.229136 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:19:58.233328 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:19:58.236045 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:19:58.242544 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:19:58.245858 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:19:58.249193 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:19:58.255666 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:19:58.258933 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:19:58.262041 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:19:58.269265 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:19:58.272568 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:19:58.275686 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5329 12:19:58.281739 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5330 12:19:58.285564 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5331 12:19:58.288757 Total UI for P1: 0, mck2ui 16
5332 12:19:58.291676 best dqsien dly found for B0: ( 1, 2, 26)
5333 12:19:58.295320 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 12:19:58.298339 Total UI for P1: 0, mck2ui 16
5335 12:19:58.301981 best dqsien dly found for B1: ( 1, 3, 0)
5336 12:19:58.305212 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5337 12:19:58.312103 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5338 12:19:58.312184
5339 12:19:58.314793 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5340 12:19:58.318241 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5341 12:19:58.321455 [Gating] SW calibration Done
5342 12:19:58.321535 ==
5343 12:19:58.324952 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 12:19:58.328379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 12:19:58.328459 ==
5346 12:19:58.330986 RX Vref Scan: 0
5347 12:19:58.331065
5348 12:19:58.331142 RX Vref 0 -> 0, step: 1
5349 12:19:58.331200
5350 12:19:58.334337 RX Delay -80 -> 252, step: 8
5351 12:19:58.338124 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5352 12:19:58.344165 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5353 12:19:58.347482 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5354 12:19:58.351012 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5355 12:19:58.353907 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5356 12:19:58.357455 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5357 12:19:58.364370 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5358 12:19:58.367331 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5359 12:19:58.370655 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5360 12:19:58.374227 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5361 12:19:58.376933 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5362 12:19:58.380286 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5363 12:19:58.386647 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5364 12:19:58.390518 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5365 12:19:58.393297 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5366 12:19:58.396834 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5367 12:19:58.396913 ==
5368 12:19:58.399914 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 12:19:58.406505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 12:19:58.406585 ==
5371 12:19:58.406647 DQS Delay:
5372 12:19:58.406704 DQS0 = 0, DQS1 = 0
5373 12:19:58.409683 DQM Delay:
5374 12:19:58.409762 DQM0 = 102, DQM1 = 89
5375 12:19:58.413132 DQ Delay:
5376 12:19:58.416716 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =95
5377 12:19:58.419983 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =107
5378 12:19:58.424005 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5379 12:19:58.426733 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5380 12:19:58.426812
5381 12:19:58.426873
5382 12:19:58.426930 ==
5383 12:19:58.429555 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 12:19:58.432931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 12:19:58.433010 ==
5386 12:19:58.433072
5387 12:19:58.433128
5388 12:19:58.436412 TX Vref Scan disable
5389 12:19:58.439883 == TX Byte 0 ==
5390 12:19:58.443269 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5391 12:19:58.446268 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5392 12:19:58.449460 == TX Byte 1 ==
5393 12:19:58.452725 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5394 12:19:58.455890 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5395 12:19:58.455969 ==
5396 12:19:58.459446 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 12:19:58.465776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 12:19:58.465857 ==
5399 12:19:58.465920
5400 12:19:58.465978
5401 12:19:58.466035 TX Vref Scan disable
5402 12:19:58.470144 == TX Byte 0 ==
5403 12:19:58.473138 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5404 12:19:58.480093 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5405 12:19:58.480173 == TX Byte 1 ==
5406 12:19:58.483253 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5407 12:19:58.489804 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5408 12:19:58.489885
5409 12:19:58.489947 [DATLAT]
5410 12:19:58.490006 Freq=933, CH0 RK1
5411 12:19:58.490062
5412 12:19:58.493553 DATLAT Default: 0xb
5413 12:19:58.496465 0, 0xFFFF, sum = 0
5414 12:19:58.496547 1, 0xFFFF, sum = 0
5415 12:19:58.499412 2, 0xFFFF, sum = 0
5416 12:19:58.499493 3, 0xFFFF, sum = 0
5417 12:19:58.503051 4, 0xFFFF, sum = 0
5418 12:19:58.503171 5, 0xFFFF, sum = 0
5419 12:19:58.506351 6, 0xFFFF, sum = 0
5420 12:19:58.506432 7, 0xFFFF, sum = 0
5421 12:19:58.509136 8, 0xFFFF, sum = 0
5422 12:19:58.509217 9, 0xFFFF, sum = 0
5423 12:19:58.512843 10, 0x0, sum = 1
5424 12:19:58.512925 11, 0x0, sum = 2
5425 12:19:58.516212 12, 0x0, sum = 3
5426 12:19:58.516294 13, 0x0, sum = 4
5427 12:19:58.519641 best_step = 11
5428 12:19:58.519721
5429 12:19:58.519783 ==
5430 12:19:58.522357 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 12:19:58.525777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 12:19:58.525858 ==
5433 12:19:58.525920 RX Vref Scan: 0
5434 12:19:58.529842
5435 12:19:58.529920 RX Vref 0 -> 0, step: 1
5436 12:19:58.529982
5437 12:19:58.532247 RX Delay -61 -> 252, step: 4
5438 12:19:58.538940 iDelay=195, Bit 0, Center 98 (15 ~ 182) 168
5439 12:19:58.541934 iDelay=195, Bit 1, Center 104 (19 ~ 190) 172
5440 12:19:58.545581 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5441 12:19:58.549323 iDelay=195, Bit 3, Center 100 (15 ~ 186) 172
5442 12:19:58.551976 iDelay=195, Bit 4, Center 102 (15 ~ 190) 176
5443 12:19:58.558237 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5444 12:19:58.561611 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5445 12:19:58.565553 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5446 12:19:58.568758 iDelay=195, Bit 8, Center 78 (-9 ~ 166) 176
5447 12:19:58.571849 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5448 12:19:58.578765 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5449 12:19:58.581779 iDelay=195, Bit 11, Center 82 (-1 ~ 166) 168
5450 12:19:58.585640 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5451 12:19:58.588140 iDelay=195, Bit 13, Center 96 (15 ~ 178) 164
5452 12:19:58.594451 iDelay=195, Bit 14, Center 100 (15 ~ 186) 172
5453 12:19:58.598000 iDelay=195, Bit 15, Center 98 (15 ~ 182) 168
5454 12:19:58.598079 ==
5455 12:19:58.601065 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 12:19:58.604320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 12:19:58.604400 ==
5458 12:19:58.604462 DQS Delay:
5459 12:19:58.607888 DQS0 = 0, DQS1 = 0
5460 12:19:58.607967 DQM Delay:
5461 12:19:58.610832 DQM0 = 101, DQM1 = 90
5462 12:19:58.610911 DQ Delay:
5463 12:19:58.614571 DQ0 =98, DQ1 =104, DQ2 =96, DQ3 =100
5464 12:19:58.618093 DQ4 =102, DQ5 =92, DQ6 =108, DQ7 =108
5465 12:19:58.621199 DQ8 =78, DQ9 =76, DQ10 =94, DQ11 =82
5466 12:19:58.624148 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =98
5467 12:19:58.624228
5468 12:19:58.624291
5469 12:19:58.634598 [DQSOSCAuto] RK1, (LSB)MR18= 0x100d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5470 12:19:58.637440 CH0 RK1: MR19=505, MR18=100D
5471 12:19:58.640945 CH0_RK1: MR19=0x505, MR18=0x100D, DQSOSC=416, MR23=63, INC=62, DEC=41
5472 12:19:58.643921 [RxdqsGatingPostProcess] freq 933
5473 12:19:58.650791 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 12:19:58.653823 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 12:19:58.657125 best DQS1 dly(2T, 0.5T) = (0, 11)
5476 12:19:58.660608 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 12:19:58.664139 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5478 12:19:58.666735 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 12:19:58.670113 best DQS1 dly(2T, 0.5T) = (0, 11)
5480 12:19:58.673697 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 12:19:58.677077 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5482 12:19:58.680561 Pre-setting of DQS Precalculation
5483 12:19:58.683472 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 12:19:58.683552 ==
5485 12:19:58.686596 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 12:19:58.693107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 12:19:58.693188 ==
5488 12:19:58.696555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 12:19:58.702798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5490 12:19:58.706237 [CA 0] Center 36 (6~67) winsize 62
5491 12:19:58.709445 [CA 1] Center 36 (6~67) winsize 62
5492 12:19:58.712872 [CA 2] Center 34 (4~65) winsize 62
5493 12:19:58.716106 [CA 3] Center 33 (3~64) winsize 62
5494 12:19:58.719173 [CA 4] Center 34 (4~64) winsize 61
5495 12:19:58.723130 [CA 5] Center 33 (3~64) winsize 62
5496 12:19:58.723210
5497 12:19:58.726449 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5498 12:19:58.726532
5499 12:19:58.729322 [CATrainingPosCal] consider 1 rank data
5500 12:19:58.732250 u2DelayCellTimex100 = 270/100 ps
5501 12:19:58.736144 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 12:19:58.742832 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 12:19:58.745435 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 12:19:58.749188 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5505 12:19:58.752239 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5506 12:19:58.755726 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 12:19:58.755806
5508 12:19:58.758698 CA PerBit enable=1, Macro0, CA PI delay=33
5509 12:19:58.758778
5510 12:19:58.762201 [CBTSetCACLKResult] CA Dly = 33
5511 12:19:58.762281 CS Dly: 4 (0~35)
5512 12:19:58.766109 ==
5513 12:19:58.768988 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 12:19:58.772192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 12:19:58.772272 ==
5516 12:19:58.778669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 12:19:58.782024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5518 12:19:58.785893 [CA 0] Center 36 (5~67) winsize 63
5519 12:19:58.789033 [CA 1] Center 37 (7~67) winsize 61
5520 12:19:58.792234 [CA 2] Center 34 (4~65) winsize 62
5521 12:19:58.795815 [CA 3] Center 33 (3~64) winsize 62
5522 12:19:58.799431 [CA 4] Center 34 (4~64) winsize 61
5523 12:19:58.802110 [CA 5] Center 33 (3~64) winsize 62
5524 12:19:58.802190
5525 12:19:58.805529 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5526 12:19:58.805609
5527 12:19:58.809395 [CATrainingPosCal] consider 2 rank data
5528 12:19:58.812101 u2DelayCellTimex100 = 270/100 ps
5529 12:19:58.815467 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 12:19:58.822631 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5531 12:19:58.825305 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5532 12:19:58.828474 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5533 12:19:58.832312 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 12:19:58.835137 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 12:19:58.835217
5536 12:19:58.838654 CA PerBit enable=1, Macro0, CA PI delay=33
5537 12:19:58.838734
5538 12:19:58.841890 [CBTSetCACLKResult] CA Dly = 33
5539 12:19:58.845341 CS Dly: 5 (0~38)
5540 12:19:58.845422
5541 12:19:58.848543 ----->DramcWriteLeveling(PI) begin...
5542 12:19:58.848625 ==
5543 12:19:58.851577 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 12:19:58.854757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 12:19:58.854838 ==
5546 12:19:58.858515 Write leveling (Byte 0): 29 => 29
5547 12:19:58.861655 Write leveling (Byte 1): 28 => 28
5548 12:19:58.864843 DramcWriteLeveling(PI) end<-----
5549 12:19:58.864923
5550 12:19:58.864985 ==
5551 12:19:58.868264 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 12:19:58.871358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 12:19:58.871439 ==
5554 12:19:58.874495 [Gating] SW mode calibration
5555 12:19:58.881063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 12:19:58.887937 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 12:19:58.890962 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5558 12:19:58.897536 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 12:19:58.901339 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 12:19:58.904433 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 12:19:58.910907 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 12:19:58.914280 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 12:19:58.917252 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 12:19:58.923758 0 14 28 | B1->B0 | 2d2d 2929 | 0 0 | (1 1) (1 1)
5565 12:19:58.927355 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 12:19:58.930811 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 12:19:58.936937 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 12:19:58.940267 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 12:19:58.943518 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 12:19:58.950083 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 12:19:58.953552 0 15 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5572 12:19:58.956628 0 15 28 | B1->B0 | 3333 3b3a | 0 1 | (0 0) (0 0)
5573 12:19:58.964069 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 12:19:58.966483 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 12:19:58.969830 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 12:19:58.976681 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 12:19:58.979876 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 12:19:58.983281 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 12:19:58.989834 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 12:19:58.992819 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5581 12:19:58.996028 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:19:59.002641 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:19:59.006358 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:19:59.009120 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:19:59.015985 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:19:59.019239 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:19:59.022664 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:19:59.029083 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:19:59.032389 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:19:59.035942 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:19:59.042358 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:19:59.045849 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:19:59.049275 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:19:59.055640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 12:19:59.058648 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 12:19:59.062057 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5597 12:19:59.068638 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 12:19:59.068719 Total UI for P1: 0, mck2ui 16
5599 12:19:59.075350 best dqsien dly found for B0: ( 1, 2, 28)
5600 12:19:59.075430 Total UI for P1: 0, mck2ui 16
5601 12:19:59.082261 best dqsien dly found for B1: ( 1, 2, 28)
5602 12:19:59.085174 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5603 12:19:59.088199 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5604 12:19:59.088278
5605 12:19:59.092208 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5606 12:19:59.095294 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5607 12:19:59.098043 [Gating] SW calibration Done
5608 12:19:59.098122 ==
5609 12:19:59.101323 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 12:19:59.104693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 12:19:59.104773 ==
5612 12:19:59.108137 RX Vref Scan: 0
5613 12:19:59.108216
5614 12:19:59.108278 RX Vref 0 -> 0, step: 1
5615 12:19:59.111214
5616 12:19:59.111292 RX Delay -80 -> 252, step: 8
5617 12:19:59.117693 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5618 12:19:59.120953 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5619 12:19:59.124366 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5620 12:19:59.127638 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5621 12:19:59.131069 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5622 12:19:59.134301 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5623 12:19:59.141229 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5624 12:19:59.144689 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5625 12:19:59.148284 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5626 12:19:59.150926 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5627 12:19:59.154055 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5628 12:19:59.157192 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5629 12:19:59.164067 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5630 12:19:59.167522 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5631 12:19:59.170958 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5632 12:19:59.173996 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5633 12:19:59.174077 ==
5634 12:19:59.177177 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 12:19:59.184255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 12:19:59.184336 ==
5637 12:19:59.184399 DQS Delay:
5638 12:19:59.187166 DQS0 = 0, DQS1 = 0
5639 12:19:59.187247 DQM Delay:
5640 12:19:59.187311 DQM0 = 100, DQM1 = 96
5641 12:19:59.190238 DQ Delay:
5642 12:19:59.193583 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5643 12:19:59.196784 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5644 12:19:59.200283 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5645 12:19:59.203735 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5646 12:19:59.203815
5647 12:19:59.203877
5648 12:19:59.203936 ==
5649 12:19:59.206813 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 12:19:59.210127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 12:19:59.210207 ==
5652 12:19:59.213056
5653 12:19:59.213135
5654 12:19:59.213196 TX Vref Scan disable
5655 12:19:59.216903 == TX Byte 0 ==
5656 12:19:59.220048 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5657 12:19:59.223118 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5658 12:19:59.226745 == TX Byte 1 ==
5659 12:19:59.229990 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5660 12:19:59.232879 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5661 12:19:59.232960 ==
5662 12:19:59.236052 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 12:19:59.242657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 12:19:59.242736 ==
5665 12:19:59.242798
5666 12:19:59.242855
5667 12:19:59.246434 TX Vref Scan disable
5668 12:19:59.246513 == TX Byte 0 ==
5669 12:19:59.253174 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5670 12:19:59.255709 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5671 12:19:59.255788 == TX Byte 1 ==
5672 12:19:59.262847 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5673 12:19:59.265654 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5674 12:19:59.265733
5675 12:19:59.265795 [DATLAT]
5676 12:19:59.268873 Freq=933, CH1 RK0
5677 12:19:59.268953
5678 12:19:59.269015 DATLAT Default: 0xd
5679 12:19:59.272370 0, 0xFFFF, sum = 0
5680 12:19:59.272451 1, 0xFFFF, sum = 0
5681 12:19:59.275882 2, 0xFFFF, sum = 0
5682 12:19:59.275962 3, 0xFFFF, sum = 0
5683 12:19:59.279267 4, 0xFFFF, sum = 0
5684 12:19:59.279347 5, 0xFFFF, sum = 0
5685 12:19:59.282335 6, 0xFFFF, sum = 0
5686 12:19:59.285749 7, 0xFFFF, sum = 0
5687 12:19:59.285829 8, 0xFFFF, sum = 0
5688 12:19:59.288634 9, 0xFFFF, sum = 0
5689 12:19:59.288715 10, 0x0, sum = 1
5690 12:19:59.292141 11, 0x0, sum = 2
5691 12:19:59.292222 12, 0x0, sum = 3
5692 12:19:59.292285 13, 0x0, sum = 4
5693 12:19:59.295866 best_step = 11
5694 12:19:59.295945
5695 12:19:59.296007 ==
5696 12:19:59.298859 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 12:19:59.302309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 12:19:59.302389 ==
5699 12:19:59.305173 RX Vref Scan: 1
5700 12:19:59.305258
5701 12:19:59.308795 RX Vref 0 -> 0, step: 1
5702 12:19:59.308875
5703 12:19:59.308937 RX Delay -53 -> 252, step: 4
5704 12:19:59.308995
5705 12:19:59.311820 Set Vref, RX VrefLevel [Byte0]: 51
5706 12:19:59.315164 [Byte1]: 53
5707 12:19:59.319940
5708 12:19:59.320046 Final RX Vref Byte 0 = 51 to rank0
5709 12:19:59.323159 Final RX Vref Byte 1 = 53 to rank0
5710 12:19:59.326574 Final RX Vref Byte 0 = 51 to rank1
5711 12:19:59.329711 Final RX Vref Byte 1 = 53 to rank1==
5712 12:19:59.332781 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 12:19:59.339271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 12:19:59.339351 ==
5715 12:19:59.339414 DQS Delay:
5716 12:19:59.342906 DQS0 = 0, DQS1 = 0
5717 12:19:59.343011 DQM Delay:
5718 12:19:59.343138 DQM0 = 98, DQM1 = 95
5719 12:19:59.346335 DQ Delay:
5720 12:19:59.349145 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
5721 12:19:59.352699 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =92
5722 12:19:59.355924 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =88
5723 12:19:59.358920 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5724 12:19:59.359025
5725 12:19:59.359114
5726 12:19:59.365841 [DQSOSCAuto] RK0, (LSB)MR18= 0x10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 422 ps
5727 12:19:59.368892 CH1 RK0: MR19=505, MR18=10
5728 12:19:59.375478 CH1_RK0: MR19=0x505, MR18=0x10, DQSOSC=416, MR23=63, INC=62, DEC=41
5729 12:19:59.375558
5730 12:19:59.378681 ----->DramcWriteLeveling(PI) begin...
5731 12:19:59.378762 ==
5732 12:19:59.382930 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 12:19:59.385174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 12:19:59.385254 ==
5735 12:19:59.388827 Write leveling (Byte 0): 25 => 25
5736 12:19:59.392078 Write leveling (Byte 1): 28 => 28
5737 12:19:59.395174 DramcWriteLeveling(PI) end<-----
5738 12:19:59.395254
5739 12:19:59.395316 ==
5740 12:19:59.398691 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 12:19:59.405783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 12:19:59.405863 ==
5743 12:19:59.405926 [Gating] SW mode calibration
5744 12:19:59.415268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5745 12:19:59.418323 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5746 12:19:59.421721 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5747 12:19:59.428469 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 12:19:59.431587 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 12:19:59.438125 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 12:19:59.441155 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 12:19:59.444909 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 12:19:59.451404 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
5753 12:19:59.454374 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
5754 12:19:59.458110 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5755 12:19:59.464827 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 12:19:59.467411 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 12:19:59.471540 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 12:19:59.477537 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 12:19:59.480547 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 12:19:59.483993 0 15 24 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
5761 12:19:59.490462 0 15 28 | B1->B0 | 3636 4545 | 0 0 | (1 1) (0 0)
5762 12:19:59.493739 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 12:19:59.497027 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 12:19:59.503704 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 12:19:59.506736 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 12:19:59.510668 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 12:19:59.516979 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 12:19:59.520129 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5769 12:19:59.523386 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 12:19:59.530392 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:19:59.533283 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:19:59.536743 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:19:59.543043 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:19:59.546731 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:19:59.549811 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:19:59.556479 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:19:59.559936 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:19:59.562895 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:19:59.569392 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:19:59.573242 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:19:59.576392 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:19:59.582320 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:19:59.586010 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:19:59.588948 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 12:19:59.596130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5786 12:19:59.599315 Total UI for P1: 0, mck2ui 16
5787 12:19:59.602155 best dqsien dly found for B0: ( 1, 2, 26)
5788 12:19:59.605786 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 12:19:59.608764 Total UI for P1: 0, mck2ui 16
5790 12:19:59.612212 best dqsien dly found for B1: ( 1, 2, 28)
5791 12:19:59.615561 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5792 12:19:59.618779 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5793 12:19:59.618858
5794 12:19:59.622011 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5795 12:19:59.628961 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5796 12:19:59.629040 [Gating] SW calibration Done
5797 12:19:59.629102 ==
5798 12:19:59.631545 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 12:19:59.638351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 12:19:59.638430 ==
5801 12:19:59.638491 RX Vref Scan: 0
5802 12:19:59.638548
5803 12:19:59.641808 RX Vref 0 -> 0, step: 1
5804 12:19:59.641887
5805 12:19:59.645087 RX Delay -80 -> 252, step: 8
5806 12:19:59.648536 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5807 12:19:59.651756 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5808 12:19:59.654835 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5809 12:19:59.658098 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5810 12:19:59.664693 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5811 12:19:59.668010 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5812 12:19:59.671501 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5813 12:19:59.674487 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5814 12:19:59.677921 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5815 12:19:59.681500 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5816 12:19:59.687582 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5817 12:19:59.691128 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5818 12:19:59.694484 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5819 12:19:59.697723 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5820 12:19:59.701240 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5821 12:19:59.707529 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5822 12:19:59.707608 ==
5823 12:19:59.711395 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 12:19:59.714209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 12:19:59.714289 ==
5826 12:19:59.714351 DQS Delay:
5827 12:19:59.717729 DQS0 = 0, DQS1 = 0
5828 12:19:59.717808 DQM Delay:
5829 12:19:59.720859 DQM0 = 97, DQM1 = 94
5830 12:19:59.720938 DQ Delay:
5831 12:19:59.724255 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =95
5832 12:19:59.727785 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5833 12:19:59.730676 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5834 12:19:59.733763 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5835 12:19:59.733843
5836 12:19:59.733905
5837 12:19:59.733962 ==
5838 12:19:59.737029 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 12:19:59.743491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 12:19:59.743571 ==
5841 12:19:59.743634
5842 12:19:59.743691
5843 12:19:59.743746 TX Vref Scan disable
5844 12:19:59.747268 == TX Byte 0 ==
5845 12:19:59.750933 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5846 12:19:59.757841 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5847 12:19:59.757921 == TX Byte 1 ==
5848 12:19:59.760580 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5849 12:19:59.766825 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5850 12:19:59.766945 ==
5851 12:19:59.770198 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 12:19:59.773378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 12:19:59.773458 ==
5854 12:19:59.773520
5855 12:19:59.773577
5856 12:19:59.776800 TX Vref Scan disable
5857 12:19:59.780085 == TX Byte 0 ==
5858 12:19:59.783654 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5859 12:19:59.786892 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5860 12:19:59.790140 == TX Byte 1 ==
5861 12:19:59.793726 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5862 12:19:59.796644 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5863 12:19:59.796724
5864 12:19:59.796785 [DATLAT]
5865 12:19:59.799970 Freq=933, CH1 RK1
5866 12:19:59.800050
5867 12:19:59.802936 DATLAT Default: 0xb
5868 12:19:59.803015 0, 0xFFFF, sum = 0
5869 12:19:59.806331 1, 0xFFFF, sum = 0
5870 12:19:59.806412 2, 0xFFFF, sum = 0
5871 12:19:59.809949 3, 0xFFFF, sum = 0
5872 12:19:59.810029 4, 0xFFFF, sum = 0
5873 12:19:59.812970 5, 0xFFFF, sum = 0
5874 12:19:59.813050 6, 0xFFFF, sum = 0
5875 12:19:59.816242 7, 0xFFFF, sum = 0
5876 12:19:59.816323 8, 0xFFFF, sum = 0
5877 12:19:59.819479 9, 0xFFFF, sum = 0
5878 12:19:59.819559 10, 0x0, sum = 1
5879 12:19:59.822691 11, 0x0, sum = 2
5880 12:19:59.822771 12, 0x0, sum = 3
5881 12:19:59.826462 13, 0x0, sum = 4
5882 12:19:59.826543 best_step = 11
5883 12:19:59.826605
5884 12:19:59.826663 ==
5885 12:19:59.829766 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 12:19:59.835861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 12:19:59.835941 ==
5888 12:19:59.836003 RX Vref Scan: 0
5889 12:19:59.836061
5890 12:19:59.839485 RX Vref 0 -> 0, step: 1
5891 12:19:59.839564
5892 12:19:59.842476 RX Delay -53 -> 252, step: 4
5893 12:19:59.845886 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5894 12:19:59.849538 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5895 12:19:59.855529 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5896 12:19:59.858977 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5897 12:19:59.862301 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5898 12:19:59.865452 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5899 12:19:59.868848 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5900 12:19:59.875198 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5901 12:19:59.879035 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5902 12:19:59.882053 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5903 12:19:59.886330 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5904 12:19:59.888662 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5905 12:19:59.895271 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5906 12:19:59.898650 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
5907 12:19:59.901586 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5908 12:19:59.904955 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5909 12:19:59.905034 ==
5910 12:19:59.908884 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 12:19:59.911283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 12:19:59.915193 ==
5913 12:19:59.915272 DQS Delay:
5914 12:19:59.915335 DQS0 = 0, DQS1 = 0
5915 12:19:59.918526 DQM Delay:
5916 12:19:59.918605 DQM0 = 96, DQM1 = 92
5917 12:19:59.921613 DQ Delay:
5918 12:19:59.925033 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5919 12:19:59.928252 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =92
5920 12:19:59.931573 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5921 12:19:59.934723 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =102
5922 12:19:59.934802
5923 12:19:59.934864
5924 12:19:59.941065 [DQSOSCAuto] RK1, (LSB)MR18= 0xa21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5925 12:19:59.944474 CH1 RK1: MR19=505, MR18=A21
5926 12:19:59.951282 CH1_RK1: MR19=0x505, MR18=0xA21, DQSOSC=411, MR23=63, INC=64, DEC=42
5927 12:19:59.954899 [RxdqsGatingPostProcess] freq 933
5928 12:19:59.957606 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5929 12:19:59.960858 best DQS0 dly(2T, 0.5T) = (0, 10)
5930 12:19:59.964055 best DQS1 dly(2T, 0.5T) = (0, 10)
5931 12:19:59.967603 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5932 12:19:59.970717 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5933 12:19:59.973772 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 12:19:59.977532 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 12:19:59.980802 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 12:19:59.984386 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 12:19:59.987004 Pre-setting of DQS Precalculation
5938 12:19:59.993554 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5939 12:20:00.000253 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5940 12:20:00.006595 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5941 12:20:00.006675
5942 12:20:00.006738
5943 12:20:00.010010 [Calibration Summary] 1866 Mbps
5944 12:20:00.010090 CH 0, Rank 0
5945 12:20:00.013098 SW Impedance : PASS
5946 12:20:00.016386 DUTY Scan : NO K
5947 12:20:00.016466 ZQ Calibration : PASS
5948 12:20:00.019925 Jitter Meter : NO K
5949 12:20:00.023335 CBT Training : PASS
5950 12:20:00.023414 Write leveling : PASS
5951 12:20:00.026600 RX DQS gating : PASS
5952 12:20:00.029680 RX DQ/DQS(RDDQC) : PASS
5953 12:20:00.029759 TX DQ/DQS : PASS
5954 12:20:00.033092 RX DATLAT : PASS
5955 12:20:00.033173 RX DQ/DQS(Engine): PASS
5956 12:20:00.036415 TX OE : NO K
5957 12:20:00.036495 All Pass.
5958 12:20:00.036559
5959 12:20:00.039577 CH 0, Rank 1
5960 12:20:00.042797 SW Impedance : PASS
5961 12:20:00.042877 DUTY Scan : NO K
5962 12:20:00.046389 ZQ Calibration : PASS
5963 12:20:00.046468 Jitter Meter : NO K
5964 12:20:00.049936 CBT Training : PASS
5965 12:20:00.052795 Write leveling : PASS
5966 12:20:00.052875 RX DQS gating : PASS
5967 12:20:00.056306 RX DQ/DQS(RDDQC) : PASS
5968 12:20:00.059454 TX DQ/DQS : PASS
5969 12:20:00.059534 RX DATLAT : PASS
5970 12:20:00.062737 RX DQ/DQS(Engine): PASS
5971 12:20:00.066290 TX OE : NO K
5972 12:20:00.066370 All Pass.
5973 12:20:00.066434
5974 12:20:00.066509 CH 1, Rank 0
5975 12:20:00.069236 SW Impedance : PASS
5976 12:20:00.072624 DUTY Scan : NO K
5977 12:20:00.072703 ZQ Calibration : PASS
5978 12:20:00.075968 Jitter Meter : NO K
5979 12:20:00.078962 CBT Training : PASS
5980 12:20:00.079068 Write leveling : PASS
5981 12:20:00.082655 RX DQS gating : PASS
5982 12:20:00.086407 RX DQ/DQS(RDDQC) : PASS
5983 12:20:00.086487 TX DQ/DQS : PASS
5984 12:20:00.089224 RX DATLAT : PASS
5985 12:20:00.092537 RX DQ/DQS(Engine): PASS
5986 12:20:00.092617 TX OE : NO K
5987 12:20:00.095933 All Pass.
5988 12:20:00.096012
5989 12:20:00.096075 CH 1, Rank 1
5990 12:20:00.099143 SW Impedance : PASS
5991 12:20:00.099222 DUTY Scan : NO K
5992 12:20:00.102092 ZQ Calibration : PASS
5993 12:20:00.105700 Jitter Meter : NO K
5994 12:20:00.105780 CBT Training : PASS
5995 12:20:00.108711 Write leveling : PASS
5996 12:20:00.112220 RX DQS gating : PASS
5997 12:20:00.112300 RX DQ/DQS(RDDQC) : PASS
5998 12:20:00.115213 TX DQ/DQS : PASS
5999 12:20:00.119257 RX DATLAT : PASS
6000 12:20:00.119337 RX DQ/DQS(Engine): PASS
6001 12:20:00.121854 TX OE : NO K
6002 12:20:00.121934 All Pass.
6003 12:20:00.121996
6004 12:20:00.125185 DramC Write-DBI off
6005 12:20:00.129080 PER_BANK_REFRESH: Hybrid Mode
6006 12:20:00.129160 TX_TRACKING: ON
6007 12:20:00.138734 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6008 12:20:00.141354 [FAST_K] Save calibration result to emmc
6009 12:20:00.144846 dramc_set_vcore_voltage set vcore to 650000
6010 12:20:00.148317 Read voltage for 400, 6
6011 12:20:00.148397 Vio18 = 0
6012 12:20:00.148459 Vcore = 650000
6013 12:20:00.151182 Vdram = 0
6014 12:20:00.151262 Vddq = 0
6015 12:20:00.151324 Vmddr = 0
6016 12:20:00.157854 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6017 12:20:00.161521 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6018 12:20:00.164622 MEM_TYPE=3, freq_sel=20
6019 12:20:00.168030 sv_algorithm_assistance_LP4_800
6020 12:20:00.171069 ============ PULL DRAM RESETB DOWN ============
6021 12:20:00.174564 ========== PULL DRAM RESETB DOWN end =========
6022 12:20:00.181228 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6023 12:20:00.184746 ===================================
6024 12:20:00.187767 LPDDR4 DRAM CONFIGURATION
6025 12:20:00.191033 ===================================
6026 12:20:00.191130 EX_ROW_EN[0] = 0x0
6027 12:20:00.194081 EX_ROW_EN[1] = 0x0
6028 12:20:00.194160 LP4Y_EN = 0x0
6029 12:20:00.197701 WORK_FSP = 0x0
6030 12:20:00.197781 WL = 0x2
6031 12:20:00.201042 RL = 0x2
6032 12:20:00.201121 BL = 0x2
6033 12:20:00.204552 RPST = 0x0
6034 12:20:00.204632 RD_PRE = 0x0
6035 12:20:00.207291 WR_PRE = 0x1
6036 12:20:00.207371 WR_PST = 0x0
6037 12:20:00.210606 DBI_WR = 0x0
6038 12:20:00.210686 DBI_RD = 0x0
6039 12:20:00.213832 OTF = 0x1
6040 12:20:00.217299 ===================================
6041 12:20:00.220718 ===================================
6042 12:20:00.220798 ANA top config
6043 12:20:00.223933 ===================================
6044 12:20:00.227257 DLL_ASYNC_EN = 0
6045 12:20:00.230291 ALL_SLAVE_EN = 1
6046 12:20:00.233602 NEW_RANK_MODE = 1
6047 12:20:00.237071 DLL_IDLE_MODE = 1
6048 12:20:00.237151 LP45_APHY_COMB_EN = 1
6049 12:20:00.240818 TX_ODT_DIS = 1
6050 12:20:00.243902 NEW_8X_MODE = 1
6051 12:20:00.247219 ===================================
6052 12:20:00.250927 ===================================
6053 12:20:00.253820 data_rate = 800
6054 12:20:00.257394 CKR = 1
6055 12:20:00.257475 DQ_P2S_RATIO = 4
6056 12:20:00.260559 ===================================
6057 12:20:00.263308 CA_P2S_RATIO = 4
6058 12:20:00.266896 DQ_CA_OPEN = 0
6059 12:20:00.269890 DQ_SEMI_OPEN = 1
6060 12:20:00.273240 CA_SEMI_OPEN = 1
6061 12:20:00.276774 CA_FULL_RATE = 0
6062 12:20:00.276854 DQ_CKDIV4_EN = 0
6063 12:20:00.279779 CA_CKDIV4_EN = 1
6064 12:20:00.283025 CA_PREDIV_EN = 0
6065 12:20:00.286559 PH8_DLY = 0
6066 12:20:00.290371 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6067 12:20:00.293305 DQ_AAMCK_DIV = 0
6068 12:20:00.296713 CA_AAMCK_DIV = 0
6069 12:20:00.296794 CA_ADMCK_DIV = 4
6070 12:20:00.299995 DQ_TRACK_CA_EN = 0
6071 12:20:00.302954 CA_PICK = 800
6072 12:20:00.306235 CA_MCKIO = 400
6073 12:20:00.309825 MCKIO_SEMI = 400
6074 12:20:00.313039 PLL_FREQ = 3016
6075 12:20:00.316206 DQ_UI_PI_RATIO = 32
6076 12:20:00.316286 CA_UI_PI_RATIO = 32
6077 12:20:00.319695 ===================================
6078 12:20:00.322753 ===================================
6079 12:20:00.326193 memory_type:LPDDR4
6080 12:20:00.329554 GP_NUM : 10
6081 12:20:00.329632 SRAM_EN : 1
6082 12:20:00.332977 MD32_EN : 0
6083 12:20:00.335693 ===================================
6084 12:20:00.339296 [ANA_INIT] >>>>>>>>>>>>>>
6085 12:20:00.342447 <<<<<< [CONFIGURE PHASE]: ANA_TX
6086 12:20:00.345655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6087 12:20:00.348698 ===================================
6088 12:20:00.352182 data_rate = 800,PCW = 0X7400
6089 12:20:00.355458 ===================================
6090 12:20:00.358775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6091 12:20:00.362140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 12:20:00.375310 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 12:20:00.378810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6094 12:20:00.381920 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6095 12:20:00.385024 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6096 12:20:00.388007 [ANA_INIT] flow start
6097 12:20:00.391284 [ANA_INIT] PLL >>>>>>>>
6098 12:20:00.391367 [ANA_INIT] PLL <<<<<<<<
6099 12:20:00.395013 [ANA_INIT] MIDPI >>>>>>>>
6100 12:20:00.398227 [ANA_INIT] MIDPI <<<<<<<<
6101 12:20:00.398310 [ANA_INIT] DLL >>>>>>>>
6102 12:20:00.401931 [ANA_INIT] flow end
6103 12:20:00.404715 ============ LP4 DIFF to SE enter ============
6104 12:20:00.408220 ============ LP4 DIFF to SE exit ============
6105 12:20:00.411526 [ANA_INIT] <<<<<<<<<<<<<
6106 12:20:00.414825 [Flow] Enable top DCM control >>>>>
6107 12:20:00.418117 [Flow] Enable top DCM control <<<<<
6108 12:20:00.421484 Enable DLL master slave shuffle
6109 12:20:00.427794 ==============================================================
6110 12:20:00.427877 Gating Mode config
6111 12:20:00.434786 ==============================================================
6112 12:20:00.437674 Config description:
6113 12:20:00.447317 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6114 12:20:00.453766 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6115 12:20:00.457041 SELPH_MODE 0: By rank 1: By Phase
6116 12:20:00.463680 ==============================================================
6117 12:20:00.466915 GAT_TRACK_EN = 0
6118 12:20:00.470607 RX_GATING_MODE = 2
6119 12:20:00.470690 RX_GATING_TRACK_MODE = 2
6120 12:20:00.473496 SELPH_MODE = 1
6121 12:20:00.476917 PICG_EARLY_EN = 1
6122 12:20:00.480238 VALID_LAT_VALUE = 1
6123 12:20:00.486930 ==============================================================
6124 12:20:00.489882 Enter into Gating configuration >>>>
6125 12:20:00.493234 Exit from Gating configuration <<<<
6126 12:20:00.496739 Enter into DVFS_PRE_config >>>>>
6127 12:20:00.506313 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6128 12:20:00.509697 Exit from DVFS_PRE_config <<<<<
6129 12:20:00.513333 Enter into PICG configuration >>>>
6130 12:20:00.516470 Exit from PICG configuration <<<<
6131 12:20:00.519660 [RX_INPUT] configuration >>>>>
6132 12:20:00.523462 [RX_INPUT] configuration <<<<<
6133 12:20:00.526237 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6134 12:20:00.532885 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6135 12:20:00.539116 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 12:20:00.545848 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 12:20:00.552558 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6138 12:20:00.559426 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6139 12:20:00.562242 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6140 12:20:00.565981 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6141 12:20:00.569188 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6142 12:20:00.575355 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6143 12:20:00.579257 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6144 12:20:00.582079 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6145 12:20:00.585661 ===================================
6146 12:20:00.588680 LPDDR4 DRAM CONFIGURATION
6147 12:20:00.592431 ===================================
6148 12:20:00.592514 EX_ROW_EN[0] = 0x0
6149 12:20:00.595404 EX_ROW_EN[1] = 0x0
6150 12:20:00.598442 LP4Y_EN = 0x0
6151 12:20:00.598525 WORK_FSP = 0x0
6152 12:20:00.602010 WL = 0x2
6153 12:20:00.602095 RL = 0x2
6154 12:20:00.605392 BL = 0x2
6155 12:20:00.605474 RPST = 0x0
6156 12:20:00.608357 RD_PRE = 0x0
6157 12:20:00.608481 WR_PRE = 0x1
6158 12:20:00.611934 WR_PST = 0x0
6159 12:20:00.612018 DBI_WR = 0x0
6160 12:20:00.615119 DBI_RD = 0x0
6161 12:20:00.615201 OTF = 0x1
6162 12:20:00.618434 ===================================
6163 12:20:00.621696 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6164 12:20:00.628389 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6165 12:20:00.631865 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6166 12:20:00.634927 ===================================
6167 12:20:00.637989 LPDDR4 DRAM CONFIGURATION
6168 12:20:00.641331 ===================================
6169 12:20:00.641411 EX_ROW_EN[0] = 0x10
6170 12:20:00.644590 EX_ROW_EN[1] = 0x0
6171 12:20:00.648193 LP4Y_EN = 0x0
6172 12:20:00.648273 WORK_FSP = 0x0
6173 12:20:00.651123 WL = 0x2
6174 12:20:00.651249 RL = 0x2
6175 12:20:00.655123 BL = 0x2
6176 12:20:00.655293 RPST = 0x0
6177 12:20:00.657908 RD_PRE = 0x0
6178 12:20:00.657988 WR_PRE = 0x1
6179 12:20:00.660858 WR_PST = 0x0
6180 12:20:00.660938 DBI_WR = 0x0
6181 12:20:00.664380 DBI_RD = 0x0
6182 12:20:00.664460 OTF = 0x1
6183 12:20:00.668133 ===================================
6184 12:20:00.674801 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6185 12:20:00.678975 nWR fixed to 30
6186 12:20:00.682300 [ModeRegInit_LP4] CH0 RK0
6187 12:20:00.682393 [ModeRegInit_LP4] CH0 RK1
6188 12:20:00.685908 [ModeRegInit_LP4] CH1 RK0
6189 12:20:00.689405 [ModeRegInit_LP4] CH1 RK1
6190 12:20:00.689485 match AC timing 19
6191 12:20:00.695164 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6192 12:20:00.699394 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6193 12:20:00.702030 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6194 12:20:00.708081 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6195 12:20:00.711980 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6196 12:20:00.712061 ==
6197 12:20:00.714814 Dram Type= 6, Freq= 0, CH_0, rank 0
6198 12:20:00.717949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6199 12:20:00.721202 ==
6200 12:20:00.724752 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6201 12:20:00.731774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6202 12:20:00.734803 [CA 0] Center 36 (8~64) winsize 57
6203 12:20:00.737663 [CA 1] Center 36 (8~64) winsize 57
6204 12:20:00.741418 [CA 2] Center 36 (8~64) winsize 57
6205 12:20:00.744806 [CA 3] Center 36 (8~64) winsize 57
6206 12:20:00.748166 [CA 4] Center 36 (8~64) winsize 57
6207 12:20:00.750987 [CA 5] Center 36 (8~64) winsize 57
6208 12:20:00.751113
6209 12:20:00.754362 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6210 12:20:00.754441
6211 12:20:00.757458 [CATrainingPosCal] consider 1 rank data
6212 12:20:00.760997 u2DelayCellTimex100 = 270/100 ps
6213 12:20:00.764136 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 12:20:00.767575 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 12:20:00.770547 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 12:20:00.773977 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 12:20:00.777472 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 12:20:00.780948 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 12:20:00.781075
6220 12:20:00.787059 CA PerBit enable=1, Macro0, CA PI delay=36
6221 12:20:00.787160
6222 12:20:00.790237 [CBTSetCACLKResult] CA Dly = 36
6223 12:20:00.790349 CS Dly: 1 (0~32)
6224 12:20:00.790416 ==
6225 12:20:00.793632 Dram Type= 6, Freq= 0, CH_0, rank 1
6226 12:20:00.796686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 12:20:00.796766 ==
6228 12:20:00.803866 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 12:20:00.810682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6230 12:20:00.813675 [CA 0] Center 36 (8~64) winsize 57
6231 12:20:00.816731 [CA 1] Center 36 (8~64) winsize 57
6232 12:20:00.820020 [CA 2] Center 36 (8~64) winsize 57
6233 12:20:00.823628 [CA 3] Center 36 (8~64) winsize 57
6234 12:20:00.826788 [CA 4] Center 36 (8~64) winsize 57
6235 12:20:00.829936 [CA 5] Center 36 (8~64) winsize 57
6236 12:20:00.830016
6237 12:20:00.833135 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6238 12:20:00.833215
6239 12:20:00.836566 [CATrainingPosCal] consider 2 rank data
6240 12:20:00.839695 u2DelayCellTimex100 = 270/100 ps
6241 12:20:00.842895 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 12:20:00.846449 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 12:20:00.849946 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:20:00.852821 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:20:00.856151 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:20:00.859815 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:20:00.859927
6248 12:20:00.866017 CA PerBit enable=1, Macro0, CA PI delay=36
6249 12:20:00.866098
6250 12:20:00.866160 [CBTSetCACLKResult] CA Dly = 36
6251 12:20:00.869776 CS Dly: 1 (0~32)
6252 12:20:00.869856
6253 12:20:00.872576 ----->DramcWriteLeveling(PI) begin...
6254 12:20:00.872657 ==
6255 12:20:00.875916 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 12:20:00.879564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 12:20:00.879644 ==
6258 12:20:00.882443 Write leveling (Byte 0): 40 => 8
6259 12:20:00.886395 Write leveling (Byte 1): 40 => 8
6260 12:20:00.889461 DramcWriteLeveling(PI) end<-----
6261 12:20:00.889539
6262 12:20:00.889612 ==
6263 12:20:00.892494 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 12:20:00.898913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 12:20:00.899021 ==
6266 12:20:00.899144 [Gating] SW mode calibration
6267 12:20:00.908748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6268 12:20:00.912163 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6269 12:20:00.915709 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 12:20:00.922432 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 12:20:00.925582 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 12:20:00.928683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 12:20:00.935524 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 12:20:00.938417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 12:20:00.945333 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 12:20:00.948298 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 12:20:00.951899 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 12:20:00.954952 Total UI for P1: 0, mck2ui 16
6279 12:20:00.958479 best dqsien dly found for B0: ( 0, 14, 24)
6280 12:20:00.961473 Total UI for P1: 0, mck2ui 16
6281 12:20:00.965094 best dqsien dly found for B1: ( 0, 14, 24)
6282 12:20:00.967996 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6283 12:20:00.970933 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6284 12:20:00.971030
6285 12:20:00.978113 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 12:20:00.981351 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 12:20:00.984408 [Gating] SW calibration Done
6288 12:20:00.984506 ==
6289 12:20:00.988238 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 12:20:00.990908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 12:20:00.990977 ==
6292 12:20:00.991035 RX Vref Scan: 0
6293 12:20:00.991133
6294 12:20:00.994165 RX Vref 0 -> 0, step: 1
6295 12:20:00.994259
6296 12:20:00.997302 RX Delay -410 -> 252, step: 16
6297 12:20:01.000772 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6298 12:20:01.007397 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6299 12:20:01.010864 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6300 12:20:01.013722 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6301 12:20:01.016972 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6302 12:20:01.023994 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6303 12:20:01.026864 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6304 12:20:01.030466 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6305 12:20:01.033399 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6306 12:20:01.040253 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6307 12:20:01.043316 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6308 12:20:01.046652 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6309 12:20:01.053379 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6310 12:20:01.056508 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6311 12:20:01.059928 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6312 12:20:01.063224 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6313 12:20:01.066334 ==
6314 12:20:01.066414 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 12:20:01.073164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 12:20:01.073244 ==
6317 12:20:01.073306 DQS Delay:
6318 12:20:01.076759 DQS0 = 35, DQS1 = 51
6319 12:20:01.076839 DQM Delay:
6320 12:20:01.079757 DQM0 = 5, DQM1 = 10
6321 12:20:01.079835 DQ Delay:
6322 12:20:01.082635 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6323 12:20:01.086146 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6324 12:20:01.089330 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6325 12:20:01.092842 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6326 12:20:01.092921
6327 12:20:01.092983
6328 12:20:01.093039 ==
6329 12:20:01.096065 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 12:20:01.098969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 12:20:01.099049 ==
6332 12:20:01.099153
6333 12:20:01.099211
6334 12:20:01.102456 TX Vref Scan disable
6335 12:20:01.102534 == TX Byte 0 ==
6336 12:20:01.109322 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6337 12:20:01.112527 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6338 12:20:01.112612 == TX Byte 1 ==
6339 12:20:01.119236 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 12:20:01.122826 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 12:20:01.122910 ==
6342 12:20:01.125955 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 12:20:01.129070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 12:20:01.129151 ==
6345 12:20:01.129213
6346 12:20:01.129270
6347 12:20:01.132088 TX Vref Scan disable
6348 12:20:01.132168 == TX Byte 0 ==
6349 12:20:01.139062 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 12:20:01.142655 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 12:20:01.142735 == TX Byte 1 ==
6352 12:20:01.148893 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 12:20:01.152200 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 12:20:01.152279
6355 12:20:01.152341 [DATLAT]
6356 12:20:01.155372 Freq=400, CH0 RK0
6357 12:20:01.155451
6358 12:20:01.155512 DATLAT Default: 0xf
6359 12:20:01.158886 0, 0xFFFF, sum = 0
6360 12:20:01.158967 1, 0xFFFF, sum = 0
6361 12:20:01.162086 2, 0xFFFF, sum = 0
6362 12:20:01.162166 3, 0xFFFF, sum = 0
6363 12:20:01.165093 4, 0xFFFF, sum = 0
6364 12:20:01.165173 5, 0xFFFF, sum = 0
6365 12:20:01.168537 6, 0xFFFF, sum = 0
6366 12:20:01.171690 7, 0xFFFF, sum = 0
6367 12:20:01.171785 8, 0xFFFF, sum = 0
6368 12:20:01.175349 9, 0xFFFF, sum = 0
6369 12:20:01.175429 10, 0xFFFF, sum = 0
6370 12:20:01.178208 11, 0xFFFF, sum = 0
6371 12:20:01.178291 12, 0xFFFF, sum = 0
6372 12:20:01.182167 13, 0x0, sum = 1
6373 12:20:01.182253 14, 0x0, sum = 2
6374 12:20:01.184867 15, 0x0, sum = 3
6375 12:20:01.184947 16, 0x0, sum = 4
6376 12:20:01.185010 best_step = 14
6377 12:20:01.188266
6378 12:20:01.188346 ==
6379 12:20:01.191506 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 12:20:01.195344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 12:20:01.195424 ==
6382 12:20:01.195486 RX Vref Scan: 1
6383 12:20:01.195544
6384 12:20:01.198476 RX Vref 0 -> 0, step: 1
6385 12:20:01.198555
6386 12:20:01.201258 RX Delay -343 -> 252, step: 8
6387 12:20:01.201338
6388 12:20:01.204797 Set Vref, RX VrefLevel [Byte0]: 59
6389 12:20:01.208208 [Byte1]: 49
6390 12:20:01.212802
6391 12:20:01.212881 Final RX Vref Byte 0 = 59 to rank0
6392 12:20:01.215971 Final RX Vref Byte 1 = 49 to rank0
6393 12:20:01.218805 Final RX Vref Byte 0 = 59 to rank1
6394 12:20:01.221950 Final RX Vref Byte 1 = 49 to rank1==
6395 12:20:01.225318 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 12:20:01.232018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 12:20:01.232098 ==
6398 12:20:01.232160 DQS Delay:
6399 12:20:01.234894 DQS0 = 44, DQS1 = 60
6400 12:20:01.234973 DQM Delay:
6401 12:20:01.238535 DQM0 = 11, DQM1 = 17
6402 12:20:01.238613 DQ Delay:
6403 12:20:01.241959 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6404 12:20:01.245234 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6405 12:20:01.248440 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =12
6406 12:20:01.252228 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6407 12:20:01.252307
6408 12:20:01.252368
6409 12:20:01.258228 [DQSOSCAuto] RK0, (LSB)MR18= 0x8579, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6410 12:20:01.261406 CH0 RK0: MR19=C0C, MR18=8579
6411 12:20:01.268462 CH0_RK0: MR19=0xC0C, MR18=0x8579, DQSOSC=393, MR23=63, INC=382, DEC=254
6412 12:20:01.268541 ==
6413 12:20:01.271250 Dram Type= 6, Freq= 0, CH_0, rank 1
6414 12:20:01.275018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 12:20:01.275138 ==
6416 12:20:01.277968 [Gating] SW mode calibration
6417 12:20:01.285014 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6418 12:20:01.291132 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6419 12:20:01.294682 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 12:20:01.297511 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 12:20:01.305024 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 12:20:01.307920 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 12:20:01.314052 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 12:20:01.318030 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 12:20:01.320777 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 12:20:01.327224 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 12:20:01.330715 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 12:20:01.333868 Total UI for P1: 0, mck2ui 16
6429 12:20:01.337199 best dqsien dly found for B0: ( 0, 14, 24)
6430 12:20:01.340433 Total UI for P1: 0, mck2ui 16
6431 12:20:01.343719 best dqsien dly found for B1: ( 0, 14, 24)
6432 12:20:01.346780 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6433 12:20:01.350448 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6434 12:20:01.350527
6435 12:20:01.354151 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 12:20:01.356830 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 12:20:01.360129 [Gating] SW calibration Done
6438 12:20:01.360208 ==
6439 12:20:01.363245 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 12:20:01.366634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 12:20:01.370132 ==
6442 12:20:01.370212 RX Vref Scan: 0
6443 12:20:01.370273
6444 12:20:01.373088 RX Vref 0 -> 0, step: 1
6445 12:20:01.373167
6446 12:20:01.376430 RX Delay -410 -> 252, step: 16
6447 12:20:01.379914 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6448 12:20:01.383065 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6449 12:20:01.386438 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6450 12:20:01.392814 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6451 12:20:01.396443 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6452 12:20:01.399270 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6453 12:20:01.406040 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6454 12:20:01.409481 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6455 12:20:01.412723 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6456 12:20:01.415936 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6457 12:20:01.422396 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6458 12:20:01.425736 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6459 12:20:01.429184 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6460 12:20:01.432435 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6461 12:20:01.438848 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6462 12:20:01.442784 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6463 12:20:01.442865 ==
6464 12:20:01.445326 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 12:20:01.448952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 12:20:01.449033 ==
6467 12:20:01.451998 DQS Delay:
6468 12:20:01.452078 DQS0 = 35, DQS1 = 51
6469 12:20:01.455247 DQM Delay:
6470 12:20:01.455327 DQM0 = 6, DQM1 = 10
6471 12:20:01.458398 DQ Delay:
6472 12:20:01.458477 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6473 12:20:01.462220 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6474 12:20:01.465265 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6475 12:20:01.468532 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6476 12:20:01.468613
6477 12:20:01.468697
6478 12:20:01.468790 ==
6479 12:20:01.471710 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 12:20:01.478068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 12:20:01.478148 ==
6482 12:20:01.478212
6483 12:20:01.478270
6484 12:20:01.478326 TX Vref Scan disable
6485 12:20:01.481265 == TX Byte 0 ==
6486 12:20:01.484712 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6487 12:20:01.488234 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6488 12:20:01.491108 == TX Byte 1 ==
6489 12:20:01.494919 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6490 12:20:01.497921 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6491 12:20:01.501203 ==
6492 12:20:01.504570 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 12:20:01.508097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 12:20:01.508177 ==
6495 12:20:01.508240
6496 12:20:01.508309
6497 12:20:01.510993 TX Vref Scan disable
6498 12:20:01.511082 == TX Byte 0 ==
6499 12:20:01.514236 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6500 12:20:01.520758 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6501 12:20:01.520839 == TX Byte 1 ==
6502 12:20:01.524159 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6503 12:20:01.530710 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6504 12:20:01.530790
6505 12:20:01.530853 [DATLAT]
6506 12:20:01.530911 Freq=400, CH0 RK1
6507 12:20:01.530968
6508 12:20:01.533853 DATLAT Default: 0xe
6509 12:20:01.537746 0, 0xFFFF, sum = 0
6510 12:20:01.537827 1, 0xFFFF, sum = 0
6511 12:20:01.540903 2, 0xFFFF, sum = 0
6512 12:20:01.540984 3, 0xFFFF, sum = 0
6513 12:20:01.544032 4, 0xFFFF, sum = 0
6514 12:20:01.544114 5, 0xFFFF, sum = 0
6515 12:20:01.547320 6, 0xFFFF, sum = 0
6516 12:20:01.547401 7, 0xFFFF, sum = 0
6517 12:20:01.550521 8, 0xFFFF, sum = 0
6518 12:20:01.550603 9, 0xFFFF, sum = 0
6519 12:20:01.553737 10, 0xFFFF, sum = 0
6520 12:20:01.553819 11, 0xFFFF, sum = 0
6521 12:20:01.557283 12, 0xFFFF, sum = 0
6522 12:20:01.557364 13, 0x0, sum = 1
6523 12:20:01.560442 14, 0x0, sum = 2
6524 12:20:01.560548 15, 0x0, sum = 3
6525 12:20:01.563711 16, 0x0, sum = 4
6526 12:20:01.563796 best_step = 14
6527 12:20:01.563859
6528 12:20:01.563918 ==
6529 12:20:01.566828 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 12:20:01.573696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 12:20:01.573771 ==
6532 12:20:01.573832 RX Vref Scan: 0
6533 12:20:01.573891
6534 12:20:01.576739 RX Vref 0 -> 0, step: 1
6535 12:20:01.576810
6536 12:20:01.580045 RX Delay -343 -> 252, step: 8
6537 12:20:01.586990 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6538 12:20:01.590522 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6539 12:20:01.593344 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6540 12:20:01.597120 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6541 12:20:01.603298 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6542 12:20:01.606470 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6543 12:20:01.609889 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6544 12:20:01.613051 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6545 12:20:01.619777 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6546 12:20:01.623195 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6547 12:20:01.626069 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6548 12:20:01.632619 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6549 12:20:01.636213 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6550 12:20:01.639427 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6551 12:20:01.642795 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6552 12:20:01.649126 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6553 12:20:01.649230 ==
6554 12:20:01.652354 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 12:20:01.655877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 12:20:01.655950 ==
6557 12:20:01.656010 DQS Delay:
6558 12:20:01.658804 DQS0 = 40, DQS1 = 60
6559 12:20:01.658878 DQM Delay:
6560 12:20:01.662441 DQM0 = 6, DQM1 = 14
6561 12:20:01.662508 DQ Delay:
6562 12:20:01.665455 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6563 12:20:01.669390 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6564 12:20:01.672457 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6565 12:20:01.675484 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6566 12:20:01.675565
6567 12:20:01.675627
6568 12:20:01.682082 [DQSOSCAuto] RK1, (LSB)MR18= 0x7b75, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
6569 12:20:01.685601 CH0 RK1: MR19=C0C, MR18=7B75
6570 12:20:01.691823 CH0_RK1: MR19=0xC0C, MR18=0x7B75, DQSOSC=394, MR23=63, INC=380, DEC=253
6571 12:20:01.695238 [RxdqsGatingPostProcess] freq 400
6572 12:20:01.702110 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6573 12:20:01.705046 best DQS0 dly(2T, 0.5T) = (0, 10)
6574 12:20:01.708253 best DQS1 dly(2T, 0.5T) = (0, 10)
6575 12:20:01.711902 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6576 12:20:01.715290 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6577 12:20:01.715366 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 12:20:01.718900 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 12:20:01.721900 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 12:20:01.725227 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 12:20:01.728339 Pre-setting of DQS Precalculation
6582 12:20:01.735424 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6583 12:20:01.735500 ==
6584 12:20:01.738524 Dram Type= 6, Freq= 0, CH_1, rank 0
6585 12:20:01.742220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 12:20:01.742295 ==
6587 12:20:01.748177 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6588 12:20:01.754994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6589 12:20:01.758244 [CA 0] Center 36 (8~64) winsize 57
6590 12:20:01.758319 [CA 1] Center 36 (8~64) winsize 57
6591 12:20:01.761158 [CA 2] Center 36 (8~64) winsize 57
6592 12:20:01.764459 [CA 3] Center 36 (8~64) winsize 57
6593 12:20:01.767981 [CA 4] Center 36 (8~64) winsize 57
6594 12:20:01.770944 [CA 5] Center 36 (8~64) winsize 57
6595 12:20:01.771020
6596 12:20:01.774226 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6597 12:20:01.774300
6598 12:20:01.781178 [CATrainingPosCal] consider 1 rank data
6599 12:20:01.781261 u2DelayCellTimex100 = 270/100 ps
6600 12:20:01.787476 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 12:20:01.790837 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 12:20:01.794520 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 12:20:01.797319 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 12:20:01.800987 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 12:20:01.803877 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 12:20:01.803945
6607 12:20:01.807337 CA PerBit enable=1, Macro0, CA PI delay=36
6608 12:20:01.807414
6609 12:20:01.810423 [CBTSetCACLKResult] CA Dly = 36
6610 12:20:01.813975 CS Dly: 1 (0~32)
6611 12:20:01.814078 ==
6612 12:20:01.817256 Dram Type= 6, Freq= 0, CH_1, rank 1
6613 12:20:01.820387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 12:20:01.820468 ==
6615 12:20:01.826866 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 12:20:01.833721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6617 12:20:01.833804 [CA 0] Center 36 (8~64) winsize 57
6618 12:20:01.836970 [CA 1] Center 36 (8~64) winsize 57
6619 12:20:01.840276 [CA 2] Center 36 (8~64) winsize 57
6620 12:20:01.843683 [CA 3] Center 36 (8~64) winsize 57
6621 12:20:01.846872 [CA 4] Center 36 (8~64) winsize 57
6622 12:20:01.850406 [CA 5] Center 36 (8~64) winsize 57
6623 12:20:01.850474
6624 12:20:01.853514 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6625 12:20:01.853585
6626 12:20:01.856603 [CATrainingPosCal] consider 2 rank data
6627 12:20:01.859947 u2DelayCellTimex100 = 270/100 ps
6628 12:20:01.863215 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 12:20:01.869795 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 12:20:01.872880 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:20:01.876166 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:20:01.879612 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:20:01.882983 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:20:01.883061
6635 12:20:01.886151 CA PerBit enable=1, Macro0, CA PI delay=36
6636 12:20:01.886221
6637 12:20:01.889689 [CBTSetCACLKResult] CA Dly = 36
6638 12:20:01.892855 CS Dly: 1 (0~32)
6639 12:20:01.892932
6640 12:20:01.896245 ----->DramcWriteLeveling(PI) begin...
6641 12:20:01.896319 ==
6642 12:20:01.899742 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 12:20:01.902533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 12:20:01.902602 ==
6645 12:20:01.905764 Write leveling (Byte 0): 40 => 8
6646 12:20:01.909149 Write leveling (Byte 1): 40 => 8
6647 12:20:01.913172 DramcWriteLeveling(PI) end<-----
6648 12:20:01.913248
6649 12:20:01.913309 ==
6650 12:20:01.916134 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 12:20:01.918951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 12:20:01.919030 ==
6653 12:20:01.922325 [Gating] SW mode calibration
6654 12:20:01.928979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6655 12:20:01.935433 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6656 12:20:01.938598 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 12:20:01.945087 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 12:20:01.948526 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 12:20:01.951591 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 12:20:01.958541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 12:20:01.961694 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 12:20:01.964806 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 12:20:01.971812 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 12:20:01.974782 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 12:20:01.978306 Total UI for P1: 0, mck2ui 16
6666 12:20:01.981882 best dqsien dly found for B0: ( 0, 14, 24)
6667 12:20:01.984850 Total UI for P1: 0, mck2ui 16
6668 12:20:01.987754 best dqsien dly found for B1: ( 0, 14, 24)
6669 12:20:01.991137 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6670 12:20:01.994902 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6671 12:20:01.995011
6672 12:20:01.997565 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 12:20:02.001114 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 12:20:02.004317 [Gating] SW calibration Done
6675 12:20:02.004414 ==
6676 12:20:02.007700 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 12:20:02.013949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 12:20:02.014060 ==
6679 12:20:02.014131 RX Vref Scan: 0
6680 12:20:02.014207
6681 12:20:02.017590 RX Vref 0 -> 0, step: 1
6682 12:20:02.017671
6683 12:20:02.020596 RX Delay -410 -> 252, step: 16
6684 12:20:02.024459 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6685 12:20:02.027740 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6686 12:20:02.034364 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6687 12:20:02.037503 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6688 12:20:02.040977 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6689 12:20:02.043719 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6690 12:20:02.050434 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6691 12:20:02.053469 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6692 12:20:02.057131 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6693 12:20:02.059996 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6694 12:20:02.067055 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6695 12:20:02.070219 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6696 12:20:02.073476 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6697 12:20:02.077103 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6698 12:20:02.083371 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6699 12:20:02.086453 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6700 12:20:02.086533 ==
6701 12:20:02.089946 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 12:20:02.092916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 12:20:02.093045 ==
6704 12:20:02.097036 DQS Delay:
6705 12:20:02.097115 DQS0 = 35, DQS1 = 51
6706 12:20:02.099877 DQM Delay:
6707 12:20:02.099948 DQM0 = 6, DQM1 = 14
6708 12:20:02.100007 DQ Delay:
6709 12:20:02.102954 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6710 12:20:02.106828 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6711 12:20:02.110030 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6712 12:20:02.113522 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6713 12:20:02.113615
6714 12:20:02.113688
6715 12:20:02.113754 ==
6716 12:20:02.116121 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 12:20:02.123351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 12:20:02.123769 ==
6719 12:20:02.124092
6720 12:20:02.124392
6721 12:20:02.124679 TX Vref Scan disable
6722 12:20:02.126451 == TX Byte 0 ==
6723 12:20:02.130465 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6724 12:20:02.134428 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6725 12:20:02.136745 == TX Byte 1 ==
6726 12:20:02.139907 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 12:20:02.143515 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 12:20:02.146357 ==
6729 12:20:02.150088 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 12:20:02.153928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 12:20:02.154439 ==
6732 12:20:02.154768
6733 12:20:02.155114
6734 12:20:02.156280 TX Vref Scan disable
6735 12:20:02.156692 == TX Byte 0 ==
6736 12:20:02.159562 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 12:20:02.167182 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 12:20:02.167711 == TX Byte 1 ==
6739 12:20:02.169472 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 12:20:02.176474 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 12:20:02.176995
6742 12:20:02.177324 [DATLAT]
6743 12:20:02.177626 Freq=400, CH1 RK0
6744 12:20:02.177919
6745 12:20:02.179378 DATLAT Default: 0xf
6746 12:20:02.179794 0, 0xFFFF, sum = 0
6747 12:20:02.182784 1, 0xFFFF, sum = 0
6748 12:20:02.185802 2, 0xFFFF, sum = 0
6749 12:20:02.186221 3, 0xFFFF, sum = 0
6750 12:20:02.189513 4, 0xFFFF, sum = 0
6751 12:20:02.190054 5, 0xFFFF, sum = 0
6752 12:20:02.192263 6, 0xFFFF, sum = 0
6753 12:20:02.192685 7, 0xFFFF, sum = 0
6754 12:20:02.195639 8, 0xFFFF, sum = 0
6755 12:20:02.196062 9, 0xFFFF, sum = 0
6756 12:20:02.198942 10, 0xFFFF, sum = 0
6757 12:20:02.199406 11, 0xFFFF, sum = 0
6758 12:20:02.202519 12, 0xFFFF, sum = 0
6759 12:20:02.202959 13, 0x0, sum = 1
6760 12:20:02.205820 14, 0x0, sum = 2
6761 12:20:02.206241 15, 0x0, sum = 3
6762 12:20:02.208680 16, 0x0, sum = 4
6763 12:20:02.209102 best_step = 14
6764 12:20:02.209566
6765 12:20:02.209892 ==
6766 12:20:02.212011 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 12:20:02.218406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 12:20:02.218826 ==
6769 12:20:02.219285 RX Vref Scan: 1
6770 12:20:02.219624
6771 12:20:02.221895 RX Vref 0 -> 0, step: 1
6772 12:20:02.222321
6773 12:20:02.225437 RX Delay -343 -> 252, step: 8
6774 12:20:02.226029
6775 12:20:02.228444 Set Vref, RX VrefLevel [Byte0]: 51
6776 12:20:02.231964 [Byte1]: 53
6777 12:20:02.232486
6778 12:20:02.235124 Final RX Vref Byte 0 = 51 to rank0
6779 12:20:02.238292 Final RX Vref Byte 1 = 53 to rank0
6780 12:20:02.242098 Final RX Vref Byte 0 = 51 to rank1
6781 12:20:02.245430 Final RX Vref Byte 1 = 53 to rank1==
6782 12:20:02.248336 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 12:20:02.255220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 12:20:02.255766 ==
6785 12:20:02.256104 DQS Delay:
6786 12:20:02.258382 DQS0 = 44, DQS1 = 52
6787 12:20:02.258892 DQM Delay:
6788 12:20:02.259278 DQM0 = 10, DQM1 = 10
6789 12:20:02.261826 DQ Delay:
6790 12:20:02.264827 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6791 12:20:02.268453 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6792 12:20:02.269033 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6793 12:20:02.271364 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6794 12:20:02.274630
6795 12:20:02.275043
6796 12:20:02.281249 [DQSOSCAuto] RK0, (LSB)MR18= 0x6187, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6797 12:20:02.284548 CH1 RK0: MR19=C0C, MR18=6187
6798 12:20:02.291047 CH1_RK0: MR19=0xC0C, MR18=0x6187, DQSOSC=392, MR23=63, INC=384, DEC=256
6799 12:20:02.291664 ==
6800 12:20:02.294767 Dram Type= 6, Freq= 0, CH_1, rank 1
6801 12:20:02.297609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 12:20:02.298285 ==
6803 12:20:02.301560 [Gating] SW mode calibration
6804 12:20:02.307911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6805 12:20:02.314224 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6806 12:20:02.317504 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 12:20:02.320426 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 12:20:02.327412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 12:20:02.330314 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 12:20:02.333786 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 12:20:02.340604 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 12:20:02.343750 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 12:20:02.346654 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 12:20:02.353708 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 12:20:02.356849 Total UI for P1: 0, mck2ui 16
6816 12:20:02.359848 best dqsien dly found for B0: ( 0, 14, 24)
6817 12:20:02.363286 Total UI for P1: 0, mck2ui 16
6818 12:20:02.367058 best dqsien dly found for B1: ( 0, 14, 24)
6819 12:20:02.369748 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6820 12:20:02.373559 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6821 12:20:02.373980
6822 12:20:02.376115 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 12:20:02.379633 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 12:20:02.382749 [Gating] SW calibration Done
6825 12:20:02.383196 ==
6826 12:20:02.386042 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 12:20:02.389332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 12:20:02.392373 ==
6829 12:20:02.392794 RX Vref Scan: 0
6830 12:20:02.393120
6831 12:20:02.396315 RX Vref 0 -> 0, step: 1
6832 12:20:02.396750
6833 12:20:02.399453 RX Delay -410 -> 252, step: 16
6834 12:20:02.402841 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6835 12:20:02.405761 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6836 12:20:02.409574 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6837 12:20:02.415708 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6838 12:20:02.418972 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6839 12:20:02.422280 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6840 12:20:02.425266 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6841 12:20:02.431611 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6842 12:20:02.434731 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6843 12:20:02.438587 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6844 12:20:02.444828 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6845 12:20:02.448558 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6846 12:20:02.451560 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6847 12:20:02.455021 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6848 12:20:02.461504 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6849 12:20:02.464470 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6850 12:20:02.464578 ==
6851 12:20:02.468049 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 12:20:02.471255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 12:20:02.471339 ==
6854 12:20:02.474515 DQS Delay:
6855 12:20:02.474623 DQS0 = 43, DQS1 = 51
6856 12:20:02.477771 DQM Delay:
6857 12:20:02.477852 DQM0 = 9, DQM1 = 15
6858 12:20:02.477916 DQ Delay:
6859 12:20:02.481021 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6860 12:20:02.484443 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6861 12:20:02.487537 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6862 12:20:02.491092 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6863 12:20:02.491175
6864 12:20:02.491243
6865 12:20:02.491323 ==
6866 12:20:02.494758 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 12:20:02.500734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 12:20:02.500816 ==
6869 12:20:02.500881
6870 12:20:02.500940
6871 12:20:02.500997 TX Vref Scan disable
6872 12:20:02.504193 == TX Byte 0 ==
6873 12:20:02.507289 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6874 12:20:02.510949 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6875 12:20:02.514590 == TX Byte 1 ==
6876 12:20:02.517537 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6877 12:20:02.520661 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6878 12:20:02.520743 ==
6879 12:20:02.524367 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 12:20:02.530479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 12:20:02.530563 ==
6882 12:20:02.530626
6883 12:20:02.530688
6884 12:20:02.533772 TX Vref Scan disable
6885 12:20:02.533853 == TX Byte 0 ==
6886 12:20:02.537566 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6887 12:20:02.540059 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6888 12:20:02.543328 == TX Byte 1 ==
6889 12:20:02.546748 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6890 12:20:02.549742 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6891 12:20:02.553053
6892 12:20:02.553134 [DATLAT]
6893 12:20:02.553198 Freq=400, CH1 RK1
6894 12:20:02.553256
6895 12:20:02.557191 DATLAT Default: 0xe
6896 12:20:02.557298 0, 0xFFFF, sum = 0
6897 12:20:02.559908 1, 0xFFFF, sum = 0
6898 12:20:02.560017 2, 0xFFFF, sum = 0
6899 12:20:02.563280 3, 0xFFFF, sum = 0
6900 12:20:02.567148 4, 0xFFFF, sum = 0
6901 12:20:02.567230 5, 0xFFFF, sum = 0
6902 12:20:02.569757 6, 0xFFFF, sum = 0
6903 12:20:02.569839 7, 0xFFFF, sum = 0
6904 12:20:02.572780 8, 0xFFFF, sum = 0
6905 12:20:02.572863 9, 0xFFFF, sum = 0
6906 12:20:02.576529 10, 0xFFFF, sum = 0
6907 12:20:02.576611 11, 0xFFFF, sum = 0
6908 12:20:02.579853 12, 0xFFFF, sum = 0
6909 12:20:02.579936 13, 0x0, sum = 1
6910 12:20:02.583053 14, 0x0, sum = 2
6911 12:20:02.583176 15, 0x0, sum = 3
6912 12:20:02.586331 16, 0x0, sum = 4
6913 12:20:02.586413 best_step = 14
6914 12:20:02.586476
6915 12:20:02.586535 ==
6916 12:20:02.589662 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 12:20:02.592855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 12:20:02.595957 ==
6919 12:20:02.596038 RX Vref Scan: 0
6920 12:20:02.596102
6921 12:20:02.599750 RX Vref 0 -> 0, step: 1
6922 12:20:02.599831
6923 12:20:02.603047 RX Delay -343 -> 252, step: 8
6924 12:20:02.609332 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6925 12:20:02.612432 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6926 12:20:02.616386 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6927 12:20:02.619589 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6928 12:20:02.625538 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6929 12:20:02.628996 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6930 12:20:02.632408 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6931 12:20:02.635844 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6932 12:20:02.642915 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6933 12:20:02.645855 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6934 12:20:02.648803 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6935 12:20:02.652430 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6936 12:20:02.658762 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6937 12:20:02.662196 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6938 12:20:02.665168 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6939 12:20:02.672238 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6940 12:20:02.672322 ==
6941 12:20:02.675232 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 12:20:02.678271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 12:20:02.678353 ==
6944 12:20:02.678417 DQS Delay:
6945 12:20:02.681627 DQS0 = 48, DQS1 = 52
6946 12:20:02.681707 DQM Delay:
6947 12:20:02.685095 DQM0 = 11, DQM1 = 10
6948 12:20:02.685176 DQ Delay:
6949 12:20:02.688722 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6950 12:20:02.691715 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6951 12:20:02.694519 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6952 12:20:02.698098 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6953 12:20:02.698179
6954 12:20:02.698243
6955 12:20:02.704840 [DQSOSCAuto] RK1, (LSB)MR18= 0x629a, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
6956 12:20:02.708202 CH1 RK1: MR19=C0C, MR18=629A
6957 12:20:02.714676 CH1_RK1: MR19=0xC0C, MR18=0x629A, DQSOSC=390, MR23=63, INC=388, DEC=258
6958 12:20:02.718103 [RxdqsGatingPostProcess] freq 400
6959 12:20:02.724556 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6960 12:20:02.728253 best DQS0 dly(2T, 0.5T) = (0, 10)
6961 12:20:02.731450 best DQS1 dly(2T, 0.5T) = (0, 10)
6962 12:20:02.734434 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6963 12:20:02.737790 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6964 12:20:02.737871 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 12:20:02.740693 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 12:20:02.744086 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 12:20:02.747622 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 12:20:02.750983 Pre-setting of DQS Precalculation
6969 12:20:02.757191 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6970 12:20:02.763849 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6971 12:20:02.770507 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6972 12:20:02.770589
6973 12:20:02.770652
6974 12:20:02.773763 [Calibration Summary] 800 Mbps
6975 12:20:02.773846 CH 0, Rank 0
6976 12:20:02.777054 SW Impedance : PASS
6977 12:20:02.780439 DUTY Scan : NO K
6978 12:20:02.780520 ZQ Calibration : PASS
6979 12:20:02.783489 Jitter Meter : NO K
6980 12:20:02.786732 CBT Training : PASS
6981 12:20:02.786813 Write leveling : PASS
6982 12:20:02.790021 RX DQS gating : PASS
6983 12:20:02.793897 RX DQ/DQS(RDDQC) : PASS
6984 12:20:02.793977 TX DQ/DQS : PASS
6985 12:20:02.796543 RX DATLAT : PASS
6986 12:20:02.799847 RX DQ/DQS(Engine): PASS
6987 12:20:02.799928 TX OE : NO K
6988 12:20:02.803025 All Pass.
6989 12:20:02.803121
6990 12:20:02.803186 CH 0, Rank 1
6991 12:20:02.806120 SW Impedance : PASS
6992 12:20:02.806200 DUTY Scan : NO K
6993 12:20:02.809853 ZQ Calibration : PASS
6994 12:20:02.812887 Jitter Meter : NO K
6995 12:20:02.812968 CBT Training : PASS
6996 12:20:02.816311 Write leveling : NO K
6997 12:20:02.819576 RX DQS gating : PASS
6998 12:20:02.819657 RX DQ/DQS(RDDQC) : PASS
6999 12:20:02.822839 TX DQ/DQS : PASS
7000 12:20:02.826234 RX DATLAT : PASS
7001 12:20:02.826316 RX DQ/DQS(Engine): PASS
7002 12:20:02.829309 TX OE : NO K
7003 12:20:02.829390 All Pass.
7004 12:20:02.829453
7005 12:20:02.832623 CH 1, Rank 0
7006 12:20:02.832704 SW Impedance : PASS
7007 12:20:02.837220 DUTY Scan : NO K
7008 12:20:02.839407 ZQ Calibration : PASS
7009 12:20:02.839489 Jitter Meter : NO K
7010 12:20:02.842850 CBT Training : PASS
7011 12:20:02.845865 Write leveling : PASS
7012 12:20:02.845945 RX DQS gating : PASS
7013 12:20:02.849135 RX DQ/DQS(RDDQC) : PASS
7014 12:20:02.853034 TX DQ/DQS : PASS
7015 12:20:02.853116 RX DATLAT : PASS
7016 12:20:02.856027 RX DQ/DQS(Engine): PASS
7017 12:20:02.858919 TX OE : NO K
7018 12:20:02.859001 All Pass.
7019 12:20:02.859064
7020 12:20:02.859170 CH 1, Rank 1
7021 12:20:02.862513 SW Impedance : PASS
7022 12:20:02.865492 DUTY Scan : NO K
7023 12:20:02.865574 ZQ Calibration : PASS
7024 12:20:02.869315 Jitter Meter : NO K
7025 12:20:02.872453 CBT Training : PASS
7026 12:20:02.872534 Write leveling : NO K
7027 12:20:02.875966 RX DQS gating : PASS
7028 12:20:02.876048 RX DQ/DQS(RDDQC) : PASS
7029 12:20:02.879308 TX DQ/DQS : PASS
7030 12:20:02.881979 RX DATLAT : PASS
7031 12:20:02.882060 RX DQ/DQS(Engine): PASS
7032 12:20:02.885482 TX OE : NO K
7033 12:20:02.885563 All Pass.
7034 12:20:02.885626
7035 12:20:02.888335 DramC Write-DBI off
7036 12:20:02.891939 PER_BANK_REFRESH: Hybrid Mode
7037 12:20:02.892021 TX_TRACKING: ON
7038 12:20:02.902260 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7039 12:20:02.905257 [FAST_K] Save calibration result to emmc
7040 12:20:02.908303 dramc_set_vcore_voltage set vcore to 725000
7041 12:20:02.912095 Read voltage for 1600, 0
7042 12:20:02.912177 Vio18 = 0
7043 12:20:02.914858 Vcore = 725000
7044 12:20:02.914938 Vdram = 0
7045 12:20:02.915001 Vddq = 0
7046 12:20:02.915061 Vmddr = 0
7047 12:20:02.921834 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7048 12:20:02.928016 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7049 12:20:02.928101 MEM_TYPE=3, freq_sel=13
7050 12:20:02.931250 sv_algorithm_assistance_LP4_3733
7051 12:20:02.934732 ============ PULL DRAM RESETB DOWN ============
7052 12:20:02.941140 ========== PULL DRAM RESETB DOWN end =========
7053 12:20:02.945816 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7054 12:20:02.948078 ===================================
7055 12:20:02.951558 LPDDR4 DRAM CONFIGURATION
7056 12:20:02.954250 ===================================
7057 12:20:02.954330 EX_ROW_EN[0] = 0x0
7058 12:20:02.957816 EX_ROW_EN[1] = 0x0
7059 12:20:02.961643 LP4Y_EN = 0x0
7060 12:20:02.961724 WORK_FSP = 0x1
7061 12:20:02.964713 WL = 0x5
7062 12:20:02.964795 RL = 0x5
7063 12:20:02.968460 BL = 0x2
7064 12:20:02.968542 RPST = 0x0
7065 12:20:02.970943 RD_PRE = 0x0
7066 12:20:02.971050 WR_PRE = 0x1
7067 12:20:02.974388 WR_PST = 0x1
7068 12:20:02.974470 DBI_WR = 0x0
7069 12:20:02.977690 DBI_RD = 0x0
7070 12:20:02.977771 OTF = 0x1
7071 12:20:02.980648 ===================================
7072 12:20:02.984064 ===================================
7073 12:20:02.987490 ANA top config
7074 12:20:02.991038 ===================================
7075 12:20:02.991164 DLL_ASYNC_EN = 0
7076 12:20:02.994311 ALL_SLAVE_EN = 0
7077 12:20:02.997157 NEW_RANK_MODE = 1
7078 12:20:03.001141 DLL_IDLE_MODE = 1
7079 12:20:03.004200 LP45_APHY_COMB_EN = 1
7080 12:20:03.004281 TX_ODT_DIS = 0
7081 12:20:03.007290 NEW_8X_MODE = 1
7082 12:20:03.010634 ===================================
7083 12:20:03.014349 ===================================
7084 12:20:03.016820 data_rate = 3200
7085 12:20:03.020792 CKR = 1
7086 12:20:03.023540 DQ_P2S_RATIO = 8
7087 12:20:03.026900 ===================================
7088 12:20:03.030420 CA_P2S_RATIO = 8
7089 12:20:03.030501 DQ_CA_OPEN = 0
7090 12:20:03.033590 DQ_SEMI_OPEN = 0
7091 12:20:03.037041 CA_SEMI_OPEN = 0
7092 12:20:03.040164 CA_FULL_RATE = 0
7093 12:20:03.043030 DQ_CKDIV4_EN = 0
7094 12:20:03.046580 CA_CKDIV4_EN = 0
7095 12:20:03.046661 CA_PREDIV_EN = 0
7096 12:20:03.050301 PH8_DLY = 12
7097 12:20:03.053093 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7098 12:20:03.056416 DQ_AAMCK_DIV = 4
7099 12:20:03.059680 CA_AAMCK_DIV = 4
7100 12:20:03.062997 CA_ADMCK_DIV = 4
7101 12:20:03.066645 DQ_TRACK_CA_EN = 0
7102 12:20:03.066727 CA_PICK = 1600
7103 12:20:03.069745 CA_MCKIO = 1600
7104 12:20:03.072890 MCKIO_SEMI = 0
7105 12:20:03.077058 PLL_FREQ = 3068
7106 12:20:03.079514 DQ_UI_PI_RATIO = 32
7107 12:20:03.082909 CA_UI_PI_RATIO = 0
7108 12:20:03.086411 ===================================
7109 12:20:03.089331 ===================================
7110 12:20:03.092959 memory_type:LPDDR4
7111 12:20:03.093040 GP_NUM : 10
7112 12:20:03.095825 SRAM_EN : 1
7113 12:20:03.095905 MD32_EN : 0
7114 12:20:03.099206 ===================================
7115 12:20:03.102628 [ANA_INIT] >>>>>>>>>>>>>>
7116 12:20:03.105558 <<<<<< [CONFIGURE PHASE]: ANA_TX
7117 12:20:03.109376 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7118 12:20:03.112735 ===================================
7119 12:20:03.115312 data_rate = 3200,PCW = 0X7600
7120 12:20:03.118803 ===================================
7121 12:20:03.121903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7122 12:20:03.128817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 12:20:03.132518 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 12:20:03.138448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7125 12:20:03.142003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7126 12:20:03.145065 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7127 12:20:03.145147 [ANA_INIT] flow start
7128 12:20:03.148756 [ANA_INIT] PLL >>>>>>>>
7129 12:20:03.151866 [ANA_INIT] PLL <<<<<<<<
7130 12:20:03.154861 [ANA_INIT] MIDPI >>>>>>>>
7131 12:20:03.154942 [ANA_INIT] MIDPI <<<<<<<<
7132 12:20:03.158148 [ANA_INIT] DLL >>>>>>>>
7133 12:20:03.163199 [ANA_INIT] DLL <<<<<<<<
7134 12:20:03.163281 [ANA_INIT] flow end
7135 12:20:03.164668 ============ LP4 DIFF to SE enter ============
7136 12:20:03.171399 ============ LP4 DIFF to SE exit ============
7137 12:20:03.171482 [ANA_INIT] <<<<<<<<<<<<<
7138 12:20:03.174495 [Flow] Enable top DCM control >>>>>
7139 12:20:03.178716 [Flow] Enable top DCM control <<<<<
7140 12:20:03.181875 Enable DLL master slave shuffle
7141 12:20:03.188096 ==============================================================
7142 12:20:03.191920 Gating Mode config
7143 12:20:03.194878 ==============================================================
7144 12:20:03.198503 Config description:
7145 12:20:03.207929 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7146 12:20:03.214385 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7147 12:20:03.217544 SELPH_MODE 0: By rank 1: By Phase
7148 12:20:03.224438 ==============================================================
7149 12:20:03.227793 GAT_TRACK_EN = 1
7150 12:20:03.231132 RX_GATING_MODE = 2
7151 12:20:03.234201 RX_GATING_TRACK_MODE = 2
7152 12:20:03.237715 SELPH_MODE = 1
7153 12:20:03.240997 PICG_EARLY_EN = 1
7154 12:20:03.241228 VALID_LAT_VALUE = 1
7155 12:20:03.247043 ==============================================================
7156 12:20:03.250452 Enter into Gating configuration >>>>
7157 12:20:03.253795 Exit from Gating configuration <<<<
7158 12:20:03.257061 Enter into DVFS_PRE_config >>>>>
7159 12:20:03.267233 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7160 12:20:03.270682 Exit from DVFS_PRE_config <<<<<
7161 12:20:03.273815 Enter into PICG configuration >>>>
7162 12:20:03.276732 Exit from PICG configuration <<<<
7163 12:20:03.280494 [RX_INPUT] configuration >>>>>
7164 12:20:03.283618 [RX_INPUT] configuration <<<<<
7165 12:20:03.290445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7166 12:20:03.293690 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7167 12:20:03.299944 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 12:20:03.306835 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 12:20:03.313270 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7170 12:20:03.319357 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7171 12:20:03.322679 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7172 12:20:03.326423 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7173 12:20:03.329950 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7174 12:20:03.336221 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7175 12:20:03.339549 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7176 12:20:03.342992 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7177 12:20:03.346653 ===================================
7178 12:20:03.349285 LPDDR4 DRAM CONFIGURATION
7179 12:20:03.352801 ===================================
7180 12:20:03.356232 EX_ROW_EN[0] = 0x0
7181 12:20:03.356747 EX_ROW_EN[1] = 0x0
7182 12:20:03.359238 LP4Y_EN = 0x0
7183 12:20:03.359775 WORK_FSP = 0x1
7184 12:20:03.362467 WL = 0x5
7185 12:20:03.362882 RL = 0x5
7186 12:20:03.365812 BL = 0x2
7187 12:20:03.366331 RPST = 0x0
7188 12:20:03.369017 RD_PRE = 0x0
7189 12:20:03.372070 WR_PRE = 0x1
7190 12:20:03.372488 WR_PST = 0x1
7191 12:20:03.375381 DBI_WR = 0x0
7192 12:20:03.375796 DBI_RD = 0x0
7193 12:20:03.378802 OTF = 0x1
7194 12:20:03.382144 ===================================
7195 12:20:03.385810 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7196 12:20:03.388670 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7197 12:20:03.391504 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7198 12:20:03.395149 ===================================
7199 12:20:03.398316 LPDDR4 DRAM CONFIGURATION
7200 12:20:03.402131 ===================================
7201 12:20:03.406176 EX_ROW_EN[0] = 0x10
7202 12:20:03.406724 EX_ROW_EN[1] = 0x0
7203 12:20:03.408114 LP4Y_EN = 0x0
7204 12:20:03.408528 WORK_FSP = 0x1
7205 12:20:03.411439 WL = 0x5
7206 12:20:03.411857 RL = 0x5
7207 12:20:03.414604 BL = 0x2
7208 12:20:03.418507 RPST = 0x0
7209 12:20:03.419131 RD_PRE = 0x0
7210 12:20:03.421294 WR_PRE = 0x1
7211 12:20:03.421727 WR_PST = 0x1
7212 12:20:03.424669 DBI_WR = 0x0
7213 12:20:03.425086 DBI_RD = 0x0
7214 12:20:03.428369 OTF = 0x1
7215 12:20:03.431022 ===================================
7216 12:20:03.437986 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7217 12:20:03.438493 ==
7218 12:20:03.441352 Dram Type= 6, Freq= 0, CH_0, rank 0
7219 12:20:03.444590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7220 12:20:03.445228 ==
7221 12:20:03.447326 [Duty_Offset_Calibration]
7222 12:20:03.447827 B0:2 B1:0 CA:4
7223 12:20:03.448276
7224 12:20:03.450801 [DutyScan_Calibration_Flow] k_type=0
7225 12:20:03.460517
7226 12:20:03.461020 ==CLK 0==
7227 12:20:03.463778 Final CLK duty delay cell = -4
7228 12:20:03.467478 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7229 12:20:03.470550 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7230 12:20:03.473948 [-4] AVG Duty = 4922%(X100)
7231 12:20:03.474395
7232 12:20:03.478500 CH0 CLK Duty spec in!! Max-Min= 218%
7233 12:20:03.479958 [DutyScan_Calibration_Flow] ====Done====
7234 12:20:03.480367
7235 12:20:03.483829 [DutyScan_Calibration_Flow] k_type=1
7236 12:20:03.500697
7237 12:20:03.501234 ==DQS 0 ==
7238 12:20:03.503582 Final DQS duty delay cell = 0
7239 12:20:03.507108 [0] MAX Duty = 5218%(X100), DQS PI = 22
7240 12:20:03.510420 [0] MIN Duty = 5093%(X100), DQS PI = 6
7241 12:20:03.513631 [0] AVG Duty = 5155%(X100)
7242 12:20:03.514194
7243 12:20:03.514632 ==DQS 1 ==
7244 12:20:03.517280 Final DQS duty delay cell = 0
7245 12:20:03.520466 [0] MAX Duty = 5156%(X100), DQS PI = 2
7246 12:20:03.524200 [0] MIN Duty = 4969%(X100), DQS PI = 10
7247 12:20:03.527015 [0] AVG Duty = 5062%(X100)
7248 12:20:03.527467
7249 12:20:03.530003 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7250 12:20:03.530410
7251 12:20:03.533341 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7252 12:20:03.537090 [DutyScan_Calibration_Flow] ====Done====
7253 12:20:03.537499
7254 12:20:03.539904 [DutyScan_Calibration_Flow] k_type=3
7255 12:20:03.557516
7256 12:20:03.558162 ==DQM 0 ==
7257 12:20:03.560713 Final DQM duty delay cell = 0
7258 12:20:03.564906 [0] MAX Duty = 5124%(X100), DQS PI = 22
7259 12:20:03.567765 [0] MIN Duty = 4875%(X100), DQS PI = 54
7260 12:20:03.571621 [0] AVG Duty = 4999%(X100)
7261 12:20:03.572128
7262 12:20:03.572450 ==DQM 1 ==
7263 12:20:03.574305 Final DQM duty delay cell = 0
7264 12:20:03.577564 [0] MAX Duty = 4969%(X100), DQS PI = 0
7265 12:20:03.581067 [0] MIN Duty = 4844%(X100), DQS PI = 14
7266 12:20:03.584120 [0] AVG Duty = 4906%(X100)
7267 12:20:03.584526
7268 12:20:03.587663 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7269 12:20:03.588072
7270 12:20:03.591325 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7271 12:20:03.594621 [DutyScan_Calibration_Flow] ====Done====
7272 12:20:03.595035
7273 12:20:03.597464 [DutyScan_Calibration_Flow] k_type=2
7274 12:20:03.614888
7275 12:20:03.615611 ==DQ 0 ==
7276 12:20:03.618266 Final DQ duty delay cell = 0
7277 12:20:03.621442 [0] MAX Duty = 5156%(X100), DQS PI = 26
7278 12:20:03.625095 [0] MIN Duty = 4938%(X100), DQS PI = 58
7279 12:20:03.625514 [0] AVG Duty = 5047%(X100)
7280 12:20:03.627935
7281 12:20:03.628363 ==DQ 1 ==
7282 12:20:03.631651 Final DQ duty delay cell = 0
7283 12:20:03.634634 [0] MAX Duty = 5187%(X100), DQS PI = 2
7284 12:20:03.638349 [0] MIN Duty = 4907%(X100), DQS PI = 34
7285 12:20:03.638867 [0] AVG Duty = 5047%(X100)
7286 12:20:03.641285
7287 12:20:03.644501 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7288 12:20:03.645017
7289 12:20:03.648223 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7290 12:20:03.651192 [DutyScan_Calibration_Flow] ====Done====
7291 12:20:03.651711 ==
7292 12:20:03.654795 Dram Type= 6, Freq= 0, CH_1, rank 0
7293 12:20:03.657314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 12:20:03.657731 ==
7295 12:20:03.660845 [Duty_Offset_Calibration]
7296 12:20:03.661259 B0:0 B1:-1 CA:3
7297 12:20:03.661578
7298 12:20:03.663959 [DutyScan_Calibration_Flow] k_type=0
7299 12:20:03.673959
7300 12:20:03.674376 ==CLK 0==
7301 12:20:03.677261 Final CLK duty delay cell = -4
7302 12:20:03.680782 [-4] MAX Duty = 5000%(X100), DQS PI = 2
7303 12:20:03.684208 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7304 12:20:03.687631 [-4] AVG Duty = 4922%(X100)
7305 12:20:03.688138
7306 12:20:03.690782 CH1 CLK Duty spec in!! Max-Min= 156%
7307 12:20:03.693873 [DutyScan_Calibration_Flow] ====Done====
7308 12:20:03.694286
7309 12:20:03.696954 [DutyScan_Calibration_Flow] k_type=1
7310 12:20:03.713296
7311 12:20:03.713810 ==DQS 0 ==
7312 12:20:03.716833 Final DQS duty delay cell = 0
7313 12:20:03.719953 [0] MAX Duty = 5250%(X100), DQS PI = 30
7314 12:20:03.723018 [0] MIN Duty = 4938%(X100), DQS PI = 40
7315 12:20:03.726882 [0] AVG Duty = 5094%(X100)
7316 12:20:03.727329
7317 12:20:03.727644 ==DQS 1 ==
7318 12:20:03.730024 Final DQS duty delay cell = -4
7319 12:20:03.733395 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7320 12:20:03.736450 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7321 12:20:03.740053 [-4] AVG Duty = 4922%(X100)
7322 12:20:03.740455
7323 12:20:03.743431 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7324 12:20:03.743936
7325 12:20:03.746201 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7326 12:20:03.750177 [DutyScan_Calibration_Flow] ====Done====
7327 12:20:03.750695
7328 12:20:03.752969 [DutyScan_Calibration_Flow] k_type=3
7329 12:20:03.770552
7330 12:20:03.771052 ==DQM 0 ==
7331 12:20:03.774142 Final DQM duty delay cell = 0
7332 12:20:03.777456 [0] MAX Duty = 5062%(X100), DQS PI = 30
7333 12:20:03.780583 [0] MIN Duty = 4782%(X100), DQS PI = 38
7334 12:20:03.783787 [0] AVG Duty = 4922%(X100)
7335 12:20:03.784211
7336 12:20:03.784542 ==DQM 1 ==
7337 12:20:03.787252 Final DQM duty delay cell = 0
7338 12:20:03.790508 [0] MAX Duty = 5000%(X100), DQS PI = 30
7339 12:20:03.793663 [0] MIN Duty = 4813%(X100), DQS PI = 0
7340 12:20:03.796753 [0] AVG Duty = 4906%(X100)
7341 12:20:03.797103
7342 12:20:03.799952 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7343 12:20:03.800182
7344 12:20:03.803173 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7345 12:20:03.806874 [DutyScan_Calibration_Flow] ====Done====
7346 12:20:03.807094
7347 12:20:03.809916 [DutyScan_Calibration_Flow] k_type=2
7348 12:20:03.826377
7349 12:20:03.826548 ==DQ 0 ==
7350 12:20:03.829854 Final DQ duty delay cell = -4
7351 12:20:03.833120 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7352 12:20:03.836701 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7353 12:20:03.840213 [-4] AVG Duty = 4875%(X100)
7354 12:20:03.840370
7355 12:20:03.840439 ==DQ 1 ==
7356 12:20:03.842679 Final DQ duty delay cell = 0
7357 12:20:03.845945 [0] MAX Duty = 5031%(X100), DQS PI = 30
7358 12:20:03.849306 [0] MIN Duty = 4875%(X100), DQS PI = 54
7359 12:20:03.852998 [0] AVG Duty = 4953%(X100)
7360 12:20:03.853153
7361 12:20:03.855588 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7362 12:20:03.855750
7363 12:20:03.859181 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7364 12:20:03.862384 [DutyScan_Calibration_Flow] ====Done====
7365 12:20:03.866186 nWR fixed to 30
7366 12:20:03.869185 [ModeRegInit_LP4] CH0 RK0
7367 12:20:03.869595 [ModeRegInit_LP4] CH0 RK1
7368 12:20:03.872782 [ModeRegInit_LP4] CH1 RK0
7369 12:20:03.875597 [ModeRegInit_LP4] CH1 RK1
7370 12:20:03.876032 match AC timing 5
7371 12:20:03.882753 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7372 12:20:03.886430 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7373 12:20:03.889008 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7374 12:20:03.895794 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7375 12:20:03.898691 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7376 12:20:03.902622 [MiockJmeterHQA]
7377 12:20:03.903179
7378 12:20:03.905879 [DramcMiockJmeter] u1RxGatingPI = 0
7379 12:20:03.906394 0 : 4257, 4032
7380 12:20:03.906724 4 : 4255, 4029
7381 12:20:03.908721 8 : 4252, 4027
7382 12:20:03.909239 12 : 4255, 4029
7383 12:20:03.912096 16 : 4255, 4029
7384 12:20:03.912523 20 : 4252, 4027
7385 12:20:03.914915 24 : 4252, 4027
7386 12:20:03.915382 28 : 4363, 4137
7387 12:20:03.919261 32 : 4252, 4027
7388 12:20:03.919802 36 : 4253, 4027
7389 12:20:03.920149 40 : 4250, 4027
7390 12:20:03.922039 44 : 4255, 4029
7391 12:20:03.922530 48 : 4250, 4026
7392 12:20:03.925289 52 : 4252, 4027
7393 12:20:03.925749 56 : 4366, 4140
7394 12:20:03.929051 60 : 4250, 4027
7395 12:20:03.929565 64 : 4252, 4029
7396 12:20:03.931910 68 : 4250, 4027
7397 12:20:03.932327 72 : 4361, 4138
7398 12:20:03.932660 76 : 4250, 4027
7399 12:20:03.935436 80 : 4250, 4026
7400 12:20:03.936126 84 : 4252, 4030
7401 12:20:03.938364 88 : 4250, 4027
7402 12:20:03.938813 92 : 4250, 4027
7403 12:20:03.941647 96 : 4250, 3142
7404 12:20:03.942162 100 : 4250, 0
7405 12:20:03.942494 104 : 4250, 0
7406 12:20:03.946390 108 : 4250, 0
7407 12:20:03.946952 112 : 4250, 0
7408 12:20:03.948090 116 : 4250, 0
7409 12:20:03.948453 120 : 4249, 0
7410 12:20:03.948764 124 : 4250, 0
7411 12:20:03.951714 128 : 4360, 0
7412 12:20:03.952238 132 : 4361, 0
7413 12:20:03.954812 136 : 4250, 0
7414 12:20:03.955275 140 : 4252, 0
7415 12:20:03.955611 144 : 4250, 0
7416 12:20:03.958134 148 : 4250, 0
7417 12:20:03.958550 152 : 4250, 0
7418 12:20:03.961412 156 : 4249, 0
7419 12:20:03.961831 160 : 4252, 0
7420 12:20:03.962158 164 : 4250, 0
7421 12:20:03.964823 168 : 4360, 0
7422 12:20:03.965355 172 : 4250, 0
7423 12:20:03.967995 176 : 4361, 0
7424 12:20:03.968508 180 : 4360, 0
7425 12:20:03.968846 184 : 4250, 0
7426 12:20:03.971637 188 : 4250, 0
7427 12:20:03.972054 192 : 4250, 0
7428 12:20:03.972383 196 : 4250, 0
7429 12:20:03.974405 200 : 4250, 0
7430 12:20:03.974825 204 : 4250, 0
7431 12:20:03.977423 208 : 4249, 0
7432 12:20:03.978029 212 : 4249, 0
7433 12:20:03.978368 216 : 4250, 0
7434 12:20:03.981131 220 : 4249, 343
7435 12:20:03.981551 224 : 4361, 4045
7436 12:20:03.984147 228 : 4363, 4140
7437 12:20:03.984562 232 : 4250, 4027
7438 12:20:03.987848 236 : 4255, 4030
7439 12:20:03.988265 240 : 4250, 4026
7440 12:20:03.990959 244 : 4363, 4138
7441 12:20:03.991515 248 : 4250, 4027
7442 12:20:03.994494 252 : 4363, 4138
7443 12:20:03.995014 256 : 4250, 4026
7444 12:20:03.997596 260 : 4250, 4027
7445 12:20:03.998118 264 : 4249, 4027
7446 12:20:04.001317 268 : 4250, 4027
7447 12:20:04.001838 272 : 4250, 4027
7448 12:20:04.004035 276 : 4361, 4137
7449 12:20:04.004454 280 : 4250, 4027
7450 12:20:04.004785 284 : 4250, 4027
7451 12:20:04.007697 288 : 4250, 4027
7452 12:20:04.008204 292 : 4250, 4026
7453 12:20:04.010587 296 : 4361, 4138
7454 12:20:04.011051 300 : 4250, 4027
7455 12:20:04.014529 304 : 4360, 4138
7456 12:20:04.015039 308 : 4250, 4026
7457 12:20:04.017305 312 : 4250, 4027
7458 12:20:04.017726 316 : 4250, 4027
7459 12:20:04.020654 320 : 4250, 4027
7460 12:20:04.021108 324 : 4255, 4029
7461 12:20:04.023654 328 : 4361, 4137
7462 12:20:04.024069 332 : 4250, 4024
7463 12:20:04.027132 336 : 4250, 2136
7464 12:20:04.027546 340 : 4250, 7
7465 12:20:04.027873
7466 12:20:04.030585 MIOCK jitter meter ch=0
7467 12:20:04.030990
7468 12:20:04.033634 1T = (340-100) = 240 dly cells
7469 12:20:04.037092 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7470 12:20:04.037500 ==
7471 12:20:04.040433 Dram Type= 6, Freq= 0, CH_0, rank 0
7472 12:20:04.046909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7473 12:20:04.047456 ==
7474 12:20:04.049962 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7475 12:20:04.057165 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7476 12:20:04.060662 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7477 12:20:04.066668 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7478 12:20:04.075650 [CA 0] Center 43 (13~74) winsize 62
7479 12:20:04.078788 [CA 1] Center 42 (12~73) winsize 62
7480 12:20:04.080902 [CA 2] Center 37 (8~67) winsize 60
7481 12:20:04.084665 [CA 3] Center 37 (8~67) winsize 60
7482 12:20:04.088792 [CA 4] Center 36 (6~66) winsize 61
7483 12:20:04.090757 [CA 5] Center 35 (5~66) winsize 62
7484 12:20:04.091232
7485 12:20:04.094173 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7486 12:20:04.094580
7487 12:20:04.100970 [CATrainingPosCal] consider 1 rank data
7488 12:20:04.101380 u2DelayCellTimex100 = 271/100 ps
7489 12:20:04.107112 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7490 12:20:04.110145 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7491 12:20:04.113925 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7492 12:20:04.117000 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7493 12:20:04.119896 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7494 12:20:04.123546 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7495 12:20:04.123958
7496 12:20:04.127680 CA PerBit enable=1, Macro0, CA PI delay=35
7497 12:20:04.128089
7498 12:20:04.129939 [CBTSetCACLKResult] CA Dly = 35
7499 12:20:04.133588 CS Dly: 11 (0~42)
7500 12:20:04.136763 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7501 12:20:04.139865 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7502 12:20:04.140273 ==
7503 12:20:04.143234 Dram Type= 6, Freq= 0, CH_0, rank 1
7504 12:20:04.149650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7505 12:20:04.150062 ==
7506 12:20:04.153433 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7507 12:20:04.159911 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7508 12:20:04.163395 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7509 12:20:04.169620 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7510 12:20:04.177828 [CA 0] Center 44 (14~75) winsize 62
7511 12:20:04.181304 [CA 1] Center 44 (14~74) winsize 61
7512 12:20:04.184283 [CA 2] Center 39 (10~69) winsize 60
7513 12:20:04.187389 [CA 3] Center 39 (10~68) winsize 59
7514 12:20:04.191104 [CA 4] Center 37 (7~67) winsize 61
7515 12:20:04.194285 [CA 5] Center 36 (7~66) winsize 60
7516 12:20:04.194690
7517 12:20:04.197414 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7518 12:20:04.197961
7519 12:20:04.204629 [CATrainingPosCal] consider 2 rank data
7520 12:20:04.205040 u2DelayCellTimex100 = 271/100 ps
7521 12:20:04.210479 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7522 12:20:04.213818 CA1 delay=43 (14~73),Diff = 7 PI (25 cell)
7523 12:20:04.217100 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7524 12:20:04.220657 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7525 12:20:04.223760 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7526 12:20:04.226964 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7527 12:20:04.227201
7528 12:20:04.230117 CA PerBit enable=1, Macro0, CA PI delay=36
7529 12:20:04.230335
7530 12:20:04.234025 [CBTSetCACLKResult] CA Dly = 36
7531 12:20:04.236882 CS Dly: 12 (0~44)
7532 12:20:04.240212 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7533 12:20:04.243748 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7534 12:20:04.243967
7535 12:20:04.247068 ----->DramcWriteLeveling(PI) begin...
7536 12:20:04.250529 ==
7537 12:20:04.254078 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 12:20:04.257111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 12:20:04.257330 ==
7540 12:20:04.259875 Write leveling (Byte 0): 36 => 36
7541 12:20:04.263873 Write leveling (Byte 1): 26 => 26
7542 12:20:04.267231 DramcWriteLeveling(PI) end<-----
7543 12:20:04.267448
7544 12:20:04.267640 ==
7545 12:20:04.270501 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 12:20:04.273592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 12:20:04.273673 ==
7548 12:20:04.276023 [Gating] SW mode calibration
7549 12:20:04.282884 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7550 12:20:04.289530 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7551 12:20:04.293152 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 12:20:04.296105 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 12:20:04.302708 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7554 12:20:04.306256 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7555 12:20:04.309895 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7556 12:20:04.315907 1 4 20 | B1->B0 | 2d2d 3434 | 0 1 | (1 1) (1 1)
7557 12:20:04.318916 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 12:20:04.322626 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 12:20:04.329029 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 12:20:04.332462 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 12:20:04.335527 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7562 12:20:04.342157 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7563 12:20:04.345429 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7564 12:20:04.348695 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7565 12:20:04.356489 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7566 12:20:04.358651 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 12:20:04.362015 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 12:20:04.368767 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 12:20:04.371723 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7570 12:20:04.374979 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7571 12:20:04.381476 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7572 12:20:04.385105 1 6 20 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
7573 12:20:04.388423 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 12:20:04.394770 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 12:20:04.398050 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 12:20:04.401392 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 12:20:04.408037 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 12:20:04.411492 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 12:20:04.414433 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7580 12:20:04.421900 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7581 12:20:04.424636 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 12:20:04.427712 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7583 12:20:04.434159 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:20:04.437726 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:20:04.440784 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 12:20:04.447749 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 12:20:04.451258 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 12:20:04.454944 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 12:20:04.461174 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 12:20:04.464776 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 12:20:04.467454 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 12:20:04.474032 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 12:20:04.477372 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 12:20:04.480629 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7595 12:20:04.487038 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7596 12:20:04.490117 Total UI for P1: 0, mck2ui 16
7597 12:20:04.493878 best dqsien dly found for B0: ( 1, 9, 10)
7598 12:20:04.496706 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 12:20:04.500189 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 12:20:04.503306 Total UI for P1: 0, mck2ui 16
7601 12:20:04.507059 best dqsien dly found for B1: ( 1, 9, 20)
7602 12:20:04.510068 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7603 12:20:04.516410 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7604 12:20:04.516819
7605 12:20:04.519763 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7606 12:20:04.523023 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7607 12:20:04.526360 [Gating] SW calibration Done
7608 12:20:04.526854 ==
7609 12:20:04.529796 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 12:20:04.533003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 12:20:04.533418 ==
7612 12:20:04.536098 RX Vref Scan: 0
7613 12:20:04.536508
7614 12:20:04.536827 RX Vref 0 -> 0, step: 1
7615 12:20:04.537123
7616 12:20:04.539573 RX Delay 0 -> 252, step: 8
7617 12:20:04.542851 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7618 12:20:04.549306 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7619 12:20:04.552771 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7620 12:20:04.556402 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7621 12:20:04.559370 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7622 12:20:04.563153 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7623 12:20:04.569865 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7624 12:20:04.572481 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7625 12:20:04.575778 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7626 12:20:04.579150 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7627 12:20:04.582929 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7628 12:20:04.589047 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7629 12:20:04.591952 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7630 12:20:04.595648 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7631 12:20:04.598925 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7632 12:20:04.605477 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7633 12:20:04.605892 ==
7634 12:20:04.608555 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 12:20:04.612038 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 12:20:04.612453 ==
7637 12:20:04.612775 DQS Delay:
7638 12:20:04.615164 DQS0 = 0, DQS1 = 0
7639 12:20:04.615822 DQM Delay:
7640 12:20:04.618731 DQM0 = 131, DQM1 = 126
7641 12:20:04.619602 DQ Delay:
7642 12:20:04.622191 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7643 12:20:04.625043 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7644 12:20:04.628163 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7645 12:20:04.631683 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7646 12:20:04.632207
7647 12:20:04.632667
7648 12:20:04.635230 ==
7649 12:20:04.638463 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 12:20:04.641484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 12:20:04.641798 ==
7652 12:20:04.642104
7653 12:20:04.642391
7654 12:20:04.645213 TX Vref Scan disable
7655 12:20:04.645440 == TX Byte 0 ==
7656 12:20:04.651425 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7657 12:20:04.654612 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7658 12:20:04.654796 == TX Byte 1 ==
7659 12:20:04.661231 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7660 12:20:04.664375 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7661 12:20:04.664516 ==
7662 12:20:04.667830 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 12:20:04.671326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 12:20:04.671454 ==
7665 12:20:04.686073
7666 12:20:04.688645 TX Vref early break, caculate TX vref
7667 12:20:04.692139 TX Vref=16, minBit 1, minWin=22, winSum=367
7668 12:20:04.695048 TX Vref=18, minBit 1, minWin=23, winSum=380
7669 12:20:04.698809 TX Vref=20, minBit 1, minWin=23, winSum=386
7670 12:20:04.702174 TX Vref=22, minBit 0, minWin=24, winSum=399
7671 12:20:04.705374 TX Vref=24, minBit 1, minWin=24, winSum=409
7672 12:20:04.712578 TX Vref=26, minBit 2, minWin=25, winSum=420
7673 12:20:04.715324 TX Vref=28, minBit 2, minWin=25, winSum=424
7674 12:20:04.718293 TX Vref=30, minBit 0, minWin=25, winSum=423
7675 12:20:04.721678 TX Vref=32, minBit 2, minWin=24, winSum=410
7676 12:20:04.725214 TX Vref=34, minBit 4, minWin=23, winSum=398
7677 12:20:04.731835 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 28
7678 12:20:04.731917
7679 12:20:04.735129 Final TX Range 0 Vref 28
7680 12:20:04.735213
7681 12:20:04.735295 ==
7682 12:20:04.738580 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 12:20:04.741432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 12:20:04.741513 ==
7685 12:20:04.741577
7686 12:20:04.741636
7687 12:20:04.745136 TX Vref Scan disable
7688 12:20:04.751297 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7689 12:20:04.751376 == TX Byte 0 ==
7690 12:20:04.754669 u2DelayCellOfst[0]=10 cells (3 PI)
7691 12:20:04.757935 u2DelayCellOfst[1]=14 cells (4 PI)
7692 12:20:04.761495 u2DelayCellOfst[2]=10 cells (3 PI)
7693 12:20:04.764701 u2DelayCellOfst[3]=10 cells (3 PI)
7694 12:20:04.767836 u2DelayCellOfst[4]=7 cells (2 PI)
7695 12:20:04.770957 u2DelayCellOfst[5]=0 cells (0 PI)
7696 12:20:04.774446 u2DelayCellOfst[6]=18 cells (5 PI)
7697 12:20:04.777733 u2DelayCellOfst[7]=18 cells (5 PI)
7698 12:20:04.780875 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7699 12:20:04.784892 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7700 12:20:04.787581 == TX Byte 1 ==
7701 12:20:04.790925 u2DelayCellOfst[8]=0 cells (0 PI)
7702 12:20:04.794192 u2DelayCellOfst[9]=0 cells (0 PI)
7703 12:20:04.797365 u2DelayCellOfst[10]=3 cells (1 PI)
7704 12:20:04.800866 u2DelayCellOfst[11]=0 cells (0 PI)
7705 12:20:04.803645 u2DelayCellOfst[12]=10 cells (3 PI)
7706 12:20:04.806953 u2DelayCellOfst[13]=10 cells (3 PI)
7707 12:20:04.807035 u2DelayCellOfst[14]=18 cells (5 PI)
7708 12:20:04.810423 u2DelayCellOfst[15]=10 cells (3 PI)
7709 12:20:04.817164 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7710 12:20:04.820076 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7711 12:20:04.823613 DramC Write-DBI on
7712 12:20:04.823686 ==
7713 12:20:04.827266 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 12:20:04.830197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 12:20:04.830281 ==
7716 12:20:04.830345
7717 12:20:04.830404
7718 12:20:04.833999 TX Vref Scan disable
7719 12:20:04.834082 == TX Byte 0 ==
7720 12:20:04.839883 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7721 12:20:04.839968 == TX Byte 1 ==
7722 12:20:04.843658 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7723 12:20:04.846570 DramC Write-DBI off
7724 12:20:04.846676
7725 12:20:04.846785 [DATLAT]
7726 12:20:04.850061 Freq=1600, CH0 RK0
7727 12:20:04.850160
7728 12:20:04.850250 DATLAT Default: 0xf
7729 12:20:04.853262 0, 0xFFFF, sum = 0
7730 12:20:04.856847 1, 0xFFFF, sum = 0
7731 12:20:04.856917 2, 0xFFFF, sum = 0
7732 12:20:04.860147 3, 0xFFFF, sum = 0
7733 12:20:04.860229 4, 0xFFFF, sum = 0
7734 12:20:04.863284 5, 0xFFFF, sum = 0
7735 12:20:04.863366 6, 0xFFFF, sum = 0
7736 12:20:04.866350 7, 0xFFFF, sum = 0
7737 12:20:04.866465 8, 0xFFFF, sum = 0
7738 12:20:04.869551 9, 0xFFFF, sum = 0
7739 12:20:04.869638 10, 0xFFFF, sum = 0
7740 12:20:04.872826 11, 0xFFFF, sum = 0
7741 12:20:04.872921 12, 0xFFFF, sum = 0
7742 12:20:04.876257 13, 0xFFFF, sum = 0
7743 12:20:04.876352 14, 0x0, sum = 1
7744 12:20:04.879302 15, 0x0, sum = 2
7745 12:20:04.879397 16, 0x0, sum = 3
7746 12:20:04.882526 17, 0x0, sum = 4
7747 12:20:04.882620 best_step = 15
7748 12:20:04.882693
7749 12:20:04.882760 ==
7750 12:20:04.886687 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 12:20:04.892756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 12:20:04.892880 ==
7753 12:20:04.892985 RX Vref Scan: 1
7754 12:20:04.893089
7755 12:20:04.895898 Set Vref Range= 24 -> 127
7756 12:20:04.895991
7757 12:20:04.899007 RX Vref 24 -> 127, step: 1
7758 12:20:04.899112
7759 12:20:04.902386 RX Delay 11 -> 252, step: 4
7760 12:20:04.902476
7761 12:20:04.905915 Set Vref, RX VrefLevel [Byte0]: 24
7762 12:20:04.909300 [Byte1]: 24
7763 12:20:04.909380
7764 12:20:04.912452 Set Vref, RX VrefLevel [Byte0]: 25
7765 12:20:04.915517 [Byte1]: 25
7766 12:20:04.915604
7767 12:20:04.918679 Set Vref, RX VrefLevel [Byte0]: 26
7768 12:20:04.922470 [Byte1]: 26
7769 12:20:04.925593
7770 12:20:04.925671 Set Vref, RX VrefLevel [Byte0]: 27
7771 12:20:04.928935 [Byte1]: 27
7772 12:20:04.933216
7773 12:20:04.933295 Set Vref, RX VrefLevel [Byte0]: 28
7774 12:20:04.936354 [Byte1]: 28
7775 12:20:04.940351
7776 12:20:04.940429 Set Vref, RX VrefLevel [Byte0]: 29
7777 12:20:04.943955 [Byte1]: 29
7778 12:20:04.948269
7779 12:20:04.948348 Set Vref, RX VrefLevel [Byte0]: 30
7780 12:20:04.951838 [Byte1]: 30
7781 12:20:04.956135
7782 12:20:04.956214 Set Vref, RX VrefLevel [Byte0]: 31
7783 12:20:04.959384 [Byte1]: 31
7784 12:20:04.963286
7785 12:20:04.963364 Set Vref, RX VrefLevel [Byte0]: 32
7786 12:20:04.966691 [Byte1]: 32
7787 12:20:04.971259
7788 12:20:04.971338 Set Vref, RX VrefLevel [Byte0]: 33
7789 12:20:04.974363 [Byte1]: 33
7790 12:20:04.978643
7791 12:20:04.978724 Set Vref, RX VrefLevel [Byte0]: 34
7792 12:20:04.981984 [Byte1]: 34
7793 12:20:04.987110
7794 12:20:04.987519 Set Vref, RX VrefLevel [Byte0]: 35
7795 12:20:04.990125 [Byte1]: 35
7796 12:20:04.994653
7797 12:20:04.995056 Set Vref, RX VrefLevel [Byte0]: 36
7798 12:20:04.997459 [Byte1]: 36
7799 12:20:05.002136
7800 12:20:05.002700 Set Vref, RX VrefLevel [Byte0]: 37
7801 12:20:05.005671 [Byte1]: 37
7802 12:20:05.009601
7803 12:20:05.010138 Set Vref, RX VrefLevel [Byte0]: 38
7804 12:20:05.013430 [Byte1]: 38
7805 12:20:05.017410
7806 12:20:05.017949 Set Vref, RX VrefLevel [Byte0]: 39
7807 12:20:05.020374 [Byte1]: 39
7808 12:20:05.024820
7809 12:20:05.025345 Set Vref, RX VrefLevel [Byte0]: 40
7810 12:20:05.028370 [Byte1]: 40
7811 12:20:05.032551
7812 12:20:05.032963 Set Vref, RX VrefLevel [Byte0]: 41
7813 12:20:05.035437 [Byte1]: 41
7814 12:20:05.039992
7815 12:20:05.040454 Set Vref, RX VrefLevel [Byte0]: 42
7816 12:20:05.043314 [Byte1]: 42
7817 12:20:05.047934
7818 12:20:05.048346 Set Vref, RX VrefLevel [Byte0]: 43
7819 12:20:05.051054 [Byte1]: 43
7820 12:20:05.055006
7821 12:20:05.055263 Set Vref, RX VrefLevel [Byte0]: 44
7822 12:20:05.058115 [Byte1]: 44
7823 12:20:05.062350
7824 12:20:05.062504 Set Vref, RX VrefLevel [Byte0]: 45
7825 12:20:05.065746 [Byte1]: 45
7826 12:20:05.069884
7827 12:20:05.070055 Set Vref, RX VrefLevel [Byte0]: 46
7828 12:20:05.073163 [Byte1]: 46
7829 12:20:05.077883
7830 12:20:05.078061 Set Vref, RX VrefLevel [Byte0]: 47
7831 12:20:05.081299 [Byte1]: 47
7832 12:20:05.085275
7833 12:20:05.085451 Set Vref, RX VrefLevel [Byte0]: 48
7834 12:20:05.088738 [Byte1]: 48
7835 12:20:05.093091
7836 12:20:05.093266 Set Vref, RX VrefLevel [Byte0]: 49
7837 12:20:05.096373 [Byte1]: 49
7838 12:20:05.100611
7839 12:20:05.100740 Set Vref, RX VrefLevel [Byte0]: 50
7840 12:20:05.104099 [Byte1]: 50
7841 12:20:05.108322
7842 12:20:05.108502 Set Vref, RX VrefLevel [Byte0]: 51
7843 12:20:05.111475 [Byte1]: 51
7844 12:20:05.115767
7845 12:20:05.115937 Set Vref, RX VrefLevel [Byte0]: 52
7846 12:20:05.119162 [Byte1]: 52
7847 12:20:05.123414
7848 12:20:05.123592 Set Vref, RX VrefLevel [Byte0]: 53
7849 12:20:05.126776 [Byte1]: 53
7850 12:20:05.130952
7851 12:20:05.131133 Set Vref, RX VrefLevel [Byte0]: 54
7852 12:20:05.134425 [Byte1]: 54
7853 12:20:05.138455
7854 12:20:05.138640 Set Vref, RX VrefLevel [Byte0]: 55
7855 12:20:05.142077 [Byte1]: 55
7856 12:20:05.146277
7857 12:20:05.146414 Set Vref, RX VrefLevel [Byte0]: 56
7858 12:20:05.149742 [Byte1]: 56
7859 12:20:05.153944
7860 12:20:05.154119 Set Vref, RX VrefLevel [Byte0]: 57
7861 12:20:05.156968 [Byte1]: 57
7862 12:20:05.161289
7863 12:20:05.161464 Set Vref, RX VrefLevel [Byte0]: 58
7864 12:20:05.164754 [Byte1]: 58
7865 12:20:05.168946
7866 12:20:05.169120 Set Vref, RX VrefLevel [Byte0]: 59
7867 12:20:05.172119 [Byte1]: 59
7868 12:20:05.176886
7869 12:20:05.179828 Set Vref, RX VrefLevel [Byte0]: 60
7870 12:20:05.183677 [Byte1]: 60
7871 12:20:05.183805
7872 12:20:05.186399 Set Vref, RX VrefLevel [Byte0]: 61
7873 12:20:05.189946 [Byte1]: 61
7874 12:20:05.190122
7875 12:20:05.192884 Set Vref, RX VrefLevel [Byte0]: 62
7876 12:20:05.196416 [Byte1]: 62
7877 12:20:05.200104
7878 12:20:05.200231 Set Vref, RX VrefLevel [Byte0]: 63
7879 12:20:05.203082 [Byte1]: 63
7880 12:20:05.208068
7881 12:20:05.208239 Set Vref, RX VrefLevel [Byte0]: 64
7882 12:20:05.210612 [Byte1]: 64
7883 12:20:05.214703
7884 12:20:05.214858 Set Vref, RX VrefLevel [Byte0]: 65
7885 12:20:05.218095 [Byte1]: 65
7886 12:20:05.222310
7887 12:20:05.222489 Set Vref, RX VrefLevel [Byte0]: 66
7888 12:20:05.226013 [Byte1]: 66
7889 12:20:05.229676
7890 12:20:05.229828 Set Vref, RX VrefLevel [Byte0]: 67
7891 12:20:05.233392 [Byte1]: 67
7892 12:20:05.237676
7893 12:20:05.237803 Set Vref, RX VrefLevel [Byte0]: 68
7894 12:20:05.240641 [Byte1]: 68
7895 12:20:05.245692
7896 12:20:05.245798 Set Vref, RX VrefLevel [Byte0]: 69
7897 12:20:05.249011 [Byte1]: 69
7898 12:20:05.252717
7899 12:20:05.252806 Set Vref, RX VrefLevel [Byte0]: 70
7900 12:20:05.256012 [Byte1]: 70
7901 12:20:05.260483
7902 12:20:05.260567 Set Vref, RX VrefLevel [Byte0]: 71
7903 12:20:05.263602 [Byte1]: 71
7904 12:20:05.267981
7905 12:20:05.268058 Set Vref, RX VrefLevel [Byte0]: 72
7906 12:20:05.271598 [Byte1]: 72
7907 12:20:05.275293
7908 12:20:05.275363 Set Vref, RX VrefLevel [Byte0]: 73
7909 12:20:05.278807 [Byte1]: 73
7910 12:20:05.283269
7911 12:20:05.283346 Set Vref, RX VrefLevel [Byte0]: 74
7912 12:20:05.286213 [Byte1]: 74
7913 12:20:05.291284
7914 12:20:05.291356 Final RX Vref Byte 0 = 55 to rank0
7915 12:20:05.294054 Final RX Vref Byte 1 = 60 to rank0
7916 12:20:05.297349 Final RX Vref Byte 0 = 55 to rank1
7917 12:20:05.300974 Final RX Vref Byte 1 = 60 to rank1==
7918 12:20:05.303811 Dram Type= 6, Freq= 0, CH_0, rank 0
7919 12:20:05.310807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7920 12:20:05.310881 ==
7921 12:20:05.310941 DQS Delay:
7922 12:20:05.313881 DQS0 = 0, DQS1 = 0
7923 12:20:05.313950 DQM Delay:
7924 12:20:05.317332 DQM0 = 128, DQM1 = 124
7925 12:20:05.317401 DQ Delay:
7926 12:20:05.320055 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7927 12:20:05.323568 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =132
7928 12:20:05.326811 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =120
7929 12:20:05.329951 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =130
7930 12:20:05.330022
7931 12:20:05.330082
7932 12:20:05.330138
7933 12:20:05.333623 [DramC_TX_OE_Calibration] TA2
7934 12:20:05.336518 Original DQ_B0 (3 6) =30, OEN = 27
7935 12:20:05.339702 Original DQ_B1 (3 6) =30, OEN = 27
7936 12:20:05.343196 24, 0x0, End_B0=24 End_B1=24
7937 12:20:05.346715 25, 0x0, End_B0=25 End_B1=25
7938 12:20:05.346796 26, 0x0, End_B0=26 End_B1=26
7939 12:20:05.349956 27, 0x0, End_B0=27 End_B1=27
7940 12:20:05.353127 28, 0x0, End_B0=28 End_B1=28
7941 12:20:05.356649 29, 0x0, End_B0=29 End_B1=29
7942 12:20:05.359577 30, 0x0, End_B0=30 End_B1=30
7943 12:20:05.359659 31, 0x4141, End_B0=30 End_B1=30
7944 12:20:05.363130 Byte0 end_step=30 best_step=27
7945 12:20:05.366612 Byte1 end_step=30 best_step=27
7946 12:20:05.369698 Byte0 TX OE(2T, 0.5T) = (3, 3)
7947 12:20:05.373081 Byte1 TX OE(2T, 0.5T) = (3, 3)
7948 12:20:05.373182
7949 12:20:05.373259
7950 12:20:05.379821 [DQSOSCAuto] RK0, (LSB)MR18= 0x1512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
7951 12:20:05.382878 CH0 RK0: MR19=303, MR18=1512
7952 12:20:05.389666 CH0_RK0: MR19=0x303, MR18=0x1512, DQSOSC=399, MR23=63, INC=23, DEC=15
7953 12:20:05.389848
7954 12:20:05.393257 ----->DramcWriteLeveling(PI) begin...
7955 12:20:05.393420 ==
7956 12:20:05.396292 Dram Type= 6, Freq= 0, CH_0, rank 1
7957 12:20:05.399440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 12:20:05.399556 ==
7959 12:20:05.402909 Write leveling (Byte 0): 35 => 35
7960 12:20:05.405782 Write leveling (Byte 1): 29 => 29
7961 12:20:05.409585 DramcWriteLeveling(PI) end<-----
7962 12:20:05.409726
7963 12:20:05.409851 ==
7964 12:20:05.412668 Dram Type= 6, Freq= 0, CH_0, rank 1
7965 12:20:05.419239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 12:20:05.419410 ==
7967 12:20:05.419544 [Gating] SW mode calibration
7968 12:20:05.429106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7969 12:20:05.432264 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7970 12:20:05.438913 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7971 12:20:05.443110 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7972 12:20:05.445461 1 4 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7973 12:20:05.452158 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7974 12:20:05.455775 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7975 12:20:05.458451 1 4 20 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7976 12:20:05.465032 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 12:20:05.468588 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 12:20:05.471696 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7979 12:20:05.478164 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7980 12:20:05.481518 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7981 12:20:05.485573 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 1)
7982 12:20:05.491600 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7983 12:20:05.494758 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
7984 12:20:05.499127 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7985 12:20:05.505551 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 12:20:05.508028 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7987 12:20:05.511715 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7988 12:20:05.517972 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7989 12:20:05.521244 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7990 12:20:05.525223 1 6 16 | B1->B0 | 2c2b 4646 | 1 0 | (1 1) (0 0)
7991 12:20:05.531255 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7992 12:20:05.534249 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 12:20:05.537450 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 12:20:05.544348 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 12:20:05.547632 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7996 12:20:05.550974 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7997 12:20:05.557829 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7998 12:20:05.560959 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7999 12:20:05.564043 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8000 12:20:05.570788 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 12:20:05.573889 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 12:20:05.577415 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 12:20:05.583868 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 12:20:05.587302 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 12:20:05.590433 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 12:20:05.597085 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 12:20:05.600398 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 12:20:05.603944 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 12:20:05.610369 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:20:05.613712 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:20:05.617028 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8012 12:20:05.623429 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8013 12:20:05.626371 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8014 12:20:05.629950 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8015 12:20:05.633144 Total UI for P1: 0, mck2ui 16
8016 12:20:05.636561 best dqsien dly found for B0: ( 1, 9, 8)
8017 12:20:05.643129 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8018 12:20:05.646520 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 12:20:05.649485 Total UI for P1: 0, mck2ui 16
8020 12:20:05.652928 best dqsien dly found for B1: ( 1, 9, 18)
8021 12:20:05.656244 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8022 12:20:05.659204 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8023 12:20:05.659853
8024 12:20:05.662468 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8025 12:20:05.669181 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8026 12:20:05.669818 [Gating] SW calibration Done
8027 12:20:05.670335 ==
8028 12:20:05.672683 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 12:20:05.679149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 12:20:05.679531 ==
8031 12:20:05.679840 RX Vref Scan: 0
8032 12:20:05.680153
8033 12:20:05.682255 RX Vref 0 -> 0, step: 1
8034 12:20:05.682663
8035 12:20:05.686076 RX Delay 0 -> 252, step: 8
8036 12:20:05.688833 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
8037 12:20:05.692396 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
8038 12:20:05.695522 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
8039 12:20:05.702240 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
8040 12:20:05.705814 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
8041 12:20:05.708407 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
8042 12:20:05.711827 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
8043 12:20:05.715494 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
8044 12:20:05.721988 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
8045 12:20:05.725069 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
8046 12:20:05.728746 iDelay=192, Bit 10, Center 127 (64 ~ 191) 128
8047 12:20:05.731653 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
8048 12:20:05.735179 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
8049 12:20:05.742405 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
8050 12:20:05.745052 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
8051 12:20:05.748382 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
8052 12:20:05.748788 ==
8053 12:20:05.751955 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 12:20:05.754700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 12:20:05.758168 ==
8056 12:20:05.758683 DQS Delay:
8057 12:20:05.759252 DQS0 = 0, DQS1 = 0
8058 12:20:05.761551 DQM Delay:
8059 12:20:05.761956 DQM0 = 131, DQM1 = 124
8060 12:20:05.765015 DQ Delay:
8061 12:20:05.768255 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8062 12:20:05.771059 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
8063 12:20:05.774936 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =115
8064 12:20:05.778127 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8065 12:20:05.778652
8066 12:20:05.778970
8067 12:20:05.779336 ==
8068 12:20:05.781104 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 12:20:05.784304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 12:20:05.788208 ==
8071 12:20:05.788730
8072 12:20:05.789054
8073 12:20:05.789350 TX Vref Scan disable
8074 12:20:05.790940 == TX Byte 0 ==
8075 12:20:05.795228 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8076 12:20:05.798661 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8077 12:20:05.801111 == TX Byte 1 ==
8078 12:20:05.804232 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8079 12:20:05.807465 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8080 12:20:05.811022 ==
8081 12:20:05.813989 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 12:20:05.817579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 12:20:05.817992 ==
8084 12:20:05.830553
8085 12:20:05.833941 TX Vref early break, caculate TX vref
8086 12:20:05.837105 TX Vref=16, minBit 3, minWin=23, winSum=381
8087 12:20:05.840117 TX Vref=18, minBit 9, minWin=23, winSum=389
8088 12:20:05.843687 TX Vref=20, minBit 0, minWin=24, winSum=394
8089 12:20:05.846526 TX Vref=22, minBit 1, minWin=25, winSum=405
8090 12:20:05.850683 TX Vref=24, minBit 1, minWin=25, winSum=412
8091 12:20:05.857404 TX Vref=26, minBit 2, minWin=25, winSum=417
8092 12:20:05.859890 TX Vref=28, minBit 0, minWin=25, winSum=418
8093 12:20:05.863333 TX Vref=30, minBit 1, minWin=25, winSum=416
8094 12:20:05.866854 TX Vref=32, minBit 1, minWin=24, winSum=409
8095 12:20:05.869943 TX Vref=34, minBit 0, minWin=24, winSum=396
8096 12:20:05.876458 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8097 12:20:05.877021
8098 12:20:05.879597 Final TX Range 0 Vref 28
8099 12:20:05.880058
8100 12:20:05.880413 ==
8101 12:20:05.882723 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 12:20:05.886551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 12:20:05.887070 ==
8104 12:20:05.887458
8105 12:20:05.887763
8106 12:20:05.889494 TX Vref Scan disable
8107 12:20:05.896084 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8108 12:20:05.896501 == TX Byte 0 ==
8109 12:20:05.899827 u2DelayCellOfst[0]=10 cells (3 PI)
8110 12:20:05.903096 u2DelayCellOfst[1]=14 cells (4 PI)
8111 12:20:05.906779 u2DelayCellOfst[2]=7 cells (2 PI)
8112 12:20:05.909221 u2DelayCellOfst[3]=10 cells (3 PI)
8113 12:20:05.916122 u2DelayCellOfst[4]=7 cells (2 PI)
8114 12:20:05.916532 u2DelayCellOfst[5]=0 cells (0 PI)
8115 12:20:05.919124 u2DelayCellOfst[6]=14 cells (4 PI)
8116 12:20:05.922173 u2DelayCellOfst[7]=14 cells (4 PI)
8117 12:20:05.925173 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8118 12:20:05.928789 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8119 12:20:05.932519 == TX Byte 1 ==
8120 12:20:05.935378 u2DelayCellOfst[8]=0 cells (0 PI)
8121 12:20:05.938841 u2DelayCellOfst[9]=0 cells (0 PI)
8122 12:20:05.941975 u2DelayCellOfst[10]=7 cells (2 PI)
8123 12:20:05.942452 u2DelayCellOfst[11]=3 cells (1 PI)
8124 12:20:05.945029 u2DelayCellOfst[12]=10 cells (3 PI)
8125 12:20:05.948391 u2DelayCellOfst[13]=10 cells (3 PI)
8126 12:20:05.951636 u2DelayCellOfst[14]=18 cells (5 PI)
8127 12:20:05.954930 u2DelayCellOfst[15]=14 cells (4 PI)
8128 12:20:05.961637 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8129 12:20:05.964386 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8130 12:20:05.964677 DramC Write-DBI on
8131 12:20:05.967970 ==
8132 12:20:05.971495 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 12:20:05.974533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 12:20:05.974772 ==
8135 12:20:05.974962
8136 12:20:05.975202
8137 12:20:05.977711 TX Vref Scan disable
8138 12:20:05.977897 == TX Byte 0 ==
8139 12:20:05.984454 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8140 12:20:05.984749 == TX Byte 1 ==
8141 12:20:05.987571 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8142 12:20:05.990894 DramC Write-DBI off
8143 12:20:05.991173
8144 12:20:05.991454 [DATLAT]
8145 12:20:05.994198 Freq=1600, CH0 RK1
8146 12:20:05.994474
8147 12:20:05.994648 DATLAT Default: 0xf
8148 12:20:05.997824 0, 0xFFFF, sum = 0
8149 12:20:05.998130 1, 0xFFFF, sum = 0
8150 12:20:06.000735 2, 0xFFFF, sum = 0
8151 12:20:06.001063 3, 0xFFFF, sum = 0
8152 12:20:06.004199 4, 0xFFFF, sum = 0
8153 12:20:06.007526 5, 0xFFFF, sum = 0
8154 12:20:06.007813 6, 0xFFFF, sum = 0
8155 12:20:06.010912 7, 0xFFFF, sum = 0
8156 12:20:06.011220 8, 0xFFFF, sum = 0
8157 12:20:06.013971 9, 0xFFFF, sum = 0
8158 12:20:06.014061 10, 0xFFFF, sum = 0
8159 12:20:06.017882 11, 0xFFFF, sum = 0
8160 12:20:06.017964 12, 0xFFFF, sum = 0
8161 12:20:06.020680 13, 0xFFFF, sum = 0
8162 12:20:06.020762 14, 0x0, sum = 1
8163 12:20:06.023774 15, 0x0, sum = 2
8164 12:20:06.023856 16, 0x0, sum = 3
8165 12:20:06.026804 17, 0x0, sum = 4
8166 12:20:06.026894 best_step = 15
8167 12:20:06.026956
8168 12:20:06.027014 ==
8169 12:20:06.030540 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 12:20:06.037284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 12:20:06.037391 ==
8172 12:20:06.037486 RX Vref Scan: 0
8173 12:20:06.037578
8174 12:20:06.040690 RX Vref 0 -> 0, step: 1
8175 12:20:06.041051
8176 12:20:06.044138 RX Delay 11 -> 252, step: 4
8177 12:20:06.046739 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8178 12:20:06.050313 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8179 12:20:06.053685 iDelay=191, Bit 2, Center 126 (75 ~ 178) 104
8180 12:20:06.060373 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8181 12:20:06.063511 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8182 12:20:06.066424 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8183 12:20:06.070568 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8184 12:20:06.073540 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8185 12:20:06.079809 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8186 12:20:06.083143 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8187 12:20:06.086407 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8188 12:20:06.089574 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8189 12:20:06.096530 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8190 12:20:06.100008 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8191 12:20:06.103249 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8192 12:20:06.106090 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8193 12:20:06.106521 ==
8194 12:20:06.109814 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 12:20:06.116836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 12:20:06.117363 ==
8197 12:20:06.117696 DQS Delay:
8198 12:20:06.119780 DQS0 = 0, DQS1 = 0
8199 12:20:06.120196 DQM Delay:
8200 12:20:06.120524 DQM0 = 129, DQM1 = 124
8201 12:20:06.123014 DQ Delay:
8202 12:20:06.126028 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8203 12:20:06.129359 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8204 12:20:06.132279 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8205 12:20:06.136083 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8206 12:20:06.136501
8207 12:20:06.136822
8208 12:20:06.137120
8209 12:20:06.138855 [DramC_TX_OE_Calibration] TA2
8210 12:20:06.142548 Original DQ_B0 (3 6) =30, OEN = 27
8211 12:20:06.146036 Original DQ_B1 (3 6) =30, OEN = 27
8212 12:20:06.149512 24, 0x0, End_B0=24 End_B1=24
8213 12:20:06.152834 25, 0x0, End_B0=25 End_B1=25
8214 12:20:06.153351 26, 0x0, End_B0=26 End_B1=26
8215 12:20:06.155753 27, 0x0, End_B0=27 End_B1=27
8216 12:20:06.159363 28, 0x0, End_B0=28 End_B1=28
8217 12:20:06.161980 29, 0x0, End_B0=29 End_B1=29
8218 12:20:06.162464 30, 0x0, End_B0=30 End_B1=30
8219 12:20:06.165284 31, 0x4545, End_B0=30 End_B1=30
8220 12:20:06.169012 Byte0 end_step=30 best_step=27
8221 12:20:06.171849 Byte1 end_step=30 best_step=27
8222 12:20:06.175381 Byte0 TX OE(2T, 0.5T) = (3, 3)
8223 12:20:06.178369 Byte1 TX OE(2T, 0.5T) = (3, 3)
8224 12:20:06.178809
8225 12:20:06.179338
8226 12:20:06.185038 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8227 12:20:06.187963 CH0 RK1: MR19=303, MR18=1210
8228 12:20:06.194843 CH0_RK1: MR19=0x303, MR18=0x1210, DQSOSC=400, MR23=63, INC=23, DEC=15
8229 12:20:06.198641 [RxdqsGatingPostProcess] freq 1600
8230 12:20:06.205000 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8231 12:20:06.207964 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 12:20:06.208491 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 12:20:06.211433 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 12:20:06.214344 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 12:20:06.217485 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 12:20:06.220713 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 12:20:06.223954 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 12:20:06.227327 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 12:20:06.230958 Pre-setting of DQS Precalculation
8240 12:20:06.234362 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8241 12:20:06.237769 ==
8242 12:20:06.240518 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 12:20:06.243667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 12:20:06.243746 ==
8245 12:20:06.247030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8246 12:20:06.254098 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8247 12:20:06.257171 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8248 12:20:06.263587 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8249 12:20:06.271715 [CA 0] Center 42 (12~72) winsize 61
8250 12:20:06.275037 [CA 1] Center 42 (12~72) winsize 61
8251 12:20:06.278686 [CA 2] Center 38 (9~67) winsize 59
8252 12:20:06.282350 [CA 3] Center 36 (7~66) winsize 60
8253 12:20:06.285177 [CA 4] Center 38 (8~68) winsize 61
8254 12:20:06.288248 [CA 5] Center 36 (7~66) winsize 60
8255 12:20:06.288323
8256 12:20:06.291527 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8257 12:20:06.291594
8258 12:20:06.297960 [CATrainingPosCal] consider 1 rank data
8259 12:20:06.298051 u2DelayCellTimex100 = 271/100 ps
8260 12:20:06.304921 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8261 12:20:06.308239 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8262 12:20:06.311912 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8263 12:20:06.315097 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8264 12:20:06.318397 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8265 12:20:06.321365 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8266 12:20:06.321477
8267 12:20:06.324508 CA PerBit enable=1, Macro0, CA PI delay=36
8268 12:20:06.324618
8269 12:20:06.327831 [CBTSetCACLKResult] CA Dly = 36
8270 12:20:06.331354 CS Dly: 8 (0~39)
8271 12:20:06.334421 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8272 12:20:06.338428 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8273 12:20:06.338538 ==
8274 12:20:06.340778 Dram Type= 6, Freq= 0, CH_1, rank 1
8275 12:20:06.347696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 12:20:06.347829 ==
8277 12:20:06.350935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 12:20:06.357929 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 12:20:06.360865 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 12:20:06.368076 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 12:20:06.375587 [CA 0] Center 42 (12~72) winsize 61
8282 12:20:06.379276 [CA 1] Center 42 (13~72) winsize 60
8283 12:20:06.381929 [CA 2] Center 38 (9~68) winsize 60
8284 12:20:06.385713 [CA 3] Center 37 (8~66) winsize 59
8285 12:20:06.389363 [CA 4] Center 38 (8~68) winsize 61
8286 12:20:06.392385 [CA 5] Center 37 (8~67) winsize 60
8287 12:20:06.392815
8288 12:20:06.395472 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8289 12:20:06.395891
8290 12:20:06.398551 [CATrainingPosCal] consider 2 rank data
8291 12:20:06.403161 u2DelayCellTimex100 = 271/100 ps
8292 12:20:06.408713 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8293 12:20:06.411945 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8294 12:20:06.414877 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8295 12:20:06.418094 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8296 12:20:06.421271 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8297 12:20:06.424780 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8298 12:20:06.425231
8299 12:20:06.428311 CA PerBit enable=1, Macro0, CA PI delay=37
8300 12:20:06.429004
8301 12:20:06.431388 [CBTSetCACLKResult] CA Dly = 37
8302 12:20:06.434786 CS Dly: 9 (0~42)
8303 12:20:06.438226 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 12:20:06.441537 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 12:20:06.441839
8306 12:20:06.444575 ----->DramcWriteLeveling(PI) begin...
8307 12:20:06.444885 ==
8308 12:20:06.448138 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 12:20:06.454362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 12:20:06.454717 ==
8311 12:20:06.458090 Write leveling (Byte 0): 25 => 25
8312 12:20:06.461088 Write leveling (Byte 1): 26 => 26
8313 12:20:06.461564 DramcWriteLeveling(PI) end<-----
8314 12:20:06.464766
8315 12:20:06.465255 ==
8316 12:20:06.467489 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 12:20:06.471743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 12:20:06.472228 ==
8319 12:20:06.473943 [Gating] SW mode calibration
8320 12:20:06.481375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8321 12:20:06.484677 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8322 12:20:06.490704 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 12:20:06.494780 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 12:20:06.497190 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 12:20:06.504166 1 4 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
8326 12:20:06.507999 1 4 16 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
8327 12:20:06.510588 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 12:20:06.517179 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 12:20:06.520431 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 12:20:06.527024 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 12:20:06.530425 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 12:20:06.533998 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 12:20:06.540088 1 5 12 | B1->B0 | 3333 3131 | 0 0 | (1 0) (0 0)
8334 12:20:06.543410 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8335 12:20:06.546919 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 12:20:06.553007 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 12:20:06.556985 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 12:20:06.560174 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 12:20:06.566942 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 12:20:06.569884 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8341 12:20:06.573204 1 6 12 | B1->B0 | 2b2b 4343 | 0 0 | (0 0) (0 0)
8342 12:20:06.580131 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 12:20:06.583037 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 12:20:06.586071 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 12:20:06.592993 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 12:20:06.596631 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 12:20:06.599539 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 12:20:06.605741 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 12:20:06.609284 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8350 12:20:06.612602 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8351 12:20:06.619302 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 12:20:06.622494 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 12:20:06.625535 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 12:20:06.633259 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 12:20:06.635598 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 12:20:06.638818 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 12:20:06.645578 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 12:20:06.648325 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 12:20:06.652690 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 12:20:06.658907 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 12:20:06.662178 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:20:06.665252 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:20:06.671463 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 12:20:06.675071 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 12:20:06.678391 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8366 12:20:06.684750 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8367 12:20:06.685176 Total UI for P1: 0, mck2ui 16
8368 12:20:06.691541 best dqsien dly found for B0: ( 1, 9, 12)
8369 12:20:06.694686 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 12:20:06.698172 Total UI for P1: 0, mck2ui 16
8371 12:20:06.701625 best dqsien dly found for B1: ( 1, 9, 14)
8372 12:20:06.704536 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8373 12:20:06.707650 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8374 12:20:06.708059
8375 12:20:06.711362 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8376 12:20:06.714509 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8377 12:20:06.718144 [Gating] SW calibration Done
8378 12:20:06.718622 ==
8379 12:20:06.720911 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 12:20:06.727174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 12:20:06.727806 ==
8382 12:20:06.728145 RX Vref Scan: 0
8383 12:20:06.728464
8384 12:20:06.730788 RX Vref 0 -> 0, step: 1
8385 12:20:06.731309
8386 12:20:06.734333 RX Delay 0 -> 252, step: 8
8387 12:20:06.737238 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8388 12:20:06.741084 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8389 12:20:06.744141 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8390 12:20:06.750275 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8391 12:20:06.754188 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8392 12:20:06.757074 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8393 12:20:06.760664 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8394 12:20:06.763373 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8395 12:20:06.770159 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8396 12:20:06.773495 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8397 12:20:06.776749 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8398 12:20:06.781491 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8399 12:20:06.783176 iDelay=200, Bit 12, Center 143 (96 ~ 191) 96
8400 12:20:06.789969 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8401 12:20:06.793275 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8402 12:20:06.796391 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8403 12:20:06.796802 ==
8404 12:20:06.799942 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 12:20:06.803251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 12:20:06.806340 ==
8407 12:20:06.806944 DQS Delay:
8408 12:20:06.807588 DQS0 = 0, DQS1 = 0
8409 12:20:06.809951 DQM Delay:
8410 12:20:06.810359 DQM0 = 134, DQM1 = 132
8411 12:20:06.813193 DQ Delay:
8412 12:20:06.815977 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8413 12:20:06.819030 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =127
8414 12:20:06.822580 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8415 12:20:06.826144 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8416 12:20:06.826558
8417 12:20:06.826876
8418 12:20:06.827225 ==
8419 12:20:06.829555 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 12:20:06.832631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 12:20:06.836140 ==
8422 12:20:06.836436
8423 12:20:06.836667
8424 12:20:06.836882 TX Vref Scan disable
8425 12:20:06.838894 == TX Byte 0 ==
8426 12:20:06.842560 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8427 12:20:06.845445 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8428 12:20:06.848801 == TX Byte 1 ==
8429 12:20:06.852316 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8430 12:20:06.855370 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8431 12:20:06.858685 ==
8432 12:20:06.862603 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 12:20:06.865788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 12:20:06.866296 ==
8435 12:20:06.878403
8436 12:20:06.881816 TX Vref early break, caculate TX vref
8437 12:20:06.885486 TX Vref=16, minBit 9, minWin=21, winSum=367
8438 12:20:06.888820 TX Vref=18, minBit 1, minWin=23, winSum=381
8439 12:20:06.891887 TX Vref=20, minBit 6, minWin=23, winSum=386
8440 12:20:06.894823 TX Vref=22, minBit 8, minWin=23, winSum=400
8441 12:20:06.897894 TX Vref=24, minBit 1, minWin=24, winSum=407
8442 12:20:06.904593 TX Vref=26, minBit 3, minWin=25, winSum=413
8443 12:20:06.908484 TX Vref=28, minBit 0, minWin=25, winSum=418
8444 12:20:06.911053 TX Vref=30, minBit 0, minWin=25, winSum=413
8445 12:20:06.914520 TX Vref=32, minBit 11, minWin=23, winSum=402
8446 12:20:06.917990 TX Vref=34, minBit 0, minWin=24, winSum=398
8447 12:20:06.924753 TX Vref=36, minBit 9, minWin=22, winSum=386
8448 12:20:06.927949 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8449 12:20:06.928516
8450 12:20:06.931209 Final TX Range 0 Vref 28
8451 12:20:06.931619
8452 12:20:06.931937 ==
8453 12:20:06.934143 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 12:20:06.937260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 12:20:06.940358 ==
8456 12:20:06.940646
8457 12:20:06.940873
8458 12:20:06.941125 TX Vref Scan disable
8459 12:20:06.947272 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8460 12:20:06.947492 == TX Byte 0 ==
8461 12:20:06.950388 u2DelayCellOfst[0]=18 cells (5 PI)
8462 12:20:06.953769 u2DelayCellOfst[1]=10 cells (3 PI)
8463 12:20:06.957531 u2DelayCellOfst[2]=0 cells (0 PI)
8464 12:20:06.960546 u2DelayCellOfst[3]=7 cells (2 PI)
8465 12:20:06.963660 u2DelayCellOfst[4]=10 cells (3 PI)
8466 12:20:06.966869 u2DelayCellOfst[5]=18 cells (5 PI)
8467 12:20:06.970525 u2DelayCellOfst[6]=14 cells (4 PI)
8468 12:20:06.973585 u2DelayCellOfst[7]=7 cells (2 PI)
8469 12:20:06.976913 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8470 12:20:06.980039 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8471 12:20:06.983523 == TX Byte 1 ==
8472 12:20:06.986491 u2DelayCellOfst[8]=0 cells (0 PI)
8473 12:20:06.989622 u2DelayCellOfst[9]=7 cells (2 PI)
8474 12:20:06.993125 u2DelayCellOfst[10]=10 cells (3 PI)
8475 12:20:06.996497 u2DelayCellOfst[11]=7 cells (2 PI)
8476 12:20:06.999552 u2DelayCellOfst[12]=14 cells (4 PI)
8477 12:20:07.002744 u2DelayCellOfst[13]=18 cells (5 PI)
8478 12:20:07.006380 u2DelayCellOfst[14]=18 cells (5 PI)
8479 12:20:07.009332 u2DelayCellOfst[15]=18 cells (5 PI)
8480 12:20:07.012757 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8481 12:20:07.015890 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8482 12:20:07.019191 DramC Write-DBI on
8483 12:20:07.019281 ==
8484 12:20:07.022748 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 12:20:07.026068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 12:20:07.026188 ==
8487 12:20:07.026286
8488 12:20:07.026358
8489 12:20:07.029245 TX Vref Scan disable
8490 12:20:07.032229 == TX Byte 0 ==
8491 12:20:07.035618 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8492 12:20:07.035722 == TX Byte 1 ==
8493 12:20:07.042681 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8494 12:20:07.042787 DramC Write-DBI off
8495 12:20:07.042866
8496 12:20:07.045559 [DATLAT]
8497 12:20:07.045672 Freq=1600, CH1 RK0
8498 12:20:07.045758
8499 12:20:07.049314 DATLAT Default: 0xf
8500 12:20:07.049448 0, 0xFFFF, sum = 0
8501 12:20:07.051877 1, 0xFFFF, sum = 0
8502 12:20:07.052013 2, 0xFFFF, sum = 0
8503 12:20:07.056472 3, 0xFFFF, sum = 0
8504 12:20:07.056626 4, 0xFFFF, sum = 0
8505 12:20:07.058516 5, 0xFFFF, sum = 0
8506 12:20:07.058625 6, 0xFFFF, sum = 0
8507 12:20:07.061963 7, 0xFFFF, sum = 0
8508 12:20:07.062073 8, 0xFFFF, sum = 0
8509 12:20:07.065411 9, 0xFFFF, sum = 0
8510 12:20:07.065521 10, 0xFFFF, sum = 0
8511 12:20:07.068687 11, 0xFFFF, sum = 0
8512 12:20:07.071766 12, 0xFFFF, sum = 0
8513 12:20:07.071875 13, 0xFFFF, sum = 0
8514 12:20:07.075817 14, 0x0, sum = 1
8515 12:20:07.075927 15, 0x0, sum = 2
8516 12:20:07.076012 16, 0x0, sum = 3
8517 12:20:07.078830 17, 0x0, sum = 4
8518 12:20:07.078940 best_step = 15
8519 12:20:07.079063
8520 12:20:07.081706 ==
8521 12:20:07.081813 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 12:20:07.088256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 12:20:07.088412 ==
8524 12:20:07.088569 RX Vref Scan: 1
8525 12:20:07.088694
8526 12:20:07.091727 Set Vref Range= 24 -> 127
8527 12:20:07.091829
8528 12:20:07.094952 RX Vref 24 -> 127, step: 1
8529 12:20:07.095094
8530 12:20:07.098379 RX Delay 19 -> 252, step: 4
8531 12:20:07.098485
8532 12:20:07.101344 Set Vref, RX VrefLevel [Byte0]: 24
8533 12:20:07.105213 [Byte1]: 24
8534 12:20:07.105321
8535 12:20:07.108778 Set Vref, RX VrefLevel [Byte0]: 25
8536 12:20:07.111393 [Byte1]: 25
8537 12:20:07.111501
8538 12:20:07.114804 Set Vref, RX VrefLevel [Byte0]: 26
8539 12:20:07.117710 [Byte1]: 26
8540 12:20:07.121319
8541 12:20:07.121460 Set Vref, RX VrefLevel [Byte0]: 27
8542 12:20:07.124602 [Byte1]: 27
8543 12:20:07.129011
8544 12:20:07.129153 Set Vref, RX VrefLevel [Byte0]: 28
8545 12:20:07.132501 [Byte1]: 28
8546 12:20:07.136586
8547 12:20:07.136759 Set Vref, RX VrefLevel [Byte0]: 29
8548 12:20:07.140103 [Byte1]: 29
8549 12:20:07.144175
8550 12:20:07.144381 Set Vref, RX VrefLevel [Byte0]: 30
8551 12:20:07.147792 [Byte1]: 30
8552 12:20:07.152319
8553 12:20:07.152514 Set Vref, RX VrefLevel [Byte0]: 31
8554 12:20:07.155054 [Byte1]: 31
8555 12:20:07.159989
8556 12:20:07.160276 Set Vref, RX VrefLevel [Byte0]: 32
8557 12:20:07.163061 [Byte1]: 32
8558 12:20:07.167264
8559 12:20:07.167640 Set Vref, RX VrefLevel [Byte0]: 33
8560 12:20:07.170457 [Byte1]: 33
8561 12:20:07.174974
8562 12:20:07.175443 Set Vref, RX VrefLevel [Byte0]: 34
8563 12:20:07.178204 [Byte1]: 34
8564 12:20:07.182580
8565 12:20:07.182985 Set Vref, RX VrefLevel [Byte0]: 35
8566 12:20:07.186089 [Byte1]: 35
8567 12:20:07.190037
8568 12:20:07.190688 Set Vref, RX VrefLevel [Byte0]: 36
8569 12:20:07.192998 [Byte1]: 36
8570 12:20:07.198247
8571 12:20:07.198682 Set Vref, RX VrefLevel [Byte0]: 37
8572 12:20:07.200537 [Byte1]: 37
8573 12:20:07.205410
8574 12:20:07.205816 Set Vref, RX VrefLevel [Byte0]: 38
8575 12:20:07.208791 [Byte1]: 38
8576 12:20:07.212706
8577 12:20:07.213111 Set Vref, RX VrefLevel [Byte0]: 39
8578 12:20:07.216154 [Byte1]: 39
8579 12:20:07.220206
8580 12:20:07.220612 Set Vref, RX VrefLevel [Byte0]: 40
8581 12:20:07.223312 [Byte1]: 40
8582 12:20:07.227784
8583 12:20:07.228331 Set Vref, RX VrefLevel [Byte0]: 41
8584 12:20:07.231457 [Byte1]: 41
8585 12:20:07.235614
8586 12:20:07.235984 Set Vref, RX VrefLevel [Byte0]: 42
8587 12:20:07.238240 [Byte1]: 42
8588 12:20:07.242633
8589 12:20:07.242942 Set Vref, RX VrefLevel [Byte0]: 43
8590 12:20:07.245765 [Byte1]: 43
8591 12:20:07.250694
8592 12:20:07.250800 Set Vref, RX VrefLevel [Byte0]: 44
8593 12:20:07.253624 [Byte1]: 44
8594 12:20:07.257636
8595 12:20:07.257735 Set Vref, RX VrefLevel [Byte0]: 45
8596 12:20:07.261287 [Byte1]: 45
8597 12:20:07.265509
8598 12:20:07.265693 Set Vref, RX VrefLevel [Byte0]: 46
8599 12:20:07.268625 [Byte1]: 46
8600 12:20:07.272877
8601 12:20:07.272981 Set Vref, RX VrefLevel [Byte0]: 47
8602 12:20:07.276315 [Byte1]: 47
8603 12:20:07.280338
8604 12:20:07.280450 Set Vref, RX VrefLevel [Byte0]: 48
8605 12:20:07.283685 [Byte1]: 48
8606 12:20:07.287722
8607 12:20:07.287827 Set Vref, RX VrefLevel [Byte0]: 49
8608 12:20:07.291375 [Byte1]: 49
8609 12:20:07.295558
8610 12:20:07.295663 Set Vref, RX VrefLevel [Byte0]: 50
8611 12:20:07.299316 [Byte1]: 50
8612 12:20:07.302956
8613 12:20:07.303069 Set Vref, RX VrefLevel [Byte0]: 51
8614 12:20:07.306391 [Byte1]: 51
8615 12:20:07.310830
8616 12:20:07.310950 Set Vref, RX VrefLevel [Byte0]: 52
8617 12:20:07.314094 [Byte1]: 52
8618 12:20:07.318134
8619 12:20:07.318227 Set Vref, RX VrefLevel [Byte0]: 53
8620 12:20:07.321620 [Byte1]: 53
8621 12:20:07.325959
8622 12:20:07.326118 Set Vref, RX VrefLevel [Byte0]: 54
8623 12:20:07.329326 [Byte1]: 54
8624 12:20:07.333376
8625 12:20:07.333542 Set Vref, RX VrefLevel [Byte0]: 55
8626 12:20:07.336782 [Byte1]: 55
8627 12:20:07.341252
8628 12:20:07.341463 Set Vref, RX VrefLevel [Byte0]: 56
8629 12:20:07.347609 [Byte1]: 56
8630 12:20:07.347852
8631 12:20:07.350879 Set Vref, RX VrefLevel [Byte0]: 57
8632 12:20:07.354854 [Byte1]: 57
8633 12:20:07.355120
8634 12:20:07.357743 Set Vref, RX VrefLevel [Byte0]: 58
8635 12:20:07.360619 [Byte1]: 58
8636 12:20:07.360839
8637 12:20:07.363892 Set Vref, RX VrefLevel [Byte0]: 59
8638 12:20:07.367602 [Byte1]: 59
8639 12:20:07.371393
8640 12:20:07.371625 Set Vref, RX VrefLevel [Byte0]: 60
8641 12:20:07.374712 [Byte1]: 60
8642 12:20:07.379380
8643 12:20:07.379626 Set Vref, RX VrefLevel [Byte0]: 61
8644 12:20:07.382254 [Byte1]: 61
8645 12:20:07.386474
8646 12:20:07.386707 Set Vref, RX VrefLevel [Byte0]: 62
8647 12:20:07.389909 [Byte1]: 62
8648 12:20:07.394261
8649 12:20:07.394437 Set Vref, RX VrefLevel [Byte0]: 63
8650 12:20:07.397459 [Byte1]: 63
8651 12:20:07.401815
8652 12:20:07.401991 Set Vref, RX VrefLevel [Byte0]: 64
8653 12:20:07.405342 [Byte1]: 64
8654 12:20:07.409287
8655 12:20:07.409463 Set Vref, RX VrefLevel [Byte0]: 65
8656 12:20:07.413343 [Byte1]: 65
8657 12:20:07.416804
8658 12:20:07.417012 Set Vref, RX VrefLevel [Byte0]: 66
8659 12:20:07.420501 [Byte1]: 66
8660 12:20:07.425038
8661 12:20:07.425444 Set Vref, RX VrefLevel [Byte0]: 67
8662 12:20:07.428054 [Byte1]: 67
8663 12:20:07.432791
8664 12:20:07.433196 Set Vref, RX VrefLevel [Byte0]: 68
8665 12:20:07.435827 [Byte1]: 68
8666 12:20:07.439938
8667 12:20:07.440368 Set Vref, RX VrefLevel [Byte0]: 69
8668 12:20:07.446267 [Byte1]: 69
8669 12:20:07.446683
8670 12:20:07.450213 Set Vref, RX VrefLevel [Byte0]: 70
8671 12:20:07.453527 [Byte1]: 70
8672 12:20:07.453938
8673 12:20:07.456203 Set Vref, RX VrefLevel [Byte0]: 71
8674 12:20:07.460334 [Byte1]: 71
8675 12:20:07.460850
8676 12:20:07.463306 Final RX Vref Byte 0 = 63 to rank0
8677 12:20:07.466126 Final RX Vref Byte 1 = 63 to rank0
8678 12:20:07.469755 Final RX Vref Byte 0 = 63 to rank1
8679 12:20:07.473151 Final RX Vref Byte 1 = 63 to rank1==
8680 12:20:07.476187 Dram Type= 6, Freq= 0, CH_1, rank 0
8681 12:20:07.482475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8682 12:20:07.482890 ==
8683 12:20:07.483267 DQS Delay:
8684 12:20:07.483576 DQS0 = 0, DQS1 = 0
8685 12:20:07.486034 DQM Delay:
8686 12:20:07.486443 DQM0 = 132, DQM1 = 130
8687 12:20:07.489902 DQ Delay:
8688 12:20:07.492866 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8689 12:20:07.496559 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =128
8690 12:20:07.499344 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =122
8691 12:20:07.502795 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8692 12:20:07.503278
8693 12:20:07.503615
8694 12:20:07.503917
8695 12:20:07.506115 [DramC_TX_OE_Calibration] TA2
8696 12:20:07.508876 Original DQ_B0 (3 6) =30, OEN = 27
8697 12:20:07.512556 Original DQ_B1 (3 6) =30, OEN = 27
8698 12:20:07.515601 24, 0x0, End_B0=24 End_B1=24
8699 12:20:07.516113 25, 0x0, End_B0=25 End_B1=25
8700 12:20:07.518696 26, 0x0, End_B0=26 End_B1=26
8701 12:20:07.522423 27, 0x0, End_B0=27 End_B1=27
8702 12:20:07.525614 28, 0x0, End_B0=28 End_B1=28
8703 12:20:07.528574 29, 0x0, End_B0=29 End_B1=29
8704 12:20:07.529014 30, 0x0, End_B0=30 End_B1=30
8705 12:20:07.531928 31, 0x4141, End_B0=30 End_B1=30
8706 12:20:07.535015 Byte0 end_step=30 best_step=27
8707 12:20:07.538615 Byte1 end_step=30 best_step=27
8708 12:20:07.541730 Byte0 TX OE(2T, 0.5T) = (3, 3)
8709 12:20:07.545598 Byte1 TX OE(2T, 0.5T) = (3, 3)
8710 12:20:07.546106
8711 12:20:07.546432
8712 12:20:07.551654 [DQSOSCAuto] RK0, (LSB)MR18= 0x811, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 405 ps
8713 12:20:07.555289 CH1 RK0: MR19=303, MR18=811
8714 12:20:07.561757 CH1_RK0: MR19=0x303, MR18=0x811, DQSOSC=401, MR23=63, INC=22, DEC=15
8715 12:20:07.562336
8716 12:20:07.565384 ----->DramcWriteLeveling(PI) begin...
8717 12:20:07.565806 ==
8718 12:20:07.568217 Dram Type= 6, Freq= 0, CH_1, rank 1
8719 12:20:07.571190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8720 12:20:07.571610 ==
8721 12:20:07.574998 Write leveling (Byte 0): 23 => 23
8722 12:20:07.578107 Write leveling (Byte 1): 27 => 27
8723 12:20:07.581534 DramcWriteLeveling(PI) end<-----
8724 12:20:07.581950
8725 12:20:07.582274 ==
8726 12:20:07.584167 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 12:20:07.587781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 12:20:07.591597 ==
8729 12:20:07.592016 [Gating] SW mode calibration
8730 12:20:07.601301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8731 12:20:07.604164 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8732 12:20:07.607292 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8733 12:20:07.613887 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8734 12:20:07.617929 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8735 12:20:07.620727 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8736 12:20:07.627118 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 12:20:07.630707 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 12:20:07.633737 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 12:20:07.640225 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 12:20:07.643460 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 12:20:07.646779 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8742 12:20:07.653178 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8743 12:20:07.656986 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8744 12:20:07.663367 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8745 12:20:07.666835 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 12:20:07.669899 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 12:20:07.676744 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 12:20:07.679888 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 12:20:07.683139 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8750 12:20:07.689676 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8751 12:20:07.692596 1 6 12 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8752 12:20:07.695934 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 12:20:07.703050 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 12:20:07.706493 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 12:20:07.709798 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 12:20:07.715991 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 12:20:07.719335 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 12:20:07.721974 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8759 12:20:07.728418 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8760 12:20:07.732183 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8761 12:20:07.735184 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 12:20:07.741991 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 12:20:07.745195 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 12:20:07.748878 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 12:20:07.755041 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 12:20:07.758495 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 12:20:07.761744 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 12:20:07.768277 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 12:20:07.771480 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 12:20:07.775044 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 12:20:07.781332 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 12:20:07.785293 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 12:20:07.788096 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 12:20:07.795059 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8775 12:20:07.797829 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8776 12:20:07.801106 Total UI for P1: 0, mck2ui 16
8777 12:20:07.804446 best dqsien dly found for B0: ( 1, 9, 8)
8778 12:20:07.808124 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 12:20:07.810933 Total UI for P1: 0, mck2ui 16
8780 12:20:07.814574 best dqsien dly found for B1: ( 1, 9, 12)
8781 12:20:07.817714 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8782 12:20:07.820767 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8783 12:20:07.821183
8784 12:20:07.827636 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8785 12:20:07.830783 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8786 12:20:07.834180 [Gating] SW calibration Done
8787 12:20:07.834664 ==
8788 12:20:07.837167 Dram Type= 6, Freq= 0, CH_1, rank 1
8789 12:20:07.840418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8790 12:20:07.841151 ==
8791 12:20:07.841728 RX Vref Scan: 0
8792 12:20:07.842239
8793 12:20:07.843911 RX Vref 0 -> 0, step: 1
8794 12:20:07.844322
8795 12:20:07.846969 RX Delay 0 -> 252, step: 8
8796 12:20:07.850532 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8797 12:20:07.853745 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8798 12:20:07.860373 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8799 12:20:07.863508 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8800 12:20:07.867211 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8801 12:20:07.870284 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8802 12:20:07.873916 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8803 12:20:07.880179 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8804 12:20:07.883584 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8805 12:20:07.886919 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8806 12:20:07.890894 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8807 12:20:07.893290 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8808 12:20:07.899532 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8809 12:20:07.903010 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8810 12:20:07.906352 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8811 12:20:07.909488 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8812 12:20:07.913113 ==
8813 12:20:07.916071 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 12:20:07.919712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 12:20:07.920129 ==
8816 12:20:07.920451 DQS Delay:
8817 12:20:07.922498 DQS0 = 0, DQS1 = 0
8818 12:20:07.922920 DQM Delay:
8819 12:20:07.925913 DQM0 = 135, DQM1 = 131
8820 12:20:07.926323 DQ Delay:
8821 12:20:07.928995 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8822 12:20:07.932483 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8823 12:20:07.935978 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8824 12:20:07.939151 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8825 12:20:07.939564
8826 12:20:07.939885
8827 12:20:07.943013 ==
8828 12:20:07.943455 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 12:20:07.949025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 12:20:07.949439 ==
8831 12:20:07.949758
8832 12:20:07.950055
8833 12:20:07.952360 TX Vref Scan disable
8834 12:20:07.952773 == TX Byte 0 ==
8835 12:20:07.955925 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8836 12:20:07.962033 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8837 12:20:07.962443 == TX Byte 1 ==
8838 12:20:07.965458 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8839 12:20:07.971877 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8840 12:20:07.972288 ==
8841 12:20:07.974959 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 12:20:07.978186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 12:20:07.978620 ==
8844 12:20:07.992854
8845 12:20:07.996974 TX Vref early break, caculate TX vref
8846 12:20:07.999865 TX Vref=16, minBit 9, minWin=20, winSum=373
8847 12:20:08.002832 TX Vref=18, minBit 9, minWin=22, winSum=387
8848 12:20:08.006516 TX Vref=20, minBit 9, minWin=22, winSum=393
8849 12:20:08.009355 TX Vref=22, minBit 9, minWin=23, winSum=398
8850 12:20:08.012881 TX Vref=24, minBit 9, minWin=24, winSum=410
8851 12:20:08.019315 TX Vref=26, minBit 9, minWin=24, winSum=414
8852 12:20:08.022434 TX Vref=28, minBit 5, minWin=25, winSum=418
8853 12:20:08.025871 TX Vref=30, minBit 9, minWin=24, winSum=419
8854 12:20:08.029426 TX Vref=32, minBit 8, minWin=24, winSum=410
8855 12:20:08.032976 TX Vref=34, minBit 9, minWin=23, winSum=401
8856 12:20:08.038883 TX Vref=36, minBit 0, minWin=23, winSum=395
8857 12:20:08.042705 [TxChooseVref] Worse bit 5, Min win 25, Win sum 418, Final Vref 28
8858 12:20:08.043243
8859 12:20:08.045874 Final TX Range 0 Vref 28
8860 12:20:08.046287
8861 12:20:08.046607 ==
8862 12:20:08.050148 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 12:20:08.052554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 12:20:08.055466 ==
8865 12:20:08.055880
8866 12:20:08.056259
8867 12:20:08.056566 TX Vref Scan disable
8868 12:20:08.062624 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8869 12:20:08.063127 == TX Byte 0 ==
8870 12:20:08.065823 u2DelayCellOfst[0]=14 cells (4 PI)
8871 12:20:08.068696 u2DelayCellOfst[1]=10 cells (3 PI)
8872 12:20:08.072310 u2DelayCellOfst[2]=0 cells (0 PI)
8873 12:20:08.075352 u2DelayCellOfst[3]=7 cells (2 PI)
8874 12:20:08.078649 u2DelayCellOfst[4]=7 cells (2 PI)
8875 12:20:08.082188 u2DelayCellOfst[5]=18 cells (5 PI)
8876 12:20:08.085306 u2DelayCellOfst[6]=18 cells (5 PI)
8877 12:20:08.088567 u2DelayCellOfst[7]=7 cells (2 PI)
8878 12:20:08.092009 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8879 12:20:08.095400 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8880 12:20:08.098675 == TX Byte 1 ==
8881 12:20:08.101640 u2DelayCellOfst[8]=0 cells (0 PI)
8882 12:20:08.104991 u2DelayCellOfst[9]=3 cells (1 PI)
8883 12:20:08.108558 u2DelayCellOfst[10]=10 cells (3 PI)
8884 12:20:08.111930 u2DelayCellOfst[11]=7 cells (2 PI)
8885 12:20:08.114704 u2DelayCellOfst[12]=14 cells (4 PI)
8886 12:20:08.118297 u2DelayCellOfst[13]=14 cells (4 PI)
8887 12:20:08.121259 u2DelayCellOfst[14]=18 cells (5 PI)
8888 12:20:08.124727 u2DelayCellOfst[15]=18 cells (5 PI)
8889 12:20:08.127999 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8890 12:20:08.131442 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8891 12:20:08.134810 DramC Write-DBI on
8892 12:20:08.135264 ==
8893 12:20:08.137911 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 12:20:08.141427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 12:20:08.141894 ==
8896 12:20:08.142222
8897 12:20:08.142521
8898 12:20:08.144527 TX Vref Scan disable
8899 12:20:08.148177 == TX Byte 0 ==
8900 12:20:08.151400 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8901 12:20:08.151922 == TX Byte 1 ==
8902 12:20:08.157942 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8903 12:20:08.158517 DramC Write-DBI off
8904 12:20:08.158887
8905 12:20:08.159242 [DATLAT]
8906 12:20:08.161641 Freq=1600, CH1 RK1
8907 12:20:08.162051
8908 12:20:08.164213 DATLAT Default: 0xf
8909 12:20:08.164626 0, 0xFFFF, sum = 0
8910 12:20:08.167628 1, 0xFFFF, sum = 0
8911 12:20:08.168044 2, 0xFFFF, sum = 0
8912 12:20:08.170647 3, 0xFFFF, sum = 0
8913 12:20:08.171215 4, 0xFFFF, sum = 0
8914 12:20:08.174305 5, 0xFFFF, sum = 0
8915 12:20:08.174816 6, 0xFFFF, sum = 0
8916 12:20:08.177243 7, 0xFFFF, sum = 0
8917 12:20:08.177782 8, 0xFFFF, sum = 0
8918 12:20:08.181155 9, 0xFFFF, sum = 0
8919 12:20:08.181574 10, 0xFFFF, sum = 0
8920 12:20:08.184040 11, 0xFFFF, sum = 0
8921 12:20:08.184471 12, 0xFFFF, sum = 0
8922 12:20:08.187103 13, 0xFFFF, sum = 0
8923 12:20:08.187616 14, 0x0, sum = 1
8924 12:20:08.190609 15, 0x0, sum = 2
8925 12:20:08.191030 16, 0x0, sum = 3
8926 12:20:08.193448 17, 0x0, sum = 4
8927 12:20:08.193930 best_step = 15
8928 12:20:08.194278
8929 12:20:08.194585 ==
8930 12:20:08.197406 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 12:20:08.203852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 12:20:08.204378 ==
8933 12:20:08.204763 RX Vref Scan: 0
8934 12:20:08.205073
8935 12:20:08.206698 RX Vref 0 -> 0, step: 1
8936 12:20:08.207171
8937 12:20:08.210652 RX Delay 19 -> 252, step: 4
8938 12:20:08.213629 iDelay=195, Bit 0, Center 140 (91 ~ 190) 100
8939 12:20:08.217001 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8940 12:20:08.223646 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8941 12:20:08.226630 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8942 12:20:08.229735 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8943 12:20:08.233126 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8944 12:20:08.236446 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8945 12:20:08.243117 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8946 12:20:08.246304 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8947 12:20:08.249547 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8948 12:20:08.252863 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8949 12:20:08.259323 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8950 12:20:08.262835 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8951 12:20:08.266563 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8952 12:20:08.269322 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8953 12:20:08.272905 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8954 12:20:08.275655 ==
8955 12:20:08.279768 Dram Type= 6, Freq= 0, CH_1, rank 1
8956 12:20:08.282703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8957 12:20:08.283250 ==
8958 12:20:08.283588 DQS Delay:
8959 12:20:08.285601 DQS0 = 0, DQS1 = 0
8960 12:20:08.286013 DQM Delay:
8961 12:20:08.289249 DQM0 = 133, DQM1 = 127
8962 12:20:08.289662 DQ Delay:
8963 12:20:08.291977 DQ0 =140, DQ1 =132, DQ2 =120, DQ3 =130
8964 12:20:08.295386 DQ4 =130, DQ5 =144, DQ6 =140, DQ7 =130
8965 12:20:08.298890 DQ8 =112, DQ9 =118, DQ10 =128, DQ11 =120
8966 12:20:08.302628 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8967 12:20:08.303195
8968 12:20:08.303537
8969 12:20:08.303838
8970 12:20:08.306014 [DramC_TX_OE_Calibration] TA2
8971 12:20:08.308552 Original DQ_B0 (3 6) =30, OEN = 27
8972 12:20:08.312111 Original DQ_B1 (3 6) =30, OEN = 27
8973 12:20:08.316025 24, 0x0, End_B0=24 End_B1=24
8974 12:20:08.318623 25, 0x0, End_B0=25 End_B1=25
8975 12:20:08.322163 26, 0x0, End_B0=26 End_B1=26
8976 12:20:08.322578 27, 0x0, End_B0=27 End_B1=27
8977 12:20:08.325060 28, 0x0, End_B0=28 End_B1=28
8978 12:20:08.328850 29, 0x0, End_B0=29 End_B1=29
8979 12:20:08.332200 30, 0x0, End_B0=30 End_B1=30
8980 12:20:08.335216 31, 0x4545, End_B0=30 End_B1=30
8981 12:20:08.335640 Byte0 end_step=30 best_step=27
8982 12:20:08.338675 Byte1 end_step=30 best_step=27
8983 12:20:08.341811 Byte0 TX OE(2T, 0.5T) = (3, 3)
8984 12:20:08.345207 Byte1 TX OE(2T, 0.5T) = (3, 3)
8985 12:20:08.345714
8986 12:20:08.346040
8987 12:20:08.351795 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
8988 12:20:08.354876 CH1 RK1: MR19=303, MR18=D1B
8989 12:20:08.361605 CH1_RK1: MR19=0x303, MR18=0xD1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8990 12:20:08.364934 [RxdqsGatingPostProcess] freq 1600
8991 12:20:08.371337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8992 12:20:08.375030 best DQS0 dly(2T, 0.5T) = (1, 1)
8993 12:20:08.375584 best DQS1 dly(2T, 0.5T) = (1, 1)
8994 12:20:08.378282 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8995 12:20:08.381291 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8996 12:20:08.384579 best DQS0 dly(2T, 0.5T) = (1, 1)
8997 12:20:08.388610 best DQS1 dly(2T, 0.5T) = (1, 1)
8998 12:20:08.391128 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8999 12:20:08.394197 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9000 12:20:08.398030 Pre-setting of DQS Precalculation
9001 12:20:08.404271 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9002 12:20:08.410814 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9003 12:20:08.417426 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9004 12:20:08.417932
9005 12:20:08.418257
9006 12:20:08.420597 [Calibration Summary] 3200 Mbps
9007 12:20:08.421106 CH 0, Rank 0
9008 12:20:08.423665 SW Impedance : PASS
9009 12:20:08.427572 DUTY Scan : NO K
9010 12:20:08.428013 ZQ Calibration : PASS
9011 12:20:08.430346 Jitter Meter : NO K
9012 12:20:08.433742 CBT Training : PASS
9013 12:20:08.434154 Write leveling : PASS
9014 12:20:08.437620 RX DQS gating : PASS
9015 12:20:08.440065 RX DQ/DQS(RDDQC) : PASS
9016 12:20:08.440476 TX DQ/DQS : PASS
9017 12:20:08.443311 RX DATLAT : PASS
9018 12:20:08.447305 RX DQ/DQS(Engine): PASS
9019 12:20:08.447814 TX OE : PASS
9020 12:20:08.450593 All Pass.
9021 12:20:08.451002
9022 12:20:08.451357 CH 0, Rank 1
9023 12:20:08.453541 SW Impedance : PASS
9024 12:20:08.453952 DUTY Scan : NO K
9025 12:20:08.456850 ZQ Calibration : PASS
9026 12:20:08.460376 Jitter Meter : NO K
9027 12:20:08.460883 CBT Training : PASS
9028 12:20:08.463258 Write leveling : PASS
9029 12:20:08.466720 RX DQS gating : PASS
9030 12:20:08.467268 RX DQ/DQS(RDDQC) : PASS
9031 12:20:08.470721 TX DQ/DQS : PASS
9032 12:20:08.473473 RX DATLAT : PASS
9033 12:20:08.473978 RX DQ/DQS(Engine): PASS
9034 12:20:08.476607 TX OE : PASS
9035 12:20:08.477115 All Pass.
9036 12:20:08.477442
9037 12:20:08.479533 CH 1, Rank 0
9038 12:20:08.479946 SW Impedance : PASS
9039 12:20:08.482892 DUTY Scan : NO K
9040 12:20:08.486641 ZQ Calibration : PASS
9041 12:20:08.487195 Jitter Meter : NO K
9042 12:20:08.489434 CBT Training : PASS
9043 12:20:08.489937 Write leveling : PASS
9044 12:20:08.492614 RX DQS gating : PASS
9045 12:20:08.496259 RX DQ/DQS(RDDQC) : PASS
9046 12:20:08.496674 TX DQ/DQS : PASS
9047 12:20:08.499192 RX DATLAT : PASS
9048 12:20:08.502798 RX DQ/DQS(Engine): PASS
9049 12:20:08.503374 TX OE : PASS
9050 12:20:08.506070 All Pass.
9051 12:20:08.506475
9052 12:20:08.506799 CH 1, Rank 1
9053 12:20:08.509386 SW Impedance : PASS
9054 12:20:08.509894 DUTY Scan : NO K
9055 12:20:08.512304 ZQ Calibration : PASS
9056 12:20:08.515565 Jitter Meter : NO K
9057 12:20:08.515977 CBT Training : PASS
9058 12:20:08.519166 Write leveling : PASS
9059 12:20:08.522036 RX DQS gating : PASS
9060 12:20:08.522450 RX DQ/DQS(RDDQC) : PASS
9061 12:20:08.525337 TX DQ/DQS : PASS
9062 12:20:08.529029 RX DATLAT : PASS
9063 12:20:08.529441 RX DQ/DQS(Engine): PASS
9064 12:20:08.532182 TX OE : PASS
9065 12:20:08.532594 All Pass.
9066 12:20:08.532916
9067 12:20:08.535289 DramC Write-DBI on
9068 12:20:08.539454 PER_BANK_REFRESH: Hybrid Mode
9069 12:20:08.539870 TX_TRACKING: ON
9070 12:20:08.548870 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9071 12:20:08.554883 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9072 12:20:08.562097 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9073 12:20:08.568397 [FAST_K] Save calibration result to emmc
9074 12:20:08.568811 sync common calibartion params.
9075 12:20:08.571475 sync cbt_mode0:1, 1:1
9076 12:20:08.574787 dram_init: ddr_geometry: 2
9077 12:20:08.578731 dram_init: ddr_geometry: 2
9078 12:20:08.579172 dram_init: ddr_geometry: 2
9079 12:20:08.581327 0:dram_rank_size:100000000
9080 12:20:08.584958 1:dram_rank_size:100000000
9081 12:20:08.587755 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9082 12:20:08.591449 DFS_SHUFFLE_HW_MODE: ON
9083 12:20:08.595211 dramc_set_vcore_voltage set vcore to 725000
9084 12:20:08.598201 Read voltage for 1600, 0
9085 12:20:08.598622 Vio18 = 0
9086 12:20:08.601440 Vcore = 725000
9087 12:20:08.601953 Vdram = 0
9088 12:20:08.602280 Vddq = 0
9089 12:20:08.602579 Vmddr = 0
9090 12:20:08.604600 switch to 3200 Mbps bootup
9091 12:20:08.607814 [DramcRunTimeConfig]
9092 12:20:08.608223 PHYPLL
9093 12:20:08.611476 DPM_CONTROL_AFTERK: ON
9094 12:20:08.612056 PER_BANK_REFRESH: ON
9095 12:20:08.614686 REFRESH_OVERHEAD_REDUCTION: ON
9096 12:20:08.617680 CMD_PICG_NEW_MODE: OFF
9097 12:20:08.618192 XRTWTW_NEW_MODE: ON
9098 12:20:08.620924 XRTRTR_NEW_MODE: ON
9099 12:20:08.621351 TX_TRACKING: ON
9100 12:20:08.624237 RDSEL_TRACKING: OFF
9101 12:20:08.627361 DQS Precalculation for DVFS: ON
9102 12:20:08.627774 RX_TRACKING: OFF
9103 12:20:08.630910 HW_GATING DBG: ON
9104 12:20:08.631413 ZQCS_ENABLE_LP4: ON
9105 12:20:08.633972 RX_PICG_NEW_MODE: ON
9106 12:20:08.634384 TX_PICG_NEW_MODE: ON
9107 12:20:08.637955 ENABLE_RX_DCM_DPHY: ON
9108 12:20:08.640980 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9109 12:20:08.643591 DUMMY_READ_FOR_TRACKING: OFF
9110 12:20:08.644078 !!! SPM_CONTROL_AFTERK: OFF
9111 12:20:08.647184 !!! SPM could not control APHY
9112 12:20:08.650413 IMPEDANCE_TRACKING: ON
9113 12:20:08.650915 TEMP_SENSOR: ON
9114 12:20:08.654128 HW_SAVE_FOR_SR: OFF
9115 12:20:08.658189 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9116 12:20:08.660197 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9117 12:20:08.663592 Read ODT Tracking: ON
9118 12:20:08.664008 Refresh Rate DeBounce: ON
9119 12:20:08.667181 DFS_NO_QUEUE_FLUSH: ON
9120 12:20:08.670741 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9121 12:20:08.673467 ENABLE_DFS_RUNTIME_MRW: OFF
9122 12:20:08.673966 DDR_RESERVE_NEW_MODE: ON
9123 12:20:08.677197 MR_CBT_SWITCH_FREQ: ON
9124 12:20:08.680438 =========================
9125 12:20:08.697674 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9126 12:20:08.701050 dram_init: ddr_geometry: 2
9127 12:20:08.718837 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9128 12:20:08.722192 dram_init: dram init end (result: 0)
9129 12:20:08.729140 DRAM-K: Full calibration passed in 24460 msecs
9130 12:20:08.732138 MRC: failed to locate region type 0.
9131 12:20:08.732552 DRAM rank0 size:0x100000000,
9132 12:20:08.735795 DRAM rank1 size=0x100000000
9133 12:20:08.745202 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9134 12:20:08.752211 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9135 12:20:08.761829 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9136 12:20:08.768505 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9137 12:20:08.769020 DRAM rank0 size:0x100000000,
9138 12:20:08.771924 DRAM rank1 size=0x100000000
9139 12:20:08.772439 CBMEM:
9140 12:20:08.775000 IMD: root @ 0xfffff000 254 entries.
9141 12:20:08.778771 IMD: root @ 0xffffec00 62 entries.
9142 12:20:08.784730 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9143 12:20:08.788291 WARNING: RO_VPD is uninitialized or empty.
9144 12:20:08.791744 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9145 12:20:08.799503 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9146 12:20:08.811879 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9147 12:20:08.823544 BS: romstage times (exec / console): total (unknown) / 23985 ms
9148 12:20:08.824137
9149 12:20:08.824506
9150 12:20:08.833681 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9151 12:20:08.836623 ARM64: Exception handlers installed.
9152 12:20:08.839717 ARM64: Testing exception
9153 12:20:08.843416 ARM64: Done test exception
9154 12:20:08.843910 Enumerating buses...
9155 12:20:08.846277 Show all devs... Before device enumeration.
9156 12:20:08.850217 Root Device: enabled 1
9157 12:20:08.853116 CPU_CLUSTER: 0: enabled 1
9158 12:20:08.853536 CPU: 00: enabled 1
9159 12:20:08.856009 Compare with tree...
9160 12:20:08.856420 Root Device: enabled 1
9161 12:20:08.859166 CPU_CLUSTER: 0: enabled 1
9162 12:20:08.863046 CPU: 00: enabled 1
9163 12:20:08.863605 Root Device scanning...
9164 12:20:08.865963 scan_static_bus for Root Device
9165 12:20:08.868965 CPU_CLUSTER: 0 enabled
9166 12:20:08.872495 scan_static_bus for Root Device done
9167 12:20:08.875768 scan_bus: bus Root Device finished in 8 msecs
9168 12:20:08.876284 done
9169 12:20:08.882097 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9170 12:20:08.885536 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9171 12:20:08.892383 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9172 12:20:08.898635 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9173 12:20:08.899057 Allocating resources...
9174 12:20:08.902170 Reading resources...
9175 12:20:08.905263 Root Device read_resources bus 0 link: 0
9176 12:20:08.908565 DRAM rank0 size:0x100000000,
9177 12:20:08.908982 DRAM rank1 size=0x100000000
9178 12:20:08.915371 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9179 12:20:08.919001 CPU: 00 missing read_resources
9180 12:20:08.922123 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9181 12:20:08.924955 Root Device read_resources bus 0 link: 0 done
9182 12:20:08.928408 Done reading resources.
9183 12:20:08.931597 Show resources in subtree (Root Device)...After reading.
9184 12:20:08.934983 Root Device child on link 0 CPU_CLUSTER: 0
9185 12:20:08.938375 CPU_CLUSTER: 0 child on link 0 CPU: 00
9186 12:20:08.948016 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9187 12:20:08.948431 CPU: 00
9188 12:20:08.954745 Root Device assign_resources, bus 0 link: 0
9189 12:20:08.958218 CPU_CLUSTER: 0 missing set_resources
9190 12:20:08.961307 Root Device assign_resources, bus 0 link: 0 done
9191 12:20:08.964954 Done setting resources.
9192 12:20:08.967760 Show resources in subtree (Root Device)...After assigning values.
9193 12:20:08.974325 Root Device child on link 0 CPU_CLUSTER: 0
9194 12:20:08.977743 CPU_CLUSTER: 0 child on link 0 CPU: 00
9195 12:20:08.984430 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9196 12:20:08.987811 CPU: 00
9197 12:20:08.988334 Done allocating resources.
9198 12:20:08.994084 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9199 12:20:08.997309 Enabling resources...
9200 12:20:08.997774 done.
9201 12:20:09.001198 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9202 12:20:09.004085 Initializing devices...
9203 12:20:09.004497 Root Device init
9204 12:20:09.007217 init hardware done!
9205 12:20:09.010365 0x00000018: ctrlr->caps
9206 12:20:09.010785 52.000 MHz: ctrlr->f_max
9207 12:20:09.014189 0.400 MHz: ctrlr->f_min
9208 12:20:09.017209 0x40ff8080: ctrlr->voltages
9209 12:20:09.017631 sclk: 390625
9210 12:20:09.017958 Bus Width = 1
9211 12:20:09.020615 sclk: 390625
9212 12:20:09.021025 Bus Width = 1
9213 12:20:09.023658 Early init status = 3
9214 12:20:09.027036 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9215 12:20:09.031676 in-header: 03 fc 00 00 01 00 00 00
9216 12:20:09.034469 in-data: 00
9217 12:20:09.037861 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9218 12:20:09.042921 in-header: 03 fd 00 00 00 00 00 00
9219 12:20:09.045986 in-data:
9220 12:20:09.049802 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9221 12:20:09.054654 in-header: 03 fc 00 00 01 00 00 00
9222 12:20:09.057087 in-data: 00
9223 12:20:09.060191 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9224 12:20:09.067064 in-header: 03 fd 00 00 00 00 00 00
9225 12:20:09.070134 in-data:
9226 12:20:09.073300 [SSUSB] Setting up USB HOST controller...
9227 12:20:09.076366 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9228 12:20:09.079983 [SSUSB] phy power-on done.
9229 12:20:09.083133 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9230 12:20:09.089470 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9231 12:20:09.092869 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9232 12:20:09.100038 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9233 12:20:09.105774 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9234 12:20:09.113868 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9235 12:20:09.118963 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9236 12:20:09.126243 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9237 12:20:09.129316 SPM: binary array size = 0x9dc
9238 12:20:09.132513 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9239 12:20:09.138693 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9240 12:20:09.145157 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9241 12:20:09.152023 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9242 12:20:09.155155 configure_display: Starting display init
9243 12:20:09.189900 anx7625_power_on_init: Init interface.
9244 12:20:09.193445 anx7625_disable_pd_protocol: Disabled PD feature.
9245 12:20:09.196036 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9246 12:20:09.223880 anx7625_start_dp_work: Secure OCM version=00
9247 12:20:09.227545 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9248 12:20:09.242633 sp_tx_get_edid_block: EDID Block = 1
9249 12:20:09.344724 Extracted contents:
9250 12:20:09.348272 header: 00 ff ff ff ff ff ff 00
9251 12:20:09.351499 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9252 12:20:09.354782 version: 01 04
9253 12:20:09.358542 basic params: 95 1f 11 78 0a
9254 12:20:09.360973 chroma info: 76 90 94 55 54 90 27 21 50 54
9255 12:20:09.364476 established: 00 00 00
9256 12:20:09.371290 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9257 12:20:09.378014 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9258 12:20:09.381496 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9259 12:20:09.387861 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9260 12:20:09.394085 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9261 12:20:09.397492 extensions: 00
9262 12:20:09.397967 checksum: fb
9263 12:20:09.398453
9264 12:20:09.403637 Manufacturer: IVO Model 57d Serial Number 0
9265 12:20:09.404075 Made week 0 of 2020
9266 12:20:09.406971 EDID version: 1.4
9267 12:20:09.407480 Digital display
9268 12:20:09.410254 6 bits per primary color channel
9269 12:20:09.413464 DisplayPort interface
9270 12:20:09.414107 Maximum image size: 31 cm x 17 cm
9271 12:20:09.417154 Gamma: 220%
9272 12:20:09.417561 Check DPMS levels
9273 12:20:09.423233 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9274 12:20:09.426468 First detailed timing is preferred timing
9275 12:20:09.430109 Established timings supported:
9276 12:20:09.430557 Standard timings supported:
9277 12:20:09.433552 Detailed timings
9278 12:20:09.436517 Hex of detail: 383680a07038204018303c0035ae10000019
9279 12:20:09.443125 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9280 12:20:09.446536 0780 0798 07c8 0820 hborder 0
9281 12:20:09.449440 0438 043b 0447 0458 vborder 0
9282 12:20:09.452746 -hsync -vsync
9283 12:20:09.455790 Did detailed timing
9284 12:20:09.459571 Hex of detail: 000000000000000000000000000000000000
9285 12:20:09.462966 Manufacturer-specified data, tag 0
9286 12:20:09.466050 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9287 12:20:09.469775 ASCII string: InfoVision
9288 12:20:09.472730 Hex of detail: 000000fe00523134304e574635205248200a
9289 12:20:09.475653 ASCII string: R140NWF5 RH
9290 12:20:09.476066 Checksum
9291 12:20:09.479147 Checksum: 0xfb (valid)
9292 12:20:09.482060 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9293 12:20:09.485314 DSI data_rate: 832800000 bps
9294 12:20:09.492113 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9295 12:20:09.495505 anx7625_parse_edid: pixelclock(138800).
9296 12:20:09.498501 hactive(1920), hsync(48), hfp(24), hbp(88)
9297 12:20:09.501972 vactive(1080), vsync(12), vfp(3), vbp(17)
9298 12:20:09.505337 anx7625_dsi_config: config dsi.
9299 12:20:09.512454 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9300 12:20:09.526637 anx7625_dsi_config: success to config DSI
9301 12:20:09.530213 anx7625_dp_start: MIPI phy setup OK.
9302 12:20:09.533188 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9303 12:20:09.536746 mtk_ddp_mode_set invalid vrefresh 60
9304 12:20:09.539411 main_disp_path_setup
9305 12:20:09.539815 ovl_layer_smi_id_en
9306 12:20:09.543041 ovl_layer_smi_id_en
9307 12:20:09.543486 ccorr_config
9308 12:20:09.543807 aal_config
9309 12:20:09.546190 gamma_config
9310 12:20:09.546591 postmask_config
9311 12:20:09.549559 dither_config
9312 12:20:09.553284 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9313 12:20:09.559281 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9314 12:20:09.562801 Root Device init finished in 554 msecs
9315 12:20:09.565931 CPU_CLUSTER: 0 init
9316 12:20:09.572302 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9317 12:20:09.579264 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9318 12:20:09.579772 APU_MBOX 0x190000b0 = 0x10001
9319 12:20:09.582703 APU_MBOX 0x190001b0 = 0x10001
9320 12:20:09.585496 APU_MBOX 0x190005b0 = 0x10001
9321 12:20:09.588972 APU_MBOX 0x190006b0 = 0x10001
9322 12:20:09.595728 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9323 12:20:09.605887 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9324 12:20:09.618777 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9325 12:20:09.625052 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9326 12:20:09.636852 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9327 12:20:09.645799 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9328 12:20:09.649172 CPU_CLUSTER: 0 init finished in 81 msecs
9329 12:20:09.652309 Devices initialized
9330 12:20:09.655644 Show all devs... After init.
9331 12:20:09.656099 Root Device: enabled 1
9332 12:20:09.659274 CPU_CLUSTER: 0: enabled 1
9333 12:20:09.662306 CPU: 00: enabled 1
9334 12:20:09.665412 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9335 12:20:09.668632 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9336 12:20:09.672117 ELOG: NV offset 0x57f000 size 0x1000
9337 12:20:09.678656 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9338 12:20:09.685266 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9339 12:20:09.688790 ELOG: Event(17) added with size 13 at 2023-10-27 12:20:09 UTC
9340 12:20:09.695600 out: cmd=0x121: 03 db 21 01 00 00 00 00
9341 12:20:09.698278 in-header: 03 00 00 00 2c 00 00 00
9342 12:20:09.708224 in-data: 5f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9343 12:20:09.714807 ELOG: Event(A1) added with size 10 at 2023-10-27 12:20:09 UTC
9344 12:20:09.721512 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9345 12:20:09.727911 ELOG: Event(A0) added with size 9 at 2023-10-27 12:20:09 UTC
9346 12:20:09.731980 elog_add_boot_reason: Logged dev mode boot
9347 12:20:09.738309 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9348 12:20:09.738877 Finalize devices...
9349 12:20:09.741368 Devices finalized
9350 12:20:09.744731 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9351 12:20:09.747776 Writing coreboot table at 0xffe64000
9352 12:20:09.750610 0. 000000000010a000-0000000000113fff: RAMSTAGE
9353 12:20:09.757378 1. 0000000040000000-00000000400fffff: RAM
9354 12:20:09.760493 2. 0000000040100000-000000004032afff: RAMSTAGE
9355 12:20:09.764086 3. 000000004032b000-00000000545fffff: RAM
9356 12:20:09.767420 4. 0000000054600000-000000005465ffff: BL31
9357 12:20:09.771027 5. 0000000054660000-00000000ffe63fff: RAM
9358 12:20:09.777203 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9359 12:20:09.780539 7. 0000000100000000-000000023fffffff: RAM
9360 12:20:09.783658 Passing 5 GPIOs to payload:
9361 12:20:09.786750 NAME | PORT | POLARITY | VALUE
9362 12:20:09.794643 EC in RW | 0x000000aa | low | undefined
9363 12:20:09.797048 EC interrupt | 0x00000005 | low | undefined
9364 12:20:09.803598 TPM interrupt | 0x000000ab | high | undefined
9365 12:20:09.807238 SD card detect | 0x00000011 | high | undefined
9366 12:20:09.810451 speaker enable | 0x00000093 | high | undefined
9367 12:20:09.813820 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9368 12:20:09.817932 in-header: 03 f9 00 00 02 00 00 00
9369 12:20:09.821311 in-data: 02 00
9370 12:20:09.824621 ADC[4]: Raw value=902586 ID=7
9371 12:20:09.827982 ADC[3]: Raw value=213916 ID=1
9372 12:20:09.828538 RAM Code: 0x71
9373 12:20:09.831189 ADC[6]: Raw value=75000 ID=0
9374 12:20:09.834740 ADC[5]: Raw value=213916 ID=1
9375 12:20:09.835221 SKU Code: 0x1
9376 12:20:09.841180 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c159
9377 12:20:09.841720 coreboot table: 964 bytes.
9378 12:20:09.844584 IMD ROOT 0. 0xfffff000 0x00001000
9379 12:20:09.847713 IMD SMALL 1. 0xffffe000 0x00001000
9380 12:20:09.851150 RO MCACHE 2. 0xffffc000 0x00001104
9381 12:20:09.854223 CONSOLE 3. 0xfff7c000 0x00080000
9382 12:20:09.857762 FMAP 4. 0xfff7b000 0x00000452
9383 12:20:09.860917 TIME STAMP 5. 0xfff7a000 0x00000910
9384 12:20:09.864133 VBOOT WORK 6. 0xfff66000 0x00014000
9385 12:20:09.867420 RAMOOPS 7. 0xffe66000 0x00100000
9386 12:20:09.871150 COREBOOT 8. 0xffe64000 0x00002000
9387 12:20:09.874026 IMD small region:
9388 12:20:09.877374 IMD ROOT 0. 0xffffec00 0x00000400
9389 12:20:09.880935 VPD 1. 0xffffeb80 0x0000006c
9390 12:20:09.883778 MMC STATUS 2. 0xffffeb60 0x00000004
9391 12:20:09.890566 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9392 12:20:09.891117 Probing TPM: done!
9393 12:20:09.897131 Connected to device vid:did:rid of 1ae0:0028:00
9394 12:20:09.904128 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9395 12:20:09.906850 Initialized TPM device CR50 revision 0
9396 12:20:09.910855 Checking cr50 for pending updates
9397 12:20:09.916359 Reading cr50 TPM mode
9398 12:20:09.924856 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9399 12:20:09.932197 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9400 12:20:09.971445 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9401 12:20:09.975027 Checking segment from ROM address 0x40100000
9402 12:20:09.978148 Checking segment from ROM address 0x4010001c
9403 12:20:09.984875 Loading segment from ROM address 0x40100000
9404 12:20:09.985332 code (compression=0)
9405 12:20:09.994894 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9406 12:20:10.001610 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9407 12:20:10.002044 it's not compressed!
9408 12:20:10.008514 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9409 12:20:10.011828 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9410 12:20:10.032711 Loading segment from ROM address 0x4010001c
9411 12:20:10.033163 Entry Point 0x80000000
9412 12:20:10.035578 Loaded segments
9413 12:20:10.039631 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9414 12:20:10.045708 Jumping to boot code at 0x80000000(0xffe64000)
9415 12:20:10.052327 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9416 12:20:10.058433 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9417 12:20:10.066307 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9418 12:20:10.070031 Checking segment from ROM address 0x40100000
9419 12:20:10.073036 Checking segment from ROM address 0x4010001c
9420 12:20:10.079487 Loading segment from ROM address 0x40100000
9421 12:20:10.079898 code (compression=1)
9422 12:20:10.086253 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9423 12:20:10.096446 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9424 12:20:10.096959 using LZMA
9425 12:20:10.105352 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9426 12:20:10.111182 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9427 12:20:10.114519 Loading segment from ROM address 0x4010001c
9428 12:20:10.114927 Entry Point 0x54601000
9429 12:20:10.118143 Loaded segments
9430 12:20:10.121602 NOTICE: MT8192 bl31_setup
9431 12:20:10.128502 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9432 12:20:10.132011 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9433 12:20:10.134737 WARNING: region 0:
9434 12:20:10.138351 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9435 12:20:10.138759 WARNING: region 1:
9436 12:20:10.144972 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9437 12:20:10.148399 WARNING: region 2:
9438 12:20:10.151557 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9439 12:20:10.155189 WARNING: region 3:
9440 12:20:10.158468 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9441 12:20:10.161676 WARNING: region 4:
9442 12:20:10.169124 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9443 12:20:10.169640 WARNING: region 5:
9444 12:20:10.171651 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9445 12:20:10.175165 WARNING: region 6:
9446 12:20:10.178843 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 12:20:10.181572 WARNING: region 7:
9448 12:20:10.184909 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 12:20:10.191988 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9450 12:20:10.195238 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9451 12:20:10.198676 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9452 12:20:10.204644 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9453 12:20:10.208163 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9454 12:20:10.211982 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9455 12:20:10.218207 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9456 12:20:10.221001 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9457 12:20:10.227816 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9458 12:20:10.231390 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9459 12:20:10.234641 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9460 12:20:10.241276 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9461 12:20:10.244684 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9462 12:20:10.247886 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9463 12:20:10.255029 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9464 12:20:10.257861 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9465 12:20:10.264642 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9466 12:20:10.267529 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9467 12:20:10.270617 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9468 12:20:10.277975 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9469 12:20:10.281159 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9470 12:20:10.287305 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9471 12:20:10.291182 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9472 12:20:10.294427 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9473 12:20:10.300865 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9474 12:20:10.304152 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9475 12:20:10.310913 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9476 12:20:10.313940 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9477 12:20:10.317735 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9478 12:20:10.323972 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9479 12:20:10.327531 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9480 12:20:10.333733 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9481 12:20:10.337108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9482 12:20:10.340329 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9483 12:20:10.343744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9484 12:20:10.350652 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9485 12:20:10.354245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9486 12:20:10.357083 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9487 12:20:10.360714 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9488 12:20:10.367165 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9489 12:20:10.370251 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9490 12:20:10.374378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9491 12:20:10.377742 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9492 12:20:10.383844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9493 12:20:10.386890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9494 12:20:10.391161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9495 12:20:10.394370 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9496 12:20:10.400460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9497 12:20:10.403473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9498 12:20:10.410509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9499 12:20:10.413565 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9500 12:20:10.416862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9501 12:20:10.424038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9502 12:20:10.426823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9503 12:20:10.433498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9504 12:20:10.437161 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9505 12:20:10.444126 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9506 12:20:10.446931 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9507 12:20:10.450473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9508 12:20:10.456755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9509 12:20:10.460291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9510 12:20:10.466827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9511 12:20:10.470304 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9512 12:20:10.477204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9513 12:20:10.479793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9514 12:20:10.487429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9515 12:20:10.490313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9516 12:20:10.494409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9517 12:20:10.500051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9518 12:20:10.503011 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9519 12:20:10.509876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9520 12:20:10.513369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9521 12:20:10.520183 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9522 12:20:10.523412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9523 12:20:10.526473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9524 12:20:10.533540 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9525 12:20:10.536368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9526 12:20:10.543024 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9527 12:20:10.546612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9528 12:20:10.552997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9529 12:20:10.556112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9530 12:20:10.563044 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9531 12:20:10.566788 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9532 12:20:10.570341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9533 12:20:10.576683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9534 12:20:10.579668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9535 12:20:10.586708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9536 12:20:10.589759 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9537 12:20:10.596311 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9538 12:20:10.599495 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9539 12:20:10.603045 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9540 12:20:10.609766 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9541 12:20:10.612842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9542 12:20:10.619833 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9543 12:20:10.623123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9544 12:20:10.629400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9545 12:20:10.633117 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9546 12:20:10.636258 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9547 12:20:10.639139 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9548 12:20:10.645829 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9549 12:20:10.649137 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9550 12:20:10.652745 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9551 12:20:10.659063 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9552 12:20:10.662509 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9553 12:20:10.669232 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9554 12:20:10.672747 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9555 12:20:10.675930 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9556 12:20:10.682345 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9557 12:20:10.686204 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9558 12:20:10.692733 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9559 12:20:10.696194 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9560 12:20:10.699187 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9561 12:20:10.705760 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9562 12:20:10.708725 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9563 12:20:10.715439 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9564 12:20:10.719201 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9565 12:20:10.722399 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9566 12:20:10.728586 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9567 12:20:10.732173 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9568 12:20:10.735387 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9569 12:20:10.738606 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9570 12:20:10.745381 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9571 12:20:10.748748 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9572 12:20:10.752173 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9573 12:20:10.758633 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9574 12:20:10.762502 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9575 12:20:10.765343 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9576 12:20:10.772195 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9577 12:20:10.775397 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9578 12:20:10.782065 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9579 12:20:10.785631 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9580 12:20:10.788324 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9581 12:20:10.794789 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9582 12:20:10.798302 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9583 12:20:10.805104 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9584 12:20:10.808386 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9585 12:20:10.811751 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9586 12:20:10.818188 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9587 12:20:10.821371 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9588 12:20:10.827825 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9589 12:20:10.831261 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9590 12:20:10.835066 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9591 12:20:10.841613 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9592 12:20:10.844403 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9593 12:20:10.851460 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9594 12:20:10.854818 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9595 12:20:10.857761 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9596 12:20:10.864864 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9597 12:20:10.867296 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9598 12:20:10.874309 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9599 12:20:10.877564 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9600 12:20:10.881108 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9601 12:20:10.887337 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9602 12:20:10.891063 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9603 12:20:10.897503 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9604 12:20:10.900509 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9605 12:20:10.904531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9606 12:20:10.910568 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9607 12:20:10.914076 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9608 12:20:10.917621 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9609 12:20:10.923586 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9610 12:20:10.926753 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9611 12:20:10.933533 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9612 12:20:10.937734 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9613 12:20:10.943554 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9614 12:20:10.946912 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9615 12:20:10.950333 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9616 12:20:10.957411 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9617 12:20:10.960528 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9618 12:20:10.966488 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9619 12:20:10.969388 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9620 12:20:10.973544 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9621 12:20:10.979937 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9622 12:20:10.983428 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9623 12:20:10.989298 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9624 12:20:10.992984 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9625 12:20:10.996088 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9626 12:20:11.002583 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9627 12:20:11.006227 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9628 12:20:11.012765 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9629 12:20:11.015822 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9630 12:20:11.019235 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9631 12:20:11.025914 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9632 12:20:11.030019 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9633 12:20:11.035608 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9634 12:20:11.038538 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9635 12:20:11.042210 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9636 12:20:11.048777 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9637 12:20:11.052624 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9638 12:20:11.058821 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9639 12:20:11.062043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9640 12:20:11.068349 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9641 12:20:11.071952 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9642 12:20:11.075115 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9643 12:20:11.082116 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9644 12:20:11.085032 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9645 12:20:11.091758 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9646 12:20:11.095154 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9647 12:20:11.101412 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9648 12:20:11.104515 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9649 12:20:11.107710 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9650 12:20:11.114402 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9651 12:20:11.118051 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9652 12:20:11.124578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9653 12:20:11.127486 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9654 12:20:11.134378 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9655 12:20:11.137702 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9656 12:20:11.140771 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9657 12:20:11.147197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9658 12:20:11.150433 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9659 12:20:11.157379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9660 12:20:11.160741 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9661 12:20:11.167587 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9662 12:20:11.170783 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9663 12:20:11.174439 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9664 12:20:11.180280 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9665 12:20:11.183791 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9666 12:20:11.190237 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9667 12:20:11.193525 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9668 12:20:11.200829 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9669 12:20:11.203516 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9670 12:20:11.206812 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9671 12:20:11.213691 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9672 12:20:11.217280 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9673 12:20:11.223106 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9674 12:20:11.226583 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9675 12:20:11.233406 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9676 12:20:11.236478 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9677 12:20:11.239811 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9678 12:20:11.246324 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9679 12:20:11.249393 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9680 12:20:11.252803 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9681 12:20:11.256778 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9682 12:20:11.263251 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9683 12:20:11.266209 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9684 12:20:11.269764 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9685 12:20:11.276751 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9686 12:20:11.279507 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9687 12:20:11.283221 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9688 12:20:11.289210 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9689 12:20:11.292666 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9690 12:20:11.299819 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9691 12:20:11.303042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9692 12:20:11.305856 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9693 12:20:11.312583 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9694 12:20:11.315628 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9695 12:20:11.318734 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9696 12:20:11.325719 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9697 12:20:11.329057 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9698 12:20:11.335866 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9699 12:20:11.338976 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9700 12:20:11.342086 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9701 12:20:11.348599 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9702 12:20:11.351532 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9703 12:20:11.355250 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9704 12:20:11.361545 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9705 12:20:11.364913 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9706 12:20:11.371835 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9707 12:20:11.375226 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9708 12:20:11.378402 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9709 12:20:11.385095 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9710 12:20:11.388092 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9711 12:20:11.395005 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9712 12:20:11.398131 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9713 12:20:11.401631 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9714 12:20:11.408271 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9715 12:20:11.410677 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9716 12:20:11.414863 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9717 12:20:11.420947 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9718 12:20:11.424808 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9719 12:20:11.427928 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9720 12:20:11.430911 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9721 12:20:11.437500 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9722 12:20:11.440768 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9723 12:20:11.444071 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9724 12:20:11.447772 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9725 12:20:11.453988 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9726 12:20:11.458600 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9727 12:20:11.461092 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9728 12:20:11.463612 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9729 12:20:11.470580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9730 12:20:11.474014 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9731 12:20:11.477721 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9732 12:20:11.483825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9733 12:20:11.487453 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9734 12:20:11.493531 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9735 12:20:11.496983 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9736 12:20:11.503275 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9737 12:20:11.506635 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9738 12:20:11.509869 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9739 12:20:11.517008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9740 12:20:11.519905 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9741 12:20:11.526460 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9742 12:20:11.530281 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9743 12:20:11.536703 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9744 12:20:11.539550 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9745 12:20:11.542580 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9746 12:20:11.549834 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9747 12:20:11.553085 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9748 12:20:11.559186 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9749 12:20:11.562442 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9750 12:20:11.565671 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9751 12:20:11.572895 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9752 12:20:11.576186 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9753 12:20:11.582482 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9754 12:20:11.586194 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9755 12:20:11.589382 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9756 12:20:11.595656 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9757 12:20:11.599039 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9758 12:20:11.605549 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9759 12:20:11.609044 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9760 12:20:11.615538 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9761 12:20:11.619048 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9762 12:20:11.622371 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9763 12:20:11.628582 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9764 12:20:11.631951 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9765 12:20:11.638472 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9766 12:20:11.642176 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9767 12:20:11.648588 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9768 12:20:11.651456 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9769 12:20:11.655164 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9770 12:20:11.662616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9771 12:20:11.665482 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9772 12:20:11.671544 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9773 12:20:11.675205 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9774 12:20:11.677885 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9775 12:20:11.684455 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9776 12:20:11.688048 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9777 12:20:11.694505 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9778 12:20:11.697995 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9779 12:20:11.701538 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9780 12:20:11.708266 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9781 12:20:11.711304 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9782 12:20:11.718200 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9783 12:20:11.720667 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9784 12:20:11.727290 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9785 12:20:11.730758 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9786 12:20:11.734010 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9787 12:20:11.740524 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9788 12:20:11.744381 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9789 12:20:11.750574 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9790 12:20:11.754490 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9791 12:20:11.760736 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9792 12:20:11.764022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9793 12:20:11.767233 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9794 12:20:11.773896 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9795 12:20:11.777248 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9796 12:20:11.783647 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9797 12:20:11.787319 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9798 12:20:11.790250 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9799 12:20:11.797945 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9800 12:20:11.800426 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9801 12:20:11.806758 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9802 12:20:11.810409 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9803 12:20:11.817269 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9804 12:20:11.820135 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9805 12:20:11.822863 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9806 12:20:11.829663 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9807 12:20:11.832720 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9808 12:20:11.839463 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9809 12:20:11.842874 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9810 12:20:11.849730 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9811 12:20:11.853006 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9812 12:20:11.859070 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9813 12:20:11.862638 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9814 12:20:11.869369 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9815 12:20:11.872703 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9816 12:20:11.875496 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9817 12:20:11.882569 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9818 12:20:11.885749 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9819 12:20:11.892100 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9820 12:20:11.895579 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9821 12:20:11.902031 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9822 12:20:11.905496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9823 12:20:11.911765 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9824 12:20:11.914974 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9825 12:20:11.922117 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9826 12:20:11.925225 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9827 12:20:11.928615 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9828 12:20:11.934835 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9829 12:20:11.938051 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9830 12:20:11.944718 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9831 12:20:11.948278 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9832 12:20:11.954843 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9833 12:20:11.958318 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9834 12:20:11.961309 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9835 12:20:11.967693 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9836 12:20:11.971389 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9837 12:20:11.978097 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9838 12:20:11.981409 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9839 12:20:11.988067 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9840 12:20:11.990968 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9841 12:20:11.998462 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9842 12:20:12.000880 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9843 12:20:12.003956 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9844 12:20:12.010908 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9845 12:20:12.014348 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9846 12:20:12.020473 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9847 12:20:12.023764 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9848 12:20:12.030653 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9849 12:20:12.033760 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9850 12:20:12.037441 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9851 12:20:12.043582 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9852 12:20:12.047364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9853 12:20:12.053697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9854 12:20:12.056865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9855 12:20:12.063626 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9856 12:20:12.067278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9857 12:20:12.073511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9858 12:20:12.076677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9859 12:20:12.083436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9860 12:20:12.086859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9861 12:20:12.093623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9862 12:20:12.096389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9863 12:20:12.103319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9864 12:20:12.106163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9865 12:20:12.112841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9866 12:20:12.116021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9867 12:20:12.122663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9868 12:20:12.125742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9869 12:20:12.132854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9870 12:20:12.135955 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9871 12:20:12.142771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9872 12:20:12.145902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9873 12:20:12.152142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9874 12:20:12.155771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9875 12:20:12.162088 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9876 12:20:12.165709 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9877 12:20:12.172737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9878 12:20:12.175828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9879 12:20:12.182148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9880 12:20:12.185657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9881 12:20:12.191730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9882 12:20:12.195356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9883 12:20:12.201802 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9884 12:20:12.202337 INFO: [APUAPC] vio 0
9885 12:20:12.208106 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9886 12:20:12.211992 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9887 12:20:12.214670 INFO: [APUAPC] D0_APC_0: 0x400510
9888 12:20:12.218563 INFO: [APUAPC] D0_APC_1: 0x0
9889 12:20:12.221406 INFO: [APUAPC] D0_APC_2: 0x1540
9890 12:20:12.224876 INFO: [APUAPC] D0_APC_3: 0x0
9891 12:20:12.228387 INFO: [APUAPC] D1_APC_0: 0xffffffff
9892 12:20:12.231386 INFO: [APUAPC] D1_APC_1: 0xffffffff
9893 12:20:12.234914 INFO: [APUAPC] D1_APC_2: 0x3fffff
9894 12:20:12.237953 INFO: [APUAPC] D1_APC_3: 0x0
9895 12:20:12.241280 INFO: [APUAPC] D2_APC_0: 0xffffffff
9896 12:20:12.245339 INFO: [APUAPC] D2_APC_1: 0xffffffff
9897 12:20:12.248125 INFO: [APUAPC] D2_APC_2: 0x3fffff
9898 12:20:12.251038 INFO: [APUAPC] D2_APC_3: 0x0
9899 12:20:12.254407 INFO: [APUAPC] D3_APC_0: 0xffffffff
9900 12:20:12.257774 INFO: [APUAPC] D3_APC_1: 0xffffffff
9901 12:20:12.261347 INFO: [APUAPC] D3_APC_2: 0x3fffff
9902 12:20:12.264201 INFO: [APUAPC] D3_APC_3: 0x0
9903 12:20:12.267960 INFO: [APUAPC] D4_APC_0: 0xffffffff
9904 12:20:12.270853 INFO: [APUAPC] D4_APC_1: 0xffffffff
9905 12:20:12.274524 INFO: [APUAPC] D4_APC_2: 0x3fffff
9906 12:20:12.278146 INFO: [APUAPC] D4_APC_3: 0x0
9907 12:20:12.281497 INFO: [APUAPC] D5_APC_0: 0xffffffff
9908 12:20:12.284716 INFO: [APUAPC] D5_APC_1: 0xffffffff
9909 12:20:12.287909 INFO: [APUAPC] D5_APC_2: 0x3fffff
9910 12:20:12.288418 INFO: [APUAPC] D5_APC_3: 0x0
9911 12:20:12.294632 INFO: [APUAPC] D6_APC_0: 0xffffffff
9912 12:20:12.297673 INFO: [APUAPC] D6_APC_1: 0xffffffff
9913 12:20:12.300691 INFO: [APUAPC] D6_APC_2: 0x3fffff
9914 12:20:12.301106 INFO: [APUAPC] D6_APC_3: 0x0
9915 12:20:12.303797 INFO: [APUAPC] D7_APC_0: 0xffffffff
9916 12:20:12.311038 INFO: [APUAPC] D7_APC_1: 0xffffffff
9917 12:20:12.313935 INFO: [APUAPC] D7_APC_2: 0x3fffff
9918 12:20:12.314348 INFO: [APUAPC] D7_APC_3: 0x0
9919 12:20:12.317208 INFO: [APUAPC] D8_APC_0: 0xffffffff
9920 12:20:12.320685 INFO: [APUAPC] D8_APC_1: 0xffffffff
9921 12:20:12.323839 INFO: [APUAPC] D8_APC_2: 0x3fffff
9922 12:20:12.327467 INFO: [APUAPC] D8_APC_3: 0x0
9923 12:20:12.330345 INFO: [APUAPC] D9_APC_0: 0xffffffff
9924 12:20:12.333687 INFO: [APUAPC] D9_APC_1: 0xffffffff
9925 12:20:12.337958 INFO: [APUAPC] D9_APC_2: 0x3fffff
9926 12:20:12.340396 INFO: [APUAPC] D9_APC_3: 0x0
9927 12:20:12.343586 INFO: [APUAPC] D10_APC_0: 0xffffffff
9928 12:20:12.346957 INFO: [APUAPC] D10_APC_1: 0xffffffff
9929 12:20:12.350207 INFO: [APUAPC] D10_APC_2: 0x3fffff
9930 12:20:12.353545 INFO: [APUAPC] D10_APC_3: 0x0
9931 12:20:12.356994 INFO: [APUAPC] D11_APC_0: 0xffffffff
9932 12:20:12.363676 INFO: [APUAPC] D11_APC_1: 0xffffffff
9933 12:20:12.366570 INFO: [APUAPC] D11_APC_2: 0x3fffff
9934 12:20:12.366984 INFO: [APUAPC] D11_APC_3: 0x0
9935 12:20:12.373074 INFO: [APUAPC] D12_APC_0: 0xffffffff
9936 12:20:12.376318 INFO: [APUAPC] D12_APC_1: 0xffffffff
9937 12:20:12.379386 INFO: [APUAPC] D12_APC_2: 0x3fffff
9938 12:20:12.379802 INFO: [APUAPC] D12_APC_3: 0x0
9939 12:20:12.386858 INFO: [APUAPC] D13_APC_0: 0xffffffff
9940 12:20:12.389730 INFO: [APUAPC] D13_APC_1: 0xffffffff
9941 12:20:12.392855 INFO: [APUAPC] D13_APC_2: 0x3fffff
9942 12:20:12.396118 INFO: [APUAPC] D13_APC_3: 0x0
9943 12:20:12.399887 INFO: [APUAPC] D14_APC_0: 0xffffffff
9944 12:20:12.402916 INFO: [APUAPC] D14_APC_1: 0xffffffff
9945 12:20:12.406673 INFO: [APUAPC] D14_APC_2: 0x3fffff
9946 12:20:12.409483 INFO: [APUAPC] D14_APC_3: 0x0
9947 12:20:12.412755 INFO: [APUAPC] D15_APC_0: 0xffffffff
9948 12:20:12.415677 INFO: [APUAPC] D15_APC_1: 0xffffffff
9949 12:20:12.419405 INFO: [APUAPC] D15_APC_2: 0x3fffff
9950 12:20:12.422735 INFO: [APUAPC] D15_APC_3: 0x0
9951 12:20:12.423184 INFO: [APUAPC] APC_CON: 0x4
9952 12:20:12.425519 INFO: [NOCDAPC] D0_APC_0: 0x0
9953 12:20:12.429544 INFO: [NOCDAPC] D0_APC_1: 0x0
9954 12:20:12.432501 INFO: [NOCDAPC] D1_APC_0: 0x0
9955 12:20:12.436533 INFO: [NOCDAPC] D1_APC_1: 0xfff
9956 12:20:12.438803 INFO: [NOCDAPC] D2_APC_0: 0x0
9957 12:20:12.442661 INFO: [NOCDAPC] D2_APC_1: 0xfff
9958 12:20:12.445649 INFO: [NOCDAPC] D3_APC_0: 0x0
9959 12:20:12.448855 INFO: [NOCDAPC] D3_APC_1: 0xfff
9960 12:20:12.451896 INFO: [NOCDAPC] D4_APC_0: 0x0
9961 12:20:12.455797 INFO: [NOCDAPC] D4_APC_1: 0xfff
9962 12:20:12.456392 INFO: [NOCDAPC] D5_APC_0: 0x0
9963 12:20:12.458931 INFO: [NOCDAPC] D5_APC_1: 0xfff
9964 12:20:12.462457 INFO: [NOCDAPC] D6_APC_0: 0x0
9965 12:20:12.465712 INFO: [NOCDAPC] D6_APC_1: 0xfff
9966 12:20:12.468722 INFO: [NOCDAPC] D7_APC_0: 0x0
9967 12:20:12.472068 INFO: [NOCDAPC] D7_APC_1: 0xfff
9968 12:20:12.475440 INFO: [NOCDAPC] D8_APC_0: 0x0
9969 12:20:12.478807 INFO: [NOCDAPC] D8_APC_1: 0xfff
9970 12:20:12.482273 INFO: [NOCDAPC] D9_APC_0: 0x0
9971 12:20:12.485419 INFO: [NOCDAPC] D9_APC_1: 0xfff
9972 12:20:12.488332 INFO: [NOCDAPC] D10_APC_0: 0x0
9973 12:20:12.491816 INFO: [NOCDAPC] D10_APC_1: 0xfff
9974 12:20:12.494798 INFO: [NOCDAPC] D11_APC_0: 0x0
9975 12:20:12.498037 INFO: [NOCDAPC] D11_APC_1: 0xfff
9976 12:20:12.498477 INFO: [NOCDAPC] D12_APC_0: 0x0
9977 12:20:12.502245 INFO: [NOCDAPC] D12_APC_1: 0xfff
9978 12:20:12.504771 INFO: [NOCDAPC] D13_APC_0: 0x0
9979 12:20:12.507929 INFO: [NOCDAPC] D13_APC_1: 0xfff
9980 12:20:12.511430 INFO: [NOCDAPC] D14_APC_0: 0x0
9981 12:20:12.514897 INFO: [NOCDAPC] D14_APC_1: 0xfff
9982 12:20:12.518631 INFO: [NOCDAPC] D15_APC_0: 0x0
9983 12:20:12.522098 INFO: [NOCDAPC] D15_APC_1: 0xfff
9984 12:20:12.524869 INFO: [NOCDAPC] APC_CON: 0x4
9985 12:20:12.528160 INFO: [APUAPC] set_apusys_apc done
9986 12:20:12.531692 INFO: [DEVAPC] devapc_init done
9987 12:20:12.534585 INFO: GICv3 without legacy support detected.
9988 12:20:12.538260 INFO: ARM GICv3 driver initialized in EL3
9989 12:20:12.541650 INFO: Maximum SPI INTID supported: 639
9990 12:20:12.547963 INFO: BL31: Initializing runtime services
9991 12:20:12.551411 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9992 12:20:12.554260 INFO: SPM: enable CPC mode
9993 12:20:12.561251 INFO: mcdi ready for mcusys-off-idle and system suspend
9994 12:20:12.564255 INFO: BL31: Preparing for EL3 exit to normal world
9995 12:20:12.567464 INFO: Entry point address = 0x80000000
9996 12:20:12.571187 INFO: SPSR = 0x8
9997 12:20:12.576931
9998 12:20:12.577476
9999 12:20:12.577831
10000 12:20:12.580361 Starting depthcharge on Spherion...
10001 12:20:12.580908
10002 12:20:12.581269 Wipe memory regions:
10003 12:20:12.581601
10004 12:20:12.584254 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10005 12:20:12.584792 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10006 12:20:12.585227 Setting prompt string to ['asurada:']
10007 12:20:12.585625 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10008 12:20:12.586367 [0x00000040000000, 0x00000054600000)
10009 12:20:12.705536
10010 12:20:12.706080 [0x00000054660000, 0x00000080000000)
10011 12:20:12.966631
10012 12:20:12.967213 [0x000000821a7280, 0x000000ffe64000)
10013 12:20:13.711713
10014 12:20:13.712257 [0x00000100000000, 0x00000240000000)
10015 12:20:15.601856
10016 12:20:15.604276 Initializing XHCI USB controller at 0x11200000.
10017 12:20:16.642769
10018 12:20:16.645759 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10019 12:20:16.646221
10020 12:20:16.646648
10021 12:20:16.646954
10022 12:20:16.647725 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10024 12:20:16.749097 asurada: tftpboot 192.168.201.1 11893130/tftp-deploy-ggesbx_0/kernel/image.itb 11893130/tftp-deploy-ggesbx_0/kernel/cmdline
10025 12:20:16.749751 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10026 12:20:16.750336 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10027 12:20:16.755398 tftpboot 192.168.201.1 11893130/tftp-deploy-ggesbx_0/kernel/image.itbtp-deploy-ggesbx_0/kernel/cmdline
10028 12:20:16.755953
10029 12:20:16.756312 Waiting for link
10030 12:20:16.915955
10031 12:20:16.916496 R8152: Initializing
10032 12:20:16.916921
10033 12:20:16.918920 Version 6 (ocp_data = 5c30)
10034 12:20:16.919534
10035 12:20:16.922269 R8152: Done initializing
10036 12:20:16.922724
10037 12:20:16.923123 Adding net device
10038 12:20:18.773581
10039 12:20:18.774083 done.
10040 12:20:18.774409
10041 12:20:18.774712 MAC: 00:24:32:30:7c:7b
10042 12:20:18.775003
10043 12:20:18.777121 Sending DHCP discover... done.
10044 12:20:18.777628
10045 12:20:23.601923 Waiting for reply... done.
10046 12:20:23.602434
10047 12:20:23.602769 Sending DHCP request... done.
10048 12:20:23.604726
10049 12:20:23.608998 Waiting for reply... done.
10050 12:20:23.609406
10051 12:20:23.609725 My ip is 192.168.201.14
10052 12:20:23.610020
10053 12:20:23.612324 The DHCP server ip is 192.168.201.1
10054 12:20:23.612737
10055 12:20:23.618733 TFTP server IP predefined by user: 192.168.201.1
10056 12:20:23.619193
10057 12:20:23.625049 Bootfile predefined by user: 11893130/tftp-deploy-ggesbx_0/kernel/image.itb
10058 12:20:23.625499
10059 12:20:23.628446 Sending tftp read request... done.
10060 12:20:23.628860
10061 12:20:23.634923 Waiting for the transfer...
10062 12:20:23.635412
10063 12:20:24.210847 00000000 ################################################################
10064 12:20:24.210995
10065 12:20:24.777132 00080000 ################################################################
10066 12:20:24.777306
10067 12:20:25.364495 00100000 ################################################################
10068 12:20:25.364634
10069 12:20:25.966232 00180000 ################################################################
10070 12:20:25.966380
10071 12:20:26.565849 00200000 ################################################################
10072 12:20:26.566363
10073 12:20:27.189885 00280000 ################################################################
10074 12:20:27.190017
10075 12:20:27.771462 00300000 ################################################################
10076 12:20:27.771605
10077 12:20:28.482021 00380000 ################################################################
10078 12:20:28.482178
10079 12:20:29.165347 00400000 ################################################################
10080 12:20:29.165506
10081 12:20:29.743649 00480000 ################################################################
10082 12:20:29.743781
10083 12:20:30.291512 00500000 ################################################################
10084 12:20:30.291646
10085 12:20:30.971604 00580000 ################################################################
10086 12:20:30.971755
10087 12:20:31.628668 00600000 ################################################################
10088 12:20:31.628812
10089 12:20:32.190451 00680000 ################################################################
10090 12:20:32.190596
10091 12:20:32.777995 00700000 ################################################################
10092 12:20:32.778480
10093 12:20:33.394351 00780000 ################################################################
10094 12:20:33.394514
10095 12:20:33.989179 00800000 ################################################################
10096 12:20:33.989312
10097 12:20:34.550451 00880000 ################################################################
10098 12:20:34.550606
10099 12:20:35.084404 00900000 ################################################################
10100 12:20:35.084656
10101 12:20:35.633947 00980000 ################################################################
10102 12:20:35.634090
10103 12:20:36.216017 00a00000 ################################################################
10104 12:20:36.216190
10105 12:20:36.892616 00a80000 ################################################################
10106 12:20:36.892791
10107 12:20:37.572301 00b00000 ################################################################
10108 12:20:37.572495
10109 12:20:38.298356 00b80000 ################################################################
10110 12:20:38.298527
10111 12:20:39.010518 00c00000 ################################################################
10112 12:20:39.010692
10113 12:20:39.702061 00c80000 ################################################################
10114 12:20:39.702211
10115 12:20:40.369205 00d00000 ################################################################
10116 12:20:40.369332
10117 12:20:41.000294 00d80000 ################################################################
10118 12:20:41.000436
10119 12:20:41.663687 00e00000 ################################################################
10120 12:20:41.664199
10121 12:20:42.322867 00e80000 ################################################################
10122 12:20:42.323013
10123 12:20:42.962639 00f00000 ################################################################
10124 12:20:42.962816
10125 12:20:43.683881 00f80000 ################################################################
10126 12:20:43.684032
10127 12:20:44.362772 01000000 ################################################################
10128 12:20:44.362922
10129 12:20:45.066536 01080000 ################################################################
10130 12:20:45.066718
10131 12:20:45.775560 01100000 ################################################################
10132 12:20:45.775705
10133 12:20:46.487621 01180000 ################################################################
10134 12:20:46.488116
10135 12:20:47.171078 01200000 ################################################################
10136 12:20:47.171237
10137 12:20:47.889363 01280000 ################################################################
10138 12:20:47.889511
10139 12:20:48.600536 01300000 ################################################################
10140 12:20:48.600685
10141 12:20:49.299120 01380000 ################################################################
10142 12:20:49.299272
10143 12:20:50.003986 01400000 ################################################################
10144 12:20:50.004135
10145 12:20:50.664301 01480000 ################################################################
10146 12:20:50.664443
10147 12:20:51.371290 01500000 ################################################################
10148 12:20:51.371440
10149 12:20:52.061410 01580000 ################################################################
10150 12:20:52.061560
10151 12:20:52.771704 01600000 ################################################################
10152 12:20:52.771880
10153 12:20:53.483033 01680000 ################################################################
10154 12:20:53.483217
10155 12:20:54.184933 01700000 ################################################################
10156 12:20:54.185128
10157 12:20:54.765571 01780000 ################################################################
10158 12:20:54.765707
10159 12:20:55.393119 01800000 ################################################################
10160 12:20:55.393264
10161 12:20:56.077436 01880000 ################################################################
10162 12:20:56.077585
10163 12:20:56.744396 01900000 ################################################################
10164 12:20:56.744530
10165 12:20:57.447005 01980000 ################################################################
10166 12:20:57.447193
10167 12:20:58.139895 01a00000 ################################################################
10168 12:20:58.140042
10169 12:20:58.856771 01a80000 ################################################################
10170 12:20:58.856929
10171 12:20:59.547417 01b00000 ################################################################
10172 12:20:59.547587
10173 12:21:00.265760 01b80000 ################################################################
10174 12:21:00.265912
10175 12:21:00.958793 01c00000 ################################################################
10176 12:21:00.958936
10177 12:21:01.657259 01c80000 ################################################################
10178 12:21:01.657408
10179 12:21:02.339809 01d00000 ################################################################
10180 12:21:02.339950
10181 12:21:03.050843 01d80000 ################################################################
10182 12:21:03.050992
10183 12:21:03.763421 01e00000 ################################################################
10184 12:21:03.763572
10185 12:21:04.442047 01e80000 ################################################################
10186 12:21:04.442222
10187 12:21:05.138143 01f00000 ################################################################
10188 12:21:05.138292
10189 12:21:05.830106 01f80000 ################################################################
10190 12:21:05.830257
10191 12:21:06.518079 02000000 ################################################################
10192 12:21:06.518255
10193 12:21:07.206598 02080000 ################################################################
10194 12:21:07.206749
10195 12:21:07.894688 02100000 ################################################################
10196 12:21:07.894854
10197 12:21:08.602231 02180000 ################################################################
10198 12:21:08.602386
10199 12:21:09.305273 02200000 ################################################################
10200 12:21:09.305461
10201 12:21:10.007735 02280000 ################################################################
10202 12:21:10.007948
10203 12:21:10.697623 02300000 ################################################################
10204 12:21:10.697810
10205 12:21:11.378146 02380000 ################################################################
10206 12:21:11.378305
10207 12:21:12.056653 02400000 ################################################################
10208 12:21:12.056819
10209 12:21:12.752473 02480000 ################################################################
10210 12:21:12.752625
10211 12:21:13.440304 02500000 ################################################################
10212 12:21:13.440484
10213 12:21:14.143775 02580000 ################################################################
10214 12:21:14.143927
10215 12:21:14.839720 02600000 ################################################################
10216 12:21:14.839870
10217 12:21:15.523014 02680000 ################################################################
10218 12:21:15.523189
10219 12:21:16.191054 02700000 ################################################################
10220 12:21:16.191228
10221 12:21:16.890026 02780000 ################################################################
10222 12:21:16.890167
10223 12:21:17.566599 02800000 ################################################################
10224 12:21:17.566760
10225 12:21:18.269491 02880000 ################################################################
10226 12:21:18.269691
10227 12:21:18.963610 02900000 ################################################################
10228 12:21:18.963781
10229 12:21:19.672511 02980000 ################################################################
10230 12:21:19.672728
10231 12:21:20.357631 02a00000 ################################################################
10232 12:21:20.357794
10233 12:21:21.030765 02a80000 ################################################################
10234 12:21:21.030932
10235 12:21:21.700662 02b00000 ################################################################
10236 12:21:21.700831
10237 12:21:22.373959 02b80000 ################################################################
10238 12:21:22.374124
10239 12:21:23.055206 02c00000 ################################################################
10240 12:21:23.055341
10241 12:21:23.728372 02c80000 ################################################################
10242 12:21:23.728539
10243 12:21:24.394822 02d00000 ################################################################
10244 12:21:24.394986
10245 12:21:25.082913 02d80000 ################################################################
10246 12:21:25.083058
10247 12:21:25.764169 02e00000 ################################################################
10248 12:21:25.764300
10249 12:21:26.395025 02e80000 ################################################################
10250 12:21:26.395191
10251 12:21:27.049064 02f00000 ################################################################
10252 12:21:27.049216
10253 12:21:27.684701 02f80000 ################################################################
10254 12:21:27.684838
10255 12:21:28.322771 03000000 ################################################################
10256 12:21:28.322917
10257 12:21:28.956129 03080000 ################################################################
10258 12:21:28.956262
10259 12:21:29.577025 03100000 ################################################################
10260 12:21:29.577190
10261 12:21:30.207381 03180000 ################################################################
10262 12:21:30.207525
10263 12:21:30.834722 03200000 ################################################################
10264 12:21:30.834888
10265 12:21:31.454601 03280000 ################################################################
10266 12:21:31.454736
10267 12:21:32.058322 03300000 ################################################################
10268 12:21:32.058493
10269 12:21:32.670241 03380000 ################################################################
10270 12:21:32.670426
10271 12:21:33.281867 03400000 ################################################################
10272 12:21:33.282030
10273 12:21:33.890000 03480000 ################################################################
10274 12:21:33.890162
10275 12:21:34.500680 03500000 ################################################################
10276 12:21:34.500842
10277 12:21:35.108700 03580000 ################################################################
10278 12:21:35.108864
10279 12:21:35.711462 03600000 ################################################################
10280 12:21:35.711635
10281 12:21:36.326451 03680000 ################################################################
10282 12:21:36.326644
10283 12:21:36.946666 03700000 ################################################################
10284 12:21:36.946830
10285 12:21:37.448730 03780000 ##################################################### done.
10286 12:21:37.448888
10287 12:21:37.451770 The bootfile was 58622002 bytes long.
10288 12:21:37.451879
10289 12:21:37.455303 Sending tftp read request... done.
10290 12:21:37.455390
10291 12:21:37.455461 Waiting for the transfer...
10292 12:21:37.458463
10293 12:21:37.458568 00000000 # done.
10294 12:21:37.458664
10295 12:21:37.465041 Command line loaded dynamically from TFTP file: 11893130/tftp-deploy-ggesbx_0/kernel/cmdline
10296 12:21:37.465152
10297 12:21:37.478110 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10298 12:21:37.481571
10299 12:21:37.481678 Loading FIT.
10300 12:21:37.481777
10301 12:21:37.484712 Image ramdisk-1 has 47524695 bytes.
10302 12:21:37.484817
10303 12:21:37.487855 Image fdt-1 has 47278 bytes.
10304 12:21:37.487959
10305 12:21:37.491192 Image kernel-1 has 11047994 bytes.
10306 12:21:37.491293
10307 12:21:37.497706 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10308 12:21:37.497810
10309 12:21:37.517453 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10310 12:21:37.517579
10311 12:21:37.520767 Choosing best match conf-1 for compat google,spherion-rev2.
10312 12:21:37.525634
10313 12:21:37.530319 Connected to device vid:did:rid of 1ae0:0028:00
10314 12:21:37.536982
10315 12:21:37.540598 tpm_get_response: command 0x17b, return code 0x0
10316 12:21:37.540713
10317 12:21:37.544095 ec_init: CrosEC protocol v3 supported (256, 248)
10318 12:21:37.547703
10319 12:21:37.551371 tpm_cleanup: add release locality here.
10320 12:21:37.551476
10321 12:21:37.551567 Shutting down all USB controllers.
10322 12:21:37.554492
10323 12:21:37.554599 Removing current net device
10324 12:21:37.554691
10325 12:21:37.561050 Exiting depthcharge with code 4 at timestamp: 114267265
10326 12:21:37.561154
10327 12:21:37.564825 LZMA decompressing kernel-1 to 0x821a6718
10328 12:21:37.564931
10329 12:21:37.567583 LZMA decompressing kernel-1 to 0x40000000
10330 12:21:38.956286
10331 12:21:38.956445 jumping to kernel
10332 12:21:38.957482 end: 2.2.4 bootloader-commands (duration 00:01:26) [common]
10333 12:21:38.957611 start: 2.2.5 auto-login-action (timeout 00:02:59) [common]
10334 12:21:38.957726 Setting prompt string to ['Linux version [0-9]']
10335 12:21:38.957824 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10336 12:21:38.957926 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10337 12:21:39.038011
10338 12:21:39.041544 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10339 12:21:39.044768 start: 2.2.5.1 login-action (timeout 00:02:59) [common]
10340 12:21:39.044886 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10341 12:21:39.044985 Setting prompt string to []
10342 12:21:39.045104 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10343 12:21:39.045210 Using line separator: #'\n'#
10344 12:21:39.045298 No login prompt set.
10345 12:21:39.045401 Parsing kernel messages
10346 12:21:39.045486 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10347 12:21:39.045638 [login-action] Waiting for messages, (timeout 00:02:59)
10348 12:21:39.064358 [ 0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023
10349 12:21:39.067545 [ 0.000000] random: crng init done
10350 12:21:39.074652 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10351 12:21:39.077755 [ 0.000000] efi: UEFI not found.
10352 12:21:39.084570 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10353 12:21:39.090769 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10354 12:21:39.100572 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10355 12:21:39.110588 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10356 12:21:39.117155 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10357 12:21:39.123720 [ 0.000000] printk: bootconsole [mtk8250] enabled
10358 12:21:39.130057 [ 0.000000] NUMA: No NUMA configuration found
10359 12:21:39.136684 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10360 12:21:39.140240 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10361 12:21:39.143482 [ 0.000000] Zone ranges:
10362 12:21:39.150142 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10363 12:21:39.153630 [ 0.000000] DMA32 empty
10364 12:21:39.160275 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10365 12:21:39.163304 [ 0.000000] Movable zone start for each node
10366 12:21:39.166280 [ 0.000000] Early memory node ranges
10367 12:21:39.172951 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10368 12:21:39.179483 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10369 12:21:39.186178 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10370 12:21:39.192657 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10371 12:21:39.199587 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10372 12:21:39.205910 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10373 12:21:39.262198 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10374 12:21:39.268794 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10375 12:21:39.275743 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10376 12:21:39.278804 [ 0.000000] psci: probing for conduit method from DT.
10377 12:21:39.285421 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10378 12:21:39.289046 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10379 12:21:39.295100 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10380 12:21:39.298443 [ 0.000000] psci: SMC Calling Convention v1.2
10381 12:21:39.305044 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10382 12:21:39.308413 [ 0.000000] Detected VIPT I-cache on CPU0
10383 12:21:39.314970 [ 0.000000] CPU features: detected: GIC system register CPU interface
10384 12:21:39.321478 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10385 12:21:39.328105 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10386 12:21:39.334620 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10387 12:21:39.344643 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10388 12:21:39.351544 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10389 12:21:39.354250 [ 0.000000] alternatives: applying boot alternatives
10390 12:21:39.361426 [ 0.000000] Fallback order for Node 0: 0
10391 12:21:39.367689 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10392 12:21:39.371307 [ 0.000000] Policy zone: Normal
10393 12:21:39.383946 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10394 12:21:39.394167 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10395 12:21:39.406543 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10396 12:21:39.416208 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10397 12:21:39.422686 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10398 12:21:39.426357 <6>[ 0.000000] software IO TLB: area num 8.
10399 12:21:39.483176 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10400 12:21:39.632107 <6>[ 0.000000] Memory: 7923080K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 429688K reserved, 32768K cma-reserved)
10401 12:21:39.638276 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10402 12:21:39.645610 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10403 12:21:39.648533 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10404 12:21:39.655236 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10405 12:21:39.661805 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10406 12:21:39.664761 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10407 12:21:39.674720 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10408 12:21:39.681370 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10409 12:21:39.687954 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10410 12:21:39.694306 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10411 12:21:39.697642 <6>[ 0.000000] GICv3: 608 SPIs implemented
10412 12:21:39.701103 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10413 12:21:39.707822 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10414 12:21:39.710644 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10415 12:21:39.717766 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10416 12:21:39.730831 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10417 12:21:39.743555 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10418 12:21:39.750546 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10419 12:21:39.758139 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10420 12:21:39.771281 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10421 12:21:39.777879 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10422 12:21:39.784880 <6>[ 0.009233] Console: colour dummy device 80x25
10423 12:21:39.794924 <6>[ 0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10424 12:21:39.801099 <6>[ 0.024450] pid_max: default: 32768 minimum: 301
10425 12:21:39.804404 <6>[ 0.029351] LSM: Security Framework initializing
10426 12:21:39.811442 <6>[ 0.034290] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10427 12:21:39.821433 <6>[ 0.042153] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10428 12:21:39.830870 <6>[ 0.051573] cblist_init_generic: Setting adjustable number of callback queues.
10429 12:21:39.834496 <6>[ 0.059013] cblist_init_generic: Setting shift to 3 and lim to 1.
10430 12:21:39.844534 <6>[ 0.065352] cblist_init_generic: Setting adjustable number of callback queues.
10431 12:21:39.851175 <6>[ 0.072825] cblist_init_generic: Setting shift to 3 and lim to 1.
10432 12:21:39.854225 <6>[ 0.079267] rcu: Hierarchical SRCU implementation.
10433 12:21:39.860772 <6>[ 0.084282] rcu: Max phase no-delay instances is 1000.
10434 12:21:39.867375 <6>[ 0.091309] EFI services will not be available.
10435 12:21:39.870802 <6>[ 0.096266] smp: Bringing up secondary CPUs ...
10436 12:21:39.879657 <6>[ 0.101317] Detected VIPT I-cache on CPU1
10437 12:21:39.886145 <6>[ 0.101387] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10438 12:21:39.892527 <6>[ 0.101418] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10439 12:21:39.895940 <6>[ 0.101756] Detected VIPT I-cache on CPU2
10440 12:21:39.905896 <6>[ 0.101806] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10441 12:21:39.912510 <6>[ 0.101823] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10442 12:21:39.915282 <6>[ 0.102088] Detected VIPT I-cache on CPU3
10443 12:21:39.921807 <6>[ 0.102136] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10444 12:21:39.928856 <6>[ 0.102149] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10445 12:21:39.934969 <6>[ 0.102439] CPU features: detected: Spectre-v4
10446 12:21:39.938526 <6>[ 0.102445] CPU features: detected: Spectre-BHB
10447 12:21:39.941961 <6>[ 0.102449] Detected PIPT I-cache on CPU4
10448 12:21:39.951720 <6>[ 0.102500] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10449 12:21:39.958290 <6>[ 0.102516] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10450 12:21:39.961654 <6>[ 0.102802] Detected PIPT I-cache on CPU5
10451 12:21:39.968270 <6>[ 0.102864] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10452 12:21:39.974887 <6>[ 0.102881] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10453 12:21:39.977616 <6>[ 0.103163] Detected PIPT I-cache on CPU6
10454 12:21:39.987774 <6>[ 0.103228] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10455 12:21:39.994393 <6>[ 0.103245] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10456 12:21:39.997352 <6>[ 0.103543] Detected PIPT I-cache on CPU7
10457 12:21:40.004166 <6>[ 0.103608] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10458 12:21:40.010823 <6>[ 0.103625] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10459 12:21:40.013757 <6>[ 0.103671] smp: Brought up 1 node, 8 CPUs
10460 12:21:40.020736 <6>[ 0.244994] SMP: Total of 8 processors activated.
10461 12:21:40.027121 <6>[ 0.249915] CPU features: detected: 32-bit EL0 Support
10462 12:21:40.033955 <6>[ 0.255278] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10463 12:21:40.040465 <6>[ 0.264079] CPU features: detected: Common not Private translations
10464 12:21:40.046960 <6>[ 0.270555] CPU features: detected: CRC32 instructions
10465 12:21:40.053575 <6>[ 0.275906] CPU features: detected: RCpc load-acquire (LDAPR)
10466 12:21:40.056573 <6>[ 0.281866] CPU features: detected: LSE atomic instructions
10467 12:21:40.063648 <6>[ 0.287684] CPU features: detected: Privileged Access Never
10468 12:21:40.069838 <6>[ 0.293464] CPU features: detected: RAS Extension Support
10469 12:21:40.076397 <6>[ 0.299107] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10470 12:21:40.079990 <6>[ 0.306326] CPU: All CPU(s) started at EL2
10471 12:21:40.086409 <6>[ 0.310642] alternatives: applying system-wide alternatives
10472 12:21:40.097025 <6>[ 0.321349] devtmpfs: initialized
10473 12:21:40.112745 <6>[ 0.330252] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10474 12:21:40.118973 <6>[ 0.340217] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10475 12:21:40.125394 <6>[ 0.348392] pinctrl core: initialized pinctrl subsystem
10476 12:21:40.129103 <6>[ 0.355063] DMI not present or invalid.
10477 12:21:40.135484 <6>[ 0.359478] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10478 12:21:40.145361 <6>[ 0.366355] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10479 12:21:40.152251 <6>[ 0.373945] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10480 12:21:40.161735 <6>[ 0.382167] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10481 12:21:40.164892 <6>[ 0.390411] audit: initializing netlink subsys (disabled)
10482 12:21:40.175401 <5>[ 0.396105] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10483 12:21:40.181618 <6>[ 0.396820] thermal_sys: Registered thermal governor 'step_wise'
10484 12:21:40.188109 <6>[ 0.404071] thermal_sys: Registered thermal governor 'power_allocator'
10485 12:21:40.191417 <6>[ 0.410329] cpuidle: using governor menu
10486 12:21:40.198354 <6>[ 0.421294] NET: Registered PF_QIPCRTR protocol family
10487 12:21:40.204988 <6>[ 0.426779] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10488 12:21:40.211388 <6>[ 0.433882] ASID allocator initialised with 32768 entries
10489 12:21:40.214299 <6>[ 0.440470] Serial: AMBA PL011 UART driver
10490 12:21:40.224924 <4>[ 0.449248] Trying to register duplicate clock ID: 134
10491 12:21:40.279110 <6>[ 0.506612] KASLR enabled
10492 12:21:40.293427 <6>[ 0.514372] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10493 12:21:40.299664 <6>[ 0.521386] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10494 12:21:40.306224 <6>[ 0.527876] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10495 12:21:40.312628 <6>[ 0.534883] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10496 12:21:40.319413 <6>[ 0.541370] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10497 12:21:40.326113 <6>[ 0.548375] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10498 12:21:40.332934 <6>[ 0.554863] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10499 12:21:40.339356 <6>[ 0.561869] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10500 12:21:40.342290 <6>[ 0.569393] ACPI: Interpreter disabled.
10501 12:21:40.351217 <6>[ 0.575803] iommu: Default domain type: Translated
10502 12:21:40.358197 <6>[ 0.580915] iommu: DMA domain TLB invalidation policy: strict mode
10503 12:21:40.361596 <5>[ 0.587574] SCSI subsystem initialized
10504 12:21:40.367734 <6>[ 0.591755] usbcore: registered new interface driver usbfs
10505 12:21:40.374407 <6>[ 0.597488] usbcore: registered new interface driver hub
10506 12:21:40.377883 <6>[ 0.603041] usbcore: registered new device driver usb
10507 12:21:40.384771 <6>[ 0.609146] pps_core: LinuxPPS API ver. 1 registered
10508 12:21:40.394716 <6>[ 0.614340] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10509 12:21:40.397722 <6>[ 0.623688] PTP clock support registered
10510 12:21:40.401042 <6>[ 0.627933] EDAC MC: Ver: 3.0.0
10511 12:21:40.408994 <6>[ 0.633081] FPGA manager framework
10512 12:21:40.415094 <6>[ 0.636764] Advanced Linux Sound Architecture Driver Initialized.
10513 12:21:40.418669 <6>[ 0.643552] vgaarb: loaded
10514 12:21:40.425202 <6>[ 0.646730] clocksource: Switched to clocksource arch_sys_counter
10515 12:21:40.428201 <5>[ 0.653180] VFS: Disk quotas dquot_6.6.0
10516 12:21:40.434820 <6>[ 0.657367] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10517 12:21:40.437998 <6>[ 0.664559] pnp: PnP ACPI: disabled
10518 12:21:40.446517 <6>[ 0.671299] NET: Registered PF_INET protocol family
10519 12:21:40.456581 <6>[ 0.676906] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10520 12:21:40.467834 <6>[ 0.689130] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10521 12:21:40.477647 <6>[ 0.697948] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10522 12:21:40.484484 <6>[ 0.705914] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10523 12:21:40.494448 <6>[ 0.714614] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10524 12:21:40.501153 <6>[ 0.724325] TCP: Hash tables configured (established 65536 bind 65536)
10525 12:21:40.507417 <6>[ 0.731185] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10526 12:21:40.517087 <6>[ 0.738385] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10527 12:21:40.524144 <6>[ 0.746089] NET: Registered PF_UNIX/PF_LOCAL protocol family
10528 12:21:40.530627 <6>[ 0.752258] RPC: Registered named UNIX socket transport module.
10529 12:21:40.533752 <6>[ 0.758414] RPC: Registered udp transport module.
10530 12:21:40.540244 <6>[ 0.763348] RPC: Registered tcp transport module.
10531 12:21:40.547282 <6>[ 0.768281] RPC: Registered tcp NFSv4.1 backchannel transport module.
10532 12:21:40.550278 <6>[ 0.774949] PCI: CLS 0 bytes, default 64
10533 12:21:40.553161 <6>[ 0.779359] Unpacking initramfs...
10534 12:21:40.577628 <6>[ 0.798922] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10535 12:21:40.587598 <6>[ 0.807591] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10536 12:21:40.590820 <6>[ 0.816437] kvm [1]: IPA Size Limit: 40 bits
10537 12:21:40.597371 <6>[ 0.820966] kvm [1]: GICv3: no GICV resource entry
10538 12:21:40.600767 <6>[ 0.825987] kvm [1]: disabling GICv2 emulation
10539 12:21:40.607482 <6>[ 0.830672] kvm [1]: GIC system register CPU interface enabled
10540 12:21:40.611053 <6>[ 0.836840] kvm [1]: vgic interrupt IRQ18
10541 12:21:40.617367 <6>[ 0.841200] kvm [1]: VHE mode initialized successfully
10542 12:21:40.623779 <5>[ 0.847669] Initialise system trusted keyrings
10543 12:21:40.630367 <6>[ 0.852469] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10544 12:21:40.638294 <6>[ 0.862538] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10545 12:21:40.644868 <5>[ 0.868954] NFS: Registering the id_resolver key type
10546 12:21:40.647725 <5>[ 0.874265] Key type id_resolver registered
10547 12:21:40.654800 <5>[ 0.878679] Key type id_legacy registered
10548 12:21:40.661465 <6>[ 0.882962] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10549 12:21:40.667971 <6>[ 0.889884] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10550 12:21:40.674293 <6>[ 0.897584] 9p: Installing v9fs 9p2000 file system support
10551 12:21:40.711183 <5>[ 0.935707] Key type asymmetric registered
10552 12:21:40.714639 <5>[ 0.940037] Asymmetric key parser 'x509' registered
10553 12:21:40.724677 <6>[ 0.945171] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10554 12:21:40.728027 <6>[ 0.952787] io scheduler mq-deadline registered
10555 12:21:40.731359 <6>[ 0.957564] io scheduler kyber registered
10556 12:21:40.749795 <6>[ 0.974569] EINJ: ACPI disabled.
10557 12:21:40.781849 <4>[ 0.999935] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 12:21:40.792085 <4>[ 1.010540] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 12:21:40.806557 <6>[ 1.031065] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10560 12:21:40.814324 <6>[ 1.039003] printk: console [ttyS0] disabled
10561 12:21:40.842637 <6>[ 1.063646] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10562 12:21:40.848811 <6>[ 1.073119] printk: console [ttyS0] enabled
10563 12:21:40.852294 <6>[ 1.073119] printk: console [ttyS0] enabled
10564 12:21:40.859322 <6>[ 1.082013] printk: bootconsole [mtk8250] disabled
10565 12:21:40.862186 <6>[ 1.082013] printk: bootconsole [mtk8250] disabled
10566 12:21:40.868699 <6>[ 1.093026] SuperH (H)SCI(F) driver initialized
10567 12:21:40.872339 <6>[ 1.098295] msm_serial: driver initialized
10568 12:21:40.885921 <6>[ 1.107283] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10569 12:21:40.895911 <6>[ 1.115826] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10570 12:21:40.902995 <6>[ 1.124370] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10571 12:21:40.912769 <6>[ 1.132998] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10572 12:21:40.922488 <6>[ 1.141708] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10573 12:21:40.929140 <6>[ 1.150422] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10574 12:21:40.939366 <6>[ 1.158962] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10575 12:21:40.945658 <6>[ 1.167755] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10576 12:21:40.955349 <6>[ 1.176297] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10577 12:21:40.967096 <6>[ 1.191725] loop: module loaded
10578 12:21:40.973697 <6>[ 1.197596] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10579 12:21:40.996253 <4>[ 1.220850] mtk-pmic-keys: Failed to locate of_node [id: -1]
10580 12:21:41.003200 <6>[ 1.227637] megasas: 07.719.03.00-rc1
10581 12:21:41.012996 <6>[ 1.237329] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10582 12:21:41.021935 <6>[ 1.246134] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10583 12:21:41.038592 <6>[ 1.262835] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10584 12:21:41.094989 <6>[ 1.312861] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10585 12:21:42.584313 <6>[ 2.809080] Freeing initrd memory: 46408K
10586 12:21:42.594688 <6>[ 2.819579] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10587 12:21:42.606020 <6>[ 2.830686] tun: Universal TUN/TAP device driver, 1.6
10588 12:21:42.609053 <6>[ 2.836756] thunder_xcv, ver 1.0
10589 12:21:42.612589 <6>[ 2.840260] thunder_bgx, ver 1.0
10590 12:21:42.616049 <6>[ 2.843753] nicpf, ver 1.0
10591 12:21:42.626215 <6>[ 2.847777] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10592 12:21:42.629868 <6>[ 2.855255] hns3: Copyright (c) 2017 Huawei Corporation.
10593 12:21:42.636444 <6>[ 2.860842] hclge is initializing
10594 12:21:42.639355 <6>[ 2.864421] e1000: Intel(R) PRO/1000 Network Driver
10595 12:21:42.646077 <6>[ 2.869550] e1000: Copyright (c) 1999-2006 Intel Corporation.
10596 12:21:42.649343 <6>[ 2.875562] e1000e: Intel(R) PRO/1000 Network Driver
10597 12:21:42.655933 <6>[ 2.880778] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10598 12:21:42.662532 <6>[ 2.886967] igb: Intel(R) Gigabit Ethernet Network Driver
10599 12:21:42.669291 <6>[ 2.892617] igb: Copyright (c) 2007-2014 Intel Corporation.
10600 12:21:42.675750 <6>[ 2.898452] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10601 12:21:42.682549 <6>[ 2.904971] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10602 12:21:42.686202 <6>[ 2.911433] sky2: driver version 1.30
10603 12:21:42.692521 <6>[ 2.916436] VFIO - User Level meta-driver version: 0.3
10604 12:21:42.700497 <6>[ 2.924703] usbcore: registered new interface driver usb-storage
10605 12:21:42.706755 <6>[ 2.931147] usbcore: registered new device driver onboard-usb-hub
10606 12:21:42.715564 <6>[ 2.940291] mt6397-rtc mt6359-rtc: registered as rtc0
10607 12:21:42.725795 <6>[ 2.945774] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:21:42 UTC (1698409302)
10608 12:21:42.728584 <6>[ 2.955363] i2c_dev: i2c /dev entries driver
10609 12:21:42.745632 <6>[ 2.967220] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10610 12:21:42.765286 <6>[ 2.990218] cpu cpu0: EM: created perf domain
10611 12:21:42.768898 <6>[ 2.995157] cpu cpu4: EM: created perf domain
10612 12:21:42.776380 <6>[ 3.000732] sdhci: Secure Digital Host Controller Interface driver
10613 12:21:42.782740 <6>[ 3.007164] sdhci: Copyright(c) Pierre Ossman
10614 12:21:42.789388 <6>[ 3.012125] Synopsys Designware Multimedia Card Interface Driver
10615 12:21:42.795784 <6>[ 3.018753] sdhci-pltfm: SDHCI platform and OF driver helper
10616 12:21:42.799254 <6>[ 3.018764] mmc0: CQHCI version 5.10
10617 12:21:42.805770 <6>[ 3.029049] ledtrig-cpu: registered to indicate activity on CPUs
10618 12:21:42.812412 <6>[ 3.036001] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10619 12:21:42.819510 <6>[ 3.043069] usbcore: registered new interface driver usbhid
10620 12:21:42.822144 <6>[ 3.048895] usbhid: USB HID core driver
10621 12:21:42.828782 <6>[ 3.053095] spi_master spi0: will run message pump with realtime priority
10622 12:21:42.877746 <6>[ 3.095921] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10623 12:21:42.898520 <6>[ 3.112644] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10624 12:21:42.901375 <6>[ 3.126704] mmc0: Command Queue Engine enabled
10625 12:21:42.908497 <6>[ 3.128688] cros-ec-spi spi0.0: Chrome EC device registered
10626 12:21:42.915028 <6>[ 3.131466] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10627 12:21:42.918429 <6>[ 3.144525] mmcblk0: mmc0:0001 DA4128 116 GiB
10628 12:21:42.929237 <6>[ 3.150887] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10629 12:21:42.936146 <6>[ 3.158204] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10630 12:21:42.942931 <6>[ 3.161509] NET: Registered PF_PACKET protocol family
10631 12:21:42.945853 <6>[ 3.166992] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10632 12:21:42.952723 <6>[ 3.171537] 9pnet: Installing 9P2000 support
10633 12:21:42.956161 <6>[ 3.177269] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10634 12:21:42.962565 <5>[ 3.181212] Key type dns_resolver registered
10635 12:21:42.969093 <6>[ 3.186953] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10636 12:21:42.972569 <6>[ 3.191503] registered taskstats version 1
10637 12:21:42.975571 <5>[ 3.201822] Loading compiled-in X.509 certificates
10638 12:21:43.006789 <4>[ 3.224886] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10639 12:21:43.016987 <4>[ 3.235576] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10640 12:21:43.023528 <3>[ 3.246103] debugfs: File 'uA_load' in directory '/' already present!
10641 12:21:43.029987 <3>[ 3.252802] debugfs: File 'min_uV' in directory '/' already present!
10642 12:21:43.036589 <3>[ 3.259468] debugfs: File 'max_uV' in directory '/' already present!
10643 12:21:43.043239 <3>[ 3.266082] debugfs: File 'constraint_flags' in directory '/' already present!
10644 12:21:43.054261 <3>[ 3.275556] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10645 12:21:43.064674 <6>[ 3.289255] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10646 12:21:43.071603 <6>[ 3.296045] xhci-mtk 11200000.usb: xHCI Host Controller
10647 12:21:43.077593 <6>[ 3.301551] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10648 12:21:43.088165 <6>[ 3.309401] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10649 12:21:43.094619 <6>[ 3.318838] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10650 12:21:43.101172 <6>[ 3.324908] xhci-mtk 11200000.usb: xHCI Host Controller
10651 12:21:43.107735 <6>[ 3.330391] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10652 12:21:43.114249 <6>[ 3.338037] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10653 12:21:43.121388 <6>[ 3.345895] hub 1-0:1.0: USB hub found
10654 12:21:43.124793 <6>[ 3.349929] hub 1-0:1.0: 1 port detected
10655 12:21:43.134186 <6>[ 3.354205] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10656 12:21:43.137776 <6>[ 3.362977] hub 2-0:1.0: USB hub found
10657 12:21:43.140713 <6>[ 3.366994] hub 2-0:1.0: 1 port detected
10658 12:21:43.151092 <6>[ 3.375491] mtk-msdc 11f70000.mmc: Got CD GPIO
10659 12:21:43.161211 <6>[ 3.381798] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10660 12:21:43.167802 <6>[ 3.389832] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10661 12:21:43.177173 <4>[ 3.397799] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10662 12:21:43.184309 <6>[ 3.407334] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10663 12:21:43.194236 <6>[ 3.415432] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10664 12:21:43.200563 <6>[ 3.423432] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10665 12:21:43.210400 <6>[ 3.431364] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10666 12:21:43.216783 <6>[ 3.439182] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10667 12:21:43.226749 <6>[ 3.447011] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10668 12:21:43.236834 <6>[ 3.457454] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10669 12:21:43.243183 <6>[ 3.465832] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10670 12:21:43.253241 <6>[ 3.474173] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10671 12:21:43.259735 <6>[ 3.482524] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10672 12:21:43.269800 <6>[ 3.490863] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10673 12:21:43.276521 <6>[ 3.499215] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10674 12:21:43.286533 <6>[ 3.507554] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10675 12:21:43.293167 <6>[ 3.515909] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10676 12:21:43.302614 <6>[ 3.524248] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10677 12:21:43.312444 <6>[ 3.532597] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10678 12:21:43.319400 <6>[ 3.540939] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10679 12:21:43.329212 <6>[ 3.549278] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10680 12:21:43.335907 <6>[ 3.557617] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10681 12:21:43.345459 <6>[ 3.565955] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10682 12:21:43.352273 <6>[ 3.574293] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10683 12:21:43.358809 <6>[ 3.583047] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10684 12:21:43.365598 <6>[ 3.590210] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10685 12:21:43.372222 <6>[ 3.596980] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10686 12:21:43.382282 <6>[ 3.603738] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10687 12:21:43.389044 <6>[ 3.610670] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10688 12:21:43.395469 <6>[ 3.617525] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10689 12:21:43.405131 <6>[ 3.626656] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10690 12:21:43.415028 <6>[ 3.635777] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10691 12:21:43.425078 <6>[ 3.645111] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10692 12:21:43.434755 <6>[ 3.654669] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10693 12:21:43.444939 <6>[ 3.664139] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10694 12:21:43.451317 <6>[ 3.673259] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10695 12:21:43.461483 <6>[ 3.682729] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10696 12:21:43.471398 <6>[ 3.691849] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10697 12:21:43.481283 <6>[ 3.701145] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10698 12:21:43.490763 <6>[ 3.711306] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10699 12:21:43.501582 <6>[ 3.722927] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10700 12:21:43.557282 <6>[ 3.779006] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10701 12:21:43.711820 <6>[ 3.936766] hub 1-1:1.0: USB hub found
10702 12:21:43.715420 <6>[ 3.941298] hub 1-1:1.0: 4 ports detected
10703 12:21:43.837781 <6>[ 4.059280] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10704 12:21:43.863160 <6>[ 4.088009] hub 2-1:1.0: USB hub found
10705 12:21:43.866368 <6>[ 4.092452] hub 2-1:1.0: 3 ports detected
10706 12:21:44.037172 <6>[ 4.259024] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10707 12:21:44.170382 <6>[ 4.395249] hub 1-1.4:1.0: USB hub found
10708 12:21:44.173901 <6>[ 4.399959] hub 1-1.4:1.0: 2 ports detected
10709 12:21:44.249495 <6>[ 4.471264] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10710 12:21:44.469071 <6>[ 4.690992] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10711 12:21:44.661561 <6>[ 4.883048] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10712 12:21:55.786716 <6>[ 16.016052] ALSA device list:
10713 12:21:55.793226 <6>[ 16.019340] No soundcards found.
10714 12:21:55.801534 <6>[ 16.027294] Freeing unused kernel memory: 8384K
10715 12:21:55.804475 <6>[ 16.032283] Run /init as init process
10716 12:21:55.854207 <6>[ 16.080031] NET: Registered PF_INET6 protocol family
10717 12:21:55.861122 <6>[ 16.086303] Segment Routing with IPv6
10718 12:21:55.863810 <6>[ 16.090243] In-situ OAM (IOAM) with IPv6
10719 12:21:55.897432 <30>[ 16.103849] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10720 12:21:55.900431 <30>[ 16.127614] systemd[1]: Detected architecture arm64.
10721 12:21:55.900550
10722 12:21:55.907031 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10723 12:21:55.907140
10724 12:21:55.921009 <30>[ 16.146949] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10725 12:21:56.075300 <30>[ 16.297937] systemd[1]: Queued start job for default target Graphical Interface.
10726 12:21:56.125164 <30>[ 16.351551] systemd[1]: Created slice system-getty.slice.
10727 12:21:56.131790 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10728 12:21:56.149504 <30>[ 16.375676] systemd[1]: Created slice system-modprobe.slice.
10729 12:21:56.155993 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10730 12:21:56.173367 <30>[ 16.399653] systemd[1]: Created slice system-serial\x2dgetty.slice.
10731 12:21:56.183724 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10732 12:21:57.449290 <30>[ 16.423589] systemd[1]: Created slice User and Session Slice.
10733 12:21:57.449450 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10734 12:21:57.449539 <30>[ 16.447748] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10735 12:21:57.449620 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10736 12:21:57.449684 <30>[ 16.475678] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10737 12:21:57.449756 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10738 12:21:57.449856 <30>[ 16.503504] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10739 12:21:57.449925 <30>[ 16.515755] systemd[1]: Reached target Local Encrypted Volumes.
10740 12:21:57.449985 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10741 12:21:57.450066 <30>[ 16.539554] systemd[1]: Reached target Paths.
10742 12:21:57.450125 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10743 12:21:57.450181 <30>[ 16.558991] systemd[1]: Reached target Remote File Systems.
10744 12:21:57.450241 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10745 12:21:57.450329 <30>[ 16.578978] systemd[1]: Reached target Slices.
10746 12:21:57.450389 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10747 12:21:57.450443 <30>[ 16.598994] systemd[1]: Reached target Swap.
10748 12:21:57.450497 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10749 12:21:57.450560 <30>[ 16.619479] systemd[1]: Listening on initctl Compatibility Named Pipe.
10750 12:21:57.450647 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10751 12:21:57.450733 <30>[ 16.643866] systemd[1]: Listening on Journal Audit Socket.
10752 12:21:57.450823 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10753 12:21:57.450908 <30>[ 16.668133] systemd[1]: Listening on Journal Socket (/dev/log).
10754 12:21:57.450997 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10755 12:21:57.451089 <30>[ 16.692165] systemd[1]: Listening on Journal Socket.
10756 12:21:57.451147 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10757 12:21:57.451202 <30>[ 16.711648] systemd[1]: Listening on Network Service Netlink Socket.
10758 12:21:57.451256 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10759 12:21:57.451309 <30>[ 16.736202] systemd[1]: Listening on udev Control Socket.
10760 12:21:57.451362 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10761 12:21:57.451421 <30>[ 16.760052] systemd[1]: Listening on udev Kernel Socket.
10762 12:21:57.451476 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10763 12:21:57.451529 <30>[ 16.807159] systemd[1]: Mounting Huge Pages File System...
10764 12:21:57.451582 Mounting [0;1;39mHuge Pages File System[0m...
10765 12:21:57.451635 <30>[ 16.828715] systemd[1]: Mounting POSIX Message Queue File System...
10766 12:21:57.451694 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10767 12:21:57.451754 <30>[ 16.853429] systemd[1]: Mounting Kernel Debug File System...
10768 12:21:57.451813 Mounting [0;1;39mKernel Debug File System[0m...
10769 12:21:57.451868 <30>[ 16.875432] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10770 12:21:57.451922 <30>[ 16.888153] systemd[1]: Starting Create list of static device nodes for the current kernel...
10771 12:21:57.451976 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10772 12:21:57.452031 <30>[ 16.919813] systemd[1]: Starting Load Kernel Module configfs...
10773 12:21:57.452084 Starting [0;1;39mLoad Kernel Module configfs[0m...
10774 12:21:57.452137 <30>[ 16.943532] systemd[1]: Starting Load Kernel Module drm...
10775 12:21:57.452195 Starting [0;1;39mLoad Kernel Module drm[0m...
10776 12:21:57.452250 <30>[ 16.963358] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10777 12:21:57.452304 <30>[ 17.011911] systemd[1]: Starting Journal Service...
10778 12:21:57.452357 Starting [0;1;39mJournal Service[0m...
10779 12:21:57.452410 <30>[ 17.035844] systemd[1]: Starting Load Kernel Modules...
10780 12:21:57.452462 Starting [0;1;39mLoad Kernel Modules[0m...
10781 12:21:57.452515 <30>[ 17.087813] systemd[1]: Starting Remount Root and Kernel File Systems...
10782 12:21:57.452571 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10783 12:21:57.452627 <30>[ 17.113990] systemd[1]: Starting Coldplug All udev Devices...
10784 12:21:57.452680 Starting [0;1;39mColdplug All udev Devices[0m...
10785 12:21:57.452733 <30>[ 17.137904] systemd[1]: Started Journal Service.
10786 12:21:57.452785 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10787 12:21:57.452839 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10788 12:21:57.452891 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10789 12:21:57.453222 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10790 12:21:57.453294 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10791 12:21:57.453352 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10792 12:21:57.453407 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10793 12:21:57.453478 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10794 12:21:57.453566 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10795 12:21:57.453655 See 'systemctl status systemd-remount-fs.service' for details.
10796 12:21:57.453742 Mounting [0;1;39mKernel Configuration File System[0m...
10797 12:21:57.453830 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10798 12:21:57.453915 <46>[ 17.379647] systemd-journald[186]: Received client request to flush runtime journal.
10799 12:21:57.454000 Starting [0;1;39mLoad/Save Random Seed[0m...
10800 12:21:57.454083 Starting [0;1;39mApply Kernel Variables[0m...
10801 12:21:57.454195 Starting [0;1;39mCreate System Users[0m...
10802 12:21:57.454278 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10803 12:21:57.454362 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10804 12:21:57.454436 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10805 12:21:57.454491 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10806 12:21:57.454544 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10807 12:21:57.454602 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10808 12:21:57.454657 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10809 12:21:57.454710 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10810 12:21:57.454763 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10811 12:21:57.454815 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10812 12:21:57.477816 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10813 12:21:57.502705 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10814 12:21:57.528584 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10815 12:21:57.551470 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10816 12:21:57.591403 Starting [0;1;39mNetwork Service[0m...
10817 12:21:57.616201 Starting [0;1;39mNetwork Time Synchronization[0m...
10818 12:21:57.641149 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10819 12:21:57.660886 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10820 12:21:57.696466 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10821 12:21:57.717522 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10822 12:21:57.735019 <3>[ 17.957610] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10823 12:21:57.744725 <3>[ 17.966080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10824 12:21:57.751149 <6>[ 17.971481] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10825 12:21:57.757368 <3>[ 17.974292] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10826 12:21:57.767631 [[0;32m OK [<3>[ 17.990896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 12:21:57.777490 0m] Created slic<6>[ 17.994860] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10828 12:21:57.787512 e [0;1;39msyste<3>[ 17.999337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 12:21:57.794189 <3>[ 17.999345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10830 12:21:57.804175 m-systemd\x2dbac<3>[ 17.999358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 12:21:57.813514 klight.slice[0m<3>[ 17.999368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10832 12:21:57.813601 .
10833 12:21:57.820723 <6>[ 18.000459] remoteproc remoteproc0: scp is available
10834 12:21:57.827175 <6>[ 18.008413] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10835 12:21:57.833664 <6>[ 18.019881] remoteproc remoteproc0: powering up scp
10836 12:21:57.840217 <6>[ 18.025933] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10837 12:21:57.850355 <6>[ 18.035416] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10838 12:21:57.856859 <3>[ 18.036288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 12:21:57.863410 <6>[ 18.037184] mc: Linux media interface: v0.10
10840 12:21:57.870232 <3>[ 18.055328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 12:21:57.876714 <6>[ 18.059039] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10842 12:21:57.882958 <6>[ 18.063722] videodev: Linux video capture interface: v2.00
10843 12:21:57.890132 <3>[ 18.064203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10844 12:21:57.899520 <3>[ 18.121428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10845 12:21:57.906072 <3>[ 18.124854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 12:21:57.913156 <4>[ 18.125027] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10847 12:21:57.922721 <4>[ 18.132107] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10848 12:21:57.929549 <3>[ 18.138014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 12:21:57.936218 [[0;32m OK [<6>[ 18.154207] usbcore: registered new interface driver r8152
10850 12:21:57.945991 0m] Reached targ<3>[ 18.160630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10851 12:21:57.955755 et [0;1;39mSyst<3>[ 18.160646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10852 12:21:57.962914 <3>[ 18.160651] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10853 12:21:57.972828 <6>[ 18.162652] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10854 12:21:57.979252 em Time Set[0m.<3>[ 18.169874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10855 12:21:57.979329
10856 12:21:57.989179 <6>[ 18.187063] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10857 12:21:57.995805 <6>[ 18.198162] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10858 12:21:58.002433 <6>[ 18.198205] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10859 12:21:58.008957 <6>[ 18.198215] remoteproc remoteproc0: remote processor scp is now up
10860 12:21:58.015392 <6>[ 18.202629] pci_bus 0000:00: root bus resource [bus 00-ff]
10861 12:21:58.025401 <4>[ 18.230198] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10862 12:21:58.028647 <4>[ 18.230198] Fallback method does not support PEC.
10863 12:21:58.039023 <6>[ 18.235292] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10864 12:21:58.048198 <6>[ 18.268737] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10865 12:21:58.058145 <6>[ 18.272940] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10866 12:21:58.064417 <6>[ 18.279062] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10867 12:21:58.074321 <6>[ 18.292523] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10868 12:21:58.081471 [[0;32m OK [<6>[ 18.294712] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10869 12:21:58.088018 0m] Reached target [0;1;39mSyst<6>[ 18.315381] pci 0000:00:00.0: supports D1 D2
10870 12:21:58.098023 em Time Synchron<6>[ 18.320973] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10871 12:21:58.104987 <6>[ 18.329075] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10872 12:21:58.105070 ized[0m.
10873 12:21:58.114503 <6>[ 18.329613] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10874 12:21:58.124873 <3>[ 18.334395] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 12:21:58.131387 <6>[ 18.341802] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10876 12:21:58.141383 <6>[ 18.348246] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10877 12:21:58.148112 <6>[ 18.355396] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10878 12:21:58.154765 <6>[ 18.355426] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10879 12:21:58.161351 <6>[ 18.355452] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10880 12:21:58.171068 <6>[ 18.355470] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10881 12:21:58.177382 <6>[ 18.376547] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10882 12:21:58.181072 <6>[ 18.378515] pci 0000:01:00.0: supports D1 D2
10883 12:21:58.190526 <6>[ 18.378612] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10884 12:21:58.193782 <6>[ 18.379325] usbcore: registered new interface driver cdc_ether
10885 12:21:58.204327 <4>[ 18.381481] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10886 12:21:58.214078 <4>[ 18.381501] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10887 12:21:58.223774 <6>[ 18.395064] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10888 12:21:58.230260 <6>[ 18.395435] Bluetooth: Core ver 2.22
10889 12:21:58.233987 <6>[ 18.395516] NET: Registered PF_BLUETOOTH protocol family
10890 12:21:58.240223 <6>[ 18.395518] Bluetooth: HCI device and connection manager initialized
10891 12:21:58.247238 <6>[ 18.395539] Bluetooth: HCI socket layer initialized
10892 12:21:58.250720 <6>[ 18.395545] Bluetooth: L2CAP socket layer initialized
10893 12:21:58.257211 <6>[ 18.395560] Bluetooth: SCO socket layer initialized
10894 12:21:58.264397 <6>[ 18.396173] usbcore: registered new interface driver r8153_ecm
10895 12:21:58.271222 <6>[ 18.400716] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10896 12:21:58.278018 <6>[ 18.409903] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10897 12:21:58.284627 <6>[ 18.410792] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10898 12:21:58.291828 <6>[ 18.410820] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10899 12:21:58.298433 <6>[ 18.410824] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10900 12:21:58.308164 <6>[ 18.410832] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10901 12:21:58.315009 <6>[ 18.410845] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10902 12:21:58.325044 <6>[ 18.410858] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10903 12:21:58.328578 <6>[ 18.410870] pci 0000:00:00.0: PCI bridge to [bus 01]
10904 12:21:58.338648 <6>[ 18.410874] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10905 12:21:58.342302 <6>[ 18.410996] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10906 12:21:58.348874 <6>[ 18.411486] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10907 12:21:58.355419 <6>[ 18.412010] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10908 12:21:58.361855 <6>[ 18.414501] usbcore: registered new interface driver uvcvideo
10909 12:21:58.368556 <5>[ 18.431536] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10910 12:21:58.375381 <6>[ 18.457638] usbcore: registered new interface driver btusb
10911 12:21:58.385379 <4>[ 18.458322] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10912 12:21:58.392466 <3>[ 18.458337] Bluetooth: hci0: Failed to load firmware file (-2)
10913 12:21:58.399029 <3>[ 18.458341] Bluetooth: hci0: Failed to set up firmware (-2)
10914 12:21:58.409412 <4>[ 18.458345] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10915 12:21:58.415949 <5>[ 18.472819] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10916 12:21:58.419193 <6>[ 18.474924] r8152 2-1.3:1.0 eth0: v1.12.13
10917 12:21:58.429755 <4>[ 18.478191] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10918 12:21:58.435468 <6>[ 18.495195] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10919 12:21:58.439149 <6>[ 18.501616] cfg80211: failed to load regulatory.db
10920 12:21:58.448618 <3>[ 18.513364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 12:21:58.455593 <3>[ 18.514064] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10922 12:21:58.465656 <3>[ 18.526105] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 12:21:58.472667 <3>[ 18.547595] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10924 12:21:58.482408 <3>[ 18.572484] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 12:21:58.489287 <6>[ 18.588818] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10926 12:21:58.499137 <3>[ 18.612640] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:21:58.505669 <6>[ 18.617363] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10928 12:21:58.512376 <3>[ 18.645083] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 12:21:58.518914 <6>[ 18.666717] mt7921e 0000:01:00.0: ASIC revision: 79610010
10930 12:21:58.528733 <3>[ 18.693022] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 12:21:58.535029 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10932 12:21:58.561783 <3>[ 18.784983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 12:21:58.577977 <4>[ 18.798052] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 12:21:58.592440 Starting [0;1;39mNetwork Name Resolution[0m...
10935 12:21:58.609713 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10936 12:21:58.628763 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10937 12:21:58.699567 <4>[ 18.919433] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10938 12:21:58.718213 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10939 12:21:58.821242 <4>[ 19.041267] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10940 12:21:58.856994 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10941 12:21:58.872530 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10942 12:21:58.892155 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10943 12:21:58.904521 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10944 12:21:58.924051 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10945 12:21:58.941332 <4>[ 19.161140] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10946 12:21:58.951119 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10947 12:21:58.964770 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10948 12:21:58.984709 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10949 12:21:58.996942 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10950 12:21:59.012800 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10951 12:21:59.032263 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10952 12:21:59.061593 <4>[ 19.281731] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10953 12:21:59.089788 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10954 12:21:59.119027 Starting [0;1;39mUser Login Management[0m...
10955 12:21:59.137606 Starting [0;1;39mPermit User Sessions[0m...
10956 12:21:59.156502 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10957 12:21:59.185599 <4>[ 19.405617] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10958 12:21:59.213509 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10959 12:21:59.237283 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10960 12:21:59.256998 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10961 12:21:59.281857 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10962 12:21:59.307112 <4>[ 19.526841] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10963 12:21:59.313281 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10964 12:21:59.323966 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10965 12:21:59.343320 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10966 12:21:59.361814 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10967 12:21:59.418612 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10968 12:21:59.431381 <4>[ 19.650694] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10969 12:21:59.461167 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10970 12:21:59.506996
10971 12:21:59.507151
10972 12:21:59.510030 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10973 12:21:59.510156
10974 12:21:59.513394 debian-bullseye-arm64 login: root (automatic login)
10975 12:21:59.513470
10976 12:21:59.513531
10977 12:21:59.550666 <4>[ 19.770499] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10978 12:21:59.557104 Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64
10979 12:21:59.557197
10980 12:21:59.563662 The programs included with the Debian GNU/Linux system are free software;
10981 12:21:59.570400 the exact distribution terms for each program are described in the
10982 12:21:59.576982 individual files in /usr/share/doc/*/copyright.
10983 12:21:59.577077
10984 12:21:59.580711 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10985 12:21:59.583682 permitted by applicable law.
10986 12:21:59.584319 Matched prompt #10: / #
10988 12:21:59.584630 Setting prompt string to ['/ #']
10989 12:21:59.584750 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10991 12:21:59.585048 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10992 12:21:59.585165 start: 2.2.6 expect-shell-connection (timeout 00:02:38) [common]
10993 12:21:59.585241 Setting prompt string to ['/ #']
10994 12:21:59.585302 Forcing a shell prompt, looking for ['/ #']
10996 12:21:59.635525 / #
10997 12:21:59.635665 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 12:21:59.635745 Waiting using forced prompt support (timeout 00:02:30)
10999 12:21:59.640614
11000 12:21:59.640894 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11001 12:21:59.640995 start: 2.2.7 export-device-env (timeout 00:02:38) [common]
11002 12:21:59.641091 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11003 12:21:59.641177 end: 2.2 depthcharge-retry (duration 00:02:22) [common]
11004 12:21:59.641262 end: 2 depthcharge-action (duration 00:02:22) [common]
11005 12:21:59.641349 start: 3 lava-test-retry (timeout 00:05:00) [common]
11006 12:21:59.641437 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11007 12:21:59.641512 Using namespace: common
11009 12:21:59.741859 / # #
11010 12:21:59.742035 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11011 12:21:59.742191 <4>[ 19.889529] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11012 12:21:59.747012 #
11013 12:21:59.747302 Using /lava-11893130
11015 12:21:59.847648 / # export SHELL=/bin/sh
11016 12:21:59.847836 <3>[ 20.007282] mt7921e 0000:01:00.0: hardware init failed
11017 12:21:59.852638 export SHELL=/bin/sh
11019 12:21:59.953237 / # . /lava-11893130/environment
11020 12:21:59.958477 . /lava-11893130/environment
11022 12:22:00.059100 / # /lava-11893130/bin/lava-test-runner /lava-11893130/0
11023 12:22:00.059272 Test shell timeout: 10s (minimum of the action and connection timeout)
11024 12:22:00.059621 <6>[ 20.213250] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307c7b: link becomes ready
11025 12:22:00.059699 <6>[ 20.221130] r8152 2-1.3:1.0 enx002432307c7b: carrier on
11026 12:22:00.064250 /lava-11893130/bin/lava-test-runner /lava-11893130/0
11027 12:22:00.107169 + export TESTRUN_ID=0_cros-ec
11028 12:22:00.107312 +<8>[ 20.316201] <LAVA_SIGNAL_STARTRUN 0_cros-ec 11893130_1.5.2.3.1>
11029 12:22:00.107419 cd /lava-11893130/0/tests/0_cros-ec
11030 12:22:00.107706 Received signal: <STARTRUN> 0_cros-ec 11893130_1.5.2.3.1
11031 12:22:00.107818 Starting test lava.0_cros-ec (11893130_1.5.2.3.1)
11032 12:22:00.107946 Skipping test definition patterns.
11033 12:22:00.108089 + cat uuid
11034 12:22:00.108194 + UUID=11893130_1.5.2.3.1
11035 12:22:00.108292 + set +x
11036 12:22:00.108381 + python3 -m cros.runners.lava_runner -v
11037 12:22:00.493996 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11038 12:22:00.500692 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11039 12:22:00.504318
11040 12:22:00.507815 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11042 12:22:00.510689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11043 12:22:00.517192 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11044 12:22:00.524265 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11045 12:22:00.527283
11046 12:22:00.533887 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8
11047 12:22:00.533979 Bad test result: ski<8
11048 12:22:00.537521 Received signal: <ENDRUN> 0_cros-ec 11893130_1.5.2.3.1
11049 12:22:00.537634 Ending use of test pattern.
11050 12:22:00.537726 Ending test lava.0_cros-ec (11893130_1.5.2.3.1), duration 0.43
11052 12:22:00.540315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=ski<8>[ 20.763234] <LAVA_SIGNAL_ENDRUN 0_cros-ec 11893130_1.5.2.3.1>
11053 12:22:00.540390 p>
11054 12:22:00.544027 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11055 12:22:00.550615 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11056 12:22:00.550764
11057 12:22:00.557000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11058 12:22:00.557247 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11060 12:22:00.563614 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11061 12:22:00.570452 Checks the standard ABI for the main Embedded Controller. ... ok
11062 12:22:00.570529
11063 12:22:00.573763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11064 12:22:00.574009 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11066 12:22:00.580395 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11067 12:22:00.587045 Checks the main Embedded controller character device. ... ok
11068 12:22:00.587138
11069 12:22:00.590650 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11071 12:22:00.593374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11072 12:22:00.596883 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11073 12:22:00.603226 Checks basic comunication with the main Embedded controller. ... ok
11074 12:22:00.603304
11075 12:22:00.610067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11076 12:22:00.610313 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11078 12:22:00.613395 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11079 12:22:00.623438 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11080 12:22:00.623533
11081 12:22:00.626759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11082 12:22:00.627013 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11084 12:22:00.633270 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11085 12:22:00.639730 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11086 12:22:00.639831
11087 12:22:00.646364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11088 12:22:00.646619 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11090 12:22:00.652688 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11091 12:22:00.659372 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11092 12:22:00.659473
11093 12:22:00.666419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11094 12:22:00.666687 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11096 12:22:00.669539 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11097 12:22:00.679221 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11098 12:22:00.679368
11099 12:22:00.682350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11100 12:22:00.682594 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11102 12:22:00.689264 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11103 12:22:00.699347 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11104 12:22:00.699427
11105 12:22:00.702252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11106 12:22:00.702509 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11108 12:22:00.709279 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11109 12:22:00.715556 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11110 12:22:00.715639
11111 12:22:00.722022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11112 12:22:00.722284 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11114 12:22:00.728640 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11115 12:22:00.735264 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11116 12:22:00.735345
11117 12:22:00.741753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11118 12:22:00.742007 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11120 12:22:00.748437 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11121 12:22:00.754930 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11122 12:22:00.755053
11123 12:22:00.761830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11124 12:22:00.762103 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11126 12:22:00.768638 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11127 12:22:00.775192 Check the cros battery ABI. ... skipped 'No BAT found'
11128 12:22:00.775273
11129 12:22:00.781790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11130 12:22:00.782042 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11132 12:22:00.787994 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11133 12:22:00.794771 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11134 12:22:00.794858
11135 12:22:00.801426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11136 12:22:00.801780 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11138 12:22:00.804900 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11139 12:22:00.814293 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11140 12:22:00.814374
11141 12:22:00.817696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11142 12:22:00.817950 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11144 12:22:00.824539 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11145 12:22:00.831110 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11146 12:22:00.831206
11147 12:22:00.837509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11148 12:22:00.837589
11149 12:22:00.837830 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11151 12:22:00.844160 ----------------------------------------------------------------------
11152 12:22:00.847684 Ran 18 tests in 0.008s
11153 12:22:00.847770
11154 12:22:00.847834 OK (skipped=15)
11155 12:22:00.850609 + set +x
11156 12:22:00.850754 <LAVA_TEST_RUNNER EXIT>
11157 12:22:00.851044 ok: lava_test_shell seems to have completed
11158 12:22:00.851291 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11159 12:22:00.851405 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11160 12:22:00.851506 end: 3 lava-test-retry (duration 00:00:01) [common]
11161 12:22:00.851610 start: 4 finalize (timeout 00:07:15) [common]
11162 12:22:00.851716 start: 4.1 power-off (timeout 00:00:30) [common]
11163 12:22:00.851867 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11164 12:22:00.931628 >> Command sent successfully.
11165 12:22:00.934570 Returned 0 in 0 seconds
11166 12:22:01.034946 end: 4.1 power-off (duration 00:00:00) [common]
11168 12:22:01.035378 start: 4.2 read-feedback (timeout 00:07:15) [common]
11169 12:22:01.035690 Listened to connection for namespace 'common' for up to 1s
11170 12:22:02.036603 Finalising connection for namespace 'common'
11171 12:22:02.036770 Disconnecting from shell: Finalise
11172 12:22:02.036870 / #
11173 12:22:02.137303 end: 4.2 read-feedback (duration 00:00:01) [common]
11174 12:22:02.137478 end: 4 finalize (duration 00:00:01) [common]
11175 12:22:02.137616 Cleaning after the job
11176 12:22:02.137728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/ramdisk
11177 12:22:02.144358 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/kernel
11178 12:22:02.152697 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/dtb
11179 12:22:02.152920 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893130/tftp-deploy-ggesbx_0/modules
11180 12:22:02.159990 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893130
11181 12:22:02.281097 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893130
11182 12:22:02.281282 Job finished correctly