Boot log: mt8192-asurada-spherion-r0

    1 12:22:39.823961  lava-dispatcher, installed at version: 2023.08
    2 12:22:39.824170  start: 0 validate
    3 12:22:39.824300  Start time: 2023-10-27 12:22:39.824292+00:00 (UTC)
    4 12:22:39.824420  Using caching service: 'http://localhost/cache/?uri=%s'
    5 12:22:39.824548  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
    6 12:22:40.099334  Using caching service: 'http://localhost/cache/?uri=%s'
    7 12:22:40.100137  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 12:22:40.361797  Using caching service: 'http://localhost/cache/?uri=%s'
    9 12:22:40.362636  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 12:22:40.634425  Using caching service: 'http://localhost/cache/?uri=%s'
   11 12:22:40.635235  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 12:22:40.903785  validate duration: 1.08
   14 12:22:40.904157  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 12:22:40.904257  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 12:22:40.904382  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 12:22:40.904509  Not decompressing ramdisk as can be used compressed.
   18 12:22:40.904592  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
   19 12:22:40.904657  saving as /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/ramdisk/rootfs.cpio.gz
   20 12:22:40.904719  total size: 43284872 (41 MB)
   21 12:22:40.910021  progress   0 % (0 MB)
   22 12:22:40.922266  progress   5 % (2 MB)
   23 12:22:40.934648  progress  10 % (4 MB)
   24 12:22:40.946305  progress  15 % (6 MB)
   25 12:22:40.957535  progress  20 % (8 MB)
   26 12:22:40.968994  progress  25 % (10 MB)
   27 12:22:40.980535  progress  30 % (12 MB)
   28 12:22:40.991853  progress  35 % (14 MB)
   29 12:22:41.003140  progress  40 % (16 MB)
   30 12:22:41.014492  progress  45 % (18 MB)
   31 12:22:41.025767  progress  50 % (20 MB)
   32 12:22:41.037038  progress  55 % (22 MB)
   33 12:22:41.048320  progress  60 % (24 MB)
   34 12:22:41.059642  progress  65 % (26 MB)
   35 12:22:41.070911  progress  70 % (28 MB)
   36 12:22:41.082223  progress  75 % (30 MB)
   37 12:22:41.093770  progress  80 % (33 MB)
   38 12:22:41.105013  progress  85 % (35 MB)
   39 12:22:41.116281  progress  90 % (37 MB)
   40 12:22:41.127333  progress  95 % (39 MB)
   41 12:22:41.138394  progress 100 % (41 MB)
   42 12:22:41.138647  41 MB downloaded in 0.23 s (176.46 MB/s)
   43 12:22:41.138807  end: 1.1.1 http-download (duration 00:00:00) [common]
   45 12:22:41.139054  end: 1.1 download-retry (duration 00:00:00) [common]
   46 12:22:41.139142  start: 1.2 download-retry (timeout 00:10:00) [common]
   47 12:22:41.139227  start: 1.2.1 http-download (timeout 00:10:00) [common]
   48 12:22:41.139366  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 12:22:41.139440  saving as /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/kernel/Image
   50 12:22:41.139501  total size: 49236480 (46 MB)
   51 12:22:41.139564  No compression specified
   52 12:22:41.140745  progress   0 % (0 MB)
   53 12:22:41.153587  progress   5 % (2 MB)
   54 12:22:41.166301  progress  10 % (4 MB)
   55 12:22:41.179155  progress  15 % (7 MB)
   56 12:22:41.192050  progress  20 % (9 MB)
   57 12:22:41.204979  progress  25 % (11 MB)
   58 12:22:41.217743  progress  30 % (14 MB)
   59 12:22:41.231006  progress  35 % (16 MB)
   60 12:22:41.244809  progress  40 % (18 MB)
   61 12:22:41.258285  progress  45 % (21 MB)
   62 12:22:41.272003  progress  50 % (23 MB)
   63 12:22:41.285302  progress  55 % (25 MB)
   64 12:22:41.298094  progress  60 % (28 MB)
   65 12:22:41.311021  progress  65 % (30 MB)
   66 12:22:41.323889  progress  70 % (32 MB)
   67 12:22:41.336692  progress  75 % (35 MB)
   68 12:22:41.349636  progress  80 % (37 MB)
   69 12:22:41.362327  progress  85 % (39 MB)
   70 12:22:41.375057  progress  90 % (42 MB)
   71 12:22:41.387711  progress  95 % (44 MB)
   72 12:22:41.400294  progress 100 % (46 MB)
   73 12:22:41.400494  46 MB downloaded in 0.26 s (179.91 MB/s)
   74 12:22:41.400644  end: 1.2.1 http-download (duration 00:00:00) [common]
   76 12:22:41.400879  end: 1.2 download-retry (duration 00:00:00) [common]
   77 12:22:41.400967  start: 1.3 download-retry (timeout 00:10:00) [common]
   78 12:22:41.401059  start: 1.3.1 http-download (timeout 00:10:00) [common]
   79 12:22:41.401202  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 12:22:41.401272  saving as /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/dtb/mt8192-asurada-spherion-r0.dtb
   81 12:22:41.401337  total size: 47278 (0 MB)
   82 12:22:41.401400  No compression specified
   83 12:22:41.402542  progress  69 % (0 MB)
   84 12:22:41.402817  progress 100 % (0 MB)
   85 12:22:41.402975  0 MB downloaded in 0.00 s (27.57 MB/s)
   86 12:22:41.403100  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 12:22:41.403321  end: 1.3 download-retry (duration 00:00:00) [common]
   89 12:22:41.403406  start: 1.4 download-retry (timeout 00:10:00) [common]
   90 12:22:41.403488  start: 1.4.1 http-download (timeout 00:10:00) [common]
   91 12:22:41.403604  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 12:22:41.403672  saving as /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/modules/modules.tar
   93 12:22:41.403739  total size: 8625084 (8 MB)
   94 12:22:41.403840  Using unxz to decompress xz
   95 12:22:41.407972  progress   0 % (0 MB)
   96 12:22:41.429484  progress   5 % (0 MB)
   97 12:22:41.451662  progress  10 % (0 MB)
   98 12:22:41.477437  progress  15 % (1 MB)
   99 12:22:41.502546  progress  20 % (1 MB)
  100 12:22:41.528143  progress  25 % (2 MB)
  101 12:22:41.554228  progress  30 % (2 MB)
  102 12:22:41.580801  progress  35 % (2 MB)
  103 12:22:41.605361  progress  40 % (3 MB)
  104 12:22:41.629168  progress  45 % (3 MB)
  105 12:22:41.655670  progress  50 % (4 MB)
  106 12:22:41.680857  progress  55 % (4 MB)
  107 12:22:41.705344  progress  60 % (4 MB)
  108 12:22:41.729379  progress  65 % (5 MB)
  109 12:22:41.754369  progress  70 % (5 MB)
  110 12:22:41.778874  progress  75 % (6 MB)
  111 12:22:41.805284  progress  80 % (6 MB)
  112 12:22:41.834473  progress  85 % (7 MB)
  113 12:22:41.861485  progress  90 % (7 MB)
  114 12:22:41.887739  progress  95 % (7 MB)
  115 12:22:41.911130  progress 100 % (8 MB)
  116 12:22:41.915895  8 MB downloaded in 0.51 s (16.06 MB/s)
  117 12:22:41.916155  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 12:22:41.916414  end: 1.4 download-retry (duration 00:00:01) [common]
  120 12:22:41.916508  start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
  121 12:22:41.916607  start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
  122 12:22:41.916690  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 12:22:41.916777  start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
  124 12:22:41.917005  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq
  125 12:22:41.917143  makedir: /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin
  126 12:22:41.917251  makedir: /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/tests
  127 12:22:41.917352  makedir: /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/results
  128 12:22:41.917470  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-add-keys
  129 12:22:41.917629  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-add-sources
  130 12:22:41.917763  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-background-process-start
  131 12:22:41.917894  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-background-process-stop
  132 12:22:41.918021  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-common-functions
  133 12:22:41.918147  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-echo-ipv4
  134 12:22:41.918273  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-install-packages
  135 12:22:41.918399  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-installed-packages
  136 12:22:41.918544  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-os-build
  137 12:22:41.918717  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-probe-channel
  138 12:22:41.918842  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-probe-ip
  139 12:22:41.918969  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-target-ip
  140 12:22:41.919094  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-target-mac
  141 12:22:41.919219  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-target-storage
  142 12:22:41.919349  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-test-case
  143 12:22:41.919475  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-test-event
  144 12:22:41.919599  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-test-feedback
  145 12:22:41.919729  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-test-raise
  146 12:22:41.919897  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-test-reference
  147 12:22:41.920023  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-test-runner
  148 12:22:41.920150  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-test-set
  149 12:22:41.920278  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-test-shell
  150 12:22:41.920408  Updating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-install-packages (oe)
  151 12:22:41.920566  Updating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/bin/lava-installed-packages (oe)
  152 12:22:41.920690  Creating /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/environment
  153 12:22:41.920790  LAVA metadata
  154 12:22:41.920866  - LAVA_JOB_ID=11893154
  155 12:22:41.920932  - LAVA_DISPATCHER_IP=192.168.201.1
  156 12:22:41.921033  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
  157 12:22:41.921099  skipped lava-vland-overlay
  158 12:22:41.921173  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 12:22:41.921255  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
  160 12:22:41.921318  skipped lava-multinode-overlay
  161 12:22:41.921397  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 12:22:41.921482  start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
  163 12:22:41.921557  Loading test definitions
  164 12:22:41.921647  start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
  165 12:22:41.921724  Using /lava-11893154 at stage 0
  166 12:22:41.922046  uuid=11893154_1.5.2.3.1 testdef=None
  167 12:22:41.922135  end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
  168 12:22:41.922222  start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
  169 12:22:41.922763  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  171 12:22:41.922981  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
  172 12:22:41.923607  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  174 12:22:41.923881  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
  175 12:22:41.924480  runner path: /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/0/tests/0_igt-gpu-panfrost test_uuid 11893154_1.5.2.3.1
  176 12:22:41.924641  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  178 12:22:41.924845  Creating lava-test-runner.conf files
  179 12:22:41.924908  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893154/lava-overlay-p214m0uq/lava-11893154/0 for stage 0
  180 12:22:41.924997  - 0_igt-gpu-panfrost
  181 12:22:41.925095  end: 1.5.2.3 test-definition (duration 00:00:00) [common]
  182 12:22:41.925184  start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
  183 12:22:41.931944  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  184 12:22:41.932051  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
  185 12:22:41.932136  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  186 12:22:41.932220  end: 1.5.2 lava-overlay (duration 00:00:00) [common]
  187 12:22:41.932306  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
  188 12:22:43.333944  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  189 12:22:43.334326  start: 1.5.4 extract-modules (timeout 00:09:58) [common]
  190 12:22:43.334439  extracting modules file /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893154/extract-overlay-ramdisk-ln8v8e_w/ramdisk
  191 12:22:43.566337  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  192 12:22:43.566502  start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
  193 12:22:43.566596  [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893154/compress-overlay-lcntpe59/overlay-1.5.2.4.tar.gz to ramdisk
  194 12:22:43.566667  [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893154/compress-overlay-lcntpe59/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893154/extract-overlay-ramdisk-ln8v8e_w/ramdisk
  195 12:22:43.573430  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  196 12:22:43.573545  start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
  197 12:22:43.573634  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  198 12:22:43.573727  start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
  199 12:22:43.573809  Building ramdisk /var/lib/lava/dispatcher/tmp/11893154/extract-overlay-ramdisk-ln8v8e_w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893154/extract-overlay-ramdisk-ln8v8e_w/ramdisk
  200 12:22:44.596974  >> 369948 blocks

  201 12:22:50.355434  rename /var/lib/lava/dispatcher/tmp/11893154/extract-overlay-ramdisk-ln8v8e_w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/ramdisk/ramdisk.cpio.gz
  202 12:22:50.355938  end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
  203 12:22:50.356068  start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
  204 12:22:50.356170  start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
  205 12:22:50.356277  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/kernel/Image'
  206 12:23:02.462963  Returned 0 in 12 seconds
  207 12:23:02.563991  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/kernel/image.itb
  208 12:23:03.394323  output: FIT description: Kernel Image image with one or more FDT blobs
  209 12:23:03.394699  output: Created:         Fri Oct 27 13:23:03 2023
  210 12:23:03.394773  output:  Image 0 (kernel-1)
  211 12:23:03.394842  output:   Description:  
  212 12:23:03.394906  output:   Created:      Fri Oct 27 13:23:03 2023
  213 12:23:03.394967  output:   Type:         Kernel Image
  214 12:23:03.395031  output:   Compression:  lzma compressed
  215 12:23:03.395091  output:   Data Size:    11047994 Bytes = 10789.06 KiB = 10.54 MiB
  216 12:23:03.395150  output:   Architecture: AArch64
  217 12:23:03.395211  output:   OS:           Linux
  218 12:23:03.395269  output:   Load Address: 0x00000000
  219 12:23:03.395326  output:   Entry Point:  0x00000000
  220 12:23:03.395383  output:   Hash algo:    crc32
  221 12:23:03.395439  output:   Hash value:   d33b93ae
  222 12:23:03.395495  output:  Image 1 (fdt-1)
  223 12:23:03.395551  output:   Description:  mt8192-asurada-spherion-r0
  224 12:23:03.395605  output:   Created:      Fri Oct 27 13:23:03 2023
  225 12:23:03.395690  output:   Type:         Flat Device Tree
  226 12:23:03.395814  output:   Compression:  uncompressed
  227 12:23:03.395872  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  228 12:23:03.395927  output:   Architecture: AArch64
  229 12:23:03.395981  output:   Hash algo:    crc32
  230 12:23:03.396034  output:   Hash value:   cc4352de
  231 12:23:03.396088  output:  Image 2 (ramdisk-1)
  232 12:23:03.396141  output:   Description:  unavailable
  233 12:23:03.396194  output:   Created:      Fri Oct 27 13:23:03 2023
  234 12:23:03.396248  output:   Type:         RAMDisk Image
  235 12:23:03.396300  output:   Compression:  Unknown Compression
  236 12:23:03.396353  output:   Data Size:    56428932 Bytes = 55106.38 KiB = 53.81 MiB
  237 12:23:03.396407  output:   Architecture: AArch64
  238 12:23:03.396459  output:   OS:           Linux
  239 12:23:03.396512  output:   Load Address: unavailable
  240 12:23:03.396565  output:   Entry Point:  unavailable
  241 12:23:03.396618  output:   Hash algo:    crc32
  242 12:23:03.396670  output:   Hash value:   8e887d5e
  243 12:23:03.396723  output:  Default Configuration: 'conf-1'
  244 12:23:03.396776  output:  Configuration 0 (conf-1)
  245 12:23:03.396829  output:   Description:  mt8192-asurada-spherion-r0
  246 12:23:03.396881  output:   Kernel:       kernel-1
  247 12:23:03.396934  output:   Init Ramdisk: ramdisk-1
  248 12:23:03.396986  output:   FDT:          fdt-1
  249 12:23:03.397038  output:   Loadables:    kernel-1
  250 12:23:03.397090  output: 
  251 12:23:03.397291  end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
  252 12:23:03.397395  end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
  253 12:23:03.397501  end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
  254 12:23:03.397595  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
  255 12:23:03.397675  No LXC device requested
  256 12:23:03.397754  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  257 12:23:03.397837  start: 1.7 deploy-device-env (timeout 00:09:38) [common]
  258 12:23:03.397915  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  259 12:23:03.397984  Checking files for TFTP limit of 4294967296 bytes.
  260 12:23:03.398491  end: 1 tftp-deploy (duration 00:00:22) [common]
  261 12:23:03.398592  start: 2 depthcharge-action (timeout 00:05:00) [common]
  262 12:23:03.398686  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  263 12:23:03.398809  substitutions:
  264 12:23:03.398875  - {DTB}: 11893154/tftp-deploy-7d4b6xp8/dtb/mt8192-asurada-spherion-r0.dtb
  265 12:23:03.398941  - {INITRD}: 11893154/tftp-deploy-7d4b6xp8/ramdisk/ramdisk.cpio.gz
  266 12:23:03.399000  - {KERNEL}: 11893154/tftp-deploy-7d4b6xp8/kernel/Image
  267 12:23:03.399057  - {LAVA_MAC}: None
  268 12:23:03.399113  - {PRESEED_CONFIG}: None
  269 12:23:03.399167  - {PRESEED_LOCAL}: None
  270 12:23:03.399222  - {RAMDISK}: 11893154/tftp-deploy-7d4b6xp8/ramdisk/ramdisk.cpio.gz
  271 12:23:03.399277  - {ROOT_PART}: None
  272 12:23:03.399331  - {ROOT}: None
  273 12:23:03.399385  - {SERVER_IP}: 192.168.201.1
  274 12:23:03.399439  - {TEE}: None
  275 12:23:03.399492  Parsed boot commands:
  276 12:23:03.399545  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  277 12:23:03.399732  Parsed boot commands: tftpboot 192.168.201.1 11893154/tftp-deploy-7d4b6xp8/kernel/image.itb 11893154/tftp-deploy-7d4b6xp8/kernel/cmdline 
  278 12:23:03.399822  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  279 12:23:03.399907  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  280 12:23:03.400000  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  281 12:23:03.400094  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  282 12:23:03.400164  Not connected, no need to disconnect.
  283 12:23:03.400238  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  284 12:23:03.400320  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  285 12:23:03.400387  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
  286 12:23:03.404319  Setting prompt string to ['lava-test: # ']
  287 12:23:03.404685  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  288 12:23:03.404795  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  289 12:23:03.404892  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  290 12:23:03.404985  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  291 12:23:03.405185  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
  292 12:23:08.558520  >> Command sent successfully.

  293 12:23:08.569018  Returned 0 in 5 seconds
  294 12:23:08.670190  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  296 12:23:08.671582  end: 2.2.2 reset-device (duration 00:00:05) [common]
  297 12:23:08.672130  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  298 12:23:08.672579  Setting prompt string to 'Starting depthcharge on Spherion...'
  299 12:23:08.672919  Changing prompt to 'Starting depthcharge on Spherion...'
  300 12:23:08.673280  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  301 12:23:08.674488  [Enter `^Ec?' for help]

  302 12:23:08.836825  

  303 12:23:08.837369  

  304 12:23:08.837740  F0: 102B 0000

  305 12:23:08.838075  

  306 12:23:08.838396  F3: 1001 0000 [0200]

  307 12:23:08.838724  

  308 12:23:08.840456  F3: 1001 0000

  309 12:23:08.840882  

  310 12:23:08.841265  F7: 102D 0000

  311 12:23:08.841673  

  312 12:23:08.842034  F1: 0000 0000

  313 12:23:08.844700  

  314 12:23:08.845319  V0: 0000 0000 [0001]

  315 12:23:08.845752  

  316 12:23:08.846080  00: 0007 8000

  317 12:23:08.846395  

  318 12:23:08.847999  01: 0000 0000

  319 12:23:08.848515  

  320 12:23:08.848896  BP: 0C00 0209 [0000]

  321 12:23:08.849224  

  322 12:23:08.852141  G0: 1182 0000

  323 12:23:08.852581  

  324 12:23:08.852927  EC: 0000 0021 [4000]

  325 12:23:08.853242  

  326 12:23:08.855307  S7: 0000 0000 [0000]

  327 12:23:08.855758  

  328 12:23:08.856231  CC: 0000 0000 [0001]

  329 12:23:08.856745  

  330 12:23:08.858215  T0: 0000 0040 [010F]

  331 12:23:08.858586  

  332 12:23:08.858900  Jump to BL

  333 12:23:08.859247  

  334 12:23:08.883545  

  335 12:23:08.884197  

  336 12:23:08.884545  

  337 12:23:08.890843  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  338 12:23:08.894453  ARM64: Exception handlers installed.

  339 12:23:08.898164  ARM64: Testing exception

  340 12:23:08.901341  ARM64: Done test exception

  341 12:23:08.908000  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  342 12:23:08.918805  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  343 12:23:08.925879  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  344 12:23:08.936694  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  345 12:23:08.943109  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  346 12:23:08.950036  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  347 12:23:08.960063  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  348 12:23:08.967080  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  349 12:23:08.986289  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  350 12:23:08.989398  WDT: Last reset was cold boot

  351 12:23:08.992707  SPI1(PAD0) initialized at 2873684 Hz

  352 12:23:08.996499  SPI5(PAD0) initialized at 992727 Hz

  353 12:23:08.999565  VBOOT: Loading verstage.

  354 12:23:09.006658  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  355 12:23:09.009872  FMAP: Found "FLASH" version 1.1 at 0x20000.

  356 12:23:09.012737  FMAP: base = 0x0 size = 0x800000 #areas = 25

  357 12:23:09.016207  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  358 12:23:09.023983  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  359 12:23:09.030375  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  360 12:23:09.041151  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  361 12:23:09.041737  

  362 12:23:09.042134  

  363 12:23:09.052088  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  364 12:23:09.054854  ARM64: Exception handlers installed.

  365 12:23:09.057963  ARM64: Testing exception

  366 12:23:09.058587  ARM64: Done test exception

  367 12:23:09.065079  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  368 12:23:09.067844  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  369 12:23:09.082491  Probing TPM: . done!

  370 12:23:09.083055  TPM ready after 0 ms

  371 12:23:09.089633  Connected to device vid:did:rid of 1ae0:0028:00

  372 12:23:09.099087  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

  373 12:23:09.137101  Initialized TPM device CR50 revision 0

  374 12:23:09.149487  tlcl_send_startup: Startup return code is 0

  375 12:23:09.150052  TPM: setup succeeded

  376 12:23:09.160485  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  377 12:23:09.169334  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  378 12:23:09.176026  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  379 12:23:09.188199  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  380 12:23:09.191392  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  381 12:23:09.194969  in-header: 03 07 00 00 08 00 00 00 

  382 12:23:09.198008  in-data: aa e4 47 04 13 02 00 00 

  383 12:23:09.201778  Chrome EC: UHEPI supported

  384 12:23:09.208035  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  385 12:23:09.211462  in-header: 03 ad 00 00 08 00 00 00 

  386 12:23:09.215563  in-data: 00 20 20 08 00 00 00 00 

  387 12:23:09.216248  Phase 1

  388 12:23:09.218355  FMAP: area GBB found @ 3f5000 (12032 bytes)

  389 12:23:09.224805  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  390 12:23:09.231196  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  391 12:23:09.234824  Recovery requested (1009000e)

  392 12:23:09.239206  TPM: Extending digest for VBOOT: boot mode into PCR 0

  393 12:23:09.247449  tlcl_extend: response is 0

  394 12:23:09.255397  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  395 12:23:09.260661  tlcl_extend: response is 0

  396 12:23:09.267323  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  397 12:23:09.288007  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  398 12:23:09.294503  BS: bootblock times (exec / console): total (unknown) / 148 ms

  399 12:23:09.295077  

  400 12:23:09.295452  

  401 12:23:09.304602  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  402 12:23:09.308163  ARM64: Exception handlers installed.

  403 12:23:09.308638  ARM64: Testing exception

  404 12:23:09.311808  ARM64: Done test exception

  405 12:23:09.333068  pmic_efuse_setting: Set efuses in 11 msecs

  406 12:23:09.336635  pmwrap_interface_init: Select PMIF_VLD_RDY

  407 12:23:09.343401  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  408 12:23:09.346975  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  409 12:23:09.350574  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  410 12:23:09.356930  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  411 12:23:09.361068  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  412 12:23:09.367300  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  413 12:23:09.370881  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  414 12:23:09.377272  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  415 12:23:09.380590  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  416 12:23:09.384116  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  417 12:23:09.390666  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  418 12:23:09.393983  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  419 12:23:09.400359  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  420 12:23:09.406745  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  421 12:23:09.410425  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  422 12:23:09.416802  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  423 12:23:09.424015  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  424 12:23:09.426928  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  425 12:23:09.433487  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  426 12:23:09.440305  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  427 12:23:09.443684  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  428 12:23:09.450716  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  429 12:23:09.454610  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  430 12:23:09.462158  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  431 12:23:09.465406  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  432 12:23:09.471883  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  433 12:23:09.478534  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  434 12:23:09.482630  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  435 12:23:09.489100  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  436 12:23:09.492435  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  437 12:23:09.495837  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  438 12:23:09.502408  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  439 12:23:09.506282  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  440 12:23:09.512870  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  441 12:23:09.515636  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  442 12:23:09.522551  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  443 12:23:09.525527  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  444 12:23:09.532228  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  445 12:23:09.535515  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  446 12:23:09.539446  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  447 12:23:09.546773  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  448 12:23:09.550038  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  449 12:23:09.553531  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  450 12:23:09.560208  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  451 12:23:09.564104  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  452 12:23:09.566908  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  453 12:23:09.569837  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  454 12:23:09.576612  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  455 12:23:09.580100  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  456 12:23:09.583340  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  457 12:23:09.586629  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  458 12:23:09.597086  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  459 12:23:09.603444  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  460 12:23:09.610367  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  461 12:23:09.616442  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  462 12:23:09.627029  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  463 12:23:09.629777  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  464 12:23:09.633034  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  465 12:23:09.640520  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  466 12:23:09.646360  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2a

  467 12:23:09.653279  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  468 12:23:09.656382  [RTC]rtc_osc_init,62: osc32con val = 0xde6c

  469 12:23:09.659758  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  470 12:23:09.670625  [RTC]rtc_get_frequency_meter,154: input=15, output=835

  471 12:23:09.680564  [RTC]rtc_get_frequency_meter,154: input=7, output=709

  472 12:23:09.689478  [RTC]rtc_get_frequency_meter,154: input=11, output=772

  473 12:23:09.699523  [RTC]rtc_get_frequency_meter,154: input=13, output=803

  474 12:23:09.708186  [RTC]rtc_get_frequency_meter,154: input=12, output=787

  475 12:23:09.718117  [RTC]rtc_get_frequency_meter,154: input=12, output=788

  476 12:23:09.727305  [RTC]rtc_get_frequency_meter,154: input=13, output=803

  477 12:23:09.730605  [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13

  478 12:23:09.738214  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c

  479 12:23:09.741358  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  480 12:23:09.744242  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  481 12:23:09.751218  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  482 12:23:09.754658  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  483 12:23:09.757961  ADC[4]: Raw value=901922 ID=7

  484 12:23:09.758549  ADC[3]: Raw value=213652 ID=1

  485 12:23:09.761449  RAM Code: 0x71

  486 12:23:09.764229  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  487 12:23:09.770931  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  488 12:23:09.778139  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  489 12:23:09.784657  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  490 12:23:09.787529  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  491 12:23:09.790623  in-header: 03 07 00 00 08 00 00 00 

  492 12:23:09.794383  in-data: aa e4 47 04 13 02 00 00 

  493 12:23:09.797357  Chrome EC: UHEPI supported

  494 12:23:09.804409  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  495 12:23:09.807422  in-header: 03 dd 00 00 08 00 00 00 

  496 12:23:09.810974  in-data: 90 20 60 08 00 00 00 00 

  497 12:23:09.814118  MRC: failed to locate region type 0.

  498 12:23:09.820820  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  499 12:23:09.824161  DRAM-K: Running full calibration

  500 12:23:09.830805  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  501 12:23:09.831234  header.status = 0x0

  502 12:23:09.833987  header.version = 0x6 (expected: 0x6)

  503 12:23:09.837454  header.size = 0xd00 (expected: 0xd00)

  504 12:23:09.840526  header.flags = 0x0

  505 12:23:09.847856  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  506 12:23:09.864236  read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps

  507 12:23:09.871077  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  508 12:23:09.874174  dram_init: ddr_geometry: 2

  509 12:23:09.877389  [EMI] MDL number = 2

  510 12:23:09.877816  [EMI] Get MDL freq = 0

  511 12:23:09.881301  dram_init: ddr_type: 0

  512 12:23:09.881729  is_discrete_lpddr4: 1

  513 12:23:09.884559  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  514 12:23:09.884985  

  515 12:23:09.885321  

  516 12:23:09.887476  [Bian_co] ETT version 0.0.0.1

  517 12:23:09.894665   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  518 12:23:09.895094  

  519 12:23:09.897698  dramc_set_vcore_voltage set vcore to 650000

  520 12:23:09.898124  Read voltage for 800, 4

  521 12:23:09.900900  Vio18 = 0

  522 12:23:09.901323  Vcore = 650000

  523 12:23:09.901663  Vdram = 0

  524 12:23:09.904305  Vddq = 0

  525 12:23:09.904729  Vmddr = 0

  526 12:23:09.907766  dram_init: config_dvfs: 1

  527 12:23:09.911182  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  528 12:23:09.917585  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  529 12:23:09.921115  [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9

  530 12:23:09.924335  freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9

  531 12:23:09.927561  [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9

  532 12:23:09.930312  freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9

  533 12:23:09.934069  MEM_TYPE=3, freq_sel=18

  534 12:23:09.937393  sv_algorithm_assistance_LP4_1600 

  535 12:23:09.940259  ============ PULL DRAM RESETB DOWN ============

  536 12:23:09.946766  ========== PULL DRAM RESETB DOWN end =========

  537 12:23:09.950386  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  538 12:23:09.953716  =================================== 

  539 12:23:09.957363  LPDDR4 DRAM CONFIGURATION

  540 12:23:09.960248  =================================== 

  541 12:23:09.960679  EX_ROW_EN[0]    = 0x0

  542 12:23:09.963627  EX_ROW_EN[1]    = 0x0

  543 12:23:09.964088  LP4Y_EN      = 0x0

  544 12:23:09.966751  WORK_FSP     = 0x0

  545 12:23:09.967176  WL           = 0x2

  546 12:23:09.970392  RL           = 0x2

  547 12:23:09.970820  BL           = 0x2

  548 12:23:09.973714  RPST         = 0x0

  549 12:23:09.976566  RD_PRE       = 0x0

  550 12:23:09.976991  WR_PRE       = 0x1

  551 12:23:09.980083  WR_PST       = 0x0

  552 12:23:09.980513  DBI_WR       = 0x0

  553 12:23:09.983539  DBI_RD       = 0x0

  554 12:23:09.984039  OTF          = 0x1

  555 12:23:09.986469  =================================== 

  556 12:23:09.990076  =================================== 

  557 12:23:09.993426  ANA top config

  558 12:23:09.993851  =================================== 

  559 12:23:09.996884  DLL_ASYNC_EN            =  0

  560 12:23:09.999662  ALL_SLAVE_EN            =  1

  561 12:23:10.002981  NEW_RANK_MODE           =  1

  562 12:23:10.006406  DLL_IDLE_MODE           =  1

  563 12:23:10.006843  LP45_APHY_COMB_EN       =  1

  564 12:23:10.009748  TX_ODT_DIS              =  1

  565 12:23:10.013050  NEW_8X_MODE             =  1

  566 12:23:10.016299  =================================== 

  567 12:23:10.019964  =================================== 

  568 12:23:10.023216  data_rate                  = 1600

  569 12:23:10.026721  CKR                        = 1

  570 12:23:10.029721  DQ_P2S_RATIO               = 8

  571 12:23:10.032715  =================================== 

  572 12:23:10.033149  CA_P2S_RATIO               = 8

  573 12:23:10.035808  DQ_CA_OPEN                 = 0

  574 12:23:10.039347  DQ_SEMI_OPEN               = 0

  575 12:23:10.042708  CA_SEMI_OPEN               = 0

  576 12:23:10.045970  CA_FULL_RATE               = 0

  577 12:23:10.049370  DQ_CKDIV4_EN               = 1

  578 12:23:10.049819  CA_CKDIV4_EN               = 1

  579 12:23:10.052488  CA_PREDIV_EN               = 0

  580 12:23:10.055999  PH8_DLY                    = 0

  581 12:23:10.059220  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  582 12:23:10.062483  DQ_AAMCK_DIV               = 4

  583 12:23:10.065792  CA_AAMCK_DIV               = 4

  584 12:23:10.066243  CA_ADMCK_DIV               = 4

  585 12:23:10.069366  DQ_TRACK_CA_EN             = 0

  586 12:23:10.073067  CA_PICK                    = 800

  587 12:23:10.075832  CA_MCKIO                   = 800

  588 12:23:10.079050  MCKIO_SEMI                 = 0

  589 12:23:10.083097  PLL_FREQ                   = 3068

  590 12:23:10.085639  DQ_UI_PI_RATIO             = 32

  591 12:23:10.086065  CA_UI_PI_RATIO             = 0

  592 12:23:10.089178  =================================== 

  593 12:23:10.092457  =================================== 

  594 12:23:10.095773  memory_type:LPDDR4         

  595 12:23:10.098513  GP_NUM     : 10       

  596 12:23:10.098939  SRAM_EN    : 1       

  597 12:23:10.102568  MD32_EN    : 0       

  598 12:23:10.105632  =================================== 

  599 12:23:10.108924  [ANA_INIT] >>>>>>>>>>>>>> 

  600 12:23:10.112306  <<<<<< [CONFIGURE PHASE]: ANA_TX

  601 12:23:10.115675  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  602 12:23:10.118688  =================================== 

  603 12:23:10.119115  data_rate = 1600,PCW = 0X7600

  604 12:23:10.122574  =================================== 

  605 12:23:10.125297  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  606 12:23:10.132105  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  607 12:23:10.138573  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  608 12:23:10.141716  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  609 12:23:10.145176  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  610 12:23:10.148435  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  611 12:23:10.151607  [ANA_INIT] flow start 

  612 12:23:10.155360  [ANA_INIT] PLL >>>>>>>> 

  613 12:23:10.155828  [ANA_INIT] PLL <<<<<<<< 

  614 12:23:10.158335  [ANA_INIT] MIDPI >>>>>>>> 

  615 12:23:10.161665  [ANA_INIT] MIDPI <<<<<<<< 

  616 12:23:10.162195  [ANA_INIT] DLL >>>>>>>> 

  617 12:23:10.165439  [ANA_INIT] flow end 

  618 12:23:10.168549  ============ LP4 DIFF to SE enter ============

  619 12:23:10.171775  ============ LP4 DIFF to SE exit  ============

  620 12:23:10.174967  [ANA_INIT] <<<<<<<<<<<<< 

  621 12:23:10.178675  [Flow] Enable top DCM control >>>>> 

  622 12:23:10.181655  [Flow] Enable top DCM control <<<<< 

  623 12:23:10.184884  Enable DLL master slave shuffle 

  624 12:23:10.191885  ============================================================== 

  625 12:23:10.192402  Gating Mode config

  626 12:23:10.198123  ============================================================== 

  627 12:23:10.201356  Config description: 

  628 12:23:10.208202  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  629 12:23:10.214841  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  630 12:23:10.221522  SELPH_MODE            0: By rank         1: By Phase 

  631 12:23:10.227771  ============================================================== 

  632 12:23:10.228207  GAT_TRACK_EN                 =  1

  633 12:23:10.231083  RX_GATING_MODE               =  2

  634 12:23:10.234810  RX_GATING_TRACK_MODE         =  2

  635 12:23:10.238154  SELPH_MODE                   =  1

  636 12:23:10.241350  PICG_EARLY_EN                =  1

  637 12:23:10.244835  VALID_LAT_VALUE              =  1

  638 12:23:10.251073  ============================================================== 

  639 12:23:10.254614  Enter into Gating configuration >>>> 

  640 12:23:10.258216  Exit from Gating configuration <<<< 

  641 12:23:10.261308  Enter into  DVFS_PRE_config >>>>> 

  642 12:23:10.271160  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  643 12:23:10.274617  Exit from  DVFS_PRE_config <<<<< 

  644 12:23:10.277717  Enter into PICG configuration >>>> 

  645 12:23:10.280806  Exit from PICG configuration <<<< 

  646 12:23:10.284204  [RX_INPUT] configuration >>>>> 

  647 12:23:10.284631  [RX_INPUT] configuration <<<<< 

  648 12:23:10.290926  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  649 12:23:10.298488  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  650 12:23:10.302332  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  651 12:23:10.309107  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  652 12:23:10.315841  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  653 12:23:10.322656  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  654 12:23:10.326178  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  655 12:23:10.329714  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  656 12:23:10.333105  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  657 12:23:10.336272  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  658 12:23:10.340231  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  659 12:23:10.347390  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  660 12:23:10.350945  =================================== 

  661 12:23:10.351378  LPDDR4 DRAM CONFIGURATION

  662 12:23:10.354670  =================================== 

  663 12:23:10.358449  EX_ROW_EN[0]    = 0x0

  664 12:23:10.359001  EX_ROW_EN[1]    = 0x0

  665 12:23:10.362074  LP4Y_EN      = 0x0

  666 12:23:10.362511  WORK_FSP     = 0x0

  667 12:23:10.365482  WL           = 0x2

  668 12:23:10.365909  RL           = 0x2

  669 12:23:10.368941  BL           = 0x2

  670 12:23:10.369366  RPST         = 0x0

  671 12:23:10.372804  RD_PRE       = 0x0

  672 12:23:10.373250  WR_PRE       = 0x1

  673 12:23:10.373594  WR_PST       = 0x0

  674 12:23:10.376654  DBI_WR       = 0x0

  675 12:23:10.377078  DBI_RD       = 0x0

  676 12:23:10.380917  OTF          = 0x1

  677 12:23:10.384004  =================================== 

  678 12:23:10.387773  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  679 12:23:10.391321  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  680 12:23:10.395330  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  681 12:23:10.398273  =================================== 

  682 12:23:10.401840  LPDDR4 DRAM CONFIGURATION

  683 12:23:10.406110  =================================== 

  684 12:23:10.406770  EX_ROW_EN[0]    = 0x10

  685 12:23:10.409882  EX_ROW_EN[1]    = 0x0

  686 12:23:10.410411  LP4Y_EN      = 0x0

  687 12:23:10.413320  WORK_FSP     = 0x0

  688 12:23:10.413858  WL           = 0x2

  689 12:23:10.417213  RL           = 0x2

  690 12:23:10.417706  BL           = 0x2

  691 12:23:10.420384  RPST         = 0x0

  692 12:23:10.420944  RD_PRE       = 0x0

  693 12:23:10.421294  WR_PRE       = 0x1

  694 12:23:10.424107  WR_PST       = 0x0

  695 12:23:10.424644  DBI_WR       = 0x0

  696 12:23:10.427950  DBI_RD       = 0x0

  697 12:23:10.428463  OTF          = 0x1

  698 12:23:10.431812  =================================== 

  699 12:23:10.438712  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  700 12:23:10.442452  nWR fixed to 40

  701 12:23:10.446263  [ModeRegInit_LP4] CH0 RK0

  702 12:23:10.446692  [ModeRegInit_LP4] CH0 RK1

  703 12:23:10.450056  [ModeRegInit_LP4] CH1 RK0

  704 12:23:10.450525  [ModeRegInit_LP4] CH1 RK1

  705 12:23:10.453780  match AC timing 13

  706 12:23:10.457266  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  707 12:23:10.460686  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  708 12:23:10.467528  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  709 12:23:10.470818  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  710 12:23:10.474402  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  711 12:23:10.477458  [EMI DOE] emi_dcm 0

  712 12:23:10.480847  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  713 12:23:10.481077  ==

  714 12:23:10.484293  Dram Type= 6, Freq= 0, CH_0, rank 0

  715 12:23:10.490780  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  716 12:23:10.491013  ==

  717 12:23:10.494165  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  718 12:23:10.500593  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  719 12:23:10.509899  [CA 0] Center 37 (7~68) winsize 62

  720 12:23:10.513062  [CA 1] Center 36 (6~67) winsize 62

  721 12:23:10.516346  [CA 2] Center 34 (4~65) winsize 62

  722 12:23:10.520432  [CA 3] Center 34 (4~65) winsize 62

  723 12:23:10.523485  [CA 4] Center 33 (3~64) winsize 62

  724 12:23:10.526992  [CA 5] Center 33 (3~64) winsize 62

  725 12:23:10.527472  

  726 12:23:10.530590  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  727 12:23:10.531015  

  728 12:23:10.533806  [CATrainingPosCal] consider 1 rank data

  729 12:23:10.536662  u2DelayCellTimex100 = 270/100 ps

  730 12:23:10.540147  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  731 12:23:10.543222  CA1 delay=36 (6~67),Diff = 3 PI (21 cell)

  732 12:23:10.547131  CA2 delay=34 (4~65),Diff = 1 PI (7 cell)

  733 12:23:10.553509  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  734 12:23:10.556530  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

  735 12:23:10.560314  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  736 12:23:10.560740  

  737 12:23:10.563618  CA PerBit enable=1, Macro0, CA PI delay=33

  738 12:23:10.564242  

  739 12:23:10.567472  [CBTSetCACLKResult] CA Dly = 33

  740 12:23:10.568103  CS Dly: 6 (0~37)

  741 12:23:10.568489  ==

  742 12:23:10.569995  Dram Type= 6, Freq= 0, CH_0, rank 1

  743 12:23:10.576457  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  744 12:23:10.576929  ==

  745 12:23:10.580224  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  746 12:23:10.586437  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  747 12:23:10.596386  [CA 0] Center 37 (6~68) winsize 63

  748 12:23:10.599300  [CA 1] Center 37 (7~68) winsize 62

  749 12:23:10.603044  [CA 2] Center 34 (4~65) winsize 62

  750 12:23:10.606376  [CA 3] Center 34 (4~65) winsize 62

  751 12:23:10.609807  [CA 4] Center 33 (3~64) winsize 62

  752 12:23:10.612998  [CA 5] Center 33 (3~64) winsize 62

  753 12:23:10.613474  

  754 12:23:10.616437  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  755 12:23:10.616909  

  756 12:23:10.619883  [CATrainingPosCal] consider 2 rank data

  757 12:23:10.622731  u2DelayCellTimex100 = 270/100 ps

  758 12:23:10.626207  CA0 delay=37 (7~68),Diff = 4 PI (28 cell)

  759 12:23:10.629607  CA1 delay=37 (7~67),Diff = 4 PI (28 cell)

  760 12:23:10.636202  CA2 delay=34 (4~65),Diff = 1 PI (7 cell)

  761 12:23:10.639794  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  762 12:23:10.643998  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

  763 12:23:10.647526  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  764 12:23:10.647988  

  765 12:23:10.651240  CA PerBit enable=1, Macro0, CA PI delay=33

  766 12:23:10.651825  

  767 12:23:10.652179  [CBTSetCACLKResult] CA Dly = 33

  768 12:23:10.654396  CS Dly: 6 (0~38)

  769 12:23:10.655042  

  770 12:23:10.658445  ----->DramcWriteLeveling(PI) begin...

  771 12:23:10.658957  ==

  772 12:23:10.661397  Dram Type= 6, Freq= 0, CH_0, rank 0

  773 12:23:10.664866  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  774 12:23:10.665339  ==

  775 12:23:10.669260  Write leveling (Byte 0): 31 => 31

  776 12:23:10.672122  Write leveling (Byte 1): 29 => 29

  777 12:23:10.675674  DramcWriteLeveling(PI) end<-----

  778 12:23:10.676144  

  779 12:23:10.676481  ==

  780 12:23:10.678819  Dram Type= 6, Freq= 0, CH_0, rank 0

  781 12:23:10.682254  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  782 12:23:10.682836  ==

  783 12:23:10.685447  [Gating] SW mode calibration

  784 12:23:10.692892  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  785 12:23:10.698852  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  786 12:23:10.702036   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  787 12:23:10.705561   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  788 12:23:10.712172   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  789 12:23:10.715225   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  790 12:23:10.718568   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  791 12:23:10.725224   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  792 12:23:10.729005   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  793 12:23:10.732148   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  794 12:23:10.738414   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  795 12:23:10.742161   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  796 12:23:10.745512   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  797 12:23:10.751935   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  798 12:23:10.754867   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  799 12:23:10.758716   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 12:23:10.762022   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 12:23:10.768705   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 12:23:10.771843   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 12:23:10.775291   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  804 12:23:10.781631   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

  805 12:23:10.785358   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  806 12:23:10.788512   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  807 12:23:10.794866   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  808 12:23:10.798257   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  809 12:23:10.801467   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  810 12:23:10.807894   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  811 12:23:10.811915   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  812 12:23:10.815000   0  9  8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)

  813 12:23:10.821641   0  9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)

  814 12:23:10.824708   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  815 12:23:10.827858   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  816 12:23:10.834537   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  817 12:23:10.838128   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  818 12:23:10.841433   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  819 12:23:10.847842   0 10  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  820 12:23:10.851188   0 10  8 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)

  821 12:23:10.855089   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  822 12:23:10.861232   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  823 12:23:10.864587   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  824 12:23:10.867899   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  825 12:23:10.873882   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  826 12:23:10.878120   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  827 12:23:10.881372   0 11  4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

  828 12:23:10.887254   0 11  8 | B1->B0 | 2424 3a39 | 0 1 | (0 0) (0 0)

  829 12:23:10.890767   0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)

  830 12:23:10.894464   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  831 12:23:10.900993   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  832 12:23:10.904092   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  833 12:23:10.907815   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  834 12:23:10.914054   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  835 12:23:10.917034   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  836 12:23:10.920926   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  837 12:23:10.927633   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

  838 12:23:10.930776   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  839 12:23:10.934162   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  840 12:23:10.940430   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  841 12:23:10.944431   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  842 12:23:10.947257   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  843 12:23:10.953899   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  844 12:23:10.957404   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  845 12:23:10.960738   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  846 12:23:10.964302   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  847 12:23:10.970457   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  848 12:23:10.973957   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  849 12:23:10.977483   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  850 12:23:10.984219   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  851 12:23:10.987047   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  852 12:23:10.990269   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  853 12:23:10.994307  Total UI for P1: 0, mck2ui 16

  854 12:23:10.997019  best dqsien dly found for B0: ( 0, 14,  6)

  855 12:23:11.003853   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  856 12:23:11.007107   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  857 12:23:11.010808  Total UI for P1: 0, mck2ui 16

  858 12:23:11.013660  best dqsien dly found for B1: ( 0, 14, 10)

  859 12:23:11.017105  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

  860 12:23:11.020737  best DQS1 dly(MCK, UI, PI) = (0, 14, 10)

  861 12:23:11.021225  

  862 12:23:11.023719  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

  863 12:23:11.027335  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)

  864 12:23:11.031167  [Gating] SW calibration Done

  865 12:23:11.031590  ==

  866 12:23:11.034567  Dram Type= 6, Freq= 0, CH_0, rank 0

  867 12:23:11.038313  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  868 12:23:11.038810  ==

  869 12:23:11.041648  RX Vref Scan: 0

  870 12:23:11.042104  

  871 12:23:11.042445  RX Vref 0 -> 0, step: 1

  872 12:23:11.044786  

  873 12:23:11.045317  RX Delay -130 -> 252, step: 16

  874 12:23:11.051350  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

  875 12:23:11.054311  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

  876 12:23:11.057794  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  877 12:23:11.061259  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  878 12:23:11.064320  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

  879 12:23:11.071115  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  880 12:23:11.074377  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

  881 12:23:11.077554  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

  882 12:23:11.081115  iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256

  883 12:23:11.084326  iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256

  884 12:23:11.091030  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

  885 12:23:11.097086  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

  886 12:23:11.097850  iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224

  887 12:23:11.101068  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

  888 12:23:11.104667  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

  889 12:23:11.110706  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

  890 12:23:11.111130  ==

  891 12:23:11.114120  Dram Type= 6, Freq= 0, CH_0, rank 0

  892 12:23:11.117751  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  893 12:23:11.118180  ==

  894 12:23:11.118517  DQS Delay:

  895 12:23:11.121509  DQS0 = 0, DQS1 = 0

  896 12:23:11.122131  DQM Delay:

  897 12:23:11.124721  DQM0 = 87, DQM1 = 75

  898 12:23:11.125147  DQ Delay:

  899 12:23:11.128820  DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85

  900 12:23:11.131527  DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =101

  901 12:23:11.135182  DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69

  902 12:23:11.138931  DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85

  903 12:23:11.139452  

  904 12:23:11.139842  

  905 12:23:11.140171  ==

  906 12:23:11.142835  Dram Type= 6, Freq= 0, CH_0, rank 0

  907 12:23:11.146048  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  908 12:23:11.146548  ==

  909 12:23:11.146898  

  910 12:23:11.147212  

  911 12:23:11.149754  	TX Vref Scan disable

  912 12:23:11.150245   == TX Byte 0 ==

  913 12:23:11.153033  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  914 12:23:11.160474  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  915 12:23:11.160986   == TX Byte 1 ==

  916 12:23:11.163618  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  917 12:23:11.167636  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  918 12:23:11.168237  ==

  919 12:23:11.170798  Dram Type= 6, Freq= 0, CH_0, rank 0

  920 12:23:11.177899  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  921 12:23:11.178328  ==

  922 12:23:11.189566  TX Vref=22, minBit 12, minWin=26, winSum=439

  923 12:23:11.192741  TX Vref=24, minBit 5, minWin=27, winSum=444

  924 12:23:11.196163  TX Vref=26, minBit 8, minWin=27, winSum=448

  925 12:23:11.199389  TX Vref=28, minBit 8, minWin=27, winSum=447

  926 12:23:11.203298  TX Vref=30, minBit 8, minWin=27, winSum=445

  927 12:23:11.209467  TX Vref=32, minBit 9, minWin=26, winSum=441

  928 12:23:11.213210  [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 26

  929 12:23:11.213756  

  930 12:23:11.216176  Final TX Range 1 Vref 26

  931 12:23:11.216604  

  932 12:23:11.216945  ==

  933 12:23:11.219419  Dram Type= 6, Freq= 0, CH_0, rank 0

  934 12:23:11.222941  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  935 12:23:11.223472  ==

  936 12:23:11.226060  

  937 12:23:11.226659  

  938 12:23:11.227016  	TX Vref Scan disable

  939 12:23:11.229763   == TX Byte 0 ==

  940 12:23:11.233284  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  941 12:23:11.236637  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  942 12:23:11.240360   == TX Byte 1 ==

  943 12:23:11.243534  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  944 12:23:11.246820  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  945 12:23:11.247243  

  946 12:23:11.247581  [DATLAT]

  947 12:23:11.250367  Freq=800, CH0 RK0

  948 12:23:11.250841  

  949 12:23:11.254513  DATLAT Default: 0xa

  950 12:23:11.255062  0, 0xFFFF, sum = 0

  951 12:23:11.257483  1, 0xFFFF, sum = 0

  952 12:23:11.257969  2, 0xFFFF, sum = 0

  953 12:23:11.261433  3, 0xFFFF, sum = 0

  954 12:23:11.262103  4, 0xFFFF, sum = 0

  955 12:23:11.264434  5, 0xFFFF, sum = 0

  956 12:23:11.264882  6, 0xFFFF, sum = 0

  957 12:23:11.267852  7, 0xFFFF, sum = 0

  958 12:23:11.268320  8, 0xFFFF, sum = 0

  959 12:23:11.271172  9, 0x0, sum = 1

  960 12:23:11.271598  10, 0x0, sum = 2

  961 12:23:11.271995  11, 0x0, sum = 3

  962 12:23:11.274432  12, 0x0, sum = 4

  963 12:23:11.274916  best_step = 10

  964 12:23:11.275281  

  965 12:23:11.277540  ==

  966 12:23:11.277963  Dram Type= 6, Freq= 0, CH_0, rank 0

  967 12:23:11.283882  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  968 12:23:11.284308  ==

  969 12:23:11.284762  RX Vref Scan: 1

  970 12:23:11.285221  

  971 12:23:11.287201  Set Vref Range= 32 -> 127

  972 12:23:11.287757  

  973 12:23:11.290732  RX Vref 32 -> 127, step: 1

  974 12:23:11.291155  

  975 12:23:11.294294  RX Delay -111 -> 252, step: 8

  976 12:23:11.294746  

  977 12:23:11.297443  Set Vref, RX VrefLevel [Byte0]: 32

  978 12:23:11.300503                           [Byte1]: 32

  979 12:23:11.301008  

  980 12:23:11.303836  Set Vref, RX VrefLevel [Byte0]: 33

  981 12:23:11.307306                           [Byte1]: 33

  982 12:23:11.307767  

  983 12:23:11.310642  Set Vref, RX VrefLevel [Byte0]: 34

  984 12:23:11.313958                           [Byte1]: 34

  985 12:23:11.317879  

  986 12:23:11.318458  Set Vref, RX VrefLevel [Byte0]: 35

  987 12:23:11.321040                           [Byte1]: 35

  988 12:23:11.325557  

  989 12:23:11.326076  Set Vref, RX VrefLevel [Byte0]: 36

  990 12:23:11.328413                           [Byte1]: 36

  991 12:23:11.332887  

  992 12:23:11.333309  Set Vref, RX VrefLevel [Byte0]: 37

  993 12:23:11.336187                           [Byte1]: 37

  994 12:23:11.340549  

  995 12:23:11.340972  Set Vref, RX VrefLevel [Byte0]: 38

  996 12:23:11.343655                           [Byte1]: 38

  997 12:23:11.348043  

  998 12:23:11.348541  Set Vref, RX VrefLevel [Byte0]: 39

  999 12:23:11.351488                           [Byte1]: 39

 1000 12:23:11.355884  

 1001 12:23:11.356340  Set Vref, RX VrefLevel [Byte0]: 40

 1002 12:23:11.358936                           [Byte1]: 40

 1003 12:23:11.363590  

 1004 12:23:11.364055  Set Vref, RX VrefLevel [Byte0]: 41

 1005 12:23:11.366595                           [Byte1]: 41

 1006 12:23:11.370842  

 1007 12:23:11.371262  Set Vref, RX VrefLevel [Byte0]: 42

 1008 12:23:11.374220                           [Byte1]: 42

 1009 12:23:11.378866  

 1010 12:23:11.379446  Set Vref, RX VrefLevel [Byte0]: 43

 1011 12:23:11.381732                           [Byte1]: 43

 1012 12:23:11.386353  

 1013 12:23:11.386777  Set Vref, RX VrefLevel [Byte0]: 44

 1014 12:23:11.392949                           [Byte1]: 44

 1015 12:23:11.393373  

 1016 12:23:11.396398  Set Vref, RX VrefLevel [Byte0]: 45

 1017 12:23:11.399480                           [Byte1]: 45

 1018 12:23:11.399935  

 1019 12:23:11.402716  Set Vref, RX VrefLevel [Byte0]: 46

 1020 12:23:11.406035                           [Byte1]: 46

 1021 12:23:11.406449  

 1022 12:23:11.409693  Set Vref, RX VrefLevel [Byte0]: 47

 1023 12:23:11.413318                           [Byte1]: 47

 1024 12:23:11.417541  

 1025 12:23:11.418089  Set Vref, RX VrefLevel [Byte0]: 48

 1026 12:23:11.420311                           [Byte1]: 48

 1027 12:23:11.425014  

 1028 12:23:11.425521  Set Vref, RX VrefLevel [Byte0]: 49

 1029 12:23:11.427709                           [Byte1]: 49

 1030 12:23:11.432094  

 1031 12:23:11.432521  Set Vref, RX VrefLevel [Byte0]: 50

 1032 12:23:11.435258                           [Byte1]: 50

 1033 12:23:11.439806  

 1034 12:23:11.440343  Set Vref, RX VrefLevel [Byte0]: 51

 1035 12:23:11.443451                           [Byte1]: 51

 1036 12:23:11.447177  

 1037 12:23:11.447591  Set Vref, RX VrefLevel [Byte0]: 52

 1038 12:23:11.450683                           [Byte1]: 52

 1039 12:23:11.455144  

 1040 12:23:11.458279  Set Vref, RX VrefLevel [Byte0]: 53

 1041 12:23:11.458698                           [Byte1]: 53

 1042 12:23:11.462990  

 1043 12:23:11.463405  Set Vref, RX VrefLevel [Byte0]: 54

 1044 12:23:11.466489                           [Byte1]: 54

 1045 12:23:11.470626  

 1046 12:23:11.471132  Set Vref, RX VrefLevel [Byte0]: 55

 1047 12:23:11.473634                           [Byte1]: 55

 1048 12:23:11.478221  

 1049 12:23:11.478725  Set Vref, RX VrefLevel [Byte0]: 56

 1050 12:23:11.481494                           [Byte1]: 56

 1051 12:23:11.485826  

 1052 12:23:11.486240  Set Vref, RX VrefLevel [Byte0]: 57

 1053 12:23:11.489201                           [Byte1]: 57

 1054 12:23:11.493263  

 1055 12:23:11.493676  Set Vref, RX VrefLevel [Byte0]: 58

 1056 12:23:11.496794                           [Byte1]: 58

 1057 12:23:11.500873  

 1058 12:23:11.501335  Set Vref, RX VrefLevel [Byte0]: 59

 1059 12:23:11.504312                           [Byte1]: 59

 1060 12:23:11.508677  

 1061 12:23:11.509095  Set Vref, RX VrefLevel [Byte0]: 60

 1062 12:23:11.511829                           [Byte1]: 60

 1063 12:23:11.516714  

 1064 12:23:11.517128  Set Vref, RX VrefLevel [Byte0]: 61

 1065 12:23:11.519546                           [Byte1]: 61

 1066 12:23:11.524114  

 1067 12:23:11.524529  Set Vref, RX VrefLevel [Byte0]: 62

 1068 12:23:11.527349                           [Byte1]: 62

 1069 12:23:11.532072  

 1070 12:23:11.532487  Set Vref, RX VrefLevel [Byte0]: 63

 1071 12:23:11.535115                           [Byte1]: 63

 1072 12:23:11.539893  

 1073 12:23:11.540397  Set Vref, RX VrefLevel [Byte0]: 64

 1074 12:23:11.542944                           [Byte1]: 64

 1075 12:23:11.547140  

 1076 12:23:11.547773  Set Vref, RX VrefLevel [Byte0]: 65

 1077 12:23:11.550596                           [Byte1]: 65

 1078 12:23:11.554316  

 1079 12:23:11.557530  Set Vref, RX VrefLevel [Byte0]: 66

 1080 12:23:11.557956                           [Byte1]: 66

 1081 12:23:11.562067  

 1082 12:23:11.562692  Set Vref, RX VrefLevel [Byte0]: 67

 1083 12:23:11.565569                           [Byte1]: 67

 1084 12:23:11.569909  

 1085 12:23:11.570324  Set Vref, RX VrefLevel [Byte0]: 68

 1086 12:23:11.573385                           [Byte1]: 68

 1087 12:23:11.577973  

 1088 12:23:11.578386  Set Vref, RX VrefLevel [Byte0]: 69

 1089 12:23:11.581532                           [Byte1]: 69

 1090 12:23:11.585850  

 1091 12:23:11.586262  Set Vref, RX VrefLevel [Byte0]: 70

 1092 12:23:11.588994                           [Byte1]: 70

 1093 12:23:11.592996  

 1094 12:23:11.593410  Set Vref, RX VrefLevel [Byte0]: 71

 1095 12:23:11.596731                           [Byte1]: 71

 1096 12:23:11.600720  

 1097 12:23:11.601136  Set Vref, RX VrefLevel [Byte0]: 72

 1098 12:23:11.604234                           [Byte1]: 72

 1099 12:23:11.608113  

 1100 12:23:11.608528  Set Vref, RX VrefLevel [Byte0]: 73

 1101 12:23:11.611653                           [Byte1]: 73

 1102 12:23:11.616030  

 1103 12:23:11.616481  Set Vref, RX VrefLevel [Byte0]: 74

 1104 12:23:11.619278                           [Byte1]: 74

 1105 12:23:11.623271  

 1106 12:23:11.623714  Set Vref, RX VrefLevel [Byte0]: 75

 1107 12:23:11.626548                           [Byte1]: 75

 1108 12:23:11.631209  

 1109 12:23:11.631617  Set Vref, RX VrefLevel [Byte0]: 76

 1110 12:23:11.634205                           [Byte1]: 76

 1111 12:23:11.639151  

 1112 12:23:11.639690  Set Vref, RX VrefLevel [Byte0]: 77

 1113 12:23:11.642335                           [Byte1]: 77

 1114 12:23:11.646669  

 1115 12:23:11.647077  Set Vref, RX VrefLevel [Byte0]: 78

 1116 12:23:11.650870                           [Byte1]: 78

 1117 12:23:11.654594  

 1118 12:23:11.655155  Set Vref, RX VrefLevel [Byte0]: 79

 1119 12:23:11.657679                           [Byte1]: 79

 1120 12:23:11.662292  

 1121 12:23:11.662823  Set Vref, RX VrefLevel [Byte0]: 80

 1122 12:23:11.665417                           [Byte1]: 80

 1123 12:23:11.668960  

 1124 12:23:11.672756  Final RX Vref Byte 0 = 68 to rank0

 1125 12:23:11.673310  Final RX Vref Byte 1 = 60 to rank0

 1126 12:23:11.676252  Final RX Vref Byte 0 = 68 to rank1

 1127 12:23:11.679993  Final RX Vref Byte 1 = 60 to rank1==

 1128 12:23:11.683377  Dram Type= 6, Freq= 0, CH_0, rank 0

 1129 12:23:11.687367  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1130 12:23:11.687977  ==

 1131 12:23:11.688520  DQS Delay:

 1132 12:23:11.691416  DQS0 = 0, DQS1 = 0

 1133 12:23:11.691975  DQM Delay:

 1134 12:23:11.694792  DQM0 = 88, DQM1 = 75

 1135 12:23:11.695350  DQ Delay:

 1136 12:23:11.698633  DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84

 1137 12:23:11.702466  DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96

 1138 12:23:11.706107  DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68

 1139 12:23:11.706621  DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84

 1140 12:23:11.709738  

 1141 12:23:11.710215  

 1142 12:23:11.716984  [DQSOSCAuto] RK0, (LSB)MR18= 0x4021, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps

 1143 12:23:11.720352  CH0 RK0: MR19=606, MR18=4021

 1144 12:23:11.723893  CH0_RK0: MR19=0x606, MR18=0x4021, DQSOSC=393, MR23=63, INC=95, DEC=63

 1145 12:23:11.724308  

 1146 12:23:11.727322  ----->DramcWriteLeveling(PI) begin...

 1147 12:23:11.727941  ==

 1148 12:23:11.730915  Dram Type= 6, Freq= 0, CH_0, rank 1

 1149 12:23:11.734622  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1150 12:23:11.735077  ==

 1151 12:23:11.738640  Write leveling (Byte 0): 31 => 31

 1152 12:23:11.742633  Write leveling (Byte 1): 31 => 31

 1153 12:23:11.745721  DramcWriteLeveling(PI) end<-----

 1154 12:23:11.746263  

 1155 12:23:11.746724  ==

 1156 12:23:11.749693  Dram Type= 6, Freq= 0, CH_0, rank 1

 1157 12:23:11.753311  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1158 12:23:11.753872  ==

 1159 12:23:11.757076  [Gating] SW mode calibration

 1160 12:23:11.801095  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1161 12:23:11.801977  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1162 12:23:11.802369   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1163 12:23:11.802766   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1164 12:23:11.803176   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1165 12:23:11.803767   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1166 12:23:11.804131   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1167 12:23:11.804677   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1168 12:23:11.804992   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1169 12:23:11.844645   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1170 12:23:11.845335   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1171 12:23:11.846206   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1172 12:23:11.846707   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1173 12:23:11.847255   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1174 12:23:11.847660   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1175 12:23:11.848175   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1176 12:23:11.848776   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1177 12:23:11.849264   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1178 12:23:11.849582   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1179 12:23:11.861489   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1180 12:23:11.862234   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1181 12:23:11.862620   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1182 12:23:11.865058   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1183 12:23:11.868056   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1184 12:23:11.871363   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1185 12:23:11.874651   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1186 12:23:11.878438   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1187 12:23:11.881728   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1188 12:23:11.888949   0  9  8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)

 1189 12:23:11.892851   0  9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 1190 12:23:11.896496   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1191 12:23:11.899663   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1192 12:23:11.903344   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1193 12:23:11.910604   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1194 12:23:11.914283   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1195 12:23:11.918257   0 10  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1196 12:23:11.921876   0 10  8 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (1 0)

 1197 12:23:11.925261   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1198 12:23:11.932657   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1199 12:23:11.936839   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1200 12:23:11.940107   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1201 12:23:11.944100   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1202 12:23:11.947451   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1203 12:23:11.954226   0 11  4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)

 1204 12:23:11.957270   0 11  8 | B1->B0 | 2e2e 3d3d | 0 0 | (0 0) (1 1)

 1205 12:23:11.960722   0 11 12 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)

 1206 12:23:11.964203   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1207 12:23:11.971410   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1208 12:23:11.975020   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1209 12:23:11.978062   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1210 12:23:11.984966   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1211 12:23:11.988353   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1212 12:23:11.992018   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1213 12:23:11.995308   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1214 12:23:12.001947   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1215 12:23:12.005488   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1216 12:23:12.008904   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1217 12:23:12.015664   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1218 12:23:12.018681   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1219 12:23:12.021851   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1220 12:23:12.028741   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1221 12:23:12.031853   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1222 12:23:12.035041   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1223 12:23:12.041742   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1224 12:23:12.045130   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1225 12:23:12.048175   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1226 12:23:12.055096   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1227 12:23:12.058358   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1228 12:23:12.061512   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1229 12:23:12.068551   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1230 12:23:12.069018  Total UI for P1: 0, mck2ui 16

 1231 12:23:12.074955  best dqsien dly found for B0: ( 0, 14,  8)

 1232 12:23:12.075417  Total UI for P1: 0, mck2ui 16

 1233 12:23:12.081537  best dqsien dly found for B1: ( 0, 14,  8)

 1234 12:23:12.084889  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1235 12:23:12.088559  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1236 12:23:12.089114  

 1237 12:23:12.091558  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1238 12:23:12.094741  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1239 12:23:12.098371  [Gating] SW calibration Done

 1240 12:23:12.098927  ==

 1241 12:23:12.101594  Dram Type= 6, Freq= 0, CH_0, rank 1

 1242 12:23:12.105259  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1243 12:23:12.105825  ==

 1244 12:23:12.108054  RX Vref Scan: 0

 1245 12:23:12.108512  

 1246 12:23:12.108874  RX Vref 0 -> 0, step: 1

 1247 12:23:12.109214  

 1248 12:23:12.111833  RX Delay -130 -> 252, step: 16

 1249 12:23:12.114873  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1250 12:23:12.121587  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

 1251 12:23:12.124722  iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256

 1252 12:23:12.128132  iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240

 1253 12:23:12.130986  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1254 12:23:12.134298  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

 1255 12:23:12.141383  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1256 12:23:12.144288  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

 1257 12:23:12.148015  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1258 12:23:12.151252  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1259 12:23:12.157475  iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256

 1260 12:23:12.160758  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1261 12:23:12.164316  iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256

 1262 12:23:12.167851  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1263 12:23:12.170763  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1264 12:23:12.177799  iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256

 1265 12:23:12.178332  ==

 1266 12:23:12.181021  Dram Type= 6, Freq= 0, CH_0, rank 1

 1267 12:23:12.184223  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1268 12:23:12.184679  ==

 1269 12:23:12.185035  DQS Delay:

 1270 12:23:12.187425  DQS0 = 0, DQS1 = 0

 1271 12:23:12.188018  DQM Delay:

 1272 12:23:12.190652  DQM0 = 84, DQM1 = 76

 1273 12:23:12.191194  DQ Delay:

 1274 12:23:12.194011  DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69

 1275 12:23:12.197543  DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101

 1276 12:23:12.201201  DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69

 1277 12:23:12.203780  DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =77

 1278 12:23:12.204208  

 1279 12:23:12.204536  

 1280 12:23:12.204838  ==

 1281 12:23:12.207551  Dram Type= 6, Freq= 0, CH_0, rank 1

 1282 12:23:12.210872  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1283 12:23:12.214051  ==

 1284 12:23:12.214473  

 1285 12:23:12.214795  

 1286 12:23:12.215097  	TX Vref Scan disable

 1287 12:23:12.217367   == TX Byte 0 ==

 1288 12:23:12.220392  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

 1289 12:23:12.223692  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

 1290 12:23:12.227265   == TX Byte 1 ==

 1291 12:23:12.230716  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1292 12:23:12.233859  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1293 12:23:12.234273  ==

 1294 12:23:12.237537  Dram Type= 6, Freq= 0, CH_0, rank 1

 1295 12:23:12.243405  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1296 12:23:12.243861  ==

 1297 12:23:12.255777  TX Vref=22, minBit 5, minWin=27, winSum=444

 1298 12:23:12.258937  TX Vref=24, minBit 1, minWin=28, winSum=449

 1299 12:23:12.263008  TX Vref=26, minBit 9, minWin=27, winSum=450

 1300 12:23:12.265428  TX Vref=28, minBit 9, minWin=27, winSum=449

 1301 12:23:12.268987  TX Vref=30, minBit 9, minWin=27, winSum=448

 1302 12:23:12.272610  TX Vref=32, minBit 9, minWin=27, winSum=446

 1303 12:23:12.278772  [TxChooseVref] Worse bit 1, Min win 28, Win sum 449, Final Vref 24

 1304 12:23:12.279070  

 1305 12:23:12.281890  Final TX Range 1 Vref 24

 1306 12:23:12.282186  

 1307 12:23:12.282419  ==

 1308 12:23:12.285230  Dram Type= 6, Freq= 0, CH_0, rank 1

 1309 12:23:12.288991  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1310 12:23:12.289356  ==

 1311 12:23:12.291777  

 1312 12:23:12.292154  

 1313 12:23:12.292454  	TX Vref Scan disable

 1314 12:23:12.295427   == TX Byte 0 ==

 1315 12:23:12.298781  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1316 12:23:12.305224  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1317 12:23:12.305724   == TX Byte 1 ==

 1318 12:23:12.308807  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1319 12:23:12.315881  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1320 12:23:12.316382  

 1321 12:23:12.316712  [DATLAT]

 1322 12:23:12.317022  Freq=800, CH0 RK1

 1323 12:23:12.317319  

 1324 12:23:12.318797  DATLAT Default: 0xa

 1325 12:23:12.319209  0, 0xFFFF, sum = 0

 1326 12:23:12.322165  1, 0xFFFF, sum = 0

 1327 12:23:12.325231  2, 0xFFFF, sum = 0

 1328 12:23:12.325651  3, 0xFFFF, sum = 0

 1329 12:23:12.328728  4, 0xFFFF, sum = 0

 1330 12:23:12.329145  5, 0xFFFF, sum = 0

 1331 12:23:12.331965  6, 0xFFFF, sum = 0

 1332 12:23:12.332385  7, 0xFFFF, sum = 0

 1333 12:23:12.335048  8, 0xFFFF, sum = 0

 1334 12:23:12.335465  9, 0x0, sum = 1

 1335 12:23:12.338443  10, 0x0, sum = 2

 1336 12:23:12.338864  11, 0x0, sum = 3

 1337 12:23:12.339198  12, 0x0, sum = 4

 1338 12:23:12.342449  best_step = 10

 1339 12:23:12.343010  

 1340 12:23:12.343344  ==

 1341 12:23:12.345368  Dram Type= 6, Freq= 0, CH_0, rank 1

 1342 12:23:12.348705  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1343 12:23:12.349128  ==

 1344 12:23:12.351891  RX Vref Scan: 0

 1345 12:23:12.352542  

 1346 12:23:12.355090  RX Vref 0 -> 0, step: 1

 1347 12:23:12.355496  

 1348 12:23:12.355870  RX Delay -95 -> 252, step: 8

 1349 12:23:12.362389  iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232

 1350 12:23:12.365549  iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224

 1351 12:23:12.368820  iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224

 1352 12:23:12.372222  iDelay=217, Bit 3, Center 76 (-39 ~ 192) 232

 1353 12:23:12.375169  iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232

 1354 12:23:12.382000  iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232

 1355 12:23:12.385111  iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232

 1356 12:23:12.389135  iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240

 1357 12:23:12.391913  iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232

 1358 12:23:12.395271  iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224

 1359 12:23:12.401850  iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240

 1360 12:23:12.405613  iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232

 1361 12:23:12.408607  iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232

 1362 12:23:12.412026  iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232

 1363 12:23:12.418710  iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224

 1364 12:23:12.421946  iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232

 1365 12:23:12.422450  ==

 1366 12:23:12.425083  Dram Type= 6, Freq= 0, CH_0, rank 1

 1367 12:23:12.428522  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1368 12:23:12.428991  ==

 1369 12:23:12.431821  DQS Delay:

 1370 12:23:12.432226  DQS0 = 0, DQS1 = 0

 1371 12:23:12.432584  DQM Delay:

 1372 12:23:12.435387  DQM0 = 84, DQM1 = 77

 1373 12:23:12.436008  DQ Delay:

 1374 12:23:12.438715  DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =76

 1375 12:23:12.442110  DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96

 1376 12:23:12.445330  DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68

 1377 12:23:12.448296  DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84

 1378 12:23:12.448700  

 1379 12:23:12.449020  

 1380 12:23:12.458247  [DQSOSCAuto] RK1, (LSB)MR18= 0x4208, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps

 1381 12:23:12.458807  CH0 RK1: MR19=606, MR18=4208

 1382 12:23:12.465059  CH0_RK1: MR19=0x606, MR18=0x4208, DQSOSC=393, MR23=63, INC=95, DEC=63

 1383 12:23:12.468354  [RxdqsGatingPostProcess] freq 800

 1384 12:23:12.475472  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1385 12:23:12.478151  Pre-setting of DQS Precalculation

 1386 12:23:12.481478  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1387 12:23:12.481907  ==

 1388 12:23:12.485069  Dram Type= 6, Freq= 0, CH_1, rank 0

 1389 12:23:12.491145  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1390 12:23:12.491678  ==

 1391 12:23:12.494887  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1392 12:23:12.501244  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1393 12:23:12.510719  [CA 0] Center 36 (6~67) winsize 62

 1394 12:23:12.513994  [CA 1] Center 36 (6~67) winsize 62

 1395 12:23:12.517556  [CA 2] Center 34 (4~65) winsize 62

 1396 12:23:12.520472  [CA 3] Center 34 (3~65) winsize 63

 1397 12:23:12.524177  [CA 4] Center 34 (4~65) winsize 62

 1398 12:23:12.527087  [CA 5] Center 34 (4~65) winsize 62

 1399 12:23:12.527638  

 1400 12:23:12.530257  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1401 12:23:12.530716  

 1402 12:23:12.533563  [CATrainingPosCal] consider 1 rank data

 1403 12:23:12.536829  u2DelayCellTimex100 = 270/100 ps

 1404 12:23:12.540154  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1405 12:23:12.546925  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1406 12:23:12.550067  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 1407 12:23:12.553518  CA3 delay=34 (3~65),Diff = 0 PI (0 cell)

 1408 12:23:12.556853  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1409 12:23:12.560035  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 1410 12:23:12.560678  

 1411 12:23:12.563242  CA PerBit enable=1, Macro0, CA PI delay=34

 1412 12:23:12.563702  

 1413 12:23:12.566730  [CBTSetCACLKResult] CA Dly = 34

 1414 12:23:12.569881  CS Dly: 5 (0~36)

 1415 12:23:12.570296  ==

 1416 12:23:12.573328  Dram Type= 6, Freq= 0, CH_1, rank 1

 1417 12:23:12.576411  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1418 12:23:12.576807  ==

 1419 12:23:12.583064  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1420 12:23:12.586534  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1421 12:23:12.596319  [CA 0] Center 36 (6~67) winsize 62

 1422 12:23:12.599678  [CA 1] Center 36 (6~67) winsize 62

 1423 12:23:12.603282  [CA 2] Center 34 (4~65) winsize 62

 1424 12:23:12.606100  [CA 3] Center 34 (3~65) winsize 63

 1425 12:23:12.609713  [CA 4] Center 34 (4~65) winsize 62

 1426 12:23:12.613222  [CA 5] Center 34 (4~65) winsize 62

 1427 12:23:12.613793  

 1428 12:23:12.616700  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1429 12:23:12.617239  

 1430 12:23:12.619531  [CATrainingPosCal] consider 2 rank data

 1431 12:23:12.622861  u2DelayCellTimex100 = 270/100 ps

 1432 12:23:12.626262  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1433 12:23:12.632728  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1434 12:23:12.636138  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 1435 12:23:12.639567  CA3 delay=34 (3~65),Diff = 0 PI (0 cell)

 1436 12:23:12.642723  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1437 12:23:12.646025  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 1438 12:23:12.646448  

 1439 12:23:12.649578  CA PerBit enable=1, Macro0, CA PI delay=34

 1440 12:23:12.649987  

 1441 12:23:12.652766  [CBTSetCACLKResult] CA Dly = 34

 1442 12:23:12.656453  CS Dly: 6 (0~38)

 1443 12:23:12.657109  

 1444 12:23:12.659506  ----->DramcWriteLeveling(PI) begin...

 1445 12:23:12.660059  ==

 1446 12:23:12.662840  Dram Type= 6, Freq= 0, CH_1, rank 0

 1447 12:23:12.666568  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1448 12:23:12.666977  ==

 1449 12:23:12.669644  Write leveling (Byte 0): 28 => 28

 1450 12:23:12.672705  Write leveling (Byte 1): 29 => 29

 1451 12:23:12.676475  DramcWriteLeveling(PI) end<-----

 1452 12:23:12.676885  

 1453 12:23:12.677209  ==

 1454 12:23:12.679375  Dram Type= 6, Freq= 0, CH_1, rank 0

 1455 12:23:12.682900  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1456 12:23:12.683312  ==

 1457 12:23:12.686045  [Gating] SW mode calibration

 1458 12:23:12.692869  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1459 12:23:12.699328  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1460 12:23:12.702521   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1461 12:23:12.705891   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1462 12:23:12.712492   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1463 12:23:12.715681   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1464 12:23:12.718970   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1465 12:23:12.726070   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1466 12:23:12.728963   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1467 12:23:12.732561   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1468 12:23:12.739009   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1469 12:23:12.742474   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1470 12:23:12.745795   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1471 12:23:12.752450   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1472 12:23:12.755192   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1473 12:23:12.758655   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1474 12:23:12.765442   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1475 12:23:12.769066   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1476 12:23:12.772568   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1477 12:23:12.778518   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1478 12:23:12.782508   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1479 12:23:12.786125   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1480 12:23:12.792011   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1481 12:23:12.794938   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1482 12:23:12.798441   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1483 12:23:12.805273   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1484 12:23:12.808555   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1485 12:23:12.811505   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1486 12:23:12.818343   0  9  8 | B1->B0 | 2c2c 3232 | 1 0 | (1 1) (0 0)

 1487 12:23:12.821924   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1488 12:23:12.824927   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1489 12:23:12.831305   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1490 12:23:12.834648   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1491 12:23:12.838196   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1492 12:23:12.844746   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 1493 12:23:12.847888   0 10  4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)

 1494 12:23:12.851569   0 10  8 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)

 1495 12:23:12.854573   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1496 12:23:12.861296   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1497 12:23:12.864301   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1498 12:23:12.867860   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1499 12:23:12.874372   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1500 12:23:12.877612   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1501 12:23:12.881413   0 11  4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)

 1502 12:23:12.887647   0 11  8 | B1->B0 | 3939 3b3b | 0 0 | (0 0) (0 0)

 1503 12:23:12.891090   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1504 12:23:12.894700   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1505 12:23:12.900790   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1506 12:23:12.904673   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1507 12:23:12.907871   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1508 12:23:12.914203   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1509 12:23:12.917957   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1510 12:23:12.920565   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1511 12:23:12.927407   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1512 12:23:12.930715   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1513 12:23:12.933968   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1514 12:23:12.940675   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1515 12:23:12.943807   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1516 12:23:12.947095   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1517 12:23:12.953988   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1518 12:23:12.956837   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1519 12:23:12.960458   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1520 12:23:12.967356   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1521 12:23:12.971060   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1522 12:23:12.974159   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1523 12:23:12.980516   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1524 12:23:12.983618   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1525 12:23:12.987121   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1526 12:23:12.993801   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1527 12:23:12.994358  Total UI for P1: 0, mck2ui 16

 1528 12:23:13.000300  best dqsien dly found for B0: ( 0, 14,  6)

 1529 12:23:13.003830   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1530 12:23:13.006708  Total UI for P1: 0, mck2ui 16

 1531 12:23:13.010219  best dqsien dly found for B1: ( 0, 14,  8)

 1532 12:23:13.013555  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1533 12:23:13.016443  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1534 12:23:13.017022  

 1535 12:23:13.019838  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1536 12:23:13.023602  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1537 12:23:13.026674  [Gating] SW calibration Done

 1538 12:23:13.027127  ==

 1539 12:23:13.030109  Dram Type= 6, Freq= 0, CH_1, rank 0

 1540 12:23:13.033218  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1541 12:23:13.037179  ==

 1542 12:23:13.037764  RX Vref Scan: 0

 1543 12:23:13.038142  

 1544 12:23:13.039868  RX Vref 0 -> 0, step: 1

 1545 12:23:13.040364  

 1546 12:23:13.043150  RX Delay -130 -> 252, step: 16

 1547 12:23:13.046537  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1548 12:23:13.049954  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

 1549 12:23:13.053332  iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224

 1550 12:23:13.056714  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1551 12:23:13.062948  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1552 12:23:13.066624  iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240

 1553 12:23:13.070058  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1554 12:23:13.073595  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

 1555 12:23:13.076335  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1556 12:23:13.083344  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1557 12:23:13.086565  iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240

 1558 12:23:13.089725  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1559 12:23:13.093476  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1560 12:23:13.096163  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1561 12:23:13.102580  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1562 12:23:13.106818  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1563 12:23:13.107401  ==

 1564 12:23:13.109856  Dram Type= 6, Freq= 0, CH_1, rank 0

 1565 12:23:13.112616  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1566 12:23:13.113076  ==

 1567 12:23:13.116378  DQS Delay:

 1568 12:23:13.116943  DQS0 = 0, DQS1 = 0

 1569 12:23:13.117310  DQM Delay:

 1570 12:23:13.119833  DQM0 = 89, DQM1 = 79

 1571 12:23:13.120310  DQ Delay:

 1572 12:23:13.122833  DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85

 1573 12:23:13.126333  DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85

 1574 12:23:13.129794  DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69

 1575 12:23:13.133059  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1576 12:23:13.133583  

 1577 12:23:13.133917  

 1578 12:23:13.134225  ==

 1579 12:23:13.136286  Dram Type= 6, Freq= 0, CH_1, rank 0

 1580 12:23:13.143196  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1581 12:23:13.143720  ==

 1582 12:23:13.144102  

 1583 12:23:13.144410  

 1584 12:23:13.144703  	TX Vref Scan disable

 1585 12:23:13.146643   == TX Byte 0 ==

 1586 12:23:13.149578  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1587 12:23:13.156066  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1588 12:23:13.156528   == TX Byte 1 ==

 1589 12:23:13.159617  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1590 12:23:13.166119  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1591 12:23:13.166585  ==

 1592 12:23:13.170051  Dram Type= 6, Freq= 0, CH_1, rank 0

 1593 12:23:13.172988  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1594 12:23:13.173558  ==

 1595 12:23:13.186014  TX Vref=22, minBit 10, minWin=26, winSum=441

 1596 12:23:13.189094  TX Vref=24, minBit 8, minWin=27, winSum=448

 1597 12:23:13.192120  TX Vref=26, minBit 10, minWin=27, winSum=449

 1598 12:23:13.195240  TX Vref=28, minBit 9, minWin=27, winSum=452

 1599 12:23:13.198461  TX Vref=30, minBit 9, minWin=27, winSum=450

 1600 12:23:13.205358  TX Vref=32, minBit 9, minWin=27, winSum=446

 1601 12:23:13.208440  [TxChooseVref] Worse bit 9, Min win 27, Win sum 452, Final Vref 28

 1602 12:23:13.208901  

 1603 12:23:13.212430  Final TX Range 1 Vref 28

 1604 12:23:13.212977  

 1605 12:23:13.213342  ==

 1606 12:23:13.215192  Dram Type= 6, Freq= 0, CH_1, rank 0

 1607 12:23:13.218469  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1608 12:23:13.222242  ==

 1609 12:23:13.222808  

 1610 12:23:13.223173  

 1611 12:23:13.223508  	TX Vref Scan disable

 1612 12:23:13.225454   == TX Byte 0 ==

 1613 12:23:13.229695  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1614 12:23:13.235552  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1615 12:23:13.236171   == TX Byte 1 ==

 1616 12:23:13.238805  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1617 12:23:13.246074  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1618 12:23:13.246655  

 1619 12:23:13.247022  [DATLAT]

 1620 12:23:13.247362  Freq=800, CH1 RK0

 1621 12:23:13.247691  

 1622 12:23:13.248448  DATLAT Default: 0xa

 1623 12:23:13.248806  0, 0xFFFF, sum = 0

 1624 12:23:13.252208  1, 0xFFFF, sum = 0

 1625 12:23:13.255510  2, 0xFFFF, sum = 0

 1626 12:23:13.256244  3, 0xFFFF, sum = 0

 1627 12:23:13.258817  4, 0xFFFF, sum = 0

 1628 12:23:13.259376  5, 0xFFFF, sum = 0

 1629 12:23:13.262248  6, 0xFFFF, sum = 0

 1630 12:23:13.262709  7, 0xFFFF, sum = 0

 1631 12:23:13.264937  8, 0xFFFF, sum = 0

 1632 12:23:13.265400  9, 0x0, sum = 1

 1633 12:23:13.268380  10, 0x0, sum = 2

 1634 12:23:13.268860  11, 0x0, sum = 3

 1635 12:23:13.272148  12, 0x0, sum = 4

 1636 12:23:13.272719  best_step = 10

 1637 12:23:13.273204  

 1638 12:23:13.273654  ==

 1639 12:23:13.275305  Dram Type= 6, Freq= 0, CH_1, rank 0

 1640 12:23:13.278808  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1641 12:23:13.279285  ==

 1642 12:23:13.281527  RX Vref Scan: 1

 1643 12:23:13.281999  

 1644 12:23:13.284965  Set Vref Range= 32 -> 127

 1645 12:23:13.285438  

 1646 12:23:13.285922  RX Vref 32 -> 127, step: 1

 1647 12:23:13.286376  

 1648 12:23:13.288418  RX Delay -95 -> 252, step: 8

 1649 12:23:13.288891  

 1650 12:23:13.291920  Set Vref, RX VrefLevel [Byte0]: 32

 1651 12:23:13.295361                           [Byte1]: 32

 1652 12:23:13.298364  

 1653 12:23:13.298928  Set Vref, RX VrefLevel [Byte0]: 33

 1654 12:23:13.302147                           [Byte1]: 33

 1655 12:23:13.305849  

 1656 12:23:13.306324  Set Vref, RX VrefLevel [Byte0]: 34

 1657 12:23:13.309095                           [Byte1]: 34

 1658 12:23:13.313382  

 1659 12:23:13.313851  Set Vref, RX VrefLevel [Byte0]: 35

 1660 12:23:13.316622                           [Byte1]: 35

 1661 12:23:13.321310  

 1662 12:23:13.321873  Set Vref, RX VrefLevel [Byte0]: 36

 1663 12:23:13.324298                           [Byte1]: 36

 1664 12:23:13.328720  

 1665 12:23:13.329180  Set Vref, RX VrefLevel [Byte0]: 37

 1666 12:23:13.332025                           [Byte1]: 37

 1667 12:23:13.336284  

 1668 12:23:13.336741  Set Vref, RX VrefLevel [Byte0]: 38

 1669 12:23:13.339894                           [Byte1]: 38

 1670 12:23:13.344344  

 1671 12:23:13.344893  Set Vref, RX VrefLevel [Byte0]: 39

 1672 12:23:13.347597                           [Byte1]: 39

 1673 12:23:13.351929  

 1674 12:23:13.352388  Set Vref, RX VrefLevel [Byte0]: 40

 1675 12:23:13.355065                           [Byte1]: 40

 1676 12:23:13.359373  

 1677 12:23:13.359971  Set Vref, RX VrefLevel [Byte0]: 41

 1678 12:23:13.362645                           [Byte1]: 41

 1679 12:23:13.366876  

 1680 12:23:13.367442  Set Vref, RX VrefLevel [Byte0]: 42

 1681 12:23:13.370432                           [Byte1]: 42

 1682 12:23:13.374925  

 1683 12:23:13.375514  Set Vref, RX VrefLevel [Byte0]: 43

 1684 12:23:13.377531                           [Byte1]: 43

 1685 12:23:13.381738  

 1686 12:23:13.382197  Set Vref, RX VrefLevel [Byte0]: 44

 1687 12:23:13.384932                           [Byte1]: 44

 1688 12:23:13.389264  

 1689 12:23:13.389724  Set Vref, RX VrefLevel [Byte0]: 45

 1690 12:23:13.393017                           [Byte1]: 45

 1691 12:23:13.397268  

 1692 12:23:13.397723  Set Vref, RX VrefLevel [Byte0]: 46

 1693 12:23:13.400499                           [Byte1]: 46

 1694 12:23:13.404521  

 1695 12:23:13.404936  Set Vref, RX VrefLevel [Byte0]: 47

 1696 12:23:13.408232                           [Byte1]: 47

 1697 12:23:13.412438  

 1698 12:23:13.412965  Set Vref, RX VrefLevel [Byte0]: 48

 1699 12:23:13.415606                           [Byte1]: 48

 1700 12:23:13.419863  

 1701 12:23:13.420329  Set Vref, RX VrefLevel [Byte0]: 49

 1702 12:23:13.423330                           [Byte1]: 49

 1703 12:23:13.427982  

 1704 12:23:13.428538  Set Vref, RX VrefLevel [Byte0]: 50

 1705 12:23:13.431110                           [Byte1]: 50

 1706 12:23:13.434953  

 1707 12:23:13.435443  Set Vref, RX VrefLevel [Byte0]: 51

 1708 12:23:13.438690                           [Byte1]: 51

 1709 12:23:13.442913  

 1710 12:23:13.443490  Set Vref, RX VrefLevel [Byte0]: 52

 1711 12:23:13.446040                           [Byte1]: 52

 1712 12:23:13.449961  

 1713 12:23:13.453297  Set Vref, RX VrefLevel [Byte0]: 53

 1714 12:23:13.456853                           [Byte1]: 53

 1715 12:23:13.457336  

 1716 12:23:13.460230  Set Vref, RX VrefLevel [Byte0]: 54

 1717 12:23:13.463341                           [Byte1]: 54

 1718 12:23:13.463851  

 1719 12:23:13.466361  Set Vref, RX VrefLevel [Byte0]: 55

 1720 12:23:13.470161                           [Byte1]: 55

 1721 12:23:13.470623  

 1722 12:23:13.473471  Set Vref, RX VrefLevel [Byte0]: 56

 1723 12:23:13.476699                           [Byte1]: 56

 1724 12:23:13.480926  

 1725 12:23:13.481345  Set Vref, RX VrefLevel [Byte0]: 57

 1726 12:23:13.484353                           [Byte1]: 57

 1727 12:23:13.488261  

 1728 12:23:13.488690  Set Vref, RX VrefLevel [Byte0]: 58

 1729 12:23:13.492030                           [Byte1]: 58

 1730 12:23:13.495686  

 1731 12:23:13.496296  Set Vref, RX VrefLevel [Byte0]: 59

 1732 12:23:13.499517                           [Byte1]: 59

 1733 12:23:13.503559  

 1734 12:23:13.504212  Set Vref, RX VrefLevel [Byte0]: 60

 1735 12:23:13.506825                           [Byte1]: 60

 1736 12:23:13.511182  

 1737 12:23:13.511601  Set Vref, RX VrefLevel [Byte0]: 61

 1738 12:23:13.514866                           [Byte1]: 61

 1739 12:23:13.518699  

 1740 12:23:13.519150  Set Vref, RX VrefLevel [Byte0]: 62

 1741 12:23:13.522073                           [Byte1]: 62

 1742 12:23:13.526360  

 1743 12:23:13.526929  Set Vref, RX VrefLevel [Byte0]: 63

 1744 12:23:13.530042                           [Byte1]: 63

 1745 12:23:13.533800  

 1746 12:23:13.534261  Set Vref, RX VrefLevel [Byte0]: 64

 1747 12:23:13.537265                           [Byte1]: 64

 1748 12:23:13.541281  

 1749 12:23:13.541757  Set Vref, RX VrefLevel [Byte0]: 65

 1750 12:23:13.544768                           [Byte1]: 65

 1751 12:23:13.548975  

 1752 12:23:13.552259  Set Vref, RX VrefLevel [Byte0]: 66

 1753 12:23:13.552682                           [Byte1]: 66

 1754 12:23:13.556265  

 1755 12:23:13.556709  Set Vref, RX VrefLevel [Byte0]: 67

 1756 12:23:13.560164                           [Byte1]: 67

 1757 12:23:13.564252  

 1758 12:23:13.564670  Set Vref, RX VrefLevel [Byte0]: 68

 1759 12:23:13.567635                           [Byte1]: 68

 1760 12:23:13.571773  

 1761 12:23:13.572387  Set Vref, RX VrefLevel [Byte0]: 69

 1762 12:23:13.575041                           [Byte1]: 69

 1763 12:23:13.579533  

 1764 12:23:13.580230  Set Vref, RX VrefLevel [Byte0]: 70

 1765 12:23:13.582707                           [Byte1]: 70

 1766 12:23:13.587047  

 1767 12:23:13.587814  Set Vref, RX VrefLevel [Byte0]: 71

 1768 12:23:13.590387                           [Byte1]: 71

 1769 12:23:13.594289  

 1770 12:23:13.594925  Set Vref, RX VrefLevel [Byte0]: 72

 1771 12:23:13.597840                           [Byte1]: 72

 1772 12:23:13.602220  

 1773 12:23:13.602901  Set Vref, RX VrefLevel [Byte0]: 73

 1774 12:23:13.605407                           [Byte1]: 73

 1775 12:23:13.609686  

 1776 12:23:13.610327  Set Vref, RX VrefLevel [Byte0]: 74

 1777 12:23:13.613145                           [Byte1]: 74

 1778 12:23:13.617728  

 1779 12:23:13.618405  Set Vref, RX VrefLevel [Byte0]: 75

 1780 12:23:13.620689                           [Byte1]: 75

 1781 12:23:13.625078  

 1782 12:23:13.625719  Final RX Vref Byte 0 = 55 to rank0

 1783 12:23:13.628232  Final RX Vref Byte 1 = 64 to rank0

 1784 12:23:13.631793  Final RX Vref Byte 0 = 55 to rank1

 1785 12:23:13.635245  Final RX Vref Byte 1 = 64 to rank1==

 1786 12:23:13.638054  Dram Type= 6, Freq= 0, CH_1, rank 0

 1787 12:23:13.644589  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1788 12:23:13.645019  ==

 1789 12:23:13.645458  DQS Delay:

 1790 12:23:13.647815  DQS0 = 0, DQS1 = 0

 1791 12:23:13.648230  DQM Delay:

 1792 12:23:13.648666  DQM0 = 86, DQM1 = 79

 1793 12:23:13.651291  DQ Delay:

 1794 12:23:13.654697  DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84

 1795 12:23:13.657677  DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80

 1796 12:23:13.660756  DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68

 1797 12:23:13.664076  DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88

 1798 12:23:13.664342  

 1799 12:23:13.664519  

 1800 12:23:13.670647  [DQSOSCAuto] RK0, (LSB)MR18= 0x3420, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps

 1801 12:23:13.673780  CH1 RK0: MR19=606, MR18=3420

 1802 12:23:13.680360  CH1_RK0: MR19=0x606, MR18=0x3420, DQSOSC=396, MR23=63, INC=94, DEC=62

 1803 12:23:13.680444  

 1804 12:23:13.683893  ----->DramcWriteLeveling(PI) begin...

 1805 12:23:13.683974  ==

 1806 12:23:13.687361  Dram Type= 6, Freq= 0, CH_1, rank 1

 1807 12:23:13.690591  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1808 12:23:13.690688  ==

 1809 12:23:13.694022  Write leveling (Byte 0): 28 => 28

 1810 12:23:13.697144  Write leveling (Byte 1): 29 => 29

 1811 12:23:13.700458  DramcWriteLeveling(PI) end<-----

 1812 12:23:13.700538  

 1813 12:23:13.700601  ==

 1814 12:23:13.704076  Dram Type= 6, Freq= 0, CH_1, rank 1

 1815 12:23:13.707305  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1816 12:23:13.710781  ==

 1817 12:23:13.710853  [Gating] SW mode calibration

 1818 12:23:13.716912  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1819 12:23:13.724019  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1820 12:23:13.726864   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1821 12:23:13.733767   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1822 12:23:13.737240   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1823 12:23:13.740453   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1824 12:23:13.746866   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1825 12:23:13.750300   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1826 12:23:13.753639   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1827 12:23:13.760138   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1828 12:23:13.763576   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1829 12:23:13.766607   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1830 12:23:13.773180   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1831 12:23:13.776548   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1832 12:23:13.779738   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1833 12:23:13.786824   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1834 12:23:13.790112   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1835 12:23:13.793176   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1836 12:23:13.800008   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1837 12:23:13.803178   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1838 12:23:13.806729   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1839 12:23:13.810046   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1840 12:23:13.816412   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1841 12:23:13.819589   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1842 12:23:13.823002   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1843 12:23:13.830069   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1844 12:23:13.833216   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1845 12:23:13.836527   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1846 12:23:13.843213   0  9  8 | B1->B0 | 3131 2828 | 1 0 | (1 1) (0 0)

 1847 12:23:13.846334   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1848 12:23:13.849805   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1849 12:23:13.856531   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1850 12:23:13.859737   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1851 12:23:13.862972   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1852 12:23:13.869762   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1853 12:23:13.873000   0 10  4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 1854 12:23:13.876355   0 10  8 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (1 0)

 1855 12:23:13.883383   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1856 12:23:13.886362   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1857 12:23:13.889808   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1858 12:23:13.896302   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1859 12:23:13.899486   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1860 12:23:13.902602   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1861 12:23:13.909377   0 11  4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)

 1862 12:23:13.912667   0 11  8 | B1->B0 | 4141 3535 | 0 0 | (0 0) (1 1)

 1863 12:23:13.916432   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1864 12:23:13.922819   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1865 12:23:13.926447   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1866 12:23:13.929461   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1867 12:23:13.935843   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1868 12:23:13.939340   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1869 12:23:13.942496   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1870 12:23:13.945964   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 1871 12:23:13.952998   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1872 12:23:13.955867   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1873 12:23:13.959253   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1874 12:23:13.966655   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1875 12:23:13.969141   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1876 12:23:13.972647   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1877 12:23:13.979203   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1878 12:23:13.982575   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1879 12:23:13.985766   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1880 12:23:13.992886   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1881 12:23:13.996290   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1882 12:23:13.999711   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1883 12:23:14.006493   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1884 12:23:14.009606   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1885 12:23:14.012852   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 1886 12:23:14.019799   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1887 12:23:14.020251  Total UI for P1: 0, mck2ui 16

 1888 12:23:14.026171  best dqsien dly found for B1: ( 0, 14,  4)

 1889 12:23:14.029363   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1890 12:23:14.032954  Total UI for P1: 0, mck2ui 16

 1891 12:23:14.035954  best dqsien dly found for B0: ( 0, 14,  8)

 1892 12:23:14.039258  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1893 12:23:14.042729  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1894 12:23:14.042953  

 1895 12:23:14.045495  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1896 12:23:14.049135  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1897 12:23:14.052684  [Gating] SW calibration Done

 1898 12:23:14.052842  ==

 1899 12:23:14.055593  Dram Type= 6, Freq= 0, CH_1, rank 1

 1900 12:23:14.059182  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1901 12:23:14.062242  ==

 1902 12:23:14.062385  RX Vref Scan: 0

 1903 12:23:14.062513  

 1904 12:23:14.065804  RX Vref 0 -> 0, step: 1

 1905 12:23:14.065905  

 1906 12:23:14.069090  RX Delay -130 -> 252, step: 16

 1907 12:23:14.072593  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1908 12:23:14.075535  iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224

 1909 12:23:14.078681  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1910 12:23:14.082084  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1911 12:23:14.088914  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1912 12:23:14.092096  iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240

 1913 12:23:14.095835  iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240

 1914 12:23:14.099207  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

 1915 12:23:14.102796  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1916 12:23:14.109169  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1917 12:23:14.112012  iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256

 1918 12:23:14.115786  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1919 12:23:14.119218  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1920 12:23:14.122201  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1921 12:23:14.129084  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1922 12:23:14.132656  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1923 12:23:14.133138  ==

 1924 12:23:14.135900  Dram Type= 6, Freq= 0, CH_1, rank 1

 1925 12:23:14.139283  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1926 12:23:14.140025  ==

 1927 12:23:14.142523  DQS Delay:

 1928 12:23:14.142991  DQS0 = 0, DQS1 = 0

 1929 12:23:14.143351  DQM Delay:

 1930 12:23:14.146152  DQM0 = 86, DQM1 = 78

 1931 12:23:14.146728  DQ Delay:

 1932 12:23:14.148661  DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85

 1933 12:23:14.151943  DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85

 1934 12:23:14.155213  DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69

 1935 12:23:14.158862  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1936 12:23:14.159423  

 1937 12:23:14.160029  

 1938 12:23:14.162466  ==

 1939 12:23:14.162954  Dram Type= 6, Freq= 0, CH_1, rank 1

 1940 12:23:14.168427  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1941 12:23:14.168890  ==

 1942 12:23:14.169315  

 1943 12:23:14.169703  

 1944 12:23:14.171862  	TX Vref Scan disable

 1945 12:23:14.172321   == TX Byte 0 ==

 1946 12:23:14.175016  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1947 12:23:14.182025  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1948 12:23:14.182578   == TX Byte 1 ==

 1949 12:23:14.188260  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1950 12:23:14.191376  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1951 12:23:14.191868  ==

 1952 12:23:14.194886  Dram Type= 6, Freq= 0, CH_1, rank 1

 1953 12:23:14.198189  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1954 12:23:14.198743  ==

 1955 12:23:14.211710  TX Vref=22, minBit 1, minWin=27, winSum=444

 1956 12:23:14.214787  TX Vref=24, minBit 9, minWin=26, winSum=446

 1957 12:23:14.218380  TX Vref=26, minBit 9, minWin=27, winSum=449

 1958 12:23:14.221726  TX Vref=28, minBit 9, minWin=27, winSum=452

 1959 12:23:14.225016  TX Vref=30, minBit 8, minWin=27, winSum=452

 1960 12:23:14.232013  TX Vref=32, minBit 8, minWin=27, winSum=448

 1961 12:23:14.235056  [TxChooseVref] Worse bit 9, Min win 27, Win sum 452, Final Vref 28

 1962 12:23:14.235613  

 1963 12:23:14.238369  Final TX Range 1 Vref 28

 1964 12:23:14.238823  

 1965 12:23:14.239180  ==

 1966 12:23:14.241490  Dram Type= 6, Freq= 0, CH_1, rank 1

 1967 12:23:14.244932  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1968 12:23:14.247987  ==

 1969 12:23:14.248469  

 1970 12:23:14.248832  

 1971 12:23:14.249167  	TX Vref Scan disable

 1972 12:23:14.252004   == TX Byte 0 ==

 1973 12:23:14.254829  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1974 12:23:14.258704  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1975 12:23:14.261775   == TX Byte 1 ==

 1976 12:23:14.264978  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1977 12:23:14.271672  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1978 12:23:14.272231  

 1979 12:23:14.272619  [DATLAT]

 1980 12:23:14.272963  Freq=800, CH1 RK1

 1981 12:23:14.273303  

 1982 12:23:14.274842  DATLAT Default: 0xa

 1983 12:23:14.275299  0, 0xFFFF, sum = 0

 1984 12:23:14.278303  1, 0xFFFF, sum = 0

 1985 12:23:14.281323  2, 0xFFFF, sum = 0

 1986 12:23:14.281797  3, 0xFFFF, sum = 0

 1987 12:23:14.284915  4, 0xFFFF, sum = 0

 1988 12:23:14.285349  5, 0xFFFF, sum = 0

 1989 12:23:14.287976  6, 0xFFFF, sum = 0

 1990 12:23:14.288408  7, 0xFFFF, sum = 0

 1991 12:23:14.291482  8, 0xFFFF, sum = 0

 1992 12:23:14.291954  9, 0x0, sum = 1

 1993 12:23:14.294857  10, 0x0, sum = 2

 1994 12:23:14.295407  11, 0x0, sum = 3

 1995 12:23:14.295919  12, 0x0, sum = 4

 1996 12:23:14.297730  best_step = 10

 1997 12:23:14.298156  

 1998 12:23:14.298592  ==

 1999 12:23:14.301077  Dram Type= 6, Freq= 0, CH_1, rank 1

 2000 12:23:14.304493  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2001 12:23:14.304923  ==

 2002 12:23:14.307793  RX Vref Scan: 0

 2003 12:23:14.308221  

 2004 12:23:14.311390  RX Vref 0 -> 0, step: 1

 2005 12:23:14.311979  

 2006 12:23:14.312428  RX Delay -95 -> 252, step: 8

 2007 12:23:14.318531  iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232

 2008 12:23:14.321384  iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224

 2009 12:23:14.324656  iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232

 2010 12:23:14.328465  iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216

 2011 12:23:14.331215  iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232

 2012 12:23:14.338290  iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224

 2013 12:23:14.341600  iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232

 2014 12:23:14.344769  iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232

 2015 12:23:14.347937  iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232

 2016 12:23:14.354427  iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232

 2017 12:23:14.357737  iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232

 2018 12:23:14.361106  iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232

 2019 12:23:14.364453  iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232

 2020 12:23:14.367937  iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232

 2021 12:23:14.374214  iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232

 2022 12:23:14.377771  iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240

 2023 12:23:14.378344  ==

 2024 12:23:14.381094  Dram Type= 6, Freq= 0, CH_1, rank 1

 2025 12:23:14.384156  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2026 12:23:14.384630  ==

 2027 12:23:14.387658  DQS Delay:

 2028 12:23:14.388170  DQS0 = 0, DQS1 = 0

 2029 12:23:14.388651  DQM Delay:

 2030 12:23:14.390983  DQM0 = 87, DQM1 = 78

 2031 12:23:14.391438  DQ Delay:

 2032 12:23:14.394017  DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84

 2033 12:23:14.397530  DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84

 2034 12:23:14.400699  DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68

 2035 12:23:14.403871  DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88

 2036 12:23:14.404419  

 2037 12:23:14.404789  

 2038 12:23:14.413772  [DQSOSCAuto] RK1, (LSB)MR18= 0x1911, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps

 2039 12:23:14.417364  CH1 RK1: MR19=606, MR18=1911

 2040 12:23:14.423544  CH1_RK1: MR19=0x606, MR18=0x1911, DQSOSC=403, MR23=63, INC=90, DEC=60

 2041 12:23:14.424007  [RxdqsGatingPostProcess] freq 800

 2042 12:23:14.430479  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2043 12:23:14.433490  Pre-setting of DQS Precalculation

 2044 12:23:14.440220  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2045 12:23:14.447527  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2046 12:23:14.453324  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2047 12:23:14.453839  

 2048 12:23:14.454166  

 2049 12:23:14.457170  [Calibration Summary] 1600 Mbps

 2050 12:23:14.457586  CH 0, Rank 0

 2051 12:23:14.459824  SW Impedance     : PASS

 2052 12:23:14.463602  DUTY Scan        : NO K

 2053 12:23:14.464244  ZQ Calibration   : PASS

 2054 12:23:14.466728  Jitter Meter     : NO K

 2055 12:23:14.467283  CBT Training     : PASS

 2056 12:23:14.470282  Write leveling   : PASS

 2057 12:23:14.473293  RX DQS gating    : PASS

 2058 12:23:14.473751  RX DQ/DQS(RDDQC) : PASS

 2059 12:23:14.476516  TX DQ/DQS        : PASS

 2060 12:23:14.479949  RX DATLAT        : PASS

 2061 12:23:14.480407  RX DQ/DQS(Engine): PASS

 2062 12:23:14.483569  TX OE            : NO K

 2063 12:23:14.484084  All Pass.

 2064 12:23:14.484448  

 2065 12:23:14.486463  CH 0, Rank 1

 2066 12:23:14.486970  SW Impedance     : PASS

 2067 12:23:14.489760  DUTY Scan        : NO K

 2068 12:23:14.493116  ZQ Calibration   : PASS

 2069 12:23:14.493674  Jitter Meter     : NO K

 2070 12:23:14.496443  CBT Training     : PASS

 2071 12:23:14.499488  Write leveling   : PASS

 2072 12:23:14.500085  RX DQS gating    : PASS

 2073 12:23:14.502917  RX DQ/DQS(RDDQC) : PASS

 2074 12:23:14.506848  TX DQ/DQS        : PASS

 2075 12:23:14.507399  RX DATLAT        : PASS

 2076 12:23:14.509655  RX DQ/DQS(Engine): PASS

 2077 12:23:14.513268  TX OE            : NO K

 2078 12:23:14.513725  All Pass.

 2079 12:23:14.514085  

 2080 12:23:14.514420  CH 1, Rank 0

 2081 12:23:14.516426  SW Impedance     : PASS

 2082 12:23:14.519847  DUTY Scan        : NO K

 2083 12:23:14.520261  ZQ Calibration   : PASS

 2084 12:23:14.522808  Jitter Meter     : NO K

 2085 12:23:14.523219  CBT Training     : PASS

 2086 12:23:14.526038  Write leveling   : PASS

 2087 12:23:14.529696  RX DQS gating    : PASS

 2088 12:23:14.530131  RX DQ/DQS(RDDQC) : PASS

 2089 12:23:14.532762  TX DQ/DQS        : PASS

 2090 12:23:14.536057  RX DATLAT        : PASS

 2091 12:23:14.536470  RX DQ/DQS(Engine): PASS

 2092 12:23:14.539164  TX OE            : NO K

 2093 12:23:14.539770  All Pass.

 2094 12:23:14.540230  

 2095 12:23:14.542794  CH 1, Rank 1

 2096 12:23:14.543201  SW Impedance     : PASS

 2097 12:23:14.546040  DUTY Scan        : NO K

 2098 12:23:14.549326  ZQ Calibration   : PASS

 2099 12:23:14.549740  Jitter Meter     : NO K

 2100 12:23:14.552753  CBT Training     : PASS

 2101 12:23:14.555956  Write leveling   : PASS

 2102 12:23:14.556367  RX DQS gating    : PASS

 2103 12:23:14.559493  RX DQ/DQS(RDDQC) : PASS

 2104 12:23:14.562510  TX DQ/DQS        : PASS

 2105 12:23:14.562952  RX DATLAT        : PASS

 2106 12:23:14.565907  RX DQ/DQS(Engine): PASS

 2107 12:23:14.569001  TX OE            : NO K

 2108 12:23:14.569423  All Pass.

 2109 12:23:14.569752  

 2110 12:23:14.570056  DramC Write-DBI off

 2111 12:23:14.572361  	PER_BANK_REFRESH: Hybrid Mode

 2112 12:23:14.575602  TX_TRACKING: ON

 2113 12:23:14.579350  [GetDramInforAfterCalByMRR] Vendor 6.

 2114 12:23:14.582750  [GetDramInforAfterCalByMRR] Revision 606.

 2115 12:23:14.585698  [GetDramInforAfterCalByMRR] Revision 2 0.

 2116 12:23:14.586135  MR0 0x3b3b

 2117 12:23:14.588893  MR8 0x5151

 2118 12:23:14.592464  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2119 12:23:14.592882  

 2120 12:23:14.593211  MR0 0x3b3b

 2121 12:23:14.593516  MR8 0x5151

 2122 12:23:14.598979  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2123 12:23:14.599395  

 2124 12:23:14.605417  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2125 12:23:14.609191  [FAST_K] Save calibration result to emmc

 2126 12:23:14.611934  [FAST_K] Save calibration result to emmc

 2127 12:23:14.615390  dram_init: config_dvfs: 1

 2128 12:23:14.618794  dramc_set_vcore_voltage set vcore to 662500

 2129 12:23:14.622626  Read voltage for 1200, 2

 2130 12:23:14.623192  Vio18 = 0

 2131 12:23:14.626026  Vcore = 662500

 2132 12:23:14.626701  Vdram = 0

 2133 12:23:14.627048  Vddq = 0

 2134 12:23:14.629018  Vmddr = 0

 2135 12:23:14.632032  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2136 12:23:14.638776  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2137 12:23:14.639193  MEM_TYPE=3, freq_sel=15

 2138 12:23:14.642028  sv_algorithm_assistance_LP4_1600 

 2139 12:23:14.648279  ============ PULL DRAM RESETB DOWN ============

 2140 12:23:14.651666  ========== PULL DRAM RESETB DOWN end =========

 2141 12:23:14.655262  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2142 12:23:14.658634  =================================== 

 2143 12:23:14.662142  LPDDR4 DRAM CONFIGURATION

 2144 12:23:14.665990  =================================== 

 2145 12:23:14.666547  EX_ROW_EN[0]    = 0x0

 2146 12:23:14.668703  EX_ROW_EN[1]    = 0x0

 2147 12:23:14.671787  LP4Y_EN      = 0x0

 2148 12:23:14.672244  WORK_FSP     = 0x0

 2149 12:23:14.674822  WL           = 0x4

 2150 12:23:14.675282  RL           = 0x4

 2151 12:23:14.678299  BL           = 0x2

 2152 12:23:14.678750  RPST         = 0x0

 2153 12:23:14.681411  RD_PRE       = 0x0

 2154 12:23:14.681822  WR_PRE       = 0x1

 2155 12:23:14.685270  WR_PST       = 0x0

 2156 12:23:14.685915  DBI_WR       = 0x0

 2157 12:23:14.688501  DBI_RD       = 0x0

 2158 12:23:14.688956  OTF          = 0x1

 2159 12:23:14.691577  =================================== 

 2160 12:23:14.695469  =================================== 

 2161 12:23:14.698399  ANA top config

 2162 12:23:14.701565  =================================== 

 2163 12:23:14.701983  DLL_ASYNC_EN            =  0

 2164 12:23:14.705025  ALL_SLAVE_EN            =  0

 2165 12:23:14.708331  NEW_RANK_MODE           =  1

 2166 12:23:14.711427  DLL_IDLE_MODE           =  1

 2167 12:23:14.714626  LP45_APHY_COMB_EN       =  1

 2168 12:23:14.715100  TX_ODT_DIS              =  1

 2169 12:23:14.717955  NEW_8X_MODE             =  1

 2170 12:23:14.721270  =================================== 

 2171 12:23:14.724341  =================================== 

 2172 12:23:14.728434  data_rate                  = 2400

 2173 12:23:14.731228  CKR                        = 1

 2174 12:23:14.734758  DQ_P2S_RATIO               = 8

 2175 12:23:14.738021  =================================== 

 2176 12:23:14.741430  CA_P2S_RATIO               = 8

 2177 12:23:14.741847  DQ_CA_OPEN                 = 0

 2178 12:23:14.744612  DQ_SEMI_OPEN               = 0

 2179 12:23:14.747863  CA_SEMI_OPEN               = 0

 2180 12:23:14.751205  CA_FULL_RATE               = 0

 2181 12:23:14.754207  DQ_CKDIV4_EN               = 0

 2182 12:23:14.758222  CA_CKDIV4_EN               = 0

 2183 12:23:14.758660  CA_PREDIV_EN               = 0

 2184 12:23:14.761701  PH8_DLY                    = 17

 2185 12:23:14.764299  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2186 12:23:14.767937  DQ_AAMCK_DIV               = 4

 2187 12:23:14.771301  CA_AAMCK_DIV               = 4

 2188 12:23:14.774359  CA_ADMCK_DIV               = 4

 2189 12:23:14.774875  DQ_TRACK_CA_EN             = 0

 2190 12:23:14.777939  CA_PICK                    = 1200

 2191 12:23:14.780922  CA_MCKIO                   = 1200

 2192 12:23:14.784579  MCKIO_SEMI                 = 0

 2193 12:23:14.787718  PLL_FREQ                   = 2366

 2194 12:23:14.791030  DQ_UI_PI_RATIO             = 32

 2195 12:23:14.794017  CA_UI_PI_RATIO             = 0

 2196 12:23:14.797432  =================================== 

 2197 12:23:14.800475  =================================== 

 2198 12:23:14.800888  memory_type:LPDDR4         

 2199 12:23:14.803870  GP_NUM     : 10       

 2200 12:23:14.807373  SRAM_EN    : 1       

 2201 12:23:14.807830  MD32_EN    : 0       

 2202 12:23:14.810689  =================================== 

 2203 12:23:14.814128  [ANA_INIT] >>>>>>>>>>>>>> 

 2204 12:23:14.817259  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2205 12:23:14.820487  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2206 12:23:14.823700  =================================== 

 2207 12:23:14.827068  data_rate = 2400,PCW = 0X5b00

 2208 12:23:14.830643  =================================== 

 2209 12:23:14.833797  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2210 12:23:14.837359  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2211 12:23:14.843362  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2212 12:23:14.846233  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2213 12:23:14.849925  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2214 12:23:14.853021  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2215 12:23:14.856506  [ANA_INIT] flow start 

 2216 12:23:14.860123  [ANA_INIT] PLL >>>>>>>> 

 2217 12:23:14.860203  [ANA_INIT] PLL <<<<<<<< 

 2218 12:23:14.863067  [ANA_INIT] MIDPI >>>>>>>> 

 2219 12:23:14.866526  [ANA_INIT] MIDPI <<<<<<<< 

 2220 12:23:14.869565  [ANA_INIT] DLL >>>>>>>> 

 2221 12:23:14.869645  [ANA_INIT] DLL <<<<<<<< 

 2222 12:23:14.873150  [ANA_INIT] flow end 

 2223 12:23:14.876128  ============ LP4 DIFF to SE enter ============

 2224 12:23:14.879646  ============ LP4 DIFF to SE exit  ============

 2225 12:23:14.883064  [ANA_INIT] <<<<<<<<<<<<< 

 2226 12:23:14.886078  [Flow] Enable top DCM control >>>>> 

 2227 12:23:14.889165  [Flow] Enable top DCM control <<<<< 

 2228 12:23:14.892670  Enable DLL master slave shuffle 

 2229 12:23:14.899537  ============================================================== 

 2230 12:23:14.899619  Gating Mode config

 2231 12:23:14.905748  ============================================================== 

 2232 12:23:14.905829  Config description: 

 2233 12:23:14.915833  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2234 12:23:14.922407  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2235 12:23:14.929095  SELPH_MODE            0: By rank         1: By Phase 

 2236 12:23:14.935687  ============================================================== 

 2237 12:23:14.935814  GAT_TRACK_EN                 =  1

 2238 12:23:14.938862  RX_GATING_MODE               =  2

 2239 12:23:14.942749  RX_GATING_TRACK_MODE         =  2

 2240 12:23:14.945318  SELPH_MODE                   =  1

 2241 12:23:14.948678  PICG_EARLY_EN                =  1

 2242 12:23:14.952087  VALID_LAT_VALUE              =  1

 2243 12:23:14.958974  ============================================================== 

 2244 12:23:14.961865  Enter into Gating configuration >>>> 

 2245 12:23:14.965536  Exit from Gating configuration <<<< 

 2246 12:23:14.968893  Enter into  DVFS_PRE_config >>>>> 

 2247 12:23:14.978450  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2248 12:23:14.981676  Exit from  DVFS_PRE_config <<<<< 

 2249 12:23:14.985123  Enter into PICG configuration >>>> 

 2250 12:23:14.988899  Exit from PICG configuration <<<< 

 2251 12:23:14.991700  [RX_INPUT] configuration >>>>> 

 2252 12:23:14.991816  [RX_INPUT] configuration <<<<< 

 2253 12:23:14.998393  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2254 12:23:15.005132  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2255 12:23:15.011677  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2256 12:23:15.014895  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2257 12:23:15.021926  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2258 12:23:15.028337  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2259 12:23:15.031663  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2260 12:23:15.034940  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2261 12:23:15.042563  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2262 12:23:15.044702  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2263 12:23:15.048355  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2264 12:23:15.054746  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2265 12:23:15.058511  =================================== 

 2266 12:23:15.058593  LPDDR4 DRAM CONFIGURATION

 2267 12:23:15.061541  =================================== 

 2268 12:23:15.064951  EX_ROW_EN[0]    = 0x0

 2269 12:23:15.065031  EX_ROW_EN[1]    = 0x0

 2270 12:23:15.067839  LP4Y_EN      = 0x0

 2271 12:23:15.071261  WORK_FSP     = 0x0

 2272 12:23:15.071355  WL           = 0x4

 2273 12:23:15.074585  RL           = 0x4

 2274 12:23:15.074665  BL           = 0x2

 2275 12:23:15.078124  RPST         = 0x0

 2276 12:23:15.078204  RD_PRE       = 0x0

 2277 12:23:15.081365  WR_PRE       = 0x1

 2278 12:23:15.081448  WR_PST       = 0x0

 2279 12:23:15.084525  DBI_WR       = 0x0

 2280 12:23:15.084643  DBI_RD       = 0x0

 2281 12:23:15.087999  OTF          = 0x1

 2282 12:23:15.091615  =================================== 

 2283 12:23:15.094694  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2284 12:23:15.097866  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2285 12:23:15.104296  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2286 12:23:15.107619  =================================== 

 2287 12:23:15.107700  LPDDR4 DRAM CONFIGURATION

 2288 12:23:15.110960  =================================== 

 2289 12:23:15.114306  EX_ROW_EN[0]    = 0x10

 2290 12:23:15.117645  EX_ROW_EN[1]    = 0x0

 2291 12:23:15.117726  LP4Y_EN      = 0x0

 2292 12:23:15.121198  WORK_FSP     = 0x0

 2293 12:23:15.121278  WL           = 0x4

 2294 12:23:15.124385  RL           = 0x4

 2295 12:23:15.124465  BL           = 0x2

 2296 12:23:15.127521  RPST         = 0x0

 2297 12:23:15.127601  RD_PRE       = 0x0

 2298 12:23:15.130941  WR_PRE       = 0x1

 2299 12:23:15.131022  WR_PST       = 0x0

 2300 12:23:15.133961  DBI_WR       = 0x0

 2301 12:23:15.134040  DBI_RD       = 0x0

 2302 12:23:15.137710  OTF          = 0x1

 2303 12:23:15.140775  =================================== 

 2304 12:23:15.147195  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2305 12:23:15.147275  ==

 2306 12:23:15.150784  Dram Type= 6, Freq= 0, CH_0, rank 0

 2307 12:23:15.154013  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2308 12:23:15.154093  ==

 2309 12:23:15.157390  [Duty_Offset_Calibration]

 2310 12:23:15.157469  	B0:1	B1:-1	CA:0

 2311 12:23:15.157531  

 2312 12:23:15.160752  [DutyScan_Calibration_Flow] k_type=0

 2313 12:23:15.170478  

 2314 12:23:15.170558  ==CLK 0==

 2315 12:23:15.173929  Final CLK duty delay cell = 0

 2316 12:23:15.177707  [0] MAX Duty = 5125%(X100), DQS PI = 22

 2317 12:23:15.180514  [0] MIN Duty = 4875%(X100), DQS PI = 8

 2318 12:23:15.180594  [0] AVG Duty = 5000%(X100)

 2319 12:23:15.183959  

 2320 12:23:15.184038  CH0 CLK Duty spec in!! Max-Min= 250%

 2321 12:23:15.190746  [DutyScan_Calibration_Flow] ====Done====

 2322 12:23:15.190826  

 2323 12:23:15.193771  [DutyScan_Calibration_Flow] k_type=1

 2324 12:23:15.208294  

 2325 12:23:15.208374  ==DQS 0 ==

 2326 12:23:15.211795  Final DQS duty delay cell = -4

 2327 12:23:15.215076  [-4] MAX Duty = 5062%(X100), DQS PI = 16

 2328 12:23:15.218300  [-4] MIN Duty = 4875%(X100), DQS PI = 54

 2329 12:23:15.221820  [-4] AVG Duty = 4968%(X100)

 2330 12:23:15.221900  

 2331 12:23:15.221962  ==DQS 1 ==

 2332 12:23:15.225022  Final DQS duty delay cell = -4

 2333 12:23:15.228834  [-4] MAX Duty = 5000%(X100), DQS PI = 6

 2334 12:23:15.232075  [-4] MIN Duty = 4876%(X100), DQS PI = 22

 2335 12:23:15.235032  [-4] AVG Duty = 4938%(X100)

 2336 12:23:15.235112  

 2337 12:23:15.238299  CH0 DQS 0 Duty spec in!! Max-Min= 187%

 2338 12:23:15.238379  

 2339 12:23:15.241511  CH0 DQS 1 Duty spec in!! Max-Min= 124%

 2340 12:23:15.245180  [DutyScan_Calibration_Flow] ====Done====

 2341 12:23:15.245260  

 2342 12:23:15.248026  [DutyScan_Calibration_Flow] k_type=3

 2343 12:23:15.266564  

 2344 12:23:15.266645  ==DQM 0 ==

 2345 12:23:15.269528  Final DQM duty delay cell = 0

 2346 12:23:15.273323  [0] MAX Duty = 5062%(X100), DQS PI = 18

 2347 12:23:15.276491  [0] MIN Duty = 4875%(X100), DQS PI = 8

 2348 12:23:15.279425  [0] AVG Duty = 4968%(X100)

 2349 12:23:15.279505  

 2350 12:23:15.279569  ==DQM 1 ==

 2351 12:23:15.283039  Final DQM duty delay cell = 4

 2352 12:23:15.286313  [4] MAX Duty = 5187%(X100), DQS PI = 14

 2353 12:23:15.289379  [4] MIN Duty = 4969%(X100), DQS PI = 26

 2354 12:23:15.293159  [4] AVG Duty = 5078%(X100)

 2355 12:23:15.293239  

 2356 12:23:15.296558  CH0 DQM 0 Duty spec in!! Max-Min= 187%

 2357 12:23:15.296640  

 2358 12:23:15.299147  CH0 DQM 1 Duty spec in!! Max-Min= 218%

 2359 12:23:15.302578  [DutyScan_Calibration_Flow] ====Done====

 2360 12:23:15.302658  

 2361 12:23:15.306027  [DutyScan_Calibration_Flow] k_type=2

 2362 12:23:15.322056  

 2363 12:23:15.322137  ==DQ 0 ==

 2364 12:23:15.325687  Final DQ duty delay cell = -4

 2365 12:23:15.328691  [-4] MAX Duty = 5031%(X100), DQS PI = 22

 2366 12:23:15.332299  [-4] MIN Duty = 4907%(X100), DQS PI = 48

 2367 12:23:15.335842  [-4] AVG Duty = 4969%(X100)

 2368 12:23:15.335922  

 2369 12:23:15.335985  ==DQ 1 ==

 2370 12:23:15.338663  Final DQ duty delay cell = 0

 2371 12:23:15.342488  [0] MAX Duty = 5124%(X100), DQS PI = 54

 2372 12:23:15.345955  [0] MIN Duty = 4969%(X100), DQS PI = 42

 2373 12:23:15.348503  [0] AVG Duty = 5046%(X100)

 2374 12:23:15.348583  

 2375 12:23:15.352252  CH0 DQ 0 Duty spec in!! Max-Min= 124%

 2376 12:23:15.352333  

 2377 12:23:15.355938  CH0 DQ 1 Duty spec in!! Max-Min= 155%

 2378 12:23:15.358726  [DutyScan_Calibration_Flow] ====Done====

 2379 12:23:15.358806  ==

 2380 12:23:15.362606  Dram Type= 6, Freq= 0, CH_1, rank 0

 2381 12:23:15.365448  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2382 12:23:15.365538  ==

 2383 12:23:15.369066  [Duty_Offset_Calibration]

 2384 12:23:15.369146  	B0:-1	B1:1	CA:1

 2385 12:23:15.369209  

 2386 12:23:15.371858  [DutyScan_Calibration_Flow] k_type=0

 2387 12:23:15.382162  

 2388 12:23:15.382243  ==CLK 0==

 2389 12:23:15.385505  Final CLK duty delay cell = 0

 2390 12:23:15.388804  [0] MAX Duty = 5156%(X100), DQS PI = 22

 2391 12:23:15.392188  [0] MIN Duty = 4969%(X100), DQS PI = 60

 2392 12:23:15.395866  [0] AVG Duty = 5062%(X100)

 2393 12:23:15.395947  

 2394 12:23:15.399204  CH1 CLK Duty spec in!! Max-Min= 187%

 2395 12:23:15.402091  [DutyScan_Calibration_Flow] ====Done====

 2396 12:23:15.402170  

 2397 12:23:15.405697  [DutyScan_Calibration_Flow] k_type=1

 2398 12:23:15.421579  

 2399 12:23:15.421659  ==DQS 0 ==

 2400 12:23:15.424947  Final DQS duty delay cell = 0

 2401 12:23:15.428276  [0] MAX Duty = 5156%(X100), DQS PI = 50

 2402 12:23:15.431508  [0] MIN Duty = 4875%(X100), DQS PI = 8

 2403 12:23:15.434898  [0] AVG Duty = 5015%(X100)

 2404 12:23:15.434978  

 2405 12:23:15.435041  ==DQS 1 ==

 2406 12:23:15.438124  Final DQS duty delay cell = 0

 2407 12:23:15.441753  [0] MAX Duty = 5062%(X100), DQS PI = 12

 2408 12:23:15.444681  [0] MIN Duty = 4969%(X100), DQS PI = 56

 2409 12:23:15.447970  [0] AVG Duty = 5015%(X100)

 2410 12:23:15.448053  

 2411 12:23:15.451714  CH1 DQS 0 Duty spec in!! Max-Min= 281%

 2412 12:23:15.451829  

 2413 12:23:15.455390  CH1 DQS 1 Duty spec in!! Max-Min= 93%

 2414 12:23:15.458317  [DutyScan_Calibration_Flow] ====Done====

 2415 12:23:15.458398  

 2416 12:23:15.461187  [DutyScan_Calibration_Flow] k_type=3

 2417 12:23:15.477782  

 2418 12:23:15.477869  ==DQM 0 ==

 2419 12:23:15.480991  Final DQM duty delay cell = -4

 2420 12:23:15.484037  [-4] MAX Duty = 5062%(X100), DQS PI = 34

 2421 12:23:15.487060  [-4] MIN Duty = 4876%(X100), DQS PI = 6

 2422 12:23:15.490334  [-4] AVG Duty = 4969%(X100)

 2423 12:23:15.490415  

 2424 12:23:15.490479  ==DQM 1 ==

 2425 12:23:15.493608  Final DQM duty delay cell = 0

 2426 12:23:15.497445  [0] MAX Duty = 5156%(X100), DQS PI = 8

 2427 12:23:15.500230  [0] MIN Duty = 4969%(X100), DQS PI = 28

 2428 12:23:15.503822  [0] AVG Duty = 5062%(X100)

 2429 12:23:15.503902  

 2430 12:23:15.507034  CH1 DQM 0 Duty spec in!! Max-Min= 186%

 2431 12:23:15.507114  

 2432 12:23:15.510541  CH1 DQM 1 Duty spec in!! Max-Min= 187%

 2433 12:23:15.513705  [DutyScan_Calibration_Flow] ====Done====

 2434 12:23:15.513785  

 2435 12:23:15.516979  [DutyScan_Calibration_Flow] k_type=2

 2436 12:23:15.533886  

 2437 12:23:15.533965  ==DQ 0 ==

 2438 12:23:15.537334  Final DQ duty delay cell = 0

 2439 12:23:15.540444  [0] MAX Duty = 5156%(X100), DQS PI = 28

 2440 12:23:15.543974  [0] MIN Duty = 4907%(X100), DQS PI = 6

 2441 12:23:15.544055  [0] AVG Duty = 5031%(X100)

 2442 12:23:15.544117  

 2443 12:23:15.547382  ==DQ 1 ==

 2444 12:23:15.550697  Final DQ duty delay cell = 0

 2445 12:23:15.553906  [0] MAX Duty = 5124%(X100), DQS PI = 10

 2446 12:23:15.557009  [0] MIN Duty = 4969%(X100), DQS PI = 0

 2447 12:23:15.557090  [0] AVG Duty = 5046%(X100)

 2448 12:23:15.557154  

 2449 12:23:15.560301  CH1 DQ 0 Duty spec in!! Max-Min= 249%

 2450 12:23:15.563520  

 2451 12:23:15.567268  CH1 DQ 1 Duty spec in!! Max-Min= 155%

 2452 12:23:15.570148  [DutyScan_Calibration_Flow] ====Done====

 2453 12:23:15.573738  nWR fixed to 30

 2454 12:23:15.573820  [ModeRegInit_LP4] CH0 RK0

 2455 12:23:15.577082  [ModeRegInit_LP4] CH0 RK1

 2456 12:23:15.580113  [ModeRegInit_LP4] CH1 RK0

 2457 12:23:15.583373  [ModeRegInit_LP4] CH1 RK1

 2458 12:23:15.583453  match AC timing 7

 2459 12:23:15.586861  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2460 12:23:15.593728  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2461 12:23:15.596862  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2462 12:23:15.603717  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2463 12:23:15.606607  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2464 12:23:15.606687  ==

 2465 12:23:15.609859  Dram Type= 6, Freq= 0, CH_0, rank 0

 2466 12:23:15.613276  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2467 12:23:15.613358  ==

 2468 12:23:15.620094  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2469 12:23:15.626317  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2470 12:23:15.634023  [CA 0] Center 39 (9~70) winsize 62

 2471 12:23:15.637005  [CA 1] Center 39 (9~70) winsize 62

 2472 12:23:15.640424  [CA 2] Center 35 (5~66) winsize 62

 2473 12:23:15.643785  [CA 3] Center 35 (5~65) winsize 61

 2474 12:23:15.646886  [CA 4] Center 33 (3~64) winsize 62

 2475 12:23:15.650257  [CA 5] Center 33 (4~63) winsize 60

 2476 12:23:15.650337  

 2477 12:23:15.653663  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2478 12:23:15.653743  

 2479 12:23:15.656917  [CATrainingPosCal] consider 1 rank data

 2480 12:23:15.660331  u2DelayCellTimex100 = 270/100 ps

 2481 12:23:15.663650  CA0 delay=39 (9~70),Diff = 6 PI (28 cell)

 2482 12:23:15.667000  CA1 delay=39 (9~70),Diff = 6 PI (28 cell)

 2483 12:23:15.673673  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2484 12:23:15.676760  CA3 delay=35 (5~65),Diff = 2 PI (9 cell)

 2485 12:23:15.681243  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 2486 12:23:15.683830  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 2487 12:23:15.683911  

 2488 12:23:15.686791  CA PerBit enable=1, Macro0, CA PI delay=33

 2489 12:23:15.686871  

 2490 12:23:15.690019  [CBTSetCACLKResult] CA Dly = 33

 2491 12:23:15.690099  CS Dly: 8 (0~39)

 2492 12:23:15.693717  ==

 2493 12:23:15.696930  Dram Type= 6, Freq= 0, CH_0, rank 1

 2494 12:23:15.700749  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2495 12:23:15.700836  ==

 2496 12:23:15.703940  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2497 12:23:15.710340  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2498 12:23:15.719896  [CA 0] Center 39 (9~70) winsize 62

 2499 12:23:15.723090  [CA 1] Center 39 (9~70) winsize 62

 2500 12:23:15.726120  [CA 2] Center 35 (5~66) winsize 62

 2501 12:23:15.729458  [CA 3] Center 34 (4~65) winsize 62

 2502 12:23:15.733304  [CA 4] Center 33 (3~63) winsize 61

 2503 12:23:15.736493  [CA 5] Center 33 (3~63) winsize 61

 2504 12:23:15.736713  

 2505 12:23:15.739835  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2506 12:23:15.740126  

 2507 12:23:15.743266  [CATrainingPosCal] consider 2 rank data

 2508 12:23:15.746952  u2DelayCellTimex100 = 270/100 ps

 2509 12:23:15.749534  CA0 delay=39 (9~70),Diff = 6 PI (28 cell)

 2510 12:23:15.757007  CA1 delay=39 (9~70),Diff = 6 PI (28 cell)

 2511 12:23:15.760032  CA2 delay=35 (5~66),Diff = 2 PI (9 cell)

 2512 12:23:15.763377  CA3 delay=35 (5~65),Diff = 2 PI (9 cell)

 2513 12:23:15.766605  CA4 delay=33 (3~63),Diff = 0 PI (0 cell)

 2514 12:23:15.769740  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 2515 12:23:15.770198  

 2516 12:23:15.773021  CA PerBit enable=1, Macro0, CA PI delay=33

 2517 12:23:15.773479  

 2518 12:23:15.776407  [CBTSetCACLKResult] CA Dly = 33

 2519 12:23:15.776865  CS Dly: 8 (0~40)

 2520 12:23:15.779351  

 2521 12:23:15.782794  ----->DramcWriteLeveling(PI) begin...

 2522 12:23:15.783405  ==

 2523 12:23:15.786238  Dram Type= 6, Freq= 0, CH_0, rank 0

 2524 12:23:15.789666  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2525 12:23:15.790079  ==

 2526 12:23:15.792612  Write leveling (Byte 0): 33 => 33

 2527 12:23:15.796148  Write leveling (Byte 1): 27 => 27

 2528 12:23:15.799421  DramcWriteLeveling(PI) end<-----

 2529 12:23:15.799970  

 2530 12:23:15.800309  ==

 2531 12:23:15.802685  Dram Type= 6, Freq= 0, CH_0, rank 0

 2532 12:23:15.805744  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2533 12:23:15.806426  ==

 2534 12:23:15.809178  [Gating] SW mode calibration

 2535 12:23:15.816084  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2536 12:23:15.822864  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2537 12:23:15.825928   0 15  0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)

 2538 12:23:15.829291   0 15  4 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)

 2539 12:23:15.835814   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2540 12:23:15.839172   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2541 12:23:15.842346   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2542 12:23:15.849089   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2543 12:23:15.852495   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2544 12:23:15.856295   0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)

 2545 12:23:15.862435   1  0  0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)

 2546 12:23:15.865762   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2547 12:23:15.869392   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2548 12:23:15.875533   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2549 12:23:15.879048   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2550 12:23:15.882523   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2551 12:23:15.888753   1  0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 2552 12:23:15.892084   1  0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)

 2553 12:23:15.895420   1  1  0 | B1->B0 | 2424 4444 | 0 0 | (0 0) (0 0)

 2554 12:23:15.898801   1  1  4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

 2555 12:23:15.905865   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2556 12:23:15.908670   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2557 12:23:15.912098   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2558 12:23:15.918864   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2559 12:23:15.922320   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2560 12:23:15.925591   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2561 12:23:15.932059   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2562 12:23:15.935362   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2563 12:23:15.938741   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2564 12:23:15.945276   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2565 12:23:15.948659   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2566 12:23:15.952007   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2567 12:23:15.958669   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2568 12:23:15.962221   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2569 12:23:15.965361   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2570 12:23:15.972042   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2571 12:23:15.975260   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2572 12:23:15.978578   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2573 12:23:15.985777   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2574 12:23:15.988814   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2575 12:23:15.991830   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2576 12:23:15.998529   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2577 12:23:16.001786   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2578 12:23:16.004943  Total UI for P1: 0, mck2ui 16

 2579 12:23:16.008426  best dqsien dly found for B0: ( 1,  3, 28)

 2580 12:23:16.011638   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2581 12:23:16.015006  Total UI for P1: 0, mck2ui 16

 2582 12:23:16.018850  best dqsien dly found for B1: ( 1,  4,  0)

 2583 12:23:16.021969  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 2584 12:23:16.025382  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2585 12:23:16.025901  

 2586 12:23:16.028292  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2587 12:23:16.034874  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2588 12:23:16.035382  [Gating] SW calibration Done

 2589 12:23:16.037997  ==

 2590 12:23:16.038411  Dram Type= 6, Freq= 0, CH_0, rank 0

 2591 12:23:16.045058  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2592 12:23:16.045475  ==

 2593 12:23:16.045836  RX Vref Scan: 0

 2594 12:23:16.046152  

 2595 12:23:16.048100  RX Vref 0 -> 0, step: 1

 2596 12:23:16.048515  

 2597 12:23:16.051204  RX Delay -40 -> 252, step: 8

 2598 12:23:16.054278  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2599 12:23:16.057802  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2600 12:23:16.060999  iDelay=200, Bit 2, Center 115 (40 ~ 191) 152

 2601 12:23:16.068089  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 2602 12:23:16.071527  iDelay=200, Bit 4, Center 123 (48 ~ 199) 152

 2603 12:23:16.074979  iDelay=200, Bit 5, Center 111 (40 ~ 183) 144

 2604 12:23:16.077927  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2605 12:23:16.081024  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2606 12:23:16.087653  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2607 12:23:16.091307  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2608 12:23:16.098383  iDelay=200, Bit 10, Center 107 (32 ~ 183) 152

 2609 12:23:16.099161  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 2610 12:23:16.101150  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2611 12:23:16.107717  iDelay=200, Bit 13, Center 111 (40 ~ 183) 144

 2612 12:23:16.111072  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2613 12:23:16.114425  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 2614 12:23:16.114899  ==

 2615 12:23:16.117917  Dram Type= 6, Freq= 0, CH_0, rank 0

 2616 12:23:16.120930  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2617 12:23:16.124132  ==

 2618 12:23:16.124586  DQS Delay:

 2619 12:23:16.124947  DQS0 = 0, DQS1 = 0

 2620 12:23:16.127920  DQM Delay:

 2621 12:23:16.128377  DQM0 = 119, DQM1 = 106

 2622 12:23:16.130893  DQ Delay:

 2623 12:23:16.134777  DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115

 2624 12:23:16.137927  DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123

 2625 12:23:16.141281  DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103

 2626 12:23:16.144445  DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111

 2627 12:23:16.144901  

 2628 12:23:16.145260  

 2629 12:23:16.145597  ==

 2630 12:23:16.147861  Dram Type= 6, Freq= 0, CH_0, rank 0

 2631 12:23:16.151204  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2632 12:23:16.151659  ==

 2633 12:23:16.152068  

 2634 12:23:16.152394  

 2635 12:23:16.154261  	TX Vref Scan disable

 2636 12:23:16.158327   == TX Byte 0 ==

 2637 12:23:16.160806  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2638 12:23:16.164770  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2639 12:23:16.167390   == TX Byte 1 ==

 2640 12:23:16.170811  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 2641 12:23:16.174257  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 2642 12:23:16.174769  ==

 2643 12:23:16.177516  Dram Type= 6, Freq= 0, CH_0, rank 0

 2644 12:23:16.181161  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2645 12:23:16.184608  ==

 2646 12:23:16.194964  TX Vref=22, minBit 1, minWin=25, winSum=415

 2647 12:23:16.198570  TX Vref=24, minBit 14, minWin=25, winSum=425

 2648 12:23:16.201023  TX Vref=26, minBit 11, minWin=26, winSum=431

 2649 12:23:16.204777  TX Vref=28, minBit 5, minWin=26, winSum=432

 2650 12:23:16.208068  TX Vref=30, minBit 8, minWin=26, winSum=428

 2651 12:23:16.214339  TX Vref=32, minBit 13, minWin=25, winSum=425

 2652 12:23:16.218266  [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 28

 2653 12:23:16.218820  

 2654 12:23:16.221461  Final TX Range 1 Vref 28

 2655 12:23:16.222018  

 2656 12:23:16.222377  ==

 2657 12:23:16.224277  Dram Type= 6, Freq= 0, CH_0, rank 0

 2658 12:23:16.231021  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2659 12:23:16.231480  ==

 2660 12:23:16.231889  

 2661 12:23:16.232234  

 2662 12:23:16.232556  	TX Vref Scan disable

 2663 12:23:16.234780   == TX Byte 0 ==

 2664 12:23:16.238208  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2665 12:23:16.241794  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2666 12:23:16.244566   == TX Byte 1 ==

 2667 12:23:16.248395  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 2668 12:23:16.254343  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 2669 12:23:16.254772  

 2670 12:23:16.255143  [DATLAT]

 2671 12:23:16.255505  Freq=1200, CH0 RK0

 2672 12:23:16.255841  

 2673 12:23:16.258212  DATLAT Default: 0xd

 2674 12:23:16.261557  0, 0xFFFF, sum = 0

 2675 12:23:16.261978  1, 0xFFFF, sum = 0

 2676 12:23:16.265160  2, 0xFFFF, sum = 0

 2677 12:23:16.265696  3, 0xFFFF, sum = 0

 2678 12:23:16.267880  4, 0xFFFF, sum = 0

 2679 12:23:16.268363  5, 0xFFFF, sum = 0

 2680 12:23:16.270976  6, 0xFFFF, sum = 0

 2681 12:23:16.271487  7, 0xFFFF, sum = 0

 2682 12:23:16.274683  8, 0xFFFF, sum = 0

 2683 12:23:16.275128  9, 0xFFFF, sum = 0

 2684 12:23:16.277389  10, 0xFFFF, sum = 0

 2685 12:23:16.277827  11, 0xFFFF, sum = 0

 2686 12:23:16.281452  12, 0x0, sum = 1

 2687 12:23:16.281869  13, 0x0, sum = 2

 2688 12:23:16.284615  14, 0x0, sum = 3

 2689 12:23:16.285033  15, 0x0, sum = 4

 2690 12:23:16.287580  best_step = 13

 2691 12:23:16.288034  

 2692 12:23:16.288360  ==

 2693 12:23:16.291445  Dram Type= 6, Freq= 0, CH_0, rank 0

 2694 12:23:16.294206  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2695 12:23:16.294621  ==

 2696 12:23:16.297795  RX Vref Scan: 1

 2697 12:23:16.298303  

 2698 12:23:16.298631  Set Vref Range= 32 -> 127

 2699 12:23:16.298938  

 2700 12:23:16.301020  RX Vref 32 -> 127, step: 1

 2701 12:23:16.301468  

 2702 12:23:16.304097  RX Delay -21 -> 252, step: 4

 2703 12:23:16.304512  

 2704 12:23:16.307866  Set Vref, RX VrefLevel [Byte0]: 32

 2705 12:23:16.310667                           [Byte1]: 32

 2706 12:23:16.311078  

 2707 12:23:16.314336  Set Vref, RX VrefLevel [Byte0]: 33

 2708 12:23:16.317525                           [Byte1]: 33

 2709 12:23:16.321510  

 2710 12:23:16.322020  Set Vref, RX VrefLevel [Byte0]: 34

 2711 12:23:16.324900                           [Byte1]: 34

 2712 12:23:16.329619  

 2713 12:23:16.330145  Set Vref, RX VrefLevel [Byte0]: 35

 2714 12:23:16.332273                           [Byte1]: 35

 2715 12:23:16.336826  

 2716 12:23:16.337236  Set Vref, RX VrefLevel [Byte0]: 36

 2717 12:23:16.340338                           [Byte1]: 36

 2718 12:23:16.345227  

 2719 12:23:16.345733  Set Vref, RX VrefLevel [Byte0]: 37

 2720 12:23:16.348366                           [Byte1]: 37

 2721 12:23:16.353004  

 2722 12:23:16.353429  Set Vref, RX VrefLevel [Byte0]: 38

 2723 12:23:16.356339                           [Byte1]: 38

 2724 12:23:16.360743  

 2725 12:23:16.361154  Set Vref, RX VrefLevel [Byte0]: 39

 2726 12:23:16.364219                           [Byte1]: 39

 2727 12:23:16.369002  

 2728 12:23:16.369414  Set Vref, RX VrefLevel [Byte0]: 40

 2729 12:23:16.372440                           [Byte1]: 40

 2730 12:23:16.376671  

 2731 12:23:16.377086  Set Vref, RX VrefLevel [Byte0]: 41

 2732 12:23:16.379841                           [Byte1]: 41

 2733 12:23:16.385004  

 2734 12:23:16.385455  Set Vref, RX VrefLevel [Byte0]: 42

 2735 12:23:16.387647                           [Byte1]: 42

 2736 12:23:16.392464  

 2737 12:23:16.392879  Set Vref, RX VrefLevel [Byte0]: 43

 2738 12:23:16.396016                           [Byte1]: 43

 2739 12:23:16.400961  

 2740 12:23:16.401523  Set Vref, RX VrefLevel [Byte0]: 44

 2741 12:23:16.403849                           [Byte1]: 44

 2742 12:23:16.408246  

 2743 12:23:16.408660  Set Vref, RX VrefLevel [Byte0]: 45

 2744 12:23:16.412297                           [Byte1]: 45

 2745 12:23:16.416543  

 2746 12:23:16.417049  Set Vref, RX VrefLevel [Byte0]: 46

 2747 12:23:16.419995                           [Byte1]: 46

 2748 12:23:16.424392  

 2749 12:23:16.424850  Set Vref, RX VrefLevel [Byte0]: 47

 2750 12:23:16.427695                           [Byte1]: 47

 2751 12:23:16.432254  

 2752 12:23:16.432723  Set Vref, RX VrefLevel [Byte0]: 48

 2753 12:23:16.435401                           [Byte1]: 48

 2754 12:23:16.440245  

 2755 12:23:16.440790  Set Vref, RX VrefLevel [Byte0]: 49

 2756 12:23:16.443633                           [Byte1]: 49

 2757 12:23:16.448527  

 2758 12:23:16.449078  Set Vref, RX VrefLevel [Byte0]: 50

 2759 12:23:16.451247                           [Byte1]: 50

 2760 12:23:16.456205  

 2761 12:23:16.459654  Set Vref, RX VrefLevel [Byte0]: 51

 2762 12:23:16.462414                           [Byte1]: 51

 2763 12:23:16.462873  

 2764 12:23:16.465705  Set Vref, RX VrefLevel [Byte0]: 52

 2765 12:23:16.469098                           [Byte1]: 52

 2766 12:23:16.469553  

 2767 12:23:16.472498  Set Vref, RX VrefLevel [Byte0]: 53

 2768 12:23:16.475605                           [Byte1]: 53

 2769 12:23:16.479643  

 2770 12:23:16.480281  Set Vref, RX VrefLevel [Byte0]: 54

 2771 12:23:16.483180                           [Byte1]: 54

 2772 12:23:16.487683  

 2773 12:23:16.488168  Set Vref, RX VrefLevel [Byte0]: 55

 2774 12:23:16.491055                           [Byte1]: 55

 2775 12:23:16.495686  

 2776 12:23:16.496274  Set Vref, RX VrefLevel [Byte0]: 56

 2777 12:23:16.498809                           [Byte1]: 56

 2778 12:23:16.504137  

 2779 12:23:16.504690  Set Vref, RX VrefLevel [Byte0]: 57

 2780 12:23:16.506748                           [Byte1]: 57

 2781 12:23:16.511767  

 2782 12:23:16.512343  Set Vref, RX VrefLevel [Byte0]: 58

 2783 12:23:16.515136                           [Byte1]: 58

 2784 12:23:16.519487  

 2785 12:23:16.519990  Set Vref, RX VrefLevel [Byte0]: 59

 2786 12:23:16.522634                           [Byte1]: 59

 2787 12:23:16.527950  

 2788 12:23:16.528400  Set Vref, RX VrefLevel [Byte0]: 60

 2789 12:23:16.530577                           [Byte1]: 60

 2790 12:23:16.535335  

 2791 12:23:16.535958  Set Vref, RX VrefLevel [Byte0]: 61

 2792 12:23:16.538260                           [Byte1]: 61

 2793 12:23:16.542919  

 2794 12:23:16.543349  Set Vref, RX VrefLevel [Byte0]: 62

 2795 12:23:16.546265                           [Byte1]: 62

 2796 12:23:16.551382  

 2797 12:23:16.551940  Set Vref, RX VrefLevel [Byte0]: 63

 2798 12:23:16.554733                           [Byte1]: 63

 2799 12:23:16.559371  

 2800 12:23:16.559980  Set Vref, RX VrefLevel [Byte0]: 64

 2801 12:23:16.562156                           [Byte1]: 64

 2802 12:23:16.566969  

 2803 12:23:16.567380  Set Vref, RX VrefLevel [Byte0]: 65

 2804 12:23:16.570735                           [Byte1]: 65

 2805 12:23:16.575010  

 2806 12:23:16.575535  Set Vref, RX VrefLevel [Byte0]: 66

 2807 12:23:16.578540                           [Byte1]: 66

 2808 12:23:16.582461  

 2809 12:23:16.582931  Set Vref, RX VrefLevel [Byte0]: 67

 2810 12:23:16.585941                           [Byte1]: 67

 2811 12:23:16.590852  

 2812 12:23:16.591355  Set Vref, RX VrefLevel [Byte0]: 68

 2813 12:23:16.594133                           [Byte1]: 68

 2814 12:23:16.598519  

 2815 12:23:16.599058  Set Vref, RX VrefLevel [Byte0]: 69

 2816 12:23:16.602054                           [Byte1]: 69

 2817 12:23:16.606526  

 2818 12:23:16.607050  Set Vref, RX VrefLevel [Byte0]: 70

 2819 12:23:16.609631                           [Byte1]: 70

 2820 12:23:16.614255  

 2821 12:23:16.614661  Set Vref, RX VrefLevel [Byte0]: 71

 2822 12:23:16.617915                           [Byte1]: 71

 2823 12:23:16.622742  

 2824 12:23:16.623483  Set Vref, RX VrefLevel [Byte0]: 72

 2825 12:23:16.625735                           [Byte1]: 72

 2826 12:23:16.630287  

 2827 12:23:16.630790  Set Vref, RX VrefLevel [Byte0]: 73

 2828 12:23:16.633278                           [Byte1]: 73

 2829 12:23:16.638241  

 2830 12:23:16.638646  Set Vref, RX VrefLevel [Byte0]: 74

 2831 12:23:16.641426                           [Byte1]: 74

 2832 12:23:16.646519  

 2833 12:23:16.647067  Set Vref, RX VrefLevel [Byte0]: 75

 2834 12:23:16.649569                           [Byte1]: 75

 2835 12:23:16.654415  

 2836 12:23:16.654931  Set Vref, RX VrefLevel [Byte0]: 76

 2837 12:23:16.657778                           [Byte1]: 76

 2838 12:23:16.662043  

 2839 12:23:16.662592  Set Vref, RX VrefLevel [Byte0]: 77

 2840 12:23:16.665054                           [Byte1]: 77

 2841 12:23:16.670137  

 2842 12:23:16.670555  Set Vref, RX VrefLevel [Byte0]: 78

 2843 12:23:16.673308                           [Byte1]: 78

 2844 12:23:16.678016  

 2845 12:23:16.678539  Final RX Vref Byte 0 = 60 to rank0

 2846 12:23:16.681194  Final RX Vref Byte 1 = 56 to rank0

 2847 12:23:16.684416  Final RX Vref Byte 0 = 60 to rank1

 2848 12:23:16.687917  Final RX Vref Byte 1 = 56 to rank1==

 2849 12:23:16.691399  Dram Type= 6, Freq= 0, CH_0, rank 0

 2850 12:23:16.697956  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2851 12:23:16.698508  ==

 2852 12:23:16.698876  DQS Delay:

 2853 12:23:16.699216  DQS0 = 0, DQS1 = 0

 2854 12:23:16.700954  DQM Delay:

 2855 12:23:16.701412  DQM0 = 119, DQM1 = 108

 2856 12:23:16.704182  DQ Delay:

 2857 12:23:16.708103  DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116

 2858 12:23:16.710923  DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126

 2859 12:23:16.714778  DQ8 =96, DQ9 =96, DQ10 =112, DQ11 =102

 2860 12:23:16.718308  DQ12 =112, DQ13 =110, DQ14 =122, DQ15 =114

 2861 12:23:16.718874  

 2862 12:23:16.719236  

 2863 12:23:16.727624  [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps

 2864 12:23:16.728405  CH0 RK0: MR19=403, MR18=12FE

 2865 12:23:16.734348  CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26

 2866 12:23:16.734920  

 2867 12:23:16.738070  ----->DramcWriteLeveling(PI) begin...

 2868 12:23:16.738539  ==

 2869 12:23:16.740871  Dram Type= 6, Freq= 0, CH_0, rank 1

 2870 12:23:16.744412  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2871 12:23:16.747589  ==

 2872 12:23:16.748114  Write leveling (Byte 0): 34 => 34

 2873 12:23:16.750970  Write leveling (Byte 1): 31 => 31

 2874 12:23:16.754580  DramcWriteLeveling(PI) end<-----

 2875 12:23:16.755059  

 2876 12:23:16.755426  ==

 2877 12:23:16.757569  Dram Type= 6, Freq= 0, CH_0, rank 1

 2878 12:23:16.764227  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2879 12:23:16.764642  ==

 2880 12:23:16.767444  [Gating] SW mode calibration

 2881 12:23:16.774276  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2882 12:23:16.777763  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2883 12:23:16.783786   0 15  0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)

 2884 12:23:16.787457   0 15  4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

 2885 12:23:16.790851   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2886 12:23:16.797272   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2887 12:23:16.800671   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2888 12:23:16.804375   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2889 12:23:16.810559   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 2890 12:23:16.813751   0 15 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 2891 12:23:16.817118   1  0  0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)

 2892 12:23:16.824107   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2893 12:23:16.827378   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2894 12:23:16.830508   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2895 12:23:16.837117   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2896 12:23:16.840701   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2897 12:23:16.843580   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2898 12:23:16.846915   1  0 28 | B1->B0 | 2727 3737 | 0 0 | (0 0) (0 0)

 2899 12:23:16.853903   1  1  0 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)

 2900 12:23:16.856951   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2901 12:23:16.860476   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2902 12:23:16.866832   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2903 12:23:16.870659   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2904 12:23:16.873412   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2905 12:23:16.880023   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2906 12:23:16.883292   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2907 12:23:16.886856   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2908 12:23:16.893595   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2909 12:23:16.896737   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2910 12:23:16.899925   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2911 12:23:16.906310   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2912 12:23:16.910342   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2913 12:23:16.913260   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2914 12:23:16.919775   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2915 12:23:16.923177   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2916 12:23:16.926612   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2917 12:23:16.932911   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2918 12:23:16.936209   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2919 12:23:16.939517   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2920 12:23:16.946874   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2921 12:23:16.950075   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2922 12:23:16.952919   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2923 12:23:16.959572   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2924 12:23:16.960023  Total UI for P1: 0, mck2ui 16

 2925 12:23:16.965977  best dqsien dly found for B0: ( 1,  3, 28)

 2926 12:23:16.966503  Total UI for P1: 0, mck2ui 16

 2927 12:23:16.972919  best dqsien dly found for B1: ( 1,  3, 30)

 2928 12:23:16.976241  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 2929 12:23:16.979394  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2930 12:23:16.979879  

 2931 12:23:16.982639  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2932 12:23:16.985769  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2933 12:23:16.989016  [Gating] SW calibration Done

 2934 12:23:16.989539  ==

 2935 12:23:16.992247  Dram Type= 6, Freq= 0, CH_0, rank 1

 2936 12:23:16.995576  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2937 12:23:16.996247  ==

 2938 12:23:16.999119  RX Vref Scan: 0

 2939 12:23:16.999551  

 2940 12:23:16.999933  RX Vref 0 -> 0, step: 1

 2941 12:23:17.002670  

 2942 12:23:17.003087  RX Delay -40 -> 252, step: 8

 2943 12:23:17.008888  iDelay=200, Bit 0, Center 111 (40 ~ 183) 144

 2944 12:23:17.012334  iDelay=200, Bit 1, Center 123 (48 ~ 199) 152

 2945 12:23:17.015269  iDelay=200, Bit 2, Center 111 (40 ~ 183) 144

 2946 12:23:17.018686  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 2947 12:23:17.022263  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2948 12:23:17.028748  iDelay=200, Bit 5, Center 111 (40 ~ 183) 144

 2949 12:23:17.032711  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 2950 12:23:17.035668  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2951 12:23:17.038426  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2952 12:23:17.042183  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2953 12:23:17.045647  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 2954 12:23:17.052351  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 2955 12:23:17.055642  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2956 12:23:17.058799  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2957 12:23:17.062192  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2958 12:23:17.069040  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 2959 12:23:17.069506  ==

 2960 12:23:17.071860  Dram Type= 6, Freq= 0, CH_0, rank 1

 2961 12:23:17.075172  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2962 12:23:17.075637  ==

 2963 12:23:17.076113  DQS Delay:

 2964 12:23:17.078431  DQS0 = 0, DQS1 = 0

 2965 12:23:17.078891  DQM Delay:

 2966 12:23:17.082552  DQM0 = 116, DQM1 = 108

 2967 12:23:17.083114  DQ Delay:

 2968 12:23:17.085402  DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115

 2969 12:23:17.088343  DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123

 2970 12:23:17.092070  DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103

 2971 12:23:17.095410  DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115

 2972 12:23:17.095930  

 2973 12:23:17.096429  

 2974 12:23:17.098193  ==

 2975 12:23:17.101967  Dram Type= 6, Freq= 0, CH_0, rank 1

 2976 12:23:17.104963  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2977 12:23:17.105434  ==

 2978 12:23:17.105909  

 2979 12:23:17.106357  

 2980 12:23:17.108293  	TX Vref Scan disable

 2981 12:23:17.108760   == TX Byte 0 ==

 2982 12:23:17.111493  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2983 12:23:17.118368  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2984 12:23:17.118934   == TX Byte 1 ==

 2985 12:23:17.124661  Update DQ  dly =849 (3 ,2, 17)  DQ  OEN =(2 ,7)

 2986 12:23:17.128519  Update DQM dly =849 (3 ,2, 17)  DQM OEN =(2 ,7)

 2987 12:23:17.129082  ==

 2988 12:23:17.131815  Dram Type= 6, Freq= 0, CH_0, rank 1

 2989 12:23:17.134992  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2990 12:23:17.135556  ==

 2991 12:23:17.147139  TX Vref=22, minBit 0, minWin=26, winSum=417

 2992 12:23:17.150638  TX Vref=24, minBit 1, minWin=26, winSum=423

 2993 12:23:17.153945  TX Vref=26, minBit 8, minWin=26, winSum=427

 2994 12:23:17.157111  TX Vref=28, minBit 10, minWin=26, winSum=433

 2995 12:23:17.160753  TX Vref=30, minBit 10, minWin=26, winSum=430

 2996 12:23:17.167168  TX Vref=32, minBit 10, minWin=25, winSum=427

 2997 12:23:17.170534  [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 28

 2998 12:23:17.171109  

 2999 12:23:17.174021  Final TX Range 1 Vref 28

 3000 12:23:17.174588  

 3001 12:23:17.174956  ==

 3002 12:23:17.177248  Dram Type= 6, Freq= 0, CH_0, rank 1

 3003 12:23:17.183778  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3004 12:23:17.184339  ==

 3005 12:23:17.184799  

 3006 12:23:17.185333  

 3007 12:23:17.185824  	TX Vref Scan disable

 3008 12:23:17.187597   == TX Byte 0 ==

 3009 12:23:17.190667  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 3010 12:23:17.197200  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 3011 12:23:17.197737   == TX Byte 1 ==

 3012 12:23:17.200263  Update DQ  dly =849 (3 ,2, 17)  DQ  OEN =(2 ,7)

 3013 12:23:17.207058  Update DQM dly =849 (3 ,2, 17)  DQM OEN =(2 ,7)

 3014 12:23:17.207528  

 3015 12:23:17.207938  [DATLAT]

 3016 12:23:17.208280  Freq=1200, CH0 RK1

 3017 12:23:17.208612  

 3018 12:23:17.210431  DATLAT Default: 0xd

 3019 12:23:17.211026  0, 0xFFFF, sum = 0

 3020 12:23:17.213564  1, 0xFFFF, sum = 0

 3021 12:23:17.216975  2, 0xFFFF, sum = 0

 3022 12:23:17.217546  3, 0xFFFF, sum = 0

 3023 12:23:17.220717  4, 0xFFFF, sum = 0

 3024 12:23:17.221287  5, 0xFFFF, sum = 0

 3025 12:23:17.224024  6, 0xFFFF, sum = 0

 3026 12:23:17.224591  7, 0xFFFF, sum = 0

 3027 12:23:17.226882  8, 0xFFFF, sum = 0

 3028 12:23:17.227354  9, 0xFFFF, sum = 0

 3029 12:23:17.230645  10, 0xFFFF, sum = 0

 3030 12:23:17.231311  11, 0xFFFF, sum = 0

 3031 12:23:17.233585  12, 0x0, sum = 1

 3032 12:23:17.234275  13, 0x0, sum = 2

 3033 12:23:17.237205  14, 0x0, sum = 3

 3034 12:23:17.237821  15, 0x0, sum = 4

 3035 12:23:17.240615  best_step = 13

 3036 12:23:17.241096  

 3037 12:23:17.241458  ==

 3038 12:23:17.244118  Dram Type= 6, Freq= 0, CH_0, rank 1

 3039 12:23:17.247426  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3040 12:23:17.248043  ==

 3041 12:23:17.248409  RX Vref Scan: 0

 3042 12:23:17.248749  

 3043 12:23:17.250738  RX Vref 0 -> 0, step: 1

 3044 12:23:17.251194  

 3045 12:23:17.254014  RX Delay -21 -> 252, step: 4

 3046 12:23:17.256685  iDelay=199, Bit 0, Center 114 (47 ~ 182) 136

 3047 12:23:17.263959  iDelay=199, Bit 1, Center 118 (47 ~ 190) 144

 3048 12:23:17.266947  iDelay=199, Bit 2, Center 110 (43 ~ 178) 136

 3049 12:23:17.270705  iDelay=199, Bit 3, Center 114 (43 ~ 186) 144

 3050 12:23:17.273416  iDelay=199, Bit 4, Center 116 (47 ~ 186) 140

 3051 12:23:17.277159  iDelay=199, Bit 5, Center 110 (43 ~ 178) 136

 3052 12:23:17.283619  iDelay=199, Bit 6, Center 126 (55 ~ 198) 144

 3053 12:23:17.286738  iDelay=199, Bit 7, Center 124 (55 ~ 194) 140

 3054 12:23:17.290291  iDelay=199, Bit 8, Center 98 (31 ~ 166) 136

 3055 12:23:17.294065  iDelay=199, Bit 9, Center 94 (27 ~ 162) 136

 3056 12:23:17.296774  iDelay=199, Bit 10, Center 110 (43 ~ 178) 136

 3057 12:23:17.303796  iDelay=199, Bit 11, Center 102 (35 ~ 170) 136

 3058 12:23:17.307048  iDelay=199, Bit 12, Center 116 (51 ~ 182) 132

 3059 12:23:17.309994  iDelay=199, Bit 13, Center 116 (51 ~ 182) 132

 3060 12:23:17.313413  iDelay=199, Bit 14, Center 120 (55 ~ 186) 132

 3061 12:23:17.316407  iDelay=199, Bit 15, Center 116 (51 ~ 182) 132

 3062 12:23:17.320061  ==

 3063 12:23:17.323388  Dram Type= 6, Freq= 0, CH_0, rank 1

 3064 12:23:17.326832  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3065 12:23:17.327296  ==

 3066 12:23:17.327659  DQS Delay:

 3067 12:23:17.330240  DQS0 = 0, DQS1 = 0

 3068 12:23:17.330694  DQM Delay:

 3069 12:23:17.333642  DQM0 = 116, DQM1 = 109

 3070 12:23:17.334100  DQ Delay:

 3071 12:23:17.336559  DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114

 3072 12:23:17.340153  DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124

 3073 12:23:17.343173  DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =102

 3074 12:23:17.346668  DQ12 =116, DQ13 =116, DQ14 =120, DQ15 =116

 3075 12:23:17.347230  

 3076 12:23:17.347654  

 3077 12:23:17.356282  [DQSOSCAuto] RK1, (LSB)MR18= 0xce7, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps

 3078 12:23:17.359630  CH0 RK1: MR19=403, MR18=CE7

 3079 12:23:17.362778  CH0_RK1: MR19=0x403, MR18=0xCE7, DQSOSC=405, MR23=63, INC=39, DEC=26

 3080 12:23:17.366857  [RxdqsGatingPostProcess] freq 1200

 3081 12:23:17.372976  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3082 12:23:17.376104  best DQS0 dly(2T, 0.5T) = (0, 11)

 3083 12:23:17.379490  best DQS1 dly(2T, 0.5T) = (0, 12)

 3084 12:23:17.382817  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3085 12:23:17.386195  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3086 12:23:17.389754  best DQS0 dly(2T, 0.5T) = (0, 11)

 3087 12:23:17.392874  best DQS1 dly(2T, 0.5T) = (0, 11)

 3088 12:23:17.396085  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3089 12:23:17.396500  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3090 12:23:17.399760  Pre-setting of DQS Precalculation

 3091 12:23:17.406572  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3092 12:23:17.407120  ==

 3093 12:23:17.409821  Dram Type= 6, Freq= 0, CH_1, rank 0

 3094 12:23:17.412731  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3095 12:23:17.413193  ==

 3096 12:23:17.419899  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3097 12:23:17.426291  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3098 12:23:17.433619  [CA 0] Center 37 (7~68) winsize 62

 3099 12:23:17.436868  [CA 1] Center 37 (7~68) winsize 62

 3100 12:23:17.439961  [CA 2] Center 34 (4~64) winsize 61

 3101 12:23:17.443525  [CA 3] Center 33 (3~64) winsize 62

 3102 12:23:17.446638  [CA 4] Center 34 (4~64) winsize 61

 3103 12:23:17.450132  [CA 5] Center 33 (3~64) winsize 62

 3104 12:23:17.450694  

 3105 12:23:17.453158  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3106 12:23:17.453617  

 3107 12:23:17.456687  [CATrainingPosCal] consider 1 rank data

 3108 12:23:17.459643  u2DelayCellTimex100 = 270/100 ps

 3109 12:23:17.463305  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3110 12:23:17.470006  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3111 12:23:17.473596  CA2 delay=34 (4~64),Diff = 1 PI (4 cell)

 3112 12:23:17.476549  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 3113 12:23:17.480063  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3114 12:23:17.482844  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3115 12:23:17.483256  

 3116 12:23:17.486059  CA PerBit enable=1, Macro0, CA PI delay=33

 3117 12:23:17.486488  

 3118 12:23:17.490137  [CBTSetCACLKResult] CA Dly = 33

 3119 12:23:17.490550  CS Dly: 5 (0~36)

 3120 12:23:17.493227  ==

 3121 12:23:17.496650  Dram Type= 6, Freq= 0, CH_1, rank 1

 3122 12:23:17.500180  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3123 12:23:17.500603  ==

 3124 12:23:17.503046  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3125 12:23:17.509880  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3126 12:23:17.519446  [CA 0] Center 37 (7~68) winsize 62

 3127 12:23:17.522191  [CA 1] Center 37 (7~68) winsize 62

 3128 12:23:17.525498  [CA 2] Center 34 (4~65) winsize 62

 3129 12:23:17.528832  [CA 3] Center 33 (3~64) winsize 62

 3130 12:23:17.532050  [CA 4] Center 34 (4~65) winsize 62

 3131 12:23:17.535601  [CA 5] Center 33 (3~64) winsize 62

 3132 12:23:17.536171  

 3133 12:23:17.539196  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3134 12:23:17.539608  

 3135 12:23:17.542518  [CATrainingPosCal] consider 2 rank data

 3136 12:23:17.545524  u2DelayCellTimex100 = 270/100 ps

 3137 12:23:17.549165  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3138 12:23:17.555058  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3139 12:23:17.558652  CA2 delay=34 (4~64),Diff = 1 PI (4 cell)

 3140 12:23:17.562445  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 3141 12:23:17.565729  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3142 12:23:17.568412  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3143 12:23:17.568867  

 3144 12:23:17.571680  CA PerBit enable=1, Macro0, CA PI delay=33

 3145 12:23:17.572237  

 3146 12:23:17.575001  [CBTSetCACLKResult] CA Dly = 33

 3147 12:23:17.578370  CS Dly: 7 (0~40)

 3148 12:23:17.578780  

 3149 12:23:17.581972  ----->DramcWriteLeveling(PI) begin...

 3150 12:23:17.582387  ==

 3151 12:23:17.585295  Dram Type= 6, Freq= 0, CH_1, rank 0

 3152 12:23:17.588234  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3153 12:23:17.588648  ==

 3154 12:23:17.591800  Write leveling (Byte 0): 23 => 23

 3155 12:23:17.595658  Write leveling (Byte 1): 27 => 27

 3156 12:23:17.598183  DramcWriteLeveling(PI) end<-----

 3157 12:23:17.598598  

 3158 12:23:17.598925  ==

 3159 12:23:17.601600  Dram Type= 6, Freq= 0, CH_1, rank 0

 3160 12:23:17.604891  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3161 12:23:17.605291  ==

 3162 12:23:17.608461  [Gating] SW mode calibration

 3163 12:23:17.614827  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3164 12:23:17.622367  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3165 12:23:17.625425   0 15  0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 3166 12:23:17.628225   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3167 12:23:17.635079   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3168 12:23:17.638185   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3169 12:23:17.641892   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3170 12:23:17.648503   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3171 12:23:17.651743   0 15 24 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 0)

 3172 12:23:17.654641   0 15 28 | B1->B0 | 2626 2323 | 1 0 | (0 0) (1 0)

 3173 12:23:17.661195   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3174 12:23:17.664597   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3175 12:23:17.667705   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3176 12:23:17.674781   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3177 12:23:17.677898   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3178 12:23:17.681834   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3179 12:23:17.687928   1  0 24 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)

 3180 12:23:17.691368   1  0 28 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)

 3181 12:23:17.694606   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3182 12:23:17.700894   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3183 12:23:17.704368   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3184 12:23:17.707809   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3185 12:23:17.714300   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3186 12:23:17.717647   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3187 12:23:17.720754   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3188 12:23:17.724413   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 3189 12:23:17.731625   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3190 12:23:17.734599   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3191 12:23:17.738130   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3192 12:23:17.744180   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3193 12:23:17.747449   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3194 12:23:17.751015   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3195 12:23:17.757625   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3196 12:23:17.761074   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3197 12:23:17.764068   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3198 12:23:17.770710   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3199 12:23:17.774142   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3200 12:23:17.777720   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3201 12:23:17.783929   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3202 12:23:17.787236   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3203 12:23:17.790478   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3204 12:23:17.796999   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3205 12:23:17.800509   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3206 12:23:17.803943  Total UI for P1: 0, mck2ui 16

 3207 12:23:17.807319  best dqsien dly found for B0: ( 1,  3, 26)

 3208 12:23:17.810446  Total UI for P1: 0, mck2ui 16

 3209 12:23:17.813689  best dqsien dly found for B1: ( 1,  3, 28)

 3210 12:23:17.817041  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3211 12:23:17.820749  best DQS1 dly(MCK, UI, PI) = (1, 3, 28)

 3212 12:23:17.821327  

 3213 12:23:17.823577  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3214 12:23:17.827324  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)

 3215 12:23:17.830493  [Gating] SW calibration Done

 3216 12:23:17.831039  ==

 3217 12:23:17.833471  Dram Type= 6, Freq= 0, CH_1, rank 0

 3218 12:23:17.840011  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3219 12:23:17.840556  ==

 3220 12:23:17.840925  RX Vref Scan: 0

 3221 12:23:17.841265  

 3222 12:23:17.843859  RX Vref 0 -> 0, step: 1

 3223 12:23:17.844322  

 3224 12:23:17.846781  RX Delay -40 -> 252, step: 8

 3225 12:23:17.850066  iDelay=208, Bit 0, Center 123 (48 ~ 199) 152

 3226 12:23:17.853401  iDelay=208, Bit 1, Center 111 (40 ~ 183) 144

 3227 12:23:17.856802  iDelay=208, Bit 2, Center 111 (40 ~ 183) 144

 3228 12:23:17.863707  iDelay=208, Bit 3, Center 115 (40 ~ 191) 152

 3229 12:23:17.866841  iDelay=208, Bit 4, Center 111 (40 ~ 183) 144

 3230 12:23:17.869722  iDelay=208, Bit 5, Center 131 (56 ~ 207) 152

 3231 12:23:17.873300  iDelay=208, Bit 6, Center 123 (48 ~ 199) 152

 3232 12:23:17.876538  iDelay=208, Bit 7, Center 115 (48 ~ 183) 136

 3233 12:23:17.879866  iDelay=208, Bit 8, Center 95 (24 ~ 167) 144

 3234 12:23:17.886430  iDelay=208, Bit 9, Center 99 (24 ~ 175) 152

 3235 12:23:17.889581  iDelay=208, Bit 10, Center 111 (40 ~ 183) 144

 3236 12:23:17.893129  iDelay=208, Bit 11, Center 95 (24 ~ 167) 144

 3237 12:23:17.896599  iDelay=208, Bit 12, Center 115 (40 ~ 191) 152

 3238 12:23:17.899617  iDelay=208, Bit 13, Center 119 (48 ~ 191) 144

 3239 12:23:17.906424  iDelay=208, Bit 14, Center 115 (40 ~ 191) 152

 3240 12:23:17.909473  iDelay=208, Bit 15, Center 119 (48 ~ 191) 144

 3241 12:23:17.909944  ==

 3242 12:23:17.912972  Dram Type= 6, Freq= 0, CH_1, rank 0

 3243 12:23:17.916914  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3244 12:23:17.917491  ==

 3245 12:23:17.919465  DQS Delay:

 3246 12:23:17.919977  DQS0 = 0, DQS1 = 0

 3247 12:23:17.920457  DQM Delay:

 3248 12:23:17.922962  DQM0 = 117, DQM1 = 108

 3249 12:23:17.923612  DQ Delay:

 3250 12:23:17.926362  DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115

 3251 12:23:17.929831  DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115

 3252 12:23:17.932774  DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95

 3253 12:23:17.939264  DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119

 3254 12:23:17.939769  

 3255 12:23:17.940286  

 3256 12:23:17.940696  ==

 3257 12:23:17.942998  Dram Type= 6, Freq= 0, CH_1, rank 0

 3258 12:23:17.946102  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3259 12:23:17.946487  ==

 3260 12:23:17.946911  

 3261 12:23:17.947313  

 3262 12:23:17.949333  	TX Vref Scan disable

 3263 12:23:17.949698   == TX Byte 0 ==

 3264 12:23:17.956162  Update DQ  dly =840 (3 ,1, 40)  DQ  OEN =(2 ,6)

 3265 12:23:17.959264  Update DQM dly =840 (3 ,1, 40)  DQM OEN =(2 ,6)

 3266 12:23:17.959690   == TX Byte 1 ==

 3267 12:23:17.966307  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3268 12:23:17.969276  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3269 12:23:17.969706  ==

 3270 12:23:17.972636  Dram Type= 6, Freq= 0, CH_1, rank 0

 3271 12:23:17.976329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3272 12:23:17.976760  ==

 3273 12:23:17.988617  TX Vref=22, minBit 11, minWin=24, winSum=415

 3274 12:23:17.992021  TX Vref=24, minBit 9, minWin=25, winSum=420

 3275 12:23:17.995397  TX Vref=26, minBit 8, minWin=25, winSum=425

 3276 12:23:17.998678  TX Vref=28, minBit 9, minWin=25, winSum=428

 3277 12:23:18.002294  TX Vref=30, minBit 9, minWin=25, winSum=429

 3278 12:23:18.008946  TX Vref=32, minBit 9, minWin=25, winSum=424

 3279 12:23:18.012089  [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 30

 3280 12:23:18.012533  

 3281 12:23:18.015085  Final TX Range 1 Vref 30

 3282 12:23:18.015524  

 3283 12:23:18.016067  ==

 3284 12:23:18.018553  Dram Type= 6, Freq= 0, CH_1, rank 0

 3285 12:23:18.022057  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3286 12:23:18.025234  ==

 3287 12:23:18.025793  

 3288 12:23:18.026163  

 3289 12:23:18.026469  	TX Vref Scan disable

 3290 12:23:18.028718   == TX Byte 0 ==

 3291 12:23:18.032446  Update DQ  dly =840 (3 ,1, 40)  DQ  OEN =(2 ,6)

 3292 12:23:18.035638  Update DQM dly =840 (3 ,1, 40)  DQM OEN =(2 ,6)

 3293 12:23:18.039421   == TX Byte 1 ==

 3294 12:23:18.041943  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3295 12:23:18.045215  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3296 12:23:18.048628  

 3297 12:23:18.049036  [DATLAT]

 3298 12:23:18.049356  Freq=1200, CH1 RK0

 3299 12:23:18.049663  

 3300 12:23:18.052195  DATLAT Default: 0xd

 3301 12:23:18.052494  0, 0xFFFF, sum = 0

 3302 12:23:18.055026  1, 0xFFFF, sum = 0

 3303 12:23:18.055326  2, 0xFFFF, sum = 0

 3304 12:23:18.058776  3, 0xFFFF, sum = 0

 3305 12:23:18.061805  4, 0xFFFF, sum = 0

 3306 12:23:18.061988  5, 0xFFFF, sum = 0

 3307 12:23:18.065224  6, 0xFFFF, sum = 0

 3308 12:23:18.065406  7, 0xFFFF, sum = 0

 3309 12:23:18.068858  8, 0xFFFF, sum = 0

 3310 12:23:18.069011  9, 0xFFFF, sum = 0

 3311 12:23:18.071519  10, 0xFFFF, sum = 0

 3312 12:23:18.071670  11, 0xFFFF, sum = 0

 3313 12:23:18.075361  12, 0x0, sum = 1

 3314 12:23:18.075512  13, 0x0, sum = 2

 3315 12:23:18.078297  14, 0x0, sum = 3

 3316 12:23:18.078448  15, 0x0, sum = 4

 3317 12:23:18.078568  best_step = 13

 3318 12:23:18.082052  

 3319 12:23:18.082201  ==

 3320 12:23:18.084755  Dram Type= 6, Freq= 0, CH_1, rank 0

 3321 12:23:18.088517  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3322 12:23:18.088667  ==

 3323 12:23:18.088787  RX Vref Scan: 1

 3324 12:23:18.088897  

 3325 12:23:18.091510  Set Vref Range= 32 -> 127

 3326 12:23:18.091705  

 3327 12:23:18.095089  RX Vref 32 -> 127, step: 1

 3328 12:23:18.095236  

 3329 12:23:18.098484  RX Delay -21 -> 252, step: 4

 3330 12:23:18.098655  

 3331 12:23:18.101582  Set Vref, RX VrefLevel [Byte0]: 32

 3332 12:23:18.104778                           [Byte1]: 32

 3333 12:23:18.104976  

 3334 12:23:18.108072  Set Vref, RX VrefLevel [Byte0]: 33

 3335 12:23:18.111796                           [Byte1]: 33

 3336 12:23:18.115138  

 3337 12:23:18.115518  Set Vref, RX VrefLevel [Byte0]: 34

 3338 12:23:18.118255                           [Byte1]: 34

 3339 12:23:18.123125  

 3340 12:23:18.123536  Set Vref, RX VrefLevel [Byte0]: 35

 3341 12:23:18.126106                           [Byte1]: 35

 3342 12:23:18.131332  

 3343 12:23:18.131769  Set Vref, RX VrefLevel [Byte0]: 36

 3344 12:23:18.134435                           [Byte1]: 36

 3345 12:23:18.139090  

 3346 12:23:18.139620  Set Vref, RX VrefLevel [Byte0]: 37

 3347 12:23:18.142246                           [Byte1]: 37

 3348 12:23:18.146999  

 3349 12:23:18.147413  Set Vref, RX VrefLevel [Byte0]: 38

 3350 12:23:18.150933                           [Byte1]: 38

 3351 12:23:18.154833  

 3352 12:23:18.155244  Set Vref, RX VrefLevel [Byte0]: 39

 3353 12:23:18.157959                           [Byte1]: 39

 3354 12:23:18.162552  

 3355 12:23:18.162964  Set Vref, RX VrefLevel [Byte0]: 40

 3356 12:23:18.165971                           [Byte1]: 40

 3357 12:23:18.170783  

 3358 12:23:18.171299  Set Vref, RX VrefLevel [Byte0]: 41

 3359 12:23:18.173992                           [Byte1]: 41

 3360 12:23:18.178881  

 3361 12:23:18.179452  Set Vref, RX VrefLevel [Byte0]: 42

 3362 12:23:18.181925                           [Byte1]: 42

 3363 12:23:18.186789  

 3364 12:23:18.187245  Set Vref, RX VrefLevel [Byte0]: 43

 3365 12:23:18.189918                           [Byte1]: 43

 3366 12:23:18.194777  

 3367 12:23:18.195190  Set Vref, RX VrefLevel [Byte0]: 44

 3368 12:23:18.197840                           [Byte1]: 44

 3369 12:23:18.202288  

 3370 12:23:18.202698  Set Vref, RX VrefLevel [Byte0]: 45

 3371 12:23:18.209028                           [Byte1]: 45

 3372 12:23:18.209446  

 3373 12:23:18.212476  Set Vref, RX VrefLevel [Byte0]: 46

 3374 12:23:18.215930                           [Byte1]: 46

 3375 12:23:18.216344  

 3376 12:23:18.218669  Set Vref, RX VrefLevel [Byte0]: 47

 3377 12:23:18.222131                           [Byte1]: 47

 3378 12:23:18.226508  

 3379 12:23:18.227008  Set Vref, RX VrefLevel [Byte0]: 48

 3380 12:23:18.229530                           [Byte1]: 48

 3381 12:23:18.234230  

 3382 12:23:18.234651  Set Vref, RX VrefLevel [Byte0]: 49

 3383 12:23:18.237244                           [Byte1]: 49

 3384 12:23:18.242119  

 3385 12:23:18.242531  Set Vref, RX VrefLevel [Byte0]: 50

 3386 12:23:18.245749                           [Byte1]: 50

 3387 12:23:18.249962  

 3388 12:23:18.250503  Set Vref, RX VrefLevel [Byte0]: 51

 3389 12:23:18.253094                           [Byte1]: 51

 3390 12:23:18.257942  

 3391 12:23:18.258684  Set Vref, RX VrefLevel [Byte0]: 52

 3392 12:23:18.261259                           [Byte1]: 52

 3393 12:23:18.265571  

 3394 12:23:18.266036  Set Vref, RX VrefLevel [Byte0]: 53

 3395 12:23:18.269431                           [Byte1]: 53

 3396 12:23:18.274045  

 3397 12:23:18.274453  Set Vref, RX VrefLevel [Byte0]: 54

 3398 12:23:18.276945                           [Byte1]: 54

 3399 12:23:18.281453  

 3400 12:23:18.282051  Set Vref, RX VrefLevel [Byte0]: 55

 3401 12:23:18.284933                           [Byte1]: 55

 3402 12:23:18.289628  

 3403 12:23:18.290043  Set Vref, RX VrefLevel [Byte0]: 56

 3404 12:23:18.292983                           [Byte1]: 56

 3405 12:23:18.297564  

 3406 12:23:18.297976  Set Vref, RX VrefLevel [Byte0]: 57

 3407 12:23:18.300910                           [Byte1]: 57

 3408 12:23:18.305794  

 3409 12:23:18.306397  Set Vref, RX VrefLevel [Byte0]: 58

 3410 12:23:18.308925                           [Byte1]: 58

 3411 12:23:18.313130  

 3412 12:23:18.313539  Set Vref, RX VrefLevel [Byte0]: 59

 3413 12:23:18.316469                           [Byte1]: 59

 3414 12:23:18.321399  

 3415 12:23:18.321903  Set Vref, RX VrefLevel [Byte0]: 60

 3416 12:23:18.324519                           [Byte1]: 60

 3417 12:23:18.329425  

 3418 12:23:18.330036  Set Vref, RX VrefLevel [Byte0]: 61

 3419 12:23:18.332477                           [Byte1]: 61

 3420 12:23:18.337447  

 3421 12:23:18.337854  Set Vref, RX VrefLevel [Byte0]: 62

 3422 12:23:18.340239                           [Byte1]: 62

 3423 12:23:18.345214  

 3424 12:23:18.345630  Set Vref, RX VrefLevel [Byte0]: 63

 3425 12:23:18.348399                           [Byte1]: 63

 3426 12:23:18.352678  

 3427 12:23:18.353181  Set Vref, RX VrefLevel [Byte0]: 64

 3428 12:23:18.356133                           [Byte1]: 64

 3429 12:23:18.360486  

 3430 12:23:18.360901  Set Vref, RX VrefLevel [Byte0]: 65

 3431 12:23:18.363845                           [Byte1]: 65

 3432 12:23:18.368847  

 3433 12:23:18.369365  Set Vref, RX VrefLevel [Byte0]: 66

 3434 12:23:18.372411                           [Byte1]: 66

 3435 12:23:18.376684  

 3436 12:23:18.377214  Set Vref, RX VrefLevel [Byte0]: 67

 3437 12:23:18.380355                           [Byte1]: 67

 3438 12:23:18.384272  

 3439 12:23:18.384701  Final RX Vref Byte 0 = 47 to rank0

 3440 12:23:18.387630  Final RX Vref Byte 1 = 59 to rank0

 3441 12:23:18.391133  Final RX Vref Byte 0 = 47 to rank1

 3442 12:23:18.394452  Final RX Vref Byte 1 = 59 to rank1==

 3443 12:23:18.397661  Dram Type= 6, Freq= 0, CH_1, rank 0

 3444 12:23:18.404255  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3445 12:23:18.404675  ==

 3446 12:23:18.405004  DQS Delay:

 3447 12:23:18.407598  DQS0 = 0, DQS1 = 0

 3448 12:23:18.408055  DQM Delay:

 3449 12:23:18.408388  DQM0 = 115, DQM1 = 112

 3450 12:23:18.410921  DQ Delay:

 3451 12:23:18.414537  DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112

 3452 12:23:18.418006  DQ4 =114, DQ5 =126, DQ6 =124, DQ7 =112

 3453 12:23:18.420870  DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =100

 3454 12:23:18.424321  DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =120

 3455 12:23:18.424743  

 3456 12:23:18.425072  

 3457 12:23:18.434333  [DQSOSCAuto] RK0, (LSB)MR18= 0x6f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps

 3458 12:23:18.434877  CH1 RK0: MR19=403, MR18=6F9

 3459 12:23:18.440787  CH1_RK0: MR19=0x403, MR18=0x6F9, DQSOSC=407, MR23=63, INC=39, DEC=26

 3460 12:23:18.441323  

 3461 12:23:18.444100  ----->DramcWriteLeveling(PI) begin...

 3462 12:23:18.444521  ==

 3463 12:23:18.447840  Dram Type= 6, Freq= 0, CH_1, rank 1

 3464 12:23:18.454224  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3465 12:23:18.454721  ==

 3466 12:23:18.457481  Write leveling (Byte 0): 25 => 25

 3467 12:23:18.457910  Write leveling (Byte 1): 28 => 28

 3468 12:23:18.461021  DramcWriteLeveling(PI) end<-----

 3469 12:23:18.461438  

 3470 12:23:18.461770  ==

 3471 12:23:18.464221  Dram Type= 6, Freq= 0, CH_1, rank 1

 3472 12:23:18.470750  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3473 12:23:18.471264  ==

 3474 12:23:18.474367  [Gating] SW mode calibration

 3475 12:23:18.480173  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3476 12:23:18.483824  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3477 12:23:18.490286   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3478 12:23:18.493610   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3479 12:23:18.497202   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3480 12:23:18.503766   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3481 12:23:18.507427   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3482 12:23:18.510405   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3483 12:23:18.517047   0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)

 3484 12:23:18.520028   0 15 28 | B1->B0 | 2323 2525 | 0 1 | (1 0) (1 0)

 3485 12:23:18.523306   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3486 12:23:18.530214   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3487 12:23:18.533492   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3488 12:23:18.536978   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3489 12:23:18.543356   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3490 12:23:18.546787   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3491 12:23:18.550588   1  0 24 | B1->B0 | 3c3c 2c2c | 0 0 | (0 0) (0 0)

 3492 12:23:18.556429   1  0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 3493 12:23:18.560083   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3494 12:23:18.563219   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3495 12:23:18.569544   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3496 12:23:18.572719   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3497 12:23:18.576364   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3498 12:23:18.583017   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3499 12:23:18.586125   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3500 12:23:18.589129   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3501 12:23:18.595843   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3502 12:23:18.599096   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3503 12:23:18.602357   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3504 12:23:18.609105   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3505 12:23:18.612344   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3506 12:23:18.615876   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3507 12:23:18.622599   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3508 12:23:18.625698   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3509 12:23:18.628991   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3510 12:23:18.635454   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3511 12:23:18.638742   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3512 12:23:18.641907   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3513 12:23:18.648731   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3514 12:23:18.651898   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3515 12:23:18.655193   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3516 12:23:18.661700   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 3517 12:23:18.662182  Total UI for P1: 0, mck2ui 16

 3518 12:23:18.667997  best dqsien dly found for B1: ( 1,  3, 24)

 3519 12:23:18.670958   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3520 12:23:18.674151  Total UI for P1: 0, mck2ui 16

 3521 12:23:18.677493  best dqsien dly found for B0: ( 1,  3, 26)

 3522 12:23:18.680494  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3523 12:23:18.683827  best DQS1 dly(MCK, UI, PI) = (1, 3, 24)

 3524 12:23:18.683907  

 3525 12:23:18.687097  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3526 12:23:18.690682  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3527 12:23:18.693958  [Gating] SW calibration Done

 3528 12:23:18.694039  ==

 3529 12:23:18.697434  Dram Type= 6, Freq= 0, CH_1, rank 1

 3530 12:23:18.703886  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3531 12:23:18.703967  ==

 3532 12:23:18.704031  RX Vref Scan: 0

 3533 12:23:18.704091  

 3534 12:23:18.707102  RX Vref 0 -> 0, step: 1

 3535 12:23:18.707181  

 3536 12:23:18.710489  RX Delay -40 -> 252, step: 8

 3537 12:23:18.713837  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 3538 12:23:18.716864  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 3539 12:23:18.720368  iDelay=200, Bit 2, Center 103 (32 ~ 175) 144

 3540 12:23:18.726903  iDelay=200, Bit 3, Center 111 (40 ~ 183) 144

 3541 12:23:18.729952  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 3542 12:23:18.733052  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3543 12:23:18.736529  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 3544 12:23:18.739971  iDelay=200, Bit 7, Center 115 (40 ~ 191) 152

 3545 12:23:18.746680  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3546 12:23:18.749496  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 3547 12:23:18.753046  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3548 12:23:18.756412  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 3549 12:23:18.762864  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3550 12:23:18.766142  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3551 12:23:18.769405  iDelay=200, Bit 14, Center 115 (40 ~ 191) 152

 3552 12:23:18.772737  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 3553 12:23:18.772817  ==

 3554 12:23:18.776197  Dram Type= 6, Freq= 0, CH_1, rank 1

 3555 12:23:18.782462  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3556 12:23:18.782543  ==

 3557 12:23:18.782606  DQS Delay:

 3558 12:23:18.782665  DQS0 = 0, DQS1 = 0

 3559 12:23:18.786143  DQM Delay:

 3560 12:23:18.786224  DQM0 = 116, DQM1 = 110

 3561 12:23:18.789008  DQ Delay:

 3562 12:23:18.792413  DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111

 3563 12:23:18.795660  DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115

 3564 12:23:18.798672  DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103

 3565 12:23:18.802413  DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119

 3566 12:23:18.802493  

 3567 12:23:18.802555  

 3568 12:23:18.802625  ==

 3569 12:23:18.805468  Dram Type= 6, Freq= 0, CH_1, rank 1

 3570 12:23:18.808651  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3571 12:23:18.812391  ==

 3572 12:23:18.812475  

 3573 12:23:18.812539  

 3574 12:23:18.812597  	TX Vref Scan disable

 3575 12:23:18.815653   == TX Byte 0 ==

 3576 12:23:18.818952  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3577 12:23:18.822292  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3578 12:23:18.825324   == TX Byte 1 ==

 3579 12:23:18.828645  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3580 12:23:18.831926  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3581 12:23:18.835380  ==

 3582 12:23:18.835459  Dram Type= 6, Freq= 0, CH_1, rank 1

 3583 12:23:18.841808  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3584 12:23:18.841890  ==

 3585 12:23:18.852717  TX Vref=22, minBit 1, minWin=26, winSum=422

 3586 12:23:18.856044  TX Vref=24, minBit 8, minWin=26, winSum=431

 3587 12:23:18.859447  TX Vref=26, minBit 8, minWin=26, winSum=430

 3588 12:23:18.862736  TX Vref=28, minBit 8, minWin=26, winSum=434

 3589 12:23:18.865974  TX Vref=30, minBit 8, minWin=26, winSum=431

 3590 12:23:18.872886  TX Vref=32, minBit 8, minWin=26, winSum=432

 3591 12:23:18.876321  [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 28

 3592 12:23:18.876402  

 3593 12:23:18.879731  Final TX Range 1 Vref 28

 3594 12:23:18.879813  

 3595 12:23:18.879878  ==

 3596 12:23:18.882397  Dram Type= 6, Freq= 0, CH_1, rank 1

 3597 12:23:18.885994  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3598 12:23:18.889068  ==

 3599 12:23:18.889148  

 3600 12:23:18.889211  

 3601 12:23:18.889269  	TX Vref Scan disable

 3602 12:23:18.892981   == TX Byte 0 ==

 3603 12:23:18.895981  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3604 12:23:18.902801  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3605 12:23:18.902881   == TX Byte 1 ==

 3606 12:23:18.906044  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3607 12:23:18.912292  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3608 12:23:18.912383  

 3609 12:23:18.912492  [DATLAT]

 3610 12:23:18.912568  Freq=1200, CH1 RK1

 3611 12:23:18.912627  

 3612 12:23:18.915820  DATLAT Default: 0xd

 3613 12:23:18.919068  0, 0xFFFF, sum = 0

 3614 12:23:18.919149  1, 0xFFFF, sum = 0

 3615 12:23:18.922120  2, 0xFFFF, sum = 0

 3616 12:23:18.922201  3, 0xFFFF, sum = 0

 3617 12:23:18.925609  4, 0xFFFF, sum = 0

 3618 12:23:18.925690  5, 0xFFFF, sum = 0

 3619 12:23:18.928918  6, 0xFFFF, sum = 0

 3620 12:23:18.928999  7, 0xFFFF, sum = 0

 3621 12:23:18.932317  8, 0xFFFF, sum = 0

 3622 12:23:18.932425  9, 0xFFFF, sum = 0

 3623 12:23:18.935713  10, 0xFFFF, sum = 0

 3624 12:23:18.935816  11, 0xFFFF, sum = 0

 3625 12:23:18.938801  12, 0x0, sum = 1

 3626 12:23:18.938881  13, 0x0, sum = 2

 3627 12:23:18.942318  14, 0x0, sum = 3

 3628 12:23:18.942398  15, 0x0, sum = 4

 3629 12:23:18.945415  best_step = 13

 3630 12:23:18.945494  

 3631 12:23:18.945558  ==

 3632 12:23:18.948778  Dram Type= 6, Freq= 0, CH_1, rank 1

 3633 12:23:18.951872  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3634 12:23:18.951989  ==

 3635 12:23:18.955245  RX Vref Scan: 0

 3636 12:23:18.955330  

 3637 12:23:18.955397  RX Vref 0 -> 0, step: 1

 3638 12:23:18.955477  

 3639 12:23:18.958683  RX Delay -13 -> 252, step: 4

 3640 12:23:18.965120  iDelay=199, Bit 0, Center 118 (51 ~ 186) 136

 3641 12:23:18.968731  iDelay=199, Bit 1, Center 112 (47 ~ 178) 132

 3642 12:23:18.972218  iDelay=199, Bit 2, Center 106 (43 ~ 170) 128

 3643 12:23:18.975478  iDelay=199, Bit 3, Center 114 (51 ~ 178) 128

 3644 12:23:18.978605  iDelay=199, Bit 4, Center 114 (47 ~ 182) 136

 3645 12:23:18.985261  iDelay=199, Bit 5, Center 126 (63 ~ 190) 128

 3646 12:23:18.988681  iDelay=199, Bit 6, Center 132 (67 ~ 198) 132

 3647 12:23:18.992235  iDelay=199, Bit 7, Center 114 (51 ~ 178) 128

 3648 12:23:18.995223  iDelay=199, Bit 8, Center 98 (31 ~ 166) 136

 3649 12:23:18.998517  iDelay=199, Bit 9, Center 100 (35 ~ 166) 132

 3650 12:23:19.005220  iDelay=199, Bit 10, Center 112 (47 ~ 178) 132

 3651 12:23:19.008756  iDelay=199, Bit 11, Center 102 (35 ~ 170) 136

 3652 12:23:19.012094  iDelay=199, Bit 12, Center 120 (55 ~ 186) 132

 3653 12:23:19.015544  iDelay=199, Bit 13, Center 118 (51 ~ 186) 136

 3654 12:23:19.022142  iDelay=199, Bit 14, Center 118 (51 ~ 186) 136

 3655 12:23:19.024957  iDelay=199, Bit 15, Center 120 (51 ~ 190) 140

 3656 12:23:19.025456  ==

 3657 12:23:19.028581  Dram Type= 6, Freq= 0, CH_1, rank 1

 3658 12:23:19.032126  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3659 12:23:19.032687  ==

 3660 12:23:19.034978  DQS Delay:

 3661 12:23:19.035525  DQS0 = 0, DQS1 = 0

 3662 12:23:19.036000  DQM Delay:

 3663 12:23:19.038218  DQM0 = 117, DQM1 = 111

 3664 12:23:19.038684  DQ Delay:

 3665 12:23:19.041590  DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114

 3666 12:23:19.045009  DQ4 =114, DQ5 =126, DQ6 =132, DQ7 =114

 3667 12:23:19.048279  DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102

 3668 12:23:19.054795  DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120

 3669 12:23:19.055352  

 3670 12:23:19.055715  

 3671 12:23:19.061292  [DQSOSCAuto] RK1, (LSB)MR18= 0xf4ee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps

 3672 12:23:19.064804  CH1 RK1: MR19=303, MR18=F4EE

 3673 12:23:19.072311  CH1_RK1: MR19=0x303, MR18=0xF4EE, DQSOSC=415, MR23=63, INC=38, DEC=25

 3674 12:23:19.074729  [RxdqsGatingPostProcess] freq 1200

 3675 12:23:19.078545  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3676 12:23:19.081188  best DQS0 dly(2T, 0.5T) = (0, 11)

 3677 12:23:19.084463  best DQS1 dly(2T, 0.5T) = (0, 11)

 3678 12:23:19.087905  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3679 12:23:19.091125  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3680 12:23:19.094700  best DQS0 dly(2T, 0.5T) = (0, 11)

 3681 12:23:19.097710  best DQS1 dly(2T, 0.5T) = (0, 11)

 3682 12:23:19.100708  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3683 12:23:19.104356  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3684 12:23:19.107789  Pre-setting of DQS Precalculation

 3685 12:23:19.111315  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3686 12:23:19.120490  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3687 12:23:19.127020  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3688 12:23:19.127483  

 3689 12:23:19.127916  

 3690 12:23:19.130709  [Calibration Summary] 2400 Mbps

 3691 12:23:19.131171  CH 0, Rank 0

 3692 12:23:19.133950  SW Impedance     : PASS

 3693 12:23:19.134411  DUTY Scan        : NO K

 3694 12:23:19.137400  ZQ Calibration   : PASS

 3695 12:23:19.140365  Jitter Meter     : NO K

 3696 12:23:19.140782  CBT Training     : PASS

 3697 12:23:19.143928  Write leveling   : PASS

 3698 12:23:19.147332  RX DQS gating    : PASS

 3699 12:23:19.147834  RX DQ/DQS(RDDQC) : PASS

 3700 12:23:19.150348  TX DQ/DQS        : PASS

 3701 12:23:19.153564  RX DATLAT        : PASS

 3702 12:23:19.153859  RX DQ/DQS(Engine): PASS

 3703 12:23:19.156539  TX OE            : NO K

 3704 12:23:19.156762  All Pass.

 3705 12:23:19.156939  

 3706 12:23:19.159940  CH 0, Rank 1

 3707 12:23:19.160162  SW Impedance     : PASS

 3708 12:23:19.163077  DUTY Scan        : NO K

 3709 12:23:19.166551  ZQ Calibration   : PASS

 3710 12:23:19.166730  Jitter Meter     : NO K

 3711 12:23:19.169616  CBT Training     : PASS

 3712 12:23:19.173126  Write leveling   : PASS

 3713 12:23:19.173305  RX DQS gating    : PASS

 3714 12:23:19.176303  RX DQ/DQS(RDDQC) : PASS

 3715 12:23:19.180130  TX DQ/DQS        : PASS

 3716 12:23:19.180310  RX DATLAT        : PASS

 3717 12:23:19.182988  RX DQ/DQS(Engine): PASS

 3718 12:23:19.186262  TX OE            : NO K

 3719 12:23:19.186442  All Pass.

 3720 12:23:19.186582  

 3721 12:23:19.186714  CH 1, Rank 0

 3722 12:23:19.189881  SW Impedance     : PASS

 3723 12:23:19.193382  DUTY Scan        : NO K

 3724 12:23:19.193795  ZQ Calibration   : PASS

 3725 12:23:19.196711  Jitter Meter     : NO K

 3726 12:23:19.200237  CBT Training     : PASS

 3727 12:23:19.200652  Write leveling   : PASS

 3728 12:23:19.203580  RX DQS gating    : PASS

 3729 12:23:19.204030  RX DQ/DQS(RDDQC) : PASS

 3730 12:23:19.206755  TX DQ/DQS        : PASS

 3731 12:23:19.210124  RX DATLAT        : PASS

 3732 12:23:19.210541  RX DQ/DQS(Engine): PASS

 3733 12:23:19.213686  TX OE            : NO K

 3734 12:23:19.214218  All Pass.

 3735 12:23:19.214758  

 3736 12:23:19.216634  CH 1, Rank 1

 3737 12:23:19.217087  SW Impedance     : PASS

 3738 12:23:19.219997  DUTY Scan        : NO K

 3739 12:23:19.223403  ZQ Calibration   : PASS

 3740 12:23:19.223971  Jitter Meter     : NO K

 3741 12:23:19.226864  CBT Training     : PASS

 3742 12:23:19.230245  Write leveling   : PASS

 3743 12:23:19.230803  RX DQS gating    : PASS

 3744 12:23:19.233106  RX DQ/DQS(RDDQC) : PASS

 3745 12:23:19.236537  TX DQ/DQS        : PASS

 3746 12:23:19.236947  RX DATLAT        : PASS

 3747 12:23:19.239553  RX DQ/DQS(Engine): PASS

 3748 12:23:19.243030  TX OE            : NO K

 3749 12:23:19.243440  All Pass.

 3750 12:23:19.243803  

 3751 12:23:19.244171  DramC Write-DBI off

 3752 12:23:19.246205  	PER_BANK_REFRESH: Hybrid Mode

 3753 12:23:19.249386  TX_TRACKING: ON

 3754 12:23:19.256063  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3755 12:23:19.259794  [FAST_K] Save calibration result to emmc

 3756 12:23:19.265897  dramc_set_vcore_voltage set vcore to 650000

 3757 12:23:19.266418  Read voltage for 600, 5

 3758 12:23:19.269362  Vio18 = 0

 3759 12:23:19.269770  Vcore = 650000

 3760 12:23:19.270179  Vdram = 0

 3761 12:23:19.272543  Vddq = 0

 3762 12:23:19.272954  Vmddr = 0

 3763 12:23:19.275758  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3764 12:23:19.282335  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3765 12:23:19.285762  MEM_TYPE=3, freq_sel=19

 3766 12:23:19.288769  sv_algorithm_assistance_LP4_1600 

 3767 12:23:19.292460  ============ PULL DRAM RESETB DOWN ============

 3768 12:23:19.295571  ========== PULL DRAM RESETB DOWN end =========

 3769 12:23:19.302543  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3770 12:23:19.305371  =================================== 

 3771 12:23:19.305930  LPDDR4 DRAM CONFIGURATION

 3772 12:23:19.308668  =================================== 

 3773 12:23:19.311981  EX_ROW_EN[0]    = 0x0

 3774 12:23:19.312390  EX_ROW_EN[1]    = 0x0

 3775 12:23:19.315248  LP4Y_EN      = 0x0

 3776 12:23:19.318618  WORK_FSP     = 0x0

 3777 12:23:19.319074  WL           = 0x2

 3778 12:23:19.322017  RL           = 0x2

 3779 12:23:19.322592  BL           = 0x2

 3780 12:23:19.325050  RPST         = 0x0

 3781 12:23:19.325557  RD_PRE       = 0x0

 3782 12:23:19.328356  WR_PRE       = 0x1

 3783 12:23:19.328767  WR_PST       = 0x0

 3784 12:23:19.331839  DBI_WR       = 0x0

 3785 12:23:19.332356  DBI_RD       = 0x0

 3786 12:23:19.334898  OTF          = 0x1

 3787 12:23:19.338195  =================================== 

 3788 12:23:19.341289  =================================== 

 3789 12:23:19.341701  ANA top config

 3790 12:23:19.344672  =================================== 

 3791 12:23:19.348168  DLL_ASYNC_EN            =  0

 3792 12:23:19.351028  ALL_SLAVE_EN            =  1

 3793 12:23:19.354741  NEW_RANK_MODE           =  1

 3794 12:23:19.355156  DLL_IDLE_MODE           =  1

 3795 12:23:19.358016  LP45_APHY_COMB_EN       =  1

 3796 12:23:19.361286  TX_ODT_DIS              =  1

 3797 12:23:19.364446  NEW_8X_MODE             =  1

 3798 12:23:19.367860  =================================== 

 3799 12:23:19.371143  =================================== 

 3800 12:23:19.374756  data_rate                  = 1200

 3801 12:23:19.375219  CKR                        = 1

 3802 12:23:19.377856  DQ_P2S_RATIO               = 8

 3803 12:23:19.380790  =================================== 

 3804 12:23:19.384276  CA_P2S_RATIO               = 8

 3805 12:23:19.388183  DQ_CA_OPEN                 = 0

 3806 12:23:19.391057  DQ_SEMI_OPEN               = 0

 3807 12:23:19.393949  CA_SEMI_OPEN               = 0

 3808 12:23:19.397265  CA_FULL_RATE               = 0

 3809 12:23:19.397700  DQ_CKDIV4_EN               = 1

 3810 12:23:19.400608  CA_CKDIV4_EN               = 1

 3811 12:23:19.403705  CA_PREDIV_EN               = 0

 3812 12:23:19.407209  PH8_DLY                    = 0

 3813 12:23:19.410757  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3814 12:23:19.413816  DQ_AAMCK_DIV               = 4

 3815 12:23:19.414591  CA_AAMCK_DIV               = 4

 3816 12:23:19.417079  CA_ADMCK_DIV               = 4

 3817 12:23:19.420436  DQ_TRACK_CA_EN             = 0

 3818 12:23:19.423825  CA_PICK                    = 600

 3819 12:23:19.426766  CA_MCKIO                   = 600

 3820 12:23:19.430527  MCKIO_SEMI                 = 0

 3821 12:23:19.434026  PLL_FREQ                   = 2288

 3822 12:23:19.434569  DQ_UI_PI_RATIO             = 32

 3823 12:23:19.436543  CA_UI_PI_RATIO             = 0

 3824 12:23:19.439865  =================================== 

 3825 12:23:19.443551  =================================== 

 3826 12:23:19.446722  memory_type:LPDDR4         

 3827 12:23:19.450443  GP_NUM     : 10       

 3828 12:23:19.450991  SRAM_EN    : 1       

 3829 12:23:19.453365  MD32_EN    : 0       

 3830 12:23:19.456361  =================================== 

 3831 12:23:19.459927  [ANA_INIT] >>>>>>>>>>>>>> 

 3832 12:23:19.463478  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3833 12:23:19.466613  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3834 12:23:19.469723  =================================== 

 3835 12:23:19.470178  data_rate = 1200,PCW = 0X5800

 3836 12:23:19.473460  =================================== 

 3837 12:23:19.476515  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3838 12:23:19.482722  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3839 12:23:19.489110  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3840 12:23:19.492739  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3841 12:23:19.495963  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3842 12:23:19.499027  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3843 12:23:19.502734  [ANA_INIT] flow start 

 3844 12:23:19.506258  [ANA_INIT] PLL >>>>>>>> 

 3845 12:23:19.506775  [ANA_INIT] PLL <<<<<<<< 

 3846 12:23:19.509184  [ANA_INIT] MIDPI >>>>>>>> 

 3847 12:23:19.512283  [ANA_INIT] MIDPI <<<<<<<< 

 3848 12:23:19.512739  [ANA_INIT] DLL >>>>>>>> 

 3849 12:23:19.515973  [ANA_INIT] flow end 

 3850 12:23:19.518927  ============ LP4 DIFF to SE enter ============

 3851 12:23:19.522948  ============ LP4 DIFF to SE exit  ============

 3852 12:23:19.525964  [ANA_INIT] <<<<<<<<<<<<< 

 3853 12:23:19.529260  [Flow] Enable top DCM control >>>>> 

 3854 12:23:19.532333  [Flow] Enable top DCM control <<<<< 

 3855 12:23:19.535698  Enable DLL master slave shuffle 

 3856 12:23:19.542567  ============================================================== 

 3857 12:23:19.543147  Gating Mode config

 3858 12:23:19.548933  ============================================================== 

 3859 12:23:19.549477  Config description: 

 3860 12:23:19.558544  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3861 12:23:19.565283  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3862 12:23:19.572007  SELPH_MODE            0: By rank         1: By Phase 

 3863 12:23:19.578335  ============================================================== 

 3864 12:23:19.581553  GAT_TRACK_EN                 =  1

 3865 12:23:19.582056  RX_GATING_MODE               =  2

 3866 12:23:19.584699  RX_GATING_TRACK_MODE         =  2

 3867 12:23:19.587997  SELPH_MODE                   =  1

 3868 12:23:19.591661  PICG_EARLY_EN                =  1

 3869 12:23:19.594457  VALID_LAT_VALUE              =  1

 3870 12:23:19.601083  ============================================================== 

 3871 12:23:19.605112  Enter into Gating configuration >>>> 

 3872 12:23:19.608043  Exit from Gating configuration <<<< 

 3873 12:23:19.611138  Enter into  DVFS_PRE_config >>>>> 

 3874 12:23:19.621208  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3875 12:23:19.624601  Exit from  DVFS_PRE_config <<<<< 

 3876 12:23:19.628167  Enter into PICG configuration >>>> 

 3877 12:23:19.631113  Exit from PICG configuration <<<< 

 3878 12:23:19.634430  [RX_INPUT] configuration >>>>> 

 3879 12:23:19.637997  [RX_INPUT] configuration <<<<< 

 3880 12:23:19.640635  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3881 12:23:19.647485  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3882 12:23:19.654723  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3883 12:23:19.660711  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3884 12:23:19.666992  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3885 12:23:19.670397  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3886 12:23:19.676889  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3887 12:23:19.680522  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3888 12:23:19.683610  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3889 12:23:19.687304  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3890 12:23:19.693817  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3891 12:23:19.696752  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3892 12:23:19.700395  =================================== 

 3893 12:23:19.703322  LPDDR4 DRAM CONFIGURATION

 3894 12:23:19.706898  =================================== 

 3895 12:23:19.707667  EX_ROW_EN[0]    = 0x0

 3896 12:23:19.709837  EX_ROW_EN[1]    = 0x0

 3897 12:23:19.710345  LP4Y_EN      = 0x0

 3898 12:23:19.713342  WORK_FSP     = 0x0

 3899 12:23:19.713790  WL           = 0x2

 3900 12:23:19.716493  RL           = 0x2

 3901 12:23:19.716986  BL           = 0x2

 3902 12:23:19.720027  RPST         = 0x0

 3903 12:23:19.723435  RD_PRE       = 0x0

 3904 12:23:19.723918  WR_PRE       = 0x1

 3905 12:23:19.726459  WR_PST       = 0x0

 3906 12:23:19.726930  DBI_WR       = 0x0

 3907 12:23:19.729828  DBI_RD       = 0x0

 3908 12:23:19.730375  OTF          = 0x1

 3909 12:23:19.733183  =================================== 

 3910 12:23:19.736293  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3911 12:23:19.743079  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3912 12:23:19.746319  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3913 12:23:19.749658  =================================== 

 3914 12:23:19.752831  LPDDR4 DRAM CONFIGURATION

 3915 12:23:19.756024  =================================== 

 3916 12:23:19.756559  EX_ROW_EN[0]    = 0x10

 3917 12:23:19.759446  EX_ROW_EN[1]    = 0x0

 3918 12:23:19.759984  LP4Y_EN      = 0x0

 3919 12:23:19.762831  WORK_FSP     = 0x0

 3920 12:23:19.763363  WL           = 0x2

 3921 12:23:19.766216  RL           = 0x2

 3922 12:23:19.769337  BL           = 0x2

 3923 12:23:19.769798  RPST         = 0x0

 3924 12:23:19.772310  RD_PRE       = 0x0

 3925 12:23:19.772768  WR_PRE       = 0x1

 3926 12:23:19.775853  WR_PST       = 0x0

 3927 12:23:19.776461  DBI_WR       = 0x0

 3928 12:23:19.779435  DBI_RD       = 0x0

 3929 12:23:19.780052  OTF          = 0x1

 3930 12:23:19.782508  =================================== 

 3931 12:23:19.789207  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3932 12:23:19.792978  nWR fixed to 30

 3933 12:23:19.796173  [ModeRegInit_LP4] CH0 RK0

 3934 12:23:19.796632  [ModeRegInit_LP4] CH0 RK1

 3935 12:23:19.800067  [ModeRegInit_LP4] CH1 RK0

 3936 12:23:19.802927  [ModeRegInit_LP4] CH1 RK1

 3937 12:23:19.803628  match AC timing 17

 3938 12:23:19.809327  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3939 12:23:19.813072  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3940 12:23:19.816405  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3941 12:23:19.823229  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3942 12:23:19.826185  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3943 12:23:19.826736  ==

 3944 12:23:19.829463  Dram Type= 6, Freq= 0, CH_0, rank 0

 3945 12:23:19.832398  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3946 12:23:19.832858  ==

 3947 12:23:19.839391  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3948 12:23:19.846457  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3949 12:23:19.848835  [CA 0] Center 36 (6~66) winsize 61

 3950 12:23:19.852419  [CA 1] Center 36 (6~66) winsize 61

 3951 12:23:19.855294  [CA 2] Center 34 (4~65) winsize 62

 3952 12:23:19.858679  [CA 3] Center 34 (4~65) winsize 62

 3953 12:23:19.862499  [CA 4] Center 33 (3~64) winsize 62

 3954 12:23:19.865547  [CA 5] Center 33 (3~64) winsize 62

 3955 12:23:19.866099  

 3956 12:23:19.868330  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3957 12:23:19.868790  

 3958 12:23:19.871852  [CATrainingPosCal] consider 1 rank data

 3959 12:23:19.875317  u2DelayCellTimex100 = 270/100 ps

 3960 12:23:19.878349  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 3961 12:23:19.881723  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 3962 12:23:19.885278  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3963 12:23:19.892292  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 3964 12:23:19.895203  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 3965 12:23:19.898228  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3966 12:23:19.898705  

 3967 12:23:19.901470  CA PerBit enable=1, Macro0, CA PI delay=33

 3968 12:23:19.902008  

 3969 12:23:19.904957  [CBTSetCACLKResult] CA Dly = 33

 3970 12:23:19.905426  CS Dly: 4 (0~35)

 3971 12:23:19.908487  ==

 3972 12:23:19.908957  Dram Type= 6, Freq= 0, CH_0, rank 1

 3973 12:23:19.914679  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3974 12:23:19.915250  ==

 3975 12:23:19.917900  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3976 12:23:19.924667  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3977 12:23:19.928686  [CA 0] Center 35 (5~66) winsize 62

 3978 12:23:19.932318  [CA 1] Center 36 (6~66) winsize 61

 3979 12:23:19.935383  [CA 2] Center 34 (4~64) winsize 61

 3980 12:23:19.938325  [CA 3] Center 33 (3~64) winsize 62

 3981 12:23:19.941645  [CA 4] Center 33 (3~64) winsize 62

 3982 12:23:19.944926  [CA 5] Center 33 (2~64) winsize 63

 3983 12:23:19.945480  

 3984 12:23:19.947903  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3985 12:23:19.948380  

 3986 12:23:19.951891  [CATrainingPosCal] consider 2 rank data

 3987 12:23:19.954712  u2DelayCellTimex100 = 270/100 ps

 3988 12:23:19.958020  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 3989 12:23:19.964827  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 3990 12:23:19.967517  CA2 delay=34 (4~64),Diff = 1 PI (9 cell)

 3991 12:23:19.971016  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 3992 12:23:19.974434  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 3993 12:23:19.977470  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3994 12:23:19.977942  

 3995 12:23:19.980984  CA PerBit enable=1, Macro0, CA PI delay=33

 3996 12:23:19.981436  

 3997 12:23:19.984310  [CBTSetCACLKResult] CA Dly = 33

 3998 12:23:19.987577  CS Dly: 4 (0~36)

 3999 12:23:19.988162  

 4000 12:23:19.990930  ----->DramcWriteLeveling(PI) begin...

 4001 12:23:19.991389  ==

 4002 12:23:19.994491  Dram Type= 6, Freq= 0, CH_0, rank 0

 4003 12:23:19.997918  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4004 12:23:19.998382  ==

 4005 12:23:20.000703  Write leveling (Byte 0): 33 => 33

 4006 12:23:20.004314  Write leveling (Byte 1): 28 => 28

 4007 12:23:20.007197  DramcWriteLeveling(PI) end<-----

 4008 12:23:20.007646  

 4009 12:23:20.008027  ==

 4010 12:23:20.010490  Dram Type= 6, Freq= 0, CH_0, rank 0

 4011 12:23:20.014230  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4012 12:23:20.014652  ==

 4013 12:23:20.016938  [Gating] SW mode calibration

 4014 12:23:20.023463  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4015 12:23:20.030430  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4016 12:23:20.033902   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4017 12:23:20.037253   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4018 12:23:20.043589   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4019 12:23:20.047301   0  9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)

 4020 12:23:20.050449   0  9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)

 4021 12:23:20.056969   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4022 12:23:20.060273   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4023 12:23:20.063319   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4024 12:23:20.069728   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4025 12:23:20.073678   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4026 12:23:20.076772   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4027 12:23:20.083442   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4028 12:23:20.086358   0 10 16 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)

 4029 12:23:20.089838   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4030 12:23:20.096288   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4031 12:23:20.099396   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4032 12:23:20.103065   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4033 12:23:20.109164   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4034 12:23:20.112419   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4035 12:23:20.115797   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4036 12:23:20.122845   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4037 12:23:20.125606   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4038 12:23:20.129457   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4039 12:23:20.136184   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4040 12:23:20.139085   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4041 12:23:20.142314   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4042 12:23:20.149292   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4043 12:23:20.152787   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4044 12:23:20.155879   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4045 12:23:20.162493   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4046 12:23:20.165526   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4047 12:23:20.168575   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4048 12:23:20.175450   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4049 12:23:20.178944   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4050 12:23:20.182063   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4051 12:23:20.188588   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4052 12:23:20.192223   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4053 12:23:20.195443  Total UI for P1: 0, mck2ui 16

 4054 12:23:20.198761  best dqsien dly found for B0: ( 0, 13, 14)

 4055 12:23:20.201944   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4056 12:23:20.205136  Total UI for P1: 0, mck2ui 16

 4057 12:23:20.208249  best dqsien dly found for B1: ( 0, 13, 16)

 4058 12:23:20.212024  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4059 12:23:20.218254  best DQS1 dly(MCK, UI, PI) = (0, 13, 16)

 4060 12:23:20.218668  

 4061 12:23:20.221312  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4062 12:23:20.224664  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4063 12:23:20.227999  [Gating] SW calibration Done

 4064 12:23:20.228414  ==

 4065 12:23:20.231392  Dram Type= 6, Freq= 0, CH_0, rank 0

 4066 12:23:20.234884  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4067 12:23:20.235430  ==

 4068 12:23:20.238188  RX Vref Scan: 0

 4069 12:23:20.238596  

 4070 12:23:20.238945  RX Vref 0 -> 0, step: 1

 4071 12:23:20.239271  

 4072 12:23:20.241060  RX Delay -230 -> 252, step: 16

 4073 12:23:20.244375  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4074 12:23:20.251137  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4075 12:23:20.254599  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4076 12:23:20.257399  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4077 12:23:20.261206  iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336

 4078 12:23:20.267451  iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336

 4079 12:23:20.271265  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4080 12:23:20.274137  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4081 12:23:20.277771  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4082 12:23:20.284001  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4083 12:23:20.287497  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4084 12:23:20.290506  iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336

 4085 12:23:20.294083  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4086 12:23:20.300301  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4087 12:23:20.303596  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4088 12:23:20.307813  iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336

 4089 12:23:20.308322  ==

 4090 12:23:20.310425  Dram Type= 6, Freq= 0, CH_0, rank 0

 4091 12:23:20.314495  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4092 12:23:20.315054  ==

 4093 12:23:20.317289  DQS Delay:

 4094 12:23:20.317705  DQS0 = 0, DQS1 = 0

 4095 12:23:20.320451  DQM Delay:

 4096 12:23:20.320865  DQM0 = 43, DQM1 = 29

 4097 12:23:20.321197  DQ Delay:

 4098 12:23:20.323839  DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33

 4099 12:23:20.326854  DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =49

 4100 12:23:20.330344  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17

 4101 12:23:20.333680  DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33

 4102 12:23:20.334111  

 4103 12:23:20.334445  

 4104 12:23:20.337040  ==

 4105 12:23:20.340332  Dram Type= 6, Freq= 0, CH_0, rank 0

 4106 12:23:20.343773  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4107 12:23:20.344202  ==

 4108 12:23:20.344533  

 4109 12:23:20.344842  

 4110 12:23:20.347342  	TX Vref Scan disable

 4111 12:23:20.347910   == TX Byte 0 ==

 4112 12:23:20.353454  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4113 12:23:20.357189  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4114 12:23:20.357700   == TX Byte 1 ==

 4115 12:23:20.363622  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4116 12:23:20.367269  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4117 12:23:20.367827  ==

 4118 12:23:20.370493  Dram Type= 6, Freq= 0, CH_0, rank 0

 4119 12:23:20.373928  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4120 12:23:20.374448  ==

 4121 12:23:20.374781  

 4122 12:23:20.375088  

 4123 12:23:20.376917  	TX Vref Scan disable

 4124 12:23:20.380065   == TX Byte 0 ==

 4125 12:23:20.383363  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4126 12:23:20.386925  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4127 12:23:20.389787   == TX Byte 1 ==

 4128 12:23:20.393281  Update DQ  dly =572 (2 ,1, 28)  DQ  OEN =(1 ,6)

 4129 12:23:20.396623  Update DQM dly =572 (2 ,1, 28)  DQM OEN =(1 ,6)

 4130 12:23:20.399952  

 4131 12:23:20.400468  [DATLAT]

 4132 12:23:20.400803  Freq=600, CH0 RK0

 4133 12:23:20.401139  

 4134 12:23:20.403199  DATLAT Default: 0x9

 4135 12:23:20.403650  0, 0xFFFF, sum = 0

 4136 12:23:20.406565  1, 0xFFFF, sum = 0

 4137 12:23:20.407081  2, 0xFFFF, sum = 0

 4138 12:23:20.409935  3, 0xFFFF, sum = 0

 4139 12:23:20.410358  4, 0xFFFF, sum = 0

 4140 12:23:20.412860  5, 0xFFFF, sum = 0

 4141 12:23:20.416178  6, 0xFFFF, sum = 0

 4142 12:23:20.416646  7, 0xFFFF, sum = 0

 4143 12:23:20.416993  8, 0x0, sum = 1

 4144 12:23:20.419436  9, 0x0, sum = 2

 4145 12:23:20.419906  10, 0x0, sum = 3

 4146 12:23:20.423645  11, 0x0, sum = 4

 4147 12:23:20.424294  best_step = 9

 4148 12:23:20.424631  

 4149 12:23:20.424941  ==

 4150 12:23:20.426350  Dram Type= 6, Freq= 0, CH_0, rank 0

 4151 12:23:20.433478  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4152 12:23:20.433897  ==

 4153 12:23:20.434229  RX Vref Scan: 1

 4154 12:23:20.434539  

 4155 12:23:20.436388  RX Vref 0 -> 0, step: 1

 4156 12:23:20.436879  

 4157 12:23:20.439206  RX Delay -195 -> 252, step: 8

 4158 12:23:20.439620  

 4159 12:23:20.442744  Set Vref, RX VrefLevel [Byte0]: 60

 4160 12:23:20.445944                           [Byte1]: 56

 4161 12:23:20.446363  

 4162 12:23:20.449164  Final RX Vref Byte 0 = 60 to rank0

 4163 12:23:20.452476  Final RX Vref Byte 1 = 56 to rank0

 4164 12:23:20.455674  Final RX Vref Byte 0 = 60 to rank1

 4165 12:23:20.458990  Final RX Vref Byte 1 = 56 to rank1==

 4166 12:23:20.462514  Dram Type= 6, Freq= 0, CH_0, rank 0

 4167 12:23:20.466109  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4168 12:23:20.466631  ==

 4169 12:23:20.468918  DQS Delay:

 4170 12:23:20.469343  DQS0 = 0, DQS1 = 0

 4171 12:23:20.472354  DQM Delay:

 4172 12:23:20.472760  DQM0 = 43, DQM1 = 32

 4173 12:23:20.473150  DQ Delay:

 4174 12:23:20.475520  DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40

 4175 12:23:20.478732  DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52

 4176 12:23:20.482587  DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =24

 4177 12:23:20.485377  DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40

 4178 12:23:20.485788  

 4179 12:23:20.488811  

 4180 12:23:20.495345  [DQSOSCAuto] RK0, (LSB)MR18= 0x663d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps

 4181 12:23:20.498877  CH0 RK0: MR19=808, MR18=663D

 4182 12:23:20.505358  CH0_RK0: MR19=0x808, MR18=0x663D, DQSOSC=390, MR23=63, INC=172, DEC=114

 4183 12:23:20.505777  

 4184 12:23:20.508707  ----->DramcWriteLeveling(PI) begin...

 4185 12:23:20.509126  ==

 4186 12:23:20.511908  Dram Type= 6, Freq= 0, CH_0, rank 1

 4187 12:23:20.515338  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4188 12:23:20.515810  ==

 4189 12:23:20.518690  Write leveling (Byte 0): 34 => 34

 4190 12:23:20.522021  Write leveling (Byte 1): 33 => 33

 4191 12:23:20.525431  DramcWriteLeveling(PI) end<-----

 4192 12:23:20.525998  

 4193 12:23:20.526372  ==

 4194 12:23:20.528363  Dram Type= 6, Freq= 0, CH_0, rank 1

 4195 12:23:20.531614  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4196 12:23:20.532302  ==

 4197 12:23:20.535100  [Gating] SW mode calibration

 4198 12:23:20.541688  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4199 12:23:20.548169  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4200 12:23:20.551672   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4201 12:23:20.555023   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4202 12:23:20.561336   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4203 12:23:20.564935   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 4204 12:23:20.568246   0  9 16 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)

 4205 12:23:20.575043   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4206 12:23:20.577806   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4207 12:23:20.581128   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4208 12:23:20.587954   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4209 12:23:20.591048   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4210 12:23:20.594490   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4211 12:23:20.601359   0 10 12 | B1->B0 | 2626 2626 | 1 0 | (0 0) (0 0)

 4212 12:23:20.604395   0 10 16 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)

 4213 12:23:20.607998   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4214 12:23:20.614214   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4215 12:23:20.618247   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4216 12:23:20.620992   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4217 12:23:20.627449   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4218 12:23:20.630897   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4219 12:23:20.634184   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4220 12:23:20.640922   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4221 12:23:20.644017   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4222 12:23:20.647403   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4223 12:23:20.654054   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4224 12:23:20.657656   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4225 12:23:20.660836   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4226 12:23:20.666953   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4227 12:23:20.670655   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4228 12:23:20.674209   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4229 12:23:20.680190   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4230 12:23:20.683585   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4231 12:23:20.686849   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4232 12:23:20.693251   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4233 12:23:20.696701   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4234 12:23:20.700365   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4235 12:23:20.706938   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4236 12:23:20.710231  Total UI for P1: 0, mck2ui 16

 4237 12:23:20.713133  best dqsien dly found for B0: ( 0, 13, 10)

 4238 12:23:20.716549   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4239 12:23:20.719912   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4240 12:23:20.723052  Total UI for P1: 0, mck2ui 16

 4241 12:23:20.726571  best dqsien dly found for B1: ( 0, 13, 14)

 4242 12:23:20.729987  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4243 12:23:20.736105  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4244 12:23:20.736537  

 4245 12:23:20.739440  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4246 12:23:20.742729  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4247 12:23:20.746370  [Gating] SW calibration Done

 4248 12:23:20.746823  ==

 4249 12:23:20.749325  Dram Type= 6, Freq= 0, CH_0, rank 1

 4250 12:23:20.752943  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4251 12:23:20.753394  ==

 4252 12:23:20.756111  RX Vref Scan: 0

 4253 12:23:20.756570  

 4254 12:23:20.756930  RX Vref 0 -> 0, step: 1

 4255 12:23:20.757267  

 4256 12:23:20.759360  RX Delay -230 -> 252, step: 16

 4257 12:23:20.762685  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4258 12:23:20.769530  iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336

 4259 12:23:20.772637  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4260 12:23:20.776119  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4261 12:23:20.778887  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4262 12:23:20.785959  iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336

 4263 12:23:20.789589  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4264 12:23:20.792306  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4265 12:23:20.795396  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4266 12:23:20.802487  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4267 12:23:20.805736  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4268 12:23:20.808833  iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336

 4269 12:23:20.812365  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4270 12:23:20.818824  iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320

 4271 12:23:20.822091  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4272 12:23:20.825593  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4273 12:23:20.826178  ==

 4274 12:23:20.829374  Dram Type= 6, Freq= 0, CH_0, rank 1

 4275 12:23:20.831885  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4276 12:23:20.832300  ==

 4277 12:23:20.835162  DQS Delay:

 4278 12:23:20.835753  DQS0 = 0, DQS1 = 0

 4279 12:23:20.838334  DQM Delay:

 4280 12:23:20.838832  DQM0 = 41, DQM1 = 35

 4281 12:23:20.839287  DQ Delay:

 4282 12:23:20.841650  DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33

 4283 12:23:20.845190  DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49

 4284 12:23:20.848680  DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33

 4285 12:23:20.851607  DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41

 4286 12:23:20.852263  

 4287 12:23:20.852601  

 4288 12:23:20.855195  ==

 4289 12:23:20.858652  Dram Type= 6, Freq= 0, CH_0, rank 1

 4290 12:23:20.861651  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4291 12:23:20.862071  ==

 4292 12:23:20.862400  

 4293 12:23:20.862704  

 4294 12:23:20.865020  	TX Vref Scan disable

 4295 12:23:20.865429   == TX Byte 0 ==

 4296 12:23:20.871550  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4297 12:23:20.875174  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4298 12:23:20.875587   == TX Byte 1 ==

 4299 12:23:20.881464  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4300 12:23:20.884808  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4301 12:23:20.885219  ==

 4302 12:23:20.888093  Dram Type= 6, Freq= 0, CH_0, rank 1

 4303 12:23:20.891443  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4304 12:23:20.891894  ==

 4305 12:23:20.892222  

 4306 12:23:20.892524  

 4307 12:23:20.894847  	TX Vref Scan disable

 4308 12:23:20.897802   == TX Byte 0 ==

 4309 12:23:20.901299  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4310 12:23:20.904470  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4311 12:23:20.907814   == TX Byte 1 ==

 4312 12:23:20.911315  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4313 12:23:20.914657  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4314 12:23:20.918416  

 4315 12:23:20.918931  [DATLAT]

 4316 12:23:20.919256  Freq=600, CH0 RK1

 4317 12:23:20.919559  

 4318 12:23:20.921289  DATLAT Default: 0x9

 4319 12:23:20.921816  0, 0xFFFF, sum = 0

 4320 12:23:20.924739  1, 0xFFFF, sum = 0

 4321 12:23:20.925194  2, 0xFFFF, sum = 0

 4322 12:23:20.927658  3, 0xFFFF, sum = 0

 4323 12:23:20.928121  4, 0xFFFF, sum = 0

 4324 12:23:20.930962  5, 0xFFFF, sum = 0

 4325 12:23:20.934174  6, 0xFFFF, sum = 0

 4326 12:23:20.934590  7, 0xFFFF, sum = 0

 4327 12:23:20.934923  8, 0x0, sum = 1

 4328 12:23:20.937698  9, 0x0, sum = 2

 4329 12:23:20.938116  10, 0x0, sum = 3

 4330 12:23:20.941096  11, 0x0, sum = 4

 4331 12:23:20.941522  best_step = 9

 4332 12:23:20.941844  

 4333 12:23:20.942143  ==

 4334 12:23:20.944115  Dram Type= 6, Freq= 0, CH_0, rank 1

 4335 12:23:20.950791  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4336 12:23:20.951207  ==

 4337 12:23:20.951540  RX Vref Scan: 0

 4338 12:23:20.951894  

 4339 12:23:20.954333  RX Vref 0 -> 0, step: 1

 4340 12:23:20.954744  

 4341 12:23:20.957832  RX Delay -195 -> 252, step: 8

 4342 12:23:20.961026  iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304

 4343 12:23:20.967352  iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304

 4344 12:23:20.970828  iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304

 4345 12:23:20.974136  iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312

 4346 12:23:20.977203  iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304

 4347 12:23:20.983901  iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312

 4348 12:23:20.986983  iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312

 4349 12:23:20.990482  iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304

 4350 12:23:20.993520  iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312

 4351 12:23:21.000468  iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312

 4352 12:23:21.003444  iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312

 4353 12:23:21.006554  iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304

 4354 12:23:21.010164  iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304

 4355 12:23:21.016227  iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304

 4356 12:23:21.020073  iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304

 4357 12:23:21.023133  iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304

 4358 12:23:21.023624  ==

 4359 12:23:21.026431  Dram Type= 6, Freq= 0, CH_0, rank 1

 4360 12:23:21.029805  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4361 12:23:21.032770  ==

 4362 12:23:21.033182  DQS Delay:

 4363 12:23:21.033588  DQS0 = 0, DQS1 = 0

 4364 12:23:21.036470  DQM Delay:

 4365 12:23:21.036879  DQM0 = 41, DQM1 = 36

 4366 12:23:21.039718  DQ Delay:

 4367 12:23:21.040169  DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40

 4368 12:23:21.043100  DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52

 4369 12:23:21.046336  DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28

 4370 12:23:21.049630  DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44

 4371 12:23:21.050157  

 4372 12:23:21.052930  

 4373 12:23:21.059497  [DQSOSCAuto] RK1, (LSB)MR18= 0x6012, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps

 4374 12:23:21.062518  CH0 RK1: MR19=808, MR18=6012

 4375 12:23:21.069728  CH0_RK1: MR19=0x808, MR18=0x6012, DQSOSC=391, MR23=63, INC=171, DEC=114

 4376 12:23:21.072991  [RxdqsGatingPostProcess] freq 600

 4377 12:23:21.076093  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4378 12:23:21.079331  Pre-setting of DQS Precalculation

 4379 12:23:21.086026  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4380 12:23:21.086486  ==

 4381 12:23:21.089597  Dram Type= 6, Freq= 0, CH_1, rank 0

 4382 12:23:21.092551  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4383 12:23:21.093013  ==

 4384 12:23:21.099388  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4385 12:23:21.102098  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4386 12:23:21.106478  [CA 0] Center 36 (6~66) winsize 61

 4387 12:23:21.109984  [CA 1] Center 36 (6~66) winsize 61

 4388 12:23:21.113160  [CA 2] Center 34 (4~65) winsize 62

 4389 12:23:21.116360  [CA 3] Center 33 (3~64) winsize 62

 4390 12:23:21.120075  [CA 4] Center 34 (4~65) winsize 62

 4391 12:23:21.123257  [CA 5] Center 33 (3~64) winsize 62

 4392 12:23:21.123665  

 4393 12:23:21.126654  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4394 12:23:21.127207  

 4395 12:23:21.130279  [CATrainingPosCal] consider 1 rank data

 4396 12:23:21.133089  u2DelayCellTimex100 = 270/100 ps

 4397 12:23:21.136286  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 4398 12:23:21.142680  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 4399 12:23:21.145890  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4400 12:23:21.149802  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4401 12:23:21.152790  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4402 12:23:21.155923  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4403 12:23:21.156380  

 4404 12:23:21.159386  CA PerBit enable=1, Macro0, CA PI delay=33

 4405 12:23:21.159871  

 4406 12:23:21.162422  [CBTSetCACLKResult] CA Dly = 33

 4407 12:23:21.165891  CS Dly: 4 (0~35)

 4408 12:23:21.166349  ==

 4409 12:23:21.169204  Dram Type= 6, Freq= 0, CH_1, rank 1

 4410 12:23:21.172318  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4411 12:23:21.172780  ==

 4412 12:23:21.178830  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4413 12:23:21.182196  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4414 12:23:21.186693  [CA 0] Center 35 (5~66) winsize 62

 4415 12:23:21.189906  [CA 1] Center 35 (5~66) winsize 62

 4416 12:23:21.193553  [CA 2] Center 34 (4~65) winsize 62

 4417 12:23:21.196633  [CA 3] Center 34 (4~65) winsize 62

 4418 12:23:21.200004  [CA 4] Center 34 (4~65) winsize 62

 4419 12:23:21.203318  [CA 5] Center 34 (3~65) winsize 63

 4420 12:23:21.203921  

 4421 12:23:21.206496  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4422 12:23:21.206994  

 4423 12:23:21.210489  [CATrainingPosCal] consider 2 rank data

 4424 12:23:21.212920  u2DelayCellTimex100 = 270/100 ps

 4425 12:23:21.216564  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 4426 12:23:21.223116  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 4427 12:23:21.226404  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4428 12:23:21.229861  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 4429 12:23:21.232558  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4430 12:23:21.236245  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4431 12:23:21.236705  

 4432 12:23:21.239610  CA PerBit enable=1, Macro0, CA PI delay=33

 4433 12:23:21.240123  

 4434 12:23:21.243104  [CBTSetCACLKResult] CA Dly = 33

 4435 12:23:21.245814  CS Dly: 5 (0~38)

 4436 12:23:21.246298  

 4437 12:23:21.249290  ----->DramcWriteLeveling(PI) begin...

 4438 12:23:21.249761  ==

 4439 12:23:21.253185  Dram Type= 6, Freq= 0, CH_1, rank 0

 4440 12:23:21.255991  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4441 12:23:21.256517  ==

 4442 12:23:21.259248  Write leveling (Byte 0): 29 => 29

 4443 12:23:21.262981  Write leveling (Byte 1): 29 => 29

 4444 12:23:21.266609  DramcWriteLeveling(PI) end<-----

 4445 12:23:21.267178  

 4446 12:23:21.267661  ==

 4447 12:23:21.269085  Dram Type= 6, Freq= 0, CH_1, rank 0

 4448 12:23:21.272879  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4449 12:23:21.273341  ==

 4450 12:23:21.276012  [Gating] SW mode calibration

 4451 12:23:21.282890  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4452 12:23:21.289055  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4453 12:23:21.292214   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4454 12:23:21.295217   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4455 12:23:21.302260   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4456 12:23:21.305336   0  9 12 | B1->B0 | 3131 2f2f | 0 1 | (0 1) (1 0)

 4457 12:23:21.308829   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 4458 12:23:21.315067   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4459 12:23:21.318355   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4460 12:23:21.321689   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4461 12:23:21.328234   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4462 12:23:21.331673   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4463 12:23:21.335065   0 10  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 4464 12:23:21.341524   0 10 12 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (0 0)

 4465 12:23:21.344745   0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 4466 12:23:21.347831   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4467 12:23:21.354470   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4468 12:23:21.357748   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4469 12:23:21.361178   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4470 12:23:21.367776   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4471 12:23:21.371254   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4472 12:23:21.374339   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 4473 12:23:21.381375   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4474 12:23:21.384018   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4475 12:23:21.387792   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4476 12:23:21.394416   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4477 12:23:21.397795   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4478 12:23:21.400762   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4479 12:23:21.407178   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4480 12:23:21.410942   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4481 12:23:21.413827   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4482 12:23:21.420455   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4483 12:23:21.423937   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4484 12:23:21.427153   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4485 12:23:21.433848   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4486 12:23:21.437501   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4487 12:23:21.440539   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4488 12:23:21.446965   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4489 12:23:21.450383  Total UI for P1: 0, mck2ui 16

 4490 12:23:21.453918  best dqsien dly found for B0: ( 0, 13, 10)

 4491 12:23:21.456859   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4492 12:23:21.460155  Total UI for P1: 0, mck2ui 16

 4493 12:23:21.463550  best dqsien dly found for B1: ( 0, 13, 12)

 4494 12:23:21.466794  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4495 12:23:21.470238  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4496 12:23:21.470689  

 4497 12:23:21.473251  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4498 12:23:21.479623  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4499 12:23:21.480119  [Gating] SW calibration Done

 4500 12:23:21.480497  ==

 4501 12:23:21.483370  Dram Type= 6, Freq= 0, CH_1, rank 0

 4502 12:23:21.489612  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4503 12:23:21.490088  ==

 4504 12:23:21.490472  RX Vref Scan: 0

 4505 12:23:21.490815  

 4506 12:23:21.492899  RX Vref 0 -> 0, step: 1

 4507 12:23:21.493397  

 4508 12:23:21.496168  RX Delay -230 -> 252, step: 16

 4509 12:23:21.500197  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4510 12:23:21.502900  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4511 12:23:21.509590  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4512 12:23:21.512917  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4513 12:23:21.515630  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4514 12:23:21.519042  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4515 12:23:21.522650  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4516 12:23:21.529264  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4517 12:23:21.532512  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4518 12:23:21.535961  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4519 12:23:21.539018  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4520 12:23:21.545298  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4521 12:23:21.548573  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4522 12:23:21.552054  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4523 12:23:21.555264  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4524 12:23:21.562066  iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336

 4525 12:23:21.562145  ==

 4526 12:23:21.565379  Dram Type= 6, Freq= 0, CH_1, rank 0

 4527 12:23:21.568264  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4528 12:23:21.568335  ==

 4529 12:23:21.568396  DQS Delay:

 4530 12:23:21.572036  DQS0 = 0, DQS1 = 0

 4531 12:23:21.572174  DQM Delay:

 4532 12:23:21.575143  DQM0 = 47, DQM1 = 38

 4533 12:23:21.575256  DQ Delay:

 4534 12:23:21.578459  DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41

 4535 12:23:21.581666  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41

 4536 12:23:21.584992  DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25

 4537 12:23:21.588121  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49

 4538 12:23:21.588202  

 4539 12:23:21.588265  

 4540 12:23:21.588324  ==

 4541 12:23:21.591759  Dram Type= 6, Freq= 0, CH_1, rank 0

 4542 12:23:21.598248  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4543 12:23:21.598372  ==

 4544 12:23:21.598435  

 4545 12:23:21.598495  

 4546 12:23:21.598554  	TX Vref Scan disable

 4547 12:23:21.601918   == TX Byte 0 ==

 4548 12:23:21.604577  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4549 12:23:21.611387  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4550 12:23:21.611504   == TX Byte 1 ==

 4551 12:23:21.614791  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4552 12:23:21.620976  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4553 12:23:21.621057  ==

 4554 12:23:21.624402  Dram Type= 6, Freq= 0, CH_1, rank 0

 4555 12:23:21.627869  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4556 12:23:21.627951  ==

 4557 12:23:21.628030  

 4558 12:23:21.628102  

 4559 12:23:21.631229  	TX Vref Scan disable

 4560 12:23:21.634392   == TX Byte 0 ==

 4561 12:23:21.637709  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4562 12:23:21.640956  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4563 12:23:21.644258   == TX Byte 1 ==

 4564 12:23:21.647556  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4565 12:23:21.651004  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4566 12:23:21.651085  

 4567 12:23:21.654009  [DATLAT]

 4568 12:23:21.654089  Freq=600, CH1 RK0

 4569 12:23:21.654152  

 4570 12:23:21.657460  DATLAT Default: 0x9

 4571 12:23:21.657541  0, 0xFFFF, sum = 0

 4572 12:23:21.660474  1, 0xFFFF, sum = 0

 4573 12:23:21.660557  2, 0xFFFF, sum = 0

 4574 12:23:21.663556  3, 0xFFFF, sum = 0

 4575 12:23:21.663637  4, 0xFFFF, sum = 0

 4576 12:23:21.667081  5, 0xFFFF, sum = 0

 4577 12:23:21.667163  6, 0xFFFF, sum = 0

 4578 12:23:21.670666  7, 0xFFFF, sum = 0

 4579 12:23:21.670740  8, 0x0, sum = 1

 4580 12:23:21.673925  9, 0x0, sum = 2

 4581 12:23:21.674007  10, 0x0, sum = 3

 4582 12:23:21.677266  11, 0x0, sum = 4

 4583 12:23:21.677347  best_step = 9

 4584 12:23:21.677412  

 4585 12:23:21.677470  ==

 4586 12:23:21.680456  Dram Type= 6, Freq= 0, CH_1, rank 0

 4587 12:23:21.683982  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4588 12:23:21.684067  ==

 4589 12:23:21.687132  RX Vref Scan: 1

 4590 12:23:21.687212  

 4591 12:23:21.690330  RX Vref 0 -> 0, step: 1

 4592 12:23:21.690410  

 4593 12:23:21.690474  RX Delay -195 -> 252, step: 8

 4594 12:23:21.693589  

 4595 12:23:21.693669  Set Vref, RX VrefLevel [Byte0]: 47

 4596 12:23:21.696734                           [Byte1]: 59

 4597 12:23:21.702082  

 4598 12:23:21.702162  Final RX Vref Byte 0 = 47 to rank0

 4599 12:23:21.705411  Final RX Vref Byte 1 = 59 to rank0

 4600 12:23:21.708680  Final RX Vref Byte 0 = 47 to rank1

 4601 12:23:21.711932  Final RX Vref Byte 1 = 59 to rank1==

 4602 12:23:21.714845  Dram Type= 6, Freq= 0, CH_1, rank 0

 4603 12:23:21.722044  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4604 12:23:21.722128  ==

 4605 12:23:21.722212  DQS Delay:

 4606 12:23:21.725173  DQS0 = 0, DQS1 = 0

 4607 12:23:21.725257  DQM Delay:

 4608 12:23:21.725342  DQM0 = 47, DQM1 = 38

 4609 12:23:21.728388  DQ Delay:

 4610 12:23:21.731981  DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44

 4611 12:23:21.734672  DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =40

 4612 12:23:21.738047  DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28

 4613 12:23:21.741265  DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48

 4614 12:23:21.741348  

 4615 12:23:21.741432  

 4616 12:23:21.748458  [DQSOSCAuto] RK0, (LSB)MR18= 0x4c31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps

 4617 12:23:21.751295  CH1 RK0: MR19=808, MR18=4C31

 4618 12:23:21.758119  CH1_RK0: MR19=0x808, MR18=0x4C31, DQSOSC=395, MR23=63, INC=168, DEC=112

 4619 12:23:21.758203  

 4620 12:23:21.761076  ----->DramcWriteLeveling(PI) begin...

 4621 12:23:21.761156  ==

 4622 12:23:21.764789  Dram Type= 6, Freq= 0, CH_1, rank 1

 4623 12:23:21.767962  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4624 12:23:21.768056  ==

 4625 12:23:21.771197  Write leveling (Byte 0): 30 => 30

 4626 12:23:21.774720  Write leveling (Byte 1): 30 => 30

 4627 12:23:21.778070  DramcWriteLeveling(PI) end<-----

 4628 12:23:21.778153  

 4629 12:23:21.778237  ==

 4630 12:23:21.780897  Dram Type= 6, Freq= 0, CH_1, rank 1

 4631 12:23:21.784408  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4632 12:23:21.787625  ==

 4633 12:23:21.787709  [Gating] SW mode calibration

 4634 12:23:21.797531  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4635 12:23:21.800819  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4636 12:23:21.804380   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4637 12:23:21.810894   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4638 12:23:21.814230   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4639 12:23:21.817600   0  9 12 | B1->B0 | 3030 3333 | 1 1 | (1 1) (1 1)

 4640 12:23:21.824010   0  9 16 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (1 1)

 4641 12:23:21.827356   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4642 12:23:21.830794   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4643 12:23:21.837066   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4644 12:23:21.840353   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4645 12:23:21.843561   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4646 12:23:21.850588   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4647 12:23:21.853891   0 10 12 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)

 4648 12:23:21.857379   0 10 16 | B1->B0 | 4646 4242 | 0 0 | (0 0) (1 1)

 4649 12:23:21.863590   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4650 12:23:21.867364   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4651 12:23:21.870264   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4652 12:23:21.877270   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4653 12:23:21.879745   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4654 12:23:21.883385   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4655 12:23:21.889837   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4656 12:23:21.893275   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4657 12:23:21.896460   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4658 12:23:21.903506   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4659 12:23:21.906439   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4660 12:23:21.910111   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4661 12:23:21.916497   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4662 12:23:21.919775   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4663 12:23:21.923129   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4664 12:23:21.929768   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4665 12:23:21.933165   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4666 12:23:21.936414   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4667 12:23:21.942915   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4668 12:23:21.946555   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4669 12:23:21.949828   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4670 12:23:21.956339   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4671 12:23:21.959315   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 4672 12:23:21.962847  Total UI for P1: 0, mck2ui 16

 4673 12:23:21.965893  best dqsien dly found for B1: ( 0, 13, 10)

 4674 12:23:21.969304   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4675 12:23:21.972614  Total UI for P1: 0, mck2ui 16

 4676 12:23:21.975902  best dqsien dly found for B0: ( 0, 13, 12)

 4677 12:23:21.979666  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4678 12:23:21.982751  best DQS1 dly(MCK, UI, PI) = (0, 13, 10)

 4679 12:23:21.982834  

 4680 12:23:21.989171  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4681 12:23:21.992368  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4682 12:23:21.995693  [Gating] SW calibration Done

 4683 12:23:21.995805  ==

 4684 12:23:21.998883  Dram Type= 6, Freq= 0, CH_1, rank 1

 4685 12:23:22.002287  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4686 12:23:22.002392  ==

 4687 12:23:22.002497  RX Vref Scan: 0

 4688 12:23:22.002621  

 4689 12:23:22.005791  RX Vref 0 -> 0, step: 1

 4690 12:23:22.005937  

 4691 12:23:22.009032  RX Delay -230 -> 252, step: 16

 4692 12:23:22.012369  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4693 12:23:22.019194  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4694 12:23:22.022238  iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320

 4695 12:23:22.025634  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4696 12:23:22.028455  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4697 12:23:22.031623  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4698 12:23:22.038849  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4699 12:23:22.041817  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4700 12:23:22.045255  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4701 12:23:22.048443  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4702 12:23:22.055227  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4703 12:23:22.058486  iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352

 4704 12:23:22.061545  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4705 12:23:22.064936  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4706 12:23:22.071908  iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352

 4707 12:23:22.074987  iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336

 4708 12:23:22.075069  ==

 4709 12:23:22.078902  Dram Type= 6, Freq= 0, CH_1, rank 1

 4710 12:23:22.081550  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4711 12:23:22.081634  ==

 4712 12:23:22.084792  DQS Delay:

 4713 12:23:22.084876  DQS0 = 0, DQS1 = 0

 4714 12:23:22.084961  DQM Delay:

 4715 12:23:22.088018  DQM0 = 43, DQM1 = 35

 4716 12:23:22.088100  DQ Delay:

 4717 12:23:22.091395  DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41

 4718 12:23:22.095131  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41

 4719 12:23:22.098158  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25

 4720 12:23:22.101423  DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49

 4721 12:23:22.101846  

 4722 12:23:22.102302  

 4723 12:23:22.102712  ==

 4724 12:23:22.104967  Dram Type= 6, Freq= 0, CH_1, rank 1

 4725 12:23:22.111524  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4726 12:23:22.111607  ==

 4727 12:23:22.111706  

 4728 12:23:22.111824  

 4729 12:23:22.111923  	TX Vref Scan disable

 4730 12:23:22.114849   == TX Byte 0 ==

 4731 12:23:22.118289  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4732 12:23:22.124669  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4733 12:23:22.124772   == TX Byte 1 ==

 4734 12:23:22.128184  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4735 12:23:22.135148  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4736 12:23:22.135365  ==

 4737 12:23:22.137917  Dram Type= 6, Freq= 0, CH_1, rank 1

 4738 12:23:22.141275  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4739 12:23:22.141356  ==

 4740 12:23:22.141430  

 4741 12:23:22.141494  

 4742 12:23:22.144777  	TX Vref Scan disable

 4743 12:23:22.147979   == TX Byte 0 ==

 4744 12:23:22.151395  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4745 12:23:22.154736  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4746 12:23:22.158100   == TX Byte 1 ==

 4747 12:23:22.160921  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4748 12:23:22.164869  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4749 12:23:22.164982  

 4750 12:23:22.165049  [DATLAT]

 4751 12:23:22.167615  Freq=600, CH1 RK1

 4752 12:23:22.167695  

 4753 12:23:22.171441  DATLAT Default: 0x9

 4754 12:23:22.171556  0, 0xFFFF, sum = 0

 4755 12:23:22.174770  1, 0xFFFF, sum = 0

 4756 12:23:22.174938  2, 0xFFFF, sum = 0

 4757 12:23:22.177867  3, 0xFFFF, sum = 0

 4758 12:23:22.178007  4, 0xFFFF, sum = 0

 4759 12:23:22.181080  5, 0xFFFF, sum = 0

 4760 12:23:22.181262  6, 0xFFFF, sum = 0

 4761 12:23:22.185032  7, 0xFFFF, sum = 0

 4762 12:23:22.185211  8, 0x0, sum = 1

 4763 12:23:22.187747  9, 0x0, sum = 2

 4764 12:23:22.187956  10, 0x0, sum = 3

 4765 12:23:22.190915  11, 0x0, sum = 4

 4766 12:23:22.191086  best_step = 9

 4767 12:23:22.191230  

 4768 12:23:22.191373  ==

 4769 12:23:22.194332  Dram Type= 6, Freq= 0, CH_1, rank 1

 4770 12:23:22.197497  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4771 12:23:22.197636  ==

 4772 12:23:22.201087  RX Vref Scan: 0

 4773 12:23:22.201250  

 4774 12:23:22.203988  RX Vref 0 -> 0, step: 1

 4775 12:23:22.204165  

 4776 12:23:22.204341  RX Delay -195 -> 252, step: 8

 4777 12:23:22.212094  iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296

 4778 12:23:22.215635  iDelay=205, Bit 1, Center 40 (-107 ~ 188) 296

 4779 12:23:22.219062  iDelay=205, Bit 2, Center 32 (-115 ~ 180) 296

 4780 12:23:22.222711  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4781 12:23:22.228821  iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304

 4782 12:23:22.231850  iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296

 4783 12:23:22.235511  iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296

 4784 12:23:22.239175  iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304

 4785 12:23:22.242307  iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312

 4786 12:23:22.248726  iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312

 4787 12:23:22.252079  iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320

 4788 12:23:22.255831  iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312

 4789 12:23:22.258920  iDelay=205, Bit 12, Center 48 (-107 ~ 204) 312

 4790 12:23:22.265240  iDelay=205, Bit 13, Center 44 (-115 ~ 204) 320

 4791 12:23:22.268889  iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304

 4792 12:23:22.271803  iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312

 4793 12:23:22.272334  ==

 4794 12:23:22.275413  Dram Type= 6, Freq= 0, CH_1, rank 1

 4795 12:23:22.278439  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4796 12:23:22.281776  ==

 4797 12:23:22.282185  DQS Delay:

 4798 12:23:22.282510  DQS0 = 0, DQS1 = 0

 4799 12:23:22.285378  DQM Delay:

 4800 12:23:22.285787  DQM0 = 45, DQM1 = 36

 4801 12:23:22.288336  DQ Delay:

 4802 12:23:22.291577  DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44

 4803 12:23:22.292034  DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44

 4804 12:23:22.294843  DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24

 4805 12:23:22.301748  DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48

 4806 12:23:22.302160  

 4807 12:23:22.302481  

 4808 12:23:22.308081  [DQSOSCAuto] RK1, (LSB)MR18= 0x2a1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps

 4809 12:23:22.311405  CH1 RK1: MR19=808, MR18=2A1E

 4810 12:23:22.318499  CH1_RK1: MR19=0x808, MR18=0x2A1E, DQSOSC=401, MR23=63, INC=163, DEC=108

 4811 12:23:22.321401  [RxdqsGatingPostProcess] freq 600

 4812 12:23:22.324573  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4813 12:23:22.327863  Pre-setting of DQS Precalculation

 4814 12:23:22.334217  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4815 12:23:22.340929  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4816 12:23:22.347340  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4817 12:23:22.347884  

 4818 12:23:22.348270  

 4819 12:23:22.350817  [Calibration Summary] 1200 Mbps

 4820 12:23:22.351446  CH 0, Rank 0

 4821 12:23:22.353804  SW Impedance     : PASS

 4822 12:23:22.357360  DUTY Scan        : NO K

 4823 12:23:22.357862  ZQ Calibration   : PASS

 4824 12:23:22.360483  Jitter Meter     : NO K

 4825 12:23:22.363762  CBT Training     : PASS

 4826 12:23:22.364186  Write leveling   : PASS

 4827 12:23:22.367092  RX DQS gating    : PASS

 4828 12:23:22.370668  RX DQ/DQS(RDDQC) : PASS

 4829 12:23:22.371086  TX DQ/DQS        : PASS

 4830 12:23:22.373655  RX DATLAT        : PASS

 4831 12:23:22.376955  RX DQ/DQS(Engine): PASS

 4832 12:23:22.377371  TX OE            : NO K

 4833 12:23:22.379971  All Pass.

 4834 12:23:22.380389  

 4835 12:23:22.380717  CH 0, Rank 1

 4836 12:23:22.383532  SW Impedance     : PASS

 4837 12:23:22.384103  DUTY Scan        : NO K

 4838 12:23:22.387106  ZQ Calibration   : PASS

 4839 12:23:22.389822  Jitter Meter     : NO K

 4840 12:23:22.390345  CBT Training     : PASS

 4841 12:23:22.393503  Write leveling   : PASS

 4842 12:23:22.396645  RX DQS gating    : PASS

 4843 12:23:22.397116  RX DQ/DQS(RDDQC) : PASS

 4844 12:23:22.399884  TX DQ/DQS        : PASS

 4845 12:23:22.403114  RX DATLAT        : PASS

 4846 12:23:22.403521  RX DQ/DQS(Engine): PASS

 4847 12:23:22.406836  TX OE            : NO K

 4848 12:23:22.407399  All Pass.

 4849 12:23:22.407928  

 4850 12:23:22.409568  CH 1, Rank 0

 4851 12:23:22.410058  SW Impedance     : PASS

 4852 12:23:22.413104  DUTY Scan        : NO K

 4853 12:23:22.416674  ZQ Calibration   : PASS

 4854 12:23:22.417111  Jitter Meter     : NO K

 4855 12:23:22.419844  CBT Training     : PASS

 4856 12:23:22.423121  Write leveling   : PASS

 4857 12:23:22.423625  RX DQS gating    : PASS

 4858 12:23:22.426363  RX DQ/DQS(RDDQC) : PASS

 4859 12:23:22.429682  TX DQ/DQS        : PASS

 4860 12:23:22.430136  RX DATLAT        : PASS

 4861 12:23:22.432692  RX DQ/DQS(Engine): PASS

 4862 12:23:22.436406  TX OE            : NO K

 4863 12:23:22.436869  All Pass.

 4864 12:23:22.437348  

 4865 12:23:22.437669  CH 1, Rank 1

 4866 12:23:22.439618  SW Impedance     : PASS

 4867 12:23:22.442934  DUTY Scan        : NO K

 4868 12:23:22.443385  ZQ Calibration   : PASS

 4869 12:23:22.446334  Jitter Meter     : NO K

 4870 12:23:22.446760  CBT Training     : PASS

 4871 12:23:22.449520  Write leveling   : PASS

 4872 12:23:22.452647  RX DQS gating    : PASS

 4873 12:23:22.453073  RX DQ/DQS(RDDQC) : PASS

 4874 12:23:22.456220  TX DQ/DQS        : PASS

 4875 12:23:22.459327  RX DATLAT        : PASS

 4876 12:23:22.460054  RX DQ/DQS(Engine): PASS

 4877 12:23:22.462698  TX OE            : NO K

 4878 12:23:22.463148  All Pass.

 4879 12:23:22.463581  

 4880 12:23:22.465707  DramC Write-DBI off

 4881 12:23:22.469199  	PER_BANK_REFRESH: Hybrid Mode

 4882 12:23:22.469617  TX_TRACKING: ON

 4883 12:23:22.479278  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4884 12:23:22.482179  [FAST_K] Save calibration result to emmc

 4885 12:23:22.485388  dramc_set_vcore_voltage set vcore to 662500

 4886 12:23:22.488765  Read voltage for 933, 3

 4887 12:23:22.489183  Vio18 = 0

 4888 12:23:22.492215  Vcore = 662500

 4889 12:23:22.492632  Vdram = 0

 4890 12:23:22.492964  Vddq = 0

 4891 12:23:22.493335  Vmddr = 0

 4892 12:23:22.498761  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4893 12:23:22.502183  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4894 12:23:22.505769  MEM_TYPE=3, freq_sel=17

 4895 12:23:22.508565  sv_algorithm_assistance_LP4_1600 

 4896 12:23:22.512362  ============ PULL DRAM RESETB DOWN ============

 4897 12:23:22.518596  ========== PULL DRAM RESETB DOWN end =========

 4898 12:23:22.521690  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4899 12:23:22.525144  =================================== 

 4900 12:23:22.528489  LPDDR4 DRAM CONFIGURATION

 4901 12:23:22.531863  =================================== 

 4902 12:23:22.532284  EX_ROW_EN[0]    = 0x0

 4903 12:23:22.534861  EX_ROW_EN[1]    = 0x0

 4904 12:23:22.535317  LP4Y_EN      = 0x0

 4905 12:23:22.538407  WORK_FSP     = 0x0

 4906 12:23:22.538822  WL           = 0x3

 4907 12:23:22.541773  RL           = 0x3

 4908 12:23:22.542190  BL           = 0x2

 4909 12:23:22.545131  RPST         = 0x0

 4910 12:23:22.548429  RD_PRE       = 0x0

 4911 12:23:22.548899  WR_PRE       = 0x1

 4912 12:23:22.551928  WR_PST       = 0x0

 4913 12:23:22.552337  DBI_WR       = 0x0

 4914 12:23:22.554742  DBI_RD       = 0x0

 4915 12:23:22.555148  OTF          = 0x1

 4916 12:23:22.558060  =================================== 

 4917 12:23:22.561351  =================================== 

 4918 12:23:22.564256  ANA top config

 4919 12:23:22.567547  =================================== 

 4920 12:23:22.567637  DLL_ASYNC_EN            =  0

 4921 12:23:22.570946  ALL_SLAVE_EN            =  1

 4922 12:23:22.574109  NEW_RANK_MODE           =  1

 4923 12:23:22.577529  DLL_IDLE_MODE           =  1

 4924 12:23:22.580977  LP45_APHY_COMB_EN       =  1

 4925 12:23:22.581060  TX_ODT_DIS              =  1

 4926 12:23:22.583940  NEW_8X_MODE             =  1

 4927 12:23:22.587539  =================================== 

 4928 12:23:22.590495  =================================== 

 4929 12:23:22.593744  data_rate                  = 1866

 4930 12:23:22.597072  CKR                        = 1

 4931 12:23:22.600581  DQ_P2S_RATIO               = 8

 4932 12:23:22.603849  =================================== 

 4933 12:23:22.607046  CA_P2S_RATIO               = 8

 4934 12:23:22.607157  DQ_CA_OPEN                 = 0

 4935 12:23:22.610221  DQ_SEMI_OPEN               = 0

 4936 12:23:22.613699  CA_SEMI_OPEN               = 0

 4937 12:23:22.617037  CA_FULL_RATE               = 0

 4938 12:23:22.620846  DQ_CKDIV4_EN               = 1

 4939 12:23:22.620930  CA_CKDIV4_EN               = 1

 4940 12:23:22.624025  CA_PREDIV_EN               = 0

 4941 12:23:22.627063  PH8_DLY                    = 0

 4942 12:23:22.630429  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4943 12:23:22.633275  DQ_AAMCK_DIV               = 4

 4944 12:23:22.636710  CA_AAMCK_DIV               = 4

 4945 12:23:22.636800  CA_ADMCK_DIV               = 4

 4946 12:23:22.640508  DQ_TRACK_CA_EN             = 0

 4947 12:23:22.643476  CA_PICK                    = 933

 4948 12:23:22.646905  CA_MCKIO                   = 933

 4949 12:23:22.649976  MCKIO_SEMI                 = 0

 4950 12:23:22.653344  PLL_FREQ                   = 3732

 4951 12:23:22.656753  DQ_UI_PI_RATIO             = 32

 4952 12:23:22.659926  CA_UI_PI_RATIO             = 0

 4953 12:23:22.663434  =================================== 

 4954 12:23:22.666559  =================================== 

 4955 12:23:22.666734  memory_type:LPDDR4         

 4956 12:23:22.669784  GP_NUM     : 10       

 4957 12:23:22.673262  SRAM_EN    : 1       

 4958 12:23:22.673479  MD32_EN    : 0       

 4959 12:23:22.676811  =================================== 

 4960 12:23:22.679856  [ANA_INIT] >>>>>>>>>>>>>> 

 4961 12:23:22.683117  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4962 12:23:22.686412  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4963 12:23:22.689713  =================================== 

 4964 12:23:22.693559  data_rate = 1866,PCW = 0X8f00

 4965 12:23:22.696785  =================================== 

 4966 12:23:22.700602  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4967 12:23:22.702788  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4968 12:23:22.709841  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4969 12:23:22.712914  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4970 12:23:22.716004  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4971 12:23:22.720111  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4972 12:23:22.723213  [ANA_INIT] flow start 

 4973 12:23:22.726335  [ANA_INIT] PLL >>>>>>>> 

 4974 12:23:22.726743  [ANA_INIT] PLL <<<<<<<< 

 4975 12:23:22.729416  [ANA_INIT] MIDPI >>>>>>>> 

 4976 12:23:22.732765  [ANA_INIT] MIDPI <<<<<<<< 

 4977 12:23:22.735947  [ANA_INIT] DLL >>>>>>>> 

 4978 12:23:22.736579  [ANA_INIT] flow end 

 4979 12:23:22.739609  ============ LP4 DIFF to SE enter ============

 4980 12:23:22.745654  ============ LP4 DIFF to SE exit  ============

 4981 12:23:22.746061  [ANA_INIT] <<<<<<<<<<<<< 

 4982 12:23:22.749223  [Flow] Enable top DCM control >>>>> 

 4983 12:23:22.752472  [Flow] Enable top DCM control <<<<< 

 4984 12:23:22.756041  Enable DLL master slave shuffle 

 4985 12:23:22.762104  ============================================================== 

 4986 12:23:22.762608  Gating Mode config

 4987 12:23:22.769073  ============================================================== 

 4988 12:23:22.772301  Config description: 

 4989 12:23:22.782223  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4990 12:23:22.788536  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4991 12:23:22.791978  SELPH_MODE            0: By rank         1: By Phase 

 4992 12:23:22.798547  ============================================================== 

 4993 12:23:22.801851  GAT_TRACK_EN                 =  1

 4994 12:23:22.805246  RX_GATING_MODE               =  2

 4995 12:23:22.808355  RX_GATING_TRACK_MODE         =  2

 4996 12:23:22.808935  SELPH_MODE                   =  1

 4997 12:23:22.811967  PICG_EARLY_EN                =  1

 4998 12:23:22.815440  VALID_LAT_VALUE              =  1

 4999 12:23:22.821809  ============================================================== 

 5000 12:23:22.825596  Enter into Gating configuration >>>> 

 5001 12:23:22.828310  Exit from Gating configuration <<<< 

 5002 12:23:22.831538  Enter into  DVFS_PRE_config >>>>> 

 5003 12:23:22.841245  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 5004 12:23:22.845075  Exit from  DVFS_PRE_config <<<<< 

 5005 12:23:22.847981  Enter into PICG configuration >>>> 

 5006 12:23:22.851105  Exit from PICG configuration <<<< 

 5007 12:23:22.854264  [RX_INPUT] configuration >>>>> 

 5008 12:23:22.858019  [RX_INPUT] configuration <<<<< 

 5009 12:23:22.864447  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 5010 12:23:22.867637  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 5011 12:23:22.874934  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 5012 12:23:22.880805  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 5013 12:23:22.887626  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5014 12:23:22.894004  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5015 12:23:22.897736  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5016 12:23:22.900965  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5017 12:23:22.903751  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5018 12:23:22.910382  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5019 12:23:22.913785  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5020 12:23:22.917244  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5021 12:23:22.920431  =================================== 

 5022 12:23:22.923711  LPDDR4 DRAM CONFIGURATION

 5023 12:23:22.927034  =================================== 

 5024 12:23:22.927447  EX_ROW_EN[0]    = 0x0

 5025 12:23:22.930354  EX_ROW_EN[1]    = 0x0

 5026 12:23:22.933724  LP4Y_EN      = 0x0

 5027 12:23:22.934244  WORK_FSP     = 0x0

 5028 12:23:22.937140  WL           = 0x3

 5029 12:23:22.937656  RL           = 0x3

 5030 12:23:22.940199  BL           = 0x2

 5031 12:23:22.940613  RPST         = 0x0

 5032 12:23:22.943328  RD_PRE       = 0x0

 5033 12:23:22.943770  WR_PRE       = 0x1

 5034 12:23:22.946725  WR_PST       = 0x0

 5035 12:23:22.947139  DBI_WR       = 0x0

 5036 12:23:22.950152  DBI_RD       = 0x0

 5037 12:23:22.950566  OTF          = 0x1

 5038 12:23:22.953433  =================================== 

 5039 12:23:22.956771  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5040 12:23:22.963394  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5041 12:23:22.966778  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5042 12:23:22.970080  =================================== 

 5043 12:23:22.973023  LPDDR4 DRAM CONFIGURATION

 5044 12:23:22.976522  =================================== 

 5045 12:23:22.979638  EX_ROW_EN[0]    = 0x10

 5046 12:23:22.980121  EX_ROW_EN[1]    = 0x0

 5047 12:23:22.982912  LP4Y_EN      = 0x0

 5048 12:23:22.983330  WORK_FSP     = 0x0

 5049 12:23:22.986121  WL           = 0x3

 5050 12:23:22.986560  RL           = 0x3

 5051 12:23:22.989925  BL           = 0x2

 5052 12:23:22.990342  RPST         = 0x0

 5053 12:23:22.992721  RD_PRE       = 0x0

 5054 12:23:22.993137  WR_PRE       = 0x1

 5055 12:23:22.996167  WR_PST       = 0x0

 5056 12:23:22.996584  DBI_WR       = 0x0

 5057 12:23:22.999066  DBI_RD       = 0x0

 5058 12:23:22.999483  OTF          = 0x1

 5059 12:23:23.002867  =================================== 

 5060 12:23:23.009297  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5061 12:23:23.013834  nWR fixed to 30

 5062 12:23:23.017257  [ModeRegInit_LP4] CH0 RK0

 5063 12:23:23.017694  [ModeRegInit_LP4] CH0 RK1

 5064 12:23:23.020854  [ModeRegInit_LP4] CH1 RK0

 5065 12:23:23.023793  [ModeRegInit_LP4] CH1 RK1

 5066 12:23:23.024223  match AC timing 9

 5067 12:23:23.030477  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5068 12:23:23.033512  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5069 12:23:23.037153  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5070 12:23:23.044109  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5071 12:23:23.047114  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5072 12:23:23.047674  ==

 5073 12:23:23.049912  Dram Type= 6, Freq= 0, CH_0, rank 0

 5074 12:23:23.053875  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5075 12:23:23.056326  ==

 5076 12:23:23.060267  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5077 12:23:23.066622  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5078 12:23:23.069643  [CA 0] Center 37 (7~68) winsize 62

 5079 12:23:23.073224  [CA 1] Center 37 (7~68) winsize 62

 5080 12:23:23.076273  [CA 2] Center 34 (4~65) winsize 62

 5081 12:23:23.079505  [CA 3] Center 35 (5~65) winsize 61

 5082 12:23:23.082804  [CA 4] Center 33 (3~64) winsize 62

 5083 12:23:23.086244  [CA 5] Center 33 (3~63) winsize 61

 5084 12:23:23.086651  

 5085 12:23:23.089079  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5086 12:23:23.089489  

 5087 12:23:23.092628  [CATrainingPosCal] consider 1 rank data

 5088 12:23:23.095685  u2DelayCellTimex100 = 270/100 ps

 5089 12:23:23.099526  CA0 delay=37 (7~68),Diff = 4 PI (24 cell)

 5090 12:23:23.102751  CA1 delay=37 (7~68),Diff = 4 PI (24 cell)

 5091 12:23:23.109236  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5092 12:23:23.112736  CA3 delay=35 (5~65),Diff = 2 PI (12 cell)

 5093 12:23:23.115917  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 5094 12:23:23.119412  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 5095 12:23:23.119901  

 5096 12:23:23.122629  CA PerBit enable=1, Macro0, CA PI delay=33

 5097 12:23:23.123075  

 5098 12:23:23.125412  [CBTSetCACLKResult] CA Dly = 33

 5099 12:23:23.125874  CS Dly: 7 (0~38)

 5100 12:23:23.128928  ==

 5101 12:23:23.132200  Dram Type= 6, Freq= 0, CH_0, rank 1

 5102 12:23:23.135332  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5103 12:23:23.135785  ==

 5104 12:23:23.138571  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5105 12:23:23.145037  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5106 12:23:23.149105  [CA 0] Center 37 (7~68) winsize 62

 5107 12:23:23.152331  [CA 1] Center 37 (7~68) winsize 62

 5108 12:23:23.155832  [CA 2] Center 34 (4~65) winsize 62

 5109 12:23:23.158779  [CA 3] Center 35 (5~65) winsize 61

 5110 12:23:23.162500  [CA 4] Center 33 (3~64) winsize 62

 5111 12:23:23.165676  [CA 5] Center 32 (2~63) winsize 62

 5112 12:23:23.166091  

 5113 12:23:23.168776  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5114 12:23:23.169189  

 5115 12:23:23.172277  [CATrainingPosCal] consider 2 rank data

 5116 12:23:23.175676  u2DelayCellTimex100 = 270/100 ps

 5117 12:23:23.178619  CA0 delay=37 (7~68),Diff = 4 PI (24 cell)

 5118 12:23:23.185306  CA1 delay=37 (7~68),Diff = 4 PI (24 cell)

 5119 12:23:23.188808  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5120 12:23:23.192046  CA3 delay=35 (5~65),Diff = 2 PI (12 cell)

 5121 12:23:23.195526  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 5122 12:23:23.198707  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 5123 12:23:23.199122  

 5124 12:23:23.201456  CA PerBit enable=1, Macro0, CA PI delay=33

 5125 12:23:23.201870  

 5126 12:23:23.204610  [CBTSetCACLKResult] CA Dly = 33

 5127 12:23:23.207890  CS Dly: 7 (0~39)

 5128 12:23:23.207971  

 5129 12:23:23.211292  ----->DramcWriteLeveling(PI) begin...

 5130 12:23:23.211373  ==

 5131 12:23:23.214781  Dram Type= 6, Freq= 0, CH_0, rank 0

 5132 12:23:23.217666  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5133 12:23:23.217748  ==

 5134 12:23:23.221196  Write leveling (Byte 0): 34 => 34

 5135 12:23:23.224315  Write leveling (Byte 1): 29 => 29

 5136 12:23:23.227496  DramcWriteLeveling(PI) end<-----

 5137 12:23:23.227588  

 5138 12:23:23.227661  ==

 5139 12:23:23.231392  Dram Type= 6, Freq= 0, CH_0, rank 0

 5140 12:23:23.234479  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5141 12:23:23.234588  ==

 5142 12:23:23.237900  [Gating] SW mode calibration

 5143 12:23:23.244345  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5144 12:23:23.251162  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5145 12:23:23.254093   0 14  0 | B1->B0 | 2323 3030 | 1 0 | (1 1) (0 0)

 5146 12:23:23.260993   0 14  4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)

 5147 12:23:23.264076   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5148 12:23:23.267701   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5149 12:23:23.274200   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5150 12:23:23.277592   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5151 12:23:23.281204   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5152 12:23:23.287515   0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)

 5153 12:23:23.290857   0 15  0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)

 5154 12:23:23.294066   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5155 12:23:23.300358   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5156 12:23:23.303833   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5157 12:23:23.307358   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5158 12:23:23.313984   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5159 12:23:23.316805   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5160 12:23:23.320585   0 15 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)

 5161 12:23:23.326846   1  0  0 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0)

 5162 12:23:23.330366   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5163 12:23:23.333710   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5164 12:23:23.340415   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5165 12:23:23.343492   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5166 12:23:23.346757   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5167 12:23:23.353475   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5168 12:23:23.357157   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5169 12:23:23.360058   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5170 12:23:23.366452   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5171 12:23:23.370112   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5172 12:23:23.373260   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5173 12:23:23.379632   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5174 12:23:23.382998   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5175 12:23:23.386352   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5176 12:23:23.393064   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5177 12:23:23.395844   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5178 12:23:23.399380   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5179 12:23:23.406210   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5180 12:23:23.409597   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5181 12:23:23.412723   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5182 12:23:23.419464   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5183 12:23:23.422451   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5184 12:23:23.426268   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5185 12:23:23.432502   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5186 12:23:23.433001  Total UI for P1: 0, mck2ui 16

 5187 12:23:23.435708  best dqsien dly found for B0: ( 1,  2, 28)

 5188 12:23:23.442656   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5189 12:23:23.445640  Total UI for P1: 0, mck2ui 16

 5190 12:23:23.449374  best dqsien dly found for B1: ( 1,  3,  0)

 5191 12:23:23.452313  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5192 12:23:23.455615  best DQS1 dly(MCK, UI, PI) = (1, 3, 0)

 5193 12:23:23.456079  

 5194 12:23:23.458931  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5195 12:23:23.462460  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5196 12:23:23.465804  [Gating] SW calibration Done

 5197 12:23:23.466400  ==

 5198 12:23:23.469118  Dram Type= 6, Freq= 0, CH_0, rank 0

 5199 12:23:23.472509  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5200 12:23:23.472930  ==

 5201 12:23:23.475388  RX Vref Scan: 0

 5202 12:23:23.475855  

 5203 12:23:23.478815  RX Vref 0 -> 0, step: 1

 5204 12:23:23.479266  

 5205 12:23:23.479597  RX Delay -80 -> 252, step: 8

 5206 12:23:23.485720  iDelay=208, Bit 0, Center 99 (0 ~ 199) 200

 5207 12:23:23.489415  iDelay=208, Bit 1, Center 99 (0 ~ 199) 200

 5208 12:23:23.492126  iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200

 5209 12:23:23.495228  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5210 12:23:23.498886  iDelay=208, Bit 4, Center 99 (0 ~ 199) 200

 5211 12:23:23.502267  iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208

 5212 12:23:23.508603  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5213 12:23:23.511860  iDelay=208, Bit 7, Center 107 (8 ~ 207) 200

 5214 12:23:23.515192  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5215 12:23:23.518520  iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200

 5216 12:23:23.521951  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5217 12:23:23.528425  iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192

 5218 12:23:23.531579  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5219 12:23:23.535286  iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200

 5220 12:23:23.538732  iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200

 5221 12:23:23.542013  iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200

 5222 12:23:23.545284  ==

 5223 12:23:23.545746  Dram Type= 6, Freq= 0, CH_0, rank 0

 5224 12:23:23.551289  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5225 12:23:23.551852  ==

 5226 12:23:23.552224  DQS Delay:

 5227 12:23:23.554662  DQS0 = 0, DQS1 = 0

 5228 12:23:23.555073  DQM Delay:

 5229 12:23:23.557823  DQM0 = 97, DQM1 = 86

 5230 12:23:23.558270  DQ Delay:

 5231 12:23:23.561015  DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91

 5232 12:23:23.564562  DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107

 5233 12:23:23.567592  DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79

 5234 12:23:23.571481  DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91

 5235 12:23:23.571936  

 5236 12:23:23.572291  

 5237 12:23:23.572599  ==

 5238 12:23:23.574472  Dram Type= 6, Freq= 0, CH_0, rank 0

 5239 12:23:23.577575  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5240 12:23:23.578020  ==

 5241 12:23:23.578369  

 5242 12:23:23.578689  

 5243 12:23:23.581109  	TX Vref Scan disable

 5244 12:23:23.584084   == TX Byte 0 ==

 5245 12:23:23.587596  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5246 12:23:23.591000  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5247 12:23:23.594519   == TX Byte 1 ==

 5248 12:23:23.597273  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5249 12:23:23.600849  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5250 12:23:23.600934  ==

 5251 12:23:23.603670  Dram Type= 6, Freq= 0, CH_0, rank 0

 5252 12:23:23.610353  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5253 12:23:23.610439  ==

 5254 12:23:23.610505  

 5255 12:23:23.610564  

 5256 12:23:23.610621  	TX Vref Scan disable

 5257 12:23:23.614652   == TX Byte 0 ==

 5258 12:23:23.617929  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5259 12:23:23.624463  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5260 12:23:23.624559   == TX Byte 1 ==

 5261 12:23:23.627561  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5262 12:23:23.634524  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5263 12:23:23.634645  

 5264 12:23:23.634740  [DATLAT]

 5265 12:23:23.634829  Freq=933, CH0 RK0

 5266 12:23:23.634916  

 5267 12:23:23.637757  DATLAT Default: 0xd

 5268 12:23:23.637878  0, 0xFFFF, sum = 0

 5269 12:23:23.641520  1, 0xFFFF, sum = 0

 5270 12:23:23.644753  2, 0xFFFF, sum = 0

 5271 12:23:23.645175  3, 0xFFFF, sum = 0

 5272 12:23:23.647970  4, 0xFFFF, sum = 0

 5273 12:23:23.648396  5, 0xFFFF, sum = 0

 5274 12:23:23.651360  6, 0xFFFF, sum = 0

 5275 12:23:23.651966  7, 0xFFFF, sum = 0

 5276 12:23:23.654625  8, 0xFFFF, sum = 0

 5277 12:23:23.655138  9, 0xFFFF, sum = 0

 5278 12:23:23.657634  10, 0x0, sum = 1

 5279 12:23:23.658059  11, 0x0, sum = 2

 5280 12:23:23.660826  12, 0x0, sum = 3

 5281 12:23:23.661247  13, 0x0, sum = 4

 5282 12:23:23.661622  best_step = 11

 5283 12:23:23.664379  

 5284 12:23:23.664794  ==

 5285 12:23:23.668112  Dram Type= 6, Freq= 0, CH_0, rank 0

 5286 12:23:23.671043  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5287 12:23:23.671670  ==

 5288 12:23:23.672164  RX Vref Scan: 1

 5289 12:23:23.672520  

 5290 12:23:23.673983  RX Vref 0 -> 0, step: 1

 5291 12:23:23.674444  

 5292 12:23:23.677436  RX Delay -69 -> 252, step: 4

 5293 12:23:23.677900  

 5294 12:23:23.680575  Set Vref, RX VrefLevel [Byte0]: 60

 5295 12:23:23.683867                           [Byte1]: 56

 5296 12:23:23.687483  

 5297 12:23:23.687941  Final RX Vref Byte 0 = 60 to rank0

 5298 12:23:23.690895  Final RX Vref Byte 1 = 56 to rank0

 5299 12:23:23.694333  Final RX Vref Byte 0 = 60 to rank1

 5300 12:23:23.697749  Final RX Vref Byte 1 = 56 to rank1==

 5301 12:23:23.700911  Dram Type= 6, Freq= 0, CH_0, rank 0

 5302 12:23:23.707090  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5303 12:23:23.707210  ==

 5304 12:23:23.707274  DQS Delay:

 5305 12:23:23.707334  DQS0 = 0, DQS1 = 0

 5306 12:23:23.710706  DQM Delay:

 5307 12:23:23.711168  DQM0 = 96, DQM1 = 86

 5308 12:23:23.714261  DQ Delay:

 5309 12:23:23.717578  DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92

 5310 12:23:23.720653  DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106

 5311 12:23:23.723864  DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82

 5312 12:23:23.727168  DQ12 =90, DQ13 =88, DQ14 =94, DQ15 =92

 5313 12:23:23.727582  

 5314 12:23:23.727981  

 5315 12:23:23.733914  [DQSOSCAuto] RK0, (LSB)MR18= 0x2a10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps

 5316 12:23:23.737327  CH0 RK0: MR19=505, MR18=2A10

 5317 12:23:23.744271  CH0_RK0: MR19=0x505, MR18=0x2A10, DQSOSC=408, MR23=63, INC=65, DEC=43

 5318 12:23:23.744781  

 5319 12:23:23.747497  ----->DramcWriteLeveling(PI) begin...

 5320 12:23:23.748070  ==

 5321 12:23:23.750659  Dram Type= 6, Freq= 0, CH_0, rank 1

 5322 12:23:23.754444  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5323 12:23:23.755006  ==

 5324 12:23:23.757460  Write leveling (Byte 0): 33 => 33

 5325 12:23:23.760468  Write leveling (Byte 1): 33 => 33

 5326 12:23:23.763317  DramcWriteLeveling(PI) end<-----

 5327 12:23:23.763810  

 5328 12:23:23.764173  ==

 5329 12:23:23.767438  Dram Type= 6, Freq= 0, CH_0, rank 1

 5330 12:23:23.770195  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5331 12:23:23.773420  ==

 5332 12:23:23.774015  [Gating] SW mode calibration

 5333 12:23:23.783189  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5334 12:23:23.786552  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5335 12:23:23.789946   0 14  0 | B1->B0 | 2929 3131 | 0 0 | (0 0) (1 1)

 5336 12:23:23.796023   0 14  4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 5337 12:23:23.799530   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5338 12:23:23.802863   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5339 12:23:23.809843   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5340 12:23:23.812912   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5341 12:23:23.815947   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5342 12:23:23.822409   0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)

 5343 12:23:23.825661   0 15  0 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)

 5344 12:23:23.829036   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5345 12:23:23.835672   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5346 12:23:23.839091   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5347 12:23:23.842865   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5348 12:23:23.848846   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5349 12:23:23.852461   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5350 12:23:23.855542   0 15 28 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)

 5351 12:23:23.862424   1  0  0 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)

 5352 12:23:23.865962   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5353 12:23:23.868505   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5354 12:23:23.875439   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5355 12:23:23.878767   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5356 12:23:23.885237   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5357 12:23:23.888517   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5358 12:23:23.891619   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5359 12:23:23.897960   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5360 12:23:23.901576   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5361 12:23:23.904956   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5362 12:23:23.908209   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5363 12:23:23.915011   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5364 12:23:23.918363   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5365 12:23:23.921152   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5366 12:23:23.927647   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5367 12:23:23.931115   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5368 12:23:23.937939   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5369 12:23:23.941337   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5370 12:23:23.944156   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5371 12:23:23.951231   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5372 12:23:23.954490   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5373 12:23:23.957729   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5374 12:23:23.964130   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5375 12:23:23.967622   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5376 12:23:23.971088  Total UI for P1: 0, mck2ui 16

 5377 12:23:23.974386  best dqsien dly found for B0: ( 1,  2, 28)

 5378 12:23:23.977471   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5379 12:23:23.980772  Total UI for P1: 0, mck2ui 16

 5380 12:23:23.984424  best dqsien dly found for B1: ( 1,  2, 30)

 5381 12:23:23.987395  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5382 12:23:23.990387  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5383 12:23:23.990840  

 5384 12:23:23.994066  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5385 12:23:24.000427  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5386 12:23:24.001001  [Gating] SW calibration Done

 5387 12:23:24.001427  ==

 5388 12:23:24.003570  Dram Type= 6, Freq= 0, CH_0, rank 1

 5389 12:23:24.010416  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5390 12:23:24.011060  ==

 5391 12:23:24.011428  RX Vref Scan: 0

 5392 12:23:24.011835  

 5393 12:23:24.013444  RX Vref 0 -> 0, step: 1

 5394 12:23:24.013926  

 5395 12:23:24.016658  RX Delay -80 -> 252, step: 8

 5396 12:23:24.020301  iDelay=208, Bit 0, Center 95 (0 ~ 191) 192

 5397 12:23:24.023328  iDelay=208, Bit 1, Center 99 (0 ~ 199) 200

 5398 12:23:24.026809  iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200

 5399 12:23:24.033292  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5400 12:23:24.036602  iDelay=208, Bit 4, Center 99 (0 ~ 199) 200

 5401 12:23:24.039951  iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192

 5402 12:23:24.043246  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5403 12:23:24.047062  iDelay=208, Bit 7, Center 107 (8 ~ 207) 200

 5404 12:23:24.049836  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5405 12:23:24.056773  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5406 12:23:24.060446  iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200

 5407 12:23:24.063306  iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192

 5408 12:23:24.066361  iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200

 5409 12:23:24.069870  iDelay=208, Bit 13, Center 95 (0 ~ 191) 192

 5410 12:23:24.076470  iDelay=208, Bit 14, Center 99 (0 ~ 199) 200

 5411 12:23:24.079805  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5412 12:23:24.080383  ==

 5413 12:23:24.082873  Dram Type= 6, Freq= 0, CH_0, rank 1

 5414 12:23:24.086382  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5415 12:23:24.086941  ==

 5416 12:23:24.087305  DQS Delay:

 5417 12:23:24.089585  DQS0 = 0, DQS1 = 0

 5418 12:23:24.090043  DQM Delay:

 5419 12:23:24.093155  DQM0 = 97, DQM1 = 89

 5420 12:23:24.093625  DQ Delay:

 5421 12:23:24.096175  DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91

 5422 12:23:24.099570  DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107

 5423 12:23:24.102629  DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87

 5424 12:23:24.106002  DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95

 5425 12:23:24.106463  

 5426 12:23:24.106823  

 5427 12:23:24.107237  ==

 5428 12:23:24.109224  Dram Type= 6, Freq= 0, CH_0, rank 1

 5429 12:23:24.116065  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5430 12:23:24.116526  ==

 5431 12:23:24.116888  

 5432 12:23:24.117224  

 5433 12:23:24.117546  	TX Vref Scan disable

 5434 12:23:24.119012   == TX Byte 0 ==

 5435 12:23:24.122369  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5436 12:23:24.128978  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5437 12:23:24.129396   == TX Byte 1 ==

 5438 12:23:24.132686  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5439 12:23:24.139127  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5440 12:23:24.139587  ==

 5441 12:23:24.142119  Dram Type= 6, Freq= 0, CH_0, rank 1

 5442 12:23:24.145775  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5443 12:23:24.146190  ==

 5444 12:23:24.146556  

 5445 12:23:24.146866  

 5446 12:23:24.148945  	TX Vref Scan disable

 5447 12:23:24.149431   == TX Byte 0 ==

 5448 12:23:24.155178  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5449 12:23:24.158536  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5450 12:23:24.161909   == TX Byte 1 ==

 5451 12:23:24.165634  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5452 12:23:24.168816  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5453 12:23:24.169454  

 5454 12:23:24.169827  [DATLAT]

 5455 12:23:24.171683  Freq=933, CH0 RK1

 5456 12:23:24.172139  

 5457 12:23:24.172470  DATLAT Default: 0xb

 5458 12:23:24.175223  0, 0xFFFF, sum = 0

 5459 12:23:24.178625  1, 0xFFFF, sum = 0

 5460 12:23:24.179044  2, 0xFFFF, sum = 0

 5461 12:23:24.181963  3, 0xFFFF, sum = 0

 5462 12:23:24.182381  4, 0xFFFF, sum = 0

 5463 12:23:24.185382  5, 0xFFFF, sum = 0

 5464 12:23:24.185895  6, 0xFFFF, sum = 0

 5465 12:23:24.188415  7, 0xFFFF, sum = 0

 5466 12:23:24.188835  8, 0xFFFF, sum = 0

 5467 12:23:24.191483  9, 0xFFFF, sum = 0

 5468 12:23:24.191955  10, 0x0, sum = 1

 5469 12:23:24.194724  11, 0x0, sum = 2

 5470 12:23:24.195189  12, 0x0, sum = 3

 5471 12:23:24.198532  13, 0x0, sum = 4

 5472 12:23:24.199070  best_step = 11

 5473 12:23:24.199404  

 5474 12:23:24.199708  ==

 5475 12:23:24.202372  Dram Type= 6, Freq= 0, CH_0, rank 1

 5476 12:23:24.204916  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5477 12:23:24.205331  ==

 5478 12:23:24.208256  RX Vref Scan: 0

 5479 12:23:24.208703  

 5480 12:23:24.211428  RX Vref 0 -> 0, step: 1

 5481 12:23:24.211897  

 5482 12:23:24.212276  RX Delay -61 -> 252, step: 4

 5483 12:23:24.219576  iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188

 5484 12:23:24.222990  iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196

 5485 12:23:24.226677  iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184

 5486 12:23:24.229300  iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192

 5487 12:23:24.233295  iDelay=203, Bit 4, Center 96 (3 ~ 190) 188

 5488 12:23:24.239487  iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192

 5489 12:23:24.242996  iDelay=203, Bit 6, Center 106 (11 ~ 202) 192

 5490 12:23:24.246645  iDelay=203, Bit 7, Center 104 (11 ~ 198) 188

 5491 12:23:24.249325  iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188

 5492 12:23:24.252424  iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188

 5493 12:23:24.259297  iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188

 5494 12:23:24.262447  iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188

 5495 12:23:24.266034  iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188

 5496 12:23:24.268795  iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188

 5497 12:23:24.272155  iDelay=203, Bit 14, Center 96 (3 ~ 190) 188

 5498 12:23:24.279377  iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188

 5499 12:23:24.279978  ==

 5500 12:23:24.282303  Dram Type= 6, Freq= 0, CH_0, rank 1

 5501 12:23:24.285633  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5502 12:23:24.286093  ==

 5503 12:23:24.286456  DQS Delay:

 5504 12:23:24.288730  DQS0 = 0, DQS1 = 0

 5505 12:23:24.289186  DQM Delay:

 5506 12:23:24.292075  DQM0 = 95, DQM1 = 87

 5507 12:23:24.292530  DQ Delay:

 5508 12:23:24.295116  DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94

 5509 12:23:24.298779  DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104

 5510 12:23:24.302213  DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =80

 5511 12:23:24.305718  DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92

 5512 12:23:24.306133  

 5513 12:23:24.306466  

 5514 12:23:24.315525  [DQSOSCAuto] RK1, (LSB)MR18= 0x27f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps

 5515 12:23:24.316101  CH0 RK1: MR19=504, MR18=27F8

 5516 12:23:24.322216  CH0_RK1: MR19=0x504, MR18=0x27F8, DQSOSC=409, MR23=63, INC=64, DEC=43

 5517 12:23:24.325113  [RxdqsGatingPostProcess] freq 933

 5518 12:23:24.331546  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5519 12:23:24.335150  best DQS0 dly(2T, 0.5T) = (0, 10)

 5520 12:23:24.338205  best DQS1 dly(2T, 0.5T) = (0, 11)

 5521 12:23:24.341595  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5522 12:23:24.344835  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5523 12:23:24.347983  best DQS0 dly(2T, 0.5T) = (0, 10)

 5524 12:23:24.348438  best DQS1 dly(2T, 0.5T) = (0, 10)

 5525 12:23:24.351517  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5526 12:23:24.354678  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5527 12:23:24.357890  Pre-setting of DQS Precalculation

 5528 12:23:24.364404  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5529 12:23:24.365016  ==

 5530 12:23:24.367865  Dram Type= 6, Freq= 0, CH_1, rank 0

 5531 12:23:24.370640  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5532 12:23:24.371177  ==

 5533 12:23:24.377698  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5534 12:23:24.384554  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5535 12:23:24.388200  [CA 0] Center 36 (6~67) winsize 62

 5536 12:23:24.390938  [CA 1] Center 36 (6~67) winsize 62

 5537 12:23:24.394075  [CA 2] Center 34 (4~65) winsize 62

 5538 12:23:24.397369  [CA 3] Center 33 (3~64) winsize 62

 5539 12:23:24.400991  [CA 4] Center 34 (4~64) winsize 61

 5540 12:23:24.404310  [CA 5] Center 33 (3~64) winsize 62

 5541 12:23:24.404723  

 5542 12:23:24.407003  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5543 12:23:24.407417  

 5544 12:23:24.410119  [CATrainingPosCal] consider 1 rank data

 5545 12:23:24.413377  u2DelayCellTimex100 = 270/100 ps

 5546 12:23:24.416805  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5547 12:23:24.420593  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5548 12:23:24.423690  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5549 12:23:24.426751  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5550 12:23:24.429790  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5551 12:23:24.436627  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5552 12:23:24.437058  

 5553 12:23:24.439891  CA PerBit enable=1, Macro0, CA PI delay=33

 5554 12:23:24.440306  

 5555 12:23:24.443108  [CBTSetCACLKResult] CA Dly = 33

 5556 12:23:24.443520  CS Dly: 5 (0~36)

 5557 12:23:24.443881  ==

 5558 12:23:24.446429  Dram Type= 6, Freq= 0, CH_1, rank 1

 5559 12:23:24.450263  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5560 12:23:24.453343  ==

 5561 12:23:24.456847  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5562 12:23:24.463695  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5563 12:23:24.466192  [CA 0] Center 36 (6~67) winsize 62

 5564 12:23:24.469868  [CA 1] Center 36 (6~67) winsize 62

 5565 12:23:24.473254  [CA 2] Center 34 (4~65) winsize 62

 5566 12:23:24.476195  [CA 3] Center 33 (3~64) winsize 62

 5567 12:23:24.480118  [CA 4] Center 34 (3~65) winsize 63

 5568 12:23:24.482674  [CA 5] Center 33 (3~64) winsize 62

 5569 12:23:24.483135  

 5570 12:23:24.485985  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5571 12:23:24.486442  

 5572 12:23:24.489276  [CATrainingPosCal] consider 2 rank data

 5573 12:23:24.492582  u2DelayCellTimex100 = 270/100 ps

 5574 12:23:24.496204  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5575 12:23:24.499410  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5576 12:23:24.506429  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5577 12:23:24.509419  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5578 12:23:24.512501  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5579 12:23:24.515432  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5580 12:23:24.515921  

 5581 12:23:24.519140  CA PerBit enable=1, Macro0, CA PI delay=33

 5582 12:23:24.519694  

 5583 12:23:24.522505  [CBTSetCACLKResult] CA Dly = 33

 5584 12:23:24.522916  CS Dly: 6 (0~39)

 5585 12:23:24.525353  

 5586 12:23:24.529050  ----->DramcWriteLeveling(PI) begin...

 5587 12:23:24.529604  ==

 5588 12:23:24.532107  Dram Type= 6, Freq= 0, CH_1, rank 0

 5589 12:23:24.535746  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5590 12:23:24.536173  ==

 5591 12:23:24.538674  Write leveling (Byte 0): 26 => 26

 5592 12:23:24.541798  Write leveling (Byte 1): 27 => 27

 5593 12:23:24.545799  DramcWriteLeveling(PI) end<-----

 5594 12:23:24.546460  

 5595 12:23:24.547096  ==

 5596 12:23:24.548546  Dram Type= 6, Freq= 0, CH_1, rank 0

 5597 12:23:24.552305  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5598 12:23:24.553025  ==

 5599 12:23:24.554875  [Gating] SW mode calibration

 5600 12:23:24.562015  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5601 12:23:24.568256  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5602 12:23:24.571833   0 14  0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

 5603 12:23:24.574721   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5604 12:23:24.581503   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5605 12:23:24.584620   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5606 12:23:24.588306   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5607 12:23:24.594410   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5608 12:23:24.598009   0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 5609 12:23:24.601326   0 14 28 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)

 5610 12:23:24.607838   0 15  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 5611 12:23:24.611194   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5612 12:23:24.614588   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5613 12:23:24.620891   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5614 12:23:24.624449   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5615 12:23:24.627563   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5616 12:23:24.634130   0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 5617 12:23:24.637583   0 15 28 | B1->B0 | 3737 3939 | 0 0 | (0 0) (0 0)

 5618 12:23:24.640807   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5619 12:23:24.647538   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5620 12:23:24.650487   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5621 12:23:24.653723   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5622 12:23:24.660432   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5623 12:23:24.663644   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5624 12:23:24.667278   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5625 12:23:24.674052   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5626 12:23:24.677274   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5627 12:23:24.680211   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5628 12:23:24.687109   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5629 12:23:24.690804   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5630 12:23:24.693315   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5631 12:23:24.700276   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5632 12:23:24.703236   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5633 12:23:24.706470   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5634 12:23:24.713048   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5635 12:23:24.716692   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5636 12:23:24.719702   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5637 12:23:24.726619   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5638 12:23:24.729903   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5639 12:23:24.733153   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5640 12:23:24.739451   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5641 12:23:24.743617   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5642 12:23:24.746725  Total UI for P1: 0, mck2ui 16

 5643 12:23:24.750340  best dqsien dly found for B0: ( 1,  2, 24)

 5644 12:23:24.752821  Total UI for P1: 0, mck2ui 16

 5645 12:23:24.756054  best dqsien dly found for B1: ( 1,  2, 26)

 5646 12:23:24.759106  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5647 12:23:24.763144  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5648 12:23:24.763872  

 5649 12:23:24.766294  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5650 12:23:24.772695  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5651 12:23:24.773250  [Gating] SW calibration Done

 5652 12:23:24.773689  ==

 5653 12:23:24.776046  Dram Type= 6, Freq= 0, CH_1, rank 0

 5654 12:23:24.782750  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5655 12:23:24.783282  ==

 5656 12:23:24.783775  RX Vref Scan: 0

 5657 12:23:24.784194  

 5658 12:23:24.785582  RX Vref 0 -> 0, step: 1

 5659 12:23:24.786007  

 5660 12:23:24.788768  RX Delay -80 -> 252, step: 8

 5661 12:23:24.791950  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5662 12:23:24.795828  iDelay=208, Bit 1, Center 99 (8 ~ 191) 184

 5663 12:23:24.798560  iDelay=208, Bit 2, Center 95 (0 ~ 191) 192

 5664 12:23:24.802182  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5665 12:23:24.808767  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5666 12:23:24.812128  iDelay=208, Bit 5, Center 111 (16 ~ 207) 192

 5667 12:23:24.814992  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5668 12:23:24.818852  iDelay=208, Bit 7, Center 99 (8 ~ 191) 184

 5669 12:23:24.821608  iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200

 5670 12:23:24.828292  iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200

 5671 12:23:24.831512  iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200

 5672 12:23:24.834985  iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184

 5673 12:23:24.838308  iDelay=208, Bit 12, Center 99 (0 ~ 199) 200

 5674 12:23:24.841464  iDelay=208, Bit 13, Center 99 (0 ~ 199) 200

 5675 12:23:24.848403  iDelay=208, Bit 14, Center 99 (0 ~ 199) 200

 5676 12:23:24.851695  iDelay=208, Bit 15, Center 103 (8 ~ 199) 192

 5677 12:23:24.852159  ==

 5678 12:23:24.854828  Dram Type= 6, Freq= 0, CH_1, rank 0

 5679 12:23:24.858381  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5680 12:23:24.858806  ==

 5681 12:23:24.859239  DQS Delay:

 5682 12:23:24.861815  DQS0 = 0, DQS1 = 0

 5683 12:23:24.862242  DQM Delay:

 5684 12:23:24.864484  DQM0 = 101, DQM1 = 91

 5685 12:23:24.865048  DQ Delay:

 5686 12:23:24.867968  DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99

 5687 12:23:24.871386  DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99

 5688 12:23:24.874383  DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =83

 5689 12:23:24.877819  DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103

 5690 12:23:24.878351  

 5691 12:23:24.878783  

 5692 12:23:24.879190  ==

 5693 12:23:24.881174  Dram Type= 6, Freq= 0, CH_1, rank 0

 5694 12:23:24.887828  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5695 12:23:24.888257  ==

 5696 12:23:24.888683  

 5697 12:23:24.889087  

 5698 12:23:24.889497  	TX Vref Scan disable

 5699 12:23:24.891483   == TX Byte 0 ==

 5700 12:23:24.894460  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5701 12:23:24.901220  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5702 12:23:24.901671   == TX Byte 1 ==

 5703 12:23:24.904743  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5704 12:23:24.911165  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5705 12:23:24.911591  ==

 5706 12:23:24.914609  Dram Type= 6, Freq= 0, CH_1, rank 0

 5707 12:23:24.917891  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5708 12:23:24.918358  ==

 5709 12:23:24.918791  

 5710 12:23:24.919197  

 5711 12:23:24.921061  	TX Vref Scan disable

 5712 12:23:24.921578   == TX Byte 0 ==

 5713 12:23:24.927807  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5714 12:23:24.931035  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5715 12:23:24.933998   == TX Byte 1 ==

 5716 12:23:24.937384  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5717 12:23:24.940535  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5718 12:23:24.941101  

 5719 12:23:24.941615  [DATLAT]

 5720 12:23:24.943656  Freq=933, CH1 RK0

 5721 12:23:24.944104  

 5722 12:23:24.944608  DATLAT Default: 0xd

 5723 12:23:24.947592  0, 0xFFFF, sum = 0

 5724 12:23:24.950563  1, 0xFFFF, sum = 0

 5725 12:23:24.951120  2, 0xFFFF, sum = 0

 5726 12:23:24.953960  3, 0xFFFF, sum = 0

 5727 12:23:24.954391  4, 0xFFFF, sum = 0

 5728 12:23:24.957472  5, 0xFFFF, sum = 0

 5729 12:23:24.957902  6, 0xFFFF, sum = 0

 5730 12:23:24.960203  7, 0xFFFF, sum = 0

 5731 12:23:24.960630  8, 0xFFFF, sum = 0

 5732 12:23:24.964127  9, 0xFFFF, sum = 0

 5733 12:23:24.964554  10, 0x0, sum = 1

 5734 12:23:24.967139  11, 0x0, sum = 2

 5735 12:23:24.967590  12, 0x0, sum = 3

 5736 12:23:24.970685  13, 0x0, sum = 4

 5737 12:23:24.971168  best_step = 11

 5738 12:23:24.971592  

 5739 12:23:24.972032  ==

 5740 12:23:24.974215  Dram Type= 6, Freq= 0, CH_1, rank 0

 5741 12:23:24.977321  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5742 12:23:24.977767  ==

 5743 12:23:24.980230  RX Vref Scan: 1

 5744 12:23:24.980654  

 5745 12:23:24.983675  RX Vref 0 -> 0, step: 1

 5746 12:23:24.984147  

 5747 12:23:24.984584  RX Delay -69 -> 252, step: 4

 5748 12:23:24.984994  

 5749 12:23:24.987024  Set Vref, RX VrefLevel [Byte0]: 47

 5750 12:23:24.990462                           [Byte1]: 59

 5751 12:23:24.995625  

 5752 12:23:24.996184  Final RX Vref Byte 0 = 47 to rank0

 5753 12:23:24.998140  Final RX Vref Byte 1 = 59 to rank0

 5754 12:23:25.001767  Final RX Vref Byte 0 = 47 to rank1

 5755 12:23:25.004710  Final RX Vref Byte 1 = 59 to rank1==

 5756 12:23:25.008132  Dram Type= 6, Freq= 0, CH_1, rank 0

 5757 12:23:25.014874  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5758 12:23:25.015301  ==

 5759 12:23:25.015765  DQS Delay:

 5760 12:23:25.017810  DQS0 = 0, DQS1 = 0

 5761 12:23:25.018234  DQM Delay:

 5762 12:23:25.021793  DQM0 = 100, DQM1 = 94

 5763 12:23:25.022256  DQ Delay:

 5764 12:23:25.024873  DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98

 5765 12:23:25.028181  DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =96

 5766 12:23:25.031584  DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =84

 5767 12:23:25.034724  DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102

 5768 12:23:25.035150  

 5769 12:23:25.035579  

 5770 12:23:25.041755  [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps

 5771 12:23:25.044343  CH1 RK0: MR19=505, MR18=1B0B

 5772 12:23:25.051681  CH1_RK0: MR19=0x505, MR18=0x1B0B, DQSOSC=413, MR23=63, INC=63, DEC=42

 5773 12:23:25.052252  

 5774 12:23:25.054582  ----->DramcWriteLeveling(PI) begin...

 5775 12:23:25.055106  ==

 5776 12:23:25.057861  Dram Type= 6, Freq= 0, CH_1, rank 1

 5777 12:23:25.061007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5778 12:23:25.064165  ==

 5779 12:23:25.067469  Write leveling (Byte 0): 26 => 26

 5780 12:23:25.067945  Write leveling (Byte 1): 27 => 27

 5781 12:23:25.070692  DramcWriteLeveling(PI) end<-----

 5782 12:23:25.071150  

 5783 12:23:25.071587  ==

 5784 12:23:25.074194  Dram Type= 6, Freq= 0, CH_1, rank 1

 5785 12:23:25.080915  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5786 12:23:25.081456  ==

 5787 12:23:25.084428  [Gating] SW mode calibration

 5788 12:23:25.090702  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5789 12:23:25.093907  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5790 12:23:25.100596   0 14  0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)

 5791 12:23:25.104214   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5792 12:23:25.107172   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5793 12:23:25.113740   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5794 12:23:25.116659   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5795 12:23:25.120853   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5796 12:23:25.127144   0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)

 5797 12:23:25.130406   0 14 28 | B1->B0 | 2a2a 2a2a | 0 0 | (0 0) (1 0)

 5798 12:23:25.133550   0 15  0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 5799 12:23:25.140100   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5800 12:23:25.143481   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5801 12:23:25.146965   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5802 12:23:25.153953   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5803 12:23:25.156429   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5804 12:23:25.159903   0 15 24 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)

 5805 12:23:25.166599   0 15 28 | B1->B0 | 3a3a 3231 | 0 1 | (1 1) (1 1)

 5806 12:23:25.169511   1  0  0 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)

 5807 12:23:25.172763   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5808 12:23:25.179669   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5809 12:23:25.182870   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5810 12:23:25.186291   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5811 12:23:25.192593   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5812 12:23:25.196435   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5813 12:23:25.199310   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 5814 12:23:25.206143   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5815 12:23:25.209062   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5816 12:23:25.212275   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5817 12:23:25.218780   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5818 12:23:25.221989   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5819 12:23:25.225409   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5820 12:23:25.231939   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5821 12:23:25.235087   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5822 12:23:25.238541   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5823 12:23:25.245717   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5824 12:23:25.248810   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5825 12:23:25.251984   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5826 12:23:25.258466   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5827 12:23:25.262070   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5828 12:23:25.265416   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5829 12:23:25.271694   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5830 12:23:25.274618  Total UI for P1: 0, mck2ui 16

 5831 12:23:25.278260  best dqsien dly found for B0: ( 1,  2, 26)

 5832 12:23:25.281945  Total UI for P1: 0, mck2ui 16

 5833 12:23:25.284902  best dqsien dly found for B1: ( 1,  2, 26)

 5834 12:23:25.287951  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5835 12:23:25.291545  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5836 12:23:25.292012  

 5837 12:23:25.294362  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5838 12:23:25.298088  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5839 12:23:25.301127  [Gating] SW calibration Done

 5840 12:23:25.301567  ==

 5841 12:23:25.304577  Dram Type= 6, Freq= 0, CH_1, rank 1

 5842 12:23:25.307703  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5843 12:23:25.308181  ==

 5844 12:23:25.311385  RX Vref Scan: 0

 5845 12:23:25.311897  

 5846 12:23:25.313960  RX Vref 0 -> 0, step: 1

 5847 12:23:25.314370  

 5848 12:23:25.314747  RX Delay -80 -> 252, step: 8

 5849 12:23:25.321046  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5850 12:23:25.323996  iDelay=208, Bit 1, Center 91 (0 ~ 183) 184

 5851 12:23:25.327432  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5852 12:23:25.330661  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5853 12:23:25.333968  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5854 12:23:25.337487  iDelay=208, Bit 5, Center 107 (16 ~ 199) 184

 5855 12:23:25.344086  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5856 12:23:25.347491  iDelay=208, Bit 7, Center 95 (0 ~ 191) 192

 5857 12:23:25.350506  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5858 12:23:25.353895  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5859 12:23:25.357244  iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200

 5860 12:23:25.363995  iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200

 5861 12:23:25.367261  iDelay=208, Bit 12, Center 103 (8 ~ 199) 192

 5862 12:23:25.370484  iDelay=208, Bit 13, Center 99 (0 ~ 199) 200

 5863 12:23:25.374303  iDelay=208, Bit 14, Center 99 (0 ~ 199) 200

 5864 12:23:25.377140  iDelay=208, Bit 15, Center 99 (0 ~ 199) 200

 5865 12:23:25.377570  ==

 5866 12:23:25.380665  Dram Type= 6, Freq= 0, CH_1, rank 1

 5867 12:23:25.387162  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5868 12:23:25.387768  ==

 5869 12:23:25.388224  DQS Delay:

 5870 12:23:25.390414  DQS0 = 0, DQS1 = 0

 5871 12:23:25.390837  DQM Delay:

 5872 12:23:25.391293  DQM0 = 99, DQM1 = 91

 5873 12:23:25.393412  DQ Delay:

 5874 12:23:25.396899  DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =99

 5875 12:23:25.400201  DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95

 5876 12:23:25.403143  DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83

 5877 12:23:25.406560  DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99

 5878 12:23:25.406994  

 5879 12:23:25.407425  

 5880 12:23:25.407942  ==

 5881 12:23:25.410076  Dram Type= 6, Freq= 0, CH_1, rank 1

 5882 12:23:25.413678  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5883 12:23:25.414107  ==

 5884 12:23:25.414573  

 5885 12:23:25.414983  

 5886 12:23:25.416755  	TX Vref Scan disable

 5887 12:23:25.419784   == TX Byte 0 ==

 5888 12:23:25.423404  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5889 12:23:25.426489  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5890 12:23:25.429940   == TX Byte 1 ==

 5891 12:23:25.433031  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5892 12:23:25.436285  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5893 12:23:25.436735  ==

 5894 12:23:25.439410  Dram Type= 6, Freq= 0, CH_1, rank 1

 5895 12:23:25.446353  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5896 12:23:25.446778  ==

 5897 12:23:25.447220  

 5898 12:23:25.447719  

 5899 12:23:25.448198  	TX Vref Scan disable

 5900 12:23:25.450624   == TX Byte 0 ==

 5901 12:23:25.453813  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5902 12:23:25.460277  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5903 12:23:25.460774   == TX Byte 1 ==

 5904 12:23:25.463617  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5905 12:23:25.470236  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5906 12:23:25.470688  

 5907 12:23:25.471157  [DATLAT]

 5908 12:23:25.471606  Freq=933, CH1 RK1

 5909 12:23:25.472056  

 5910 12:23:25.473752  DATLAT Default: 0xb

 5911 12:23:25.477122  0, 0xFFFF, sum = 0

 5912 12:23:25.477536  1, 0xFFFF, sum = 0

 5913 12:23:25.480096  2, 0xFFFF, sum = 0

 5914 12:23:25.480517  3, 0xFFFF, sum = 0

 5915 12:23:25.483487  4, 0xFFFF, sum = 0

 5916 12:23:25.484014  5, 0xFFFF, sum = 0

 5917 12:23:25.486439  6, 0xFFFF, sum = 0

 5918 12:23:25.486852  7, 0xFFFF, sum = 0

 5919 12:23:25.489779  8, 0xFFFF, sum = 0

 5920 12:23:25.490191  9, 0xFFFF, sum = 0

 5921 12:23:25.493145  10, 0x0, sum = 1

 5922 12:23:25.493559  11, 0x0, sum = 2

 5923 12:23:25.496554  12, 0x0, sum = 3

 5924 12:23:25.496968  13, 0x0, sum = 4

 5925 12:23:25.500066  best_step = 11

 5926 12:23:25.500472  

 5927 12:23:25.500827  ==

 5928 12:23:25.503274  Dram Type= 6, Freq= 0, CH_1, rank 1

 5929 12:23:25.506233  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5930 12:23:25.506672  ==

 5931 12:23:25.507034  RX Vref Scan: 0

 5932 12:23:25.507355  

 5933 12:23:25.509412  RX Vref 0 -> 0, step: 1

 5934 12:23:25.509818  

 5935 12:23:25.513180  RX Delay -61 -> 252, step: 4

 5936 12:23:25.519455  iDelay=207, Bit 0, Center 104 (15 ~ 194) 180

 5937 12:23:25.522708  iDelay=207, Bit 1, Center 94 (7 ~ 182) 176

 5938 12:23:25.526351  iDelay=207, Bit 2, Center 90 (3 ~ 178) 176

 5939 12:23:25.529566  iDelay=207, Bit 3, Center 98 (15 ~ 182) 168

 5940 12:23:25.532821  iDelay=207, Bit 4, Center 100 (11 ~ 190) 180

 5941 12:23:25.539434  iDelay=207, Bit 5, Center 110 (23 ~ 198) 176

 5942 12:23:25.542692  iDelay=207, Bit 6, Center 116 (27 ~ 206) 180

 5943 12:23:25.546086  iDelay=207, Bit 7, Center 96 (7 ~ 186) 180

 5944 12:23:25.549114  iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184

 5945 12:23:25.552429  iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180

 5946 12:23:25.555632  iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188

 5947 12:23:25.562475  iDelay=207, Bit 11, Center 86 (-5 ~ 178) 184

 5948 12:23:25.566414  iDelay=207, Bit 12, Center 104 (15 ~ 194) 180

 5949 12:23:25.569040  iDelay=207, Bit 13, Center 100 (7 ~ 194) 188

 5950 12:23:25.572588  iDelay=207, Bit 14, Center 104 (15 ~ 194) 180

 5951 12:23:25.576005  iDelay=207, Bit 15, Center 102 (11 ~ 194) 184

 5952 12:23:25.578807  ==

 5953 12:23:25.582617  Dram Type= 6, Freq= 0, CH_1, rank 1

 5954 12:23:25.585637  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5955 12:23:25.586112  ==

 5956 12:23:25.586590  DQS Delay:

 5957 12:23:25.588934  DQS0 = 0, DQS1 = 0

 5958 12:23:25.589399  DQM Delay:

 5959 12:23:25.592299  DQM0 = 101, DQM1 = 94

 5960 12:23:25.592769  DQ Delay:

 5961 12:23:25.595549  DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98

 5962 12:23:25.599099  DQ4 =100, DQ5 =110, DQ6 =116, DQ7 =96

 5963 12:23:25.602149  DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =86

 5964 12:23:25.605428  DQ12 =104, DQ13 =100, DQ14 =104, DQ15 =102

 5965 12:23:25.605854  

 5966 12:23:25.606289  

 5967 12:23:25.615127  [DQSOSCAuto] RK1, (LSB)MR18= 0x600, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps

 5968 12:23:25.615642  CH1 RK1: MR19=505, MR18=600

 5969 12:23:25.621751  CH1_RK1: MR19=0x505, MR18=0x600, DQSOSC=420, MR23=63, INC=61, DEC=40

 5970 12:23:25.625650  [RxdqsGatingPostProcess] freq 933

 5971 12:23:25.631574  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5972 12:23:25.634900  best DQS0 dly(2T, 0.5T) = (0, 10)

 5973 12:23:25.638068  best DQS1 dly(2T, 0.5T) = (0, 10)

 5974 12:23:25.641770  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5975 12:23:25.645088  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5976 12:23:25.648398  best DQS0 dly(2T, 0.5T) = (0, 10)

 5977 12:23:25.648990  best DQS1 dly(2T, 0.5T) = (0, 10)

 5978 12:23:25.651574  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5979 12:23:25.654937  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5980 12:23:25.658077  Pre-setting of DQS Precalculation

 5981 12:23:25.664883  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5982 12:23:25.671500  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5983 12:23:25.677976  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5984 12:23:25.678447  

 5985 12:23:25.678777  

 5986 12:23:25.681159  [Calibration Summary] 1866 Mbps

 5987 12:23:25.684571  CH 0, Rank 0

 5988 12:23:25.685239  SW Impedance     : PASS

 5989 12:23:25.688245  DUTY Scan        : NO K

 5990 12:23:25.688653  ZQ Calibration   : PASS

 5991 12:23:25.690989  Jitter Meter     : NO K

 5992 12:23:25.694575  CBT Training     : PASS

 5993 12:23:25.694988  Write leveling   : PASS

 5994 12:23:25.697612  RX DQS gating    : PASS

 5995 12:23:25.700918  RX DQ/DQS(RDDQC) : PASS

 5996 12:23:25.701326  TX DQ/DQS        : PASS

 5997 12:23:25.704831  RX DATLAT        : PASS

 5998 12:23:25.707447  RX DQ/DQS(Engine): PASS

 5999 12:23:25.707884  TX OE            : NO K

 6000 12:23:25.711587  All Pass.

 6001 12:23:25.712173  

 6002 12:23:25.712507  CH 0, Rank 1

 6003 12:23:25.714419  SW Impedance     : PASS

 6004 12:23:25.714831  DUTY Scan        : NO K

 6005 12:23:25.717482  ZQ Calibration   : PASS

 6006 12:23:25.720984  Jitter Meter     : NO K

 6007 12:23:25.721396  CBT Training     : PASS

 6008 12:23:25.724513  Write leveling   : PASS

 6009 12:23:25.727710  RX DQS gating    : PASS

 6010 12:23:25.728153  RX DQ/DQS(RDDQC) : PASS

 6011 12:23:25.731003  TX DQ/DQS        : PASS

 6012 12:23:25.733944  RX DATLAT        : PASS

 6013 12:23:25.734436  RX DQ/DQS(Engine): PASS

 6014 12:23:25.737283  TX OE            : NO K

 6015 12:23:25.737701  All Pass.

 6016 12:23:25.738028  

 6017 12:23:25.740775  CH 1, Rank 0

 6018 12:23:25.741203  SW Impedance     : PASS

 6019 12:23:25.744091  DUTY Scan        : NO K

 6020 12:23:25.747194  ZQ Calibration   : PASS

 6021 12:23:25.747705  Jitter Meter     : NO K

 6022 12:23:25.750821  CBT Training     : PASS

 6023 12:23:25.754158  Write leveling   : PASS

 6024 12:23:25.754569  RX DQS gating    : PASS

 6025 12:23:25.757481  RX DQ/DQS(RDDQC) : PASS

 6026 12:23:25.760982  TX DQ/DQS        : PASS

 6027 12:23:25.761495  RX DATLAT        : PASS

 6028 12:23:25.763835  RX DQ/DQS(Engine): PASS

 6029 12:23:25.764500  TX OE            : NO K

 6030 12:23:25.767073  All Pass.

 6031 12:23:25.767577  

 6032 12:23:25.767965  CH 1, Rank 1

 6033 12:23:25.770374  SW Impedance     : PASS

 6034 12:23:25.770780  DUTY Scan        : NO K

 6035 12:23:25.773902  ZQ Calibration   : PASS

 6036 12:23:25.776797  Jitter Meter     : NO K

 6037 12:23:25.777374  CBT Training     : PASS

 6038 12:23:25.780044  Write leveling   : PASS

 6039 12:23:25.783339  RX DQS gating    : PASS

 6040 12:23:25.783793  RX DQ/DQS(RDDQC) : PASS

 6041 12:23:25.786694  TX DQ/DQS        : PASS

 6042 12:23:25.790210  RX DATLAT        : PASS

 6043 12:23:25.790636  RX DQ/DQS(Engine): PASS

 6044 12:23:25.793134  TX OE            : NO K

 6045 12:23:25.793641  All Pass.

 6046 12:23:25.794153  

 6047 12:23:25.796373  DramC Write-DBI off

 6048 12:23:25.800197  	PER_BANK_REFRESH: Hybrid Mode

 6049 12:23:25.800607  TX_TRACKING: ON

 6050 12:23:25.809739  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6051 12:23:25.813225  [FAST_K] Save calibration result to emmc

 6052 12:23:25.816768  dramc_set_vcore_voltage set vcore to 650000

 6053 12:23:25.820046  Read voltage for 400, 6

 6054 12:23:25.820455  Vio18 = 0

 6055 12:23:25.820819  Vcore = 650000

 6056 12:23:25.823239  Vdram = 0

 6057 12:23:25.823667  Vddq = 0

 6058 12:23:25.824148  Vmddr = 0

 6059 12:23:25.829581  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6060 12:23:25.833222  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6061 12:23:25.836273  MEM_TYPE=3, freq_sel=20

 6062 12:23:25.839805  sv_algorithm_assistance_LP4_800 

 6063 12:23:25.843002  ============ PULL DRAM RESETB DOWN ============

 6064 12:23:25.849668  ========== PULL DRAM RESETB DOWN end =========

 6065 12:23:25.853074  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6066 12:23:25.856152  =================================== 

 6067 12:23:25.859594  LPDDR4 DRAM CONFIGURATION

 6068 12:23:25.863181  =================================== 

 6069 12:23:25.863693  EX_ROW_EN[0]    = 0x0

 6070 12:23:25.866342  EX_ROW_EN[1]    = 0x0

 6071 12:23:25.866749  LP4Y_EN      = 0x0

 6072 12:23:25.869711  WORK_FSP     = 0x0

 6073 12:23:25.870122  WL           = 0x2

 6074 12:23:25.872675  RL           = 0x2

 6075 12:23:25.873099  BL           = 0x2

 6076 12:23:25.875859  RPST         = 0x0

 6077 12:23:25.876273  RD_PRE       = 0x0

 6078 12:23:25.879283  WR_PRE       = 0x1

 6079 12:23:25.882585  WR_PST       = 0x0

 6080 12:23:25.883006  DBI_WR       = 0x0

 6081 12:23:25.886073  DBI_RD       = 0x0

 6082 12:23:25.886598  OTF          = 0x1

 6083 12:23:25.889308  =================================== 

 6084 12:23:25.892856  =================================== 

 6085 12:23:25.893281  ANA top config

 6086 12:23:25.896381  =================================== 

 6087 12:23:25.899071  DLL_ASYNC_EN            =  0

 6088 12:23:25.902729  ALL_SLAVE_EN            =  1

 6089 12:23:25.906422  NEW_RANK_MODE           =  1

 6090 12:23:25.908901  DLL_IDLE_MODE           =  1

 6091 12:23:25.909326  LP45_APHY_COMB_EN       =  1

 6092 12:23:25.912565  TX_ODT_DIS              =  1

 6093 12:23:25.915830  NEW_8X_MODE             =  1

 6094 12:23:25.918822  =================================== 

 6095 12:23:25.922348  =================================== 

 6096 12:23:25.925799  data_rate                  =  800

 6097 12:23:25.928939  CKR                        = 1

 6098 12:23:25.932451  DQ_P2S_RATIO               = 4

 6099 12:23:25.935511  =================================== 

 6100 12:23:25.936028  CA_P2S_RATIO               = 4

 6101 12:23:25.939082  DQ_CA_OPEN                 = 0

 6102 12:23:25.941897  DQ_SEMI_OPEN               = 1

 6103 12:23:25.945839  CA_SEMI_OPEN               = 1

 6104 12:23:25.949172  CA_FULL_RATE               = 0

 6105 12:23:25.952316  DQ_CKDIV4_EN               = 0

 6106 12:23:25.952730  CA_CKDIV4_EN               = 1

 6107 12:23:25.955279  CA_PREDIV_EN               = 0

 6108 12:23:25.958678  PH8_DLY                    = 0

 6109 12:23:25.961591  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6110 12:23:25.965388  DQ_AAMCK_DIV               = 0

 6111 12:23:25.968459  CA_AAMCK_DIV               = 0

 6112 12:23:25.968887  CA_ADMCK_DIV               = 4

 6113 12:23:25.972207  DQ_TRACK_CA_EN             = 0

 6114 12:23:25.975257  CA_PICK                    = 800

 6115 12:23:25.978096  CA_MCKIO                   = 400

 6116 12:23:25.981769  MCKIO_SEMI                 = 400

 6117 12:23:25.985096  PLL_FREQ                   = 3016

 6118 12:23:25.987837  DQ_UI_PI_RATIO             = 32

 6119 12:23:25.991413  CA_UI_PI_RATIO             = 32

 6120 12:23:25.994683  =================================== 

 6121 12:23:25.998016  =================================== 

 6122 12:23:25.998430  memory_type:LPDDR4         

 6123 12:23:26.001237  GP_NUM     : 10       

 6124 12:23:26.004792  SRAM_EN    : 1       

 6125 12:23:26.005295  MD32_EN    : 0       

 6126 12:23:26.008277  =================================== 

 6127 12:23:26.011522  [ANA_INIT] >>>>>>>>>>>>>> 

 6128 12:23:26.014404  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6129 12:23:26.018102  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6130 12:23:26.021609  =================================== 

 6131 12:23:26.024255  data_rate = 800,PCW = 0X7400

 6132 12:23:26.027843  =================================== 

 6133 12:23:26.031188  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6134 12:23:26.034528  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6135 12:23:26.047448  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6136 12:23:26.051031  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6137 12:23:26.054503  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6138 12:23:26.057683  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6139 12:23:26.060690  [ANA_INIT] flow start 

 6140 12:23:26.064145  [ANA_INIT] PLL >>>>>>>> 

 6141 12:23:26.064635  [ANA_INIT] PLL <<<<<<<< 

 6142 12:23:26.067850  [ANA_INIT] MIDPI >>>>>>>> 

 6143 12:23:26.070711  [ANA_INIT] MIDPI <<<<<<<< 

 6144 12:23:26.071171  [ANA_INIT] DLL >>>>>>>> 

 6145 12:23:26.074150  [ANA_INIT] flow end 

 6146 12:23:26.077061  ============ LP4 DIFF to SE enter ============

 6147 12:23:26.080519  ============ LP4 DIFF to SE exit  ============

 6148 12:23:26.083756  [ANA_INIT] <<<<<<<<<<<<< 

 6149 12:23:26.086966  [Flow] Enable top DCM control >>>>> 

 6150 12:23:26.090410  [Flow] Enable top DCM control <<<<< 

 6151 12:23:26.093645  Enable DLL master slave shuffle 

 6152 12:23:26.100032  ============================================================== 

 6153 12:23:26.100490  Gating Mode config

 6154 12:23:26.106546  ============================================================== 

 6155 12:23:26.107105  Config description: 

 6156 12:23:26.116835  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6157 12:23:26.123444  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6158 12:23:26.129996  SELPH_MODE            0: By rank         1: By Phase 

 6159 12:23:26.136392  ============================================================== 

 6160 12:23:26.136830  GAT_TRACK_EN                 =  0

 6161 12:23:26.139780  RX_GATING_MODE               =  2

 6162 12:23:26.142750  RX_GATING_TRACK_MODE         =  2

 6163 12:23:26.146309  SELPH_MODE                   =  1

 6164 12:23:26.149948  PICG_EARLY_EN                =  1

 6165 12:23:26.152859  VALID_LAT_VALUE              =  1

 6166 12:23:26.159342  ============================================================== 

 6167 12:23:26.163167  Enter into Gating configuration >>>> 

 6168 12:23:26.166395  Exit from Gating configuration <<<< 

 6169 12:23:26.169428  Enter into  DVFS_PRE_config >>>>> 

 6170 12:23:26.179245  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6171 12:23:26.182666  Exit from  DVFS_PRE_config <<<<< 

 6172 12:23:26.186329  Enter into PICG configuration >>>> 

 6173 12:23:26.189375  Exit from PICG configuration <<<< 

 6174 12:23:26.192664  [RX_INPUT] configuration >>>>> 

 6175 12:23:26.196218  [RX_INPUT] configuration <<<<< 

 6176 12:23:26.199243  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6177 12:23:26.205750  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6178 12:23:26.212415  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6179 12:23:26.218987  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6180 12:23:26.222153  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6181 12:23:26.228860  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6182 12:23:26.231832  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6183 12:23:26.238704  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6184 12:23:26.242004  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6185 12:23:26.245541  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6186 12:23:26.248703  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6187 12:23:26.255034  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6188 12:23:26.258069  =================================== 

 6189 12:23:26.261773  LPDDR4 DRAM CONFIGURATION

 6190 12:23:26.264814  =================================== 

 6191 12:23:26.265267  EX_ROW_EN[0]    = 0x0

 6192 12:23:26.268568  EX_ROW_EN[1]    = 0x0

 6193 12:23:26.269118  LP4Y_EN      = 0x0

 6194 12:23:26.271569  WORK_FSP     = 0x0

 6195 12:23:26.272053  WL           = 0x2

 6196 12:23:26.274708  RL           = 0x2

 6197 12:23:26.275170  BL           = 0x2

 6198 12:23:26.278320  RPST         = 0x0

 6199 12:23:26.278738  RD_PRE       = 0x0

 6200 12:23:26.281329  WR_PRE       = 0x1

 6201 12:23:26.281784  WR_PST       = 0x0

 6202 12:23:26.284943  DBI_WR       = 0x0

 6203 12:23:26.288182  DBI_RD       = 0x0

 6204 12:23:26.288685  OTF          = 0x1

 6205 12:23:26.291234  =================================== 

 6206 12:23:26.294442  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6207 12:23:26.297840  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6208 12:23:26.304619  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6209 12:23:26.307852  =================================== 

 6210 12:23:26.310959  LPDDR4 DRAM CONFIGURATION

 6211 12:23:26.314538  =================================== 

 6212 12:23:26.314952  EX_ROW_EN[0]    = 0x10

 6213 12:23:26.317712  EX_ROW_EN[1]    = 0x0

 6214 12:23:26.318123  LP4Y_EN      = 0x0

 6215 12:23:26.321383  WORK_FSP     = 0x0

 6216 12:23:26.321792  WL           = 0x2

 6217 12:23:26.324235  RL           = 0x2

 6218 12:23:26.324642  BL           = 0x2

 6219 12:23:26.327899  RPST         = 0x0

 6220 12:23:26.328429  RD_PRE       = 0x0

 6221 12:23:26.330851  WR_PRE       = 0x1

 6222 12:23:26.333968  WR_PST       = 0x0

 6223 12:23:26.334382  DBI_WR       = 0x0

 6224 12:23:26.337777  DBI_RD       = 0x0

 6225 12:23:26.338300  OTF          = 0x1

 6226 12:23:26.341332  =================================== 

 6227 12:23:26.347503  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6228 12:23:26.351055  nWR fixed to 30

 6229 12:23:26.354730  [ModeRegInit_LP4] CH0 RK0

 6230 12:23:26.355273  [ModeRegInit_LP4] CH0 RK1

 6231 12:23:26.357628  [ModeRegInit_LP4] CH1 RK0

 6232 12:23:26.361668  [ModeRegInit_LP4] CH1 RK1

 6233 12:23:26.362180  match AC timing 19

 6234 12:23:26.367380  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6235 12:23:26.370950  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6236 12:23:26.374201  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6237 12:23:26.380714  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6238 12:23:26.384416  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6239 12:23:26.384943  ==

 6240 12:23:26.387489  Dram Type= 6, Freq= 0, CH_0, rank 0

 6241 12:23:26.391092  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6242 12:23:26.391608  ==

 6243 12:23:26.397341  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6244 12:23:26.403841  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6245 12:23:26.407582  [CA 0] Center 36 (8~64) winsize 57

 6246 12:23:26.410418  [CA 1] Center 36 (8~64) winsize 57

 6247 12:23:26.413946  [CA 2] Center 36 (8~64) winsize 57

 6248 12:23:26.417157  [CA 3] Center 36 (8~64) winsize 57

 6249 12:23:26.420522  [CA 4] Center 36 (8~64) winsize 57

 6250 12:23:26.420980  [CA 5] Center 36 (8~64) winsize 57

 6251 12:23:26.421339  

 6252 12:23:26.427762  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6253 12:23:26.428356  

 6254 12:23:26.430656  [CATrainingPosCal] consider 1 rank data

 6255 12:23:26.433967  u2DelayCellTimex100 = 270/100 ps

 6256 12:23:26.437087  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6257 12:23:26.440438  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6258 12:23:26.443581  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6259 12:23:26.446609  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6260 12:23:26.450411  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6261 12:23:26.453728  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6262 12:23:26.454285  

 6263 12:23:26.456548  CA PerBit enable=1, Macro0, CA PI delay=36

 6264 12:23:26.457002  

 6265 12:23:26.460374  [CBTSetCACLKResult] CA Dly = 36

 6266 12:23:26.463361  CS Dly: 1 (0~32)

 6267 12:23:26.464008  ==

 6268 12:23:26.466688  Dram Type= 6, Freq= 0, CH_0, rank 1

 6269 12:23:26.470177  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6270 12:23:26.470594  ==

 6271 12:23:26.476623  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6272 12:23:26.483480  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6273 12:23:26.486744  [CA 0] Center 36 (8~64) winsize 57

 6274 12:23:26.490340  [CA 1] Center 36 (8~64) winsize 57

 6275 12:23:26.490920  [CA 2] Center 36 (8~64) winsize 57

 6276 12:23:26.493388  [CA 3] Center 36 (8~64) winsize 57

 6277 12:23:26.496573  [CA 4] Center 36 (8~64) winsize 57

 6278 12:23:26.499911  [CA 5] Center 36 (8~64) winsize 57

 6279 12:23:26.500514  

 6280 12:23:26.503124  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6281 12:23:26.506650  

 6282 12:23:26.509566  [CATrainingPosCal] consider 2 rank data

 6283 12:23:26.512523  u2DelayCellTimex100 = 270/100 ps

 6284 12:23:26.516482  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6285 12:23:26.519495  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6286 12:23:26.522938  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6287 12:23:26.525978  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6288 12:23:26.529402  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6289 12:23:26.532742  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6290 12:23:26.533297  

 6291 12:23:26.536009  CA PerBit enable=1, Macro0, CA PI delay=36

 6292 12:23:26.536620  

 6293 12:23:26.538954  [CBTSetCACLKResult] CA Dly = 36

 6294 12:23:26.542339  CS Dly: 1 (0~32)

 6295 12:23:26.542791  

 6296 12:23:26.545950  ----->DramcWriteLeveling(PI) begin...

 6297 12:23:26.546453  ==

 6298 12:23:26.549474  Dram Type= 6, Freq= 0, CH_0, rank 0

 6299 12:23:26.552159  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6300 12:23:26.552640  ==

 6301 12:23:26.555840  Write leveling (Byte 0): 40 => 8

 6302 12:23:26.559425  Write leveling (Byte 1): 32 => 0

 6303 12:23:26.562765  DramcWriteLeveling(PI) end<-----

 6304 12:23:26.563348  

 6305 12:23:26.563806  ==

 6306 12:23:26.565504  Dram Type= 6, Freq= 0, CH_0, rank 0

 6307 12:23:26.568815  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6308 12:23:26.569221  ==

 6309 12:23:26.572073  [Gating] SW mode calibration

 6310 12:23:26.578665  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6311 12:23:26.585314  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6312 12:23:26.588606   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6313 12:23:26.595081   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6314 12:23:26.598495   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6315 12:23:26.602266   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6316 12:23:26.608083   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6317 12:23:26.611712   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6318 12:23:26.615097   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6319 12:23:26.621284   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6320 12:23:26.625033   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6321 12:23:26.628654  Total UI for P1: 0, mck2ui 16

 6322 12:23:26.631092  best dqsien dly found for B0: ( 0, 14, 24)

 6323 12:23:26.634710  Total UI for P1: 0, mck2ui 16

 6324 12:23:26.637753  best dqsien dly found for B1: ( 0, 14, 24)

 6325 12:23:26.641442  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6326 12:23:26.644876  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6327 12:23:26.645496  

 6328 12:23:26.647929  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6329 12:23:26.651815  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6330 12:23:26.654640  [Gating] SW calibration Done

 6331 12:23:26.655193  ==

 6332 12:23:26.657511  Dram Type= 6, Freq= 0, CH_0, rank 0

 6333 12:23:26.664685  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6334 12:23:26.665252  ==

 6335 12:23:26.665611  RX Vref Scan: 0

 6336 12:23:26.665940  

 6337 12:23:26.667359  RX Vref 0 -> 0, step: 1

 6338 12:23:26.667868  

 6339 12:23:26.670893  RX Delay -410 -> 252, step: 16

 6340 12:23:26.673999  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6341 12:23:26.677442  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6342 12:23:26.683980  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6343 12:23:26.687140  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6344 12:23:26.690476  iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512

 6345 12:23:26.693800  iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512

 6346 12:23:26.700202  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6347 12:23:26.703487  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6348 12:23:26.706532  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6349 12:23:26.710138  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6350 12:23:26.716463  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6351 12:23:26.719867  iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512

 6352 12:23:26.723182  iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512

 6353 12:23:26.729574  iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512

 6354 12:23:26.732882  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6355 12:23:26.736115  iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512

 6356 12:23:26.736527  ==

 6357 12:23:26.739609  Dram Type= 6, Freq= 0, CH_0, rank 0

 6358 12:23:26.742723  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6359 12:23:26.746426  ==

 6360 12:23:26.746841  DQS Delay:

 6361 12:23:26.747165  DQS0 = 43, DQS1 = 59

 6362 12:23:26.749649  DQM Delay:

 6363 12:23:26.750061  DQM0 = 11, DQM1 = 11

 6364 12:23:26.752768  DQ Delay:

 6365 12:23:26.753181  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6366 12:23:26.756337  DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24

 6367 12:23:26.759394  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6368 12:23:26.762637  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6369 12:23:26.763050  

 6370 12:23:26.763374  

 6371 12:23:26.765946  ==

 6372 12:23:26.766360  Dram Type= 6, Freq= 0, CH_0, rank 0

 6373 12:23:26.772559  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6374 12:23:26.773053  ==

 6375 12:23:26.773386  

 6376 12:23:26.773800  

 6377 12:23:26.776017  	TX Vref Scan disable

 6378 12:23:26.776466   == TX Byte 0 ==

 6379 12:23:26.779238  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6380 12:23:26.785811  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6381 12:23:26.786303   == TX Byte 1 ==

 6382 12:23:26.788660  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6383 12:23:26.795401  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6384 12:23:26.795993  ==

 6385 12:23:26.799018  Dram Type= 6, Freq= 0, CH_0, rank 0

 6386 12:23:26.802000  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6387 12:23:26.802639  ==

 6388 12:23:26.803156  

 6389 12:23:26.803537  

 6390 12:23:26.806212  	TX Vref Scan disable

 6391 12:23:26.806672   == TX Byte 0 ==

 6392 12:23:26.809244  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6393 12:23:26.815318  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6394 12:23:26.815773   == TX Byte 1 ==

 6395 12:23:26.818597  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6396 12:23:26.825240  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6397 12:23:26.825655  

 6398 12:23:26.825980  [DATLAT]

 6399 12:23:26.828323  Freq=400, CH0 RK0

 6400 12:23:26.828735  

 6401 12:23:26.829059  DATLAT Default: 0xf

 6402 12:23:26.831706  0, 0xFFFF, sum = 0

 6403 12:23:26.832337  1, 0xFFFF, sum = 0

 6404 12:23:26.835509  2, 0xFFFF, sum = 0

 6405 12:23:26.835979  3, 0xFFFF, sum = 0

 6406 12:23:26.838871  4, 0xFFFF, sum = 0

 6407 12:23:26.839401  5, 0xFFFF, sum = 0

 6408 12:23:26.842265  6, 0xFFFF, sum = 0

 6409 12:23:26.842790  7, 0xFFFF, sum = 0

 6410 12:23:26.845355  8, 0xFFFF, sum = 0

 6411 12:23:26.845878  9, 0xFFFF, sum = 0

 6412 12:23:26.848301  10, 0xFFFF, sum = 0

 6413 12:23:26.848727  11, 0xFFFF, sum = 0

 6414 12:23:26.851546  12, 0xFFFF, sum = 0

 6415 12:23:26.852026  13, 0x0, sum = 1

 6416 12:23:26.855166  14, 0x0, sum = 2

 6417 12:23:26.855689  15, 0x0, sum = 3

 6418 12:23:26.858050  16, 0x0, sum = 4

 6419 12:23:26.858469  best_step = 14

 6420 12:23:26.858795  

 6421 12:23:26.859098  ==

 6422 12:23:26.861765  Dram Type= 6, Freq= 0, CH_0, rank 0

 6423 12:23:26.868570  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6424 12:23:26.869095  ==

 6425 12:23:26.869425  RX Vref Scan: 1

 6426 12:23:26.869730  

 6427 12:23:26.871816  RX Vref 0 -> 0, step: 1

 6428 12:23:26.872245  

 6429 12:23:26.875152  RX Delay -359 -> 252, step: 8

 6430 12:23:26.875564  

 6431 12:23:26.878577  Set Vref, RX VrefLevel [Byte0]: 60

 6432 12:23:26.881269                           [Byte1]: 56

 6433 12:23:26.885121  

 6434 12:23:26.888360  Final RX Vref Byte 0 = 60 to rank0

 6435 12:23:26.888882  Final RX Vref Byte 1 = 56 to rank0

 6436 12:23:26.891282  Final RX Vref Byte 0 = 60 to rank1

 6437 12:23:26.894547  Final RX Vref Byte 1 = 56 to rank1==

 6438 12:23:26.898096  Dram Type= 6, Freq= 0, CH_0, rank 0

 6439 12:23:26.904604  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6440 12:23:26.905019  ==

 6441 12:23:26.905348  DQS Delay:

 6442 12:23:26.907621  DQS0 = 48, DQS1 = 56

 6443 12:23:26.908081  DQM Delay:

 6444 12:23:26.908412  DQM0 = 11, DQM1 = 8

 6445 12:23:26.911552  DQ Delay:

 6446 12:23:26.914504  DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8

 6447 12:23:26.918292  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20

 6448 12:23:26.918823  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0

 6449 12:23:26.924115  DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16

 6450 12:23:26.924527  

 6451 12:23:26.924849  

 6452 12:23:26.931336  [DQSOSCAuto] RK0, (LSB)MR18= 0xb97c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps

 6453 12:23:26.934512  CH0 RK0: MR19=C0C, MR18=B97C

 6454 12:23:26.941106  CH0_RK0: MR19=0xC0C, MR18=0xB97C, DQSOSC=386, MR23=63, INC=396, DEC=264

 6455 12:23:26.941662  ==

 6456 12:23:26.944401  Dram Type= 6, Freq= 0, CH_0, rank 1

 6457 12:23:26.947416  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6458 12:23:26.947937  ==

 6459 12:23:26.950935  [Gating] SW mode calibration

 6460 12:23:26.957791  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6461 12:23:26.963770  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6462 12:23:26.967161   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6463 12:23:26.970861   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6464 12:23:26.977611   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6465 12:23:26.980659   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6466 12:23:26.983895   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6467 12:23:26.990454   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6468 12:23:26.993696   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6469 12:23:26.997186   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6470 12:23:27.003879   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6471 12:23:27.004494  Total UI for P1: 0, mck2ui 16

 6472 12:23:27.010127  best dqsien dly found for B0: ( 0, 14, 24)

 6473 12:23:27.010590  Total UI for P1: 0, mck2ui 16

 6474 12:23:27.016954  best dqsien dly found for B1: ( 0, 14, 24)

 6475 12:23:27.020440  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6476 12:23:27.023394  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6477 12:23:27.024012  

 6478 12:23:27.026977  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6479 12:23:27.030548  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6480 12:23:27.033039  [Gating] SW calibration Done

 6481 12:23:27.033502  ==

 6482 12:23:27.036355  Dram Type= 6, Freq= 0, CH_0, rank 1

 6483 12:23:27.039908  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6484 12:23:27.040372  ==

 6485 12:23:27.043196  RX Vref Scan: 0

 6486 12:23:27.043653  

 6487 12:23:27.044070  RX Vref 0 -> 0, step: 1

 6488 12:23:27.046634  

 6489 12:23:27.047090  RX Delay -410 -> 252, step: 16

 6490 12:23:27.052876  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6491 12:23:27.056192  iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512

 6492 12:23:27.059298  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6493 12:23:27.066342  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6494 12:23:27.069634  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6495 12:23:27.072948  iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496

 6496 12:23:27.076337  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6497 12:23:27.082676  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6498 12:23:27.085725  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6499 12:23:27.089323  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6500 12:23:27.092750  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6501 12:23:27.099383  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6502 12:23:27.102885  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6503 12:23:27.105652  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6504 12:23:27.109471  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6505 12:23:27.115457  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6506 12:23:27.115921  ==

 6507 12:23:27.118828  Dram Type= 6, Freq= 0, CH_0, rank 1

 6508 12:23:27.122366  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6509 12:23:27.122778  ==

 6510 12:23:27.123098  DQS Delay:

 6511 12:23:27.125642  DQS0 = 35, DQS1 = 59

 6512 12:23:27.126051  DQM Delay:

 6513 12:23:27.128858  DQM0 = 4, DQM1 = 16

 6514 12:23:27.129264  DQ Delay:

 6515 12:23:27.132281  DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0

 6516 12:23:27.135590  DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =16

 6517 12:23:27.138884  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6518 12:23:27.142407  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6519 12:23:27.142814  

 6520 12:23:27.143137  

 6521 12:23:27.143487  ==

 6522 12:23:27.145775  Dram Type= 6, Freq= 0, CH_0, rank 1

 6523 12:23:27.148929  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6524 12:23:27.149339  ==

 6525 12:23:27.149714  

 6526 12:23:27.150017  

 6527 12:23:27.152196  	TX Vref Scan disable

 6528 12:23:27.152607   == TX Byte 0 ==

 6529 12:23:27.158576  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6530 12:23:27.162227  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6531 12:23:27.162637   == TX Byte 1 ==

 6532 12:23:27.168447  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6533 12:23:27.171917  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6534 12:23:27.172351  ==

 6535 12:23:27.175713  Dram Type= 6, Freq= 0, CH_0, rank 1

 6536 12:23:27.178256  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6537 12:23:27.178667  ==

 6538 12:23:27.178990  

 6539 12:23:27.181650  

 6540 12:23:27.182059  	TX Vref Scan disable

 6541 12:23:27.185075   == TX Byte 0 ==

 6542 12:23:27.188696  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6543 12:23:27.191858  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6544 12:23:27.195191   == TX Byte 1 ==

 6545 12:23:27.198296  Update DQ  dly =578 (4 ,2, 2)  DQ  OEN =(3 ,3)

 6546 12:23:27.201406  Update DQM dly =578 (4 ,2, 2)  DQM OEN =(3 ,3)

 6547 12:23:27.201921  

 6548 12:23:27.202361  [DATLAT]

 6549 12:23:27.204811  Freq=400, CH0 RK1

 6550 12:23:27.205509  

 6551 12:23:27.205995  DATLAT Default: 0xe

 6552 12:23:27.208183  0, 0xFFFF, sum = 0

 6553 12:23:27.212308  1, 0xFFFF, sum = 0

 6554 12:23:27.212815  2, 0xFFFF, sum = 0

 6555 12:23:27.214751  3, 0xFFFF, sum = 0

 6556 12:23:27.215214  4, 0xFFFF, sum = 0

 6557 12:23:27.218342  5, 0xFFFF, sum = 0

 6558 12:23:27.218810  6, 0xFFFF, sum = 0

 6559 12:23:27.221198  7, 0xFFFF, sum = 0

 6560 12:23:27.221668  8, 0xFFFF, sum = 0

 6561 12:23:27.224343  9, 0xFFFF, sum = 0

 6562 12:23:27.224796  10, 0xFFFF, sum = 0

 6563 12:23:27.228086  11, 0xFFFF, sum = 0

 6564 12:23:27.228534  12, 0xFFFF, sum = 0

 6565 12:23:27.231328  13, 0x0, sum = 1

 6566 12:23:27.231870  14, 0x0, sum = 2

 6567 12:23:27.234656  15, 0x0, sum = 3

 6568 12:23:27.235070  16, 0x0, sum = 4

 6569 12:23:27.237650  best_step = 14

 6570 12:23:27.238061  

 6571 12:23:27.238434  ==

 6572 12:23:27.241142  Dram Type= 6, Freq= 0, CH_0, rank 1

 6573 12:23:27.244394  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6574 12:23:27.244844  ==

 6575 12:23:27.247610  RX Vref Scan: 0

 6576 12:23:27.248149  

 6577 12:23:27.248562  RX Vref 0 -> 0, step: 1

 6578 12:23:27.248916  

 6579 12:23:27.250899  RX Delay -359 -> 252, step: 8

 6580 12:23:27.258696  iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480

 6581 12:23:27.262009  iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488

 6582 12:23:27.265380  iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480

 6583 12:23:27.272417  iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488

 6584 12:23:27.275202  iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488

 6585 12:23:27.279159  iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488

 6586 12:23:27.282217  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6587 12:23:27.288502  iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488

 6588 12:23:27.291861  iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496

 6589 12:23:27.294812  iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488

 6590 12:23:27.299006  iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496

 6591 12:23:27.304875  iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488

 6592 12:23:27.308266  iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496

 6593 12:23:27.311676  iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496

 6594 12:23:27.318027  iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488

 6595 12:23:27.321368  iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496

 6596 12:23:27.321785  ==

 6597 12:23:27.324331  Dram Type= 6, Freq= 0, CH_0, rank 1

 6598 12:23:27.327832  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6599 12:23:27.328246  ==

 6600 12:23:27.331137  DQS Delay:

 6601 12:23:27.331596  DQS0 = 44, DQS1 = 60

 6602 12:23:27.332005  DQM Delay:

 6603 12:23:27.334112  DQM0 = 8, DQM1 = 14

 6604 12:23:27.334521  DQ Delay:

 6605 12:23:27.337845  DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8

 6606 12:23:27.341100  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6607 12:23:27.344316  DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8

 6608 12:23:27.347842  DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20

 6609 12:23:27.348280  

 6610 12:23:27.348619  

 6611 12:23:27.357587  [DQSOSCAuto] RK1, (LSB)MR18= 0xb541, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps

 6612 12:23:27.358046  CH0 RK1: MR19=C0C, MR18=B541

 6613 12:23:27.364162  CH0_RK1: MR19=0xC0C, MR18=0xB541, DQSOSC=387, MR23=63, INC=394, DEC=262

 6614 12:23:27.367854  [RxdqsGatingPostProcess] freq 400

 6615 12:23:27.373801  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6616 12:23:27.377341  best DQS0 dly(2T, 0.5T) = (0, 10)

 6617 12:23:27.380525  best DQS1 dly(2T, 0.5T) = (0, 10)

 6618 12:23:27.383613  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6619 12:23:27.386938  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6620 12:23:27.390470  best DQS0 dly(2T, 0.5T) = (0, 10)

 6621 12:23:27.393499  best DQS1 dly(2T, 0.5T) = (0, 10)

 6622 12:23:27.396617  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6623 12:23:27.399909  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6624 12:23:27.400322  Pre-setting of DQS Precalculation

 6625 12:23:27.406589  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6626 12:23:27.407040  ==

 6627 12:23:27.409975  Dram Type= 6, Freq= 0, CH_1, rank 0

 6628 12:23:27.413504  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6629 12:23:27.414026  ==

 6630 12:23:27.419482  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6631 12:23:27.426630  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6632 12:23:27.430031  [CA 0] Center 36 (8~64) winsize 57

 6633 12:23:27.433065  [CA 1] Center 36 (8~64) winsize 57

 6634 12:23:27.436434  [CA 2] Center 36 (8~64) winsize 57

 6635 12:23:27.439323  [CA 3] Center 36 (8~64) winsize 57

 6636 12:23:27.442686  [CA 4] Center 36 (8~64) winsize 57

 6637 12:23:27.443082  [CA 5] Center 36 (8~64) winsize 57

 6638 12:23:27.446158  

 6639 12:23:27.449705  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6640 12:23:27.450021  

 6641 12:23:27.452807  [CATrainingPosCal] consider 1 rank data

 6642 12:23:27.456309  u2DelayCellTimex100 = 270/100 ps

 6643 12:23:27.459064  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6644 12:23:27.462730  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6645 12:23:27.466425  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6646 12:23:27.469436  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6647 12:23:27.472644  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6648 12:23:27.475682  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6649 12:23:27.476109  

 6650 12:23:27.478971  CA PerBit enable=1, Macro0, CA PI delay=36

 6651 12:23:27.482809  

 6652 12:23:27.483190  [CBTSetCACLKResult] CA Dly = 36

 6653 12:23:27.485489  CS Dly: 1 (0~32)

 6654 12:23:27.485864  ==

 6655 12:23:27.488851  Dram Type= 6, Freq= 0, CH_1, rank 1

 6656 12:23:27.492341  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6657 12:23:27.492639  ==

 6658 12:23:27.498694  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6659 12:23:27.505462  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6660 12:23:27.508786  [CA 0] Center 36 (8~64) winsize 57

 6661 12:23:27.512254  [CA 1] Center 36 (8~64) winsize 57

 6662 12:23:27.515770  [CA 2] Center 36 (8~64) winsize 57

 6663 12:23:27.516335  [CA 3] Center 36 (8~64) winsize 57

 6664 12:23:27.518990  [CA 4] Center 36 (8~64) winsize 57

 6665 12:23:27.521841  [CA 5] Center 36 (8~64) winsize 57

 6666 12:23:27.522331  

 6667 12:23:27.528710  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6668 12:23:27.529121  

 6669 12:23:27.531670  [CATrainingPosCal] consider 2 rank data

 6670 12:23:27.535093  u2DelayCellTimex100 = 270/100 ps

 6671 12:23:27.539011  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6672 12:23:27.541660  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6673 12:23:27.545132  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6674 12:23:27.548400  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6675 12:23:27.551864  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6676 12:23:27.554839  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6677 12:23:27.555251  

 6678 12:23:27.558772  CA PerBit enable=1, Macro0, CA PI delay=36

 6679 12:23:27.559249  

 6680 12:23:27.561818  [CBTSetCACLKResult] CA Dly = 36

 6681 12:23:27.564982  CS Dly: 1 (0~32)

 6682 12:23:27.565397  

 6683 12:23:27.568270  ----->DramcWriteLeveling(PI) begin...

 6684 12:23:27.568705  ==

 6685 12:23:27.571408  Dram Type= 6, Freq= 0, CH_1, rank 0

 6686 12:23:27.574828  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6687 12:23:27.575240  ==

 6688 12:23:27.578289  Write leveling (Byte 0): 40 => 8

 6689 12:23:27.581299  Write leveling (Byte 1): 40 => 8

 6690 12:23:27.584909  DramcWriteLeveling(PI) end<-----

 6691 12:23:27.585414  

 6692 12:23:27.585742  ==

 6693 12:23:27.588109  Dram Type= 6, Freq= 0, CH_1, rank 0

 6694 12:23:27.591654  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6695 12:23:27.592108  ==

 6696 12:23:27.594722  [Gating] SW mode calibration

 6697 12:23:27.601567  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6698 12:23:27.608437  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6699 12:23:27.611122   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6700 12:23:27.614528   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6701 12:23:27.621559   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6702 12:23:27.624399   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6703 12:23:27.627810   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6704 12:23:27.634495   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6705 12:23:27.637898   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6706 12:23:27.644108   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6707 12:23:27.647409   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6708 12:23:27.650653  Total UI for P1: 0, mck2ui 16

 6709 12:23:27.654567  best dqsien dly found for B0: ( 0, 14, 24)

 6710 12:23:27.657332  Total UI for P1: 0, mck2ui 16

 6711 12:23:27.660969  best dqsien dly found for B1: ( 0, 14, 24)

 6712 12:23:27.663705  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6713 12:23:27.667513  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6714 12:23:27.668071  

 6715 12:23:27.670761  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6716 12:23:27.673623  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6717 12:23:27.677600  [Gating] SW calibration Done

 6718 12:23:27.678105  ==

 6719 12:23:27.680419  Dram Type= 6, Freq= 0, CH_1, rank 0

 6720 12:23:27.683987  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6721 12:23:27.684595  ==

 6722 12:23:27.687086  RX Vref Scan: 0

 6723 12:23:27.687543  

 6724 12:23:27.690867  RX Vref 0 -> 0, step: 1

 6725 12:23:27.691426  

 6726 12:23:27.693788  RX Delay -410 -> 252, step: 16

 6727 12:23:27.697252  iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512

 6728 12:23:27.700471  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6729 12:23:27.703836  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6730 12:23:27.710197  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6731 12:23:27.713495  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6732 12:23:27.716835  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6733 12:23:27.720170  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6734 12:23:27.726523  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6735 12:23:27.729914  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6736 12:23:27.733013  iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512

 6737 12:23:27.736324  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6738 12:23:27.743160  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6739 12:23:27.746679  iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512

 6740 12:23:27.749816  iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512

 6741 12:23:27.755992  iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512

 6742 12:23:27.759421  iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512

 6743 12:23:27.759979  ==

 6744 12:23:27.762844  Dram Type= 6, Freq= 0, CH_1, rank 0

 6745 12:23:27.766639  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6746 12:23:27.767154  ==

 6747 12:23:27.769504  DQS Delay:

 6748 12:23:27.770010  DQS0 = 43, DQS1 = 51

 6749 12:23:27.770343  DQM Delay:

 6750 12:23:27.772964  DQM0 = 12, DQM1 = 14

 6751 12:23:27.773379  DQ Delay:

 6752 12:23:27.776003  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6753 12:23:27.779347  DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8

 6754 12:23:27.782512  DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0

 6755 12:23:27.785953  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6756 12:23:27.786631  

 6757 12:23:27.787170  

 6758 12:23:27.787681  ==

 6759 12:23:27.789047  Dram Type= 6, Freq= 0, CH_1, rank 0

 6760 12:23:27.792456  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6761 12:23:27.795834  ==

 6762 12:23:27.796245  

 6763 12:23:27.796572  

 6764 12:23:27.796874  	TX Vref Scan disable

 6765 12:23:27.798805   == TX Byte 0 ==

 6766 12:23:27.802438  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6767 12:23:27.805666  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6768 12:23:27.809189   == TX Byte 1 ==

 6769 12:23:27.812184  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6770 12:23:27.815402  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6771 12:23:27.815977  ==

 6772 12:23:27.818887  Dram Type= 6, Freq= 0, CH_1, rank 0

 6773 12:23:27.825610  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6774 12:23:27.826101  ==

 6775 12:23:27.826431  

 6776 12:23:27.826733  

 6777 12:23:27.827020  	TX Vref Scan disable

 6778 12:23:27.828571   == TX Byte 0 ==

 6779 12:23:27.831877  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6780 12:23:27.835271  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6781 12:23:27.838766   == TX Byte 1 ==

 6782 12:23:27.842392  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6783 12:23:27.845188  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6784 12:23:27.845712  

 6785 12:23:27.848319  [DATLAT]

 6786 12:23:27.848964  Freq=400, CH1 RK0

 6787 12:23:27.849516  

 6788 12:23:27.851879  DATLAT Default: 0xf

 6789 12:23:27.852292  0, 0xFFFF, sum = 0

 6790 12:23:27.855039  1, 0xFFFF, sum = 0

 6791 12:23:27.855458  2, 0xFFFF, sum = 0

 6792 12:23:27.858401  3, 0xFFFF, sum = 0

 6793 12:23:27.858875  4, 0xFFFF, sum = 0

 6794 12:23:27.861431  5, 0xFFFF, sum = 0

 6795 12:23:27.861989  6, 0xFFFF, sum = 0

 6796 12:23:27.864713  7, 0xFFFF, sum = 0

 6797 12:23:27.867876  8, 0xFFFF, sum = 0

 6798 12:23:27.868314  9, 0xFFFF, sum = 0

 6799 12:23:27.871827  10, 0xFFFF, sum = 0

 6800 12:23:27.872246  11, 0xFFFF, sum = 0

 6801 12:23:27.874766  12, 0xFFFF, sum = 0

 6802 12:23:27.875201  13, 0x0, sum = 1

 6803 12:23:27.878278  14, 0x0, sum = 2

 6804 12:23:27.878998  15, 0x0, sum = 3

 6805 12:23:27.881805  16, 0x0, sum = 4

 6806 12:23:27.882228  best_step = 14

 6807 12:23:27.882559  

 6808 12:23:27.882866  ==

 6809 12:23:27.885176  Dram Type= 6, Freq= 0, CH_1, rank 0

 6810 12:23:27.887989  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6811 12:23:27.888409  ==

 6812 12:23:27.891516  RX Vref Scan: 1

 6813 12:23:27.891954  

 6814 12:23:27.894626  RX Vref 0 -> 0, step: 1

 6815 12:23:27.895033  

 6816 12:23:27.895355  RX Delay -343 -> 252, step: 8

 6817 12:23:27.898094  

 6818 12:23:27.898506  Set Vref, RX VrefLevel [Byte0]: 47

 6819 12:23:27.901096                           [Byte1]: 59

 6820 12:23:27.906725  

 6821 12:23:27.907167  Final RX Vref Byte 0 = 47 to rank0

 6822 12:23:27.910648  Final RX Vref Byte 1 = 59 to rank0

 6823 12:23:27.913773  Final RX Vref Byte 0 = 47 to rank1

 6824 12:23:27.916507  Final RX Vref Byte 1 = 59 to rank1==

 6825 12:23:27.919878  Dram Type= 6, Freq= 0, CH_1, rank 0

 6826 12:23:27.926606  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6827 12:23:27.927151  ==

 6828 12:23:27.927619  DQS Delay:

 6829 12:23:27.929808  DQS0 = 44, DQS1 = 56

 6830 12:23:27.930219  DQM Delay:

 6831 12:23:27.930619  DQM0 = 7, DQM1 = 12

 6832 12:23:27.933290  DQ Delay:

 6833 12:23:27.936445  DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4

 6834 12:23:27.937051  DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4

 6835 12:23:27.939860  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4

 6836 12:23:27.942929  DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24

 6837 12:23:27.943338  

 6838 12:23:27.946266  

 6839 12:23:27.953093  [DQSOSCAuto] RK0, (LSB)MR18= 0x9b73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps

 6840 12:23:27.956199  CH1 RK0: MR19=C0C, MR18=9B73

 6841 12:23:27.962880  CH1_RK0: MR19=0xC0C, MR18=0x9B73, DQSOSC=390, MR23=63, INC=388, DEC=258

 6842 12:23:27.963312  ==

 6843 12:23:27.966241  Dram Type= 6, Freq= 0, CH_1, rank 1

 6844 12:23:27.969850  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6845 12:23:27.970274  ==

 6846 12:23:27.972916  [Gating] SW mode calibration

 6847 12:23:27.979402  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6848 12:23:27.986636  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6849 12:23:27.989871   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6850 12:23:27.992683   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6851 12:23:27.999259   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6852 12:23:28.002400   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6853 12:23:28.006096   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6854 12:23:28.012421   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6855 12:23:28.016065   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6856 12:23:28.019106   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6857 12:23:28.025747   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6858 12:23:28.026426  Total UI for P1: 0, mck2ui 16

 6859 12:23:28.032164  best dqsien dly found for B0: ( 0, 14, 24)

 6860 12:23:28.032579  Total UI for P1: 0, mck2ui 16

 6861 12:23:28.038880  best dqsien dly found for B1: ( 0, 14, 24)

 6862 12:23:28.042022  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6863 12:23:28.045519  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6864 12:23:28.046068  

 6865 12:23:28.048988  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6866 12:23:28.051936  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6867 12:23:28.055164  [Gating] SW calibration Done

 6868 12:23:28.055579  ==

 6869 12:23:28.058357  Dram Type= 6, Freq= 0, CH_1, rank 1

 6870 12:23:28.062381  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6871 12:23:28.063066  ==

 6872 12:23:28.065548  RX Vref Scan: 0

 6873 12:23:28.066062  

 6874 12:23:28.068341  RX Vref 0 -> 0, step: 1

 6875 12:23:28.068765  

 6876 12:23:28.069093  RX Delay -410 -> 252, step: 16

 6877 12:23:28.074933  iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496

 6878 12:23:28.078324  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6879 12:23:28.081505  iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496

 6880 12:23:28.084635  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6881 12:23:28.091772  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6882 12:23:28.094713  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6883 12:23:28.098391  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6884 12:23:28.101392  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6885 12:23:28.108044  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6886 12:23:28.111348  iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512

 6887 12:23:28.114497  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6888 12:23:28.121043  iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512

 6889 12:23:28.124536  iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512

 6890 12:23:28.127782  iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512

 6891 12:23:28.131163  iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512

 6892 12:23:28.137612  iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512

 6893 12:23:28.138031  ==

 6894 12:23:28.141178  Dram Type= 6, Freq= 0, CH_1, rank 1

 6895 12:23:28.144210  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6896 12:23:28.144628  ==

 6897 12:23:28.144957  DQS Delay:

 6898 12:23:28.147709  DQS0 = 51, DQS1 = 59

 6899 12:23:28.148163  DQM Delay:

 6900 12:23:28.150895  DQM0 = 20, DQM1 = 22

 6901 12:23:28.151490  DQ Delay:

 6902 12:23:28.154236  DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16

 6903 12:23:28.157682  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6904 12:23:28.160972  DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16

 6905 12:23:28.164327  DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32

 6906 12:23:28.164741  

 6907 12:23:28.165067  

 6908 12:23:28.165369  ==

 6909 12:23:28.167419  Dram Type= 6, Freq= 0, CH_1, rank 1

 6910 12:23:28.173901  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6911 12:23:28.174416  ==

 6912 12:23:28.174747  

 6913 12:23:28.175055  

 6914 12:23:28.175365  	TX Vref Scan disable

 6915 12:23:28.177300   == TX Byte 0 ==

 6916 12:23:28.180577  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6917 12:23:28.183503  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6918 12:23:28.186721   == TX Byte 1 ==

 6919 12:23:28.190406  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6920 12:23:28.193898  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6921 12:23:28.194430  ==

 6922 12:23:28.196828  Dram Type= 6, Freq= 0, CH_1, rank 1

 6923 12:23:28.203637  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6924 12:23:28.204095  ==

 6925 12:23:28.204424  

 6926 12:23:28.204742  

 6927 12:23:28.205037  	TX Vref Scan disable

 6928 12:23:28.207176   == TX Byte 0 ==

 6929 12:23:28.210301  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6930 12:23:28.213481  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6931 12:23:28.216768   == TX Byte 1 ==

 6932 12:23:28.219818  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6933 12:23:28.222997  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6934 12:23:28.223411  

 6935 12:23:28.226453  [DATLAT]

 6936 12:23:28.226899  Freq=400, CH1 RK1

 6937 12:23:28.227231  

 6938 12:23:28.229714  DATLAT Default: 0xe

 6939 12:23:28.230165  0, 0xFFFF, sum = 0

 6940 12:23:28.233420  1, 0xFFFF, sum = 0

 6941 12:23:28.233840  2, 0xFFFF, sum = 0

 6942 12:23:28.236478  3, 0xFFFF, sum = 0

 6943 12:23:28.236991  4, 0xFFFF, sum = 0

 6944 12:23:28.240287  5, 0xFFFF, sum = 0

 6945 12:23:28.240708  6, 0xFFFF, sum = 0

 6946 12:23:28.242809  7, 0xFFFF, sum = 0

 6947 12:23:28.243228  8, 0xFFFF, sum = 0

 6948 12:23:28.246228  9, 0xFFFF, sum = 0

 6949 12:23:28.249471  10, 0xFFFF, sum = 0

 6950 12:23:28.249891  11, 0xFFFF, sum = 0

 6951 12:23:28.252831  12, 0xFFFF, sum = 0

 6952 12:23:28.253251  13, 0x0, sum = 1

 6953 12:23:28.256155  14, 0x0, sum = 2

 6954 12:23:28.256572  15, 0x0, sum = 3

 6955 12:23:28.256903  16, 0x0, sum = 4

 6956 12:23:28.259530  best_step = 14

 6957 12:23:28.259994  

 6958 12:23:28.260396  ==

 6959 12:23:28.262826  Dram Type= 6, Freq= 0, CH_1, rank 1

 6960 12:23:28.266186  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6961 12:23:28.266602  ==

 6962 12:23:28.269734  RX Vref Scan: 0

 6963 12:23:28.270146  

 6964 12:23:28.272677  RX Vref 0 -> 0, step: 1

 6965 12:23:28.273089  

 6966 12:23:28.273424  RX Delay -359 -> 252, step: 8

 6967 12:23:28.281268  iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480

 6968 12:23:28.284266  iDelay=217, Bit 1, Center -40 (-279 ~ 200) 480

 6969 12:23:28.288007  iDelay=217, Bit 2, Center -48 (-287 ~ 192) 480

 6970 12:23:28.290949  iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480

 6971 12:23:28.297980  iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488

 6972 12:23:28.300830  iDelay=217, Bit 5, Center -24 (-263 ~ 216) 480

 6973 12:23:28.304336  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6974 12:23:28.307522  iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488

 6975 12:23:28.314281  iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504

 6976 12:23:28.317492  iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496

 6977 12:23:28.320697  iDelay=217, Bit 10, Center -44 (-295 ~ 208) 504

 6978 12:23:28.327550  iDelay=217, Bit 11, Center -52 (-303 ~ 200) 504

 6979 12:23:28.330467  iDelay=217, Bit 12, Center -36 (-287 ~ 216) 504

 6980 12:23:28.334179  iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496

 6981 12:23:28.337443  iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496

 6982 12:23:28.344200  iDelay=217, Bit 15, Center -36 (-287 ~ 216) 504

 6983 12:23:28.344284  ==

 6984 12:23:28.347076  Dram Type= 6, Freq= 0, CH_1, rank 1

 6985 12:23:28.350355  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6986 12:23:28.350437  ==

 6987 12:23:28.350526  DQS Delay:

 6988 12:23:28.353876  DQS0 = 48, DQS1 = 60

 6989 12:23:28.353956  DQM Delay:

 6990 12:23:28.356991  DQM0 = 12, DQM1 = 14

 6991 12:23:28.357071  DQ Delay:

 6992 12:23:28.360266  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6993 12:23:28.363950  DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12

 6994 12:23:28.367129  DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8

 6995 12:23:28.370603  DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24

 6996 12:23:28.370683  

 6997 12:23:28.370746  

 6998 12:23:28.377281  [DQSOSCAuto] RK1, (LSB)MR18= 0x6b59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps

 6999 12:23:28.380385  CH1 RK1: MR19=C0C, MR18=6B59

 7000 12:23:28.386727  CH1_RK1: MR19=0xC0C, MR18=0x6B59, DQSOSC=396, MR23=63, INC=376, DEC=251

 7001 12:23:28.390327  [RxdqsGatingPostProcess] freq 400

 7002 12:23:28.397004  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 7003 12:23:28.400367  best DQS0 dly(2T, 0.5T) = (0, 10)

 7004 12:23:28.404047  best DQS1 dly(2T, 0.5T) = (0, 10)

 7005 12:23:28.407252  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7006 12:23:28.410371  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7007 12:23:28.410757  best DQS0 dly(2T, 0.5T) = (0, 10)

 7008 12:23:28.413775  best DQS1 dly(2T, 0.5T) = (0, 10)

 7009 12:23:28.417020  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7010 12:23:28.420387  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7011 12:23:28.423627  Pre-setting of DQS Precalculation

 7012 12:23:28.430515  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 7013 12:23:28.436996  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 7014 12:23:28.443294  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 7015 12:23:28.443711  

 7016 12:23:28.444092  

 7017 12:23:28.446489  [Calibration Summary] 800 Mbps

 7018 12:23:28.446899  CH 0, Rank 0

 7019 12:23:28.450071  SW Impedance     : PASS

 7020 12:23:28.453037  DUTY Scan        : NO K

 7021 12:23:28.453453  ZQ Calibration   : PASS

 7022 12:23:28.456426  Jitter Meter     : NO K

 7023 12:23:28.459793  CBT Training     : PASS

 7024 12:23:28.460208  Write leveling   : PASS

 7025 12:23:28.463509  RX DQS gating    : PASS

 7026 12:23:28.466625  RX DQ/DQS(RDDQC) : PASS

 7027 12:23:28.467036  TX DQ/DQS        : PASS

 7028 12:23:28.469822  RX DATLAT        : PASS

 7029 12:23:28.472849  RX DQ/DQS(Engine): PASS

 7030 12:23:28.473309  TX OE            : NO K

 7031 12:23:28.476390  All Pass.

 7032 12:23:28.476804  

 7033 12:23:28.477143  CH 0, Rank 1

 7034 12:23:28.480202  SW Impedance     : PASS

 7035 12:23:28.480616  DUTY Scan        : NO K

 7036 12:23:28.482884  ZQ Calibration   : PASS

 7037 12:23:28.486174  Jitter Meter     : NO K

 7038 12:23:28.486645  CBT Training     : PASS

 7039 12:23:28.489852  Write leveling   : NO K

 7040 12:23:28.493214  RX DQS gating    : PASS

 7041 12:23:28.493629  RX DQ/DQS(RDDQC) : PASS

 7042 12:23:28.496240  TX DQ/DQS        : PASS

 7043 12:23:28.499435  RX DATLAT        : PASS

 7044 12:23:28.499913  RX DQ/DQS(Engine): PASS

 7045 12:23:28.503134  TX OE            : NO K

 7046 12:23:28.503569  All Pass.

 7047 12:23:28.503974  

 7048 12:23:28.505978  CH 1, Rank 0

 7049 12:23:28.506436  SW Impedance     : PASS

 7050 12:23:28.509395  DUTY Scan        : NO K

 7051 12:23:28.509849  ZQ Calibration   : PASS

 7052 12:23:28.512670  Jitter Meter     : NO K

 7053 12:23:28.516278  CBT Training     : PASS

 7054 12:23:28.516891  Write leveling   : PASS

 7055 12:23:28.519289  RX DQS gating    : PASS

 7056 12:23:28.522590  RX DQ/DQS(RDDQC) : PASS

 7057 12:23:28.523000  TX DQ/DQS        : PASS

 7058 12:23:28.525895  RX DATLAT        : PASS

 7059 12:23:28.528906  RX DQ/DQS(Engine): PASS

 7060 12:23:28.529321  TX OE            : NO K

 7061 12:23:28.532746  All Pass.

 7062 12:23:28.533158  

 7063 12:23:28.533486  CH 1, Rank 1

 7064 12:23:28.536464  SW Impedance     : PASS

 7065 12:23:28.536900  DUTY Scan        : NO K

 7066 12:23:28.539138  ZQ Calibration   : PASS

 7067 12:23:28.542287  Jitter Meter     : NO K

 7068 12:23:28.542695  CBT Training     : PASS

 7069 12:23:28.545578  Write leveling   : NO K

 7070 12:23:28.548948  RX DQS gating    : PASS

 7071 12:23:28.549356  RX DQ/DQS(RDDQC) : PASS

 7072 12:23:28.552379  TX DQ/DQS        : PASS

 7073 12:23:28.555625  RX DATLAT        : PASS

 7074 12:23:28.556129  RX DQ/DQS(Engine): PASS

 7075 12:23:28.558764  TX OE            : NO K

 7076 12:23:28.559172  All Pass.

 7077 12:23:28.559496  

 7078 12:23:28.562246  DramC Write-DBI off

 7079 12:23:28.565296  	PER_BANK_REFRESH: Hybrid Mode

 7080 12:23:28.565756  TX_TRACKING: ON

 7081 12:23:28.575087  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7082 12:23:28.578811  [FAST_K] Save calibration result to emmc

 7083 12:23:28.581469  dramc_set_vcore_voltage set vcore to 725000

 7084 12:23:28.584762  Read voltage for 1600, 0

 7085 12:23:28.585174  Vio18 = 0

 7086 12:23:28.588115  Vcore = 725000

 7087 12:23:28.588528  Vdram = 0

 7088 12:23:28.588856  Vddq = 0

 7089 12:23:28.589158  Vmddr = 0

 7090 12:23:28.594662  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7091 12:23:28.601206  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7092 12:23:28.601755  MEM_TYPE=3, freq_sel=13

 7093 12:23:28.604931  sv_algorithm_assistance_LP4_3733 

 7094 12:23:28.608169  ============ PULL DRAM RESETB DOWN ============

 7095 12:23:28.614462  ========== PULL DRAM RESETB DOWN end =========

 7096 12:23:28.618053  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7097 12:23:28.621124  =================================== 

 7098 12:23:28.624315  LPDDR4 DRAM CONFIGURATION

 7099 12:23:28.627974  =================================== 

 7100 12:23:28.628401  EX_ROW_EN[0]    = 0x0

 7101 12:23:28.631204  EX_ROW_EN[1]    = 0x0

 7102 12:23:28.631630  LP4Y_EN      = 0x0

 7103 12:23:28.634337  WORK_FSP     = 0x1

 7104 12:23:28.637668  WL           = 0x5

 7105 12:23:28.638129  RL           = 0x5

 7106 12:23:28.640874  BL           = 0x2

 7107 12:23:28.641300  RPST         = 0x0

 7108 12:23:28.644142  RD_PRE       = 0x0

 7109 12:23:28.644571  WR_PRE       = 0x1

 7110 12:23:28.647446  WR_PST       = 0x1

 7111 12:23:28.647901  DBI_WR       = 0x0

 7112 12:23:28.650747  DBI_RD       = 0x0

 7113 12:23:28.651175  OTF          = 0x1

 7114 12:23:28.654233  =================================== 

 7115 12:23:28.657496  =================================== 

 7116 12:23:28.660626  ANA top config

 7117 12:23:28.663771  =================================== 

 7118 12:23:28.664202  DLL_ASYNC_EN            =  0

 7119 12:23:28.667168  ALL_SLAVE_EN            =  0

 7120 12:23:28.670662  NEW_RANK_MODE           =  1

 7121 12:23:28.673871  DLL_IDLE_MODE           =  1

 7122 12:23:28.677025  LP45_APHY_COMB_EN       =  1

 7123 12:23:28.677453  TX_ODT_DIS              =  0

 7124 12:23:28.680500  NEW_8X_MODE             =  1

 7125 12:23:28.683839  =================================== 

 7126 12:23:28.687291  =================================== 

 7127 12:23:28.690547  data_rate                  = 3200

 7128 12:23:28.693628  CKR                        = 1

 7129 12:23:28.696885  DQ_P2S_RATIO               = 8

 7130 12:23:28.700444  =================================== 

 7131 12:23:28.700873  CA_P2S_RATIO               = 8

 7132 12:23:28.703391  DQ_CA_OPEN                 = 0

 7133 12:23:28.706813  DQ_SEMI_OPEN               = 0

 7134 12:23:28.710278  CA_SEMI_OPEN               = 0

 7135 12:23:28.713799  CA_FULL_RATE               = 0

 7136 12:23:28.716474  DQ_CKDIV4_EN               = 0

 7137 12:23:28.717018  CA_CKDIV4_EN               = 0

 7138 12:23:28.719821  CA_PREDIV_EN               = 0

 7139 12:23:28.723331  PH8_DLY                    = 12

 7140 12:23:28.726715  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7141 12:23:28.730198  DQ_AAMCK_DIV               = 4

 7142 12:23:28.733287  CA_AAMCK_DIV               = 4

 7143 12:23:28.736736  CA_ADMCK_DIV               = 4

 7144 12:23:28.737448  DQ_TRACK_CA_EN             = 0

 7145 12:23:28.739705  CA_PICK                    = 1600

 7146 12:23:28.743114  CA_MCKIO                   = 1600

 7147 12:23:28.746377  MCKIO_SEMI                 = 0

 7148 12:23:28.749524  PLL_FREQ                   = 3068

 7149 12:23:28.753187  DQ_UI_PI_RATIO             = 32

 7150 12:23:28.756427  CA_UI_PI_RATIO             = 0

 7151 12:23:28.759845  =================================== 

 7152 12:23:28.763250  =================================== 

 7153 12:23:28.763973  memory_type:LPDDR4         

 7154 12:23:28.766287  GP_NUM     : 10       

 7155 12:23:28.769475  SRAM_EN    : 1       

 7156 12:23:28.769954  MD32_EN    : 0       

 7157 12:23:28.772946  =================================== 

 7158 12:23:28.775836  [ANA_INIT] >>>>>>>>>>>>>> 

 7159 12:23:28.779325  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7160 12:23:28.782362  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7161 12:23:28.786052  =================================== 

 7162 12:23:28.789267  data_rate = 3200,PCW = 0X7600

 7163 12:23:28.792656  =================================== 

 7164 12:23:28.795803  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7165 12:23:28.799499  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7166 12:23:28.805528  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7167 12:23:28.809558  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7168 12:23:28.815625  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7169 12:23:28.819230  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7170 12:23:28.820041  [ANA_INIT] flow start 

 7171 12:23:28.822893  [ANA_INIT] PLL >>>>>>>> 

 7172 12:23:28.825814  [ANA_INIT] PLL <<<<<<<< 

 7173 12:23:28.826268  [ANA_INIT] MIDPI >>>>>>>> 

 7174 12:23:28.829026  [ANA_INIT] MIDPI <<<<<<<< 

 7175 12:23:28.832480  [ANA_INIT] DLL >>>>>>>> 

 7176 12:23:28.832938  [ANA_INIT] DLL <<<<<<<< 

 7177 12:23:28.835621  [ANA_INIT] flow end 

 7178 12:23:28.839111  ============ LP4 DIFF to SE enter ============

 7179 12:23:28.842223  ============ LP4 DIFF to SE exit  ============

 7180 12:23:28.845543  [ANA_INIT] <<<<<<<<<<<<< 

 7181 12:23:28.848746  [Flow] Enable top DCM control >>>>> 

 7182 12:23:28.852410  [Flow] Enable top DCM control <<<<< 

 7183 12:23:28.855418  Enable DLL master slave shuffle 

 7184 12:23:28.862188  ============================================================== 

 7185 12:23:28.862722  Gating Mode config

 7186 12:23:28.868491  ============================================================== 

 7187 12:23:28.871607  Config description: 

 7188 12:23:28.878038  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7189 12:23:28.885116  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7190 12:23:28.891228  SELPH_MODE            0: By rank         1: By Phase 

 7191 12:23:28.897883  ============================================================== 

 7192 12:23:28.901371  GAT_TRACK_EN                 =  1

 7193 12:23:28.901788  RX_GATING_MODE               =  2

 7194 12:23:28.904851  RX_GATING_TRACK_MODE         =  2

 7195 12:23:28.907512  SELPH_MODE                   =  1

 7196 12:23:28.911200  PICG_EARLY_EN                =  1

 7197 12:23:28.914377  VALID_LAT_VALUE              =  1

 7198 12:23:28.920925  ============================================================== 

 7199 12:23:28.924029  Enter into Gating configuration >>>> 

 7200 12:23:28.927308  Exit from Gating configuration <<<< 

 7201 12:23:28.931072  Enter into  DVFS_PRE_config >>>>> 

 7202 12:23:28.941271  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7203 12:23:28.944074  Exit from  DVFS_PRE_config <<<<< 

 7204 12:23:28.947776  Enter into PICG configuration >>>> 

 7205 12:23:28.950182  Exit from PICG configuration <<<< 

 7206 12:23:28.953600  [RX_INPUT] configuration >>>>> 

 7207 12:23:28.957365  [RX_INPUT] configuration <<<<< 

 7208 12:23:28.960211  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7209 12:23:28.966987  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7210 12:23:28.973528  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7211 12:23:28.980375  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7212 12:23:28.983572  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7213 12:23:28.990134  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7214 12:23:28.996775  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7215 12:23:29.000329  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7216 12:23:29.003296  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7217 12:23:29.006682  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7218 12:23:29.013121  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7219 12:23:29.016351  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7220 12:23:29.019712  =================================== 

 7221 12:23:29.022892  LPDDR4 DRAM CONFIGURATION

 7222 12:23:29.026561  =================================== 

 7223 12:23:29.026977  EX_ROW_EN[0]    = 0x0

 7224 12:23:29.029518  EX_ROW_EN[1]    = 0x0

 7225 12:23:29.030179  LP4Y_EN      = 0x0

 7226 12:23:29.032621  WORK_FSP     = 0x1

 7227 12:23:29.033036  WL           = 0x5

 7228 12:23:29.036633  RL           = 0x5

 7229 12:23:29.037045  BL           = 0x2

 7230 12:23:29.039249  RPST         = 0x0

 7231 12:23:29.042777  RD_PRE       = 0x0

 7232 12:23:29.043290  WR_PRE       = 0x1

 7233 12:23:29.046145  WR_PST       = 0x1

 7234 12:23:29.046558  DBI_WR       = 0x0

 7235 12:23:29.049210  DBI_RD       = 0x0

 7236 12:23:29.049865  OTF          = 0x1

 7237 12:23:29.052996  =================================== 

 7238 12:23:29.055619  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7239 12:23:29.062463  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7240 12:23:29.066007  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7241 12:23:29.069005  =================================== 

 7242 12:23:29.072581  LPDDR4 DRAM CONFIGURATION

 7243 12:23:29.075543  =================================== 

 7244 12:23:29.076000  EX_ROW_EN[0]    = 0x10

 7245 12:23:29.079134  EX_ROW_EN[1]    = 0x0

 7246 12:23:29.079545  LP4Y_EN      = 0x0

 7247 12:23:29.082403  WORK_FSP     = 0x1

 7248 12:23:29.082815  WL           = 0x5

 7249 12:23:29.085731  RL           = 0x5

 7250 12:23:29.088914  BL           = 0x2

 7251 12:23:29.089327  RPST         = 0x0

 7252 12:23:29.092123  RD_PRE       = 0x0

 7253 12:23:29.092538  WR_PRE       = 0x1

 7254 12:23:29.094953  WR_PST       = 0x1

 7255 12:23:29.095033  DBI_WR       = 0x0

 7256 12:23:29.098081  DBI_RD       = 0x0

 7257 12:23:29.098161  OTF          = 0x1

 7258 12:23:29.101522  =================================== 

 7259 12:23:29.108392  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7260 12:23:29.108473  ==

 7261 12:23:29.111293  Dram Type= 6, Freq= 0, CH_0, rank 0

 7262 12:23:29.114943  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7263 12:23:29.117839  ==

 7264 12:23:29.117920  [Duty_Offset_Calibration]

 7265 12:23:29.121145  	B0:1	B1:-1	CA:0

 7266 12:23:29.121224  

 7267 12:23:29.124613  [DutyScan_Calibration_Flow] k_type=0

 7268 12:23:29.133337  

 7269 12:23:29.133417  ==CLK 0==

 7270 12:23:29.136577  Final CLK duty delay cell = 0

 7271 12:23:29.139875  [0] MAX Duty = 5125%(X100), DQS PI = 24

 7272 12:23:29.143481  [0] MIN Duty = 4907%(X100), DQS PI = 4

 7273 12:23:29.146960  [0] AVG Duty = 5016%(X100)

 7274 12:23:29.147040  

 7275 12:23:29.150083  CH0 CLK Duty spec in!! Max-Min= 218%

 7276 12:23:29.153178  [DutyScan_Calibration_Flow] ====Done====

 7277 12:23:29.153259  

 7278 12:23:29.156294  [DutyScan_Calibration_Flow] k_type=1

 7279 12:23:29.172923  

 7280 12:23:29.173004  ==DQS 0 ==

 7281 12:23:29.175890  Final DQS duty delay cell = -4

 7282 12:23:29.179163  [-4] MAX Duty = 4969%(X100), DQS PI = 16

 7283 12:23:29.182833  [-4] MIN Duty = 4844%(X100), DQS PI = 54

 7284 12:23:29.185728  [-4] AVG Duty = 4906%(X100)

 7285 12:23:29.185808  

 7286 12:23:29.185871  ==DQS 1 ==

 7287 12:23:29.189157  Final DQS duty delay cell = 0

 7288 12:23:29.192438  [0] MAX Duty = 5156%(X100), DQS PI = 2

 7289 12:23:29.195270  [0] MIN Duty = 5000%(X100), DQS PI = 20

 7290 12:23:29.198927  [0] AVG Duty = 5078%(X100)

 7291 12:23:29.199008  

 7292 12:23:29.202026  CH0 DQS 0 Duty spec in!! Max-Min= 125%

 7293 12:23:29.202107  

 7294 12:23:29.205458  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 7295 12:23:29.208646  [DutyScan_Calibration_Flow] ====Done====

 7296 12:23:29.208727  

 7297 12:23:29.212062  [DutyScan_Calibration_Flow] k_type=3

 7298 12:23:29.230920  

 7299 12:23:29.231038  ==DQM 0 ==

 7300 12:23:29.234443  Final DQM duty delay cell = 0

 7301 12:23:29.237307  [0] MAX Duty = 5124%(X100), DQS PI = 20

 7302 12:23:29.240863  [0] MIN Duty = 4907%(X100), DQS PI = 8

 7303 12:23:29.244344  [0] AVG Duty = 5015%(X100)

 7304 12:23:29.244437  

 7305 12:23:29.244509  ==DQM 1 ==

 7306 12:23:29.247591  Final DQM duty delay cell = 4

 7307 12:23:29.250872  [4] MAX Duty = 5249%(X100), DQS PI = 6

 7308 12:23:29.254183  [4] MIN Duty = 5062%(X100), DQS PI = 20

 7309 12:23:29.257478  [4] AVG Duty = 5155%(X100)

 7310 12:23:29.257563  

 7311 12:23:29.260734  CH0 DQM 0 Duty spec in!! Max-Min= 217%

 7312 12:23:29.260826  

 7313 12:23:29.263665  CH0 DQM 1 Duty spec in!! Max-Min= 187%

 7314 12:23:29.267296  [DutyScan_Calibration_Flow] ====Done====

 7315 12:23:29.267394  

 7316 12:23:29.270605  [DutyScan_Calibration_Flow] k_type=2

 7317 12:23:29.287253  

 7318 12:23:29.287401  ==DQ 0 ==

 7319 12:23:29.290796  Final DQ duty delay cell = -4

 7320 12:23:29.294243  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 7321 12:23:29.296915  [-4] MIN Duty = 4876%(X100), DQS PI = 52

 7322 12:23:29.300383  [-4] AVG Duty = 4953%(X100)

 7323 12:23:29.300616  

 7324 12:23:29.300801  ==DQ 1 ==

 7325 12:23:29.303753  Final DQ duty delay cell = 0

 7326 12:23:29.307582  [0] MAX Duty = 5125%(X100), DQS PI = 48

 7327 12:23:29.310467  [0] MIN Duty = 5000%(X100), DQS PI = 36

 7328 12:23:29.313932  [0] AVG Duty = 5062%(X100)

 7329 12:23:29.314351  

 7330 12:23:29.317327  CH0 DQ 0 Duty spec in!! Max-Min= 155%

 7331 12:23:29.317735  

 7332 12:23:29.320387  CH0 DQ 1 Duty spec in!! Max-Min= 125%

 7333 12:23:29.324417  [DutyScan_Calibration_Flow] ====Done====

 7334 12:23:29.324823  ==

 7335 12:23:29.327090  Dram Type= 6, Freq= 0, CH_1, rank 0

 7336 12:23:29.330845  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7337 12:23:29.331357  ==

 7338 12:23:29.333748  [Duty_Offset_Calibration]

 7339 12:23:29.334161  	B0:-1	B1:1	CA:2

 7340 12:23:29.334493  

 7341 12:23:29.336756  [DutyScan_Calibration_Flow] k_type=0

 7342 12:23:29.348036  

 7343 12:23:29.348446  ==CLK 0==

 7344 12:23:29.351800  Final CLK duty delay cell = 0

 7345 12:23:29.355117  [0] MAX Duty = 5218%(X100), DQS PI = 24

 7346 12:23:29.358539  [0] MIN Duty = 4969%(X100), DQS PI = 0

 7347 12:23:29.359171  [0] AVG Duty = 5093%(X100)

 7348 12:23:29.362013  

 7349 12:23:29.364551  CH1 CLK Duty spec in!! Max-Min= 249%

 7350 12:23:29.368046  [DutyScan_Calibration_Flow] ====Done====

 7351 12:23:29.368500  

 7352 12:23:29.371255  [DutyScan_Calibration_Flow] k_type=1

 7353 12:23:29.388332  

 7354 12:23:29.388888  ==DQS 0 ==

 7355 12:23:29.391482  Final DQS duty delay cell = 0

 7356 12:23:29.394670  [0] MAX Duty = 5124%(X100), DQS PI = 18

 7357 12:23:29.397944  [0] MIN Duty = 4907%(X100), DQS PI = 10

 7358 12:23:29.401512  [0] AVG Duty = 5015%(X100)

 7359 12:23:29.401971  

 7360 12:23:29.402431  ==DQS 1 ==

 7361 12:23:29.404527  Final DQS duty delay cell = 0

 7362 12:23:29.407757  [0] MAX Duty = 5093%(X100), DQS PI = 24

 7363 12:23:29.411188  [0] MIN Duty = 4969%(X100), DQS PI = 54

 7364 12:23:29.414554  [0] AVG Duty = 5031%(X100)

 7365 12:23:29.415013  

 7366 12:23:29.417779  CH1 DQS 0 Duty spec in!! Max-Min= 217%

 7367 12:23:29.418241  

 7368 12:23:29.420880  CH1 DQS 1 Duty spec in!! Max-Min= 124%

 7369 12:23:29.424403  [DutyScan_Calibration_Flow] ====Done====

 7370 12:23:29.424862  

 7371 12:23:29.427442  [DutyScan_Calibration_Flow] k_type=3

 7372 12:23:29.445095  

 7373 12:23:29.445644  ==DQM 0 ==

 7374 12:23:29.448174  Final DQM duty delay cell = 0

 7375 12:23:29.451558  [0] MAX Duty = 5218%(X100), DQS PI = 18

 7376 12:23:29.455186  [0] MIN Duty = 5031%(X100), DQS PI = 8

 7377 12:23:29.458056  [0] AVG Duty = 5124%(X100)

 7378 12:23:29.458514  

 7379 12:23:29.458879  ==DQM 1 ==

 7380 12:23:29.461496  Final DQM duty delay cell = 0

 7381 12:23:29.464951  [0] MAX Duty = 5156%(X100), DQS PI = 6

 7382 12:23:29.468289  [0] MIN Duty = 4969%(X100), DQS PI = 32

 7383 12:23:29.471866  [0] AVG Duty = 5062%(X100)

 7384 12:23:29.472370  

 7385 12:23:29.474743  CH1 DQM 0 Duty spec in!! Max-Min= 187%

 7386 12:23:29.475251  

 7387 12:23:29.478398  CH1 DQM 1 Duty spec in!! Max-Min= 187%

 7388 12:23:29.481374  [DutyScan_Calibration_Flow] ====Done====

 7389 12:23:29.481788  

 7390 12:23:29.484613  [DutyScan_Calibration_Flow] k_type=2

 7391 12:23:29.501573  

 7392 12:23:29.502116  ==DQ 0 ==

 7393 12:23:29.504925  Final DQ duty delay cell = 0

 7394 12:23:29.508584  [0] MAX Duty = 5187%(X100), DQS PI = 32

 7395 12:23:29.511837  [0] MIN Duty = 4906%(X100), DQS PI = 10

 7396 12:23:29.512297  [0] AVG Duty = 5046%(X100)

 7397 12:23:29.515261  

 7398 12:23:29.515856  ==DQ 1 ==

 7399 12:23:29.518567  Final DQ duty delay cell = 0

 7400 12:23:29.521523  [0] MAX Duty = 5156%(X100), DQS PI = 8

 7401 12:23:29.524830  [0] MIN Duty = 4969%(X100), DQS PI = 56

 7402 12:23:29.525291  [0] AVG Duty = 5062%(X100)

 7403 12:23:29.525654  

 7404 12:23:29.528341  CH1 DQ 0 Duty spec in!! Max-Min= 281%

 7405 12:23:29.531581  

 7406 12:23:29.534753  CH1 DQ 1 Duty spec in!! Max-Min= 187%

 7407 12:23:29.537778  [DutyScan_Calibration_Flow] ====Done====

 7408 12:23:29.541510  nWR fixed to 30

 7409 12:23:29.541970  [ModeRegInit_LP4] CH0 RK0

 7410 12:23:29.544355  [ModeRegInit_LP4] CH0 RK1

 7411 12:23:29.548283  [ModeRegInit_LP4] CH1 RK0

 7412 12:23:29.551533  [ModeRegInit_LP4] CH1 RK1

 7413 12:23:29.552107  match AC timing 5

 7414 12:23:29.558114  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7415 12:23:29.561185  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7416 12:23:29.564528  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7417 12:23:29.571403  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7418 12:23:29.574547  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7419 12:23:29.575093  [MiockJmeterHQA]

 7420 12:23:29.575455  

 7421 12:23:29.577878  [DramcMiockJmeter] u1RxGatingPI = 0

 7422 12:23:29.581005  0 : 4252, 4027

 7423 12:23:29.581476  4 : 4365, 4137

 7424 12:23:29.584096  8 : 4252, 4027

 7425 12:23:29.584727  12 : 4252, 4027

 7426 12:23:29.585114  16 : 4363, 4138

 7427 12:23:29.588114  20 : 4252, 4027

 7428 12:23:29.588671  24 : 4255, 4029

 7429 12:23:29.591205  28 : 4252, 4027

 7430 12:23:29.591804  32 : 4363, 4138

 7431 12:23:29.594532  36 : 4363, 4138

 7432 12:23:29.595081  40 : 4255, 4029

 7433 12:23:29.597888  44 : 4252, 4027

 7434 12:23:29.598444  48 : 4252, 4027

 7435 12:23:29.598816  52 : 4254, 4029

 7436 12:23:29.601181  56 : 4254, 4029

 7437 12:23:29.601647  60 : 4363, 4138

 7438 12:23:29.604685  64 : 4249, 4027

 7439 12:23:29.605148  68 : 4250, 4027

 7440 12:23:29.607547  72 : 4253, 4029

 7441 12:23:29.608049  76 : 4252, 4029

 7442 12:23:29.610880  80 : 4250, 4027

 7443 12:23:29.611376  84 : 4361, 4137

 7444 12:23:29.611842  88 : 4360, 4138

 7445 12:23:29.614211  92 : 4250, 447

 7446 12:23:29.614676  96 : 4250, 0

 7447 12:23:29.617229  100 : 4252, 0

 7448 12:23:29.617691  104 : 4250, 0

 7449 12:23:29.618062  108 : 4250, 0

 7450 12:23:29.620900  112 : 4252, 0

 7451 12:23:29.621364  116 : 4250, 0

 7452 12:23:29.624171  120 : 4250, 0

 7453 12:23:29.624593  124 : 4252, 0

 7454 12:23:29.624928  128 : 4361, 0

 7455 12:23:29.627449  132 : 4361, 0

 7456 12:23:29.628087  136 : 4363, 0

 7457 12:23:29.628439  140 : 4360, 0

 7458 12:23:29.630659  144 : 4250, 0

 7459 12:23:29.631077  148 : 4250, 0

 7460 12:23:29.634421  152 : 4250, 0

 7461 12:23:29.634938  156 : 4250, 0

 7462 12:23:29.635278  160 : 4250, 0

 7463 12:23:29.637391  164 : 4250, 0

 7464 12:23:29.637906  168 : 4250, 0

 7465 12:23:29.640336  172 : 4250, 0

 7466 12:23:29.640756  176 : 4252, 0

 7467 12:23:29.641090  180 : 4252, 0

 7468 12:23:29.643688  184 : 4250, 0

 7469 12:23:29.644141  188 : 4363, 0

 7470 12:23:29.647133  192 : 4360, 0

 7471 12:23:29.647550  196 : 4250, 0

 7472 12:23:29.647942  200 : 4361, 0

 7473 12:23:29.650500  204 : 4250, 0

 7474 12:23:29.650919  208 : 4252, 0

 7475 12:23:29.653676  212 : 4250, 0

 7476 12:23:29.654096  216 : 4252, 0

 7477 12:23:29.654436  220 : 4250, 0

 7478 12:23:29.656872  224 : 4250, 325

 7479 12:23:29.657294  228 : 4362, 3570

 7480 12:23:29.660457  232 : 4249, 4027

 7481 12:23:29.660874  236 : 4360, 4137

 7482 12:23:29.663974  240 : 4361, 4137

 7483 12:23:29.664489  244 : 4250, 4027

 7484 12:23:29.667082  248 : 4250, 4027

 7485 12:23:29.667503  252 : 4363, 4140

 7486 12:23:29.670650  256 : 4250, 4027

 7487 12:23:29.671165  260 : 4250, 4027

 7488 12:23:29.671632  264 : 4249, 4027

 7489 12:23:29.673371  268 : 4252, 4029

 7490 12:23:29.673790  272 : 4250, 4027

 7491 12:23:29.676673  276 : 4250, 4027

 7492 12:23:29.677092  280 : 4361, 4138

 7493 12:23:29.680031  284 : 4250, 4027

 7494 12:23:29.680449  288 : 4250, 4027

 7495 12:23:29.683606  292 : 4360, 4138

 7496 12:23:29.684066  296 : 4250, 4027

 7497 12:23:29.687061  300 : 4249, 4027

 7498 12:23:29.687576  304 : 4363, 4140

 7499 12:23:29.690153  308 : 4250, 4027

 7500 12:23:29.690573  312 : 4250, 4027

 7501 12:23:29.693778  316 : 4250, 4027

 7502 12:23:29.694285  320 : 4252, 4029

 7503 12:23:29.696922  324 : 4250, 4027

 7504 12:23:29.697347  328 : 4250, 4027

 7505 12:23:29.697871  332 : 4361, 4138

 7506 12:23:29.700037  336 : 4250, 3817

 7507 12:23:29.700463  340 : 4250, 2095

 7508 12:23:29.700799  

 7509 12:23:29.703469  	MIOCK jitter meter	ch=0

 7510 12:23:29.704028  

 7511 12:23:29.706429  1T = (340-92) = 248 dly cells

 7512 12:23:29.713266  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps

 7513 12:23:29.713737  ==

 7514 12:23:29.716012  Dram Type= 6, Freq= 0, CH_0, rank 0

 7515 12:23:29.719484  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7516 12:23:29.720048  ==

 7517 12:23:29.725977  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7518 12:23:29.729411  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7519 12:23:29.732728  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7520 12:23:29.739216  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7521 12:23:29.748577  [CA 0] Center 43 (12~74) winsize 63

 7522 12:23:29.752195  [CA 1] Center 43 (13~73) winsize 61

 7523 12:23:29.755217  [CA 2] Center 38 (9~68) winsize 60

 7524 12:23:29.758447  [CA 3] Center 38 (9~68) winsize 60

 7525 12:23:29.762097  [CA 4] Center 37 (8~66) winsize 59

 7526 12:23:29.765203  [CA 5] Center 36 (6~66) winsize 61

 7527 12:23:29.765619  

 7528 12:23:29.768073  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7529 12:23:29.768154  

 7530 12:23:29.774784  [CATrainingPosCal] consider 1 rank data

 7531 12:23:29.775198  u2DelayCellTimex100 = 262/100 ps

 7532 12:23:29.781798  CA0 delay=43 (12~74),Diff = 7 PI (26 cell)

 7533 12:23:29.784964  CA1 delay=43 (13~73),Diff = 7 PI (26 cell)

 7534 12:23:29.788164  CA2 delay=38 (9~68),Diff = 2 PI (7 cell)

 7535 12:23:29.791697  CA3 delay=38 (9~68),Diff = 2 PI (7 cell)

 7536 12:23:29.794792  CA4 delay=37 (8~66),Diff = 1 PI (3 cell)

 7537 12:23:29.798197  CA5 delay=36 (6~66),Diff = 0 PI (0 cell)

 7538 12:23:29.798653  

 7539 12:23:29.801330  CA PerBit enable=1, Macro0, CA PI delay=36

 7540 12:23:29.801789  

 7541 12:23:29.804902  [CBTSetCACLKResult] CA Dly = 36

 7542 12:23:29.808188  CS Dly: 11 (0~42)

 7543 12:23:29.811044  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7544 12:23:29.814602  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7545 12:23:29.815060  ==

 7546 12:23:29.818561  Dram Type= 6, Freq= 0, CH_0, rank 1

 7547 12:23:29.824812  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7548 12:23:29.825274  ==

 7549 12:23:29.828523  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7550 12:23:29.834233  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7551 12:23:29.837627  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7552 12:23:29.844459  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7553 12:23:29.852431  [CA 0] Center 42 (12~73) winsize 62

 7554 12:23:29.855801  [CA 1] Center 43 (13~73) winsize 61

 7555 12:23:29.859168  [CA 2] Center 37 (8~67) winsize 60

 7556 12:23:29.862472  [CA 3] Center 37 (7~67) winsize 61

 7557 12:23:29.865204  [CA 4] Center 35 (6~65) winsize 60

 7558 12:23:29.868697  [CA 5] Center 35 (5~65) winsize 61

 7559 12:23:29.869157  

 7560 12:23:29.871902  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7561 12:23:29.872469  

 7562 12:23:29.878304  [CATrainingPosCal] consider 2 rank data

 7563 12:23:29.878852  u2DelayCellTimex100 = 262/100 ps

 7564 12:23:29.885472  CA0 delay=42 (12~73),Diff = 7 PI (26 cell)

 7565 12:23:29.888308  CA1 delay=43 (13~73),Diff = 8 PI (29 cell)

 7566 12:23:29.891414  CA2 delay=38 (9~67),Diff = 3 PI (11 cell)

 7567 12:23:29.895155  CA3 delay=38 (9~67),Diff = 3 PI (11 cell)

 7568 12:23:29.897758  CA4 delay=36 (8~65),Diff = 1 PI (3 cell)

 7569 12:23:29.901491  CA5 delay=35 (6~65),Diff = 0 PI (0 cell)

 7570 12:23:29.902046  

 7571 12:23:29.905039  CA PerBit enable=1, Macro0, CA PI delay=35

 7572 12:23:29.905498  

 7573 12:23:29.907750  [CBTSetCACLKResult] CA Dly = 35

 7574 12:23:29.911341  CS Dly: 12 (0~44)

 7575 12:23:29.914231  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7576 12:23:29.918104  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7577 12:23:29.918664  

 7578 12:23:29.921287  ----->DramcWriteLeveling(PI) begin...

 7579 12:23:29.924641  ==

 7580 12:23:29.927886  Dram Type= 6, Freq= 0, CH_0, rank 0

 7581 12:23:29.930866  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7582 12:23:29.931311  ==

 7583 12:23:29.934201  Write leveling (Byte 0): 35 => 35

 7584 12:23:29.937908  Write leveling (Byte 1): 27 => 27

 7585 12:23:29.940804  DramcWriteLeveling(PI) end<-----

 7586 12:23:29.941244  

 7587 12:23:29.941629  ==

 7588 12:23:29.944545  Dram Type= 6, Freq= 0, CH_0, rank 0

 7589 12:23:29.947355  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7590 12:23:29.947833  ==

 7591 12:23:29.950909  [Gating] SW mode calibration

 7592 12:23:29.957203  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7593 12:23:29.964027  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7594 12:23:29.967090   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7595 12:23:29.970563   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7596 12:23:29.977137   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7597 12:23:29.980455   1  4 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)

 7598 12:23:29.983709   1  4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 7599 12:23:29.990137   1  4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)

 7600 12:23:29.993581   1  4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 7601 12:23:29.997006   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7602 12:23:30.003709   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7603 12:23:30.006759   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7604 12:23:30.010330   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 7605 12:23:30.016907   1  5 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)

 7606 12:23:30.019771   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)

 7607 12:23:30.023158   1  5 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)

 7608 12:23:30.029878   1  5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)

 7609 12:23:30.033312   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7610 12:23:30.036283   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7611 12:23:30.042659   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7612 12:23:30.046081   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7613 12:23:30.049687   1  6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)

 7614 12:23:30.056204   1  6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 7615 12:23:30.059420   1  6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)

 7616 12:23:30.062337   1  6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)

 7617 12:23:30.068960   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7618 12:23:30.072579   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7619 12:23:30.076075   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7620 12:23:30.082348   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7621 12:23:30.085839   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7622 12:23:30.088754   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 7623 12:23:30.095798   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7624 12:23:30.098950   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7625 12:23:30.102665   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7626 12:23:30.109013   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7627 12:23:30.112232   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7628 12:23:30.115218   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7629 12:23:30.122032   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7630 12:23:30.125885   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7631 12:23:30.128841   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7632 12:23:30.135152   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7633 12:23:30.138152   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7634 12:23:30.141412   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7635 12:23:30.148541   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7636 12:23:30.151830   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7637 12:23:30.154991   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7638 12:23:30.161436   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7639 12:23:30.161975  Total UI for P1: 0, mck2ui 16

 7640 12:23:30.168063  best dqsien dly found for B0: ( 1,  9, 12)

 7641 12:23:30.171849   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7642 12:23:30.174864   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7643 12:23:30.178295  Total UI for P1: 0, mck2ui 16

 7644 12:23:30.181609  best dqsien dly found for B1: ( 1,  9, 18)

 7645 12:23:30.184933  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 7646 12:23:30.187937  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 7647 12:23:30.188353  

 7648 12:23:30.194478  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 7649 12:23:30.197980  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 7650 12:23:30.201750  [Gating] SW calibration Done

 7651 12:23:30.202264  ==

 7652 12:23:30.204241  Dram Type= 6, Freq= 0, CH_0, rank 0

 7653 12:23:30.207960  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7654 12:23:30.208548  ==

 7655 12:23:30.208922  RX Vref Scan: 0

 7656 12:23:30.209264  

 7657 12:23:30.211080  RX Vref 0 -> 0, step: 1

 7658 12:23:30.211540  

 7659 12:23:30.214201  RX Delay 0 -> 252, step: 8

 7660 12:23:30.217897  iDelay=200, Bit 0, Center 135 (88 ~ 183) 96

 7661 12:23:30.221173  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 7662 12:23:30.227598  iDelay=200, Bit 2, Center 131 (80 ~ 183) 104

 7663 12:23:30.230962  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 7664 12:23:30.234063  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 7665 12:23:30.237675  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7666 12:23:30.240789  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 7667 12:23:30.244436  iDelay=200, Bit 7, Center 147 (96 ~ 199) 104

 7668 12:23:30.251415  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 7669 12:23:30.254231  iDelay=200, Bit 9, Center 111 (56 ~ 167) 112

 7670 12:23:30.257442  iDelay=200, Bit 10, Center 127 (72 ~ 183) 112

 7671 12:23:30.260800  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 7672 12:23:30.267418  iDelay=200, Bit 12, Center 131 (80 ~ 183) 104

 7673 12:23:30.270652  iDelay=200, Bit 13, Center 131 (80 ~ 183) 104

 7674 12:23:30.274077  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7675 12:23:30.276825  iDelay=200, Bit 15, Center 131 (72 ~ 191) 120

 7676 12:23:30.277244  ==

 7677 12:23:30.280170  Dram Type= 6, Freq= 0, CH_0, rank 0

 7678 12:23:30.287292  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7679 12:23:30.287860  ==

 7680 12:23:30.288209  DQS Delay:

 7681 12:23:30.290074  DQS0 = 0, DQS1 = 0

 7682 12:23:30.290490  DQM Delay:

 7683 12:23:30.290825  DQM0 = 135, DQM1 = 125

 7684 12:23:30.293692  DQ Delay:

 7685 12:23:30.296919  DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131

 7686 12:23:30.299958  DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147

 7687 12:23:30.303681  DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119

 7688 12:23:30.306695  DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131

 7689 12:23:30.307110  

 7690 12:23:30.307438  

 7691 12:23:30.307787  ==

 7692 12:23:30.310153  Dram Type= 6, Freq= 0, CH_0, rank 0

 7693 12:23:30.316532  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7694 12:23:30.317021  ==

 7695 12:23:30.317364  

 7696 12:23:30.317683  

 7697 12:23:30.317985  	TX Vref Scan disable

 7698 12:23:30.319821   == TX Byte 0 ==

 7699 12:23:30.323295  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 7700 12:23:30.329917  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 7701 12:23:30.330542   == TX Byte 1 ==

 7702 12:23:30.333458  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 7703 12:23:30.339712  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 7704 12:23:30.340170  ==

 7705 12:23:30.343057  Dram Type= 6, Freq= 0, CH_0, rank 0

 7706 12:23:30.345986  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7707 12:23:30.346408  ==

 7708 12:23:30.359892  

 7709 12:23:30.363108  TX Vref early break, caculate TX vref

 7710 12:23:30.366324  TX Vref=16, minBit 14, minWin=21, winSum=368

 7711 12:23:30.369874  TX Vref=18, minBit 1, minWin=23, winSum=379

 7712 12:23:30.372707  TX Vref=20, minBit 6, minWin=23, winSum=389

 7713 12:23:30.376061  TX Vref=22, minBit 0, minWin=25, winSum=403

 7714 12:23:30.379164  TX Vref=24, minBit 0, minWin=24, winSum=409

 7715 12:23:30.385985  TX Vref=26, minBit 4, minWin=25, winSum=417

 7716 12:23:30.389245  TX Vref=28, minBit 0, minWin=25, winSum=420

 7717 12:23:30.392339  TX Vref=30, minBit 4, minWin=24, winSum=407

 7718 12:23:30.395959  TX Vref=32, minBit 0, minWin=24, winSum=399

 7719 12:23:30.398915  TX Vref=34, minBit 6, minWin=23, winSum=389

 7720 12:23:30.405324  [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28

 7721 12:23:30.405747  

 7722 12:23:30.409023  Final TX Range 0 Vref 28

 7723 12:23:30.409602  

 7724 12:23:30.410075  ==

 7725 12:23:30.412292  Dram Type= 6, Freq= 0, CH_0, rank 0

 7726 12:23:30.415362  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7727 12:23:30.415829  ==

 7728 12:23:30.416170  

 7729 12:23:30.416479  

 7730 12:23:30.418441  	TX Vref Scan disable

 7731 12:23:30.425262  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps

 7732 12:23:30.425680   == TX Byte 0 ==

 7733 12:23:30.428371  u2DelayCellOfst[0]=18 cells (5 PI)

 7734 12:23:30.431807  u2DelayCellOfst[1]=18 cells (5 PI)

 7735 12:23:30.435325  u2DelayCellOfst[2]=14 cells (4 PI)

 7736 12:23:30.438732  u2DelayCellOfst[3]=14 cells (4 PI)

 7737 12:23:30.442195  u2DelayCellOfst[4]=11 cells (3 PI)

 7738 12:23:30.445555  u2DelayCellOfst[5]=0 cells (0 PI)

 7739 12:23:30.448357  u2DelayCellOfst[6]=22 cells (6 PI)

 7740 12:23:30.451546  u2DelayCellOfst[7]=22 cells (6 PI)

 7741 12:23:30.455034  Update DQ  dly =987 (3 ,6, 27)  DQ  OEN =(3 ,3)

 7742 12:23:30.458137  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 7743 12:23:30.461325   == TX Byte 1 ==

 7744 12:23:30.464821  u2DelayCellOfst[8]=0 cells (0 PI)

 7745 12:23:30.468295  u2DelayCellOfst[9]=0 cells (0 PI)

 7746 12:23:30.471452  u2DelayCellOfst[10]=3 cells (1 PI)

 7747 12:23:30.475060  u2DelayCellOfst[11]=0 cells (0 PI)

 7748 12:23:30.475630  u2DelayCellOfst[12]=11 cells (3 PI)

 7749 12:23:30.478536  u2DelayCellOfst[13]=11 cells (3 PI)

 7750 12:23:30.481513  u2DelayCellOfst[14]=14 cells (4 PI)

 7751 12:23:30.484928  u2DelayCellOfst[15]=11 cells (3 PI)

 7752 12:23:30.491363  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 7753 12:23:30.495224  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 7754 12:23:30.495827  DramC Write-DBI on

 7755 12:23:30.497748  ==

 7756 12:23:30.501242  Dram Type= 6, Freq= 0, CH_0, rank 0

 7757 12:23:30.504463  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7758 12:23:30.505014  ==

 7759 12:23:30.505349  

 7760 12:23:30.505660  

 7761 12:23:30.507847  	TX Vref Scan disable

 7762 12:23:30.508266   == TX Byte 0 ==

 7763 12:23:30.514573  Update DQM dly =734 (2 ,6, 30)  DQM OEN =(3 ,3)

 7764 12:23:30.515010   == TX Byte 1 ==

 7765 12:23:30.517882  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 7766 12:23:30.521615  DramC Write-DBI off

 7767 12:23:30.522140  

 7768 12:23:30.522472  [DATLAT]

 7769 12:23:30.524215  Freq=1600, CH0 RK0

 7770 12:23:30.524635  

 7771 12:23:30.524967  DATLAT Default: 0xf

 7772 12:23:30.527264  0, 0xFFFF, sum = 0

 7773 12:23:30.527884  1, 0xFFFF, sum = 0

 7774 12:23:30.531264  2, 0xFFFF, sum = 0

 7775 12:23:30.531832  3, 0xFFFF, sum = 0

 7776 12:23:30.533920  4, 0xFFFF, sum = 0

 7777 12:23:30.537205  5, 0xFFFF, sum = 0

 7778 12:23:30.537650  6, 0xFFFF, sum = 0

 7779 12:23:30.540287  7, 0xFFFF, sum = 0

 7780 12:23:30.540712  8, 0xFFFF, sum = 0

 7781 12:23:30.544055  9, 0xFFFF, sum = 0

 7782 12:23:30.544477  10, 0xFFFF, sum = 0

 7783 12:23:30.547669  11, 0xFFFF, sum = 0

 7784 12:23:30.548244  12, 0xFFFF, sum = 0

 7785 12:23:30.550512  13, 0xFFFF, sum = 0

 7786 12:23:30.550936  14, 0x0, sum = 1

 7787 12:23:30.553668  15, 0x0, sum = 2

 7788 12:23:30.554128  16, 0x0, sum = 3

 7789 12:23:30.557356  17, 0x0, sum = 4

 7790 12:23:30.557798  best_step = 15

 7791 12:23:30.558130  

 7792 12:23:30.558435  ==

 7793 12:23:30.560713  Dram Type= 6, Freq= 0, CH_0, rank 0

 7794 12:23:30.566804  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7795 12:23:30.567228  ==

 7796 12:23:30.567563  RX Vref Scan: 1

 7797 12:23:30.567961  

 7798 12:23:30.570399  Set Vref Range= 24 -> 127

 7799 12:23:30.570910  

 7800 12:23:30.573779  RX Vref 24 -> 127, step: 1

 7801 12:23:30.574365  

 7802 12:23:30.574745  RX Delay 11 -> 252, step: 4

 7803 12:23:30.575067  

 7804 12:23:30.576853  Set Vref, RX VrefLevel [Byte0]: 24

 7805 12:23:30.579989                           [Byte1]: 24

 7806 12:23:30.584233  

 7807 12:23:30.584650  Set Vref, RX VrefLevel [Byte0]: 25

 7808 12:23:30.587469                           [Byte1]: 25

 7809 12:23:30.592113  

 7810 12:23:30.592638  Set Vref, RX VrefLevel [Byte0]: 26

 7811 12:23:30.595616                           [Byte1]: 26

 7812 12:23:30.599625  

 7813 12:23:30.600187  Set Vref, RX VrefLevel [Byte0]: 27

 7814 12:23:30.602771                           [Byte1]: 27

 7815 12:23:30.607297  

 7816 12:23:30.607888  Set Vref, RX VrefLevel [Byte0]: 28

 7817 12:23:30.610747                           [Byte1]: 28

 7818 12:23:30.614524  

 7819 12:23:30.614942  Set Vref, RX VrefLevel [Byte0]: 29

 7820 12:23:30.617736                           [Byte1]: 29

 7821 12:23:30.622482  

 7822 12:23:30.622998  Set Vref, RX VrefLevel [Byte0]: 30

 7823 12:23:30.625520                           [Byte1]: 30

 7824 12:23:30.629794  

 7825 12:23:30.630211  Set Vref, RX VrefLevel [Byte0]: 31

 7826 12:23:30.633184                           [Byte1]: 31

 7827 12:23:30.637576  

 7828 12:23:30.638034  Set Vref, RX VrefLevel [Byte0]: 32

 7829 12:23:30.640924                           [Byte1]: 32

 7830 12:23:30.645171  

 7831 12:23:30.645586  Set Vref, RX VrefLevel [Byte0]: 33

 7832 12:23:30.648193                           [Byte1]: 33

 7833 12:23:30.652795  

 7834 12:23:30.653212  Set Vref, RX VrefLevel [Byte0]: 34

 7835 12:23:30.656175                           [Byte1]: 34

 7836 12:23:30.660403  

 7837 12:23:30.660986  Set Vref, RX VrefLevel [Byte0]: 35

 7838 12:23:30.663684                           [Byte1]: 35

 7839 12:23:30.668016  

 7840 12:23:30.668537  Set Vref, RX VrefLevel [Byte0]: 36

 7841 12:23:30.671340                           [Byte1]: 36

 7842 12:23:30.675620  

 7843 12:23:30.676314  Set Vref, RX VrefLevel [Byte0]: 37

 7844 12:23:30.678871                           [Byte1]: 37

 7845 12:23:30.683150  

 7846 12:23:30.683565  Set Vref, RX VrefLevel [Byte0]: 38

 7847 12:23:30.686285                           [Byte1]: 38

 7848 12:23:30.691276  

 7849 12:23:30.692068  Set Vref, RX VrefLevel [Byte0]: 39

 7850 12:23:30.694637                           [Byte1]: 39

 7851 12:23:30.698367  

 7852 12:23:30.698829  Set Vref, RX VrefLevel [Byte0]: 40

 7853 12:23:30.701660                           [Byte1]: 40

 7854 12:23:30.706303  

 7855 12:23:30.706741  Set Vref, RX VrefLevel [Byte0]: 41

 7856 12:23:30.709295                           [Byte1]: 41

 7857 12:23:30.713746  

 7858 12:23:30.714162  Set Vref, RX VrefLevel [Byte0]: 42

 7859 12:23:30.717256                           [Byte1]: 42

 7860 12:23:30.721477  

 7861 12:23:30.721908  Set Vref, RX VrefLevel [Byte0]: 43

 7862 12:23:30.724220                           [Byte1]: 43

 7863 12:23:30.729011  

 7864 12:23:30.729535  Set Vref, RX VrefLevel [Byte0]: 44

 7865 12:23:30.732360                           [Byte1]: 44

 7866 12:23:30.736677  

 7867 12:23:30.737303  Set Vref, RX VrefLevel [Byte0]: 45

 7868 12:23:30.739679                           [Byte1]: 45

 7869 12:23:30.743930  

 7870 12:23:30.744362  Set Vref, RX VrefLevel [Byte0]: 46

 7871 12:23:30.747330                           [Byte1]: 46

 7872 12:23:30.751610  

 7873 12:23:30.752080  Set Vref, RX VrefLevel [Byte0]: 47

 7874 12:23:30.755075                           [Byte1]: 47

 7875 12:23:30.759369  

 7876 12:23:30.759832  Set Vref, RX VrefLevel [Byte0]: 48

 7877 12:23:30.762483                           [Byte1]: 48

 7878 12:23:30.767325  

 7879 12:23:30.767798  Set Vref, RX VrefLevel [Byte0]: 49

 7880 12:23:30.770164                           [Byte1]: 49

 7881 12:23:30.774303  

 7882 12:23:30.774721  Set Vref, RX VrefLevel [Byte0]: 50

 7883 12:23:30.777984                           [Byte1]: 50

 7884 12:23:30.782059  

 7885 12:23:30.782497  Set Vref, RX VrefLevel [Byte0]: 51

 7886 12:23:30.785453                           [Byte1]: 51

 7887 12:23:30.789543  

 7888 12:23:30.789958  Set Vref, RX VrefLevel [Byte0]: 52

 7889 12:23:30.792798                           [Byte1]: 52

 7890 12:23:30.797023  

 7891 12:23:30.797460  Set Vref, RX VrefLevel [Byte0]: 53

 7892 12:23:30.800349                           [Byte1]: 53

 7893 12:23:30.804826  

 7894 12:23:30.805263  Set Vref, RX VrefLevel [Byte0]: 54

 7895 12:23:30.808709                           [Byte1]: 54

 7896 12:23:30.812441  

 7897 12:23:30.812859  Set Vref, RX VrefLevel [Byte0]: 55

 7898 12:23:30.815621                           [Byte1]: 55

 7899 12:23:30.820044  

 7900 12:23:30.820457  Set Vref, RX VrefLevel [Byte0]: 56

 7901 12:23:30.823683                           [Byte1]: 56

 7902 12:23:30.828097  

 7903 12:23:30.828515  Set Vref, RX VrefLevel [Byte0]: 57

 7904 12:23:30.831165                           [Byte1]: 57

 7905 12:23:30.835319  

 7906 12:23:30.835766  Set Vref, RX VrefLevel [Byte0]: 58

 7907 12:23:30.838575                           [Byte1]: 58

 7908 12:23:30.843224  

 7909 12:23:30.843749  Set Vref, RX VrefLevel [Byte0]: 59

 7910 12:23:30.846623                           [Byte1]: 59

 7911 12:23:30.850892  

 7912 12:23:30.851336  Set Vref, RX VrefLevel [Byte0]: 60

 7913 12:23:30.854029                           [Byte1]: 60

 7914 12:23:30.858369  

 7915 12:23:30.858918  Set Vref, RX VrefLevel [Byte0]: 61

 7916 12:23:30.861328                           [Byte1]: 61

 7917 12:23:30.865886  

 7918 12:23:30.866480  Set Vref, RX VrefLevel [Byte0]: 62

 7919 12:23:30.869655                           [Byte1]: 62

 7920 12:23:30.873227  

 7921 12:23:30.873683  Set Vref, RX VrefLevel [Byte0]: 63

 7922 12:23:30.877075                           [Byte1]: 63

 7923 12:23:30.881340  

 7924 12:23:30.881896  Set Vref, RX VrefLevel [Byte0]: 64

 7925 12:23:30.884683                           [Byte1]: 64

 7926 12:23:30.889103  

 7927 12:23:30.889557  Set Vref, RX VrefLevel [Byte0]: 65

 7928 12:23:30.892193                           [Byte1]: 65

 7929 12:23:30.896565  

 7930 12:23:30.897021  Set Vref, RX VrefLevel [Byte0]: 66

 7931 12:23:30.899504                           [Byte1]: 66

 7932 12:23:30.903901  

 7933 12:23:30.904319  Set Vref, RX VrefLevel [Byte0]: 67

 7934 12:23:30.907071                           [Byte1]: 67

 7935 12:23:30.911634  

 7936 12:23:30.912098  Set Vref, RX VrefLevel [Byte0]: 68

 7937 12:23:30.914977                           [Byte1]: 68

 7938 12:23:30.919041  

 7939 12:23:30.919453  Set Vref, RX VrefLevel [Byte0]: 69

 7940 12:23:30.922357                           [Byte1]: 69

 7941 12:23:30.926677  

 7942 12:23:30.927189  Set Vref, RX VrefLevel [Byte0]: 70

 7943 12:23:30.929904                           [Byte1]: 70

 7944 12:23:30.934387  

 7945 12:23:30.934889  Set Vref, RX VrefLevel [Byte0]: 71

 7946 12:23:30.938330                           [Byte1]: 71

 7947 12:23:30.942064  

 7948 12:23:30.942580  Set Vref, RX VrefLevel [Byte0]: 72

 7949 12:23:30.945634                           [Byte1]: 72

 7950 12:23:30.949779  

 7951 12:23:30.950286  Set Vref, RX VrefLevel [Byte0]: 73

 7952 12:23:30.953565                           [Byte1]: 73

 7953 12:23:30.957546  

 7954 12:23:30.958052  Set Vref, RX VrefLevel [Byte0]: 74

 7955 12:23:30.960322                           [Byte1]: 74

 7956 12:23:30.964864  

 7957 12:23:30.965410  Set Vref, RX VrefLevel [Byte0]: 75

 7958 12:23:30.967889                           [Byte1]: 75

 7959 12:23:30.972315  

 7960 12:23:30.972820  Set Vref, RX VrefLevel [Byte0]: 76

 7961 12:23:30.975848                           [Byte1]: 76

 7962 12:23:30.980260  

 7963 12:23:30.980674  Set Vref, RX VrefLevel [Byte0]: 77

 7964 12:23:30.983496                           [Byte1]: 77

 7965 12:23:30.987550  

 7966 12:23:30.988277  Set Vref, RX VrefLevel [Byte0]: 78

 7967 12:23:30.991017                           [Byte1]: 78

 7968 12:23:30.995368  

 7969 12:23:30.995891  Set Vref, RX VrefLevel [Byte0]: 79

 7970 12:23:30.998772                           [Byte1]: 79

 7971 12:23:31.002832  

 7972 12:23:31.003289  Set Vref, RX VrefLevel [Byte0]: 80

 7973 12:23:31.006592                           [Byte1]: 80

 7974 12:23:31.010677  

 7975 12:23:31.011283  Final RX Vref Byte 0 = 67 to rank0

 7976 12:23:31.014070  Final RX Vref Byte 1 = 57 to rank0

 7977 12:23:31.017108  Final RX Vref Byte 0 = 67 to rank1

 7978 12:23:31.020458  Final RX Vref Byte 1 = 57 to rank1==

 7979 12:23:31.023771  Dram Type= 6, Freq= 0, CH_0, rank 0

 7980 12:23:31.030261  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7981 12:23:31.030822  ==

 7982 12:23:31.031194  DQS Delay:

 7983 12:23:31.033725  DQS0 = 0, DQS1 = 0

 7984 12:23:31.034546  DQM Delay:

 7985 12:23:31.035089  DQM0 = 133, DQM1 = 124

 7986 12:23:31.037385  DQ Delay:

 7987 12:23:31.040567  DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132

 7988 12:23:31.043422  DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142

 7989 12:23:31.046660  DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118

 7990 12:23:31.050557  DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =130

 7991 12:23:31.051363  

 7992 12:23:31.051969  

 7993 12:23:31.052337  

 7994 12:23:31.053862  [DramC_TX_OE_Calibration] TA2

 7995 12:23:31.056956  Original DQ_B0 (3 6) =30, OEN = 27

 7996 12:23:31.060385  Original DQ_B1 (3 6) =30, OEN = 27

 7997 12:23:31.063440  24, 0x0, End_B0=24 End_B1=24

 7998 12:23:31.066974  25, 0x0, End_B0=25 End_B1=25

 7999 12:23:31.067555  26, 0x0, End_B0=26 End_B1=26

 8000 12:23:31.070052  27, 0x0, End_B0=27 End_B1=27

 8001 12:23:31.073184  28, 0x0, End_B0=28 End_B1=28

 8002 12:23:31.077030  29, 0x0, End_B0=29 End_B1=29

 8003 12:23:31.077686  30, 0x0, End_B0=30 End_B1=30

 8004 12:23:31.079780  31, 0x4141, End_B0=30 End_B1=30

 8005 12:23:31.083029  Byte0 end_step=30  best_step=27

 8006 12:23:31.086165  Byte1 end_step=30  best_step=27

 8007 12:23:31.089508  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8008 12:23:31.092740  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8009 12:23:31.093199  

 8010 12:23:31.093560  

 8011 12:23:31.099915  [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps

 8012 12:23:31.102750  CH0 RK0: MR19=303, MR18=2415

 8013 12:23:31.109080  CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16

 8014 12:23:31.109622  

 8015 12:23:31.112596  ----->DramcWriteLeveling(PI) begin...

 8016 12:23:31.113069  ==

 8017 12:23:31.115679  Dram Type= 6, Freq= 0, CH_0, rank 1

 8018 12:23:31.119249  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8019 12:23:31.119714  ==

 8020 12:23:31.122331  Write leveling (Byte 0): 38 => 38

 8021 12:23:31.125645  Write leveling (Byte 1): 26 => 26

 8022 12:23:31.129203  DramcWriteLeveling(PI) end<-----

 8023 12:23:31.129668  

 8024 12:23:31.130032  ==

 8025 12:23:31.132223  Dram Type= 6, Freq= 0, CH_0, rank 1

 8026 12:23:31.139020  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8027 12:23:31.139442  ==

 8028 12:23:31.139869  [Gating] SW mode calibration

 8029 12:23:31.149262  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8030 12:23:31.151839  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8031 12:23:31.155531   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8032 12:23:31.161918   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8033 12:23:31.165344   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8034 12:23:31.172234   1  4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8035 12:23:31.175327   1  4 16 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)

 8036 12:23:31.178642   1  4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)

 8037 12:23:31.184849   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8038 12:23:31.188423   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8039 12:23:31.191686   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8040 12:23:31.195103   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8041 12:23:31.201697   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8042 12:23:31.204752   1  5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 8043 12:23:31.208168   1  5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)

 8044 12:23:31.215065   1  5 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)

 8045 12:23:31.217895   1  5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 8046 12:23:31.221560   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8047 12:23:31.228094   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8048 12:23:31.231523   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8049 12:23:31.234561   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8050 12:23:31.241390   1  6 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)

 8051 12:23:31.244778   1  6 16 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)

 8052 12:23:31.247967   1  6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)

 8053 12:23:31.254699   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8054 12:23:31.257917   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8055 12:23:31.261379   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8056 12:23:31.267792   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8057 12:23:31.271160   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8058 12:23:31.274477   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8059 12:23:31.280763   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8060 12:23:31.284159   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8061 12:23:31.287863   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8062 12:23:31.293773   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8063 12:23:31.297598   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8064 12:23:31.300648   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8065 12:23:31.306975   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8066 12:23:31.310329   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8067 12:23:31.314251   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8068 12:23:31.320277   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8069 12:23:31.323593   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8070 12:23:31.326597   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8071 12:23:31.333894   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8072 12:23:31.336982   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8073 12:23:31.340210   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8074 12:23:31.346970   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8075 12:23:31.350210   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8076 12:23:31.353277  Total UI for P1: 0, mck2ui 16

 8077 12:23:31.356607  best dqsien dly found for B0: ( 1,  9, 12)

 8078 12:23:31.360035   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8079 12:23:31.366634   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8080 12:23:31.370065  Total UI for P1: 0, mck2ui 16

 8081 12:23:31.373281  best dqsien dly found for B1: ( 1,  9, 18)

 8082 12:23:31.376268  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8083 12:23:31.379696  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 8084 12:23:31.380338  

 8085 12:23:31.383027  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8086 12:23:31.386103  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 8087 12:23:31.389945  [Gating] SW calibration Done

 8088 12:23:31.390436  ==

 8089 12:23:31.392816  Dram Type= 6, Freq= 0, CH_0, rank 1

 8090 12:23:31.396308  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8091 12:23:31.396818  ==

 8092 12:23:31.399589  RX Vref Scan: 0

 8093 12:23:31.400047  

 8094 12:23:31.402696  RX Vref 0 -> 0, step: 1

 8095 12:23:31.403273  

 8096 12:23:31.403842  RX Delay 0 -> 252, step: 8

 8097 12:23:31.409629  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8098 12:23:31.412497  iDelay=200, Bit 1, Center 135 (80 ~ 191) 112

 8099 12:23:31.415791  iDelay=200, Bit 2, Center 127 (72 ~ 183) 112

 8100 12:23:31.419527  iDelay=200, Bit 3, Center 127 (72 ~ 183) 112

 8101 12:23:31.422503  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 8102 12:23:31.428732  iDelay=200, Bit 5, Center 123 (64 ~ 183) 120

 8103 12:23:31.432408  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8104 12:23:31.435651  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8105 12:23:31.439192  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 8106 12:23:31.445705  iDelay=200, Bit 9, Center 115 (56 ~ 175) 120

 8107 12:23:31.448736  iDelay=200, Bit 10, Center 131 (72 ~ 191) 120

 8108 12:23:31.452400  iDelay=200, Bit 11, Center 123 (64 ~ 183) 120

 8109 12:23:31.455518  iDelay=200, Bit 12, Center 131 (72 ~ 191) 120

 8110 12:23:31.458690  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8111 12:23:31.465463  iDelay=200, Bit 14, Center 139 (80 ~ 199) 120

 8112 12:23:31.468211  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8113 12:23:31.468751  ==

 8114 12:23:31.471648  Dram Type= 6, Freq= 0, CH_0, rank 1

 8115 12:23:31.475122  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8116 12:23:31.475585  ==

 8117 12:23:31.478228  DQS Delay:

 8118 12:23:31.478794  DQS0 = 0, DQS1 = 0

 8119 12:23:31.481677  DQM Delay:

 8120 12:23:31.482140  DQM0 = 133, DQM1 = 128

 8121 12:23:31.482505  DQ Delay:

 8122 12:23:31.484722  DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127

 8123 12:23:31.491213  DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143

 8124 12:23:31.494594  DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123

 8125 12:23:31.498165  DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135

 8126 12:23:31.498728  

 8127 12:23:31.499097  

 8128 12:23:31.499437  ==

 8129 12:23:31.501277  Dram Type= 6, Freq= 0, CH_0, rank 1

 8130 12:23:31.504652  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8131 12:23:31.505119  ==

 8132 12:23:31.505491  

 8133 12:23:31.505838  

 8134 12:23:31.507669  	TX Vref Scan disable

 8135 12:23:31.511143   == TX Byte 0 ==

 8136 12:23:31.514173  Update DQ  dly =994 (3 ,6, 34)  DQ  OEN =(3 ,3)

 8137 12:23:31.517950  Update DQM dly =994 (3 ,6, 34)  DQM OEN =(3 ,3)

 8138 12:23:31.520720   == TX Byte 1 ==

 8139 12:23:31.524259  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8140 12:23:31.527435  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8141 12:23:31.528031  ==

 8142 12:23:31.530894  Dram Type= 6, Freq= 0, CH_0, rank 1

 8143 12:23:31.537457  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8144 12:23:31.537927  ==

 8145 12:23:31.550490  

 8146 12:23:31.553655  TX Vref early break, caculate TX vref

 8147 12:23:31.557014  TX Vref=16, minBit 0, minWin=23, winSum=379

 8148 12:23:31.560392  TX Vref=18, minBit 4, minWin=23, winSum=389

 8149 12:23:31.563165  TX Vref=20, minBit 3, minWin=23, winSum=393

 8150 12:23:31.566455  TX Vref=22, minBit 1, minWin=24, winSum=400

 8151 12:23:31.569972  TX Vref=24, minBit 1, minWin=24, winSum=410

 8152 12:23:31.576575  TX Vref=26, minBit 4, minWin=24, winSum=414

 8153 12:23:31.579876  TX Vref=28, minBit 4, minWin=24, winSum=412

 8154 12:23:31.583458  TX Vref=30, minBit 0, minWin=24, winSum=405

 8155 12:23:31.586633  TX Vref=32, minBit 0, minWin=24, winSum=393

 8156 12:23:31.589925  TX Vref=34, minBit 2, minWin=23, winSum=391

 8157 12:23:31.596507  [TxChooseVref] Worse bit 4, Min win 24, Win sum 414, Final Vref 26

 8158 12:23:31.596940  

 8159 12:23:31.599770  Final TX Range 0 Vref 26

 8160 12:23:31.600205  

 8161 12:23:31.600536  ==

 8162 12:23:31.603299  Dram Type= 6, Freq= 0, CH_0, rank 1

 8163 12:23:31.606388  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8164 12:23:31.606808  ==

 8165 12:23:31.607307  

 8166 12:23:31.607863  

 8167 12:23:31.609645  	TX Vref Scan disable

 8168 12:23:31.616263  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps

 8169 12:23:31.616697   == TX Byte 0 ==

 8170 12:23:31.619294  u2DelayCellOfst[0]=14 cells (4 PI)

 8171 12:23:31.622795  u2DelayCellOfst[1]=14 cells (4 PI)

 8172 12:23:31.625973  u2DelayCellOfst[2]=11 cells (3 PI)

 8173 12:23:31.629138  u2DelayCellOfst[3]=11 cells (3 PI)

 8174 12:23:31.632479  u2DelayCellOfst[4]=7 cells (2 PI)

 8175 12:23:31.635623  u2DelayCellOfst[5]=0 cells (0 PI)

 8176 12:23:31.638906  u2DelayCellOfst[6]=14 cells (4 PI)

 8177 12:23:31.642588  u2DelayCellOfst[7]=14 cells (4 PI)

 8178 12:23:31.645678  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 8179 12:23:31.648844  Update DQM dly =994 (3 ,6, 34)  DQM OEN =(3 ,3)

 8180 12:23:31.652663   == TX Byte 1 ==

 8181 12:23:31.656123  u2DelayCellOfst[8]=0 cells (0 PI)

 8182 12:23:31.659402  u2DelayCellOfst[9]=0 cells (0 PI)

 8183 12:23:31.662526  u2DelayCellOfst[10]=7 cells (2 PI)

 8184 12:23:31.662970  u2DelayCellOfst[11]=0 cells (0 PI)

 8185 12:23:31.665685  u2DelayCellOfst[12]=11 cells (3 PI)

 8186 12:23:31.668998  u2DelayCellOfst[13]=11 cells (3 PI)

 8187 12:23:31.671975  u2DelayCellOfst[14]=14 cells (4 PI)

 8188 12:23:31.675464  u2DelayCellOfst[15]=11 cells (3 PI)

 8189 12:23:31.682589  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8190 12:23:31.685566  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8191 12:23:31.685981  DramC Write-DBI on

 8192 12:23:31.688369  ==

 8193 12:23:31.691790  Dram Type= 6, Freq= 0, CH_0, rank 1

 8194 12:23:31.695355  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8195 12:23:31.695979  ==

 8196 12:23:31.696351  

 8197 12:23:31.696673  

 8198 12:23:31.698574  	TX Vref Scan disable

 8199 12:23:31.699239   == TX Byte 0 ==

 8200 12:23:31.705091  Update DQM dly =738 (2 ,6, 34)  DQM OEN =(3 ,3)

 8201 12:23:31.705510   == TX Byte 1 ==

 8202 12:23:31.708646  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8203 12:23:31.711790  DramC Write-DBI off

 8204 12:23:31.712408  

 8205 12:23:31.712832  [DATLAT]

 8206 12:23:31.715226  Freq=1600, CH0 RK1

 8207 12:23:31.715638  

 8208 12:23:31.716049  DATLAT Default: 0xf

 8209 12:23:31.718616  0, 0xFFFF, sum = 0

 8210 12:23:31.721787  1, 0xFFFF, sum = 0

 8211 12:23:31.722330  2, 0xFFFF, sum = 0

 8212 12:23:31.724776  3, 0xFFFF, sum = 0

 8213 12:23:31.725232  4, 0xFFFF, sum = 0

 8214 12:23:31.728257  5, 0xFFFF, sum = 0

 8215 12:23:31.728676  6, 0xFFFF, sum = 0

 8216 12:23:31.731449  7, 0xFFFF, sum = 0

 8217 12:23:31.732051  8, 0xFFFF, sum = 0

 8218 12:23:31.734645  9, 0xFFFF, sum = 0

 8219 12:23:31.735069  10, 0xFFFF, sum = 0

 8220 12:23:31.737626  11, 0xFFFF, sum = 0

 8221 12:23:31.738043  12, 0xFFFF, sum = 0

 8222 12:23:31.741000  13, 0xFFFF, sum = 0

 8223 12:23:31.741418  14, 0x0, sum = 1

 8224 12:23:31.744261  15, 0x0, sum = 2

 8225 12:23:31.744742  16, 0x0, sum = 3

 8226 12:23:31.748099  17, 0x0, sum = 4

 8227 12:23:31.748547  best_step = 15

 8228 12:23:31.748879  

 8229 12:23:31.749184  ==

 8230 12:23:31.750673  Dram Type= 6, Freq= 0, CH_0, rank 1

 8231 12:23:31.757492  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8232 12:23:31.757926  ==

 8233 12:23:31.758413  RX Vref Scan: 0

 8234 12:23:31.758955  

 8235 12:23:31.760523  RX Vref 0 -> 0, step: 1

 8236 12:23:31.761082  

 8237 12:23:31.764272  RX Delay 11 -> 252, step: 4

 8238 12:23:31.767429  iDelay=195, Bit 0, Center 126 (75 ~ 178) 104

 8239 12:23:31.770647  iDelay=195, Bit 1, Center 134 (79 ~ 190) 112

 8240 12:23:31.777192  iDelay=195, Bit 2, Center 124 (71 ~ 178) 108

 8241 12:23:31.780197  iDelay=195, Bit 3, Center 126 (75 ~ 178) 104

 8242 12:23:31.783877  iDelay=195, Bit 4, Center 132 (79 ~ 186) 108

 8243 12:23:31.787035  iDelay=195, Bit 5, Center 120 (67 ~ 174) 108

 8244 12:23:31.790501  iDelay=195, Bit 6, Center 136 (83 ~ 190) 108

 8245 12:23:31.796927  iDelay=195, Bit 7, Center 140 (87 ~ 194) 108

 8246 12:23:31.800453  iDelay=195, Bit 8, Center 114 (59 ~ 170) 112

 8247 12:23:31.803871  iDelay=195, Bit 9, Center 112 (59 ~ 166) 108

 8248 12:23:31.806826  iDelay=195, Bit 10, Center 126 (71 ~ 182) 112

 8249 12:23:31.809824  iDelay=195, Bit 11, Center 120 (67 ~ 174) 108

 8250 12:23:31.816708  iDelay=195, Bit 12, Center 132 (79 ~ 186) 108

 8251 12:23:31.820323  iDelay=195, Bit 13, Center 132 (79 ~ 186) 108

 8252 12:23:31.823614  iDelay=195, Bit 14, Center 136 (83 ~ 190) 108

 8253 12:23:31.826664  iDelay=195, Bit 15, Center 132 (79 ~ 186) 108

 8254 12:23:31.827117  ==

 8255 12:23:31.830052  Dram Type= 6, Freq= 0, CH_0, rank 1

 8256 12:23:31.836671  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8257 12:23:31.837227  ==

 8258 12:23:31.837595  DQS Delay:

 8259 12:23:31.840178  DQS0 = 0, DQS1 = 0

 8260 12:23:31.840759  DQM Delay:

 8261 12:23:31.843021  DQM0 = 129, DQM1 = 125

 8262 12:23:31.843476  DQ Delay:

 8263 12:23:31.846563  DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =126

 8264 12:23:31.849786  DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =140

 8265 12:23:31.853131  DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120

 8266 12:23:31.856247  DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132

 8267 12:23:31.856705  

 8268 12:23:31.857063  

 8269 12:23:31.857397  

 8270 12:23:31.859358  [DramC_TX_OE_Calibration] TA2

 8271 12:23:31.862507  Original DQ_B0 (3 6) =30, OEN = 27

 8272 12:23:31.866036  Original DQ_B1 (3 6) =30, OEN = 27

 8273 12:23:31.869180  24, 0x0, End_B0=24 End_B1=24

 8274 12:23:31.872775  25, 0x0, End_B0=25 End_B1=25

 8275 12:23:31.873223  26, 0x0, End_B0=26 End_B1=26

 8276 12:23:31.876402  27, 0x0, End_B0=27 End_B1=27

 8277 12:23:31.879584  28, 0x0, End_B0=28 End_B1=28

 8278 12:23:31.882405  29, 0x0, End_B0=29 End_B1=29

 8279 12:23:31.885748  30, 0x0, End_B0=30 End_B1=30

 8280 12:23:31.886166  31, 0x4141, End_B0=30 End_B1=30

 8281 12:23:31.889124  Byte0 end_step=30  best_step=27

 8282 12:23:31.892416  Byte1 end_step=30  best_step=27

 8283 12:23:31.895795  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8284 12:23:31.899346  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8285 12:23:31.899916  

 8286 12:23:31.900253  

 8287 12:23:31.905935  [DQSOSCAuto] RK1, (LSB)MR18= 0x1d00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 395 ps

 8288 12:23:31.908944  CH0 RK1: MR19=303, MR18=1D00

 8289 12:23:31.915553  CH0_RK1: MR19=0x303, MR18=0x1D00, DQSOSC=395, MR23=63, INC=23, DEC=15

 8290 12:23:31.919257  [RxdqsGatingPostProcess] freq 1600

 8291 12:23:31.925137  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8292 12:23:31.928731  best DQS0 dly(2T, 0.5T) = (1, 1)

 8293 12:23:31.929172  best DQS1 dly(2T, 0.5T) = (1, 1)

 8294 12:23:31.932091  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8295 12:23:31.935386  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8296 12:23:31.938663  best DQS0 dly(2T, 0.5T) = (1, 1)

 8297 12:23:31.941998  best DQS1 dly(2T, 0.5T) = (1, 1)

 8298 12:23:31.945326  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8299 12:23:31.948726  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8300 12:23:31.952429  Pre-setting of DQS Precalculation

 8301 12:23:31.955418  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8302 12:23:31.958714  ==

 8303 12:23:31.962064  Dram Type= 6, Freq= 0, CH_1, rank 0

 8304 12:23:31.965422  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8305 12:23:31.965966  ==

 8306 12:23:31.968311  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8307 12:23:31.975101  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8308 12:23:31.978118  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8309 12:23:31.984905  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8310 12:23:31.993003  [CA 0] Center 41 (12~71) winsize 60

 8311 12:23:31.996227  [CA 1] Center 42 (12~72) winsize 61

 8312 12:23:31.999835  [CA 2] Center 37 (8~66) winsize 59

 8313 12:23:32.002973  [CA 3] Center 35 (6~65) winsize 60

 8314 12:23:32.006700  [CA 4] Center 36 (7~66) winsize 60

 8315 12:23:32.009520  [CA 5] Center 36 (7~66) winsize 60

 8316 12:23:32.009972  

 8317 12:23:32.012775  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8318 12:23:32.013222  

 8319 12:23:32.019570  [CATrainingPosCal] consider 1 rank data

 8320 12:23:32.020201  u2DelayCellTimex100 = 262/100 ps

 8321 12:23:32.025745  CA0 delay=41 (12~71),Diff = 6 PI (22 cell)

 8322 12:23:32.029581  CA1 delay=42 (12~72),Diff = 7 PI (26 cell)

 8323 12:23:32.032706  CA2 delay=37 (8~66),Diff = 2 PI (7 cell)

 8324 12:23:32.036429  CA3 delay=35 (6~65),Diff = 0 PI (0 cell)

 8325 12:23:32.039459  CA4 delay=36 (7~66),Diff = 1 PI (3 cell)

 8326 12:23:32.042928  CA5 delay=36 (7~66),Diff = 1 PI (3 cell)

 8327 12:23:32.043477  

 8328 12:23:32.045998  CA PerBit enable=1, Macro0, CA PI delay=35

 8329 12:23:32.046448  

 8330 12:23:32.049871  [CBTSetCACLKResult] CA Dly = 35

 8331 12:23:32.052673  CS Dly: 9 (0~40)

 8332 12:23:32.056188  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8333 12:23:32.059077  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8334 12:23:32.059623  ==

 8335 12:23:32.062489  Dram Type= 6, Freq= 0, CH_1, rank 1

 8336 12:23:32.068701  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8337 12:23:32.069333  ==

 8338 12:23:32.071996  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8339 12:23:32.078993  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8340 12:23:32.082134  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8341 12:23:32.088281  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8342 12:23:32.096665  [CA 0] Center 42 (12~72) winsize 61

 8343 12:23:32.099834  [CA 1] Center 42 (13~72) winsize 60

 8344 12:23:32.102905  [CA 2] Center 37 (8~67) winsize 60

 8345 12:23:32.106493  [CA 3] Center 36 (7~66) winsize 60

 8346 12:23:32.109189  [CA 4] Center 37 (7~67) winsize 61

 8347 12:23:32.112777  [CA 5] Center 37 (7~67) winsize 61

 8348 12:23:32.113237  

 8349 12:23:32.116221  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8350 12:23:32.116819  

 8351 12:23:32.122453  [CATrainingPosCal] consider 2 rank data

 8352 12:23:32.123009  u2DelayCellTimex100 = 262/100 ps

 8353 12:23:32.129058  CA0 delay=41 (12~71),Diff = 5 PI (18 cell)

 8354 12:23:32.132116  CA1 delay=42 (13~72),Diff = 6 PI (22 cell)

 8355 12:23:32.135666  CA2 delay=37 (8~66),Diff = 1 PI (3 cell)

 8356 12:23:32.139135  CA3 delay=36 (7~65),Diff = 0 PI (0 cell)

 8357 12:23:32.142479  CA4 delay=36 (7~66),Diff = 0 PI (0 cell)

 8358 12:23:32.145582  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8359 12:23:32.146037  

 8360 12:23:32.149107  CA PerBit enable=1, Macro0, CA PI delay=36

 8361 12:23:32.149559  

 8362 12:23:32.151684  [CBTSetCACLKResult] CA Dly = 36

 8363 12:23:32.155281  CS Dly: 11 (0~44)

 8364 12:23:32.158755  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8365 12:23:32.161788  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8366 12:23:32.162242  

 8367 12:23:32.165426  ----->DramcWriteLeveling(PI) begin...

 8368 12:23:32.168454  ==

 8369 12:23:32.168961  Dram Type= 6, Freq= 0, CH_1, rank 0

 8370 12:23:32.175535  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8371 12:23:32.176142  ==

 8372 12:23:32.178048  Write leveling (Byte 0): 23 => 23

 8373 12:23:32.181859  Write leveling (Byte 1): 27 => 27

 8374 12:23:32.184871  DramcWriteLeveling(PI) end<-----

 8375 12:23:32.185323  

 8376 12:23:32.185683  ==

 8377 12:23:32.187935  Dram Type= 6, Freq= 0, CH_1, rank 0

 8378 12:23:32.191608  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8379 12:23:32.192337  ==

 8380 12:23:32.194413  [Gating] SW mode calibration

 8381 12:23:32.201083  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8382 12:23:32.207714  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8383 12:23:32.210931   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8384 12:23:32.214248   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8385 12:23:32.220924   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8386 12:23:32.224245   1  4 12 | B1->B0 | 2c2c 3333 | 1 1 | (0 0) (1 1)

 8387 12:23:32.227213   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8388 12:23:32.233829   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8389 12:23:32.236961   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8390 12:23:32.240631   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8391 12:23:32.247301   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8392 12:23:32.250663   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8393 12:23:32.253400   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 8394 12:23:32.260197   1  5 12 | B1->B0 | 3030 2626 | 0 0 | (1 0) (0 0)

 8395 12:23:32.263852   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8396 12:23:32.267342   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8397 12:23:32.273319   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8398 12:23:32.277371   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8399 12:23:32.279891   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8400 12:23:32.286532   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8401 12:23:32.289783   1  6  8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 8402 12:23:32.293101   1  6 12 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)

 8403 12:23:32.300073   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8404 12:23:32.302800   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8405 12:23:32.306244   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8406 12:23:32.313010   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8407 12:23:32.316305   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8408 12:23:32.319783   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8409 12:23:32.326776   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8410 12:23:32.330146   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8411 12:23:32.332598   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8412 12:23:32.339426   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8413 12:23:32.342608   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8414 12:23:32.346039   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8415 12:23:32.352872   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8416 12:23:32.355893   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8417 12:23:32.359249   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8418 12:23:32.366009   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8419 12:23:32.368871   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8420 12:23:32.372222   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8421 12:23:32.378831   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8422 12:23:32.382378   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8423 12:23:32.385618   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8424 12:23:32.392315   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8425 12:23:32.395852   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8426 12:23:32.399134   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8427 12:23:32.408234   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8428 12:23:32.408713  Total UI for P1: 0, mck2ui 16

 8429 12:23:32.412094  best dqsien dly found for B0: ( 1,  9, 10)

 8430 12:23:32.415244   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8431 12:23:32.418542  Total UI for P1: 0, mck2ui 16

 8432 12:23:32.422218  best dqsien dly found for B1: ( 1,  9, 14)

 8433 12:23:32.425158  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8434 12:23:32.429151  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8435 12:23:32.429579  

 8436 12:23:32.432084  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8437 12:23:32.435356  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8438 12:23:32.439046  [Gating] SW calibration Done

 8439 12:23:32.439573  ==

 8440 12:23:32.441947  Dram Type= 6, Freq= 0, CH_1, rank 0

 8441 12:23:32.448324  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8442 12:23:32.448743  ==

 8443 12:23:32.449076  RX Vref Scan: 0

 8444 12:23:32.449384  

 8445 12:23:32.451603  RX Vref 0 -> 0, step: 1

 8446 12:23:32.452058  

 8447 12:23:32.455096  RX Delay 0 -> 252, step: 8

 8448 12:23:32.458258  iDelay=208, Bit 0, Center 143 (88 ~ 199) 112

 8449 12:23:32.461740  iDelay=208, Bit 1, Center 131 (80 ~ 183) 104

 8450 12:23:32.464764  iDelay=208, Bit 2, Center 127 (72 ~ 183) 112

 8451 12:23:32.468309  iDelay=208, Bit 3, Center 139 (88 ~ 191) 104

 8452 12:23:32.474841  iDelay=208, Bit 4, Center 135 (80 ~ 191) 112

 8453 12:23:32.477710  iDelay=208, Bit 5, Center 151 (96 ~ 207) 112

 8454 12:23:32.481115  iDelay=208, Bit 6, Center 147 (96 ~ 199) 104

 8455 12:23:32.484563  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8456 12:23:32.487845  iDelay=208, Bit 8, Center 119 (64 ~ 175) 112

 8457 12:23:32.494417  iDelay=208, Bit 9, Center 119 (64 ~ 175) 112

 8458 12:23:32.497818  iDelay=208, Bit 10, Center 131 (80 ~ 183) 104

 8459 12:23:32.501197  iDelay=208, Bit 11, Center 123 (72 ~ 175) 104

 8460 12:23:32.504477  iDelay=208, Bit 12, Center 135 (80 ~ 191) 112

 8461 12:23:32.510929  iDelay=208, Bit 13, Center 139 (80 ~ 199) 120

 8462 12:23:32.514138  iDelay=208, Bit 14, Center 139 (80 ~ 199) 120

 8463 12:23:32.517403  iDelay=208, Bit 15, Center 139 (88 ~ 191) 104

 8464 12:23:32.517822  ==

 8465 12:23:32.520782  Dram Type= 6, Freq= 0, CH_1, rank 0

 8466 12:23:32.523820  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8467 12:23:32.524266  ==

 8468 12:23:32.527796  DQS Delay:

 8469 12:23:32.528248  DQS0 = 0, DQS1 = 0

 8470 12:23:32.530537  DQM Delay:

 8471 12:23:32.531009  DQM0 = 138, DQM1 = 130

 8472 12:23:32.533779  DQ Delay:

 8473 12:23:32.537407  DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139

 8474 12:23:32.540631  DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135

 8475 12:23:32.544110  DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123

 8476 12:23:32.547424  DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139

 8477 12:23:32.547863  

 8478 12:23:32.548194  

 8479 12:23:32.548504  ==

 8480 12:23:32.550833  Dram Type= 6, Freq= 0, CH_1, rank 0

 8481 12:23:32.554237  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8482 12:23:32.554799  ==

 8483 12:23:32.555165  

 8484 12:23:32.555497  

 8485 12:23:32.557203  	TX Vref Scan disable

 8486 12:23:32.560534   == TX Byte 0 ==

 8487 12:23:32.563977  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8488 12:23:32.567107  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8489 12:23:32.570605   == TX Byte 1 ==

 8490 12:23:32.573802  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8491 12:23:32.577134  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8492 12:23:32.577594  ==

 8493 12:23:32.580451  Dram Type= 6, Freq= 0, CH_1, rank 0

 8494 12:23:32.587238  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8495 12:23:32.587850  ==

 8496 12:23:32.598883  

 8497 12:23:32.602270  TX Vref early break, caculate TX vref

 8498 12:23:32.605067  TX Vref=16, minBit 0, minWin=21, winSum=371

 8499 12:23:32.608872  TX Vref=18, minBit 0, minWin=22, winSum=380

 8500 12:23:32.612132  TX Vref=20, minBit 5, minWin=22, winSum=390

 8501 12:23:32.615134  TX Vref=22, minBit 0, minWin=23, winSum=400

 8502 12:23:32.618626  TX Vref=24, minBit 0, minWin=24, winSum=408

 8503 12:23:32.625134  TX Vref=26, minBit 0, minWin=25, winSum=416

 8504 12:23:32.628117  TX Vref=28, minBit 5, minWin=24, winSum=414

 8505 12:23:32.631866  TX Vref=30, minBit 1, minWin=24, winSum=411

 8506 12:23:32.634637  TX Vref=32, minBit 0, minWin=23, winSum=401

 8507 12:23:32.638260  TX Vref=34, minBit 0, minWin=23, winSum=394

 8508 12:23:32.644610  [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26

 8509 12:23:32.645151  

 8510 12:23:32.648391  Final TX Range 0 Vref 26

 8511 12:23:32.648844  

 8512 12:23:32.649200  ==

 8513 12:23:32.651430  Dram Type= 6, Freq= 0, CH_1, rank 0

 8514 12:23:32.655045  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8515 12:23:32.655624  ==

 8516 12:23:32.656072  

 8517 12:23:32.656414  

 8518 12:23:32.658016  	TX Vref Scan disable

 8519 12:23:32.664453  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps

 8520 12:23:32.665081   == TX Byte 0 ==

 8521 12:23:32.667989  u2DelayCellOfst[0]=18 cells (5 PI)

 8522 12:23:32.671070  u2DelayCellOfst[1]=14 cells (4 PI)

 8523 12:23:32.674187  u2DelayCellOfst[2]=0 cells (0 PI)

 8524 12:23:32.677876  u2DelayCellOfst[3]=7 cells (2 PI)

 8525 12:23:32.681284  u2DelayCellOfst[4]=11 cells (3 PI)

 8526 12:23:32.684233  u2DelayCellOfst[5]=22 cells (6 PI)

 8527 12:23:32.687814  u2DelayCellOfst[6]=22 cells (6 PI)

 8528 12:23:32.691382  u2DelayCellOfst[7]=7 cells (2 PI)

 8529 12:23:32.694332  Update DQ  dly =976 (3 ,6, 16)  DQ  OEN =(3 ,3)

 8530 12:23:32.697643  Update DQM dly =979 (3 ,6, 19)  DQM OEN =(3 ,3)

 8531 12:23:32.701136   == TX Byte 1 ==

 8532 12:23:32.704064  u2DelayCellOfst[8]=0 cells (0 PI)

 8533 12:23:32.707162  u2DelayCellOfst[9]=3 cells (1 PI)

 8534 12:23:32.710552  u2DelayCellOfst[10]=11 cells (3 PI)

 8535 12:23:32.711118  u2DelayCellOfst[11]=3 cells (1 PI)

 8536 12:23:32.713797  u2DelayCellOfst[12]=14 cells (4 PI)

 8537 12:23:32.717054  u2DelayCellOfst[13]=14 cells (4 PI)

 8538 12:23:32.720283  u2DelayCellOfst[14]=18 cells (5 PI)

 8539 12:23:32.724116  u2DelayCellOfst[15]=18 cells (5 PI)

 8540 12:23:32.730613  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8541 12:23:32.733313  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8542 12:23:32.733792  DramC Write-DBI on

 8543 12:23:32.737093  ==

 8544 12:23:32.740310  Dram Type= 6, Freq= 0, CH_1, rank 0

 8545 12:23:32.743951  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8546 12:23:32.744504  ==

 8547 12:23:32.744873  

 8548 12:23:32.745211  

 8549 12:23:32.746861  	TX Vref Scan disable

 8550 12:23:32.747322   == TX Byte 0 ==

 8551 12:23:32.753512  Update DQM dly =720 (2 ,6, 16)  DQM OEN =(3 ,3)

 8552 12:23:32.754076   == TX Byte 1 ==

 8553 12:23:32.756858  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8554 12:23:32.759904  DramC Write-DBI off

 8555 12:23:32.760369  

 8556 12:23:32.760930  [DATLAT]

 8557 12:23:32.763865  Freq=1600, CH1 RK0

 8558 12:23:32.764425  

 8559 12:23:32.764797  DATLAT Default: 0xf

 8560 12:23:32.766463  0, 0xFFFF, sum = 0

 8561 12:23:32.766932  1, 0xFFFF, sum = 0

 8562 12:23:32.769975  2, 0xFFFF, sum = 0

 8563 12:23:32.770551  3, 0xFFFF, sum = 0

 8564 12:23:32.772718  4, 0xFFFF, sum = 0

 8565 12:23:32.776078  5, 0xFFFF, sum = 0

 8566 12:23:32.776544  6, 0xFFFF, sum = 0

 8567 12:23:32.779807  7, 0xFFFF, sum = 0

 8568 12:23:32.780380  8, 0xFFFF, sum = 0

 8569 12:23:32.782709  9, 0xFFFF, sum = 0

 8570 12:23:32.783176  10, 0xFFFF, sum = 0

 8571 12:23:32.786228  11, 0xFFFF, sum = 0

 8572 12:23:32.786694  12, 0xFFFF, sum = 0

 8573 12:23:32.789436  13, 0xFFFF, sum = 0

 8574 12:23:32.789906  14, 0x0, sum = 1

 8575 12:23:32.792888  15, 0x0, sum = 2

 8576 12:23:32.793344  16, 0x0, sum = 3

 8577 12:23:32.796111  17, 0x0, sum = 4

 8578 12:23:32.796549  best_step = 15

 8579 12:23:32.796886  

 8580 12:23:32.797195  ==

 8581 12:23:32.799326  Dram Type= 6, Freq= 0, CH_1, rank 0

 8582 12:23:32.802327  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8583 12:23:32.806392  ==

 8584 12:23:32.806808  RX Vref Scan: 1

 8585 12:23:32.807141  

 8586 12:23:32.808913  Set Vref Range= 24 -> 127

 8587 12:23:32.809331  

 8588 12:23:32.812389  RX Vref 24 -> 127, step: 1

 8589 12:23:32.812826  

 8590 12:23:32.813157  RX Delay 19 -> 252, step: 4

 8591 12:23:32.813467  

 8592 12:23:32.815620  Set Vref, RX VrefLevel [Byte0]: 24

 8593 12:23:32.818955                           [Byte1]: 24

 8594 12:23:32.822943  

 8595 12:23:32.823361  Set Vref, RX VrefLevel [Byte0]: 25

 8596 12:23:32.826441                           [Byte1]: 25

 8597 12:23:32.830549  

 8598 12:23:32.830967  Set Vref, RX VrefLevel [Byte0]: 26

 8599 12:23:32.834175                           [Byte1]: 26

 8600 12:23:32.838067  

 8601 12:23:32.838483  Set Vref, RX VrefLevel [Byte0]: 27

 8602 12:23:32.841476                           [Byte1]: 27

 8603 12:23:32.846242  

 8604 12:23:32.846769  Set Vref, RX VrefLevel [Byte0]: 28

 8605 12:23:32.849379                           [Byte1]: 28

 8606 12:23:32.853008  

 8607 12:23:32.853423  Set Vref, RX VrefLevel [Byte0]: 29

 8608 12:23:32.856247                           [Byte1]: 29

 8609 12:23:32.860584  

 8610 12:23:32.861200  Set Vref, RX VrefLevel [Byte0]: 30

 8611 12:23:32.864010                           [Byte1]: 30

 8612 12:23:32.868275  

 8613 12:23:32.868695  Set Vref, RX VrefLevel [Byte0]: 31

 8614 12:23:32.871676                           [Byte1]: 31

 8615 12:23:32.876085  

 8616 12:23:32.876749  Set Vref, RX VrefLevel [Byte0]: 32

 8617 12:23:32.879757                           [Byte1]: 32

 8618 12:23:32.883771  

 8619 12:23:32.884195  Set Vref, RX VrefLevel [Byte0]: 33

 8620 12:23:32.886827                           [Byte1]: 33

 8621 12:23:32.891099  

 8622 12:23:32.891664  Set Vref, RX VrefLevel [Byte0]: 34

 8623 12:23:32.894687                           [Byte1]: 34

 8624 12:23:32.898827  

 8625 12:23:32.899388  Set Vref, RX VrefLevel [Byte0]: 35

 8626 12:23:32.902275                           [Byte1]: 35

 8627 12:23:32.906423  

 8628 12:23:32.906989  Set Vref, RX VrefLevel [Byte0]: 36

 8629 12:23:32.909396                           [Byte1]: 36

 8630 12:23:32.913634  

 8631 12:23:32.914125  Set Vref, RX VrefLevel [Byte0]: 37

 8632 12:23:32.917156                           [Byte1]: 37

 8633 12:23:32.921507  

 8634 12:23:32.921967  Set Vref, RX VrefLevel [Byte0]: 38

 8635 12:23:32.924628                           [Byte1]: 38

 8636 12:23:32.929277  

 8637 12:23:32.929842  Set Vref, RX VrefLevel [Byte0]: 39

 8638 12:23:32.932422                           [Byte1]: 39

 8639 12:23:32.936741  

 8640 12:23:32.937201  Set Vref, RX VrefLevel [Byte0]: 40

 8641 12:23:32.939971                           [Byte1]: 40

 8642 12:23:32.944240  

 8643 12:23:32.944668  Set Vref, RX VrefLevel [Byte0]: 41

 8644 12:23:32.947442                           [Byte1]: 41

 8645 12:23:32.951846  

 8646 12:23:32.952267  Set Vref, RX VrefLevel [Byte0]: 42

 8647 12:23:32.954965                           [Byte1]: 42

 8648 12:23:32.959516  

 8649 12:23:32.960293  Set Vref, RX VrefLevel [Byte0]: 43

 8650 12:23:32.962770                           [Byte1]: 43

 8651 12:23:32.967204  

 8652 12:23:32.967817  Set Vref, RX VrefLevel [Byte0]: 44

 8653 12:23:32.970123                           [Byte1]: 44

 8654 12:23:32.974635  

 8655 12:23:32.975199  Set Vref, RX VrefLevel [Byte0]: 45

 8656 12:23:32.977535                           [Byte1]: 45

 8657 12:23:32.982368  

 8658 12:23:32.982935  Set Vref, RX VrefLevel [Byte0]: 46

 8659 12:23:32.985456                           [Byte1]: 46

 8660 12:23:32.989389  

 8661 12:23:32.992846  Set Vref, RX VrefLevel [Byte0]: 47

 8662 12:23:32.995927                           [Byte1]: 47

 8663 12:23:32.996387  

 8664 12:23:32.999440  Set Vref, RX VrefLevel [Byte0]: 48

 8665 12:23:33.002898                           [Byte1]: 48

 8666 12:23:33.003454  

 8667 12:23:33.005804  Set Vref, RX VrefLevel [Byte0]: 49

 8668 12:23:33.009184                           [Byte1]: 49

 8669 12:23:33.009748  

 8670 12:23:33.012602  Set Vref, RX VrefLevel [Byte0]: 50

 8671 12:23:33.015453                           [Byte1]: 50

 8672 12:23:33.020054  

 8673 12:23:33.020472  Set Vref, RX VrefLevel [Byte0]: 51

 8674 12:23:33.023065                           [Byte1]: 51

 8675 12:23:33.027403  

 8676 12:23:33.028003  Set Vref, RX VrefLevel [Byte0]: 52

 8677 12:23:33.031062                           [Byte1]: 52

 8678 12:23:33.035104  

 8679 12:23:33.035654  Set Vref, RX VrefLevel [Byte0]: 53

 8680 12:23:33.038471                           [Byte1]: 53

 8681 12:23:33.042756  

 8682 12:23:33.043335  Set Vref, RX VrefLevel [Byte0]: 54

 8683 12:23:33.045636                           [Byte1]: 54

 8684 12:23:33.050029  

 8685 12:23:33.050645  Set Vref, RX VrefLevel [Byte0]: 55

 8686 12:23:33.053479                           [Byte1]: 55

 8687 12:23:33.058104  

 8688 12:23:33.058662  Set Vref, RX VrefLevel [Byte0]: 56

 8689 12:23:33.061160                           [Byte1]: 56

 8690 12:23:33.065363  

 8691 12:23:33.065817  Set Vref, RX VrefLevel [Byte0]: 57

 8692 12:23:33.068891                           [Byte1]: 57

 8693 12:23:33.073090  

 8694 12:23:33.073589  Set Vref, RX VrefLevel [Byte0]: 58

 8695 12:23:33.076000                           [Byte1]: 58

 8696 12:23:33.080771  

 8697 12:23:33.081326  Set Vref, RX VrefLevel [Byte0]: 59

 8698 12:23:33.084292                           [Byte1]: 59

 8699 12:23:33.087709  

 8700 12:23:33.088349  Set Vref, RX VrefLevel [Byte0]: 60

 8701 12:23:33.091427                           [Byte1]: 60

 8702 12:23:33.095714  

 8703 12:23:33.096235  Set Vref, RX VrefLevel [Byte0]: 61

 8704 12:23:33.098746                           [Byte1]: 61

 8705 12:23:33.103276  

 8706 12:23:33.103869  Set Vref, RX VrefLevel [Byte0]: 62

 8707 12:23:33.106515                           [Byte1]: 62

 8708 12:23:33.110710  

 8709 12:23:33.111278  Set Vref, RX VrefLevel [Byte0]: 63

 8710 12:23:33.113833                           [Byte1]: 63

 8711 12:23:33.118295  

 8712 12:23:33.118749  Set Vref, RX VrefLevel [Byte0]: 64

 8713 12:23:33.124542                           [Byte1]: 64

 8714 12:23:33.125000  

 8715 12:23:33.127877  Set Vref, RX VrefLevel [Byte0]: 65

 8716 12:23:33.131137                           [Byte1]: 65

 8717 12:23:33.131601  

 8718 12:23:33.134465  Set Vref, RX VrefLevel [Byte0]: 66

 8719 12:23:33.138286                           [Byte1]: 66

 8720 12:23:33.141207  

 8721 12:23:33.141673  Set Vref, RX VrefLevel [Byte0]: 67

 8722 12:23:33.144037                           [Byte1]: 67

 8723 12:23:33.148479  

 8724 12:23:33.149028  Set Vref, RX VrefLevel [Byte0]: 68

 8725 12:23:33.152165                           [Byte1]: 68

 8726 12:23:33.156049  

 8727 12:23:33.156507  Set Vref, RX VrefLevel [Byte0]: 69

 8728 12:23:33.159646                           [Byte1]: 69

 8729 12:23:33.163987  

 8730 12:23:33.164447  Set Vref, RX VrefLevel [Byte0]: 70

 8731 12:23:33.167048                           [Byte1]: 70

 8732 12:23:33.171210  

 8733 12:23:33.171629  Set Vref, RX VrefLevel [Byte0]: 71

 8734 12:23:33.174935                           [Byte1]: 71

 8735 12:23:33.178506  

 8736 12:23:33.178952  Final RX Vref Byte 0 = 57 to rank0

 8737 12:23:33.182184  Final RX Vref Byte 1 = 58 to rank0

 8738 12:23:33.185613  Final RX Vref Byte 0 = 57 to rank1

 8739 12:23:33.188792  Final RX Vref Byte 1 = 58 to rank1==

 8740 12:23:33.192026  Dram Type= 6, Freq= 0, CH_1, rank 0

 8741 12:23:33.198645  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8742 12:23:33.199137  ==

 8743 12:23:33.199613  DQS Delay:

 8744 12:23:33.202112  DQS0 = 0, DQS1 = 0

 8745 12:23:33.202581  DQM Delay:

 8746 12:23:33.202928  DQM0 = 134, DQM1 = 128

 8747 12:23:33.205412  DQ Delay:

 8748 12:23:33.208921  DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =130

 8749 12:23:33.211553  DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130

 8750 12:23:33.215179  DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =118

 8751 12:23:33.218397  DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138

 8752 12:23:33.218953  

 8753 12:23:33.219288  

 8754 12:23:33.219593  

 8755 12:23:33.222226  [DramC_TX_OE_Calibration] TA2

 8756 12:23:33.224784  Original DQ_B0 (3 6) =30, OEN = 27

 8757 12:23:33.228138  Original DQ_B1 (3 6) =30, OEN = 27

 8758 12:23:33.231605  24, 0x0, End_B0=24 End_B1=24

 8759 12:23:33.234886  25, 0x0, End_B0=25 End_B1=25

 8760 12:23:33.235464  26, 0x0, End_B0=26 End_B1=26

 8761 12:23:33.238014  27, 0x0, End_B0=27 End_B1=27

 8762 12:23:33.241968  28, 0x0, End_B0=28 End_B1=28

 8763 12:23:33.245077  29, 0x0, End_B0=29 End_B1=29

 8764 12:23:33.245643  30, 0x0, End_B0=30 End_B1=30

 8765 12:23:33.247706  31, 0x4141, End_B0=30 End_B1=30

 8766 12:23:33.251024  Byte0 end_step=30  best_step=27

 8767 12:23:33.254531  Byte1 end_step=30  best_step=27

 8768 12:23:33.257861  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8769 12:23:33.261661  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8770 12:23:33.262105  

 8771 12:23:33.262433  

 8772 12:23:33.267372  [DQSOSCAuto] RK0, (LSB)MR18= 0x170e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 398 ps

 8773 12:23:33.270854  CH1 RK0: MR19=303, MR18=170E

 8774 12:23:33.277825  CH1_RK0: MR19=0x303, MR18=0x170E, DQSOSC=398, MR23=63, INC=23, DEC=15

 8775 12:23:33.278248  

 8776 12:23:33.280705  ----->DramcWriteLeveling(PI) begin...

 8777 12:23:33.281126  ==

 8778 12:23:33.284117  Dram Type= 6, Freq= 0, CH_1, rank 1

 8779 12:23:33.287530  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8780 12:23:33.288045  ==

 8781 12:23:33.290435  Write leveling (Byte 0): 24 => 24

 8782 12:23:33.293747  Write leveling (Byte 1): 26 => 26

 8783 12:23:33.297489  DramcWriteLeveling(PI) end<-----

 8784 12:23:33.297908  

 8785 12:23:33.298241  ==

 8786 12:23:33.300568  Dram Type= 6, Freq= 0, CH_1, rank 1

 8787 12:23:33.307225  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8788 12:23:33.307643  ==

 8789 12:23:33.308062  [Gating] SW mode calibration

 8790 12:23:33.317062  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8791 12:23:33.320353  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8792 12:23:33.323693   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8793 12:23:33.330374   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8794 12:23:33.333788   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8795 12:23:33.337123   1  4 12 | B1->B0 | 3434 2423 | 1 1 | (1 1) (0 0)

 8796 12:23:33.343959   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8797 12:23:33.346853   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8798 12:23:33.350396   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8799 12:23:33.356796   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8800 12:23:33.360144   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8801 12:23:33.363627   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 8802 12:23:33.370205   1  5  8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 8803 12:23:33.373430   1  5 12 | B1->B0 | 2b2b 3434 | 0 1 | (1 0) (1 0)

 8804 12:23:33.376712   1  5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)

 8805 12:23:33.383354   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8806 12:23:33.386790   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8807 12:23:33.389901   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8808 12:23:33.396002   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8809 12:23:33.399636   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8810 12:23:33.402915   1  6  8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)

 8811 12:23:33.409731   1  6 12 | B1->B0 | 4646 2626 | 0 1 | (0 0) (0 0)

 8812 12:23:33.412681   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8813 12:23:33.416342   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8814 12:23:33.422531   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8815 12:23:33.425676   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8816 12:23:33.429140   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8817 12:23:33.435697   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8818 12:23:33.438944   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8819 12:23:33.445693   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8820 12:23:33.448522   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8821 12:23:33.452060   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8822 12:23:33.458782   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8823 12:23:33.461955   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8824 12:23:33.465546   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8825 12:23:33.471921   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8826 12:23:33.475238   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8827 12:23:33.478110   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8828 12:23:33.485197   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8829 12:23:33.488239   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8830 12:23:33.491771   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8831 12:23:33.498225   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8832 12:23:33.501551   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8833 12:23:33.504939   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8834 12:23:33.511316   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8835 12:23:33.514639   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8836 12:23:33.517571  Total UI for P1: 0, mck2ui 16

 8837 12:23:33.521061  best dqsien dly found for B1: ( 1,  9,  8)

 8838 12:23:33.524201   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8839 12:23:33.527241  Total UI for P1: 0, mck2ui 16

 8840 12:23:33.530985  best dqsien dly found for B0: ( 1,  9, 12)

 8841 12:23:33.534178  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8842 12:23:33.537296  best DQS1 dly(MCK, UI, PI) = (1, 9, 8)

 8843 12:23:33.537718  

 8844 12:23:33.543929  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8845 12:23:33.547316  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)

 8846 12:23:33.551129  [Gating] SW calibration Done

 8847 12:23:33.551690  ==

 8848 12:23:33.553793  Dram Type= 6, Freq= 0, CH_1, rank 1

 8849 12:23:33.557099  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8850 12:23:33.557522  ==

 8851 12:23:33.557975  RX Vref Scan: 0

 8852 12:23:33.558351  

 8853 12:23:33.560356  RX Vref 0 -> 0, step: 1

 8854 12:23:33.560870  

 8855 12:23:33.563815  RX Delay 0 -> 252, step: 8

 8856 12:23:33.567218  iDelay=208, Bit 0, Center 139 (80 ~ 199) 120

 8857 12:23:33.570384  iDelay=208, Bit 1, Center 131 (72 ~ 191) 120

 8858 12:23:33.576681  iDelay=208, Bit 2, Center 123 (64 ~ 183) 120

 8859 12:23:33.580456  iDelay=208, Bit 3, Center 135 (80 ~ 191) 112

 8860 12:23:33.583437  iDelay=208, Bit 4, Center 131 (72 ~ 191) 120

 8861 12:23:33.586775  iDelay=208, Bit 5, Center 147 (88 ~ 207) 120

 8862 12:23:33.590219  iDelay=208, Bit 6, Center 147 (88 ~ 207) 120

 8863 12:23:33.593540  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8864 12:23:33.600193  iDelay=208, Bit 8, Center 115 (56 ~ 175) 120

 8865 12:23:33.603783  iDelay=208, Bit 9, Center 115 (56 ~ 175) 120

 8866 12:23:33.606730  iDelay=208, Bit 10, Center 131 (72 ~ 191) 120

 8867 12:23:33.610459  iDelay=208, Bit 11, Center 123 (64 ~ 183) 120

 8868 12:23:33.616748  iDelay=208, Bit 12, Center 139 (80 ~ 199) 120

 8869 12:23:33.620163  iDelay=208, Bit 13, Center 139 (80 ~ 199) 120

 8870 12:23:33.623308  iDelay=208, Bit 14, Center 135 (80 ~ 191) 112

 8871 12:23:33.626566  iDelay=208, Bit 15, Center 139 (80 ~ 199) 120

 8872 12:23:33.626978  ==

 8873 12:23:33.629851  Dram Type= 6, Freq= 0, CH_1, rank 1

 8874 12:23:33.636801  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8875 12:23:33.637527  ==

 8876 12:23:33.638043  DQS Delay:

 8877 12:23:33.638376  DQS0 = 0, DQS1 = 0

 8878 12:23:33.640225  DQM Delay:

 8879 12:23:33.640887  DQM0 = 136, DQM1 = 129

 8880 12:23:33.643049  DQ Delay:

 8881 12:23:33.646636  DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135

 8882 12:23:33.649958  DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135

 8883 12:23:33.652937  DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123

 8884 12:23:33.656222  DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139

 8885 12:23:33.656684  

 8886 12:23:33.657044  

 8887 12:23:33.657449  ==

 8888 12:23:33.659690  Dram Type= 6, Freq= 0, CH_1, rank 1

 8889 12:23:33.666402  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8890 12:23:33.666862  ==

 8891 12:23:33.667222  

 8892 12:23:33.667526  

 8893 12:23:33.667882  	TX Vref Scan disable

 8894 12:23:33.669719   == TX Byte 0 ==

 8895 12:23:33.672839  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8896 12:23:33.676046  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8897 12:23:33.679749   == TX Byte 1 ==

 8898 12:23:33.682804  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8899 12:23:33.689421  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8900 12:23:33.689933  ==

 8901 12:23:33.692437  Dram Type= 6, Freq= 0, CH_1, rank 1

 8902 12:23:33.695953  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8903 12:23:33.696422  ==

 8904 12:23:33.708719  

 8905 12:23:33.712148  TX Vref early break, caculate TX vref

 8906 12:23:33.714658  TX Vref=16, minBit 1, minWin=22, winSum=384

 8907 12:23:33.717848  TX Vref=18, minBit 0, minWin=23, winSum=394

 8908 12:23:33.721490  TX Vref=20, minBit 1, minWin=24, winSum=402

 8909 12:23:33.724402  TX Vref=22, minBit 0, minWin=24, winSum=408

 8910 12:23:33.727928  TX Vref=24, minBit 5, minWin=25, winSum=422

 8911 12:23:33.734342  TX Vref=26, minBit 0, minWin=24, winSum=424

 8912 12:23:33.738240  TX Vref=28, minBit 1, minWin=25, winSum=421

 8913 12:23:33.741604  TX Vref=30, minBit 0, minWin=25, winSum=418

 8914 12:23:33.744431  TX Vref=32, minBit 0, minWin=24, winSum=410

 8915 12:23:33.747921  TX Vref=34, minBit 0, minWin=23, winSum=398

 8916 12:23:33.754243  [TxChooseVref] Worse bit 5, Min win 25, Win sum 422, Final Vref 24

 8917 12:23:33.754792  

 8918 12:23:33.757532  Final TX Range 0 Vref 24

 8919 12:23:33.757995  

 8920 12:23:33.758358  ==

 8921 12:23:33.760956  Dram Type= 6, Freq= 0, CH_1, rank 1

 8922 12:23:33.764177  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8923 12:23:33.764703  ==

 8924 12:23:33.765199  

 8925 12:23:33.765813  

 8926 12:23:33.767177  	TX Vref Scan disable

 8927 12:23:33.773946  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps

 8928 12:23:33.774488   == TX Byte 0 ==

 8929 12:23:33.777308  u2DelayCellOfst[0]=18 cells (5 PI)

 8930 12:23:33.780391  u2DelayCellOfst[1]=14 cells (4 PI)

 8931 12:23:33.784209  u2DelayCellOfst[2]=0 cells (0 PI)

 8932 12:23:33.787255  u2DelayCellOfst[3]=7 cells (2 PI)

 8933 12:23:33.790981  u2DelayCellOfst[4]=7 cells (2 PI)

 8934 12:23:33.793739  u2DelayCellOfst[5]=22 cells (6 PI)

 8935 12:23:33.797060  u2DelayCellOfst[6]=18 cells (5 PI)

 8936 12:23:33.800329  u2DelayCellOfst[7]=3 cells (1 PI)

 8937 12:23:33.803637  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8938 12:23:33.807854  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8939 12:23:33.810337   == TX Byte 1 ==

 8940 12:23:33.813862  u2DelayCellOfst[8]=0 cells (0 PI)

 8941 12:23:33.817096  u2DelayCellOfst[9]=3 cells (1 PI)

 8942 12:23:33.820530  u2DelayCellOfst[10]=11 cells (3 PI)

 8943 12:23:33.821084  u2DelayCellOfst[11]=7 cells (2 PI)

 8944 12:23:33.823964  u2DelayCellOfst[12]=18 cells (5 PI)

 8945 12:23:33.826713  u2DelayCellOfst[13]=18 cells (5 PI)

 8946 12:23:33.830294  u2DelayCellOfst[14]=18 cells (5 PI)

 8947 12:23:33.833313  u2DelayCellOfst[15]=18 cells (5 PI)

 8948 12:23:33.840400  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8949 12:23:33.843496  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8950 12:23:33.844009  DramC Write-DBI on

 8951 12:23:33.844500  ==

 8952 12:23:33.846834  Dram Type= 6, Freq= 0, CH_1, rank 1

 8953 12:23:33.853230  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8954 12:23:33.853773  ==

 8955 12:23:33.854136  

 8956 12:23:33.854495  

 8957 12:23:33.856684  	TX Vref Scan disable

 8958 12:23:33.857140   == TX Byte 0 ==

 8959 12:23:33.863076  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8960 12:23:33.863644   == TX Byte 1 ==

 8961 12:23:33.866258  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8962 12:23:33.869902  DramC Write-DBI off

 8963 12:23:33.870361  

 8964 12:23:33.870716  [DATLAT]

 8965 12:23:33.872696  Freq=1600, CH1 RK1

 8966 12:23:33.873155  

 8967 12:23:33.873516  DATLAT Default: 0xf

 8968 12:23:33.876745  0, 0xFFFF, sum = 0

 8969 12:23:33.877305  1, 0xFFFF, sum = 0

 8970 12:23:33.879538  2, 0xFFFF, sum = 0

 8971 12:23:33.880047  3, 0xFFFF, sum = 0

 8972 12:23:33.882989  4, 0xFFFF, sum = 0

 8973 12:23:33.883476  5, 0xFFFF, sum = 0

 8974 12:23:33.886316  6, 0xFFFF, sum = 0

 8975 12:23:33.886782  7, 0xFFFF, sum = 0

 8976 12:23:33.889844  8, 0xFFFF, sum = 0

 8977 12:23:33.890617  9, 0xFFFF, sum = 0

 8978 12:23:33.892663  10, 0xFFFF, sum = 0

 8979 12:23:33.896404  11, 0xFFFF, sum = 0

 8980 12:23:33.896875  12, 0xFFFF, sum = 0

 8981 12:23:33.899710  13, 0xFFFF, sum = 0

 8982 12:23:33.900225  14, 0x0, sum = 1

 8983 12:23:33.903675  15, 0x0, sum = 2

 8984 12:23:33.904208  16, 0x0, sum = 3

 8985 12:23:33.906221  17, 0x0, sum = 4

 8986 12:23:33.906684  best_step = 15

 8987 12:23:33.907049  

 8988 12:23:33.907387  ==

 8989 12:23:33.909456  Dram Type= 6, Freq= 0, CH_1, rank 1

 8990 12:23:33.912526  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8991 12:23:33.912948  ==

 8992 12:23:33.915945  RX Vref Scan: 0

 8993 12:23:33.916365  

 8994 12:23:33.919298  RX Vref 0 -> 0, step: 1

 8995 12:23:33.919716  

 8996 12:23:33.920125  RX Delay 11 -> 252, step: 4

 8997 12:23:33.926330  iDelay=199, Bit 0, Center 140 (87 ~ 194) 108

 8998 12:23:33.929630  iDelay=199, Bit 1, Center 128 (75 ~ 182) 108

 8999 12:23:33.932906  iDelay=199, Bit 2, Center 122 (67 ~ 178) 112

 9000 12:23:33.936054  iDelay=199, Bit 3, Center 130 (79 ~ 182) 104

 9001 12:23:33.942935  iDelay=199, Bit 4, Center 134 (79 ~ 190) 112

 9002 12:23:33.946176  iDelay=199, Bit 5, Center 144 (91 ~ 198) 108

 9003 12:23:33.949502  iDelay=199, Bit 6, Center 144 (91 ~ 198) 108

 9004 12:23:33.952898  iDelay=199, Bit 7, Center 130 (79 ~ 182) 104

 9005 12:23:33.956108  iDelay=199, Bit 8, Center 112 (55 ~ 170) 116

 9006 12:23:33.962845  iDelay=199, Bit 9, Center 116 (63 ~ 170) 108

 9007 12:23:33.965781  iDelay=199, Bit 10, Center 126 (71 ~ 182) 112

 9008 12:23:33.969438  iDelay=199, Bit 11, Center 118 (67 ~ 170) 104

 9009 12:23:33.972690  iDelay=199, Bit 12, Center 138 (83 ~ 194) 112

 9010 12:23:33.975671  iDelay=199, Bit 13, Center 136 (83 ~ 190) 108

 9011 12:23:33.982690  iDelay=199, Bit 14, Center 134 (79 ~ 190) 112

 9012 12:23:33.986051  iDelay=199, Bit 15, Center 138 (83 ~ 194) 112

 9013 12:23:33.986470  ==

 9014 12:23:33.989709  Dram Type= 6, Freq= 0, CH_1, rank 1

 9015 12:23:33.992429  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9016 12:23:33.992853  ==

 9017 12:23:33.995775  DQS Delay:

 9018 12:23:33.996291  DQS0 = 0, DQS1 = 0

 9019 12:23:33.996623  DQM Delay:

 9020 12:23:33.998732  DQM0 = 134, DQM1 = 127

 9021 12:23:33.999141  DQ Delay:

 9022 12:23:34.002656  DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130

 9023 12:23:34.005694  DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =130

 9024 12:23:34.012296  DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118

 9025 12:23:34.015589  DQ12 =138, DQ13 =136, DQ14 =134, DQ15 =138

 9026 12:23:34.016051  

 9027 12:23:34.016385  

 9028 12:23:34.016692  

 9029 12:23:34.018722  [DramC_TX_OE_Calibration] TA2

 9030 12:23:34.022021  Original DQ_B0 (3 6) =30, OEN = 27

 9031 12:23:34.025572  Original DQ_B1 (3 6) =30, OEN = 27

 9032 12:23:34.025986  24, 0x0, End_B0=24 End_B1=24

 9033 12:23:34.029031  25, 0x0, End_B0=25 End_B1=25

 9034 12:23:34.032130  26, 0x0, End_B0=26 End_B1=26

 9035 12:23:34.035328  27, 0x0, End_B0=27 End_B1=27

 9036 12:23:34.035965  28, 0x0, End_B0=28 End_B1=28

 9037 12:23:34.038554  29, 0x0, End_B0=29 End_B1=29

 9038 12:23:34.041571  30, 0x0, End_B0=30 End_B1=30

 9039 12:23:34.045549  31, 0x4141, End_B0=30 End_B1=30

 9040 12:23:34.048159  Byte0 end_step=30  best_step=27

 9041 12:23:34.051580  Byte1 end_step=30  best_step=27

 9042 12:23:34.052175  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9043 12:23:34.054745  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9044 12:23:34.055361  

 9045 12:23:34.055800  

 9046 12:23:34.064733  [DQSOSCAuto] RK1, (LSB)MR18= 0xa06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps

 9047 12:23:34.068053  CH1 RK1: MR19=303, MR18=A06

 9048 12:23:34.072132  CH1_RK1: MR19=0x303, MR18=0xA06, DQSOSC=404, MR23=63, INC=22, DEC=15

 9049 12:23:34.075056  [RxdqsGatingPostProcess] freq 1600

 9050 12:23:34.081600  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9051 12:23:34.084608  best DQS0 dly(2T, 0.5T) = (1, 1)

 9052 12:23:34.087696  best DQS1 dly(2T, 0.5T) = (1, 1)

 9053 12:23:34.091010  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9054 12:23:34.094493  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9055 12:23:34.097365  best DQS0 dly(2T, 0.5T) = (1, 1)

 9056 12:23:34.101286  best DQS1 dly(2T, 0.5T) = (1, 1)

 9057 12:23:34.104018  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9058 12:23:34.107323  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9059 12:23:34.107932  Pre-setting of DQS Precalculation

 9060 12:23:34.114146  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9061 12:23:34.120462  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9062 12:23:34.127184  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9063 12:23:34.127869  

 9064 12:23:34.130465  

 9065 12:23:34.130931  [Calibration Summary] 3200 Mbps

 9066 12:23:34.133930  CH 0, Rank 0

 9067 12:23:34.134385  SW Impedance     : PASS

 9068 12:23:34.137238  DUTY Scan        : NO K

 9069 12:23:34.140557  ZQ Calibration   : PASS

 9070 12:23:34.140968  Jitter Meter     : NO K

 9071 12:23:34.143706  CBT Training     : PASS

 9072 12:23:34.147344  Write leveling   : PASS

 9073 12:23:34.147930  RX DQS gating    : PASS

 9074 12:23:34.150136  RX DQ/DQS(RDDQC) : PASS

 9075 12:23:34.153497  TX DQ/DQS        : PASS

 9076 12:23:34.153910  RX DATLAT        : PASS

 9077 12:23:34.156461  RX DQ/DQS(Engine): PASS

 9078 12:23:34.160340  TX OE            : PASS

 9079 12:23:34.160757  All Pass.

 9080 12:23:34.161144  

 9081 12:23:34.161475  CH 0, Rank 1

 9082 12:23:34.163662  SW Impedance     : PASS

 9083 12:23:34.166988  DUTY Scan        : NO K

 9084 12:23:34.167396  ZQ Calibration   : PASS

 9085 12:23:34.170465  Jitter Meter     : NO K

 9086 12:23:34.173195  CBT Training     : PASS

 9087 12:23:34.173607  Write leveling   : PASS

 9088 12:23:34.176962  RX DQS gating    : PASS

 9089 12:23:34.180137  RX DQ/DQS(RDDQC) : PASS

 9090 12:23:34.180555  TX DQ/DQS        : PASS

 9091 12:23:34.182988  RX DATLAT        : PASS

 9092 12:23:34.183403  RX DQ/DQS(Engine): PASS

 9093 12:23:34.186522  TX OE            : PASS

 9094 12:23:34.186932  All Pass.

 9095 12:23:34.187290  

 9096 12:23:34.189680  CH 1, Rank 0

 9097 12:23:34.193679  SW Impedance     : PASS

 9098 12:23:34.194191  DUTY Scan        : NO K

 9099 12:23:34.196205  ZQ Calibration   : PASS

 9100 12:23:34.196688  Jitter Meter     : NO K

 9101 12:23:34.199643  CBT Training     : PASS

 9102 12:23:34.203050  Write leveling   : PASS

 9103 12:23:34.203596  RX DQS gating    : PASS

 9104 12:23:34.205983  RX DQ/DQS(RDDQC) : PASS

 9105 12:23:34.209362  TX DQ/DQS        : PASS

 9106 12:23:34.209773  RX DATLAT        : PASS

 9107 12:23:34.213016  RX DQ/DQS(Engine): PASS

 9108 12:23:34.216238  TX OE            : PASS

 9109 12:23:34.216722  All Pass.

 9110 12:23:34.217051  

 9111 12:23:34.217378  CH 1, Rank 1

 9112 12:23:34.219218  SW Impedance     : PASS

 9113 12:23:34.223117  DUTY Scan        : NO K

 9114 12:23:34.223526  ZQ Calibration   : PASS

 9115 12:23:34.226472  Jitter Meter     : NO K

 9116 12:23:34.229119  CBT Training     : PASS

 9117 12:23:34.229572  Write leveling   : PASS

 9118 12:23:34.232384  RX DQS gating    : PASS

 9119 12:23:34.235625  RX DQ/DQS(RDDQC) : PASS

 9120 12:23:34.236106  TX DQ/DQS        : PASS

 9121 12:23:34.239115  RX DATLAT        : PASS

 9122 12:23:34.242308  RX DQ/DQS(Engine): PASS

 9123 12:23:34.242718  TX OE            : PASS

 9124 12:23:34.245887  All Pass.

 9125 12:23:34.246402  

 9126 12:23:34.246731  DramC Write-DBI on

 9127 12:23:34.249585  	PER_BANK_REFRESH: Hybrid Mode

 9128 12:23:34.250116  TX_TRACKING: ON

 9129 12:23:34.259152  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9130 12:23:34.268756  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9131 12:23:34.275796  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9132 12:23:34.278853  [FAST_K] Save calibration result to emmc

 9133 12:23:34.282017  sync common calibartion params.

 9134 12:23:34.282571  sync cbt_mode0:1, 1:1

 9135 12:23:34.285227  dram_init: ddr_geometry: 2

 9136 12:23:34.288338  dram_init: ddr_geometry: 2

 9137 12:23:34.288749  dram_init: ddr_geometry: 2

 9138 12:23:34.291794  0:dram_rank_size:100000000

 9139 12:23:34.295315  1:dram_rank_size:100000000

 9140 12:23:34.301830  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9141 12:23:34.302245  DFS_SHUFFLE_HW_MODE: ON

 9142 12:23:34.305519  dramc_set_vcore_voltage set vcore to 725000

 9143 12:23:34.308418  Read voltage for 1600, 0

 9144 12:23:34.308919  Vio18 = 0

 9145 12:23:34.311989  Vcore = 725000

 9146 12:23:34.312471  Vdram = 0

 9147 12:23:34.312800  Vddq = 0

 9148 12:23:34.314824  Vmddr = 0

 9149 12:23:34.315235  switch to 3200 Mbps bootup

 9150 12:23:34.318390  [DramcRunTimeConfig]

 9151 12:23:34.318907  PHYPLL

 9152 12:23:34.321479  DPM_CONTROL_AFTERK: ON

 9153 12:23:34.321892  PER_BANK_REFRESH: ON

 9154 12:23:34.325321  REFRESH_OVERHEAD_REDUCTION: ON

 9155 12:23:34.328299  CMD_PICG_NEW_MODE: OFF

 9156 12:23:34.328706  XRTWTW_NEW_MODE: ON

 9157 12:23:34.331384  XRTRTR_NEW_MODE: ON

 9158 12:23:34.331833  TX_TRACKING: ON

 9159 12:23:34.334721  RDSEL_TRACKING: OFF

 9160 12:23:34.338405  DQS Precalculation for DVFS: ON

 9161 12:23:34.339126  RX_TRACKING: OFF

 9162 12:23:34.341399  HW_GATING DBG: ON

 9163 12:23:34.341815  ZQCS_ENABLE_LP4: ON

 9164 12:23:34.344340  RX_PICG_NEW_MODE: ON

 9165 12:23:34.344754  TX_PICG_NEW_MODE: ON

 9166 12:23:34.348073  ENABLE_RX_DCM_DPHY: ON

 9167 12:23:34.351799  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9168 12:23:34.354778  DUMMY_READ_FOR_TRACKING: OFF

 9169 12:23:34.357600  !!! SPM_CONTROL_AFTERK: OFF

 9170 12:23:34.358052  !!! SPM could not control APHY

 9171 12:23:34.361099  IMPEDANCE_TRACKING: ON

 9172 12:23:34.361593  TEMP_SENSOR: ON

 9173 12:23:34.364465  HW_SAVE_FOR_SR: OFF

 9174 12:23:34.368170  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9175 12:23:34.371166  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9176 12:23:34.374322  Read ODT Tracking: ON

 9177 12:23:34.374754  Refresh Rate DeBounce: ON

 9178 12:23:34.378609  DFS_NO_QUEUE_FLUSH: ON

 9179 12:23:34.380830  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9180 12:23:34.384242  ENABLE_DFS_RUNTIME_MRW: OFF

 9181 12:23:34.384699  DDR_RESERVE_NEW_MODE: ON

 9182 12:23:34.387603  MR_CBT_SWITCH_FREQ: ON

 9183 12:23:34.390761  =========================

 9184 12:23:34.408558  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9185 12:23:34.412145  dram_init: ddr_geometry: 2

 9186 12:23:34.430120  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9187 12:23:34.433869  dram_init: dram init end (result: 0)

 9188 12:23:34.440201  DRAM-K: Full calibration passed in 24604 msecs

 9189 12:23:34.443513  MRC: failed to locate region type 0.

 9190 12:23:34.443991  DRAM rank0 size:0x100000000,

 9191 12:23:34.446884  DRAM rank1 size=0x100000000

 9192 12:23:34.457132  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9193 12:23:34.463295  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9194 12:23:34.469709  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9195 12:23:34.479609  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9196 12:23:34.480198  DRAM rank0 size:0x100000000,

 9197 12:23:34.483235  DRAM rank1 size=0x100000000

 9198 12:23:34.483837  CBMEM:

 9199 12:23:34.486199  IMD: root @ 0xfffff000 254 entries.

 9200 12:23:34.489586  IMD: root @ 0xffffec00 62 entries.

 9201 12:23:34.492742  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9202 12:23:34.499469  WARNING: RO_VPD is uninitialized or empty.

 9203 12:23:34.502792  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9204 12:23:34.513453  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9205 12:23:34.523008  read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps

 9206 12:23:34.534454  BS: romstage times (exec / console): total (unknown) / 24098 ms

 9207 12:23:34.534753  

 9208 12:23:34.534932  

 9209 12:23:34.543963  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9210 12:23:34.548307  ARM64: Exception handlers installed.

 9211 12:23:34.551628  ARM64: Testing exception

 9212 12:23:34.554292  ARM64: Done test exception

 9213 12:23:34.554613  Enumerating buses...

 9214 12:23:34.557310  Show all devs... Before device enumeration.

 9215 12:23:34.560603  Root Device: enabled 1

 9216 12:23:34.564405  CPU_CLUSTER: 0: enabled 1

 9217 12:23:34.564755  CPU: 00: enabled 1

 9218 12:23:34.567650  Compare with tree...

 9219 12:23:34.568138  Root Device: enabled 1

 9220 12:23:34.571132   CPU_CLUSTER: 0: enabled 1

 9221 12:23:34.574447    CPU: 00: enabled 1

 9222 12:23:34.574998  Root Device scanning...

 9223 12:23:34.577889  scan_static_bus for Root Device

 9224 12:23:34.581234  CPU_CLUSTER: 0 enabled

 9225 12:23:34.583959  scan_static_bus for Root Device done

 9226 12:23:34.587331  scan_bus: bus Root Device finished in 8 msecs

 9227 12:23:34.587916  done

 9228 12:23:34.593802  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9229 12:23:34.597185  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9230 12:23:34.604074  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9231 12:23:34.607425  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9232 12:23:34.610696  Allocating resources...

 9233 12:23:34.613530  Reading resources...

 9234 12:23:34.616979  Root Device read_resources bus 0 link: 0

 9235 12:23:34.620362  DRAM rank0 size:0x100000000,

 9236 12:23:34.620821  DRAM rank1 size=0x100000000

 9237 12:23:34.627019  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9238 12:23:34.627581  CPU: 00 missing read_resources

 9239 12:23:34.633623  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9240 12:23:34.636838  Root Device read_resources bus 0 link: 0 done

 9241 12:23:34.639655  Done reading resources.

 9242 12:23:34.643026  Show resources in subtree (Root Device)...After reading.

 9243 12:23:34.646485   Root Device child on link 0 CPU_CLUSTER: 0

 9244 12:23:34.650464    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9245 12:23:34.659534    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9246 12:23:34.660288     CPU: 00

 9247 12:23:34.666747  Root Device assign_resources, bus 0 link: 0

 9248 12:23:34.669486  CPU_CLUSTER: 0 missing set_resources

 9249 12:23:34.673501  Root Device assign_resources, bus 0 link: 0 done

 9250 12:23:34.674082  Done setting resources.

 9251 12:23:34.679236  Show resources in subtree (Root Device)...After assigning values.

 9252 12:23:34.682962   Root Device child on link 0 CPU_CLUSTER: 0

 9253 12:23:34.689442    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9254 12:23:34.695998    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9255 12:23:34.696459     CPU: 00

 9256 12:23:34.699269  Done allocating resources.

 9257 12:23:34.706271  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9258 12:23:34.706842  Enabling resources...

 9259 12:23:34.709506  done.

 9260 12:23:34.712309  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9261 12:23:34.715635  Initializing devices...

 9262 12:23:34.716255  Root Device init

 9263 12:23:34.718929  init hardware done!

 9264 12:23:34.719378  0x00000018: ctrlr->caps

 9265 12:23:34.722392  52.000 MHz: ctrlr->f_max

 9266 12:23:34.725456  0.400 MHz: ctrlr->f_min

 9267 12:23:34.729022  0x40ff8080: ctrlr->voltages

 9268 12:23:34.729482  sclk: 390625

 9269 12:23:34.729841  Bus Width = 1

 9270 12:23:34.731809  sclk: 390625

 9271 12:23:34.732299  Bus Width = 1

 9272 12:23:34.735027  Early init status = 3

 9273 12:23:34.738360  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9274 12:23:34.742043  in-header: 03 fc 00 00 01 00 00 00 

 9275 12:23:34.745080  in-data: 00 

 9276 12:23:34.748600  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9277 12:23:34.753905  in-header: 03 fd 00 00 00 00 00 00 

 9278 12:23:34.757395  in-data: 

 9279 12:23:34.760440  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9280 12:23:34.764224  in-header: 03 fc 00 00 01 00 00 00 

 9281 12:23:34.767428  in-data: 00 

 9282 12:23:34.770361  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9283 12:23:34.775880  in-header: 03 fd 00 00 00 00 00 00 

 9284 12:23:34.779065  in-data: 

 9285 12:23:34.782410  [SSUSB] Setting up USB HOST controller...

 9286 12:23:34.785435  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9287 12:23:34.788371  [SSUSB] phy power-on done.

 9288 12:23:34.791774  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9289 12:23:34.798536  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9290 12:23:34.802107  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9291 12:23:34.808074  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9292 12:23:34.815141  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9293 12:23:34.821068  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9294 12:23:34.827963  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9295 12:23:34.834326  read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps

 9296 12:23:34.837746  SPM: binary array size = 0x9dc

 9297 12:23:34.840959  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9298 12:23:34.847891  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9299 12:23:34.854401  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9300 12:23:34.860965  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9301 12:23:34.864658  configure_display: Starting display init

 9302 12:23:34.898694  anx7625_power_on_init: Init interface.

 9303 12:23:34.902579  anx7625_disable_pd_protocol: Disabled PD feature.

 9304 12:23:34.905063  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9305 12:23:34.933108  anx7625_start_dp_work: Secure OCM version=00

 9306 12:23:34.936135  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9307 12:23:34.951222  sp_tx_get_edid_block: EDID Block = 1

 9308 12:23:35.053563  Extracted contents:

 9309 12:23:35.057051  header:          00 ff ff ff ff ff ff 00

 9310 12:23:35.060286  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9311 12:23:35.063450  version:         01 04

 9312 12:23:35.066507  basic params:    95 1f 11 78 0a

 9313 12:23:35.070480  chroma info:     76 90 94 55 54 90 27 21 50 54

 9314 12:23:35.073445  established:     00 00 00

 9315 12:23:35.080068  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9316 12:23:35.083981  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9317 12:23:35.089746  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9318 12:23:35.096274  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9319 12:23:35.102765  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9320 12:23:35.106163  extensions:      00

 9321 12:23:35.106724  checksum:        fb

 9322 12:23:35.107061  

 9323 12:23:35.109696  Manufacturer: IVO Model 57d Serial Number 0

 9324 12:23:35.113170  Made week 0 of 2020

 9325 12:23:35.116326  EDID version: 1.4

 9326 12:23:35.116873  Digital display

 9327 12:23:35.119576  6 bits per primary color channel

 9328 12:23:35.120039  DisplayPort interface

 9329 12:23:35.122840  Maximum image size: 31 cm x 17 cm

 9330 12:23:35.126114  Gamma: 220%

 9331 12:23:35.126525  Check DPMS levels

 9332 12:23:35.129524  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9333 12:23:35.136224  First detailed timing is preferred timing

 9334 12:23:35.136758  Established timings supported:

 9335 12:23:35.139125  Standard timings supported:

 9336 12:23:35.142772  Detailed timings

 9337 12:23:35.146119  Hex of detail: 383680a07038204018303c0035ae10000019

 9338 12:23:35.152553  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9339 12:23:35.156227                 0780 0798 07c8 0820 hborder 0

 9340 12:23:35.159198                 0438 043b 0447 0458 vborder 0

 9341 12:23:35.162525                 -hsync -vsync

 9342 12:23:35.163007  Did detailed timing

 9343 12:23:35.169278  Hex of detail: 000000000000000000000000000000000000

 9344 12:23:35.172482  Manufacturer-specified data, tag 0

 9345 12:23:35.175517  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9346 12:23:35.179510  ASCII string: InfoVision

 9347 12:23:35.182645  Hex of detail: 000000fe00523134304e574635205248200a

 9348 12:23:35.185433  ASCII string: R140NWF5 RH 

 9349 12:23:35.185846  Checksum

 9350 12:23:35.188814  Checksum: 0xfb (valid)

 9351 12:23:35.192152  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9352 12:23:35.195291  DSI data_rate: 832800000 bps

 9353 12:23:35.202132  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9354 12:23:35.205331  anx7625_parse_edid: pixelclock(138800).

 9355 12:23:35.208424   hactive(1920), hsync(48), hfp(24), hbp(88)

 9356 12:23:35.212403   vactive(1080), vsync(12), vfp(3), vbp(17)

 9357 12:23:35.215097  anx7625_dsi_config: config dsi.

 9358 12:23:35.221564  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9359 12:23:35.235439  anx7625_dsi_config: success to config DSI

 9360 12:23:35.238666  anx7625_dp_start: MIPI phy setup OK.

 9361 12:23:35.241902  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9362 12:23:35.245436  mtk_ddp_mode_set invalid vrefresh 60

 9363 12:23:35.248587  main_disp_path_setup

 9364 12:23:35.248996  ovl_layer_smi_id_en

 9365 12:23:35.251778  ovl_layer_smi_id_en

 9366 12:23:35.252285  ccorr_config

 9367 12:23:35.252703  aal_config

 9368 12:23:35.255404  gamma_config

 9369 12:23:35.255951  postmask_config

 9370 12:23:35.258414  dither_config

 9371 12:23:35.261919  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9372 12:23:35.268075                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9373 12:23:35.271554  Root Device init finished in 552 msecs

 9374 12:23:35.274692  CPU_CLUSTER: 0 init

 9375 12:23:35.281311  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9376 12:23:35.287983  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9377 12:23:35.288061  APU_MBOX 0x190000b0 = 0x10001

 9378 12:23:35.291162  APU_MBOX 0x190001b0 = 0x10001

 9379 12:23:35.294392  APU_MBOX 0x190005b0 = 0x10001

 9380 12:23:35.298199  APU_MBOX 0x190006b0 = 0x10001

 9381 12:23:35.305011  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9382 12:23:35.314397  read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps

 9383 12:23:35.326756  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9384 12:23:35.332948  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9385 12:23:35.344833  read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps

 9386 12:23:35.353976  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9387 12:23:35.357329  CPU_CLUSTER: 0 init finished in 81 msecs

 9388 12:23:35.360628  Devices initialized

 9389 12:23:35.364096  Show all devs... After init.

 9390 12:23:35.364179  Root Device: enabled 1

 9391 12:23:35.366989  CPU_CLUSTER: 0: enabled 1

 9392 12:23:35.370543  CPU: 00: enabled 1

 9393 12:23:35.373654  BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms

 9394 12:23:35.376747  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9395 12:23:35.380131  ELOG: NV offset 0x57f000 size 0x1000

 9396 12:23:35.387164  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9397 12:23:35.393542  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9398 12:23:35.396945  ELOG: Event(17) added with size 13 at 2023-10-27 12:23:35 UTC

 9399 12:23:35.403687  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9400 12:23:35.406465  in-header: 03 d7 00 00 2c 00 00 00 

 9401 12:23:35.416619  in-data: 88 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9402 12:23:35.423175  ELOG: Event(A1) added with size 10 at 2023-10-27 12:23:35 UTC

 9403 12:23:35.429901  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9404 12:23:35.436456  ELOG: Event(A0) added with size 9 at 2023-10-27 12:23:35 UTC

 9405 12:23:35.439909  elog_add_boot_reason: Logged dev mode boot

 9406 12:23:35.446547  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9407 12:23:35.446661  Finalize devices...

 9408 12:23:35.449633  Devices finalized

 9409 12:23:35.453157  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9410 12:23:35.456904  Writing coreboot table at 0xffe64000

 9411 12:23:35.459780   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9412 12:23:35.466443   1. 0000000040000000-00000000400fffff: RAM

 9413 12:23:35.469834   2. 0000000040100000-000000004032afff: RAMSTAGE

 9414 12:23:35.473023   3. 000000004032b000-00000000545fffff: RAM

 9415 12:23:35.476420   4. 0000000054600000-000000005465ffff: BL31

 9416 12:23:35.479625   5. 0000000054660000-00000000ffe63fff: RAM

 9417 12:23:35.486489   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9418 12:23:35.489472   7. 0000000100000000-000000023fffffff: RAM

 9419 12:23:35.492918  Passing 5 GPIOs to payload:

 9420 12:23:35.496158              NAME |       PORT | POLARITY |     VALUE

 9421 12:23:35.502329          EC in RW | 0x000000aa |      low | undefined

 9422 12:23:35.506123      EC interrupt | 0x00000005 |      low | undefined

 9423 12:23:35.509061     TPM interrupt | 0x000000ab |     high | undefined

 9424 12:23:35.516169    SD card detect | 0x00000011 |     high | undefined

 9425 12:23:35.519120    speaker enable | 0x00000093 |     high | undefined

 9426 12:23:35.522307  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9427 12:23:35.525501  in-header: 03 f9 00 00 02 00 00 00 

 9428 12:23:35.528977  in-data: 02 00 

 9429 12:23:35.532327  ADC[4]: Raw value=904509 ID=7

 9430 12:23:35.532411  ADC[3]: Raw value=214021 ID=1

 9431 12:23:35.535523  RAM Code: 0x71

 9432 12:23:35.538848  ADC[6]: Raw value=75036 ID=0

 9433 12:23:35.538926  ADC[5]: Raw value=212912 ID=1

 9434 12:23:35.542355  SKU Code: 0x1

 9435 12:23:35.548837  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a169

 9436 12:23:35.548910  coreboot table: 964 bytes.

 9437 12:23:35.552135  IMD ROOT    0. 0xfffff000 0x00001000

 9438 12:23:35.555935  IMD SMALL   1. 0xffffe000 0x00001000

 9439 12:23:35.558661  RO MCACHE   2. 0xffffc000 0x00001104

 9440 12:23:35.562473  CONSOLE     3. 0xfff7c000 0x00080000

 9441 12:23:35.565087  FMAP        4. 0xfff7b000 0x00000452

 9442 12:23:35.568720  TIME STAMP  5. 0xfff7a000 0x00000910

 9443 12:23:35.571836  VBOOT WORK  6. 0xfff66000 0x00014000

 9444 12:23:35.575672  RAMOOPS     7. 0xffe66000 0x00100000

 9445 12:23:35.578618  COREBOOT    8. 0xffe64000 0x00002000

 9446 12:23:35.582190  IMD small region:

 9447 12:23:35.585170    IMD ROOT    0. 0xffffec00 0x00000400

 9448 12:23:35.588467    VPD         1. 0xffffeb80 0x0000006c

 9449 12:23:35.592093    MMC STATUS  2. 0xffffeb60 0x00000004

 9450 12:23:35.595333  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9451 12:23:35.598573  Probing TPM:  done!

 9452 12:23:35.601827  Connected to device vid:did:rid of 1ae0:0028:00

 9453 12:23:35.612854  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

 9454 12:23:35.616417  Initialized TPM device CR50 revision 0

 9455 12:23:35.619434  Checking cr50 for pending updates

 9456 12:23:35.623894  Reading cr50 TPM mode

 9457 12:23:35.632364  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9458 12:23:35.638850  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9459 12:23:35.679095  read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps

 9460 12:23:35.682281  Checking segment from ROM address 0x40100000

 9461 12:23:35.685622  Checking segment from ROM address 0x4010001c

 9462 12:23:35.692307  Loading segment from ROM address 0x40100000

 9463 12:23:35.692387    code (compression=0)

 9464 12:23:35.702371    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9465 12:23:35.709155  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9466 12:23:35.709238  it's not compressed!

 9467 12:23:35.715838  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9468 12:23:35.722527  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9469 12:23:35.739263  Loading segment from ROM address 0x4010001c

 9470 12:23:35.739343    Entry Point 0x80000000

 9471 12:23:35.742830  Loaded segments

 9472 12:23:35.746233  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9473 12:23:35.752387  Jumping to boot code at 0x80000000(0xffe64000)

 9474 12:23:35.759548  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9475 12:23:35.766266  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9476 12:23:35.773831  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9477 12:23:35.777001  Checking segment from ROM address 0x40100000

 9478 12:23:35.780354  Checking segment from ROM address 0x4010001c

 9479 12:23:35.787266  Loading segment from ROM address 0x40100000

 9480 12:23:35.787349    code (compression=1)

 9481 12:23:35.793885    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9482 12:23:35.803483  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9483 12:23:35.803563  using LZMA

 9484 12:23:35.811927  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9485 12:23:35.818890  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9486 12:23:35.822204  Loading segment from ROM address 0x4010001c

 9487 12:23:35.822281    Entry Point 0x54601000

 9488 12:23:35.826178  Loaded segments

 9489 12:23:35.828787  NOTICE:  MT8192 bl31_setup

 9490 12:23:35.835596  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9491 12:23:35.839535  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9492 12:23:35.842684  WARNING: region 0:

 9493 12:23:35.845549  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9494 12:23:35.845619  WARNING: region 1:

 9495 12:23:35.852542  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9496 12:23:35.855649  WARNING: region 2:

 9497 12:23:35.859269  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9498 12:23:35.862372  WARNING: region 3:

 9499 12:23:35.865679  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9500 12:23:35.869297  WARNING: region 4:

 9501 12:23:35.875877  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9502 12:23:35.875980  WARNING: region 5:

 9503 12:23:35.879442  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9504 12:23:35.882513  WARNING: region 6:

 9505 12:23:35.886059  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9506 12:23:35.886136  WARNING: region 7:

 9507 12:23:35.892951  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9508 12:23:35.899468  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9509 12:23:35.902334  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9510 12:23:35.905904  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9511 12:23:35.912764  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9512 12:23:35.915864  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9513 12:23:35.919094  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9514 12:23:35.925493  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9515 12:23:35.928784  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9516 12:23:35.935880  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9517 12:23:35.939027  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9518 12:23:35.942179  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9519 12:23:35.948271  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9520 12:23:35.951736  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9521 12:23:35.958324  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9522 12:23:35.961647  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9523 12:23:35.965124  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9524 12:23:35.971834  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9525 12:23:35.975186  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9526 12:23:35.978307  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9527 12:23:35.984834  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9528 12:23:35.988582  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9529 12:23:35.994771  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9530 12:23:35.998305  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9531 12:23:36.001407  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9532 12:23:36.008205  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9533 12:23:36.010964  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9534 12:23:36.018001  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9535 12:23:36.021196  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9536 12:23:36.028059  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9537 12:23:36.031330  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9538 12:23:36.034371  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9539 12:23:36.041069  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9540 12:23:36.044345  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9541 12:23:36.047533  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9542 12:23:36.051057  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9543 12:23:36.057445  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9544 12:23:36.061420  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9545 12:23:36.064762  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9546 12:23:36.067249  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9547 12:23:36.074176  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9548 12:23:36.077675  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9549 12:23:36.080847  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9550 12:23:36.084220  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9551 12:23:36.090537  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9552 12:23:36.093775  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9553 12:23:36.097315  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9554 12:23:36.104231  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9555 12:23:36.107077  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9556 12:23:36.110556  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9557 12:23:36.117646  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9558 12:23:36.120493  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9559 12:23:36.127408  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9560 12:23:36.130276  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9561 12:23:36.137058  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9562 12:23:36.140601  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9563 12:23:36.143755  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9564 12:23:36.150346  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9565 12:23:36.153624  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9566 12:23:36.160368  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9567 12:23:36.163574  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9568 12:23:36.170505  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9569 12:23:36.173861  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9570 12:23:36.180455  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9571 12:23:36.183919  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9572 12:23:36.187068  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9573 12:23:36.193204  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9574 12:23:36.196747  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9575 12:23:36.203370  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9576 12:23:36.206777  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9577 12:23:36.213465  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9578 12:23:36.216822  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9579 12:23:36.219826  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9580 12:23:36.226715  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9581 12:23:36.229812  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9582 12:23:36.236745  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9583 12:23:36.240044  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9584 12:23:36.246542  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9585 12:23:36.249752  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9586 12:23:36.256323  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9587 12:23:36.259451  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9588 12:23:36.266184  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9589 12:23:36.269567  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9590 12:23:36.273020  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9591 12:23:36.279432  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9592 12:23:36.282690  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9593 12:23:36.289475  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9594 12:23:36.292966  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9595 12:23:36.299305  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9596 12:23:36.302647  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9597 12:23:36.305866  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9598 12:23:36.312568  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9599 12:23:36.315973  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9600 12:23:36.322461  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9601 12:23:36.326126  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9602 12:23:36.332206  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9603 12:23:36.335442  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9604 12:23:36.338747  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9605 12:23:36.345745  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9606 12:23:36.348916  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9607 12:23:36.352287  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9608 12:23:36.359039  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9609 12:23:36.362216  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9610 12:23:36.365314  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9611 12:23:36.371907  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9612 12:23:36.375263  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9613 12:23:36.382164  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9614 12:23:36.385490  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9615 12:23:36.388541  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9616 12:23:36.395392  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9617 12:23:36.398335  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9618 12:23:36.405210  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9619 12:23:36.408427  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9620 12:23:36.411866  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9621 12:23:36.418172  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9622 12:23:36.421607  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9623 12:23:36.428079  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9624 12:23:36.432272  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9625 12:23:36.435069  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9626 12:23:36.441182  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9627 12:23:36.445071  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9628 12:23:36.448169  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9629 12:23:36.451608  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9630 12:23:36.457827  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9631 12:23:36.461679  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9632 12:23:36.464346  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9633 12:23:36.471029  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9634 12:23:36.474805  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9635 12:23:36.477796  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9636 12:23:36.484149  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9637 12:23:36.487678  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9638 12:23:36.494478  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9639 12:23:36.497681  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9640 12:23:36.500776  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9641 12:23:36.507388  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9642 12:23:36.510598  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9643 12:23:36.517465  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9644 12:23:36.520648  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9645 12:23:36.523777  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9646 12:23:36.530320  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9647 12:23:36.533704  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9648 12:23:36.540124  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9649 12:23:36.543541  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9650 12:23:36.546734  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9651 12:23:36.553462  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9652 12:23:36.556867  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9653 12:23:36.563446  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9654 12:23:36.566670  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9655 12:23:36.570365  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9656 12:23:36.576518  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9657 12:23:36.580191  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9658 12:23:36.586768  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9659 12:23:36.589958  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9660 12:23:36.593022  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9661 12:23:36.600035  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9662 12:23:36.603387  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9663 12:23:36.610072  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9664 12:23:36.613142  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9665 12:23:36.616728  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9666 12:23:36.623004  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9667 12:23:36.626151  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9668 12:23:36.633218  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9669 12:23:36.636191  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9670 12:23:36.639266  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9671 12:23:36.646317  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9672 12:23:36.649195  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9673 12:23:36.656060  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9674 12:23:36.659044  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9675 12:23:36.662283  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9676 12:23:36.669177  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9677 12:23:36.672449  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9678 12:23:36.679445  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9679 12:23:36.682302  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9680 12:23:36.685792  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9681 12:23:36.692420  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9682 12:23:36.695635  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9683 12:23:36.702336  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9684 12:23:36.705633  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9685 12:23:36.708884  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9686 12:23:36.715636  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9687 12:23:36.718254  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9688 12:23:36.724859  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9689 12:23:36.728207  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9690 12:23:36.732111  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9691 12:23:36.738533  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9692 12:23:36.741346  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9693 12:23:36.748133  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9694 12:23:36.751776  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9695 12:23:36.754936  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9696 12:23:36.761337  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9697 12:23:36.764507  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9698 12:23:36.771222  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9699 12:23:36.774944  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9700 12:23:36.781152  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9701 12:23:36.784326  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9702 12:23:36.787837  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9703 12:23:36.794358  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9704 12:23:36.798016  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9705 12:23:36.803923  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9706 12:23:36.807870  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9707 12:23:36.814438  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9708 12:23:36.817234  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9709 12:23:36.820695  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9710 12:23:36.827159  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9711 12:23:36.830623  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9712 12:23:36.837090  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9713 12:23:36.840378  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9714 12:23:36.847374  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9715 12:23:36.850107  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9716 12:23:36.854519  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9717 12:23:36.860204  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9718 12:23:36.864004  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9719 12:23:36.870409  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9720 12:23:36.873437  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9721 12:23:36.880114  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9722 12:23:36.883492  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9723 12:23:36.886544  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9724 12:23:36.893153  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9725 12:23:36.896456  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9726 12:23:36.903495  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9727 12:23:36.907897  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9728 12:23:36.913460  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9729 12:23:36.916303  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9730 12:23:36.919325  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9731 12:23:36.926049  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9732 12:23:36.929728  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9733 12:23:36.936210  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9734 12:23:36.939479  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9735 12:23:36.942471  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9736 12:23:36.949079  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9737 12:23:36.952248  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9738 12:23:36.956016  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9739 12:23:36.962457  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9740 12:23:36.965418  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9741 12:23:36.969389  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9742 12:23:36.972558  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9743 12:23:36.979175  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9744 12:23:36.982120  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9745 12:23:36.988889  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9746 12:23:36.991929  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9747 12:23:36.995488  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9748 12:23:37.002358  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9749 12:23:37.005555  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9750 12:23:37.008913  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9751 12:23:37.015811  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9752 12:23:37.018725  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9753 12:23:37.022288  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9754 12:23:37.029151  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9755 12:23:37.031860  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9756 12:23:37.035634  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9757 12:23:37.041877  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9758 12:23:37.045014  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9759 12:23:37.052302  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9760 12:23:37.055234  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9761 12:23:37.058763  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9762 12:23:37.065071  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9763 12:23:37.068088  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9764 12:23:37.074911  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9765 12:23:37.078347  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9766 12:23:37.081213  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9767 12:23:37.087845  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9768 12:23:37.091179  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9769 12:23:37.098102  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9770 12:23:37.101023  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9771 12:23:37.104144  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9772 12:23:37.111141  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9773 12:23:37.114217  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9774 12:23:37.117667  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9775 12:23:37.124038  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9776 12:23:37.127190  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9777 12:23:37.131102  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9778 12:23:37.137289  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9779 12:23:37.140565  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9780 12:23:37.143878  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9781 12:23:37.147133  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9782 12:23:37.150308  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9783 12:23:37.156940  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9784 12:23:37.160181  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9785 12:23:37.163615  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9786 12:23:37.170213  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9787 12:23:37.173459  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9788 12:23:37.176812  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9789 12:23:37.180326  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9790 12:23:37.186848  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9791 12:23:37.189787  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9792 12:23:37.196543  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9793 12:23:37.200171  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9794 12:23:37.206695  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9795 12:23:37.209721  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9796 12:23:37.212937  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9797 12:23:37.219492  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9798 12:23:37.222753  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9799 12:23:37.229684  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9800 12:23:37.233090  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9801 12:23:37.236504  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9802 12:23:37.242573  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9803 12:23:37.245796  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9804 12:23:37.252719  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9805 12:23:37.255924  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9806 12:23:37.262699  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9807 12:23:37.265727  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9808 12:23:37.268795  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9809 12:23:37.275943  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9810 12:23:37.279017  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9811 12:23:37.286297  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9812 12:23:37.289043  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9813 12:23:37.292857  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9814 12:23:37.299196  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9815 12:23:37.302636  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9816 12:23:37.308968  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9817 12:23:37.312000  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9818 12:23:37.318608  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9819 12:23:37.321901  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9820 12:23:37.325352  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9821 12:23:37.332156  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9822 12:23:37.335457  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9823 12:23:37.341574  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9824 12:23:37.345534  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9825 12:23:37.348414  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9826 12:23:37.354984  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9827 12:23:37.358508  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9828 12:23:37.364820  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9829 12:23:37.368341  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9830 12:23:37.371467  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9831 12:23:37.378284  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9832 12:23:37.381356  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9833 12:23:37.388169  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9834 12:23:37.391651  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9835 12:23:37.398089  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9836 12:23:37.401484  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9837 12:23:37.404749  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9838 12:23:37.411395  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9839 12:23:37.414375  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9840 12:23:37.420846  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9841 12:23:37.424479  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9842 12:23:37.431288  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9843 12:23:37.434509  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9844 12:23:37.437876  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9845 12:23:37.444070  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9846 12:23:37.447317  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9847 12:23:37.453796  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9848 12:23:37.457369  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9849 12:23:37.460993  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9850 12:23:37.466935  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9851 12:23:37.470139  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9852 12:23:37.477186  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9853 12:23:37.480553  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9854 12:23:37.484044  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9855 12:23:37.490428  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9856 12:23:37.493416  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9857 12:23:37.500257  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9858 12:23:37.504074  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9859 12:23:37.510298  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9860 12:23:37.513622  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9861 12:23:37.516985  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9862 12:23:37.523284  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9863 12:23:37.526529  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9864 12:23:37.533624  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9865 12:23:37.536834  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9866 12:23:37.543137  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9867 12:23:37.546392  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9868 12:23:37.552901  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9869 12:23:37.556240  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9870 12:23:37.559647  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9871 12:23:37.566290  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9872 12:23:37.569513  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9873 12:23:37.575748  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9874 12:23:37.579003  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9875 12:23:37.585997  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9876 12:23:37.589337  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9877 12:23:37.592405  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9878 12:23:37.599207  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9879 12:23:37.602235  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9880 12:23:37.609170  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9881 12:23:37.612448  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9882 12:23:37.618964  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9883 12:23:37.622412  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9884 12:23:37.629101  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9885 12:23:37.632310  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9886 12:23:37.635293  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9887 12:23:37.642076  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9888 12:23:37.645294  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9889 12:23:37.652034  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9890 12:23:37.655309  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9891 12:23:37.662183  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9892 12:23:37.665269  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9893 12:23:37.671669  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9894 12:23:37.675333  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9895 12:23:37.678252  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9896 12:23:37.685203  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9897 12:23:37.688106  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9898 12:23:37.695204  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9899 12:23:37.698153  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9900 12:23:37.704697  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9901 12:23:37.708193  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9902 12:23:37.714842  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9903 12:23:37.718163  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9904 12:23:37.721502  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9905 12:23:37.728188  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9906 12:23:37.731416  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9907 12:23:37.737935  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9908 12:23:37.741250  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9909 12:23:37.748047  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9910 12:23:37.750871  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9911 12:23:37.754236  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9912 12:23:37.761239  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9913 12:23:37.764286  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9914 12:23:37.771227  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9915 12:23:37.774434  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9916 12:23:37.780694  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9917 12:23:37.784328  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9918 12:23:37.790645  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9919 12:23:37.793838  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9920 12:23:37.800557  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9921 12:23:37.803847  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9922 12:23:37.810994  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9923 12:23:37.814086  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9924 12:23:37.821099  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9925 12:23:37.823978  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9926 12:23:37.830926  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9927 12:23:37.833810  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9928 12:23:37.840168  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9929 12:23:37.843947  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9930 12:23:37.850085  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9931 12:23:37.853266  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9932 12:23:37.860072  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9933 12:23:37.863373  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9934 12:23:37.869900  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9935 12:23:37.873634  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9936 12:23:37.880445  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9937 12:23:37.883526  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9938 12:23:37.890435  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9939 12:23:37.893658  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9940 12:23:37.899782  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9941 12:23:37.903210  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9942 12:23:37.910407  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9943 12:23:37.910985  INFO:    [APUAPC] vio 0

 9944 12:23:37.916392  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9945 12:23:37.919217  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9946 12:23:37.923138  INFO:    [APUAPC] D0_APC_0: 0x400510

 9947 12:23:37.926117  INFO:    [APUAPC] D0_APC_1: 0x0

 9948 12:23:37.929562  INFO:    [APUAPC] D0_APC_2: 0x1540

 9949 12:23:37.932671  INFO:    [APUAPC] D0_APC_3: 0x0

 9950 12:23:37.936121  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9951 12:23:37.939868  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9952 12:23:37.942511  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9953 12:23:37.945735  INFO:    [APUAPC] D1_APC_3: 0x0

 9954 12:23:37.949628  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9955 12:23:37.952574  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9956 12:23:37.955773  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9957 12:23:37.958831  INFO:    [APUAPC] D2_APC_3: 0x0

 9958 12:23:37.962148  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9959 12:23:37.966091  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9960 12:23:37.969252  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9961 12:23:37.972642  INFO:    [APUAPC] D3_APC_3: 0x0

 9962 12:23:37.975661  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9963 12:23:37.979098  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9964 12:23:37.982265  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9965 12:23:37.985728  INFO:    [APUAPC] D4_APC_3: 0x0

 9966 12:23:37.989198  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9967 12:23:37.992263  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9968 12:23:37.995272  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9969 12:23:37.995691  INFO:    [APUAPC] D5_APC_3: 0x0

 9970 12:23:38.002631  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9971 12:23:38.005702  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9972 12:23:38.008761  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9973 12:23:38.009175  INFO:    [APUAPC] D6_APC_3: 0x0

 9974 12:23:38.012056  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9975 12:23:38.015619  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9976 12:23:38.018808  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9977 12:23:38.022183  INFO:    [APUAPC] D7_APC_3: 0x0

 9978 12:23:38.024883  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9979 12:23:38.028745  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9980 12:23:38.031969  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9981 12:23:38.035370  INFO:    [APUAPC] D8_APC_3: 0x0

 9982 12:23:38.038519  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9983 12:23:38.041651  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9984 12:23:38.044685  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9985 12:23:38.048094  INFO:    [APUAPC] D9_APC_3: 0x0

 9986 12:23:38.051658  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9987 12:23:38.055158  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9988 12:23:38.058323  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9989 12:23:38.061688  INFO:    [APUAPC] D10_APC_3: 0x0

 9990 12:23:38.064575  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9991 12:23:38.068356  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9992 12:23:38.071748  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9993 12:23:38.074772  INFO:    [APUAPC] D11_APC_3: 0x0

 9994 12:23:38.078022  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9995 12:23:38.081309  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9996 12:23:38.087638  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9997 12:23:38.088168  INFO:    [APUAPC] D12_APC_3: 0x0

 9998 12:23:38.091114  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9999 12:23:38.097711  INFO:    [APUAPC] D13_APC_1: 0xffffffff

10000 12:23:38.100821  INFO:    [APUAPC] D13_APC_2: 0x3fffff

10001 12:23:38.101279  INFO:    [APUAPC] D13_APC_3: 0x0

10002 12:23:38.107307  INFO:    [APUAPC] D14_APC_0: 0xffffffff

10003 12:23:38.110994  INFO:    [APUAPC] D14_APC_1: 0xffffffff

10004 12:23:38.114503  INFO:    [APUAPC] D14_APC_2: 0x3fffff

10005 12:23:38.117692  INFO:    [APUAPC] D14_APC_3: 0x0

10006 12:23:38.120833  INFO:    [APUAPC] D15_APC_0: 0xffffffff

10007 12:23:38.124029  INFO:    [APUAPC] D15_APC_1: 0xffffffff

10008 12:23:38.127429  INFO:    [APUAPC] D15_APC_2: 0x3fffff

10009 12:23:38.130910  INFO:    [APUAPC] D15_APC_3: 0x0

10010 12:23:38.131478  INFO:    [APUAPC] APC_CON: 0x4

10011 12:23:38.134026  INFO:    [NOCDAPC] D0_APC_0: 0x0

10012 12:23:38.137320  INFO:    [NOCDAPC] D0_APC_1: 0x0

10013 12:23:38.140926  INFO:    [NOCDAPC] D1_APC_0: 0x0

10014 12:23:38.143826  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10015 12:23:38.146859  INFO:    [NOCDAPC] D2_APC_0: 0x0

10016 12:23:38.150245  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10017 12:23:38.153663  INFO:    [NOCDAPC] D3_APC_0: 0x0

10018 12:23:38.157383  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10019 12:23:38.160327  INFO:    [NOCDAPC] D4_APC_0: 0x0

10020 12:23:38.163657  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10021 12:23:38.164116  INFO:    [NOCDAPC] D5_APC_0: 0x0

10022 12:23:38.167279  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10023 12:23:38.170484  INFO:    [NOCDAPC] D6_APC_0: 0x0

10024 12:23:38.173263  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10025 12:23:38.176572  INFO:    [NOCDAPC] D7_APC_0: 0x0

10026 12:23:38.179885  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10027 12:23:38.183216  INFO:    [NOCDAPC] D8_APC_0: 0x0

10028 12:23:38.186646  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10029 12:23:38.189683  INFO:    [NOCDAPC] D9_APC_0: 0x0

10030 12:23:38.192898  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10031 12:23:38.196180  INFO:    [NOCDAPC] D10_APC_0: 0x0

10032 12:23:38.199508  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10033 12:23:38.200003  INFO:    [NOCDAPC] D11_APC_0: 0x0

10034 12:23:38.203057  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10035 12:23:38.206224  INFO:    [NOCDAPC] D12_APC_0: 0x0

10036 12:23:38.209897  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10037 12:23:38.213142  INFO:    [NOCDAPC] D13_APC_0: 0x0

10038 12:23:38.216347  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10039 12:23:38.219675  INFO:    [NOCDAPC] D14_APC_0: 0x0

10040 12:23:38.222715  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10041 12:23:38.226348  INFO:    [NOCDAPC] D15_APC_0: 0x0

10042 12:23:38.229922  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10043 12:23:38.232568  INFO:    [NOCDAPC] APC_CON: 0x4

10044 12:23:38.235713  INFO:    [APUAPC] set_apusys_apc done

10045 12:23:38.239295  INFO:    [DEVAPC] devapc_init done

10046 12:23:38.242681  INFO:    GICv3 without legacy support detected.

10047 12:23:38.246014  INFO:    ARM GICv3 driver initialized in EL3

10048 12:23:38.248986  INFO:    Maximum SPI INTID supported: 639

10049 12:23:38.256101  INFO:    BL31: Initializing runtime services

10050 12:23:38.259347  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10051 12:23:38.262296  INFO:    SPM: enable CPC mode

10052 12:23:38.268838  INFO:    mcdi ready for mcusys-off-idle and system suspend

10053 12:23:38.272446  INFO:    BL31: Preparing for EL3 exit to normal world

10054 12:23:38.275826  INFO:    Entry point address = 0x80000000

10055 12:23:38.279086  INFO:    SPSR = 0x8

10056 12:23:38.284571  

10057 12:23:38.285125  

10058 12:23:38.285486  

10059 12:23:38.287450  Starting depthcharge on Spherion...

10060 12:23:38.287943  

10061 12:23:38.288306  Wipe memory regions:

10062 12:23:38.288639  

10063 12:23:38.291381  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10064 12:23:38.292034  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10065 12:23:38.292492  Setting prompt string to ['asurada:']
10066 12:23:38.292924  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10067 12:23:38.293802  	[0x00000040000000, 0x00000054600000)

10068 12:23:38.413064  

10069 12:23:38.413577  	[0x00000054660000, 0x00000080000000)

10070 12:23:38.674000  

10071 12:23:38.674546  	[0x000000821a7280, 0x000000ffe64000)

10072 12:23:39.418677  

10073 12:23:39.419238  	[0x00000100000000, 0x00000240000000)

10074 12:23:41.308813  

10075 12:23:41.311923  Initializing XHCI USB controller at 0x11200000.

10076 12:23:42.294060  

10077 12:23:42.294612  R8152: Initializing

10078 12:23:42.294978  

10079 12:23:42.296748  Version 9 (ocp_data = 6010)

10080 12:23:42.297205  

10081 12:23:42.300396  R8152: Done initializing

10082 12:23:42.300904  

10083 12:23:42.301280  Adding net device

10084 12:23:42.822694  

10085 12:23:42.825528  [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43

10086 12:23:42.826075  

10087 12:23:42.826443  

10088 12:23:42.826750  

10089 12:23:42.827529  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10091 12:23:42.928972  asurada: tftpboot 192.168.201.1 11893154/tftp-deploy-7d4b6xp8/kernel/image.itb 11893154/tftp-deploy-7d4b6xp8/kernel/cmdline 

10092 12:23:42.929642  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10093 12:23:42.930103  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10094 12:23:42.934845  tftpboot 192.168.201.1 11893154/tftp-deploy-7d4b6xp8/kernel/image.ittp-deploy-7d4b6xp8/kernel/cmdline 

10095 12:23:42.935315  

10096 12:23:42.935828  Waiting for link

10097 12:23:43.137108  

10098 12:23:43.137748  done.

10099 12:23:43.138244  

10100 12:23:43.138706  MAC: f4:f5:e8:50:de:0a

10101 12:23:43.139193  

10102 12:23:43.140785  Sending DHCP discover... done.

10103 12:23:43.141203  

10104 12:23:43.144564  Waiting for reply... done.

10105 12:23:43.145164  

10106 12:23:43.146726  Sending DHCP request... done.

10107 12:23:43.147249  

10108 12:23:43.147711  Waiting for reply... done.

10109 12:23:43.148088  

10110 12:23:43.150216  My ip is 192.168.201.14

10111 12:23:43.150631  

10112 12:23:43.153669  The DHCP server ip is 192.168.201.1

10113 12:23:43.154237  

10114 12:23:43.156843  TFTP server IP predefined by user: 192.168.201.1

10115 12:23:43.157534  

10116 12:23:43.163892  Bootfile predefined by user: 11893154/tftp-deploy-7d4b6xp8/kernel/image.itb

10117 12:23:43.164315  

10118 12:23:43.166970  Sending tftp read request... done.

10119 12:23:43.167389  

10120 12:23:43.175111  Waiting for the transfer... 

10121 12:23:43.175619  

10122 12:23:43.540966  00000000 ################################################################

10123 12:23:43.541655  

10124 12:23:43.858611  00080000 ################################################################

10125 12:23:43.858758  

10126 12:23:44.099345  00100000 ################################################################

10127 12:23:44.099486  

10128 12:23:44.358891  00180000 ################################################################

10129 12:23:44.359042  

10130 12:23:44.614469  00200000 ################################################################

10131 12:23:44.614617  

10132 12:23:44.876549  00280000 ################################################################

10133 12:23:44.876699  

10134 12:23:45.117235  00300000 ################################################################

10135 12:23:45.117438  

10136 12:23:45.367924  00380000 ################################################################

10137 12:23:45.368075  

10138 12:23:45.605168  00400000 ################################################################

10139 12:23:45.605320  

10140 12:23:45.849751  00480000 ################################################################

10141 12:23:45.849883  

10142 12:23:46.122207  00500000 ################################################################

10143 12:23:46.122352  

10144 12:23:46.394193  00580000 ################################################################

10145 12:23:46.394340  

10146 12:23:46.629503  00600000 ################################################################

10147 12:23:46.629649  

10148 12:23:46.869892  00680000 ################################################################

10149 12:23:46.870030  

10150 12:23:47.136807  00700000 ################################################################

10151 12:23:47.136949  

10152 12:23:47.382073  00780000 ################################################################

10153 12:23:47.382219  

10154 12:23:47.629448  00800000 ################################################################

10155 12:23:47.629630  

10156 12:23:47.872107  00880000 ################################################################

10157 12:23:47.872251  

10158 12:23:48.113356  00900000 ################################################################

10159 12:23:48.113515  

10160 12:23:48.371960  00980000 ################################################################

10161 12:23:48.372106  

10162 12:23:48.632085  00a00000 ################################################################

10163 12:23:48.632259  

10164 12:23:48.881798  00a80000 ################################################################

10165 12:23:48.881945  

10166 12:23:49.130780  00b00000 ################################################################

10167 12:23:49.130924  

10168 12:23:49.360464  00b80000 ################################################################

10169 12:23:49.360604  

10170 12:23:49.592037  00c00000 ################################################################

10171 12:23:49.592177  

10172 12:23:49.823431  00c80000 ################################################################

10173 12:23:49.823574  

10174 12:23:50.057437  00d00000 ################################################################

10175 12:23:50.057584  

10176 12:23:50.287129  00d80000 ################################################################

10177 12:23:50.287274  

10178 12:23:50.532232  00e00000 ################################################################

10179 12:23:50.532378  

10180 12:23:50.848170  00e80000 ################################################################

10181 12:23:50.848330  

10182 12:23:51.171958  00f00000 ################################################################

10183 12:23:51.172106  

10184 12:23:51.431293  00f80000 ################################################################

10185 12:23:51.431439  

10186 12:23:51.673425  01000000 ################################################################

10187 12:23:51.673571  

10188 12:23:51.925231  01080000 ################################################################

10189 12:23:51.925373  

10190 12:23:52.170920  01100000 ################################################################

10191 12:23:52.171067  

10192 12:23:52.412637  01180000 ################################################################

10193 12:23:52.412778  

10194 12:23:52.647319  01200000 ################################################################

10195 12:23:52.647468  

10196 12:23:52.890462  01280000 ################################################################

10197 12:23:52.890656  

10198 12:23:53.127221  01300000 ################################################################

10199 12:23:53.127369  

10200 12:23:53.360935  01380000 ################################################################

10201 12:23:53.361077  

10202 12:23:53.605722  01400000 ################################################################

10203 12:23:53.605870  

10204 12:23:53.872057  01480000 ################################################################

10205 12:23:53.872199  

10206 12:23:54.119493  01500000 ################################################################

10207 12:23:54.119637  

10208 12:23:54.349846  01580000 ################################################################

10209 12:23:54.349986  

10210 12:23:54.592312  01600000 ################################################################

10211 12:23:54.592455  

10212 12:23:54.857147  01680000 ################################################################

10213 12:23:54.857292  

10214 12:23:55.104862  01700000 ################################################################

10215 12:23:55.105007  

10216 12:23:55.333901  01780000 ################################################################

10217 12:23:55.334042  

10218 12:23:55.573948  01800000 ################################################################

10219 12:23:55.574095  

10220 12:23:55.875656  01880000 ################################################################

10221 12:23:55.875852  

10222 12:23:56.150050  01900000 ################################################################

10223 12:23:56.150199  

10224 12:23:56.412670  01980000 ################################################################

10225 12:23:56.412817  

10226 12:23:56.650381  01a00000 ################################################################

10227 12:23:56.650552  

10228 12:23:56.898099  01a80000 ################################################################

10229 12:23:56.898263  

10230 12:23:57.148394  01b00000 ################################################################

10231 12:23:57.148531  

10232 12:23:57.412437  01b80000 ################################################################

10233 12:23:57.412585  

10234 12:23:57.698712  01c00000 ################################################################

10235 12:23:57.698872  

10236 12:23:57.975472  01c80000 ################################################################

10237 12:23:57.975616  

10238 12:23:58.230780  01d00000 ################################################################

10239 12:23:58.230950  

10240 12:23:58.463584  01d80000 ################################################################

10241 12:23:58.463757  

10242 12:23:58.714234  01e00000 ################################################################

10243 12:23:58.714371  

10244 12:23:58.947672  01e80000 ################################################################

10245 12:23:58.947854  

10246 12:23:59.176846  01f00000 ################################################################

10247 12:23:59.176983  

10248 12:23:59.421458  01f80000 ################################################################

10249 12:23:59.421620  

10250 12:23:59.664372  02000000 ################################################################

10251 12:23:59.664517  

10252 12:23:59.895491  02080000 ################################################################

10253 12:23:59.895660  

10254 12:24:00.128593  02100000 ################################################################

10255 12:24:00.128734  

10256 12:24:00.374182  02180000 ################################################################

10257 12:24:00.374351  

10258 12:24:00.604970  02200000 ################################################################

10259 12:24:00.605115  

10260 12:24:00.831115  02280000 ################################################################

10261 12:24:00.831261  

10262 12:24:01.058839  02300000 ################################################################

10263 12:24:01.059004  

10264 12:24:01.286301  02380000 ################################################################

10265 12:24:01.286467  

10266 12:24:01.538258  02400000 ################################################################

10267 12:24:01.538425  

10268 12:24:01.770797  02480000 ################################################################

10269 12:24:01.770933  

10270 12:24:02.020662  02500000 ################################################################

10271 12:24:02.020799  

10272 12:24:02.288988  02580000 ################################################################

10273 12:24:02.289134  

10274 12:24:02.526094  02600000 ################################################################

10275 12:24:02.526242  

10276 12:24:02.760609  02680000 ################################################################

10277 12:24:02.760755  

10278 12:24:03.014913  02700000 ################################################################

10279 12:24:03.015058  

10280 12:24:03.248784  02780000 ################################################################

10281 12:24:03.248930  

10282 12:24:03.475393  02800000 ################################################################

10283 12:24:03.475558  

10284 12:24:03.725189  02880000 ################################################################

10285 12:24:03.725362  

10286 12:24:04.030899  02900000 ################################################################

10287 12:24:04.031047  

10288 12:24:04.294872  02980000 ################################################################

10289 12:24:04.295019  

10290 12:24:04.538133  02a00000 ################################################################

10291 12:24:04.538301  

10292 12:24:04.817641  02a80000 ################################################################

10293 12:24:04.817807  

10294 12:24:05.081974  02b00000 ################################################################

10295 12:24:05.082120  

10296 12:24:05.379529  02b80000 ################################################################

10297 12:24:05.379702  

10298 12:24:05.632905  02c00000 ################################################################

10299 12:24:05.633072  

10300 12:24:05.933128  02c80000 ################################################################

10301 12:24:05.933302  

10302 12:24:06.169868  02d00000 ################################################################

10303 12:24:06.170015  

10304 12:24:06.408885  02d80000 ################################################################

10305 12:24:06.409028  

10306 12:24:06.669538  02e00000 ################################################################

10307 12:24:06.669680  

10308 12:24:06.937635  02e80000 ################################################################

10309 12:24:06.937775  

10310 12:24:07.190953  02f00000 ################################################################

10311 12:24:07.191099  

10312 12:24:07.455342  02f80000 ################################################################

10313 12:24:07.455510  

10314 12:24:07.692502  03000000 ################################################################

10315 12:24:07.692671  

10316 12:24:07.933003  03080000 ################################################################

10317 12:24:07.933167  

10318 12:24:08.172820  03100000 ################################################################

10319 12:24:08.172958  

10320 12:24:08.414923  03180000 ################################################################

10321 12:24:08.415095  

10322 12:24:08.666715  03200000 ################################################################

10323 12:24:08.666886  

10324 12:24:08.938935  03280000 ################################################################

10325 12:24:08.939101  

10326 12:24:09.190213  03300000 ################################################################

10327 12:24:09.190381  

10328 12:24:09.455203  03380000 ################################################################

10329 12:24:09.455375  

10330 12:24:09.693818  03400000 ################################################################

10331 12:24:09.693984  

10332 12:24:09.941082  03480000 ################################################################

10333 12:24:09.941257  

10334 12:24:10.165534  03500000 ################################################################

10335 12:24:10.165703  

10336 12:24:10.409925  03580000 ################################################################

10337 12:24:10.410094  

10338 12:24:10.654686  03600000 ################################################################

10339 12:24:10.654856  

10340 12:24:10.908250  03680000 ################################################################

10341 12:24:10.908390  

10342 12:24:11.161479  03700000 ################################################################

10343 12:24:11.161645  

10344 12:24:11.424115  03780000 ################################################################

10345 12:24:11.424260  

10346 12:24:11.667335  03800000 ################################################################

10347 12:24:11.667506  

10348 12:24:11.923786  03880000 ################################################################

10349 12:24:11.923928  

10350 12:24:12.155813  03900000 ################################################################

10351 12:24:12.155953  

10352 12:24:12.387513  03980000 ################################################################

10353 12:24:12.387657  

10354 12:24:12.643613  03a00000 ################################################################

10355 12:24:12.643828  

10356 12:24:12.882001  03a80000 ################################################################

10357 12:24:12.882145  

10358 12:24:13.120699  03b00000 ################################################################

10359 12:24:13.120844  

10360 12:24:13.374931  03b80000 ################################################################

10361 12:24:13.375075  

10362 12:24:13.604643  03c00000 ################################################################

10363 12:24:13.604790  

10364 12:24:13.863186  03c80000 ################################################################

10365 12:24:13.863333  

10366 12:24:14.091082  03d00000 ################################################################

10367 12:24:14.091227  

10368 12:24:14.319404  03d80000 ################################################################

10369 12:24:14.319545  

10370 12:24:14.581117  03e00000 ################################################################

10371 12:24:14.581258  

10372 12:24:14.834631  03e80000 ################################################################

10373 12:24:14.834780  

10374 12:24:15.103808  03f00000 ################################################################

10375 12:24:15.103962  

10376 12:24:15.330767  03f80000 ################################################################

10377 12:24:15.330923  

10378 12:24:15.512411  04000000 ################################################### done.

10379 12:24:15.512547  

10380 12:24:15.515684  The bootfile was 67526238 bytes long.

10381 12:24:15.515806  

10382 12:24:15.519187  Sending tftp read request... done.

10383 12:24:15.519273  

10384 12:24:15.519341  Waiting for the transfer... 

10385 12:24:15.519404  

10386 12:24:15.522505  00000000 # done.

10387 12:24:15.522679  

10388 12:24:15.529282  Command line loaded dynamically from TFTP file: 11893154/tftp-deploy-7d4b6xp8/kernel/cmdline

10389 12:24:15.529385  

10390 12:24:15.542723  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10391 12:24:15.542938  

10392 12:24:15.545624  Loading FIT.

10393 12:24:15.545833  

10394 12:24:15.549288  Image ramdisk-1 has 56428932 bytes.

10395 12:24:15.549439  

10396 12:24:15.552034  Image fdt-1 has 47278 bytes.

10397 12:24:15.552203  

10398 12:24:15.552336  Image kernel-1 has 11047994 bytes.

10399 12:24:15.552460  

10400 12:24:15.562530  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10401 12:24:15.562842  

10402 12:24:15.581788  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10403 12:24:15.582303  

10404 12:24:15.585956  Choosing best match conf-1 for compat google,spherion-rev2.

10405 12:24:15.589926  

10406 12:24:15.594078  Connected to device vid:did:rid of 1ae0:0028:00

10407 12:24:15.601377  

10408 12:24:15.604795  tpm_get_response: command 0x17b, return code 0x0

10409 12:24:15.605208  

10410 12:24:15.607818  ec_init: CrosEC protocol v3 supported (256, 248)

10411 12:24:15.612318  

10412 12:24:15.615087  tpm_cleanup: add release locality here.

10413 12:24:15.615523  

10414 12:24:15.615883  Shutting down all USB controllers.

10415 12:24:15.618548  

10416 12:24:15.618978  Removing current net device

10417 12:24:15.619304  

10418 12:24:15.625287  Exiting depthcharge with code 4 at timestamp: 66738106

10419 12:24:15.625790  

10420 12:24:15.628335  LZMA decompressing kernel-1 to 0x821a6718

10421 12:24:15.628758  

10422 12:24:15.631885  LZMA decompressing kernel-1 to 0x40000000

10423 12:24:17.020931  

10424 12:24:17.021485  jumping to kernel

10425 12:24:17.023715  end: 2.2.4 bootloader-commands (duration 00:00:39) [common]
10426 12:24:17.024290  start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10427 12:24:17.024700  Setting prompt string to ['Linux version [0-9]']
10428 12:24:17.025082  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10429 12:24:17.025477  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10430 12:24:17.103934  

10431 12:24:17.107207  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10432 12:24:17.110867  start: 2.2.5.1 login-action (timeout 00:03:46) [common]
10433 12:24:17.111449  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10434 12:24:17.111893  Setting prompt string to []
10435 12:24:17.112329  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10436 12:24:17.112732  Using line separator: #'\n'#
10437 12:24:17.113062  No login prompt set.
10438 12:24:17.113400  Parsing kernel messages
10439 12:24:17.113707  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10440 12:24:17.114261  [login-action] Waiting for messages, (timeout 00:03:46)
10441 12:24:17.130305  [    0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023

10442 12:24:17.133919  [    0.000000] random: crng init done

10443 12:24:17.140486  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10444 12:24:17.143252  [    0.000000] efi: UEFI not found.

10445 12:24:17.149793  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10446 12:24:17.156655  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10447 12:24:17.166701  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10448 12:24:17.176511  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10449 12:24:17.183219  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10450 12:24:17.189549  [    0.000000] printk: bootconsole [mtk8250] enabled

10451 12:24:17.196138  [    0.000000] NUMA: No NUMA configuration found

10452 12:24:17.202881  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10453 12:24:17.205901  [    0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]

10454 12:24:17.209585  [    0.000000] Zone ranges:

10455 12:24:17.215968  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10456 12:24:17.219185  [    0.000000]   DMA32    empty

10457 12:24:17.226015  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10458 12:24:17.229421  [    0.000000] Movable zone start for each node

10459 12:24:17.232151  [    0.000000] Early memory node ranges

10460 12:24:17.238955  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10461 12:24:17.245785  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10462 12:24:17.251951  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10463 12:24:17.258460  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10464 12:24:17.265196  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10465 12:24:17.271865  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10466 12:24:17.327718  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10467 12:24:17.334365  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10468 12:24:17.341113  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10469 12:24:17.344479  [    0.000000] psci: probing for conduit method from DT.

10470 12:24:17.350587  [    0.000000] psci: PSCIv1.1 detected in firmware.

10471 12:24:17.353978  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10472 12:24:17.360960  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10473 12:24:17.364720  [    0.000000] psci: SMC Calling Convention v1.2

10474 12:24:17.370735  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10475 12:24:17.373956  [    0.000000] Detected VIPT I-cache on CPU0

10476 12:24:17.380895  [    0.000000] CPU features: detected: GIC system register CPU interface

10477 12:24:17.387297  [    0.000000] CPU features: detected: Virtualization Host Extensions

10478 12:24:17.393616  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10479 12:24:17.400276  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10480 12:24:17.410381  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10481 12:24:17.416656  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10482 12:24:17.419930  [    0.000000] alternatives: applying boot alternatives

10483 12:24:17.426929  [    0.000000] Fallback order for Node 0: 0 

10484 12:24:17.433104  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10485 12:24:17.436987  [    0.000000] Policy zone: Normal

10486 12:24:17.450107  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10487 12:24:17.459836  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10488 12:24:17.472272  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10489 12:24:17.482481  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10490 12:24:17.488697  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10491 12:24:17.492103  <6>[    0.000000] software IO TLB: area num 8.

10492 12:24:17.549386  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10493 12:24:17.698293  <6>[    0.000000] Memory: 7914380K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 438388K reserved, 32768K cma-reserved)

10494 12:24:17.705339  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10495 12:24:17.711958  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10496 12:24:17.715003  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10497 12:24:17.721658  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10498 12:24:17.728389  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10499 12:24:17.730964  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10500 12:24:17.740968  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10501 12:24:17.747379  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10502 12:24:17.754151  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10503 12:24:17.760634  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10504 12:24:17.764422  <6>[    0.000000] GICv3: 608 SPIs implemented

10505 12:24:17.767962  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10506 12:24:17.774076  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10507 12:24:17.777603  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10508 12:24:17.784049  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10509 12:24:17.796906  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10510 12:24:17.810486  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10511 12:24:17.817727  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10512 12:24:17.825189  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10513 12:24:17.838467  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10514 12:24:17.844526  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10515 12:24:17.851219  <6>[    0.009174] Console: colour dummy device 80x25

10516 12:24:17.861321  <6>[    0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10517 12:24:17.868129  <6>[    0.024343] pid_max: default: 32768 minimum: 301

10518 12:24:17.871037  <6>[    0.029214] LSM: Security Framework initializing

10519 12:24:17.877816  <6>[    0.034182] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10520 12:24:17.887754  <6>[    0.042041] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10521 12:24:17.897446  <6>[    0.051456] cblist_init_generic: Setting adjustable number of callback queues.

10522 12:24:17.900824  <6>[    0.058945] cblist_init_generic: Setting shift to 3 and lim to 1.

10523 12:24:17.910904  <6>[    0.065324] cblist_init_generic: Setting adjustable number of callback queues.

10524 12:24:17.917809  <6>[    0.072796] cblist_init_generic: Setting shift to 3 and lim to 1.

10525 12:24:17.920994  <6>[    0.079197] rcu: Hierarchical SRCU implementation.

10526 12:24:17.927392  <6>[    0.084212] rcu: 	Max phase no-delay instances is 1000.

10527 12:24:17.933853  <6>[    0.091237] EFI services will not be available.

10528 12:24:17.937150  <6>[    0.096225] smp: Bringing up secondary CPUs ...

10529 12:24:17.945847  <6>[    0.101276] Detected VIPT I-cache on CPU1

10530 12:24:17.952338  <6>[    0.101348] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10531 12:24:17.958760  <6>[    0.101377] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10532 12:24:17.962539  <6>[    0.101721] Detected VIPT I-cache on CPU2

10533 12:24:17.971486  <6>[    0.101775] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10534 12:24:17.978571  <6>[    0.101792] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10535 12:24:17.981571  <6>[    0.102054] Detected VIPT I-cache on CPU3

10536 12:24:17.988724  <6>[    0.102100] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10537 12:24:17.995025  <6>[    0.102114] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10538 12:24:18.001627  <6>[    0.102420] CPU features: detected: Spectre-v4

10539 12:24:18.004681  <6>[    0.102426] CPU features: detected: Spectre-BHB

10540 12:24:18.007921  <6>[    0.102431] Detected PIPT I-cache on CPU4

10541 12:24:18.014882  <6>[    0.102488] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10542 12:24:18.024557  <6>[    0.102505] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10543 12:24:18.028620  <6>[    0.102800] Detected PIPT I-cache on CPU5

10544 12:24:18.034367  <6>[    0.102861] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10545 12:24:18.040971  <6>[    0.102878] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10546 12:24:18.044121  <6>[    0.103161] Detected PIPT I-cache on CPU6

10547 12:24:18.054849  <6>[    0.103225] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10548 12:24:18.060842  <6>[    0.103242] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10549 12:24:18.064261  <6>[    0.103538] Detected PIPT I-cache on CPU7

10550 12:24:18.070943  <6>[    0.103606] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10551 12:24:18.077356  <6>[    0.103622] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10552 12:24:18.081004  <6>[    0.103668] smp: Brought up 1 node, 8 CPUs

10553 12:24:18.087473  <6>[    0.244888] SMP: Total of 8 processors activated.

10554 12:24:18.090571  <6>[    0.249839] CPU features: detected: 32-bit EL0 Support

10555 12:24:18.100546  <6>[    0.255202] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10556 12:24:18.107529  <6>[    0.264057] CPU features: detected: Common not Private translations

10557 12:24:18.114161  <6>[    0.270533] CPU features: detected: CRC32 instructions

10558 12:24:18.120898  <6>[    0.275885] CPU features: detected: RCpc load-acquire (LDAPR)

10559 12:24:18.124102  <6>[    0.281881] CPU features: detected: LSE atomic instructions

10560 12:24:18.130173  <6>[    0.287663] CPU features: detected: Privileged Access Never

10561 12:24:18.137017  <6>[    0.293443] CPU features: detected: RAS Extension Support

10562 12:24:18.143841  <6>[    0.299087] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10563 12:24:18.147095  <6>[    0.306308] CPU: All CPU(s) started at EL2

10564 12:24:18.153489  <6>[    0.310651] alternatives: applying system-wide alternatives

10565 12:24:18.163326  <6>[    0.321359] devtmpfs: initialized

10566 12:24:18.175490  <6>[    0.330129] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10567 12:24:18.185964  <6>[    0.340091] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10568 12:24:18.191867  <6>[    0.348225] pinctrl core: initialized pinctrl subsystem

10569 12:24:18.195681  <6>[    0.354890] DMI not present or invalid.

10570 12:24:18.201839  <6>[    0.359299] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10571 12:24:18.212070  <6>[    0.366166] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10572 12:24:18.218434  <6>[    0.373748] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10573 12:24:18.228699  <6>[    0.381966] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10574 12:24:18.231261  <6>[    0.390209] audit: initializing netlink subsys (disabled)

10575 12:24:18.241296  <5>[    0.395906] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1

10576 12:24:18.248259  <6>[    0.396610] thermal_sys: Registered thermal governor 'step_wise'

10577 12:24:18.254808  <6>[    0.403874] thermal_sys: Registered thermal governor 'power_allocator'

10578 12:24:18.257888  <6>[    0.410131] cpuidle: using governor menu

10579 12:24:18.264469  <6>[    0.421093] NET: Registered PF_QIPCRTR protocol family

10580 12:24:18.271112  <6>[    0.426572] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10581 12:24:18.277573  <6>[    0.433677] ASID allocator initialised with 32768 entries

10582 12:24:18.280907  <6>[    0.440241] Serial: AMBA PL011 UART driver

10583 12:24:18.291519  <4>[    0.449003] Trying to register duplicate clock ID: 134

10584 12:24:18.345072  <6>[    0.506154] KASLR enabled

10585 12:24:18.359290  <6>[    0.513785] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10586 12:24:18.365479  <6>[    0.520799] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10587 12:24:18.372533  <6>[    0.527288] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10588 12:24:18.378991  <6>[    0.534293] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10589 12:24:18.385691  <6>[    0.540781] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10590 12:24:18.392876  <6>[    0.547786] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10591 12:24:18.398642  <6>[    0.554274] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10592 12:24:18.405622  <6>[    0.561280] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10593 12:24:18.408417  <6>[    0.568731] ACPI: Interpreter disabled.

10594 12:24:18.417279  <6>[    0.575157] iommu: Default domain type: Translated 

10595 12:24:18.424220  <6>[    0.580271] iommu: DMA domain TLB invalidation policy: strict mode 

10596 12:24:18.427468  <5>[    0.586930] SCSI subsystem initialized

10597 12:24:18.433875  <6>[    0.591180] usbcore: registered new interface driver usbfs

10598 12:24:18.441029  <6>[    0.596907] usbcore: registered new interface driver hub

10599 12:24:18.443573  <6>[    0.602460] usbcore: registered new device driver usb

10600 12:24:18.450513  <6>[    0.608579] pps_core: LinuxPPS API ver. 1 registered

10601 12:24:18.460593  <6>[    0.613772] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10602 12:24:18.463887  <6>[    0.623116] PTP clock support registered

10603 12:24:18.467360  <6>[    0.627356] EDAC MC: Ver: 3.0.0

10604 12:24:18.474426  <6>[    0.632541] FPGA manager framework

10605 12:24:18.480979  <6>[    0.636216] Advanced Linux Sound Architecture Driver Initialized.

10606 12:24:18.484359  <6>[    0.642982] vgaarb: loaded

10607 12:24:18.491355  <6>[    0.646148] clocksource: Switched to clocksource arch_sys_counter

10608 12:24:18.494627  <5>[    0.652596] VFS: Disk quotas dquot_6.6.0

10609 12:24:18.500868  <6>[    0.656784] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10610 12:24:18.504063  <6>[    0.663974] pnp: PnP ACPI: disabled

10611 12:24:18.512721  <6>[    0.670613] NET: Registered PF_INET protocol family

10612 12:24:18.519387  <6>[    0.675894] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10613 12:24:18.533362  <6>[    0.688196] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10614 12:24:18.543676  <6>[    0.697016] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10615 12:24:18.550330  <6>[    0.704988] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10616 12:24:18.559802  <6>[    0.713691] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10617 12:24:18.566709  <6>[    0.723438] TCP: Hash tables configured (established 65536 bind 65536)

10618 12:24:18.573119  <6>[    0.730306] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10619 12:24:18.582924  <6>[    0.737504] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10620 12:24:18.589479  <6>[    0.745203] NET: Registered PF_UNIX/PF_LOCAL protocol family

10621 12:24:18.595946  <6>[    0.751373] RPC: Registered named UNIX socket transport module.

10622 12:24:18.599590  <6>[    0.757527] RPC: Registered udp transport module.

10623 12:24:18.606094  <6>[    0.762461] RPC: Registered tcp transport module.

10624 12:24:18.613098  <6>[    0.767393] RPC: Registered tcp NFSv4.1 backchannel transport module.

10625 12:24:18.615754  <6>[    0.774061] PCI: CLS 0 bytes, default 64

10626 12:24:18.619174  <6>[    0.778475] Unpacking initramfs...

10627 12:24:18.643887  <6>[    0.798271] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10628 12:24:18.653934  <6>[    0.806918] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10629 12:24:18.657189  <6>[    0.815774] kvm [1]: IPA Size Limit: 40 bits

10630 12:24:18.663708  <6>[    0.820298] kvm [1]: GICv3: no GICV resource entry

10631 12:24:18.666938  <6>[    0.825321] kvm [1]: disabling GICv2 emulation

10632 12:24:18.673386  <6>[    0.830007] kvm [1]: GIC system register CPU interface enabled

10633 12:24:18.676706  <6>[    0.836169] kvm [1]: vgic interrupt IRQ18

10634 12:24:18.683574  <6>[    0.840522] kvm [1]: VHE mode initialized successfully

10635 12:24:18.689714  <5>[    0.846997] Initialise system trusted keyrings

10636 12:24:18.696800  <6>[    0.851837] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10637 12:24:18.704191  <6>[    0.861703] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10638 12:24:18.710655  <5>[    0.868081] NFS: Registering the id_resolver key type

10639 12:24:18.714480  <5>[    0.873384] Key type id_resolver registered

10640 12:24:18.720709  <5>[    0.877802] Key type id_legacy registered

10641 12:24:18.726695  <6>[    0.882077] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10642 12:24:18.733558  <6>[    0.889000] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10643 12:24:18.740127  <6>[    0.896735] 9p: Installing v9fs 9p2000 file system support

10644 12:24:18.777136  <5>[    0.935204] Key type asymmetric registered

10645 12:24:18.780652  <5>[    0.939535] Asymmetric key parser 'x509' registered

10646 12:24:18.790245  <6>[    0.944677] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10647 12:24:18.794065  <6>[    0.952293] io scheduler mq-deadline registered

10648 12:24:18.797098  <6>[    0.957054] io scheduler kyber registered

10649 12:24:18.816022  <6>[    0.974107] EINJ: ACPI disabled.

10650 12:24:18.848420  <4>[    0.999798] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10651 12:24:18.858192  <4>[    1.010441] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10652 12:24:18.873321  <6>[    1.031126] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10653 12:24:18.881134  <6>[    1.039116] printk: console [ttyS0] disabled

10654 12:24:18.909252  <6>[    1.063774] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10655 12:24:18.916146  <6>[    1.073248] printk: console [ttyS0] enabled

10656 12:24:18.919303  <6>[    1.073248] printk: console [ttyS0] enabled

10657 12:24:18.926151  <6>[    1.082142] printk: bootconsole [mtk8250] disabled

10658 12:24:18.929116  <6>[    1.082142] printk: bootconsole [mtk8250] disabled

10659 12:24:18.935582  <6>[    1.093361] SuperH (H)SCI(F) driver initialized

10660 12:24:18.939189  <6>[    1.098631] msm_serial: driver initialized

10661 12:24:18.953106  <6>[    1.107601] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10662 12:24:18.962977  <6>[    1.116148] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10663 12:24:18.969606  <6>[    1.124692] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10664 12:24:18.979684  <6>[    1.133320] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10665 12:24:18.989160  <6>[    1.142027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10666 12:24:18.995619  <6>[    1.150746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10667 12:24:19.005620  <6>[    1.159286] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10668 12:24:19.014900  <6>[    1.168092] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10669 12:24:19.021953  <6>[    1.176635] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10670 12:24:19.034495  <6>[    1.192415] loop: module loaded

10671 12:24:19.041347  <6>[    1.198488] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10672 12:24:19.064057  <4>[    1.221799] mtk-pmic-keys: Failed to locate of_node [id: -1]

10673 12:24:19.071287  <6>[    1.228688] megasas: 07.719.03.00-rc1

10674 12:24:19.080325  <6>[    1.238269] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10675 12:24:19.087629  <6>[    1.245515] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10676 12:24:19.103946  <6>[    1.262185] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10677 12:24:19.164227  <6>[    1.315971] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7

10678 12:24:21.028688  <6>[    3.187030] Freeing initrd memory: 55104K

10679 12:24:21.039572  <6>[    3.197654] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10680 12:24:21.050364  <6>[    3.208538] tun: Universal TUN/TAP device driver, 1.6

10681 12:24:21.053731  <6>[    3.214613] thunder_xcv, ver 1.0

10682 12:24:21.056824  <6>[    3.218105] thunder_bgx, ver 1.0

10683 12:24:21.059923  <6>[    3.221604] nicpf, ver 1.0

10684 12:24:21.071082  <6>[    3.225636] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10685 12:24:21.074102  <6>[    3.233112] hns3: Copyright (c) 2017 Huawei Corporation.

10686 12:24:21.080411  <6>[    3.238698] hclge is initializing

10687 12:24:21.083921  <6>[    3.242277] e1000: Intel(R) PRO/1000 Network Driver

10688 12:24:21.090566  <6>[    3.247407] e1000: Copyright (c) 1999-2006 Intel Corporation.

10689 12:24:21.093945  <6>[    3.253423] e1000e: Intel(R) PRO/1000 Network Driver

10690 12:24:21.100863  <6>[    3.258638] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10691 12:24:21.106951  <6>[    3.264822] igb: Intel(R) Gigabit Ethernet Network Driver

10692 12:24:21.114037  <6>[    3.270472] igb: Copyright (c) 2007-2014 Intel Corporation.

10693 12:24:21.120508  <6>[    3.276308] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10694 12:24:21.127259  <6>[    3.282826] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10695 12:24:21.130115  <6>[    3.289295] sky2: driver version 1.30

10696 12:24:21.136737  <6>[    3.294299] VFIO - User Level meta-driver version: 0.3

10697 12:24:21.144629  <6>[    3.302567] usbcore: registered new interface driver usb-storage

10698 12:24:21.151295  <6>[    3.309012] usbcore: registered new device driver onboard-usb-hub

10699 12:24:21.159685  <6>[    3.318188] mt6397-rtc mt6359-rtc: registered as rtc0

10700 12:24:21.169788  <6>[    3.323648] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:24:21 UTC (1698409461)

10701 12:24:21.173009  <6>[    3.333211] i2c_dev: i2c /dev entries driver

10702 12:24:21.190149  <6>[    3.344913] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10703 12:24:21.209759  <6>[    3.367919] cpu cpu0: EM: created perf domain

10704 12:24:21.213059  <6>[    3.372854] cpu cpu4: EM: created perf domain

10705 12:24:21.220196  <6>[    3.378433] sdhci: Secure Digital Host Controller Interface driver

10706 12:24:21.226760  <6>[    3.384865] sdhci: Copyright(c) Pierre Ossman

10707 12:24:21.233580  <6>[    3.389832] Synopsys Designware Multimedia Card Interface Driver

10708 12:24:21.240135  <6>[    3.396468] sdhci-pltfm: SDHCI platform and OF driver helper

10709 12:24:21.243377  <6>[    3.396518] mmc0: CQHCI version 5.10

10710 12:24:21.250153  <6>[    3.406604] ledtrig-cpu: registered to indicate activity on CPUs

10711 12:24:21.256325  <6>[    3.413654] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10712 12:24:21.263165  <6>[    3.420706] usbcore: registered new interface driver usbhid

10713 12:24:21.266468  <6>[    3.426532] usbhid: USB HID core driver

10714 12:24:21.273005  <6>[    3.430760] spi_master spi0: will run message pump with realtime priority

10715 12:24:21.317532  <6>[    3.469461] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10716 12:24:21.336812  <6>[    3.485530] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10717 12:24:21.340395  <6>[    3.499259] mmc0: Command Queue Engine enabled

10718 12:24:21.347604  <6>[    3.504093] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10719 12:24:21.353842  <6>[    3.511404] mmcblk0: mmc0:0001 DA4128 116 GiB 

10720 12:24:21.360315  <6>[    3.516370] cros-ec-spi spi0.0: Chrome EC device registered

10721 12:24:21.363342  <6>[    3.520383]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10722 12:24:21.371188  <6>[    3.529591] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10723 12:24:21.377803  <6>[    3.535660] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10724 12:24:21.384533  <6>[    3.541468] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10725 12:24:21.401444  <6>[    3.557063] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10726 12:24:21.408856  <6>[    3.567646] NET: Registered PF_PACKET protocol family

10727 12:24:21.412596  <6>[    3.573051] 9pnet: Installing 9P2000 support

10728 12:24:21.418704  <5>[    3.577618] Key type dns_resolver registered

10729 12:24:21.422570  <6>[    3.582620] registered taskstats version 1

10730 12:24:21.429032  <5>[    3.587018] Loading compiled-in X.509 certificates

10731 12:24:21.459150  <4>[    3.611460] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10732 12:24:21.468943  <4>[    3.622334] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10733 12:24:21.475559  <3>[    3.632869] debugfs: File 'uA_load' in directory '/' already present!

10734 12:24:21.482397  <3>[    3.639571] debugfs: File 'min_uV' in directory '/' already present!

10735 12:24:21.489106  <3>[    3.646179] debugfs: File 'max_uV' in directory '/' already present!

10736 12:24:21.495505  <3>[    3.652788] debugfs: File 'constraint_flags' in directory '/' already present!

10737 12:24:21.507293  <3>[    3.662877] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10738 12:24:21.520613  <6>[    3.679270] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10739 12:24:21.527456  <6>[    3.686023] xhci-mtk 11200000.usb: xHCI Host Controller

10740 12:24:21.533675  <6>[    3.691540] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10741 12:24:21.543828  <6>[    3.699402] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10742 12:24:21.551023  <6>[    3.708830] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10743 12:24:21.557052  <6>[    3.714982] xhci-mtk 11200000.usb: xHCI Host Controller

10744 12:24:21.563866  <6>[    3.720480] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10745 12:24:21.570339  <6>[    3.728148] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10746 12:24:21.577184  <6>[    3.736195] hub 1-0:1.0: USB hub found

10747 12:24:21.581068  <6>[    3.740222] hub 1-0:1.0: 1 port detected

10748 12:24:21.590538  <6>[    3.744522] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10749 12:24:21.593759  <6>[    3.753330] hub 2-0:1.0: USB hub found

10750 12:24:21.597253  <6>[    3.757351] hub 2-0:1.0: 1 port detected

10751 12:24:21.606076  <6>[    3.765111] mtk-msdc 11f70000.mmc: Got CD GPIO

10752 12:24:21.617102  <6>[    3.772813] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10753 12:24:21.623767  <6>[    3.780844] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10754 12:24:21.634075  <4>[    3.788753] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10755 12:24:21.643845  <6>[    3.798293] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10756 12:24:21.650524  <6>[    3.806370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10757 12:24:21.657127  <6>[    3.814384] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10758 12:24:21.666644  <6>[    3.822301] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10759 12:24:21.673324  <6>[    3.830120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10760 12:24:21.683265  <6>[    3.837937] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10761 12:24:21.693342  <6>[    3.848326] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10762 12:24:21.699889  <6>[    3.856695] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10763 12:24:21.709933  <6>[    3.865049] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10764 12:24:21.716694  <6>[    3.873388] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10765 12:24:21.726023  <6>[    3.881726] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10766 12:24:21.736752  <6>[    3.890091] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10767 12:24:21.743205  <6>[    3.898432] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10768 12:24:21.753162  <6>[    3.906771] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10769 12:24:21.759913  <6>[    3.915108] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10770 12:24:21.769637  <6>[    3.923446] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10771 12:24:21.776383  <6>[    3.931783] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10772 12:24:21.786664  <6>[    3.940121] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10773 12:24:21.793006  <6>[    3.948459] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10774 12:24:21.803319  <6>[    3.956800] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10775 12:24:21.809565  <6>[    3.965138] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10776 12:24:21.816231  <6>[    3.973857] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10777 12:24:21.822925  <6>[    3.980990] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10778 12:24:21.829647  <6>[    3.987752] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10779 12:24:21.839986  <6>[    3.994516] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10780 12:24:21.846596  <6>[    4.001449] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10781 12:24:21.852778  <6>[    4.008302] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10782 12:24:21.862419  <6>[    4.017434] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10783 12:24:21.872631  <6>[    4.026555] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10784 12:24:21.882353  <6>[    4.035848] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10785 12:24:21.892215  <6>[    4.045316] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10786 12:24:21.902010  <6>[    4.054784] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10787 12:24:21.908551  <6>[    4.063910] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10788 12:24:21.918428  <6>[    4.073378] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10789 12:24:21.929025  <6>[    4.082498] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10790 12:24:21.938830  <6>[    4.091794] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10791 12:24:21.948704  <6>[    4.101953] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10792 12:24:21.958785  <6>[    4.113767] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10793 12:24:22.011384  <6>[    4.166419] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10794 12:24:22.165902  <6>[    4.324280] hub 1-1:1.0: USB hub found

10795 12:24:22.169334  <6>[    4.328835] hub 1-1:1.0: 4 ports detected

10796 12:24:22.291266  <6>[    4.446423] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10797 12:24:22.317700  <6>[    4.475867] hub 2-1:1.0: USB hub found

10798 12:24:22.321071  <6>[    4.480335] hub 2-1:1.0: 3 ports detected

10799 12:24:22.491872  <6>[    4.646408] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk

10800 12:24:22.622481  <6>[    4.780657] hub 1-1.1:1.0: USB hub found

10801 12:24:22.625515  <6>[    4.785002] hub 1-1.1:1.0: 4 ports detected

10802 12:24:22.739277  <6>[    4.894503] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk

10803 12:24:22.871951  <6>[    5.030337] hub 1-1.4:1.0: USB hub found

10804 12:24:22.875263  <6>[    5.035013] hub 1-1.4:1.0: 2 ports detected

10805 12:24:22.955409  <6>[    5.110469] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk

10806 12:24:23.147672  <6>[    5.302466] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk

10807 12:24:23.232049  <3>[    5.390646] usb 1-1.1.4: device descriptor read/64, error -32

10808 12:24:23.423845  <3>[    5.582645] usb 1-1.1.4: device descriptor read/64, error -32

10809 12:24:23.619325  <6>[    5.774475] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk

10810 12:24:23.807474  <6>[    5.962540] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk

10811 12:24:23.892114  <3>[    6.050560] usb 1-1.1.4: device descriptor read/64, error -32

10812 12:24:24.084009  <3>[    6.242662] usb 1-1.1.4: device descriptor read/64, error -32

10813 12:24:24.196714  <6>[    6.354997] usb 1-1.1-port4: attempt power cycle

10814 12:24:24.283603  <6>[    6.438466] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk

10815 12:24:24.807447  <6>[    6.962509] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk

10816 12:24:24.813921  <4>[    6.969998] usb 1-1.1.4: Device not responding to setup address.

10817 12:24:25.024343  <4>[    7.182726] usb 1-1.1.4: Device not responding to setup address.

10818 12:24:25.235596  <3>[    7.394458] usb 1-1.1.4: device not accepting address 10, error -71

10819 12:24:25.322480  <6>[    7.478465] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk

10820 12:24:25.329050  <4>[    7.485870] usb 1-1.1.4: Device not responding to setup address.

10821 12:24:25.540359  <4>[    7.698516] usb 1-1.1.4: Device not responding to setup address.

10822 12:24:25.751872  <3>[    7.910459] usb 1-1.1.4: device not accepting address 11, error -71

10823 12:24:25.758965  <3>[    7.917483] usb 1-1.1-port4: unable to enumerate USB device

10824 12:24:34.236685  <6>[   16.399463] ALSA device list:

10825 12:24:34.242975  <6>[   16.402755]   No soundcards found.

10826 12:24:34.251254  <6>[   16.410748] Freeing unused kernel memory: 8384K

10827 12:24:34.254224  <6>[   16.415735] Run /init as init process

10828 12:24:34.304246  <6>[   16.464159] NET: Registered PF_INET6 protocol family

10829 12:24:34.311281  <6>[   16.471062] Segment Routing with IPv6

10830 12:24:34.314410  <6>[   16.475030] In-situ OAM (IOAM) with IPv6

10831 12:24:34.352473  <30>[   16.492221] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10832 12:24:34.355476  <30>[   16.516005] systemd[1]: Detected architecture arm64.

10833 12:24:34.356232  

10834 12:24:34.362164  Welcome to Debian GNU/Linux 11 (bullseye)!

10835 12:24:34.362631  

10836 12:24:34.374819  <30>[   16.534413] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10837 12:24:34.517051  <30>[   16.673249] systemd[1]: Queued start job for default target Graphical Interface.

10838 12:24:34.544141  <30>[   16.703506] systemd[1]: Created slice system-getty.slice.

10839 12:24:34.550531  [  OK  ] Created slice system-getty.slice.

10840 12:24:34.567178  <30>[   16.726813] systemd[1]: Created slice system-modprobe.slice.

10841 12:24:34.573913  [  OK  ] Created slice system-modprobe.slice.

10842 12:24:34.594915  <30>[   16.751346] systemd[1]: Created slice system-serial\x2dgetty.slice.

10843 12:24:34.601882  [  OK  ] Created slice system-serial\x2dgetty.slice.

10844 12:24:34.615690  <30>[   16.775439] systemd[1]: Created slice User and Session Slice.

10845 12:24:34.622361  [  OK  ] Created slice User and Session Slice.

10846 12:24:34.642321  <30>[   16.798966] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10847 12:24:34.652449  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10848 12:24:34.670674  <30>[   16.826954] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10849 12:24:34.677436  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10850 12:24:34.701975  <30>[   16.854854] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10851 12:24:34.708842  <30>[   16.867084] systemd[1]: Reached target Local Encrypted Volumes.

10852 12:24:34.715213  [  OK  ] Reached target Local Encrypted Volumes.

10853 12:24:34.731071  <30>[   16.890837] systemd[1]: Reached target Paths.

10854 12:24:34.734488  [  OK  ] Reached target Paths.

10855 12:24:34.750705  <30>[   16.910435] systemd[1]: Reached target Remote File Systems.

10856 12:24:34.757064  [  OK  ] Reached target Remote File Systems.

10857 12:24:34.770661  <30>[   16.930351] systemd[1]: Reached target Slices.

10858 12:24:34.773510  [  OK  ] Reached target Slices.

10859 12:24:34.790854  <30>[   16.950405] systemd[1]: Reached target Swap.

10860 12:24:34.794067  [  OK  ] Reached target Swap.

10861 12:24:34.814726  <30>[   16.970853] systemd[1]: Listening on initctl Compatibility Named Pipe.

10862 12:24:34.821261  [  OK  ] Listening on initctl Compatibility Named Pipe.

10863 12:24:34.835822  <30>[   16.995793] systemd[1]: Listening on Journal Audit Socket.

10864 12:24:34.842289  [  OK  ] Listening on Journal Audit Socket.

10865 12:24:34.859385  <30>[   17.019499] systemd[1]: Listening on Journal Socket (/dev/log).

10866 12:24:34.866653  [  OK  ] Listening on Journal Socket (/dev/log).

10867 12:24:34.883221  <30>[   17.042869] systemd[1]: Listening on Journal Socket.

10868 12:24:34.889628  [  OK  ] Listening on Journal Socket.

10869 12:24:34.903521  <30>[   17.062925] systemd[1]: Listening on udev Control Socket.

10870 12:24:34.909768  [  OK  ] Listening on udev Control Socket.

10871 12:24:34.928149  <30>[   17.087387] systemd[1]: Listening on udev Kernel Socket.

10872 12:24:34.934371  [  OK  ] Listening on udev Kernel Socket.

10873 12:24:34.975262  <30>[   17.134543] systemd[1]: Mounting Huge Pages File System...

10874 12:24:34.981139           Mounting Huge Pages File System...

10875 12:24:34.997269  <30>[   17.155993] systemd[1]: Mounting POSIX Message Queue File System...

10876 12:24:35.003276           Mounting POSIX Message Queue File System...

10877 12:24:35.020771  <30>[   17.180372] systemd[1]: Mounting Kernel Debug File System...

10878 12:24:35.027105           Mounting Kernel Debug File System...

10879 12:24:35.046278  <30>[   17.202627] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10880 12:24:35.058610  <30>[   17.214637] systemd[1]: Starting Create list of static device nodes for the current kernel...

10881 12:24:35.064972           Starting Create list of st…odes for the current kernel...

10882 12:24:35.086119  <30>[   17.245780] systemd[1]: Starting Load Kernel Module configfs...

10883 12:24:35.092729           Starting Load Kernel Module configfs...

10884 12:24:35.111228  <30>[   17.271045] systemd[1]: Starting Load Kernel Module drm...

10885 12:24:35.117935           Starting Load Kernel Module drm...

10886 12:24:35.134584  <30>[   17.290814] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10887 12:24:35.148945  <30>[   17.308651] systemd[1]: Starting Journal Service...

10888 12:24:35.155708           Starting Journal Service...

10889 12:24:35.176278  <30>[   17.335836] systemd[1]: Starting Load Kernel Modules...

10890 12:24:35.182848           Starting Load Kernel Modules...

10891 12:24:35.222699  <30>[   17.378956] systemd[1]: Starting Remount Root and Kernel File Systems...

10892 12:24:35.228767           Starting Remount Root and Kernel File Systems...

10893 12:24:35.245595  <30>[   17.405007] systemd[1]: Starting Coldplug All udev Devices...

10894 12:24:35.252132           Starting Coldplug All udev Devices...

10895 12:24:35.269043  <30>[   17.429075] systemd[1]: Started Journal Service.

10896 12:24:35.275715  [  OK  ] Started Journal Service.

10897 12:24:35.294509  [  OK  ] Mounted Huge Pages File System.

10898 12:24:35.315566  [  OK  ] Mounted POSIX Message Queue File System.

10899 12:24:35.331706  [  OK  ] Mounted Kernel Debug File System.

10900 12:24:35.352031  [  OK  ] Finished Create list of st… nodes for the current kernel.

10901 12:24:35.373008  [  OK  ] Finished Load Kernel Module configfs.

10902 12:24:35.398100  [  OK  ] Finished Load Kernel Module drm.

10903 12:24:35.416775  [  OK  ] Finished Load Kernel Modules.

10904 12:24:35.436703  [FAILED] Failed to start Remount Root and Kernel File Systems.

10905 12:24:35.454884  See 'systemctl status systemd-remount-fs.service' for details.

10906 12:24:35.508657           Mounting Kernel Configuration File System...

10907 12:24:35.525840           Starting Flush Journal to Persistent Storage...

10908 12:24:35.540793  <46>[   17.697411] systemd-journald[178]: Received client request to flush runtime journal.

10909 12:24:35.550085           Starting Load/Save Random Seed...

10910 12:24:35.576603           Starting Apply Kernel Variables...

10911 12:24:35.600093           Starting Create System Users...

10912 12:24:35.619606  [  OK  ] Mounted Kernel Configuration File System.

10913 12:24:35.637160  [  OK  ] Finished Coldplug All udev Devices.

10914 12:24:35.664405  [  OK  ] Finished Flush Journal to Persistent Storage.

10915 12:24:35.680849  [  OK  ] Finished Load/Save Random Seed.

10916 12:24:35.700471  [  OK  ] Finished Apply Kernel Variables.

10917 12:24:35.716239  [  OK  ] Finished Create System Users.

10918 12:24:35.763589           Starting Create Static Device Nodes in /dev...

10919 12:24:35.783332  [  OK  ] Finished Create Static Device Nodes in /dev.

10920 12:24:35.795051  [  OK  ] Reached target Local File Systems (Pre).

10921 12:24:35.814848  [  OK  ] Reached target Local File Systems.

10922 12:24:35.867415           Starting Create Volatile Files and Directories...

10923 12:24:35.897982           Starting Rule-based Manage…for Device Events and Files...

10924 12:24:35.917955  [  OK  ] Finished Create Volatile Files and Directories.

10925 12:24:35.940742  [  OK  ] Started Rule-based Manager for Device Events and Files.

10926 12:24:35.996420           Starting Network Time Synchronization...

10927 12:24:36.021080           Starting Update UTMP about System Boot/Shutdown...

10928 12:24:36.066274  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10929 12:24:36.087346  [  OK  ] Started [0;<6>[   18.242064] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10930 12:24:36.090415  1;39mNetwork Time Synchronization.

10931 12:24:36.098222  <6>[   18.258047] remoteproc remoteproc0: scp is available

10932 12:24:36.104716  <6>[   18.264088] remoteproc remoteproc0: powering up scp

10933 12:24:36.115271  <6>[   18.269776] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10934 12:24:36.118340  <6>[   18.278234] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10935 12:24:36.124793  [  OK  ] Found device /dev/ttyS0.

10936 12:24:36.138862  <6>[   18.295559] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10937 12:24:36.145711  <6>[   18.303207] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10938 12:24:36.155683  <3>[   18.308285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10939 12:24:36.165400  <6>[   18.311914] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10940 12:24:36.172427  <3>[   18.319988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10941 12:24:36.178363  <3>[   18.319995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10942 12:24:36.188562  [  OK  ] Created slic<6>[   18.346908] mc: Linux media interface: v0.10

10943 12:24:36.198300  e system-systemd\x2dbacklight.slice<3>[   18.356168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10944 12:24:36.198727  .

10945 12:24:36.207931  <4>[   18.358871] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10946 12:24:36.215200  <3>[   18.364740] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10947 12:24:36.224703  <3>[   18.364745] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10948 12:24:36.231309  <3>[   18.364751] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10949 12:24:36.241430  <3>[   18.364754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10950 12:24:36.248159  <4>[   18.375678] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10951 12:24:36.254516  <3>[   18.381950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10952 12:24:36.264421  <6>[   18.382573] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10953 12:24:36.270978  <6>[   18.409993] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10954 12:24:36.277732  <6>[   18.412096] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10955 12:24:36.284647  <6>[   18.412108] remoteproc remoteproc0: remote processor scp is now up

10956 12:24:36.291194  <6>[   18.414411] videodev: Linux video capture interface: v2.00

10957 12:24:36.297506  <3>[   18.418440] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10958 12:24:36.307766  <3>[   18.418479] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10959 12:24:36.313754  <3>[   18.418491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10960 12:24:36.323754  <3>[   18.419181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10961 12:24:36.330582  <3>[   18.419204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10962 12:24:36.340418  <3>[   18.419212] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10963 12:24:36.347389  <3>[   18.419228] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10964 12:24:36.356853  <3>[   18.419237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10965 12:24:36.363692  <3>[   18.419307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10966 12:24:36.370262  <6>[   18.420917] usbcore: registered new interface driver r8152

10967 12:24:36.380316  <4>[   18.439751] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10968 12:24:36.383304  <4>[   18.439751] Fallback method does not support PEC.

10969 12:24:36.389833  <6>[   18.461233] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10970 12:24:36.399781  <6>[   18.471070] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003

10971 12:24:36.406841  <6>[   18.472617] pci_bus 0000:00: root bus resource [bus 00-ff]

10972 12:24:36.416350  <6>[   18.480907] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2

10973 12:24:36.422525  <6>[   18.488908] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10974 12:24:36.432825  <6>[   18.497427] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3

10975 12:24:36.439694  <6>[   18.499425] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10976 12:24:36.449298  <6>[   18.501594] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10977 12:24:36.460076  <6>[   18.504753] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10978 12:24:36.466537  <6>[   18.529248] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk

10979 12:24:36.472942  <6>[   18.534919] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10980 12:24:36.476713  <6>[   18.548821] usbcore: registered new interface driver cdc_ether

10981 12:24:36.484108  <6>[   18.556134] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10982 12:24:36.490447  <6>[   18.571765] Bluetooth: Core ver 2.22

10983 12:24:36.493907  <6>[   18.580360] pci 0000:00:00.0: supports D1 D2

10984 12:24:36.500704  <6>[   18.580742] usbcore: registered new interface driver r8153_ecm

10985 12:24:36.503765  <6>[   18.587968] NET: Registered PF_BLUETOOTH protocol family

10986 12:24:36.510870  <6>[   18.596750] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10987 12:24:36.517940  <6>[   18.597814] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10988 12:24:36.530874  <6>[   18.599605] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10989 12:24:36.537565  <6>[   18.599849] usbcore: registered new interface driver uvcvideo

10990 12:24:36.544180  <6>[   18.605923] Bluetooth: HCI device and connection manager initialized

10991 12:24:36.554264  <6>[   18.614742] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10992 12:24:36.557589  <6>[   18.623202] Bluetooth: HCI socket layer initialized

10993 12:24:36.564714  <6>[   18.623841] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10994 12:24:36.571099  <6>[   18.630663] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10995 12:24:36.578150  <3>[   18.632720] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10996 12:24:36.587689  <3>[   18.633432] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6

10997 12:24:36.594421  <6>[   18.636779] Bluetooth: L2CAP socket layer initialized

10998 12:24:36.601430  <6>[   18.642861] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10999 12:24:36.604901  <6>[   18.650323] Bluetooth: SCO socket layer initialized

11000 12:24:36.614461  <3>[   18.652107] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11001 12:24:36.621358  <3>[   18.652855] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6

11002 12:24:36.628719  <6>[   18.654143] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

11003 12:24:36.639143  <4>[   18.662219] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

11004 12:24:36.645742  <6>[   18.664742] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

11005 12:24:36.655248  <4>[   18.670324] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

11006 12:24:36.658825  <6>[   18.677271] pci 0000:01:00.0: supports D1 D2

11007 12:24:36.669338  <3>[   18.683864] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11008 12:24:36.675825  <3>[   18.684580] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6

11009 12:24:36.682219  <6>[   18.696608] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

11010 12:24:36.689309  <6>[   18.703180] usbcore: registered new interface driver btusb

11011 12:24:36.699410  <4>[   18.704072] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

11012 12:24:36.706664  <3>[   18.704087] Bluetooth: hci0: Failed to load firmware file (-2)

11013 12:24:36.713180  <3>[   18.704094] Bluetooth: hci0: Failed to set up firmware (-2)

11014 12:24:36.723122  <4>[   18.704102] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

11015 12:24:36.729803  <6>[   18.710464] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

11016 12:24:36.736303  <3>[   18.732060] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11017 12:24:36.746611  <6>[   18.735469] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

11018 12:24:36.753263  <3>[   18.763317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11019 12:24:36.763861  <6>[   18.765316] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

11020 12:24:36.770721  <3>[   18.792717] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11021 12:24:36.780966  <6>[   18.795110] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

11022 12:24:36.784496  <6>[   18.814425] r8152 1-1.1.1:1.0 eth0: v1.12.13

11023 12:24:36.791066  <6>[   18.820035] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

11024 12:24:36.800213  <3>[   18.828558] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11025 12:24:36.807199  <6>[   18.833328] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

11026 12:24:36.813239  <6>[   18.840768] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0

11027 12:24:36.819960  <6>[   18.979848] pci 0000:00:00.0: PCI bridge to [bus 01]

11028 12:24:36.826620  <6>[   18.979857] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

11029 12:24:36.833057  <6>[   18.980024] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

11030 12:24:36.843650  [  OK  [<6>[   19.000048] pcieport 0000:00:00.0: PME: Signaling with IRQ 283

11031 12:24:36.849535  0m] Reached targ<6>[   19.007814] pcieport 0000:00:00.0: AER: enabled with IRQ 283

11032 12:24:36.852774  et System Time Set.

11033 12:24:36.876564  [  OK  ] Reached target System Time Synchron<5>[   19.031412] cfg80211: Loading compiled-in X.509 certificates for regulatory database

11034 12:24:36.876654  ized.

11035 12:24:36.896579  <5>[   19.053792] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

11036 12:24:36.903151  <4>[   19.060830] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

11037 12:24:36.909853  <6>[   19.069740] cfg80211: failed to load regulatory.db

11038 12:24:36.941299           Starting Load/Save Screen …of leds:white:kbd_backlight...

11039 12:24:36.968900  [  OK  ] Finished Load/Save Screen …s of l<6>[   19.127395] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

11040 12:24:36.978580  eds:white:kbd_ba<6>[   19.136150] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

11041 12:24:36.978694  cklight.

11042 12:24:37.001981  <6>[   19.162373] mt7921e 0000:01:00.0: ASIC revision: 79610010

11043 12:24:37.099973  <4>[   19.253726] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11044 12:24:37.130260  [  OK  ] Reached target Bluetooth.

11045 12:24:37.146162  [  OK  ] Reached target System Initialization.

11046 12:24:37.165509  [  OK  ] Started Discard unused blocks once a week.

11047 12:24:37.185299  [  OK  ] Started Daily Cleanup of Temporary Directories.

11048 12:24:37.198143  [  OK  ] Reached target Timers.

11049 12:24:37.221893  <4>[   19.375290] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11050 12:24:37.228063  [  OK  ] Listening on D-Bus System Message Bus Socket.

11051 12:24:37.242066  [  OK  ] Reached target Sockets.

11052 12:24:37.263110  [  OK  ] Reached target Basic System.

11053 12:24:37.286258  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

11054 12:24:37.329095  [  OK  ] Started D-Bus System Message Bus.

11055 12:24:37.344270  <4>[   19.497621] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11056 12:24:37.374963           Starting User Login Management...

11057 12:24:37.394990           Starting Permit User Sessions...

11058 12:24:37.416992           Starting Load/Save RF Kill Switch Status...

11059 12:24:37.427406  [  OK  ] Finished Permit User Sessions.

11060 12:24:37.443513  [  OK  ] Started Load/Save RF Kill Switch Status.

11061 12:24:37.465589  <4>[   19.619255] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11062 12:24:37.472314  [  OK  ] Started User Login Management.

11063 12:24:37.524311  [  OK  ] Started Getty on tty1.

11064 12:24:37.544958  [  OK  ] Started Serial Getty on ttyS0.

11065 12:24:37.563919  [  OK  ] Reached target Login Prompts.

11066 12:24:37.580214  [  OK  ] Reached target Multi-User System.

11067 12:24:37.593849  <4>[   19.747518] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11068 12:24:37.600569  [  OK  ] Reached target Graphical Interface.

11069 12:24:37.659582           Starting Update UTMP about System Runlevel Changes...

11070 12:24:37.698227  [  OK  ] Finished Update UTMP about System Runlevel Changes.

11071 12:24:37.717523  <4>[   19.871211] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11072 12:24:37.755417  

11073 12:24:37.756022  

11074 12:24:37.758985  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

11075 12:24:37.759570  

11076 12:24:37.761693  debian-bullseye-arm64 login: root (automatic login)

11077 12:24:37.762156  

11078 12:24:37.762522  

11079 12:24:37.778949  Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64

11080 12:24:37.779521  

11081 12:24:37.784803  The programs included with the Debian GNU/Linux system are free software;

11082 12:24:37.791835  the exact distribution terms for each program are described in the

11083 12:24:37.795243  individual files in /usr/share/doc/*/copyright.

11084 12:24:37.795705  

11085 12:24:37.801305  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

11086 12:24:37.804434  permitted by applicable law.

11087 12:24:37.805843  Matched prompt #10: / #
11089 12:24:37.806944  Setting prompt string to ['/ #']
11090 12:24:37.807415  end: 2.2.5.1 login-action (duration 00:00:21) [common]
11092 12:24:37.808561  end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11093 12:24:37.809038  start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
11094 12:24:37.809418  Setting prompt string to ['/ #']
11095 12:24:37.809760  Forcing a shell prompt, looking for ['/ #']
11097 12:24:37.860613  / # 

11098 12:24:37.861288  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11099 12:24:37.861799  Waiting using forced prompt support (timeout 00:02:30)
11100 12:24:37.862324  <4>[   19.995291] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11101 12:24:37.866637  

11102 12:24:37.867523  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11103 12:24:37.868082  start: 2.2.7 export-device-env (timeout 00:03:26) [common]
11104 12:24:37.868600  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11105 12:24:37.869077  end: 2.2 depthcharge-retry (duration 00:01:34) [common]
11106 12:24:37.869545  end: 2 depthcharge-action (duration 00:01:34) [common]
11107 12:24:37.870020  start: 3 lava-test-retry (timeout 00:08:03) [common]
11108 12:24:37.870506  start: 3.1 lava-test-shell (timeout 00:08:03) [common]
11109 12:24:37.870918  Using namespace: common
11111 12:24:37.972037  / # #

11112 12:24:37.972685  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11113 12:24:37.973250  #<4>[   20.119023] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11114 12:24:37.979050  

11115 12:24:37.979958  Using /lava-11893154
11117 12:24:38.081318  / # export SHELL=/bin/sh

11118 12:24:38.124290  export SHELL=/bin/sh<4>[   20.239071] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11119 12:24:38.124866  

11121 12:24:38.226405  / # . /lava-11893154/environment

11122 12:24:38.227178  . /lava-11893154/environment<4>[   20.359320] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11123 12:24:38.232975  

11125 12:24:38.334854  / # /lava-11893154/bin/lava-test-runner /lava-11893154/0

11126 12:24:38.335486  Test shell timeout: 10s (minimum of the action and connection timeout)
11127 12:24:38.337208  /lava-11893154/bin/lava-test-runner /lava-11893154/0<3>[   20.476463] mt7921e 0000:01:00.0: hardware init failed

11128 12:24:38.341300  

11129 12:24:38.384003  + export TESTRUN_ID=0_igt-gpu-pa<8>[   20.527987] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 11893154_1.5.2.3.1>

11130 12:24:38.384191  nfrost

11131 12:24:38.384279  + cd /lava-11893154/0/tests/0_igt-gpu-panfrost

11132 12:24:38.384362  + cat uuid

11133 12:24:38.384441  + UUID=11893154_1.5.2.3.1

11134 12:24:38.384519  + set +x

11135 12:24:38.384784  Received signal: <STARTRUN> 0_igt-gpu-panfrost 11893154_1.5.2.3.1
11136 12:24:38.384879  Starting test lava.0_igt-gpu-panfrost (11893154_1.5.2.3.1)
11137 12:24:38.384986  Skipping test definition patterns.
11138 12:24:38.392410  + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param <8>[   20.552155] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>

11139 12:24:38.392808  Received signal: <TESTSET> START panfrost_gem_new
11140 12:24:38.392935  Starting test_set panfrost_gem_new
11141 12:24:38.395404  panfrost_prime panfrost_submit

11142 12:24:38.409634  <14>[   20.569979] [IGT] panfrost_gem_new: executing

11143 12:24:38.415980  IGT-Version: 1.27.1-g621c2d3 (aa<14>[   20.576919] [IGT] panfrost_gem_new: exiting, ret=77

11144 12:24:38.420032  rch64) (Linux: 6.1.59-cip7 aarch64)

11145 12:24:38.432950  Test requirement not met in function drm_open_driver, file <8>[   20.590092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>

11146 12:24:38.433797  Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11148 12:24:38.436221  ../lib/drmtest.c:621:

11149 12:24:38.436749  Test requirement: !(fd<0)

11150 12:24:38.442691  No known gpu found for chipset flags 0x32 (panfrost)

11151 12:24:38.449563  Last errno: 2, No such file or directory<14>[   20.610340] [IGT] panfrost_gem_new: executing

11152 12:24:38.450029  

11153 12:24:38.459488  Subtest gem-new-4096: SKIP<14>[   20.617511] [IGT] panfrost_gem_new: exiting, ret=77

11154 12:24:38.460024   (0.000s)

11155 12:24:38.469077  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<8>[   20.628386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>

11156 12:24:38.470100  Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11158 12:24:38.472349  1.59-cip7 aarch64)

11159 12:24:38.479239  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11160 12:24:38.482270  Test requirement: !(fd<0)

11161 12:24:38.488755  No known gpu fo<14>[   20.648182] [IGT] panfrost_gem_new: executing

11162 12:24:38.495293  und for chipset flags 0x32 (panf<14>[   20.655310] [IGT] panfrost_gem_new: exiting, ret=77

11163 12:24:38.496023  rost)

11164 12:24:38.499195  Last errno: 2, No such file or directory

11165 12:24:38.508602  Subtest gem<8>[   20.665574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>

11166 12:24:38.509343  Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11168 12:24:38.512341  -new-0: SKIP (0.000s)

11169 12:24:38.515363  IGT-V<8>[   20.675299] <LAVA_SIGNAL_TESTSET STOP>

11170 12:24:38.516219  Received signal: <TESTSET> STOP
11171 12:24:38.516595  Closing test_set panfrost_gem_new
11172 12:24:38.521797  ersion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)

11173 12:24:38.528497  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11174 12:24:38.531843  Test requirement: !(fd<0)

11175 12:24:38.534900  No <8>[   20.695406] <LAVA_SIGNAL_TESTSET START panfrost_get_param>

11176 12:24:38.535581  Received signal: <TESTSET> START panfrost_get_param
11177 12:24:38.536027  Starting test_set panfrost_get_param
11178 12:24:38.541605  known gpu found for chipset flags 0x32 (panfrost)

11179 12:24:38.544998  Last errno: 2, No such file or directory

11180 12:24:38.548291  Subtest gem-new-zeroed: SKIP (0.000s)

11181 12:24:38.554586  <14>[   20.713439] [IGT] panfrost_get_param: executing

11182 12:24:38.561145  IGT-Version: 1.27.1-g621c2d3 (aa<14>[   20.720856] [IGT] panfrost_get_param: exiting, ret=77

11183 12:24:38.564683  rch64) (Linux: 6.1.59-cip7 aarch64)

11184 12:24:38.574376  Test requirement not met in<8>[   20.731534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>

11185 12:24:38.575307  Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11187 12:24:38.578300   function drm_open_driver, file ../lib/drmtest.c:621:

11188 12:24:38.580844  Test requirement: !(fd<0)

11189 12:24:38.587828  No known gpu found for chipset flags 0x32 (panfrost)

11190 12:24:38.590908  Last errno: 2, No such file or directory

11191 12:24:38.594319  Subtest ba<14>[   20.755246] [IGT] panfrost_get_param: executing

11192 12:24:38.597601  se-params: SKIP (0.000s)

11193 12:24:38.604756  IG<14>[   20.763371] [IGT] panfrost_get_param: exiting, ret=77

11194 12:24:38.617564  T-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64<8>[   20.773959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>

11195 12:24:38.618118  )

11196 12:24:38.618755  Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11198 12:24:38.624510  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11199 12:24:38.627934  Test requirement: !(fd<0)

11200 12:24:38.631128  No known gpu found for chipset flags 0x32 (panfrost)

11201 12:24:38.637582  Last errno: 2, No such fil<14>[   20.797729] [IGT] panfrost_get_param: executing

11202 12:24:38.640974  e or directory

11203 12:24:38.647087  Subtest get-<14>[   20.805914] [IGT] panfrost_get_param: exiting, ret=77

11204 12:24:38.650628  bad-param: SKIP (0.000s)

11205 12:24:38.660860  IGT-Version: 1.27.1-g621c2d3 (aarc<8>[   20.816705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>

11206 12:24:38.661681  Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11208 12:24:38.667047  h64) (Linux: 6.1.59-cip7 aarch64<8>[   20.826369] <LAVA_SIGNAL_TESTSET STOP>

11209 12:24:38.667514  )

11210 12:24:38.668192  Received signal: <TESTSET> STOP
11211 12:24:38.668562  Closing test_set panfrost_get_param
11212 12:24:38.673763  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11213 12:24:38.678056  Test requirement: !(fd<0)

11214 12:24:38.680097  No known gpu found for chipset flags 0x32 (panfrost)

11215 12:24:38.687134  Last errno<8>[   20.846685] <LAVA_SIGNAL_TESTSET START panfrost_prime>

11216 12:24:38.687941  Received signal: <TESTSET> START panfrost_prime
11217 12:24:38.688313  Starting test_set panfrost_prime
11218 12:24:38.690607  : 2, No such file or directory

11219 12:24:38.693610  Subtest get-bad-padding: SKIP (0.000s)

11220 12:24:38.708235  <14>[   20.868286] [IGT] panfrost_prime: executing

11221 12:24:38.714299  IGT-Version: 1.27.1-g621c2d3 (aa<14>[   20.875001] [IGT] panfrost_prime: exiting, ret=77

11222 12:24:38.717882  rch64) (Linux: 6.1.59-cip7 aarch64)

11223 12:24:38.727850  Test requirement not met in<8>[   20.885269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>

11224 12:24:38.728545  Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11226 12:24:38.734205   function drm_open_driver, file <8>[   20.895155] <LAVA_SIGNAL_TESTSET STOP>

11227 12:24:38.734884  Received signal: <TESTSET> STOP
11228 12:24:38.735235  Closing test_set panfrost_prime
11229 12:24:38.737568  ../lib/drmtest.c:621:

11230 12:24:38.741449  Test requirement: !(fd<0)

11231 12:24:38.744268  No known gpu found for chipset flags 0x32 (panfrost)

11232 12:24:38.747763  Last errno: 2, No such file or directory

11233 12:24:38.757787  Subtest gem-prime-import: <8>[   20.915323] <LAVA_SIGNAL_TESTSET START panfrost_submit>

11234 12:24:38.758221  SKIP (0.000s)

11235 12:24:38.758818  Received signal: <TESTSET> START panfrost_submit
11236 12:24:38.759180  Starting test_set panfrost_submit
11237 12:24:38.772906  <14>[   20.932976] [IGT] panfrost_submit: executing

11238 12:24:38.779499  IGT-Version: 1.27.1-g621c2d3 (aa<14>[   20.939624] [IGT] panfrost_submit: exiting, ret=77

11239 12:24:38.782690  rch64) (Linux: 6.1.59-cip7 aarch64)

11240 12:24:38.792601  Test requirement not met in<8>[   20.950425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>

11241 12:24:38.793292  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11243 12:24:38.799192   function drm_open_driver, file ../lib/drmtest.c:621:

11244 12:24:38.799610  Test requirement: !(fd<0)

11245 12:24:38.805895  No known gpu found for chipset flags 0x32 (panfrost)

11246 12:24:38.809655  Last err<14>[   20.969607] [IGT] panfrost_submit: executing

11247 12:24:38.819474  no: 2, No such file or directory<14>[   20.977061] [IGT] panfrost_submit: exiting, ret=77

11248 12:24:38.820073  

11249 12:24:38.823073  Subtest pan-submit: SKIP (0.000s)

11250 12:24:38.832231  IGT-Version: 1.27.1<8>[   20.987768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>

11251 12:24:38.833110  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11253 12:24:38.835489  -g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)

11254 12:24:38.842191  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11255 12:24:38.848517  Test require<14>[   21.008734] [IGT] panfrost_submit: executing

11256 12:24:38.849084  ment: !(fd<0)

11257 12:24:38.855250  No known gpu foun<14>[   21.015851] [IGT] panfrost_submit: exiting, ret=77

11258 12:24:38.858729  d for chipset flags 0x32 (panfrost)

11259 12:24:38.871704  Last errno: 2, No such file<8>[   21.026411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>

11260 12:24:38.872303   or directory

11261 12:24:38.873067  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11263 12:24:38.878501  Subtest pan-submit-error-no-jc: SKIP (0.000s)

11264 12:24:38.882427  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)

11265 12:24:38.888083  Test <14>[   21.047667] [IGT] panfrost_submit: executing

11266 12:24:38.895100  requirement not met in function <14>[   21.055003] [IGT] panfrost_submit: exiting, ret=77

11267 12:24:38.897849  drm_open_driver, file ../lib/drmtest.c:621:

11268 12:24:38.911627  Test requirement: !<8>[   21.065722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>

11269 12:24:38.912244  (fd<0)

11270 12:24:38.912493  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11272 12:24:38.914238  No known gpu found for chipset flags 0x32 (panfrost)

11273 12:24:38.917915  Last errno: 2, No such file or directory

11274 12:24:38.927419  Subtest pan-submit-error-bad-in-sync<14>[   21.087549] [IGT] panfrost_submit: executing

11275 12:24:38.927595  s: SKIP (0.000s)

11276 12:24:38.934156  IGT-Versio<14>[   21.094546] [IGT] panfrost_submit: exiting, ret=77

11277 12:24:38.940534  n: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)

11278 12:24:38.950499  Test <8>[   21.104862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>

11279 12:24:38.951364  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11281 12:24:38.957222  requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11282 12:24:38.957656  Test requirement: !(fd<0)

11283 12:24:38.964010  No known gpu found for chipset flags 0x32 (panfrost)

11284 12:24:38.967458  La<14>[   21.127271] [IGT] panfrost_submit: executing

11285 12:24:38.977160  st errno: 2, No such file or dir<14>[   21.135382] [IGT] panfrost_submit: exiting, ret=77

11286 12:24:38.977690  ectory

11287 12:24:38.990698  Subtest pan-submit-error-bad-bo-handles: SKIP (0.000<8>[   21.145756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>

11288 12:24:38.991293  s)

11289 12:24:38.992068  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11291 12:24:38.996920  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)

11292 12:24:39.003396  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11293 12:24:39.006588  Test requirement: !(fd<0)

11294 12:24:39.010070  No known gpu found for chipset flags 0x32 (panfrost)

11295 12:24:39.016793  Last errno: 2, No such file or d<14>[   21.178401] [IGT] panfrost_submit: executing

11296 12:24:39.019789  irectory

11297 12:24:39.026678  Subtest pan-submit-error-bad-requi<14>[   21.186603] [IGT] panfrost_submit: exiting, ret=77

11298 12:24:39.029154  rements: SKIP (0.000s)

11299 12:24:39.039503  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.5<8>[   21.198760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>

11300 12:24:39.040266  Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11302 12:24:39.043195  9-cip7 aarch64)

11303 12:24:39.049585  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11304 12:24:39.052935  Test requirement: !(fd<0)

11305 12:24:39.059659  No known gpu found for chipset fla<14>[   21.219147] [IGT] panfrost_submit: executing

11306 12:24:39.062662  gs 0x32 (panfrost)

11307 12:24:39.069069  Last errno: <14>[   21.227241] [IGT] panfrost_submit: exiting, ret=77

11308 12:24:39.069502  2, No such file or directory

11309 12:24:39.082688  Subtest pan-submit-error-bad-o<8>[   21.237610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>

11310 12:24:39.083262  ut-sync: SKIP (0.000s)

11311 12:24:39.084137  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11313 12:24:39.089123  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)

11314 12:24:39.099406  Test requirement not met in function drm_open_d<14>[   21.258023] [IGT] panfrost_submit: executing

11315 12:24:39.105606  river, file ../lib/drmtest.c:621<14>[   21.265431] [IGT] panfrost_submit: exiting, ret=77

11316 12:24:39.106169  :

11317 12:24:39.109102  Test requirement: !(fd<0)

11318 12:24:39.118873  No known gpu found for chipset fla<8>[   21.275958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>

11319 12:24:39.119622  Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11321 12:24:39.122341  gs 0x32 (panfrost)

11322 12:24:39.125772  Last errno: <8>[   21.286472] <LAVA_SIGNAL_TESTSET STOP>

11323 12:24:39.126603  Received signal: <TESTSET> STOP
11324 12:24:39.127007  Closing test_set panfrost_submit
11325 12:24:39.135285  2, No such file <8>[   21.293058] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 11893154_1.5.2.3.1>

11326 12:24:39.135893  or directory

11327 12:24:39.136540  Received signal: <ENDRUN> 0_igt-gpu-panfrost 11893154_1.5.2.3.1
11328 12:24:39.136970  Ending use of test pattern.
11329 12:24:39.137310  Ending test lava.0_igt-gpu-panfrost (11893154_1.5.2.3.1), duration 0.75
11331 12:24:39.139242  Subtest pan-reset: SKIP (0.000s)

11332 12:24:39.145070  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)

11333 12:24:39.151981  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11334 12:24:39.155152  Test requirement: !(fd<0)

11335 12:24:39.158325  No known gpu found for chipset flags 0x32 (panfrost)

11336 12:24:39.165023  Last errno: 2, No such file or directory

11337 12:24:39.168440  Subtest pan-submit-and-close: SKIP (0.000s)

11338 12:24:39.174853  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)

11339 12:24:39.181462  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11340 12:24:39.184862  Test requirement: !(fd<0)

11341 12:24:39.188095  No known gpu found for chipset flags 0x32 (panfrost)

11342 12:24:39.191162  Last errno: 2, No such file or directory

11343 12:24:39.197728  Subtest pan-unhandled-pagefault: SKIP (0.000s)

11344 12:24:39.198144  + set +x

11345 12:24:39.198747  ok: lava_test_shell seems to have completed
11346 12:24:39.200420  base-params:
  result: skip
  set: panfrost_get_param
gem-new-0:
  result: skip
  set: panfrost_gem_new
gem-new-4096:
  result: skip
  set: panfrost_gem_new
gem-new-zeroed:
  result: skip
  set: panfrost_gem_new
gem-prime-import:
  result: skip
  set: panfrost_prime
get-bad-padding:
  result: skip
  set: panfrost_get_param
get-bad-param:
  result: skip
  set: panfrost_get_param
pan-reset:
  result: skip
  set: panfrost_submit
pan-submit:
  result: skip
  set: panfrost_submit
pan-submit-and-close:
  result: skip
  set: panfrost_submit
pan-submit-error-bad-bo-handles:
  result: skip
  set: panfrost_submit
pan-submit-error-bad-in-syncs:
  result: skip
  set: panfrost_submit
pan-submit-error-bad-out-sync:
  result: skip
  set: panfrost_submit
pan-submit-error-bad-requirements:
  result: skip
  set: panfrost_submit
pan-submit-error-no-jc:
  result: skip
  set: panfrost_submit
pan-unhandled-pagefault:
  result: skip
  set: panfrost_submit

11347 12:24:39.200906  end: 3.1 lava-test-shell (duration 00:00:01) [common]
11348 12:24:39.201344  end: 3 lava-test-retry (duration 00:00:01) [common]
11349 12:24:39.201785  start: 4 finalize (timeout 00:08:02) [common]
11350 12:24:39.202241  start: 4.1 power-off (timeout 00:00:30) [common]
11351 12:24:39.202975  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11352 12:24:39.325357  >> Command sent successfully.

11353 12:24:39.336447  Returned 0 in 0 seconds
11354 12:24:39.437848  end: 4.1 power-off (duration 00:00:00) [common]
11356 12:24:39.439592  start: 4.2 read-feedback (timeout 00:08:01) [common]
11358 12:24:39.442073  Listened to connection for namespace 'common' for up to 1s
11359 12:24:40.441688  Finalising connection for namespace 'common'
11360 12:24:40.442342  Disconnecting from shell: Finalise
11361 12:24:40.442739  / # 
11362 12:24:40.543789  end: 4.2 read-feedback (duration 00:00:01) [common]
11363 12:24:40.544532  end: 4 finalize (duration 00:00:01) [common]
11364 12:24:40.545164  Cleaning after the job
11365 12:24:40.545761  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/ramdisk
11366 12:24:40.579377  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/kernel
11367 12:24:40.594930  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/dtb
11368 12:24:40.595200  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893154/tftp-deploy-7d4b6xp8/modules
11369 12:24:40.604643  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893154
11370 12:24:40.722651  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893154
11371 12:24:40.722830  Job finished correctly