Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 20
- Kernel Errors: 34
- Errors: 0
- Boot result: PASS
1 12:16:12.894852 lava-dispatcher, installed at version: 2023.08
2 12:16:12.895067 start: 0 validate
3 12:16:12.895194 Start time: 2023-10-27 12:16:12.895186+00:00 (UTC)
4 12:16:12.895314 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:16:12.895484 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:16:13.164508 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:16:13.164677 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:16:50.467220 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:16:50.468049 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:16:50.738839 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:16:50.739161 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:16:53.512488 validate duration: 40.62
14 12:16:53.512767 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:16:53.512866 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:16:53.512958 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:16:53.513091 Not decompressing ramdisk as can be used compressed.
18 12:16:53.513177 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 12:16:53.513244 saving as /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/ramdisk/rootfs.cpio.gz
20 12:16:53.513309 total size: 43284872 (41 MB)
21 12:16:53.772877 progress 0 % (0 MB)
22 12:16:53.790570 progress 5 % (2 MB)
23 12:16:53.807973 progress 10 % (4 MB)
24 12:16:53.821986 progress 15 % (6 MB)
25 12:16:53.833551 progress 20 % (8 MB)
26 12:16:53.845172 progress 25 % (10 MB)
27 12:16:53.856881 progress 30 % (12 MB)
28 12:16:53.869537 progress 35 % (14 MB)
29 12:16:53.882230 progress 40 % (16 MB)
30 12:16:53.893502 progress 45 % (18 MB)
31 12:16:53.904806 progress 50 % (20 MB)
32 12:16:53.916128 progress 55 % (22 MB)
33 12:16:53.927631 progress 60 % (24 MB)
34 12:16:53.939000 progress 65 % (26 MB)
35 12:16:53.950361 progress 70 % (28 MB)
36 12:16:53.961817 progress 75 % (30 MB)
37 12:16:53.973377 progress 80 % (33 MB)
38 12:16:53.985092 progress 85 % (35 MB)
39 12:16:53.996567 progress 90 % (37 MB)
40 12:16:54.007673 progress 95 % (39 MB)
41 12:16:54.018733 progress 100 % (41 MB)
42 12:16:54.019037 41 MB downloaded in 0.51 s (81.62 MB/s)
43 12:16:54.019208 end: 1.1.1 http-download (duration 00:00:01) [common]
45 12:16:54.019502 end: 1.1 download-retry (duration 00:00:01) [common]
46 12:16:54.019593 start: 1.2 download-retry (timeout 00:09:59) [common]
47 12:16:54.019678 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 12:16:54.019821 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:16:54.019893 saving as /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/kernel/Image
50 12:16:54.019957 total size: 49236480 (46 MB)
51 12:16:54.020024 No compression specified
52 12:16:54.021144 progress 0 % (0 MB)
53 12:16:54.034117 progress 5 % (2 MB)
54 12:16:54.046886 progress 10 % (4 MB)
55 12:16:54.060017 progress 15 % (7 MB)
56 12:16:54.072881 progress 20 % (9 MB)
57 12:16:54.085808 progress 25 % (11 MB)
58 12:16:54.099044 progress 30 % (14 MB)
59 12:16:54.112196 progress 35 % (16 MB)
60 12:16:54.125202 progress 40 % (18 MB)
61 12:16:54.138110 progress 45 % (21 MB)
62 12:16:54.151067 progress 50 % (23 MB)
63 12:16:54.164105 progress 55 % (25 MB)
64 12:16:54.177040 progress 60 % (28 MB)
65 12:16:54.189944 progress 65 % (30 MB)
66 12:16:54.203021 progress 70 % (32 MB)
67 12:16:54.216153 progress 75 % (35 MB)
68 12:16:54.229422 progress 80 % (37 MB)
69 12:16:54.242340 progress 85 % (39 MB)
70 12:16:54.255354 progress 90 % (42 MB)
71 12:16:54.268077 progress 95 % (44 MB)
72 12:16:54.280651 progress 100 % (46 MB)
73 12:16:54.280905 46 MB downloaded in 0.26 s (179.95 MB/s)
74 12:16:54.281084 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:16:54.281318 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:16:54.281458 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:16:54.281600 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:16:54.281740 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:16:54.281809 saving as /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/dtb/mt8192-asurada-spherion-r0.dtb
81 12:16:54.281874 total size: 47278 (0 MB)
82 12:16:54.281937 No compression specified
83 12:16:54.283098 progress 69 % (0 MB)
84 12:16:54.283375 progress 100 % (0 MB)
85 12:16:54.283574 0 MB downloaded in 0.00 s (26.56 MB/s)
86 12:16:54.283698 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:16:54.283942 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:16:54.284077 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:16:54.284161 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:16:54.284275 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:16:54.284344 saving as /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/modules/modules.tar
93 12:16:54.284405 total size: 8625084 (8 MB)
94 12:16:54.284466 Using unxz to decompress xz
95 12:16:54.288746 progress 0 % (0 MB)
96 12:16:54.310339 progress 5 % (0 MB)
97 12:16:54.332769 progress 10 % (0 MB)
98 12:16:54.359309 progress 15 % (1 MB)
99 12:16:54.385079 progress 20 % (1 MB)
100 12:16:54.410794 progress 25 % (2 MB)
101 12:16:54.437290 progress 30 % (2 MB)
102 12:16:54.464513 progress 35 % (2 MB)
103 12:16:54.491355 progress 40 % (3 MB)
104 12:16:54.516321 progress 45 % (3 MB)
105 12:16:54.543060 progress 50 % (4 MB)
106 12:16:54.568458 progress 55 % (4 MB)
107 12:16:54.593719 progress 60 % (4 MB)
108 12:16:54.618979 progress 65 % (5 MB)
109 12:16:54.644497 progress 70 % (5 MB)
110 12:16:54.668812 progress 75 % (6 MB)
111 12:16:54.695281 progress 80 % (6 MB)
112 12:16:54.725009 progress 85 % (7 MB)
113 12:16:54.752827 progress 90 % (7 MB)
114 12:16:54.778982 progress 95 % (7 MB)
115 12:16:54.802618 progress 100 % (8 MB)
116 12:16:54.807502 8 MB downloaded in 0.52 s (15.72 MB/s)
117 12:16:54.807769 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:16:54.808038 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:16:54.808135 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:16:54.808234 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:16:54.808316 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:16:54.808401 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:16:54.808644 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv
125 12:16:54.808785 makedir: /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin
126 12:16:54.808895 makedir: /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/tests
127 12:16:54.808995 makedir: /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/results
128 12:16:54.809119 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-add-keys
129 12:16:54.809271 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-add-sources
130 12:16:54.809405 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-background-process-start
131 12:16:54.809537 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-background-process-stop
132 12:16:54.809670 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-common-functions
133 12:16:54.809848 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-echo-ipv4
134 12:16:54.810007 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-install-packages
135 12:16:54.810138 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-installed-packages
136 12:16:54.810266 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-os-build
137 12:16:54.810399 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-probe-channel
138 12:16:54.810527 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-probe-ip
139 12:16:54.810654 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-target-ip
140 12:16:54.810780 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-target-mac
141 12:16:54.810909 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-target-storage
142 12:16:54.811045 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-test-case
143 12:16:54.811174 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-test-event
144 12:16:54.811300 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-test-feedback
145 12:16:54.811466 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-test-raise
146 12:16:54.811601 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-test-reference
147 12:16:54.811730 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-test-runner
148 12:16:54.811858 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-test-set
149 12:16:54.811988 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-test-shell
150 12:16:54.812118 Updating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-install-packages (oe)
151 12:16:54.812302 Updating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/bin/lava-installed-packages (oe)
152 12:16:54.812468 Creating /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/environment
153 12:16:54.812572 LAVA metadata
154 12:16:54.812648 - LAVA_JOB_ID=11893121
155 12:16:54.812715 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:16:54.812819 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:16:54.812894 skipped lava-vland-overlay
158 12:16:54.812970 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:16:54.813054 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:16:54.813118 skipped lava-multinode-overlay
161 12:16:54.813195 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:16:54.813280 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:16:54.813356 Loading test definitions
164 12:16:54.813452 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:16:54.813546 Using /lava-11893121 at stage 0
166 12:16:54.813860 uuid=11893121_1.5.2.3.1 testdef=None
167 12:16:54.813949 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:16:54.814040 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:16:54.814581 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:16:54.814813 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:16:54.815563 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:16:54.815800 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:16:54.816412 runner path: /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/0/tests/0_igt-kms-mediatek test_uuid 11893121_1.5.2.3.1
176 12:16:54.816575 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:16:54.816789 Creating lava-test-runner.conf files
179 12:16:54.816853 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893121/lava-overlay-wfqdjpwv/lava-11893121/0 for stage 0
180 12:16:54.816953 - 0_igt-kms-mediatek
181 12:16:54.817051 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:16:54.817137 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:16:54.824083 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:16:54.824217 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:16:54.824311 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:16:54.824399 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:16:54.824499 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:16:56.257794 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:16:56.258186 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 12:16:56.258307 extracting modules file /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893121/extract-overlay-ramdisk-jwd_bgct/ramdisk
191 12:16:56.492007 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:16:56.492177 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:16:56.492273 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893121/compress-overlay-449bj5ia/overlay-1.5.2.4.tar.gz to ramdisk
194 12:16:56.492347 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893121/compress-overlay-449bj5ia/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893121/extract-overlay-ramdisk-jwd_bgct/ramdisk
195 12:16:56.499154 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:16:56.499274 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:16:56.499365 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:16:56.499517 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:16:56.499599 Building ramdisk /var/lib/lava/dispatcher/tmp/11893121/extract-overlay-ramdisk-jwd_bgct/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893121/extract-overlay-ramdisk-jwd_bgct/ramdisk
200 12:16:57.541116 >> 369948 blocks
201 12:17:03.345645 rename /var/lib/lava/dispatcher/tmp/11893121/extract-overlay-ramdisk-jwd_bgct/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/ramdisk/ramdisk.cpio.gz
202 12:17:03.346286 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:17:03.346510 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 12:17:03.346708 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 12:17:03.346900 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/kernel/Image'
206 12:17:15.976970 Returned 0 in 12 seconds
207 12:17:16.077617 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/kernel/image.itb
208 12:17:16.904121 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:17:16.904500 output: Created: Fri Oct 27 13:17:16 2023
210 12:17:16.904578 output: Image 0 (kernel-1)
211 12:17:16.904645 output: Description:
212 12:17:16.904710 output: Created: Fri Oct 27 13:17:16 2023
213 12:17:16.904772 output: Type: Kernel Image
214 12:17:16.904832 output: Compression: lzma compressed
215 12:17:16.904894 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
216 12:17:16.904955 output: Architecture: AArch64
217 12:17:16.905015 output: OS: Linux
218 12:17:16.905075 output: Load Address: 0x00000000
219 12:17:16.905136 output: Entry Point: 0x00000000
220 12:17:16.905197 output: Hash algo: crc32
221 12:17:16.905256 output: Hash value: d33b93ae
222 12:17:16.905315 output: Image 1 (fdt-1)
223 12:17:16.905371 output: Description: mt8192-asurada-spherion-r0
224 12:17:16.905426 output: Created: Fri Oct 27 13:17:16 2023
225 12:17:16.905480 output: Type: Flat Device Tree
226 12:17:16.905535 output: Compression: uncompressed
227 12:17:16.905588 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:17:16.905642 output: Architecture: AArch64
229 12:17:16.905696 output: Hash algo: crc32
230 12:17:16.905749 output: Hash value: cc4352de
231 12:17:16.905803 output: Image 2 (ramdisk-1)
232 12:17:16.905855 output: Description: unavailable
233 12:17:16.905908 output: Created: Fri Oct 27 13:17:16 2023
234 12:17:16.905962 output: Type: RAMDisk Image
235 12:17:16.906015 output: Compression: Unknown Compression
236 12:17:16.906068 output: Data Size: 56410424 Bytes = 55088.30 KiB = 53.80 MiB
237 12:17:16.906122 output: Architecture: AArch64
238 12:17:16.906175 output: OS: Linux
239 12:17:16.906229 output: Load Address: unavailable
240 12:17:16.906282 output: Entry Point: unavailable
241 12:17:16.906335 output: Hash algo: crc32
242 12:17:16.906388 output: Hash value: 9b8af289
243 12:17:16.906441 output: Default Configuration: 'conf-1'
244 12:17:16.906494 output: Configuration 0 (conf-1)
245 12:17:16.906546 output: Description: mt8192-asurada-spherion-r0
246 12:17:16.906600 output: Kernel: kernel-1
247 12:17:16.906652 output: Init Ramdisk: ramdisk-1
248 12:17:16.906705 output: FDT: fdt-1
249 12:17:16.906758 output: Loadables: kernel-1
250 12:17:16.906811 output:
251 12:17:16.907013 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:17:16.907112 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:17:16.907214 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 12:17:16.907313 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 12:17:16.907422 No LXC device requested
256 12:17:16.907521 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:17:16.907609 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 12:17:16.907690 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:17:16.907766 Checking files for TFTP limit of 4294967296 bytes.
260 12:17:16.908271 end: 1 tftp-deploy (duration 00:00:23) [common]
261 12:17:16.908375 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:17:16.908464 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:17:16.908583 substitutions:
264 12:17:16.908654 - {DTB}: 11893121/tftp-deploy-10zv6gap/dtb/mt8192-asurada-spherion-r0.dtb
265 12:17:16.908722 - {INITRD}: 11893121/tftp-deploy-10zv6gap/ramdisk/ramdisk.cpio.gz
266 12:17:16.908782 - {KERNEL}: 11893121/tftp-deploy-10zv6gap/kernel/Image
267 12:17:16.908840 - {LAVA_MAC}: None
268 12:17:16.908897 - {PRESEED_CONFIG}: None
269 12:17:16.908955 - {PRESEED_LOCAL}: None
270 12:17:16.909011 - {RAMDISK}: 11893121/tftp-deploy-10zv6gap/ramdisk/ramdisk.cpio.gz
271 12:17:16.909068 - {ROOT_PART}: None
272 12:17:16.909123 - {ROOT}: None
273 12:17:16.909178 - {SERVER_IP}: 192.168.201.1
274 12:17:16.909232 - {TEE}: None
275 12:17:16.909287 Parsed boot commands:
276 12:17:16.909341 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:17:16.909521 Parsed boot commands: tftpboot 192.168.201.1 11893121/tftp-deploy-10zv6gap/kernel/image.itb 11893121/tftp-deploy-10zv6gap/kernel/cmdline
278 12:17:16.909611 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:17:16.909699 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:17:16.909793 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:17:16.909880 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:17:16.909956 Not connected, no need to disconnect.
283 12:17:16.910032 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:17:16.910116 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:17:16.910185 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 12:17:16.914154 Setting prompt string to ['lava-test: # ']
287 12:17:16.914515 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:17:16.914622 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:17:16.914720 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:17:16.914850 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:17:16.915077 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 12:17:22.051814 >> Command sent successfully.
293 12:17:22.054272 Returned 0 in 5 seconds
294 12:17:22.154650 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:17:22.154975 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:17:22.155074 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:17:22.155164 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:17:22.155232 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:17:22.155298 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:17:22.155576 [Enter `^Ec?' for help]
302 12:17:22.326076
303 12:17:22.326241
304 12:17:22.326316 F0: 102B 0000
305 12:17:22.326383
306 12:17:22.326443 F3: 1001 0000 [0200]
307 12:17:22.326504
308 12:17:22.329819 F3: 1001 0000
309 12:17:22.329905
310 12:17:22.329971 F7: 102D 0000
311 12:17:22.330033
312 12:17:22.333208 F1: 0000 0000
313 12:17:22.333298
314 12:17:22.333369 V0: 0000 0000 [0001]
315 12:17:22.333432
316 12:17:22.333493 00: 0007 8000
317 12:17:22.333556
318 12:17:22.337506 01: 0000 0000
319 12:17:22.337593
320 12:17:22.337660 BP: 0C00 0209 [0000]
321 12:17:22.337721
322 12:17:22.340960 G0: 1182 0000
323 12:17:22.341049
324 12:17:22.341116 EC: 0000 0021 [4000]
325 12:17:22.341179
326 12:17:22.344301 S7: 0000 0000 [0000]
327 12:17:22.344386
328 12:17:22.344452 CC: 0000 0000 [0001]
329 12:17:22.344514
330 12:17:22.347958 T0: 0000 0040 [010F]
331 12:17:22.348046
332 12:17:22.348112 Jump to BL
333 12:17:22.348174
334 12:17:22.373181
335 12:17:22.373345
336 12:17:22.373575
337 12:17:22.379810 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:17:22.383810 ARM64: Exception handlers installed.
339 12:17:22.387380 ARM64: Testing exception
340 12:17:22.390916 ARM64: Done test exception
341 12:17:22.398262 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:17:22.409157 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:17:22.412852 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:17:22.423686 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:17:22.430519 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:17:22.440435 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:17:22.451415 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:17:22.457840 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:17:22.475951 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:17:22.479264 WDT: Last reset was cold boot
351 12:17:22.482190 SPI1(PAD0) initialized at 2873684 Hz
352 12:17:22.486017 SPI5(PAD0) initialized at 992727 Hz
353 12:17:22.489268 VBOOT: Loading verstage.
354 12:17:22.495848 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:17:22.499311 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:17:22.502193 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:17:22.505424 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:17:22.513090 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:17:22.519871 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:17:22.530733 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:17:22.530819
362 12:17:22.530884
363 12:17:22.540658 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:17:22.544157 ARM64: Exception handlers installed.
365 12:17:22.547546 ARM64: Testing exception
366 12:17:22.547631 ARM64: Done test exception
367 12:17:22.554632 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:17:22.557955 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:17:22.572152 Probing TPM: . done!
370 12:17:22.572245 TPM ready after 0 ms
371 12:17:22.578648 Connected to device vid:did:rid of 1ae0:0028:00
372 12:17:22.585584 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:17:22.626680 Initialized TPM device CR50 revision 0
374 12:17:22.638192 tlcl_send_startup: Startup return code is 0
375 12:17:22.638302 TPM: setup succeeded
376 12:17:22.650333 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:17:22.658587 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:17:22.670261 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:17:22.680191 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:17:22.683138 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:17:22.687224 in-header: 03 07 00 00 08 00 00 00
382 12:17:22.690742 in-data: aa e4 47 04 13 02 00 00
383 12:17:22.694007 Chrome EC: UHEPI supported
384 12:17:22.700635 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:17:22.704910 in-header: 03 9d 00 00 08 00 00 00
386 12:17:22.709225 in-data: 10 20 20 08 00 00 00 00
387 12:17:22.709312 Phase 1
388 12:17:22.712412 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:17:22.719945 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:17:22.727220 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:17:22.727308 Recovery requested (1009000e)
392 12:17:22.735725 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:17:22.741320 tlcl_extend: response is 0
394 12:17:22.749440 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:17:22.754857 tlcl_extend: response is 0
396 12:17:22.761783 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:17:22.782827 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:17:22.789491 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:17:22.789595
400 12:17:22.789663
401 12:17:22.800535 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:17:22.800629 ARM64: Exception handlers installed.
403 12:17:22.804021 ARM64: Testing exception
404 12:17:22.807213 ARM64: Done test exception
405 12:17:22.827580 pmic_efuse_setting: Set efuses in 11 msecs
406 12:17:22.831784 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:17:22.835077 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:17:22.842751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:17:22.846447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:17:22.850489 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:17:22.857995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:17:22.861141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:17:22.864694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:17:22.871581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:17:22.875263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:17:22.878379 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:17:22.885035 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:17:22.888465 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:17:22.891599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:17:22.899068 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:17:22.905813 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:17:22.912362 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:17:22.915513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:17:22.922128 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:17:22.929168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:17:22.933376 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:17:22.941289 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:17:22.943775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:17:22.950784 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:17:22.958129 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:17:22.961387 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:17:22.967554 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:17:22.971135 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:17:22.977700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:17:22.981666 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:17:22.984763 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:17:22.992433 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:17:22.995679 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:17:23.003332 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:17:23.006638 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:17:23.010350 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:17:23.017682 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:17:23.021185 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:17:23.024592 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:17:23.031217 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:17:23.034741 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:17:23.038148 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:17:23.044535 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:17:23.048096 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:17:23.051791 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:17:23.057770 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:17:23.061188 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:17:23.064785 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:17:23.071707 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:17:23.075014 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:17:23.078201 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:17:23.081509 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:17:23.091799 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:17:23.098589 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:17:23.104716 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:17:23.111579 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:17:23.121963 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:17:23.125241 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:17:23.128165 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:17:23.135043 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:17:23.141567 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5
467 12:17:23.144825 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:17:23.151673 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 12:17:23.154986 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:17:23.164401 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 12:17:23.167793 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 12:17:23.174554 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 12:17:23.178047 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 12:17:23.181370 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 12:17:23.184717 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 12:17:23.187823 ADC[4]: Raw value=895191 ID=7
477 12:17:23.191091 ADC[3]: Raw value=212700 ID=1
478 12:17:23.194762 RAM Code: 0x71
479 12:17:23.198170 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 12:17:23.201044 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 12:17:23.211419 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 12:17:23.218392 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 12:17:23.221749 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 12:17:23.225138 in-header: 03 07 00 00 08 00 00 00
485 12:17:23.228181 in-data: aa e4 47 04 13 02 00 00
486 12:17:23.231992 Chrome EC: UHEPI supported
487 12:17:23.235417 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 12:17:23.239320 in-header: 03 d5 00 00 08 00 00 00
489 12:17:23.243108 in-data: 98 20 60 08 00 00 00 00
490 12:17:23.246868 MRC: failed to locate region type 0.
491 12:17:23.254664 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 12:17:23.258165 DRAM-K: Running full calibration
493 12:17:23.261521 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 12:17:23.265009 header.status = 0x0
495 12:17:23.268608 header.version = 0x6 (expected: 0x6)
496 12:17:23.272347 header.size = 0xd00 (expected: 0xd00)
497 12:17:23.272430 header.flags = 0x0
498 12:17:23.279374 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 12:17:23.297030 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 12:17:23.304575 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 12:17:23.307552 dram_init: ddr_geometry: 2
502 12:17:23.307638 [EMI] MDL number = 2
503 12:17:23.311696 [EMI] Get MDL freq = 0
504 12:17:23.311779 dram_init: ddr_type: 0
505 12:17:23.315330 is_discrete_lpddr4: 1
506 12:17:23.319279 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 12:17:23.319378
508 12:17:23.319469
509 12:17:23.322881 [Bian_co] ETT version 0.0.0.1
510 12:17:23.326106 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 12:17:23.326190
512 12:17:23.329715 dramc_set_vcore_voltage set vcore to 650000
513 12:17:23.334050 Read voltage for 800, 4
514 12:17:23.334133 Vio18 = 0
515 12:17:23.334199 Vcore = 650000
516 12:17:23.334261 Vdram = 0
517 12:17:23.337669 Vddq = 0
518 12:17:23.337752 Vmddr = 0
519 12:17:23.340899 dram_init: config_dvfs: 1
520 12:17:23.344655 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 12:17:23.348416 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 12:17:23.352439 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 12:17:23.355993 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 12:17:23.362291 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 12:17:23.365442 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 12:17:23.365526 MEM_TYPE=3, freq_sel=18
527 12:17:23.369271 sv_algorithm_assistance_LP4_1600
528 12:17:23.375493 ============ PULL DRAM RESETB DOWN ============
529 12:17:23.379079 ========== PULL DRAM RESETB DOWN end =========
530 12:17:23.382474 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 12:17:23.385709 ===================================
532 12:17:23.388866 LPDDR4 DRAM CONFIGURATION
533 12:17:23.392237 ===================================
534 12:17:23.392320 EX_ROW_EN[0] = 0x0
535 12:17:23.396105 EX_ROW_EN[1] = 0x0
536 12:17:23.398672 LP4Y_EN = 0x0
537 12:17:23.398755 WORK_FSP = 0x0
538 12:17:23.402503 WL = 0x2
539 12:17:23.402587 RL = 0x2
540 12:17:23.405499 BL = 0x2
541 12:17:23.405582 RPST = 0x0
542 12:17:23.409214 RD_PRE = 0x0
543 12:17:23.409297 WR_PRE = 0x1
544 12:17:23.412390 WR_PST = 0x0
545 12:17:23.412473 DBI_WR = 0x0
546 12:17:23.415369 DBI_RD = 0x0
547 12:17:23.415490 OTF = 0x1
548 12:17:23.418957 ===================================
549 12:17:23.422180 ===================================
550 12:17:23.425504 ANA top config
551 12:17:23.428869 ===================================
552 12:17:23.428953 DLL_ASYNC_EN = 0
553 12:17:23.432367 ALL_SLAVE_EN = 1
554 12:17:23.435878 NEW_RANK_MODE = 1
555 12:17:23.438764 DLL_IDLE_MODE = 1
556 12:17:23.438848 LP45_APHY_COMB_EN = 1
557 12:17:23.442389 TX_ODT_DIS = 1
558 12:17:23.445661 NEW_8X_MODE = 1
559 12:17:23.449040 ===================================
560 12:17:23.452112 ===================================
561 12:17:23.455751 data_rate = 1600
562 12:17:23.459020 CKR = 1
563 12:17:23.462059 DQ_P2S_RATIO = 8
564 12:17:23.465555 ===================================
565 12:17:23.465640 CA_P2S_RATIO = 8
566 12:17:23.468683 DQ_CA_OPEN = 0
567 12:17:23.472024 DQ_SEMI_OPEN = 0
568 12:17:23.475563 CA_SEMI_OPEN = 0
569 12:17:23.478825 CA_FULL_RATE = 0
570 12:17:23.478909 DQ_CKDIV4_EN = 1
571 12:17:23.482071 CA_CKDIV4_EN = 1
572 12:17:23.485982 CA_PREDIV_EN = 0
573 12:17:23.489065 PH8_DLY = 0
574 12:17:23.492272 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 12:17:23.495572 DQ_AAMCK_DIV = 4
576 12:17:23.495684 CA_AAMCK_DIV = 4
577 12:17:23.498759 CA_ADMCK_DIV = 4
578 12:17:23.502023 DQ_TRACK_CA_EN = 0
579 12:17:23.505488 CA_PICK = 800
580 12:17:23.509005 CA_MCKIO = 800
581 12:17:23.512425 MCKIO_SEMI = 0
582 12:17:23.515512 PLL_FREQ = 3068
583 12:17:23.515595 DQ_UI_PI_RATIO = 32
584 12:17:23.518749 CA_UI_PI_RATIO = 0
585 12:17:23.522531 ===================================
586 12:17:23.525776 ===================================
587 12:17:23.529066 memory_type:LPDDR4
588 12:17:23.531969 GP_NUM : 10
589 12:17:23.532052 SRAM_EN : 1
590 12:17:23.535665 MD32_EN : 0
591 12:17:23.539066 ===================================
592 12:17:23.542274 [ANA_INIT] >>>>>>>>>>>>>>
593 12:17:23.542358 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 12:17:23.545430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 12:17:23.549339 ===================================
596 12:17:23.552523 data_rate = 1600,PCW = 0X7600
597 12:17:23.556066 ===================================
598 12:17:23.560612 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:17:23.564153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 12:17:23.571345 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 12:17:23.574947 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 12:17:23.578499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 12:17:23.582241 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 12:17:23.585738 [ANA_INIT] flow start
605 12:17:23.585823 [ANA_INIT] PLL >>>>>>>>
606 12:17:23.589254 [ANA_INIT] PLL <<<<<<<<
607 12:17:23.592855 [ANA_INIT] MIDPI >>>>>>>>
608 12:17:23.592939 [ANA_INIT] MIDPI <<<<<<<<
609 12:17:23.596344 [ANA_INIT] DLL >>>>>>>>
610 12:17:23.596430 [ANA_INIT] flow end
611 12:17:23.600621 ============ LP4 DIFF to SE enter ============
612 12:17:23.607977 ============ LP4 DIFF to SE exit ============
613 12:17:23.608062 [ANA_INIT] <<<<<<<<<<<<<
614 12:17:23.611197 [Flow] Enable top DCM control >>>>>
615 12:17:23.614698 [Flow] Enable top DCM control <<<<<
616 12:17:23.618491 Enable DLL master slave shuffle
617 12:17:23.622391 ==============================================================
618 12:17:23.626196 Gating Mode config
619 12:17:23.629714 ==============================================================
620 12:17:23.633533 Config description:
621 12:17:23.640618 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 12:17:23.648358 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 12:17:23.652212 SELPH_MODE 0: By rank 1: By Phase
624 12:17:23.659339 ==============================================================
625 12:17:23.662758 GAT_TRACK_EN = 1
626 12:17:23.666604 RX_GATING_MODE = 2
627 12:17:23.666687 RX_GATING_TRACK_MODE = 2
628 12:17:23.670286 SELPH_MODE = 1
629 12:17:23.674466 PICG_EARLY_EN = 1
630 12:17:23.678036 VALID_LAT_VALUE = 1
631 12:17:23.682145 ==============================================================
632 12:17:23.685633 Enter into Gating configuration >>>>
633 12:17:23.688939 Exit from Gating configuration <<<<
634 12:17:23.693184 Enter into DVFS_PRE_config >>>>>
635 12:17:23.704174 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 12:17:23.708017 Exit from DVFS_PRE_config <<<<<
637 12:17:23.711253 Enter into PICG configuration >>>>
638 12:17:23.711362 Exit from PICG configuration <<<<
639 12:17:23.715076 [RX_INPUT] configuration >>>>>
640 12:17:23.718232 [RX_INPUT] configuration <<<<<
641 12:17:23.722201 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 12:17:23.729479 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 12:17:23.737239 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 12:17:23.740174 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 12:17:23.747480 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 12:17:23.755246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 12:17:23.758653 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 12:17:23.762314 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 12:17:23.766145 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 12:17:23.769687 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 12:17:23.772873 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 12:17:23.776873 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 12:17:23.781195 ===================================
654 12:17:23.784451 LPDDR4 DRAM CONFIGURATION
655 12:17:23.788464 ===================================
656 12:17:23.788549 EX_ROW_EN[0] = 0x0
657 12:17:23.792517 EX_ROW_EN[1] = 0x0
658 12:17:23.792601 LP4Y_EN = 0x0
659 12:17:23.795817 WORK_FSP = 0x0
660 12:17:23.795902 WL = 0x2
661 12:17:23.799630 RL = 0x2
662 12:17:23.799726 BL = 0x2
663 12:17:23.803117 RPST = 0x0
664 12:17:23.803201 RD_PRE = 0x0
665 12:17:23.807200 WR_PRE = 0x1
666 12:17:23.807284 WR_PST = 0x0
667 12:17:23.807350 DBI_WR = 0x0
668 12:17:23.811048 DBI_RD = 0x0
669 12:17:23.811131 OTF = 0x1
670 12:17:23.814398 ===================================
671 12:17:23.818663 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 12:17:23.822424 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 12:17:23.829654 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 12:17:23.833049 ===================================
675 12:17:23.833134 LPDDR4 DRAM CONFIGURATION
676 12:17:23.837083 ===================================
677 12:17:23.840791 EX_ROW_EN[0] = 0x10
678 12:17:23.840876 EX_ROW_EN[1] = 0x0
679 12:17:23.843946 LP4Y_EN = 0x0
680 12:17:23.844030 WORK_FSP = 0x0
681 12:17:23.847730 WL = 0x2
682 12:17:23.847815 RL = 0x2
683 12:17:23.851763 BL = 0x2
684 12:17:23.851849 RPST = 0x0
685 12:17:23.855269 RD_PRE = 0x0
686 12:17:23.855353 WR_PRE = 0x1
687 12:17:23.855463 WR_PST = 0x0
688 12:17:23.859266 DBI_WR = 0x0
689 12:17:23.859350 DBI_RD = 0x0
690 12:17:23.862846 OTF = 0x1
691 12:17:23.866498 ===================================
692 12:17:23.870282 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 12:17:23.875296 nWR fixed to 40
694 12:17:23.878817 [ModeRegInit_LP4] CH0 RK0
695 12:17:23.878902 [ModeRegInit_LP4] CH0 RK1
696 12:17:23.882916 [ModeRegInit_LP4] CH1 RK0
697 12:17:23.883001 [ModeRegInit_LP4] CH1 RK1
698 12:17:23.886256 match AC timing 13
699 12:17:23.890397 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 12:17:23.893727 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 12:17:23.897596 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 12:17:23.904164 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 12:17:23.907602 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 12:17:23.911189 [EMI DOE] emi_dcm 0
705 12:17:23.913944 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 12:17:23.914044 ==
707 12:17:23.917353 Dram Type= 6, Freq= 0, CH_0, rank 0
708 12:17:23.920761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 12:17:23.920847 ==
710 12:17:23.927322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 12:17:23.933689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 12:17:23.942933 [CA 0] Center 38 (7~69) winsize 63
713 12:17:23.946145 [CA 1] Center 37 (7~68) winsize 62
714 12:17:23.949326 [CA 2] Center 35 (5~66) winsize 62
715 12:17:23.952774 [CA 3] Center 35 (5~66) winsize 62
716 12:17:23.956357 [CA 4] Center 34 (4~65) winsize 62
717 12:17:23.959234 [CA 5] Center 34 (4~65) winsize 62
718 12:17:23.959324
719 12:17:23.962530 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 12:17:23.962616
721 12:17:23.966081 [CATrainingPosCal] consider 1 rank data
722 12:17:23.969784 u2DelayCellTimex100 = 270/100 ps
723 12:17:23.972904 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 12:17:23.975951 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 12:17:23.982911 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 12:17:23.986073 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 12:17:23.989190 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 12:17:23.992684 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 12:17:23.992772
730 12:17:23.996323 CA PerBit enable=1, Macro0, CA PI delay=34
731 12:17:23.996408
732 12:17:23.999425 [CBTSetCACLKResult] CA Dly = 34
733 12:17:23.999525 CS Dly: 6 (0~37)
734 12:17:23.999593 ==
735 12:17:24.003059 Dram Type= 6, Freq= 0, CH_0, rank 1
736 12:17:24.009297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 12:17:24.009399 ==
738 12:17:24.012577 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 12:17:24.019338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 12:17:24.028864 [CA 0] Center 38 (7~69) winsize 63
741 12:17:24.032245 [CA 1] Center 38 (7~69) winsize 63
742 12:17:24.035610 [CA 2] Center 35 (5~66) winsize 62
743 12:17:24.039027 [CA 3] Center 35 (5~66) winsize 62
744 12:17:24.042222 [CA 4] Center 34 (4~65) winsize 62
745 12:17:24.045786 [CA 5] Center 34 (4~64) winsize 61
746 12:17:24.045874
747 12:17:24.048794 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 12:17:24.048879
749 12:17:24.052196 [CATrainingPosCal] consider 2 rank data
750 12:17:24.055615 u2DelayCellTimex100 = 270/100 ps
751 12:17:24.058998 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 12:17:24.062425 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 12:17:24.065803 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 12:17:24.072288 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 12:17:24.075610 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 12:17:24.078926 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 12:17:24.079014
758 12:17:24.082273 CA PerBit enable=1, Macro0, CA PI delay=34
759 12:17:24.082358
760 12:17:24.085362 [CBTSetCACLKResult] CA Dly = 34
761 12:17:24.085447 CS Dly: 6 (0~38)
762 12:17:24.085514
763 12:17:24.089190 ----->DramcWriteLeveling(PI) begin...
764 12:17:24.092131 ==
765 12:17:24.095656 Dram Type= 6, Freq= 0, CH_0, rank 0
766 12:17:24.099112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 12:17:24.099199 ==
768 12:17:24.102503 Write leveling (Byte 0): 31 => 31
769 12:17:24.105748 Write leveling (Byte 1): 31 => 31
770 12:17:24.108838 DramcWriteLeveling(PI) end<-----
771 12:17:24.108926
772 12:17:24.108992 ==
773 12:17:24.112333 Dram Type= 6, Freq= 0, CH_0, rank 0
774 12:17:24.115701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 12:17:24.115790 ==
776 12:17:24.118616 [Gating] SW mode calibration
777 12:17:24.125569 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 12:17:24.129030 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 12:17:24.135826 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 12:17:24.138851 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 12:17:24.142280 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 12:17:24.148918 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
783 12:17:24.152415 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 12:17:24.155629 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 12:17:24.162093 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 12:17:24.165570 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:17:24.168883 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:17:24.176078 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:17:24.179248 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:17:24.181987 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:17:24.189172 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:17:24.192883 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:17:24.196486 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:17:24.200069 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:17:24.203892 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:17:24.210108 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:17:24.214578 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 12:17:24.217805 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
799 12:17:24.220831 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:17:24.227652 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:17:24.230825 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:17:24.234045 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:17:24.240933 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:17:24.244182 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:17:24.247366 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:17:24.254771 0 9 12 | B1->B0 | 2a2a 3131 | 1 0 | (1 1) (0 0)
807 12:17:24.257396 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 12:17:24.260739 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 12:17:24.267569 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 12:17:24.270856 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 12:17:24.274453 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:17:24.281262 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:17:24.284353 0 10 8 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
814 12:17:24.287814 0 10 12 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (1 0)
815 12:17:24.294494 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:17:24.297791 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:17:24.301117 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:17:24.304155 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:17:24.311021 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:17:24.314521 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:17:24.317614 0 11 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
822 12:17:24.324707 0 11 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
823 12:17:24.327423 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 12:17:24.331405 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 12:17:24.337744 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 12:17:24.340785 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 12:17:24.344141 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:17:24.351779 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:17:24.354236 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 12:17:24.358086 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 12:17:24.364350 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 12:17:24.367843 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 12:17:24.371195 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 12:17:24.377675 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:17:24.380902 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:17:24.384166 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:17:24.390938 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:17:24.394165 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:17:24.397451 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:17:24.400931 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:17:24.408075 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:17:24.411142 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:17:24.414395 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:17:24.421010 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:17:24.424818 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 12:17:24.427538 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:17:24.430873 Total UI for P1: 0, mck2ui 16
848 12:17:24.434107 best dqsien dly found for B0: ( 0, 14, 8)
849 12:17:24.438102 Total UI for P1: 0, mck2ui 16
850 12:17:24.440884 best dqsien dly found for B1: ( 0, 14, 10)
851 12:17:24.444324 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 12:17:24.447771 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 12:17:24.447862
854 12:17:24.454213 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 12:17:24.457676 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 12:17:24.460762 [Gating] SW calibration Done
857 12:17:24.460850 ==
858 12:17:24.463984 Dram Type= 6, Freq= 0, CH_0, rank 0
859 12:17:24.467322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 12:17:24.467440 ==
861 12:17:24.467523 RX Vref Scan: 0
862 12:17:24.467587
863 12:17:24.470702 RX Vref 0 -> 0, step: 1
864 12:17:24.470787
865 12:17:24.474323 RX Delay -130 -> 252, step: 16
866 12:17:24.477432 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 12:17:24.481062 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 12:17:24.487639 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
869 12:17:24.490831 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 12:17:24.494387 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 12:17:24.497899 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
872 12:17:24.500721 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 12:17:24.504480 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 12:17:24.510970 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 12:17:24.514489 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
876 12:17:24.517738 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 12:17:24.521124 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 12:17:24.524759 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 12:17:24.531120 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 12:17:24.534491 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
881 12:17:24.537586 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 12:17:24.537684 ==
883 12:17:24.541529 Dram Type= 6, Freq= 0, CH_0, rank 0
884 12:17:24.544740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 12:17:24.547333 ==
886 12:17:24.547465 DQS Delay:
887 12:17:24.547534 DQS0 = 0, DQS1 = 0
888 12:17:24.551417 DQM Delay:
889 12:17:24.551522 DQM0 = 82, DQM1 = 70
890 12:17:24.554276 DQ Delay:
891 12:17:24.554349 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
892 12:17:24.557581 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
893 12:17:24.560920 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
894 12:17:24.564167 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
895 12:17:24.564266
896 12:17:24.567670
897 12:17:24.567758 ==
898 12:17:24.570762 Dram Type= 6, Freq= 0, CH_0, rank 0
899 12:17:24.574196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 12:17:24.574286 ==
901 12:17:24.574353
902 12:17:24.574416
903 12:17:24.577646 TX Vref Scan disable
904 12:17:24.577738 == TX Byte 0 ==
905 12:17:24.583879 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
906 12:17:24.587479 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
907 12:17:24.587579 == TX Byte 1 ==
908 12:17:24.591452 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
909 12:17:24.598241 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
910 12:17:24.598360 ==
911 12:17:24.602053 Dram Type= 6, Freq= 0, CH_0, rank 0
912 12:17:24.604692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 12:17:24.604781 ==
914 12:17:24.617502 TX Vref=22, minBit 1, minWin=26, winSum=435
915 12:17:24.620788 TX Vref=24, minBit 11, minWin=26, winSum=437
916 12:17:24.624365 TX Vref=26, minBit 0, minWin=27, winSum=440
917 12:17:24.627487 TX Vref=28, minBit 0, minWin=27, winSum=441
918 12:17:24.631317 TX Vref=30, minBit 9, minWin=27, winSum=442
919 12:17:24.637752 TX Vref=32, minBit 12, minWin=26, winSum=439
920 12:17:24.641278 [TxChooseVref] Worse bit 9, Min win 27, Win sum 442, Final Vref 30
921 12:17:24.641374
922 12:17:24.643983 Final TX Range 1 Vref 30
923 12:17:24.644071
924 12:17:24.644138 ==
925 12:17:24.647962 Dram Type= 6, Freq= 0, CH_0, rank 0
926 12:17:24.651142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 12:17:24.651231 ==
928 12:17:24.651299
929 12:17:24.654333
930 12:17:24.654420 TX Vref Scan disable
931 12:17:24.657545 == TX Byte 0 ==
932 12:17:24.660761 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
933 12:17:24.663970 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
934 12:17:24.667834 == TX Byte 1 ==
935 12:17:24.671022 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
936 12:17:24.674079 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
937 12:17:24.677971
938 12:17:24.678080 [DATLAT]
939 12:17:24.678147 Freq=800, CH0 RK0
940 12:17:24.678210
941 12:17:24.680972 DATLAT Default: 0xa
942 12:17:24.681058 0, 0xFFFF, sum = 0
943 12:17:24.684247 1, 0xFFFF, sum = 0
944 12:17:24.684338 2, 0xFFFF, sum = 0
945 12:17:24.687769 3, 0xFFFF, sum = 0
946 12:17:24.687856 4, 0xFFFF, sum = 0
947 12:17:24.690642 5, 0xFFFF, sum = 0
948 12:17:24.693961 6, 0xFFFF, sum = 0
949 12:17:24.694051 7, 0xFFFF, sum = 0
950 12:17:24.697769 8, 0xFFFF, sum = 0
951 12:17:24.697856 9, 0x0, sum = 1
952 12:17:24.697925 10, 0x0, sum = 2
953 12:17:24.700968 11, 0x0, sum = 3
954 12:17:24.701054 12, 0x0, sum = 4
955 12:17:24.704141 best_step = 10
956 12:17:24.704228
957 12:17:24.704294 ==
958 12:17:24.707280 Dram Type= 6, Freq= 0, CH_0, rank 0
959 12:17:24.710613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 12:17:24.710703 ==
961 12:17:24.714345 RX Vref Scan: 1
962 12:17:24.714444
963 12:17:24.714511 Set Vref Range= 32 -> 127
964 12:17:24.714573
965 12:17:24.717897 RX Vref 32 -> 127, step: 1
966 12:17:24.717982
967 12:17:24.721195 RX Delay -111 -> 252, step: 8
968 12:17:24.721280
969 12:17:24.724071 Set Vref, RX VrefLevel [Byte0]: 32
970 12:17:24.727494 [Byte1]: 32
971 12:17:24.727581
972 12:17:24.731285 Set Vref, RX VrefLevel [Byte0]: 33
973 12:17:24.734327 [Byte1]: 33
974 12:17:24.738071
975 12:17:24.738161 Set Vref, RX VrefLevel [Byte0]: 34
976 12:17:24.741515 [Byte1]: 34
977 12:17:24.745972
978 12:17:24.746063 Set Vref, RX VrefLevel [Byte0]: 35
979 12:17:24.748834 [Byte1]: 35
980 12:17:24.753231
981 12:17:24.753319 Set Vref, RX VrefLevel [Byte0]: 36
982 12:17:24.756694 [Byte1]: 36
983 12:17:24.761390
984 12:17:24.761482 Set Vref, RX VrefLevel [Byte0]: 37
985 12:17:24.764274 [Byte1]: 37
986 12:17:24.768753
987 12:17:24.768850 Set Vref, RX VrefLevel [Byte0]: 38
988 12:17:24.772225 [Byte1]: 38
989 12:17:24.776081
990 12:17:24.776168 Set Vref, RX VrefLevel [Byte0]: 39
991 12:17:24.782666 [Byte1]: 39
992 12:17:24.782772
993 12:17:24.786179 Set Vref, RX VrefLevel [Byte0]: 40
994 12:17:24.789794 [Byte1]: 40
995 12:17:24.789885
996 12:17:24.793312 Set Vref, RX VrefLevel [Byte0]: 41
997 12:17:24.796164 [Byte1]: 41
998 12:17:24.796253
999 12:17:24.799421 Set Vref, RX VrefLevel [Byte0]: 42
1000 12:17:24.802735 [Byte1]: 42
1001 12:17:24.807006
1002 12:17:24.807098 Set Vref, RX VrefLevel [Byte0]: 43
1003 12:17:24.809906 [Byte1]: 43
1004 12:17:24.814544
1005 12:17:24.814639 Set Vref, RX VrefLevel [Byte0]: 44
1006 12:17:24.817940 [Byte1]: 44
1007 12:17:24.822126
1008 12:17:24.822216 Set Vref, RX VrefLevel [Byte0]: 45
1009 12:17:24.825596 [Byte1]: 45
1010 12:17:24.830252
1011 12:17:24.830345 Set Vref, RX VrefLevel [Byte0]: 46
1012 12:17:24.833103 [Byte1]: 46
1013 12:17:24.837431
1014 12:17:24.837521 Set Vref, RX VrefLevel [Byte0]: 47
1015 12:17:24.840919 [Byte1]: 47
1016 12:17:24.844990
1017 12:17:24.845090 Set Vref, RX VrefLevel [Byte0]: 48
1018 12:17:24.848713 [Byte1]: 48
1019 12:17:24.853001
1020 12:17:24.853108 Set Vref, RX VrefLevel [Byte0]: 49
1021 12:17:24.856293 [Byte1]: 49
1022 12:17:24.861165
1023 12:17:24.861265 Set Vref, RX VrefLevel [Byte0]: 50
1024 12:17:24.864276 [Byte1]: 50
1025 12:17:24.868508
1026 12:17:24.868601 Set Vref, RX VrefLevel [Byte0]: 51
1027 12:17:24.871847 [Byte1]: 51
1028 12:17:24.876565
1029 12:17:24.876663 Set Vref, RX VrefLevel [Byte0]: 52
1030 12:17:24.879854 [Byte1]: 52
1031 12:17:24.883521
1032 12:17:24.883612 Set Vref, RX VrefLevel [Byte0]: 53
1033 12:17:24.886689 [Byte1]: 53
1034 12:17:24.891138
1035 12:17:24.891236 Set Vref, RX VrefLevel [Byte0]: 54
1036 12:17:24.894347 [Byte1]: 54
1037 12:17:24.898553
1038 12:17:24.898640 Set Vref, RX VrefLevel [Byte0]: 55
1039 12:17:24.901819 [Byte1]: 55
1040 12:17:24.906167
1041 12:17:24.906256 Set Vref, RX VrefLevel [Byte0]: 56
1042 12:17:24.909641 [Byte1]: 56
1043 12:17:24.914086
1044 12:17:24.914178 Set Vref, RX VrefLevel [Byte0]: 57
1045 12:17:24.917176 [Byte1]: 57
1046 12:17:24.921339
1047 12:17:24.921426 Set Vref, RX VrefLevel [Byte0]: 58
1048 12:17:24.925005 [Byte1]: 58
1049 12:17:24.929134
1050 12:17:24.929224 Set Vref, RX VrefLevel [Byte0]: 59
1051 12:17:24.932519 [Byte1]: 59
1052 12:17:24.936737
1053 12:17:24.936827 Set Vref, RX VrefLevel [Byte0]: 60
1054 12:17:24.940028 [Byte1]: 60
1055 12:17:24.944470
1056 12:17:24.944600 Set Vref, RX VrefLevel [Byte0]: 61
1057 12:17:24.947640 [Byte1]: 61
1058 12:17:24.951888
1059 12:17:24.951981 Set Vref, RX VrefLevel [Byte0]: 62
1060 12:17:24.955298 [Byte1]: 62
1061 12:17:24.959771
1062 12:17:24.959864 Set Vref, RX VrefLevel [Byte0]: 63
1063 12:17:24.963380 [Byte1]: 63
1064 12:17:24.967357
1065 12:17:24.967486 Set Vref, RX VrefLevel [Byte0]: 64
1066 12:17:24.970765 [Byte1]: 64
1067 12:17:24.975329
1068 12:17:24.975427 Set Vref, RX VrefLevel [Byte0]: 65
1069 12:17:24.978506 [Byte1]: 65
1070 12:17:24.982376
1071 12:17:24.982466 Set Vref, RX VrefLevel [Byte0]: 66
1072 12:17:24.986257 [Byte1]: 66
1073 12:17:24.990105
1074 12:17:24.990252 Set Vref, RX VrefLevel [Byte0]: 67
1075 12:17:24.993352 [Byte1]: 67
1076 12:17:24.997674
1077 12:17:24.997766 Set Vref, RX VrefLevel [Byte0]: 68
1078 12:17:25.001176 [Byte1]: 68
1079 12:17:25.005588
1080 12:17:25.005679 Set Vref, RX VrefLevel [Byte0]: 69
1081 12:17:25.008909 [Byte1]: 69
1082 12:17:25.013599
1083 12:17:25.013697 Set Vref, RX VrefLevel [Byte0]: 70
1084 12:17:25.016353 [Byte1]: 70
1085 12:17:25.020671
1086 12:17:25.020763 Set Vref, RX VrefLevel [Byte0]: 71
1087 12:17:25.024469 [Byte1]: 71
1088 12:17:25.028457
1089 12:17:25.028553 Set Vref, RX VrefLevel [Byte0]: 72
1090 12:17:25.031779 [Byte1]: 72
1091 12:17:25.036010
1092 12:17:25.036113 Set Vref, RX VrefLevel [Byte0]: 73
1093 12:17:25.039812 [Byte1]: 73
1094 12:17:25.043994
1095 12:17:25.044088 Set Vref, RX VrefLevel [Byte0]: 74
1096 12:17:25.046936 [Byte1]: 74
1097 12:17:25.051313
1098 12:17:25.051470 Set Vref, RX VrefLevel [Byte0]: 75
1099 12:17:25.054758 [Byte1]: 75
1100 12:17:25.058963
1101 12:17:25.059079 Set Vref, RX VrefLevel [Byte0]: 76
1102 12:17:25.062506 [Byte1]: 76
1103 12:17:25.066846
1104 12:17:25.066936 Set Vref, RX VrefLevel [Byte0]: 77
1105 12:17:25.069975 [Byte1]: 77
1106 12:17:25.074454
1107 12:17:25.074547 Set Vref, RX VrefLevel [Byte0]: 78
1108 12:17:25.078003 [Byte1]: 78
1109 12:17:25.082212
1110 12:17:25.082305 Set Vref, RX VrefLevel [Byte0]: 79
1111 12:17:25.085205 [Byte1]: 79
1112 12:17:25.089931
1113 12:17:25.090030 Set Vref, RX VrefLevel [Byte0]: 80
1114 12:17:25.093350 [Byte1]: 80
1115 12:17:25.097347
1116 12:17:25.097437 Final RX Vref Byte 0 = 64 to rank0
1117 12:17:25.100411 Final RX Vref Byte 1 = 63 to rank0
1118 12:17:25.103753 Final RX Vref Byte 0 = 64 to rank1
1119 12:17:25.107475 Final RX Vref Byte 1 = 63 to rank1==
1120 12:17:25.111008 Dram Type= 6, Freq= 0, CH_0, rank 0
1121 12:17:25.117436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1122 12:17:25.117564 ==
1123 12:17:25.117638 DQS Delay:
1124 12:17:25.117700 DQS0 = 0, DQS1 = 0
1125 12:17:25.120736 DQM Delay:
1126 12:17:25.120840 DQM0 = 81, DQM1 = 68
1127 12:17:25.123897 DQ Delay:
1128 12:17:25.127717 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1129 12:17:25.127838 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1130 12:17:25.130965 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =64
1131 12:17:25.134178 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1132 12:17:25.137160
1133 12:17:25.137264
1134 12:17:25.144020 [DQSOSCAuto] RK0, (LSB)MR18= 0x2726, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1135 12:17:25.147251 CH0 RK0: MR19=606, MR18=2726
1136 12:17:25.154258 CH0_RK0: MR19=0x606, MR18=0x2726, DQSOSC=400, MR23=63, INC=92, DEC=61
1137 12:17:25.154383
1138 12:17:25.157402 ----->DramcWriteLeveling(PI) begin...
1139 12:17:25.157495 ==
1140 12:17:25.160497 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 12:17:25.163953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 12:17:25.164044 ==
1143 12:17:25.167173 Write leveling (Byte 0): 32 => 32
1144 12:17:25.170917 Write leveling (Byte 1): 32 => 32
1145 12:17:25.173889 DramcWriteLeveling(PI) end<-----
1146 12:17:25.173983
1147 12:17:25.174049 ==
1148 12:17:25.177235 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 12:17:25.180568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 12:17:25.180664 ==
1151 12:17:25.184046 [Gating] SW mode calibration
1152 12:17:25.190553 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1153 12:17:25.197334 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1154 12:17:25.200573 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1155 12:17:25.204136 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1156 12:17:25.210714 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1157 12:17:25.214223 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:17:25.216951 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:17:25.224084 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:17:25.227484 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:17:25.230849 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:17:25.237234 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:17:25.240507 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:17:25.243777 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:17:25.250693 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:17:25.294907 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:17:25.295276 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:17:25.295448 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:17:25.295542 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:17:25.295647 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:17:25.295736 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1172 12:17:25.295823 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1173 12:17:25.295909 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1174 12:17:25.296188 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:17:25.296889 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:17:25.338572 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:17:25.338733 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:17:25.338810 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:17:25.339065 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:17:25.339326 0 9 8 | B1->B0 | 2323 2b2b | 1 1 | (1 1) (0 0)
1181 12:17:25.339888 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1182 12:17:25.339972 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:17:25.340221 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:17:25.340288 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:17:25.340390 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:17:25.383269 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:17:25.383441 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1188 12:17:25.383711 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
1189 12:17:25.384494 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:17:25.384763 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:17:25.385522 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:17:25.385622 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:17:25.385909 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:17:25.385975 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:17:25.386035 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:17:25.389098 0 11 8 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
1197 12:17:25.389194 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1198 12:17:25.392414 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:17:25.399523 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:17:25.402436 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:17:25.405814 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:17:25.412368 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:17:25.415783 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1204 12:17:25.419220 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1205 12:17:25.426406 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:17:25.429439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:17:25.433510 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:17:25.437170 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:17:25.443667 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:17:25.447963 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:17:25.450620 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:17:25.454253 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:17:25.461087 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:17:25.464414 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:17:25.468101 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:17:25.475137 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:17:25.478067 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:17:25.481614 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:17:25.488005 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1220 12:17:25.491148 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1221 12:17:25.494474 Total UI for P1: 0, mck2ui 16
1222 12:17:25.498047 best dqsien dly found for B0: ( 0, 14, 4)
1223 12:17:25.501224 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 12:17:25.504697 Total UI for P1: 0, mck2ui 16
1225 12:17:25.508032 best dqsien dly found for B1: ( 0, 14, 8)
1226 12:17:25.511167 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1227 12:17:25.514662 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1228 12:17:25.514773
1229 12:17:25.518361 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1230 12:17:25.521418 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 12:17:25.524335 [Gating] SW calibration Done
1232 12:17:25.524446 ==
1233 12:17:25.528155 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 12:17:25.534756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 12:17:25.534898 ==
1236 12:17:25.534970 RX Vref Scan: 0
1237 12:17:25.535033
1238 12:17:25.537724 RX Vref 0 -> 0, step: 1
1239 12:17:25.537813
1240 12:17:25.541687 RX Delay -130 -> 252, step: 16
1241 12:17:25.544332 iDelay=222, Bit 0, Center 77 (-34 ~ 189) 224
1242 12:17:25.548184 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1243 12:17:25.551528 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1244 12:17:25.554318 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1245 12:17:25.561081 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1246 12:17:25.565134 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1247 12:17:25.567733 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1248 12:17:25.570975 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1249 12:17:25.574330 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1250 12:17:25.580914 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1251 12:17:25.584258 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1252 12:17:25.587731 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1253 12:17:25.590856 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1254 12:17:25.594855 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1255 12:17:25.601261 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1256 12:17:25.604712 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1257 12:17:25.604839 ==
1258 12:17:25.608063 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 12:17:25.611237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 12:17:25.611354 ==
1261 12:17:25.614695 DQS Delay:
1262 12:17:25.614804 DQS0 = 0, DQS1 = 0
1263 12:17:25.614898 DQM Delay:
1264 12:17:25.618047 DQM0 = 78, DQM1 = 69
1265 12:17:25.618184 DQ Delay:
1266 12:17:25.621173 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1267 12:17:25.624632 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1268 12:17:25.627856 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1269 12:17:25.631521 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1270 12:17:25.631644
1271 12:17:25.631737
1272 12:17:25.631819 ==
1273 12:17:25.634343 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 12:17:25.638223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 12:17:25.641405 ==
1276 12:17:25.641527
1277 12:17:25.641620
1278 12:17:25.641702 TX Vref Scan disable
1279 12:17:25.644921 == TX Byte 0 ==
1280 12:17:25.648307 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1281 12:17:25.651620 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1282 12:17:25.654845 == TX Byte 1 ==
1283 12:17:25.657971 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1284 12:17:25.661497 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1285 12:17:25.664831 ==
1286 12:17:25.664944 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:17:25.671845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:17:25.671983 ==
1289 12:17:25.683160 TX Vref=22, minBit 1, minWin=27, winSum=435
1290 12:17:25.686406 TX Vref=24, minBit 11, minWin=26, winSum=438
1291 12:17:25.689568 TX Vref=26, minBit 1, minWin=27, winSum=439
1292 12:17:25.693256 TX Vref=28, minBit 1, minWin=27, winSum=442
1293 12:17:25.696225 TX Vref=30, minBit 1, minWin=27, winSum=442
1294 12:17:25.703165 TX Vref=32, minBit 11, minWin=27, winSum=445
1295 12:17:25.706576 [TxChooseVref] Worse bit 11, Min win 27, Win sum 445, Final Vref 32
1296 12:17:25.706701
1297 12:17:25.710132 Final TX Range 1 Vref 32
1298 12:17:25.710276
1299 12:17:25.710344 ==
1300 12:17:25.714336 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 12:17:25.716455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 12:17:25.719987 ==
1303 12:17:25.720099
1304 12:17:25.720167
1305 12:17:25.720228 TX Vref Scan disable
1306 12:17:25.723521 == TX Byte 0 ==
1307 12:17:25.727030 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1308 12:17:25.730371 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1309 12:17:25.733300 == TX Byte 1 ==
1310 12:17:25.736826 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1311 12:17:25.740586 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1312 12:17:25.743490
1313 12:17:25.743600 [DATLAT]
1314 12:17:25.743666 Freq=800, CH0 RK1
1315 12:17:25.743727
1316 12:17:25.747216 DATLAT Default: 0xa
1317 12:17:25.747356 0, 0xFFFF, sum = 0
1318 12:17:25.749952 1, 0xFFFF, sum = 0
1319 12:17:25.750045 2, 0xFFFF, sum = 0
1320 12:17:25.753226 3, 0xFFFF, sum = 0
1321 12:17:25.753327 4, 0xFFFF, sum = 0
1322 12:17:25.757253 5, 0xFFFF, sum = 0
1323 12:17:25.757358 6, 0xFFFF, sum = 0
1324 12:17:25.760448 7, 0xFFFF, sum = 0
1325 12:17:25.763581 8, 0xFFFF, sum = 0
1326 12:17:25.763682 9, 0x0, sum = 1
1327 12:17:25.763750 10, 0x0, sum = 2
1328 12:17:25.766784 11, 0x0, sum = 3
1329 12:17:25.766878 12, 0x0, sum = 4
1330 12:17:25.770517 best_step = 10
1331 12:17:25.770619
1332 12:17:25.770687 ==
1333 12:17:25.773233 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 12:17:25.777097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 12:17:25.777210 ==
1336 12:17:25.780578 RX Vref Scan: 0
1337 12:17:25.780685
1338 12:17:25.780753 RX Vref 0 -> 0, step: 1
1339 12:17:25.780815
1340 12:17:25.783443 RX Delay -111 -> 252, step: 8
1341 12:17:25.790628 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1342 12:17:25.793739 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1343 12:17:25.797119 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1344 12:17:25.800455 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1345 12:17:25.803872 iDelay=209, Bit 4, Center 80 (-31 ~ 192) 224
1346 12:17:25.810585 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1347 12:17:25.813623 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1348 12:17:25.817219 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1349 12:17:25.820779 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1350 12:17:25.824300 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1351 12:17:25.830821 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1352 12:17:25.833413 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1353 12:17:25.836733 iDelay=209, Bit 12, Center 76 (-39 ~ 192) 232
1354 12:17:25.840096 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1355 12:17:25.843406 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1356 12:17:25.850374 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1357 12:17:25.850519 ==
1358 12:17:25.853621 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 12:17:25.857021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 12:17:25.857180 ==
1361 12:17:25.857251 DQS Delay:
1362 12:17:25.860516 DQS0 = 0, DQS1 = 0
1363 12:17:25.860609 DQM Delay:
1364 12:17:25.863784 DQM0 = 79, DQM1 = 70
1365 12:17:25.863882 DQ Delay:
1366 12:17:25.866913 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1367 12:17:25.870023 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =92
1368 12:17:25.874210 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1369 12:17:25.876886 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =76
1370 12:17:25.876996
1371 12:17:25.877061
1372 12:17:25.883587 [DQSOSCAuto] RK1, (LSB)MR18= 0x4621, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1373 12:17:25.886844 CH0 RK1: MR19=606, MR18=4621
1374 12:17:25.893640 CH0_RK1: MR19=0x606, MR18=0x4621, DQSOSC=392, MR23=63, INC=96, DEC=64
1375 12:17:25.896693 [RxdqsGatingPostProcess] freq 800
1376 12:17:25.903472 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 12:17:25.906835 Pre-setting of DQS Precalculation
1378 12:17:25.909920 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 12:17:25.910048 ==
1380 12:17:25.913614 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 12:17:25.916955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 12:17:25.917073 ==
1383 12:17:25.923703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 12:17:25.929895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 12:17:25.938535 [CA 0] Center 36 (6~66) winsize 61
1386 12:17:25.941909 [CA 1] Center 36 (6~67) winsize 62
1387 12:17:25.945391 [CA 2] Center 34 (5~64) winsize 60
1388 12:17:25.948701 [CA 3] Center 34 (4~64) winsize 61
1389 12:17:25.951974 [CA 4] Center 34 (4~65) winsize 62
1390 12:17:25.955209 [CA 5] Center 34 (4~64) winsize 61
1391 12:17:25.955316
1392 12:17:25.958899 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1393 12:17:25.958998
1394 12:17:25.962065 [CATrainingPosCal] consider 1 rank data
1395 12:17:25.965502 u2DelayCellTimex100 = 270/100 ps
1396 12:17:25.968534 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1397 12:17:25.971728 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 12:17:25.978362 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1399 12:17:25.981653 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1400 12:17:25.985903 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 12:17:25.988773 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1402 12:17:25.988893
1403 12:17:25.991695 CA PerBit enable=1, Macro0, CA PI delay=34
1404 12:17:25.991787
1405 12:17:25.995227 [CBTSetCACLKResult] CA Dly = 34
1406 12:17:25.995323 CS Dly: 5 (0~36)
1407 12:17:25.998489 ==
1408 12:17:25.998581 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 12:17:26.005188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 12:17:26.005326 ==
1411 12:17:26.008390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 12:17:26.014995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 12:17:26.024721 [CA 0] Center 37 (7~67) winsize 61
1414 12:17:26.027991 [CA 1] Center 36 (6~67) winsize 62
1415 12:17:26.031636 [CA 2] Center 34 (4~65) winsize 62
1416 12:17:26.034556 [CA 3] Center 33 (3~64) winsize 62
1417 12:17:26.037636 [CA 4] Center 34 (4~65) winsize 62
1418 12:17:26.041424 [CA 5] Center 33 (3~64) winsize 62
1419 12:17:26.041556
1420 12:17:26.044821 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1421 12:17:26.044926
1422 12:17:26.048144 [CATrainingPosCal] consider 2 rank data
1423 12:17:26.051101 u2DelayCellTimex100 = 270/100 ps
1424 12:17:26.055060 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1425 12:17:26.058088 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 12:17:26.064509 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1427 12:17:26.067946 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1428 12:17:26.071289 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 12:17:26.074644 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1430 12:17:26.074757
1431 12:17:26.078193 CA PerBit enable=1, Macro0, CA PI delay=34
1432 12:17:26.078296
1433 12:17:26.081887 [CBTSetCACLKResult] CA Dly = 34
1434 12:17:26.081999 CS Dly: 6 (0~38)
1435 12:17:26.082070
1436 12:17:26.084741 ----->DramcWriteLeveling(PI) begin...
1437 12:17:26.088056 ==
1438 12:17:26.088169 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 12:17:26.095213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 12:17:26.095354 ==
1441 12:17:26.099114 Write leveling (Byte 0): 31 => 31
1442 12:17:26.099280 Write leveling (Byte 1): 31 => 31
1443 12:17:26.103158 DramcWriteLeveling(PI) end<-----
1444 12:17:26.103277
1445 12:17:26.103380 ==
1446 12:17:26.106501 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 12:17:26.110100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 12:17:26.110259 ==
1449 12:17:26.114041 [Gating] SW mode calibration
1450 12:17:26.121476 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 12:17:26.124586 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 12:17:26.131290 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 12:17:26.134940 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 12:17:26.137972 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1455 12:17:26.145017 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:17:26.148236 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:17:26.151440 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:17:26.158156 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:17:26.162132 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:17:26.164957 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:17:26.171973 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:17:26.174578 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:17:26.177957 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:17:26.184856 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:17:26.188119 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:17:26.191412 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:17:26.195408 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:17:26.201713 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:17:26.204833 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:17:26.207962 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:17:26.215290 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:17:26.218084 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:17:26.221666 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:17:26.227976 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:17:26.231305 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:17:26.234872 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:17:26.241711 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:17:26.244635 0 9 8 | B1->B0 | 2b2b 2c2c | 0 0 | (0 0) (0 0)
1479 12:17:26.248242 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:17:26.254620 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:17:26.257944 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:17:26.261575 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:17:26.268420 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:17:26.272322 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 12:17:26.275130 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1486 12:17:26.281291 0 10 8 | B1->B0 | 2b2b 2d2d | 0 0 | (1 1) (1 1)
1487 12:17:26.285024 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:17:26.288206 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:17:26.291441 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:17:26.297920 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:17:26.301396 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:17:26.304523 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:17:26.311226 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:17:26.314493 0 11 8 | B1->B0 | 3332 3d3d | 1 0 | (1 1) (1 1)
1495 12:17:26.317801 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:17:26.324938 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:17:26.328207 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:17:26.331496 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:17:26.337983 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:17:26.341151 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:17:26.344705 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 12:17:26.351207 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1503 12:17:26.354690 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:17:26.357834 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:17:26.364395 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:17:26.368050 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:17:26.371120 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:17:26.378357 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:17:26.381154 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:17:26.385305 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:17:26.391124 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:17:26.394731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:17:26.398165 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:17:26.404824 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:17:26.408121 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:17:26.411353 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:17:26.414623 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 12:17:26.421389 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1519 12:17:26.424286 Total UI for P1: 0, mck2ui 16
1520 12:17:26.427936 best dqsien dly found for B0: ( 0, 14, 6)
1521 12:17:26.431350 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 12:17:26.434542 Total UI for P1: 0, mck2ui 16
1523 12:17:26.437757 best dqsien dly found for B1: ( 0, 14, 8)
1524 12:17:26.441187 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1525 12:17:26.444762 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1526 12:17:26.444893
1527 12:17:26.447981 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 12:17:26.451343 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1529 12:17:26.454749 [Gating] SW calibration Done
1530 12:17:26.454856 ==
1531 12:17:26.457768 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 12:17:26.461254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 12:17:26.464739 ==
1534 12:17:26.464854 RX Vref Scan: 0
1535 12:17:26.464923
1536 12:17:26.467899 RX Vref 0 -> 0, step: 1
1537 12:17:26.467993
1538 12:17:26.470996 RX Delay -130 -> 252, step: 16
1539 12:17:26.474203 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1540 12:17:26.477768 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1541 12:17:26.481230 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1542 12:17:26.484222 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1543 12:17:26.491118 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1544 12:17:26.494327 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1545 12:17:26.497863 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1546 12:17:26.501066 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1547 12:17:26.504652 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1548 12:17:26.507815 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1549 12:17:26.514497 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1550 12:17:26.517732 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1551 12:17:26.521083 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1552 12:17:26.524306 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1553 12:17:26.531597 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1554 12:17:26.534943 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1555 12:17:26.535054 ==
1556 12:17:26.537823 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 12:17:26.541159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 12:17:26.541283 ==
1559 12:17:26.541354 DQS Delay:
1560 12:17:26.544664 DQS0 = 0, DQS1 = 0
1561 12:17:26.544765 DQM Delay:
1562 12:17:26.548279 DQM0 = 79, DQM1 = 70
1563 12:17:26.548400 DQ Delay:
1564 12:17:26.551190 DQ0 =77, DQ1 =77, DQ2 =61, DQ3 =77
1565 12:17:26.554358 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1566 12:17:26.558135 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1567 12:17:26.561093 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1568 12:17:26.561202
1569 12:17:26.561269
1570 12:17:26.561329 ==
1571 12:17:26.564607 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 12:17:26.568181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 12:17:26.571083 ==
1574 12:17:26.571191
1575 12:17:26.571257
1576 12:17:26.571317 TX Vref Scan disable
1577 12:17:26.574868 == TX Byte 0 ==
1578 12:17:26.578142 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1579 12:17:26.581108 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1580 12:17:26.584446 == TX Byte 1 ==
1581 12:17:26.588120 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1582 12:17:26.591344 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1583 12:17:26.591484 ==
1584 12:17:26.594937 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:17:26.601629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:17:26.601776 ==
1587 12:17:26.613157 TX Vref=22, minBit 0, minWin=27, winSum=440
1588 12:17:26.616408 TX Vref=24, minBit 4, minWin=27, winSum=442
1589 12:17:26.619752 TX Vref=26, minBit 1, minWin=27, winSum=445
1590 12:17:26.623304 TX Vref=28, minBit 9, minWin=27, winSum=447
1591 12:17:26.626506 TX Vref=30, minBit 11, minWin=27, winSum=449
1592 12:17:26.633424 TX Vref=32, minBit 4, minWin=27, winSum=449
1593 12:17:26.636591 [TxChooseVref] Worse bit 11, Min win 27, Win sum 449, Final Vref 30
1594 12:17:26.636710
1595 12:17:26.640245 Final TX Range 1 Vref 30
1596 12:17:26.640350
1597 12:17:26.640416 ==
1598 12:17:26.643113 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 12:17:26.647061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 12:17:26.649338 ==
1601 12:17:26.649479
1602 12:17:26.649576
1603 12:17:26.649664 TX Vref Scan disable
1604 12:17:26.653494 == TX Byte 0 ==
1605 12:17:26.656477 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1606 12:17:26.660285 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1607 12:17:26.663295 == TX Byte 1 ==
1608 12:17:26.667060 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1609 12:17:26.670872 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1610 12:17:26.671011
1611 12:17:26.674303 [DATLAT]
1612 12:17:26.674406 Freq=800, CH1 RK0
1613 12:17:26.674480
1614 12:17:26.677701 DATLAT Default: 0xa
1615 12:17:26.677797 0, 0xFFFF, sum = 0
1616 12:17:26.681004 1, 0xFFFF, sum = 0
1617 12:17:26.681182 2, 0xFFFF, sum = 0
1618 12:17:26.684703 3, 0xFFFF, sum = 0
1619 12:17:26.684805 4, 0xFFFF, sum = 0
1620 12:17:26.687593 5, 0xFFFF, sum = 0
1621 12:17:26.687695 6, 0xFFFF, sum = 0
1622 12:17:26.691076 7, 0xFFFF, sum = 0
1623 12:17:26.691173 8, 0xFFFF, sum = 0
1624 12:17:26.694226 9, 0x0, sum = 1
1625 12:17:26.694331 10, 0x0, sum = 2
1626 12:17:26.697442 11, 0x0, sum = 3
1627 12:17:26.697558 12, 0x0, sum = 4
1628 12:17:26.697628 best_step = 10
1629 12:17:26.701293
1630 12:17:26.701398 ==
1631 12:17:26.704167 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 12:17:26.707682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 12:17:26.707796 ==
1634 12:17:26.707869 RX Vref Scan: 1
1635 12:17:26.708039
1636 12:17:26.710886 Set Vref Range= 32 -> 127
1637 12:17:26.711024
1638 12:17:26.714186 RX Vref 32 -> 127, step: 1
1639 12:17:26.714285
1640 12:17:26.717709 RX Delay -111 -> 252, step: 8
1641 12:17:26.717803
1642 12:17:26.721031 Set Vref, RX VrefLevel [Byte0]: 32
1643 12:17:26.723978 [Byte1]: 32
1644 12:17:26.724079
1645 12:17:26.727360 Set Vref, RX VrefLevel [Byte0]: 33
1646 12:17:26.730822 [Byte1]: 33
1647 12:17:26.730925
1648 12:17:26.734394 Set Vref, RX VrefLevel [Byte0]: 34
1649 12:17:26.737750 [Byte1]: 34
1650 12:17:26.741623
1651 12:17:26.741738 Set Vref, RX VrefLevel [Byte0]: 35
1652 12:17:26.744841 [Byte1]: 35
1653 12:17:26.749487
1654 12:17:26.749638 Set Vref, RX VrefLevel [Byte0]: 36
1655 12:17:26.752155 [Byte1]: 36
1656 12:17:26.756954
1657 12:17:26.757091 Set Vref, RX VrefLevel [Byte0]: 37
1658 12:17:26.760069 [Byte1]: 37
1659 12:17:26.764276
1660 12:17:26.764392 Set Vref, RX VrefLevel [Byte0]: 38
1661 12:17:26.767844 [Byte1]: 38
1662 12:17:26.772397
1663 12:17:26.772522 Set Vref, RX VrefLevel [Byte0]: 39
1664 12:17:26.775423 [Byte1]: 39
1665 12:17:26.779407
1666 12:17:26.779542 Set Vref, RX VrefLevel [Byte0]: 40
1667 12:17:26.783551 [Byte1]: 40
1668 12:17:26.787270
1669 12:17:26.787379 Set Vref, RX VrefLevel [Byte0]: 41
1670 12:17:26.790672 [Byte1]: 41
1671 12:17:26.795330
1672 12:17:26.795475 Set Vref, RX VrefLevel [Byte0]: 42
1673 12:17:26.798257 [Byte1]: 42
1674 12:17:26.802813
1675 12:17:26.802936 Set Vref, RX VrefLevel [Byte0]: 43
1676 12:17:26.806289 [Byte1]: 43
1677 12:17:26.810549
1678 12:17:26.810717 Set Vref, RX VrefLevel [Byte0]: 44
1679 12:17:26.813846 [Byte1]: 44
1680 12:17:26.817816
1681 12:17:26.817934 Set Vref, RX VrefLevel [Byte0]: 45
1682 12:17:26.821658 [Byte1]: 45
1683 12:17:26.825520
1684 12:17:26.825635 Set Vref, RX VrefLevel [Byte0]: 46
1685 12:17:26.829124 [Byte1]: 46
1686 12:17:26.833250
1687 12:17:26.833364 Set Vref, RX VrefLevel [Byte0]: 47
1688 12:17:26.836330 [Byte1]: 47
1689 12:17:26.840764
1690 12:17:26.840875 Set Vref, RX VrefLevel [Byte0]: 48
1691 12:17:26.844389 [Byte1]: 48
1692 12:17:26.848280
1693 12:17:26.848403 Set Vref, RX VrefLevel [Byte0]: 49
1694 12:17:26.851772 [Byte1]: 49
1695 12:17:26.856364
1696 12:17:26.856488 Set Vref, RX VrefLevel [Byte0]: 50
1697 12:17:26.859666 [Byte1]: 50
1698 12:17:26.863582
1699 12:17:26.863691 Set Vref, RX VrefLevel [Byte0]: 51
1700 12:17:26.867306 [Byte1]: 51
1701 12:17:26.871373
1702 12:17:26.871498 Set Vref, RX VrefLevel [Byte0]: 52
1703 12:17:26.874613 [Byte1]: 52
1704 12:17:26.879336
1705 12:17:26.879493 Set Vref, RX VrefLevel [Byte0]: 53
1706 12:17:26.882298 [Byte1]: 53
1707 12:17:26.886859
1708 12:17:26.886983 Set Vref, RX VrefLevel [Byte0]: 54
1709 12:17:26.890006 [Byte1]: 54
1710 12:17:26.894519
1711 12:17:26.894649 Set Vref, RX VrefLevel [Byte0]: 55
1712 12:17:26.897715 [Byte1]: 55
1713 12:17:26.901941
1714 12:17:26.902063 Set Vref, RX VrefLevel [Byte0]: 56
1715 12:17:26.905645 [Byte1]: 56
1716 12:17:26.909639
1717 12:17:26.909765 Set Vref, RX VrefLevel [Byte0]: 57
1718 12:17:26.912815 [Byte1]: 57
1719 12:17:26.917563
1720 12:17:26.917694 Set Vref, RX VrefLevel [Byte0]: 58
1721 12:17:26.920762 [Byte1]: 58
1722 12:17:26.924902
1723 12:17:26.925020 Set Vref, RX VrefLevel [Byte0]: 59
1724 12:17:26.928622 [Byte1]: 59
1725 12:17:26.932361
1726 12:17:26.932509 Set Vref, RX VrefLevel [Byte0]: 60
1727 12:17:26.935824 [Byte1]: 60
1728 12:17:26.940712
1729 12:17:26.940841 Set Vref, RX VrefLevel [Byte0]: 61
1730 12:17:26.943897 [Byte1]: 61
1731 12:17:26.948312
1732 12:17:26.948449 Set Vref, RX VrefLevel [Byte0]: 62
1733 12:17:26.951157 [Byte1]: 62
1734 12:17:26.955443
1735 12:17:26.955562 Set Vref, RX VrefLevel [Byte0]: 63
1736 12:17:26.959153 [Byte1]: 63
1737 12:17:26.963209
1738 12:17:26.963329 Set Vref, RX VrefLevel [Byte0]: 64
1739 12:17:26.966492 [Byte1]: 64
1740 12:17:26.970751
1741 12:17:26.970860 Set Vref, RX VrefLevel [Byte0]: 65
1742 12:17:26.974187 [Byte1]: 65
1743 12:17:26.978660
1744 12:17:26.978776 Set Vref, RX VrefLevel [Byte0]: 66
1745 12:17:26.982050 [Byte1]: 66
1746 12:17:26.986528
1747 12:17:26.986651 Set Vref, RX VrefLevel [Byte0]: 67
1748 12:17:26.989653 [Byte1]: 67
1749 12:17:26.994066
1750 12:17:26.994185 Set Vref, RX VrefLevel [Byte0]: 68
1751 12:17:26.997431 [Byte1]: 68
1752 12:17:27.001600
1753 12:17:27.001726 Set Vref, RX VrefLevel [Byte0]: 69
1754 12:17:27.007910 [Byte1]: 69
1755 12:17:27.008075
1756 12:17:27.011147 Set Vref, RX VrefLevel [Byte0]: 70
1757 12:17:27.014478 [Byte1]: 70
1758 12:17:27.014617
1759 12:17:27.017928 Set Vref, RX VrefLevel [Byte0]: 71
1760 12:17:27.021051 [Byte1]: 71
1761 12:17:27.024776
1762 12:17:27.024924 Set Vref, RX VrefLevel [Byte0]: 72
1763 12:17:27.027830 [Byte1]: 72
1764 12:17:27.032107
1765 12:17:27.032254 Set Vref, RX VrefLevel [Byte0]: 73
1766 12:17:27.035332 [Byte1]: 73
1767 12:17:27.039478
1768 12:17:27.039625 Final RX Vref Byte 0 = 62 to rank0
1769 12:17:27.043037 Final RX Vref Byte 1 = 54 to rank0
1770 12:17:27.046348 Final RX Vref Byte 0 = 62 to rank1
1771 12:17:27.049712 Final RX Vref Byte 1 = 54 to rank1==
1772 12:17:27.053100 Dram Type= 6, Freq= 0, CH_1, rank 0
1773 12:17:27.059764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1774 12:17:27.059939 ==
1775 12:17:27.060051 DQS Delay:
1776 12:17:27.060143 DQS0 = 0, DQS1 = 0
1777 12:17:27.063194 DQM Delay:
1778 12:17:27.063309 DQM0 = 80, DQM1 = 71
1779 12:17:27.066386 DQ Delay:
1780 12:17:27.069413 DQ0 =88, DQ1 =72, DQ2 =68, DQ3 =76
1781 12:17:27.069537 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1782 12:17:27.072729 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1783 12:17:27.076449 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =76
1784 12:17:27.079596
1785 12:17:27.079731
1786 12:17:27.086194 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1787 12:17:27.089599 CH1 RK0: MR19=606, MR18=F19
1788 12:17:27.096130 CH1_RK0: MR19=0x606, MR18=0xF19, DQSOSC=403, MR23=63, INC=90, DEC=60
1789 12:17:27.096273
1790 12:17:27.099665 ----->DramcWriteLeveling(PI) begin...
1791 12:17:27.099769 ==
1792 12:17:27.103149 Dram Type= 6, Freq= 0, CH_1, rank 1
1793 12:17:27.106158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 12:17:27.106260 ==
1795 12:17:27.109836 Write leveling (Byte 0): 29 => 29
1796 12:17:27.112812 Write leveling (Byte 1): 29 => 29
1797 12:17:27.116284 DramcWriteLeveling(PI) end<-----
1798 12:17:27.116400
1799 12:17:27.116467 ==
1800 12:17:27.119868 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 12:17:27.123007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 12:17:27.123113 ==
1803 12:17:27.126424 [Gating] SW mode calibration
1804 12:17:27.133327 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1805 12:17:27.139619 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1806 12:17:27.143206 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1807 12:17:27.146157 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1808 12:17:27.153064 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:17:27.156458 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:17:27.159742 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:17:27.163051 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:17:27.169946 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:17:27.173951 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:17:27.176587 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:17:27.182975 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:17:27.186444 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:17:27.189765 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:17:27.196035 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:17:27.199884 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:17:27.203022 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:17:27.209419 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:17:27.212964 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1823 12:17:27.216112 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1824 12:17:27.222929 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:17:27.226161 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:17:27.229661 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:17:27.236235 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:17:27.239606 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:17:27.243278 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:17:27.249645 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:17:27.252968 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1832 12:17:27.255996 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1833 12:17:27.262822 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:17:27.266682 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 12:17:27.269455 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 12:17:27.272827 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 12:17:27.279609 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 12:17:27.282825 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 12:17:27.286783 0 10 4 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (0 1)
1840 12:17:27.292953 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1841 12:17:27.296285 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:17:27.299977 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:17:27.306310 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:17:27.309629 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:17:27.313215 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:17:27.320087 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1847 12:17:27.323650 0 11 4 | B1->B0 | 2929 3e3e | 0 0 | (1 1) (0 0)
1848 12:17:27.326436 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (1 1) (0 0)
1849 12:17:27.333169 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:17:27.336180 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 12:17:27.339708 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 12:17:27.346339 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 12:17:27.349589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 12:17:27.353077 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:17:27.356547 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1856 12:17:27.363446 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:17:27.366703 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1858 12:17:27.369856 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:17:27.376745 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:17:27.379798 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:17:27.383302 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:17:27.389795 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:17:27.393145 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:17:27.396495 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:17:27.403110 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:17:27.406916 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:17:27.409767 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:17:27.416562 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:17:27.419742 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:17:27.423202 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:17:27.429977 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1872 12:17:27.430133 Total UI for P1: 0, mck2ui 16
1873 12:17:27.433276 best dqsien dly found for B0: ( 0, 14, 2)
1874 12:17:27.440003 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 12:17:27.443379 Total UI for P1: 0, mck2ui 16
1876 12:17:27.446386 best dqsien dly found for B1: ( 0, 14, 4)
1877 12:17:27.450215 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1878 12:17:27.453283 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1879 12:17:27.453404
1880 12:17:27.456532 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1881 12:17:27.459891 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 12:17:27.463376 [Gating] SW calibration Done
1883 12:17:27.463529 ==
1884 12:17:27.466466 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 12:17:27.470132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 12:17:27.470253 ==
1887 12:17:27.473247 RX Vref Scan: 0
1888 12:17:27.473344
1889 12:17:27.473431 RX Vref 0 -> 0, step: 1
1890 12:17:27.473513
1891 12:17:27.476497 RX Delay -130 -> 252, step: 16
1892 12:17:27.483468 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1893 12:17:27.486709 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1894 12:17:27.490456 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1895 12:17:27.493380 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1896 12:17:27.496772 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1897 12:17:27.500144 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1898 12:17:27.506435 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1899 12:17:27.510586 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1900 12:17:27.513304 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1901 12:17:27.517083 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1902 12:17:27.520082 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1903 12:17:27.526756 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1904 12:17:27.530381 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1905 12:17:27.533238 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1906 12:17:27.536788 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1907 12:17:27.543264 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1908 12:17:27.543445 ==
1909 12:17:27.546350 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 12:17:27.549993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 12:17:27.550112 ==
1912 12:17:27.550208 DQS Delay:
1913 12:17:27.553491 DQS0 = 0, DQS1 = 0
1914 12:17:27.553593 DQM Delay:
1915 12:17:27.556774 DQM0 = 76, DQM1 = 71
1916 12:17:27.556891 DQ Delay:
1917 12:17:27.559858 DQ0 =77, DQ1 =69, DQ2 =61, DQ3 =77
1918 12:17:27.563364 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1919 12:17:27.566424 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1920 12:17:27.570127 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1921 12:17:27.570246
1922 12:17:27.570341
1923 12:17:27.570424 ==
1924 12:17:27.573376 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 12:17:27.576568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 12:17:27.576674 ==
1927 12:17:27.576764
1928 12:17:27.576845
1929 12:17:27.579798 TX Vref Scan disable
1930 12:17:27.583276 == TX Byte 0 ==
1931 12:17:27.587107 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1932 12:17:27.589733 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1933 12:17:27.593129 == TX Byte 1 ==
1934 12:17:27.596898 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1935 12:17:27.599747 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1936 12:17:27.599856 ==
1937 12:17:27.603607 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 12:17:27.606380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 12:17:27.609702 ==
1940 12:17:27.621260 TX Vref=22, minBit 1, minWin=27, winSum=447
1941 12:17:27.624625 TX Vref=24, minBit 1, minWin=27, winSum=449
1942 12:17:27.627369 TX Vref=26, minBit 5, minWin=27, winSum=453
1943 12:17:27.630913 TX Vref=28, minBit 1, minWin=27, winSum=456
1944 12:17:27.634968 TX Vref=30, minBit 1, minWin=27, winSum=456
1945 12:17:27.640856 TX Vref=32, minBit 1, minWin=27, winSum=454
1946 12:17:27.644080 [TxChooseVref] Worse bit 1, Min win 27, Win sum 456, Final Vref 28
1947 12:17:27.644199
1948 12:17:27.647627 Final TX Range 1 Vref 28
1949 12:17:27.647729
1950 12:17:27.647818 ==
1951 12:17:27.650982 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 12:17:27.654158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 12:17:27.654268 ==
1954 12:17:27.657541
1955 12:17:27.657641
1956 12:17:27.657731 TX Vref Scan disable
1957 12:17:27.660921 == TX Byte 0 ==
1958 12:17:27.664302 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1959 12:17:27.667623 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1960 12:17:27.671280 == TX Byte 1 ==
1961 12:17:27.674190 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1962 12:17:27.678117 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1963 12:17:27.681391
1964 12:17:27.681524 [DATLAT]
1965 12:17:27.681617 Freq=800, CH1 RK1
1966 12:17:27.681718
1967 12:17:27.684515 DATLAT Default: 0xa
1968 12:17:27.684610 0, 0xFFFF, sum = 0
1969 12:17:27.687733 1, 0xFFFF, sum = 0
1970 12:17:27.687830 2, 0xFFFF, sum = 0
1971 12:17:27.690904 3, 0xFFFF, sum = 0
1972 12:17:27.690999 4, 0xFFFF, sum = 0
1973 12:17:27.694392 5, 0xFFFF, sum = 0
1974 12:17:27.697726 6, 0xFFFF, sum = 0
1975 12:17:27.697837 7, 0xFFFF, sum = 0
1976 12:17:27.701163 8, 0xFFFF, sum = 0
1977 12:17:27.701264 9, 0x0, sum = 1
1978 12:17:27.701353 10, 0x0, sum = 2
1979 12:17:27.704572 11, 0x0, sum = 3
1980 12:17:27.704668 12, 0x0, sum = 4
1981 12:17:27.707285 best_step = 10
1982 12:17:27.707379
1983 12:17:27.707496 ==
1984 12:17:27.711157 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 12:17:27.714408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 12:17:27.714522 ==
1987 12:17:27.717865 RX Vref Scan: 0
1988 12:17:27.717963
1989 12:17:27.718031 RX Vref 0 -> 0, step: 1
1990 12:17:27.718092
1991 12:17:27.720637 RX Delay -111 -> 252, step: 8
1992 12:17:27.727794 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1993 12:17:27.731229 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1994 12:17:27.734320 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1995 12:17:27.737463 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1996 12:17:27.740896 iDelay=209, Bit 4, Center 72 (-47 ~ 192) 240
1997 12:17:27.747925 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1998 12:17:27.750675 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1999 12:17:27.754399 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2000 12:17:27.757613 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2001 12:17:27.760935 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2002 12:17:27.767600 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2003 12:17:27.771092 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2004 12:17:27.774100 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2005 12:17:27.777442 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2006 12:17:27.784029 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2007 12:17:27.787842 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2008 12:17:27.787976 ==
2009 12:17:27.791155 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 12:17:27.794534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 12:17:27.794648 ==
2012 12:17:27.794741 DQS Delay:
2013 12:17:27.797592 DQS0 = 0, DQS1 = 0
2014 12:17:27.797686 DQM Delay:
2015 12:17:27.800825 DQM0 = 77, DQM1 = 75
2016 12:17:27.800920 DQ Delay:
2017 12:17:27.804080 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2018 12:17:27.807745 DQ4 =72, DQ5 =88, DQ6 =88, DQ7 =76
2019 12:17:27.810754 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
2020 12:17:27.814375 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2021 12:17:27.814533
2022 12:17:27.814629
2023 12:17:27.824109 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2024 12:17:27.824266 CH1 RK1: MR19=606, MR18=1F38
2025 12:17:27.830640 CH1_RK1: MR19=0x606, MR18=0x1F38, DQSOSC=395, MR23=63, INC=94, DEC=63
2026 12:17:27.834551 [RxdqsGatingPostProcess] freq 800
2027 12:17:27.840561 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 12:17:27.843842 Pre-setting of DQS Precalculation
2029 12:17:27.847454 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 12:17:27.854433 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 12:17:27.860873 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 12:17:27.861027
2033 12:17:27.864266
2034 12:17:27.864368 [Calibration Summary] 1600 Mbps
2035 12:17:27.867731 CH 0, Rank 0
2036 12:17:27.867836 SW Impedance : PASS
2037 12:17:27.870730 DUTY Scan : NO K
2038 12:17:27.874226 ZQ Calibration : PASS
2039 12:17:27.874339 Jitter Meter : NO K
2040 12:17:27.877338 CBT Training : PASS
2041 12:17:27.880927 Write leveling : PASS
2042 12:17:27.881041 RX DQS gating : PASS
2043 12:17:27.884390 RX DQ/DQS(RDDQC) : PASS
2044 12:17:27.887798 TX DQ/DQS : PASS
2045 12:17:27.887913 RX DATLAT : PASS
2046 12:17:27.890873 RX DQ/DQS(Engine): PASS
2047 12:17:27.890973 TX OE : NO K
2048 12:17:27.894275 All Pass.
2049 12:17:27.894382
2050 12:17:27.894474 CH 0, Rank 1
2051 12:17:27.897665 SW Impedance : PASS
2052 12:17:27.897761 DUTY Scan : NO K
2053 12:17:27.900984 ZQ Calibration : PASS
2054 12:17:27.904419 Jitter Meter : NO K
2055 12:17:27.904525 CBT Training : PASS
2056 12:17:27.907572 Write leveling : PASS
2057 12:17:27.910931 RX DQS gating : PASS
2058 12:17:27.911039 RX DQ/DQS(RDDQC) : PASS
2059 12:17:27.914138 TX DQ/DQS : PASS
2060 12:17:27.917506 RX DATLAT : PASS
2061 12:17:27.917619 RX DQ/DQS(Engine): PASS
2062 12:17:27.921052 TX OE : NO K
2063 12:17:27.921156 All Pass.
2064 12:17:27.921244
2065 12:17:27.923990 CH 1, Rank 0
2066 12:17:27.924082 SW Impedance : PASS
2067 12:17:27.928255 DUTY Scan : NO K
2068 12:17:27.930807 ZQ Calibration : PASS
2069 12:17:27.930909 Jitter Meter : NO K
2070 12:17:27.934411 CBT Training : PASS
2071 12:17:27.934517 Write leveling : PASS
2072 12:17:27.937785 RX DQS gating : PASS
2073 12:17:27.941092 RX DQ/DQS(RDDQC) : PASS
2074 12:17:27.941196 TX DQ/DQS : PASS
2075 12:17:27.944557 RX DATLAT : PASS
2076 12:17:27.947566 RX DQ/DQS(Engine): PASS
2077 12:17:27.947675 TX OE : NO K
2078 12:17:27.950859 All Pass.
2079 12:17:27.950960
2080 12:17:27.951049 CH 1, Rank 1
2081 12:17:27.954089 SW Impedance : PASS
2082 12:17:27.954185 DUTY Scan : NO K
2083 12:17:27.957556 ZQ Calibration : PASS
2084 12:17:27.960882 Jitter Meter : NO K
2085 12:17:27.960990 CBT Training : PASS
2086 12:17:27.964607 Write leveling : PASS
2087 12:17:27.967529 RX DQS gating : PASS
2088 12:17:27.967636 RX DQ/DQS(RDDQC) : PASS
2089 12:17:27.970740 TX DQ/DQS : PASS
2090 12:17:27.975185 RX DATLAT : PASS
2091 12:17:27.975312 RX DQ/DQS(Engine): PASS
2092 12:17:27.977491 TX OE : NO K
2093 12:17:27.977582 All Pass.
2094 12:17:27.977690
2095 12:17:27.980936 DramC Write-DBI off
2096 12:17:27.983873 PER_BANK_REFRESH: Hybrid Mode
2097 12:17:27.983984 TX_TRACKING: ON
2098 12:17:27.987342 [GetDramInforAfterCalByMRR] Vendor 6.
2099 12:17:27.990984 [GetDramInforAfterCalByMRR] Revision 606.
2100 12:17:27.994320 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 12:17:27.997514 MR0 0x3b3b
2102 12:17:27.997635 MR8 0x5151
2103 12:17:28.000533 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 12:17:28.000633
2105 12:17:28.000721 MR0 0x3b3b
2106 12:17:28.004160 MR8 0x5151
2107 12:17:28.007394 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 12:17:28.007507
2109 12:17:28.013828 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 12:17:28.020516 [FAST_K] Save calibration result to emmc
2111 12:17:28.023813 [FAST_K] Save calibration result to emmc
2112 12:17:28.023927 dram_init: config_dvfs: 1
2113 12:17:28.027125 dramc_set_vcore_voltage set vcore to 662500
2114 12:17:28.030738 Read voltage for 1200, 2
2115 12:17:28.030854 Vio18 = 0
2116 12:17:28.033959 Vcore = 662500
2117 12:17:28.034064 Vdram = 0
2118 12:17:28.034155 Vddq = 0
2119 12:17:28.037233 Vmddr = 0
2120 12:17:28.040419 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 12:17:28.047376 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 12:17:28.047561 MEM_TYPE=3, freq_sel=15
2123 12:17:28.050791 sv_algorithm_assistance_LP4_1600
2124 12:17:28.057132 ============ PULL DRAM RESETB DOWN ============
2125 12:17:28.060726 ========== PULL DRAM RESETB DOWN end =========
2126 12:17:28.064196 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 12:17:28.067246 ===================================
2128 12:17:28.071009 LPDDR4 DRAM CONFIGURATION
2129 12:17:28.074295 ===================================
2130 12:17:28.077267 EX_ROW_EN[0] = 0x0
2131 12:17:28.077376 EX_ROW_EN[1] = 0x0
2132 12:17:28.080849 LP4Y_EN = 0x0
2133 12:17:28.080955 WORK_FSP = 0x0
2134 12:17:28.084263 WL = 0x4
2135 12:17:28.084372 RL = 0x4
2136 12:17:28.087669 BL = 0x2
2137 12:17:28.087769 RPST = 0x0
2138 12:17:28.091014 RD_PRE = 0x0
2139 12:17:28.091109 WR_PRE = 0x1
2140 12:17:28.094765 WR_PST = 0x0
2141 12:17:28.094869 DBI_WR = 0x0
2142 12:17:28.097487 DBI_RD = 0x0
2143 12:17:28.097583 OTF = 0x1
2144 12:17:28.100711 ===================================
2145 12:17:28.104258 ===================================
2146 12:17:28.107611 ANA top config
2147 12:17:28.111065 ===================================
2148 12:17:28.111176 DLL_ASYNC_EN = 0
2149 12:17:28.113993 ALL_SLAVE_EN = 0
2150 12:17:28.117599 NEW_RANK_MODE = 1
2151 12:17:28.121277 DLL_IDLE_MODE = 1
2152 12:17:28.124074 LP45_APHY_COMB_EN = 1
2153 12:17:28.124177 TX_ODT_DIS = 1
2154 12:17:28.127336 NEW_8X_MODE = 1
2155 12:17:28.131148 ===================================
2156 12:17:28.134403 ===================================
2157 12:17:28.137405 data_rate = 2400
2158 12:17:28.141061 CKR = 1
2159 12:17:28.144328 DQ_P2S_RATIO = 8
2160 12:17:28.147618 ===================================
2161 12:17:28.147733 CA_P2S_RATIO = 8
2162 12:17:28.151295 DQ_CA_OPEN = 0
2163 12:17:28.154576 DQ_SEMI_OPEN = 0
2164 12:17:28.157583 CA_SEMI_OPEN = 0
2165 12:17:28.160861 CA_FULL_RATE = 0
2166 12:17:28.164167 DQ_CKDIV4_EN = 0
2167 12:17:28.164276 CA_CKDIV4_EN = 0
2168 12:17:28.167420 CA_PREDIV_EN = 0
2169 12:17:28.171344 PH8_DLY = 17
2170 12:17:28.174263 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 12:17:28.177444 DQ_AAMCK_DIV = 4
2172 12:17:28.177548 CA_AAMCK_DIV = 4
2173 12:17:28.181340 CA_ADMCK_DIV = 4
2174 12:17:28.184476 DQ_TRACK_CA_EN = 0
2175 12:17:28.187620 CA_PICK = 1200
2176 12:17:28.190900 CA_MCKIO = 1200
2177 12:17:28.194354 MCKIO_SEMI = 0
2178 12:17:28.198011 PLL_FREQ = 2366
2179 12:17:28.200708 DQ_UI_PI_RATIO = 32
2180 12:17:28.200815 CA_UI_PI_RATIO = 0
2181 12:17:28.204766 ===================================
2182 12:17:28.207967 ===================================
2183 12:17:28.210716 memory_type:LPDDR4
2184 12:17:28.214274 GP_NUM : 10
2185 12:17:28.214393 SRAM_EN : 1
2186 12:17:28.217861 MD32_EN : 0
2187 12:17:28.221521 ===================================
2188 12:17:28.224480 [ANA_INIT] >>>>>>>>>>>>>>
2189 12:17:28.224586 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 12:17:28.230841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 12:17:28.230971 ===================================
2192 12:17:28.234612 data_rate = 2400,PCW = 0X5b00
2193 12:17:28.237785 ===================================
2194 12:17:28.241141 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 12:17:28.248041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 12:17:28.254780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 12:17:28.258058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 12:17:28.261568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 12:17:28.264706 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 12:17:28.268158 [ANA_INIT] flow start
2201 12:17:28.268275 [ANA_INIT] PLL >>>>>>>>
2202 12:17:28.270903 [ANA_INIT] PLL <<<<<<<<
2203 12:17:28.274627 [ANA_INIT] MIDPI >>>>>>>>
2204 12:17:28.274739 [ANA_INIT] MIDPI <<<<<<<<
2205 12:17:28.277846 [ANA_INIT] DLL >>>>>>>>
2206 12:17:28.281072 [ANA_INIT] DLL <<<<<<<<
2207 12:17:28.281178 [ANA_INIT] flow end
2208 12:17:28.287962 ============ LP4 DIFF to SE enter ============
2209 12:17:28.291603 ============ LP4 DIFF to SE exit ============
2210 12:17:28.291725 [ANA_INIT] <<<<<<<<<<<<<
2211 12:17:28.294850 [Flow] Enable top DCM control >>>>>
2212 12:17:28.297839 [Flow] Enable top DCM control <<<<<
2213 12:17:28.301313 Enable DLL master slave shuffle
2214 12:17:28.307938 ==============================================================
2215 12:17:28.311299 Gating Mode config
2216 12:17:28.314510 ==============================================================
2217 12:17:28.317863 Config description:
2218 12:17:28.327745 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 12:17:28.334743 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 12:17:28.338042 SELPH_MODE 0: By rank 1: By Phase
2221 12:17:28.344799 ==============================================================
2222 12:17:28.347794 GAT_TRACK_EN = 1
2223 12:17:28.351788 RX_GATING_MODE = 2
2224 12:17:28.351923 RX_GATING_TRACK_MODE = 2
2225 12:17:28.354449 SELPH_MODE = 1
2226 12:17:28.358148 PICG_EARLY_EN = 1
2227 12:17:28.362301 VALID_LAT_VALUE = 1
2228 12:17:28.368048 ==============================================================
2229 12:17:28.371294 Enter into Gating configuration >>>>
2230 12:17:28.375189 Exit from Gating configuration <<<<
2231 12:17:28.378156 Enter into DVFS_PRE_config >>>>>
2232 12:17:28.388201 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 12:17:28.391718 Exit from DVFS_PRE_config <<<<<
2234 12:17:28.395173 Enter into PICG configuration >>>>
2235 12:17:28.398336 Exit from PICG configuration <<<<
2236 12:17:28.401355 [RX_INPUT] configuration >>>>>
2237 12:17:28.404711 [RX_INPUT] configuration <<<<<
2238 12:17:28.407818 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 12:17:28.414883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 12:17:28.421359 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 12:17:28.424653 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 12:17:28.431641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 12:17:28.437830 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 12:17:28.441583 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 12:17:28.444923 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 12:17:28.451364 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 12:17:28.454614 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 12:17:28.457903 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 12:17:28.464439 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 12:17:28.468148 ===================================
2251 12:17:28.468278 LPDDR4 DRAM CONFIGURATION
2252 12:17:28.471426 ===================================
2253 12:17:28.474805 EX_ROW_EN[0] = 0x0
2254 12:17:28.477901 EX_ROW_EN[1] = 0x0
2255 12:17:28.478013 LP4Y_EN = 0x0
2256 12:17:28.481346 WORK_FSP = 0x0
2257 12:17:28.481447 WL = 0x4
2258 12:17:28.484723 RL = 0x4
2259 12:17:28.484829 BL = 0x2
2260 12:17:28.487645 RPST = 0x0
2261 12:17:28.487740 RD_PRE = 0x0
2262 12:17:28.491695 WR_PRE = 0x1
2263 12:17:28.491798 WR_PST = 0x0
2264 12:17:28.495521 DBI_WR = 0x0
2265 12:17:28.495624 DBI_RD = 0x0
2266 12:17:28.498374 OTF = 0x1
2267 12:17:28.501239 ===================================
2268 12:17:28.504594 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 12:17:28.507694 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 12:17:28.511050 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 12:17:28.514436 ===================================
2272 12:17:28.517932 LPDDR4 DRAM CONFIGURATION
2273 12:17:28.521255 ===================================
2274 12:17:28.524706 EX_ROW_EN[0] = 0x10
2275 12:17:28.524878 EX_ROW_EN[1] = 0x0
2276 12:17:28.527601 LP4Y_EN = 0x0
2277 12:17:28.527692 WORK_FSP = 0x0
2278 12:17:28.531360 WL = 0x4
2279 12:17:28.531502 RL = 0x4
2280 12:17:28.534187 BL = 0x2
2281 12:17:28.534273 RPST = 0x0
2282 12:17:28.537514 RD_PRE = 0x0
2283 12:17:28.541075 WR_PRE = 0x1
2284 12:17:28.541179 WR_PST = 0x0
2285 12:17:28.544530 DBI_WR = 0x0
2286 12:17:28.544628 DBI_RD = 0x0
2287 12:17:28.547905 OTF = 0x1
2288 12:17:28.551305 ===================================
2289 12:17:28.554665 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 12:17:28.557615 ==
2291 12:17:28.557724 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 12:17:28.564430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 12:17:28.564569 ==
2294 12:17:28.567598 [Duty_Offset_Calibration]
2295 12:17:28.567692 B0:2 B1:0 CA:4
2296 12:17:28.567756
2297 12:17:28.570962 [DutyScan_Calibration_Flow] k_type=0
2298 12:17:28.580342
2299 12:17:28.580498 ==CLK 0==
2300 12:17:28.584142 Final CLK duty delay cell = 0
2301 12:17:28.587495 [0] MAX Duty = 5031%(X100), DQS PI = 12
2302 12:17:28.590135 [0] MIN Duty = 4907%(X100), DQS PI = 8
2303 12:17:28.590236 [0] AVG Duty = 4969%(X100)
2304 12:17:28.593473
2305 12:17:28.596692 CH0 CLK Duty spec in!! Max-Min= 124%
2306 12:17:28.600539 [DutyScan_Calibration_Flow] ====Done====
2307 12:17:28.600672
2308 12:17:28.603515 [DutyScan_Calibration_Flow] k_type=1
2309 12:17:28.618714
2310 12:17:28.618977 ==DQS 0 ==
2311 12:17:28.622336 Final DQS duty delay cell = 0
2312 12:17:28.625796 [0] MAX Duty = 5062%(X100), DQS PI = 12
2313 12:17:28.628885 [0] MIN Duty = 4907%(X100), DQS PI = 2
2314 12:17:28.628991 [0] AVG Duty = 4984%(X100)
2315 12:17:28.632328
2316 12:17:28.632428 ==DQS 1 ==
2317 12:17:28.635398 Final DQS duty delay cell = -4
2318 12:17:28.638836 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2319 12:17:28.642509 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2320 12:17:28.645994 [-4] AVG Duty = 4922%(X100)
2321 12:17:28.646103
2322 12:17:28.649121 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2323 12:17:28.649215
2324 12:17:28.652199 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2325 12:17:28.655607 [DutyScan_Calibration_Flow] ====Done====
2326 12:17:28.655717
2327 12:17:28.658597 [DutyScan_Calibration_Flow] k_type=3
2328 12:17:28.676313
2329 12:17:28.676472 ==DQM 0 ==
2330 12:17:28.679377 Final DQM duty delay cell = 0
2331 12:17:28.683034 [0] MAX Duty = 5124%(X100), DQS PI = 28
2332 12:17:28.686207 [0] MIN Duty = 4907%(X100), DQS PI = 0
2333 12:17:28.686318 [0] AVG Duty = 5015%(X100)
2334 12:17:28.689666
2335 12:17:28.689764 ==DQM 1 ==
2336 12:17:28.692415 Final DQM duty delay cell = 4
2337 12:17:28.695799 [4] MAX Duty = 5124%(X100), DQS PI = 50
2338 12:17:28.699360 [4] MIN Duty = 5031%(X100), DQS PI = 12
2339 12:17:28.702675 [4] AVG Duty = 5077%(X100)
2340 12:17:28.702783
2341 12:17:28.705897 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2342 12:17:28.706003
2343 12:17:28.709133 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2344 12:17:28.712495 [DutyScan_Calibration_Flow] ====Done====
2345 12:17:28.712605
2346 12:17:28.716223 [DutyScan_Calibration_Flow] k_type=2
2347 12:17:28.731225
2348 12:17:28.731382 ==DQ 0 ==
2349 12:17:28.734134 Final DQ duty delay cell = -4
2350 12:17:28.737467 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2351 12:17:28.741209 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2352 12:17:28.744154 [-4] AVG Duty = 4969%(X100)
2353 12:17:28.744263
2354 12:17:28.744327 ==DQ 1 ==
2355 12:17:28.747534 Final DQ duty delay cell = -4
2356 12:17:28.750920 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2357 12:17:28.754614 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2358 12:17:28.758025 [-4] AVG Duty = 4938%(X100)
2359 12:17:28.758146
2360 12:17:28.760780 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2361 12:17:28.760871
2362 12:17:28.764254 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2363 12:17:28.767542 [DutyScan_Calibration_Flow] ====Done====
2364 12:17:28.767647 ==
2365 12:17:28.770763 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 12:17:28.774049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 12:17:28.774150 ==
2368 12:17:28.777359 [Duty_Offset_Calibration]
2369 12:17:28.777456 B0:1 B1:-2 CA:0
2370 12:17:28.777520
2371 12:17:28.780944 [DutyScan_Calibration_Flow] k_type=0
2372 12:17:28.791672
2373 12:17:28.791828 ==CLK 0==
2374 12:17:28.794978 Final CLK duty delay cell = 0
2375 12:17:28.798312 [0] MAX Duty = 5000%(X100), DQS PI = 0
2376 12:17:28.801987 [0] MIN Duty = 4844%(X100), DQS PI = 26
2377 12:17:28.802107 [0] AVG Duty = 4922%(X100)
2378 12:17:28.805131
2379 12:17:28.805227 CH1 CLK Duty spec in!! Max-Min= 156%
2380 12:17:28.811726 [DutyScan_Calibration_Flow] ====Done====
2381 12:17:28.811858
2382 12:17:28.815797 [DutyScan_Calibration_Flow] k_type=1
2383 12:17:28.830063
2384 12:17:28.830223 ==DQS 0 ==
2385 12:17:28.833328 Final DQS duty delay cell = -4
2386 12:17:28.836600 [-4] MAX Duty = 5031%(X100), DQS PI = 56
2387 12:17:28.840243 [-4] MIN Duty = 4907%(X100), DQS PI = 4
2388 12:17:28.843676 [-4] AVG Duty = 4969%(X100)
2389 12:17:28.843797
2390 12:17:28.843863 ==DQS 1 ==
2391 12:17:28.846777 Final DQS duty delay cell = 0
2392 12:17:28.849724 [0] MAX Duty = 5093%(X100), DQS PI = 34
2393 12:17:28.853195 [0] MIN Duty = 4875%(X100), DQS PI = 10
2394 12:17:28.856922 [0] AVG Duty = 4984%(X100)
2395 12:17:28.857047
2396 12:17:28.860235 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2397 12:17:28.860338
2398 12:17:28.863327 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2399 12:17:28.867431 [DutyScan_Calibration_Flow] ====Done====
2400 12:17:28.867544
2401 12:17:28.870436 [DutyScan_Calibration_Flow] k_type=3
2402 12:17:28.886924
2403 12:17:28.887080 ==DQM 0 ==
2404 12:17:28.890397 Final DQM duty delay cell = 0
2405 12:17:28.893360 [0] MAX Duty = 5000%(X100), DQS PI = 54
2406 12:17:28.896610 [0] MIN Duty = 4876%(X100), DQS PI = 20
2407 12:17:28.896720 [0] AVG Duty = 4938%(X100)
2408 12:17:28.900158
2409 12:17:28.900257 ==DQM 1 ==
2410 12:17:28.903309 Final DQM duty delay cell = 0
2411 12:17:28.906794 [0] MAX Duty = 5031%(X100), DQS PI = 4
2412 12:17:28.910175 [0] MIN Duty = 4907%(X100), DQS PI = 44
2413 12:17:28.910289 [0] AVG Duty = 4969%(X100)
2414 12:17:28.913813
2415 12:17:28.917164 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2416 12:17:28.917274
2417 12:17:28.920330 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2418 12:17:28.923350 [DutyScan_Calibration_Flow] ====Done====
2419 12:17:28.923476
2420 12:17:28.926862 [DutyScan_Calibration_Flow] k_type=2
2421 12:17:28.942906
2422 12:17:28.943085 ==DQ 0 ==
2423 12:17:28.946193 Final DQ duty delay cell = 0
2424 12:17:28.950012 [0] MAX Duty = 5062%(X100), DQS PI = 0
2425 12:17:28.953076 [0] MIN Duty = 4938%(X100), DQS PI = 26
2426 12:17:28.953223 [0] AVG Duty = 5000%(X100)
2427 12:17:28.953333
2428 12:17:28.956500 ==DQ 1 ==
2429 12:17:28.959984 Final DQ duty delay cell = 0
2430 12:17:28.962842 [0] MAX Duty = 5125%(X100), DQS PI = 14
2431 12:17:28.966346 [0] MIN Duty = 4969%(X100), DQS PI = 58
2432 12:17:28.966505 [0] AVG Duty = 5047%(X100)
2433 12:17:28.966605
2434 12:17:28.969768 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2435 12:17:28.973216
2436 12:17:28.976385 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2437 12:17:28.979592 [DutyScan_Calibration_Flow] ====Done====
2438 12:17:28.983028 nWR fixed to 30
2439 12:17:28.983174 [ModeRegInit_LP4] CH0 RK0
2440 12:17:28.986379 [ModeRegInit_LP4] CH0 RK1
2441 12:17:28.989618 [ModeRegInit_LP4] CH1 RK0
2442 12:17:28.989803 [ModeRegInit_LP4] CH1 RK1
2443 12:17:28.992796 match AC timing 7
2444 12:17:28.996495 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 12:17:28.999634 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 12:17:29.006654 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 12:17:29.009812 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 12:17:29.016425 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 12:17:29.016636 ==
2450 12:17:29.019711 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 12:17:29.022791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 12:17:29.022920 ==
2453 12:17:29.029498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 12:17:29.032846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2455 12:17:29.043158 [CA 0] Center 40 (10~71) winsize 62
2456 12:17:29.046402 [CA 1] Center 39 (9~70) winsize 62
2457 12:17:29.049551 [CA 2] Center 36 (6~66) winsize 61
2458 12:17:29.053138 [CA 3] Center 35 (5~66) winsize 62
2459 12:17:29.056460 [CA 4] Center 34 (4~65) winsize 62
2460 12:17:29.060196 [CA 5] Center 33 (3~63) winsize 61
2461 12:17:29.060317
2462 12:17:29.063342 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2463 12:17:29.063496
2464 12:17:29.066583 [CATrainingPosCal] consider 1 rank data
2465 12:17:29.069845 u2DelayCellTimex100 = 270/100 ps
2466 12:17:29.073210 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2467 12:17:29.076394 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2468 12:17:29.083125 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2469 12:17:29.086362 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2470 12:17:29.090056 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2471 12:17:29.092807 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2472 12:17:29.092921
2473 12:17:29.096879 CA PerBit enable=1, Macro0, CA PI delay=33
2474 12:17:29.096984
2475 12:17:29.099798 [CBTSetCACLKResult] CA Dly = 33
2476 12:17:29.099915 CS Dly: 7 (0~38)
2477 12:17:29.102952 ==
2478 12:17:29.103046 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 12:17:29.109769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 12:17:29.109910 ==
2481 12:17:29.113197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 12:17:29.119855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 12:17:29.129109 [CA 0] Center 40 (10~70) winsize 61
2484 12:17:29.132603 [CA 1] Center 40 (10~70) winsize 61
2485 12:17:29.135840 [CA 2] Center 35 (5~66) winsize 62
2486 12:17:29.139288 [CA 3] Center 35 (5~66) winsize 62
2487 12:17:29.142563 [CA 4] Center 34 (3~65) winsize 63
2488 12:17:29.145626 [CA 5] Center 33 (3~64) winsize 62
2489 12:17:29.145739
2490 12:17:29.149488 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 12:17:29.149598
2492 12:17:29.152353 [CATrainingPosCal] consider 2 rank data
2493 12:17:29.155737 u2DelayCellTimex100 = 270/100 ps
2494 12:17:29.159037 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2495 12:17:29.165861 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2496 12:17:29.169034 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2497 12:17:29.172296 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 12:17:29.175687 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2499 12:17:29.179274 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 12:17:29.179398
2501 12:17:29.182529 CA PerBit enable=1, Macro0, CA PI delay=33
2502 12:17:29.182624
2503 12:17:29.185524 [CBTSetCACLKResult] CA Dly = 33
2504 12:17:29.188873 CS Dly: 8 (0~40)
2505 12:17:29.188982
2506 12:17:29.192140 ----->DramcWriteLeveling(PI) begin...
2507 12:17:29.192236 ==
2508 12:17:29.195985 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 12:17:29.198756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 12:17:29.198860 ==
2511 12:17:29.202417 Write leveling (Byte 0): 33 => 33
2512 12:17:29.205961 Write leveling (Byte 1): 30 => 30
2513 12:17:29.209227 DramcWriteLeveling(PI) end<-----
2514 12:17:29.209335
2515 12:17:29.209401 ==
2516 12:17:29.212683 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 12:17:29.215885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 12:17:29.215993 ==
2519 12:17:29.218815 [Gating] SW mode calibration
2520 12:17:29.225958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 12:17:29.232517 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 12:17:29.235829 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
2523 12:17:29.239256 0 15 4 | B1->B0 | 2828 3333 | 1 0 | (1 1) (0 0)
2524 12:17:29.245886 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 12:17:29.248894 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 12:17:29.252785 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 12:17:29.259215 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 12:17:29.262633 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 12:17:29.266103 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2530 12:17:29.268928 1 0 0 | B1->B0 | 3131 2a2a | 1 0 | (1 0) (0 0)
2531 12:17:29.276063 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 12:17:29.279131 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 12:17:29.282368 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 12:17:29.289003 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 12:17:29.292502 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 12:17:29.295935 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 12:17:29.302336 1 0 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2538 12:17:29.305795 1 1 0 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
2539 12:17:29.309039 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2540 12:17:29.315934 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 12:17:29.319420 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 12:17:29.322370 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 12:17:29.329050 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 12:17:29.332595 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 12:17:29.335637 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 12:17:29.339222 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2547 12:17:29.345814 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2548 12:17:29.349208 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:17:29.352665 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:17:29.359167 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:17:29.362738 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:17:29.366131 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:17:29.372392 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:17:29.376027 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:17:29.379495 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:17:29.385635 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:17:29.389020 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:17:29.392231 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:17:29.399413 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:17:29.402345 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:17:29.405839 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 12:17:29.412415 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2563 12:17:29.415526 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2564 12:17:29.418988 Total UI for P1: 0, mck2ui 16
2565 12:17:29.422093 best dqsien dly found for B0: ( 1, 3, 30)
2566 12:17:29.425402 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2567 12:17:29.429029 Total UI for P1: 0, mck2ui 16
2568 12:17:29.432359 best dqsien dly found for B1: ( 1, 4, 2)
2569 12:17:29.435782 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2570 12:17:29.439100 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2571 12:17:29.439211
2572 12:17:29.442147 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2573 12:17:29.449195 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2574 12:17:29.449353 [Gating] SW calibration Done
2575 12:17:29.449460 ==
2576 12:17:29.452382 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 12:17:29.459574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 12:17:29.459723 ==
2579 12:17:29.459792 RX Vref Scan: 0
2580 12:17:29.459852
2581 12:17:29.462752 RX Vref 0 -> 0, step: 1
2582 12:17:29.462840
2583 12:17:29.465888 RX Delay -40 -> 252, step: 8
2584 12:17:29.469413 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2585 12:17:29.472194 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2586 12:17:29.475729 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2587 12:17:29.478930 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2588 12:17:29.485657 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2589 12:17:29.489491 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2590 12:17:29.492528 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2591 12:17:29.495906 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2592 12:17:29.499155 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2593 12:17:29.503083 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2594 12:17:29.509134 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2595 12:17:29.512323 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2596 12:17:29.516214 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2597 12:17:29.518969 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2598 12:17:29.525707 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2599 12:17:29.529216 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2600 12:17:29.529341 ==
2601 12:17:29.532569 Dram Type= 6, Freq= 0, CH_0, rank 0
2602 12:17:29.535964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2603 12:17:29.536080 ==
2604 12:17:29.536148 DQS Delay:
2605 12:17:29.539218 DQS0 = 0, DQS1 = 0
2606 12:17:29.539312 DQM Delay:
2607 12:17:29.542655 DQM0 = 112, DQM1 = 103
2608 12:17:29.542747 DQ Delay:
2609 12:17:29.545814 DQ0 =111, DQ1 =115, DQ2 =111, DQ3 =107
2610 12:17:29.549240 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2611 12:17:29.552622 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2612 12:17:29.555649 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =111
2613 12:17:29.555760
2614 12:17:29.555827
2615 12:17:29.559007 ==
2616 12:17:29.562637 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 12:17:29.566076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 12:17:29.566188 ==
2619 12:17:29.566254
2620 12:17:29.566313
2621 12:17:29.568893 TX Vref Scan disable
2622 12:17:29.568986 == TX Byte 0 ==
2623 12:17:29.572624 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2624 12:17:29.578789 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2625 12:17:29.578922 == TX Byte 1 ==
2626 12:17:29.585498 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2627 12:17:29.589376 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2628 12:17:29.589497 ==
2629 12:17:29.592552 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 12:17:29.595993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 12:17:29.596103 ==
2632 12:17:29.608013 TX Vref=22, minBit 0, minWin=26, winSum=418
2633 12:17:29.611258 TX Vref=24, minBit 0, minWin=26, winSum=424
2634 12:17:29.614359 TX Vref=26, minBit 13, minWin=26, winSum=432
2635 12:17:29.617873 TX Vref=28, minBit 8, minWin=26, winSum=433
2636 12:17:29.621372 TX Vref=30, minBit 7, minWin=26, winSum=432
2637 12:17:29.628204 TX Vref=32, minBit 8, minWin=26, winSum=428
2638 12:17:29.631307 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 28
2639 12:17:29.631485
2640 12:17:29.634787 Final TX Range 1 Vref 28
2641 12:17:29.634888
2642 12:17:29.634953 ==
2643 12:17:29.637954 Dram Type= 6, Freq= 0, CH_0, rank 0
2644 12:17:29.641466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2645 12:17:29.641575 ==
2646 12:17:29.644474
2647 12:17:29.644588
2648 12:17:29.644654 TX Vref Scan disable
2649 12:17:29.648120 == TX Byte 0 ==
2650 12:17:29.651334 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2651 12:17:29.654683 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2652 12:17:29.657895 == TX Byte 1 ==
2653 12:17:29.661109 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2654 12:17:29.664485 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2655 12:17:29.667917
2656 12:17:29.668026 [DATLAT]
2657 12:17:29.668094 Freq=1200, CH0 RK0
2658 12:17:29.668154
2659 12:17:29.671357 DATLAT Default: 0xd
2660 12:17:29.671495 0, 0xFFFF, sum = 0
2661 12:17:29.675768 1, 0xFFFF, sum = 0
2662 12:17:29.675874 2, 0xFFFF, sum = 0
2663 12:17:29.677809 3, 0xFFFF, sum = 0
2664 12:17:29.677895 4, 0xFFFF, sum = 0
2665 12:17:29.681405 5, 0xFFFF, sum = 0
2666 12:17:29.681505 6, 0xFFFF, sum = 0
2667 12:17:29.684785 7, 0xFFFF, sum = 0
2668 12:17:29.688159 8, 0xFFFF, sum = 0
2669 12:17:29.688272 9, 0xFFFF, sum = 0
2670 12:17:29.691193 10, 0xFFFF, sum = 0
2671 12:17:29.691287 11, 0xFFFF, sum = 0
2672 12:17:29.694552 12, 0x0, sum = 1
2673 12:17:29.694649 13, 0x0, sum = 2
2674 12:17:29.697970 14, 0x0, sum = 3
2675 12:17:29.698065 15, 0x0, sum = 4
2676 12:17:29.698131 best_step = 13
2677 12:17:29.698191
2678 12:17:29.701659 ==
2679 12:17:29.704717 Dram Type= 6, Freq= 0, CH_0, rank 0
2680 12:17:29.708094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2681 12:17:29.708202 ==
2682 12:17:29.708269 RX Vref Scan: 1
2683 12:17:29.708330
2684 12:17:29.711476 Set Vref Range= 32 -> 127
2685 12:17:29.711569
2686 12:17:29.714937 RX Vref 32 -> 127, step: 1
2687 12:17:29.715040
2688 12:17:29.717664 RX Delay -37 -> 252, step: 4
2689 12:17:29.717757
2690 12:17:29.721533 Set Vref, RX VrefLevel [Byte0]: 32
2691 12:17:29.724569 [Byte1]: 32
2692 12:17:29.724674
2693 12:17:29.727728 Set Vref, RX VrefLevel [Byte0]: 33
2694 12:17:29.731353 [Byte1]: 33
2695 12:17:29.731504
2696 12:17:29.734646 Set Vref, RX VrefLevel [Byte0]: 34
2697 12:17:29.737693 [Byte1]: 34
2698 12:17:29.742280
2699 12:17:29.742403 Set Vref, RX VrefLevel [Byte0]: 35
2700 12:17:29.745494 [Byte1]: 35
2701 12:17:29.750521
2702 12:17:29.750660 Set Vref, RX VrefLevel [Byte0]: 36
2703 12:17:29.754195 [Byte1]: 36
2704 12:17:29.758451
2705 12:17:29.758574 Set Vref, RX VrefLevel [Byte0]: 37
2706 12:17:29.761767 [Byte1]: 37
2707 12:17:29.766425
2708 12:17:29.766553 Set Vref, RX VrefLevel [Byte0]: 38
2709 12:17:29.769692 [Byte1]: 38
2710 12:17:29.774345
2711 12:17:29.774474 Set Vref, RX VrefLevel [Byte0]: 39
2712 12:17:29.777878 [Byte1]: 39
2713 12:17:29.782489
2714 12:17:29.782612 Set Vref, RX VrefLevel [Byte0]: 40
2715 12:17:29.785577 [Byte1]: 40
2716 12:17:29.790349
2717 12:17:29.790477 Set Vref, RX VrefLevel [Byte0]: 41
2718 12:17:29.793677 [Byte1]: 41
2719 12:17:29.798416
2720 12:17:29.798544 Set Vref, RX VrefLevel [Byte0]: 42
2721 12:17:29.801882 [Byte1]: 42
2722 12:17:29.806289
2723 12:17:29.806414 Set Vref, RX VrefLevel [Byte0]: 43
2724 12:17:29.809685 [Byte1]: 43
2725 12:17:29.814656
2726 12:17:29.814783 Set Vref, RX VrefLevel [Byte0]: 44
2727 12:17:29.817848 [Byte1]: 44
2728 12:17:29.822510
2729 12:17:29.822637 Set Vref, RX VrefLevel [Byte0]: 45
2730 12:17:29.825931 [Byte1]: 45
2731 12:17:29.830803
2732 12:17:29.830928 Set Vref, RX VrefLevel [Byte0]: 46
2733 12:17:29.833823 [Byte1]: 46
2734 12:17:29.838378
2735 12:17:29.838507 Set Vref, RX VrefLevel [Byte0]: 47
2736 12:17:29.841682 [Byte1]: 47
2737 12:17:29.846702
2738 12:17:29.846833 Set Vref, RX VrefLevel [Byte0]: 48
2739 12:17:29.849688 [Byte1]: 48
2740 12:17:29.854571
2741 12:17:29.854738 Set Vref, RX VrefLevel [Byte0]: 49
2742 12:17:29.857650 [Byte1]: 49
2743 12:17:29.862749
2744 12:17:29.862878 Set Vref, RX VrefLevel [Byte0]: 50
2745 12:17:29.865751 [Byte1]: 50
2746 12:17:29.870930
2747 12:17:29.871059 Set Vref, RX VrefLevel [Byte0]: 51
2748 12:17:29.873631 [Byte1]: 51
2749 12:17:29.878285
2750 12:17:29.878414 Set Vref, RX VrefLevel [Byte0]: 52
2751 12:17:29.881608 [Byte1]: 52
2752 12:17:29.886678
2753 12:17:29.886816 Set Vref, RX VrefLevel [Byte0]: 53
2754 12:17:29.889638 [Byte1]: 53
2755 12:17:29.894597
2756 12:17:29.894734 Set Vref, RX VrefLevel [Byte0]: 54
2757 12:17:29.897784 [Byte1]: 54
2758 12:17:29.902959
2759 12:17:29.903096 Set Vref, RX VrefLevel [Byte0]: 55
2760 12:17:29.906039 [Byte1]: 55
2761 12:17:29.910584
2762 12:17:29.910715 Set Vref, RX VrefLevel [Byte0]: 56
2763 12:17:29.913631 [Byte1]: 56
2764 12:17:29.918759
2765 12:17:29.918893 Set Vref, RX VrefLevel [Byte0]: 57
2766 12:17:29.921948 [Byte1]: 57
2767 12:17:29.926685
2768 12:17:29.926814 Set Vref, RX VrefLevel [Byte0]: 58
2769 12:17:29.929565 [Byte1]: 58
2770 12:17:29.934417
2771 12:17:29.934550 Set Vref, RX VrefLevel [Byte0]: 59
2772 12:17:29.938358 [Byte1]: 59
2773 12:17:29.942714
2774 12:17:29.942837 Set Vref, RX VrefLevel [Byte0]: 60
2775 12:17:29.945913 [Byte1]: 60
2776 12:17:29.950605
2777 12:17:29.950739 Set Vref, RX VrefLevel [Byte0]: 61
2778 12:17:29.953597 [Byte1]: 61
2779 12:17:29.958595
2780 12:17:29.958726 Set Vref, RX VrefLevel [Byte0]: 62
2781 12:17:29.961706 [Byte1]: 62
2782 12:17:29.966804
2783 12:17:29.966935 Set Vref, RX VrefLevel [Byte0]: 63
2784 12:17:29.969616 [Byte1]: 63
2785 12:17:29.974510
2786 12:17:29.974635 Set Vref, RX VrefLevel [Byte0]: 64
2787 12:17:29.977799 [Byte1]: 64
2788 12:17:29.982725
2789 12:17:29.982853 Set Vref, RX VrefLevel [Byte0]: 65
2790 12:17:29.985782 [Byte1]: 65
2791 12:17:29.990474
2792 12:17:29.990608 Set Vref, RX VrefLevel [Byte0]: 66
2793 12:17:29.993896 [Byte1]: 66
2794 12:17:29.998385
2795 12:17:29.998514 Set Vref, RX VrefLevel [Byte0]: 67
2796 12:17:30.001736 [Byte1]: 67
2797 12:17:30.006539
2798 12:17:30.006668 Set Vref, RX VrefLevel [Byte0]: 68
2799 12:17:30.009701 [Byte1]: 68
2800 12:17:30.014480
2801 12:17:30.014611 Set Vref, RX VrefLevel [Byte0]: 69
2802 12:17:30.018384 [Byte1]: 69
2803 12:17:30.022422
2804 12:17:30.022549 Set Vref, RX VrefLevel [Byte0]: 70
2805 12:17:30.026238 [Byte1]: 70
2806 12:17:30.030600
2807 12:17:30.030734 Set Vref, RX VrefLevel [Byte0]: 71
2808 12:17:30.033705 [Byte1]: 71
2809 12:17:30.038806
2810 12:17:30.038944 Set Vref, RX VrefLevel [Byte0]: 72
2811 12:17:30.041951 [Byte1]: 72
2812 12:17:30.046291
2813 12:17:30.046414 Set Vref, RX VrefLevel [Byte0]: 73
2814 12:17:30.050070 [Byte1]: 73
2815 12:17:30.054519
2816 12:17:30.054653 Set Vref, RX VrefLevel [Byte0]: 74
2817 12:17:30.058046 [Byte1]: 74
2818 12:17:30.062555
2819 12:17:30.062680 Final RX Vref Byte 0 = 63 to rank0
2820 12:17:30.065912 Final RX Vref Byte 1 = 50 to rank0
2821 12:17:30.069225 Final RX Vref Byte 0 = 63 to rank1
2822 12:17:30.072801 Final RX Vref Byte 1 = 50 to rank1==
2823 12:17:30.076157 Dram Type= 6, Freq= 0, CH_0, rank 0
2824 12:17:30.082738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 12:17:30.082890 ==
2826 12:17:30.082965 DQS Delay:
2827 12:17:30.083026 DQS0 = 0, DQS1 = 0
2828 12:17:30.086115 DQM Delay:
2829 12:17:30.086206 DQM0 = 112, DQM1 = 101
2830 12:17:30.089179 DQ Delay:
2831 12:17:30.092415 DQ0 =110, DQ1 =112, DQ2 =114, DQ3 =108
2832 12:17:30.095879 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2833 12:17:30.099348 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2834 12:17:30.102298 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2835 12:17:30.102411
2836 12:17:30.102480
2837 12:17:30.109228 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
2838 12:17:30.112637 CH0 RK0: MR19=303, MR18=FCFB
2839 12:17:30.119462 CH0_RK0: MR19=0x303, MR18=0xFCFB, DQSOSC=411, MR23=63, INC=38, DEC=25
2840 12:17:30.119606
2841 12:17:30.122462 ----->DramcWriteLeveling(PI) begin...
2842 12:17:30.122558 ==
2843 12:17:30.125716 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 12:17:30.129109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 12:17:30.129218 ==
2846 12:17:30.132613 Write leveling (Byte 0): 33 => 33
2847 12:17:30.135697 Write leveling (Byte 1): 31 => 31
2848 12:17:30.139358 DramcWriteLeveling(PI) end<-----
2849 12:17:30.139481
2850 12:17:30.139631 ==
2851 12:17:30.142477 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 12:17:30.149079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 12:17:30.149217 ==
2854 12:17:30.149289 [Gating] SW mode calibration
2855 12:17:30.159026 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2856 12:17:30.162497 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2857 12:17:30.166214 0 15 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2858 12:17:30.172732 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 12:17:30.175838 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 12:17:30.179251 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:17:30.185732 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 12:17:30.189076 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 12:17:30.192388 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2864 12:17:30.199504 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2865 12:17:30.202534 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2866 12:17:30.205947 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 12:17:30.212394 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 12:17:30.215646 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:17:30.218953 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 12:17:30.226205 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 12:17:30.229014 1 0 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
2872 12:17:30.232343 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2873 12:17:30.239021 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2874 12:17:30.242553 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 12:17:30.245616 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:17:30.249489 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:17:30.255628 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:17:30.258867 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 12:17:30.262368 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 12:17:30.269170 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2881 12:17:30.272485 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 12:17:30.275739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:17:30.282220 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:17:30.285819 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:17:30.289488 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:17:30.295937 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:17:30.299041 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:17:30.302398 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:17:30.309182 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:17:30.312334 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:17:30.315631 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:17:30.322264 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:17:30.325581 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:17:30.328872 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:17:30.336100 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:17:30.339349 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2897 12:17:30.342535 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2898 12:17:30.345993 Total UI for P1: 0, mck2ui 16
2899 12:17:30.349286 best dqsien dly found for B0: ( 1, 3, 28)
2900 12:17:30.352337 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 12:17:30.356052 Total UI for P1: 0, mck2ui 16
2902 12:17:30.359415 best dqsien dly found for B1: ( 1, 3, 30)
2903 12:17:30.363590 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2904 12:17:30.365983 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2905 12:17:30.366096
2906 12:17:30.372726 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2907 12:17:30.375679 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2908 12:17:30.379080 [Gating] SW calibration Done
2909 12:17:30.379195 ==
2910 12:17:30.382422 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 12:17:30.385973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 12:17:30.386086 ==
2913 12:17:30.386181 RX Vref Scan: 0
2914 12:17:30.386264
2915 12:17:30.389028 RX Vref 0 -> 0, step: 1
2916 12:17:30.389124
2917 12:17:30.392580 RX Delay -40 -> 252, step: 8
2918 12:17:30.395905 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2919 12:17:30.398919 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2920 12:17:30.405850 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2921 12:17:30.409071 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2922 12:17:30.412665 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2923 12:17:30.416088 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2924 12:17:30.419063 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2925 12:17:30.422397 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2926 12:17:30.429120 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2927 12:17:30.432271 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2928 12:17:30.435562 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2929 12:17:30.438904 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2930 12:17:30.442368 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2931 12:17:30.449072 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2932 12:17:30.452300 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2933 12:17:30.455836 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2934 12:17:30.455958 ==
2935 12:17:30.459078 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 12:17:30.462459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 12:17:30.462570 ==
2938 12:17:30.465851 DQS Delay:
2939 12:17:30.465953 DQS0 = 0, DQS1 = 0
2940 12:17:30.468892 DQM Delay:
2941 12:17:30.468987 DQM0 = 112, DQM1 = 101
2942 12:17:30.472200 DQ Delay:
2943 12:17:30.475669 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2944 12:17:30.478818 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2945 12:17:30.482361 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2946 12:17:30.485890 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
2947 12:17:30.486024
2948 12:17:30.486118
2949 12:17:30.486200 ==
2950 12:17:30.489187 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 12:17:30.492502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 12:17:30.492609 ==
2953 12:17:30.492701
2954 12:17:30.492783
2955 12:17:30.495691 TX Vref Scan disable
2956 12:17:30.495787 == TX Byte 0 ==
2957 12:17:30.502508 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2958 12:17:30.505693 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2959 12:17:30.505809 == TX Byte 1 ==
2960 12:17:30.512410 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2961 12:17:30.515853 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2962 12:17:30.515976 ==
2963 12:17:30.519203 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 12:17:30.522861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 12:17:30.522979 ==
2966 12:17:30.535916 TX Vref=22, minBit 2, minWin=26, winSum=425
2967 12:17:30.538683 TX Vref=24, minBit 3, minWin=26, winSum=431
2968 12:17:30.542323 TX Vref=26, minBit 0, minWin=27, winSum=442
2969 12:17:30.545579 TX Vref=28, minBit 0, minWin=27, winSum=439
2970 12:17:30.548728 TX Vref=30, minBit 1, minWin=27, winSum=443
2971 12:17:30.551875 TX Vref=32, minBit 5, minWin=26, winSum=440
2972 12:17:30.558931 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 30
2973 12:17:30.559081
2974 12:17:30.562139 Final TX Range 1 Vref 30
2975 12:17:30.562246
2976 12:17:30.562334 ==
2977 12:17:30.565434 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 12:17:30.568837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 12:17:30.568951 ==
2980 12:17:30.572142
2981 12:17:30.572242
2982 12:17:30.572329 TX Vref Scan disable
2983 12:17:30.575303 == TX Byte 0 ==
2984 12:17:30.578435 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2985 12:17:30.582114 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2986 12:17:30.585407 == TX Byte 1 ==
2987 12:17:30.588463 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2988 12:17:30.592190 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2989 12:17:30.595148
2990 12:17:30.595264 [DATLAT]
2991 12:17:30.595370 Freq=1200, CH0 RK1
2992 12:17:30.595495
2993 12:17:30.598627 DATLAT Default: 0xd
2994 12:17:30.598729 0, 0xFFFF, sum = 0
2995 12:17:30.601822 1, 0xFFFF, sum = 0
2996 12:17:30.601919 2, 0xFFFF, sum = 0
2997 12:17:30.605781 3, 0xFFFF, sum = 0
2998 12:17:30.605885 4, 0xFFFF, sum = 0
2999 12:17:30.609026 5, 0xFFFF, sum = 0
3000 12:17:30.609123 6, 0xFFFF, sum = 0
3001 12:17:30.612467 7, 0xFFFF, sum = 0
3002 12:17:30.615225 8, 0xFFFF, sum = 0
3003 12:17:30.615368 9, 0xFFFF, sum = 0
3004 12:17:30.618916 10, 0xFFFF, sum = 0
3005 12:17:30.619021 11, 0xFFFF, sum = 0
3006 12:17:30.621873 12, 0x0, sum = 1
3007 12:17:30.621973 13, 0x0, sum = 2
3008 12:17:30.625432 14, 0x0, sum = 3
3009 12:17:30.625531 15, 0x0, sum = 4
3010 12:17:30.625600 best_step = 13
3011 12:17:30.625659
3012 12:17:30.628827 ==
3013 12:17:30.631982 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 12:17:30.635238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 12:17:30.635348 ==
3016 12:17:30.635459 RX Vref Scan: 0
3017 12:17:30.635521
3018 12:17:30.638895 RX Vref 0 -> 0, step: 1
3019 12:17:30.638995
3020 12:17:30.642105 RX Delay -37 -> 252, step: 4
3021 12:17:30.645296 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3022 12:17:30.651857 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3023 12:17:30.655318 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3024 12:17:30.658763 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3025 12:17:30.661840 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3026 12:17:30.665577 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3027 12:17:30.668802 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3028 12:17:30.675549 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3029 12:17:30.679077 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3030 12:17:30.682363 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3031 12:17:30.685771 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3032 12:17:30.688473 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3033 12:17:30.695688 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3034 12:17:30.698606 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3035 12:17:30.701974 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3036 12:17:30.705514 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3037 12:17:30.705636 ==
3038 12:17:30.708477 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 12:17:30.715224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 12:17:30.715370 ==
3041 12:17:30.715511 DQS Delay:
3042 12:17:30.715614 DQS0 = 0, DQS1 = 0
3043 12:17:30.719213 DQM Delay:
3044 12:17:30.719336 DQM0 = 111, DQM1 = 100
3045 12:17:30.722395 DQ Delay:
3046 12:17:30.725755 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =110
3047 12:17:30.728552 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3048 12:17:30.732202 DQ8 =90, DQ9 =82, DQ10 =104, DQ11 =92
3049 12:17:30.735533 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =108
3050 12:17:30.735649
3051 12:17:30.735718
3052 12:17:30.742464 [DQSOSCAuto] RK1, (LSB)MR18= 0x16fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 401 ps
3053 12:17:30.745525 CH0 RK1: MR19=403, MR18=16FE
3054 12:17:30.752169 CH0_RK1: MR19=0x403, MR18=0x16FE, DQSOSC=401, MR23=63, INC=40, DEC=27
3055 12:17:30.756158 [RxdqsGatingPostProcess] freq 1200
3056 12:17:30.762500 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 12:17:30.765771 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 12:17:30.765893 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 12:17:30.769043 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 12:17:30.772245 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 12:17:30.775674 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 12:17:30.778556 best DQS1 dly(2T, 0.5T) = (0, 11)
3063 12:17:30.782023 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 12:17:30.785398 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3065 12:17:30.788701 Pre-setting of DQS Precalculation
3066 12:17:30.795692 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 12:17:30.795844 ==
3068 12:17:30.798800 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 12:17:30.802365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 12:17:30.802480 ==
3071 12:17:30.808687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 12:17:30.811758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3073 12:17:30.821393 [CA 0] Center 37 (7~67) winsize 61
3074 12:17:30.824791 [CA 1] Center 38 (8~68) winsize 61
3075 12:17:30.828175 [CA 2] Center 34 (5~64) winsize 60
3076 12:17:30.831512 [CA 3] Center 33 (3~64) winsize 62
3077 12:17:30.834773 [CA 4] Center 34 (4~64) winsize 61
3078 12:17:30.838117 [CA 5] Center 33 (3~63) winsize 61
3079 12:17:30.838239
3080 12:17:30.841250 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3081 12:17:30.841351
3082 12:17:30.844820 [CATrainingPosCal] consider 1 rank data
3083 12:17:30.848008 u2DelayCellTimex100 = 270/100 ps
3084 12:17:30.851521 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3085 12:17:30.858228 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3086 12:17:30.861495 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3087 12:17:30.864731 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3088 12:17:30.868050 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3089 12:17:30.871515 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3090 12:17:30.871633
3091 12:17:30.874560 CA PerBit enable=1, Macro0, CA PI delay=33
3092 12:17:30.874657
3093 12:17:30.878134 [CBTSetCACLKResult] CA Dly = 33
3094 12:17:30.878235 CS Dly: 6 (0~37)
3095 12:17:30.881145 ==
3096 12:17:30.881241 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 12:17:30.887813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 12:17:30.887944 ==
3099 12:17:30.891101 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 12:17:30.897743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3101 12:17:30.907312 [CA 0] Center 37 (8~67) winsize 60
3102 12:17:30.910577 [CA 1] Center 37 (7~68) winsize 62
3103 12:17:30.913814 [CA 2] Center 34 (4~65) winsize 62
3104 12:17:30.917315 [CA 3] Center 33 (3~64) winsize 62
3105 12:17:30.920414 [CA 4] Center 34 (4~65) winsize 62
3106 12:17:30.923712 [CA 5] Center 33 (3~64) winsize 62
3107 12:17:30.923832
3108 12:17:30.927013 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3109 12:17:30.927117
3110 12:17:30.930462 [CATrainingPosCal] consider 2 rank data
3111 12:17:30.934047 u2DelayCellTimex100 = 270/100 ps
3112 12:17:30.937275 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3113 12:17:30.940326 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3114 12:17:30.946926 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3115 12:17:30.950843 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3116 12:17:30.953613 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3117 12:17:30.956938 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3118 12:17:30.957138
3119 12:17:30.960571 CA PerBit enable=1, Macro0, CA PI delay=33
3120 12:17:30.960681
3121 12:17:30.963894 [CBTSetCACLKResult] CA Dly = 33
3122 12:17:30.964035 CS Dly: 7 (0~40)
3123 12:17:30.964104
3124 12:17:30.967096 ----->DramcWriteLeveling(PI) begin...
3125 12:17:30.970172 ==
3126 12:17:30.973482 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 12:17:30.977031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 12:17:30.977187 ==
3129 12:17:30.980365 Write leveling (Byte 0): 25 => 25
3130 12:17:30.983615 Write leveling (Byte 1): 28 => 28
3131 12:17:30.987030 DramcWriteLeveling(PI) end<-----
3132 12:17:30.987141
3133 12:17:30.987208 ==
3134 12:17:30.990279 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 12:17:30.993854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 12:17:30.993963 ==
3137 12:17:30.997150 [Gating] SW mode calibration
3138 12:17:31.003790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 12:17:31.007378 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 12:17:31.014048 0 15 0 | B1->B0 | 2828 2c2b | 0 1 | (0 0) (0 0)
3141 12:17:31.017297 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 12:17:31.020272 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 12:17:31.027486 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 12:17:31.030448 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 12:17:31.034350 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 12:17:31.040305 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 12:17:31.043788 0 15 28 | B1->B0 | 3131 3232 | 1 0 | (1 0) (1 0)
3148 12:17:31.046906 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 12:17:31.053823 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 12:17:31.057290 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 12:17:31.060526 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:17:31.066989 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:17:31.070118 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 12:17:31.073797 1 0 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
3155 12:17:31.080440 1 0 28 | B1->B0 | 4343 3838 | 0 0 | (0 0) (1 1)
3156 12:17:31.083698 1 1 0 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
3157 12:17:31.087099 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:17:31.093731 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 12:17:31.097065 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:17:31.100654 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:17:31.103586 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:17:31.110368 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:17:31.113563 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3164 12:17:31.116864 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 12:17:31.123675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:17:31.127363 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:17:31.130613 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:17:31.136896 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:17:31.140648 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:17:31.143949 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:17:31.150325 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:17:31.153878 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:17:31.157120 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:17:31.164391 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:17:31.167700 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:17:31.170479 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:17:31.177334 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:17:31.180506 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 12:17:31.184009 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3180 12:17:31.187238 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 12:17:31.190635 Total UI for P1: 0, mck2ui 16
3182 12:17:31.194033 best dqsien dly found for B0: ( 1, 3, 28)
3183 12:17:31.197249 Total UI for P1: 0, mck2ui 16
3184 12:17:31.200439 best dqsien dly found for B1: ( 1, 3, 28)
3185 12:17:31.203903 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3186 12:17:31.207084 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3187 12:17:31.207175
3188 12:17:31.213859 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3189 12:17:31.217296 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3190 12:17:31.220438 [Gating] SW calibration Done
3191 12:17:31.220539 ==
3192 12:17:31.224256 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 12:17:31.227067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 12:17:31.227158 ==
3195 12:17:31.227224 RX Vref Scan: 0
3196 12:17:31.227284
3197 12:17:31.230768 RX Vref 0 -> 0, step: 1
3198 12:17:31.230853
3199 12:17:31.234073 RX Delay -40 -> 252, step: 8
3200 12:17:31.237323 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3201 12:17:31.240661 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3202 12:17:31.247145 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3203 12:17:31.250476 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3204 12:17:31.253792 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3205 12:17:31.257290 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3206 12:17:31.260639 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3207 12:17:31.265032 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3208 12:17:31.270774 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3209 12:17:31.274290 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3210 12:17:31.277439 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3211 12:17:31.281212 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3212 12:17:31.284741 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3213 12:17:31.290918 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3214 12:17:31.294025 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3215 12:17:31.297528 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3216 12:17:31.297624 ==
3217 12:17:31.300845 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 12:17:31.304055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 12:17:31.304150 ==
3220 12:17:31.307366 DQS Delay:
3221 12:17:31.307482 DQS0 = 0, DQS1 = 0
3222 12:17:31.310949 DQM Delay:
3223 12:17:31.311035 DQM0 = 115, DQM1 = 106
3224 12:17:31.311100 DQ Delay:
3225 12:17:31.317524 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3226 12:17:31.320875 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3227 12:17:31.324067 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3228 12:17:31.327211 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3229 12:17:31.327302
3230 12:17:31.327366
3231 12:17:31.327472 ==
3232 12:17:31.330756 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 12:17:31.334257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 12:17:31.334348 ==
3235 12:17:31.334414
3236 12:17:31.334473
3237 12:17:31.337196 TX Vref Scan disable
3238 12:17:31.340685 == TX Byte 0 ==
3239 12:17:31.344315 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3240 12:17:31.347346 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3241 12:17:31.350413 == TX Byte 1 ==
3242 12:17:31.354424 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3243 12:17:31.357326 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3244 12:17:31.357419 ==
3245 12:17:31.360768 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 12:17:31.363859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 12:17:31.363947 ==
3248 12:17:31.377283 TX Vref=22, minBit 1, minWin=24, winSum=405
3249 12:17:31.380868 TX Vref=24, minBit 1, minWin=24, winSum=411
3250 12:17:31.383678 TX Vref=26, minBit 1, minWin=25, winSum=415
3251 12:17:31.386953 TX Vref=28, minBit 1, minWin=25, winSum=419
3252 12:17:31.390603 TX Vref=30, minBit 1, minWin=25, winSum=418
3253 12:17:31.393924 TX Vref=32, minBit 1, minWin=25, winSum=415
3254 12:17:31.400762 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
3255 12:17:31.400888
3256 12:17:31.403946 Final TX Range 1 Vref 28
3257 12:17:31.404036
3258 12:17:31.404160 ==
3259 12:17:31.407898 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 12:17:31.410395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 12:17:31.410483 ==
3262 12:17:31.410548
3263 12:17:31.410608
3264 12:17:31.414005 TX Vref Scan disable
3265 12:17:31.417445 == TX Byte 0 ==
3266 12:17:31.420610 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3267 12:17:31.423823 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3268 12:17:31.427510 == TX Byte 1 ==
3269 12:17:31.430904 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 12:17:31.434189 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 12:17:31.434279
3272 12:17:31.437425 [DATLAT]
3273 12:17:31.437511 Freq=1200, CH1 RK0
3274 12:17:31.437576
3275 12:17:31.440928 DATLAT Default: 0xd
3276 12:17:31.441012 0, 0xFFFF, sum = 0
3277 12:17:31.444394 1, 0xFFFF, sum = 0
3278 12:17:31.444479 2, 0xFFFF, sum = 0
3279 12:17:31.447362 3, 0xFFFF, sum = 0
3280 12:17:31.447474 4, 0xFFFF, sum = 0
3281 12:17:31.450450 5, 0xFFFF, sum = 0
3282 12:17:31.450534 6, 0xFFFF, sum = 0
3283 12:17:31.454025 7, 0xFFFF, sum = 0
3284 12:17:31.454112 8, 0xFFFF, sum = 0
3285 12:17:31.457175 9, 0xFFFF, sum = 0
3286 12:17:31.460747 10, 0xFFFF, sum = 0
3287 12:17:31.460843 11, 0xFFFF, sum = 0
3288 12:17:31.464119 12, 0x0, sum = 1
3289 12:17:31.464209 13, 0x0, sum = 2
3290 12:17:31.464279 14, 0x0, sum = 3
3291 12:17:31.467888 15, 0x0, sum = 4
3292 12:17:31.467976 best_step = 13
3293 12:17:31.468040
3294 12:17:31.468099 ==
3295 12:17:31.470325 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 12:17:31.477184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 12:17:31.477306 ==
3298 12:17:31.477373 RX Vref Scan: 1
3299 12:17:31.477434
3300 12:17:31.480752 Set Vref Range= 32 -> 127
3301 12:17:31.480837
3302 12:17:31.484054 RX Vref 32 -> 127, step: 1
3303 12:17:31.484140
3304 12:17:31.487528 RX Delay -21 -> 252, step: 4
3305 12:17:31.487616
3306 12:17:31.490453 Set Vref, RX VrefLevel [Byte0]: 32
3307 12:17:31.490539 [Byte1]: 32
3308 12:17:31.495314
3309 12:17:31.495430 Set Vref, RX VrefLevel [Byte0]: 33
3310 12:17:31.498884 [Byte1]: 33
3311 12:17:31.503593
3312 12:17:31.503692 Set Vref, RX VrefLevel [Byte0]: 34
3313 12:17:31.506731 [Byte1]: 34
3314 12:17:31.511162
3315 12:17:31.511258 Set Vref, RX VrefLevel [Byte0]: 35
3316 12:17:31.514756 [Byte1]: 35
3317 12:17:31.519378
3318 12:17:31.519503 Set Vref, RX VrefLevel [Byte0]: 36
3319 12:17:31.522854 [Byte1]: 36
3320 12:17:31.527336
3321 12:17:31.527444 Set Vref, RX VrefLevel [Byte0]: 37
3322 12:17:31.530489 [Byte1]: 37
3323 12:17:31.535438
3324 12:17:31.535534 Set Vref, RX VrefLevel [Byte0]: 38
3325 12:17:31.538736 [Byte1]: 38
3326 12:17:31.543037
3327 12:17:31.543129 Set Vref, RX VrefLevel [Byte0]: 39
3328 12:17:31.546153 [Byte1]: 39
3329 12:17:31.550944
3330 12:17:31.551042 Set Vref, RX VrefLevel [Byte0]: 40
3331 12:17:31.554074 [Byte1]: 40
3332 12:17:31.559169
3333 12:17:31.559273 Set Vref, RX VrefLevel [Byte0]: 41
3334 12:17:31.562344 [Byte1]: 41
3335 12:17:31.566831
3336 12:17:31.566928 Set Vref, RX VrefLevel [Byte0]: 42
3337 12:17:31.569809 [Byte1]: 42
3338 12:17:31.574740
3339 12:17:31.574843 Set Vref, RX VrefLevel [Byte0]: 43
3340 12:17:31.578355 [Byte1]: 43
3341 12:17:31.582642
3342 12:17:31.582741 Set Vref, RX VrefLevel [Byte0]: 44
3343 12:17:31.585856 [Byte1]: 44
3344 12:17:31.590500
3345 12:17:31.590604 Set Vref, RX VrefLevel [Byte0]: 45
3346 12:17:31.593598 [Byte1]: 45
3347 12:17:31.598559
3348 12:17:31.598653 Set Vref, RX VrefLevel [Byte0]: 46
3349 12:17:31.601632 [Byte1]: 46
3350 12:17:31.606311
3351 12:17:31.606401 Set Vref, RX VrefLevel [Byte0]: 47
3352 12:17:31.609864 [Byte1]: 47
3353 12:17:31.614212
3354 12:17:31.614311 Set Vref, RX VrefLevel [Byte0]: 48
3355 12:17:31.617404 [Byte1]: 48
3356 12:17:31.622337
3357 12:17:31.622485 Set Vref, RX VrefLevel [Byte0]: 49
3358 12:17:31.625866 [Byte1]: 49
3359 12:17:31.630423
3360 12:17:31.630520 Set Vref, RX VrefLevel [Byte0]: 50
3361 12:17:31.633836 [Byte1]: 50
3362 12:17:31.638460
3363 12:17:31.638562 Set Vref, RX VrefLevel [Byte0]: 51
3364 12:17:31.641209 [Byte1]: 51
3365 12:17:31.646349
3366 12:17:31.646454 Set Vref, RX VrefLevel [Byte0]: 52
3367 12:17:31.649529 [Byte1]: 52
3368 12:17:31.653837
3369 12:17:31.653975 Set Vref, RX VrefLevel [Byte0]: 53
3370 12:17:31.657261 [Byte1]: 53
3371 12:17:31.662091
3372 12:17:31.662194 Set Vref, RX VrefLevel [Byte0]: 54
3373 12:17:31.664890 [Byte1]: 54
3374 12:17:31.669726
3375 12:17:31.669827 Set Vref, RX VrefLevel [Byte0]: 55
3376 12:17:31.673126 [Byte1]: 55
3377 12:17:31.678040
3378 12:17:31.678162 Set Vref, RX VrefLevel [Byte0]: 56
3379 12:17:31.680902 [Byte1]: 56
3380 12:17:31.685497
3381 12:17:31.685607 Set Vref, RX VrefLevel [Byte0]: 57
3382 12:17:31.688752 [Byte1]: 57
3383 12:17:31.693381
3384 12:17:31.693489 Set Vref, RX VrefLevel [Byte0]: 58
3385 12:17:31.696529 [Byte1]: 58
3386 12:17:31.701383
3387 12:17:31.701483 Set Vref, RX VrefLevel [Byte0]: 59
3388 12:17:31.704553 [Byte1]: 59
3389 12:17:31.709509
3390 12:17:31.709605 Set Vref, RX VrefLevel [Byte0]: 60
3391 12:17:31.712475 [Byte1]: 60
3392 12:17:31.716947
3393 12:17:31.717039 Set Vref, RX VrefLevel [Byte0]: 61
3394 12:17:31.720384 [Byte1]: 61
3395 12:17:31.725217
3396 12:17:31.725325 Set Vref, RX VrefLevel [Byte0]: 62
3397 12:17:31.728250 [Byte1]: 62
3398 12:17:31.732794
3399 12:17:31.732894 Set Vref, RX VrefLevel [Byte0]: 63
3400 12:17:31.736785 [Byte1]: 63
3401 12:17:31.741011
3402 12:17:31.741113 Set Vref, RX VrefLevel [Byte0]: 64
3403 12:17:31.744247 [Byte1]: 64
3404 12:17:31.749121
3405 12:17:31.749218 Set Vref, RX VrefLevel [Byte0]: 65
3406 12:17:31.752367 [Byte1]: 65
3407 12:17:31.756833
3408 12:17:31.756935 Set Vref, RX VrefLevel [Byte0]: 66
3409 12:17:31.760173 [Byte1]: 66
3410 12:17:31.764547
3411 12:17:31.764649 Set Vref, RX VrefLevel [Byte0]: 67
3412 12:17:31.768361 [Byte1]: 67
3413 12:17:31.772621
3414 12:17:31.772725 Set Vref, RX VrefLevel [Byte0]: 68
3415 12:17:31.776062 [Byte1]: 68
3416 12:17:31.780584
3417 12:17:31.780696 Set Vref, RX VrefLevel [Byte0]: 69
3418 12:17:31.783757 [Byte1]: 69
3419 12:17:31.788857
3420 12:17:31.788990 Set Vref, RX VrefLevel [Byte0]: 70
3421 12:17:31.792079 [Byte1]: 70
3422 12:17:31.796736
3423 12:17:31.796925 Set Vref, RX VrefLevel [Byte0]: 71
3424 12:17:31.799571 [Byte1]: 71
3425 12:17:31.804190
3426 12:17:31.804294 Final RX Vref Byte 0 = 57 to rank0
3427 12:17:31.807604 Final RX Vref Byte 1 = 48 to rank0
3428 12:17:31.811217 Final RX Vref Byte 0 = 57 to rank1
3429 12:17:31.814557 Final RX Vref Byte 1 = 48 to rank1==
3430 12:17:31.817821 Dram Type= 6, Freq= 0, CH_1, rank 0
3431 12:17:31.824525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 12:17:31.824667 ==
3433 12:17:31.824766 DQS Delay:
3434 12:17:31.824850 DQS0 = 0, DQS1 = 0
3435 12:17:31.827751 DQM Delay:
3436 12:17:31.827842 DQM0 = 115, DQM1 = 106
3437 12:17:31.831221 DQ Delay:
3438 12:17:31.834329 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3439 12:17:31.838006 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =114
3440 12:17:31.841479 DQ8 =94, DQ9 =100, DQ10 =104, DQ11 =102
3441 12:17:31.844771 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =112
3442 12:17:31.844877
3443 12:17:31.844966
3444 12:17:31.851235 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3fa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 415 ps
3445 12:17:31.854406 CH1 RK0: MR19=303, MR18=F3FA
3446 12:17:31.860910 CH1_RK0: MR19=0x303, MR18=0xF3FA, DQSOSC=412, MR23=63, INC=38, DEC=25
3447 12:17:31.861050
3448 12:17:31.864426 ----->DramcWriteLeveling(PI) begin...
3449 12:17:31.864532 ==
3450 12:17:31.868496 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 12:17:31.871375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 12:17:31.874415 ==
3453 12:17:31.874517 Write leveling (Byte 0): 24 => 24
3454 12:17:31.877628 Write leveling (Byte 1): 28 => 28
3455 12:17:31.881109 DramcWriteLeveling(PI) end<-----
3456 12:17:31.881214
3457 12:17:31.881304 ==
3458 12:17:31.884273 Dram Type= 6, Freq= 0, CH_1, rank 1
3459 12:17:31.891548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 12:17:31.891688 ==
3461 12:17:31.891788 [Gating] SW mode calibration
3462 12:17:31.901229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3463 12:17:31.904208 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3464 12:17:31.908054 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3465 12:17:31.914512 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 12:17:31.917489 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 12:17:31.920923 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 12:17:31.927546 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 12:17:31.930975 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3470 12:17:31.934461 0 15 24 | B1->B0 | 3333 2525 | 1 0 | (1 0) (1 0)
3471 12:17:31.941030 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3472 12:17:31.944751 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 12:17:31.947852 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 12:17:31.954685 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 12:17:31.957711 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 12:17:31.960968 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 12:17:31.967624 1 0 20 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3478 12:17:31.971175 1 0 24 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
3479 12:17:31.974330 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3480 12:17:31.981013 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 12:17:31.984300 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 12:17:31.987490 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 12:17:31.994428 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 12:17:31.997573 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 12:17:32.001040 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 12:17:32.007960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3487 12:17:32.010892 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3488 12:17:32.014331 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:17:32.017607 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:17:32.024430 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 12:17:32.027228 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 12:17:32.030711 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 12:17:32.037742 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 12:17:32.040591 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 12:17:32.043868 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 12:17:32.050415 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 12:17:32.053665 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 12:17:32.057561 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 12:17:32.063921 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 12:17:32.067194 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 12:17:32.070279 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3502 12:17:32.076972 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3503 12:17:32.080308 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 12:17:32.083716 Total UI for P1: 0, mck2ui 16
3505 12:17:32.086952 best dqsien dly found for B0: ( 1, 3, 22)
3506 12:17:32.090375 Total UI for P1: 0, mck2ui 16
3507 12:17:32.093904 best dqsien dly found for B1: ( 1, 3, 24)
3508 12:17:32.096965 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3509 12:17:32.100204 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3510 12:17:32.100307
3511 12:17:32.103877 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3512 12:17:32.106828 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3513 12:17:32.110002 [Gating] SW calibration Done
3514 12:17:32.110111 ==
3515 12:17:32.113515 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 12:17:32.120167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 12:17:32.120291 ==
3518 12:17:32.120360 RX Vref Scan: 0
3519 12:17:32.120420
3520 12:17:32.123513 RX Vref 0 -> 0, step: 1
3521 12:17:32.123608
3522 12:17:32.126776 RX Delay -40 -> 252, step: 8
3523 12:17:32.130211 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3524 12:17:32.133426 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3525 12:17:32.136877 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3526 12:17:32.139967 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3527 12:17:32.146725 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3528 12:17:32.149949 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3529 12:17:32.153125 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3530 12:17:32.156586 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3531 12:17:32.159983 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3532 12:17:32.166489 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3533 12:17:32.169674 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3534 12:17:32.173723 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3535 12:17:32.176537 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3536 12:17:32.179703 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3537 12:17:32.186442 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3538 12:17:32.189830 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3539 12:17:32.189940 ==
3540 12:17:32.193212 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 12:17:32.196514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 12:17:32.196610 ==
3543 12:17:32.199676 DQS Delay:
3544 12:17:32.199766 DQS0 = 0, DQS1 = 0
3545 12:17:32.199831 DQM Delay:
3546 12:17:32.203304 DQM0 = 112, DQM1 = 107
3547 12:17:32.203417 DQ Delay:
3548 12:17:32.206701 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3549 12:17:32.210056 DQ4 =107, DQ5 =123, DQ6 =119, DQ7 =111
3550 12:17:32.212941 DQ8 =91, DQ9 =99, DQ10 =111, DQ11 =99
3551 12:17:32.219523 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =115
3552 12:17:32.219662
3553 12:17:32.219730
3554 12:17:32.219790 ==
3555 12:17:32.222768 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 12:17:32.226139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 12:17:32.226241 ==
3558 12:17:32.226331
3559 12:17:32.226414
3560 12:17:32.229635 TX Vref Scan disable
3561 12:17:32.229731 == TX Byte 0 ==
3562 12:17:32.236210 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3563 12:17:32.239619 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3564 12:17:32.239730 == TX Byte 1 ==
3565 12:17:32.246003 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3566 12:17:32.249729 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3567 12:17:32.249836 ==
3568 12:17:32.252775 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 12:17:32.256186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 12:17:32.256283 ==
3571 12:17:32.269075 TX Vref=22, minBit 0, minWin=25, winSum=415
3572 12:17:32.272211 TX Vref=24, minBit 0, minWin=25, winSum=417
3573 12:17:32.275481 TX Vref=26, minBit 0, minWin=25, winSum=419
3574 12:17:32.278919 TX Vref=28, minBit 0, minWin=25, winSum=424
3575 12:17:32.282220 TX Vref=30, minBit 1, minWin=25, winSum=422
3576 12:17:32.285692 TX Vref=32, minBit 0, minWin=26, winSum=423
3577 12:17:32.292333 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 32
3578 12:17:32.292465
3579 12:17:32.295361 Final TX Range 1 Vref 32
3580 12:17:32.295488
3581 12:17:32.295573 ==
3582 12:17:32.298951 Dram Type= 6, Freq= 0, CH_1, rank 1
3583 12:17:32.302018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3584 12:17:32.302123 ==
3585 12:17:32.305346
3586 12:17:32.305430
3587 12:17:32.305515 TX Vref Scan disable
3588 12:17:32.309129 == TX Byte 0 ==
3589 12:17:32.312450 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3590 12:17:32.315726 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3591 12:17:32.318633 == TX Byte 1 ==
3592 12:17:32.321847 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3593 12:17:32.328781 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3594 12:17:32.328882
3595 12:17:32.328970 [DATLAT]
3596 12:17:32.329052 Freq=1200, CH1 RK1
3597 12:17:32.329131
3598 12:17:32.332400 DATLAT Default: 0xd
3599 12:17:32.332485 0, 0xFFFF, sum = 0
3600 12:17:32.335312 1, 0xFFFF, sum = 0
3601 12:17:32.338735 2, 0xFFFF, sum = 0
3602 12:17:32.338822 3, 0xFFFF, sum = 0
3603 12:17:32.342237 4, 0xFFFF, sum = 0
3604 12:17:32.342324 5, 0xFFFF, sum = 0
3605 12:17:32.345261 6, 0xFFFF, sum = 0
3606 12:17:32.345347 7, 0xFFFF, sum = 0
3607 12:17:32.348616 8, 0xFFFF, sum = 0
3608 12:17:32.348704 9, 0xFFFF, sum = 0
3609 12:17:32.352029 10, 0xFFFF, sum = 0
3610 12:17:32.352116 11, 0xFFFF, sum = 0
3611 12:17:32.355046 12, 0x0, sum = 1
3612 12:17:32.355133 13, 0x0, sum = 2
3613 12:17:32.358752 14, 0x0, sum = 3
3614 12:17:32.358840 15, 0x0, sum = 4
3615 12:17:32.362208 best_step = 13
3616 12:17:32.362294
3617 12:17:32.362380 ==
3618 12:17:32.365216 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 12:17:32.368637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 12:17:32.368723 ==
3621 12:17:32.368808 RX Vref Scan: 0
3622 12:17:32.368889
3623 12:17:32.371797 RX Vref 0 -> 0, step: 1
3624 12:17:32.371882
3625 12:17:32.374935 RX Delay -21 -> 252, step: 4
3626 12:17:32.378381 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3627 12:17:32.385298 iDelay=195, Bit 1, Center 106 (39 ~ 174) 136
3628 12:17:32.388479 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3629 12:17:32.391724 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3630 12:17:32.395051 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3631 12:17:32.398401 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3632 12:17:32.405007 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3633 12:17:32.408144 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3634 12:17:32.411310 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
3635 12:17:32.415091 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3636 12:17:32.418114 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3637 12:17:32.424710 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3638 12:17:32.428285 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3639 12:17:32.431789 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3640 12:17:32.435119 iDelay=195, Bit 14, Center 118 (59 ~ 178) 120
3641 12:17:32.441602 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3642 12:17:32.441688 ==
3643 12:17:32.444723 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 12:17:32.447946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 12:17:32.448030 ==
3646 12:17:32.448116 DQS Delay:
3647 12:17:32.451493 DQS0 = 0, DQS1 = 0
3648 12:17:32.451577 DQM Delay:
3649 12:17:32.454734 DQM0 = 111, DQM1 = 109
3650 12:17:32.454819 DQ Delay:
3651 12:17:32.457790 DQ0 =114, DQ1 =106, DQ2 =100, DQ3 =108
3652 12:17:32.461420 DQ4 =106, DQ5 =122, DQ6 =124, DQ7 =108
3653 12:17:32.464314 DQ8 =94, DQ9 =100, DQ10 =110, DQ11 =100
3654 12:17:32.467798 DQ12 =120, DQ13 =116, DQ14 =118, DQ15 =118
3655 12:17:32.467884
3656 12:17:32.467970
3657 12:17:32.477915 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3658 12:17:32.481139 CH1 RK1: MR19=304, MR18=F707
3659 12:17:32.484578 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3660 12:17:32.487821 [RxdqsGatingPostProcess] freq 1200
3661 12:17:32.494283 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3662 12:17:32.497463 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 12:17:32.500735 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 12:17:32.504469 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 12:17:32.507380 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 12:17:32.510821 best DQS0 dly(2T, 0.5T) = (0, 11)
3667 12:17:32.514102 best DQS1 dly(2T, 0.5T) = (0, 11)
3668 12:17:32.517844 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3669 12:17:32.521279 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3670 12:17:32.523877 Pre-setting of DQS Precalculation
3671 12:17:32.527597 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3672 12:17:32.534027 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3673 12:17:32.544370 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3674 12:17:32.544490
3675 12:17:32.544557
3676 12:17:32.547526 [Calibration Summary] 2400 Mbps
3677 12:17:32.547611 CH 0, Rank 0
3678 12:17:32.550685 SW Impedance : PASS
3679 12:17:32.550768 DUTY Scan : NO K
3680 12:17:32.553846 ZQ Calibration : PASS
3681 12:17:32.553928 Jitter Meter : NO K
3682 12:17:32.557254 CBT Training : PASS
3683 12:17:32.560231 Write leveling : PASS
3684 12:17:32.560316 RX DQS gating : PASS
3685 12:17:32.564039 RX DQ/DQS(RDDQC) : PASS
3686 12:17:32.567238 TX DQ/DQS : PASS
3687 12:17:32.567324 RX DATLAT : PASS
3688 12:17:32.570361 RX DQ/DQS(Engine): PASS
3689 12:17:32.574047 TX OE : NO K
3690 12:17:32.574132 All Pass.
3691 12:17:32.574196
3692 12:17:32.574257 CH 0, Rank 1
3693 12:17:32.577467 SW Impedance : PASS
3694 12:17:32.580650 DUTY Scan : NO K
3695 12:17:32.580733 ZQ Calibration : PASS
3696 12:17:32.583489 Jitter Meter : NO K
3697 12:17:32.587204 CBT Training : PASS
3698 12:17:32.587288 Write leveling : PASS
3699 12:17:32.590364 RX DQS gating : PASS
3700 12:17:32.593662 RX DQ/DQS(RDDQC) : PASS
3701 12:17:32.593746 TX DQ/DQS : PASS
3702 12:17:32.596714 RX DATLAT : PASS
3703 12:17:32.600039 RX DQ/DQS(Engine): PASS
3704 12:17:32.600123 TX OE : NO K
3705 12:17:32.600189 All Pass.
3706 12:17:32.603610
3707 12:17:32.603693 CH 1, Rank 0
3708 12:17:32.607101 SW Impedance : PASS
3709 12:17:32.607183 DUTY Scan : NO K
3710 12:17:32.610468 ZQ Calibration : PASS
3711 12:17:32.610551 Jitter Meter : NO K
3712 12:17:32.613220 CBT Training : PASS
3713 12:17:32.617115 Write leveling : PASS
3714 12:17:32.617202 RX DQS gating : PASS
3715 12:17:32.619812 RX DQ/DQS(RDDQC) : PASS
3716 12:17:32.623228 TX DQ/DQS : PASS
3717 12:17:32.623312 RX DATLAT : PASS
3718 12:17:32.626916 RX DQ/DQS(Engine): PASS
3719 12:17:32.630076 TX OE : NO K
3720 12:17:32.630163 All Pass.
3721 12:17:32.630227
3722 12:17:32.630288 CH 1, Rank 1
3723 12:17:32.633213 SW Impedance : PASS
3724 12:17:32.636734 DUTY Scan : NO K
3725 12:17:32.636817 ZQ Calibration : PASS
3726 12:17:32.640113 Jitter Meter : NO K
3727 12:17:32.643514 CBT Training : PASS
3728 12:17:32.643596 Write leveling : PASS
3729 12:17:32.646785 RX DQS gating : PASS
3730 12:17:32.650191 RX DQ/DQS(RDDQC) : PASS
3731 12:17:32.650274 TX DQ/DQS : PASS
3732 12:17:32.652934 RX DATLAT : PASS
3733 12:17:32.656106 RX DQ/DQS(Engine): PASS
3734 12:17:32.656188 TX OE : NO K
3735 12:17:32.660128 All Pass.
3736 12:17:32.660211
3737 12:17:32.660276 DramC Write-DBI off
3738 12:17:32.663065 PER_BANK_REFRESH: Hybrid Mode
3739 12:17:32.663147 TX_TRACKING: ON
3740 12:17:32.673693 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3741 12:17:32.676601 [FAST_K] Save calibration result to emmc
3742 12:17:32.679641 dramc_set_vcore_voltage set vcore to 650000
3743 12:17:32.683091 Read voltage for 600, 5
3744 12:17:32.683173 Vio18 = 0
3745 12:17:32.686626 Vcore = 650000
3746 12:17:32.686708 Vdram = 0
3747 12:17:32.686772 Vddq = 0
3748 12:17:32.686831 Vmddr = 0
3749 12:17:32.692869 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3750 12:17:32.699608 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3751 12:17:32.699699 MEM_TYPE=3, freq_sel=19
3752 12:17:32.703006 sv_algorithm_assistance_LP4_1600
3753 12:17:32.706324 ============ PULL DRAM RESETB DOWN ============
3754 12:17:32.713108 ========== PULL DRAM RESETB DOWN end =========
3755 12:17:32.716353 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3756 12:17:32.719860 ===================================
3757 12:17:32.722599 LPDDR4 DRAM CONFIGURATION
3758 12:17:32.726446 ===================================
3759 12:17:32.726542 EX_ROW_EN[0] = 0x0
3760 12:17:32.729549 EX_ROW_EN[1] = 0x0
3761 12:17:32.729636 LP4Y_EN = 0x0
3762 12:17:32.732686 WORK_FSP = 0x0
3763 12:17:32.732772 WL = 0x2
3764 12:17:32.735967 RL = 0x2
3765 12:17:32.739378 BL = 0x2
3766 12:17:32.739507 RPST = 0x0
3767 12:17:32.742532 RD_PRE = 0x0
3768 12:17:32.742619 WR_PRE = 0x1
3769 12:17:32.746185 WR_PST = 0x0
3770 12:17:32.746272 DBI_WR = 0x0
3771 12:17:32.749451 DBI_RD = 0x0
3772 12:17:32.749539 OTF = 0x1
3773 12:17:32.752391 ===================================
3774 12:17:32.755956 ===================================
3775 12:17:32.759025 ANA top config
3776 12:17:32.762854 ===================================
3777 12:17:32.762948 DLL_ASYNC_EN = 0
3778 12:17:32.766068 ALL_SLAVE_EN = 1
3779 12:17:32.769372 NEW_RANK_MODE = 1
3780 12:17:32.772807 DLL_IDLE_MODE = 1
3781 12:17:32.772895 LP45_APHY_COMB_EN = 1
3782 12:17:32.776036 TX_ODT_DIS = 1
3783 12:17:32.779188 NEW_8X_MODE = 1
3784 12:17:32.782643 ===================================
3785 12:17:32.786156 ===================================
3786 12:17:32.789350 data_rate = 1200
3787 12:17:32.792580 CKR = 1
3788 12:17:32.796148 DQ_P2S_RATIO = 8
3789 12:17:32.799133 ===================================
3790 12:17:32.799222 CA_P2S_RATIO = 8
3791 12:17:32.802758 DQ_CA_OPEN = 0
3792 12:17:32.805833 DQ_SEMI_OPEN = 0
3793 12:17:32.809333 CA_SEMI_OPEN = 0
3794 12:17:32.812679 CA_FULL_RATE = 0
3795 12:17:32.815607 DQ_CKDIV4_EN = 1
3796 12:17:32.815692 CA_CKDIV4_EN = 1
3797 12:17:32.818776 CA_PREDIV_EN = 0
3798 12:17:32.822111 PH8_DLY = 0
3799 12:17:32.825585 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3800 12:17:32.828689 DQ_AAMCK_DIV = 4
3801 12:17:32.832492 CA_AAMCK_DIV = 4
3802 12:17:32.832578 CA_ADMCK_DIV = 4
3803 12:17:32.835706 DQ_TRACK_CA_EN = 0
3804 12:17:32.838826 CA_PICK = 600
3805 12:17:32.842611 CA_MCKIO = 600
3806 12:17:32.845941 MCKIO_SEMI = 0
3807 12:17:32.848678 PLL_FREQ = 2288
3808 12:17:32.852104 DQ_UI_PI_RATIO = 32
3809 12:17:32.852194 CA_UI_PI_RATIO = 0
3810 12:17:32.855127 ===================================
3811 12:17:32.858916 ===================================
3812 12:17:32.862250 memory_type:LPDDR4
3813 12:17:32.865351 GP_NUM : 10
3814 12:17:32.865444 SRAM_EN : 1
3815 12:17:32.868514 MD32_EN : 0
3816 12:17:32.871839 ===================================
3817 12:17:32.875218 [ANA_INIT] >>>>>>>>>>>>>>
3818 12:17:32.878755 <<<<<< [CONFIGURE PHASE]: ANA_TX
3819 12:17:32.882272 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3820 12:17:32.885349 ===================================
3821 12:17:32.885438 data_rate = 1200,PCW = 0X5800
3822 12:17:32.888814 ===================================
3823 12:17:32.892085 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3824 12:17:32.898336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 12:17:32.904881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3826 12:17:32.908540 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3827 12:17:32.911692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3828 12:17:32.914998 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3829 12:17:32.918046 [ANA_INIT] flow start
3830 12:17:32.922003 [ANA_INIT] PLL >>>>>>>>
3831 12:17:32.922094 [ANA_INIT] PLL <<<<<<<<
3832 12:17:32.924776 [ANA_INIT] MIDPI >>>>>>>>
3833 12:17:32.928030 [ANA_INIT] MIDPI <<<<<<<<
3834 12:17:32.928117 [ANA_INIT] DLL >>>>>>>>
3835 12:17:32.931352 [ANA_INIT] flow end
3836 12:17:32.934871 ============ LP4 DIFF to SE enter ============
3837 12:17:32.938404 ============ LP4 DIFF to SE exit ============
3838 12:17:32.941452 [ANA_INIT] <<<<<<<<<<<<<
3839 12:17:32.944605 [Flow] Enable top DCM control >>>>>
3840 12:17:32.948014 [Flow] Enable top DCM control <<<<<
3841 12:17:32.951101 Enable DLL master slave shuffle
3842 12:17:32.957839 ==============================================================
3843 12:17:32.957944 Gating Mode config
3844 12:17:32.964894 ==============================================================
3845 12:17:32.965005 Config description:
3846 12:17:32.975037 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3847 12:17:32.980808 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3848 12:17:32.987672 SELPH_MODE 0: By rank 1: By Phase
3849 12:17:32.994364 ==============================================================
3850 12:17:32.994482 GAT_TRACK_EN = 1
3851 12:17:32.997304 RX_GATING_MODE = 2
3852 12:17:33.001177 RX_GATING_TRACK_MODE = 2
3853 12:17:33.003897 SELPH_MODE = 1
3854 12:17:33.007778 PICG_EARLY_EN = 1
3855 12:17:33.010489 VALID_LAT_VALUE = 1
3856 12:17:33.017050 ==============================================================
3857 12:17:33.020710 Enter into Gating configuration >>>>
3858 12:17:33.024061 Exit from Gating configuration <<<<
3859 12:17:33.027318 Enter into DVFS_PRE_config >>>>>
3860 12:17:33.037044 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3861 12:17:33.040457 Exit from DVFS_PRE_config <<<<<
3862 12:17:33.043821 Enter into PICG configuration >>>>
3863 12:17:33.046965 Exit from PICG configuration <<<<
3864 12:17:33.049993 [RX_INPUT] configuration >>>>>
3865 12:17:33.053611 [RX_INPUT] configuration <<<<<
3866 12:17:33.056613 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3867 12:17:33.063742 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3868 12:17:33.070506 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3869 12:17:33.073537 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3870 12:17:33.079892 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 12:17:33.086959 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 12:17:33.090345 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3873 12:17:33.096406 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3874 12:17:33.100112 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3875 12:17:33.103221 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3876 12:17:33.106642 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3877 12:17:33.113127 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3878 12:17:33.116636 ===================================
3879 12:17:33.116746 LPDDR4 DRAM CONFIGURATION
3880 12:17:33.120011 ===================================
3881 12:17:33.123173 EX_ROW_EN[0] = 0x0
3882 12:17:33.126411 EX_ROW_EN[1] = 0x0
3883 12:17:33.126510 LP4Y_EN = 0x0
3884 12:17:33.129612 WORK_FSP = 0x0
3885 12:17:33.129703 WL = 0x2
3886 12:17:33.132948 RL = 0x2
3887 12:17:33.133038 BL = 0x2
3888 12:17:33.136790 RPST = 0x0
3889 12:17:33.136881 RD_PRE = 0x0
3890 12:17:33.140013 WR_PRE = 0x1
3891 12:17:33.140103 WR_PST = 0x0
3892 12:17:33.143668 DBI_WR = 0x0
3893 12:17:33.143766 DBI_RD = 0x0
3894 12:17:33.146827 OTF = 0x1
3895 12:17:33.149798 ===================================
3896 12:17:33.153440 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3897 12:17:33.156345 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3898 12:17:33.163030 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 12:17:33.166505 ===================================
3900 12:17:33.166612 LPDDR4 DRAM CONFIGURATION
3901 12:17:33.169770 ===================================
3902 12:17:33.173155 EX_ROW_EN[0] = 0x10
3903 12:17:33.173249 EX_ROW_EN[1] = 0x0
3904 12:17:33.176502 LP4Y_EN = 0x0
3905 12:17:33.179776 WORK_FSP = 0x0
3906 12:17:33.179871 WL = 0x2
3907 12:17:33.183270 RL = 0x2
3908 12:17:33.183373 BL = 0x2
3909 12:17:33.186285 RPST = 0x0
3910 12:17:33.186388 RD_PRE = 0x0
3911 12:17:33.189959 WR_PRE = 0x1
3912 12:17:33.190069 WR_PST = 0x0
3913 12:17:33.192973 DBI_WR = 0x0
3914 12:17:33.193084 DBI_RD = 0x0
3915 12:17:33.196291 OTF = 0x1
3916 12:17:33.199898 ===================================
3917 12:17:33.206683 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3918 12:17:33.209923 nWR fixed to 30
3919 12:17:33.210050 [ModeRegInit_LP4] CH0 RK0
3920 12:17:33.213229 [ModeRegInit_LP4] CH0 RK1
3921 12:17:33.216382 [ModeRegInit_LP4] CH1 RK0
3922 12:17:33.216499 [ModeRegInit_LP4] CH1 RK1
3923 12:17:33.219674 match AC timing 17
3924 12:17:33.223120 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3925 12:17:33.225975 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3926 12:17:33.232651 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3927 12:17:33.235854 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3928 12:17:33.242812 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3929 12:17:33.242958 ==
3930 12:17:33.245853 Dram Type= 6, Freq= 0, CH_0, rank 0
3931 12:17:33.249582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 12:17:33.249701 ==
3933 12:17:33.255736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 12:17:33.262707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3935 12:17:33.265947 [CA 0] Center 37 (7~67) winsize 61
3936 12:17:33.269268 [CA 1] Center 37 (7~67) winsize 61
3937 12:17:33.272635 [CA 2] Center 35 (5~65) winsize 61
3938 12:17:33.275568 [CA 3] Center 35 (5~65) winsize 61
3939 12:17:33.278892 [CA 4] Center 34 (4~65) winsize 62
3940 12:17:33.282283 [CA 5] Center 34 (4~64) winsize 61
3941 12:17:33.282375
3942 12:17:33.285980 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3943 12:17:33.286067
3944 12:17:33.288940 [CATrainingPosCal] consider 1 rank data
3945 12:17:33.292119 u2DelayCellTimex100 = 270/100 ps
3946 12:17:33.295565 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3947 12:17:33.298972 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3948 12:17:33.301974 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3949 12:17:33.305942 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3950 12:17:33.308969 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3951 12:17:33.311935 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3952 12:17:33.312020
3953 12:17:33.318685 CA PerBit enable=1, Macro0, CA PI delay=34
3954 12:17:33.318803
3955 12:17:33.318870 [CBTSetCACLKResult] CA Dly = 34
3956 12:17:33.322023 CS Dly: 6 (0~37)
3957 12:17:33.322108 ==
3958 12:17:33.325201 Dram Type= 6, Freq= 0, CH_0, rank 1
3959 12:17:33.328544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 12:17:33.328632 ==
3961 12:17:33.335215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3962 12:17:33.342461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3963 12:17:33.345123 [CA 0] Center 37 (7~67) winsize 61
3964 12:17:33.348479 [CA 1] Center 36 (6~67) winsize 62
3965 12:17:33.352212 [CA 2] Center 35 (5~65) winsize 61
3966 12:17:33.355175 [CA 3] Center 34 (4~65) winsize 62
3967 12:17:33.358598 [CA 4] Center 34 (4~64) winsize 61
3968 12:17:33.361555 [CA 5] Center 33 (3~64) winsize 62
3969 12:17:33.361727
3970 12:17:33.365243 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3971 12:17:33.365356
3972 12:17:33.368142 [CATrainingPosCal] consider 2 rank data
3973 12:17:33.371550 u2DelayCellTimex100 = 270/100 ps
3974 12:17:33.374854 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3975 12:17:33.378129 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3976 12:17:33.381926 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3977 12:17:33.385096 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3978 12:17:33.388480 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3979 12:17:33.395285 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3980 12:17:33.395445
3981 12:17:33.398330 CA PerBit enable=1, Macro0, CA PI delay=34
3982 12:17:33.398415
3983 12:17:33.401518 [CBTSetCACLKResult] CA Dly = 34
3984 12:17:33.401602 CS Dly: 6 (0~38)
3985 12:17:33.401666
3986 12:17:33.405362 ----->DramcWriteLeveling(PI) begin...
3987 12:17:33.405454 ==
3988 12:17:33.408155 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 12:17:33.411302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3990 12:17:33.414604 ==
3991 12:17:33.414688 Write leveling (Byte 0): 35 => 35
3992 12:17:33.418526 Write leveling (Byte 1): 31 => 31
3993 12:17:33.421824 DramcWriteLeveling(PI) end<-----
3994 12:17:33.421912
3995 12:17:33.421976 ==
3996 12:17:33.425067 Dram Type= 6, Freq= 0, CH_0, rank 0
3997 12:17:33.431486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 12:17:33.431633 ==
3999 12:17:33.434584 [Gating] SW mode calibration
4000 12:17:33.441586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4001 12:17:33.444900 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4002 12:17:33.451271 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 12:17:33.454660 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 12:17:33.458238 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 12:17:33.465056 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4006 12:17:33.467724 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4007 12:17:33.471177 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 12:17:33.474589 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 12:17:33.481650 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 12:17:33.484504 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 12:17:33.487951 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 12:17:33.494572 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 12:17:33.498088 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4014 12:17:33.501149 0 10 16 | B1->B0 | 3030 3838 | 1 1 | (0 0) (0 0)
4015 12:17:33.507659 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 12:17:33.511010 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 12:17:33.514359 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 12:17:33.520698 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 12:17:33.524174 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 12:17:33.527620 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 12:17:33.534185 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4022 12:17:33.537600 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4023 12:17:33.540695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:17:33.547246 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:17:33.550577 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 12:17:33.554109 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 12:17:33.560844 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 12:17:33.564212 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 12:17:33.567792 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 12:17:33.574081 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 12:17:33.577262 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 12:17:33.580652 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 12:17:33.587039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 12:17:33.590756 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 12:17:33.593982 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 12:17:33.600493 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 12:17:33.603764 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4038 12:17:33.607047 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4039 12:17:33.610566 Total UI for P1: 0, mck2ui 16
4040 12:17:33.613593 best dqsien dly found for B0: ( 0, 13, 12)
4041 12:17:33.620726 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 12:17:33.620866 Total UI for P1: 0, mck2ui 16
4043 12:17:33.623621 best dqsien dly found for B1: ( 0, 13, 16)
4044 12:17:33.630379 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4045 12:17:33.633494 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4046 12:17:33.633613
4047 12:17:33.636961 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4048 12:17:33.640091 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4049 12:17:33.643626 [Gating] SW calibration Done
4050 12:17:33.643735 ==
4051 12:17:33.646961 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 12:17:33.650558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 12:17:33.650667 ==
4054 12:17:33.653486 RX Vref Scan: 0
4055 12:17:33.653589
4056 12:17:33.653677 RX Vref 0 -> 0, step: 1
4057 12:17:33.653761
4058 12:17:33.656683 RX Delay -230 -> 252, step: 16
4059 12:17:33.663328 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4060 12:17:33.666603 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4061 12:17:33.669913 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4062 12:17:33.673376 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4063 12:17:33.676697 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4064 12:17:33.683136 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4065 12:17:33.686461 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4066 12:17:33.690135 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4067 12:17:33.693384 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4068 12:17:33.699940 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4069 12:17:33.703042 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4070 12:17:33.706569 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4071 12:17:33.709914 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4072 12:17:33.716398 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4073 12:17:33.719662 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4074 12:17:33.722963 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4075 12:17:33.723078 ==
4076 12:17:33.726927 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 12:17:33.729842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 12:17:33.729956 ==
4079 12:17:33.732601 DQS Delay:
4080 12:17:33.732707 DQS0 = 0, DQS1 = 0
4081 12:17:33.735913 DQM Delay:
4082 12:17:33.736017 DQM0 = 38, DQM1 = 30
4083 12:17:33.736106 DQ Delay:
4084 12:17:33.739482 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4085 12:17:33.742526 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4086 12:17:33.745798 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =17
4087 12:17:33.749290 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4088 12:17:33.749398
4089 12:17:33.752354
4090 12:17:33.752461 ==
4091 12:17:33.756072 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 12:17:33.759415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 12:17:33.759540 ==
4094 12:17:33.759629
4095 12:17:33.759713
4096 12:17:33.762860 TX Vref Scan disable
4097 12:17:33.762962 == TX Byte 0 ==
4098 12:17:33.769445 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4099 12:17:33.772875 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4100 12:17:33.772986 == TX Byte 1 ==
4101 12:17:33.779286 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4102 12:17:33.782700 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4103 12:17:33.782807 ==
4104 12:17:33.786054 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 12:17:33.788939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 12:17:33.789044 ==
4107 12:17:33.789133
4108 12:17:33.789218
4109 12:17:33.792226 TX Vref Scan disable
4110 12:17:33.795965 == TX Byte 0 ==
4111 12:17:33.799320 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4112 12:17:33.802499 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4113 12:17:33.805730 == TX Byte 1 ==
4114 12:17:33.809169 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4115 12:17:33.812124 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4116 12:17:33.812230
4117 12:17:33.815573 [DATLAT]
4118 12:17:33.815677 Freq=600, CH0 RK0
4119 12:17:33.815764
4120 12:17:33.819047 DATLAT Default: 0x9
4121 12:17:33.819150 0, 0xFFFF, sum = 0
4122 12:17:33.822115 1, 0xFFFF, sum = 0
4123 12:17:33.822226 2, 0xFFFF, sum = 0
4124 12:17:33.825655 3, 0xFFFF, sum = 0
4125 12:17:33.825761 4, 0xFFFF, sum = 0
4126 12:17:33.829171 5, 0xFFFF, sum = 0
4127 12:17:33.829276 6, 0xFFFF, sum = 0
4128 12:17:33.832060 7, 0xFFFF, sum = 0
4129 12:17:33.832168 8, 0x0, sum = 1
4130 12:17:33.835942 9, 0x0, sum = 2
4131 12:17:33.836056 10, 0x0, sum = 3
4132 12:17:33.838981 11, 0x0, sum = 4
4133 12:17:33.839088 best_step = 9
4134 12:17:33.839181
4135 12:17:33.839271 ==
4136 12:17:33.842346 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 12:17:33.849219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 12:17:33.849346 ==
4139 12:17:33.849445 RX Vref Scan: 1
4140 12:17:33.849537
4141 12:17:33.852166 RX Vref 0 -> 0, step: 1
4142 12:17:33.852271
4143 12:17:33.856209 RX Delay -195 -> 252, step: 8
4144 12:17:33.856324
4145 12:17:33.858763 Set Vref, RX VrefLevel [Byte0]: 63
4146 12:17:33.861935 [Byte1]: 50
4147 12:17:33.862043
4148 12:17:33.865689 Final RX Vref Byte 0 = 63 to rank0
4149 12:17:33.869080 Final RX Vref Byte 1 = 50 to rank0
4150 12:17:33.872254 Final RX Vref Byte 0 = 63 to rank1
4151 12:17:33.875677 Final RX Vref Byte 1 = 50 to rank1==
4152 12:17:33.878862 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 12:17:33.881885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 12:17:33.881998 ==
4155 12:17:33.885478 DQS Delay:
4156 12:17:33.885588 DQS0 = 0, DQS1 = 0
4157 12:17:33.885682 DQM Delay:
4158 12:17:33.888687 DQM0 = 35, DQM1 = 28
4159 12:17:33.888794 DQ Delay:
4160 12:17:33.892264 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4161 12:17:33.895180 DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =44
4162 12:17:33.898579 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4163 12:17:33.901959 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4164 12:17:33.902073
4165 12:17:33.902167
4166 12:17:33.911493 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4167 12:17:33.915045 CH0 RK0: MR19=808, MR18=3E3D
4168 12:17:33.918283 CH0_RK0: MR19=0x808, MR18=0x3E3D, DQSOSC=398, MR23=63, INC=165, DEC=110
4169 12:17:33.921696
4170 12:17:33.924854 ----->DramcWriteLeveling(PI) begin...
4171 12:17:33.924985 ==
4172 12:17:33.928076 Dram Type= 6, Freq= 0, CH_0, rank 1
4173 12:17:33.931481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 12:17:33.931596 ==
4175 12:17:33.935128 Write leveling (Byte 0): 31 => 31
4176 12:17:33.938520 Write leveling (Byte 1): 33 => 33
4177 12:17:33.941357 DramcWriteLeveling(PI) end<-----
4178 12:17:33.941489
4179 12:17:33.941585 ==
4180 12:17:33.944705 Dram Type= 6, Freq= 0, CH_0, rank 1
4181 12:17:33.947819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 12:17:33.947933 ==
4183 12:17:33.951313 [Gating] SW mode calibration
4184 12:17:33.958107 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4185 12:17:33.964518 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4186 12:17:33.967791 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 12:17:33.970896 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 12:17:33.977996 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 12:17:33.980953 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
4190 12:17:33.984537 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4191 12:17:33.991200 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 12:17:33.994206 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 12:17:33.997787 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 12:17:34.004012 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 12:17:34.007571 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 12:17:34.010741 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 12:17:34.017567 0 10 12 | B1->B0 | 2626 3e3e | 0 1 | (0 0) (1 1)
4198 12:17:34.020629 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
4199 12:17:34.023980 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 12:17:34.030518 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 12:17:34.034081 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 12:17:34.037513 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 12:17:34.043893 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 12:17:34.047069 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 12:17:34.050336 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4206 12:17:34.057235 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4207 12:17:34.060636 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:17:34.063567 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:17:34.070055 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:17:34.073859 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 12:17:34.076973 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 12:17:34.083521 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 12:17:34.087293 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 12:17:34.090299 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 12:17:34.096567 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 12:17:34.100213 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 12:17:34.103059 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 12:17:34.110146 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 12:17:34.113423 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 12:17:34.116560 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4221 12:17:34.123085 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4222 12:17:34.126541 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 12:17:34.129578 Total UI for P1: 0, mck2ui 16
4224 12:17:34.133218 best dqsien dly found for B0: ( 0, 13, 10)
4225 12:17:34.136496 Total UI for P1: 0, mck2ui 16
4226 12:17:34.139861 best dqsien dly found for B1: ( 0, 13, 12)
4227 12:17:34.142570 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4228 12:17:34.146509 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4229 12:17:34.146618
4230 12:17:34.149267 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4231 12:17:34.152716 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4232 12:17:34.156499 [Gating] SW calibration Done
4233 12:17:34.156609 ==
4234 12:17:34.159302 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 12:17:34.163101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 12:17:34.163213 ==
4237 12:17:34.166396 RX Vref Scan: 0
4238 12:17:34.166503
4239 12:17:34.169141 RX Vref 0 -> 0, step: 1
4240 12:17:34.169248
4241 12:17:34.172440 RX Delay -230 -> 252, step: 16
4242 12:17:34.175892 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4243 12:17:34.179112 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4244 12:17:34.182671 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4245 12:17:34.189065 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4246 12:17:34.192595 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4247 12:17:34.195907 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4248 12:17:34.199102 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4249 12:17:34.202439 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4250 12:17:34.209215 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4251 12:17:34.212213 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4252 12:17:34.215320 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4253 12:17:34.218691 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4254 12:17:34.225575 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4255 12:17:34.228807 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4256 12:17:34.232311 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4257 12:17:34.235650 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4258 12:17:34.235763 ==
4259 12:17:34.238939 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 12:17:34.245624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 12:17:34.245764 ==
4262 12:17:34.245864 DQS Delay:
4263 12:17:34.249007 DQS0 = 0, DQS1 = 0
4264 12:17:34.249119 DQM Delay:
4265 12:17:34.251944 DQM0 = 36, DQM1 = 29
4266 12:17:34.252051 DQ Delay:
4267 12:17:34.255078 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4268 12:17:34.258659 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4269 12:17:34.262349 DQ8 =17, DQ9 =9, DQ10 =33, DQ11 =25
4270 12:17:34.265293 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =33
4271 12:17:34.265403
4272 12:17:34.265494
4273 12:17:34.265581 ==
4274 12:17:34.268320 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 12:17:34.271648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 12:17:34.271754 ==
4277 12:17:34.271841
4278 12:17:34.271926
4279 12:17:34.275229 TX Vref Scan disable
4280 12:17:34.278365 == TX Byte 0 ==
4281 12:17:34.281427 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4282 12:17:34.285368 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4283 12:17:34.288507 == TX Byte 1 ==
4284 12:17:34.291461 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4285 12:17:34.295048 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4286 12:17:34.295157 ==
4287 12:17:34.298521 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 12:17:34.301788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 12:17:34.304700 ==
4290 12:17:34.304805
4291 12:17:34.304897
4292 12:17:34.304984 TX Vref Scan disable
4293 12:17:34.308927 == TX Byte 0 ==
4294 12:17:34.312405 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4295 12:17:34.318399 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4296 12:17:34.318532 == TX Byte 1 ==
4297 12:17:34.322109 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4298 12:17:34.329008 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4299 12:17:34.329155
4300 12:17:34.329250 [DATLAT]
4301 12:17:34.329338 Freq=600, CH0 RK1
4302 12:17:34.329425
4303 12:17:34.331875 DATLAT Default: 0x9
4304 12:17:34.331977 0, 0xFFFF, sum = 0
4305 12:17:34.335326 1, 0xFFFF, sum = 0
4306 12:17:34.338915 2, 0xFFFF, sum = 0
4307 12:17:34.339021 3, 0xFFFF, sum = 0
4308 12:17:34.341862 4, 0xFFFF, sum = 0
4309 12:17:34.341968 5, 0xFFFF, sum = 0
4310 12:17:34.345123 6, 0xFFFF, sum = 0
4311 12:17:34.345228 7, 0xFFFF, sum = 0
4312 12:17:34.348376 8, 0x0, sum = 1
4313 12:17:34.348482 9, 0x0, sum = 2
4314 12:17:34.348573 10, 0x0, sum = 3
4315 12:17:34.352156 11, 0x0, sum = 4
4316 12:17:34.352263 best_step = 9
4317 12:17:34.352352
4318 12:17:34.352438 ==
4319 12:17:34.355258 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 12:17:34.361342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 12:17:34.361472 ==
4322 12:17:34.361565 RX Vref Scan: 0
4323 12:17:34.361652
4324 12:17:34.364866 RX Vref 0 -> 0, step: 1
4325 12:17:34.364976
4326 12:17:34.368320 RX Delay -195 -> 252, step: 8
4327 12:17:34.374718 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4328 12:17:34.377807 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4329 12:17:34.381323 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4330 12:17:34.384699 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4331 12:17:34.387808 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4332 12:17:34.394880 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4333 12:17:34.398255 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4334 12:17:34.401062 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4335 12:17:34.404908 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4336 12:17:34.410968 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4337 12:17:34.415045 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4338 12:17:34.417917 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4339 12:17:34.420924 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4340 12:17:34.427822 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4341 12:17:34.431258 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4342 12:17:34.434333 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4343 12:17:34.434459 ==
4344 12:17:34.437808 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 12:17:34.441294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 12:17:34.441407 ==
4347 12:17:34.444406 DQS Delay:
4348 12:17:34.444515 DQS0 = 0, DQS1 = 0
4349 12:17:34.447381 DQM Delay:
4350 12:17:34.447511 DQM0 = 33, DQM1 = 29
4351 12:17:34.447654 DQ Delay:
4352 12:17:34.450726 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4353 12:17:34.454149 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4354 12:17:34.457377 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =20
4355 12:17:34.460955 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4356 12:17:34.461074
4357 12:17:34.461168
4358 12:17:34.471206 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e3c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps
4359 12:17:34.474055 CH0 RK1: MR19=808, MR18=6E3C
4360 12:17:34.481424 CH0_RK1: MR19=0x808, MR18=0x6E3C, DQSOSC=389, MR23=63, INC=173, DEC=115
4361 12:17:34.481590 [RxdqsGatingPostProcess] freq 600
4362 12:17:34.487259 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4363 12:17:34.490966 Pre-setting of DQS Precalculation
4364 12:17:34.494288 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4365 12:17:34.497561 ==
4366 12:17:34.500778 Dram Type= 6, Freq= 0, CH_1, rank 0
4367 12:17:34.504310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 12:17:34.504455 ==
4369 12:17:34.507463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 12:17:34.513747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4371 12:17:34.517866 [CA 0] Center 35 (5~66) winsize 62
4372 12:17:34.521191 [CA 1] Center 36 (6~66) winsize 61
4373 12:17:34.524405 [CA 2] Center 34 (4~65) winsize 62
4374 12:17:34.527478 [CA 3] Center 34 (4~65) winsize 62
4375 12:17:34.530917 [CA 4] Center 34 (4~65) winsize 62
4376 12:17:34.534056 [CA 5] Center 33 (3~64) winsize 62
4377 12:17:34.534168
4378 12:17:34.537614 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4379 12:17:34.537717
4380 12:17:34.540849 [CATrainingPosCal] consider 1 rank data
4381 12:17:34.544339 u2DelayCellTimex100 = 270/100 ps
4382 12:17:34.547606 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 12:17:34.554137 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4384 12:17:34.557510 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 12:17:34.560841 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 12:17:34.564320 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 12:17:34.567249 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 12:17:34.567396
4389 12:17:34.570445 CA PerBit enable=1, Macro0, CA PI delay=33
4390 12:17:34.570556
4391 12:17:34.574019 [CBTSetCACLKResult] CA Dly = 33
4392 12:17:34.574158 CS Dly: 4 (0~35)
4393 12:17:34.577313 ==
4394 12:17:34.580501 Dram Type= 6, Freq= 0, CH_1, rank 1
4395 12:17:34.584383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 12:17:34.584511 ==
4397 12:17:34.587677 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 12:17:34.594696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4399 12:17:34.597664 [CA 0] Center 36 (6~66) winsize 61
4400 12:17:34.601236 [CA 1] Center 36 (6~67) winsize 62
4401 12:17:34.604920 [CA 2] Center 34 (4~65) winsize 62
4402 12:17:34.607512 [CA 3] Center 34 (3~65) winsize 63
4403 12:17:34.611213 [CA 4] Center 34 (4~65) winsize 62
4404 12:17:34.614864 [CA 5] Center 33 (3~64) winsize 62
4405 12:17:34.614946
4406 12:17:34.617520 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4407 12:17:34.617621
4408 12:17:34.621008 [CATrainingPosCal] consider 2 rank data
4409 12:17:34.624355 u2DelayCellTimex100 = 270/100 ps
4410 12:17:34.628168 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4411 12:17:34.634387 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4412 12:17:34.637663 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 12:17:34.640742 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 12:17:34.644327 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 12:17:34.647315 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 12:17:34.647437
4417 12:17:34.651215 CA PerBit enable=1, Macro0, CA PI delay=33
4418 12:17:34.651305
4419 12:17:34.654233 [CBTSetCACLKResult] CA Dly = 33
4420 12:17:34.654318 CS Dly: 4 (0~36)
4421 12:17:34.657610
4422 12:17:34.660981 ----->DramcWriteLeveling(PI) begin...
4423 12:17:34.661073 ==
4424 12:17:34.664128 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 12:17:34.667423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 12:17:34.667519 ==
4427 12:17:34.670716 Write leveling (Byte 0): 28 => 28
4428 12:17:34.673809 Write leveling (Byte 1): 31 => 31
4429 12:17:34.677026 DramcWriteLeveling(PI) end<-----
4430 12:17:34.677114
4431 12:17:34.677178 ==
4432 12:17:34.680384 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 12:17:34.684337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 12:17:34.684430 ==
4435 12:17:34.687743 [Gating] SW mode calibration
4436 12:17:34.693716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4437 12:17:34.700768 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4438 12:17:34.703935 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 12:17:34.706902 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 12:17:34.713777 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 12:17:34.717077 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (1 0) (1 0)
4442 12:17:34.720435 0 9 16 | B1->B0 | 2323 2828 | 0 0 | (1 0) (1 1)
4443 12:17:34.727122 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 12:17:34.730370 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 12:17:34.733841 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 12:17:34.740242 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 12:17:34.744019 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 12:17:34.747115 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 12:17:34.750379 0 10 12 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
4450 12:17:34.756924 0 10 16 | B1->B0 | 4343 4545 | 0 0 | (1 1) (0 0)
4451 12:17:34.760530 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 12:17:34.763718 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 12:17:34.770631 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 12:17:34.773808 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 12:17:34.776846 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 12:17:34.783680 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 12:17:34.786830 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4458 12:17:34.790394 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4459 12:17:34.796897 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:17:34.800165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 12:17:34.803623 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 12:17:34.809934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 12:17:34.813272 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 12:17:34.816976 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 12:17:34.823466 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 12:17:34.826696 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 12:17:34.829988 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 12:17:34.837192 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 12:17:34.839955 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 12:17:34.843063 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 12:17:34.849613 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 12:17:34.852959 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 12:17:34.856535 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4474 12:17:34.859640 Total UI for P1: 0, mck2ui 16
4475 12:17:34.862829 best dqsien dly found for B0: ( 0, 13, 10)
4476 12:17:34.869325 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 12:17:34.869457 Total UI for P1: 0, mck2ui 16
4478 12:17:34.876008 best dqsien dly found for B1: ( 0, 13, 12)
4479 12:17:34.879693 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4480 12:17:34.882797 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4481 12:17:34.882913
4482 12:17:34.886107 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4483 12:17:34.889362 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4484 12:17:34.892753 [Gating] SW calibration Done
4485 12:17:34.892852 ==
4486 12:17:34.896260 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 12:17:34.899362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 12:17:34.899499 ==
4489 12:17:34.902853 RX Vref Scan: 0
4490 12:17:34.902945
4491 12:17:34.903031 RX Vref 0 -> 0, step: 1
4492 12:17:34.905968
4493 12:17:34.906055 RX Delay -230 -> 252, step: 16
4494 12:17:34.912630 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4495 12:17:34.916009 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4496 12:17:34.919258 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4497 12:17:34.923137 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4498 12:17:34.925692 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4499 12:17:34.932423 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4500 12:17:34.935697 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4501 12:17:34.939289 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4502 12:17:34.942618 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4503 12:17:34.948706 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4504 12:17:34.952216 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4505 12:17:34.955928 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4506 12:17:34.958738 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4507 12:17:34.965332 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4508 12:17:34.969100 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4509 12:17:34.972144 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4510 12:17:34.972273 ==
4511 12:17:34.975636 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 12:17:34.978794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 12:17:34.982162 ==
4514 12:17:34.982350 DQS Delay:
4515 12:17:34.982482 DQS0 = 0, DQS1 = 0
4516 12:17:34.985399 DQM Delay:
4517 12:17:34.985576 DQM0 = 38, DQM1 = 28
4518 12:17:34.989029 DQ Delay:
4519 12:17:34.989199 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4520 12:17:34.992509 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4521 12:17:34.995749 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4522 12:17:34.999056 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4523 12:17:34.999176
4524 12:17:35.002080
4525 12:17:35.002181 ==
4526 12:17:35.005293 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 12:17:35.009193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 12:17:35.009310 ==
4529 12:17:35.009403
4530 12:17:35.009486
4531 12:17:35.012107 TX Vref Scan disable
4532 12:17:35.012197 == TX Byte 0 ==
4533 12:17:35.018684 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 12:17:35.022370 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 12:17:35.022508 == TX Byte 1 ==
4536 12:17:35.028370 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4537 12:17:35.031703 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4538 12:17:35.031868 ==
4539 12:17:35.034980 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 12:17:35.038715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 12:17:35.038843 ==
4542 12:17:35.038939
4543 12:17:35.039032
4544 12:17:35.041863 TX Vref Scan disable
4545 12:17:35.045203 == TX Byte 0 ==
4546 12:17:35.048495 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4547 12:17:35.051756 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4548 12:17:35.054960 == TX Byte 1 ==
4549 12:17:35.058615 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4550 12:17:35.061764 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4551 12:17:35.061873
4552 12:17:35.065076 [DATLAT]
4553 12:17:35.065168 Freq=600, CH1 RK0
4554 12:17:35.065241
4555 12:17:35.068269 DATLAT Default: 0x9
4556 12:17:35.068362 0, 0xFFFF, sum = 0
4557 12:17:35.072039 1, 0xFFFF, sum = 0
4558 12:17:35.072129 2, 0xFFFF, sum = 0
4559 12:17:35.074924 3, 0xFFFF, sum = 0
4560 12:17:35.075026 4, 0xFFFF, sum = 0
4561 12:17:35.078836 5, 0xFFFF, sum = 0
4562 12:17:35.078944 6, 0xFFFF, sum = 0
4563 12:17:35.081561 7, 0xFFFF, sum = 0
4564 12:17:35.081683 8, 0x0, sum = 1
4565 12:17:35.085291 9, 0x0, sum = 2
4566 12:17:35.085410 10, 0x0, sum = 3
4567 12:17:35.088274 11, 0x0, sum = 4
4568 12:17:35.088358 best_step = 9
4569 12:17:35.088460
4570 12:17:35.088517 ==
4571 12:17:35.091732 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 12:17:35.098276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 12:17:35.098442 ==
4574 12:17:35.098514 RX Vref Scan: 1
4575 12:17:35.098617
4576 12:17:35.101443 RX Vref 0 -> 0, step: 1
4577 12:17:35.101535
4578 12:17:35.104878 RX Delay -195 -> 252, step: 8
4579 12:17:35.104988
4580 12:17:35.108411 Set Vref, RX VrefLevel [Byte0]: 57
4581 12:17:35.111382 [Byte1]: 48
4582 12:17:35.111524
4583 12:17:35.114781 Final RX Vref Byte 0 = 57 to rank0
4584 12:17:35.118053 Final RX Vref Byte 1 = 48 to rank0
4585 12:17:35.121501 Final RX Vref Byte 0 = 57 to rank1
4586 12:17:35.124720 Final RX Vref Byte 1 = 48 to rank1==
4587 12:17:35.128339 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 12:17:35.131661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 12:17:35.131755 ==
4590 12:17:35.134611 DQS Delay:
4591 12:17:35.134738 DQS0 = 0, DQS1 = 0
4592 12:17:35.134833 DQM Delay:
4593 12:17:35.138436 DQM0 = 38, DQM1 = 29
4594 12:17:35.138536 DQ Delay:
4595 12:17:35.141581 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4596 12:17:35.144525 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4597 12:17:35.148276 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4598 12:17:35.151357 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4599 12:17:35.151517
4600 12:17:35.151671
4601 12:17:35.161534 [DQSOSCAuto] RK0, (LSB)MR18= 0x222f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4602 12:17:35.164941 CH1 RK0: MR19=808, MR18=222F
4603 12:17:35.167820 CH1_RK0: MR19=0x808, MR18=0x222F, DQSOSC=400, MR23=63, INC=163, DEC=109
4604 12:17:35.167910
4605 12:17:35.170985 ----->DramcWriteLeveling(PI) begin...
4606 12:17:35.174655 ==
4607 12:17:35.177511 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 12:17:35.180847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 12:17:35.180995 ==
4610 12:17:35.184437 Write leveling (Byte 0): 29 => 29
4611 12:17:35.187685 Write leveling (Byte 1): 29 => 29
4612 12:17:35.190957 DramcWriteLeveling(PI) end<-----
4613 12:17:35.191079
4614 12:17:35.191148 ==
4615 12:17:35.194383 Dram Type= 6, Freq= 0, CH_1, rank 1
4616 12:17:35.197365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 12:17:35.197494 ==
4618 12:17:35.200709 [Gating] SW mode calibration
4619 12:17:35.207817 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4620 12:17:35.214015 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4621 12:17:35.217337 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 12:17:35.220852 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 12:17:35.227260 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 12:17:35.230975 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)
4625 12:17:35.233938 0 9 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4626 12:17:35.240520 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 12:17:35.244360 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 12:17:35.247176 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 12:17:35.250965 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 12:17:35.257298 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 12:17:35.260546 0 10 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
4632 12:17:35.263627 0 10 12 | B1->B0 | 2f2f 4242 | 0 0 | (0 0) (0 0)
4633 12:17:35.270494 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4634 12:17:35.273599 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 12:17:35.277225 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 12:17:35.283771 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 12:17:35.287289 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 12:17:35.290406 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 12:17:35.297036 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 12:17:35.300018 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4641 12:17:35.303656 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:17:35.310621 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:17:35.313356 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 12:17:35.316991 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 12:17:35.323393 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 12:17:35.326582 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 12:17:35.330000 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 12:17:35.337027 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 12:17:35.340006 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 12:17:35.343303 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 12:17:35.349578 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 12:17:35.352951 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 12:17:35.356759 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 12:17:35.363200 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 12:17:35.366562 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 12:17:35.369704 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4657 12:17:35.373008 Total UI for P1: 0, mck2ui 16
4658 12:17:35.376358 best dqsien dly found for B0: ( 0, 13, 10)
4659 12:17:35.383184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 12:17:35.383296 Total UI for P1: 0, mck2ui 16
4661 12:17:35.389510 best dqsien dly found for B1: ( 0, 13, 12)
4662 12:17:35.392755 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4663 12:17:35.395997 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4664 12:17:35.396087
4665 12:17:35.399350 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4666 12:17:35.403001 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4667 12:17:35.406019 [Gating] SW calibration Done
4668 12:17:35.406104 ==
4669 12:17:35.409234 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 12:17:35.412956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 12:17:35.413047 ==
4672 12:17:35.416599 RX Vref Scan: 0
4673 12:17:35.416685
4674 12:17:35.416772 RX Vref 0 -> 0, step: 1
4675 12:17:35.420018
4676 12:17:35.420104 RX Delay -230 -> 252, step: 16
4677 12:17:35.426518 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4678 12:17:35.429358 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4679 12:17:35.433087 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4680 12:17:35.436147 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4681 12:17:35.439306 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4682 12:17:35.446343 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4683 12:17:35.449398 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4684 12:17:35.452787 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4685 12:17:35.455953 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4686 12:17:35.462509 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4687 12:17:35.465944 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4688 12:17:35.469115 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4689 12:17:35.472453 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4690 12:17:35.479584 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4691 12:17:35.482380 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4692 12:17:35.485822 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4693 12:17:35.485910 ==
4694 12:17:35.488985 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 12:17:35.492697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 12:17:35.492784 ==
4697 12:17:35.495932 DQS Delay:
4698 12:17:35.496020 DQS0 = 0, DQS1 = 0
4699 12:17:35.499162 DQM Delay:
4700 12:17:35.499252 DQM0 = 35, DQM1 = 29
4701 12:17:35.499351 DQ Delay:
4702 12:17:35.502304 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4703 12:17:35.505615 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4704 12:17:35.509151 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4705 12:17:35.512371 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4706 12:17:35.512458
4707 12:17:35.512544
4708 12:17:35.515623 ==
4709 12:17:35.518907 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 12:17:35.522214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 12:17:35.522302 ==
4712 12:17:35.522389
4713 12:17:35.522470
4714 12:17:35.525441 TX Vref Scan disable
4715 12:17:35.525530 == TX Byte 0 ==
4716 12:17:35.532096 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4717 12:17:35.535597 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4718 12:17:35.535685 == TX Byte 1 ==
4719 12:17:35.542460 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4720 12:17:35.545772 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4721 12:17:35.545860 ==
4722 12:17:35.548784 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 12:17:35.552411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 12:17:35.552498 ==
4725 12:17:35.552585
4726 12:17:35.552665
4727 12:17:35.555357 TX Vref Scan disable
4728 12:17:35.558588 == TX Byte 0 ==
4729 12:17:35.561982 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4730 12:17:35.565355 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4731 12:17:35.568897 == TX Byte 1 ==
4732 12:17:35.572679 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4733 12:17:35.575264 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4734 12:17:35.575353
4735 12:17:35.579002 [DATLAT]
4736 12:17:35.579088 Freq=600, CH1 RK1
4737 12:17:35.579190
4738 12:17:35.581935 DATLAT Default: 0x9
4739 12:17:35.582021 0, 0xFFFF, sum = 0
4740 12:17:35.585278 1, 0xFFFF, sum = 0
4741 12:17:35.585366 2, 0xFFFF, sum = 0
4742 12:17:35.588721 3, 0xFFFF, sum = 0
4743 12:17:35.588808 4, 0xFFFF, sum = 0
4744 12:17:35.592103 5, 0xFFFF, sum = 0
4745 12:17:35.592192 6, 0xFFFF, sum = 0
4746 12:17:35.595008 7, 0xFFFF, sum = 0
4747 12:17:35.595094 8, 0x0, sum = 1
4748 12:17:35.598463 9, 0x0, sum = 2
4749 12:17:35.598551 10, 0x0, sum = 3
4750 12:17:35.601801 11, 0x0, sum = 4
4751 12:17:35.601888 best_step = 9
4752 12:17:35.601974
4753 12:17:35.602055 ==
4754 12:17:35.605310 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 12:17:35.611704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 12:17:35.611795 ==
4757 12:17:35.611881 RX Vref Scan: 0
4758 12:17:35.611967
4759 12:17:35.614937 RX Vref 0 -> 0, step: 1
4760 12:17:35.615023
4761 12:17:35.618190 RX Delay -195 -> 252, step: 8
4762 12:17:35.622096 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4763 12:17:35.625296 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4764 12:17:35.632023 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4765 12:17:35.634884 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4766 12:17:35.638524 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4767 12:17:35.641702 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4768 12:17:35.648797 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4769 12:17:35.651777 iDelay=205, Bit 7, Center 28 (-131 ~ 188) 320
4770 12:17:35.655017 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4771 12:17:35.658196 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4772 12:17:35.665070 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4773 12:17:35.668454 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4774 12:17:35.671832 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4775 12:17:35.675533 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4776 12:17:35.681364 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4777 12:17:35.684586 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4778 12:17:35.684669 ==
4779 12:17:35.688481 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 12:17:35.691338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 12:17:35.691473 ==
4782 12:17:35.694694 DQS Delay:
4783 12:17:35.694777 DQS0 = 0, DQS1 = 0
4784 12:17:35.694842 DQM Delay:
4785 12:17:35.698148 DQM0 = 34, DQM1 = 30
4786 12:17:35.698231 DQ Delay:
4787 12:17:35.701501 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4788 12:17:35.704553 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =28
4789 12:17:35.707634 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =24
4790 12:17:35.711075 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4791 12:17:35.711158
4792 12:17:35.711222
4793 12:17:35.721336 [DQSOSCAuto] RK1, (LSB)MR18= 0x3555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4794 12:17:35.721455 CH1 RK1: MR19=808, MR18=3555
4795 12:17:35.727773 CH1_RK1: MR19=0x808, MR18=0x3555, DQSOSC=393, MR23=63, INC=169, DEC=113
4796 12:17:35.731084 [RxdqsGatingPostProcess] freq 600
4797 12:17:35.737536 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4798 12:17:35.740852 Pre-setting of DQS Precalculation
4799 12:17:35.744295 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4800 12:17:35.751191 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4801 12:17:35.761215 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4802 12:17:35.761320
4803 12:17:35.761407
4804 12:17:35.764336 [Calibration Summary] 1200 Mbps
4805 12:17:35.764423 CH 0, Rank 0
4806 12:17:35.767427 SW Impedance : PASS
4807 12:17:35.767515 DUTY Scan : NO K
4808 12:17:35.770630 ZQ Calibration : PASS
4809 12:17:35.774208 Jitter Meter : NO K
4810 12:17:35.774295 CBT Training : PASS
4811 12:17:35.777392 Write leveling : PASS
4812 12:17:35.777484 RX DQS gating : PASS
4813 12:17:35.780563 RX DQ/DQS(RDDQC) : PASS
4814 12:17:35.783961 TX DQ/DQS : PASS
4815 12:17:35.784047 RX DATLAT : PASS
4816 12:17:35.787291 RX DQ/DQS(Engine): PASS
4817 12:17:35.791025 TX OE : NO K
4818 12:17:35.791112 All Pass.
4819 12:17:35.791199
4820 12:17:35.791322 CH 0, Rank 1
4821 12:17:35.794300 SW Impedance : PASS
4822 12:17:35.797055 DUTY Scan : NO K
4823 12:17:35.797140 ZQ Calibration : PASS
4824 12:17:35.800433 Jitter Meter : NO K
4825 12:17:35.803809 CBT Training : PASS
4826 12:17:35.803896 Write leveling : PASS
4827 12:17:35.807359 RX DQS gating : PASS
4828 12:17:35.810514 RX DQ/DQS(RDDQC) : PASS
4829 12:17:35.810597 TX DQ/DQS : PASS
4830 12:17:35.813677 RX DATLAT : PASS
4831 12:17:35.816851 RX DQ/DQS(Engine): PASS
4832 12:17:35.816936 TX OE : NO K
4833 12:17:35.820397 All Pass.
4834 12:17:35.820479
4835 12:17:35.820544 CH 1, Rank 0
4836 12:17:35.823638 SW Impedance : PASS
4837 12:17:35.823721 DUTY Scan : NO K
4838 12:17:35.826882 ZQ Calibration : PASS
4839 12:17:35.830022 Jitter Meter : NO K
4840 12:17:35.830109 CBT Training : PASS
4841 12:17:35.833644 Write leveling : PASS
4842 12:17:35.837255 RX DQS gating : PASS
4843 12:17:35.837339 RX DQ/DQS(RDDQC) : PASS
4844 12:17:35.840538 TX DQ/DQS : PASS
4845 12:17:35.840620 RX DATLAT : PASS
4846 12:17:35.843617 RX DQ/DQS(Engine): PASS
4847 12:17:35.846834 TX OE : NO K
4848 12:17:35.846917 All Pass.
4849 12:17:35.846981
4850 12:17:35.847042 CH 1, Rank 1
4851 12:17:35.849947 SW Impedance : PASS
4852 12:17:35.853214 DUTY Scan : NO K
4853 12:17:35.853296 ZQ Calibration : PASS
4854 12:17:35.857033 Jitter Meter : NO K
4855 12:17:35.860401 CBT Training : PASS
4856 12:17:35.860484 Write leveling : PASS
4857 12:17:35.863171 RX DQS gating : PASS
4858 12:17:35.866689 RX DQ/DQS(RDDQC) : PASS
4859 12:17:35.866774 TX DQ/DQS : PASS
4860 12:17:35.870068 RX DATLAT : PASS
4861 12:17:35.873340 RX DQ/DQS(Engine): PASS
4862 12:17:35.873424 TX OE : NO K
4863 12:17:35.876647 All Pass.
4864 12:17:35.876734
4865 12:17:35.876820 DramC Write-DBI off
4866 12:17:35.879788 PER_BANK_REFRESH: Hybrid Mode
4867 12:17:35.879874 TX_TRACKING: ON
4868 12:17:35.889786 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4869 12:17:35.893109 [FAST_K] Save calibration result to emmc
4870 12:17:35.896297 dramc_set_vcore_voltage set vcore to 662500
4871 12:17:35.899583 Read voltage for 933, 3
4872 12:17:35.899671 Vio18 = 0
4873 12:17:35.903191 Vcore = 662500
4874 12:17:35.903278 Vdram = 0
4875 12:17:35.903379 Vddq = 0
4876 12:17:35.906315 Vmddr = 0
4877 12:17:35.910103 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4878 12:17:35.916407 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4879 12:17:35.916500 MEM_TYPE=3, freq_sel=17
4880 12:17:35.919616 sv_algorithm_assistance_LP4_1600
4881 12:17:35.926289 ============ PULL DRAM RESETB DOWN ============
4882 12:17:35.929548 ========== PULL DRAM RESETB DOWN end =========
4883 12:17:35.932758 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4884 12:17:35.936330 ===================================
4885 12:17:35.939195 LPDDR4 DRAM CONFIGURATION
4886 12:17:35.942916 ===================================
4887 12:17:35.945733 EX_ROW_EN[0] = 0x0
4888 12:17:35.945820 EX_ROW_EN[1] = 0x0
4889 12:17:35.949535 LP4Y_EN = 0x0
4890 12:17:35.949622 WORK_FSP = 0x0
4891 12:17:35.952754 WL = 0x3
4892 12:17:35.952840 RL = 0x3
4893 12:17:35.956242 BL = 0x2
4894 12:17:35.956329 RPST = 0x0
4895 12:17:35.959146 RD_PRE = 0x0
4896 12:17:35.959232 WR_PRE = 0x1
4897 12:17:35.963076 WR_PST = 0x0
4898 12:17:35.963187 DBI_WR = 0x0
4899 12:17:35.966032 DBI_RD = 0x0
4900 12:17:35.966139 OTF = 0x1
4901 12:17:35.969540 ===================================
4902 12:17:35.972953 ===================================
4903 12:17:35.976238 ANA top config
4904 12:17:35.979721 ===================================
4905 12:17:35.979805 DLL_ASYNC_EN = 0
4906 12:17:35.982466 ALL_SLAVE_EN = 1
4907 12:17:35.986005 NEW_RANK_MODE = 1
4908 12:17:35.989387 DLL_IDLE_MODE = 1
4909 12:17:35.992484 LP45_APHY_COMB_EN = 1
4910 12:17:35.992569 TX_ODT_DIS = 1
4911 12:17:35.996023 NEW_8X_MODE = 1
4912 12:17:35.999224 ===================================
4913 12:17:36.002521 ===================================
4914 12:17:36.006262 data_rate = 1866
4915 12:17:36.009855 CKR = 1
4916 12:17:36.012997 DQ_P2S_RATIO = 8
4917 12:17:36.016016 ===================================
4918 12:17:36.016100 CA_P2S_RATIO = 8
4919 12:17:36.019432 DQ_CA_OPEN = 0
4920 12:17:36.022650 DQ_SEMI_OPEN = 0
4921 12:17:36.026095 CA_SEMI_OPEN = 0
4922 12:17:36.029181 CA_FULL_RATE = 0
4923 12:17:36.033304 DQ_CKDIV4_EN = 1
4924 12:17:36.033391 CA_CKDIV4_EN = 1
4925 12:17:36.035996 CA_PREDIV_EN = 0
4926 12:17:36.039688 PH8_DLY = 0
4927 12:17:36.042463 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4928 12:17:36.045945 DQ_AAMCK_DIV = 4
4929 12:17:36.049308 CA_AAMCK_DIV = 4
4930 12:17:36.049395 CA_ADMCK_DIV = 4
4931 12:17:36.052644 DQ_TRACK_CA_EN = 0
4932 12:17:36.055823 CA_PICK = 933
4933 12:17:36.058996 CA_MCKIO = 933
4934 12:17:36.062479 MCKIO_SEMI = 0
4935 12:17:36.065750 PLL_FREQ = 3732
4936 12:17:36.069106 DQ_UI_PI_RATIO = 32
4937 12:17:36.069194 CA_UI_PI_RATIO = 0
4938 12:17:36.072462 ===================================
4939 12:17:36.075782 ===================================
4940 12:17:36.079167 memory_type:LPDDR4
4941 12:17:36.082458 GP_NUM : 10
4942 12:17:36.082542 SRAM_EN : 1
4943 12:17:36.085766 MD32_EN : 0
4944 12:17:36.088994 ===================================
4945 12:17:36.092128 [ANA_INIT] >>>>>>>>>>>>>>
4946 12:17:36.095526 <<<<<< [CONFIGURE PHASE]: ANA_TX
4947 12:17:36.098667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4948 12:17:36.102136 ===================================
4949 12:17:36.102236 data_rate = 1866,PCW = 0X8f00
4950 12:17:36.105606 ===================================
4951 12:17:36.108962 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4952 12:17:36.115419 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 12:17:36.122700 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 12:17:36.125413 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4955 12:17:36.129059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4956 12:17:36.131804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4957 12:17:36.135196 [ANA_INIT] flow start
4958 12:17:36.138591 [ANA_INIT] PLL >>>>>>>>
4959 12:17:36.138674 [ANA_INIT] PLL <<<<<<<<
4960 12:17:36.141973 [ANA_INIT] MIDPI >>>>>>>>
4961 12:17:36.145107 [ANA_INIT] MIDPI <<<<<<<<
4962 12:17:36.145190 [ANA_INIT] DLL >>>>>>>>
4963 12:17:36.148590 [ANA_INIT] flow end
4964 12:17:36.152166 ============ LP4 DIFF to SE enter ============
4965 12:17:36.154884 ============ LP4 DIFF to SE exit ============
4966 12:17:36.158528 [ANA_INIT] <<<<<<<<<<<<<
4967 12:17:36.161526 [Flow] Enable top DCM control >>>>>
4968 12:17:36.165355 [Flow] Enable top DCM control <<<<<
4969 12:17:36.168159 Enable DLL master slave shuffle
4970 12:17:36.174835 ==============================================================
4971 12:17:36.174925 Gating Mode config
4972 12:17:36.181786 ==============================================================
4973 12:17:36.181877 Config description:
4974 12:17:36.191533 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4975 12:17:36.198577 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4976 12:17:36.204740 SELPH_MODE 0: By rank 1: By Phase
4977 12:17:36.208228 ==============================================================
4978 12:17:36.211783 GAT_TRACK_EN = 1
4979 12:17:36.214922 RX_GATING_MODE = 2
4980 12:17:36.218369 RX_GATING_TRACK_MODE = 2
4981 12:17:36.221649 SELPH_MODE = 1
4982 12:17:36.224744 PICG_EARLY_EN = 1
4983 12:17:36.228083 VALID_LAT_VALUE = 1
4984 12:17:36.235009 ==============================================================
4985 12:17:36.238161 Enter into Gating configuration >>>>
4986 12:17:36.241122 Exit from Gating configuration <<<<
4987 12:17:36.244391 Enter into DVFS_PRE_config >>>>>
4988 12:17:36.254248 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4989 12:17:36.257745 Exit from DVFS_PRE_config <<<<<
4990 12:17:36.261169 Enter into PICG configuration >>>>
4991 12:17:36.264865 Exit from PICG configuration <<<<
4992 12:17:36.267651 [RX_INPUT] configuration >>>>>
4993 12:17:36.267738 [RX_INPUT] configuration <<<<<
4994 12:17:36.274234 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4995 12:17:36.280908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4996 12:17:36.284346 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4997 12:17:36.291084 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4998 12:17:36.297521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4999 12:17:36.304166 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5000 12:17:36.307584 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5001 12:17:36.310816 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5002 12:17:36.317744 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5003 12:17:36.320487 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5004 12:17:36.324085 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5005 12:17:36.330819 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5006 12:17:36.334012 ===================================
5007 12:17:36.334105 LPDDR4 DRAM CONFIGURATION
5008 12:17:36.337260 ===================================
5009 12:17:36.340998 EX_ROW_EN[0] = 0x0
5010 12:17:36.341085 EX_ROW_EN[1] = 0x0
5011 12:17:36.343802 LP4Y_EN = 0x0
5012 12:17:36.346986 WORK_FSP = 0x0
5013 12:17:36.347070 WL = 0x3
5014 12:17:36.350765 RL = 0x3
5015 12:17:36.350874 BL = 0x2
5016 12:17:36.354103 RPST = 0x0
5017 12:17:36.354187 RD_PRE = 0x0
5018 12:17:36.357329 WR_PRE = 0x1
5019 12:17:36.357412 WR_PST = 0x0
5020 12:17:36.360388 DBI_WR = 0x0
5021 12:17:36.360490 DBI_RD = 0x0
5022 12:17:36.363669 OTF = 0x1
5023 12:17:36.367178 ===================================
5024 12:17:36.370435 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5025 12:17:36.373617 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5026 12:17:36.379990 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 12:17:36.383724 ===================================
5028 12:17:36.383816 LPDDR4 DRAM CONFIGURATION
5029 12:17:36.386760 ===================================
5030 12:17:36.390195 EX_ROW_EN[0] = 0x10
5031 12:17:36.390284 EX_ROW_EN[1] = 0x0
5032 12:17:36.393462 LP4Y_EN = 0x0
5033 12:17:36.393547 WORK_FSP = 0x0
5034 12:17:36.397236 WL = 0x3
5035 12:17:36.400271 RL = 0x3
5036 12:17:36.400359 BL = 0x2
5037 12:17:36.403728 RPST = 0x0
5038 12:17:36.403812 RD_PRE = 0x0
5039 12:17:36.407116 WR_PRE = 0x1
5040 12:17:36.407200 WR_PST = 0x0
5041 12:17:36.410182 DBI_WR = 0x0
5042 12:17:36.410316 DBI_RD = 0x0
5043 12:17:36.413496 OTF = 0x1
5044 12:17:36.416785 ===================================
5045 12:17:36.423272 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5046 12:17:36.426573 nWR fixed to 30
5047 12:17:36.426665 [ModeRegInit_LP4] CH0 RK0
5048 12:17:36.430007 [ModeRegInit_LP4] CH0 RK1
5049 12:17:36.433604 [ModeRegInit_LP4] CH1 RK0
5050 12:17:36.433693 [ModeRegInit_LP4] CH1 RK1
5051 12:17:36.436951 match AC timing 9
5052 12:17:36.440113 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5053 12:17:36.443322 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5054 12:17:36.449798 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5055 12:17:36.453085 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5056 12:17:36.459784 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5057 12:17:36.459872 ==
5058 12:17:36.462995 Dram Type= 6, Freq= 0, CH_0, rank 0
5059 12:17:36.466339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5060 12:17:36.466427 ==
5061 12:17:36.473306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5062 12:17:36.479668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5063 12:17:36.482912 [CA 0] Center 38 (8~69) winsize 62
5064 12:17:36.486234 [CA 1] Center 38 (7~69) winsize 63
5065 12:17:36.489396 [CA 2] Center 35 (6~65) winsize 60
5066 12:17:36.492922 [CA 3] Center 35 (5~65) winsize 61
5067 12:17:36.496276 [CA 4] Center 34 (4~65) winsize 62
5068 12:17:36.496400 [CA 5] Center 33 (3~64) winsize 62
5069 12:17:36.499309
5070 12:17:36.503035 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5071 12:17:36.503122
5072 12:17:36.506185 [CATrainingPosCal] consider 1 rank data
5073 12:17:36.509250 u2DelayCellTimex100 = 270/100 ps
5074 12:17:36.512559 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5075 12:17:36.516194 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5076 12:17:36.519175 CA2 delay=35 (6~65),Diff = 2 PI (12 cell)
5077 12:17:36.522427 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5078 12:17:36.525960 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5079 12:17:36.529193 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5080 12:17:36.529287
5081 12:17:36.535732 CA PerBit enable=1, Macro0, CA PI delay=33
5082 12:17:36.535820
5083 12:17:36.535906 [CBTSetCACLKResult] CA Dly = 33
5084 12:17:36.539310 CS Dly: 7 (0~38)
5085 12:17:36.539405 ==
5086 12:17:36.542304 Dram Type= 6, Freq= 0, CH_0, rank 1
5087 12:17:36.545876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 12:17:36.545964 ==
5089 12:17:36.552444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 12:17:36.559404 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5091 12:17:36.562654 [CA 0] Center 38 (8~69) winsize 62
5092 12:17:36.565736 [CA 1] Center 38 (8~68) winsize 61
5093 12:17:36.568982 [CA 2] Center 35 (5~66) winsize 62
5094 12:17:36.572581 [CA 3] Center 35 (5~65) winsize 61
5095 12:17:36.575873 [CA 4] Center 34 (4~65) winsize 62
5096 12:17:36.579145 [CA 5] Center 34 (4~64) winsize 61
5097 12:17:36.579231
5098 12:17:36.582217 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5099 12:17:36.582333
5100 12:17:36.585414 [CATrainingPosCal] consider 2 rank data
5101 12:17:36.588856 u2DelayCellTimex100 = 270/100 ps
5102 12:17:36.592177 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5103 12:17:36.595594 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5104 12:17:36.598747 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5105 12:17:36.602105 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5106 12:17:36.605697 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5107 12:17:36.608777 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5108 12:17:36.611901
5109 12:17:36.615495 CA PerBit enable=1, Macro0, CA PI delay=34
5110 12:17:36.615581
5111 12:17:36.618522 [CBTSetCACLKResult] CA Dly = 34
5112 12:17:36.618610 CS Dly: 7 (0~38)
5113 12:17:36.618696
5114 12:17:36.621687 ----->DramcWriteLeveling(PI) begin...
5115 12:17:36.621774 ==
5116 12:17:36.625347 Dram Type= 6, Freq= 0, CH_0, rank 0
5117 12:17:36.631604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5118 12:17:36.631697 ==
5119 12:17:36.635273 Write leveling (Byte 0): 33 => 33
5120 12:17:36.635358 Write leveling (Byte 1): 33 => 33
5121 12:17:36.638495 DramcWriteLeveling(PI) end<-----
5122 12:17:36.638578
5123 12:17:36.638642 ==
5124 12:17:36.641479 Dram Type= 6, Freq= 0, CH_0, rank 0
5125 12:17:36.648323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 12:17:36.648411 ==
5127 12:17:36.652044 [Gating] SW mode calibration
5128 12:17:36.658528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5129 12:17:36.661355 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5130 12:17:36.668193 0 14 0 | B1->B0 | 2323 2f2e | 0 1 | (0 0) (0 0)
5131 12:17:36.671237 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 12:17:36.674533 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 12:17:36.681364 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 12:17:36.684705 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 12:17:36.687731 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 12:17:36.694700 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 12:17:36.697722 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5138 12:17:36.701011 0 15 0 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (1 1)
5139 12:17:36.707884 0 15 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5140 12:17:36.711884 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 12:17:36.714756 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 12:17:36.718037 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 12:17:36.724590 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 12:17:36.727677 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 12:17:36.731141 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5146 12:17:36.737955 1 0 0 | B1->B0 | 2828 3a3a | 0 0 | (0 0) (1 1)
5147 12:17:36.740988 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5148 12:17:36.744533 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 12:17:36.751568 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 12:17:36.754259 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 12:17:36.757645 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 12:17:36.764644 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 12:17:36.767382 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 12:17:36.770950 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5155 12:17:36.777789 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5156 12:17:36.780604 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:17:36.784235 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 12:17:36.790900 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 12:17:36.794546 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 12:17:36.797275 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 12:17:36.803939 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 12:17:36.807436 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 12:17:36.810586 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 12:17:36.817338 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 12:17:36.820358 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 12:17:36.823814 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 12:17:36.830349 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 12:17:36.833685 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 12:17:36.837168 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 12:17:36.843694 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5171 12:17:36.843782 Total UI for P1: 0, mck2ui 16
5172 12:17:36.850818 best dqsien dly found for B0: ( 1, 2, 30)
5173 12:17:36.853805 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5174 12:17:36.856935 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 12:17:36.860450 Total UI for P1: 0, mck2ui 16
5176 12:17:36.863936 best dqsien dly found for B1: ( 1, 3, 2)
5177 12:17:36.866704 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5178 12:17:36.870288 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5179 12:17:36.870381
5180 12:17:36.877014 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5181 12:17:36.879848 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5182 12:17:36.879935 [Gating] SW calibration Done
5183 12:17:36.883423 ==
5184 12:17:36.887131 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 12:17:36.890294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 12:17:36.890379 ==
5187 12:17:36.890466 RX Vref Scan: 0
5188 12:17:36.890547
5189 12:17:36.893531 RX Vref 0 -> 0, step: 1
5190 12:17:36.893616
5191 12:17:36.896770 RX Delay -80 -> 252, step: 8
5192 12:17:36.900064 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5193 12:17:36.903293 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5194 12:17:36.907176 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5195 12:17:36.913250 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5196 12:17:36.916365 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5197 12:17:36.919689 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5198 12:17:36.923267 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5199 12:17:36.926427 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5200 12:17:36.929846 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5201 12:17:36.936318 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5202 12:17:36.939742 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5203 12:17:36.943027 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5204 12:17:36.946080 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5205 12:17:36.953188 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5206 12:17:36.956448 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5207 12:17:36.959567 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5208 12:17:36.959677 ==
5209 12:17:36.963339 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 12:17:36.966666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 12:17:36.966765 ==
5212 12:17:36.969974 DQS Delay:
5213 12:17:36.970060 DQS0 = 0, DQS1 = 0
5214 12:17:36.970125 DQM Delay:
5215 12:17:36.972977 DQM0 = 94, DQM1 = 84
5216 12:17:36.973079 DQ Delay:
5217 12:17:36.975726 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5218 12:17:36.979281 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =111
5219 12:17:36.982799 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5220 12:17:36.986042 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5221 12:17:36.986151
5222 12:17:36.986220
5223 12:17:36.989526 ==
5224 12:17:36.989619 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 12:17:36.996009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 12:17:36.996118 ==
5227 12:17:36.996186
5228 12:17:36.996247
5229 12:17:36.999131 TX Vref Scan disable
5230 12:17:36.999214 == TX Byte 0 ==
5231 12:17:37.002594 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5232 12:17:37.009578 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5233 12:17:37.009688 == TX Byte 1 ==
5234 12:17:37.012183 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5235 12:17:37.019023 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5236 12:17:37.019127 ==
5237 12:17:37.022536 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 12:17:37.025685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 12:17:37.025772 ==
5240 12:17:37.025858
5241 12:17:37.025940
5242 12:17:37.028948 TX Vref Scan disable
5243 12:17:37.032160 == TX Byte 0 ==
5244 12:17:37.035465 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5245 12:17:37.038969 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5246 12:17:37.042094 == TX Byte 1 ==
5247 12:17:37.045695 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5248 12:17:37.049236 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5249 12:17:37.049322
5250 12:17:37.049409 [DATLAT]
5251 12:17:37.052153 Freq=933, CH0 RK0
5252 12:17:37.052239
5253 12:17:37.055645 DATLAT Default: 0xd
5254 12:17:37.055731 0, 0xFFFF, sum = 0
5255 12:17:37.058988 1, 0xFFFF, sum = 0
5256 12:17:37.059074 2, 0xFFFF, sum = 0
5257 12:17:37.062136 3, 0xFFFF, sum = 0
5258 12:17:37.062222 4, 0xFFFF, sum = 0
5259 12:17:37.065267 5, 0xFFFF, sum = 0
5260 12:17:37.065354 6, 0xFFFF, sum = 0
5261 12:17:37.068723 7, 0xFFFF, sum = 0
5262 12:17:37.068810 8, 0xFFFF, sum = 0
5263 12:17:37.072643 9, 0xFFFF, sum = 0
5264 12:17:37.072732 10, 0x0, sum = 1
5265 12:17:37.075910 11, 0x0, sum = 2
5266 12:17:37.075997 12, 0x0, sum = 3
5267 12:17:37.078762 13, 0x0, sum = 4
5268 12:17:37.078848 best_step = 11
5269 12:17:37.078934
5270 12:17:37.079015 ==
5271 12:17:37.082183 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 12:17:37.085270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 12:17:37.088476 ==
5274 12:17:37.088563 RX Vref Scan: 1
5275 12:17:37.088649
5276 12:17:37.091770 RX Vref 0 -> 0, step: 1
5277 12:17:37.091855
5278 12:17:37.095267 RX Delay -69 -> 252, step: 4
5279 12:17:37.095356
5280 12:17:37.098832 Set Vref, RX VrefLevel [Byte0]: 63
5281 12:17:37.102278 [Byte1]: 50
5282 12:17:37.102361
5283 12:17:37.104930 Final RX Vref Byte 0 = 63 to rank0
5284 12:17:37.108565 Final RX Vref Byte 1 = 50 to rank0
5285 12:17:37.111573 Final RX Vref Byte 0 = 63 to rank1
5286 12:17:37.115122 Final RX Vref Byte 1 = 50 to rank1==
5287 12:17:37.118590 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 12:17:37.121633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 12:17:37.121721 ==
5290 12:17:37.125312 DQS Delay:
5291 12:17:37.125401 DQS0 = 0, DQS1 = 0
5292 12:17:37.125510 DQM Delay:
5293 12:17:37.128572 DQM0 = 95, DQM1 = 83
5294 12:17:37.128680 DQ Delay:
5295 12:17:37.131612 DQ0 =94, DQ1 =96, DQ2 =94, DQ3 =92
5296 12:17:37.134956 DQ4 =98, DQ5 =84, DQ6 =102, DQ7 =106
5297 12:17:37.138177 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =76
5298 12:17:37.141524 DQ12 =86, DQ13 =86, DQ14 =96, DQ15 =90
5299 12:17:37.141607
5300 12:17:37.141671
5301 12:17:37.151348 [DQSOSCAuto] RK0, (LSB)MR18= 0x1110, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5302 12:17:37.154692 CH0 RK0: MR19=505, MR18=1110
5303 12:17:37.158363 CH0_RK0: MR19=0x505, MR18=0x1110, DQSOSC=416, MR23=63, INC=62, DEC=41
5304 12:17:37.158448
5305 12:17:37.161297 ----->DramcWriteLeveling(PI) begin...
5306 12:17:37.164808 ==
5307 12:17:37.168247 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 12:17:37.171245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 12:17:37.171329 ==
5310 12:17:37.174983 Write leveling (Byte 0): 34 => 34
5311 12:17:37.178317 Write leveling (Byte 1): 31 => 31
5312 12:17:37.181241 DramcWriteLeveling(PI) end<-----
5313 12:17:37.181324
5314 12:17:37.181388 ==
5315 12:17:37.184480 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 12:17:37.188096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 12:17:37.188179 ==
5318 12:17:37.191319 [Gating] SW mode calibration
5319 12:17:37.197993 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5320 12:17:37.204374 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5321 12:17:37.207724 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5322 12:17:37.211264 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 12:17:37.217780 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 12:17:37.220969 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 12:17:37.224270 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 12:17:37.231211 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 12:17:37.234309 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 12:17:37.237580 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
5329 12:17:37.240559 0 15 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5330 12:17:37.247995 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 12:17:37.250622 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 12:17:37.254334 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 12:17:37.260722 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 12:17:37.263983 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 12:17:37.267112 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 12:17:37.274277 0 15 28 | B1->B0 | 2626 3535 | 0 0 | (0 0) (0 0)
5337 12:17:37.277185 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
5338 12:17:37.280341 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 12:17:37.287267 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 12:17:37.290306 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 12:17:37.293675 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 12:17:37.300620 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 12:17:37.304008 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 12:17:37.307018 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 12:17:37.313830 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:17:37.317110 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 12:17:37.320506 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 12:17:37.326676 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 12:17:37.330363 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 12:17:37.333634 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 12:17:37.340277 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 12:17:37.343346 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 12:17:37.346867 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 12:17:37.353775 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 12:17:37.357185 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 12:17:37.359911 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 12:17:37.366543 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 12:17:37.369824 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 12:17:37.373293 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 12:17:37.379937 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5361 12:17:37.380023 Total UI for P1: 0, mck2ui 16
5362 12:17:37.386764 best dqsien dly found for B0: ( 1, 2, 26)
5363 12:17:37.389704 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5364 12:17:37.393452 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 12:17:37.396549 Total UI for P1: 0, mck2ui 16
5366 12:17:37.399983 best dqsien dly found for B1: ( 1, 3, 0)
5367 12:17:37.403428 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5368 12:17:37.406470 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5369 12:17:37.406553
5370 12:17:37.409782 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5371 12:17:37.416354 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5372 12:17:37.416438 [Gating] SW calibration Done
5373 12:17:37.416504 ==
5374 12:17:37.420029 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 12:17:37.426616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 12:17:37.426704 ==
5377 12:17:37.426769 RX Vref Scan: 0
5378 12:17:37.426830
5379 12:17:37.430277 RX Vref 0 -> 0, step: 1
5380 12:17:37.430361
5381 12:17:37.433152 RX Delay -80 -> 252, step: 8
5382 12:17:37.436469 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5383 12:17:37.439933 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5384 12:17:37.443643 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5385 12:17:37.446511 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5386 12:17:37.453091 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5387 12:17:37.456151 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5388 12:17:37.459579 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5389 12:17:37.463268 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5390 12:17:37.466016 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5391 12:17:37.472721 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5392 12:17:37.476470 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5393 12:17:37.479450 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5394 12:17:37.482991 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5395 12:17:37.486337 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5396 12:17:37.492847 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5397 12:17:37.496331 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5398 12:17:37.496415 ==
5399 12:17:37.499286 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 12:17:37.502800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 12:17:37.502884 ==
5402 12:17:37.502949 DQS Delay:
5403 12:17:37.506429 DQS0 = 0, DQS1 = 0
5404 12:17:37.506511 DQM Delay:
5405 12:17:37.509282 DQM0 = 91, DQM1 = 83
5406 12:17:37.509364 DQ Delay:
5407 12:17:37.512820 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5408 12:17:37.516156 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5409 12:17:37.519569 DQ8 =75, DQ9 =63, DQ10 =87, DQ11 =75
5410 12:17:37.522364 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =87
5411 12:17:37.522446
5412 12:17:37.522511
5413 12:17:37.522570 ==
5414 12:17:37.525958 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 12:17:37.532374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 12:17:37.532458 ==
5417 12:17:37.532524
5418 12:17:37.532584
5419 12:17:37.532641 TX Vref Scan disable
5420 12:17:37.535861 == TX Byte 0 ==
5421 12:17:37.539054 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5422 12:17:37.545791 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5423 12:17:37.545874 == TX Byte 1 ==
5424 12:17:37.549255 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5425 12:17:37.556190 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5426 12:17:37.556274 ==
5427 12:17:37.559065 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 12:17:37.562578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 12:17:37.562661 ==
5430 12:17:37.562725
5431 12:17:37.562783
5432 12:17:37.565542 TX Vref Scan disable
5433 12:17:37.565624 == TX Byte 0 ==
5434 12:17:37.572268 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5435 12:17:37.575507 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5436 12:17:37.575590 == TX Byte 1 ==
5437 12:17:37.582038 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5438 12:17:37.585160 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5439 12:17:37.585248
5440 12:17:37.585313 [DATLAT]
5441 12:17:37.588709 Freq=933, CH0 RK1
5442 12:17:37.588792
5443 12:17:37.588857 DATLAT Default: 0xb
5444 12:17:37.591957 0, 0xFFFF, sum = 0
5445 12:17:37.592041 1, 0xFFFF, sum = 0
5446 12:17:37.595510 2, 0xFFFF, sum = 0
5447 12:17:37.598794 3, 0xFFFF, sum = 0
5448 12:17:37.598877 4, 0xFFFF, sum = 0
5449 12:17:37.602038 5, 0xFFFF, sum = 0
5450 12:17:37.602121 6, 0xFFFF, sum = 0
5451 12:17:37.605483 7, 0xFFFF, sum = 0
5452 12:17:37.605566 8, 0xFFFF, sum = 0
5453 12:17:37.608774 9, 0xFFFF, sum = 0
5454 12:17:37.608857 10, 0x0, sum = 1
5455 12:17:37.611912 11, 0x0, sum = 2
5456 12:17:37.612034 12, 0x0, sum = 3
5457 12:17:37.615646 13, 0x0, sum = 4
5458 12:17:37.615729 best_step = 11
5459 12:17:37.615793
5460 12:17:37.615852 ==
5461 12:17:37.618893 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 12:17:37.621821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 12:17:37.621924 ==
5464 12:17:37.625566 RX Vref Scan: 0
5465 12:17:37.625647
5466 12:17:37.628395 RX Vref 0 -> 0, step: 1
5467 12:17:37.628476
5468 12:17:37.628540 RX Delay -77 -> 252, step: 4
5469 12:17:37.636279 iDelay=199, Bit 0, Center 90 (-1 ~ 182) 184
5470 12:17:37.639869 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5471 12:17:37.642995 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5472 12:17:37.645991 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5473 12:17:37.649685 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5474 12:17:37.656441 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5475 12:17:37.659829 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5476 12:17:37.662722 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5477 12:17:37.666147 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5478 12:17:37.669488 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5479 12:17:37.676120 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5480 12:17:37.679515 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5481 12:17:37.683121 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5482 12:17:37.686198 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5483 12:17:37.689288 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5484 12:17:37.692926 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5485 12:17:37.696541 ==
5486 12:17:37.699457 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 12:17:37.702551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 12:17:37.702634 ==
5489 12:17:37.702699 DQS Delay:
5490 12:17:37.705698 DQS0 = 0, DQS1 = 0
5491 12:17:37.705780 DQM Delay:
5492 12:17:37.709285 DQM0 = 92, DQM1 = 84
5493 12:17:37.709367 DQ Delay:
5494 12:17:37.712728 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5495 12:17:37.715884 DQ4 =92, DQ5 =80, DQ6 =106, DQ7 =104
5496 12:17:37.719011 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5497 12:17:37.721972 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5498 12:17:37.722054
5499 12:17:37.722118
5500 12:17:37.729313 [DQSOSCAuto] RK1, (LSB)MR18= 0x3111, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5501 12:17:37.732479 CH0 RK1: MR19=505, MR18=3111
5502 12:17:37.738694 CH0_RK1: MR19=0x505, MR18=0x3111, DQSOSC=406, MR23=63, INC=65, DEC=43
5503 12:17:37.742133 [RxdqsGatingPostProcess] freq 933
5504 12:17:37.748546 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5505 12:17:37.751864 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 12:17:37.755565 best DQS1 dly(2T, 0.5T) = (0, 11)
5507 12:17:37.758843 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 12:17:37.762464 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5509 12:17:37.762547 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 12:17:37.765122 best DQS1 dly(2T, 0.5T) = (0, 11)
5511 12:17:37.768708 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 12:17:37.771429 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5513 12:17:37.775047 Pre-setting of DQS Precalculation
5514 12:17:37.781645 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5515 12:17:37.781728 ==
5516 12:17:37.785141 Dram Type= 6, Freq= 0, CH_1, rank 0
5517 12:17:37.788666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 12:17:37.788748 ==
5519 12:17:37.795254 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 12:17:37.801877 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5521 12:17:37.804876 [CA 0] Center 37 (7~68) winsize 62
5522 12:17:37.808199 [CA 1] Center 37 (7~68) winsize 62
5523 12:17:37.811575 [CA 2] Center 34 (5~64) winsize 60
5524 12:17:37.815254 [CA 3] Center 34 (4~64) winsize 61
5525 12:17:37.818720 [CA 4] Center 34 (5~64) winsize 60
5526 12:17:37.818802 [CA 5] Center 34 (4~64) winsize 61
5527 12:17:37.818866
5528 12:17:37.824870 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5529 12:17:37.824953
5530 12:17:37.828653 [CATrainingPosCal] consider 1 rank data
5531 12:17:37.831648 u2DelayCellTimex100 = 270/100 ps
5532 12:17:37.834773 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5533 12:17:37.838768 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5534 12:17:37.841346 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5535 12:17:37.844994 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5536 12:17:37.848105 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5537 12:17:37.851641 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5538 12:17:37.851723
5539 12:17:37.854665 CA PerBit enable=1, Macro0, CA PI delay=34
5540 12:17:37.854747
5541 12:17:37.858195 [CBTSetCACLKResult] CA Dly = 34
5542 12:17:37.861410 CS Dly: 5 (0~36)
5543 12:17:37.861492 ==
5544 12:17:37.864623 Dram Type= 6, Freq= 0, CH_1, rank 1
5545 12:17:37.868278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 12:17:37.868365 ==
5547 12:17:37.874540 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 12:17:37.881183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5549 12:17:37.884388 [CA 0] Center 37 (8~67) winsize 60
5550 12:17:37.887979 [CA 1] Center 37 (7~68) winsize 62
5551 12:17:37.891239 [CA 2] Center 35 (5~65) winsize 61
5552 12:17:37.894264 [CA 3] Center 34 (4~64) winsize 61
5553 12:17:37.897521 [CA 4] Center 35 (5~65) winsize 61
5554 12:17:37.900745 [CA 5] Center 34 (4~64) winsize 61
5555 12:17:37.900827
5556 12:17:37.904267 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5557 12:17:37.904348
5558 12:17:37.907285 [CATrainingPosCal] consider 2 rank data
5559 12:17:37.910594 u2DelayCellTimex100 = 270/100 ps
5560 12:17:37.914056 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5561 12:17:37.917563 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5562 12:17:37.920930 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5563 12:17:37.923842 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5564 12:17:37.927101 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5565 12:17:37.930782 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5566 12:17:37.933754
5567 12:17:37.937010 CA PerBit enable=1, Macro0, CA PI delay=34
5568 12:17:37.937090
5569 12:17:37.940537 [CBTSetCACLKResult] CA Dly = 34
5570 12:17:37.940676 CS Dly: 6 (0~39)
5571 12:17:37.940753
5572 12:17:37.944022 ----->DramcWriteLeveling(PI) begin...
5573 12:17:37.944104 ==
5574 12:17:37.947128 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 12:17:37.950448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 12:17:37.953553 ==
5577 12:17:37.953632 Write leveling (Byte 0): 26 => 26
5578 12:17:37.957325 Write leveling (Byte 1): 27 => 27
5579 12:17:37.960224 DramcWriteLeveling(PI) end<-----
5580 12:17:37.960304
5581 12:17:37.960398 ==
5582 12:17:37.963841 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 12:17:37.970694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 12:17:37.970777 ==
5585 12:17:37.970841 [Gating] SW mode calibration
5586 12:17:37.980249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5587 12:17:37.983830 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5588 12:17:37.990100 0 14 0 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
5589 12:17:37.993748 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 12:17:37.996679 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 12:17:38.003297 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 12:17:38.006659 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 12:17:38.009856 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 12:17:38.013521 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 12:17:38.019917 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
5596 12:17:38.023055 0 15 0 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5597 12:17:38.026403 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 12:17:38.033782 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 12:17:38.036880 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 12:17:38.040491 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 12:17:38.046776 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 12:17:38.050446 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 12:17:38.053826 0 15 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
5604 12:17:38.059741 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5605 12:17:38.063355 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 12:17:38.066693 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 12:17:38.073311 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 12:17:38.076745 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 12:17:38.080472 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 12:17:38.086964 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 12:17:38.090291 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5612 12:17:38.093274 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5613 12:17:38.099790 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 12:17:38.103278 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 12:17:38.106609 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 12:17:38.113376 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 12:17:38.117050 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 12:17:38.120035 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 12:17:38.126466 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 12:17:38.129542 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 12:17:38.132656 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 12:17:38.139204 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 12:17:38.142793 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 12:17:38.146115 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 12:17:38.152755 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 12:17:38.155750 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5627 12:17:38.159365 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5628 12:17:38.165754 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 12:17:38.165845 Total UI for P1: 0, mck2ui 16
5630 12:17:38.172307 best dqsien dly found for B0: ( 1, 2, 26)
5631 12:17:38.172412 Total UI for P1: 0, mck2ui 16
5632 12:17:38.175786 best dqsien dly found for B1: ( 1, 2, 26)
5633 12:17:38.182799 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5634 12:17:38.185810 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5635 12:17:38.185905
5636 12:17:38.189436 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5637 12:17:38.192529 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5638 12:17:38.195780 [Gating] SW calibration Done
5639 12:17:38.195863 ==
5640 12:17:38.199297 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 12:17:38.202703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 12:17:38.202786 ==
5643 12:17:38.206225 RX Vref Scan: 0
5644 12:17:38.206308
5645 12:17:38.206373 RX Vref 0 -> 0, step: 1
5646 12:17:38.206434
5647 12:17:38.208960 RX Delay -80 -> 252, step: 8
5648 12:17:38.212481 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5649 12:17:38.215562 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5650 12:17:38.222395 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5651 12:17:38.225702 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5652 12:17:38.228928 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5653 12:17:38.232431 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5654 12:17:38.235895 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5655 12:17:38.242438 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5656 12:17:38.245574 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5657 12:17:38.249019 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5658 12:17:38.252018 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5659 12:17:38.255813 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5660 12:17:38.262113 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5661 12:17:38.265738 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5662 12:17:38.268607 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5663 12:17:38.272142 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5664 12:17:38.272226 ==
5665 12:17:38.275520 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 12:17:38.278753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 12:17:38.282029 ==
5668 12:17:38.282111 DQS Delay:
5669 12:17:38.282176 DQS0 = 0, DQS1 = 0
5670 12:17:38.285075 DQM Delay:
5671 12:17:38.285156 DQM0 = 94, DQM1 = 86
5672 12:17:38.289050 DQ Delay:
5673 12:17:38.289135 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5674 12:17:38.292102 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5675 12:17:38.295169 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5676 12:17:38.298736 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5677 12:17:38.302005
5678 12:17:38.302087
5679 12:17:38.302151 ==
5680 12:17:38.304976 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 12:17:38.308537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 12:17:38.308620 ==
5683 12:17:38.308688
5684 12:17:38.308749
5685 12:17:38.311783 TX Vref Scan disable
5686 12:17:38.311865 == TX Byte 0 ==
5687 12:17:38.318567 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5688 12:17:38.322048 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5689 12:17:38.322130 == TX Byte 1 ==
5690 12:17:38.328244 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5691 12:17:38.331524 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5692 12:17:38.331607 ==
5693 12:17:38.335001 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 12:17:38.338079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 12:17:38.338162 ==
5696 12:17:38.338226
5697 12:17:38.338286
5698 12:17:38.341609 TX Vref Scan disable
5699 12:17:38.345280 == TX Byte 0 ==
5700 12:17:38.348539 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5701 12:17:38.351769 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5702 12:17:38.355518 == TX Byte 1 ==
5703 12:17:38.358602 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5704 12:17:38.361606 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5705 12:17:38.361717
5706 12:17:38.365175 [DATLAT]
5707 12:17:38.365257 Freq=933, CH1 RK0
5708 12:17:38.365323
5709 12:17:38.368112 DATLAT Default: 0xd
5710 12:17:38.368194 0, 0xFFFF, sum = 0
5711 12:17:38.371445 1, 0xFFFF, sum = 0
5712 12:17:38.371528 2, 0xFFFF, sum = 0
5713 12:17:38.375014 3, 0xFFFF, sum = 0
5714 12:17:38.375098 4, 0xFFFF, sum = 0
5715 12:17:38.378244 5, 0xFFFF, sum = 0
5716 12:17:38.378328 6, 0xFFFF, sum = 0
5717 12:17:38.381399 7, 0xFFFF, sum = 0
5718 12:17:38.381483 8, 0xFFFF, sum = 0
5719 12:17:38.385048 9, 0xFFFF, sum = 0
5720 12:17:38.385132 10, 0x0, sum = 1
5721 12:17:38.387963 11, 0x0, sum = 2
5722 12:17:38.388046 12, 0x0, sum = 3
5723 12:17:38.391946 13, 0x0, sum = 4
5724 12:17:38.392029 best_step = 11
5725 12:17:38.392094
5726 12:17:38.392154 ==
5727 12:17:38.394573 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 12:17:38.401293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 12:17:38.401376 ==
5730 12:17:38.401441 RX Vref Scan: 1
5731 12:17:38.401501
5732 12:17:38.404821 RX Vref 0 -> 0, step: 1
5733 12:17:38.404903
5734 12:17:38.408123 RX Delay -69 -> 252, step: 4
5735 12:17:38.408206
5736 12:17:38.411344 Set Vref, RX VrefLevel [Byte0]: 57
5737 12:17:38.414561 [Byte1]: 48
5738 12:17:38.414643
5739 12:17:38.418076 Final RX Vref Byte 0 = 57 to rank0
5740 12:17:38.421141 Final RX Vref Byte 1 = 48 to rank0
5741 12:17:38.424410 Final RX Vref Byte 0 = 57 to rank1
5742 12:17:38.427899 Final RX Vref Byte 1 = 48 to rank1==
5743 12:17:38.431206 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 12:17:38.434339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 12:17:38.434427 ==
5746 12:17:38.437918 DQS Delay:
5747 12:17:38.438003 DQS0 = 0, DQS1 = 0
5748 12:17:38.438069 DQM Delay:
5749 12:17:38.440971 DQM0 = 96, DQM1 = 88
5750 12:17:38.441052 DQ Delay:
5751 12:17:38.444516 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =94
5752 12:17:38.448082 DQ4 =94, DQ5 =106, DQ6 =106, DQ7 =94
5753 12:17:38.451116 DQ8 =76, DQ9 =78, DQ10 =88, DQ11 =82
5754 12:17:38.454899 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =94
5755 12:17:38.454980
5756 12:17:38.455045
5757 12:17:38.464435 [DQSOSCAuto] RK0, (LSB)MR18= 0x20a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5758 12:17:38.468016 CH1 RK0: MR19=505, MR18=20A
5759 12:17:38.471396 CH1_RK0: MR19=0x505, MR18=0x20A, DQSOSC=418, MR23=63, INC=62, DEC=41
5760 12:17:38.471516
5761 12:17:38.474681 ----->DramcWriteLeveling(PI) begin...
5762 12:17:38.477491 ==
5763 12:17:38.477573 Dram Type= 6, Freq= 0, CH_1, rank 1
5764 12:17:38.484589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 12:17:38.484716 ==
5766 12:17:38.487304 Write leveling (Byte 0): 25 => 25
5767 12:17:38.491241 Write leveling (Byte 1): 31 => 31
5768 12:17:38.494432 DramcWriteLeveling(PI) end<-----
5769 12:17:38.494520
5770 12:17:38.494584 ==
5771 12:17:38.497403 Dram Type= 6, Freq= 0, CH_1, rank 1
5772 12:17:38.500872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 12:17:38.500959 ==
5774 12:17:38.503900 [Gating] SW mode calibration
5775 12:17:38.510776 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5776 12:17:38.517909 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5777 12:17:38.520889 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 12:17:38.524799 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 12:17:38.530899 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 12:17:38.534733 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 12:17:38.537995 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 12:17:38.544287 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 12:17:38.547344 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (1 0)
5784 12:17:38.551104 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 0)
5785 12:17:38.557516 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 12:17:38.560932 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 12:17:38.564186 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 12:17:38.567375 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 12:17:38.574554 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 12:17:38.577074 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5791 12:17:38.580696 0 15 24 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
5792 12:17:38.587963 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5793 12:17:38.590864 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 12:17:38.594256 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 12:17:38.600876 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 12:17:38.603703 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 12:17:38.607509 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 12:17:38.614271 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 12:17:38.617771 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5800 12:17:38.620887 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5801 12:17:38.627254 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 12:17:38.630584 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 12:17:38.634066 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 12:17:38.641103 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 12:17:38.643782 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 12:17:38.647129 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 12:17:38.653632 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 12:17:38.657072 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 12:17:38.660753 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 12:17:38.667490 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 12:17:38.670082 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 12:17:38.673499 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 12:17:38.679910 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 12:17:38.683291 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 12:17:38.687235 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5816 12:17:38.693601 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5817 12:17:38.696921 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 12:17:38.700310 Total UI for P1: 0, mck2ui 16
5819 12:17:38.703022 best dqsien dly found for B0: ( 1, 2, 26)
5820 12:17:38.706892 Total UI for P1: 0, mck2ui 16
5821 12:17:38.710622 best dqsien dly found for B1: ( 1, 2, 28)
5822 12:17:38.713627 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5823 12:17:38.716482 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5824 12:17:38.716903
5825 12:17:38.719507 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5826 12:17:38.723346 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5827 12:17:38.726292 [Gating] SW calibration Done
5828 12:17:38.726712 ==
5829 12:17:38.729363 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 12:17:38.733243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 12:17:38.736394 ==
5832 12:17:38.736917 RX Vref Scan: 0
5833 12:17:38.737250
5834 12:17:38.739543 RX Vref 0 -> 0, step: 1
5835 12:17:38.739960
5836 12:17:38.743222 RX Delay -80 -> 252, step: 8
5837 12:17:38.746579 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5838 12:17:38.749792 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5839 12:17:38.752623 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5840 12:17:38.756245 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5841 12:17:38.762852 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5842 12:17:38.765988 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5843 12:17:38.769079 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5844 12:17:38.772331 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5845 12:17:38.775941 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5846 12:17:38.779528 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5847 12:17:38.785995 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5848 12:17:38.789386 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5849 12:17:38.792119 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5850 12:17:38.795469 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5851 12:17:38.799020 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5852 12:17:38.805738 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5853 12:17:38.806261 ==
5854 12:17:38.808755 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 12:17:38.812262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 12:17:38.812688 ==
5857 12:17:38.813021 DQS Delay:
5858 12:17:38.815617 DQS0 = 0, DQS1 = 0
5859 12:17:38.816034 DQM Delay:
5860 12:17:38.819337 DQM0 = 93, DQM1 = 87
5861 12:17:38.819930 DQ Delay:
5862 12:17:38.822647 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5863 12:17:38.825575 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5864 12:17:38.828483 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5865 12:17:38.832342 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5866 12:17:38.832868
5867 12:17:38.833199
5868 12:17:38.833508 ==
5869 12:17:38.835498 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 12:17:38.838860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 12:17:38.842437 ==
5872 12:17:38.842959
5873 12:17:38.843289
5874 12:17:38.843650 TX Vref Scan disable
5875 12:17:38.845870 == TX Byte 0 ==
5876 12:17:38.848543 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5877 12:17:38.852183 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5878 12:17:38.855227 == TX Byte 1 ==
5879 12:17:38.859093 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5880 12:17:38.862102 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5881 12:17:38.865168 ==
5882 12:17:38.868824 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 12:17:38.871722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 12:17:38.872245 ==
5885 12:17:38.872644
5886 12:17:38.873164
5887 12:17:38.875230 TX Vref Scan disable
5888 12:17:38.875815 == TX Byte 0 ==
5889 12:17:38.882131 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5890 12:17:38.885105 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5891 12:17:38.885525 == TX Byte 1 ==
5892 12:17:38.891586 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5893 12:17:38.894527 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5894 12:17:38.894950
5895 12:17:38.895278 [DATLAT]
5896 12:17:38.898075 Freq=933, CH1 RK1
5897 12:17:38.898501
5898 12:17:38.898830 DATLAT Default: 0xb
5899 12:17:38.901807 0, 0xFFFF, sum = 0
5900 12:17:38.902341 1, 0xFFFF, sum = 0
5901 12:17:38.904499 2, 0xFFFF, sum = 0
5902 12:17:38.904928 3, 0xFFFF, sum = 0
5903 12:17:38.908034 4, 0xFFFF, sum = 0
5904 12:17:38.911459 5, 0xFFFF, sum = 0
5905 12:17:38.911887 6, 0xFFFF, sum = 0
5906 12:17:38.914373 7, 0xFFFF, sum = 0
5907 12:17:38.914793 8, 0xFFFF, sum = 0
5908 12:17:38.918240 9, 0xFFFF, sum = 0
5909 12:17:38.918772 10, 0x0, sum = 1
5910 12:17:38.921162 11, 0x0, sum = 2
5911 12:17:38.921688 12, 0x0, sum = 3
5912 12:17:38.924398 13, 0x0, sum = 4
5913 12:17:38.924819 best_step = 11
5914 12:17:38.925150
5915 12:17:38.925459 ==
5916 12:17:38.927625 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 12:17:38.930947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 12:17:38.931499 ==
5919 12:17:38.934380 RX Vref Scan: 0
5920 12:17:38.934894
5921 12:17:38.937585 RX Vref 0 -> 0, step: 1
5922 12:17:38.938003
5923 12:17:38.938330 RX Delay -69 -> 252, step: 4
5924 12:17:38.946154 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5925 12:17:38.948859 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5926 12:17:38.952669 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5927 12:17:38.956133 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5928 12:17:38.959240 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5929 12:17:38.965936 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5930 12:17:38.968517 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5931 12:17:38.972101 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5932 12:17:38.975556 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5933 12:17:38.978825 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5934 12:17:38.985242 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5935 12:17:38.988646 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5936 12:17:38.992054 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5937 12:17:38.995151 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5938 12:17:38.998578 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5939 12:17:39.001682 iDelay=203, Bit 15, Center 98 (7 ~ 190) 184
5940 12:17:39.002207 ==
5941 12:17:39.005354 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 12:17:39.011492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 12:17:39.011914 ==
5944 12:17:39.012243 DQS Delay:
5945 12:17:39.014743 DQS0 = 0, DQS1 = 0
5946 12:17:39.015159 DQM Delay:
5947 12:17:39.015533 DQM0 = 92, DQM1 = 90
5948 12:17:39.018251 DQ Delay:
5949 12:17:39.021707 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5950 12:17:39.025313 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =90
5951 12:17:39.028321 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
5952 12:17:39.031810 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5953 12:17:39.032233
5954 12:17:39.032564
5955 12:17:39.038408 [DQSOSCAuto] RK1, (LSB)MR18= 0x1024, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5956 12:17:39.041953 CH1 RK1: MR19=505, MR18=1024
5957 12:17:39.048402 CH1_RK1: MR19=0x505, MR18=0x1024, DQSOSC=410, MR23=63, INC=64, DEC=42
5958 12:17:39.052043 [RxdqsGatingPostProcess] freq 933
5959 12:17:39.055540 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5960 12:17:39.058293 best DQS0 dly(2T, 0.5T) = (0, 10)
5961 12:17:39.061770 best DQS1 dly(2T, 0.5T) = (0, 10)
5962 12:17:39.065107 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5963 12:17:39.068294 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5964 12:17:39.071672 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 12:17:39.074867 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 12:17:39.078179 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 12:17:39.081862 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 12:17:39.084407 Pre-setting of DQS Precalculation
5969 12:17:39.088044 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5970 12:17:39.097836 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5971 12:17:39.104424 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5972 12:17:39.104947
5973 12:17:39.105280
5974 12:17:39.107627 [Calibration Summary] 1866 Mbps
5975 12:17:39.108045 CH 0, Rank 0
5976 12:17:39.111431 SW Impedance : PASS
5977 12:17:39.111967 DUTY Scan : NO K
5978 12:17:39.114224 ZQ Calibration : PASS
5979 12:17:39.118308 Jitter Meter : NO K
5980 12:17:39.118843 CBT Training : PASS
5981 12:17:39.121438 Write leveling : PASS
5982 12:17:39.125029 RX DQS gating : PASS
5983 12:17:39.125550 RX DQ/DQS(RDDQC) : PASS
5984 12:17:39.127873 TX DQ/DQS : PASS
5985 12:17:39.130912 RX DATLAT : PASS
5986 12:17:39.131478 RX DQ/DQS(Engine): PASS
5987 12:17:39.134505 TX OE : NO K
5988 12:17:39.135034 All Pass.
5989 12:17:39.135368
5990 12:17:39.137693 CH 0, Rank 1
5991 12:17:39.138220 SW Impedance : PASS
5992 12:17:39.141298 DUTY Scan : NO K
5993 12:17:39.144672 ZQ Calibration : PASS
5994 12:17:39.145090 Jitter Meter : NO K
5995 12:17:39.147950 CBT Training : PASS
5996 12:17:39.150929 Write leveling : PASS
5997 12:17:39.151347 RX DQS gating : PASS
5998 12:17:39.154466 RX DQ/DQS(RDDQC) : PASS
5999 12:17:39.157964 TX DQ/DQS : PASS
6000 12:17:39.158507 RX DATLAT : PASS
6001 12:17:39.160668 RX DQ/DQS(Engine): PASS
6002 12:17:39.161190 TX OE : NO K
6003 12:17:39.164095 All Pass.
6004 12:17:39.164612
6005 12:17:39.164947 CH 1, Rank 0
6006 12:17:39.168267 SW Impedance : PASS
6007 12:17:39.168798 DUTY Scan : NO K
6008 12:17:39.171554 ZQ Calibration : PASS
6009 12:17:39.174440 Jitter Meter : NO K
6010 12:17:39.174969 CBT Training : PASS
6011 12:17:39.178141 Write leveling : PASS
6012 12:17:39.180784 RX DQS gating : PASS
6013 12:17:39.181302 RX DQ/DQS(RDDQC) : PASS
6014 12:17:39.184318 TX DQ/DQS : PASS
6015 12:17:39.187837 RX DATLAT : PASS
6016 12:17:39.188360 RX DQ/DQS(Engine): PASS
6017 12:17:39.190613 TX OE : NO K
6018 12:17:39.191030 All Pass.
6019 12:17:39.191359
6020 12:17:39.194134 CH 1, Rank 1
6021 12:17:39.194551 SW Impedance : PASS
6022 12:17:39.197412 DUTY Scan : NO K
6023 12:17:39.200364 ZQ Calibration : PASS
6024 12:17:39.200837 Jitter Meter : NO K
6025 12:17:39.204090 CBT Training : PASS
6026 12:17:39.207536 Write leveling : PASS
6027 12:17:39.208051 RX DQS gating : PASS
6028 12:17:39.210663 RX DQ/DQS(RDDQC) : PASS
6029 12:17:39.213912 TX DQ/DQS : PASS
6030 12:17:39.214437 RX DATLAT : PASS
6031 12:17:39.217437 RX DQ/DQS(Engine): PASS
6032 12:17:39.217957 TX OE : NO K
6033 12:17:39.220852 All Pass.
6034 12:17:39.221373
6035 12:17:39.221708 DramC Write-DBI off
6036 12:17:39.223815 PER_BANK_REFRESH: Hybrid Mode
6037 12:17:39.227133 TX_TRACKING: ON
6038 12:17:39.233882 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6039 12:17:39.237731 [FAST_K] Save calibration result to emmc
6040 12:17:39.244121 dramc_set_vcore_voltage set vcore to 650000
6041 12:17:39.244650 Read voltage for 400, 6
6042 12:17:39.244989 Vio18 = 0
6043 12:17:39.247269 Vcore = 650000
6044 12:17:39.247840 Vdram = 0
6045 12:17:39.248178 Vddq = 0
6046 12:17:39.250116 Vmddr = 0
6047 12:17:39.253628 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6048 12:17:39.260415 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6049 12:17:39.263809 MEM_TYPE=3, freq_sel=20
6050 12:17:39.264334 sv_algorithm_assistance_LP4_800
6051 12:17:39.270331 ============ PULL DRAM RESETB DOWN ============
6052 12:17:39.273790 ========== PULL DRAM RESETB DOWN end =========
6053 12:17:39.276911 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6054 12:17:39.279884 ===================================
6055 12:17:39.283547 LPDDR4 DRAM CONFIGURATION
6056 12:17:39.286976 ===================================
6057 12:17:39.290025 EX_ROW_EN[0] = 0x0
6058 12:17:39.290446 EX_ROW_EN[1] = 0x0
6059 12:17:39.293283 LP4Y_EN = 0x0
6060 12:17:39.293703 WORK_FSP = 0x0
6061 12:17:39.296625 WL = 0x2
6062 12:17:39.297042 RL = 0x2
6063 12:17:39.300203 BL = 0x2
6064 12:17:39.300620 RPST = 0x0
6065 12:17:39.303606 RD_PRE = 0x0
6066 12:17:39.304025 WR_PRE = 0x1
6067 12:17:39.306801 WR_PST = 0x0
6068 12:17:39.307217 DBI_WR = 0x0
6069 12:17:39.310103 DBI_RD = 0x0
6070 12:17:39.310520 OTF = 0x1
6071 12:17:39.313078 ===================================
6072 12:17:39.316384 ===================================
6073 12:17:39.320050 ANA top config
6074 12:17:39.322910 ===================================
6075 12:17:39.326184 DLL_ASYNC_EN = 0
6076 12:17:39.326604 ALL_SLAVE_EN = 1
6077 12:17:39.330234 NEW_RANK_MODE = 1
6078 12:17:39.333033 DLL_IDLE_MODE = 1
6079 12:17:39.336758 LP45_APHY_COMB_EN = 1
6080 12:17:39.337271 TX_ODT_DIS = 1
6081 12:17:39.340211 NEW_8X_MODE = 1
6082 12:17:39.343671 ===================================
6083 12:17:39.346959 ===================================
6084 12:17:39.350134 data_rate = 800
6085 12:17:39.352877 CKR = 1
6086 12:17:39.356338 DQ_P2S_RATIO = 4
6087 12:17:39.359853 ===================================
6088 12:17:39.363762 CA_P2S_RATIO = 4
6089 12:17:39.364285 DQ_CA_OPEN = 0
6090 12:17:39.366484 DQ_SEMI_OPEN = 1
6091 12:17:39.369438 CA_SEMI_OPEN = 1
6092 12:17:39.373179 CA_FULL_RATE = 0
6093 12:17:39.376269 DQ_CKDIV4_EN = 0
6094 12:17:39.380128 CA_CKDIV4_EN = 1
6095 12:17:39.380648 CA_PREDIV_EN = 0
6096 12:17:39.383232 PH8_DLY = 0
6097 12:17:39.386474 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6098 12:17:39.390108 DQ_AAMCK_DIV = 0
6099 12:17:39.393405 CA_AAMCK_DIV = 0
6100 12:17:39.396098 CA_ADMCK_DIV = 4
6101 12:17:39.396619 DQ_TRACK_CA_EN = 0
6102 12:17:39.399969 CA_PICK = 800
6103 12:17:39.403276 CA_MCKIO = 400
6104 12:17:39.406233 MCKIO_SEMI = 400
6105 12:17:39.409709 PLL_FREQ = 3016
6106 12:17:39.412764 DQ_UI_PI_RATIO = 32
6107 12:17:39.416074 CA_UI_PI_RATIO = 32
6108 12:17:39.419957 ===================================
6109 12:17:39.423187 ===================================
6110 12:17:39.423765 memory_type:LPDDR4
6111 12:17:39.426568 GP_NUM : 10
6112 12:17:39.429430 SRAM_EN : 1
6113 12:17:39.429869 MD32_EN : 0
6114 12:17:39.432910 ===================================
6115 12:17:39.436355 [ANA_INIT] >>>>>>>>>>>>>>
6116 12:17:39.439678 <<<<<< [CONFIGURE PHASE]: ANA_TX
6117 12:17:39.443190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6118 12:17:39.446335 ===================================
6119 12:17:39.449871 data_rate = 800,PCW = 0X7400
6120 12:17:39.452630 ===================================
6121 12:17:39.456325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6122 12:17:39.459629 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6123 12:17:39.472417 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 12:17:39.476204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6125 12:17:39.479191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6126 12:17:39.482978 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6127 12:17:39.485794 [ANA_INIT] flow start
6128 12:17:39.489101 [ANA_INIT] PLL >>>>>>>>
6129 12:17:39.489645 [ANA_INIT] PLL <<<<<<<<
6130 12:17:39.492104 [ANA_INIT] MIDPI >>>>>>>>
6131 12:17:39.495603 [ANA_INIT] MIDPI <<<<<<<<
6132 12:17:39.496209 [ANA_INIT] DLL >>>>>>>>
6133 12:17:39.499072 [ANA_INIT] flow end
6134 12:17:39.501895 ============ LP4 DIFF to SE enter ============
6135 12:17:39.508896 ============ LP4 DIFF to SE exit ============
6136 12:17:39.509528 [ANA_INIT] <<<<<<<<<<<<<
6137 12:17:39.511885 [Flow] Enable top DCM control >>>>>
6138 12:17:39.515611 [Flow] Enable top DCM control <<<<<
6139 12:17:39.518910 Enable DLL master slave shuffle
6140 12:17:39.525177 ==============================================================
6141 12:17:39.525682 Gating Mode config
6142 12:17:39.532122 ==============================================================
6143 12:17:39.534998 Config description:
6144 12:17:39.542207 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6145 12:17:39.548458 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6146 12:17:39.555560 SELPH_MODE 0: By rank 1: By Phase
6147 12:17:39.561613 ==============================================================
6148 12:17:39.564797 GAT_TRACK_EN = 0
6149 12:17:39.565313 RX_GATING_MODE = 2
6150 12:17:39.568868 RX_GATING_TRACK_MODE = 2
6151 12:17:39.571742 SELPH_MODE = 1
6152 12:17:39.575450 PICG_EARLY_EN = 1
6153 12:17:39.578215 VALID_LAT_VALUE = 1
6154 12:17:39.584668 ==============================================================
6155 12:17:39.588327 Enter into Gating configuration >>>>
6156 12:17:39.591180 Exit from Gating configuration <<<<
6157 12:17:39.594919 Enter into DVFS_PRE_config >>>>>
6158 12:17:39.604865 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6159 12:17:39.608190 Exit from DVFS_PRE_config <<<<<
6160 12:17:39.611417 Enter into PICG configuration >>>>
6161 12:17:39.614374 Exit from PICG configuration <<<<
6162 12:17:39.617796 [RX_INPUT] configuration >>>>>
6163 12:17:39.621086 [RX_INPUT] configuration <<<<<
6164 12:17:39.624054 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6165 12:17:39.631246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6166 12:17:39.637622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6167 12:17:39.644502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6168 12:17:39.647964 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6169 12:17:39.654645 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6170 12:17:39.657577 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6171 12:17:39.664293 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6172 12:17:39.667943 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6173 12:17:39.671166 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6174 12:17:39.674010 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6175 12:17:39.681449 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6176 12:17:39.684101 ===================================
6177 12:17:39.684521 LPDDR4 DRAM CONFIGURATION
6178 12:17:39.687780 ===================================
6179 12:17:39.691175 EX_ROW_EN[0] = 0x0
6180 12:17:39.694327 EX_ROW_EN[1] = 0x0
6181 12:17:39.694841 LP4Y_EN = 0x0
6182 12:17:39.697478 WORK_FSP = 0x0
6183 12:17:39.697994 WL = 0x2
6184 12:17:39.700252 RL = 0x2
6185 12:17:39.700670 BL = 0x2
6186 12:17:39.704310 RPST = 0x0
6187 12:17:39.704822 RD_PRE = 0x0
6188 12:17:39.707270 WR_PRE = 0x1
6189 12:17:39.707710 WR_PST = 0x0
6190 12:17:39.710555 DBI_WR = 0x0
6191 12:17:39.710991 DBI_RD = 0x0
6192 12:17:39.713873 OTF = 0x1
6193 12:17:39.717121 ===================================
6194 12:17:39.720078 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6195 12:17:39.723593 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6196 12:17:39.730689 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6197 12:17:39.733469 ===================================
6198 12:17:39.733892 LPDDR4 DRAM CONFIGURATION
6199 12:17:39.736608 ===================================
6200 12:17:39.740291 EX_ROW_EN[0] = 0x10
6201 12:17:39.743503 EX_ROW_EN[1] = 0x0
6202 12:17:39.743928 LP4Y_EN = 0x0
6203 12:17:39.747046 WORK_FSP = 0x0
6204 12:17:39.747613 WL = 0x2
6205 12:17:39.750387 RL = 0x2
6206 12:17:39.750957 BL = 0x2
6207 12:17:39.753319 RPST = 0x0
6208 12:17:39.753737 RD_PRE = 0x0
6209 12:17:39.757040 WR_PRE = 0x1
6210 12:17:39.757570 WR_PST = 0x0
6211 12:17:39.760141 DBI_WR = 0x0
6212 12:17:39.760560 DBI_RD = 0x0
6213 12:17:39.763833 OTF = 0x1
6214 12:17:39.766352 ===================================
6215 12:17:39.773340 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6216 12:17:39.776340 nWR fixed to 30
6217 12:17:39.780063 [ModeRegInit_LP4] CH0 RK0
6218 12:17:39.780477 [ModeRegInit_LP4] CH0 RK1
6219 12:17:39.783237 [ModeRegInit_LP4] CH1 RK0
6220 12:17:39.786690 [ModeRegInit_LP4] CH1 RK1
6221 12:17:39.787205 match AC timing 19
6222 12:17:39.793736 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6223 12:17:39.797016 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6224 12:17:39.800318 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6225 12:17:39.806982 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6226 12:17:39.810015 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6227 12:17:39.810434 ==
6228 12:17:39.813439 Dram Type= 6, Freq= 0, CH_0, rank 0
6229 12:17:39.816754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6230 12:17:39.817183 ==
6231 12:17:39.823412 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6232 12:17:39.829927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6233 12:17:39.832851 [CA 0] Center 36 (8~64) winsize 57
6234 12:17:39.836288 [CA 1] Center 36 (8~64) winsize 57
6235 12:17:39.836813 [CA 2] Center 36 (8~64) winsize 57
6236 12:17:39.840263 [CA 3] Center 36 (8~64) winsize 57
6237 12:17:39.843206 [CA 4] Center 36 (8~64) winsize 57
6238 12:17:39.847130 [CA 5] Center 36 (8~64) winsize 57
6239 12:17:39.847709
6240 12:17:39.849909 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6241 12:17:39.850431
6242 12:17:39.856867 [CATrainingPosCal] consider 1 rank data
6243 12:17:39.857397 u2DelayCellTimex100 = 270/100 ps
6244 12:17:39.863870 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:17:39.866373 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:17:39.869614 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 12:17:39.873175 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 12:17:39.876438 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 12:17:39.879924 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 12:17:39.880346
6251 12:17:39.883168 CA PerBit enable=1, Macro0, CA PI delay=36
6252 12:17:39.883742
6253 12:17:39.886540 [CBTSetCACLKResult] CA Dly = 36
6254 12:17:39.890243 CS Dly: 1 (0~32)
6255 12:17:39.890765 ==
6256 12:17:39.892983 Dram Type= 6, Freq= 0, CH_0, rank 1
6257 12:17:39.896389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 12:17:39.896914 ==
6259 12:17:39.902879 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6260 12:17:39.906773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6261 12:17:39.909291 [CA 0] Center 36 (8~64) winsize 57
6262 12:17:39.912790 [CA 1] Center 36 (8~64) winsize 57
6263 12:17:39.916150 [CA 2] Center 36 (8~64) winsize 57
6264 12:17:39.919181 [CA 3] Center 36 (8~64) winsize 57
6265 12:17:39.922579 [CA 4] Center 36 (8~64) winsize 57
6266 12:17:39.926084 [CA 5] Center 36 (8~64) winsize 57
6267 12:17:39.926606
6268 12:17:39.929139 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6269 12:17:39.929559
6270 12:17:39.932617 [CATrainingPosCal] consider 2 rank data
6271 12:17:39.936248 u2DelayCellTimex100 = 270/100 ps
6272 12:17:39.939521 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 12:17:39.942687 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 12:17:39.946507 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 12:17:39.952534 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 12:17:39.955846 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 12:17:39.959243 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 12:17:39.959812
6279 12:17:39.962381 CA PerBit enable=1, Macro0, CA PI delay=36
6280 12:17:39.962901
6281 12:17:39.966097 [CBTSetCACLKResult] CA Dly = 36
6282 12:17:39.966621 CS Dly: 1 (0~32)
6283 12:17:39.966955
6284 12:17:39.969093 ----->DramcWriteLeveling(PI) begin...
6285 12:17:39.969515 ==
6286 12:17:39.972490 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 12:17:39.979229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 12:17:39.979697 ==
6289 12:17:39.982192 Write leveling (Byte 0): 40 => 8
6290 12:17:39.985811 Write leveling (Byte 1): 40 => 8
6291 12:17:39.986329 DramcWriteLeveling(PI) end<-----
6292 12:17:39.986663
6293 12:17:39.988990 ==
6294 12:17:39.992523 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 12:17:39.995286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 12:17:39.995780 ==
6297 12:17:39.999480 [Gating] SW mode calibration
6298 12:17:40.005669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6299 12:17:40.008727 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6300 12:17:40.015557 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6301 12:17:40.019288 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 12:17:40.022400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 12:17:40.029028 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 12:17:40.032177 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 12:17:40.035315 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 12:17:40.042391 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 12:17:40.045153 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 12:17:40.049277 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6309 12:17:40.051883 Total UI for P1: 0, mck2ui 16
6310 12:17:40.055488 best dqsien dly found for B0: ( 0, 14, 24)
6311 12:17:40.059002 Total UI for P1: 0, mck2ui 16
6312 12:17:40.062405 best dqsien dly found for B1: ( 0, 14, 24)
6313 12:17:40.065457 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6314 12:17:40.069134 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6315 12:17:40.069655
6316 12:17:40.075511 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6317 12:17:40.078876 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 12:17:40.079294 [Gating] SW calibration Done
6319 12:17:40.082166 ==
6320 12:17:40.082678 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 12:17:40.089154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 12:17:40.089736 ==
6323 12:17:40.090227 RX Vref Scan: 0
6324 12:17:40.090551
6325 12:17:40.092429 RX Vref 0 -> 0, step: 1
6326 12:17:40.092845
6327 12:17:40.095766 RX Delay -410 -> 252, step: 16
6328 12:17:40.098842 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6329 12:17:40.102298 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6330 12:17:40.109096 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6331 12:17:40.111909 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6332 12:17:40.115373 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6333 12:17:40.119107 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6334 12:17:40.125702 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6335 12:17:40.129226 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6336 12:17:40.132091 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6337 12:17:40.135234 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6338 12:17:40.142571 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6339 12:17:40.145231 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6340 12:17:40.148403 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6341 12:17:40.155271 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6342 12:17:40.158484 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6343 12:17:40.161534 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6344 12:17:40.161954 ==
6345 12:17:40.165411 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 12:17:40.168768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 12:17:40.169282 ==
6348 12:17:40.172402 DQS Delay:
6349 12:17:40.172912 DQS0 = 59, DQS1 = 59
6350 12:17:40.175314 DQM Delay:
6351 12:17:40.175863 DQM0 = 18, DQM1 = 10
6352 12:17:40.178706 DQ Delay:
6353 12:17:40.179212 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6354 12:17:40.181653 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6355 12:17:40.185464 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6356 12:17:40.188075 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6357 12:17:40.188492
6358 12:17:40.188815
6359 12:17:40.189121 ==
6360 12:17:40.191883 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 12:17:40.198669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 12:17:40.199183 ==
6363 12:17:40.199585
6364 12:17:40.199921
6365 12:17:40.200352 TX Vref Scan disable
6366 12:17:40.201919 == TX Byte 0 ==
6367 12:17:40.204940 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6368 12:17:40.208098 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6369 12:17:40.211628 == TX Byte 1 ==
6370 12:17:40.215203 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6371 12:17:40.219088 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6372 12:17:40.221776 ==
6373 12:17:40.222284 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 12:17:40.228363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 12:17:40.228939 ==
6376 12:17:40.229287
6377 12:17:40.229592
6378 12:17:40.231600 TX Vref Scan disable
6379 12:17:40.232014 == TX Byte 0 ==
6380 12:17:40.235140 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6381 12:17:40.241679 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6382 12:17:40.242195 == TX Byte 1 ==
6383 12:17:40.244696 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6384 12:17:40.248479 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6385 12:17:40.252173
6386 12:17:40.252682 [DATLAT]
6387 12:17:40.253011 Freq=400, CH0 RK0
6388 12:17:40.253319
6389 12:17:40.254590 DATLAT Default: 0xf
6390 12:17:40.255005 0, 0xFFFF, sum = 0
6391 12:17:40.258527 1, 0xFFFF, sum = 0
6392 12:17:40.259043 2, 0xFFFF, sum = 0
6393 12:17:40.262118 3, 0xFFFF, sum = 0
6394 12:17:40.262634 4, 0xFFFF, sum = 0
6395 12:17:40.265409 5, 0xFFFF, sum = 0
6396 12:17:40.268396 6, 0xFFFF, sum = 0
6397 12:17:40.268914 7, 0xFFFF, sum = 0
6398 12:17:40.271614 8, 0xFFFF, sum = 0
6399 12:17:40.272034 9, 0xFFFF, sum = 0
6400 12:17:40.274925 10, 0xFFFF, sum = 0
6401 12:17:40.275484 11, 0xFFFF, sum = 0
6402 12:17:40.278113 12, 0xFFFF, sum = 0
6403 12:17:40.278533 13, 0x0, sum = 1
6404 12:17:40.281195 14, 0x0, sum = 2
6405 12:17:40.281613 15, 0x0, sum = 3
6406 12:17:40.284752 16, 0x0, sum = 4
6407 12:17:40.285266 best_step = 14
6408 12:17:40.285596
6409 12:17:40.285903 ==
6410 12:17:40.287758 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 12:17:40.291544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 12:17:40.292066 ==
6413 12:17:40.294853 RX Vref Scan: 1
6414 12:17:40.295361
6415 12:17:40.298023 RX Vref 0 -> 0, step: 1
6416 12:17:40.298534
6417 12:17:40.298860 RX Delay -359 -> 252, step: 8
6418 12:17:40.301439
6419 12:17:40.301966 Set Vref, RX VrefLevel [Byte0]: 63
6420 12:17:40.304206 [Byte1]: 50
6421 12:17:40.310155
6422 12:17:40.310661 Final RX Vref Byte 0 = 63 to rank0
6423 12:17:40.313121 Final RX Vref Byte 1 = 50 to rank0
6424 12:17:40.316875 Final RX Vref Byte 0 = 63 to rank1
6425 12:17:40.319909 Final RX Vref Byte 1 = 50 to rank1==
6426 12:17:40.323831 Dram Type= 6, Freq= 0, CH_0, rank 0
6427 12:17:40.330223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6428 12:17:40.330721 ==
6429 12:17:40.331051 DQS Delay:
6430 12:17:40.333388 DQS0 = 60, DQS1 = 68
6431 12:17:40.333803 DQM Delay:
6432 12:17:40.334131 DQM0 = 14, DQM1 = 13
6433 12:17:40.336542 DQ Delay:
6434 12:17:40.340322 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =8
6435 12:17:40.343673 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6436 12:17:40.344189 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6437 12:17:40.346737 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6438 12:17:40.349913
6439 12:17:40.350427
6440 12:17:40.356762 [DQSOSCAuto] RK0, (LSB)MR18= 0x8886, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6441 12:17:40.360263 CH0 RK0: MR19=C0C, MR18=8886
6442 12:17:40.366583 CH0_RK0: MR19=0xC0C, MR18=0x8886, DQSOSC=392, MR23=63, INC=384, DEC=256
6443 12:17:40.367100 ==
6444 12:17:40.370137 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 12:17:40.373174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 12:17:40.373599 ==
6447 12:17:40.376357 [Gating] SW mode calibration
6448 12:17:40.383347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6449 12:17:40.389912 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6450 12:17:40.393190 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6451 12:17:40.396656 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 12:17:40.402959 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 12:17:40.406786 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 12:17:40.409801 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 12:17:40.416070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 12:17:40.419550 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 12:17:40.423259 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 12:17:40.429485 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6459 12:17:40.429991 Total UI for P1: 0, mck2ui 16
6460 12:17:40.432901 best dqsien dly found for B0: ( 0, 14, 24)
6461 12:17:40.436184 Total UI for P1: 0, mck2ui 16
6462 12:17:40.439440 best dqsien dly found for B1: ( 0, 14, 24)
6463 12:17:40.443473 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6464 12:17:40.449295 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6465 12:17:40.449713
6466 12:17:40.453372 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6467 12:17:40.456357 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 12:17:40.459529 [Gating] SW calibration Done
6469 12:17:40.459949 ==
6470 12:17:40.463190 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 12:17:40.466707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 12:17:40.467232 ==
6473 12:17:40.469642 RX Vref Scan: 0
6474 12:17:40.470156
6475 12:17:40.470489 RX Vref 0 -> 0, step: 1
6476 12:17:40.470801
6477 12:17:40.473263 RX Delay -410 -> 252, step: 16
6478 12:17:40.476623 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6479 12:17:40.482717 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6480 12:17:40.485902 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6481 12:17:40.489628 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6482 12:17:40.492224 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6483 12:17:40.499122 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6484 12:17:40.502421 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6485 12:17:40.505906 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6486 12:17:40.512113 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6487 12:17:40.515329 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6488 12:17:40.519293 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6489 12:17:40.522165 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6490 12:17:40.528869 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6491 12:17:40.532522 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6492 12:17:40.535426 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6493 12:17:40.538912 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6494 12:17:40.539331 ==
6495 12:17:40.542628 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 12:17:40.549216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 12:17:40.549745 ==
6498 12:17:40.550082 DQS Delay:
6499 12:17:40.552013 DQS0 = 59, DQS1 = 59
6500 12:17:40.552433 DQM Delay:
6501 12:17:40.555292 DQM0 = 17, DQM1 = 10
6502 12:17:40.555750 DQ Delay:
6503 12:17:40.558750 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6504 12:17:40.562454 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6505 12:17:40.565548 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6506 12:17:40.568915 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6507 12:17:40.569442
6508 12:17:40.569832
6509 12:17:40.570154 ==
6510 12:17:40.572158 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 12:17:40.575570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 12:17:40.576086 ==
6513 12:17:40.576420
6514 12:17:40.576729
6515 12:17:40.578545 TX Vref Scan disable
6516 12:17:40.578963 == TX Byte 0 ==
6517 12:17:40.585841 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6518 12:17:40.588709 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6519 12:17:40.589129 == TX Byte 1 ==
6520 12:17:40.595363 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6521 12:17:40.598792 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6522 12:17:40.599317 ==
6523 12:17:40.602652 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 12:17:40.605995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 12:17:40.606520 ==
6526 12:17:40.606855
6527 12:17:40.607160
6528 12:17:40.608557 TX Vref Scan disable
6529 12:17:40.608972 == TX Byte 0 ==
6530 12:17:40.615444 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6531 12:17:40.618499 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6532 12:17:40.618922 == TX Byte 1 ==
6533 12:17:40.625183 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6534 12:17:40.628207 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6535 12:17:40.628626
6536 12:17:40.628956 [DATLAT]
6537 12:17:40.631972 Freq=400, CH0 RK1
6538 12:17:40.632391
6539 12:17:40.632722 DATLAT Default: 0xe
6540 12:17:40.635465 0, 0xFFFF, sum = 0
6541 12:17:40.636005 1, 0xFFFF, sum = 0
6542 12:17:40.638541 2, 0xFFFF, sum = 0
6543 12:17:40.639075 3, 0xFFFF, sum = 0
6544 12:17:40.641805 4, 0xFFFF, sum = 0
6545 12:17:40.642326 5, 0xFFFF, sum = 0
6546 12:17:40.645347 6, 0xFFFF, sum = 0
6547 12:17:40.645773 7, 0xFFFF, sum = 0
6548 12:17:40.648651 8, 0xFFFF, sum = 0
6549 12:17:40.649075 9, 0xFFFF, sum = 0
6550 12:17:40.652058 10, 0xFFFF, sum = 0
6551 12:17:40.655241 11, 0xFFFF, sum = 0
6552 12:17:40.655714 12, 0xFFFF, sum = 0
6553 12:17:40.658065 13, 0x0, sum = 1
6554 12:17:40.658490 14, 0x0, sum = 2
6555 12:17:40.658828 15, 0x0, sum = 3
6556 12:17:40.661834 16, 0x0, sum = 4
6557 12:17:40.662353 best_step = 14
6558 12:17:40.662685
6559 12:17:40.665393 ==
6560 12:17:40.665913 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 12:17:40.671923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 12:17:40.672446 ==
6563 12:17:40.672788 RX Vref Scan: 0
6564 12:17:40.673100
6565 12:17:40.675361 RX Vref 0 -> 0, step: 1
6566 12:17:40.675933
6567 12:17:40.678177 RX Delay -359 -> 252, step: 8
6568 12:17:40.684969 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6569 12:17:40.687986 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6570 12:17:40.691535 iDelay=217, Bit 2, Center -56 (-303 ~ 192) 496
6571 12:17:40.695484 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6572 12:17:40.701376 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6573 12:17:40.704539 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6574 12:17:40.708030 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6575 12:17:40.715051 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6576 12:17:40.717894 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6577 12:17:40.721586 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6578 12:17:40.725066 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6579 12:17:40.731135 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6580 12:17:40.734543 iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504
6581 12:17:40.738197 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6582 12:17:40.741291 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6583 12:17:40.748194 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6584 12:17:40.748721 ==
6585 12:17:40.751263 Dram Type= 6, Freq= 0, CH_0, rank 1
6586 12:17:40.754449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 12:17:40.754984 ==
6588 12:17:40.755320 DQS Delay:
6589 12:17:40.757710 DQS0 = 60, DQS1 = 72
6590 12:17:40.758242 DQM Delay:
6591 12:17:40.761223 DQM0 = 11, DQM1 = 17
6592 12:17:40.761749 DQ Delay:
6593 12:17:40.764249 DQ0 =12, DQ1 =16, DQ2 =4, DQ3 =8
6594 12:17:40.767691 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6595 12:17:40.771091 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6596 12:17:40.774273 DQ12 =20, DQ13 =28, DQ14 =28, DQ15 =24
6597 12:17:40.774785
6598 12:17:40.775116
6599 12:17:40.781454 [DQSOSCAuto] RK1, (LSB)MR18= 0xcc7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6600 12:17:40.783984 CH0 RK1: MR19=C0C, MR18=CC7E
6601 12:17:40.790906 CH0_RK1: MR19=0xC0C, MR18=0xCC7E, DQSOSC=384, MR23=63, INC=400, DEC=267
6602 12:17:40.794351 [RxdqsGatingPostProcess] freq 400
6603 12:17:40.800692 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6604 12:17:40.804423 best DQS0 dly(2T, 0.5T) = (0, 10)
6605 12:17:40.807278 best DQS1 dly(2T, 0.5T) = (0, 10)
6606 12:17:40.810694 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6607 12:17:40.811220 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6608 12:17:40.813896 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 12:17:40.817133 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 12:17:40.820638 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 12:17:40.823974 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 12:17:40.827332 Pre-setting of DQS Precalculation
6613 12:17:40.833979 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6614 12:17:40.834498 ==
6615 12:17:40.837597 Dram Type= 6, Freq= 0, CH_1, rank 0
6616 12:17:40.840818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 12:17:40.841334 ==
6618 12:17:40.847661 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6619 12:17:40.851353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6620 12:17:40.853790 [CA 0] Center 36 (8~64) winsize 57
6621 12:17:40.857559 [CA 1] Center 36 (8~64) winsize 57
6622 12:17:40.860480 [CA 2] Center 36 (8~64) winsize 57
6623 12:17:40.863930 [CA 3] Center 36 (8~64) winsize 57
6624 12:17:40.867505 [CA 4] Center 36 (8~64) winsize 57
6625 12:17:40.871307 [CA 5] Center 36 (8~64) winsize 57
6626 12:17:40.871899
6627 12:17:40.873784 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6628 12:17:40.874205
6629 12:17:40.877409 [CATrainingPosCal] consider 1 rank data
6630 12:17:40.880537 u2DelayCellTimex100 = 270/100 ps
6631 12:17:40.883487 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:17:40.887439 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:17:40.893975 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 12:17:40.897543 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 12:17:40.901053 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 12:17:40.904066 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 12:17:40.904590
6638 12:17:40.907046 CA PerBit enable=1, Macro0, CA PI delay=36
6639 12:17:40.907606
6640 12:17:40.910398 [CBTSetCACLKResult] CA Dly = 36
6641 12:17:40.910818 CS Dly: 1 (0~32)
6642 12:17:40.911154 ==
6643 12:17:40.913782 Dram Type= 6, Freq= 0, CH_1, rank 1
6644 12:17:40.920863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 12:17:40.921383 ==
6646 12:17:40.923646 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6647 12:17:40.930688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6648 12:17:40.933712 [CA 0] Center 36 (8~64) winsize 57
6649 12:17:40.937079 [CA 1] Center 36 (8~64) winsize 57
6650 12:17:40.940399 [CA 2] Center 36 (8~64) winsize 57
6651 12:17:40.944038 [CA 3] Center 36 (8~64) winsize 57
6652 12:17:40.947774 [CA 4] Center 36 (8~64) winsize 57
6653 12:17:40.950549 [CA 5] Center 36 (8~64) winsize 57
6654 12:17:40.951089
6655 12:17:40.953564 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6656 12:17:40.953996
6657 12:17:40.956885 [CATrainingPosCal] consider 2 rank data
6658 12:17:40.960518 u2DelayCellTimex100 = 270/100 ps
6659 12:17:40.963508 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 12:17:40.966486 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 12:17:40.970391 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 12:17:40.973565 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 12:17:40.976703 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 12:17:40.983132 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 12:17:40.983748
6666 12:17:40.986770 CA PerBit enable=1, Macro0, CA PI delay=36
6667 12:17:40.987185
6668 12:17:40.989616 [CBTSetCACLKResult] CA Dly = 36
6669 12:17:40.990033 CS Dly: 1 (0~32)
6670 12:17:40.990365
6671 12:17:40.993324 ----->DramcWriteLeveling(PI) begin...
6672 12:17:40.993855 ==
6673 12:17:40.997038 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 12:17:41.003697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 12:17:41.004244 ==
6676 12:17:41.006395 Write leveling (Byte 0): 40 => 8
6677 12:17:41.006920 Write leveling (Byte 1): 40 => 8
6678 12:17:41.009912 DramcWriteLeveling(PI) end<-----
6679 12:17:41.010332
6680 12:17:41.010664 ==
6681 12:17:41.013597 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 12:17:41.019735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 12:17:41.020177 ==
6684 12:17:41.022947 [Gating] SW mode calibration
6685 12:17:41.029530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6686 12:17:41.032692 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6687 12:17:41.039871 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6688 12:17:41.043276 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6689 12:17:41.046006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 12:17:41.053036 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 12:17:41.055959 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 12:17:41.059546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 12:17:41.066313 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 12:17:41.069304 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 12:17:41.072714 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6696 12:17:41.076062 Total UI for P1: 0, mck2ui 16
6697 12:17:41.079539 best dqsien dly found for B0: ( 0, 14, 24)
6698 12:17:41.082993 Total UI for P1: 0, mck2ui 16
6699 12:17:41.085918 best dqsien dly found for B1: ( 0, 14, 24)
6700 12:17:41.089611 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6701 12:17:41.092602 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6702 12:17:41.093027
6703 12:17:41.095860 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6704 12:17:41.103264 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 12:17:41.103879 [Gating] SW calibration Done
6706 12:17:41.104218 ==
6707 12:17:41.106786 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 12:17:41.113063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 12:17:41.113589 ==
6710 12:17:41.113928 RX Vref Scan: 0
6711 12:17:41.114241
6712 12:17:41.115923 RX Vref 0 -> 0, step: 1
6713 12:17:41.116343
6714 12:17:41.119598 RX Delay -410 -> 252, step: 16
6715 12:17:41.122743 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6716 12:17:41.126289 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6717 12:17:41.132654 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6718 12:17:41.135992 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6719 12:17:41.139620 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6720 12:17:41.142529 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6721 12:17:41.148857 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6722 12:17:41.152137 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6723 12:17:41.156028 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6724 12:17:41.159655 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6725 12:17:41.166071 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6726 12:17:41.168741 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6727 12:17:41.172312 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6728 12:17:41.175504 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6729 12:17:41.181836 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6730 12:17:41.185211 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6731 12:17:41.185634 ==
6732 12:17:41.189071 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 12:17:41.191957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 12:17:41.192385 ==
6735 12:17:41.196082 DQS Delay:
6736 12:17:41.196606 DQS0 = 51, DQS1 = 59
6737 12:17:41.198749 DQM Delay:
6738 12:17:41.199165 DQM0 = 12, DQM1 = 11
6739 12:17:41.199540 DQ Delay:
6740 12:17:41.202235 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6741 12:17:41.205460 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6742 12:17:41.209585 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6743 12:17:41.211875 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6744 12:17:41.212291
6745 12:17:41.212621
6746 12:17:41.212927 ==
6747 12:17:41.215660 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 12:17:41.222214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 12:17:41.222736 ==
6750 12:17:41.223074
6751 12:17:41.223381
6752 12:17:41.223722 TX Vref Scan disable
6753 12:17:41.225554 == TX Byte 0 ==
6754 12:17:41.229233 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 12:17:41.231517 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 12:17:41.235486 == TX Byte 1 ==
6757 12:17:41.238678 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6758 12:17:41.242298 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6759 12:17:41.242826 ==
6760 12:17:41.245529 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 12:17:41.251852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 12:17:41.252382 ==
6763 12:17:41.252717
6764 12:17:41.253026
6765 12:17:41.253320 TX Vref Scan disable
6766 12:17:41.255081 == TX Byte 0 ==
6767 12:17:41.258086 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 12:17:41.261946 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 12:17:41.265066 == TX Byte 1 ==
6770 12:17:41.268334 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6771 12:17:41.271767 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6772 12:17:41.272295
6773 12:17:41.274900 [DATLAT]
6774 12:17:41.275484 Freq=400, CH1 RK0
6775 12:17:41.275834
6776 12:17:41.278362 DATLAT Default: 0xf
6777 12:17:41.278884 0, 0xFFFF, sum = 0
6778 12:17:41.281488 1, 0xFFFF, sum = 0
6779 12:17:41.282049 2, 0xFFFF, sum = 0
6780 12:17:41.284781 3, 0xFFFF, sum = 0
6781 12:17:41.285447 4, 0xFFFF, sum = 0
6782 12:17:41.288085 5, 0xFFFF, sum = 0
6783 12:17:41.288509 6, 0xFFFF, sum = 0
6784 12:17:41.291911 7, 0xFFFF, sum = 0
6785 12:17:41.294766 8, 0xFFFF, sum = 0
6786 12:17:41.295295 9, 0xFFFF, sum = 0
6787 12:17:41.297878 10, 0xFFFF, sum = 0
6788 12:17:41.298304 11, 0xFFFF, sum = 0
6789 12:17:41.301064 12, 0xFFFF, sum = 0
6790 12:17:41.301489 13, 0x0, sum = 1
6791 12:17:41.304381 14, 0x0, sum = 2
6792 12:17:41.304808 15, 0x0, sum = 3
6793 12:17:41.308076 16, 0x0, sum = 4
6794 12:17:41.308528 best_step = 14
6795 12:17:41.308863
6796 12:17:41.309172 ==
6797 12:17:41.311118 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 12:17:41.314575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 12:17:41.315105 ==
6800 12:17:41.317350 RX Vref Scan: 1
6801 12:17:41.317768
6802 12:17:41.321198 RX Vref 0 -> 0, step: 1
6803 12:17:41.321616
6804 12:17:41.321945 RX Delay -359 -> 252, step: 8
6805 12:17:41.324697
6806 12:17:41.325228 Set Vref, RX VrefLevel [Byte0]: 57
6807 12:17:41.327699 [Byte1]: 48
6808 12:17:41.333631
6809 12:17:41.334050 Final RX Vref Byte 0 = 57 to rank0
6810 12:17:41.336377 Final RX Vref Byte 1 = 48 to rank0
6811 12:17:41.340043 Final RX Vref Byte 0 = 57 to rank1
6812 12:17:41.343542 Final RX Vref Byte 1 = 48 to rank1==
6813 12:17:41.346749 Dram Type= 6, Freq= 0, CH_1, rank 0
6814 12:17:41.353335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6815 12:17:41.353859 ==
6816 12:17:41.354196 DQS Delay:
6817 12:17:41.356185 DQS0 = 52, DQS1 = 68
6818 12:17:41.356606 DQM Delay:
6819 12:17:41.356938 DQM0 = 9, DQM1 = 14
6820 12:17:41.360350 DQ Delay:
6821 12:17:41.363321 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6822 12:17:41.363891 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6823 12:17:41.366712 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6824 12:17:41.370167 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6825 12:17:41.370692
6826 12:17:41.371027
6827 12:17:41.379961 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6828 12:17:41.382947 CH1 RK0: MR19=C0C, MR18=5E71
6829 12:17:41.389949 CH1_RK0: MR19=0xC0C, MR18=0x5E71, DQSOSC=395, MR23=63, INC=378, DEC=252
6830 12:17:41.390371 ==
6831 12:17:41.393215 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 12:17:41.396282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 12:17:41.396705 ==
6834 12:17:41.400099 [Gating] SW mode calibration
6835 12:17:41.406460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6836 12:17:41.413278 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6837 12:17:41.416089 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6838 12:17:41.419494 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 12:17:41.423284 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 12:17:41.429528 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 12:17:41.432743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 12:17:41.435822 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 12:17:41.443121 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 12:17:41.445643 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 12:17:41.449261 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6846 12:17:41.452920 Total UI for P1: 0, mck2ui 16
6847 12:17:41.456041 best dqsien dly found for B0: ( 0, 14, 24)
6848 12:17:41.459774 Total UI for P1: 0, mck2ui 16
6849 12:17:41.462801 best dqsien dly found for B1: ( 0, 14, 24)
6850 12:17:41.465921 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6851 12:17:41.472494 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6852 12:17:41.473024
6853 12:17:41.475955 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6854 12:17:41.479115 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 12:17:41.482976 [Gating] SW calibration Done
6856 12:17:41.483540 ==
6857 12:17:41.486100 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 12:17:41.489065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 12:17:41.489596 ==
6860 12:17:41.492552 RX Vref Scan: 0
6861 12:17:41.492971
6862 12:17:41.493344 RX Vref 0 -> 0, step: 1
6863 12:17:41.493665
6864 12:17:41.496180 RX Delay -410 -> 252, step: 16
6865 12:17:41.499096 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6866 12:17:41.505739 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6867 12:17:41.509023 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6868 12:17:41.511898 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6869 12:17:41.515680 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6870 12:17:41.522925 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6871 12:17:41.525865 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6872 12:17:41.529283 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6873 12:17:41.531867 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6874 12:17:41.539037 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6875 12:17:41.541892 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6876 12:17:41.545483 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6877 12:17:41.551746 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6878 12:17:41.554818 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6879 12:17:41.558048 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6880 12:17:41.562015 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6881 12:17:41.564940 ==
6882 12:17:41.568013 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 12:17:41.571598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 12:17:41.572038 ==
6885 12:17:41.572371 DQS Delay:
6886 12:17:41.574654 DQS0 = 59, DQS1 = 59
6887 12:17:41.575164 DQM Delay:
6888 12:17:41.578373 DQM0 = 19, DQM1 = 12
6889 12:17:41.578884 DQ Delay:
6890 12:17:41.581502 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6891 12:17:41.584909 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6892 12:17:41.588037 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6893 12:17:41.591811 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6894 12:17:41.592339
6895 12:17:41.592674
6896 12:17:41.592980 ==
6897 12:17:41.594410 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 12:17:41.598186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 12:17:41.598750 ==
6900 12:17:41.599243
6901 12:17:41.599710
6902 12:17:41.600915 TX Vref Scan disable
6903 12:17:41.601331 == TX Byte 0 ==
6904 12:17:41.607965 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6905 12:17:41.611326 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6906 12:17:41.611879 == TX Byte 1 ==
6907 12:17:41.617875 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6908 12:17:41.621495 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6909 12:17:41.622015 ==
6910 12:17:41.624135 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 12:17:41.628265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 12:17:41.628792 ==
6913 12:17:41.629123
6914 12:17:41.629431
6915 12:17:41.631350 TX Vref Scan disable
6916 12:17:41.633949 == TX Byte 0 ==
6917 12:17:41.637933 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6918 12:17:41.640931 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6919 12:17:41.641457 == TX Byte 1 ==
6920 12:17:41.648119 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6921 12:17:41.650868 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6922 12:17:41.651425
6923 12:17:41.651770 [DATLAT]
6924 12:17:41.654256 Freq=400, CH1 RK1
6925 12:17:41.654672
6926 12:17:41.655003 DATLAT Default: 0xe
6927 12:17:41.657521 0, 0xFFFF, sum = 0
6928 12:17:41.658020 1, 0xFFFF, sum = 0
6929 12:17:41.660956 2, 0xFFFF, sum = 0
6930 12:17:41.661481 3, 0xFFFF, sum = 0
6931 12:17:41.663774 4, 0xFFFF, sum = 0
6932 12:17:41.667299 5, 0xFFFF, sum = 0
6933 12:17:41.667787 6, 0xFFFF, sum = 0
6934 12:17:41.670288 7, 0xFFFF, sum = 0
6935 12:17:41.670713 8, 0xFFFF, sum = 0
6936 12:17:41.673653 9, 0xFFFF, sum = 0
6937 12:17:41.674077 10, 0xFFFF, sum = 0
6938 12:17:41.677188 11, 0xFFFF, sum = 0
6939 12:17:41.677612 12, 0xFFFF, sum = 0
6940 12:17:41.680146 13, 0x0, sum = 1
6941 12:17:41.680570 14, 0x0, sum = 2
6942 12:17:41.684019 15, 0x0, sum = 3
6943 12:17:41.684560 16, 0x0, sum = 4
6944 12:17:41.686875 best_step = 14
6945 12:17:41.687450
6946 12:17:41.687898 ==
6947 12:17:41.690012 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 12:17:41.694739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 12:17:41.695440 ==
6950 12:17:41.695807 RX Vref Scan: 0
6951 12:17:41.696477
6952 12:17:41.696827 RX Vref 0 -> 0, step: 1
6953 12:17:41.697134
6954 12:17:41.700313 RX Delay -359 -> 252, step: 8
6955 12:17:41.707506 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6956 12:17:41.711317 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6957 12:17:41.714355 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6958 12:17:41.717997 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6959 12:17:41.724128 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6960 12:17:41.728014 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6961 12:17:41.730848 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6962 12:17:41.737720 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6963 12:17:41.740473 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6964 12:17:41.743712 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6965 12:17:41.747192 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6966 12:17:41.753718 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6967 12:17:41.757416 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6968 12:17:41.760842 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6969 12:17:41.763533 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6970 12:17:41.770683 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6971 12:17:41.771114 ==
6972 12:17:41.774205 Dram Type= 6, Freq= 0, CH_1, rank 1
6973 12:17:41.776934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6974 12:17:41.777416 ==
6975 12:17:41.777759 DQS Delay:
6976 12:17:41.780208 DQS0 = 60, DQS1 = 64
6977 12:17:41.780638 DQM Delay:
6978 12:17:41.783315 DQM0 = 13, DQM1 = 10
6979 12:17:41.783772 DQ Delay:
6980 12:17:41.787106 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6981 12:17:41.790202 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6982 12:17:41.793887 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6983 12:17:41.797582 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6984 12:17:41.798107
6985 12:17:41.798441
6986 12:17:41.803364 [DQSOSCAuto] RK1, (LSB)MR18= 0x7bab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6987 12:17:41.806664 CH1 RK1: MR19=C0C, MR18=7BAB
6988 12:17:41.813293 CH1_RK1: MR19=0xC0C, MR18=0x7BAB, DQSOSC=388, MR23=63, INC=392, DEC=261
6989 12:17:41.816825 [RxdqsGatingPostProcess] freq 400
6990 12:17:41.823625 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6991 12:17:41.827427 best DQS0 dly(2T, 0.5T) = (0, 10)
6992 12:17:41.829651 best DQS1 dly(2T, 0.5T) = (0, 10)
6993 12:17:41.833178 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6994 12:17:41.836162 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6995 12:17:41.836585 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 12:17:41.839590 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 12:17:41.842918 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 12:17:41.846962 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 12:17:41.850050 Pre-setting of DQS Precalculation
7000 12:17:41.856711 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7001 12:17:41.863294 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7002 12:17:41.869809 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7003 12:17:41.870325
7004 12:17:41.870660
7005 12:17:41.873342 [Calibration Summary] 800 Mbps
7006 12:17:41.873858 CH 0, Rank 0
7007 12:17:41.876553 SW Impedance : PASS
7008 12:17:41.879515 DUTY Scan : NO K
7009 12:17:41.880089 ZQ Calibration : PASS
7010 12:17:41.883210 Jitter Meter : NO K
7011 12:17:41.886302 CBT Training : PASS
7012 12:17:41.886727 Write leveling : PASS
7013 12:17:41.889851 RX DQS gating : PASS
7014 12:17:41.893280 RX DQ/DQS(RDDQC) : PASS
7015 12:17:41.893798 TX DQ/DQS : PASS
7016 12:17:41.896743 RX DATLAT : PASS
7017 12:17:41.899469 RX DQ/DQS(Engine): PASS
7018 12:17:41.899893 TX OE : NO K
7019 12:17:41.900226 All Pass.
7020 12:17:41.903265
7021 12:17:41.903823 CH 0, Rank 1
7022 12:17:41.906303 SW Impedance : PASS
7023 12:17:41.906746 DUTY Scan : NO K
7024 12:17:41.910097 ZQ Calibration : PASS
7025 12:17:41.913162 Jitter Meter : NO K
7026 12:17:41.913685 CBT Training : PASS
7027 12:17:41.916949 Write leveling : NO K
7028 12:17:41.917467 RX DQS gating : PASS
7029 12:17:41.919539 RX DQ/DQS(RDDQC) : PASS
7030 12:17:41.922836 TX DQ/DQS : PASS
7031 12:17:41.923354 RX DATLAT : PASS
7032 12:17:41.925966 RX DQ/DQS(Engine): PASS
7033 12:17:41.929630 TX OE : NO K
7034 12:17:41.930149 All Pass.
7035 12:17:41.930489
7036 12:17:41.930802 CH 1, Rank 0
7037 12:17:41.932970 SW Impedance : PASS
7038 12:17:41.936214 DUTY Scan : NO K
7039 12:17:41.936639 ZQ Calibration : PASS
7040 12:17:41.939527 Jitter Meter : NO K
7041 12:17:41.942978 CBT Training : PASS
7042 12:17:41.943544 Write leveling : PASS
7043 12:17:41.946185 RX DQS gating : PASS
7044 12:17:41.949829 RX DQ/DQS(RDDQC) : PASS
7045 12:17:41.950346 TX DQ/DQS : PASS
7046 12:17:41.952560 RX DATLAT : PASS
7047 12:17:41.955980 RX DQ/DQS(Engine): PASS
7048 12:17:41.956415 TX OE : NO K
7049 12:17:41.956750 All Pass.
7050 12:17:41.959281
7051 12:17:41.959774 CH 1, Rank 1
7052 12:17:41.963069 SW Impedance : PASS
7053 12:17:41.963653 DUTY Scan : NO K
7054 12:17:41.966104 ZQ Calibration : PASS
7055 12:17:41.966642 Jitter Meter : NO K
7056 12:17:41.968972 CBT Training : PASS
7057 12:17:41.973319 Write leveling : NO K
7058 12:17:41.973833 RX DQS gating : PASS
7059 12:17:41.975865 RX DQ/DQS(RDDQC) : PASS
7060 12:17:41.979709 TX DQ/DQS : PASS
7061 12:17:41.980284 RX DATLAT : PASS
7062 12:17:41.982353 RX DQ/DQS(Engine): PASS
7063 12:17:41.985246 TX OE : NO K
7064 12:17:41.985633 All Pass.
7065 12:17:41.985957
7066 12:17:41.989102 DramC Write-DBI off
7067 12:17:41.989561 PER_BANK_REFRESH: Hybrid Mode
7068 12:17:41.992783 TX_TRACKING: ON
7069 12:17:42.002763 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7070 12:17:42.005729 [FAST_K] Save calibration result to emmc
7071 12:17:42.008987 dramc_set_vcore_voltage set vcore to 725000
7072 12:17:42.009413 Read voltage for 1600, 0
7073 12:17:42.012783 Vio18 = 0
7074 12:17:42.013299 Vcore = 725000
7075 12:17:42.013636 Vdram = 0
7076 12:17:42.015515 Vddq = 0
7077 12:17:42.015938 Vmddr = 0
7078 12:17:42.021857 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7079 12:17:42.025379 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7080 12:17:42.029392 MEM_TYPE=3, freq_sel=13
7081 12:17:42.031889 sv_algorithm_assistance_LP4_3733
7082 12:17:42.035754 ============ PULL DRAM RESETB DOWN ============
7083 12:17:42.038653 ========== PULL DRAM RESETB DOWN end =========
7084 12:17:42.045860 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7085 12:17:42.048554 ===================================
7086 12:17:42.049082 LPDDR4 DRAM CONFIGURATION
7087 12:17:42.052265 ===================================
7088 12:17:42.055380 EX_ROW_EN[0] = 0x0
7089 12:17:42.058530 EX_ROW_EN[1] = 0x0
7090 12:17:42.058950 LP4Y_EN = 0x0
7091 12:17:42.061794 WORK_FSP = 0x1
7092 12:17:42.062364 WL = 0x5
7093 12:17:42.064813 RL = 0x5
7094 12:17:42.065338 BL = 0x2
7095 12:17:42.068245 RPST = 0x0
7096 12:17:42.068815 RD_PRE = 0x0
7097 12:17:42.071634 WR_PRE = 0x1
7098 12:17:42.072053 WR_PST = 0x1
7099 12:17:42.075232 DBI_WR = 0x0
7100 12:17:42.075783 DBI_RD = 0x0
7101 12:17:42.078112 OTF = 0x1
7102 12:17:42.081404 ===================================
7103 12:17:42.084677 ===================================
7104 12:17:42.085204 ANA top config
7105 12:17:42.088472 ===================================
7106 12:17:42.091510 DLL_ASYNC_EN = 0
7107 12:17:42.094786 ALL_SLAVE_EN = 0
7108 12:17:42.098367 NEW_RANK_MODE = 1
7109 12:17:42.098889 DLL_IDLE_MODE = 1
7110 12:17:42.101891 LP45_APHY_COMB_EN = 1
7111 12:17:42.104901 TX_ODT_DIS = 0
7112 12:17:42.108125 NEW_8X_MODE = 1
7113 12:17:42.111918 ===================================
7114 12:17:42.114721 ===================================
7115 12:17:42.118108 data_rate = 3200
7116 12:17:42.118623 CKR = 1
7117 12:17:42.121307 DQ_P2S_RATIO = 8
7118 12:17:42.124710 ===================================
7119 12:17:42.127785 CA_P2S_RATIO = 8
7120 12:17:42.131600 DQ_CA_OPEN = 0
7121 12:17:42.134687 DQ_SEMI_OPEN = 0
7122 12:17:42.138439 CA_SEMI_OPEN = 0
7123 12:17:42.138959 CA_FULL_RATE = 0
7124 12:17:42.141059 DQ_CKDIV4_EN = 0
7125 12:17:42.144817 CA_CKDIV4_EN = 0
7126 12:17:42.148028 CA_PREDIV_EN = 0
7127 12:17:42.151713 PH8_DLY = 12
7128 12:17:42.154825 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7129 12:17:42.155412 DQ_AAMCK_DIV = 4
7130 12:17:42.158197 CA_AAMCK_DIV = 4
7131 12:17:42.161602 CA_ADMCK_DIV = 4
7132 12:17:42.164581 DQ_TRACK_CA_EN = 0
7133 12:17:42.168011 CA_PICK = 1600
7134 12:17:42.171496 CA_MCKIO = 1600
7135 12:17:42.172010 MCKIO_SEMI = 0
7136 12:17:42.174834 PLL_FREQ = 3068
7137 12:17:42.177553 DQ_UI_PI_RATIO = 32
7138 12:17:42.181253 CA_UI_PI_RATIO = 0
7139 12:17:42.184379 ===================================
7140 12:17:42.187859 ===================================
7141 12:17:42.191110 memory_type:LPDDR4
7142 12:17:42.191578 GP_NUM : 10
7143 12:17:42.194434 SRAM_EN : 1
7144 12:17:42.197787 MD32_EN : 0
7145 12:17:42.201388 ===================================
7146 12:17:42.201908 [ANA_INIT] >>>>>>>>>>>>>>
7147 12:17:42.204201 <<<<<< [CONFIGURE PHASE]: ANA_TX
7148 12:17:42.207358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7149 12:17:42.211045 ===================================
7150 12:17:42.214737 data_rate = 3200,PCW = 0X7600
7151 12:17:42.217839 ===================================
7152 12:17:42.221050 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7153 12:17:42.227495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7154 12:17:42.231251 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 12:17:42.237425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7156 12:17:42.241073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7157 12:17:42.244155 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7158 12:17:42.244676 [ANA_INIT] flow start
7159 12:17:42.247769 [ANA_INIT] PLL >>>>>>>>
7160 12:17:42.250574 [ANA_INIT] PLL <<<<<<<<
7161 12:17:42.254363 [ANA_INIT] MIDPI >>>>>>>>
7162 12:17:42.254882 [ANA_INIT] MIDPI <<<<<<<<
7163 12:17:42.257276 [ANA_INIT] DLL >>>>>>>>
7164 12:17:42.261020 [ANA_INIT] DLL <<<<<<<<
7165 12:17:42.261436 [ANA_INIT] flow end
7166 12:17:42.263857 ============ LP4 DIFF to SE enter ============
7167 12:17:42.271245 ============ LP4 DIFF to SE exit ============
7168 12:17:42.271813 [ANA_INIT] <<<<<<<<<<<<<
7169 12:17:42.273734 [Flow] Enable top DCM control >>>>>
7170 12:17:42.277406 [Flow] Enable top DCM control <<<<<
7171 12:17:42.280701 Enable DLL master slave shuffle
7172 12:17:42.287287 ==============================================================
7173 12:17:42.290467 Gating Mode config
7174 12:17:42.293974 ==============================================================
7175 12:17:42.296734 Config description:
7176 12:17:42.307099 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7177 12:17:42.314472 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7178 12:17:42.317255 SELPH_MODE 0: By rank 1: By Phase
7179 12:17:42.323722 ==============================================================
7180 12:17:42.326988 GAT_TRACK_EN = 1
7181 12:17:42.330247 RX_GATING_MODE = 2
7182 12:17:42.333392 RX_GATING_TRACK_MODE = 2
7183 12:17:42.333946 SELPH_MODE = 1
7184 12:17:42.336577 PICG_EARLY_EN = 1
7185 12:17:42.340011 VALID_LAT_VALUE = 1
7186 12:17:42.347178 ==============================================================
7187 12:17:42.349940 Enter into Gating configuration >>>>
7188 12:17:42.353079 Exit from Gating configuration <<<<
7189 12:17:42.356388 Enter into DVFS_PRE_config >>>>>
7190 12:17:42.366974 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7191 12:17:42.370383 Exit from DVFS_PRE_config <<<<<
7192 12:17:42.373766 Enter into PICG configuration >>>>
7193 12:17:42.376975 Exit from PICG configuration <<<<
7194 12:17:42.380106 [RX_INPUT] configuration >>>>>
7195 12:17:42.383809 [RX_INPUT] configuration <<<<<
7196 12:17:42.387250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7197 12:17:42.393268 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7198 12:17:42.400046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7199 12:17:42.406139 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7200 12:17:42.409869 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7201 12:17:42.416516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7202 12:17:42.423163 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7203 12:17:42.426513 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7204 12:17:42.429461 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7205 12:17:42.432932 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7206 12:17:42.436194 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7207 12:17:42.443366 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7208 12:17:42.445901 ===================================
7209 12:17:42.449515 LPDDR4 DRAM CONFIGURATION
7210 12:17:42.452766 ===================================
7211 12:17:42.453190 EX_ROW_EN[0] = 0x0
7212 12:17:42.456225 EX_ROW_EN[1] = 0x0
7213 12:17:42.456665 LP4Y_EN = 0x0
7214 12:17:42.459302 WORK_FSP = 0x1
7215 12:17:42.459816 WL = 0x5
7216 12:17:42.462672 RL = 0x5
7217 12:17:42.463144 BL = 0x2
7218 12:17:42.466101 RPST = 0x0
7219 12:17:42.466524 RD_PRE = 0x0
7220 12:17:42.469174 WR_PRE = 0x1
7221 12:17:42.469596 WR_PST = 0x1
7222 12:17:42.472252 DBI_WR = 0x0
7223 12:17:42.472671 DBI_RD = 0x0
7224 12:17:42.476077 OTF = 0x1
7225 12:17:42.478985 ===================================
7226 12:17:42.482537 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7227 12:17:42.485679 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7228 12:17:42.492312 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7229 12:17:42.495807 ===================================
7230 12:17:42.498984 LPDDR4 DRAM CONFIGURATION
7231 12:17:42.499636 ===================================
7232 12:17:42.502339 EX_ROW_EN[0] = 0x10
7233 12:17:42.505541 EX_ROW_EN[1] = 0x0
7234 12:17:42.505966 LP4Y_EN = 0x0
7235 12:17:42.508678 WORK_FSP = 0x1
7236 12:17:42.509250 WL = 0x5
7237 12:17:42.512322 RL = 0x5
7238 12:17:42.512744 BL = 0x2
7239 12:17:42.515500 RPST = 0x0
7240 12:17:42.515921 RD_PRE = 0x0
7241 12:17:42.518827 WR_PRE = 0x1
7242 12:17:42.519248 WR_PST = 0x1
7243 12:17:42.522249 DBI_WR = 0x0
7244 12:17:42.522668 DBI_RD = 0x0
7245 12:17:42.525872 OTF = 0x1
7246 12:17:42.529243 ===================================
7247 12:17:42.535761 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7248 12:17:42.536186 ==
7249 12:17:42.539234 Dram Type= 6, Freq= 0, CH_0, rank 0
7250 12:17:42.542757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7251 12:17:42.543288 ==
7252 12:17:42.545757 [Duty_Offset_Calibration]
7253 12:17:42.546301 B0:2 B1:0 CA:3
7254 12:17:42.546640
7255 12:17:42.549144 [DutyScan_Calibration_Flow] k_type=0
7256 12:17:42.560105
7257 12:17:42.560634 ==CLK 0==
7258 12:17:42.563256 Final CLK duty delay cell = 0
7259 12:17:42.566691 [0] MAX Duty = 5031%(X100), DQS PI = 12
7260 12:17:42.569712 [0] MIN Duty = 4875%(X100), DQS PI = 54
7261 12:17:42.573153 [0] AVG Duty = 4953%(X100)
7262 12:17:42.573725
7263 12:17:42.576183 CH0 CLK Duty spec in!! Max-Min= 156%
7264 12:17:42.579967 [DutyScan_Calibration_Flow] ====Done====
7265 12:17:42.580512
7266 12:17:42.583120 [DutyScan_Calibration_Flow] k_type=1
7267 12:17:42.599943
7268 12:17:42.600471 ==DQS 0 ==
7269 12:17:42.603082 Final DQS duty delay cell = 0
7270 12:17:42.606892 [0] MAX Duty = 5094%(X100), DQS PI = 30
7271 12:17:42.609859 [0] MIN Duty = 4875%(X100), DQS PI = 50
7272 12:17:42.613211 [0] AVG Duty = 4984%(X100)
7273 12:17:42.613662
7274 12:17:42.614164 ==DQS 1 ==
7275 12:17:42.616311 Final DQS duty delay cell = 0
7276 12:17:42.619930 [0] MAX Duty = 5156%(X100), DQS PI = 30
7277 12:17:42.623154 [0] MIN Duty = 5031%(X100), DQS PI = 12
7278 12:17:42.626691 [0] AVG Duty = 5093%(X100)
7279 12:17:42.627213
7280 12:17:42.629899 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7281 12:17:42.630504
7282 12:17:42.633025 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7283 12:17:42.636654 [DutyScan_Calibration_Flow] ====Done====
7284 12:17:42.637068
7285 12:17:42.639449 [DutyScan_Calibration_Flow] k_type=3
7286 12:17:42.658335
7287 12:17:42.659101 ==DQM 0 ==
7288 12:17:42.660952 Final DQM duty delay cell = 0
7289 12:17:42.664405 [0] MAX Duty = 5125%(X100), DQS PI = 12
7290 12:17:42.668206 [0] MIN Duty = 4875%(X100), DQS PI = 48
7291 12:17:42.671112 [0] AVG Duty = 5000%(X100)
7292 12:17:42.671666
7293 12:17:42.672012 ==DQM 1 ==
7294 12:17:42.674730 Final DQM duty delay cell = 4
7295 12:17:42.677891 [4] MAX Duty = 5187%(X100), DQS PI = 62
7296 12:17:42.681415 [4] MIN Duty = 5000%(X100), DQS PI = 12
7297 12:17:42.684971 [4] AVG Duty = 5093%(X100)
7298 12:17:42.685489
7299 12:17:42.688110 CH0 DQM 0 Duty spec in!! Max-Min= 250%
7300 12:17:42.688616
7301 12:17:42.691132 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7302 12:17:42.694660 [DutyScan_Calibration_Flow] ====Done====
7303 12:17:42.695096
7304 12:17:42.698194 [DutyScan_Calibration_Flow] k_type=2
7305 12:17:42.715003
7306 12:17:42.715581 ==DQ 0 ==
7307 12:17:42.718111 Final DQ duty delay cell = -4
7308 12:17:42.721101 [-4] MAX Duty = 5000%(X100), DQS PI = 16
7309 12:17:42.724732 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7310 12:17:42.727786 [-4] AVG Duty = 4938%(X100)
7311 12:17:42.728302
7312 12:17:42.728841 ==DQ 1 ==
7313 12:17:42.730730 Final DQ duty delay cell = 0
7314 12:17:42.734186 [0] MAX Duty = 5156%(X100), DQS PI = 60
7315 12:17:42.737669 [0] MIN Duty = 5000%(X100), DQS PI = 16
7316 12:17:42.740916 [0] AVG Duty = 5078%(X100)
7317 12:17:42.741335
7318 12:17:42.744803 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7319 12:17:42.745325
7320 12:17:42.747560 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7321 12:17:42.751131 [DutyScan_Calibration_Flow] ====Done====
7322 12:17:42.751721 ==
7323 12:17:42.754571 Dram Type= 6, Freq= 0, CH_1, rank 0
7324 12:17:42.757780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7325 12:17:42.758389 ==
7326 12:17:42.760859 [Duty_Offset_Calibration]
7327 12:17:42.761278 B0:1 B1:-2 CA:0
7328 12:17:42.761610
7329 12:17:42.764363 [DutyScan_Calibration_Flow] k_type=0
7330 12:17:42.775553
7331 12:17:42.776073 ==CLK 0==
7332 12:17:42.778452 Final CLK duty delay cell = 0
7333 12:17:42.782119 [0] MAX Duty = 5062%(X100), DQS PI = 18
7334 12:17:42.785387 [0] MIN Duty = 4813%(X100), DQS PI = 60
7335 12:17:42.785911 [0] AVG Duty = 4937%(X100)
7336 12:17:42.788323
7337 12:17:42.791564 CH1 CLK Duty spec in!! Max-Min= 249%
7338 12:17:42.794727 [DutyScan_Calibration_Flow] ====Done====
7339 12:17:42.795143
7340 12:17:42.798624 [DutyScan_Calibration_Flow] k_type=1
7341 12:17:42.814311
7342 12:17:42.814844 ==DQS 0 ==
7343 12:17:42.817437 Final DQS duty delay cell = -4
7344 12:17:42.820901 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7345 12:17:42.823865 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7346 12:17:42.826857 [-4] AVG Duty = 4922%(X100)
7347 12:17:42.827286
7348 12:17:42.827695 ==DQS 1 ==
7349 12:17:42.830590 Final DQS duty delay cell = 0
7350 12:17:42.833709 [0] MAX Duty = 5093%(X100), DQS PI = 60
7351 12:17:42.837208 [0] MIN Duty = 4844%(X100), DQS PI = 24
7352 12:17:42.840251 [0] AVG Duty = 4968%(X100)
7353 12:17:42.840673
7354 12:17:42.843882 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7355 12:17:42.844302
7356 12:17:42.846879 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7357 12:17:42.850474 [DutyScan_Calibration_Flow] ====Done====
7358 12:17:42.850893
7359 12:17:42.853900 [DutyScan_Calibration_Flow] k_type=3
7360 12:17:42.870936
7361 12:17:42.871361 ==DQM 0 ==
7362 12:17:42.874283 Final DQM duty delay cell = 0
7363 12:17:42.877807 [0] MAX Duty = 5031%(X100), DQS PI = 24
7364 12:17:42.881448 [0] MIN Duty = 4813%(X100), DQS PI = 56
7365 12:17:42.885169 [0] AVG Duty = 4922%(X100)
7366 12:17:42.885692
7367 12:17:42.886023 ==DQM 1 ==
7368 12:17:42.888142 Final DQM duty delay cell = 0
7369 12:17:42.891088 [0] MAX Duty = 5093%(X100), DQS PI = 36
7370 12:17:42.894500 [0] MIN Duty = 4875%(X100), DQS PI = 26
7371 12:17:42.897793 [0] AVG Duty = 4984%(X100)
7372 12:17:42.898218
7373 12:17:42.900720 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7374 12:17:42.901138
7375 12:17:42.904030 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7376 12:17:42.907649 [DutyScan_Calibration_Flow] ====Done====
7377 12:17:42.908084
7378 12:17:42.910852 [DutyScan_Calibration_Flow] k_type=2
7379 12:17:42.928166
7380 12:17:42.928585 ==DQ 0 ==
7381 12:17:42.931616 Final DQ duty delay cell = 0
7382 12:17:42.935240 [0] MAX Duty = 5093%(X100), DQS PI = 22
7383 12:17:42.938113 [0] MIN Duty = 4907%(X100), DQS PI = 62
7384 12:17:42.938594 [0] AVG Duty = 5000%(X100)
7385 12:17:42.941506
7386 12:17:42.941924 ==DQ 1 ==
7387 12:17:42.944758 Final DQ duty delay cell = 0
7388 12:17:42.948411 [0] MAX Duty = 5125%(X100), DQS PI = 20
7389 12:17:42.951205 [0] MIN Duty = 4969%(X100), DQS PI = 24
7390 12:17:42.951741 [0] AVG Duty = 5047%(X100)
7391 12:17:42.954887
7392 12:17:42.957772 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7393 12:17:42.958235
7394 12:17:42.962161 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7395 12:17:42.964527 [DutyScan_Calibration_Flow] ====Done====
7396 12:17:42.968065 nWR fixed to 30
7397 12:17:42.968506 [ModeRegInit_LP4] CH0 RK0
7398 12:17:42.970860 [ModeRegInit_LP4] CH0 RK1
7399 12:17:42.974109 [ModeRegInit_LP4] CH1 RK0
7400 12:17:42.977625 [ModeRegInit_LP4] CH1 RK1
7401 12:17:42.978044 match AC timing 5
7402 12:17:42.984736 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7403 12:17:42.987496 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7404 12:17:42.990863 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7405 12:17:42.997784 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7406 12:17:43.000861 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7407 12:17:43.001291 [MiockJmeterHQA]
7408 12:17:43.001630
7409 12:17:43.004561 [DramcMiockJmeter] u1RxGatingPI = 0
7410 12:17:43.007460 0 : 4255, 4026
7411 12:17:43.007895 4 : 4365, 4140
7412 12:17:43.010849 8 : 4253, 4027
7413 12:17:43.011276 12 : 4252, 4027
7414 12:17:43.011738 16 : 4253, 4026
7415 12:17:43.014354 20 : 4252, 4027
7416 12:17:43.014781 24 : 4254, 4029
7417 12:17:43.017306 28 : 4253, 4026
7418 12:17:43.017737 32 : 4252, 4027
7419 12:17:43.021153 36 : 4365, 4140
7420 12:17:43.021583 40 : 4255, 4029
7421 12:17:43.024354 44 : 4255, 4029
7422 12:17:43.024789 48 : 4253, 4026
7423 12:17:43.025132 52 : 4363, 4138
7424 12:17:43.027269 56 : 4252, 4027
7425 12:17:43.027736 60 : 4361, 4137
7426 12:17:43.030649 64 : 4251, 4027
7427 12:17:43.031074 68 : 4250, 4027
7428 12:17:43.034285 72 : 4250, 4027
7429 12:17:43.034710 76 : 4252, 4029
7430 12:17:43.037580 80 : 4250, 4026
7431 12:17:43.038008 84 : 4249, 4027
7432 12:17:43.038353 88 : 4363, 4140
7433 12:17:43.041102 92 : 4250, 4027
7434 12:17:43.041528 96 : 4252, 4029
7435 12:17:43.043844 100 : 4250, 4026
7436 12:17:43.044274 104 : 4250, 3698
7437 12:17:43.047138 108 : 4250, 4
7438 12:17:43.047598 112 : 4360, 0
7439 12:17:43.047942 116 : 4363, 0
7440 12:17:43.050568 120 : 4253, 0
7441 12:17:43.050998 124 : 4250, 0
7442 12:17:43.053798 128 : 4363, 0
7443 12:17:43.054293 132 : 4250, 0
7444 12:17:43.054682 136 : 4250, 0
7445 12:17:43.057063 140 : 4250, 0
7446 12:17:43.057648 144 : 4253, 0
7447 12:17:43.060417 148 : 4363, 0
7448 12:17:43.060921 152 : 4250, 0
7449 12:17:43.061328 156 : 4250, 0
7450 12:17:43.064240 160 : 4249, 0
7451 12:17:43.064672 164 : 4361, 0
7452 12:17:43.065061 168 : 4360, 0
7453 12:17:43.067038 172 : 4250, 0
7454 12:17:43.067640 176 : 4250, 0
7455 12:17:43.070501 180 : 4250, 0
7456 12:17:43.071001 184 : 4252, 0
7457 12:17:43.071435 188 : 4250, 0
7458 12:17:43.073814 192 : 4250, 0
7459 12:17:43.074306 196 : 4252, 0
7460 12:17:43.077146 200 : 4360, 0
7461 12:17:43.077635 204 : 4250, 0
7462 12:17:43.078149 208 : 4250, 0
7463 12:17:43.080143 212 : 4249, 0
7464 12:17:43.080682 216 : 4361, 0
7465 12:17:43.083703 220 : 4360, 0
7466 12:17:43.084312 224 : 4250, 0
7467 12:17:43.084759 228 : 4252, 0
7468 12:17:43.087187 232 : 4250, 0
7469 12:17:43.087781 236 : 4252, 1255
7470 12:17:43.090253 240 : 4360, 4137
7471 12:17:43.090679 244 : 4252, 4029
7472 12:17:43.093567 248 : 4250, 4027
7473 12:17:43.093995 252 : 4250, 4027
7474 12:17:43.097058 256 : 4252, 4029
7475 12:17:43.097491 260 : 4250, 4026
7476 12:17:43.097838 264 : 4250, 4027
7477 12:17:43.100148 268 : 4249, 4027
7478 12:17:43.100576 272 : 4252, 4029
7479 12:17:43.103798 276 : 4250, 4026
7480 12:17:43.104225 280 : 4361, 4137
7481 12:17:43.106962 284 : 4360, 4138
7482 12:17:43.107651 288 : 4250, 4027
7483 12:17:43.110326 292 : 4363, 4140
7484 12:17:43.110880 296 : 4360, 4138
7485 12:17:43.113526 300 : 4250, 4027
7486 12:17:43.113952 304 : 4249, 4027
7487 12:17:43.116994 308 : 4252, 4029
7488 12:17:43.117561 312 : 4250, 4026
7489 12:17:43.120360 316 : 4250, 4026
7490 12:17:43.120881 320 : 4249, 4027
7491 12:17:43.121380 324 : 4252, 4029
7492 12:17:43.123481 328 : 4250, 4026
7493 12:17:43.123988 332 : 4361, 4137
7494 12:17:43.126825 336 : 4361, 4138
7495 12:17:43.127249 340 : 4250, 4027
7496 12:17:43.130634 344 : 4363, 4140
7497 12:17:43.131064 348 : 4360, 4138
7498 12:17:43.133885 352 : 4250, 4025
7499 12:17:43.134314 356 : 4250, 2985
7500 12:17:43.136536 360 : 4252, 0
7501 12:17:43.137067
7502 12:17:43.137411 MIOCK jitter meter ch=0
7503 12:17:43.137865
7504 12:17:43.140416 1T = (360-108) = 252 dly cells
7505 12:17:43.146747 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7506 12:17:43.147246 ==
7507 12:17:43.149751 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 12:17:43.154097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 12:17:43.154628 ==
7510 12:17:43.159896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 12:17:43.163655 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 12:17:43.166820 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 12:17:43.173778 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 12:17:43.183727 [CA 0] Center 43 (13~74) winsize 62
7515 12:17:43.186560 [CA 1] Center 43 (13~74) winsize 62
7516 12:17:43.189941 [CA 2] Center 39 (10~68) winsize 59
7517 12:17:43.193114 [CA 3] Center 38 (9~68) winsize 60
7518 12:17:43.196509 [CA 4] Center 36 (7~66) winsize 60
7519 12:17:43.199870 [CA 5] Center 36 (7~66) winsize 60
7520 12:17:43.200399
7521 12:17:43.203205 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7522 12:17:43.203807
7523 12:17:43.206521 [CATrainingPosCal] consider 1 rank data
7524 12:17:43.209851 u2DelayCellTimex100 = 258/100 ps
7525 12:17:43.213272 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7526 12:17:43.220110 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7527 12:17:43.222705 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7528 12:17:43.226434 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7529 12:17:43.229285 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7530 12:17:43.232915 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7531 12:17:43.233425
7532 12:17:43.236460 CA PerBit enable=1, Macro0, CA PI delay=36
7533 12:17:43.236934
7534 12:17:43.239903 [CBTSetCACLKResult] CA Dly = 36
7535 12:17:43.242794 CS Dly: 11 (0~42)
7536 12:17:43.246121 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 12:17:43.249519 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 12:17:43.249944 ==
7539 12:17:43.252693 Dram Type= 6, Freq= 0, CH_0, rank 1
7540 12:17:43.255893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 12:17:43.259534 ==
7542 12:17:43.262723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 12:17:43.266377 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 12:17:43.272665 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 12:17:43.279323 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 12:17:43.287318 [CA 0] Center 44 (14~75) winsize 62
7547 12:17:43.290298 [CA 1] Center 43 (13~74) winsize 62
7548 12:17:43.293347 [CA 2] Center 39 (10~69) winsize 60
7549 12:17:43.297068 [CA 3] Center 39 (10~69) winsize 60
7550 12:17:43.299690 [CA 4] Center 37 (8~67) winsize 60
7551 12:17:43.303416 [CA 5] Center 37 (7~67) winsize 61
7552 12:17:43.303937
7553 12:17:43.306628 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7554 12:17:43.307113
7555 12:17:43.313693 [CATrainingPosCal] consider 2 rank data
7556 12:17:43.314269 u2DelayCellTimex100 = 258/100 ps
7557 12:17:43.316671 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7558 12:17:43.323258 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7559 12:17:43.326792 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7560 12:17:43.329988 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7561 12:17:43.334330 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7562 12:17:43.336665 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7563 12:17:43.337093
7564 12:17:43.339960 CA PerBit enable=1, Macro0, CA PI delay=36
7565 12:17:43.340385
7566 12:17:43.343328 [CBTSetCACLKResult] CA Dly = 36
7567 12:17:43.346429 CS Dly: 11 (0~42)
7568 12:17:43.350172 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 12:17:43.353168 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 12:17:43.353686
7571 12:17:43.356675 ----->DramcWriteLeveling(PI) begin...
7572 12:17:43.357218 ==
7573 12:17:43.359942 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 12:17:43.366419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 12:17:43.366940 ==
7576 12:17:43.370207 Write leveling (Byte 0): 36 => 36
7577 12:17:43.373364 Write leveling (Byte 1): 28 => 28
7578 12:17:43.373892 DramcWriteLeveling(PI) end<-----
7579 12:17:43.376132
7580 12:17:43.376563 ==
7581 12:17:43.379510 Dram Type= 6, Freq= 0, CH_0, rank 0
7582 12:17:43.382892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7583 12:17:43.383316 ==
7584 12:17:43.386348 [Gating] SW mode calibration
7585 12:17:43.392878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7586 12:17:43.399772 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7587 12:17:43.403245 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 12:17:43.405951 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 12:17:43.409382 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7590 12:17:43.416385 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7591 12:17:43.419797 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 0)
7592 12:17:43.422437 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7593 12:17:43.428885 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 12:17:43.432407 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 12:17:43.435519 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 12:17:43.442830 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 12:17:43.445875 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7598 12:17:43.449369 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7599 12:17:43.455276 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
7600 12:17:43.458654 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7601 12:17:43.462384 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7602 12:17:43.469349 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 12:17:43.472040 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 12:17:43.475784 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 12:17:43.482482 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 12:17:43.485056 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 12:17:43.488274 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7608 12:17:43.495057 1 6 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7609 12:17:43.498097 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7610 12:17:43.501876 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:17:43.508365 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 12:17:43.511802 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 12:17:43.514687 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7614 12:17:43.521350 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7615 12:17:43.525010 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7616 12:17:43.528486 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7617 12:17:43.534509 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7618 12:17:43.538001 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 12:17:43.541616 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 12:17:43.548062 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 12:17:43.551244 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 12:17:43.555040 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 12:17:43.561848 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 12:17:43.564903 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 12:17:43.567738 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 12:17:43.574385 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 12:17:43.577500 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 12:17:43.581181 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 12:17:43.587778 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 12:17:43.590822 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7631 12:17:43.594160 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7632 12:17:43.600716 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 12:17:43.601191 Total UI for P1: 0, mck2ui 16
7634 12:17:43.607801 best dqsien dly found for B0: ( 1, 9, 14)
7635 12:17:43.610532 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7636 12:17:43.614008 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 12:17:43.617431 Total UI for P1: 0, mck2ui 16
7638 12:17:43.620361 best dqsien dly found for B1: ( 1, 9, 22)
7639 12:17:43.623773 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7640 12:17:43.627224 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7641 12:17:43.627837
7642 12:17:43.633997 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7643 12:17:43.637330 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7644 12:17:43.640209 [Gating] SW calibration Done
7645 12:17:43.640653 ==
7646 12:17:43.643681 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 12:17:43.647180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 12:17:43.647656 ==
7649 12:17:43.648000 RX Vref Scan: 0
7650 12:17:43.648318
7651 12:17:43.650216 RX Vref 0 -> 0, step: 1
7652 12:17:43.650653
7653 12:17:43.653867 RX Delay 0 -> 252, step: 8
7654 12:17:43.657721 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7655 12:17:43.660759 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7656 12:17:43.666924 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7657 12:17:43.670526 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7658 12:17:43.673781 iDelay=192, Bit 4, Center 131 (80 ~ 183) 104
7659 12:17:43.676960 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7660 12:17:43.680086 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7661 12:17:43.683791 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7662 12:17:43.690117 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7663 12:17:43.694232 iDelay=192, Bit 9, Center 107 (48 ~ 167) 120
7664 12:17:43.697527 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7665 12:17:43.700196 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7666 12:17:43.706827 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7667 12:17:43.709854 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7668 12:17:43.713453 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7669 12:17:43.716923 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7670 12:17:43.717588 ==
7671 12:17:43.719918 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 12:17:43.726551 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 12:17:43.727048 ==
7674 12:17:43.727575 DQS Delay:
7675 12:17:43.727937 DQS0 = 0, DQS1 = 0
7676 12:17:43.729838 DQM Delay:
7677 12:17:43.730329 DQM0 = 128, DQM1 = 122
7678 12:17:43.732912 DQ Delay:
7679 12:17:43.736234 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7680 12:17:43.739672 DQ4 =131, DQ5 =111, DQ6 =139, DQ7 =135
7681 12:17:43.742857 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7682 12:17:43.746683 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
7683 12:17:43.746990
7684 12:17:43.747205
7685 12:17:43.747486 ==
7686 12:17:43.749361 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 12:17:43.752897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 12:17:43.756182 ==
7689 12:17:43.756437
7690 12:17:43.756713
7691 12:17:43.756896 TX Vref Scan disable
7692 12:17:43.759836 == TX Byte 0 ==
7693 12:17:43.762714 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7694 12:17:43.766328 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7695 12:17:43.769304 == TX Byte 1 ==
7696 12:17:43.772745 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7697 12:17:43.776381 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7698 12:17:43.776612 ==
7699 12:17:43.779832 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 12:17:43.785800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 12:17:43.786032 ==
7702 12:17:43.800194
7703 12:17:43.803789 TX Vref early break, caculate TX vref
7704 12:17:43.806936 TX Vref=16, minBit 8, minWin=21, winSum=359
7705 12:17:43.810062 TX Vref=18, minBit 8, minWin=21, winSum=370
7706 12:17:43.813560 TX Vref=20, minBit 4, minWin=23, winSum=381
7707 12:17:43.816820 TX Vref=22, minBit 8, minWin=23, winSum=391
7708 12:17:43.820110 TX Vref=24, minBit 4, minWin=24, winSum=402
7709 12:17:43.826612 TX Vref=26, minBit 9, minWin=24, winSum=404
7710 12:17:43.830297 TX Vref=28, minBit 8, minWin=24, winSum=405
7711 12:17:43.833361 TX Vref=30, minBit 8, minWin=23, winSum=405
7712 12:17:43.836635 TX Vref=32, minBit 0, minWin=24, winSum=397
7713 12:17:43.840307 TX Vref=34, minBit 9, minWin=22, winSum=385
7714 12:17:43.843196 TX Vref=36, minBit 8, minWin=21, winSum=372
7715 12:17:43.850056 [TxChooseVref] Worse bit 8, Min win 24, Win sum 405, Final Vref 28
7716 12:17:43.850375
7717 12:17:43.853139 Final TX Range 0 Vref 28
7718 12:17:43.853382
7719 12:17:43.853618 ==
7720 12:17:43.856993 Dram Type= 6, Freq= 0, CH_0, rank 0
7721 12:17:43.860522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7722 12:17:43.860754 ==
7723 12:17:43.860988
7724 12:17:43.861210
7725 12:17:43.863437 TX Vref Scan disable
7726 12:17:43.870019 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7727 12:17:43.870387 == TX Byte 0 ==
7728 12:17:43.873459 u2DelayCellOfst[0]=11 cells (3 PI)
7729 12:17:43.877008 u2DelayCellOfst[1]=15 cells (4 PI)
7730 12:17:43.879774 u2DelayCellOfst[2]=11 cells (3 PI)
7731 12:17:43.883317 u2DelayCellOfst[3]=11 cells (3 PI)
7732 12:17:43.886616 u2DelayCellOfst[4]=7 cells (2 PI)
7733 12:17:43.889882 u2DelayCellOfst[5]=0 cells (0 PI)
7734 12:17:43.893366 u2DelayCellOfst[6]=15 cells (4 PI)
7735 12:17:43.896691 u2DelayCellOfst[7]=15 cells (4 PI)
7736 12:17:43.899883 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7737 12:17:43.903117 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7738 12:17:43.906501 == TX Byte 1 ==
7739 12:17:43.910127 u2DelayCellOfst[8]=0 cells (0 PI)
7740 12:17:43.913370 u2DelayCellOfst[9]=3 cells (1 PI)
7741 12:17:43.916356 u2DelayCellOfst[10]=7 cells (2 PI)
7742 12:17:43.916773 u2DelayCellOfst[11]=7 cells (2 PI)
7743 12:17:43.919651 u2DelayCellOfst[12]=15 cells (4 PI)
7744 12:17:43.923139 u2DelayCellOfst[13]=11 cells (3 PI)
7745 12:17:43.926133 u2DelayCellOfst[14]=15 cells (4 PI)
7746 12:17:43.929463 u2DelayCellOfst[15]=11 cells (3 PI)
7747 12:17:43.936079 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7748 12:17:43.939556 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7749 12:17:43.940266 DramC Write-DBI on
7750 12:17:43.940641 ==
7751 12:17:43.942796 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 12:17:43.949478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 12:17:43.950105 ==
7754 12:17:43.950886
7755 12:17:43.951440
7756 12:17:43.952074 TX Vref Scan disable
7757 12:17:43.953640 == TX Byte 0 ==
7758 12:17:43.957274 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7759 12:17:43.960584 == TX Byte 1 ==
7760 12:17:43.963767 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7761 12:17:43.966983 DramC Write-DBI off
7762 12:17:43.967441
7763 12:17:43.967788 [DATLAT]
7764 12:17:43.968099 Freq=1600, CH0 RK0
7765 12:17:43.968399
7766 12:17:43.970600 DATLAT Default: 0xf
7767 12:17:43.971137 0, 0xFFFF, sum = 0
7768 12:17:43.973975 1, 0xFFFF, sum = 0
7769 12:17:43.977300 2, 0xFFFF, sum = 0
7770 12:17:43.977731 3, 0xFFFF, sum = 0
7771 12:17:43.980881 4, 0xFFFF, sum = 0
7772 12:17:43.981313 5, 0xFFFF, sum = 0
7773 12:17:43.983763 6, 0xFFFF, sum = 0
7774 12:17:43.984188 7, 0xFFFF, sum = 0
7775 12:17:43.987254 8, 0xFFFF, sum = 0
7776 12:17:43.987824 9, 0xFFFF, sum = 0
7777 12:17:43.990625 10, 0xFFFF, sum = 0
7778 12:17:43.991157 11, 0xFFFF, sum = 0
7779 12:17:43.993734 12, 0xFFFF, sum = 0
7780 12:17:43.994270 13, 0xFFFF, sum = 0
7781 12:17:43.997128 14, 0x0, sum = 1
7782 12:17:43.997555 15, 0x0, sum = 2
7783 12:17:44.000028 16, 0x0, sum = 3
7784 12:17:44.000459 17, 0x0, sum = 4
7785 12:17:44.003822 best_step = 15
7786 12:17:44.004346
7787 12:17:44.004682 ==
7788 12:17:44.006867 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 12:17:44.011104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 12:17:44.011707 ==
7791 12:17:44.014041 RX Vref Scan: 1
7792 12:17:44.014559
7793 12:17:44.014899 Set Vref Range= 24 -> 127
7794 12:17:44.015215
7795 12:17:44.016969 RX Vref 24 -> 127, step: 1
7796 12:17:44.017508
7797 12:17:44.020301 RX Delay 3 -> 252, step: 4
7798 12:17:44.020744
7799 12:17:44.023203 Set Vref, RX VrefLevel [Byte0]: 24
7800 12:17:44.026793 [Byte1]: 24
7801 12:17:44.027232
7802 12:17:44.030282 Set Vref, RX VrefLevel [Byte0]: 25
7803 12:17:44.033283 [Byte1]: 25
7804 12:17:44.036663
7805 12:17:44.037250 Set Vref, RX VrefLevel [Byte0]: 26
7806 12:17:44.040136 [Byte1]: 26
7807 12:17:44.044617
7808 12:17:44.045142 Set Vref, RX VrefLevel [Byte0]: 27
7809 12:17:44.047649 [Byte1]: 27
7810 12:17:44.051810
7811 12:17:44.052252 Set Vref, RX VrefLevel [Byte0]: 28
7812 12:17:44.055147 [Byte1]: 28
7813 12:17:44.059481
7814 12:17:44.060034 Set Vref, RX VrefLevel [Byte0]: 29
7815 12:17:44.062455 [Byte1]: 29
7816 12:17:44.067080
7817 12:17:44.067548 Set Vref, RX VrefLevel [Byte0]: 30
7818 12:17:44.070740 [Byte1]: 30
7819 12:17:44.074633
7820 12:17:44.075156 Set Vref, RX VrefLevel [Byte0]: 31
7821 12:17:44.078354 [Byte1]: 31
7822 12:17:44.082317
7823 12:17:44.082764 Set Vref, RX VrefLevel [Byte0]: 32
7824 12:17:44.085627 [Byte1]: 32
7825 12:17:44.090405
7826 12:17:44.090847 Set Vref, RX VrefLevel [Byte0]: 33
7827 12:17:44.093816 [Byte1]: 33
7828 12:17:44.097812
7829 12:17:44.098263 Set Vref, RX VrefLevel [Byte0]: 34
7830 12:17:44.101153 [Byte1]: 34
7831 12:17:44.105305
7832 12:17:44.105731 Set Vref, RX VrefLevel [Byte0]: 35
7833 12:17:44.108966 [Byte1]: 35
7834 12:17:44.113009
7835 12:17:44.113431 Set Vref, RX VrefLevel [Byte0]: 36
7836 12:17:44.116656 [Byte1]: 36
7837 12:17:44.120649
7838 12:17:44.121068 Set Vref, RX VrefLevel [Byte0]: 37
7839 12:17:44.124235 [Byte1]: 37
7840 12:17:44.128311
7841 12:17:44.128867 Set Vref, RX VrefLevel [Byte0]: 38
7842 12:17:44.131723 [Byte1]: 38
7843 12:17:44.136066
7844 12:17:44.136524 Set Vref, RX VrefLevel [Byte0]: 39
7845 12:17:44.139045 [Byte1]: 39
7846 12:17:44.143783
7847 12:17:44.144205 Set Vref, RX VrefLevel [Byte0]: 40
7848 12:17:44.147204 [Byte1]: 40
7849 12:17:44.151217
7850 12:17:44.151689 Set Vref, RX VrefLevel [Byte0]: 41
7851 12:17:44.154675 [Byte1]: 41
7852 12:17:44.158797
7853 12:17:44.159216 Set Vref, RX VrefLevel [Byte0]: 42
7854 12:17:44.162694 [Byte1]: 42
7855 12:17:44.166604
7856 12:17:44.167026 Set Vref, RX VrefLevel [Byte0]: 43
7857 12:17:44.170095 [Byte1]: 43
7858 12:17:44.174407
7859 12:17:44.174831 Set Vref, RX VrefLevel [Byte0]: 44
7860 12:17:44.177868 [Byte1]: 44
7861 12:17:44.182591
7862 12:17:44.183015 Set Vref, RX VrefLevel [Byte0]: 45
7863 12:17:44.185037 [Byte1]: 45
7864 12:17:44.189406
7865 12:17:44.189828 Set Vref, RX VrefLevel [Byte0]: 46
7866 12:17:44.192896 [Byte1]: 46
7867 12:17:44.197495
7868 12:17:44.197955 Set Vref, RX VrefLevel [Byte0]: 47
7869 12:17:44.200767 [Byte1]: 47
7870 12:17:44.204894
7871 12:17:44.205326 Set Vref, RX VrefLevel [Byte0]: 48
7872 12:17:44.208490 [Byte1]: 48
7873 12:17:44.212318
7874 12:17:44.212798 Set Vref, RX VrefLevel [Byte0]: 49
7875 12:17:44.215993 [Byte1]: 49
7876 12:17:44.220354
7877 12:17:44.220774 Set Vref, RX VrefLevel [Byte0]: 50
7878 12:17:44.223127 [Byte1]: 50
7879 12:17:44.228078
7880 12:17:44.228506 Set Vref, RX VrefLevel [Byte0]: 51
7881 12:17:44.231324 [Byte1]: 51
7882 12:17:44.235683
7883 12:17:44.236110 Set Vref, RX VrefLevel [Byte0]: 52
7884 12:17:44.238710 [Byte1]: 52
7885 12:17:44.243208
7886 12:17:44.243771 Set Vref, RX VrefLevel [Byte0]: 53
7887 12:17:44.246438 [Byte1]: 53
7888 12:17:44.250755
7889 12:17:44.251174 Set Vref, RX VrefLevel [Byte0]: 54
7890 12:17:44.254023 [Byte1]: 54
7891 12:17:44.258209
7892 12:17:44.258629 Set Vref, RX VrefLevel [Byte0]: 55
7893 12:17:44.262004 [Byte1]: 55
7894 12:17:44.265975
7895 12:17:44.266396 Set Vref, RX VrefLevel [Byte0]: 56
7896 12:17:44.269171 [Byte1]: 56
7897 12:17:44.274136
7898 12:17:44.274561 Set Vref, RX VrefLevel [Byte0]: 57
7899 12:17:44.277002 [Byte1]: 57
7900 12:17:44.281808
7901 12:17:44.282231 Set Vref, RX VrefLevel [Byte0]: 58
7902 12:17:44.284358 [Byte1]: 58
7903 12:17:44.288812
7904 12:17:44.289278 Set Vref, RX VrefLevel [Byte0]: 59
7905 12:17:44.292205 [Byte1]: 59
7906 12:17:44.296697
7907 12:17:44.297123 Set Vref, RX VrefLevel [Byte0]: 60
7908 12:17:44.300058 [Byte1]: 60
7909 12:17:44.304631
7910 12:17:44.305050 Set Vref, RX VrefLevel [Byte0]: 61
7911 12:17:44.307562 [Byte1]: 61
7912 12:17:44.312082
7913 12:17:44.312503 Set Vref, RX VrefLevel [Byte0]: 62
7914 12:17:44.315323 [Byte1]: 62
7915 12:17:44.319527
7916 12:17:44.320021 Set Vref, RX VrefLevel [Byte0]: 63
7917 12:17:44.322784 [Byte1]: 63
7918 12:17:44.327320
7919 12:17:44.327816 Set Vref, RX VrefLevel [Byte0]: 64
7920 12:17:44.330708 [Byte1]: 64
7921 12:17:44.334680
7922 12:17:44.335165 Set Vref, RX VrefLevel [Byte0]: 65
7923 12:17:44.338041 [Byte1]: 65
7924 12:17:44.343078
7925 12:17:44.343572 Set Vref, RX VrefLevel [Byte0]: 66
7926 12:17:44.346208 [Byte1]: 66
7927 12:17:44.349952
7928 12:17:44.350557 Set Vref, RX VrefLevel [Byte0]: 67
7929 12:17:44.353607 [Byte1]: 67
7930 12:17:44.357698
7931 12:17:44.358277 Set Vref, RX VrefLevel [Byte0]: 68
7932 12:17:44.361568 [Byte1]: 68
7933 12:17:44.365600
7934 12:17:44.366200 Set Vref, RX VrefLevel [Byte0]: 69
7935 12:17:44.368889 [Byte1]: 69
7936 12:17:44.373488
7937 12:17:44.374009 Set Vref, RX VrefLevel [Byte0]: 70
7938 12:17:44.376811 [Byte1]: 70
7939 12:17:44.380963
7940 12:17:44.381310 Set Vref, RX VrefLevel [Byte0]: 71
7941 12:17:44.383989 [Byte1]: 71
7942 12:17:44.388392
7943 12:17:44.388812 Set Vref, RX VrefLevel [Byte0]: 72
7944 12:17:44.391535 [Byte1]: 72
7945 12:17:44.395882
7946 12:17:44.395966 Set Vref, RX VrefLevel [Byte0]: 73
7947 12:17:44.399603 [Byte1]: 73
7948 12:17:44.403816
7949 12:17:44.403899 Set Vref, RX VrefLevel [Byte0]: 74
7950 12:17:44.406512 [Byte1]: 74
7951 12:17:44.411409
7952 12:17:44.411492 Set Vref, RX VrefLevel [Byte0]: 75
7953 12:17:44.414416 [Byte1]: 75
7954 12:17:44.418669
7955 12:17:44.418778 Final RX Vref Byte 0 = 64 to rank0
7956 12:17:44.421991 Final RX Vref Byte 1 = 57 to rank0
7957 12:17:44.425210 Final RX Vref Byte 0 = 64 to rank1
7958 12:17:44.428417 Final RX Vref Byte 1 = 57 to rank1==
7959 12:17:44.431914 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 12:17:44.439221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 12:17:44.439306 ==
7962 12:17:44.439373 DQS Delay:
7963 12:17:44.439471 DQS0 = 0, DQS1 = 0
7964 12:17:44.442064 DQM Delay:
7965 12:17:44.442146 DQM0 = 126, DQM1 = 119
7966 12:17:44.445609 DQ Delay:
7967 12:17:44.448684 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7968 12:17:44.452142 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7969 12:17:44.455343 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7970 12:17:44.458769 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7971 12:17:44.458878
7972 12:17:44.458971
7973 12:17:44.459061
7974 12:17:44.462334 [DramC_TX_OE_Calibration] TA2
7975 12:17:44.465227 Original DQ_B0 (3 6) =30, OEN = 27
7976 12:17:44.468378 Original DQ_B1 (3 6) =30, OEN = 27
7977 12:17:44.471853 24, 0x0, End_B0=24 End_B1=24
7978 12:17:44.471937 25, 0x0, End_B0=25 End_B1=25
7979 12:17:44.475280 26, 0x0, End_B0=26 End_B1=26
7980 12:17:44.478216 27, 0x0, End_B0=27 End_B1=27
7981 12:17:44.481887 28, 0x0, End_B0=28 End_B1=28
7982 12:17:44.481970 29, 0x0, End_B0=29 End_B1=29
7983 12:17:44.485460 30, 0x0, End_B0=30 End_B1=30
7984 12:17:44.488300 31, 0x4141, End_B0=30 End_B1=30
7985 12:17:44.491586 Byte0 end_step=30 best_step=27
7986 12:17:44.494954 Byte1 end_step=30 best_step=27
7987 12:17:44.498283 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 12:17:44.502007 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 12:17:44.502089
7990 12:17:44.502153
7991 12:17:44.508184 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7992 12:17:44.511925 CH0 RK0: MR19=303, MR18=1414
7993 12:17:44.518522 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
7994 12:17:44.518606
7995 12:17:44.522035 ----->DramcWriteLeveling(PI) begin...
7996 12:17:44.522118 ==
7997 12:17:44.525135 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 12:17:44.528470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 12:17:44.528552 ==
8000 12:17:44.531333 Write leveling (Byte 0): 32 => 32
8001 12:17:44.534879 Write leveling (Byte 1): 28 => 28
8002 12:17:44.537872 DramcWriteLeveling(PI) end<-----
8003 12:17:44.537954
8004 12:17:44.538018 ==
8005 12:17:44.542040 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 12:17:44.544609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 12:17:44.544713 ==
8008 12:17:44.548089 [Gating] SW mode calibration
8009 12:17:44.554838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 12:17:44.561378 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 12:17:44.564721 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 12:17:44.571116 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 12:17:44.574551 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8014 12:17:44.577596 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8015 12:17:44.584792 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8016 12:17:44.587717 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8017 12:17:44.591258 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 12:17:44.597742 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 12:17:44.601343 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 12:17:44.604413 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8021 12:17:44.607661 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8022 12:17:44.614526 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8023 12:17:44.618074 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8024 12:17:44.621007 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8025 12:17:44.627399 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 12:17:44.630763 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 12:17:44.633945 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 12:17:44.641020 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 12:17:44.644149 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8030 12:17:44.647647 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8031 12:17:44.654008 1 6 16 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8032 12:17:44.657370 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 12:17:44.660768 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 12:17:44.667127 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 12:17:44.670714 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 12:17:44.673732 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 12:17:44.680540 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 12:17:44.683952 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8039 12:17:44.686899 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8040 12:17:44.693470 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 12:17:44.697157 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 12:17:44.700104 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 12:17:44.706728 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 12:17:44.710151 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 12:17:44.713383 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 12:17:44.719796 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 12:17:44.723274 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 12:17:44.726959 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:17:44.733559 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:17:44.736390 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:17:44.740130 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:17:44.746843 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:17:44.749703 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 12:17:44.752839 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 12:17:44.759697 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 12:17:44.759780 Total UI for P1: 0, mck2ui 16
8057 12:17:44.766281 best dqsien dly found for B0: ( 1, 9, 10)
8058 12:17:44.769889 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 12:17:44.772761 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 12:17:44.776203 Total UI for P1: 0, mck2ui 16
8061 12:17:44.779516 best dqsien dly found for B1: ( 1, 9, 18)
8062 12:17:44.782754 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8063 12:17:44.786309 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8064 12:17:44.786390
8065 12:17:44.792863 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8066 12:17:44.795793 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8067 12:17:44.799519 [Gating] SW calibration Done
8068 12:17:44.799596 ==
8069 12:17:44.802417 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 12:17:44.805640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 12:17:44.805722 ==
8072 12:17:44.805786 RX Vref Scan: 0
8073 12:17:44.809132
8074 12:17:44.809212 RX Vref 0 -> 0, step: 1
8075 12:17:44.809278
8076 12:17:44.812479 RX Delay 0 -> 252, step: 8
8077 12:17:44.815920 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8078 12:17:44.819008 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8079 12:17:44.825934 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8080 12:17:44.829025 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8081 12:17:44.831973 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8082 12:17:44.835490 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8083 12:17:44.838742 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8084 12:17:44.845370 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8085 12:17:44.849123 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8086 12:17:44.851974 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8087 12:17:44.855299 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8088 12:17:44.858915 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8089 12:17:44.865445 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8090 12:17:44.868889 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8091 12:17:44.872291 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8092 12:17:44.875302 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8093 12:17:44.875449 ==
8094 12:17:44.878663 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 12:17:44.885186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 12:17:44.885268 ==
8097 12:17:44.885333 DQS Delay:
8098 12:17:44.888544 DQS0 = 0, DQS1 = 0
8099 12:17:44.888628 DQM Delay:
8100 12:17:44.891647 DQM0 = 127, DQM1 = 121
8101 12:17:44.891738 DQ Delay:
8102 12:17:44.895246 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8103 12:17:44.898473 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8104 12:17:44.901922 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8105 12:17:44.905517 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8106 12:17:44.905648
8107 12:17:44.905739
8108 12:17:44.905821 ==
8109 12:17:44.908450 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 12:17:44.915153 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 12:17:44.915277 ==
8112 12:17:44.915374
8113 12:17:44.915483
8114 12:17:44.915578 TX Vref Scan disable
8115 12:17:44.918274 == TX Byte 0 ==
8116 12:17:44.921884 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8117 12:17:44.925454 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8118 12:17:44.928592 == TX Byte 1 ==
8119 12:17:44.931474 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8120 12:17:44.938852 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8121 12:17:44.939094 ==
8122 12:17:44.941758 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 12:17:44.945036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 12:17:44.945355 ==
8125 12:17:44.958722
8126 12:17:44.962190 TX Vref early break, caculate TX vref
8127 12:17:44.965834 TX Vref=16, minBit 8, minWin=21, winSum=364
8128 12:17:44.968683 TX Vref=18, minBit 8, minWin=22, winSum=373
8129 12:17:44.972444 TX Vref=20, minBit 8, minWin=22, winSum=377
8130 12:17:44.975713 TX Vref=22, minBit 1, minWin=23, winSum=386
8131 12:17:44.978983 TX Vref=24, minBit 8, minWin=24, winSum=401
8132 12:17:44.985779 TX Vref=26, minBit 8, minWin=24, winSum=407
8133 12:17:44.989051 TX Vref=28, minBit 3, minWin=24, winSum=408
8134 12:17:44.991918 TX Vref=30, minBit 8, minWin=23, winSum=402
8135 12:17:44.995198 TX Vref=32, minBit 8, minWin=23, winSum=395
8136 12:17:44.998662 TX Vref=34, minBit 8, minWin=22, winSum=389
8137 12:17:45.002190 TX Vref=36, minBit 8, minWin=22, winSum=378
8138 12:17:45.008830 [TxChooseVref] Worse bit 3, Min win 24, Win sum 408, Final Vref 28
8139 12:17:45.009255
8140 12:17:45.012204 Final TX Range 0 Vref 28
8141 12:17:45.012628
8142 12:17:45.012966 ==
8143 12:17:45.015764 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 12:17:45.018572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 12:17:45.019150 ==
8146 12:17:45.019615
8147 12:17:45.019933
8148 12:17:45.021959 TX Vref Scan disable
8149 12:17:45.028978 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8150 12:17:45.029584 == TX Byte 0 ==
8151 12:17:45.031769 u2DelayCellOfst[0]=11 cells (3 PI)
8152 12:17:45.035072 u2DelayCellOfst[1]=18 cells (5 PI)
8153 12:17:45.039068 u2DelayCellOfst[2]=11 cells (3 PI)
8154 12:17:45.042128 u2DelayCellOfst[3]=11 cells (3 PI)
8155 12:17:45.045170 u2DelayCellOfst[4]=3 cells (1 PI)
8156 12:17:45.048906 u2DelayCellOfst[5]=0 cells (0 PI)
8157 12:17:45.052143 u2DelayCellOfst[6]=18 cells (5 PI)
8158 12:17:45.055043 u2DelayCellOfst[7]=18 cells (5 PI)
8159 12:17:45.058516 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8160 12:17:45.061896 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8161 12:17:45.065818 == TX Byte 1 ==
8162 12:17:45.068246 u2DelayCellOfst[8]=0 cells (0 PI)
8163 12:17:45.068848 u2DelayCellOfst[9]=0 cells (0 PI)
8164 12:17:45.071744 u2DelayCellOfst[10]=7 cells (2 PI)
8165 12:17:45.075286 u2DelayCellOfst[11]=7 cells (2 PI)
8166 12:17:45.078500 u2DelayCellOfst[12]=11 cells (3 PI)
8167 12:17:45.081525 u2DelayCellOfst[13]=11 cells (3 PI)
8168 12:17:45.084854 u2DelayCellOfst[14]=15 cells (4 PI)
8169 12:17:45.088336 u2DelayCellOfst[15]=11 cells (3 PI)
8170 12:17:45.091628 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8171 12:17:45.098488 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8172 12:17:45.098729 DramC Write-DBI on
8173 12:17:45.098913 ==
8174 12:17:45.101757 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 12:17:45.107843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 12:17:45.108104 ==
8177 12:17:45.108345
8178 12:17:45.108620
8179 12:17:45.108889 TX Vref Scan disable
8180 12:17:45.111827 == TX Byte 0 ==
8181 12:17:45.115253 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8182 12:17:45.118920 == TX Byte 1 ==
8183 12:17:45.122414 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8184 12:17:45.125346 DramC Write-DBI off
8185 12:17:45.125964
8186 12:17:45.126540 [DATLAT]
8187 12:17:45.126973 Freq=1600, CH0 RK1
8188 12:17:45.127510
8189 12:17:45.128911 DATLAT Default: 0xf
8190 12:17:45.129347 0, 0xFFFF, sum = 0
8191 12:17:45.132558 1, 0xFFFF, sum = 0
8192 12:17:45.132988 2, 0xFFFF, sum = 0
8193 12:17:45.135810 3, 0xFFFF, sum = 0
8194 12:17:45.138781 4, 0xFFFF, sum = 0
8195 12:17:45.139345 5, 0xFFFF, sum = 0
8196 12:17:45.142348 6, 0xFFFF, sum = 0
8197 12:17:45.142777 7, 0xFFFF, sum = 0
8198 12:17:45.145389 8, 0xFFFF, sum = 0
8199 12:17:45.145982 9, 0xFFFF, sum = 0
8200 12:17:45.149006 10, 0xFFFF, sum = 0
8201 12:17:45.149508 11, 0xFFFF, sum = 0
8202 12:17:45.152051 12, 0xFFFF, sum = 0
8203 12:17:45.152523 13, 0xCFFF, sum = 0
8204 12:17:45.155843 14, 0x0, sum = 1
8205 12:17:45.156352 15, 0x0, sum = 2
8206 12:17:45.158926 16, 0x0, sum = 3
8207 12:17:45.159356 17, 0x0, sum = 4
8208 12:17:45.162354 best_step = 15
8209 12:17:45.162872
8210 12:17:45.163367 ==
8211 12:17:45.165629 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 12:17:45.168817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 12:17:45.169459 ==
8214 12:17:45.169972 RX Vref Scan: 0
8215 12:17:45.172414
8216 12:17:45.172869 RX Vref 0 -> 0, step: 1
8217 12:17:45.173394
8218 12:17:45.175211 RX Delay 3 -> 252, step: 4
8219 12:17:45.178561 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8220 12:17:45.185207 iDelay=191, Bit 1, Center 126 (75 ~ 178) 104
8221 12:17:45.188795 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8222 12:17:45.191895 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8223 12:17:45.195617 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8224 12:17:45.198669 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8225 12:17:45.205926 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8226 12:17:45.208892 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8227 12:17:45.212089 iDelay=191, Bit 8, Center 112 (55 ~ 170) 116
8228 12:17:45.216005 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8229 12:17:45.218757 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8230 12:17:45.225483 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8231 12:17:45.228434 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8232 12:17:45.231997 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8233 12:17:45.235274 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8234 12:17:45.238823 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8235 12:17:45.241578 ==
8236 12:17:45.245338 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 12:17:45.248179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 12:17:45.248620 ==
8239 12:17:45.249062 DQS Delay:
8240 12:17:45.251780 DQS0 = 0, DQS1 = 0
8241 12:17:45.252215 DQM Delay:
8242 12:17:45.255261 DQM0 = 124, DQM1 = 118
8243 12:17:45.255751 DQ Delay:
8244 12:17:45.258313 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8245 12:17:45.261431 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8246 12:17:45.264710 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
8247 12:17:45.268002 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8248 12:17:45.268442
8249 12:17:45.268892
8250 12:17:45.269311
8251 12:17:45.271508 [DramC_TX_OE_Calibration] TA2
8252 12:17:45.274812 Original DQ_B0 (3 6) =30, OEN = 27
8253 12:17:45.277961 Original DQ_B1 (3 6) =30, OEN = 27
8254 12:17:45.281734 24, 0x0, End_B0=24 End_B1=24
8255 12:17:45.284656 25, 0x0, End_B0=25 End_B1=25
8256 12:17:45.285086 26, 0x0, End_B0=26 End_B1=26
8257 12:17:45.288242 27, 0x0, End_B0=27 End_B1=27
8258 12:17:45.291646 28, 0x0, End_B0=28 End_B1=28
8259 12:17:45.294757 29, 0x0, End_B0=29 End_B1=29
8260 12:17:45.298287 30, 0x0, End_B0=30 End_B1=30
8261 12:17:45.298733 31, 0x4141, End_B0=30 End_B1=30
8262 12:17:45.301090 Byte0 end_step=30 best_step=27
8263 12:17:45.304335 Byte1 end_step=30 best_step=27
8264 12:17:45.308029 Byte0 TX OE(2T, 0.5T) = (3, 3)
8265 12:17:45.311696 Byte1 TX OE(2T, 0.5T) = (3, 3)
8266 12:17:45.312121
8267 12:17:45.312457
8268 12:17:45.318005 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8269 12:17:45.321400 CH0 RK1: MR19=303, MR18=220F
8270 12:17:45.327892 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8271 12:17:45.331074 [RxdqsGatingPostProcess] freq 1600
8272 12:17:45.337669 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8273 12:17:45.341318 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 12:17:45.341761 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 12:17:45.343972 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 12:17:45.347496 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 12:17:45.350531 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 12:17:45.353914 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 12:17:45.357438 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 12:17:45.360698 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 12:17:45.363998 Pre-setting of DQS Precalculation
8282 12:17:45.367693 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8283 12:17:45.370652 ==
8284 12:17:45.374052 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 12:17:45.377245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 12:17:45.377843 ==
8287 12:17:45.380458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 12:17:45.387155 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 12:17:45.390375 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 12:17:45.396808 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 12:17:45.405042 [CA 0] Center 42 (13~71) winsize 59
8292 12:17:45.409035 [CA 1] Center 42 (13~72) winsize 60
8293 12:17:45.412057 [CA 2] Center 37 (9~66) winsize 58
8294 12:17:45.415658 [CA 3] Center 36 (7~66) winsize 60
8295 12:17:45.418661 [CA 4] Center 37 (8~66) winsize 59
8296 12:17:45.421715 [CA 5] Center 36 (7~66) winsize 60
8297 12:17:45.422130
8298 12:17:45.425122 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8299 12:17:45.425541
8300 12:17:45.428176 [CATrainingPosCal] consider 1 rank data
8301 12:17:45.431882 u2DelayCellTimex100 = 258/100 ps
8302 12:17:45.435124 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8303 12:17:45.441556 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8304 12:17:45.444871 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8305 12:17:45.448561 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8306 12:17:45.451987 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8307 12:17:45.455318 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 12:17:45.455656
8309 12:17:45.458353 CA PerBit enable=1, Macro0, CA PI delay=36
8310 12:17:45.458673
8311 12:17:45.461428 [CBTSetCACLKResult] CA Dly = 36
8312 12:17:45.465402 CS Dly: 9 (0~40)
8313 12:17:45.467941 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 12:17:45.471298 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 12:17:45.471606 ==
8316 12:17:45.475059 Dram Type= 6, Freq= 0, CH_1, rank 1
8317 12:17:45.478199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 12:17:45.481246 ==
8319 12:17:45.484854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 12:17:45.488097 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 12:17:45.494547 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 12:17:45.501102 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 12:17:45.508338 [CA 0] Center 42 (13~71) winsize 59
8324 12:17:45.511624 [CA 1] Center 42 (12~72) winsize 61
8325 12:17:45.514976 [CA 2] Center 37 (8~67) winsize 60
8326 12:17:45.518598 [CA 3] Center 36 (7~66) winsize 60
8327 12:17:45.522111 [CA 4] Center 38 (8~68) winsize 61
8328 12:17:45.525158 [CA 5] Center 36 (7~66) winsize 60
8329 12:17:45.525512
8330 12:17:45.529058 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8331 12:17:45.529517
8332 12:17:45.531754 [CATrainingPosCal] consider 2 rank data
8333 12:17:45.534638 u2DelayCellTimex100 = 258/100 ps
8334 12:17:45.538324 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8335 12:17:45.545037 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8336 12:17:45.548431 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8337 12:17:45.551295 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8338 12:17:45.555472 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8339 12:17:45.558685 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 12:17:45.559209
8341 12:17:45.561280 CA PerBit enable=1, Macro0, CA PI delay=36
8342 12:17:45.561724
8343 12:17:45.564852 [CBTSetCACLKResult] CA Dly = 36
8344 12:17:45.568382 CS Dly: 10 (0~42)
8345 12:17:45.571743 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 12:17:45.574447 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 12:17:45.574801
8348 12:17:45.578044 ----->DramcWriteLeveling(PI) begin...
8349 12:17:45.578402 ==
8350 12:17:45.581593 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 12:17:45.587919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 12:17:45.588280 ==
8353 12:17:45.591207 Write leveling (Byte 0): 25 => 25
8354 12:17:45.591597 Write leveling (Byte 1): 28 => 28
8355 12:17:45.594629 DramcWriteLeveling(PI) end<-----
8356 12:17:45.594980
8357 12:17:45.595259 ==
8358 12:17:45.598056 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 12:17:45.604521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 12:17:45.604859 ==
8361 12:17:45.608108 [Gating] SW mode calibration
8362 12:17:45.614438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8363 12:17:45.617671 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8364 12:17:45.624292 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 12:17:45.627578 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 12:17:45.631030 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 12:17:45.637307 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 12:17:45.640592 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8369 12:17:45.644323 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 12:17:45.650699 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 12:17:45.654050 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 12:17:45.657419 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 12:17:45.664116 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 12:17:45.667327 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 12:17:45.670701 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8376 12:17:45.677146 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8377 12:17:45.680356 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8378 12:17:45.683849 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 12:17:45.687267 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 12:17:45.693482 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 12:17:45.697514 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 12:17:45.703547 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 12:17:45.706738 1 6 12 | B1->B0 | 2d2d 2525 | 0 1 | (0 0) (0 0)
8384 12:17:45.710020 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 12:17:45.716908 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 12:17:45.720311 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 12:17:45.724299 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 12:17:45.727331 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 12:17:45.733396 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 12:17:45.736757 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 12:17:45.740031 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8392 12:17:45.746714 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8393 12:17:45.750197 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8394 12:17:45.753554 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 12:17:45.759930 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 12:17:45.763318 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 12:17:45.766586 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 12:17:45.773360 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 12:17:45.776451 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 12:17:45.779740 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:17:45.786273 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:17:45.789322 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:17:45.792974 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:17:45.799326 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:17:45.802925 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:17:45.805933 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:17:45.812460 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:17:45.815608 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8409 12:17:45.819612 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8410 12:17:45.822914 Total UI for P1: 0, mck2ui 16
8411 12:17:45.825857 best dqsien dly found for B1: ( 1, 9, 16)
8412 12:17:45.833313 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 12:17:45.836523 Total UI for P1: 0, mck2ui 16
8414 12:17:45.839285 best dqsien dly found for B0: ( 1, 9, 18)
8415 12:17:45.843126 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
8416 12:17:45.846068 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8417 12:17:45.846486
8418 12:17:45.850081 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
8419 12:17:45.852817 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8420 12:17:45.855877 [Gating] SW calibration Done
8421 12:17:45.856298 ==
8422 12:17:45.859069 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 12:17:45.862574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 12:17:45.863096 ==
8425 12:17:45.866269 RX Vref Scan: 0
8426 12:17:45.866785
8427 12:17:45.869875 RX Vref 0 -> 0, step: 1
8428 12:17:45.870390
8429 12:17:45.870727 RX Delay 0 -> 252, step: 8
8430 12:17:45.875922 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8431 12:17:45.878964 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8432 12:17:45.882208 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8433 12:17:45.885506 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8434 12:17:45.888883 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8435 12:17:45.895312 iDelay=208, Bit 5, Center 143 (80 ~ 207) 128
8436 12:17:45.899481 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8437 12:17:45.902200 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8438 12:17:45.905842 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8439 12:17:45.909270 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8440 12:17:45.915559 iDelay=208, Bit 10, Center 127 (80 ~ 175) 96
8441 12:17:45.919022 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8442 12:17:45.922273 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8443 12:17:45.925050 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8444 12:17:45.931654 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8445 12:17:45.935529 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8446 12:17:45.935953 ==
8447 12:17:45.938778 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 12:17:45.942329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 12:17:45.942853 ==
8450 12:17:45.943189 DQS Delay:
8451 12:17:45.945056 DQS0 = 0, DQS1 = 0
8452 12:17:45.945474 DQM Delay:
8453 12:17:45.948327 DQM0 = 132, DQM1 = 126
8454 12:17:45.948748 DQ Delay:
8455 12:17:45.952067 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8456 12:17:45.954665 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8457 12:17:45.958138 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8458 12:17:45.965419 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8459 12:17:45.965935
8460 12:17:45.966274
8461 12:17:45.966577 ==
8462 12:17:45.968004 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 12:17:45.971342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 12:17:45.971813 ==
8465 12:17:45.972147
8466 12:17:45.972453
8467 12:17:45.975577 TX Vref Scan disable
8468 12:17:45.976111 == TX Byte 0 ==
8469 12:17:45.981403 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8470 12:17:45.985050 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8471 12:17:45.985566 == TX Byte 1 ==
8472 12:17:45.991631 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8473 12:17:45.994878 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8474 12:17:45.995419 ==
8475 12:17:45.997919 Dram Type= 6, Freq= 0, CH_1, rank 0
8476 12:17:46.001254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8477 12:17:46.001773 ==
8478 12:17:46.016341
8479 12:17:46.019784 TX Vref early break, caculate TX vref
8480 12:17:46.022855 TX Vref=16, minBit 10, minWin=21, winSum=361
8481 12:17:46.026478 TX Vref=18, minBit 11, minWin=22, winSum=372
8482 12:17:46.029714 TX Vref=20, minBit 10, minWin=22, winSum=378
8483 12:17:46.033034 TX Vref=22, minBit 10, minWin=23, winSum=391
8484 12:17:46.036018 TX Vref=24, minBit 1, minWin=24, winSum=403
8485 12:17:46.042962 TX Vref=26, minBit 1, minWin=25, winSum=412
8486 12:17:46.045990 TX Vref=28, minBit 0, minWin=24, winSum=416
8487 12:17:46.049550 TX Vref=30, minBit 6, minWin=24, winSum=414
8488 12:17:46.053004 TX Vref=32, minBit 0, minWin=24, winSum=407
8489 12:17:46.056357 TX Vref=34, minBit 0, minWin=23, winSum=398
8490 12:17:46.062823 TX Vref=36, minBit 0, minWin=23, winSum=388
8491 12:17:46.066360 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 26
8492 12:17:46.066926
8493 12:17:46.069967 Final TX Range 0 Vref 26
8494 12:17:46.070530
8495 12:17:46.070900 ==
8496 12:17:46.073061 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 12:17:46.075747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 12:17:46.076216 ==
8499 12:17:46.079483
8500 12:17:46.079918
8501 12:17:46.080251 TX Vref Scan disable
8502 12:17:46.086228 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8503 12:17:46.086743 == TX Byte 0 ==
8504 12:17:46.089170 u2DelayCellOfst[0]=22 cells (6 PI)
8505 12:17:46.092472 u2DelayCellOfst[1]=15 cells (4 PI)
8506 12:17:46.096321 u2DelayCellOfst[2]=0 cells (0 PI)
8507 12:17:46.098857 u2DelayCellOfst[3]=7 cells (2 PI)
8508 12:17:46.102668 u2DelayCellOfst[4]=11 cells (3 PI)
8509 12:17:46.105782 u2DelayCellOfst[5]=22 cells (6 PI)
8510 12:17:46.109423 u2DelayCellOfst[6]=22 cells (6 PI)
8511 12:17:46.112275 u2DelayCellOfst[7]=7 cells (2 PI)
8512 12:17:46.115652 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8513 12:17:46.119234 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8514 12:17:46.122785 == TX Byte 1 ==
8515 12:17:46.125948 u2DelayCellOfst[8]=0 cells (0 PI)
8516 12:17:46.129520 u2DelayCellOfst[9]=3 cells (1 PI)
8517 12:17:46.132615 u2DelayCellOfst[10]=11 cells (3 PI)
8518 12:17:46.135570 u2DelayCellOfst[11]=7 cells (2 PI)
8519 12:17:46.136028 u2DelayCellOfst[12]=15 cells (4 PI)
8520 12:17:46.139227 u2DelayCellOfst[13]=18 cells (5 PI)
8521 12:17:46.142146 u2DelayCellOfst[14]=18 cells (5 PI)
8522 12:17:46.145452 u2DelayCellOfst[15]=22 cells (6 PI)
8523 12:17:46.152334 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8524 12:17:46.155714 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8525 12:17:46.156155 DramC Write-DBI on
8526 12:17:46.159101 ==
8527 12:17:46.159709 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 12:17:46.165451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 12:17:46.165867 ==
8530 12:17:46.166193
8531 12:17:46.166494
8532 12:17:46.168410 TX Vref Scan disable
8533 12:17:46.168826 == TX Byte 0 ==
8534 12:17:46.175280 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8535 12:17:46.175834 == TX Byte 1 ==
8536 12:17:46.178835 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8537 12:17:46.181781 DramC Write-DBI off
8538 12:17:46.182193
8539 12:17:46.182517 [DATLAT]
8540 12:17:46.185168 Freq=1600, CH1 RK0
8541 12:17:46.185727
8542 12:17:46.186066 DATLAT Default: 0xf
8543 12:17:46.188525 0, 0xFFFF, sum = 0
8544 12:17:46.189236 1, 0xFFFF, sum = 0
8545 12:17:46.191999 2, 0xFFFF, sum = 0
8546 12:17:46.192419 3, 0xFFFF, sum = 0
8547 12:17:46.195024 4, 0xFFFF, sum = 0
8548 12:17:46.195793 5, 0xFFFF, sum = 0
8549 12:17:46.198349 6, 0xFFFF, sum = 0
8550 12:17:46.198769 7, 0xFFFF, sum = 0
8551 12:17:46.201913 8, 0xFFFF, sum = 0
8552 12:17:46.202386 9, 0xFFFF, sum = 0
8553 12:17:46.205119 10, 0xFFFF, sum = 0
8554 12:17:46.208184 11, 0xFFFF, sum = 0
8555 12:17:46.208882 12, 0xFFFF, sum = 0
8556 12:17:46.211735 13, 0x8FFF, sum = 0
8557 12:17:46.212182 14, 0x0, sum = 1
8558 12:17:46.214870 15, 0x0, sum = 2
8559 12:17:46.215633 16, 0x0, sum = 3
8560 12:17:46.218173 17, 0x0, sum = 4
8561 12:17:46.218592 best_step = 15
8562 12:17:46.219036
8563 12:17:46.219533 ==
8564 12:17:46.221646 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 12:17:46.224885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 12:17:46.225350 ==
8567 12:17:46.228049 RX Vref Scan: 1
8568 12:17:46.228463
8569 12:17:46.231927 Set Vref Range= 24 -> 127
8570 12:17:46.232341
8571 12:17:46.232666 RX Vref 24 -> 127, step: 1
8572 12:17:46.232975
8573 12:17:46.235074 RX Delay 11 -> 252, step: 4
8574 12:17:46.235547
8575 12:17:46.238824 Set Vref, RX VrefLevel [Byte0]: 24
8576 12:17:46.241707 [Byte1]: 24
8577 12:17:46.245624
8578 12:17:46.246141 Set Vref, RX VrefLevel [Byte0]: 25
8579 12:17:46.248693 [Byte1]: 25
8580 12:17:46.252506
8581 12:17:46.252919 Set Vref, RX VrefLevel [Byte0]: 26
8582 12:17:46.256133 [Byte1]: 26
8583 12:17:46.260139
8584 12:17:46.260553 Set Vref, RX VrefLevel [Byte0]: 27
8585 12:17:46.263544 [Byte1]: 27
8586 12:17:46.268398
8587 12:17:46.268909 Set Vref, RX VrefLevel [Byte0]: 28
8588 12:17:46.271574 [Byte1]: 28
8589 12:17:46.275201
8590 12:17:46.275654 Set Vref, RX VrefLevel [Byte0]: 29
8591 12:17:46.279022 [Byte1]: 29
8592 12:17:46.283766
8593 12:17:46.284276 Set Vref, RX VrefLevel [Byte0]: 30
8594 12:17:46.286679 [Byte1]: 30
8595 12:17:46.291302
8596 12:17:46.291860 Set Vref, RX VrefLevel [Byte0]: 31
8597 12:17:46.294171 [Byte1]: 31
8598 12:17:46.298253
8599 12:17:46.298691 Set Vref, RX VrefLevel [Byte0]: 32
8600 12:17:46.301700 [Byte1]: 32
8601 12:17:46.306168
8602 12:17:46.306585 Set Vref, RX VrefLevel [Byte0]: 33
8603 12:17:46.308982 [Byte1]: 33
8604 12:17:46.313409
8605 12:17:46.313821 Set Vref, RX VrefLevel [Byte0]: 34
8606 12:17:46.316674 [Byte1]: 34
8607 12:17:46.321690
8608 12:17:46.322210 Set Vref, RX VrefLevel [Byte0]: 35
8609 12:17:46.324155 [Byte1]: 35
8610 12:17:46.328785
8611 12:17:46.329324 Set Vref, RX VrefLevel [Byte0]: 36
8612 12:17:46.331900 [Byte1]: 36
8613 12:17:46.336837
8614 12:17:46.337350 Set Vref, RX VrefLevel [Byte0]: 37
8615 12:17:46.339452 [Byte1]: 37
8616 12:17:46.344406
8617 12:17:46.344915 Set Vref, RX VrefLevel [Byte0]: 38
8618 12:17:46.346861 [Byte1]: 38
8619 12:17:46.351615
8620 12:17:46.352034 Set Vref, RX VrefLevel [Byte0]: 39
8621 12:17:46.355171 [Byte1]: 39
8622 12:17:46.359173
8623 12:17:46.359726 Set Vref, RX VrefLevel [Byte0]: 40
8624 12:17:46.362684 [Byte1]: 40
8625 12:17:46.367488
8626 12:17:46.368013 Set Vref, RX VrefLevel [Byte0]: 41
8627 12:17:46.369975 [Byte1]: 41
8628 12:17:46.374579
8629 12:17:46.375091 Set Vref, RX VrefLevel [Byte0]: 42
8630 12:17:46.377990 [Byte1]: 42
8631 12:17:46.382191
8632 12:17:46.382703 Set Vref, RX VrefLevel [Byte0]: 43
8633 12:17:46.385631 [Byte1]: 43
8634 12:17:46.389664
8635 12:17:46.390234 Set Vref, RX VrefLevel [Byte0]: 44
8636 12:17:46.393082 [Byte1]: 44
8637 12:17:46.397352
8638 12:17:46.397930 Set Vref, RX VrefLevel [Byte0]: 45
8639 12:17:46.400866 [Byte1]: 45
8640 12:17:46.404816
8641 12:17:46.405381 Set Vref, RX VrefLevel [Byte0]: 46
8642 12:17:46.408155 [Byte1]: 46
8643 12:17:46.412719
8644 12:17:46.413252 Set Vref, RX VrefLevel [Byte0]: 47
8645 12:17:46.415937 [Byte1]: 47
8646 12:17:46.420381
8647 12:17:46.420935 Set Vref, RX VrefLevel [Byte0]: 48
8648 12:17:46.423353 [Byte1]: 48
8649 12:17:46.427624
8650 12:17:46.428176 Set Vref, RX VrefLevel [Byte0]: 49
8651 12:17:46.431059 [Byte1]: 49
8652 12:17:46.435589
8653 12:17:46.436152 Set Vref, RX VrefLevel [Byte0]: 50
8654 12:17:46.439005 [Byte1]: 50
8655 12:17:46.442990
8656 12:17:46.443548 Set Vref, RX VrefLevel [Byte0]: 51
8657 12:17:46.446399 [Byte1]: 51
8658 12:17:46.450800
8659 12:17:46.451352 Set Vref, RX VrefLevel [Byte0]: 52
8660 12:17:46.454152 [Byte1]: 52
8661 12:17:46.458308
8662 12:17:46.458866 Set Vref, RX VrefLevel [Byte0]: 53
8663 12:17:46.461109 [Byte1]: 53
8664 12:17:46.465929
8665 12:17:46.466656 Set Vref, RX VrefLevel [Byte0]: 54
8666 12:17:46.469163 [Byte1]: 54
8667 12:17:46.473598
8668 12:17:46.474109 Set Vref, RX VrefLevel [Byte0]: 55
8669 12:17:46.476843 [Byte1]: 55
8670 12:17:46.480772
8671 12:17:46.481193 Set Vref, RX VrefLevel [Byte0]: 56
8672 12:17:46.484766 [Byte1]: 56
8673 12:17:46.488486
8674 12:17:46.488907 Set Vref, RX VrefLevel [Byte0]: 57
8675 12:17:46.491553 [Byte1]: 57
8676 12:17:46.496373
8677 12:17:46.496886 Set Vref, RX VrefLevel [Byte0]: 58
8678 12:17:46.499779 [Byte1]: 58
8679 12:17:46.504052
8680 12:17:46.504565 Set Vref, RX VrefLevel [Byte0]: 59
8681 12:17:46.507604 [Byte1]: 59
8682 12:17:46.511328
8683 12:17:46.511772 Set Vref, RX VrefLevel [Byte0]: 60
8684 12:17:46.514673 [Byte1]: 60
8685 12:17:46.519251
8686 12:17:46.519817 Set Vref, RX VrefLevel [Byte0]: 61
8687 12:17:46.522913 [Byte1]: 61
8688 12:17:46.526860
8689 12:17:46.527501 Set Vref, RX VrefLevel [Byte0]: 62
8690 12:17:46.530361 [Byte1]: 62
8691 12:17:46.534436
8692 12:17:46.534994 Set Vref, RX VrefLevel [Byte0]: 63
8693 12:17:46.537897 [Byte1]: 63
8694 12:17:46.541625
8695 12:17:46.542085 Set Vref, RX VrefLevel [Byte0]: 64
8696 12:17:46.545278 [Byte1]: 64
8697 12:17:46.549814
8698 12:17:46.550241 Set Vref, RX VrefLevel [Byte0]: 65
8699 12:17:46.552528 [Byte1]: 65
8700 12:17:46.557085
8701 12:17:46.557611 Set Vref, RX VrefLevel [Byte0]: 66
8702 12:17:46.560112 [Byte1]: 66
8703 12:17:46.564475
8704 12:17:46.564987 Set Vref, RX VrefLevel [Byte0]: 67
8705 12:17:46.568134 [Byte1]: 67
8706 12:17:46.572836
8707 12:17:46.573349 Set Vref, RX VrefLevel [Byte0]: 68
8708 12:17:46.575525 [Byte1]: 68
8709 12:17:46.580028
8710 12:17:46.580446 Set Vref, RX VrefLevel [Byte0]: 69
8711 12:17:46.582874 [Byte1]: 69
8712 12:17:46.587260
8713 12:17:46.587731 Set Vref, RX VrefLevel [Byte0]: 70
8714 12:17:46.591151 [Byte1]: 70
8715 12:17:46.594898
8716 12:17:46.595317 Final RX Vref Byte 0 = 55 to rank0
8717 12:17:46.598495 Final RX Vref Byte 1 = 56 to rank0
8718 12:17:46.601827 Final RX Vref Byte 0 = 55 to rank1
8719 12:17:46.604924 Final RX Vref Byte 1 = 56 to rank1==
8720 12:17:46.608627 Dram Type= 6, Freq= 0, CH_1, rank 0
8721 12:17:46.614816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 12:17:46.615296 ==
8723 12:17:46.615710 DQS Delay:
8724 12:17:46.616028 DQS0 = 0, DQS1 = 0
8725 12:17:46.618568 DQM Delay:
8726 12:17:46.619061 DQM0 = 131, DQM1 = 123
8727 12:17:46.621862 DQ Delay:
8728 12:17:46.625009 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8729 12:17:46.628666 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8730 12:17:46.631499 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8731 12:17:46.634816 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8732 12:17:46.635267
8733 12:17:46.635680
8734 12:17:46.636005
8735 12:17:46.638370 [DramC_TX_OE_Calibration] TA2
8736 12:17:46.641744 Original DQ_B0 (3 6) =30, OEN = 27
8737 12:17:46.645349 Original DQ_B1 (3 6) =30, OEN = 27
8738 12:17:46.648018 24, 0x0, End_B0=24 End_B1=24
8739 12:17:46.648470 25, 0x0, End_B0=25 End_B1=25
8740 12:17:46.651620 26, 0x0, End_B0=26 End_B1=26
8741 12:17:46.654665 27, 0x0, End_B0=27 End_B1=27
8742 12:17:46.658077 28, 0x0, End_B0=28 End_B1=28
8743 12:17:46.658518 29, 0x0, End_B0=29 End_B1=29
8744 12:17:46.661767 30, 0x0, End_B0=30 End_B1=30
8745 12:17:46.664754 31, 0x4141, End_B0=30 End_B1=30
8746 12:17:46.668264 Byte0 end_step=30 best_step=27
8747 12:17:46.671559 Byte1 end_step=30 best_step=27
8748 12:17:46.674572 Byte0 TX OE(2T, 0.5T) = (3, 3)
8749 12:17:46.678167 Byte1 TX OE(2T, 0.5T) = (3, 3)
8750 12:17:46.678570
8751 12:17:46.678889
8752 12:17:46.684437 [DQSOSCAuto] RK0, (LSB)MR18= 0x70c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
8753 12:17:46.687862 CH1 RK0: MR19=303, MR18=70C
8754 12:17:46.694315 CH1_RK0: MR19=0x303, MR18=0x70C, DQSOSC=403, MR23=63, INC=22, DEC=15
8755 12:17:46.694719
8756 12:17:46.697832 ----->DramcWriteLeveling(PI) begin...
8757 12:17:46.698229 ==
8758 12:17:46.701169 Dram Type= 6, Freq= 0, CH_1, rank 1
8759 12:17:46.704712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 12:17:46.705101 ==
8761 12:17:46.707665 Write leveling (Byte 0): 25 => 25
8762 12:17:46.710866 Write leveling (Byte 1): 28 => 28
8763 12:17:46.714419 DramcWriteLeveling(PI) end<-----
8764 12:17:46.714802
8765 12:17:46.715128 ==
8766 12:17:46.717902 Dram Type= 6, Freq= 0, CH_1, rank 1
8767 12:17:46.721003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8768 12:17:46.721375 ==
8769 12:17:46.724513 [Gating] SW mode calibration
8770 12:17:46.730768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8771 12:17:46.737264 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8772 12:17:46.740841 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 12:17:46.744259 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 12:17:46.750702 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8775 12:17:46.753819 1 4 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
8776 12:17:46.757415 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 12:17:46.763843 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 12:17:46.767334 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 12:17:46.770925 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8780 12:17:46.777381 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 12:17:46.780138 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 12:17:46.783630 1 5 8 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (1 0)
8783 12:17:46.790083 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8784 12:17:46.793518 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 12:17:46.796551 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 12:17:46.803482 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 12:17:46.806663 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 12:17:46.809885 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 12:17:46.816422 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 12:17:46.820088 1 6 8 | B1->B0 | 2929 4343 | 0 0 | (0 0) (0 0)
8791 12:17:46.823733 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8792 12:17:46.830108 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 12:17:46.833404 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 12:17:46.836673 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 12:17:46.842916 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 12:17:46.846372 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 12:17:46.849749 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 12:17:46.856382 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8799 12:17:46.859332 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8800 12:17:46.862610 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 12:17:46.869724 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 12:17:46.872560 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 12:17:46.876157 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 12:17:46.883131 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 12:17:46.885902 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 12:17:46.889319 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 12:17:46.895752 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 12:17:46.899130 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 12:17:46.902473 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 12:17:46.908862 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:17:46.912544 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 12:17:46.915696 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:17:46.922656 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:17:46.925265 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8815 12:17:46.928721 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8816 12:17:46.932397 Total UI for P1: 0, mck2ui 16
8817 12:17:46.935841 best dqsien dly found for B0: ( 1, 9, 8)
8818 12:17:46.942123 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 12:17:46.942591 Total UI for P1: 0, mck2ui 16
8820 12:17:46.948876 best dqsien dly found for B1: ( 1, 9, 10)
8821 12:17:46.951955 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8822 12:17:46.955175 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8823 12:17:46.955659
8824 12:17:46.958876 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8825 12:17:46.961744 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8826 12:17:46.965303 [Gating] SW calibration Done
8827 12:17:46.965720 ==
8828 12:17:46.968030 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 12:17:46.971331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 12:17:46.971436 ==
8831 12:17:46.975073 RX Vref Scan: 0
8832 12:17:46.975154
8833 12:17:46.975217 RX Vref 0 -> 0, step: 1
8834 12:17:46.975277
8835 12:17:46.977896 RX Delay 0 -> 252, step: 8
8836 12:17:46.984685 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8837 12:17:46.988245 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8838 12:17:46.991248 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8839 12:17:46.994787 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8840 12:17:46.998288 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8841 12:17:47.001277 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8842 12:17:47.007749 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8843 12:17:47.011169 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8844 12:17:47.014846 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8845 12:17:47.017935 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8846 12:17:47.024246 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8847 12:17:47.027562 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8848 12:17:47.030882 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8849 12:17:47.034141 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8850 12:17:47.037424 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8851 12:17:47.044191 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8852 12:17:47.044272 ==
8853 12:17:47.047273 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 12:17:47.050594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 12:17:47.050670 ==
8856 12:17:47.050733 DQS Delay:
8857 12:17:47.053789 DQS0 = 0, DQS1 = 0
8858 12:17:47.053860 DQM Delay:
8859 12:17:47.057547 DQM0 = 129, DQM1 = 129
8860 12:17:47.057635 DQ Delay:
8861 12:17:47.060656 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8862 12:17:47.064083 DQ4 =123, DQ5 =139, DQ6 =139, DQ7 =127
8863 12:17:47.067606 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8864 12:17:47.070688 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8865 12:17:47.070768
8866 12:17:47.074314
8867 12:17:47.074394 ==
8868 12:17:47.077366 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 12:17:47.080439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 12:17:47.080521 ==
8871 12:17:47.080586
8872 12:17:47.080645
8873 12:17:47.083727 TX Vref Scan disable
8874 12:17:47.083808 == TX Byte 0 ==
8875 12:17:47.090401 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8876 12:17:47.093892 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8877 12:17:47.093972 == TX Byte 1 ==
8878 12:17:47.100174 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8879 12:17:47.103654 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8880 12:17:47.103734 ==
8881 12:17:47.107302 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 12:17:47.110107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 12:17:47.110188 ==
8884 12:17:47.125049
8885 12:17:47.128406 TX Vref early break, caculate TX vref
8886 12:17:47.131424 TX Vref=16, minBit 0, minWin=22, winSum=382
8887 12:17:47.134947 TX Vref=18, minBit 0, minWin=23, winSum=392
8888 12:17:47.138500 TX Vref=20, minBit 0, minWin=24, winSum=400
8889 12:17:47.141820 TX Vref=22, minBit 0, minWin=24, winSum=411
8890 12:17:47.144954 TX Vref=24, minBit 0, minWin=25, winSum=418
8891 12:17:47.151149 TX Vref=26, minBit 0, minWin=25, winSum=425
8892 12:17:47.154812 TX Vref=28, minBit 0, minWin=25, winSum=423
8893 12:17:47.158180 TX Vref=30, minBit 1, minWin=24, winSum=423
8894 12:17:47.161290 TX Vref=32, minBit 0, minWin=24, winSum=411
8895 12:17:47.164257 TX Vref=34, minBit 0, minWin=24, winSum=407
8896 12:17:47.167941 TX Vref=36, minBit 0, minWin=23, winSum=394
8897 12:17:47.174314 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8898 12:17:47.174396
8899 12:17:47.177789 Final TX Range 0 Vref 26
8900 12:17:47.177870
8901 12:17:47.177932 ==
8902 12:17:47.181080 Dram Type= 6, Freq= 0, CH_1, rank 1
8903 12:17:47.184248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8904 12:17:47.184329 ==
8905 12:17:47.184393
8906 12:17:47.188119
8907 12:17:47.188199 TX Vref Scan disable
8908 12:17:47.194341 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8909 12:17:47.194422 == TX Byte 0 ==
8910 12:17:47.197591 u2DelayCellOfst[0]=18 cells (5 PI)
8911 12:17:47.200988 u2DelayCellOfst[1]=15 cells (4 PI)
8912 12:17:47.204253 u2DelayCellOfst[2]=0 cells (0 PI)
8913 12:17:47.207898 u2DelayCellOfst[3]=7 cells (2 PI)
8914 12:17:47.210891 u2DelayCellOfst[4]=7 cells (2 PI)
8915 12:17:47.214362 u2DelayCellOfst[5]=26 cells (7 PI)
8916 12:17:47.217235 u2DelayCellOfst[6]=18 cells (5 PI)
8917 12:17:47.220891 u2DelayCellOfst[7]=11 cells (3 PI)
8918 12:17:47.224365 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8919 12:17:47.227121 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 12:17:47.230576 == TX Byte 1 ==
8921 12:17:47.233967 u2DelayCellOfst[8]=0 cells (0 PI)
8922 12:17:47.236931 u2DelayCellOfst[9]=7 cells (2 PI)
8923 12:17:47.240594 u2DelayCellOfst[10]=11 cells (3 PI)
8924 12:17:47.243913 u2DelayCellOfst[11]=7 cells (2 PI)
8925 12:17:47.247072 u2DelayCellOfst[12]=15 cells (4 PI)
8926 12:17:47.247157 u2DelayCellOfst[13]=18 cells (5 PI)
8927 12:17:47.250545 u2DelayCellOfst[14]=18 cells (5 PI)
8928 12:17:47.253815 u2DelayCellOfst[15]=18 cells (5 PI)
8929 12:17:47.260158 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8930 12:17:47.263984 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8931 12:17:47.264087 DramC Write-DBI on
8932 12:17:47.266846 ==
8933 12:17:47.270194 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 12:17:47.273768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 12:17:47.273851 ==
8936 12:17:47.273916
8937 12:17:47.273975
8938 12:17:47.276600 TX Vref Scan disable
8939 12:17:47.276681 == TX Byte 0 ==
8940 12:17:47.283356 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8941 12:17:47.283481 == TX Byte 1 ==
8942 12:17:47.286930 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8943 12:17:47.290090 DramC Write-DBI off
8944 12:17:47.290170
8945 12:17:47.290234 [DATLAT]
8946 12:17:47.293590 Freq=1600, CH1 RK1
8947 12:17:47.293671
8948 12:17:47.293735 DATLAT Default: 0xf
8949 12:17:47.296826 0, 0xFFFF, sum = 0
8950 12:17:47.296908 1, 0xFFFF, sum = 0
8951 12:17:47.299691 2, 0xFFFF, sum = 0
8952 12:17:47.299773 3, 0xFFFF, sum = 0
8953 12:17:47.303434 4, 0xFFFF, sum = 0
8954 12:17:47.303517 5, 0xFFFF, sum = 0
8955 12:17:47.306553 6, 0xFFFF, sum = 0
8956 12:17:47.310184 7, 0xFFFF, sum = 0
8957 12:17:47.310267 8, 0xFFFF, sum = 0
8958 12:17:47.313545 9, 0xFFFF, sum = 0
8959 12:17:47.313627 10, 0xFFFF, sum = 0
8960 12:17:47.316200 11, 0xFFFF, sum = 0
8961 12:17:47.316282 12, 0xFFFF, sum = 0
8962 12:17:47.319879 13, 0x8FFF, sum = 0
8963 12:17:47.319961 14, 0x0, sum = 1
8964 12:17:47.323372 15, 0x0, sum = 2
8965 12:17:47.323494 16, 0x0, sum = 3
8966 12:17:47.326254 17, 0x0, sum = 4
8967 12:17:47.326335 best_step = 15
8968 12:17:47.326399
8969 12:17:47.326458 ==
8970 12:17:47.329913 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 12:17:47.333305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 12:17:47.336193 ==
8973 12:17:47.336273 RX Vref Scan: 0
8974 12:17:47.336336
8975 12:17:47.339355 RX Vref 0 -> 0, step: 1
8976 12:17:47.339480
8977 12:17:47.339544 RX Delay 11 -> 252, step: 4
8978 12:17:47.347053 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8979 12:17:47.350643 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8980 12:17:47.353433 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8981 12:17:47.356981 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8982 12:17:47.360346 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8983 12:17:47.366882 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8984 12:17:47.369980 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8985 12:17:47.373955 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
8986 12:17:47.376695 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
8987 12:17:47.380295 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8988 12:17:47.387005 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8989 12:17:47.389923 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8990 12:17:47.393389 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8991 12:17:47.396704 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8992 12:17:47.403514 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8993 12:17:47.407059 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8994 12:17:47.407141 ==
8995 12:17:47.410389 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 12:17:47.413609 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 12:17:47.413692 ==
8998 12:17:47.413757 DQS Delay:
8999 12:17:47.416708 DQS0 = 0, DQS1 = 0
9000 12:17:47.416790 DQM Delay:
9001 12:17:47.420172 DQM0 = 127, DQM1 = 125
9002 12:17:47.420254 DQ Delay:
9003 12:17:47.423855 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =124
9004 12:17:47.426818 DQ4 =124, DQ5 =140, DQ6 =138, DQ7 =122
9005 12:17:47.429808 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =120
9006 12:17:47.436524 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =134
9007 12:17:47.436606
9008 12:17:47.436670
9009 12:17:47.436729
9010 12:17:47.436786 [DramC_TX_OE_Calibration] TA2
9011 12:17:47.439642 Original DQ_B0 (3 6) =30, OEN = 27
9012 12:17:47.443615 Original DQ_B1 (3 6) =30, OEN = 27
9013 12:17:47.446437 24, 0x0, End_B0=24 End_B1=24
9014 12:17:47.450122 25, 0x0, End_B0=25 End_B1=25
9015 12:17:47.453519 26, 0x0, End_B0=26 End_B1=26
9016 12:17:47.453602 27, 0x0, End_B0=27 End_B1=27
9017 12:17:47.456398 28, 0x0, End_B0=28 End_B1=28
9018 12:17:47.459766 29, 0x0, End_B0=29 End_B1=29
9019 12:17:47.462810 30, 0x0, End_B0=30 End_B1=30
9020 12:17:47.466396 31, 0x4141, End_B0=30 End_B1=30
9021 12:17:47.469738 Byte0 end_step=30 best_step=27
9022 12:17:47.469820 Byte1 end_step=30 best_step=27
9023 12:17:47.473191 Byte0 TX OE(2T, 0.5T) = (3, 3)
9024 12:17:47.476041 Byte1 TX OE(2T, 0.5T) = (3, 3)
9025 12:17:47.476122
9026 12:17:47.476185
9027 12:17:47.486164 [DQSOSCAuto] RK1, (LSB)MR18= 0x141f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
9028 12:17:47.486248 CH1 RK1: MR19=303, MR18=141F
9029 12:17:47.493258 CH1_RK1: MR19=0x303, MR18=0x141F, DQSOSC=394, MR23=63, INC=23, DEC=15
9030 12:17:47.496231 [RxdqsGatingPostProcess] freq 1600
9031 12:17:47.502894 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9032 12:17:47.505999 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 12:17:47.509519 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 12:17:47.512607 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 12:17:47.515869 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 12:17:47.515953 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 12:17:47.519264 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 12:17:47.522428 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 12:17:47.525801 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 12:17:47.529184 Pre-setting of DQS Precalculation
9041 12:17:47.536411 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9042 12:17:47.542289 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9043 12:17:47.549063 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9044 12:17:47.549155
9045 12:17:47.549241
9046 12:17:47.552759 [Calibration Summary] 3200 Mbps
9047 12:17:47.552858 CH 0, Rank 0
9048 12:17:47.555759 SW Impedance : PASS
9049 12:17:47.559229 DUTY Scan : NO K
9050 12:17:47.559322 ZQ Calibration : PASS
9051 12:17:47.562495 Jitter Meter : NO K
9052 12:17:47.565709 CBT Training : PASS
9053 12:17:47.565786 Write leveling : PASS
9054 12:17:47.568878 RX DQS gating : PASS
9055 12:17:47.572484 RX DQ/DQS(RDDQC) : PASS
9056 12:17:47.572556 TX DQ/DQS : PASS
9057 12:17:47.575490 RX DATLAT : PASS
9058 12:17:47.578709 RX DQ/DQS(Engine): PASS
9059 12:17:47.578789 TX OE : PASS
9060 12:17:47.582087 All Pass.
9061 12:17:47.582185
9062 12:17:47.582283 CH 0, Rank 1
9063 12:17:47.585202 SW Impedance : PASS
9064 12:17:47.585297 DUTY Scan : NO K
9065 12:17:47.588541 ZQ Calibration : PASS
9066 12:17:47.592190 Jitter Meter : NO K
9067 12:17:47.592259 CBT Training : PASS
9068 12:17:47.595292 Write leveling : PASS
9069 12:17:47.595416 RX DQS gating : PASS
9070 12:17:47.598529 RX DQ/DQS(RDDQC) : PASS
9071 12:17:47.602041 TX DQ/DQS : PASS
9072 12:17:47.602117 RX DATLAT : PASS
9073 12:17:47.605290 RX DQ/DQS(Engine): PASS
9074 12:17:47.608870 TX OE : PASS
9075 12:17:47.608951 All Pass.
9076 12:17:47.609015
9077 12:17:47.609073 CH 1, Rank 0
9078 12:17:47.611933 SW Impedance : PASS
9079 12:17:47.615213 DUTY Scan : NO K
9080 12:17:47.615293 ZQ Calibration : PASS
9081 12:17:47.618520 Jitter Meter : NO K
9082 12:17:47.621833 CBT Training : PASS
9083 12:17:47.621916 Write leveling : PASS
9084 12:17:47.625059 RX DQS gating : PASS
9085 12:17:47.628390 RX DQ/DQS(RDDQC) : PASS
9086 12:17:47.628471 TX DQ/DQS : PASS
9087 12:17:47.631988 RX DATLAT : PASS
9088 12:17:47.635691 RX DQ/DQS(Engine): PASS
9089 12:17:47.635773 TX OE : PASS
9090 12:17:47.638114 All Pass.
9091 12:17:47.638196
9092 12:17:47.638261 CH 1, Rank 1
9093 12:17:47.641523 SW Impedance : PASS
9094 12:17:47.641606 DUTY Scan : NO K
9095 12:17:47.644602 ZQ Calibration : PASS
9096 12:17:47.648001 Jitter Meter : NO K
9097 12:17:47.648083 CBT Training : PASS
9098 12:17:47.651642 Write leveling : PASS
9099 12:17:47.654944 RX DQS gating : PASS
9100 12:17:47.655026 RX DQ/DQS(RDDQC) : PASS
9101 12:17:47.657904 TX DQ/DQS : PASS
9102 12:17:47.661284 RX DATLAT : PASS
9103 12:17:47.661366 RX DQ/DQS(Engine): PASS
9104 12:17:47.665003 TX OE : PASS
9105 12:17:47.665086 All Pass.
9106 12:17:47.665151
9107 12:17:47.668352 DramC Write-DBI on
9108 12:17:47.668434 PER_BANK_REFRESH: Hybrid Mode
9109 12:17:47.671425 TX_TRACKING: ON
9110 12:17:47.681228 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9111 12:17:47.688207 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9112 12:17:47.694471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9113 12:17:47.698202 [FAST_K] Save calibration result to emmc
9114 12:17:47.700937 sync common calibartion params.
9115 12:17:47.704361 sync cbt_mode0:1, 1:1
9116 12:17:47.707919 dram_init: ddr_geometry: 2
9117 12:17:47.708000 dram_init: ddr_geometry: 2
9118 12:17:47.710877 dram_init: ddr_geometry: 2
9119 12:17:47.714370 0:dram_rank_size:100000000
9120 12:17:47.714454 1:dram_rank_size:100000000
9121 12:17:47.721358 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9122 12:17:47.724462 DFS_SHUFFLE_HW_MODE: ON
9123 12:17:47.727506 dramc_set_vcore_voltage set vcore to 725000
9124 12:17:47.731381 Read voltage for 1600, 0
9125 12:17:47.731485 Vio18 = 0
9126 12:17:47.731551 Vcore = 725000
9127 12:17:47.734215 Vdram = 0
9128 12:17:47.734297 Vddq = 0
9129 12:17:47.734376 Vmddr = 0
9130 12:17:47.737594 switch to 3200 Mbps bootup
9131 12:17:47.737686 [DramcRunTimeConfig]
9132 12:17:47.741132 PHYPLL
9133 12:17:47.741214 DPM_CONTROL_AFTERK: ON
9134 12:17:47.744119 PER_BANK_REFRESH: ON
9135 12:17:47.747703 REFRESH_OVERHEAD_REDUCTION: ON
9136 12:17:47.747784 CMD_PICG_NEW_MODE: OFF
9137 12:17:47.750706 XRTWTW_NEW_MODE: ON
9138 12:17:47.750788 XRTRTR_NEW_MODE: ON
9139 12:17:47.753969 TX_TRACKING: ON
9140 12:17:47.754052 RDSEL_TRACKING: OFF
9141 12:17:47.757258 DQS Precalculation for DVFS: ON
9142 12:17:47.760839 RX_TRACKING: OFF
9143 12:17:47.760921 HW_GATING DBG: ON
9144 12:17:47.764436 ZQCS_ENABLE_LP4: ON
9145 12:17:47.764518 RX_PICG_NEW_MODE: ON
9146 12:17:47.767808 TX_PICG_NEW_MODE: ON
9147 12:17:47.770629 ENABLE_RX_DCM_DPHY: ON
9148 12:17:47.770711 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9149 12:17:47.774165 DUMMY_READ_FOR_TRACKING: OFF
9150 12:17:47.777161 !!! SPM_CONTROL_AFTERK: OFF
9151 12:17:47.780638 !!! SPM could not control APHY
9152 12:17:47.780761 IMPEDANCE_TRACKING: ON
9153 12:17:47.784135 TEMP_SENSOR: ON
9154 12:17:47.784217 HW_SAVE_FOR_SR: OFF
9155 12:17:47.787052 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9156 12:17:47.790389 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9157 12:17:47.793856 Read ODT Tracking: ON
9158 12:17:47.796934 Refresh Rate DeBounce: ON
9159 12:17:47.797016 DFS_NO_QUEUE_FLUSH: ON
9160 12:17:47.800293 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9161 12:17:47.803781 ENABLE_DFS_RUNTIME_MRW: OFF
9162 12:17:47.806673 DDR_RESERVE_NEW_MODE: ON
9163 12:17:47.806745 MR_CBT_SWITCH_FREQ: ON
9164 12:17:47.810347 =========================
9165 12:17:47.829900 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9166 12:17:47.832861 dram_init: ddr_geometry: 2
9167 12:17:47.851345 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9168 12:17:47.854196 dram_init: dram init end (result: 0)
9169 12:17:47.860846 DRAM-K: Full calibration passed in 24592 msecs
9170 12:17:47.864136 MRC: failed to locate region type 0.
9171 12:17:47.864217 DRAM rank0 size:0x100000000,
9172 12:17:47.868310 DRAM rank1 size=0x100000000
9173 12:17:47.877650 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9174 12:17:47.884415 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9175 12:17:47.890762 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9176 12:17:47.897432 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9177 12:17:47.900815 DRAM rank0 size:0x100000000,
9178 12:17:47.904486 DRAM rank1 size=0x100000000
9179 12:17:47.904570 CBMEM:
9180 12:17:47.907489 IMD: root @ 0xfffff000 254 entries.
9181 12:17:47.910563 IMD: root @ 0xffffec00 62 entries.
9182 12:17:47.914089 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9183 12:17:47.920352 WARNING: RO_VPD is uninitialized or empty.
9184 12:17:47.923800 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9185 12:17:47.931228 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9186 12:17:47.943889 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9187 12:17:47.955298 BS: romstage times (exec / console): total (unknown) / 24050 ms
9188 12:17:47.955426
9189 12:17:47.955532
9190 12:17:47.965344 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9191 12:17:47.968208 ARM64: Exception handlers installed.
9192 12:17:47.971794 ARM64: Testing exception
9193 12:17:47.975278 ARM64: Done test exception
9194 12:17:47.975359 Enumerating buses...
9195 12:17:47.978622 Show all devs... Before device enumeration.
9196 12:17:47.981847 Root Device: enabled 1
9197 12:17:47.985070 CPU_CLUSTER: 0: enabled 1
9198 12:17:47.985151 CPU: 00: enabled 1
9199 12:17:47.988301 Compare with tree...
9200 12:17:47.988382 Root Device: enabled 1
9201 12:17:47.991915 CPU_CLUSTER: 0: enabled 1
9202 12:17:47.995264 CPU: 00: enabled 1
9203 12:17:47.995370 Root Device scanning...
9204 12:17:47.998080 scan_static_bus for Root Device
9205 12:17:48.001280 CPU_CLUSTER: 0 enabled
9206 12:17:48.004735 scan_static_bus for Root Device done
9207 12:17:48.008199 scan_bus: bus Root Device finished in 8 msecs
9208 12:17:48.008280 done
9209 12:17:48.015003 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9210 12:17:48.018168 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9211 12:17:48.024611 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9212 12:17:48.027914 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9213 12:17:48.031330 Allocating resources...
9214 12:17:48.034750 Reading resources...
9215 12:17:48.038067 Root Device read_resources bus 0 link: 0
9216 12:17:48.041395 DRAM rank0 size:0x100000000,
9217 12:17:48.041476 DRAM rank1 size=0x100000000
9218 12:17:48.044716 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9219 12:17:48.048148 CPU: 00 missing read_resources
9220 12:17:48.054908 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9221 12:17:48.057643 Root Device read_resources bus 0 link: 0 done
9222 12:17:48.057724 Done reading resources.
9223 12:17:48.064303 Show resources in subtree (Root Device)...After reading.
9224 12:17:48.067395 Root Device child on link 0 CPU_CLUSTER: 0
9225 12:17:48.070771 CPU_CLUSTER: 0 child on link 0 CPU: 00
9226 12:17:48.080695 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9227 12:17:48.080777 CPU: 00
9228 12:17:48.084127 Root Device assign_resources, bus 0 link: 0
9229 12:17:48.087369 CPU_CLUSTER: 0 missing set_resources
9230 12:17:48.093987 Root Device assign_resources, bus 0 link: 0 done
9231 12:17:48.094071 Done setting resources.
9232 12:17:48.100847 Show resources in subtree (Root Device)...After assigning values.
9233 12:17:48.104287 Root Device child on link 0 CPU_CLUSTER: 0
9234 12:17:48.107304 CPU_CLUSTER: 0 child on link 0 CPU: 00
9235 12:17:48.117497 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9236 12:17:48.117582 CPU: 00
9237 12:17:48.120588 Done allocating resources.
9238 12:17:48.127631 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9239 12:17:48.127729 Enabling resources...
9240 12:17:48.127825 done.
9241 12:17:48.134024 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9242 12:17:48.134182 Initializing devices...
9243 12:17:48.137424 Root Device init
9244 12:17:48.140954 init hardware done!
9245 12:17:48.141036 0x00000018: ctrlr->caps
9246 12:17:48.143869 52.000 MHz: ctrlr->f_max
9247 12:17:48.147059 0.400 MHz: ctrlr->f_min
9248 12:17:48.147144 0x40ff8080: ctrlr->voltages
9249 12:17:48.150644 sclk: 390625
9250 12:17:48.150755 Bus Width = 1
9251 12:17:48.150819 sclk: 390625
9252 12:17:48.154022 Bus Width = 1
9253 12:17:48.154104 Early init status = 3
9254 12:17:48.160558 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9255 12:17:48.163707 in-header: 03 fc 00 00 01 00 00 00
9256 12:17:48.167249 in-data: 00
9257 12:17:48.170397 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9258 12:17:48.174262 in-header: 03 fd 00 00 00 00 00 00
9259 12:17:48.177179 in-data:
9260 12:17:48.180778 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9261 12:17:48.184247 in-header: 03 fc 00 00 01 00 00 00
9262 12:17:48.187403 in-data: 00
9263 12:17:48.190997 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9264 12:17:48.195140 in-header: 03 fd 00 00 00 00 00 00
9265 12:17:48.198474 in-data:
9266 12:17:48.202042 [SSUSB] Setting up USB HOST controller...
9267 12:17:48.205484 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9268 12:17:48.208488 [SSUSB] phy power-on done.
9269 12:17:48.211735 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9270 12:17:48.218553 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9271 12:17:48.221878 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9272 12:17:48.228622 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9273 12:17:48.235001 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9274 12:17:48.242158 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9275 12:17:48.248013 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9276 12:17:48.254936 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9277 12:17:48.258497 SPM: binary array size = 0x9dc
9278 12:17:48.261439 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9279 12:17:48.268175 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9280 12:17:48.275001 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9281 12:17:48.281486 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9282 12:17:48.284809 configure_display: Starting display init
9283 12:17:48.318787 anx7625_power_on_init: Init interface.
9284 12:17:48.321925 anx7625_disable_pd_protocol: Disabled PD feature.
9285 12:17:48.325178 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9286 12:17:48.353030 anx7625_start_dp_work: Secure OCM version=00
9287 12:17:48.356292 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9288 12:17:48.371297 sp_tx_get_edid_block: EDID Block = 1
9289 12:17:48.473791 Extracted contents:
9290 12:17:48.476811 header: 00 ff ff ff ff ff ff 00
9291 12:17:48.480338 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9292 12:17:48.483503 version: 01 04
9293 12:17:48.486942 basic params: 95 1f 11 78 0a
9294 12:17:48.490136 chroma info: 76 90 94 55 54 90 27 21 50 54
9295 12:17:48.493607 established: 00 00 00
9296 12:17:48.499878 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9297 12:17:48.506320 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9298 12:17:48.509828 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9299 12:17:48.516298 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9300 12:17:48.523228 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9301 12:17:48.526143 extensions: 00
9302 12:17:48.526222 checksum: fb
9303 12:17:48.526285
9304 12:17:48.532865 Manufacturer: IVO Model 57d Serial Number 0
9305 12:17:48.532945 Made week 0 of 2020
9306 12:17:48.536073 EDID version: 1.4
9307 12:17:48.536152 Digital display
9308 12:17:48.539420 6 bits per primary color channel
9309 12:17:48.539516 DisplayPort interface
9310 12:17:48.543018 Maximum image size: 31 cm x 17 cm
9311 12:17:48.546054 Gamma: 220%
9312 12:17:48.546135 Check DPMS levels
9313 12:17:48.550026 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9314 12:17:48.556522 First detailed timing is preferred timing
9315 12:17:48.556603 Established timings supported:
9316 12:17:48.559635 Standard timings supported:
9317 12:17:48.562981 Detailed timings
9318 12:17:48.565973 Hex of detail: 383680a07038204018303c0035ae10000019
9319 12:17:48.573029 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9320 12:17:48.575788 0780 0798 07c8 0820 hborder 0
9321 12:17:48.578987 0438 043b 0447 0458 vborder 0
9322 12:17:48.582356 -hsync -vsync
9323 12:17:48.582470 Did detailed timing
9324 12:17:48.589170 Hex of detail: 000000000000000000000000000000000000
9325 12:17:48.592540 Manufacturer-specified data, tag 0
9326 12:17:48.595375 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9327 12:17:48.599156 ASCII string: InfoVision
9328 12:17:48.602257 Hex of detail: 000000fe00523134304e574635205248200a
9329 12:17:48.605690 ASCII string: R140NWF5 RH
9330 12:17:48.605764 Checksum
9331 12:17:48.609353 Checksum: 0xfb (valid)
9332 12:17:48.612069 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9333 12:17:48.615629 DSI data_rate: 832800000 bps
9334 12:17:48.622046 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9335 12:17:48.625371 anx7625_parse_edid: pixelclock(138800).
9336 12:17:48.629183 hactive(1920), hsync(48), hfp(24), hbp(88)
9337 12:17:48.632644 vactive(1080), vsync(12), vfp(3), vbp(17)
9338 12:17:48.635260 anx7625_dsi_config: config dsi.
9339 12:17:48.642444 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9340 12:17:48.655642 anx7625_dsi_config: success to config DSI
9341 12:17:48.658990 anx7625_dp_start: MIPI phy setup OK.
9342 12:17:48.662534 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9343 12:17:48.665589 mtk_ddp_mode_set invalid vrefresh 60
9344 12:17:48.668970 main_disp_path_setup
9345 12:17:48.669051 ovl_layer_smi_id_en
9346 12:17:48.672149 ovl_layer_smi_id_en
9347 12:17:48.672229 ccorr_config
9348 12:17:48.672293 aal_config
9349 12:17:48.675354 gamma_config
9350 12:17:48.675472 postmask_config
9351 12:17:48.678579 dither_config
9352 12:17:48.682180 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9353 12:17:48.688704 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9354 12:17:48.691983 Root Device init finished in 551 msecs
9355 12:17:48.695357 CPU_CLUSTER: 0 init
9356 12:17:48.702050 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9357 12:17:48.705549 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9358 12:17:48.708926 APU_MBOX 0x190000b0 = 0x10001
9359 12:17:48.712254 APU_MBOX 0x190001b0 = 0x10001
9360 12:17:48.715171 APU_MBOX 0x190005b0 = 0x10001
9361 12:17:48.718784 APU_MBOX 0x190006b0 = 0x10001
9362 12:17:48.722170 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9363 12:17:48.734662 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9364 12:17:48.747263 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9365 12:17:48.754086 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9366 12:17:48.765078 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9367 12:17:48.774315 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9368 12:17:48.777798 CPU_CLUSTER: 0 init finished in 81 msecs
9369 12:17:48.781304 Devices initialized
9370 12:17:48.784767 Show all devs... After init.
9371 12:17:48.784850 Root Device: enabled 1
9372 12:17:48.787595 CPU_CLUSTER: 0: enabled 1
9373 12:17:48.791252 CPU: 00: enabled 1
9374 12:17:48.794252 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9375 12:17:48.797916 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9376 12:17:48.801324 ELOG: NV offset 0x57f000 size 0x1000
9377 12:17:48.807399 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9378 12:17:48.814086 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9379 12:17:48.817525 ELOG: Event(17) added with size 13 at 2023-10-27 12:17:49 UTC
9380 12:17:48.821100 out: cmd=0x121: 03 db 21 01 00 00 00 00
9381 12:17:48.824842 in-header: 03 49 00 00 2c 00 00 00
9382 12:17:48.838181 in-data: 15 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9383 12:17:48.844842 ELOG: Event(A1) added with size 10 at 2023-10-27 12:17:49 UTC
9384 12:17:48.851205 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9385 12:17:48.858219 ELOG: Event(A0) added with size 9 at 2023-10-27 12:17:49 UTC
9386 12:17:48.861758 elog_add_boot_reason: Logged dev mode boot
9387 12:17:48.864647 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9388 12:17:48.868011 Finalize devices...
9389 12:17:48.868092 Devices finalized
9390 12:17:48.874500 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9391 12:17:48.877872 Writing coreboot table at 0xffe64000
9392 12:17:48.881089 0. 000000000010a000-0000000000113fff: RAMSTAGE
9393 12:17:48.884698 1. 0000000040000000-00000000400fffff: RAM
9394 12:17:48.887793 2. 0000000040100000-000000004032afff: RAMSTAGE
9395 12:17:48.894764 3. 000000004032b000-00000000545fffff: RAM
9396 12:17:48.897747 4. 0000000054600000-000000005465ffff: BL31
9397 12:17:48.900991 5. 0000000054660000-00000000ffe63fff: RAM
9398 12:17:48.904597 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9399 12:17:48.911133 7. 0000000100000000-000000023fffffff: RAM
9400 12:17:48.911233 Passing 5 GPIOs to payload:
9401 12:17:48.917781 NAME | PORT | POLARITY | VALUE
9402 12:17:48.921141 EC in RW | 0x000000aa | low | undefined
9403 12:17:48.928022 EC interrupt | 0x00000005 | low | undefined
9404 12:17:48.931379 TPM interrupt | 0x000000ab | high | undefined
9405 12:17:48.934392 SD card detect | 0x00000011 | high | undefined
9406 12:17:48.941395 speaker enable | 0x00000093 | high | undefined
9407 12:17:48.944478 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9408 12:17:48.947719 in-header: 03 f9 00 00 02 00 00 00
9409 12:17:48.947802 in-data: 02 00
9410 12:17:48.951083 ADC[4]: Raw value=896300 ID=7
9411 12:17:48.954686 ADC[3]: Raw value=213440 ID=1
9412 12:17:48.954761 RAM Code: 0x71
9413 12:17:48.957858 ADC[6]: Raw value=74722 ID=0
9414 12:17:48.960878 ADC[5]: Raw value=212330 ID=1
9415 12:17:48.960959 SKU Code: 0x1
9416 12:17:48.967981 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 360f
9417 12:17:48.970963 coreboot table: 964 bytes.
9418 12:17:48.974346 IMD ROOT 0. 0xfffff000 0x00001000
9419 12:17:48.977731 IMD SMALL 1. 0xffffe000 0x00001000
9420 12:17:48.981436 RO MCACHE 2. 0xffffc000 0x00001104
9421 12:17:48.984247 CONSOLE 3. 0xfff7c000 0x00080000
9422 12:17:48.987553 FMAP 4. 0xfff7b000 0x00000452
9423 12:17:48.991200 TIME STAMP 5. 0xfff7a000 0x00000910
9424 12:17:48.994215 VBOOT WORK 6. 0xfff66000 0x00014000
9425 12:17:48.997649 RAMOOPS 7. 0xffe66000 0x00100000
9426 12:17:49.001160 COREBOOT 8. 0xffe64000 0x00002000
9427 12:17:49.001263 IMD small region:
9428 12:17:49.004247 IMD ROOT 0. 0xffffec00 0x00000400
9429 12:17:49.007878 VPD 1. 0xffffeb80 0x0000006c
9430 12:17:49.010812 MMC STATUS 2. 0xffffeb60 0x00000004
9431 12:17:49.017563 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9432 12:17:49.017646 Probing TPM: done!
9433 12:17:49.024008 Connected to device vid:did:rid of 1ae0:0028:00
9434 12:17:49.034457 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9435 12:17:49.037884 Initialized TPM device CR50 revision 0
9436 12:17:49.037965 Checking cr50 for pending updates
9437 12:17:49.044387 Reading cr50 TPM mode
9438 12:17:49.052584 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9439 12:17:49.059205 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9440 12:17:49.099442 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9441 12:17:49.102813 Checking segment from ROM address 0x40100000
9442 12:17:49.105840 Checking segment from ROM address 0x4010001c
9443 12:17:49.112874 Loading segment from ROM address 0x40100000
9444 12:17:49.112956 code (compression=0)
9445 12:17:49.119275 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9446 12:17:49.129842 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9447 12:17:49.129924 it's not compressed!
9448 12:17:49.136382 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9449 12:17:49.139770 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9450 12:17:49.159645 Loading segment from ROM address 0x4010001c
9451 12:17:49.159727 Entry Point 0x80000000
9452 12:17:49.162918 Loaded segments
9453 12:17:49.166379 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9454 12:17:49.173160 Jumping to boot code at 0x80000000(0xffe64000)
9455 12:17:49.179482 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9456 12:17:49.186505 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9457 12:17:49.194120 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9458 12:17:49.197585 Checking segment from ROM address 0x40100000
9459 12:17:49.201053 Checking segment from ROM address 0x4010001c
9460 12:17:49.207748 Loading segment from ROM address 0x40100000
9461 12:17:49.207830 code (compression=1)
9462 12:17:49.214457 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9463 12:17:49.224311 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9464 12:17:49.224392 using LZMA
9465 12:17:49.232938 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9466 12:17:49.239495 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9467 12:17:49.242810 Loading segment from ROM address 0x4010001c
9468 12:17:49.242893 Entry Point 0x54601000
9469 12:17:49.246083 Loaded segments
9470 12:17:49.249044 NOTICE: MT8192 bl31_setup
9471 12:17:49.256311 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9472 12:17:49.259939 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9473 12:17:49.263135 WARNING: region 0:
9474 12:17:49.266179 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 12:17:49.266262 WARNING: region 1:
9476 12:17:49.273157 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9477 12:17:49.275957 WARNING: region 2:
9478 12:17:49.279568 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9479 12:17:49.282556 WARNING: region 3:
9480 12:17:49.286103 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9481 12:17:49.289418 WARNING: region 4:
9482 12:17:49.296074 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9483 12:17:49.296157 WARNING: region 5:
9484 12:17:49.299677 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 12:17:49.303070 WARNING: region 6:
9486 12:17:49.306065 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9487 12:17:49.309351 WARNING: region 7:
9488 12:17:49.312832 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 12:17:49.319533 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9490 12:17:49.323004 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9491 12:17:49.326062 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9492 12:17:49.332614 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9493 12:17:49.336004 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9494 12:17:49.339278 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9495 12:17:49.346482 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9496 12:17:49.349279 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9497 12:17:49.356118 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9498 12:17:49.359587 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9499 12:17:49.362924 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9500 12:17:49.369301 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9501 12:17:49.373093 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9502 12:17:49.376052 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9503 12:17:49.383249 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9504 12:17:49.386514 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9505 12:17:49.392613 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9506 12:17:49.396191 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9507 12:17:49.399360 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9508 12:17:49.406058 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9509 12:17:49.409545 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9510 12:17:49.413143 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9511 12:17:49.419548 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9512 12:17:49.422952 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9513 12:17:49.429296 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9514 12:17:49.432624 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9515 12:17:49.436118 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9516 12:17:49.442860 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9517 12:17:49.445917 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9518 12:17:49.453007 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9519 12:17:49.456267 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9520 12:17:49.459241 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9521 12:17:49.466224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9522 12:17:49.469314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9523 12:17:49.472685 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9524 12:17:49.475779 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9525 12:17:49.483021 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9526 12:17:49.486034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9527 12:17:49.489409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9528 12:17:49.492703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9529 12:17:49.499280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9530 12:17:49.502540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9531 12:17:49.506053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9532 12:17:49.509161 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9533 12:17:49.515925 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9534 12:17:49.519574 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9535 12:17:49.522520 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9536 12:17:49.526098 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9537 12:17:49.532932 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9538 12:17:49.535885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9539 12:17:49.542683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9540 12:17:49.546227 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9541 12:17:49.549409 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9542 12:17:49.555602 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9543 12:17:49.559188 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9544 12:17:49.566045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9545 12:17:49.569554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9546 12:17:49.575981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9547 12:17:49.579184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9548 12:17:49.585824 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9549 12:17:49.589133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9550 12:17:49.592860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9551 12:17:49.599018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9552 12:17:49.602520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9553 12:17:49.609234 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9554 12:17:49.612606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9555 12:17:49.618891 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9556 12:17:49.622552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9557 12:17:49.628801 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9558 12:17:49.632483 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9559 12:17:49.635402 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9560 12:17:49.642029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9561 12:17:49.645410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9562 12:17:49.652440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9563 12:17:49.655685 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9564 12:17:49.662283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9565 12:17:49.665347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9566 12:17:49.668797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9567 12:17:49.675854 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9568 12:17:49.679303 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9569 12:17:49.685768 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9570 12:17:49.688921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9571 12:17:49.695593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9572 12:17:49.698842 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9573 12:17:49.702994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9574 12:17:49.708734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9575 12:17:49.711915 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9576 12:17:49.718600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9577 12:17:49.722221 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9578 12:17:49.728659 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9579 12:17:49.731914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9580 12:17:49.735614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9581 12:17:49.742224 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9582 12:17:49.745458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9583 12:17:49.752211 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9584 12:17:49.755590 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9585 12:17:49.758514 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9586 12:17:49.765703 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9587 12:17:49.769020 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9588 12:17:49.772036 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9589 12:17:49.775325 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9590 12:17:49.782032 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9591 12:17:49.785286 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9592 12:17:49.792052 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9593 12:17:49.795552 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9594 12:17:49.798819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9595 12:17:49.805956 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9596 12:17:49.808708 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9597 12:17:49.815362 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9598 12:17:49.818791 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9599 12:17:49.822451 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9600 12:17:49.828942 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9601 12:17:49.831929 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9602 12:17:49.838828 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9603 12:17:49.842243 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9604 12:17:49.845373 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9605 12:17:49.849286 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9606 12:17:49.855815 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9607 12:17:49.859300 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9608 12:17:49.862325 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9609 12:17:49.868962 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9610 12:17:49.872270 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9611 12:17:49.875743 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9612 12:17:49.879305 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9613 12:17:49.885624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9614 12:17:49.889230 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9615 12:17:49.896216 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9616 12:17:49.899120 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9617 12:17:49.902541 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9618 12:17:49.909162 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9619 12:17:49.912397 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9620 12:17:49.915907 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9621 12:17:49.922321 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9622 12:17:49.925792 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9623 12:17:49.932882 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9624 12:17:49.935664 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9625 12:17:49.938983 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9626 12:17:49.945603 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9627 12:17:49.948696 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9628 12:17:49.955405 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9629 12:17:49.959060 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9630 12:17:49.962632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9631 12:17:49.968803 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9632 12:17:49.972427 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9633 12:17:49.978675 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9634 12:17:49.982142 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9635 12:17:49.985749 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9636 12:17:49.992280 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9637 12:17:49.995796 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9638 12:17:50.002284 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9639 12:17:50.005678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9640 12:17:50.009046 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9641 12:17:50.015661 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9642 12:17:50.019021 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9643 12:17:50.022180 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9644 12:17:50.029168 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9645 12:17:50.032431 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9646 12:17:50.038911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9647 12:17:50.042414 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9648 12:17:50.045396 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9649 12:17:50.051916 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9650 12:17:50.055270 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9651 12:17:50.061833 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9652 12:17:50.065482 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9653 12:17:50.068726 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9654 12:17:50.075643 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9655 12:17:50.078894 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9656 12:17:50.082298 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9657 12:17:50.088616 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9658 12:17:50.092184 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9659 12:17:50.098333 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9660 12:17:50.101804 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9661 12:17:50.104918 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9662 12:17:50.111989 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9663 12:17:50.114963 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9664 12:17:50.121748 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9665 12:17:50.125103 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9666 12:17:50.128197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9667 12:17:50.135026 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9668 12:17:50.138146 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9669 12:17:50.145212 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9670 12:17:50.148211 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9671 12:17:50.151607 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9672 12:17:50.158198 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9673 12:17:50.161744 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9674 12:17:50.168145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9675 12:17:50.171828 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9676 12:17:50.174484 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9677 12:17:50.181414 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9678 12:17:50.184860 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9679 12:17:50.191107 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9680 12:17:50.194598 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9681 12:17:50.197893 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9682 12:17:50.204714 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9683 12:17:50.207755 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9684 12:17:50.214414 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9685 12:17:50.218001 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9686 12:17:50.224209 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9687 12:17:50.227620 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9688 12:17:50.230809 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9689 12:17:50.237464 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9690 12:17:50.241404 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9691 12:17:50.247484 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9692 12:17:50.251287 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9693 12:17:50.254492 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9694 12:17:50.261150 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9695 12:17:50.264559 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9696 12:17:50.271181 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9697 12:17:50.274007 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9698 12:17:50.280826 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9699 12:17:50.284169 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9700 12:17:50.287283 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9701 12:17:50.293896 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9702 12:17:50.297294 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9703 12:17:50.304391 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9704 12:17:50.307376 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9705 12:17:50.313874 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9706 12:17:50.317514 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9707 12:17:50.320494 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9708 12:17:50.326910 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9709 12:17:50.330895 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9710 12:17:50.336986 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9711 12:17:50.340686 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9712 12:17:50.343774 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9713 12:17:50.350513 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9714 12:17:50.354136 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9715 12:17:50.360298 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9716 12:17:50.364034 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9717 12:17:50.366954 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9718 12:17:50.373858 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9719 12:17:50.377073 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9720 12:17:50.380314 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9721 12:17:50.383826 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9722 12:17:50.390496 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9723 12:17:50.393591 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9724 12:17:50.397366 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9725 12:17:50.403855 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9726 12:17:50.406794 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9727 12:17:50.410183 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9728 12:17:50.416873 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9729 12:17:50.420570 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9730 12:17:50.426700 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9731 12:17:50.430241 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9732 12:17:50.433216 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9733 12:17:50.439827 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9734 12:17:50.443140 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9735 12:17:50.446665 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9736 12:17:50.453312 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9737 12:17:50.456934 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9738 12:17:50.460092 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9739 12:17:50.466242 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9740 12:17:50.470356 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9741 12:17:50.476650 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9742 12:17:50.480048 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9743 12:17:50.482987 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9744 12:17:50.489596 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9745 12:17:50.493497 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9746 12:17:50.499463 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9747 12:17:50.503014 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9748 12:17:50.506591 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9749 12:17:50.512949 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9750 12:17:50.516092 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9751 12:17:50.519233 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9752 12:17:50.526040 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9753 12:17:50.529526 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9754 12:17:50.532397 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9755 12:17:50.539565 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9756 12:17:50.543178 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9757 12:17:50.546356 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9758 12:17:50.552866 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9759 12:17:50.555914 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9760 12:17:50.559489 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9761 12:17:50.562741 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9762 12:17:50.565811 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9763 12:17:50.572360 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9764 12:17:50.575570 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9765 12:17:50.578852 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9766 12:17:50.585664 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9767 12:17:50.588960 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9768 12:17:50.592593 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9769 12:17:50.595696 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9770 12:17:50.602092 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9771 12:17:50.605693 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9772 12:17:50.612010 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9773 12:17:50.615413 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9774 12:17:50.618969 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9775 12:17:50.625302 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9776 12:17:50.628749 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9777 12:17:50.635773 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9778 12:17:50.638770 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9779 12:17:50.642385 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9780 12:17:50.648948 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9781 12:17:50.652299 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9782 12:17:50.659001 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9783 12:17:50.661773 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9784 12:17:50.668655 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9785 12:17:50.671941 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9786 12:17:50.675584 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9787 12:17:50.682378 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9788 12:17:50.685310 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9789 12:17:50.688715 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9790 12:17:50.695602 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9791 12:17:50.698916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9792 12:17:50.705676 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9793 12:17:50.708471 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9794 12:17:50.711986 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9795 12:17:50.718708 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9796 12:17:50.721903 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9797 12:17:50.728812 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9798 12:17:50.731718 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9799 12:17:50.738192 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9800 12:17:50.741563 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9801 12:17:50.748089 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9802 12:17:50.751646 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9803 12:17:50.754571 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9804 12:17:50.761715 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9805 12:17:50.765179 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9806 12:17:50.771262 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9807 12:17:50.774798 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9808 12:17:50.777970 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9809 12:17:50.784758 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9810 12:17:50.788009 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9811 12:17:50.794671 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9812 12:17:50.798162 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9813 12:17:50.801551 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9814 12:17:50.808144 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9815 12:17:50.811686 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9816 12:17:50.818230 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9817 12:17:50.821446 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9818 12:17:50.824193 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9819 12:17:50.830910 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9820 12:17:50.834283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9821 12:17:50.841095 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9822 12:17:50.844128 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9823 12:17:50.851125 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9824 12:17:50.854110 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9825 12:17:50.857317 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9826 12:17:50.864567 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9827 12:17:50.867487 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9828 12:17:50.874176 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9829 12:17:50.877596 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9830 12:17:50.880900 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9831 12:17:50.887332 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9832 12:17:50.890897 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9833 12:17:50.897210 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9834 12:17:50.900813 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9835 12:17:50.904170 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9836 12:17:50.910387 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9837 12:17:50.913696 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9838 12:17:50.920556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9839 12:17:50.924044 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9840 12:17:50.930325 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9841 12:17:50.933843 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9842 12:17:50.936942 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9843 12:17:50.944221 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9844 12:17:50.947034 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9845 12:17:50.953655 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9846 12:17:50.956827 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9847 12:17:50.963448 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9848 12:17:50.966710 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9849 12:17:50.970407 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9850 12:17:50.976631 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9851 12:17:50.980011 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9852 12:17:50.987139 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9853 12:17:50.990573 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9854 12:17:50.996989 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9855 12:17:50.999896 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9856 12:17:51.003546 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9857 12:17:51.010136 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9858 12:17:51.013456 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9859 12:17:51.019818 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9860 12:17:51.023276 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9861 12:17:51.029902 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9862 12:17:51.033358 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9863 12:17:51.036518 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9864 12:17:51.043157 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9865 12:17:51.046298 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9866 12:17:51.052891 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9867 12:17:51.056370 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9868 12:17:51.063021 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9869 12:17:51.066117 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9870 12:17:51.073112 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9871 12:17:51.076137 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9872 12:17:51.079571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9873 12:17:51.086143 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9874 12:17:51.089689 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9875 12:17:51.096521 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9876 12:17:51.099320 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9877 12:17:51.105884 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9878 12:17:51.109255 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9879 12:17:51.112921 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9880 12:17:51.119567 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9881 12:17:51.122783 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9882 12:17:51.129218 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9883 12:17:51.133167 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9884 12:17:51.139192 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9885 12:17:51.142987 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9886 12:17:51.145886 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9887 12:17:51.152796 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9888 12:17:51.155955 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9889 12:17:51.163020 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9890 12:17:51.166013 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9891 12:17:51.169335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9892 12:17:51.176333 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9893 12:17:51.179178 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9894 12:17:51.185759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9895 12:17:51.189097 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9896 12:17:51.195457 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9897 12:17:51.199019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9898 12:17:51.205463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9899 12:17:51.209145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9900 12:17:51.215325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9901 12:17:51.218982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9902 12:17:51.225302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9903 12:17:51.228876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9904 12:17:51.235270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9905 12:17:51.238557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9906 12:17:51.245354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9907 12:17:51.248830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9908 12:17:51.255302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9909 12:17:51.258350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9910 12:17:51.265383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9911 12:17:51.268386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9912 12:17:51.275027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9913 12:17:51.278241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9914 12:17:51.284817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9915 12:17:51.288274 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9916 12:17:51.294786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9917 12:17:51.298208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9918 12:17:51.304803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9919 12:17:51.308359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9920 12:17:51.315053 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9921 12:17:51.318505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9922 12:17:51.325050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9923 12:17:51.328645 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9924 12:17:51.331285 INFO: [APUAPC] vio 0
9925 12:17:51.334972 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9926 12:17:51.338291 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9927 12:17:51.341555 INFO: [APUAPC] D0_APC_0: 0x400510
9928 12:17:51.344825 INFO: [APUAPC] D0_APC_1: 0x0
9929 12:17:51.348133 INFO: [APUAPC] D0_APC_2: 0x1540
9930 12:17:51.351288 INFO: [APUAPC] D0_APC_3: 0x0
9931 12:17:51.354787 INFO: [APUAPC] D1_APC_0: 0xffffffff
9932 12:17:51.358326 INFO: [APUAPC] D1_APC_1: 0xffffffff
9933 12:17:51.361168 INFO: [APUAPC] D1_APC_2: 0x3fffff
9934 12:17:51.365082 INFO: [APUAPC] D1_APC_3: 0x0
9935 12:17:51.367946 INFO: [APUAPC] D2_APC_0: 0xffffffff
9936 12:17:51.371263 INFO: [APUAPC] D2_APC_1: 0xffffffff
9937 12:17:51.374674 INFO: [APUAPC] D2_APC_2: 0x3fffff
9938 12:17:51.377882 INFO: [APUAPC] D2_APC_3: 0x0
9939 12:17:51.381147 INFO: [APUAPC] D3_APC_0: 0xffffffff
9940 12:17:51.385218 INFO: [APUAPC] D3_APC_1: 0xffffffff
9941 12:17:51.388129 INFO: [APUAPC] D3_APC_2: 0x3fffff
9942 12:17:51.391494 INFO: [APUAPC] D3_APC_3: 0x0
9943 12:17:51.394668 INFO: [APUAPC] D4_APC_0: 0xffffffff
9944 12:17:51.398041 INFO: [APUAPC] D4_APC_1: 0xffffffff
9945 12:17:51.401528 INFO: [APUAPC] D4_APC_2: 0x3fffff
9946 12:17:51.404486 INFO: [APUAPC] D4_APC_3: 0x0
9947 12:17:51.408303 INFO: [APUAPC] D5_APC_0: 0xffffffff
9948 12:17:51.411269 INFO: [APUAPC] D5_APC_1: 0xffffffff
9949 12:17:51.414516 INFO: [APUAPC] D5_APC_2: 0x3fffff
9950 12:17:51.418105 INFO: [APUAPC] D5_APC_3: 0x0
9951 12:17:51.421314 INFO: [APUAPC] D6_APC_0: 0xffffffff
9952 12:17:51.424641 INFO: [APUAPC] D6_APC_1: 0xffffffff
9953 12:17:51.427661 INFO: [APUAPC] D6_APC_2: 0x3fffff
9954 12:17:51.431675 INFO: [APUAPC] D6_APC_3: 0x0
9955 12:17:51.434436 INFO: [APUAPC] D7_APC_0: 0xffffffff
9956 12:17:51.437958 INFO: [APUAPC] D7_APC_1: 0xffffffff
9957 12:17:51.441258 INFO: [APUAPC] D7_APC_2: 0x3fffff
9958 12:17:51.441361 INFO: [APUAPC] D7_APC_3: 0x0
9959 12:17:51.447732 INFO: [APUAPC] D8_APC_0: 0xffffffff
9960 12:17:51.451539 INFO: [APUAPC] D8_APC_1: 0xffffffff
9961 12:17:51.454420 INFO: [APUAPC] D8_APC_2: 0x3fffff
9962 12:17:51.454503 INFO: [APUAPC] D8_APC_3: 0x0
9963 12:17:51.458041 INFO: [APUAPC] D9_APC_0: 0xffffffff
9964 12:17:51.461115 INFO: [APUAPC] D9_APC_1: 0xffffffff
9965 12:17:51.464710 INFO: [APUAPC] D9_APC_2: 0x3fffff
9966 12:17:51.467838 INFO: [APUAPC] D9_APC_3: 0x0
9967 12:17:51.471339 INFO: [APUAPC] D10_APC_0: 0xffffffff
9968 12:17:51.474167 INFO: [APUAPC] D10_APC_1: 0xffffffff
9969 12:17:51.478352 INFO: [APUAPC] D10_APC_2: 0x3fffff
9970 12:17:51.481117 INFO: [APUAPC] D10_APC_3: 0x0
9971 12:17:51.484638 INFO: [APUAPC] D11_APC_0: 0xffffffff
9972 12:17:51.487896 INFO: [APUAPC] D11_APC_1: 0xffffffff
9973 12:17:51.491285 INFO: [APUAPC] D11_APC_2: 0x3fffff
9974 12:17:51.494389 INFO: [APUAPC] D11_APC_3: 0x0
9975 12:17:51.497869 INFO: [APUAPC] D12_APC_0: 0xffffffff
9976 12:17:51.504518 INFO: [APUAPC] D12_APC_1: 0xffffffff
9977 12:17:51.507238 INFO: [APUAPC] D12_APC_2: 0x3fffff
9978 12:17:51.507342 INFO: [APUAPC] D12_APC_3: 0x0
9979 12:17:51.514034 INFO: [APUAPC] D13_APC_0: 0xffffffff
9980 12:17:51.517282 INFO: [APUAPC] D13_APC_1: 0xffffffff
9981 12:17:51.521039 INFO: [APUAPC] D13_APC_2: 0x3fffff
9982 12:17:51.521144 INFO: [APUAPC] D13_APC_3: 0x0
9983 12:17:51.527772 INFO: [APUAPC] D14_APC_0: 0xffffffff
9984 12:17:51.530452 INFO: [APUAPC] D14_APC_1: 0xffffffff
9985 12:17:51.533912 INFO: [APUAPC] D14_APC_2: 0x3fffff
9986 12:17:51.537229 INFO: [APUAPC] D14_APC_3: 0x0
9987 12:17:51.540178 INFO: [APUAPC] D15_APC_0: 0xffffffff
9988 12:17:51.543773 INFO: [APUAPC] D15_APC_1: 0xffffffff
9989 12:17:51.546839 INFO: [APUAPC] D15_APC_2: 0x3fffff
9990 12:17:51.550071 INFO: [APUAPC] D15_APC_3: 0x0
9991 12:17:51.550174 INFO: [APUAPC] APC_CON: 0x4
9992 12:17:51.553504 INFO: [NOCDAPC] D0_APC_0: 0x0
9993 12:17:51.556975 INFO: [NOCDAPC] D0_APC_1: 0x0
9994 12:17:51.560446 INFO: [NOCDAPC] D1_APC_0: 0x0
9995 12:17:51.563565 INFO: [NOCDAPC] D1_APC_1: 0xfff
9996 12:17:51.566842 INFO: [NOCDAPC] D2_APC_0: 0x0
9997 12:17:51.570507 INFO: [NOCDAPC] D2_APC_1: 0xfff
9998 12:17:51.573329 INFO: [NOCDAPC] D3_APC_0: 0x0
9999 12:17:51.576712 INFO: [NOCDAPC] D3_APC_1: 0xfff
10000 12:17:51.580393 INFO: [NOCDAPC] D4_APC_0: 0x0
10001 12:17:51.580501 INFO: [NOCDAPC] D4_APC_1: 0xfff
10002 12:17:51.583715 INFO: [NOCDAPC] D5_APC_0: 0x0
10003 12:17:51.586617 INFO: [NOCDAPC] D5_APC_1: 0xfff
10004 12:17:51.590345 INFO: [NOCDAPC] D6_APC_0: 0x0
10005 12:17:51.593351 INFO: [NOCDAPC] D6_APC_1: 0xfff
10006 12:17:51.596842 INFO: [NOCDAPC] D7_APC_0: 0x0
10007 12:17:51.599861 INFO: [NOCDAPC] D7_APC_1: 0xfff
10008 12:17:51.603458 INFO: [NOCDAPC] D8_APC_0: 0x0
10009 12:17:51.606794 INFO: [NOCDAPC] D8_APC_1: 0xfff
10010 12:17:51.609753 INFO: [NOCDAPC] D9_APC_0: 0x0
10011 12:17:51.613275 INFO: [NOCDAPC] D9_APC_1: 0xfff
10012 12:17:51.613381 INFO: [NOCDAPC] D10_APC_0: 0x0
10013 12:17:51.616446 INFO: [NOCDAPC] D10_APC_1: 0xfff
10014 12:17:51.620161 INFO: [NOCDAPC] D11_APC_0: 0x0
10015 12:17:51.623618 INFO: [NOCDAPC] D11_APC_1: 0xfff
10016 12:17:51.626586 INFO: [NOCDAPC] D12_APC_0: 0x0
10017 12:17:51.630031 INFO: [NOCDAPC] D12_APC_1: 0xfff
10018 12:17:51.632942 INFO: [NOCDAPC] D13_APC_0: 0x0
10019 12:17:51.636019 INFO: [NOCDAPC] D13_APC_1: 0xfff
10020 12:17:51.639499 INFO: [NOCDAPC] D14_APC_0: 0x0
10021 12:17:51.642997 INFO: [NOCDAPC] D14_APC_1: 0xfff
10022 12:17:51.646233 INFO: [NOCDAPC] D15_APC_0: 0x0
10023 12:17:51.649611 INFO: [NOCDAPC] D15_APC_1: 0xfff
10024 12:17:51.652567 INFO: [NOCDAPC] APC_CON: 0x4
10025 12:17:51.656104 INFO: [APUAPC] set_apusys_apc done
10026 12:17:51.659694 INFO: [DEVAPC] devapc_init done
10027 12:17:51.662835 INFO: GICv3 without legacy support detected.
10028 12:17:51.666118 INFO: ARM GICv3 driver initialized in EL3
10029 12:17:51.669235 INFO: Maximum SPI INTID supported: 639
10030 12:17:51.672755 INFO: BL31: Initializing runtime services
10031 12:17:51.679376 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10032 12:17:51.682460 INFO: SPM: enable CPC mode
10033 12:17:51.689184 INFO: mcdi ready for mcusys-off-idle and system suspend
10034 12:17:51.692954 INFO: BL31: Preparing for EL3 exit to normal world
10035 12:17:51.695662 INFO: Entry point address = 0x80000000
10036 12:17:51.699705 INFO: SPSR = 0x8
10037 12:17:51.704217
10038 12:17:51.704311
10039 12:17:51.704402
10040 12:17:51.707245 Starting depthcharge on Spherion...
10041 12:17:51.707344
10042 12:17:51.707464 Wipe memory regions:
10043 12:17:51.707525
10044 12:17:51.708342 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10045 12:17:51.708503 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10046 12:17:51.708638 Setting prompt string to ['asurada:']
10047 12:17:51.708753 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10048 12:17:51.710668 [0x00000040000000, 0x00000054600000)
10049 12:17:51.833352
10050 12:17:51.833513 [0x00000054660000, 0x00000080000000)
10051 12:17:52.093878
10052 12:17:52.094043 [0x000000821a7280, 0x000000ffe64000)
10053 12:17:52.838198
10054 12:17:52.838356 [0x00000100000000, 0x00000240000000)
10055 12:17:54.728545
10056 12:17:54.731933 Initializing XHCI USB controller at 0x11200000.
10057 12:17:55.770997
10058 12:17:55.773678 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10059 12:17:55.773791
10060 12:17:55.773882
10061 12:17:55.773976
10062 12:17:55.774290 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10064 12:17:55.874649 asurada: tftpboot 192.168.201.1 11893121/tftp-deploy-10zv6gap/kernel/image.itb 11893121/tftp-deploy-10zv6gap/kernel/cmdline
10065 12:17:55.874789 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 12:17:55.874885 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10067 12:17:55.878850 tftpboot 192.168.201.1 11893121/tftp-deploy-10zv6gap/kernel/image.ittp-deploy-10zv6gap/kernel/cmdline
10068 12:17:55.878936
10069 12:17:55.879005 Waiting for link
10070 12:17:56.039556
10071 12:17:56.039684 R8152: Initializing
10072 12:17:56.039755
10073 12:17:56.043149 Version 6 (ocp_data = 5c30)
10074 12:17:56.043253
10075 12:17:56.046315 R8152: Done initializing
10076 12:17:56.046420
10077 12:17:56.046522 Adding net device
10078 12:17:58.013140
10079 12:17:58.013315 done.
10080 12:17:58.013418
10081 12:17:58.013519 MAC: 00:24:32:30:78:ff
10082 12:17:58.013619
10083 12:17:58.016502 Sending DHCP discover... done.
10084 12:17:58.016590
10085 12:17:58.019484 Waiting for reply... done.
10086 12:17:58.019589
10087 12:17:58.023348 Sending DHCP request... done.
10088 12:17:58.023476
10089 12:17:58.023585 Waiting for reply... done.
10090 12:17:58.023685
10091 12:17:58.026261 My ip is 192.168.201.21
10092 12:17:58.026363
10093 12:17:58.029624 The DHCP server ip is 192.168.201.1
10094 12:17:58.029732
10095 12:17:58.032950 TFTP server IP predefined by user: 192.168.201.1
10096 12:17:58.033054
10097 12:17:58.039868 Bootfile predefined by user: 11893121/tftp-deploy-10zv6gap/kernel/image.itb
10098 12:17:58.039958
10099 12:17:58.042999 Sending tftp read request... done.
10100 12:17:58.043081
10101 12:17:58.046141 Waiting for the transfer...
10102 12:17:58.046225
10103 12:17:58.599092 00000000 ################################################################
10104 12:17:58.599227
10105 12:17:59.143125 00080000 ################################################################
10106 12:17:59.143265
10107 12:17:59.680378 00100000 ################################################################
10108 12:17:59.680544
10109 12:18:00.211954 00180000 ################################################################
10110 12:18:00.212100
10111 12:18:00.747976 00200000 ################################################################
10112 12:18:00.748129
10113 12:18:01.292084 00280000 ################################################################
10114 12:18:01.292229
10115 12:18:01.830946 00300000 ################################################################
10116 12:18:01.831088
10117 12:18:02.365565 00380000 ################################################################
10118 12:18:02.365701
10119 12:18:02.917074 00400000 ################################################################
10120 12:18:02.917224
10121 12:18:03.454385 00480000 ################################################################
10122 12:18:03.454549
10123 12:18:04.020808 00500000 ################################################################
10124 12:18:04.020948
10125 12:18:04.574579 00580000 ################################################################
10126 12:18:04.574753
10127 12:18:05.171378 00600000 ################################################################
10128 12:18:05.171637
10129 12:18:05.773736 00680000 ################################################################
10130 12:18:05.773890
10131 12:18:06.330420 00700000 ################################################################
10132 12:18:06.330560
10133 12:18:06.897227 00780000 ################################################################
10134 12:18:06.897366
10135 12:18:07.443890 00800000 ################################################################
10136 12:18:07.444059
10137 12:18:07.997864 00880000 ################################################################
10138 12:18:07.998002
10139 12:18:08.581514 00900000 ################################################################
10140 12:18:08.581648
10141 12:18:09.151743 00980000 ################################################################
10142 12:18:09.152163
10143 12:18:09.836363 00a00000 ################################################################
10144 12:18:09.836918
10145 12:18:10.542562 00a80000 ################################################################
10146 12:18:10.543208
10147 12:18:11.236028 00b00000 ################################################################
10148 12:18:11.236617
10149 12:18:11.949972 00b80000 ################################################################
10150 12:18:11.950517
10151 12:18:12.650706 00c00000 ################################################################
10152 12:18:12.651343
10153 12:18:13.354390 00c80000 ################################################################
10154 12:18:13.354976
10155 12:18:14.067448 00d00000 ################################################################
10156 12:18:14.068019
10157 12:18:14.782128 00d80000 ################################################################
10158 12:18:14.782747
10159 12:18:15.495482 00e00000 ################################################################
10160 12:18:15.496081
10161 12:18:16.213419 00e80000 ################################################################
10162 12:18:16.213985
10163 12:18:16.929214 00f00000 ################################################################
10164 12:18:16.929762
10165 12:18:17.614625 00f80000 ################################################################
10166 12:18:17.615315
10167 12:18:18.314987 01000000 ################################################################
10168 12:18:18.315555
10169 12:18:19.020606 01080000 ################################################################
10170 12:18:19.021217
10171 12:18:19.733793 01100000 ################################################################
10172 12:18:19.734322
10173 12:18:20.409310 01180000 ################################################################
10174 12:18:20.409447
10175 12:18:21.029085 01200000 ################################################################
10176 12:18:21.029632
10177 12:18:21.710625 01280000 ################################################################
10178 12:18:21.710769
10179 12:18:22.335215 01300000 ################################################################
10180 12:18:22.335382
10181 12:18:22.940839 01380000 ################################################################
10182 12:18:22.941006
10183 12:18:23.489237 01400000 ################################################################
10184 12:18:23.489387
10185 12:18:24.035927 01480000 ################################################################
10186 12:18:24.036065
10187 12:18:24.627624 01500000 ################################################################
10188 12:18:24.627769
10189 12:18:25.225928 01580000 ################################################################
10190 12:18:25.226062
10191 12:18:25.798851 01600000 ################################################################
10192 12:18:25.798988
10193 12:18:26.341338 01680000 ################################################################
10194 12:18:26.341509
10195 12:18:26.891067 01700000 ################################################################
10196 12:18:26.891251
10197 12:18:27.440719 01780000 ################################################################
10198 12:18:27.440871
10199 12:18:28.002167 01800000 ################################################################
10200 12:18:28.002306
10201 12:18:28.549378 01880000 ################################################################
10202 12:18:28.549517
10203 12:18:29.092825 01900000 ################################################################
10204 12:18:29.092967
10205 12:18:29.641385 01980000 ################################################################
10206 12:18:29.641523
10207 12:18:30.174826 01a00000 ################################################################
10208 12:18:30.174963
10209 12:18:30.719924 01a80000 ################################################################
10210 12:18:30.720087
10211 12:18:31.273696 01b00000 ################################################################
10212 12:18:31.273833
10213 12:18:31.813112 01b80000 ################################################################
10214 12:18:31.813254
10215 12:18:32.342245 01c00000 ################################################################
10216 12:18:32.342442
10217 12:18:32.884132 01c80000 ################################################################
10218 12:18:32.884273
10219 12:18:33.430989 01d00000 ################################################################
10220 12:18:33.431163
10221 12:18:33.983375 01d80000 ################################################################
10222 12:18:33.983522
10223 12:18:34.536498 01e00000 ################################################################
10224 12:18:34.536667
10225 12:18:35.148817 01e80000 ################################################################
10226 12:18:35.149539
10227 12:18:35.732205 01f00000 ################################################################
10228 12:18:35.732339
10229 12:18:36.302836 01f80000 ################################################################
10230 12:18:36.302972
10231 12:18:36.931994 02000000 ################################################################
10232 12:18:36.932557
10233 12:18:37.539076 02080000 ################################################################
10234 12:18:37.539271
10235 12:18:38.106106 02100000 ################################################################
10236 12:18:38.106242
10237 12:18:38.700588 02180000 ################################################################
10238 12:18:38.700735
10239 12:18:39.316284 02200000 ################################################################
10240 12:18:39.316839
10241 12:18:40.017363 02280000 ################################################################
10242 12:18:40.017881
10243 12:18:40.716889 02300000 ################################################################
10244 12:18:40.717400
10245 12:18:41.420002 02380000 ################################################################
10246 12:18:41.420518
10247 12:18:42.062451 02400000 ################################################################
10248 12:18:42.063068
10249 12:18:42.776553 02480000 ################################################################
10250 12:18:42.777147
10251 12:18:43.405589 02500000 ################################################################
10252 12:18:43.405811
10253 12:18:43.966219 02580000 ################################################################
10254 12:18:43.966368
10255 12:18:44.596624 02600000 ################################################################
10256 12:18:44.597141
10257 12:18:45.225590 02680000 ################################################################
10258 12:18:45.226085
10259 12:18:45.912271 02700000 ################################################################
10260 12:18:45.912780
10261 12:18:46.544773 02780000 ################################################################
10262 12:18:46.544920
10263 12:18:47.130962 02800000 ################################################################
10264 12:18:47.131455
10265 12:18:47.823310 02880000 ################################################################
10266 12:18:47.823863
10267 12:18:48.509241 02900000 ################################################################
10268 12:18:48.509785
10269 12:18:49.218910 02980000 ################################################################
10270 12:18:49.219456
10271 12:18:49.911880 02a00000 ################################################################
10272 12:18:49.912386
10273 12:18:50.599874 02a80000 ################################################################
10274 12:18:50.600387
10275 12:18:51.287628 02b00000 ################################################################
10276 12:18:51.288252
10277 12:18:51.967288 02b80000 ################################################################
10278 12:18:51.967863
10279 12:18:52.638614 02c00000 ################################################################
10280 12:18:52.639175
10281 12:18:53.307255 02c80000 ################################################################
10282 12:18:53.307880
10283 12:18:53.989162 02d00000 ################################################################
10284 12:18:53.989756
10285 12:18:54.662357 02d80000 ################################################################
10286 12:18:54.662910
10287 12:18:55.339881 02e00000 ################################################################
10288 12:18:55.340417
10289 12:18:56.032863 02e80000 ################################################################
10290 12:18:56.033433
10291 12:18:56.680470 02f00000 ################################################################
10292 12:18:56.680619
10293 12:18:57.260376 02f80000 ################################################################
10294 12:18:57.260517
10295 12:18:57.900769 03000000 ################################################################
10296 12:18:57.900919
10297 12:18:58.520812 03080000 ################################################################
10298 12:18:58.521374
10299 12:18:59.193171 03100000 ################################################################
10300 12:18:59.193715
10301 12:18:59.878072 03180000 ################################################################
10302 12:18:59.878582
10303 12:19:00.587292 03200000 ################################################################
10304 12:19:00.587856
10305 12:19:01.267154 03280000 ################################################################
10306 12:19:01.267759
10307 12:19:01.938812 03300000 ################################################################
10308 12:19:01.939334
10309 12:19:02.636542 03380000 ################################################################
10310 12:19:02.637129
10311 12:19:03.316601 03400000 ################################################################
10312 12:19:03.317115
10313 12:19:03.996924 03480000 ################################################################
10314 12:19:03.997489
10315 12:19:04.673668 03500000 ################################################################
10316 12:19:04.674183
10317 12:19:05.355303 03580000 ################################################################
10318 12:19:05.355850
10319 12:19:06.027334 03600000 ################################################################
10320 12:19:06.027933
10321 12:19:06.695185 03680000 ################################################################
10322 12:19:06.695832
10323 12:19:07.383432 03700000 ################################################################
10324 12:19:07.383959
10325 12:19:08.074509 03780000 ################################################################
10326 12:19:08.075022
10327 12:19:08.760262 03800000 ################################################################
10328 12:19:08.760779
10329 12:19:09.444684 03880000 ################################################################
10330 12:19:09.445190
10331 12:19:10.153040 03900000 ################################################################
10332 12:19:10.153607
10333 12:19:10.843000 03980000 ################################################################
10334 12:19:10.843542
10335 12:19:11.524719 03a00000 ################################################################
10336 12:19:11.525314
10337 12:19:12.222130 03a80000 ################################################################
10338 12:19:12.222663
10339 12:19:12.898647 03b00000 ################################################################
10340 12:19:12.899208
10341 12:19:13.518485 03b80000 ################################################################
10342 12:19:13.518631
10343 12:19:14.152867 03c00000 ################################################################
10344 12:19:14.153409
10345 12:19:14.763580 03c80000 ################################################################
10346 12:19:14.763721
10347 12:19:15.341188 03d00000 ################################################################
10348 12:19:15.341328
10349 12:19:15.915298 03d80000 ################################################################
10350 12:19:15.915486
10351 12:19:16.479631 03e00000 ################################################################
10352 12:19:16.479787
10353 12:19:17.045178 03e80000 ################################################################
10354 12:19:17.045330
10355 12:19:17.617000 03f00000 ################################################################
10356 12:19:17.617150
10357 12:19:18.188967 03f80000 ################################################################
10358 12:19:18.189109
10359 12:19:18.628615 04000000 ################################################# done.
10360 12:19:18.628765
10361 12:19:18.631988 The bootfile was 67507730 bytes long.
10362 12:19:18.632077
10363 12:19:18.635016 Sending tftp read request... done.
10364 12:19:18.635099
10365 12:19:18.635207 Waiting for the transfer...
10366 12:19:18.635270
10367 12:19:18.638213 00000000 # done.
10368 12:19:18.638298
10369 12:19:18.644815 Command line loaded dynamically from TFTP file: 11893121/tftp-deploy-10zv6gap/kernel/cmdline
10370 12:19:18.644899
10371 12:19:18.657904 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10372 12:19:18.657998
10373 12:19:18.661665 Loading FIT.
10374 12:19:18.661749
10375 12:19:18.664580 Image ramdisk-1 has 56410424 bytes.
10376 12:19:18.664664
10377 12:19:18.667881 Image fdt-1 has 47278 bytes.
10378 12:19:18.667964
10379 12:19:18.668029 Image kernel-1 has 11047994 bytes.
10380 12:19:18.671688
10381 12:19:18.678134 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10382 12:19:18.678217
10383 12:19:18.694778 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10384 12:19:18.694873
10385 12:19:18.701270 Choosing best match conf-1 for compat google,spherion-rev2.
10386 12:19:18.705659
10387 12:19:18.710374 Connected to device vid:did:rid of 1ae0:0028:00
10388 12:19:18.718305
10389 12:19:18.721505 tpm_get_response: command 0x17b, return code 0x0
10390 12:19:18.721592
10391 12:19:18.724956 ec_init: CrosEC protocol v3 supported (256, 248)
10392 12:19:18.729032
10393 12:19:18.732214 tpm_cleanup: add release locality here.
10394 12:19:18.732299
10395 12:19:18.732383 Shutting down all USB controllers.
10396 12:19:18.735675
10397 12:19:18.735759 Removing current net device
10398 12:19:18.735843
10399 12:19:18.742664 Exiting depthcharge with code 4 at timestamp: 116365481
10400 12:19:18.742748
10401 12:19:18.745677 LZMA decompressing kernel-1 to 0x821a6718
10402 12:19:18.745761
10403 12:19:18.748748 LZMA decompressing kernel-1 to 0x40000000
10404 12:19:20.138753
10405 12:19:20.138904 jumping to kernel
10406 12:19:20.139491 end: 2.2.4 bootloader-commands (duration 00:01:28) [common]
10407 12:19:20.139602 start: 2.2.5 auto-login-action (timeout 00:02:57) [common]
10408 12:19:20.139688 Setting prompt string to ['Linux version [0-9]']
10409 12:19:20.139773 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10410 12:19:20.139856 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10411 12:19:20.220034
10412 12:19:20.223053 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10413 12:19:20.226396 start: 2.2.5.1 login-action (timeout 00:02:57) [common]
10414 12:19:20.226519 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10415 12:19:20.226621 Setting prompt string to []
10416 12:19:20.226731 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10417 12:19:20.226840 Using line separator: #'\n'#
10418 12:19:20.226930 No login prompt set.
10419 12:19:20.227026 Parsing kernel messages
10420 12:19:20.227114 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10421 12:19:20.227271 [login-action] Waiting for messages, (timeout 00:02:57)
10422 12:19:20.246482 [ 0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023
10423 12:19:20.249787 [ 0.000000] random: crng init done
10424 12:19:20.256133 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10425 12:19:20.256241 [ 0.000000] efi: UEFI not found.
10426 12:19:20.266319 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10427 12:19:20.273159 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10428 12:19:20.283033 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10429 12:19:20.292695 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10430 12:19:20.299190 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10431 12:19:20.302480 [ 0.000000] printk: bootconsole [mtk8250] enabled
10432 12:19:20.311781 [ 0.000000] NUMA: No NUMA configuration found
10433 12:19:20.318059 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10434 12:19:20.324530 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10435 12:19:20.324642 [ 0.000000] Zone ranges:
10436 12:19:20.331062 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10437 12:19:20.334341 [ 0.000000] DMA32 empty
10438 12:19:20.341177 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10439 12:19:20.344664 [ 0.000000] Movable zone start for each node
10440 12:19:20.348184 [ 0.000000] Early memory node ranges
10441 12:19:20.354558 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10442 12:19:20.360911 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10443 12:19:20.367576 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10444 12:19:20.374203 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10445 12:19:20.380691 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10446 12:19:20.387267 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10447 12:19:20.443931 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10448 12:19:20.451073 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10449 12:19:20.457452 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10450 12:19:20.460586 [ 0.000000] psci: probing for conduit method from DT.
10451 12:19:20.467133 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10452 12:19:20.470353 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10453 12:19:20.477014 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10454 12:19:20.480349 [ 0.000000] psci: SMC Calling Convention v1.2
10455 12:19:20.487353 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10456 12:19:20.490637 [ 0.000000] Detected VIPT I-cache on CPU0
10457 12:19:20.497013 [ 0.000000] CPU features: detected: GIC system register CPU interface
10458 12:19:20.503685 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10459 12:19:20.510280 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10460 12:19:20.516861 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10461 12:19:20.523348 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10462 12:19:20.533130 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10463 12:19:20.536892 [ 0.000000] alternatives: applying boot alternatives
10464 12:19:20.543123 [ 0.000000] Fallback order for Node 0: 0
10465 12:19:20.549859 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10466 12:19:20.553103 [ 0.000000] Policy zone: Normal
10467 12:19:20.566308 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10468 12:19:20.576407 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10469 12:19:20.587052 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10470 12:19:20.597116 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10471 12:19:20.603601 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10472 12:19:20.606562 <6>[ 0.000000] software IO TLB: area num 8.
10473 12:19:20.663526 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10474 12:19:20.813288 <6>[ 0.000000] Memory: 7914400K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 438368K reserved, 32768K cma-reserved)
10475 12:19:20.819641 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10476 12:19:20.826240 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10477 12:19:20.829656 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10478 12:19:20.836152 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10479 12:19:20.842619 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10480 12:19:20.846050 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10481 12:19:20.855713 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10482 12:19:20.862834 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10483 12:19:20.869526 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10484 12:19:20.876418 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10485 12:19:20.879165 <6>[ 0.000000] GICv3: 608 SPIs implemented
10486 12:19:20.882587 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10487 12:19:20.888912 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10488 12:19:20.892187 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10489 12:19:20.898721 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10490 12:19:20.912508 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10491 12:19:20.925843 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10492 12:19:20.931810 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10493 12:19:20.939341 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10494 12:19:20.952964 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10495 12:19:20.959208 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10496 12:19:20.965774 <6>[ 0.009182] Console: colour dummy device 80x25
10497 12:19:20.976156 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10498 12:19:20.982280 <6>[ 0.024351] pid_max: default: 32768 minimum: 301
10499 12:19:20.985731 <6>[ 0.029222] LSM: Security Framework initializing
10500 12:19:20.992293 <6>[ 0.034159] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10501 12:19:21.002382 <6>[ 0.042020] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10502 12:19:21.012071 <6>[ 0.051440] cblist_init_generic: Setting adjustable number of callback queues.
10503 12:19:21.015618 <6>[ 0.058929] cblist_init_generic: Setting shift to 3 and lim to 1.
10504 12:19:21.025511 <6>[ 0.065268] cblist_init_generic: Setting adjustable number of callback queues.
10505 12:19:21.032039 <6>[ 0.072695] cblist_init_generic: Setting shift to 3 and lim to 1.
10506 12:19:21.035515 <6>[ 0.079096] rcu: Hierarchical SRCU implementation.
10507 12:19:21.042121 <6>[ 0.084143] rcu: Max phase no-delay instances is 1000.
10508 12:19:21.048663 <6>[ 0.091203] EFI services will not be available.
10509 12:19:21.051887 <6>[ 0.096161] smp: Bringing up secondary CPUs ...
10510 12:19:21.060361 <6>[ 0.101242] Detected VIPT I-cache on CPU1
10511 12:19:21.066822 <6>[ 0.101311] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10512 12:19:21.073720 <6>[ 0.101342] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10513 12:19:21.077224 <6>[ 0.101687] Detected VIPT I-cache on CPU2
10514 12:19:21.083884 <6>[ 0.101739] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10515 12:19:21.093684 <6>[ 0.101756] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10516 12:19:21.097127 <6>[ 0.102019] Detected VIPT I-cache on CPU3
10517 12:19:21.103399 <6>[ 0.102066] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10518 12:19:21.110241 <6>[ 0.102080] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10519 12:19:21.113216 <6>[ 0.102386] CPU features: detected: Spectre-v4
10520 12:19:21.119898 <6>[ 0.102392] CPU features: detected: Spectre-BHB
10521 12:19:21.123139 <6>[ 0.102397] Detected PIPT I-cache on CPU4
10522 12:19:21.129549 <6>[ 0.102455] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10523 12:19:21.136265 <6>[ 0.102473] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10524 12:19:21.142761 <6>[ 0.102764] Detected PIPT I-cache on CPU5
10525 12:19:21.149525 <6>[ 0.102828] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10526 12:19:21.156365 <6>[ 0.102844] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10527 12:19:21.159680 <6>[ 0.103127] Detected PIPT I-cache on CPU6
10528 12:19:21.166073 <6>[ 0.103192] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10529 12:19:21.172946 <6>[ 0.103208] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10530 12:19:21.179134 <6>[ 0.103506] Detected PIPT I-cache on CPU7
10531 12:19:21.185720 <6>[ 0.103572] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10532 12:19:21.192935 <6>[ 0.103588] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10533 12:19:21.195928 <6>[ 0.103635] smp: Brought up 1 node, 8 CPUs
10534 12:19:21.202614 <6>[ 0.244984] SMP: Total of 8 processors activated.
10535 12:19:21.205837 <6>[ 0.249905] CPU features: detected: 32-bit EL0 Support
10536 12:19:21.215806 <6>[ 0.255268] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10537 12:19:21.222196 <6>[ 0.264123] CPU features: detected: Common not Private translations
10538 12:19:21.229133 <6>[ 0.270599] CPU features: detected: CRC32 instructions
10539 12:19:21.232572 <6>[ 0.275951] CPU features: detected: RCpc load-acquire (LDAPR)
10540 12:19:21.238740 <6>[ 0.281948] CPU features: detected: LSE atomic instructions
10541 12:19:21.245325 <6>[ 0.287766] CPU features: detected: Privileged Access Never
10542 12:19:21.252077 <6>[ 0.293546] CPU features: detected: RAS Extension Support
10543 12:19:21.258466 <6>[ 0.299155] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10544 12:19:21.262085 <6>[ 0.306423] CPU: All CPU(s) started at EL2
10545 12:19:21.268572 <6>[ 0.310739] alternatives: applying system-wide alternatives
10546 12:19:21.278113 <6>[ 0.321458] devtmpfs: initialized
10547 12:19:21.293397 <6>[ 0.330229] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10548 12:19:21.300039 <6>[ 0.340195] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10549 12:19:21.306500 <6>[ 0.348207] pinctrl core: initialized pinctrl subsystem
10550 12:19:21.310435 <6>[ 0.354886] DMI not present or invalid.
10551 12:19:21.316897 <6>[ 0.359299] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10552 12:19:21.326879 <6>[ 0.366150] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10553 12:19:21.333444 <6>[ 0.373738] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10554 12:19:21.343564 <6>[ 0.381953] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10555 12:19:21.346392 <6>[ 0.390194] audit: initializing netlink subsys (disabled)
10556 12:19:21.356368 <5>[ 0.395888] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10557 12:19:21.362921 <6>[ 0.396598] thermal_sys: Registered thermal governor 'step_wise'
10558 12:19:21.369828 <6>[ 0.403856] thermal_sys: Registered thermal governor 'power_allocator'
10559 12:19:21.373000 <6>[ 0.410111] cpuidle: using governor menu
10560 12:19:21.379343 <6>[ 0.421074] NET: Registered PF_QIPCRTR protocol family
10561 12:19:21.386204 <6>[ 0.426555] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10562 12:19:21.392648 <6>[ 0.433661] ASID allocator initialised with 32768 entries
10563 12:19:21.395981 <6>[ 0.440243] Serial: AMBA PL011 UART driver
10564 12:19:21.405867 <4>[ 0.449064] Trying to register duplicate clock ID: 134
10565 12:19:21.461762 <6>[ 0.508441] KASLR enabled
10566 12:19:21.476606 <6>[ 0.516176] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10567 12:19:21.482884 <6>[ 0.523190] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10568 12:19:21.489223 <6>[ 0.529680] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10569 12:19:21.495930 <6>[ 0.536686] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10570 12:19:21.502643 <6>[ 0.543175] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10571 12:19:21.509077 <6>[ 0.550182] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10572 12:19:21.515789 <6>[ 0.556672] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10573 12:19:21.522487 <6>[ 0.563680] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10574 12:19:21.525619 <6>[ 0.571193] ACPI: Interpreter disabled.
10575 12:19:21.534338 <6>[ 0.577618] iommu: Default domain type: Translated
10576 12:19:21.541181 <6>[ 0.582732] iommu: DMA domain TLB invalidation policy: strict mode
10577 12:19:21.544407 <5>[ 0.589393] SCSI subsystem initialized
10578 12:19:21.550988 <6>[ 0.593576] usbcore: registered new interface driver usbfs
10579 12:19:21.557319 <6>[ 0.599311] usbcore: registered new interface driver hub
10580 12:19:21.560955 <6>[ 0.604863] usbcore: registered new device driver usb
10581 12:19:21.567448 <6>[ 0.610970] pps_core: LinuxPPS API ver. 1 registered
10582 12:19:21.577490 <6>[ 0.616164] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10583 12:19:21.581278 <6>[ 0.625512] PTP clock support registered
10584 12:19:21.584131 <6>[ 0.629755] EDAC MC: Ver: 3.0.0
10585 12:19:21.591635 <6>[ 0.634917] FPGA manager framework
10586 12:19:21.597974 <6>[ 0.638599] Advanced Linux Sound Architecture Driver Initialized.
10587 12:19:21.601580 <6>[ 0.645387] vgaarb: loaded
10588 12:19:21.608088 <6>[ 0.648509] clocksource: Switched to clocksource arch_sys_counter
10589 12:19:21.611631 <5>[ 0.654955] VFS: Disk quotas dquot_6.6.0
10590 12:19:21.618393 <6>[ 0.659142] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10591 12:19:21.621553 <6>[ 0.666333] pnp: PnP ACPI: disabled
10592 12:19:21.629900 <6>[ 0.673032] NET: Registered PF_INET protocol family
10593 12:19:21.639655 <6>[ 0.678622] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10594 12:19:21.650675 <6>[ 0.690948] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10595 12:19:21.660799 <6>[ 0.699767] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10596 12:19:21.667220 <6>[ 0.707738] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10597 12:19:21.677121 <6>[ 0.716440] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10598 12:19:21.684069 <6>[ 0.726198] TCP: Hash tables configured (established 65536 bind 65536)
10599 12:19:21.690554 <6>[ 0.733061] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10600 12:19:21.700262 <6>[ 0.740261] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10601 12:19:21.707058 <6>[ 0.747959] NET: Registered PF_UNIX/PF_LOCAL protocol family
10602 12:19:21.710222 <6>[ 0.754110] RPC: Registered named UNIX socket transport module.
10603 12:19:21.717023 <6>[ 0.760264] RPC: Registered udp transport module.
10604 12:19:21.720020 <6>[ 0.765197] RPC: Registered tcp transport module.
10605 12:19:21.730264 <6>[ 0.770130] RPC: Registered tcp NFSv4.1 backchannel transport module.
10606 12:19:21.733323 <6>[ 0.776796] PCI: CLS 0 bytes, default 64
10607 12:19:21.736482 <6>[ 0.781117] Unpacking initramfs...
10608 12:19:21.746329 <6>[ 0.785187] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10609 12:19:21.753122 <6>[ 0.793804] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10610 12:19:21.759544 <6>[ 0.802580] kvm [1]: IPA Size Limit: 40 bits
10611 12:19:21.763000 <6>[ 0.807104] kvm [1]: GICv3: no GICV resource entry
10612 12:19:21.769993 <6>[ 0.812125] kvm [1]: disabling GICv2 emulation
10613 12:19:21.773394 <6>[ 0.816810] kvm [1]: GIC system register CPU interface enabled
10614 12:19:21.779635 <6>[ 0.822978] kvm [1]: vgic interrupt IRQ18
10615 12:19:21.782849 <6>[ 0.827334] kvm [1]: VHE mode initialized successfully
10616 12:19:21.790515 <5>[ 0.833624] Initialise system trusted keyrings
10617 12:19:21.796584 <6>[ 0.838393] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10618 12:19:21.804961 <6>[ 0.848450] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10619 12:19:21.812088 <5>[ 0.854820] NFS: Registering the id_resolver key type
10620 12:19:21.815056 <5>[ 0.860120] Key type id_resolver registered
10621 12:19:21.821922 <5>[ 0.864536] Key type id_legacy registered
10622 12:19:21.828620 <6>[ 0.868815] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10623 12:19:21.834756 <6>[ 0.875737] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10624 12:19:21.841349 <6>[ 0.883430] 9p: Installing v9fs 9p2000 file system support
10625 12:19:21.878789 <5>[ 0.921929] Key type asymmetric registered
10626 12:19:21.881770 <5>[ 0.926258] Asymmetric key parser 'x509' registered
10627 12:19:21.891715 <6>[ 0.931400] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10628 12:19:21.895068 <6>[ 0.939014] io scheduler mq-deadline registered
10629 12:19:21.898294 <6>[ 0.943776] io scheduler kyber registered
10630 12:19:21.917648 <6>[ 0.960845] EINJ: ACPI disabled.
10631 12:19:21.950583 <4>[ 0.986999] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10632 12:19:21.960107 <4>[ 0.997630] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10633 12:19:21.975004 <6>[ 1.018492] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10634 12:19:21.983305 <6>[ 1.026407] printk: console [ttyS0] disabled
10635 12:19:22.011030 <6>[ 1.051070] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10636 12:19:22.017715 <6>[ 1.060548] printk: console [ttyS0] enabled
10637 12:19:22.021371 <6>[ 1.060548] printk: console [ttyS0] enabled
10638 12:19:22.027311 <6>[ 1.069449] printk: bootconsole [mtk8250] disabled
10639 12:19:22.030861 <6>[ 1.069449] printk: bootconsole [mtk8250] disabled
10640 12:19:22.037640 <6>[ 1.080514] SuperH (H)SCI(F) driver initialized
10641 12:19:22.040877 <6>[ 1.085788] msm_serial: driver initialized
10642 12:19:22.054489 <6>[ 1.094715] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10643 12:19:22.064432 <6>[ 1.103260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10644 12:19:22.071200 <6>[ 1.111802] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10645 12:19:22.081238 <6>[ 1.120430] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10646 12:19:22.091264 <6>[ 1.129137] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10647 12:19:22.097656 <6>[ 1.137850] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10648 12:19:22.107901 <6>[ 1.146392] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10649 12:19:22.114131 <6>[ 1.155188] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10650 12:19:22.124174 <6>[ 1.163731] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10651 12:19:22.136218 <6>[ 1.179192] loop: module loaded
10652 12:19:22.142421 <6>[ 1.185185] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10653 12:19:22.164848 <4>[ 1.208316] mtk-pmic-keys: Failed to locate of_node [id: -1]
10654 12:19:22.171550 <6>[ 1.215145] megasas: 07.719.03.00-rc1
10655 12:19:22.181354 <6>[ 1.224785] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10656 12:19:22.188822 <6>[ 1.231905] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10657 12:19:22.205426 <6>[ 1.248634] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10658 12:19:22.261840 <6>[ 1.298549] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10659 12:19:24.182133 <6>[ 3.225869] Freeing initrd memory: 55088K
10660 12:19:24.192263 <6>[ 3.236149] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10661 12:19:24.203709 <6>[ 3.246774] tun: Universal TUN/TAP device driver, 1.6
10662 12:19:24.206371 <6>[ 3.252850] thunder_xcv, ver 1.0
10663 12:19:24.210137 <6>[ 3.256343] thunder_bgx, ver 1.0
10664 12:19:24.212899 <6>[ 3.259840] nicpf, ver 1.0
10665 12:19:24.223601 <6>[ 3.263866] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10666 12:19:24.227128 <6>[ 3.271342] hns3: Copyright (c) 2017 Huawei Corporation.
10667 12:19:24.233626 <6>[ 3.276929] hclge is initializing
10668 12:19:24.237171 <6>[ 3.280507] e1000: Intel(R) PRO/1000 Network Driver
10669 12:19:24.243433 <6>[ 3.285637] e1000: Copyright (c) 1999-2006 Intel Corporation.
10670 12:19:24.246697 <6>[ 3.291649] e1000e: Intel(R) PRO/1000 Network Driver
10671 12:19:24.253663 <6>[ 3.296865] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10672 12:19:24.260214 <6>[ 3.303054] igb: Intel(R) Gigabit Ethernet Network Driver
10673 12:19:24.266697 <6>[ 3.308704] igb: Copyright (c) 2007-2014 Intel Corporation.
10674 12:19:24.273336 <6>[ 3.314539] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10675 12:19:24.279658 <6>[ 3.321057] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10676 12:19:24.283636 <6>[ 3.327522] sky2: driver version 1.30
10677 12:19:24.289646 <6>[ 3.332524] VFIO - User Level meta-driver version: 0.3
10678 12:19:24.297252 <6>[ 3.340783] usbcore: registered new interface driver usb-storage
10679 12:19:24.303923 <6>[ 3.347225] usbcore: registered new device driver onboard-usb-hub
10680 12:19:24.312670 <6>[ 3.356370] mt6397-rtc mt6359-rtc: registered as rtc0
10681 12:19:24.322823 <6>[ 3.361837] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:19:24 UTC (1698409164)
10682 12:19:24.325786 <6>[ 3.371405] i2c_dev: i2c /dev entries driver
10683 12:19:24.343188 <6>[ 3.383201] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10684 12:19:24.362654 <6>[ 3.406206] cpu cpu0: EM: created perf domain
10685 12:19:24.365992 <6>[ 3.411114] cpu cpu4: EM: created perf domain
10686 12:19:24.373083 <6>[ 3.416689] sdhci: Secure Digital Host Controller Interface driver
10687 12:19:24.379505 <6>[ 3.423119] sdhci: Copyright(c) Pierre Ossman
10688 12:19:24.386373 <6>[ 3.428078] Synopsys Designware Multimedia Card Interface Driver
10689 12:19:24.392779 <6>[ 3.434731] sdhci-pltfm: SDHCI platform and OF driver helper
10690 12:19:24.395978 <6>[ 3.434860] mmc0: CQHCI version 5.10
10691 12:19:24.402586 <6>[ 3.444751] ledtrig-cpu: registered to indicate activity on CPUs
10692 12:19:24.409725 <6>[ 3.451650] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10693 12:19:24.416046 <6>[ 3.458715] usbcore: registered new interface driver usbhid
10694 12:19:24.419307 <6>[ 3.464540] usbhid: USB HID core driver
10695 12:19:24.426285 <6>[ 3.468741] spi_master spi0: will run message pump with realtime priority
10696 12:19:24.470460 <6>[ 3.507253] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10697 12:19:24.488466 <6>[ 3.522172] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10698 12:19:24.495882 <6>[ 3.537968] cros-ec-spi spi0.0: Chrome EC device registered
10699 12:19:24.499024 <6>[ 3.544037] mmc0: Command Queue Engine enabled
10700 12:19:24.505796 <6>[ 3.548792] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10701 12:19:24.513114 <6>[ 3.556567] mmcblk0: mmc0:0001 DA4128 116 GiB
10702 12:19:24.527524 <6>[ 3.570777] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10703 12:19:24.537116 <6>[ 3.571270] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10704 12:19:24.543588 <6>[ 3.578089] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10705 12:19:24.547098 <6>[ 3.587300] NET: Registered PF_PACKET protocol family
10706 12:19:24.553758 <6>[ 3.591901] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10707 12:19:24.557374 <6>[ 3.596614] 9pnet: Installing 9P2000 support
10708 12:19:24.563799 <6>[ 3.602457] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10709 12:19:24.570306 <5>[ 3.606333] Key type dns_resolver registered
10710 12:19:24.573569 <6>[ 3.617795] registered taskstats version 1
10711 12:19:24.580088 <5>[ 3.622173] Loading compiled-in X.509 certificates
10712 12:19:24.605918 <4>[ 3.642588] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10713 12:19:24.615254 <4>[ 3.653348] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10714 12:19:24.621854 <3>[ 3.663884] debugfs: File 'uA_load' in directory '/' already present!
10715 12:19:24.628682 <3>[ 3.670588] debugfs: File 'min_uV' in directory '/' already present!
10716 12:19:24.635830 <3>[ 3.677245] debugfs: File 'max_uV' in directory '/' already present!
10717 12:19:24.641881 <3>[ 3.683863] debugfs: File 'constraint_flags' in directory '/' already present!
10718 12:19:24.654025 <3>[ 3.694250] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10719 12:19:24.666776 <6>[ 3.710223] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10720 12:19:24.673540 <6>[ 3.717081] xhci-mtk 11200000.usb: xHCI Host Controller
10721 12:19:24.680507 <6>[ 3.722605] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10722 12:19:24.690189 <6>[ 3.730538] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10723 12:19:24.696796 <6>[ 3.739977] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10724 12:19:24.703730 <6>[ 3.746038] xhci-mtk 11200000.usb: xHCI Host Controller
10725 12:19:24.710305 <6>[ 3.751516] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10726 12:19:24.716864 <6>[ 3.759166] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10727 12:19:24.723996 <6>[ 3.766964] hub 1-0:1.0: USB hub found
10728 12:19:24.726656 <6>[ 3.771000] hub 1-0:1.0: 1 port detected
10729 12:19:24.736821 <6>[ 3.775288] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10730 12:19:24.739777 <6>[ 3.783994] hub 2-0:1.0: USB hub found
10731 12:19:24.743322 <6>[ 3.788031] hub 2-0:1.0: 1 port detected
10732 12:19:24.751785 <6>[ 3.795107] mtk-msdc 11f70000.mmc: Got CD GPIO
10733 12:19:24.763315 <6>[ 3.803478] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10734 12:19:24.770173 <6>[ 3.811535] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10735 12:19:24.779705 <4>[ 3.819429] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10736 12:19:24.789616 <6>[ 3.828963] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10737 12:19:24.796358 <6>[ 3.837042] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10738 12:19:24.802939 <6>[ 3.845209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10739 12:19:24.812723 <6>[ 3.853164] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10740 12:19:24.819221 <6>[ 3.860983] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10741 12:19:24.829448 <6>[ 3.868800] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10742 12:19:24.839047 <6>[ 3.879302] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10743 12:19:24.846271 <6>[ 3.887687] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10744 12:19:24.855850 <6>[ 3.896045] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10745 12:19:24.865663 <6>[ 3.904386] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10746 12:19:24.872204 <6>[ 3.912727] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10747 12:19:24.882406 <6>[ 3.921066] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10748 12:19:24.888996 <6>[ 3.929405] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10749 12:19:24.898790 <6>[ 3.937743] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10750 12:19:24.905172 <6>[ 3.946082] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10751 12:19:24.915308 <6>[ 3.954422] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10752 12:19:24.921525 <6>[ 3.962761] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10753 12:19:24.931793 <6>[ 3.971100] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10754 12:19:24.938260 <6>[ 3.979439] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10755 12:19:24.948635 <6>[ 3.987778] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10756 12:19:24.955144 <6>[ 3.996122] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10757 12:19:24.961418 <6>[ 4.004893] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10758 12:19:24.968658 <6>[ 4.012067] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10759 12:19:24.975168 <6>[ 4.018847] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10760 12:19:24.985300 <6>[ 4.025608] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10761 12:19:24.992009 <6>[ 4.032545] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10762 12:19:24.998589 <6>[ 4.039390] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10763 12:19:25.008314 <6>[ 4.048522] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10764 12:19:25.018504 <6>[ 4.057643] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10765 12:19:25.028591 <6>[ 4.066938] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10766 12:19:25.037986 <6>[ 4.076406] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10767 12:19:25.044558 <6>[ 4.085874] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10768 12:19:25.054619 <6>[ 4.094995] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10769 12:19:25.064614 <6>[ 4.104461] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10770 12:19:25.074321 <6>[ 4.113585] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10771 12:19:25.084470 <6>[ 4.122881] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10772 12:19:25.094133 <6>[ 4.133041] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10773 12:19:25.104321 <6>[ 4.144668] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10774 12:19:25.132325 <6>[ 4.172780] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10775 12:19:25.161021 <6>[ 4.204881] hub 2-1:1.0: USB hub found
10776 12:19:25.164193 <6>[ 4.209377] hub 2-1:1.0: 3 ports detected
10777 12:19:25.284111 <6>[ 4.324775] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10778 12:19:25.439137 <6>[ 4.482825] hub 1-1:1.0: USB hub found
10779 12:19:25.441985 <6>[ 4.487246] hub 1-1:1.0: 4 ports detected
10780 12:19:25.516366 <6>[ 4.557096] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10781 12:19:25.764157 <6>[ 4.804828] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10782 12:19:25.896450 <6>[ 4.940160] hub 1-1.4:1.0: USB hub found
10783 12:19:25.899633 <6>[ 4.944785] hub 1-1.4:1.0: 2 ports detected
10784 12:19:26.195992 <6>[ 5.236817] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10785 12:19:26.388538 <6>[ 5.428817] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10786 12:19:37.389558 <6>[ 16.437870] ALSA device list:
10787 12:19:37.396204 <6>[ 16.441167] No soundcards found.
10788 12:19:37.404178 <6>[ 16.449324] Freeing unused kernel memory: 8384K
10789 12:19:37.407373 <6>[ 16.454330] Run /init as init process
10790 12:19:37.459280 <6>[ 16.504356] NET: Registered PF_INET6 protocol family
10791 12:19:37.466025 <6>[ 16.510766] Segment Routing with IPv6
10792 12:19:37.469087 <6>[ 16.514723] In-situ OAM (IOAM) with IPv6
10793 12:19:37.504460 <30>[ 16.529555] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10794 12:19:37.507599 <30>[ 16.553624] systemd[1]: Detected architecture arm64.
10795 12:19:37.510871
10796 12:19:37.514195 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10797 12:19:37.514278
10798 12:19:37.528066 <30>[ 16.573011] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10799 12:19:37.710428 <30>[ 16.752035] systemd[1]: Queued start job for default target Graphical Interface.
10800 12:19:37.760645 <30>[ 16.805440] systemd[1]: Created slice system-getty.slice.
10801 12:19:37.767265 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10802 12:19:37.784172 <30>[ 16.829262] systemd[1]: Created slice system-modprobe.slice.
10803 12:19:37.790538 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10804 12:19:37.809006 <30>[ 16.854204] systemd[1]: Created slice system-serial\x2dgetty.slice.
10805 12:19:37.819048 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10806 12:19:37.832222 <30>[ 16.877204] systemd[1]: Created slice User and Session Slice.
10807 12:19:37.838628 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10808 12:19:37.859805 <30>[ 16.901338] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10809 12:19:37.869329 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10810 12:19:37.886934 <30>[ 16.928703] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10811 12:19:37.893721 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10812 12:19:37.914178 <30>[ 16.952701] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10813 12:19:37.920640 <30>[ 16.964745] systemd[1]: Reached target Local Encrypted Volumes.
10814 12:19:37.927714 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10815 12:19:37.944118 <30>[ 16.989182] systemd[1]: Reached target Paths.
10816 12:19:37.947508 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10817 12:19:37.964030 <30>[ 17.008758] systemd[1]: Reached target Remote File Systems.
10818 12:19:37.970417 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10819 12:19:37.983972 <30>[ 17.028695] systemd[1]: Reached target Slices.
10820 12:19:37.986710 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10821 12:19:38.003983 <30>[ 17.048796] systemd[1]: Reached target Swap.
10822 12:19:38.006986 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10823 12:19:38.027423 <30>[ 17.069298] systemd[1]: Listening on initctl Compatibility Named Pipe.
10824 12:19:38.033801 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10825 12:19:38.048545 <30>[ 17.093740] systemd[1]: Listening on Journal Audit Socket.
10826 12:19:38.055116 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10827 12:19:38.072885 <30>[ 17.117963] systemd[1]: Listening on Journal Socket (/dev/log).
10828 12:19:38.079396 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10829 12:19:38.097081 <30>[ 17.142000] systemd[1]: Listening on Journal Socket.
10830 12:19:38.103528 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10831 12:19:38.116074 <30>[ 17.161383] systemd[1]: Listening on udev Control Socket.
10832 12:19:38.123156 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10833 12:19:38.140934 <30>[ 17.185841] systemd[1]: Listening on udev Kernel Socket.
10834 12:19:38.147194 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10835 12:19:38.203823 <30>[ 17.248893] systemd[1]: Mounting Huge Pages File System...
10836 12:19:38.210536 Mounting [0;1;39mHuge Pages File System[0m...
10837 12:19:38.227665 <30>[ 17.272608] systemd[1]: Mounting POSIX Message Queue File System...
10838 12:19:38.234203 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10839 12:19:38.271775 <30>[ 17.316824] systemd[1]: Mounting Kernel Debug File System...
10840 12:19:38.278129 Mounting [0;1;39mKernel Debug File System[0m...
10841 12:19:38.295671 <30>[ 17.337237] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10842 12:19:38.308656 <30>[ 17.350448] systemd[1]: Starting Create list of static device nodes for the current kernel...
10843 12:19:38.314959 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10844 12:19:38.352056 <30>[ 17.397012] systemd[1]: Starting Load Kernel Module configfs...
10845 12:19:38.358341 Starting [0;1;39mLoad Kernel Module configfs[0m...
10846 12:19:38.375974 <30>[ 17.421331] systemd[1]: Starting Load Kernel Module drm...
10847 12:19:38.382554 Starting [0;1;39mLoad Kernel Module drm[0m...
10848 12:19:38.399094 <30>[ 17.441132] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10849 12:19:38.431765 <30>[ 17.477262] systemd[1]: Starting Journal Service...
10850 12:19:38.435281 Starting [0;1;39mJournal Service[0m...
10851 12:19:38.454345 <30>[ 17.499639] systemd[1]: Starting Load Kernel Modules...
10852 12:19:38.460768 Starting [0;1;39mLoad Kernel Modules[0m...
10853 12:19:38.484173 <30>[ 17.525889] systemd[1]: Starting Remount Root and Kernel File Systems...
10854 12:19:38.490213 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10855 12:19:38.520692 <30>[ 17.565440] systemd[1]: Starting Coldplug All udev Devices...
10856 12:19:38.526780 Starting [0;1;39mColdplug All udev Devices[0m...
10857 12:19:38.544670 <30>[ 17.589447] systemd[1]: Started Journal Service.
10858 12:19:38.550745 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10859 12:19:38.569361 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10860 12:19:38.584583 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10861 12:19:38.604689 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10862 12:19:38.624646 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10863 12:19:38.641938 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10864 12:19:38.661219 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10865 12:19:38.677761 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10866 12:19:38.701351 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10867 12:19:38.715724 See 'systemctl status systemd-remount-fs.service' for details.
10868 12:19:38.772238 Mounting [0;1;39mKernel Configuration File System[0m...
10869 12:19:38.797327 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10870 12:19:38.822630 Starting [0;1;39mLoad/<46>[ 17.862996] systemd-journald[185]: Received client request to flush runtime journal.
10871 12:19:38.822757 Save Random Seed[0m...
10872 12:19:38.881659 Starting [0;1;39mApply Kernel Variables[0m...
10873 12:19:38.904609 Starting [0;1;39mCreate System Users[0m...
10874 12:19:38.922971 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10875 12:19:38.944392 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10876 12:19:38.968989 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10877 12:19:38.990023 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10878 12:19:39.014083 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10879 12:19:39.032626 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10880 12:19:39.068096 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10881 12:19:39.090243 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10882 12:19:39.103739 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10883 12:19:39.119638 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10884 12:19:39.164276 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10885 12:19:39.189276 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10886 12:19:39.216175 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10887 12:19:39.238810 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10888 12:19:39.290474 Starting [0;1;39mNetwork Time Synchronization[0m...
10889 12:19:39.303522 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10890 12:19:39.355006 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10891 12:19:39.370152 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10892 12:19:39.400427 <6>[ 18.442492] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10893 12:19:39.413202 <3>[ 18.454849] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10894 12:19:39.419450 <3>[ 18.463156] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10895 12:19:39.426231 <6>[ 18.463567] remoteproc remoteproc0: scp is available
10896 12:19:39.432322 <6>[ 18.464775] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10897 12:19:39.442780 <6>[ 18.464807] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10898 12:19:39.452876 <6>[ 18.464817] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10899 12:19:39.458978 <3>[ 18.471255] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 12:19:39.465926 <3>[ 18.502722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10901 12:19:39.475597 [[0;32m OK [<4>[ 18.508355] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10902 12:19:39.482139 0m] Created slic<6>[ 18.509596] remoteproc remoteproc0: powering up scp
10903 12:19:39.491972 <3>[ 18.517620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10904 12:19:39.498651 e [0;1;39msyste<4>[ 18.524997] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10905 12:19:39.508804 <6>[ 18.526389] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10906 12:19:39.518543 m-systemd\x2dbac<3>[ 18.532817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10907 12:19:39.525324 klight.slice[0m<6>[ 18.540930] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10908 12:19:39.525406 .
10909 12:19:39.531512 <6>[ 18.542417] usbcore: registered new interface driver r8152
10910 12:19:39.538626 <3>[ 18.549972] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10911 12:19:39.544998 <6>[ 18.577576] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10912 12:19:39.554826 <3>[ 18.580562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 12:19:39.558630 <6>[ 18.592578] mc: Linux media interface: v0.10
10914 12:19:39.568224 <3>[ 18.601023] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10915 12:19:39.574927 <6>[ 18.612194] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10916 12:19:39.581798 <3>[ 18.619929] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 12:19:39.588227 <6>[ 18.626438] videodev: Linux video capture interface: v2.00
10918 12:19:39.594713 <6>[ 18.627139] pci_bus 0000:00: root bus resource [bus 00-ff]
10919 12:19:39.601306 <6>[ 18.627170] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10920 12:19:39.611548 <6>[ 18.627181] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10921 12:19:39.617899 <6>[ 18.627303] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10922 12:19:39.624212 <6>[ 18.627351] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10923 12:19:39.631129 <6>[ 18.627514] pci 0000:00:00.0: supports D1 D2
10924 12:19:39.638191 <6>[ 18.627521] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10925 12:19:39.644823 <3>[ 18.632218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10926 12:19:39.655004 <3>[ 18.632230] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10927 12:19:39.661380 <6>[ 18.638966] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10928 12:19:39.671212 <4>[ 18.645601] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10929 12:19:39.674514 <4>[ 18.645601] Fallback method does not support PEC.
10930 12:19:39.684802 <3>[ 18.647174] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10931 12:19:39.691493 <3>[ 18.647208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10932 12:19:39.701360 <3>[ 18.647219] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10933 12:19:39.708467 <3>[ 18.647226] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10934 12:19:39.714854 <3>[ 18.647234] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10935 12:19:39.724784 <3>[ 18.652856] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10936 12:19:39.731497 <6>[ 18.662444] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10937 12:19:39.741512 <6>[ 18.670391] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10938 12:19:39.751124 <6>[ 18.674182] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10939 12:19:39.758335 <6>[ 18.676325] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10940 12:19:39.764651 <6>[ 18.683316] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10941 12:19:39.775148 <6>[ 18.683322] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10942 12:19:39.781566 <6>[ 18.687523] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10943 12:19:39.788227 <6>[ 18.687931] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10944 12:19:39.799162 <6>[ 18.690343] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10945 12:19:39.805921 <3>[ 18.693168] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 12:19:39.812803 <6>[ 18.695557] remoteproc remoteproc0: remote processor scp is now up
10947 12:19:39.822678 <4>[ 18.721089] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10948 12:19:39.829636 <6>[ 18.726005] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10949 12:19:39.836103 <4>[ 18.733941] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10950 12:19:39.842560 <6>[ 18.742716] pci 0000:01:00.0: supports D1 D2
10951 12:19:39.849355 <6>[ 18.760408] usbcore: registered new interface driver cdc_ether
10952 12:19:39.852387 <6>[ 18.764926] Bluetooth: Core ver 2.22
10953 12:19:39.855882 <6>[ 18.765010] NET: Registered PF_BLUETOOTH protocol family
10954 12:19:39.862685 <6>[ 18.765013] Bluetooth: HCI device and connection manager initialized
10955 12:19:39.869362 <6>[ 18.765043] Bluetooth: HCI socket layer initialized
10956 12:19:39.875652 <6>[ 18.765052] Bluetooth: L2CAP socket layer initialized
10957 12:19:39.879055 <6>[ 18.765063] Bluetooth: SCO socket layer initialized
10958 12:19:39.886082 <6>[ 18.766546] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10959 12:19:39.892434 <6>[ 18.776571] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10960 12:19:39.902583 <6>[ 18.791321] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10961 12:19:39.905606 <6>[ 18.800876] r8152 2-1.3:1.0 eth0: v1.12.13
10962 12:19:39.915640 <6>[ 18.800897] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10963 12:19:39.922127 <6>[ 18.800905] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10964 12:19:39.928794 <6>[ 18.800918] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10965 12:19:39.938304 <6>[ 18.800934] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10966 12:19:39.945075 <6>[ 18.800947] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10967 12:19:39.951921 <6>[ 18.800960] pci 0000:00:00.0: PCI bridge to [bus 01]
10968 12:19:39.958595 <6>[ 18.800965] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10969 12:19:39.964823 <6>[ 18.801166] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10970 12:19:39.974316 <3>[ 18.801374] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 12:19:39.981330 <6>[ 18.801573] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10972 12:19:39.987893 <6>[ 18.801820] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10973 12:19:39.997921 <3>[ 18.802135] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10974 12:19:40.001146 <6>[ 18.802384] usbcore: registered new interface driver r8153_ecm
10975 12:19:40.007425 <6>[ 18.802429] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10976 12:19:40.021011 <6>[ 18.806654] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10977 12:19:40.027510 <6>[ 18.807009] usbcore: registered new interface driver uvcvideo
10978 12:19:40.034062 <6>[ 18.820003] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10979 12:19:40.043831 <4>[ 18.820659] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10980 12:19:40.050803 <3>[ 18.820678] Bluetooth: hci0: Failed to load firmware file (-2)
10981 12:19:40.053653 <3>[ 18.820683] Bluetooth: hci0: Failed to set up firmware (-2)
10982 12:19:40.067292 <4>[ 18.820687] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10983 12:19:40.070227 <6>[ 18.821703] usbcore: registered new interface driver btusb
10984 12:19:40.077379 <6>[ 18.834666] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10985 12:19:40.087103 <5>[ 18.840180] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10986 12:19:40.093777 <6>[ 18.841152] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10987 12:19:40.103229 <3>[ 18.849819] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 12:19:40.110106 <3>[ 18.850632] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10989 12:19:40.120039 <3>[ 18.863937] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 12:19:40.126779 <5>[ 18.870172] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10991 12:19:40.139545 [[0;32m OK [0m] Reached target [0;1;39mSyst<4>[ 19.181287] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10992 12:19:40.146923 em Time Set[0m.<6>[ 19.190857] cfg80211: failed to load regulatory.db
10993 12:19:40.147014
10994 12:19:40.157964 <3>[ 19.200069] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10995 12:19:40.164412 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10996 12:19:40.183689 <6>[ 19.228415] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10997 12:19:40.193688 <3>[ 19.233923] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10998 12:19:40.200365 <6>[ 19.235999] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10999 12:19:40.223627 <3>[ 19.265562] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 12:19:40.230452 <6>[ 19.274545] mt7921e 0000:01:00.0: ASIC revision: 79610010
11001 12:19:40.236790 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11002 12:19:40.252951 <3>[ 19.294852] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 12:19:40.264244 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11004 12:19:40.282539 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11005 12:19:40.333687 <4>[ 19.371882] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 12:19:40.403065 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11007 12:19:40.415583 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11008 12:19:40.436167 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11009 12:19:40.451343 <4>[ 19.489323] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11010 12:19:40.457962 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11011 12:19:40.464935 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11012 12:19:40.484571 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11013 12:19:40.496286 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11014 12:19:40.516089 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11015 12:19:40.535428 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11016 12:19:40.576072 <4>[ 19.614516] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11017 12:19:40.591178 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11018 12:19:40.634098 Starting [0;1;39mUser Login Management[0m...
11019 12:19:40.650643 Starting [0;1;39mPermit User Sessions[0m...
11020 12:19:40.665835 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11021 12:19:40.706992 <4>[ 19.744922] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11022 12:19:40.737655 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11023 12:19:40.757662 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11024 12:19:40.772354 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11025 12:19:40.792297 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11026 12:19:40.811165 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11027 12:19:40.827929 <4>[ 19.866070] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11028 12:19:40.836396 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11029 12:19:40.846883 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11030 12:19:40.865352 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11031 12:19:40.912892 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11032 12:19:40.952333 <4>[ 19.990447] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11033 12:19:40.958959 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11034 12:19:41.020801
11035 12:19:41.021323
11036 12:19:41.024147 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11037 12:19:41.024594
11038 12:19:41.027298 debian-bullseye-arm64 login: root (automatic login)
11039 12:19:41.027881
11040 12:19:41.028250
11041 12:19:41.044820 Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64
11042 12:19:41.045332
11043 12:19:41.052062 The programs included with the Debian GNU/Linux system are free software;
11044 12:19:41.058693 the exact distribution terms for each program are described in the
11045 12:19:41.061833 individual files in /usr/share/doc/*/copyright.
11046 12:19:41.062352
11047 12:19:41.074729 Debian GNU/Linux comes with ABS<4>[ 20.114402] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11048 12:19:41.078270 OLUTELY NO WARRANTY, to the extent
11049 12:19:41.081531 permitted by applicable law.
11050 12:19:41.082933 Matched prompt #10: / #
11052 12:19:41.083970 Setting prompt string to ['/ #']
11053 12:19:41.084400 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11055 12:19:41.085370 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11056 12:19:41.085786 start: 2.2.6 expect-shell-connection (timeout 00:02:36) [common]
11057 12:19:41.086125 Setting prompt string to ['/ #']
11058 12:19:41.086435 Forcing a shell prompt, looking for ['/ #']
11060 12:19:41.137260 / #
11061 12:19:41.137884 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11062 12:19:41.138333 Waiting using forced prompt support (timeout 00:02:30)
11063 12:19:41.143487
11064 12:19:41.144359 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11065 12:19:41.144840 start: 2.2.7 export-device-env (timeout 00:02:36) [common]
11066 12:19:41.145383 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11067 12:19:41.145819 end: 2.2 depthcharge-retry (duration 00:02:24) [common]
11068 12:19:41.146247 end: 2 depthcharge-action (duration 00:02:24) [common]
11069 12:19:41.146690 start: 3 lava-test-retry (timeout 00:07:12) [common]
11070 12:19:41.147198 start: 3.1 lava-test-shell (timeout 00:07:12) [common]
11071 12:19:41.147697 Using namespace: common
11073 12:19:41.248987 / # #
11074 12:19:41.249603 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11075 12:19:41.250160 <4>[ 20.237908] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11076 12:19:41.255274 #
11077 12:19:41.256176 Using /lava-11893121
11079 12:19:41.357405 / # export SHELL=/bin/sh
11080 12:19:41.358151 export<4>[ 20.361735] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11081 12:19:41.363679 SHELL=/bin/sh
11083 12:19:41.465434 / # . /lava-11893121/environment
11084 12:19:41.466182 . /lava-11893121/environment<4>[ 20.485624] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11085 12:19:41.472136
11087 12:19:41.573931 / # /lava-11893121/bin/lava-test-runner /lava-11893121/0
11088 12:19:41.574518 Test shell timeout: 10s (minimum of the action and connection timeout)
11089 12:19:41.576135 /lava-11893121/bin/lava-test-runner /lava-11893121/0<3>[ 20.607337] mt7921e 0000:01:00.0: hardware init failed
11090 12:19:41.579919
11091 12:19:41.623885 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.651008] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 11893121_1.5.2.3.1>
11092 12:19:41.624409 diatek
11093 12:19:41.624740 + cd /lava-11893121/0/tests/0_igt-kms-mediatek
11094 12:19:41.625055 + cat uuid
11095 12:19:41.625350 + UUID=11893121_1.5.2.3.1
11096 12:19:41.625645 + set +x
11097 12:19:41.626230 Received signal: <STARTRUN> 0_igt-kms-mediatek 11893121_1.5.2.3.1
11098 12:19:41.626749 Starting test lava.0_igt-kms-mediatek (11893121_1.5.2.3.1)
11099 12:19:41.627152 Skipping test definition patterns.
11100 12:19:41.630352 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversi<8>[ 20.675897] <LAVA_SIGNAL_TESTSET START core_auth>
11101 12:19:41.631166 Received signal: <TESTSET> START core_auth
11102 12:19:41.631597 Starting test_set core_auth
11103 12:19:41.644109 on core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11104 12:19:41.646564 <14>[ 20.694038] [IGT] core_auth: executing
11105 12:19:41.656837 IGT-Version: 1.2<14>[ 20.698523] [IGT] core_auth: starting subtest getclient-simple
11106 12:19:41.663262 7.1-g621c2d3 (aa<14>[ 20.706195] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11107 12:19:41.670044 rch64) (Linux: 6<14>[ 20.714540] [IGT] core_auth: exiting, ret=0
11108 12:19:41.673149 .1.59-cip7 aarch64)
11109 12:19:41.676705 Starting subtest: getclient-simple
11110 12:19:41.683558 Opened device: /dev/dri<8>[ 20.727192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11111 12:19:41.684354 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11113 12:19:41.687118 /card0
11114 12:19:41.689834 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11115 12:19:41.717772 <14>[ 20.762977] [IGT] core_auth: executing
11116 12:19:41.724692 IGT-Version: 1.2<14>[ 20.767519] [IGT] core_auth: starting subtest getclient-master-drop
11117 12:19:41.734448 7.1-g621c2d3 (aa<14>[ 20.775850] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11118 12:19:41.740754 rch64) (Linux: 6<14>[ 20.784288] [IGT] core_auth: exiting, ret=0
11119 12:19:41.741184 .1.59-cip7 aarch64)
11120 12:19:41.744171 Starting subtest: getclient-master-drop
11121 12:19:41.754316 Op<8>[ 20.795353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11122 12:19:41.755061 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11124 12:19:41.757418 ened device: /dev/dri/card0
11125 12:19:41.760837 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11126 12:19:41.781842 <14>[ 20.827217] [IGT] core_auth: executing
11127 12:19:41.789156 IGT-Version: 1.2<14>[ 20.831846] [IGT] core_auth: starting subtest basic-auth
11128 12:19:41.795832 7.1-g621c2d3 (aa<14>[ 20.838786] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11129 12:19:41.802286 <14>[ 20.846541] [IGT] core_auth: exiting, ret=0
11130 12:19:41.805628 rch64) (Linux: 6.1.59-cip7 aarch64)
11131 12:19:41.812364 Opened device: /dev/dri/car<8>[ 20.856074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11132 12:19:41.813178 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11134 12:19:41.815178 d0
11135 12:19:41.815638 Starting subtest: basic-auth
11136 12:19:41.822087 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11137 12:19:41.847570 <14>[ 20.892699] [IGT] core_auth: executing
11138 12:19:41.854292 IGT-Version: 1.2<14>[ 20.897355] [IGT] core_auth: starting subtest many-magics
11139 12:19:41.857693 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11140 12:19:41.860800 Opened device: /dev/dri/card0
11141 12:19:41.864216 Starting subtest: many-magics
11142 12:19:41.874378 Reopening device failed after<14>[ 20.915407] [IGT] core_auth: finished subtest many-magics, SUCCESS
11143 12:19:41.874916 1020 opens
11144 12:19:41.880739 [1<14>[ 20.923351] [IGT] core_auth: exiting, ret=0
11145 12:19:41.884116 mSubtest many-magics: SUCCESS (0.011s)[0m
11146 12:19:41.891272 <8>[ 20.934344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11147 12:19:41.892138 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11149 12:19:41.897724 <8>[ 20.942593] <LAVA_SIGNAL_TESTSET STOP>
11150 12:19:41.898528 Received signal: <TESTSET> STOP
11151 12:19:41.898902 Closing test_set core_auth
11152 12:19:41.927484 <14>[ 20.972169] [IGT] core_getclient: executing
11153 12:19:41.934146 IGT-Version: 1.2<14>[ 20.977029] [IGT] core_getclient: exiting, ret=0
11154 12:19:41.937145 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11155 12:19:41.947214 Opened devi<8>[ 20.987937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11156 12:19:41.947781 ce: /dev/dri/card0
11157 12:19:41.948397 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11159 12:19:41.950216 SUCCESS (0.006s)
11160 12:19:41.976265 <14>[ 21.021100] [IGT] core_getstats: executing
11161 12:19:41.983079 IGT-Version: 1.2<14>[ 21.025845] [IGT] core_getstats: exiting, ret=0
11162 12:19:41.985779 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11163 12:19:41.996330 Opened devi<8>[ 21.036473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11164 12:19:41.996868 ce: /dev/dri/card0
11165 12:19:41.997490 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11167 12:19:41.998746 SUCCESS (0.006s)
11168 12:19:42.025300 <14>[ 21.069750] [IGT] core_getversion: executing
11169 12:19:42.031684 IGT-Version: 1.2<14>[ 21.074799] [IGT] core_getversion: exiting, ret=0
11170 12:19:42.034928 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11171 12:19:42.044262 Opened devi<8>[ 21.085592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11172 12:19:42.044800 ce: /dev/dri/card0
11173 12:19:42.045503 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11175 12:19:42.048280 SUCCESS (0.006s)
11176 12:19:42.077739 <14>[ 21.122703] [IGT] core_setmaster_vs_auth: executing
11177 12:19:42.083848 IGT-Version: 1.2<14>[ 21.128297] [IGT] core_setmaster_vs_auth: exiting, ret=0
11178 12:19:42.090936 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11179 12:19:42.097105 Opened devi<8>[ 21.139704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11180 12:19:42.097802 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11182 12:19:42.100747 ce: /dev/dri/card0
11183 12:19:42.101280 SUCCESS (0.007s)
11184 12:19:42.118430 <8>[ 21.163633] <LAVA_SIGNAL_TESTSET START drm_read>
11185 12:19:42.119237 Received signal: <TESTSET> START drm_read
11186 12:19:42.119641 Starting test_set drm_read
11187 12:19:42.137008 <14>[ 21.181685] [IGT] drm_read: executing
11188 12:19:42.143769 IGT-Version: 1.2<14>[ 21.186230] [IGT] drm_read: exiting, ret=77
11189 12:19:42.146181 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11190 12:19:42.153507 Opened devi<8>[ 21.196588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11191 12:19:42.154324 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11193 12:19:42.156227 ce: /dev/dri/card0
11194 12:19:42.159545 No KMS driver or no outputs, pipes: 8, outputs: 0
11195 12:19:42.166338 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11196 12:19:42.169788 <14>[ 21.216304] [IGT] drm_read: executing
11197 12:19:42.176198 IGT-Version: 1.2<14>[ 21.220877] [IGT] drm_read: exiting, ret=77
11198 12:19:42.179627 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11199 12:19:42.190314 Opened devi<8>[ 21.231080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11200 12:19:42.190840 ce: /dev/dri/card0
11201 12:19:42.191478 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11203 12:19:42.196233 No KMS driver or no outputs, pipes: 8, outputs: 0
11204 12:19:42.200006 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11205 12:19:42.206024 <14>[ 21.251247] [IGT] drm_read: executing
11206 12:19:42.212642 IGT-Version: 1.2<14>[ 21.255660] [IGT] drm_read: exiting, ret=77
11207 12:19:42.216062 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11208 12:19:42.222827 Opened devi<8>[ 21.265999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11209 12:19:42.223628 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11211 12:19:42.226514 ce: /dev/dri/card0
11212 12:19:42.228894 No KMS driver or no outputs, pipes: 8, outputs: 0
11213 12:19:42.232917 [1mSubtest empty-block: SKIP (0.000s)[0m
11214 12:19:42.241246 <14>[ 21.286249] [IGT] drm_read: executing
11215 12:19:42.248079 IGT-Version: 1.2<14>[ 21.290676] [IGT] drm_read: exiting, ret=77
11216 12:19:42.251194 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11217 12:19:42.258200 Opened devi<8>[ 21.301078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11218 12:19:42.259066 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11220 12:19:42.260567 ce: /dev/dri/card0
11221 12:19:42.264579 No KMS driver or no outputs, pipes: 8, outputs: 0
11222 12:19:42.270763 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11223 12:19:42.273976 <14>[ 21.320939] [IGT] drm_read: executing
11224 12:19:42.280618 IGT-Version: 1.2<14>[ 21.325371] [IGT] drm_read: exiting, ret=77
11225 12:19:42.283824 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11226 12:19:42.294528 Opened devi<8>[ 21.335563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11227 12:19:42.295331 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11229 12:19:42.297078 ce: /dev/dri/card0
11230 12:19:42.300869 No KMS driver or no outputs, pipes: 8, outputs: 0
11231 12:19:42.304337 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11232 12:19:42.311373 <14>[ 21.356469] [IGT] drm_read: executing
11233 12:19:42.317756 IGT-Version: 1.2<14>[ 21.361230] [IGT] drm_read: exiting, ret=77
11234 12:19:42.321341 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11235 12:19:42.331520 Opened devi<8>[ 21.371269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11236 12:19:42.332057 ce: /dev/dri/card0
11237 12:19:42.332675 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11239 12:19:42.334999 No KMS driver or no outputs, pipes: 8, outputs: 0
11240 12:19:42.340987 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11241 12:19:42.344187 <14>[ 21.392148] [IGT] drm_read: executing
11242 12:19:42.350612 IGT-Version: 1.2<14>[ 21.396664] [IGT] drm_read: exiting, ret=77
11243 12:19:42.357990 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11244 12:19:42.364177 Opened devi<8>[ 21.406977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11245 12:19:42.364590 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11247 12:19:42.367536 ce: /dev/dri/card0
11248 12:19:42.370319 No KMS drive<8>[ 21.416919] <LAVA_SIGNAL_TESTSET STOP>
11249 12:19:42.370695 Received signal: <TESTSET> STOP
11250 12:19:42.370789 Closing test_set drm_read
11251 12:19:42.373690 r or no outputs, pipes: 8, outputs: 0
11252 12:19:42.380366 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11253 12:19:42.391923 <8>[ 21.437235] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11254 12:19:42.392391 Received signal: <TESTSET> START kms_addfb_basic
11255 12:19:42.392581 Starting test_set kms_addfb_basic
11256 12:19:42.409787 <14>[ 21.454962] [IGT] kms_addfb_basic: executing
11257 12:19:42.423520 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch<14>[ 21.464038] [IGT] kms_addfb_basic: starting subtest unused-handle
11258 12:19:42.424042 64)
11259 12:19:42.429452 Opened devi<14>[ 21.471876] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11260 12:19:42.432824 ce: /dev/dri/card0
11261 12:19:42.436399 Starting subtest: unused-handle
11262 12:19:42.443075 [1mSubtest unused-handle: SUCCESS (0.000s)<14>[ 21.488713] [IGT] kms_addfb_basic: exiting, ret=0
11263 12:19:42.443646 [0m
11264 12:19:42.456223 Test requirement not met in function igt_require_i915, file ../lib/drmtest<8>[ 21.499727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11265 12:19:42.457057 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11267 12:19:42.459930 .c:720:
11268 12:19:42.462939 Test requirement: is_i915_device(fd)
11269 12:19:42.469828 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11270 12:19:42.476016 Test requirement: is_i915_devi<14>[ 21.520587] [IGT] kms_addfb_basic: executing
11271 12:19:42.476540 ce(fd)
11272 12:19:42.482532 No KMS driver or no outputs, pipes: 8, outputs: 0
11273 12:19:42.489631 IGT-V<14>[ 21.530942] [IGT] kms_addfb_basic: starting subtest unused-pitches
11274 12:19:42.496039 ersion: 1.27.1-g<14>[ 21.538856] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11275 12:19:42.503079 621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11276 12:19:42.505705 Opened device: /dev/dri/card0
11277 12:19:42.509620 Starting subtest:<14>[ 21.555745] [IGT] kms_addfb_basic: exiting, ret=0
11278 12:19:42.512665 unused-pitches
11279 12:19:42.522611 [1mSubtest unused-pitches: SUCCESS (0.000s)[0<8>[ 21.565445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11280 12:19:42.523117 m
11281 12:19:42.523791 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11283 12:19:42.532266 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11284 12:19:42.535344 Test requirement: is_i915_device(fd)
11285 12:19:42.542690 Test requirement not<14>[ 21.585791] [IGT] kms_addfb_basic: executing
11286 12:19:42.545605 met in function igt_require_i915, file ../lib/drmtest.c:720:
11287 12:19:42.552350 T<14>[ 21.595209] [IGT] kms_addfb_basic: starting subtest unused-offsets
11288 12:19:42.562170 est requirement:<14>[ 21.603213] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11289 12:19:42.562693 is_i915_device(fd)
11290 12:19:42.568328 No KMS driver or no outputs, pipes: 8, outputs: 0
11291 12:19:42.575271 IGT-Version: 1.27.1-g621<14>[ 21.619837] [IGT] kms_addfb_basic: exiting, ret=0
11292 12:19:42.578307 c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11293 12:19:42.581367 Opened device: /dev/dri/card0
11294 12:19:42.588114 Star<8>[ 21.631195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11295 12:19:42.588907 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11297 12:19:42.591553 ting subtest: unused-offsets
11298 12:19:42.595183 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11299 12:19:42.604643 Test requirement not met in function igt_require_i915, file ../l<14>[ 21.651814] [IGT] kms_addfb_basic: executing
11300 12:19:42.608117 ib/drmtest.c:720:
11301 12:19:42.611092 Test requirement: is_i915_device(fd)
11302 12:19:42.617755 Test re<14>[ 21.661151] [IGT] kms_addfb_basic: starting subtest unused-modifier
11303 12:19:42.627943 quirement not me<14>[ 21.668883] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11304 12:19:42.630906 t in function igt_require_i915, file ../lib/drmtest.c:720:
11305 12:19:42.641422 Test requirement: is_i915_device(fd)<14>[ 21.685736] [IGT] kms_addfb_basic: exiting, ret=0
11306 12:19:42.641861
11307 12:19:42.644284 No KMS driver or no outputs, pipes: 8, outputs: 0
11308 12:19:42.654193 IGT-Version: 1.27.1-g621c2d<8>[ 21.696892] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11309 12:19:42.654877 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11311 12:19:42.657496 3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11312 12:19:42.661371 Opened device: /dev/dri/card0
11313 12:19:42.664164 Starting subtest: unused-modifier
11314 12:19:42.667501 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11315 12:19:42.674263 T<14>[ 21.718261] [IGT] kms_addfb_basic: executing
11316 12:19:42.687111 est requirement not met in function igt_require_i915, file ../li<14>[ 21.728288] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11317 12:19:42.693625 b/drmtest.c:720:<14>[ 21.736594] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11318 12:19:42.694215
11319 12:19:42.697211 Test requirement: is_i915_device(fd)
11320 12:19:42.707132 Test requirement not met in function igt_require_i915, f<14>[ 21.753528] [IGT] kms_addfb_basic: exiting, ret=77
11321 12:19:42.710438 ile ../lib/drmtest.c:720:
11322 12:19:42.714094 Test requirement: is_i915_device(fd)
11323 12:19:42.723807 No KMS driver o<8>[ 21.764734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11324 12:19:42.724575 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11326 12:19:42.727186 r no outputs, pipes: 8, outputs: 0
11327 12:19:42.733711 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11328 12:19:42.734180 Opened device: /dev/dri/card0
11329 12:19:42.740482 Starting subtest: clobbe<14>[ 21.786177] [IGT] kms_addfb_basic: executing
11330 12:19:42.743703 rred-modifier
11331 12:19:42.753476 Test requirement not met in function igt_require_<14>[ 21.796454] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11332 12:19:42.763270 i915, file ../li<14>[ 21.805554] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11333 12:19:42.766495 b/drmtest.c:720:
11334 12:19:42.770261 Test requirement: is_i915_device(fd)
11335 12:19:42.779883 [1mSubtest clobberred-modifier: SKIP (0<14>[ 21.823183] [IGT] kms_addfb_basic: exiting, ret=77
11336 12:19:42.780311 .000s)[0m
11337 12:19:42.793247 Test requirement not met in function igt_require_i915, file ../lib/d<8>[ 21.834284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11338 12:19:42.794127 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11340 12:19:42.796507 rmtest.c:720:
11341 12:19:42.799667 Test requirement: is_i915_device(fd)
11342 12:19:42.806233 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11343 12:19:42.812853 Test requirement: is_i91<14>[ 21.856902] [IGT] kms_addfb_basic: executing
11344 12:19:42.813281 5_device(fd)
11345 12:19:42.819841 No KMS driver or no outputs, pipes: 8, outputs: 0
11346 12:19:42.822561 <14>[ 21.866836] [IGT] kms_addfb_basic: starting subtest legacy-format
11347 12:19:42.822988
11348 12:19:42.829451 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11349 12:19:42.839298 Opened dev<14>[ 21.881120] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11350 12:19:42.839772 ice: /dev/dri/card0
11351 12:19:42.845702 Starting subtest: invalid-smem-bo-on-discrete
11352 12:19:42.852476 Test requirement not met in <14>[ 21.896944] [IGT] kms_addfb_basic: exiting, ret=0
11353 12:19:42.855504 function igt_require_intel, file ../lib/drmtest.c:715:
11354 12:19:42.865755 Test requirement: is_int<8>[ 21.908196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11355 12:19:42.866457 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11357 12:19:42.868846 el_device(fd)
11358 12:19:42.872127 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11359 12:19:42.882291 Test requirement not met in function igt_require_i915, file ../lib/dr<14>[ 21.928864] [IGT] kms_addfb_basic: executing
11360 12:19:42.885712 mtest.c:720:
11361 12:19:42.889317 Test requirement: is_i915_device(fd)
11362 12:19:42.895273 Test requirement not met in <14>[ 21.940003] [IGT] kms_addfb_basic: starting subtest no-handle
11363 12:19:42.905212 function igt_req<14>[ 21.946831] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11364 12:19:42.908390 uire_i915, file ../lib/drmtest.c:720:
11365 12:19:42.911582 Test requirement: is_i915_device(fd)
11366 12:19:42.917987 No <14>[ 21.961009] [IGT] kms_addfb_basic: exiting, ret=0
11367 12:19:42.921614 KMS driver or no outputs, pipes: 8, outputs: 0
11368 12:19:42.928109 IGT-Version: 1.2<8>[ 21.971332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11369 12:19:42.928881 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11371 12:19:42.935531 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11372 12:19:42.936105 Opened device: /dev/dri/card0
11373 12:19:42.938526 Starting subtest: legacy-format
11374 12:19:42.944888 Successfully fuzzed 10000 {<14>[ 21.991785] [IGT] kms_addfb_basic: executing
11375 12:19:42.947833 bpp, depth} variations
11376 12:19:42.951148 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11377 12:19:42.957661 Test re<14>[ 22.002984] [IGT] kms_addfb_basic: starting subtest basic
11378 12:19:42.967775 quirement not me<14>[ 22.009460] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11379 12:19:42.970810 t in function igt_require_i915, file ../lib/drmtest.c:720:
11380 12:19:42.978267 Test requirement: is<14>[ 22.023133] [IGT] kms_addfb_basic: exiting, ret=0
11381 12:19:42.980998 _i915_device(fd)
11382 12:19:42.991605 Test requirement not met in function igt_require_i915, file ..<8>[ 22.035294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11383 12:19:42.992418 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11385 12:19:42.994218 /lib/drmtest.c:720:
11386 12:19:42.998059 Test requirement: is_i915_device(fd)
11387 12:19:43.000603 No KMS driver or no outputs, pipes: 8, outputs: 0
11388 12:19:43.010765 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1<14>[ 22.055354] [IGT] kms_addfb_basic: executing
11389 12:19:43.014392 .59-cip7 aarch64)
11390 12:19:43.014866 Opened device: /dev/dri/card0
11391 12:19:43.017236 Starting subtest: no-handle
11392 12:19:43.023888 <14>[ 22.067730] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11393 12:19:43.034631 [1mSubtest no-ha<14>[ 22.074773] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11394 12:19:43.035158 ndle: SUCCESS (0.000s)[0m
11395 12:19:43.043941 Test requirement not met in function igt_require_i91<14>[ 22.089069] [IGT] kms_addfb_basic: exiting, ret=0
11396 12:19:43.047129 5, file ../lib/drmtest.c:720:
11397 12:19:43.050659 Test requirement: is_i915_device(fd)
11398 12:19:43.056702 Test requir<8>[ 22.100927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11399 12:19:43.057391 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11401 12:19:43.064033 ement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11402 12:19:43.067451 Test requirement: is_i915_device(fd)
11403 12:19:43.074332 No KMS driver or no outputs, pipes: 8, outputs: 0
11404 12:19:43.077226 <14>[ 22.121600] [IGT] kms_addfb_basic: executing
11405 12:19:43.077742
11406 12:19:43.083580 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11407 12:19:43.091105 Opened dev<14>[ 22.134147] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11408 12:19:43.101041 ice: /dev/dri/ca<14>[ 22.141293] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11409 12:19:43.101554 rd0
11410 12:19:43.103821 Starting subtest: basic
11411 12:19:43.107057 [1mSubtest basic: SUCCESS (0.000s)[0m
11412 12:19:43.110113 Test requ<14>[ 22.155651] [IGT] kms_addfb_basic: exiting, ret=0
11413 12:19:43.116813 irement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11414 12:19:43.126395 Test r<8>[ 22.167465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11415 12:19:43.126817 equirement: is_i915_device(fd)
11416 12:19:43.127452 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11418 12:19:43.136314 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11419 12:19:43.140497 Test requirement: is_i915_device(fd)
11420 12:19:43.143141 No KMS <14>[ 22.188264] [IGT] kms_addfb_basic: executing
11421 12:19:43.146607 driver or no outputs, pipes: 8, outputs: 0
11422 12:19:43.156280 IGT-Version: 1.27.1-g621c2d3 (aarch6<14>[ 22.200891] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11423 12:19:43.166164 4) (Linux: 6.1.5<14>[ 22.207781] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11424 12:19:43.166692 9-cip7 aarch64)
11425 12:19:43.169195 Opened device: /dev/dri/card0
11426 12:19:43.172771 Starting subtest: bad-pitch-0
11427 12:19:43.179368 <14>[ 22.222238] [IGT] kms_addfb_basic: exiting, ret=0
11428 12:19:43.182756 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11429 12:19:43.192439 Test requirement not met in functi<8>[ 22.234305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11430 12:19:43.193131 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11432 12:19:43.195493 on igt_require_i915, file ../lib/drmtest.c:720:
11433 12:19:43.198802 Test requirement: is_i915_device(fd)
11434 12:19:43.208821 Test requirement not met in function igt_require_i915, file ../lib/drmtes<14>[ 22.254897] [IGT] kms_addfb_basic: executing
11435 12:19:43.212794 t.c:720:
11436 12:19:43.215797 Test requirement: is_i915_device(fd)
11437 12:19:43.225265 No KMS driver or no outputs, pip<14>[ 22.267391] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11438 12:19:43.231876 es: 8, outputs: <14>[ 22.274500] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11439 12:19:43.232350 0
11440 12:19:43.238919 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11441 12:19:43.245172 Opened d<14>[ 22.288929] [IGT] kms_addfb_basic: exiting, ret=0
11442 12:19:43.245591 evice: /dev/dri/card0
11443 12:19:43.248655 Starting subtest: bad-pitch-32
11444 12:19:43.258958 [1mSubte<8>[ 22.300587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11445 12:19:43.259640 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11447 12:19:43.261976 st bad-pitch-32: SUCCESS (0.000s)[0m
11448 12:19:43.268234 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11449 12:19:43.271500 Test requirement: is_i915_device(fd)
11450 12:19:43.275070 <14>[ 22.320411] [IGT] kms_addfb_basic: executing
11451 12:19:43.287842 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<14>[ 22.332887] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11452 12:19:43.288266 :
11453 12:19:43.298093 Test requirem<14>[ 22.340015] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11454 12:19:43.301410 ent: is_i915_device(fd)
11455 12:19:43.305101 No KMS driver or no outputs, pipes: 8, outputs: 0
11456 12:19:43.311317 IGT-<14>[ 22.354494] [IGT] kms_addfb_basic: exiting, ret=0
11457 12:19:43.314885 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11458 12:19:43.324353 Opened device: <8>[ 22.366553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11459 12:19:43.324783 /dev/dri/card0
11460 12:19:43.325452 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11462 12:19:43.327874 Starting subtest: bad-pitch-63
11463 12:19:43.330789 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11464 12:19:43.343999 Test requirement not met in function igt_require_i915, file ../l<14>[ 22.387258] [IGT] kms_addfb_basic: executing
11465 12:19:43.344553 ib/drmtest.c:720:
11466 12:19:43.347545 Test requirement: is_i915_device(fd)
11467 12:19:43.357697 Test requirement not me<14>[ 22.399713] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11468 12:19:43.364057 t in function ig<14>[ 22.406972] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11469 12:19:43.367418 t_require_i915, file ../lib/drmtest.c:720:
11470 12:19:43.377323 Test requirement: is_i915_device(fd)<14>[ 22.421531] [IGT] kms_addfb_basic: exiting, ret=0
11471 12:19:43.377747
11472 12:19:43.380738 No KMS driver or no outputs, pipes: 8, outputs: 0
11473 12:19:43.390502 IGT-Version: 1.27.1-g621c2d<8>[ 22.433594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11474 12:19:43.391193 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11476 12:19:43.393679 3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11477 12:19:43.397264 Opened device: /dev/dri/card0
11478 12:19:43.400421 Starting subtest: bad-pitch-128
11479 12:19:43.403741 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11480 12:19:43.411009 Test <14>[ 22.454286] [IGT] kms_addfb_basic: executing
11481 12:19:43.417035 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11482 12:19:43.423780 Te<14>[ 22.466901] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11483 12:19:43.433989 st requirement: <14>[ 22.473982] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11484 12:19:43.434513 is_i915_device(fd)
11485 12:19:43.443616 Test requirement not met in function igt_require_i915, file <14>[ 22.488422] [IGT] kms_addfb_basic: exiting, ret=0
11486 12:19:43.446802 ../lib/drmtest.c:720:
11487 12:19:43.450316 Test requirement: is_i915_device(fd)
11488 12:19:43.456859 No KMS driver or no<8>[ 22.500363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11489 12:19:43.457672 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11491 12:19:43.460161 outputs, pipes: 8, outputs: 0
11492 12:19:43.466833 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11493 12:19:43.469829 Opened device: /dev/dri/card0
11494 12:19:43.476419 Starting sub<14>[ 22.521110] [IGT] kms_addfb_basic: executing
11495 12:19:43.476844 test: bad-pitch-256
11496 12:19:43.483152 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11497 12:19:43.490087 Test requi<14>[ 22.532345] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11498 12:19:43.499565 rement not met i<14>[ 22.539637] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11499 12:19:43.502866 n function igt_require_i915, file ../lib/drmtest.c:720:
11500 12:19:43.509437 Test requirement: is_i9<14>[ 22.554199] [IGT] kms_addfb_basic: exiting, ret=0
11501 12:19:43.512837 15_device(fd)
11502 12:19:43.522300 Test requirement not met in function igt_require_<8>[ 22.565316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11503 12:19:43.523049 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11505 12:19:43.526021 i915, file ../lib/drmtest.c:720:
11506 12:19:43.529091 Test requirement: is_i915_device(fd)
11507 12:19:43.532875 No KMS driver or no outputs, pipes: 8, outputs: 0
11508 12:19:43.539215 IGT-Version: 1.27.1-g<14>[ 22.585372] [IGT] kms_addfb_basic: executing
11509 12:19:43.545486 621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11510 12:19:43.545917 Opened device: /dev/dri/card0
11511 12:19:43.549297 Starting subtest: bad-pitch-1024
11512 12:19:43.555701 <14>[ 22.598790] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11513 12:19:43.556312
11514 12:19:43.565565 [1mSubtest bad<14>[ 22.607398] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11515 12:19:43.569079 -pitch-1024: SUCCESS (0.000s)[0m
11516 12:19:43.575544 Test requirem<14>[ 22.620555] [IGT] kms_addfb_basic: exiting, ret=0
11517 12:19:43.582314 ent not met in function igt_require_i915, file ../lib/drmtest.c:720:
11518 12:19:43.588767 Test requi<8>[ 22.631639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11519 12:19:43.589506 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11521 12:19:43.592082 rement: is_i915_device(fd)
11522 12:19:43.598602 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11523 12:19:43.608659 Test requirement: is_i915_device(<14>[ 22.653234] [IGT] kms_addfb_basic: executing
11524 12:19:43.609084 fd)
11525 12:19:43.611898 No KMS driver or no outputs, pipes: 8, outputs: 0
11526 12:19:43.625535 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-ci<14>[ 22.666729] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11527 12:19:43.626058 p7 aarch64)
11528 12:19:43.632090 Ope<14>[ 22.674763] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11529 12:19:43.635336 ned device: /dev/dri/card0
11530 12:19:43.641921 Starting subtest: ba<14>[ 22.687522] [IGT] kms_addfb_basic: exiting, ret=0
11531 12:19:43.645307 d-pitch-999
11532 12:19:43.648355 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11533 12:19:43.658653 Test requirement n<8>[ 22.698532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11534 12:19:43.659498 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11536 12:19:43.661374 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11537 12:19:43.664856 Test requirement: is_i915_device(fd)
11538 12:19:43.674865 Test requirement not met in function igt_require_i915, fi<14>[ 22.719893] [IGT] kms_addfb_basic: executing
11539 12:19:43.678441 le ../lib/drmtest.c:720:
11540 12:19:43.681420 Test requirement: is_i915_device(fd)
11541 12:19:43.691064 No KMS driver or no outputs, pipes: 8, outputs: <14>[ 22.734125] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11542 12:19:43.691627 0
11543 12:19:43.701622 IGT-Version: <14>[ 22.742731] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11544 12:19:43.711258 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aa<14>[ 22.755912] [IGT] kms_addfb_basic: exiting, ret=0
11545 12:19:43.711839 rch64)
11546 12:19:43.714701 Opened device: /dev/dri/card0
11547 12:19:43.717517 Starting subtest: bad-pitch-65536
11548 12:19:43.724407 [1mSu<8>[ 22.766801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11549 12:19:43.725237 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11551 12:19:43.731431 btest bad-pitch-65536: SUCCESS (0.000s)[0m
11552 12:19:43.737723 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11553 12:19:43.744333 Test requirement<14>[ 22.788121] [IGT] kms_addfb_basic: executing
11554 12:19:43.744856 : is_i915_device(fd)
11555 12:19:43.750877 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11556 12:19:43.760412 Test re<14>[ 22.801361] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11557 12:19:43.767650 quirement: is_i9<14>[ 22.809551] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11558 12:19:43.770666 15_device(fd)
11559 12:19:43.777067 No KMS driver or no outputs, pipe<14>[ 22.822364] [IGT] kms_addfb_basic: exiting, ret=0
11560 12:19:43.780385 s: 8, outputs: 0
11561 12:19:43.790350 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aar<8>[ 22.833464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11562 12:19:43.791046 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11564 12:19:43.793823 ch64)
11565 12:19:43.794347 Opened device: /dev/dri/card0
11566 12:19:43.796768 Starting subtest: invalid-get-prop-any
11567 12:19:43.803204 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11568 12:19:43.810244 Test requi<14>[ 22.854485] [IGT] kms_addfb_basic: executing
11569 12:19:43.816604 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11570 12:19:43.819845 Test requirement: is_i915_device(fd)
11571 12:19:43.826525 Test requirement <14>[ 22.869742] [IGT] kms_addfb_basic: starting subtest master-rmfb
11572 12:19:43.832944 not met in funct<14>[ 22.876859] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11573 12:19:43.843149 ion igt_require_i915, file ../li<14>[ 22.887332] [IGT] kms_addfb_basic: exiting, ret=0
11574 12:19:43.843659 b/drmtest.c:720:
11575 12:19:43.846142 Test requirement: is_i915_device(fd)
11576 12:19:43.856249 No KMS driver or no outp<8>[ 22.898921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11577 12:19:43.856939 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11579 12:19:43.859884 uts, pipes: 8, outputs: 0
11580 12:19:43.866329 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11581 12:19:43.866757 Opened device: /dev/dri/card0
11582 12:19:43.876431 Starting subtest: invalid-get-pro<14>[ 22.919670] [IGT] kms_addfb_basic: executing
11583 12:19:43.876847 p
11584 12:19:43.879457 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11585 12:19:43.885918 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11586 12:19:43.895914 Test r<14>[ 22.937783] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11587 12:19:43.905844 equirement: is_i<14>[ 22.945685] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11588 12:19:43.906402 915_device(fd)
11589 12:19:43.912481 <14>[ 22.955302] [IGT] kms_addfb_basic: exiting, ret=0
11590 12:19:43.925403 Test requirement not met in function igt_require_i915, file ../l<8>[ 22.966311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11591 12:19:43.925635 ib/drmtest.c:720:
11592 12:19:43.926026 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11594 12:19:43.928734 Test requirement: is_i915_device(fd)
11595 12:19:43.935350 No KMS driver or no outputs, pipes: 8, outputs: 0
11596 12:19:43.942244 IGT-Version: 1.27.1-g621c2d3 (aarch6<14>[ 22.987531] [IGT] kms_addfb_basic: executing
11597 12:19:43.945554 4) (Linux: 6.1.59-cip7 aarch64)
11598 12:19:43.948857 Opened device: /dev/dri/card0
11599 12:19:43.952028 Starting subtest: invalid-set-prop-any
11600 12:19:43.962327 [1mSubtest invalid-set-prop-any: SUCCES<14>[ 23.004840] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11601 12:19:43.962844 S (0.000s)[0m
11602 12:19:43.975309 Test requirement not met in function igt_require<14>[ 23.017277] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11603 12:19:43.981768 _i915, file ../l<14>[ 23.025488] [IGT] kms_addfb_basic: exiting, ret=98
11604 12:19:43.982164 ib/drmtest.c:720:
11605 12:19:43.985391 Test requirement: is_i915_device(fd)
11606 12:19:43.995333 Test requirement not me<8>[ 23.038027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11607 12:19:43.996034 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11609 12:19:44.001981 t in function igt_require_i915, file ../lib/drmtest.c:720:
11610 12:19:44.005164 Test requirement: is_i915_device(fd)
11611 12:19:44.008507 No KMS driver or no outputs, pipes: 8, outputs: 0
11612 12:19:44.014825 IGT-Version<14>[ 23.059118] [IGT] kms_addfb_basic: executing
11613 12:19:44.018456 : 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11614 12:19:44.021743 Opened device: /dev/dri/card0
11615 12:19:44.025129 Starting subtest: invalid-set-prop
11616 12:19:44.031820 [1mSubtest invalid<14>[ 23.077620] [IGT] kms_addfb_basic: exiting, ret=77
11617 12:19:44.035106 -set-prop: SUCCESS (0.000s)[0m
11618 12:19:44.044874 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11620 12:19:44.047948 Test requirement not met in fun<8>[ 23.087380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11621 12:19:44.051216 ction igt_require_i915, file ../lib/drmtest.c:720:
11622 12:19:44.054851 Test requirement: is_i915_device(fd)
11623 12:19:44.064748 Test requirement not met in function igt_require_i915, file ../lib/drm<14>[ 23.109628] [IGT] kms_addfb_basic: executing
11624 12:19:44.065142 test.c:720:
11625 12:19:44.068180 Test requirement: is_i915_device(fd)
11626 12:19:44.075153 No KMS driver or no outputs, pipes: 8, outputs: 0
11627 12:19:44.081377 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Li<14>[ 23.128110] [IGT] kms_addfb_basic: exiting, ret=77
11628 12:19:44.084817 nux: 6.1.59-cip7 aarch64)
11629 12:19:44.087823 Opened device: /dev/dri/card0
11630 12:19:44.094704 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11632 12:19:44.097763 Starti<8>[ 23.138305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11633 12:19:44.098292 ng subtest: master-rmfb
11634 12:19:44.101432 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11635 12:19:44.114378 Test requirement not met in function igt_require_i915, file ../lib/drmte<14>[ 23.159181] [IGT] kms_addfb_basic: executing
11636 12:19:44.114788 st.c:720:
11637 12:19:44.117605 Test requirement: is_i915_device(fd)
11638 12:19:44.124157 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11639 12:19:44.130826 Test requirement: is_i915_de<14>[ 23.176794] [IGT] kms_addfb_basic: exiting, ret=77
11640 12:19:44.134277 vice(fd)
11641 12:19:44.137391 No KMS driver or no outputs, pipes: 8, outputs: 0
11642 12:19:44.147592 IGT<8>[ 23.187679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11643 12:19:44.148416 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11645 12:19:44.154451 -Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11646 12:19:44.154990 Opened device: /dev/dri/card0
11647 12:19:44.161066 Starting subtest: addfb25-modifier-no-flag
11648 12:19:44.164237 [1<14>[ 23.209629] [IGT] kms_addfb_basic: executing
11649 12:19:44.167508 mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11650 12:19:44.178036 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11651 12:19:44.180882 Test requirement: is_i915_device(fd)
11652 12:19:44.187947 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11653 12:19:44.190780 Test requirement: is_i915_device(fd)
11654 12:19:44.193839 No KMS driver or no outputs, pipes: 8, outputs: 0
11655 12:19:44.200833 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11656 12:19:44.204849 Opened device: /dev/dri/card0
11657 12:19:44.207556 Starting subtest: addfb25-bad-modifier
11658 12:19:44.217335 (kms_addfb_basic:437) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11659 12:19:44.233954 (kms_addfb_basic:437) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11660 12:19:44.240467 (kms_addfb_basic:437) CRITICAL: error: 0 != -1
11661 12:19:44.240978 Stack trace:
11662 12:19:44.243831 #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11663 12:19:44.247042 #1 [<unknown>+0xd81147e0]
11664 12:19:44.250424 #2 [<unknown>+0xd8116278]
11665 12:19:44.253762 #3 [<unknown>+0xd811167c]
11666 12:19:44.254275 #4 [__libc_start_main+0xe8]
11667 12:19:44.256896 #5 [<unknown>+0xd81116b4]
11668 12:19:44.260134 #6 [<unknown>+0xd81116b4]
11669 12:19:44.263874 Subtest addfb25-bad-modifier failed.
11670 12:19:44.264405 **** DEBUG ****
11671 12:19:44.273792 (kms_addfb_basic:437) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11672 12:19:44.283416 (kms_addfb_basic:437) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11673 12:19:44.300128 (kms_addfb_basic:437) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11674 12:19:44.307047 (kms_addfb_basic:437) CRITICAL: error: 0 != -1
11675 12:19:44.310093 (kms_addfb_basic:437) igt_core-INFO: Stack trace:
11676 12:19:44.316698 (kms_addfb_basic:437) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11677 12:19:44.323928 (kms_addfb_basic:437) igt_core-INFO: #1 [<unknown>+0xd81147e0]
11678 12:19:44.329737 (kms_addfb_basic:437) igt_core-INFO: #2 [<unknown>+0xd8116278]
11679 12:19:44.333142 (kms_addfb_basic:437) igt_core-INFO: #3 [<unknown>+0xd811167c]
11680 12:19:44.339973 (kms_addfb_basic:437) igt_core-INFO: #4 [__libc_start_main+0xe8]
11681 12:19:44.346798 (kms_addfb_basic:437) igt_core-INFO: #5 [<unknown>+0xd81116b4]
11682 12:19:44.353093 (kms_addfb_basic:437) igt_core-INFO: #6 [<unknown>+0xd81116b4]
11683 12:19:44.353620 **** END ****
11684 12:19:44.356034 [1mSubtest addfb25-bad-modifier: FAIL (0.005s)[0m
11685 12:19:44.366530 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11686 12:19:44.369727 Test requirement: is_i915_device(fd)
11687 12:19:44.375995 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11688 12:19:44.379578 Test requirement: is_i915_device(fd)
11689 12:19:44.382926 No KMS driver or no outputs, pipes: 8, outputs: 0
11690 12:19:44.389085 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11691 12:19:44.392896 Opened device: /dev/dri/card0
11692 12:19:44.399122 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11693 12:19:44.402810 Test requirement: is_i915_device(fd)
11694 12:19:44.409435 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11695 12:19:44.416048 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11696 12:19:44.419188 Test requirement: is_i915_device(fd)
11697 12:19:44.422615 No KMS driver or no outputs, pipes: 8, outputs: 0
11698 12:19:44.429088 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11699 12:19:44.432775 Opened device: /dev/dri/card0
11700 12:19:44.439434 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11701 12:19:44.442847 Test requirement: is_i915_device(fd)
11702 12:19:44.445586 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11703 12:19:44.455762 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11704 12:19:44.459163 Test requirement: is_i915_device(fd)
11705 12:19:44.462183 No KMS driver or no outputs, pipes: 8, outputs: 0
11706 12:19:44.468737 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11707 12:19:44.471989 Opened device: /dev/dri/card0
11708 12:19:44.478819 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11709 12:19:44.482024 Test requirement: is_i915_device(fd)
11710 12:19:44.488617 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11711 12:19:44.495282 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11712 12:19:44.497819 Test requirement: is_i915_device(fd)
11713 12:19:44.501630 No KMS driver or no outputs, pipes: 8, outputs: 0
11714 12:19:44.508223 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11715 12:19:44.511449 Opened device: /dev/dri/card0
11716 12:19:44.514941 T<14>[ 23.559786] [IGT] kms_addfb_basic: exiting, ret=77
11717 12:19:44.527718 est requirement not met in function igt_require_i915, file ../li<8>[ 23.570567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11718 12:19:44.528471 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11720 12:19:44.530915 b/drmtest.c:720:
11721 12:19:44.534162 Test requirement: is_i915_device(fd)
11722 12:19:44.540843 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11723 12:19:44.544178 Test <14>[ 23.591084] [IGT] kms_addfb_basic: executing
11724 12:19:44.547363 requirement: is_i915_device(fd)
11725 12:19:44.554135 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11726 12:19:44.557904 No KMS driver or no outputs, pipes: 8, outputs: 0
11727 12:19:44.564209 IGT-Version: 1.27.1-g62<14>[ 23.609139] [IGT] kms_addfb_basic: exiting, ret=77
11728 12:19:44.567788 1c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11729 12:19:44.577410 Opened device: /de<8>[ 23.620275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11730 12:19:44.578100 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11732 12:19:53.880728 v/dri/card0
11733 12:19:53.880840 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11734 12:19:53.880955 Test requirement: is_i915_device(fd)
11735 12:19:53.881069 Test requi<14>[ 23.641484] [IGT] kms_addfb_basic: executing
11736 12:19:53.881180 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11737 12:19:53.881278 Test requirement: is_i915_device(fd)
11738 12:19:53.881369 [1mSubtest framebuffer-vs-set-ti<14>[ 23.658995] [IGT] kms_addfb_basic: exiting, ret=77
11739 12:19:53.881454 ling: SKIP (0.000s)[0m
11740 12:19:53.881539 No KMS driver or no outputs, pipes: 8, <8>[ 23.669071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11741 12:19:53.881624 outputs: 0
11742 12:19:53.881681 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11743 12:19:53.881736 Opened device: /dev/dri/card0
11744 12:19:53.881789 Test requirement not met in func<14>[ 23.689270] [IGT] kms_addfb_basic: executing
11745 12:19:53.881843 tion igt_require_i915, file ../lib/drmtest.c:720:
11746 12:19:53.881897 Test requirement: is_i915_device(fd)
11747 12:19:53.881956 Test requirement not met in function igt_require_i915, <14>[ 23.707179] [IGT] kms_addfb_basic: exiting, ret=77
11748 12:19:53.882010 file ../lib/drmtest.c:720:
11749 12:19:53.882063 Test requirement: is_i915_device(fd)<8>[ 23.717215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11750 12:19:53.882117
11751 12:19:53.882170 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11752 12:19:53.882228 No KMS driver or no outputs, pipes: 8, outputs: 0
11753 12:19:53.882314 IGT-Version: 1.27.1-g621c2d3 (aarch64) <14>[ 23.737474] [IGT] kms_addfb_basic: executing
11754 12:19:53.882396 (Linux: 6.1.59-cip7 aarch64)
11755 12:19:53.882477 Opened device: /dev/dri/card0
11756 12:19:53.882548 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11757 12:19:53.882603 <14>[ 23.755353] [IGT] kms_addfb_basic: exiting, ret=77
11758 12:19:53.882657 Test requirement: is_i915_device(fd)
11759 12:19:53.882710 Test requirement not met i<8>[ 23.765494] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11760 12:19:53.882764 n function igt_require_i915, file ../lib/drmtest.c:720:
11761 12:19:53.882821 Test requirement: is_i915_device(fd)
11762 12:19:53.882932 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[<14>[ 23.785334] [IGT] kms_addfb_basic: executing
11763 12:19:53.883039 0m
11764 12:19:53.883148 No KMS driver or no outputs, pipes: 8, outputs: 0
11765 12:19:53.883257 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11766 12:19:53.883363 Opened device: /dev/dri/card0
11767 12:19:53.883511 Test <14>[ 23.802745] [IGT] kms_addfb_basic: exiting, ret=77
11768 12:19:53.883621 requirement not met in function igt_require_i915, file ../lib/dr<8>[ 23.813917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11769 12:19:53.883723 mtest.c:720:
11770 12:19:53.883787 Test requirement: is_i915_device(fd)
11771 12:19:53.883842 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11772 12:19:53.883896 Test requ<14>[ 23.833109] [IGT] kms_addfb_basic: executing
11773 12:19:53.883949 irement: is_i915_device(fd)
11774 12:19:53.884002 No KMS driver or no outputs, pipes: 8, outputs: 0
11775 12:19:53.884059 [1mSubtest size-max: SKIP (0.000s)[0m
11776 12:19:53.884113 IGT-Version: 1.27.1-g62<14>[ 23.851184] [IGT] kms_addfb_basic: exiting, ret=77
11777 12:19:53.884165 1c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11778 12:19:53.884220 Opened device: /de<8>[ 23.861264] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11779 12:19:53.884273 v/dri/card0
11780 12:19:53.884326 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11781 12:19:53.884385 Test requirement: is_i915_device(fd)
11782 12:19:53.884438 Test requi<14>[ 23.880343] [IGT] kms_addfb_basic: executing
11783 12:19:53.884491 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11784 12:19:53.884544 Test requirement: is_i915_device(fd)
11785 12:19:53.884596 No KMS driver or no outputs, pipes: 8, outputs: 0<14>[ 23.898429] [IGT] kms_addfb_basic: exiting, ret=77
11786 12:19:53.884657
11787 12:19:53.884715 [1mSubtest too-wide: SKIP (0.000s)[0m
11788 12:19:53.884771 IGT-Version: 1.27.1-g<8>[ 23.909636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11789 12:19:53.884824 621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11790 12:19:53.884879 Opened device: /dev/dri/card0
11791 12:19:53.884933 Test requirement not met in function igt_require_i915, file ../li<14>[ 23.929116] [IGT] kms_addfb_basic: executing
11792 12:19:53.885006 b/drmtest.c:720:
11793 12:19:53.885089 Test requirement: is_i915_device(fd)
11794 12:19:53.885172 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11795 12:19:53.885255 Test requirement: is_<14>[ 23.947326] [IGT] kms_addfb_basic: exiting, ret=77
11796 12:19:53.885340 i915_device(fd)
11797 12:19:53.885424 No KMS driver or no outputs, pipes: 8, outputs:<8>[ 23.958744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11798 12:19:53.885507 0
11799 12:19:53.885592 [1mSubtest too-high: SKIP (0.000s)[0m
11800 12:19:53.885676 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11801 12:19:53.885758 Opened device: /dev/dri/card0
11802 12:19:53.885841 <14>[ 23.978451] [IGT] kms_addfb_basic: executing
11803 12:19:53.885925
11804 12:19:53.886194 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11806 12:19:53.886569 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11808 12:19:53.886947 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11810 12:19:53.887268 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11812 12:19:53.887540 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11814 12:19:53.887827 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11816 12:19:53.888026 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11818 12:19:53.888321 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11819 12:19:53.888415 Test requirement: is_i915_device(fd)
11820 12:19:53.888505 Test requirement not met in function i<14>[ 23.995913] [IGT] kms_addfb_basic: exiting, ret=77
11821 12:19:53.888595 gt_require_i915, file ../lib/drmtest.c:720:
11822 12:19:53.888681 Test requirement: i<8>[ 24.007160] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11823 12:19:53.888766 s_i915_device(fd)
11824 12:19:53.888852 No KMS driver or no outputs, pipes: 8, outputs: 0
11825 12:19:53.888937 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11826 12:19:53.889020 IGT-Version: 1.27.1-g621c2d3 <14>[ 24.028444] [IGT] kms_addfb_basic: executing
11827 12:19:53.889104 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11828 12:19:53.889190 Opened device: /dev/dri/card0
11829 12:19:53.889274 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11830 12:19:53.889358 Test r<14>[ 24.045857] [IGT] kms_addfb_basic: exiting, ret=77
11831 12:19:53.889443 equirement: is_i915_device(fd)
11832 12:19:53.889527 Test requirement not met in func<8>[ 24.057110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11833 12:19:53.889611 tion igt_require_i915, file ../lib/drmtest.c:720:
11834 12:19:53.889694 Test requirement: is_i915_device(fd)
11835 12:19:53.889780 No KMS driver or no outputs, pipes: 8, outputs: 0
11836 12:19:53.889864 [1m<14>[ 24.077871] [IGT] kms_addfb_basic: executing
11837 12:19:53.889947 Subtest small-bo: SKIP (0.000s)[0m
11838 12:19:53.890032 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11839 12:19:53.890115 Opened device: /dev/dri/card0
11840 12:19:53.890201 Test re<14>[ 24.095642] [IGT] kms_addfb_basic: exiting, ret=77
11841 12:19:53.890287 quirement not met in function igt_require_i915, file ../lib/drmt<8>[ 24.105755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11842 12:19:53.890374 est.c:720:
11843 12:19:53.890456 Test requirement: is_i915_device(fd)
11844 12:19:53.890539 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11845 12:19:53.890623 Test requir<14>[ 24.126178] [IGT] kms_addfb_basic: executing
11846 12:19:53.890683 ement: is_i915_device(fd)
11847 12:19:53.890737 No KMS driver or no outputs, pipes: 8, outputs: 0
11848 12:19:53.890791 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11849 12:19:53.890845 IGT-Ver<14>[ 24.144008] [IGT] kms_addfb_basic: exiting, ret=77
11850 12:19:53.890899 sion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11851 12:19:53.890964 Op<8>[ 24.153968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11852 12:19:53.891048 ened device: /dev/dri/card0
11853 12:19:53.891131 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11854 12:19:53.891213 Test requirement: is_i915_device(fd)
11855 12:19:53.891299 Test requi<14>[ 24.175728] [IGT] kms_addfb_basic: executing
11856 12:19:53.891388 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11857 12:19:53.891480 Test requirement: is_i915_device(fd)
11858 12:19:53.891535 No KMS driver or no outputs, pipes: 8, outputs: 0<14>[ 24.194463] [IGT] kms_addfb_basic: exiting, ret=77
11859 12:19:53.891597
11860 12:19:53.891651 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11861 12:19:53.891705 IGT-Ver<8>[ 24.205359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11862 12:19:53.891759 sion: 1.27.1-g621c2d3 (aarch64) <8>[ 24.215124] <LAVA_SIGNAL_TESTSET STOP>
11863 12:19:53.891812 (Linux: 6.1.59-cip7 aarch64)
11864 12:19:53.891865 Opened device: /dev/dri/card0
11865 12:19:53.891923 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11866 12:19:53.891977 Test requirement: is_i915_device<8>[ 24.235391] <LAVA_SIGNAL_TESTSET START kms_atomic>
11867 12:19:53.892036 (fd)
11868 12:19:53.892095 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11869 12:19:53.892149 Test requirement: is_i915_device(fd)
11870 12:19:53.892209 No KMS driver or no outputs, pipe<14>[ 24.253694] [IGT] kms_atomic: executing
11871 12:19:53.892264 s: 8, outputs: 0<14>[ 24.259459] [IGT] kms_atomic: exiting, ret=77
11872 12:19:53.892317
11873 12:19:53.892370 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11874 12:19:53.892423 IGT-Ve<8>[ 24.269792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11875 12:19:53.892481 rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11876 12:19:53.892590 Opened device: /dev/dri/card0
11877 12:19:53.892699 Test requirement not met in function igt_require_i<14>[ 24.290506] [IGT] kms_atomic: executing
11878 12:19:53.892808 915, file ../lib<14>[ 24.295592] [IGT] kms_atomic: exiting, ret=77
11879 12:19:53.892919 /drmtest.c:720:
11880 12:19:53.893024 Test requirement: is_i915_device(fd)
11881 12:19:53.893133 Test requ<8>[ 24.305991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11882 12:19:53.893241 irement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11883 12:19:53.893343 Test requirement: is_i915_device(fd)
11884 12:19:53.893432 No KMS driver or no outputs, pip<14>[ 24.326869] [IGT] kms_atomic: executing
11885 12:19:53.893518 es: 8, outputs: <14>[ 24.331767] [IGT] kms_atomic: exiting, ret=77
11886 12:19:53.893601 0
11887 12:19:53.893686 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11888 12:19:53.893956 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11890 12:19:53.894288 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11892 12:19:53.894533 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11894 12:19:53.894717 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11896 12:19:53.894906 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11898 12:19:53.895182 Received signal: <TESTSET> STOP
11899 12:19:53.895273 Closing test_set kms_addfb_basic
11900 12:19:53.895442 Received signal: <TESTSET> START kms_atomic
11901 12:19:53.895517 Starting test_set kms_atomic
11902 12:19:53.895600 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11904 12:19:53.895789 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11906 12:19:53.895992 <8>[ 24.341943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11907 12:19:53.896100 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11908 12:19:53.896210 Opened device: /dev/dri/card0
11909 12:19:53.896323 Test requirement not met in function igt_req<14>[ 24.363886] [IGT] kms_atomic: executing
11910 12:19:53.896434 uire_i915, file <14>[ 24.369317] [IGT] kms_atomic: exiting, ret=77
11911 12:19:53.896541 ../lib/drmtest.c:720:
11912 12:19:53.896651 Test requirement: is_i915_device(fd)
11913 12:19:53.896760 Tes<8>[ 24.379467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11914 12:19:53.896870 t requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11915 12:19:53.896980 Test requirement: is_i915_device(fd)
11916 12:19:53.897089 No KMS driver or no output<14>[ 24.400774] [IGT] kms_atomic: executing
11917 12:19:53.897200 s, pipes: 8, out<14>[ 24.405421] [IGT] kms_atomic: exiting, ret=77
11918 12:19:53.897309 puts: 0
11919 12:19:53.897400 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11920 12:19:53.897488 IGT-Ver<8>[ 24.415639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11921 12:19:53.897573 sion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11922 12:19:53.897656 Opened device: /dev/dri/card0
11923 12:19:53.897740 No KMS driver or no outputs, pipes: 8, outputs: 0
11924 12:19:53.897797 <14>[ 24.435409] [IGT] kms_atomic: executing
11925 12:19:53.897852 [1mSubtest plan<14>[ 24.440857] [IGT] kms_atomic: exiting, ret=77
11926 12:19:53.897906 e-overlay-legacy: SKIP (0.000s)[0m
11927 12:19:53.897960 IGT-Version: 1.27.1-g621c2d<8>[ 24.451312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11928 12:19:53.898014 3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11929 12:19:53.898075 Opened device: /dev/dri/card0
11930 12:19:53.898129 No KMS driver or no outputs, pipes: 8, outputs: 0
11931 12:19:53.898183 [1mSubtest plane-pr<14>[ 24.471490] [IGT] kms_atomic: executing
11932 12:19:53.898236 imary-legacy: SK<14>[ 24.477049] [IGT] kms_atomic: exiting, ret=77
11933 12:19:53.898289 IP (0.000s)[0m
11934 12:19:53.898346 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: <8>[ 24.487423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11935 12:19:53.898402 6.1.59-cip7 aarch64)
11936 12:19:53.898456 Opened device: /dev/dri/card0
11937 12:19:53.898510 No KMS driver or no outputs, pipes: 8, outputs: 0
11938 12:19:53.898611 [1mSubtest plane-primary-overlay-mutabl<14>[ 24.507861] [IGT] kms_atomic: executing
11939 12:19:53.898725 e-zpos: SKIP (0.<14>[ 24.513083] [IGT] kms_atomic: exiting, ret=77
11940 12:19:53.898834 000s)[0m
11941 12:19:53.898948 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59<8>[ 24.523266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11942 12:19:53.899048 -cip7 aarch64)
11943 12:19:53.899107 Opened device: /dev/dri/card0
11944 12:19:53.899167 No KMS driver or no outputs, pipes: 8, outputs: 0
11945 12:19:53.899283 [1mSubtest plane-immutable-zpos: SKIP (0.000s<14>[ 24.544532] [IGT] kms_atomic: executing
11946 12:19:53.899372 )[0m
11947 12:19:53.899474 IGT-Versi<14>[ 24.549770] [IGT] kms_atomic: exiting, ret=77
11948 12:19:53.899533 on: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11949 12:19:53.899626 Open<8>[ 24.560151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11950 12:19:53.899683 ed device: /dev/dri/card0
11951 12:19:53.899738 No KMS driver or no outputs, pipes: 8, outputs: 0
11952 12:19:53.899792 [1mSubtest test-only: SKIP (0.000s)[0m
11953 12:19:53.899846 IGT-Version: 1.27.1-g621<14>[ 24.580933] [IGT] kms_atomic: executing
11954 12:19:53.899900 c2d3 (aarch64) (<14>[ 24.585849] [IGT] kms_atomic: exiting, ret=77
11955 12:19:53.899956 Linux: 6.1.59-cip7 aarch64)
11956 12:19:53.900012 Opened device: /dev/dri/card0
11957 12:19:53.900065 No K<8>[ 24.596116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11958 12:19:53.900120 MS driver or no outputs, pipes: 8, outputs: 0
11959 12:19:53.900173 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11960 12:19:53.900226 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux<14>[ 24.617570] [IGT] kms_atomic: executing
11961 12:19:53.900280 : 6.1.59-cip7 aa<14>[ 24.622495] [IGT] kms_atomic: exiting, ret=77
11962 12:19:53.900333 rch64)
11963 12:19:53.900386 Opened device: /dev/dri/card0
11964 12:19:53.900438 No KMS driver or no outpu<8>[ 24.632978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11965 12:19:53.900492 ts, pipes: 8, outputs: 0
11966 12:19:53.900545 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11967 12:19:53.900597 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch6<14>[ 24.653692] [IGT] kms_atomic: executing
11968 12:19:53.900651 4)
11969 12:19:53.900704 Opened devic<14>[ 24.658712] [IGT] kms_atomic: exiting, ret=77
11970 12:19:53.900758 e: /dev/dri/card0
11971 12:19:53.900810 No KMS driver or no outputs, pipes: 8, output<8>[ 24.669385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11972 12:19:53.900865 s: 0
11973 12:19:53.900917 [1mSubtest plane-invalid-<8>[ 24.679233] <LAVA_SIGNAL_TESTSET STOP>
11974 12:19:53.900970 params-fence: SKIP (0.000s)[0m
11975 12:19:53.901023 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
11976 12:19:53.901075 Opened device: /dev/dri/card0
11977 12:19:53.901306 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11979 12:19:53.901488 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11981 12:19:53.901671 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11983 12:19:53.901854 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11985 12:19:53.902036 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11987 12:19:53.902219 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11989 12:19:53.902399 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11991 12:19:53.902579 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11993 12:19:53.902759 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11995 12:19:53.902937 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11997 12:19:53.903115 Received signal: <TESTSET> STOP
11998 12:19:53.903176 Closing test_set kms_atomic
11999 12:19:53.903272 No KMS driver or no outputs, pipes: 8, outp<8>[ 24.699278] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12000 12:19:53.903424 uts: 0
12001 12:19:53.903487 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12002 12:19:53.903545 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12003 12:19:53.903602 Opened device: /dev/dri/card0
12004 12:19:53.903658 No KMS driver or<14>[ 24.720830] [IGT] kms_flip_event_leak: executing
12005 12:19:53.903713 no outputs, pip<14>[ 24.726571] [IGT] kms_flip_event_leak: exiting, ret=77
12006 12:19:53.903767 es: 8, outputs: 0
12007 12:19:53.903821 [1mSubtest crtc-invalid-params-fence: SKIP (<8>[ 24.737590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12008 12:19:53.903875 0.000s)[0m
12009 12:19:53.903930 IGT-Version: 1.27.1<8>[ 24.746461] <LAVA_SIGNAL_TESTSET STOP>
12010 12:19:53.903984 -g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12011 12:19:53.904039 Opened device: /dev/dri/card0
12012 12:19:53.904092 No KMS driver or no outputs, pipes: 8, outputs: 0
12013 12:19:53.904148 [1mSubtest atomic-invalid-params: SKIP (0.0<8>[ 24.766772] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12014 12:19:53.904201 00s)[0m
12015 12:19:53.904255 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12016 12:19:53.904309 Opened device: /dev/dri/card0
12017 12:19:53.904362 No KMS driver or no outputs, pipes<14>[ 24.784682] [IGT] kms_prop_blob: executing
12018 12:19:53.904416 : 8, outputs: 0
12019 12:19:53.904469 <14>[ 24.789691] [IGT] kms_prop_blob: starting subtest basic
12020 12:19:53.904523 <14>[ 24.796466] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12021 12:19:53.904576 <14>[ 24.802871] [IGT] kms_prop_blob: exiting, ret=0
12022 12:19:53.904629
12023 12:19:53.904683 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
12024 12:19:53.904735 IGT-Version<8>[ 24.812238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12025 12:19:53.904789 : 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12026 12:19:53.904842 Opened device: /dev/dri/card0
12027 12:19:53.904894 No KMS driver or no outputs, pipes: 8, outputs: 0
12028 12:19:53.904948 [1m<14>[ 24.831140] [IGT] kms_prop_blob: executing
12029 12:19:53.905000 Subtest basic: S<14>[ 24.837142] [IGT] kms_prop_blob: starting subtest blob-prop-core
12030 12:19:53.905054 KIP (0.000s)[0m<14>[ 24.844624] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12031 12:19:53.905107
12032 12:19:53.905159 IGT-Version: 1<14>[ 24.853203] [IGT] kms_prop_blob: exiting, ret=0
12033 12:19:53.905213 .27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12034 12:19:53.905267 Opened de<8>[ 24.864177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12035 12:19:53.905321 vice: /dev/dri/card0
12036 12:19:53.905420 Starting subtest: basic
12037 12:19:53.905503 [1mSubtest basic: SUCCESS (0.000s)[0m
12038 12:19:53.905570 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-ci<14>[ 24.883586] [IGT] kms_prop_blob: executing
12039 12:19:53.905622 p7 aarch64)
12040 12:19:53.905675 Ope<14>[ 24.889622] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12041 12:19:53.905729 ned device: /dev<14>[ 24.897471] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12042 12:19:53.905783 <14>[ 24.906344] [IGT] kms_prop_blob: exiting, ret=0
12043 12:19:53.905836 /dri/card0
12044 12:19:53.905888 Starting subtest: blob-prop-core
12045 12:19:53.905940 [1mSubtest blob-p<8>[ 24.915512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12046 12:19:53.905994 rop-core: SUCCESS (0.000s)[0m
12047 12:19:53.906047 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12048 12:19:53.906100 Opened device: /dev/dri/card0
12049 12:19:53.906152 Starting sub<14>[ 24.936298] [IGT] kms_prop_blob: executing
12050 12:19:53.906205 test: blob-prop-<14>[ 24.941699] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12051 12:19:53.906258 validate
12052 12:19:53.906310 [1mSu<14>[ 24.949612] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12053 12:19:53.906363 <14>[ 24.958492] [IGT] kms_prop_blob: exiting, ret=0
12054 12:19:53.906417 btest blob-prop-validate: SUCCESS (0.000s)[0m
12055 12:19:53.906470 IGT-Version: 1.2<8>[ 24.967871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12056 12:19:53.906523 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12057 12:19:53.906577 Opened device: /dev/dri/card0
12058 12:19:53.906630 Starting subtest: blob-prop-lifetime
12059 12:19:53.906683 [1mSubtest blob-prop-<14>[ 24.988433] [IGT] kms_prop_blob: executing
12060 12:19:53.906736 lifetime: SUCCES<14>[ 24.993855] [IGT] kms_prop_blob: starting subtest blob-multiple
12061 12:19:53.906788 S (0.000s)[0m
12062 12:19:53.906841 <14>[ 25.001410] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12063 12:19:53.906894 <14>[ 25.009801] [IGT] kms_prop_blob: exiting, ret=0
12064 12:19:53.906977 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch<8>[ 25.019297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12065 12:19:53.907061 64)
12066 12:19:53.907114 Opened device: /dev/dri/card0
12067 12:19:53.907168 Starting subtest: blob-multiple
12068 12:19:53.907220 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12069 12:19:53.907273 <14>[ 25.039750] [IGT] kms_prop_blob: executing
12070 12:19:53.907327 IGT-Version: 1.2<14>[ 25.044576] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12071 12:19:53.907381 7.1-g621c2d3 (aa<14>[ 25.052791] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12072 12:19:53.907652 Received signal: <TESTSET> START kms_flip_event_leak
12073 12:19:53.907711 Starting test_set kms_flip_event_leak
12074 12:19:53.907793 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12076 12:19:53.907971 Received signal: <TESTSET> STOP
12077 12:19:53.908031 Closing test_set kms_flip_event_leak
12078 12:19:53.908112 Received signal: <TESTSET> START kms_prop_blob
12079 12:19:53.908172 Starting test_set kms_prop_blob
12080 12:19:53.908251 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12082 12:19:53.908430 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12084 12:19:53.908611 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12086 12:19:53.908790 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12088 12:19:53.908968 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12090 12:19:53.909157 <14>[ 25.061749] [IGT] kms_prop_blob: exiting, ret=0
12091 12:19:53.909220 rch64) (Linux: 6.1.59-cip7 aarch64)
12092 12:19:53.909277 Opened device: /dev/dri/car<8>[ 25.071053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12093 12:19:53.909335 d0
12094 12:19:53.909389 Starting subtest: invalid-get-prop-any
12095 12:19:53.909444 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12096 12:19:53.909498 <14>[ 25.091366] [IGT] kms_prop_blob: executing
12097 12:19:53.909552 IGT-Version: 1.2<14>[ 25.096160] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12098 12:19:53.909607 <14>[ 25.103958] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12099 12:19:53.909661 7.1-g621c2d3 (aa<14>[ 25.111304] [IGT] kms_prop_blob: exiting, ret=0
12100 12:19:53.909716 rch64) (Linux: 6.1.59-cip7 aarch64)
12101 12:19:53.909770 Opened device: /dev/dri/car<8>[ 25.121947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12102 12:19:53.909824 d0
12103 12:19:53.909877 Starting subtest: invalid-get-prop
12104 12:19:53.909931 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12105 12:19:53.909984 <14>[ 25.142387] [IGT] kms_prop_blob: executing
12106 12:19:53.910038 IGT-Version: 1.2<14>[ 25.147149] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12107 12:19:53.910092 7.1-g621c2d3 (aa<14>[ 25.155420] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12108 12:19:53.910147 <14>[ 25.164402] [IGT] kms_prop_blob: exiting, ret=0
12109 12:19:53.910201 rch64) (Linux: 6.1.59-cip7 aarch64)
12110 12:19:53.910255 Opened devi<8>[ 25.173489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12111 12:19:53.910308 ce: /dev/dri/card0
12112 12:19:53.910361 Starting subtest: invalid-set-prop-any
12113 12:19:53.910414 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12114 12:19:53.910468 <14>[ 25.193483] [IGT] kms_prop_blob: executing
12115 12:19:53.910521 IGT-Version: 1.2<14>[ 25.198240] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12116 12:19:53.910575 7.1-g621c2d3 (aa<14>[ 25.206048] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12117 12:19:53.910630 <14>[ 25.214801] [IGT] kms_prop_blob: exiting, ret=0
12118 12:19:53.910683 rch64) (Linux: 6.1.59-cip7 aarch64)
12119 12:19:53.910735 Opened devi<8>[ 25.223880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12120 12:19:53.910789 ce: /dev/dri/card0
12121 12:19:53.910841 Starting sub<8>[ 25.232746] <LAVA_SIGNAL_TESTSET STOP>
12122 12:19:53.910894 test: invalid-set-prop
12123 12:19:53.910947 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
12124 12:19:53.911000 <8>[ 25.253180] <LAVA_SIGNAL_TESTSET START kms_setmode>
12125 12:19:53.911054 <14>[ 25.274417] [IGT] kms_setmode: executing
12126 12:19:53.911107 IGT-Version: 1.2<14>[ 25.279223] [IGT] kms_setmode: starting subtest basic
12127 12:19:53.911160 7.1-g621c2d3 (aa<14>[ 25.285858] [IGT] kms_setmode: finished subtest basic, SKIP
12128 12:19:53.911215 rch64) (Linux: 6<14>[ 25.293253] [IGT] kms_setmode: exiting, ret=77
12129 12:19:53.911268 .1.59-cip7 aarch64)
12130 12:19:53.911322 Opened device: /dev/dri/card0
12131 12:19:53.911375 Starting sub<8>[ 25.303702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12132 12:19:53.911474 test: basic
12133 12:19:53.911527 No dynamic tests executed.
12134 12:19:53.911580 [1mSubtest basic: SKIP (0.000s)[0m
12135 12:19:53.911633 <14>[ 25.323537] [IGT] kms_setmode: executing
12136 12:19:53.911686 IGT-Version: 1.2<14>[ 25.328188] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12137 12:19:53.911740 <14>[ 25.336366] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12138 12:19:53.911794 <14>[ 25.343898] [IGT] kms_setmode: exiting, ret=77
12139 12:19:53.911847 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12140 12:19:53.911901 Opened devi<8>[ 25.353110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12141 12:19:53.911955 ce: /dev/dri/card0
12142 12:19:53.912007 Starting subtest: basic-clone-single-crtc
12143 12:19:53.912060 No dynamic tests executed.
12144 12:19:53.912113 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0<14>[ 25.374714] [IGT] kms_setmode: executing
12145 12:19:53.912165 m
12146 12:19:53.912218 IGT-Version: 1.2<14>[ 25.379447] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12147 12:19:53.912271 <14>[ 25.387922] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12148 12:19:53.912325 7.1-g621c2d3 (aa<14>[ 25.395684] [IGT] kms_setmode: exiting, ret=77
12149 12:19:53.912379 rch64) (Linux: 6.1.59-cip7 aarch64)
12150 12:19:53.912432 Opened device: /dev/dri/car<8>[ 25.406110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12151 12:19:53.912485 d0
12152 12:19:53.912538 Starting subtest: invalid-clone-single-crtc
12153 12:19:53.912590 No dynamic tests executed.
12154 12:19:53.912644 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12155 12:19:53.912696 <14>[ 25.428340] [IGT] kms_setmode: executing
12156 12:19:53.912749 IGT-Version: 1.2<14>[ 25.433026] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12157 12:19:53.912803 <14>[ 25.441648] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12158 12:19:53.912857 <14>[ 25.449609] [IGT] kms_setmode: exiting, ret=77
12159 12:19:53.912910 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12160 12:19:53.913140 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12162 12:19:53.913319 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12164 12:19:53.913498 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12166 12:19:53.913680 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12168 12:19:53.913861 Received signal: <TESTSET> STOP
12169 12:19:53.913921 Closing test_set kms_prop_blob
12170 12:19:53.914001 Received signal: <TESTSET> START kms_setmode
12171 12:19:53.914061 Starting test_set kms_setmode
12172 12:19:53.914140 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12174 12:19:53.914317 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12176 12:19:53.914497 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12178 12:19:53.914686 Opened devi<8>[ 25.458889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12179 12:19:53.914750 ce: /dev/dri/card0
12180 12:19:53.914808 Starting subtest: invalid-clone-exclusive-crtc
12181 12:19:53.914863 No dynamic tests executed.
12182 12:19:53.914918 [1mSubtest invalid-clone-exclusive-crtc: SKIP (<14>[ 25.480196] [IGT] kms_setmode: executing
12183 12:19:53.914972 0.000s)[0m
12184 12:19:53.915028 <14>[ 25.485606] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12185 12:19:53.915083 <14>[ 25.493193] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12186 12:19:53.915154 <14>[ 25.500466] [IGT] kms_setmode: exiting, ret=77
12187 12:19:53.915222 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch<8>[ 25.509588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12188 12:19:53.915275 64)
12189 12:19:53.915329 Opened device: /dev/dri/card0
12190 12:19:53.915381 Starting subtest: clone-exclusive-crtc
12191 12:19:53.915470 No dynamic tests executed.
12192 12:19:53.915524 [1mSubtest clone-exclusive-crtc: SKIP (<14>[ 25.531027] [IGT] kms_setmode: executing
12193 12:19:53.915578 0.000s)[0m
12194 12:19:53.915633 <14>[ 25.535698] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12195 12:19:53.915687 <14>[ 25.544494] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12196 12:19:53.915742 IGT-Version: 1.2<14>[ 25.553061] [IGT] kms_setmode: exiting, ret=77
12197 12:19:53.915795 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch<8>[ 25.563307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12198 12:19:53.915851 64)
12199 12:19:53.915905 Opened device: /dev/dri/car<8>[ 25.573864] <LAVA_SIGNAL_TESTSET STOP>
12200 12:19:53.915959 d0
12201 12:19:53.916011 Starting subtest: invalid-clone-single-crtc-stealing
12202 12:19:53.916064 No dynamic tests executed.
12203 12:19:53.916118 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12204 12:19:53.916171 <8>[ 25.594928] <LAVA_SIGNAL_TESTSET START kms_vblank>
12205 12:19:53.916225 <14>[ 25.612809] [IGT] kms_vblank: executing
12206 12:19:53.916277 IGT-Version: 1.2<14>[ 25.617633] [IGT] kms_vblank: exiting, ret=77
12207 12:19:53.916330 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12208 12:19:53.916385 Opened devi<8>[ 25.627905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12209 12:19:53.916438 ce: /dev/dri/card0
12210 12:19:53.916491 No KMS driver or no outputs, pipes: 8, outputs: 0
12211 12:19:53.916545 [1mSubtest invalid: SKIP (0.000s)[0m
12212 12:19:53.916598 <14>[ 25.647389] [IGT] kms_vblank: executing
12213 12:19:53.916651 IGT-Version: 1.2<14>[ 25.652117] [IGT] kms_vblank: exiting, ret=77
12214 12:19:53.916704 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12215 12:19:53.916759 Opened devi<8>[ 25.662543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12216 12:19:53.916813 ce: /dev/dri/card0
12217 12:19:53.916865 No KMS driver or no outputs, pipes: 8, outputs: 0
12218 12:19:53.916918 [1mSubtest crtc-id: SKIP (0.000s)[0m
12219 12:19:53.916971 <14>[ 25.682522] [IGT] kms_vblank: executing
12220 12:19:53.917023 IGT-Version: 1.2<14>[ 25.687268] [IGT] kms_vblank: exiting, ret=77
12221 12:19:53.917076 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12222 12:19:53.917131 Opened devi<8>[ 25.697743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12223 12:19:53.917184 ce: /dev/dri/card0
12224 12:19:53.917237 No KMS driver or no outputs, pipes: 8, outputs: 0
12225 12:19:53.917290 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12226 12:19:53.917343 <14>[ 25.718524] [IGT] kms_vblank: executing
12227 12:19:53.917396 IGT-Version: 1.2<14>[ 25.723278] [IGT] kms_vblank: exiting, ret=77
12228 12:19:53.917448 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12229 12:19:53.917503 Opened devi<8>[ 25.733547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12230 12:19:53.917556 ce: /dev/dri/card0
12231 12:19:53.917608 No KMS driver or no outputs, pipes: 8, outputs: 0
12232 12:19:53.917661 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12233 12:19:53.917713 <14>[ 25.754274] [IGT] kms_vblank: executing
12234 12:19:53.917766 IGT-Version: 1.2<14>[ 25.759022] [IGT] kms_vblank: exiting, ret=77
12235 12:19:53.917819 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12236 12:19:53.917873 Opened devi<8>[ 25.769432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12237 12:19:53.917927 ce: /dev/dri/card0
12238 12:19:53.917980 No KMS driver or no outputs, pipes: 8, outputs: 0
12239 12:19:53.918033 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12240 12:19:53.918086 <14>[ 25.790271] [IGT] kms_vblank: executing
12241 12:19:53.918139 IGT-Version: 1.2<14>[ 25.795023] [IGT] kms_vblank: exiting, ret=77
12242 12:19:53.918192 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12243 12:19:53.918246 Opened devi<8>[ 25.805291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12244 12:19:53.918300 ce: /dev/dri/card0
12245 12:19:53.918352 No KMS driver or no outputs, pipes: 8, outputs: 0
12246 12:19:53.918406 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12247 12:19:53.918458 <14>[ 25.825737] [IGT] kms_vblank: executing
12248 12:19:53.918512 IGT-Version: 1.2<14>[ 25.830697] [IGT] kms_vblank: exiting, ret=77
12249 12:19:53.918565 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12250 12:19:53.918811 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12252 12:19:53.919146 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12254 12:19:53.919502 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12256 12:19:53.919812 Received signal: <TESTSET> STOP
12257 12:19:53.919905 Closing test_set kms_setmode
12258 12:19:53.920037 Received signal: <TESTSET> START kms_vblank
12259 12:19:53.920129 Starting test_set kms_vblank
12260 12:19:53.920255 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12262 12:19:53.920557 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12264 12:19:53.920865 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12266 12:19:53.921165 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12268 12:19:53.921464 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12270 12:19:53.921767 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12272 12:19:53.922081 Opened devi<8>[ 25.841037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12273 12:19:53.922176 ce: /dev/dri/card0
12274 12:19:53.922272 No KMS driver or no outputs, pipes: 8, outputs: 0
12275 12:19:53.922368 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12276 12:19:53.922455 <14>[ 25.862044] [IGT] kms_vblank: executing
12277 12:19:53.922552 IGT-Version: 1.2<14>[ 25.866760] [IGT] kms_vblank: exiting, ret=77
12278 12:19:53.922641 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12279 12:19:53.922730 Opened devi<8>[ 25.877367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12280 12:19:53.922827 ce: /dev/dri/card0
12281 12:19:53.922914 No KMS driver or no outputs, pipes: 8, outputs: 0
12282 12:19:53.922999 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12283 12:19:53.923135 <14>[ 25.897963] [IGT] kms_vblank: executing
12284 12:19:53.923248 IGT-Version: 1.2<14>[ 25.902700] [IGT] kms_vblank: exiting, ret=77
12285 12:19:53.923345 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12286 12:19:53.923473 Opened devi<8>[ 25.913302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12287 12:19:53.923568 ce: /dev/dri/card0
12288 12:19:53.923654 No KMS driver or no outputs, pipes: 8, outputs: 0
12289 12:19:53.923738 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12290 12:19:53.923834 <14>[ 25.933933] [IGT] kms_vblank: executing
12291 12:19:53.923921 IGT-Version: 1.2<14>[ 25.938661] [IGT] kms_vblank: exiting, ret=77
12292 12:19:53.924005 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12293 12:19:53.924104 Opened devi<8>[ 25.949210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12294 12:19:53.924189 ce: /dev/dri/card0
12295 12:19:53.924273 No KMS driver or no outputs, pipes: 8, outputs: 0
12296 12:19:53.924371 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12297 12:19:53.924456 <14>[ 25.970180] [IGT] kms_vblank: executing
12298 12:19:53.924545 IGT-Version: 1.2<14>[ 25.974902] [IGT] kms_vblank: exiting, ret=77
12299 12:19:53.924636 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12300 12:19:53.924723 Opened devi<8>[ 25.985460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12301 12:19:53.924816 ce: /dev/dri/card0
12302 12:19:53.924905 No KMS driver or no outputs, pipes: 8, outputs: 0
12303 12:19:53.924989 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12304 12:19:53.925084 <14>[ 26.010673] [IGT] kms_vblank: executing
12305 12:19:53.925170 IGT-Version: 1.2<14>[ 26.015420] [IGT] kms_vblank: exiting, ret=77
12306 12:19:53.925253 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12307 12:19:53.925351 Opened devi<8>[ 26.025615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12308 12:19:53.925438 ce: /dev/dri/card0
12309 12:19:53.925521 No KMS driver or no outputs, pipes: 8, outputs: 0
12310 12:19:53.925616 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12311 12:19:53.925700 <14>[ 26.046439] [IGT] kms_vblank: executing
12312 12:19:53.925783 IGT-Version: 1.2<14>[ 26.051228] [IGT] kms_vblank: exiting, ret=77
12313 12:19:53.925878 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12314 12:19:53.925967 Opened devi<8>[ 26.061654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12315 12:19:53.926060 ce: /dev/dri/card0
12316 12:19:53.926150 No KMS driver or no outputs, pipes: 8, outputs: 0
12317 12:19:53.926234 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12318 12:19:53.926326 <14>[ 26.082264] [IGT] kms_vblank: executing
12319 12:19:53.926412 IGT-Version: 1.2<14>[ 26.087010] [IGT] kms_vblank: exiting, ret=77
12320 12:19:53.926470 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12321 12:19:53.926526 Opened devi<8>[ 26.097452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12322 12:19:53.926610 ce: /dev/dri/card0
12323 12:19:53.926695 No KMS driver or no outputs, pipes: 8, outputs: 0
12324 12:19:53.926778 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12325 12:19:53.926874 <14>[ 26.118257] [IGT] kms_vblank: executing
12326 12:19:53.926961 IGT-Version: 1.2<14>[ 26.122997] [IGT] kms_vblank: exiting, ret=77
12327 12:19:53.927044 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12328 12:19:53.927143 Opened devi<8>[ 26.133557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12329 12:19:53.927227 ce: /dev/dri/card0
12330 12:19:53.927310 No KMS driver or no outputs, pipes: 8, outputs: 0
12331 12:19:53.927442 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12332 12:19:53.927527 <14>[ 26.154133] [IGT] kms_vblank: executing
12333 12:19:53.927624 IGT-Version: 1.2<14>[ 26.158896] [IGT] kms_vblank: exiting, ret=77
12334 12:19:53.927709 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12335 12:19:53.927796 Opened devi<8>[ 26.169194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12336 12:19:53.927891 ce: /dev/dri/card0
12337 12:19:53.927977 No KMS driver or no outputs, pipes: 8, outputs: 0
12338 12:19:53.928061 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12339 12:19:53.928157 <14>[ 26.189930] [IGT] kms_vblank: executing
12340 12:19:53.928241 IGT-Version: 1.2<14>[ 26.194647] [IGT] kms_vblank: exiting, ret=77
12341 12:19:53.928325 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12342 12:19:53.928424 Opened devi<8>[ 26.205210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12343 12:19:53.928509 ce: /dev/dri/card0
12344 12:19:53.928601 No KMS driver or no outputs, pipes: 8, outputs: 0
12345 12:19:53.928869 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12347 12:19:53.929177 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12349 12:19:53.929484 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12351 12:19:53.929789 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12353 12:19:53.930100 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12355 12:19:53.930403 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12357 12:19:53.930706 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12359 12:19:53.931005 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12361 12:19:53.931238 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12363 12:19:53.931461 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12365 12:19:53.931663 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12367 12:19:53.931864 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12368 12:19:53.931947 <14>[ 26.225929] [IGT] kms_vblank: executing
12369 12:19:53.932013 IGT-Version: 1.2<14>[ 26.230635] [IGT] kms_vblank: exiting, ret=77
12370 12:19:53.932073 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12371 12:19:53.932144 Opened devi<8>[ 26.241286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12372 12:19:53.932210 ce: /dev/dri/card0
12373 12:19:53.932267 No KMS driver or no outputs, pipes: 8, outputs: 0
12374 12:19:53.932323 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12375 12:19:53.932383 <14>[ 26.262058] [IGT] kms_vblank: executing
12376 12:19:53.932455 IGT-Version: 1.2<14>[ 26.266801] [IGT] kms_vblank: exiting, ret=77
12377 12:19:53.932529 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12378 12:19:53.932617 Opened devi<8>[ 26.277354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12379 12:19:53.932714 ce: /dev/dri/card0
12380 12:19:53.932799 No KMS driver or no outputs, pipes: 8, outputs: 0
12381 12:19:53.932883 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12382 12:19:53.932980 <14>[ 26.298516] [IGT] kms_vblank: executing
12383 12:19:53.933067 IGT-Version: 1.2<14>[ 26.303248] [IGT] kms_vblank: exiting, ret=77
12384 12:19:53.933158 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12385 12:19:53.933252 Opened devi<8>[ 26.313661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12386 12:19:53.933337 ce: /dev/dri/card0
12387 12:19:53.933429 No KMS driver or no outputs, pipes: 8, outputs: 0
12388 12:19:53.933519 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12389 12:19:53.933603 <14>[ 26.334708] [IGT] kms_vblank: executing
12390 12:19:53.933699 IGT-Version: 1.2<14>[ 26.339521] [IGT] kms_vblank: exiting, ret=77
12391 12:19:53.933784 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12392 12:19:53.933871 Opened devi<8>[ 26.349707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12393 12:19:53.933967 ce: /dev/dri/card0
12394 12:19:53.934052 No KMS driver or no outputs, pipes: 8, outputs: 0
12395 12:19:53.934137 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12396 12:19:53.934233 <14>[ 26.371274] [IGT] kms_vblank: executing
12397 12:19:53.934318 IGT-Version: 1.2<14>[ 26.376305] [IGT] kms_vblank: exiting, ret=77
12398 12:19:53.934403 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12399 12:19:53.934501 Opened devi<8>[ 26.386599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12400 12:19:53.934587 ce: /dev/dri/card0
12401 12:19:53.934679 No KMS driver or no outputs, pipes: 8, outputs: 0
12402 12:19:53.934768 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12403 12:19:53.934852 <14>[ 26.408033] [IGT] kms_vblank: executing
12404 12:19:53.934945 IGT-Version: 1.2<14>[ 26.412901] [IGT] kms_vblank: exiting, ret=77
12405 12:19:53.935034 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12406 12:19:53.935121 Opened devi<8>[ 26.423137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12407 12:19:53.935217 ce: /dev/dri/card0
12408 12:19:53.935301 No KMS driver or no outputs, pipes: 8, outputs: 0
12409 12:19:53.935414 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12410 12:19:53.935524 <14>[ 26.444952] [IGT] kms_vblank: executing
12411 12:19:53.935582 IGT-Version: 1.2<14>[ 26.449965] [IGT] kms_vblank: exiting, ret=77
12412 12:19:53.935636 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12413 12:19:53.935717 Opened devi<8>[ 26.460312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12414 12:19:53.935803 ce: /dev/dri/card0
12415 12:19:53.935886 No KMS driver or no outputs, pipes: 8, outputs: 0
12416 12:19:53.935984 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12417 12:19:53.936071 <14>[ 26.481917] [IGT] kms_vblank: executing
12418 12:19:53.936155 IGT-Version: 1.2<14>[ 26.486765] [IGT] kms_vblank: exiting, ret=77
12419 12:19:53.936251 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12420 12:19:53.936340 Opened devi<8>[ 26.497255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12421 12:19:53.936423 ce: /dev/dri/card0
12422 12:19:53.936522 No KMS driver or no outputs, pipes: 8, outputs: 0
12423 12:19:53.936611 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12424 12:19:53.936701 <14>[ 26.522764] [IGT] kms_vblank: executing
12425 12:19:53.936793 IGT-Version: 1.2<14>[ 26.527499] [IGT] kms_vblank: exiting, ret=77
12426 12:19:53.936876 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12427 12:19:53.936973 Opened devi<8>[ 26.537831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12428 12:19:53.937062 ce: /dev/dri/card0
12429 12:19:53.937145 No KMS driver or no outputs, pipes: 8, outputs: 0
12430 12:19:53.937241 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12431 12:19:53.937327 <14>[ 26.559394] [IGT] kms_vblank: executing
12432 12:19:53.937411 IGT-Version: 1.2<14>[ 26.564857] [IGT] kms_vblank: exiting, ret=77
12433 12:19:53.937507 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12434 12:19:53.937598 Opened devi<8>[ 26.575146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12435 12:19:53.937681 ce: /dev/dri/card0
12436 12:19:53.937953 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12438 12:19:53.938265 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12440 12:19:53.938566 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12442 12:19:53.938864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12444 12:19:53.939162 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12446 12:19:53.939506 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12448 12:19:53.939807 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12450 12:19:53.940090 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12452 12:19:53.940386 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12454 12:19:53.940682 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12456 12:19:53.940978 No KMS driver or no outputs, pipes: 8, outputs: 0
12457 12:19:53.941067 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12458 12:19:53.941148 <14>[ 26.596997] [IGT] kms_vblank: executing
12459 12:19:53.941236 IGT-Version: 1.2<14>[ 26.601780] [IGT] kms_vblank: exiting, ret=77
12460 12:19:53.941319 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12461 12:19:53.941378 Opened devi<8>[ 26.612064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12462 12:19:53.941436 ce: /dev/dri/card0
12463 12:19:53.941492 No KMS driver or no outputs, pipes: 8, outputs: 0
12464 12:19:53.941591 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12465 12:19:53.941678 <14>[ 26.632944] [IGT] kms_vblank: executing
12466 12:19:53.941769 IGT-Version: 1.2<14>[ 26.637665] [IGT] kms_vblank: exiting, ret=77
12467 12:19:53.941861 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12468 12:19:53.941949 Opened devi<8>[ 26.648019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12469 12:19:53.942042 ce: /dev/dri/card0
12470 12:19:53.942131 No KMS driver or no outputs, pipes: 8, outputs: 0
12471 12:19:53.942216 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12472 12:19:53.942311 <14>[ 26.668275] [IGT] kms_vblank: executing
12473 12:19:53.942398 IGT-Version: 1.2<14>[ 26.673237] [IGT] kms_vblank: exiting, ret=77
12474 12:19:53.942481 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12475 12:19:53.942580 Opened devi<8>[ 26.683575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12476 12:19:53.942667 ce: /dev/dri/card0
12477 12:19:53.942750 No KMS driver or no outputs, pipes: 8, outputs: 0
12478 12:19:53.942847 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12479 12:19:53.942944 <14>[ 26.704442] [IGT] kms_vblank: executing
12480 12:19:53.943038 IGT-Version: 1.2<14>[ 26.709272] [IGT] kms_vblank: exiting, ret=77
12481 12:19:53.943128 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12482 12:19:53.943216 Opened devi<8>[ 26.719625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12483 12:19:53.943309 ce: /dev/dri/card0
12484 12:19:53.943433 No KMS driver or no outputs, pipes: 8, outputs: 0
12485 12:19:53.943492 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12486 12:19:53.943567 <14>[ 26.740419] [IGT] kms_vblank: executing
12487 12:19:53.943631 IGT-Version: 1.2<14>[ 26.745249] [IGT] kms_vblank: exiting, ret=77
12488 12:19:53.943686 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12489 12:19:53.943742 Opened devi<8>[ 26.755482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12490 12:19:53.943812 ce: /dev/dri/card0
12491 12:19:53.943873 No KMS driver or no outputs, pipes: 8, outputs: 0
12492 12:19:53.943928 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12493 12:19:53.943981 <14>[ 26.776453] [IGT] kms_vblank: executing
12494 12:19:53.944040 IGT-Version: 1.2<14>[ 26.781232] [IGT] kms_vblank: exiting, ret=77
12495 12:19:53.944111 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12496 12:19:53.944186 Opened devi<8>[ 26.791514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12497 12:19:53.944270 ce: /dev/dri/card0
12498 12:19:53.944351 No KMS driver or no outputs, pipes: 8, outputs: 0
12499 12:19:53.944409 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12500 12:19:53.944462 <14>[ 26.812167] [IGT] kms_vblank: executing
12501 12:19:53.944516 IGT-Version: 1.2<14>[ 26.817068] [IGT] kms_vblank: exiting, ret=77
12502 12:19:53.944592 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12503 12:19:53.944653 Opened devi<8>[ 26.827466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12504 12:19:53.944709 ce: /dev/dri/card0
12505 12:19:53.944762 No KMS driver or no outputs, pipes: 8, outputs: 0
12506 12:19:53.944833 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12507 12:19:53.944894 <14>[ 26.847843] [IGT] kms_vblank: executing
12508 12:19:53.944985 IGT-Version: 1.2<14>[ 26.852654] [IGT] kms_vblank: exiting, ret=77
12509 12:19:53.945080 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12510 12:19:53.945172 Opened devi<8>[ 26.862974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12511 12:19:53.945259 ce: /dev/dri/card0
12512 12:19:53.945343 No KMS driver or no outputs, pipes: 8, outputs: 0
12513 12:19:53.945408 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12514 12:19:53.945472 <14>[ 26.884212] [IGT] kms_vblank: executing
12515 12:19:53.945556 IGT-Version: 1.2<14>[ 26.889100] [IGT] kms_vblank: exiting, ret=77
12516 12:19:53.945639 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12517 12:19:53.945707 Opened devi<8>[ 26.899432] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12518 12:19:53.945767 ce: /dev/dri/card0
12519 12:19:53.945825 No KMS driver or no outputs, pipes: 8, outputs: 0
12520 12:19:53.945879 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12521 12:19:53.945933 <14>[ 26.921189] [IGT] kms_vblank: executing
12522 12:19:53.946008 IGT-Version: 1.2<14>[ 26.925909] [IGT] kms_vblank: exiting, ret=77
12523 12:19:53.946095 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12524 12:19:53.946181 Opened devi<8>[ 26.936397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12525 12:19:53.946264 ce: /dev/dri/card0
12526 12:19:53.946321 No KMS driver or no outputs, pipes: 8, outputs: 0
12527 12:19:53.946405 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12528 12:19:53.946668 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12530 12:19:53.946963 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12532 12:19:53.947252 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12534 12:19:53.947532 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12536 12:19:53.947779 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12538 12:19:53.947968 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12540 12:19:53.948168 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12542 12:19:53.948402 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12544 12:19:53.948587 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12546 12:19:53.948785 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12548 12:19:53.949022 <14>[ 26.956369] [IGT] kms_vblank: executing
12549 12:19:53.949117 IGT-Version: 1.2<14>[ 26.961155] [IGT] kms_vblank: exiting, ret=77
12550 12:19:53.949206 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12551 12:19:53.949300 Opened devi<8>[ 26.971585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12552 12:19:53.949388 ce: /dev/dri/card0
12553 12:19:53.949472 No KMS driver or no outputs, pipes: 8, outputs: 0
12554 12:19:53.949561 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12555 12:19:53.949648 <14>[ 26.992295] [IGT] kms_vblank: executing
12556 12:19:53.949733 IGT-Version: 1.2<14>[ 26.997195] [IGT] kms_vblank: exiting, ret=77
12557 12:19:53.949819 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12558 12:19:53.949909 Opened devi<8>[ 27.007427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12559 12:19:53.949996 ce: /dev/dri/card0
12560 12:19:53.950079 No KMS driver or no outputs, pipes: 8, outputs: 0
12561 12:19:53.950166 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12562 12:19:53.950252 <14>[ 27.028285] [IGT] kms_vblank: executing
12563 12:19:53.950336 IGT-Version: 1.2<14>[ 27.033120] [IGT] kms_vblank: exiting, ret=77
12564 12:19:53.950422 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12565 12:19:53.950512 Opened devi<8>[ 27.043356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12566 12:19:53.950597 ce: /dev/dri/card0
12567 12:19:53.950681 No KMS driver or no outputs, pipes: 8, outputs: 0
12568 12:19:53.950768 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12569 12:19:53.950853 <14>[ 27.063829] [IGT] kms_vblank: executing
12570 12:19:53.950938 IGT-Version: 1.2<14>[ 27.068598] [IGT] kms_vblank: exiting, ret=77
12571 12:19:53.951023 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12572 12:19:53.951112 Opened devi<8>[ 27.078923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12573 12:19:53.951198 ce: /dev/dri/card0
12574 12:19:53.951281 No KMS driver or no outputs, pipes: 8, outputs: 0
12575 12:19:53.951368 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12576 12:19:53.951466 <14>[ 27.099570] [IGT] kms_vblank: executing
12577 12:19:53.951550 IGT-Version: 1.2<14>[ 27.104357] [IGT] kms_vblank: exiting, ret=77
12578 12:19:53.951635 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12579 12:19:53.951724 Opened devi<8>[ 27.114699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12580 12:19:53.951810 ce: /dev/dri/card0
12581 12:19:53.951892 No KMS driver or no outputs, pipes: 8, outputs: 0
12582 12:19:53.951979 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12583 12:19:53.952064 <14>[ 27.135300] [IGT] kms_vblank: executing
12584 12:19:53.952148 IGT-Version: 1.2<14>[ 27.140045] [IGT] kms_vblank: exiting, ret=77
12585 12:19:53.952233 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12586 12:19:53.952322 Opened devi<8>[ 27.150367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12587 12:19:53.952407 ce: /dev/dri/card0
12588 12:19:53.952489 No KMS driver or no outputs, pipes: 8, outputs: 0
12589 12:19:53.952576 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12590 12:19:53.952662 <14>[ 27.171193] [IGT] kms_vblank: executing
12591 12:19:53.952745 IGT-Version: 1.2<14>[ 27.175928] [IGT] kms_vblank: exiting, ret=77
12592 12:19:53.952830 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12593 12:19:53.952919 Opened devi<8>[ 27.186096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12594 12:19:53.953004 ce: /dev/dri/card0
12595 12:19:53.953086 No KMS driver or no outputs, pipes: 8, outputs: 0
12596 12:19:53.953173 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12597 12:19:53.953259 <14>[ 27.208268] [IGT] kms_vblank: executing
12598 12:19:53.953342 IGT-Version: 1.2<14>[ 27.213172] [IGT] kms_vblank: exiting, ret=77
12599 12:19:53.953427 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12600 12:19:53.953517 Opened device: /dev/dri/car<8>[ 27.224358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12601 12:19:53.953602 d0
12602 12:19:53.953684 No KMS driver or no outputs, pipes: 8, outputs: 0
12603 12:19:53.953771 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12604 12:19:53.953856 <14>[ 27.246573] [IGT] kms_vblank: executing
12605 12:19:53.953940 IGT-Version: 1.2<14>[ 27.251301] [IGT] kms_vblank: exiting, ret=77
12606 12:19:53.954026 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12607 12:19:53.954115 Opened devi<8>[ 27.261591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12608 12:19:53.954199 ce: /dev/dri/card0
12609 12:19:53.954283 No KMS driver or no outputs, pipes: 8, outputs: 0
12610 12:19:53.954369 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12611 12:19:53.954453 <14>[ 27.283548] [IGT] kms_vblank: executing
12612 12:19:53.954536 IGT-Version: 1.2<14>[ 27.288289] [IGT] kms_vblank: exiting, ret=77
12613 12:19:53.954622 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12614 12:19:53.954711 Opened devi<8>[ 27.298562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12615 12:19:53.954796 ce: /dev/dri/card0
12616 12:19:53.954881 No KMS driver or no outputs, pipes: 8, outputs: 0
12617 12:19:53.954968 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12618 12:19:53.955051 <14>[ 27.320039] [IGT] kms_vblank: executing
12619 12:19:53.955314 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12621 12:19:53.955649 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12623 12:19:53.955869 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12625 12:19:53.956139 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12627 12:19:53.956328 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12629 12:19:53.956523 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12631 12:19:53.956806 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12633 12:19:53.957095 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12635 12:19:53.957385 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12637 12:19:53.957671 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12639 12:19:53.957970 IGT-Version: 1.2<14>[ 27.324894] [IGT] kms_vblank: exiting, ret=77
12640 12:19:53.958063 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12641 12:19:53.958155 Opened devi<8>[ 27.335001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12642 12:19:53.958245 ce: /dev/dri/card0
12643 12:19:53.958334 No KMS driver or no outputs, pipes: 8, outputs: 0
12644 12:19:53.958420 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12645 12:19:53.958509 <14>[ 27.357017] [IGT] kms_vblank: executing
12646 12:19:53.958596 IGT-Version: 1.2<14>[ 27.361996] [IGT] kms_vblank: exiting, ret=77
12647 12:19:53.958680 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12648 12:19:53.958770 Opened devi<8>[ 27.372404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12649 12:19:53.958856 ce: /dev/dri/card0
12650 12:19:53.958945 No KMS driver or no outputs, pipes: 8, outputs: 0
12651 12:19:53.959030 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12652 12:19:53.959117 <14>[ 27.394110] [IGT] kms_vblank: executing
12653 12:19:53.959204 IGT-Version: 1.2<14>[ 27.398821] [IGT] kms_vblank: exiting, ret=77
12654 12:19:53.959287 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12655 12:19:53.959376 Opened devi<8>[ 27.409463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12656 12:19:53.959480 ce: /dev/dri/card0
12657 12:19:53.959540 No KMS driver or no outputs, pipes: 8, outputs: 0
12658 12:19:53.959595 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12659 12:19:53.959650 <14>[ 27.435027] [IGT] kms_vblank: executing
12660 12:19:53.959711 IGT-Version: 1.2<14>[ 27.439755] [IGT] kms_vblank: exiting, ret=77
12661 12:19:53.959769 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12662 12:19:53.959825 Opened devi<8>[ 27.449885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12663 12:19:53.959880 ce: /dev/dri/card0
12664 12:19:53.959934 No KMS driver or no outputs, pipes: 8, outputs: 0
12665 12:19:53.959995 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12666 12:19:53.960053 <14>[ 27.471882] [IGT] kms_vblank: executing
12667 12:19:53.960114 IGT-Version: 1.2<14>[ 27.477071] [IGT] kms_vblank: exiting, ret=77
12668 12:19:53.960198 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12669 12:19:53.960289 Opened devi<8>[ 27.487288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12670 12:19:53.960375 ce: /dev/dri/card0
12671 12:19:53.960457 No KMS driver or no outputs, pipes: 8, outputs: 0
12672 12:19:53.960543 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12673 12:19:53.960601 <14>[ 27.509107] [IGT] kms_vblank: executing
12674 12:19:53.960659 IGT-Version: 1.2<14>[ 27.513961] [IGT] kms_vblank: exiting, ret=77
12675 12:19:53.960737 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12676 12:19:53.960823 Opened devi<8>[ 27.524320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12677 12:19:53.960914 ce: /dev/dri/card0
12678 12:19:53.961049 No KMS driver or no outputs, pipes: 8, outputs: 0
12679 12:19:53.961149 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12680 12:19:53.961236 <14>[ 27.545266] [IGT] kms_vblank: executing
12681 12:19:53.961320 IGT-Version: 1.2<14>[ 27.550052] [IGT] kms_vblank: exiting, ret=77
12682 12:19:53.961416 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12683 12:19:53.961504 Opened devi<8>[ 27.560374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12684 12:19:53.961587 ce: /dev/dri/card0
12685 12:19:53.961683 No KMS driver or no outputs, pipes: 8, outputs: 0
12686 12:19:53.961769 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12687 12:19:53.961860 <14>[ 27.580857] [IGT] kms_vblank: executing
12688 12:19:53.961949 IGT-Version: 1.2<14>[ 27.585575] [IGT] kms_vblank: exiting, ret=77
12689 12:19:53.962032 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12690 12:19:53.962129 Opened devi<8>[ 27.595815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12691 12:19:53.962217 ce: /dev/dri/card0
12692 12:19:53.962300 No KMS driver or no outputs, pipes: 8, outputs: 0
12693 12:19:53.962395 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12694 12:19:53.962480 <14>[ 27.617083] [IGT] kms_vblank: executing
12695 12:19:53.962564 IGT-Version: 1.2<14>[ 27.621793] [IGT] kms_vblank: exiting, ret=77
12696 12:19:53.962659 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12697 12:19:53.962749 Opened devi<8>[ 27.632091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12698 12:19:53.962832 ce: /dev/dri/card0
12699 12:19:53.962927 No KMS driver or no outputs, pipes: 8, outputs: 0
12700 12:19:53.963015 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12701 12:19:53.963122 <14>[ 27.652774] [IGT] kms_vblank: executing
12702 12:19:53.963215 IGT-Version: 1.2<14>[ 27.657521] [IGT] kms_vblank: exiting, ret=77
12703 12:19:53.963299 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12704 12:19:53.963422 Opened devi<8>[ 27.667690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12705 12:19:53.963523 ce: /dev/dri/card0
12706 12:19:53.963607 No KMS driver or no outputs, pipes: 8, outputs: 0
12707 12:19:53.963703 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12708 12:19:53.963789 <14>[ 27.688991] [IGT] kms_vblank: executing
12709 12:19:53.964061 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12711 12:19:53.964372 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12713 12:19:53.964673 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12715 12:19:53.964975 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12717 12:19:53.965271 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12719 12:19:55.120775 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12721 12:19:55.121080 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12723 12:19:55.121374 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12725 12:19:55.121663 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12727 12:19:55.121954 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12729 12:19:55.122267 IGT-Version: 1.2<14>[ 27.693729] [IGT] kms_vblank: exiting, ret=77
12730 12:19:55.122397 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12731 12:19:55.122463 Opened devi<8>[ 27.703999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12732 12:19:55.122525 ce: /dev/dri/card0
12733 12:19:55.122583 No KMS driver or no outputs, pipes: 8, outputs: 0
12734 12:19:55.122648 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12735 12:19:55.122708 <14>[ 27.724349] [IGT] kms_vblank: executing
12736 12:19:55.122764 IGT-Version: 1.2<14>[ 27.729168] [IGT] kms_vblank: exiting, ret=77
12737 12:19:55.122820 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12738 12:19:55.122877 Opened devi<8>[ 27.739418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12739 12:19:55.122953 ce: /dev/dri/card0
12740 12:19:55.123040 No KMS driver or no outputs, pipes: 8, outputs: 0
12741 12:19:55.123124 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12742 12:19:55.123210 <14>[ 27.760399] [IGT] kms_vblank: executing
12743 12:19:55.123297 IGT-Version: 1.2<14>[ 27.765194] [IGT] kms_vblank: exiting, ret=77
12744 12:19:55.123381 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12745 12:19:55.123482 Opened devi<8>[ 27.775455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12746 12:19:55.123544 ce: /dev/dri/card0
12747 12:19:55.123615 No KMS driver or no outputs, pipes: 8, outputs: 0
12748 12:19:55.123700 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12749 12:19:55.123784 <14>[ 27.796794] [IGT] kms_vblank: executing
12750 12:19:55.123872 IGT-Version: 1.2<14>[ 27.801543] [IGT] kms_vblank: exiting, ret=77
12751 12:19:55.123956 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12752 12:19:55.124043 Opened devi<8>[ 27.811845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12753 12:19:55.124130 ce: /dev/dri/card0
12754 12:19:55.124215 No KMS driver or no outputs, pipes: 8, outputs: 0
12755 12:19:55.124299 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12756 12:19:55.124385 <14>[ 27.844550] [IGT] kms_vblank: executing
12757 12:19:55.124471 IGT-Version: 1.2<14>[ 27.849739] [IGT] kms_vblank: exiting, ret=77
12758 12:19:55.124556 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12759 12:19:55.124643 Opened device: /dev/dri/car<8>[ 27.861045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12760 12:19:55.124730 d0
12761 12:19:55.124815 No KMS driver or no outputs, pipes: 8, outputs: 0
12762 12:19:55.124900 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12763 12:19:55.124985 <14>[ 27.882170] [IGT] kms_vblank: executing
12764 12:19:55.125072 IGT-Version: 1.2<14>[ 27.886891] [IGT] kms_vblank: exiting, ret=77
12765 12:19:55.125156 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12766 12:19:55.125242 Opened devi<8>[ 27.897404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12767 12:19:55.125329 ce: /dev/dri/card0
12768 12:19:55.125414 No KMS driver or no outputs, pipes: 8, outputs: 0
12769 12:19:55.125498 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12770 12:19:55.125584 <14>[ 27.918444] [IGT] kms_vblank: executing
12771 12:19:55.125671 IGT-Version: 1.2<14>[ 27.923162] [IGT] kms_vblank: exiting, ret=77
12772 12:19:55.125754 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12773 12:19:55.125841 Opened devi<8>[ 27.933633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12774 12:19:55.125928 ce: /dev/dri/card0
12775 12:19:55.126012 No KMS driver or no outputs, pipes: 8, outputs: 0
12776 12:19:55.126095 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12777 12:19:55.126182 <14>[ 27.953932] [IGT] kms_vblank: executing
12778 12:19:55.126268 IGT-Version: 1.2<14>[ 27.958650] [IGT] kms_vblank: exiting, ret=77
12779 12:19:55.126351 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12780 12:19:55.126437 Opened devi<8>[ 27.969342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12781 12:19:55.126495 ce: /dev/dri/card0
12782 12:19:55.126554 No KMS driver or no outputs, pipes: 8, outputs: 0
12783 12:19:55.126609 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12784 12:19:55.126663 <14>[ 27.989768] [IGT] kms_vblank: executing
12785 12:19:55.126718 IGT-Version: 1.2<14>[ 27.994575] [IGT] kms_vblank: exiting, ret=77
12786 12:19:55.126803 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12787 12:19:55.126902 Opened devi<8>[ 28.005119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12788 12:19:55.126987 ce: /dev/dri/card0
12789 12:19:55.127073 No KMS driver or no outputs, pipes: 8, outputs: 0
12790 12:19:55.127160 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12791 12:19:55.127243 <14>[ 28.025710] [IGT] kms_vblank: executing
12792 12:19:55.127329 IGT-Version: 1.2<14>[ 28.030436] [IGT] kms_vblank: exiting, ret=77
12793 12:19:55.127456 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12794 12:19:55.127544 Opened devi<8>[ 28.041054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12795 12:19:55.127630 ce: /dev/dri/card0
12796 12:19:55.127717 No KMS driver or no outputs, pipes: 8, outputs: 0
12797 12:19:55.127801 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12798 12:19:55.127884 <14>[ 28.061442] [IGT] kms_vblank: executing
12799 12:19:55.127971 IGT-Version: 1.2<14>[ 28.066177] [IGT] kms_vblank: exiting, ret=77
12800 12:19:55.128058 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12801 12:19:55.128324 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12803 12:19:55.128615 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12805 12:19:55.128907 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12807 12:19:55.129197 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12809 12:19:55.129459 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12811 12:19:55.129648 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12813 12:19:55.129933 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12815 12:19:55.130220 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12817 12:19:55.130448 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12819 12:19:55.130723 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12821 12:19:55.131049 Opened devi<8>[ 28.076411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12822 12:19:55.131157 ce: /dev/dri/card0
12823 12:19:55.131255 No KMS driver or no outputs, pipes: 8, outputs: 0
12824 12:19:55.131351 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12825 12:19:55.131457 <14>[ 28.097255] [IGT] kms_vblank: executing
12826 12:19:55.131563 IGT-Version: 1.2<14>[ 28.101967] [IGT] kms_vblank: exiting, ret=77
12827 12:19:55.131656 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12828 12:19:55.131737 Opened devi<8>[ 28.112241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12829 12:19:55.131805 ce: /dev/dri/card0
12830 12:19:55.131866 No KMS driver or no outputs, pipes: 8, outputs: 0
12831 12:19:55.131926 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12832 12:19:55.131990 <14>[ 28.133942] [IGT] kms_vblank: executing
12833 12:19:55.132084 IGT-Version: 1.2<14>[ 28.138665] [IGT] kms_vblank: exiting, ret=77
12834 12:19:55.132175 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12835 12:19:55.132269 Opened devi<8>[ 28.149046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12836 12:19:55.132365 ce: /dev/dri/card0
12837 12:19:55.132455 No KMS driver or no outputs, pipes: 8, outputs: 0
12838 12:19:55.132550 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12839 12:19:55.132636 <14>[ 28.170296] [IGT] kms_vblank: executing
12840 12:19:55.132727 IGT-Version: 1.2<14>[ 28.175075] [IGT] kms_vblank: exiting, ret=77
12841 12:19:55.132819 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12842 12:19:55.132916 Opened devi<8>[ 28.185581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12843 12:19:55.133006 ce: /dev/dri/card0
12844 12:19:55.133101 No KMS driver or no outputs, pipes: 8, outputs: 0
12845 12:19:55.133193 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12846 12:19:55.133282 <14>[ 28.207285] [IGT] kms_vblank: executing
12847 12:19:55.133377 IGT-Version: 1.2<14>[ 28.212029] [IGT] kms_vblank: exiting, ret=77
12848 12:19:55.133467 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12849 12:19:55.133560 Opened devi<8>[ 28.222387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12850 12:19:55.133653 ce: /dev/dri/card0
12851 12:19:55.133745 No KMS driver or no outputs, pipes: 8, outputs: 0
12852 12:19:55.133836 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12853 12:19:55.133930 <14>[ 28.247735] [IGT] kms_vblank: executing
12854 12:19:55.134022 IGT-Version: 1.2<14>[ 28.252526] [IGT] kms_vblank: exiting, ret=77
12855 12:19:55.134111 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12856 12:19:55.134208 Opened devi<8>[ 28.262727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12857 12:19:55.134299 ce: /dev/dri/card0
12858 12:19:55.134389 No KMS driver or no outputs, pipes: 8, outputs: 0
12859 12:19:55.134492 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12860 12:19:55.134554 <14>[ 28.285246] [IGT] kms_vblank: executing
12861 12:19:55.134613 IGT-Version: 1.2<14>[ 28.289987] [IGT] kms_vblank: exiting, ret=77
12862 12:19:55.134671 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12863 12:19:55.134778 Opened devi<8>[ 28.300361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12864 12:19:55.134869 ce: /dev/dri/card0
12865 12:19:55.134969 No KMS driver or no outputs, pipes: 8, outputs: 0
12866 12:19:55.135064 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12867 12:19:55.135154 <14>[ 28.322360] [IGT] kms_vblank: executing
12868 12:19:55.135258 IGT-Version: 1.2<14>[ 28.327126] [IGT] kms_vblank: exiting, ret=77
12869 12:19:55.135349 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12870 12:19:55.135456 Opened devi<8>[ 28.337414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12871 12:19:55.135558 ce: /dev/dri/card0
12872 12:19:55.135648 No KMS driver or no outputs, pipes: 8, outputs: 0
12873 12:19:55.135751 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12874 12:19:55.135843 <14>[ 28.358752] [IGT] kms_vblank: executing
12875 12:19:55.135942 IGT-Version: 1.2<14>[ 28.363508] [IGT] kms_vblank: exiting, ret=77
12876 12:19:55.136047 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12877 12:19:55.136142 Opened devi<8>[ 28.373706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12878 12:19:55.136241 ce: /dev/dri/card0
12879 12:19:55.136336 No KMS driver or no outputs, pipes: 8, outputs: 0
12880 12:19:55.136427 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12881 12:19:55.136529 <14>[ 28.395596] [IGT] kms_vblank: executing
12882 12:19:55.136622 IGT-Version: 1.2<14>[ 28.400801] [IGT] kms_vblank: exiting, ret=77
12883 12:19:55.136711 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12884 12:19:55.136818 Opened devi<8>[ 28.411323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12885 12:19:55.136909 ce: /dev/dri/card0
12886 12:19:55.137006 No KMS driver or no outputs, pipes: 8, outputs: 0
12887 12:19:55.137074 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12888 12:19:55.137134 <14>[ 28.436440] [IGT] kms_vblank: executing
12889 12:19:55.137193 IGT-Version: 1.2<14>[ 28.441202] [IGT] kms_vblank: exiting, ret=77
12890 12:19:55.137269 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12891 12:19:55.137547 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12893 12:19:55.137867 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12895 12:19:55.138101 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12897 12:19:55.138323 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12899 12:19:55.138596 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12901 12:19:55.138913 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12903 12:19:55.139225 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12905 12:19:55.139496 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12907 12:19:55.139697 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12909 12:19:55.139906 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12911 12:19:55.140145 Opened devi<8>[ 28.451617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12912 12:19:55.140219 ce: /dev/dri/card0
12913 12:19:55.140283 No KMS driver or no outputs, pipes: 8, outputs: 0
12914 12:19:55.140351 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12915 12:19:55.140413 <14>[ 28.472062] [IGT] kms_vblank: executing
12916 12:19:55.140506 IGT-Version: 1.2<14>[ 28.476960] [IGT] kms_vblank: exiting, ret=77
12917 12:19:55.140597 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12918 12:19:55.140695 Opened devi<8>[ 28.487209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12919 12:19:55.140789 ce: /dev/dri/card0
12920 12:19:55.140879 No KMS driver or no outputs, pipes: 8, outputs: 0
12921 12:19:55.140973 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12922 12:19:55.141066 <14>[ 28.507953] [IGT] kms_vblank: executing
12923 12:19:55.141156 IGT-Version: 1.2<14>[ 28.512850] [IGT] kms_vblank: exiting, ret=77
12924 12:19:55.141248 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12925 12:19:55.141344 Opened devi<8>[ 28.523158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12926 12:19:55.141435 ce: /dev/dri/card0
12927 12:19:55.141524 No KMS driver or no outputs, pipes: 8, outputs: 0
12928 12:19:55.141617 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12929 12:19:55.141709 <14>[ 28.543605] [IGT] kms_vblank: executing
12930 12:19:55.141798 IGT-Version: 1.2<14>[ 28.548324] [IGT] kms_vblank: exiting, ret=77
12931 12:19:55.141891 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12932 12:19:55.141987 Opened devi<8>[ 28.558774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12933 12:19:55.142076 ce: /dev/dri/card0
12934 12:19:55.142167 No KMS driver or no outputs, pipes: 8, outputs: 0
12935 12:19:55.142260 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12936 12:19:55.142350 <14>[ 28.590671] [IGT] kms_vblank: executing
12937 12:19:55.142439 IGT-Version: 1.2<14>[ 28.595867] [IGT] kms_vblank: exiting, ret=77
12938 12:19:55.142531 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12939 12:19:55.142626 Opened device: /dev/dri/car<8>[ 28.606944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12940 12:19:55.142715 d0
12941 12:19:55.142807 No KMS driver or no outputs, pipes: 8, outputs: 0
12942 12:19:55.142899 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12943 12:19:55.142988 <14>[ 28.628526] [IGT] kms_vblank: executing
12944 12:19:55.143074 IGT-Version: 1.2<14>[ 28.633241] [IGT] kms_vblank: exiting, ret=77
12945 12:19:55.143135 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12946 12:19:55.143230 Opened devi<8>[ 28.643611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12947 12:19:55.143319 ce: /dev/dri/card0
12948 12:19:55.143421 No KMS driver or no outputs, pipes: 8, outputs: 0
12949 12:19:55.143514 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12950 12:19:55.143603 <14>[ 28.663734] [IGT] kms_vblank: executing
12951 12:19:55.143696 IGT-Version: 1.2<14>[ 28.668461] [IGT] kms_vblank: exiting, ret=77
12952 12:19:55.143788 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12953 12:19:55.143881 Opened devi<8>[ 28.678903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12954 12:19:55.143973 ce: /dev/dri/card0
12955 12:19:55.144042 No KMS driver or no outputs, pipes: 8, outputs: 0
12956 12:19:55.144104 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12957 12:19:55.144163 <14>[ 28.700356] [IGT] kms_vblank: executing
12958 12:19:55.144221 IGT-Version: 1.2<14>[ 28.705241] [IGT] kms_vblank: exiting, ret=77
12959 12:19:55.144284 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12960 12:19:55.144349 Opened devi<8>[ 28.715507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12961 12:19:55.144440 ce: /dev/dri/card0
12962 12:19:55.144528 No KMS driver or no outputs, pipes: 8, outputs: 0
12963 12:19:55.144622 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12964 12:19:55.144724 <14>[ 28.736484] [IGT] kms_vblank: executing
12965 12:19:55.144815 IGT-Version: 1.2<14>[ 28.741247] [IGT] kms_vblank: exiting, ret=77
12966 12:19:55.144909 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12967 12:19:55.145005 Opened devi<8>[ 28.751487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12968 12:19:55.145094 ce: /dev/dri/card0
12969 12:19:55.145187 No KMS driver or no outputs, pipes: 8, outputs: 0
12970 12:19:55.145280 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12971 12:19:55.145369 <14>[ 28.776545] [IGT] kms_vblank: executing
12972 12:19:55.145461 IGT-Version: 1.2<14>[ 28.781334] [IGT] kms_vblank: exiting, ret=77
12973 12:19:55.145553 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12974 12:19:55.145645 Opened devi<8>[ 28.791529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12975 12:19:55.145737 ce: /dev/dri/card0
12976 12:19:55.145828 No KMS driver or no outputs, pipes: 8, outputs: 0
12977 12:19:55.145918 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12978 12:19:55.146006 <14>[ 28.811688] [IGT] kms_vblank: executing
12979 12:19:55.146100 IGT-Version: 1.2<14>[ 28.816451] [IGT] kms_vblank: exiting, ret=77
12980 12:19:55.146190 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
12981 12:19:55.146283 Opened devi<8>[ 28.827072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12982 12:19:55.146375 ce: /dev/dri/card0
12983 12:19:55.146624 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12985 12:19:55.146904 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12987 12:19:55.147214 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12989 12:19:55.147486 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12991 12:19:55.147767 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12993 12:19:55.148046 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12995 12:19:55.148318 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12997 12:19:55.148625 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12999 12:19:55.148854 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
13001 12:19:55.149060 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
13003 12:19:55.149261 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
13005 12:19:55.149502 No KMS driver or no outputs, pipes: 8, outputs: 0
13006 12:19:55.149575 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
13007 12:19:55.149686 <14>[ 28.848204] [IGT] kms_vblank: executing
13008 12:19:55.149781 IGT-Version: 1.2<14>[ 28.853072] [IGT] kms_vblank: exiting, ret=77
13009 12:19:55.149888 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13010 12:19:55.149986 Opened devi<8>[ 28.863351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
13011 12:19:55.150078 ce: /dev/dri/card0
13012 12:19:55.150182 No KMS driver or no outputs, pipes: 8, outputs: 0
13013 12:19:55.150275 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
13014 12:19:55.150375 <14>[ 28.883598] [IGT] kms_vblank: executing
13015 12:19:55.150472 IGT-Version: 1.2<14>[ 28.888368] [IGT] kms_vblank: exiting, ret=77
13016 12:19:55.150563 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13017 12:19:55.150670 Opened devi<8>[ 28.898780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
13018 12:19:55.150762 ce: /dev/dri/card0
13019 12:19:55.150851 No KMS driver or no outputs, pipes: 8, outputs: 0
13020 12:19:55.150955 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
13021 12:19:55.151046 <14>[ 28.919495] [IGT] kms_vblank: executing
13022 12:19:55.151145 IGT-Version: 1.2<14>[ 28.924230] [IGT] kms_vblank: exiting, ret=77
13023 12:19:55.151241 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13024 12:19:55.151334 Opened devi<8>[ 28.934554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
13025 12:19:55.151446 ce: /dev/dri/card0
13026 12:19:55.151537 No KMS driver or no outputs, pipes: 8, outputs: 0
13027 12:19:55.151627 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
13028 12:19:55.151731 <14>[ 28.966057] [IGT] kms_vblank: executing
13029 12:19:55.151823 IGT-Version: 1.2<14>[ 28.971135] [IGT] kms_vblank: exiting, ret=77
13030 12:19:55.151922 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13031 12:19:55.152020 Opened device: /dev/dri/car<8>[ 28.982236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
13032 12:19:55.152110 d0
13033 12:19:55.152213 No KMS driver or no outputs, pipes: 8, outputs: 0
13034 12:19:55.152306 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
13035 12:19:55.152395 <14>[ 29.003704] [IGT] kms_vblank: executing
13036 12:19:55.152499 IGT-Version: 1.2<14>[ 29.008437] [IGT] kms_vblank: exiting, ret=77
13037 12:19:55.152590 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13038 12:19:55.152694 Opened devi<8>[ 29.019000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
13039 12:19:55.152788 ce: /dev/dri/card0
13040 12:19:55.152877 No KMS driver or no outputs, pipes: 8, outputs: 0
13041 12:19:55.152981 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
13042 12:19:55.153072 <14>[ 29.040055] [IGT] kms_vblank: executing
13043 12:19:55.153162 IGT-Version: 1.2<14>[ 29.044929] [IGT] kms_vblank: exiting, ret=77
13044 12:19:55.153265 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13045 12:19:55.153359 Opened devi<8>[ 29.055165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
13046 12:19:55.153458 ce: /dev/dri/card0
13047 12:19:55.153552 No KMS driver or no outputs, pipes: 8, outputs: 0
13048 12:19:55.153642 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13049 12:19:55.153744 <14>[ 29.076981] [IGT] kms_vblank: executing
13050 12:19:55.153845 IGT-Version: 1.2<14>[ 29.081711] [IGT] kms_vblank: exiting, ret=77
13051 12:19:55.153936 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13052 12:19:55.154044 Opened devi<8>[ 29.091954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13053 12:19:55.154134 ce: /dev/dri/card0
13054 12:19:55.154232 No KMS driver or no outputs, pipes: 8, outputs: 0
13055 12:19:55.154327 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13056 12:19:55.154416 <14>[ 29.113842] [IGT] kms_vblank: executing
13057 12:19:55.154519 IGT-Version: 1.2<14>[ 29.118593] [IGT] kms_vblank: exiting, ret=77
13058 12:19:55.154610 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13059 12:19:55.154704 Opened devi<8>[ 29.129197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13060 12:19:55.154807 ce: /dev/dri/card0
13061 12:19:55.154896 No KMS driver or no outputs, pipes: 8, outputs: 0
13062 12:19:55.154997 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13063 12:19:55.155090 <14>[ 29.150417] [IGT] kms_vblank: executing
13064 12:19:55.155180 IGT-Version: 1.2<14>[ 29.155216] [IGT] kms_vblank: exiting, ret=77
13065 12:19:55.155282 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13066 12:19:55.155377 Opened devi<8>[ 29.165623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13067 12:19:55.155453 ce: /dev/dri/card0
13068 12:19:55.155539 No KMS driver or no outputs, pipes: 8, outputs: 0
13069 12:19:55.155600 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13070 12:19:55.155659 <14>[ 29.187077] [IGT] kms_vblank: executing
13071 12:19:55.155738 IGT-Version: 1.2<14>[ 29.191795] [IGT] kms_vblank: exiting, ret=77
13072 12:19:55.155805 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13073 12:19:55.155862 Opened devi<8>[ 29.202040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13074 12:19:55.155918 ce: /dev/dri/card0
13075 12:19:55.155972 No KMS driver or no outputs, pipes: 8, outputs: 0
13076 12:19:55.156226 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
13078 12:19:55.156525 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
13080 12:19:55.156721 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
13082 12:19:55.156933 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
13084 12:19:55.157141 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
13086 12:19:55.157356 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13088 12:19:55.157560 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13090 12:19:55.157749 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13092 12:19:55.157984 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13094 12:19:55.158263 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13096 12:19:55.158570 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13097 12:19:55.158667 <14>[ 29.223988] [IGT] kms_vblank: executing
13098 12:19:55.158757 IGT-Version: 1.2<14>[ 29.229138] [IGT] kms_vblank: exiting, ret=77
13099 12:19:55.158859 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13100 12:19:55.158950 Opened devi<8>[ 29.239261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13101 12:19:55.159037 ce: /dev/dri/card0
13102 12:19:55.159136 No KMS driver or no outputs, pipes: 8, outputs: 0
13103 12:19:55.159223 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13104 12:19:55.159311 <14>[ 29.260754] [IGT] kms_vblank: executing
13105 12:19:55.159435 IGT-Version: 1.2<14>[ 29.265456] [IGT] kms_vblank: exiting, ret=77
13106 12:19:55.159508 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13107 12:19:55.159578 Opened devi<8>[ 29.275985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13108 12:19:55.159646 ce: /dev/dri/card0
13109 12:19:55.159701 No KMS driver or no outputs, pipes: 8, outputs: 0
13110 12:19:55.159757 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13111 12:19:55.159816 <14>[ 29.297428] [IGT] kms_vblank: executing
13112 12:19:55.159889 IGT-Version: 1.2<14>[ 29.302183] [IGT] kms_vblank: exiting, ret=77
13113 12:19:55.159946 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13114 12:19:55.160002 Opened devi<8>[ 29.312397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13115 12:19:55.160058 ce: /dev/dri/card0
13116 12:19:55.160138 No KMS driver or no outputs, pipes: 8, outputs: 0
13117 12:19:55.160195 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13118 12:19:55.160250 <14>[ 29.334519] [IGT] kms_vblank: executing
13119 12:19:55.160305 IGT-Version: 1.2<14>[ 29.339348] [IGT] kms_vblank: exiting, ret=77
13120 12:19:55.160384 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13121 12:19:55.160462 Opened devi<8>[ 29.349643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13122 12:19:55.160531 ce: /dev/dri/card0
13123 12:19:55.160599 No KMS driver or no outputs, pipes: 8, outputs: 0
13124 12:19:55.160661 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13125 12:19:55.160716 <14>[ 29.371339] [IGT] kms_vblank: executing
13126 12:19:55.160771 IGT-Version: 1.2<14>[ 29.376349] [IGT] kms_vblank: exiting, ret=77
13127 12:19:55.160829 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13128 12:19:55.160903 Opened devi<8>[ 29.386799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13129 12:19:55.160960 ce: /dev/dri/card0
13130 12:19:55.161014 No KMS driver or no outputs, pipes: 8, outputs: 0
13131 12:19:55.161068 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13132 12:19:55.161146 <14>[ 29.407201] [IGT] kms_vblank: executing
13133 12:19:55.161202 IGT-Version: 1.2<14>[ 29.411915] [IGT] kms_vblank: exiting, ret=77
13134 12:19:55.161257 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13135 12:19:55.161313 Opened devi<8>[ 29.422448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13136 12:19:55.161393 ce: /dev/dri/card0
13137 12:19:55.161449 No KMS driver or no outputs, pipes: 8, outputs: 0
13138 12:19:55.161505 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13139 12:19:55.161559 <14>[ 29.443529] [IGT] kms_vblank: executing
13140 12:19:55.161630 IGT-Version: 1.2<14>[ 29.448382] [IGT] kms_vblank: exiting, ret=77
13141 12:19:55.161692 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13142 12:19:55.161749 Opened devi<8>[ 29.458519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13143 12:19:55.161804 ce: /dev/dri/card0
13144 12:19:55.161870 No KMS driver or no outputs, pipes: 8, outputs: 0
13145 12:19:55.161934 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13146 12:19:55.161993 <14>[ 29.479813] [IGT] kms_vblank: executing
13147 12:19:55.162048 IGT-Version: 1.2<14>[ 29.484575] [IGT] kms_vblank: exiting, ret=77
13148 12:19:55.162102 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13149 12:19:55.162162 Opened devi<8>[ 29.494926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13150 12:19:55.162219 ce: /dev/dri/card0
13151 12:19:55.162278 No KMS driver or no outputs, pipes: 8, outputs: 0
13152 12:19:55.162334 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13153 12:19:55.162388 <14>[ 29.515809] [IGT] kms_vblank: executing
13154 12:19:55.162442 IGT-Version: 1.2<14>[ 29.520555] [IGT] kms_vblank: exiting, ret=77
13155 12:19:55.162503 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13156 12:19:55.162563 Opened devi<8>[ 29.530812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13157 12:19:55.162619 ce: /dev/dri/card0
13158 12:19:55.162673 No KMS driver or no outputs, pipes: 8, outputs: 0
13159 12:19:55.162727 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13160 12:19:55.162785 <14>[ 29.551597] [IGT] kms_vblank: executing
13161 12:19:55.162841 IGT-Version: 1.2<14>[ 29.556292] [IGT] kms_vblank: exiting, ret=77
13162 12:19:55.162920 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13163 12:19:55.163007 Opened devi<8>[ 29.566788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13164 12:19:55.163093 ce: /dev/dri/card0
13165 12:19:55.163178 No KMS driver or no outputs, pipes: 8, outputs: 0
13166 12:19:55.163263 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13167 12:19:55.163523 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13169 12:19:55.163714 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13171 12:19:55.163910 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13173 12:19:55.164103 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13175 12:19:55.164291 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13177 12:19:55.164518 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13179 12:19:55.164807 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13181 12:19:55.165033 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13183 12:19:55.165218 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13185 12:19:55.165410 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13187 12:19:55.165611 <14>[ 29.587296] [IGT] kms_vblank: executing
13188 12:19:55.165682 IGT-Version: 1.2<14>[ 29.592008] [IGT] kms_vblank: exiting, ret=77
13189 12:19:55.165743 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13190 12:19:55.165804 Opened devi<8>[ 29.602477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13191 12:19:55.165878 ce: /dev/dri/card0
13192 12:19:55.165941 No KMS driver or no outputs, pipes: 8, outputs: 0
13193 12:19:55.165999 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13194 12:19:55.166055 <14>[ 29.623184] [IGT] kms_vblank: executing
13195 12:19:55.166122 IGT-Version: 1.2<14>[ 29.627984] [IGT] kms_vblank: exiting, ret=77
13196 12:19:55.166189 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13197 12:19:55.166247 Opened devi<8>[ 29.638282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13198 12:19:55.166302 ce: /dev/dri/card0
13199 12:19:55.166365 No KMS driver or no outputs, pipes: 8, outputs: 0
13200 12:19:55.166435 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13201 12:19:55.166491 <14>[ 29.659304] [IGT] kms_vblank: executing
13202 12:19:55.166546 IGT-Version: 1.2<14>[ 29.664044] [IGT] kms_vblank: exiting, ret=77
13203 12:19:55.166601 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13204 12:19:55.166680 Opened devi<8>[ 29.674282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13205 12:19:55.166737 ce: /dev/dri/card0
13206 12:19:55.166792 No KMS driver or no outputs, pipes: 8, outputs: 0
13207 12:19:55.166847 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13208 12:19:55.166931 <14>[ 29.699287] [IGT] kms_vblank: executing
13209 12:19:55.167017 IGT-Version: 1.2<14>[ 29.704019] [IGT] kms_vblank: exiting, ret=77
13210 12:19:55.167101 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13211 12:19:55.167202 Opened devi<8>[ 29.714298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13212 12:19:55.167287 ce: /dev/dri/card0
13213 12:19:55.167370 No KMS driver or no outputs, pipes: 8, outputs: 0
13214 12:19:55.167509 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13215 12:19:55.167594 <14>[ 29.734599] [IGT] kms_vblank: executing
13216 12:19:55.167690 IGT-Version: 1.2<14>[ 29.739339] [IGT] kms_vblank: exiting, ret=77
13217 12:19:55.167777 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13218 12:19:55.167864 Opened devi<8>[ 29.749662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13219 12:19:55.167961 ce: /dev/dri/card0
13220 12:19:55.168046 No KMS driver or no outputs, pipes: 8, outputs: 0
13221 12:19:55.168131 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13222 12:19:55.168227 <14>[ 29.770318] [IGT] kms_vblank: executing
13223 12:19:55.168312 IGT-Version: 1.2<14>[ 29.775052] [IGT] kms_vblank: exiting, ret=77
13224 12:19:55.168396 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13225 12:19:55.168496 Opened devi<8>[ 29.785477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13226 12:19:55.168581 ce: /dev/dri/card0
13227 12:19:55.168665 No KMS driver or no outputs, pipes: 8, outputs: 0
13228 12:19:55.168761 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13229 12:19:55.168844 <14>[ 29.806340] [IGT] kms_vblank: executing
13230 12:19:55.168935 IGT-Version: 1.2<14>[ 29.811071] [IGT] kms_vblank: exiting, ret=77
13231 12:19:55.169025 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13232 12:19:55.169112 Opened devi<8>[ 29.821527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13233 12:19:55.169205 ce: /dev/dri/card0
13234 12:19:55.169291 No KMS driver or no outputs, pipes: 8, outputs: 0
13235 12:19:55.169375 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13236 12:19:55.169470 <14>[ 29.842359] [IGT] kms_vblank: executing
13237 12:19:55.169556 IGT-Version: 1.2<14>[ 29.847153] [IGT] kms_vblank: exiting, ret=77
13238 12:19:55.169639 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13239 12:19:55.169739 Opened devi<8>[ 29.857484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13240 12:19:55.169824 ce: /dev/dri/card0
13241 12:19:55.169907 No KMS driver or no outputs, pipes: 8, outputs: 0
13242 12:19:55.170004 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13243 12:19:55.170088 <14>[ 29.878313] [IGT] kms_vblank: executing
13244 12:19:55.170172 IGT-Version: 1.2<14>[ 29.883037] [IGT] kms_vblank: exiting, ret=77
13245 12:19:55.170268 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13246 12:19:55.170356 Opened devi<8>[ 29.893490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13247 12:19:55.170441 ce: /dev/dri/card0
13248 12:19:55.170535 No KMS driver or no outputs, pipes: 8, outputs: 0
13249 12:19:55.170619 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13250 12:19:55.170710 <14>[ 29.913980] [IGT] kms_vblank: executing
13251 12:19:55.170800 IGT-Version: 1.2<14>[ 29.918868] [IGT] kms_vblank: exiting, ret=77
13252 12:19:55.170883 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13253 12:19:55.170980 Opened devi<8>[ 29.929329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13254 12:19:55.171067 ce: /dev/dri/card0
13255 12:19:55.171150 No KMS driver or no outputs, pipes: 8, outputs: 0
13256 12:19:55.171246 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13257 12:19:55.171331 <14>[ 29.950047] [IGT] kms_vblank: executing
13258 12:19:55.171451 IGT-Version: 1.2<14>[ 29.954865] [IGT] kms_vblank: exiting, ret=77
13259 12:19:55.171712 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13261 12:19:55.172013 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13263 12:19:55.172303 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13265 12:19:55.172490 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13267 12:19:55.172698 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13269 12:19:55.172903 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13271 12:19:55.173112 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13273 12:19:55.173312 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13275 12:19:55.173499 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13277 12:19:55.173798 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13279 12:19:55.174104 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13280 12:19:55.174204 Opened devi<8>[ 29.965356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13281 12:19:55.174299 ce: /dev/dri/card0
13282 12:19:55.174393 No KMS driver or no outputs, pipes: 8, outputs: 0
13283 12:19:55.174481 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13284 12:19:55.174576 <14>[ 29.986259] [IGT] kms_vblank: executing
13285 12:19:55.174666 IGT-Version: 1.2<14>[ 29.990986] [IGT] kms_vblank: exiting, ret=77
13286 12:19:55.174750 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13287 12:19:55.174857 Opened devi<8>[ 30.001548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13288 12:19:55.174945 ce: /dev/dri/card0
13289 12:19:55.175029 No KMS driver or no outputs, pipes: 8, outputs: 0
13290 12:19:55.175127 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13291 12:19:55.175212 <14>[ 30.026540] [IGT] kms_vblank: executing
13292 12:19:55.175296 IGT-Version: 1.2<14>[ 30.031272] [IGT] kms_vblank: exiting, ret=77
13293 12:19:55.175401 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13294 12:19:55.175463 Opened devi<8>[ 30.041549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13295 12:19:55.175520 ce: /dev/dri/card0
13296 12:19:55.175588 No KMS driver or no outputs, pipes: 8, outputs: 0
13297 12:19:55.175651 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13298 12:19:55.175706 <14>[ 30.063533] [IGT] kms_vblank: executing
13299 12:19:55.175760 IGT-Version: 1.2<14>[ 30.068263] [IGT] kms_vblank: exiting, ret=77
13300 12:19:55.175818 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13301 12:19:55.175892 Opened devi<8>[ 30.078553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13302 12:19:55.175948 ce: /dev/dri/card0
13303 12:19:55.176001 No KMS driver or no outputs, pipes: 8, outputs: 0
13304 12:19:55.176056 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13305 12:19:55.176133 <14>[ 30.099985] [IGT] kms_vblank: executing
13306 12:19:55.176190 IGT-Version: 1.2<14>[ 30.104894] [IGT] kms_vblank: exiting, ret=77
13307 12:19:55.176244 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13308 12:19:55.176300 Opened devi<8>[ 30.115211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13309 12:19:55.176379 ce: /dev/dri/card0
13310 12:19:55.176435 No KMS driver or no outputs, pipes: 8, outputs: 0
13311 12:19:55.176492 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13312 12:19:55.176546 <14>[ 30.136990] [IGT] kms_vblank: executing
13313 12:19:55.176619 IGT-Version: 1.2<14>[ 30.141990] [IGT] kms_vblank: exiting, ret=77
13314 12:19:55.176706 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13315 12:19:55.176793 Opened devi<8>[ 30.152418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13316 12:19:55.176884 ce: /dev/dri/card0
13317 12:19:55.176941 No KMS driver or no outputs, pipes: 8, outputs: 0
13318 12:19:55.176999 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13319 12:19:55.177053 <14>[ 30.174135] [IGT] kms_vblank: executing
13320 12:19:55.177123 IGT-Version: 1.2<14>[ 30.178867] [IGT] kms_vblank: exiting, ret=77
13321 12:19:55.177184 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13322 12:19:55.177240 Opened devi<8>[ 30.189345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13323 12:19:55.177294 ce: /dev/dri/card0
13324 12:19:55.177361 No KMS driver or no outputs, pipes: 8, outputs: 0
13325 12:19:55.177423 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13326 12:19:55.177478 <14>[ 30.214701] [IGT] kms_vblank: executing
13327 12:19:55.177533 IGT-Version: 1.2<14>[ 30.219430] [IGT] kms_vblank: exiting, ret=77
13328 12:19:55.177589 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13329 12:19:55.177664 Opened devi<8>[ 30.229722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13330 12:19:55.177720 ce: /dev/dri/card0
13331 12:19:55.177773 No KMS driver or no outputs, pipes: 8, outputs: 0
13332 12:19:55.177826 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13333 12:19:55.177908 <14>[ 30.251955] [IGT] kms_vblank: executing
13334 12:19:55.177993 IGT-Version: 1.2<14>[ 30.256716] [IGT] kms_vblank: exiting, ret=77
13335 12:19:55.178076 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13336 12:19:55.178175 Opened devi<8>[ 30.266932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13337 12:19:55.178259 ce: /dev/dri/card0
13338 12:19:55.178342 No KMS driver or no outputs, pipes: 8, outputs: 0
13339 12:19:55.178439 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13340 12:19:55.178523 <14>[ 30.288844] [IGT] kms_vblank: executing
13341 12:19:55.178608 IGT-Version: 1.2<14>[ 30.293709] [IGT] kms_vblank: exiting, ret=77
13342 12:19:55.178704 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13343 12:19:55.178792 Opened devi<8>[ 30.303986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13344 12:19:55.178883 ce: /dev/dri/card0
13345 12:19:55.178977 No KMS driver or no outputs, pipes: 8, outputs: 0
13346 12:19:55.179063 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13347 12:19:55.179156 <14>[ 30.324865] [IGT] kms_vblank: executing
13348 12:19:55.179418 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13350 12:19:55.179716 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13352 12:19:55.180016 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13354 12:19:55.180319 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13356 12:19:55.180617 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13358 12:19:55.180923 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13360 12:19:55.181223 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13362 12:19:55.181522 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13364 12:19:55.181818 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13366 12:19:55.182114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13368 12:19:55.182420 IGT-Version: 1.2<14>[ 30.329588] [IGT] kms_vblank: exiting, ret=77
13369 12:19:55.182514 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13370 12:19:55.182606 Opened devi<8>[ 30.340007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13371 12:19:55.182693 ce: /dev/dri/card0
13372 12:19:55.182779 No KMS driver or no outputs, pipes: 8, outputs: 0
13373 12:19:55.182869 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13374 12:19:55.182929 <14>[ 30.360241] [IGT] kms_vblank: executing
13375 12:19:55.182986 IGT-Version: 1.2<14>[ 30.365147] [IGT] kms_vblank: exiting, ret=77
13376 12:19:55.183042 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13377 12:19:55.183098 Opened devi<8>[ 30.375479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13378 12:19:55.183153 ce: /dev/dri/card0
13379 12:19:55.183211 No KMS driver or no outputs, pipes: 8, outputs: 0
13380 12:19:55.183307 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13381 12:19:55.183423 <14>[ 30.396651] [IGT] kms_vblank: executing
13382 12:19:55.183496 IGT-Version: 1.2<14>[ 30.401389] [IGT] kms_vblank: exiting, ret=77
13383 12:19:55.183552 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13384 12:19:55.183633 Opened devi<8>[ 30.411550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13385 12:19:55.183690 ce: /dev/dri/card0
13386 12:19:55.183745 No KMS driver or no outputs, pipes: 8, outputs: 0
13387 12:19:55.183803 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13388 12:19:55.183874 <14>[ 30.432653] [IGT] kms_vblank: executing
13389 12:19:55.183950 IGT-Version: 1.2<14>[ 30.437389] [IGT] kms_vblank: exiting, ret=77
13390 12:19:55.184006 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13391 12:19:55.184062 Opened devi<8>[ 30.447708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13392 12:19:55.184117 ce: /dev/dri/card0
13393 12:19:55.184177 No KMS driver or no outputs, pipes: 8, outputs: 0
13394 12:19:55.184235 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13395 12:19:55.184290 <14>[ 30.469233] [IGT] kms_vblank: executing
13396 12:19:55.184345 IGT-Version: 1.2<14>[ 30.473966] [IGT] kms_vblank: exiting, ret=77
13397 12:19:55.184399 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13398 12:19:55.184461 Opened devi<8>[ 30.484165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13399 12:19:55.184517 ce: /dev/dri/card0
13400 12:19:55.184574 No KMS driver or no outputs, pipes: 8, outputs: 0
13401 12:19:55.184629 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13402 12:19:55.184682 <14>[ 30.505270] [IGT] kms_vblank: executing
13403 12:19:55.184735 IGT-Version: 1.2<14>[ 30.510060] [IGT] kms_vblank: exiting, ret=77
13404 12:19:55.184794 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13405 12:19:55.184852 Opened devi<8>[ 30.520363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13406 12:19:55.184907 ce: /dev/dri/card0
13407 12:19:55.184961 No KMS driver or no outputs, pipes: 8, outputs: 0
13408 12:19:55.185014 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13409 12:19:55.185073 <14>[ 30.541076] [IGT] kms_vblank: executing
13410 12:19:55.185127 IGT-Version: 1.2<14>[ 30.545810] [IGT] kms_vblank: exiting, ret=77
13411 12:19:55.185185 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13412 12:19:55.185241 Opened devi<8>[ 30.556063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13413 12:19:55.185295 ce: /dev/dri/card0
13414 12:19:55.185348 No KMS driver or no outputs, pipes: 8, outputs: 0
13415 12:19:55.185435 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13416 12:19:55.185520 <14>[ 30.577336] [IGT] kms_vblank: executing
13417 12:19:55.185604 IGT-Version: 1.2<14>[ 30.582069] [IGT] kms_vblank: exiting, ret=77
13418 12:19:55.185690 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13419 12:19:55.185779 Opened devi<8>[ 30.592360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13420 12:19:55.185862 ce: /dev/dri/card0
13421 12:19:55.185947 No KMS driver or no outputs, pipes: 8, outputs: 0
13422 12:19:55.186035 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13423 12:19:55.186118 <14>[ 30.613934] [IGT] kms_vblank: executing
13424 12:19:55.186201 IGT-Version: 1.2<14>[ 30.618679] [IGT] kms_vblank: exiting, ret=77
13425 12:19:55.186289 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13426 12:19:55.186376 Opened devi<8>[ 30.629250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13427 12:19:55.186460 ce: /dev/dri/card0
13428 12:19:55.186546 No KMS driver or no outputs, pipes: 8, outputs: 0
13429 12:19:55.186631 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13430 12:19:55.186713 <14>[ 30.649640] [IGT] kms_vblank: executing
13431 12:19:55.186800 IGT-Version: 1.2<14>[ 30.654413] [IGT] kms_vblank: exiting, ret=77
13432 12:19:55.186886 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13433 12:19:55.186972 Opened devi<8>[ 30.665085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13434 12:19:55.187058 ce: /dev/dri/card0
13435 12:19:55.187143 No KMS driver or no outputs, pipes: 8, outputs: 0
13436 12:19:55.187227 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13437 12:19:55.187310 <14>[ 30.685249] [IGT] kms_vblank: executing
13438 12:19:55.187404 IGT-Version: 1.2<14>[ 30.690057] [IGT] kms_vblank: exiting, ret=77
13439 12:19:55.187503 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13440 12:19:55.187738 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13442 12:19:55.187922 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13444 12:19:55.188115 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13446 12:19:55.188311 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13448 12:19:55.188513 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13450 12:19:55.188781 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13452 12:19:55.189072 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13454 12:19:55.189361 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13456 12:19:55.189648 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13458 12:19:55.189935 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13460 12:19:55.190235 Opened devi<8>[ 30.700574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13461 12:19:55.190341 ce: /dev/dri/card0
13462 12:19:55.190430 No KMS driver or no outputs, pipes: 8, outputs: 0
13463 12:19:55.190521 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13464 12:19:55.190617 <14>[ 30.721209] [IGT] kms_vblank: executing
13465 12:19:55.190704 IGT-Version: 1.2<14>[ 30.725949] [IGT] kms_vblank: exiting, ret=77
13466 12:19:55.190798 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13467 12:19:55.190890 Opened devi<8>[ 30.736252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13468 12:19:55.190975 ce: /dev/dri/card0
13469 12:19:55.191069 No KMS driver or no outputs, pipes: 8, outputs: 0
13470 12:19:55.191156 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13471 12:19:55.191239 <14>[ 30.757297] [IGT] kms_vblank: executing
13472 12:19:55.191335 IGT-Version: 1.2<14>[ 30.762012] [IGT] kms_vblank: exiting, ret=77
13473 12:19:55.191456 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13474 12:19:55.191563 Opened devi<8>[ 30.772273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13475 12:19:55.191626 ce: /dev/dri/card0
13476 12:19:55.191680 No KMS driver or no outputs, pipes: 8, outputs: 0
13477 12:19:55.191735 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13478 12:19:55.191800 <14>[ 30.792959] [IGT] kms_vblank: executing
13479 12:19:55.191891 IGT-Version: 1.2<14>[ 30.797685] [IGT] kms_vblank: exiting, ret=77
13480 12:19:55.191975 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13481 12:19:55.192071 Opened devi<8>[ 30.808002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13482 12:19:55.192160 ce: /dev/dri/card0
13483 12:19:55.192243 No KMS driver or no outputs, pipes: 8, outputs: 0
13484 12:19:55.192339 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13485 12:19:55.192424 <14>[ 30.828898] [IGT] kms_vblank: executing
13486 12:19:55.192517 IGT-Version: 1.2<14>[ 30.833633] [IGT] kms_vblank: exiting, ret=77
13487 12:19:55.192616 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13488 12:19:55.192706 Opened devi<8>[ 30.844082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13489 12:19:55.192790 ce: /dev/dri/card0
13490 12:19:55.192876 No KMS driver or no outputs, pipes: 8, outputs: 0
13491 12:19:55.192963 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13492 12:19:55.193049 <14>[ 30.865177] [IGT] kms_vblank: executing
13493 12:19:55.193136 IGT-Version: 1.2<14>[ 30.869951] [IGT] kms_vblank: exiting, ret=77
13494 12:19:55.193221 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13495 12:19:55.193308 Opened devi<8>[ 30.880279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13496 12:19:55.193391 ce: /dev/dri/card0
13497 12:19:55.193477 No KMS driver or no outputs, pipes: 8, outputs: 0
13498 12:19:55.193563 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13499 12:19:55.193646 <14>[ 30.901859] [IGT] kms_vblank: executing
13500 12:19:55.193733 IGT-Version: 1.2<14>[ 30.906600] [IGT] kms_vblank: exiting, ret=77
13501 12:19:55.193818 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13502 12:19:55.193905 Opened device: /dev/dri/car<8>[ 30.918927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13503 12:19:55.193988 d0
13504 12:19:55.194076 No KMS driver or no outputs, pipes: 8, outputs: 0
13505 12:19:55.194160 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13506 12:19:55.194243 <14>[ 30.939841] [IGT] kms_vblank: executing
13507 12:19:55.194329 IGT-Version: 1.2<14>[ 30.944654] [IGT] kms_vblank: exiting, ret=77
13508 12:19:55.194414 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13509 12:19:55.194501 Opened devi<8>[ 30.954954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13510 12:19:55.194584 ce: /dev/dri/card0
13511 12:19:55.194640 No KMS driver or no outputs, pipes: 8, outputs: 0
13512 12:19:55.194698 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13513 12:19:55.194753 <14>[ 30.976334] [IGT] kms_vblank: executing
13514 12:19:55.194806 IGT-Version: 1.2<14>[ 30.981218] [IGT] kms_vblank: exiting, ret=77
13515 12:19:55.194864 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13516 12:19:55.194954 Opened devi<8>[ 30.991514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13517 12:19:55.195037 ce: /dev/dri/card0
13518 12:19:55.195119 No KMS driver or no outputs, pipes: 8, outputs: 0
13519 12:19:55.195206 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13520 12:19:55.195291 <14>[ 31.013148] [IGT] kms_vblank: executing
13521 12:19:55.195375 IGT-Version: 1.2<14>[ 31.017898] [IGT] kms_vblank: exiting, ret=77
13522 12:19:55.195483 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13523 12:19:55.195541 Opened devi<8>[ 31.028186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13524 12:19:55.195598 ce: /dev/dri/card0
13525 12:19:55.195652 No KMS driver or no outputs, pipes: 8, outputs: 0
13526 12:19:55.195706 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13527 12:19:55.195760 <14>[ 31.050224] [IGT] kms_vblank: executing
13528 12:19:55.195819 IGT-Version: 1.2<14>[ 31.055075] [IGT] kms_vblank: exiting, ret=77
13529 12:19:55.195883 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13530 12:19:55.195970 Opened devi<8>[ 31.065661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13531 12:19:55.196231 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13533 12:19:55.196519 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13535 12:19:55.196807 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13537 12:19:55.197094 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13539 12:19:55.197381 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13541 12:19:55.197666 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13543 12:19:55.197950 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13545 12:19:55.198234 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13547 12:19:55.198519 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13549 12:19:55.198708 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13551 12:19:55.198971 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13553 12:19:55.199266 ce: /dev/dri/card0
13554 12:19:55.199359 No KMS driver or no outputs, pipes: 8, outputs: 0
13555 12:19:55.199476 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13556 12:19:55.199542 <14>[ 31.086892] [IGT] kms_vblank: executing
13557 12:19:55.199603 IGT-Version: 1.2<14>[ 31.091638] [IGT] kms_vblank: exiting, ret=77
13558 12:19:55.199659 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13559 12:19:55.199716 Opened devi<8>[ 31.101778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13560 12:19:55.199776 ce: /dev/dri/card0
13561 12:19:55.199852 No KMS driver or no outputs, pipes: 8, outputs: 0
13562 12:19:55.199937 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13563 12:19:55.200024 <14>[ 31.123402] [IGT] kms_vblank: executing
13564 12:19:55.200111 IGT-Version: 1.2<14>[ 31.128137] [IGT] kms_vblank: exiting, ret=77
13565 12:19:55.200195 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13566 12:19:55.200286 Opened devi<8>[ 31.138450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13567 12:19:55.200372 ce: /dev/dri/card0
13568 12:19:55.200455 No KMS driver or no outputs, pipes: 8, outputs: 0
13569 12:19:55.200544 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13570 12:19:55.200628 <14>[ 31.160203] [IGT] kms_vblank: executing
13571 12:19:55.200711 IGT-Version: 1.2<14>[ 31.165467] [IGT] kms_vblank: exiting, ret=77
13572 12:19:55.200799 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13573 12:19:55.200887 Opened devi<8>[ 31.175681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13574 12:19:55.200970 ce: /dev/dri/card0
13575 12:19:55.201057 No KMS driver or no outputs, pipes: 8, outputs: 0
13576 12:19:55.201142 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13577 12:19:55.201224 <14>[ 31.197658] [IGT] kms_vblank: executing
13578 12:19:55.201313 IGT-Version: 1.2<14>[ 31.202520] [IGT] kms_vblank: exiting, ret=77
13579 12:19:55.201396 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13580 12:19:55.201483 Opened devi<8>[ 31.212967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13581 12:19:55.201569 ce: /dev/dri/card0
13582 12:19:55.201652 No KMS driver or no outputs, pipes: 8, outputs: 0
13583 12:19:55.201738 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13584 12:19:55.201823 <14>[ 31.233335] [IGT] kms_vblank: executing
13585 12:19:55.201907 IGT-Version: 1.2<14>[ 31.238145] [IGT] kms_vblank: exiting, ret=77
13586 12:19:55.201992 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13587 12:19:55.202080 Opened devi<8>[ 31.248366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13588 12:19:55.202163 ce: /dev/dri/card0
13589 12:19:55.202248 No KMS driver or no outputs, pipes: 8, outputs: 0
13590 12:19:55.202333 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13591 12:19:55.202416 <14>[ 31.269046] [IGT] kms_vblank: executing
13592 12:19:55.202496 IGT-Version: 1.2<14>[ 31.273899] [IGT] kms_vblank: exiting, ret=77
13593 12:19:55.202556 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13594 12:19:55.202613 Opened devi<8>[ 31.284200] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13595 12:19:55.202667 ce: /dev/dri/card0
13596 12:19:55.202724 No KMS driver or no outputs, pipes: 8, outputs: 0
13597 12:19:55.202812 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13598 12:19:55.202895 <14>[ 31.305259] [IGT] kms_vblank: executing
13599 12:19:55.202981 IGT-Version: 1.2<14>[ 31.309976] [IGT] kms_vblank: exiting, ret=77
13600 12:19:55.203067 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13601 12:19:55.203154 Opened devi<8>[ 31.320268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13602 12:19:55.203240 ce: /dev/dri/card0
13603 12:19:55.203324 No KMS driver or no outputs, pipes: 8, outputs: 0
13604 12:19:55.203439 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13605 12:19:55.203519 <14>[ 31.341092] [IGT] kms_vblank: executing
13606 12:19:55.203575 IGT-Version: 1.2<14>[ 31.345824] [IGT] kms_vblank: exiting, ret=77
13607 12:19:55.203629 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13608 12:19:55.203684 Opened devi<8>[ 31.356095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13609 12:19:55.203751 ce: /dev/dri/card0
13610 12:19:55.203836 No KMS driver or no outputs, pipes: 8, outputs: 0
13611 12:19:55.203920 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13612 12:19:55.204008 <14>[ 31.377211] [IGT] kms_vblank: executing
13613 12:19:55.204093 IGT-Version: 1.2<14>[ 31.381937] [IGT] kms_vblank: exiting, ret=77
13614 12:19:55.204176 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13615 12:19:55.204266 Opened devi<8>[ 31.392314] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13616 12:19:55.204350 ce: /dev/dri/card0
13617 12:19:55.204432 No KMS driver or no outputs, pipes: 8, outputs: 0
13618 12:19:55.204520 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13619 12:19:55.204603 <14>[ 31.412914] [IGT] kms_vblank: executing
13620 12:19:55.204687 IGT-Version: 1.2<14>[ 31.417657] [IGT] kms_vblank: exiting, ret=77
13621 12:19:55.204774 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13622 12:19:55.204861 Opened devi<8>[ 31.427948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13623 12:19:55.204943 ce: /dev/dri/card0
13624 12:19:55.205211 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13626 12:19:55.205502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13628 12:19:55.205790 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13630 12:19:55.206076 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13632 12:19:55.206361 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13634 12:19:55.206577 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13636 12:19:55.206764 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13638 12:19:55.207056 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13640 12:19:55.207342 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13642 12:19:55.207641 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13644 12:19:55.207872 No KMS driver or no outputs, pipes: 8, outputs: 0
13645 12:19:55.207967 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13646 12:19:55.208058 <14>[ 31.449124] [IGT] kms_vblank: executing
13647 12:19:55.208149 IGT-Version: 1.2<14>[ 31.453950] [IGT] kms_vblank: exiting, ret=77
13648 12:19:55.208235 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13649 12:19:55.208327 Opened devi<8>[ 31.464318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13650 12:19:55.208415 ce: /dev/dri/card0
13651 12:19:55.208498 No KMS driver or no outputs, pipes: 8, outputs: 0
13652 12:19:55.208597 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13653 12:19:55.208682 <14>[ 31.485275] [IGT] kms_vblank: executing
13654 12:19:55.208767 IGT-Version: 1.2<14>[ 31.490019] [IGT] kms_vblank: exiting, ret=77
13655 12:19:55.208864 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13656 12:19:55.208952 Opened devi<8>[ 31.500294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13657 12:19:55.209046 ce: /dev/dri/card0
13658 12:19:55.209133 No KMS driver or no outputs, pipes: 8, outputs: 0
13659 12:19:55.209218 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13660 12:19:55.209301 <14>[ 31.521822] [IGT] kms_vblank: executing
13661 12:19:55.209397 IGT-Version: 1.2<14>[ 31.526553] [IGT] kms_vblank: exiting, ret=77
13662 12:19:55.209482 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13663 12:19:55.209569 Opened devi<8>[ 31.537052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13664 12:19:55.209665 ce: /dev/dri/card0
13665 12:19:55.209748 No KMS driver or no outputs, pipes: 8, outputs: 0
13666 12:19:55.209833 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13667 12:19:55.209927 <14>[ 31.557568] [IGT] kms_vblank: executing
13668 12:19:55.210012 IGT-Version: 1.2<14>[ 31.562303] [IGT] kms_vblank: exiting, ret=77
13669 12:19:55.210099 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13670 12:19:55.210193 Opened devi<8>[ 31.572766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13671 12:19:55.210277 ce: /dev/dri/card0
13672 12:19:55.210368 No KMS driver or no outputs, pipes: 8, outputs: 0
13673 12:19:55.210456 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13674 12:19:55.210539 <14>[ 31.593589] [IGT] kms_vblank: executing
13675 12:19:55.210629 IGT-Version: 1.2<14>[ 31.598291] [IGT] kms_vblank: exiting, ret=77
13676 12:19:55.210691 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13677 12:19:55.210747 Opened devi<8>[ 31.608899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13678 12:19:55.210802 ce: /dev/dri/card0
13679 12:19:55.210869 No KMS driver or no outputs, pipes: 8, outputs: 0
13680 12:19:55.210958 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13681 12:19:55.211042 <14>[ 31.629355] [IGT] kms_vblank: executing
13682 12:19:55.211134 IGT-Version: 1.2<14>[ 31.634100] [IGT] kms_vblank: exiting, ret=77
13683 12:19:55.211221 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13684 12:19:55.211309 Opened devi<8>[ 31.644443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13685 12:19:55.211410 ce: /dev/dri/card0
13686 12:19:55.211468 No KMS driver or no outputs, pipes: 8, outputs: 0
13687 12:19:55.211523 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13688 12:19:55.211578 <14>[ 31.665518] [IGT] kms_vblank: executing
13689 12:19:55.211653 IGT-Version: 1.2<14>[ 31.670218] [IGT] kms_vblank: exiting, ret=77
13690 12:19:55.211712 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13691 12:19:55.211768 Opened devi<8>[ 31.680578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13692 12:19:55.211822 ce: /dev/dri/card0
13693 12:19:55.211887 No KMS driver or no outputs, pipes: 8, outputs: 0
13694 12:19:55.211953 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13695 12:19:55.212007 <14>[ 31.700881] [IGT] kms_vblank: executing
13696 12:19:55.212062 IGT-Version: 1.2<14>[ 31.705613] [IGT] kms_vblank: exiting, ret=77
13697 12:19:55.212115 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13698 12:19:55.212195 Opened devi<8>[ 31.715814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13699 12:19:55.212251 ce: /dev/dri/card0
13700 12:19:55.212304 No KMS driver or no outputs, pipes: 8, outputs: 0
13701 12:19:55.212359 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13702 12:19:55.212450 <14>[ 31.736747] [IGT] kms_vblank: executing
13703 12:19:55.212547 IGT-Version: 1.2<14>[ 31.741552] [IGT] kms_vblank: exiting, ret=77
13704 12:19:55.212634 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13705 12:19:55.212733 Opened devi<8>[ 31.751847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13706 12:19:55.212817 ce: /dev/dri/card0
13707 12:19:55.212906 No KMS driver or no outputs, pipes: 8, outputs: 0
13708 12:19:55.212997 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13709 12:19:55.213080 <14>[ 31.772967] [IGT] kms_vblank: executing
13710 12:19:55.213173 IGT-Version: 1.2<14>[ 31.777692] [IGT] kms_vblank: exiting, ret=77
13711 12:19:55.213261 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13712 12:19:55.213348 Opened devi<8>[ 31.788066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13713 12:19:55.213443 ce: /dev/dri/card0
13714 12:19:55.213528 No KMS driver or no outputs, pipes: 8, outputs: 0
13715 12:19:55.213612 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13716 12:19:57.364070 <14>[ 31.809625] [IGT] kms_vblank: executing
13717 12:19:57.364403 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13719 12:19:57.364636 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13721 12:19:57.364891 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13723 12:19:57.365207 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13725 12:19:57.365502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13727 12:19:57.365792 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13729 12:19:57.366088 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13731 12:19:57.366375 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13733 12:19:57.366677 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13735 12:19:57.366966 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13737 12:19:57.367276 IGT-Version: 1.2<14>[ 31.814343] [IGT] kms_vblank: exiting, ret=77
13738 12:19:57.367373 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13739 12:19:57.367478 Opened devi<8>[ 31.824634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13740 12:19:57.367566 ce: /dev/dri/card0
13741 12:19:57.367654 No KMS driver or no outputs, pipes: 8, outputs: 0
13742 12:19:57.367744 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13743 12:19:57.367831 <14>[ 31.845967] [IGT] kms_vblank: executing
13744 12:19:57.367919 IGT-Version: 1.2<14>[ 31.850709] [IGT] kms_vblank: exiting, ret=77
13745 12:19:57.368007 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13746 12:19:57.368096 Opened devi<8>[ 31.861268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13747 12:19:57.368181 ce: /dev/dri/card0
13748 12:19:57.368267 No KMS driver or no outputs, pipes: 8, outputs: 0
13749 12:19:57.368356 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13750 12:19:57.368440 <14>[ 31.882720] [IGT] kms_vblank: executing
13751 12:19:57.368528 IGT-Version: 1.2<14>[ 31.887454] [IGT] kms_vblank: exiting, ret=77
13752 12:19:57.368615 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13753 12:19:57.368702 Opened devi<8>[ 31.897795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13754 12:19:57.368795 ce: /dev/dri/card0
13755 12:19:57.368893 No KMS driver or no outputs, pipes: 8, outputs: 0
13756 12:19:57.368983 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13757 12:19:57.369068 <14>[ 31.919346] [IGT] kms_vblank: executing
13758 12:19:57.369156 IGT-Version: 1.2<14>[ 31.924088] [IGT] kms_vblank: exiting, ret=77
13759 12:19:57.369243 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13760 12:19:57.369331 Opened devi<8>[ 31.934497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13761 12:19:57.369418 ce: /dev/dri/card0
13762 12:19:57.369504 No KMS driver or no outputs, pipes: 8, outputs: 0
13763 12:19:57.369591 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13764 12:19:57.369674 <14>[ 31.956206] [IGT] kms_vblank: executing
13765 12:19:57.369761 IGT-Version: 1.2<14>[ 31.961282] [IGT] kms_vblank: exiting, ret=77
13766 12:19:57.369847 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13767 12:19:57.369934 Opened devi<8>[ 31.971811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13768 12:19:57.370021 ce: /dev/dri/card0
13769 12:19:57.370106 No KMS driver or no outputs, pipes: 8, outputs: 0
13770 12:19:57.370193 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13771 12:19:57.370276 <14>[ 31.993290] [IGT] kms_vblank: executing
13772 12:19:57.370363 IGT-Version: 1.2<14>[ 31.998027] [IGT] kms_vblank: exiting, ret=77
13773 12:19:57.370449 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13774 12:19:57.370536 Opened devi<8>[ 32.008348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13775 12:19:57.370619 ce: /dev/dri/card0
13776 12:19:57.370675 No KMS driver or no outputs, pipes: 8, outputs: 0
13777 12:19:57.370735 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13778 12:19:57.370818 <14>[ 32.030116] [IGT] kms_vblank: executing
13779 12:19:57.370910 IGT-Version: 1.2<14>[ 32.034864] [IGT] kms_vblank: exiting, ret=77
13780 12:19:57.370997 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13781 12:19:57.371087 Opened devi<8>[ 32.045577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13782 12:19:57.371170 ce: /dev/dri/card0
13783 12:19:57.371266 No KMS driver or no outputs, pipes: 8, outputs: 0
13784 12:19:57.371357 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13785 12:19:57.371485 <14>[ 32.067161] [IGT] kms_vblank: executing
13786 12:19:57.371553 IGT-Version: 1.2<14>[ 32.072101] [IGT] kms_vblank: exiting, ret=77
13787 12:19:57.371614 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13788 12:19:57.371672 Opened devi<8>[ 32.082506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13789 12:19:57.371728 ce: /dev/dri/card0
13790 12:19:57.371782 No KMS driver or no outputs, pipes: 8, outputs: 0
13791 12:19:57.371845 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13792 12:19:57.371932 <14>[ 32.104276] [IGT] kms_vblank: executing
13793 12:19:57.372017 IGT-Version: 1.2<14>[ 32.109151] [IGT] kms_vblank: exiting, ret=77
13794 12:19:57.372105 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13795 12:19:57.372193 Opened devi<8>[ 32.119425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13796 12:19:57.372276 ce: /dev/dri/card0
13797 12:19:57.372362 No KMS driver or no outputs, pipes: 8, outputs: 0
13798 12:19:57.372449 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13799 12:19:57.372534 <14>[ 32.140488] [IGT] kms_vblank: executing
13800 12:19:57.372621 IGT-Version: 1.2<14>[ 32.145228] [IGT] kms_vblank: exiting, ret=77
13801 12:19:57.372707 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13802 12:19:57.372794 Opened devi<8>[ 32.155827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13803 12:19:57.372877 ce: /dev/dri/card0
13804 12:19:57.372963 No KMS driver or no outputs, pipes: 8, outputs: 0
13805 12:19:57.373050 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13806 12:19:57.373311 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13808 12:19:57.373601 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13810 12:19:57.373896 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13812 12:19:57.374191 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13814 12:19:57.374472 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13816 12:19:57.374743 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13818 12:19:57.375031 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13820 12:19:57.375328 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13822 12:19:57.375651 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13824 12:19:57.375848 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13826 12:19:57.376050 <14>[ 32.176045] [IGT] kms_vblank: executing
13827 12:19:57.376121 IGT-Version: 1.2<14>[ 32.180893] [IGT] kms_vblank: exiting, ret=77
13828 12:19:57.376183 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13829 12:19:57.376248 Opened devi<8>[ 32.191274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13830 12:19:57.376335 ce: /dev/dri/card0
13831 12:19:57.376422 No KMS driver or no outputs, pipes: 8, outputs: 0
13832 12:19:57.376482 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13833 12:19:57.376560 <14>[ 32.212184] [IGT] kms_vblank: executing
13834 12:19:57.376646 IGT-Version: 1.2<14>[ 32.217021] [IGT] kms_vblank: exiting, ret=77
13835 12:19:57.376733 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13836 12:19:57.376828 Opened devi<8>[ 32.227261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13837 12:19:57.376917 ce: /dev/dri/card0
13838 12:19:57.377001 No KMS driver or no outputs, pipes: 8, outputs: 0
13839 12:19:57.377090 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13840 12:19:57.377177 <14>[ 32.247611] [IGT] kms_vblank: executing
13841 12:19:57.377262 IGT-Version: 1.2<14>[ 32.252319] [IGT] kms_vblank: exiting, ret=77
13842 12:19:57.377347 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13843 12:19:57.377438 Opened devi<8>[ 32.262662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13844 12:19:57.377524 ce: /dev/dri/card0
13845 12:19:57.377607 No KMS driver or no outputs, pipes: 8, outputs: 0
13846 12:19:57.377696 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13847 12:19:57.377782 <14>[ 32.284426] [IGT] kms_vblank: executing
13848 12:19:57.377867 IGT-Version: 1.2<14>[ 32.289223] [IGT] kms_vblank: exiting, ret=77
13849 12:19:57.377951 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13850 12:19:57.378041 Opened devi<8>[ 32.299515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13851 12:19:57.378128 ce: /dev/dri/card0
13852 12:19:57.378212 No KMS driver or no outputs, pipes: 8, outputs: 0
13853 12:19:57.378299 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13854 12:19:57.378386 <14>[ 32.319685] [IGT] kms_vblank: executing
13855 12:19:57.378470 IGT-Version: 1.2<14>[ 32.324396] [IGT] kms_vblank: exiting, ret=77
13856 12:19:57.378554 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13857 12:19:57.378645 Opened devi<8>[ 32.334944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13858 12:19:57.378732 ce: /dev/dri/card0
13859 12:19:57.378815 No KMS driver or no outputs, pipes: 8, outputs: 0
13860 12:19:57.378904 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13861 12:19:57.378988 <14>[ 32.356313] [IGT] kms_vblank: executing
13862 12:19:57.379073 IGT-Version: 1.2<14>[ 32.361319] [IGT] kms_vblank: exiting, ret=77
13863 12:19:57.379161 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13864 12:19:57.379251 Opened devi<8>[ 32.371711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13865 12:19:57.379334 ce: /dev/dri/card0
13866 12:19:57.379424 No KMS driver or no outputs, pipes: 8, outputs: 0
13867 12:19:57.379483 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13868 12:19:57.379538 <14>[ 32.392831] [IGT] kms_vblank: executing
13869 12:19:57.379592 IGT-Version: 1.2<14>[ 32.397552] [IGT] kms_vblank: exiting, ret=77
13870 12:19:57.379655 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13871 12:19:57.379715 Opened devi<8>[ 32.407844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13872 12:19:57.379772 ce: /dev/dri/card0
13873 12:19:57.379826 No KMS driver or no outputs, pipes: 8, outputs: 0
13874 12:19:57.379902 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13875 12:19:57.379994 <14>[ 32.432824] [IGT] kms_vblank: executing
13876 12:19:57.380084 IGT-Version: 1.2<14>[ 32.437596] [IGT] kms_vblank: exiting, ret=77
13877 12:19:57.380166 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13878 12:19:57.380249 Opened devi<8>[ 32.447875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13879 12:19:57.380338 ce: /dev/dri/card0
13880 12:19:57.380423 No KMS driver or no outputs, pipes: 8, outputs: 0
13881 12:19:57.380512 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13882 12:19:57.380598 <14>[ 32.468059] [IGT] kms_vblank: executing
13883 12:19:57.380683 IGT-Version: 1.2<14>[ 32.472976] [IGT] kms_vblank: exiting, ret=77
13884 12:19:57.380767 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13885 12:19:57.380869 Opened devi<8>[ 32.483437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13886 12:19:57.380969 ce: /dev/dri/card0
13887 12:19:57.381059 No KMS driver or no outputs, pipes: 8, outputs: 0
13888 12:19:57.381148 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13889 12:19:57.381233 <14>[ 32.504136] [IGT] kms_vblank: executing
13890 12:19:57.381318 IGT-Version: 1.2<14>[ 32.509024] [IGT] kms_vblank: exiting, ret=77
13891 12:19:57.381405 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13892 12:19:57.381495 Opened devi<8>[ 32.519383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13893 12:19:57.381581 ce: /dev/dri/card0
13894 12:19:57.381667 No KMS driver or no outputs, pipes: 8, outputs: 0
13895 12:19:57.381754 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13896 12:19:57.381838 <14>[ 32.539492] [IGT] kms_vblank: executing
13897 12:19:57.381922 IGT-Version: 1.2<14>[ 32.544222] [IGT] kms_vblank: exiting, ret=77
13898 12:19:57.382187 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13900 12:19:57.382476 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13902 12:19:57.382767 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13904 12:19:57.383057 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13906 12:19:57.383352 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13908 12:19:57.383685 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13910 12:19:57.383975 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13912 12:19:57.384262 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13914 12:19:57.384552 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13916 12:19:57.384839 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13918 12:19:57.385155 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13919 12:19:57.385255 Opened devi<8>[ 32.554584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13920 12:19:57.385353 ce: /dev/dri/card0
13921 12:19:57.385444 No KMS driver or no outputs, pipes: 8, outputs: 0
13922 12:19:57.385535 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13923 12:19:57.385611 <14>[ 32.575622] [IGT] kms_vblank: executing
13924 12:19:57.385670 IGT-Version: 1.2<14>[ 32.580359] [IGT] kms_vblank: exiting, ret=77
13925 12:19:57.385730 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13926 12:19:57.385791 Opened devi<8>[ 32.590729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13927 12:19:57.385851 ce: /dev/dri/card0
13928 12:19:57.385907 No KMS driver or no outputs, pipes: 8, outputs: 0
13929 12:19:57.385963 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13930 12:19:57.386018 <14>[ 32.611160] [IGT] kms_vblank: executing
13931 12:19:57.386078 IGT-Version: 1.2<14>[ 32.615917] [IGT] kms_vblank: exiting, ret=77
13932 12:19:57.386138 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13933 12:19:57.386205 Opened devi<8>[ 32.626222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13934 12:19:57.386289 ce: /dev/dri/card0
13935 12:19:57.386376 No KMS driver or no outputs, pipes: 8, outputs: 0
13936 12:19:57.386464 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13937 12:19:57.386548 <14>[ 32.646989] [IGT] kms_vblank: executing
13938 12:19:57.386633 IGT-Version: 1.2<14>[ 32.651719] [IGT] kms_vblank: exiting, ret=77
13939 12:19:57.386691 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13940 12:19:57.386753 Opened devi<8>[ 32.661908] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13941 12:19:57.386812 ce: /dev/dri/card0
13942 12:19:57.386866 No KMS driver or no outputs, pipes: 8, outputs: 0
13943 12:19:57.386921 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13944 12:19:57.387007 <14>[ 32.694053] [IGT] kms_vblank: executing
13945 12:19:57.387094 IGT-Version: 1.2<14>[ 32.699183] [IGT] kms_vblank: exiting, ret=77
13946 12:19:57.387178 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13947 12:19:57.387269 Opened device: /dev/dri/car<8>[ 32.710219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13948 12:19:57.387356 d0
13949 12:19:57.387455 No KMS driver or no outputs, pipes: 8, outputs: 0
13950 12:19:57.387540 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13951 12:19:57.387600 <14>[ 32.732173] [IGT] kms_vblank: executing
13952 12:19:57.387656 IGT-Version: 1.2<14>[ 32.737064] [IGT] kms_vblank: exiting, ret=77
13953 12:19:57.387711 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13954 12:19:57.387767 Opened devi<8>[ 32.747227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13955 12:19:57.387828 ce: /dev/dri/card0
13956 12:19:57.387883 No KMS driver or no outputs, pipes: 8, outputs: 0
13957 12:19:57.387942 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13958 12:19:57.388001 <14>[ 32.768403] [IGT] kms_vblank: executing
13959 12:19:57.388055 IGT-Version: 1.2<14>[ 32.773170] [IGT] kms_vblank: exiting, ret=77
13960 12:19:57.388114 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13961 12:19:57.388170 Opened devi<8>[ 32.783465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13962 12:19:57.388230 ce: /dev/dri/card0
13963 12:19:57.388283 No KMS driver or no outputs, pipes: 8, outputs: 0
13964 12:19:57.388338 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13965 12:19:57.388391 <14>[ 32.805241] [IGT] kms_vblank: executing
13966 12:19:57.388452 IGT-Version: 1.2<14>[ 32.809967] [IGT] kms_vblank: exiting, ret=77
13967 12:19:57.388512 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13968 12:19:57.388602 Opened devi<8>[ 32.820227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13969 12:19:57.388686 ce: /dev/dri/card0
13970 12:19:57.388772 No KMS driver or no outputs, pipes: 8, outputs: 0
13971 12:19:57.388859 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13972 12:19:57.388943 <14>[ 32.842180] [IGT] kms_vblank: executing
13973 12:19:57.389026 IGT-Version: 1.2<14>[ 32.846927] [IGT] kms_vblank: exiting, ret=77
13974 12:19:57.389087 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13975 12:19:57.389154 Opened devi<8>[ 32.857331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13976 12:19:57.389243 ce: /dev/dri/card0
13977 12:19:57.389332 No KMS driver or no outputs, pipes: 8, outputs: 0
13978 12:19:57.389420 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13979 12:19:57.389503 <14>[ 32.879101] [IGT] kms_vblank: executing
13980 12:19:57.389600 IGT-Version: 1.2<14>[ 32.884129] [IGT] kms_vblank: exiting, ret=77
13981 12:19:57.389688 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
13982 12:19:57.389779 Opened devi<8>[ 32.894649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13983 12:19:57.389865 ce: /dev/dri/card0
13984 12:19:57.389952 No KMS driver or no outputs, pipes: 8, outputs: 0
13985 12:19:57.390038 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13986 12:19:57.390121 <14>[ 32.916709] [IGT] kms_vblank: executing
13987 12:19:57.390208 IGT-Version: 1.2<14>[ 32.921460] [IGT] kms_vblank: exiting, ret=77
13988 12:19:57.390476 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13990 12:19:57.390765 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13992 12:19:57.391061 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13994 12:19:57.391351 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13996 12:19:57.391564 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13998 12:19:57.391763 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
14000 12:19:57.391955 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
14002 12:19:57.392213 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
14004 12:19:57.392480 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
14006 12:19:57.392770 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
14008 12:19:57.393065 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
14009 12:19:57.393166 Opened devi<8>[ 32.931918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
14010 12:19:57.393257 ce: /dev/dri/card0
14011 12:19:57.393344 No KMS driver or no outputs, pipes: 8, outputs: 0
14012 12:19:57.393435 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
14013 12:19:57.393522 <14>[ 32.953391] [IGT] kms_vblank: executing
14014 12:19:57.393608 IGT-Version: 1.2<14>[ 32.958123] [IGT] kms_vblank: exiting, ret=77
14015 12:19:57.393697 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
14016 12:19:57.393789 Opened devi<8>[ 32.968569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
14017 12:19:57.393875 ce: /dev/dri/card0
14018 12:19:57.393967 No KMS driver or no outputs, pipes: 8, outputs: 0
14019 12:19:57.394059 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
14020 12:19:57.394149 <14>[ 32.990325] [IGT] kms_vblank: executing
14021 12:19:57.394233 IGT-Version: 1.2<14>[ 32.995329] [IGT] kms_vblank: exiting, ret=77
14022 12:19:57.394325 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip7 aarch64)
14023 12:19:57.394419 Opened devi<8>[ 33.005709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
14024 12:19:57.394506 ce: /dev/dri/card0
14025 12:19:57.394595 No KMS drive<8>[ 33.016933] <LAVA_SIGNAL_TESTSET STOP>
14026 12:19:57.394654 r or no outputs,<8>[ 33.023654] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 11893121_1.5.2.3.1>
14027 12:19:57.394711 pipes: 8, outputs: 0
14028 12:19:57.394766 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
14029 12:19:57.394839 + set +x
14030 12:19:57.394922 <LAVA_TEST_RUNNER EXIT>
14031 12:19:57.395205 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
14033 12:19:57.395571 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
14035 12:19:57.395886 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
14037 12:19:57.396176 Received signal: <TESTSET> STOP
14038 12:19:57.396268 Closing test_set kms_vblank
14039 12:19:57.396386 Received signal: <ENDRUN> 0_igt-kms-mediatek 11893121_1.5.2.3.1
14040 12:19:57.396485 Ending use of test pattern.
14041 12:19:57.396572 Ending test lava.0_igt-kms-mediatek (11893121_1.5.2.3.1), duration 15.77
14043 12:19:57.397049 ok: lava_test_shell seems to have completed
14044 12:19:57.404862 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
14045 12:19:57.405137 end: 3.1 lava-test-shell (duration 00:00:16) [common]
14046 12:19:57.405260 end: 3 lava-test-retry (duration 00:00:16) [common]
14047 12:19:57.405380 start: 4 finalize (timeout 00:06:56) [common]
14048 12:19:57.405503 start: 4.1 power-off (timeout 00:00:30) [common]
14049 12:19:57.405784 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
14050 12:19:57.482868 >> Command sent successfully.
14051 12:19:57.489719 Returned 0 in 0 seconds
14052 12:19:57.590737 end: 4.1 power-off (duration 00:00:00) [common]
14054 12:19:57.592404 start: 4.2 read-feedback (timeout 00:06:56) [common]
14055 12:19:57.593919 Listened to connection for namespace 'common' for up to 1s
14056 12:19:58.594262 Finalising connection for namespace 'common'
14057 12:19:58.594439 Disconnecting from shell: Finalise
14058 12:19:58.594521 / #
14059 12:19:58.694852 end: 4.2 read-feedback (duration 00:00:01) [common]
14060 12:19:58.695003 end: 4 finalize (duration 00:00:01) [common]
14061 12:19:58.695122 Cleaning after the job
14062 12:19:58.695224 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/ramdisk
14063 12:19:58.703265 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/kernel
14064 12:19:58.712123 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/dtb
14065 12:19:58.712309 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893121/tftp-deploy-10zv6gap/modules
14066 12:19:58.719805 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893121
14067 12:19:58.838665 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893121
14068 12:19:58.838839 Job finished correctly