Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 38
- Errors: 0
- Boot result: PASS
1 12:19:40.809687 lava-dispatcher, installed at version: 2023.08
2 12:19:40.809892 start: 0 validate
3 12:19:40.810020 Start time: 2023-10-27 12:19:40.810012+00:00 (UTC)
4 12:19:40.810134 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:19:40.810266 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:19:41.099110 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:19:41.099848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:19:41.371096 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:19:41.371926 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:19:41.642487 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:19:41.643230 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:19:41.913023 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:19:41.913812 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:19:42.190947 validate duration: 1.38
16 12:19:42.192240 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:19:42.192783 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:19:42.193287 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:19:42.193898 Not decompressing ramdisk as can be used compressed.
20 12:19:42.194379 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:19:42.194737 saving as /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/ramdisk/initrd.cpio.gz
22 12:19:42.195107 total size: 5625687 (5 MB)
23 12:19:42.200400 progress 0 % (0 MB)
24 12:19:42.210265 progress 5 % (0 MB)
25 12:19:42.218173 progress 10 % (0 MB)
26 12:19:42.222932 progress 15 % (0 MB)
27 12:19:42.227211 progress 20 % (1 MB)
28 12:19:42.230584 progress 25 % (1 MB)
29 12:19:42.233634 progress 30 % (1 MB)
30 12:19:42.236595 progress 35 % (1 MB)
31 12:19:42.238881 progress 40 % (2 MB)
32 12:19:42.241367 progress 45 % (2 MB)
33 12:19:42.243353 progress 50 % (2 MB)
34 12:19:42.245580 progress 55 % (2 MB)
35 12:19:42.247570 progress 60 % (3 MB)
36 12:19:42.249339 progress 65 % (3 MB)
37 12:19:42.251282 progress 70 % (3 MB)
38 12:19:42.252879 progress 75 % (4 MB)
39 12:19:42.254743 progress 80 % (4 MB)
40 12:19:42.256371 progress 85 % (4 MB)
41 12:19:42.257996 progress 90 % (4 MB)
42 12:19:42.259613 progress 95 % (5 MB)
43 12:19:42.261067 progress 100 % (5 MB)
44 12:19:42.261259 5 MB downloaded in 0.07 s (81.06 MB/s)
45 12:19:42.261402 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:19:42.261632 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:19:42.261716 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:19:42.261796 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:19:42.261925 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:19:42.261994 saving as /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/kernel/Image
52 12:19:42.262054 total size: 49236480 (46 MB)
53 12:19:42.262113 No compression specified
54 12:19:42.263199 progress 0 % (0 MB)
55 12:19:42.275660 progress 5 % (2 MB)
56 12:19:42.288522 progress 10 % (4 MB)
57 12:19:42.301135 progress 15 % (7 MB)
58 12:19:42.313704 progress 20 % (9 MB)
59 12:19:42.326355 progress 25 % (11 MB)
60 12:19:42.338751 progress 30 % (14 MB)
61 12:19:42.351258 progress 35 % (16 MB)
62 12:19:42.364026 progress 40 % (18 MB)
63 12:19:42.376435 progress 45 % (21 MB)
64 12:19:42.389139 progress 50 % (23 MB)
65 12:19:42.401767 progress 55 % (25 MB)
66 12:19:42.414464 progress 60 % (28 MB)
67 12:19:42.427160 progress 65 % (30 MB)
68 12:19:42.439730 progress 70 % (32 MB)
69 12:19:42.452285 progress 75 % (35 MB)
70 12:19:42.465033 progress 80 % (37 MB)
71 12:19:42.477617 progress 85 % (39 MB)
72 12:19:42.490379 progress 90 % (42 MB)
73 12:19:42.502933 progress 95 % (44 MB)
74 12:19:42.515367 progress 100 % (46 MB)
75 12:19:42.515554 46 MB downloaded in 0.25 s (185.23 MB/s)
76 12:19:42.515698 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:19:42.515922 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:19:42.516007 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:19:42.516089 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:19:42.516297 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:19:42.516366 saving as /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/dtb/mt8192-asurada-spherion-r0.dtb
83 12:19:42.516427 total size: 47278 (0 MB)
84 12:19:42.516487 No compression specified
85 12:19:42.517611 progress 69 % (0 MB)
86 12:19:42.517880 progress 100 % (0 MB)
87 12:19:42.518031 0 MB downloaded in 0.00 s (28.14 MB/s)
88 12:19:42.518148 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:19:42.518364 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:19:42.518446 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:19:42.518525 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:19:42.518634 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:19:42.518702 saving as /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/nfsrootfs/full.rootfs.tar
95 12:19:42.518761 total size: 195204440 (186 MB)
96 12:19:42.518820 Using unxz to decompress xz
97 12:19:42.522857 progress 0 % (0 MB)
98 12:19:43.076186 progress 5 % (9 MB)
99 12:19:43.578205 progress 10 % (18 MB)
100 12:19:44.175337 progress 15 % (27 MB)
101 12:19:44.464039 progress 20 % (37 MB)
102 12:19:44.917313 progress 25 % (46 MB)
103 12:19:45.476553 progress 30 % (55 MB)
104 12:19:46.015834 progress 35 % (65 MB)
105 12:19:46.560217 progress 40 % (74 MB)
106 12:19:47.118267 progress 45 % (83 MB)
107 12:19:47.719661 progress 50 % (93 MB)
108 12:19:48.306058 progress 55 % (102 MB)
109 12:19:48.944435 progress 60 % (111 MB)
110 12:19:49.317811 progress 65 % (121 MB)
111 12:19:49.397643 progress 70 % (130 MB)
112 12:19:49.536508 progress 75 % (139 MB)
113 12:19:49.616386 progress 80 % (148 MB)
114 12:19:49.661298 progress 85 % (158 MB)
115 12:19:49.750837 progress 90 % (167 MB)
116 12:19:50.118996 progress 95 % (176 MB)
117 12:19:50.690072 progress 100 % (186 MB)
118 12:19:50.695105 186 MB downloaded in 8.18 s (22.77 MB/s)
119 12:19:50.695406 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:19:50.695803 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:19:50.695921 start: 1.5 download-retry (timeout 00:09:51) [common]
123 12:19:50.696036 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 12:19:50.696232 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:19:50.696329 saving as /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/modules/modules.tar
126 12:19:50.696418 total size: 8625084 (8 MB)
127 12:19:50.696509 Using unxz to decompress xz
128 12:19:50.701004 progress 0 % (0 MB)
129 12:19:50.722286 progress 5 % (0 MB)
130 12:19:50.743892 progress 10 % (0 MB)
131 12:19:50.768945 progress 15 % (1 MB)
132 12:19:50.793628 progress 20 % (1 MB)
133 12:19:50.818828 progress 25 % (2 MB)
134 12:19:50.844371 progress 30 % (2 MB)
135 12:19:50.870113 progress 35 % (2 MB)
136 12:19:50.894105 progress 40 % (3 MB)
137 12:19:50.917944 progress 45 % (3 MB)
138 12:19:50.943686 progress 50 % (4 MB)
139 12:19:50.967805 progress 55 % (4 MB)
140 12:19:50.991569 progress 60 % (4 MB)
141 12:19:51.015525 progress 65 % (5 MB)
142 12:19:51.040224 progress 70 % (5 MB)
143 12:19:51.063385 progress 75 % (6 MB)
144 12:19:51.088624 progress 80 % (6 MB)
145 12:19:51.117493 progress 85 % (7 MB)
146 12:19:51.143977 progress 90 % (7 MB)
147 12:19:51.169321 progress 95 % (7 MB)
148 12:19:51.191774 progress 100 % (8 MB)
149 12:19:51.196632 8 MB downloaded in 0.50 s (16.44 MB/s)
150 12:19:51.196872 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:19:51.197132 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:19:51.197251 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:19:51.197370 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:19:54.795299 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11893132/extract-nfsrootfs-up4tc3au
156 12:19:54.795504 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:19:54.795605 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:19:54.795774 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6
159 12:19:54.795907 makedir: /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin
160 12:19:54.796010 makedir: /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/tests
161 12:19:54.796110 makedir: /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/results
162 12:19:54.796216 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-add-keys
163 12:19:54.796364 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-add-sources
164 12:19:54.796496 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-background-process-start
165 12:19:54.796625 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-background-process-stop
166 12:19:54.796755 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-common-functions
167 12:19:54.796882 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-echo-ipv4
168 12:19:54.797008 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-install-packages
169 12:19:54.797133 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-installed-packages
170 12:19:54.797259 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-os-build
171 12:19:54.797385 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-probe-channel
172 12:19:54.797509 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-probe-ip
173 12:19:54.797634 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-target-ip
174 12:19:54.797759 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-target-mac
175 12:19:54.797888 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-target-storage
176 12:19:54.798016 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-test-case
177 12:19:54.798146 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-test-event
178 12:19:54.798367 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-test-feedback
179 12:19:54.798517 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-test-raise
180 12:19:54.798664 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-test-reference
181 12:19:54.798809 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-test-runner
182 12:19:54.798956 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-test-set
183 12:19:54.799103 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-test-shell
184 12:19:54.799255 Updating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-add-keys (debian)
185 12:19:54.799454 Updating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-add-sources (debian)
186 12:19:54.799651 Updating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-install-packages (debian)
187 12:19:54.799839 Updating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-installed-packages (debian)
188 12:19:54.800007 Updating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/bin/lava-os-build (debian)
189 12:19:54.800184 Creating /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/environment
190 12:19:54.800349 LAVA metadata
191 12:19:54.800477 - LAVA_JOB_ID=11893132
192 12:19:54.800557 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:19:54.800685 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:19:54.800760 skipped lava-vland-overlay
195 12:19:54.800860 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:19:54.800983 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:19:54.801076 skipped lava-multinode-overlay
198 12:19:54.801194 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:19:54.801315 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:19:54.801425 Loading test definitions
201 12:19:54.801540 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:19:54.801648 Using /lava-11893132 at stage 0
203 12:19:54.802018 uuid=11893132_1.6.2.3.1 testdef=None
204 12:19:54.802141 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:19:54.802267 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:19:54.802889 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:19:54.803252 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:19:54.803830 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:19:54.804195 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:19:54.804759 runner path: /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/0/tests/0_timesync-off test_uuid 11893132_1.6.2.3.1
213 12:19:54.804934 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:19:54.805190 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:19:54.805272 Using /lava-11893132 at stage 0
217 12:19:54.805400 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:19:54.805513 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/0/tests/1_kselftest-alsa'
219 12:19:58.014335 Running '/usr/bin/git checkout kernelci.org
220 12:19:58.026087 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 12:19:58.026803 uuid=11893132_1.6.2.3.5 testdef=None
222 12:19:58.026961 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 12:19:58.027201 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 12:19:58.027968 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:19:58.028235 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 12:19:58.029195 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:19:58.029419 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 12:19:58.030317 runner path: /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/0/tests/1_kselftest-alsa test_uuid 11893132_1.6.2.3.5
232 12:19:58.030408 BOARD='mt8192-asurada-spherion-r0'
233 12:19:58.030469 BRANCH='cip-gitlab'
234 12:19:58.030527 SKIPFILE='/dev/null'
235 12:19:58.030582 SKIP_INSTALL='True'
236 12:19:58.030636 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:19:58.030690 TST_CASENAME=''
238 12:19:58.030743 TST_CMDFILES='alsa'
239 12:19:58.030879 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:19:58.031077 Creating lava-test-runner.conf files
242 12:19:58.031138 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893132/lava-overlay-q176l1l6/lava-11893132/0 for stage 0
243 12:19:58.031227 - 0_timesync-off
244 12:19:58.031296 - 1_kselftest-alsa
245 12:19:58.031389 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 12:19:58.031476 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 12:20:05.382341 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 12:20:05.382526 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 12:20:05.382616 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:20:05.382713 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 12:20:05.382802 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 12:20:05.552101 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:20:05.552550 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 12:20:05.552666 extracting modules file /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893132/extract-nfsrootfs-up4tc3au
255 12:20:05.771493 extracting modules file /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893132/extract-overlay-ramdisk-q0zc7ea8/ramdisk
256 12:20:05.994813 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:20:05.994986 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 12:20:05.995075 [common] Applying overlay to NFS
259 12:20:05.995142 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893132/compress-overlay-30952p7b/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893132/extract-nfsrootfs-up4tc3au
260 12:20:06.895214 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:20:06.895381 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 12:20:06.895474 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:20:06.895561 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 12:20:06.895644 Building ramdisk /var/lib/lava/dispatcher/tmp/11893132/extract-overlay-ramdisk-q0zc7ea8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893132/extract-overlay-ramdisk-q0zc7ea8/ramdisk
265 12:20:07.261682 >> 130492 blocks
266 12:20:09.249497 rename /var/lib/lava/dispatcher/tmp/11893132/extract-overlay-ramdisk-q0zc7ea8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/ramdisk/ramdisk.cpio.gz
267 12:20:09.249956 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:20:09.250074 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 12:20:09.250176 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 12:20:09.250282 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/kernel/Image'
271 12:20:21.122769 Returned 0 in 11 seconds
272 12:20:21.223433 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/kernel/image.itb
273 12:20:21.586208 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:20:21.586585 output: Created: Fri Oct 27 13:20:21 2023
275 12:20:21.586658 output: Image 0 (kernel-1)
276 12:20:21.586720 output: Description:
277 12:20:21.586785 output: Created: Fri Oct 27 13:20:21 2023
278 12:20:21.586845 output: Type: Kernel Image
279 12:20:21.586904 output: Compression: lzma compressed
280 12:20:21.586962 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
281 12:20:21.587021 output: Architecture: AArch64
282 12:20:21.587078 output: OS: Linux
283 12:20:21.587132 output: Load Address: 0x00000000
284 12:20:21.587186 output: Entry Point: 0x00000000
285 12:20:21.587240 output: Hash algo: crc32
286 12:20:21.587295 output: Hash value: d33b93ae
287 12:20:21.587395 output: Image 1 (fdt-1)
288 12:20:21.587475 output: Description: mt8192-asurada-spherion-r0
289 12:20:21.587566 output: Created: Fri Oct 27 13:20:21 2023
290 12:20:21.587616 output: Type: Flat Device Tree
291 12:20:21.587666 output: Compression: uncompressed
292 12:20:21.587717 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:20:21.587768 output: Architecture: AArch64
294 12:20:21.587819 output: Hash algo: crc32
295 12:20:21.587868 output: Hash value: cc4352de
296 12:20:21.587919 output: Image 2 (ramdisk-1)
297 12:20:21.587969 output: Description: unavailable
298 12:20:21.588019 output: Created: Fri Oct 27 13:20:21 2023
299 12:20:21.588070 output: Type: RAMDisk Image
300 12:20:21.588120 output: Compression: Unknown Compression
301 12:20:21.588170 output: Data Size: 18751442 Bytes = 18311.96 KiB = 17.88 MiB
302 12:20:21.588259 output: Architecture: AArch64
303 12:20:21.588309 output: OS: Linux
304 12:20:21.588359 output: Load Address: unavailable
305 12:20:21.588409 output: Entry Point: unavailable
306 12:20:21.588459 output: Hash algo: crc32
307 12:20:21.588508 output: Hash value: ea469179
308 12:20:21.588558 output: Default Configuration: 'conf-1'
309 12:20:21.588608 output: Configuration 0 (conf-1)
310 12:20:21.588657 output: Description: mt8192-asurada-spherion-r0
311 12:20:21.588707 output: Kernel: kernel-1
312 12:20:21.588757 output: Init Ramdisk: ramdisk-1
313 12:20:21.588807 output: FDT: fdt-1
314 12:20:21.588857 output: Loadables: kernel-1
315 12:20:21.588907 output:
316 12:20:21.589107 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 12:20:21.589206 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 12:20:21.589304 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 12:20:21.589396 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 12:20:21.589470 No LXC device requested
321 12:20:21.589544 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:20:21.589624 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 12:20:21.589699 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:20:21.589765 Checking files for TFTP limit of 4294967296 bytes.
325 12:20:21.590266 end: 1 tftp-deploy (duration 00:00:39) [common]
326 12:20:21.590371 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:20:21.590461 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:20:21.590583 substitutions:
329 12:20:21.590650 - {DTB}: 11893132/tftp-deploy-l4a7eacn/dtb/mt8192-asurada-spherion-r0.dtb
330 12:20:21.590714 - {INITRD}: 11893132/tftp-deploy-l4a7eacn/ramdisk/ramdisk.cpio.gz
331 12:20:21.590772 - {KERNEL}: 11893132/tftp-deploy-l4a7eacn/kernel/Image
332 12:20:21.590827 - {LAVA_MAC}: None
333 12:20:21.590881 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11893132/extract-nfsrootfs-up4tc3au
334 12:20:21.590935 - {NFS_SERVER_IP}: 192.168.201.1
335 12:20:21.590987 - {PRESEED_CONFIG}: None
336 12:20:21.591040 - {PRESEED_LOCAL}: None
337 12:20:21.591092 - {RAMDISK}: 11893132/tftp-deploy-l4a7eacn/ramdisk/ramdisk.cpio.gz
338 12:20:21.591144 - {ROOT_PART}: None
339 12:20:21.591197 - {ROOT}: None
340 12:20:21.591249 - {SERVER_IP}: 192.168.201.1
341 12:20:21.591301 - {TEE}: None
342 12:20:21.591353 Parsed boot commands:
343 12:20:21.591404 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:20:21.591582 Parsed boot commands: tftpboot 192.168.201.1 11893132/tftp-deploy-l4a7eacn/kernel/image.itb 11893132/tftp-deploy-l4a7eacn/kernel/cmdline
345 12:20:21.591667 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:20:21.591747 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:20:21.591833 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:20:21.591919 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:20:21.591991 Not connected, no need to disconnect.
350 12:20:21.592062 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:20:21.592139 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:20:21.592229 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 12:20:21.596440 Setting prompt string to ['lava-test: # ']
354 12:20:21.596795 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:20:21.596903 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:20:21.597002 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:20:21.597134 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:20:21.597368 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 12:20:26.733427 >> Command sent successfully.
360 12:20:26.735861 Returned 0 in 5 seconds
361 12:20:26.836296 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:20:26.836630 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:20:26.836733 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:20:26.836821 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:20:26.836887 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:20:26.836957 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:20:26.837220 [Enter `^Ec?' for help]
369 12:20:27.015283
370 12:20:27.015436
371 12:20:27.015508 F0: 102B 0000
372 12:20:27.015574
373 12:20:27.015634 F3: 1001 0000 [0200]
374 12:20:27.015694
375 12:20:27.018462 F3: 1001 0000
376 12:20:27.018546
377 12:20:27.018612 F7: 102D 0000
378 12:20:27.018673
379 12:20:27.021791 F1: 0000 0000
380 12:20:27.021873
381 12:20:27.021939 V0: 0000 0000 [0001]
382 12:20:27.022004
383 12:20:27.025128 00: 0007 8000
384 12:20:27.025215
385 12:20:27.025282 01: 0000 0000
386 12:20:27.025344
387 12:20:27.025403 BP: 0C00 0209 [0000]
388 12:20:27.028389
389 12:20:27.028472 G0: 1182 0000
390 12:20:27.028538
391 12:20:27.028599 EC: 0000 0021 [4000]
392 12:20:27.032094
393 12:20:27.032184 S7: 0000 0000 [0000]
394 12:20:27.032252
395 12:20:27.032314 CC: 0000 0000 [0001]
396 12:20:27.035527
397 12:20:27.035609 T0: 0000 0040 [010F]
398 12:20:27.035675
399 12:20:27.035736 Jump to BL
400 12:20:27.035795
401 12:20:27.062009
402 12:20:27.062136
403 12:20:27.062230
404 12:20:27.068856 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:20:27.072624 ARM64: Exception handlers installed.
406 12:20:27.076532 ARM64: Testing exception
407 12:20:27.079553 ARM64: Done test exception
408 12:20:27.086006 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:20:27.096078 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:20:27.102902 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:20:27.112901 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:20:27.119768 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:20:27.129599 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:20:27.140111 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:20:27.146871 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:20:27.164547 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:20:27.168154 WDT: Last reset was cold boot
418 12:20:27.171427 SPI1(PAD0) initialized at 2873684 Hz
419 12:20:27.174650 SPI5(PAD0) initialized at 992727 Hz
420 12:20:27.177940 VBOOT: Loading verstage.
421 12:20:27.184746 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:20:27.188089 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:20:27.191375 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:20:27.195016 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:20:27.202267 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:20:27.208798 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:20:27.219553 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:20:27.219679
429 12:20:27.219791
430 12:20:27.229596 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:20:27.233541 ARM64: Exception handlers installed.
432 12:20:27.236517 ARM64: Testing exception
433 12:20:27.236641 ARM64: Done test exception
434 12:20:27.243295 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:20:27.246247 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:20:27.260811 Probing TPM: . done!
437 12:20:27.260965 TPM ready after 0 ms
438 12:20:27.267707 Connected to device vid:did:rid of 1ae0:0028:00
439 12:20:27.275138 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 12:20:27.322842 Initialized TPM device CR50 revision 0
441 12:20:27.336091 tlcl_send_startup: Startup return code is 0
442 12:20:27.336252 TPM: setup succeeded
443 12:20:27.352189 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:20:27.359621 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:20:27.368580 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:20:27.377555 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:20:27.380877 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:20:27.384082 in-header: 03 07 00 00 08 00 00 00
449 12:20:27.387462 in-data: aa e4 47 04 13 02 00 00
450 12:20:27.390863 Chrome EC: UHEPI supported
451 12:20:27.397923 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:20:27.401189 in-header: 03 95 00 00 08 00 00 00
453 12:20:27.404750 in-data: 18 20 20 08 00 00 00 00
454 12:20:27.404904 Phase 1
455 12:20:27.408469 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:20:27.415967 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:20:27.419429 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:20:27.422845 Recovery requested (1009000e)
459 12:20:27.432157 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:20:27.438029 tlcl_extend: response is 0
461 12:20:27.447070 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:20:27.452421 tlcl_extend: response is 0
463 12:20:27.458973 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:20:27.479996 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 12:20:27.487402 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:20:27.487553
467 12:20:27.487625
468 12:20:27.494982 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:20:27.498396 ARM64: Exception handlers installed.
470 12:20:27.502024 ARM64: Testing exception
471 12:20:27.505368 ARM64: Done test exception
472 12:20:27.525098 pmic_efuse_setting: Set efuses in 11 msecs
473 12:20:27.528357 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:20:27.535332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:20:27.538359 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:20:27.545260 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:20:27.548493 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:20:27.555385 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:20:27.558292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:20:27.564937 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:20:27.568296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:20:27.571558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:20:27.578171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:20:27.581407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:20:27.588069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:20:27.591395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:20:27.598241 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:20:27.602003 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:20:27.609560 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:20:27.612748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:20:27.620151 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:20:27.627433 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:20:27.631225 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:20:27.638689 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:20:27.642603 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:20:27.650435 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:20:27.653479 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:20:27.657316 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:20:27.664775 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:20:27.668467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:20:27.676036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:20:27.679875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:20:27.683758 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:20:27.690917 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:20:27.694878 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:20:27.698182 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:20:27.705689 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:20:27.709063 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:20:27.712670 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:20:27.720129 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:20:27.723694 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:20:27.727403 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:20:27.734595 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:20:27.738585 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:20:27.741975 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:20:27.745857 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:20:27.749164 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:20:27.756707 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:20:27.760417 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:20:27.763914 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:20:27.767417 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:20:27.770939 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:20:27.774627 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:20:27.781945 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:20:27.789596 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:20:27.796526 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:20:27.800201 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:20:27.811394 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:20:27.818417 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:20:27.822059 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:20:27.825795 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:20:27.829385 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:20:27.838491 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 12:20:27.841949 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:20:27.850203 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 12:20:27.853433 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:20:27.862452 [RTC]rtc_get_frequency_meter,154: input=15, output=765
538 12:20:27.871886 [RTC]rtc_get_frequency_meter,154: input=23, output=948
539 12:20:27.881524 [RTC]rtc_get_frequency_meter,154: input=19, output=856
540 12:20:27.891355 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 12:20:27.900626 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 12:20:27.909762 [RTC]rtc_get_frequency_meter,154: input=16, output=788
543 12:20:27.920151 [RTC]rtc_get_frequency_meter,154: input=17, output=810
544 12:20:27.923691 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 12:20:27.927483 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 12:20:27.931102 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:20:27.938657 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:20:27.942255 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:20:27.946093 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:20:27.949604 ADC[4]: Raw value=670063 ID=5
551 12:20:27.949708 ADC[3]: Raw value=212917 ID=1
552 12:20:27.953471 RAM Code: 0x51
553 12:20:27.956671 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:20:27.960542 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:20:27.971191 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 12:20:27.975119 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 12:20:27.978886 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:20:27.982330 in-header: 03 07 00 00 08 00 00 00
559 12:20:27.985904 in-data: aa e4 47 04 13 02 00 00
560 12:20:27.989540 Chrome EC: UHEPI supported
561 12:20:27.997200 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:20:28.000346 in-header: 03 95 00 00 08 00 00 00
563 12:20:28.004069 in-data: 18 20 20 08 00 00 00 00
564 12:20:28.007735 MRC: failed to locate region type 0.
565 12:20:28.014638 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:20:28.014725 DRAM-K: Running full calibration
567 12:20:28.021841 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 12:20:28.021931 header.status = 0x0
569 12:20:28.025935 header.version = 0x6 (expected: 0x6)
570 12:20:28.029377 header.size = 0xd00 (expected: 0xd00)
571 12:20:28.033113 header.flags = 0x0
572 12:20:28.039588 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:20:28.056525 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:20:28.063556 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:20:28.067402 dram_init: ddr_geometry: 0
576 12:20:28.067488 [EMI] MDL number = 0
577 12:20:28.071152 [EMI] Get MDL freq = 0
578 12:20:28.071237 dram_init: ddr_type: 0
579 12:20:28.075071 is_discrete_lpddr4: 1
580 12:20:28.078445 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:20:28.078529
582 12:20:28.078596
583 12:20:28.078657 [Bian_co] ETT version 0.0.0.1
584 12:20:28.085834 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 12:20:28.085960
586 12:20:28.089462 dramc_set_vcore_voltage set vcore to 650000
587 12:20:28.089546 Read voltage for 800, 4
588 12:20:28.093285 Vio18 = 0
589 12:20:28.093368 Vcore = 650000
590 12:20:28.093435 Vdram = 0
591 12:20:28.093496 Vddq = 0
592 12:20:28.096789 Vmddr = 0
593 12:20:28.096872 dram_init: config_dvfs: 1
594 12:20:28.104251 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:20:28.108032 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:20:28.111755 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 12:20:28.115234 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 12:20:28.118981 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 12:20:28.122636 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 12:20:28.126273 MEM_TYPE=3, freq_sel=18
601 12:20:28.130190 sv_algorithm_assistance_LP4_1600
602 12:20:28.133787 ============ PULL DRAM RESETB DOWN ============
603 12:20:28.137273 ========== PULL DRAM RESETB DOWN end =========
604 12:20:28.140454 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:20:28.144099 ===================================
606 12:20:28.147855 LPDDR4 DRAM CONFIGURATION
607 12:20:28.151560 ===================================
608 12:20:28.151686 EX_ROW_EN[0] = 0x0
609 12:20:28.155212 EX_ROW_EN[1] = 0x0
610 12:20:28.155295 LP4Y_EN = 0x0
611 12:20:28.158620 WORK_FSP = 0x0
612 12:20:28.158703 WL = 0x2
613 12:20:28.162254 RL = 0x2
614 12:20:28.162336 BL = 0x2
615 12:20:28.166071 RPST = 0x0
616 12:20:28.166154 RD_PRE = 0x0
617 12:20:28.170199 WR_PRE = 0x1
618 12:20:28.170282 WR_PST = 0x0
619 12:20:28.173578 DBI_WR = 0x0
620 12:20:28.173660 DBI_RD = 0x0
621 12:20:28.177395 OTF = 0x1
622 12:20:28.177484 ===================================
623 12:20:28.181064 ===================================
624 12:20:28.184656 ANA top config
625 12:20:28.188620 ===================================
626 12:20:28.188705 DLL_ASYNC_EN = 0
627 12:20:28.192032 ALL_SLAVE_EN = 1
628 12:20:28.195592 NEW_RANK_MODE = 1
629 12:20:28.195676 DLL_IDLE_MODE = 1
630 12:20:28.199580 LP45_APHY_COMB_EN = 1
631 12:20:28.202769 TX_ODT_DIS = 1
632 12:20:28.206256 NEW_8X_MODE = 1
633 12:20:28.206341 ===================================
634 12:20:28.209640 ===================================
635 12:20:28.212931 data_rate = 1600
636 12:20:28.216250 CKR = 1
637 12:20:28.219752 DQ_P2S_RATIO = 8
638 12:20:28.223156 ===================================
639 12:20:28.226967 CA_P2S_RATIO = 8
640 12:20:28.230304 DQ_CA_OPEN = 0
641 12:20:28.230387 DQ_SEMI_OPEN = 0
642 12:20:28.233993 CA_SEMI_OPEN = 0
643 12:20:28.237784 CA_FULL_RATE = 0
644 12:20:28.241411 DQ_CKDIV4_EN = 1
645 12:20:28.241498 CA_CKDIV4_EN = 1
646 12:20:28.245010 CA_PREDIV_EN = 0
647 12:20:28.248251 PH8_DLY = 0
648 12:20:28.251498 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:20:28.254772 DQ_AAMCK_DIV = 4
650 12:20:28.254855 CA_AAMCK_DIV = 4
651 12:20:28.258238 CA_ADMCK_DIV = 4
652 12:20:28.261665 DQ_TRACK_CA_EN = 0
653 12:20:28.265622 CA_PICK = 800
654 12:20:28.269139 CA_MCKIO = 800
655 12:20:28.269224 MCKIO_SEMI = 0
656 12:20:28.272436 PLL_FREQ = 3068
657 12:20:28.275615 DQ_UI_PI_RATIO = 32
658 12:20:28.278767 CA_UI_PI_RATIO = 0
659 12:20:28.282257 ===================================
660 12:20:28.286416 ===================================
661 12:20:28.286500 memory_type:LPDDR4
662 12:20:28.289821 GP_NUM : 10
663 12:20:28.293407 SRAM_EN : 1
664 12:20:28.293501 MD32_EN : 0
665 12:20:28.297348 ===================================
666 12:20:28.300789 [ANA_INIT] >>>>>>>>>>>>>>
667 12:20:28.300873 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:20:28.304399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:20:28.308145 ===================================
670 12:20:28.312005 data_rate = 1600,PCW = 0X7600
671 12:20:28.315311 ===================================
672 12:20:28.319158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:20:28.325868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:20:28.329042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:20:28.335901 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:20:28.339129 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:20:28.342577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:20:28.342661 [ANA_INIT] flow start
679 12:20:28.345793 [ANA_INIT] PLL >>>>>>>>
680 12:20:28.349008 [ANA_INIT] PLL <<<<<<<<
681 12:20:28.349090 [ANA_INIT] MIDPI >>>>>>>>
682 12:20:28.352537 [ANA_INIT] MIDPI <<<<<<<<
683 12:20:28.355733 [ANA_INIT] DLL >>>>>>>>
684 12:20:28.355816 [ANA_INIT] flow end
685 12:20:28.359085 ============ LP4 DIFF to SE enter ============
686 12:20:28.365727 ============ LP4 DIFF to SE exit ============
687 12:20:28.365811 [ANA_INIT] <<<<<<<<<<<<<
688 12:20:28.369301 [Flow] Enable top DCM control >>>>>
689 12:20:28.372418 [Flow] Enable top DCM control <<<<<
690 12:20:28.375785 Enable DLL master slave shuffle
691 12:20:28.382801 ==============================================================
692 12:20:28.382888 Gating Mode config
693 12:20:28.389387 ==============================================================
694 12:20:28.392679 Config description:
695 12:20:28.402559 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:20:28.409150 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:20:28.412540 SELPH_MODE 0: By rank 1: By Phase
698 12:20:28.419096 ==============================================================
699 12:20:28.422555 GAT_TRACK_EN = 1
700 12:20:28.422638 RX_GATING_MODE = 2
701 12:20:28.425918 RX_GATING_TRACK_MODE = 2
702 12:20:28.429304 SELPH_MODE = 1
703 12:20:28.432984 PICG_EARLY_EN = 1
704 12:20:28.436098 VALID_LAT_VALUE = 1
705 12:20:28.442855 ==============================================================
706 12:20:28.446115 Enter into Gating configuration >>>>
707 12:20:28.449721 Exit from Gating configuration <<<<
708 12:20:28.452845 Enter into DVFS_PRE_config >>>>>
709 12:20:28.462606 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:20:28.466079 Exit from DVFS_PRE_config <<<<<
711 12:20:28.469442 Enter into PICG configuration >>>>
712 12:20:28.472979 Exit from PICG configuration <<<<
713 12:20:28.476005 [RX_INPUT] configuration >>>>>
714 12:20:28.476089 [RX_INPUT] configuration <<<<<
715 12:20:28.482990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:20:28.489724 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:20:28.492529 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:20:28.499475 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:20:28.506120 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:20:28.512549 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:20:28.516002 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:20:28.519426 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:20:28.525817 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:20:28.529322 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:20:28.532570 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:20:28.539084 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:20:28.542512 ===================================
728 12:20:28.542608 LPDDR4 DRAM CONFIGURATION
729 12:20:28.545787 ===================================
730 12:20:28.549028 EX_ROW_EN[0] = 0x0
731 12:20:28.549111 EX_ROW_EN[1] = 0x0
732 12:20:28.552428 LP4Y_EN = 0x0
733 12:20:28.552511 WORK_FSP = 0x0
734 12:20:28.556147 WL = 0x2
735 12:20:28.556245 RL = 0x2
736 12:20:28.559190 BL = 0x2
737 12:20:28.562598 RPST = 0x0
738 12:20:28.562681 RD_PRE = 0x0
739 12:20:28.565800 WR_PRE = 0x1
740 12:20:28.565883 WR_PST = 0x0
741 12:20:28.569035 DBI_WR = 0x0
742 12:20:28.569118 DBI_RD = 0x0
743 12:20:28.572443 OTF = 0x1
744 12:20:28.575869 ===================================
745 12:20:28.579150 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:20:28.582395 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:20:28.585924 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:20:28.589302 ===================================
749 12:20:28.592449 LPDDR4 DRAM CONFIGURATION
750 12:20:28.595566 ===================================
751 12:20:28.599042 EX_ROW_EN[0] = 0x10
752 12:20:28.599124 EX_ROW_EN[1] = 0x0
753 12:20:28.602529 LP4Y_EN = 0x0
754 12:20:28.602612 WORK_FSP = 0x0
755 12:20:28.606167 WL = 0x2
756 12:20:28.606250 RL = 0x2
757 12:20:28.609026 BL = 0x2
758 12:20:28.609108 RPST = 0x0
759 12:20:28.612349 RD_PRE = 0x0
760 12:20:28.612432 WR_PRE = 0x1
761 12:20:28.615652 WR_PST = 0x0
762 12:20:28.615762 DBI_WR = 0x0
763 12:20:28.619037 DBI_RD = 0x0
764 12:20:28.622574 OTF = 0x1
765 12:20:28.622657 ===================================
766 12:20:28.628876 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:20:28.634052 nWR fixed to 40
768 12:20:28.637322 [ModeRegInit_LP4] CH0 RK0
769 12:20:28.637404 [ModeRegInit_LP4] CH0 RK1
770 12:20:28.640860 [ModeRegInit_LP4] CH1 RK0
771 12:20:28.644058 [ModeRegInit_LP4] CH1 RK1
772 12:20:28.644140 match AC timing 12
773 12:20:28.650648 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 12:20:28.653908 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:20:28.657291 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:20:28.663986 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:20:28.667650 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:20:28.667738 [EMI DOE] emi_dcm 0
779 12:20:28.674365 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:20:28.674449 ==
781 12:20:28.677720 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:20:28.680984 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 12:20:28.681231 ==
784 12:20:28.687533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:20:28.694407 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:20:28.701475 [CA 0] Center 37 (7~68) winsize 62
787 12:20:28.704858 [CA 1] Center 37 (7~68) winsize 62
788 12:20:28.708219 [CA 2] Center 35 (5~66) winsize 62
789 12:20:28.711510 [CA 3] Center 35 (5~66) winsize 62
790 12:20:28.714830 [CA 4] Center 34 (3~65) winsize 63
791 12:20:28.718211 [CA 5] Center 33 (3~64) winsize 62
792 12:20:28.718471
793 12:20:28.722004 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:20:28.722378
795 12:20:28.725109 [CATrainingPosCal] consider 1 rank data
796 12:20:28.728614 u2DelayCellTimex100 = 270/100 ps
797 12:20:28.731646 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 12:20:28.735050 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 12:20:28.742180 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 12:20:28.745044 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
801 12:20:28.748644 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 12:20:28.751660 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:20:28.752056
804 12:20:28.755644 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:20:28.756217
806 12:20:28.758743 [CBTSetCACLKResult] CA Dly = 33
807 12:20:28.759230 CS Dly: 5 (0~36)
808 12:20:28.761963 ==
809 12:20:28.762455 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:20:28.768332 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 12:20:28.768737 ==
812 12:20:28.771649 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:20:28.778538 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:20:28.787711 [CA 0] Center 37 (6~68) winsize 63
815 12:20:28.791454 [CA 1] Center 37 (6~68) winsize 63
816 12:20:28.794810 [CA 2] Center 35 (4~66) winsize 63
817 12:20:28.797885 [CA 3] Center 34 (4~65) winsize 62
818 12:20:28.801223 [CA 4] Center 33 (3~64) winsize 62
819 12:20:28.804598 [CA 5] Center 33 (3~64) winsize 62
820 12:20:28.804992
821 12:20:28.808258 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 12:20:28.808753
823 12:20:28.811573 [CATrainingPosCal] consider 2 rank data
824 12:20:28.814948 u2DelayCellTimex100 = 270/100 ps
825 12:20:28.818025 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 12:20:28.821893 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 12:20:28.827856 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 12:20:28.831427 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
829 12:20:28.834682 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 12:20:28.837909 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:20:28.838412
832 12:20:28.841560 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:20:28.842054
834 12:20:28.844741 [CBTSetCACLKResult] CA Dly = 33
835 12:20:28.845271 CS Dly: 6 (0~38)
836 12:20:28.845614
837 12:20:28.847833 ----->DramcWriteLeveling(PI) begin...
838 12:20:28.850991 ==
839 12:20:28.854574 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:20:28.858200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 12:20:28.858744 ==
842 12:20:28.861307 Write leveling (Byte 0): 32 => 32
843 12:20:28.865160 Write leveling (Byte 1): 28 => 28
844 12:20:28.865732 DramcWriteLeveling(PI) end<-----
845 12:20:28.866104
846 12:20:28.868369 ==
847 12:20:28.868793 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:20:28.875800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 12:20:28.876259 ==
850 12:20:28.876585 [Gating] SW mode calibration
851 12:20:28.882943 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:20:28.889887 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:20:28.893863 0 6 0 | B1->B0 | 3232 3131 | 1 0 | (1 0) (0 0)
854 12:20:28.896945 0 6 4 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
855 12:20:28.903547 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:20:28.906855 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:20:28.910296 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:20:28.917022 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:20:28.920141 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:20:28.923979 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:20:28.930166 0 7 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
862 12:20:28.933680 0 7 4 | B1->B0 | 3939 4040 | 0 1 | (0 0) (0 0)
863 12:20:28.936941 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 12:20:28.943511 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 12:20:28.946986 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 12:20:28.949981 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 12:20:28.956671 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 12:20:28.959961 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 12:20:28.963603 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
870 12:20:28.966754 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
871 12:20:28.973564 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 12:20:28.976759 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 12:20:28.979925 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 12:20:28.986723 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 12:20:28.990077 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 12:20:28.993495 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 12:20:28.999976 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 12:20:29.003319 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 12:20:29.006949 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 12:20:29.013656 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 12:20:29.016790 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 12:20:29.020413 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 12:20:29.027027 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 12:20:29.030305 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 12:20:29.033542 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 12:20:29.040243 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 12:20:29.040639 Total UI for P1: 0, mck2ui 16
888 12:20:29.043694 best dqsien dly found for B0: ( 0, 10, 0)
889 12:20:29.046674 Total UI for P1: 0, mck2ui 16
890 12:20:29.050061 best dqsien dly found for B1: ( 0, 10, 0)
891 12:20:29.053600 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 12:20:29.060641 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 12:20:29.061204
894 12:20:29.063775 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 12:20:29.067129 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 12:20:29.070538 [Gating] SW calibration Done
897 12:20:29.071068 ==
898 12:20:29.073845 Dram Type= 6, Freq= 0, CH_0, rank 0
899 12:20:29.076920 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 12:20:29.077345 ==
901 12:20:29.077682 RX Vref Scan: 0
902 12:20:29.080115
903 12:20:29.080547 RX Vref 0 -> 0, step: 1
904 12:20:29.080875
905 12:20:29.083390 RX Delay -130 -> 252, step: 16
906 12:20:29.086885 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 12:20:29.090313 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 12:20:29.096808 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 12:20:29.100235 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 12:20:29.103247 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
911 12:20:29.106972 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 12:20:29.110102 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 12:20:29.117170 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
914 12:20:29.120164 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
915 12:20:29.124254 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 12:20:29.127093 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 12:20:29.130235 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 12:20:29.136864 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 12:20:29.140390 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 12:20:29.143841 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 12:20:29.146837 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 12:20:29.147217 ==
923 12:20:29.150670 Dram Type= 6, Freq= 0, CH_0, rank 0
924 12:20:29.157313 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 12:20:29.157744 ==
926 12:20:29.158083 DQS Delay:
927 12:20:29.158398 DQS0 = 0, DQS1 = 0
928 12:20:29.160156 DQM Delay:
929 12:20:29.160636 DQM0 = 82, DQM1 = 75
930 12:20:29.163854 DQ Delay:
931 12:20:29.167383 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 12:20:29.170379 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =101
933 12:20:29.173686 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
934 12:20:29.176867 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 12:20:29.177291
936 12:20:29.177628
937 12:20:29.177989 ==
938 12:20:29.180382 Dram Type= 6, Freq= 0, CH_0, rank 0
939 12:20:29.183671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 12:20:29.184095 ==
941 12:20:29.184550
942 12:20:29.184871
943 12:20:29.187190 TX Vref Scan disable
944 12:20:29.187652 == TX Byte 0 ==
945 12:20:29.193985 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
946 12:20:29.197258 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
947 12:20:29.197783 == TX Byte 1 ==
948 12:20:29.203795 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
949 12:20:29.207174 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
950 12:20:29.207718 ==
951 12:20:29.210666 Dram Type= 6, Freq= 0, CH_0, rank 0
952 12:20:29.213822 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 12:20:29.214350 ==
954 12:20:29.228269 TX Vref=22, minBit 0, minWin=27, winSum=444
955 12:20:29.231225 TX Vref=24, minBit 5, minWin=27, winSum=452
956 12:20:29.234836 TX Vref=26, minBit 2, minWin=28, winSum=454
957 12:20:29.238159 TX Vref=28, minBit 4, minWin=28, winSum=458
958 12:20:29.241716 TX Vref=30, minBit 0, minWin=28, winSum=456
959 12:20:29.244667 TX Vref=32, minBit 0, minWin=28, winSum=454
960 12:20:29.251293 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 28
961 12:20:29.251819
962 12:20:29.254472 Final TX Range 1 Vref 28
963 12:20:29.254904
964 12:20:29.255242 ==
965 12:20:29.257869 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:20:29.261717 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 12:20:29.262271 ==
968 12:20:29.262621
969 12:20:29.262938
970 12:20:29.265274 TX Vref Scan disable
971 12:20:29.268338 == TX Byte 0 ==
972 12:20:29.271725 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
973 12:20:29.275544 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
974 12:20:29.278562 == TX Byte 1 ==
975 12:20:29.281638 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
976 12:20:29.285025 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
977 12:20:29.285454
978 12:20:29.288514 [DATLAT]
979 12:20:29.288946 Freq=800, CH0 RK0
980 12:20:29.289336
981 12:20:29.291747 DATLAT Default: 0xa
982 12:20:29.292203 0, 0xFFFF, sum = 0
983 12:20:29.295335 1, 0xFFFF, sum = 0
984 12:20:29.295893 2, 0xFFFF, sum = 0
985 12:20:29.298876 3, 0xFFFF, sum = 0
986 12:20:29.299418 4, 0xFFFF, sum = 0
987 12:20:29.301840 5, 0xFFFF, sum = 0
988 12:20:29.302278 6, 0xFFFF, sum = 0
989 12:20:29.305634 7, 0xFFFF, sum = 0
990 12:20:29.306176 8, 0x0, sum = 1
991 12:20:29.308352 9, 0x0, sum = 2
992 12:20:29.308787 10, 0x0, sum = 3
993 12:20:29.312359 11, 0x0, sum = 4
994 12:20:29.312923 best_step = 9
995 12:20:29.313272
996 12:20:29.313589 ==
997 12:20:29.315115 Dram Type= 6, Freq= 0, CH_0, rank 0
998 12:20:29.318774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 12:20:29.319312 ==
1000 12:20:29.321970 RX Vref Scan: 1
1001 12:20:29.322513
1002 12:20:29.325329 Set Vref Range= 32 -> 127
1003 12:20:29.325759
1004 12:20:29.326099 RX Vref 32 -> 127, step: 1
1005 12:20:29.328488
1006 12:20:29.328915 RX Delay -111 -> 252, step: 8
1007 12:20:29.329260
1008 12:20:29.332054 Set Vref, RX VrefLevel [Byte0]: 32
1009 12:20:29.335547 [Byte1]: 32
1010 12:20:29.905442
1011 12:20:29.905983 Set Vref, RX VrefLevel [Byte0]: 33
1012 12:20:29.906701 [Byte1]: 33
1013 12:20:29.907066
1014 12:20:29.907382 Set Vref, RX VrefLevel [Byte0]: 34
1015 12:20:29.907760 [Byte1]: 34
1016 12:20:29.908071
1017 12:20:29.908443 Set Vref, RX VrefLevel [Byte0]: 35
1018 12:20:29.908744 [Byte1]: 35
1019 12:20:29.909032
1020 12:20:29.909315 Set Vref, RX VrefLevel [Byte0]: 36
1021 12:20:29.909597 [Byte1]: 36
1022 12:20:29.909882
1023 12:20:29.910166 Set Vref, RX VrefLevel [Byte0]: 37
1024 12:20:29.910452 [Byte1]: 37
1025 12:20:29.910578
1026 12:20:29.910634 Set Vref, RX VrefLevel [Byte0]: 38
1027 12:20:29.910688 [Byte1]: 38
1028 12:20:29.910742
1029 12:20:29.910794 Set Vref, RX VrefLevel [Byte0]: 39
1030 12:20:29.910847 [Byte1]: 39
1031 12:20:29.910899
1032 12:20:29.910951 Set Vref, RX VrefLevel [Byte0]: 40
1033 12:20:29.911003 [Byte1]: 40
1034 12:20:29.911056
1035 12:20:29.911107 Set Vref, RX VrefLevel [Byte0]: 41
1036 12:20:29.911160 [Byte1]: 41
1037 12:20:29.911212
1038 12:20:29.911264 Set Vref, RX VrefLevel [Byte0]: 42
1039 12:20:29.911316 [Byte1]: 42
1040 12:20:29.911368
1041 12:20:29.911420 Set Vref, RX VrefLevel [Byte0]: 43
1042 12:20:29.911473 [Byte1]: 43
1043 12:20:29.911550
1044 12:20:29.911609 Set Vref, RX VrefLevel [Byte0]: 44
1045 12:20:29.911663 [Byte1]: 44
1046 12:20:29.911716
1047 12:20:29.911769 Set Vref, RX VrefLevel [Byte0]: 45
1048 12:20:29.911822 [Byte1]: 45
1049 12:20:29.911875
1050 12:20:29.911928 Set Vref, RX VrefLevel [Byte0]: 46
1051 12:20:29.911980 [Byte1]: 46
1052 12:20:29.912033
1053 12:20:29.912085 Set Vref, RX VrefLevel [Byte0]: 47
1054 12:20:29.912138 [Byte1]: 47
1055 12:20:29.912232
1056 12:20:29.912299 Set Vref, RX VrefLevel [Byte0]: 48
1057 12:20:29.912351 [Byte1]: 48
1058 12:20:29.912403
1059 12:20:29.912455 Set Vref, RX VrefLevel [Byte0]: 49
1060 12:20:29.912507 [Byte1]: 49
1061 12:20:29.912558
1062 12:20:29.912610 Set Vref, RX VrefLevel [Byte0]: 50
1063 12:20:29.912662 [Byte1]: 50
1064 12:20:29.912714
1065 12:20:29.912765 Set Vref, RX VrefLevel [Byte0]: 51
1066 12:20:29.912817 [Byte1]: 51
1067 12:20:29.912870
1068 12:20:29.912921 Set Vref, RX VrefLevel [Byte0]: 52
1069 12:20:29.912973 [Byte1]: 52
1070 12:20:29.913025
1071 12:20:29.913104 Set Vref, RX VrefLevel [Byte0]: 53
1072 12:20:29.913156 [Byte1]: 53
1073 12:20:29.913207
1074 12:20:29.913259 Set Vref, RX VrefLevel [Byte0]: 54
1075 12:20:29.913311 [Byte1]: 54
1076 12:20:29.913363
1077 12:20:29.913415 Set Vref, RX VrefLevel [Byte0]: 55
1078 12:20:29.913466 [Byte1]: 55
1079 12:20:29.913518
1080 12:20:29.913569 Set Vref, RX VrefLevel [Byte0]: 56
1081 12:20:29.913621 [Byte1]: 56
1082 12:20:29.913673
1083 12:20:29.913754 Set Vref, RX VrefLevel [Byte0]: 57
1084 12:20:29.913806 [Byte1]: 57
1085 12:20:29.913858
1086 12:20:29.913910 Set Vref, RX VrefLevel [Byte0]: 58
1087 12:20:29.913961 [Byte1]: 58
1088 12:20:29.914013
1089 12:20:29.914064 Set Vref, RX VrefLevel [Byte0]: 59
1090 12:20:29.914116 [Byte1]: 59
1091 12:20:29.914168
1092 12:20:29.914219 Set Vref, RX VrefLevel [Byte0]: 60
1093 12:20:29.914270 [Byte1]: 60
1094 12:20:29.914323
1095 12:20:29.914374 Set Vref, RX VrefLevel [Byte0]: 61
1096 12:20:29.914426 [Byte1]: 61
1097 12:20:29.914478
1098 12:20:29.914529 Set Vref, RX VrefLevel [Byte0]: 62
1099 12:20:29.914581 [Byte1]: 62
1100 12:20:29.914632
1101 12:20:29.914684 Set Vref, RX VrefLevel [Byte0]: 63
1102 12:20:29.914736 [Byte1]: 63
1103 12:20:29.914788
1104 12:20:29.914838 Set Vref, RX VrefLevel [Byte0]: 64
1105 12:20:29.914890 [Byte1]: 64
1106 12:20:29.914942
1107 12:20:29.914994 Set Vref, RX VrefLevel [Byte0]: 65
1108 12:20:29.915046 [Byte1]: 65
1109 12:20:29.915098
1110 12:20:29.915150 Set Vref, RX VrefLevel [Byte0]: 66
1111 12:20:29.915202 [Byte1]: 66
1112 12:20:29.915253
1113 12:20:29.915304 Set Vref, RX VrefLevel [Byte0]: 67
1114 12:20:29.915357 [Byte1]: 67
1115 12:20:29.915408
1116 12:20:29.915460 Set Vref, RX VrefLevel [Byte0]: 68
1117 12:20:29.915530 [Byte1]: 68
1118 12:20:29.915625
1119 12:20:29.915721 Set Vref, RX VrefLevel [Byte0]: 69
1120 12:20:29.915777 [Byte1]: 69
1121 12:20:29.915843
1122 12:20:29.915896 Set Vref, RX VrefLevel [Byte0]: 70
1123 12:20:29.915949 [Byte1]: 70
1124 12:20:29.916000
1125 12:20:29.916052 Set Vref, RX VrefLevel [Byte0]: 71
1126 12:20:29.916105 [Byte1]: 71
1127 12:20:29.916157
1128 12:20:29.916266 Set Vref, RX VrefLevel [Byte0]: 72
1129 12:20:29.916318 [Byte1]: 72
1130 12:20:29.916370
1131 12:20:29.916422 Set Vref, RX VrefLevel [Byte0]: 73
1132 12:20:29.916473 [Byte1]: 73
1133 12:20:29.916524
1134 12:20:29.916576 Set Vref, RX VrefLevel [Byte0]: 74
1135 12:20:29.916628 [Byte1]: 74
1136 12:20:29.916680
1137 12:20:29.916731 Final RX Vref Byte 0 = 52 to rank0
1138 12:20:29.916783 Final RX Vref Byte 1 = 49 to rank0
1139 12:20:29.916836 Final RX Vref Byte 0 = 52 to rank1
1140 12:20:29.916888 Final RX Vref Byte 1 = 49 to rank1==
1141 12:20:29.916940 Dram Type= 6, Freq= 0, CH_0, rank 0
1142 12:20:29.916992 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1143 12:20:29.917045 ==
1144 12:20:29.917097 DQS Delay:
1145 12:20:29.917149 DQS0 = 0, DQS1 = 0
1146 12:20:29.917201 DQM Delay:
1147 12:20:29.917252 DQM0 = 83, DQM1 = 73
1148 12:20:29.917304 DQ Delay:
1149 12:20:29.917356 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1150 12:20:29.917409 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1151 12:20:29.917460 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1152 12:20:29.917528 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1153 12:20:29.917581
1154 12:20:29.917634
1155 12:20:29.917704 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d3d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1156 12:20:29.917758 CH0 RK0: MR19=606, MR18=3D3D
1157 12:20:29.917811 CH0_RK0: MR19=0x606, MR18=0x3D3D, DQSOSC=394, MR23=63, INC=95, DEC=63
1158 12:20:29.917864
1159 12:20:29.917916 ----->DramcWriteLeveling(PI) begin...
1160 12:20:29.917969 ==
1161 12:20:29.918058 Dram Type= 6, Freq= 0, CH_0, rank 1
1162 12:20:29.918110 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1163 12:20:29.918163 ==
1164 12:20:29.918215 Write leveling (Byte 0): 29 => 29
1165 12:20:29.918267 Write leveling (Byte 1): 28 => 28
1166 12:20:29.918319 DramcWriteLeveling(PI) end<-----
1167 12:20:29.918372
1168 12:20:29.918423 ==
1169 12:20:29.918671 Dram Type= 6, Freq= 0, CH_0, rank 1
1170 12:20:29.918732 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1171 12:20:29.918787 ==
1172 12:20:29.918840 [Gating] SW mode calibration
1173 12:20:29.918893 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1174 12:20:29.918947 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1175 12:20:29.919000 0 6 0 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 0)
1176 12:20:29.919052 0 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1177 12:20:29.919104 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:20:29.919187 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:20:29.919269 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:20:29.919321 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:20:29.919373 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:20:29.919426 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:20:29.919478 0 7 0 | B1->B0 | 2b2b 3030 | 0 0 | (0 0) (0 0)
1184 12:20:29.919530 0 7 4 | B1->B0 | 4242 4040 | 0 1 | (0 0) (0 0)
1185 12:20:29.919582 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 12:20:29.919634 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 12:20:29.919686 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 12:20:29.919737 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 12:20:29.919789 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 12:20:29.919842 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 12:20:29.919894 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1192 12:20:29.919946 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1193 12:20:29.919998 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 12:20:29.920049 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 12:20:29.920102 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 12:20:29.920154 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 12:20:29.920253 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 12:20:29.920308 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:20:29.920360 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:20:29.920413 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:20:29.920465 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:20:29.920517 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:20:29.920569 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:20:29.920621 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:20:29.920674 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:20:29.920726 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:20:29.920778 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1208 12:20:29.920830 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 12:20:29.920881 Total UI for P1: 0, mck2ui 16
1210 12:20:29.920934 best dqsien dly found for B0: ( 0, 10, 0)
1211 12:20:29.920987 Total UI for P1: 0, mck2ui 16
1212 12:20:29.921090 best dqsien dly found for B1: ( 0, 10, 0)
1213 12:20:29.922824 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1214 12:20:29.929319 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1215 12:20:29.929493
1216 12:20:29.932801 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1217 12:20:29.936249 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1218 12:20:29.939927 [Gating] SW calibration Done
1219 12:20:29.940500 ==
1220 12:20:29.983920 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 12:20:29.984550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 12:20:29.985022 ==
1223 12:20:29.985366 RX Vref Scan: 0
1224 12:20:29.985667
1225 12:20:29.985963 RX Vref 0 -> 0, step: 1
1226 12:20:29.986255
1227 12:20:29.986886 RX Delay -130 -> 252, step: 16
1228 12:20:29.987207 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1229 12:20:29.987499 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1230 12:20:29.987786 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1231 12:20:29.988065 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1232 12:20:29.988421 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1233 12:20:29.988708 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1234 12:20:29.989056 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1235 12:20:29.989448 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1236 12:20:30.026503 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1237 12:20:30.027144 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1238 12:20:30.027860 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1239 12:20:30.028248 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1240 12:20:30.028571 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1241 12:20:30.028872 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1242 12:20:30.029169 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1243 12:20:30.029462 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1244 12:20:30.029747 ==
1245 12:20:30.030033 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 12:20:30.030379 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1247 12:20:30.030683 ==
1248 12:20:30.030963 DQS Delay:
1249 12:20:30.031242 DQS0 = 0, DQS1 = 0
1250 12:20:30.031519 DQM Delay:
1251 12:20:30.033988 DQM0 = 85, DQM1 = 70
1252 12:20:30.034511 DQ Delay:
1253 12:20:30.034849 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1254 12:20:30.037029 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =101
1255 12:20:30.040863 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1256 12:20:30.044108 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1257 12:20:30.044672
1258 12:20:30.047168
1259 12:20:30.047687 ==
1260 12:20:30.050656 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 12:20:30.053642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1262 12:20:30.054067 ==
1263 12:20:30.054403
1264 12:20:30.054710
1265 12:20:30.057289 TX Vref Scan disable
1266 12:20:30.057812 == TX Byte 0 ==
1267 12:20:30.064035 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1268 12:20:30.066979 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1269 12:20:30.067419 == TX Byte 1 ==
1270 12:20:30.073909 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1271 12:20:30.077511 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1272 12:20:30.078031 ==
1273 12:20:30.080414 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 12:20:30.083833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1275 12:20:30.084405 ==
1276 12:20:30.097630 TX Vref=22, minBit 0, minWin=27, winSum=445
1277 12:20:30.100510 TX Vref=24, minBit 2, minWin=27, winSum=451
1278 12:20:30.104068 TX Vref=26, minBit 0, minWin=28, winSum=452
1279 12:20:30.107147 TX Vref=28, minBit 2, minWin=28, winSum=459
1280 12:20:30.110933 TX Vref=30, minBit 2, minWin=28, winSum=460
1281 12:20:30.114839 TX Vref=32, minBit 0, minWin=28, winSum=457
1282 12:20:30.122071 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 30
1283 12:20:30.122595
1284 12:20:30.125274 Final TX Range 1 Vref 30
1285 12:20:30.125695
1286 12:20:30.126027 ==
1287 12:20:30.128636 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 12:20:30.132149 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1289 12:20:30.132761 ==
1290 12:20:30.133147
1291 12:20:30.133461
1292 12:20:30.135433 TX Vref Scan disable
1293 12:20:30.135847 == TX Byte 0 ==
1294 12:20:30.143009 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1295 12:20:30.145846 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1296 12:20:30.146269 == TX Byte 1 ==
1297 12:20:30.152586 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1298 12:20:30.155752 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1299 12:20:30.156203
1300 12:20:30.156547 [DATLAT]
1301 12:20:30.159228 Freq=800, CH0 RK1
1302 12:20:30.159648
1303 12:20:30.159978 DATLAT Default: 0x9
1304 12:20:30.162704 0, 0xFFFF, sum = 0
1305 12:20:30.163128 1, 0xFFFF, sum = 0
1306 12:20:30.165970 2, 0xFFFF, sum = 0
1307 12:20:30.166394 3, 0xFFFF, sum = 0
1308 12:20:30.169692 4, 0xFFFF, sum = 0
1309 12:20:30.170118 5, 0xFFFF, sum = 0
1310 12:20:30.172684 6, 0xFFFF, sum = 0
1311 12:20:30.173109 7, 0xFFFF, sum = 0
1312 12:20:30.176055 8, 0x0, sum = 1
1313 12:20:30.176510 9, 0x0, sum = 2
1314 12:20:30.179463 10, 0x0, sum = 3
1315 12:20:30.180135 11, 0x0, sum = 4
1316 12:20:30.182792 best_step = 9
1317 12:20:30.183206
1318 12:20:30.183536 ==
1319 12:20:30.185757 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 12:20:30.189127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1321 12:20:30.189460 ==
1322 12:20:30.189732 RX Vref Scan: 0
1323 12:20:30.189963
1324 12:20:30.192391 RX Vref 0 -> 0, step: 1
1325 12:20:30.192616
1326 12:20:30.195781 RX Delay -111 -> 252, step: 8
1327 12:20:30.199049 iDelay=217, Bit 0, Center 80 (-39 ~ 200) 240
1328 12:20:30.205852 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1329 12:20:30.209161 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1330 12:20:30.212510 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1331 12:20:30.215568 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1332 12:20:30.219092 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1333 12:20:30.225699 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1334 12:20:30.229207 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1335 12:20:30.232493 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1336 12:20:30.235678 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1337 12:20:30.239157 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1338 12:20:30.245612 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1339 12:20:30.249241 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1340 12:20:30.252191 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1341 12:20:30.255571 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1342 12:20:30.259121 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1343 12:20:30.262631 ==
1344 12:20:30.265929 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 12:20:30.269328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1346 12:20:30.269519 ==
1347 12:20:30.269619 DQS Delay:
1348 12:20:30.272547 DQS0 = 0, DQS1 = 0
1349 12:20:30.272753 DQM Delay:
1350 12:20:30.275996 DQM0 = 86, DQM1 = 73
1351 12:20:30.276239 DQ Delay:
1352 12:20:30.279376 DQ0 =80, DQ1 =92, DQ2 =84, DQ3 =84
1353 12:20:30.282793 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1354 12:20:30.285863 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1355 12:20:30.289202 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1356 12:20:30.289471
1357 12:20:30.289629
1358 12:20:30.295708 [DQSOSCAuto] RK1, (LSB)MR18= 0x4444, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1359 12:20:30.299146 CH0 RK1: MR19=606, MR18=4444
1360 12:20:30.306016 CH0_RK1: MR19=0x606, MR18=0x4444, DQSOSC=392, MR23=63, INC=96, DEC=64
1361 12:20:30.309260 [RxdqsGatingPostProcess] freq 800
1362 12:20:30.312720 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 12:20:30.315723 Pre-setting of DQS Precalculation
1364 12:20:30.322551 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1365 12:20:30.322969 ==
1366 12:20:30.326019 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 12:20:30.329299 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1368 12:20:30.329822 ==
1369 12:20:30.335892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 12:20:30.342687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 12:20:30.350125 [CA 0] Center 37 (6~68) winsize 63
1372 12:20:30.353119 [CA 1] Center 37 (6~68) winsize 63
1373 12:20:30.356475 [CA 2] Center 34 (4~65) winsize 62
1374 12:20:30.359643 [CA 3] Center 34 (4~65) winsize 62
1375 12:20:30.363126 [CA 4] Center 33 (3~64) winsize 62
1376 12:20:30.366349 [CA 5] Center 33 (3~64) winsize 62
1377 12:20:30.366717
1378 12:20:30.369724 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 12:20:30.370081
1380 12:20:30.372838 [CATrainingPosCal] consider 1 rank data
1381 12:20:30.376144 u2DelayCellTimex100 = 270/100 ps
1382 12:20:30.379567 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1383 12:20:30.382881 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1384 12:20:30.389458 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 12:20:30.393038 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 12:20:30.396279 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1387 12:20:30.399746 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 12:20:30.400296
1389 12:20:30.402941 CA PerBit enable=1, Macro0, CA PI delay=33
1390 12:20:30.403451
1391 12:20:30.406194 [CBTSetCACLKResult] CA Dly = 33
1392 12:20:30.406605 CS Dly: 5 (0~36)
1393 12:20:30.409857 ==
1394 12:20:30.410368 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 12:20:30.416799 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1396 12:20:30.417318 ==
1397 12:20:30.419535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 12:20:30.426252 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 12:20:30.435905 [CA 0] Center 37 (6~68) winsize 63
1400 12:20:30.439194 [CA 1] Center 37 (6~68) winsize 63
1401 12:20:30.442314 [CA 2] Center 34 (4~65) winsize 62
1402 12:20:30.445916 [CA 3] Center 34 (4~65) winsize 62
1403 12:20:30.449118 [CA 4] Center 33 (3~64) winsize 62
1404 12:20:30.452551 [CA 5] Center 33 (3~64) winsize 62
1405 12:20:30.453195
1406 12:20:30.455610 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1407 12:20:30.456023
1408 12:20:30.459121 [CATrainingPosCal] consider 2 rank data
1409 12:20:30.462416 u2DelayCellTimex100 = 270/100 ps
1410 12:20:30.465661 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1411 12:20:30.469201 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1412 12:20:30.475661 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 12:20:30.479236 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 12:20:30.482275 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1415 12:20:30.485760 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 12:20:30.486279
1417 12:20:30.488964 CA PerBit enable=1, Macro0, CA PI delay=33
1418 12:20:30.489380
1419 12:20:30.491833 [CBTSetCACLKResult] CA Dly = 33
1420 12:20:30.492305 CS Dly: 5 (0~37)
1421 12:20:30.492648
1422 12:20:30.495711 ----->DramcWriteLeveling(PI) begin...
1423 12:20:30.498938 ==
1424 12:20:30.502306 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 12:20:30.505205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1426 12:20:30.505634 ==
1427 12:20:30.508640 Write leveling (Byte 0): 24 => 24
1428 12:20:30.512274 Write leveling (Byte 1): 24 => 24
1429 12:20:30.515256 DramcWriteLeveling(PI) end<-----
1430 12:20:30.515882
1431 12:20:30.516375 ==
1432 12:20:30.519094 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 12:20:30.521923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1434 12:20:30.522429 ==
1435 12:20:30.525306 [Gating] SW mode calibration
1436 12:20:30.531585 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 12:20:30.538513 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 12:20:30.541921 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1439 12:20:30.545332 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 12:20:30.551973 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 12:20:30.555049 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 12:20:30.558477 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 12:20:30.561992 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 12:20:30.568314 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 12:20:30.571724 0 6 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1446 12:20:30.575414 0 7 0 | B1->B0 | 2e2e 4242 | 0 0 | (0 0) (0 0)
1447 12:20:30.581979 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 12:20:30.585393 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 12:20:30.588233 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 12:20:30.595035 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 12:20:30.598237 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 12:20:30.601778 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 12:20:30.608042 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 12:20:30.611654 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1455 12:20:30.615104 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 12:20:30.621957 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 12:20:30.624852 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 12:20:30.629206 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 12:20:30.635314 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 12:20:30.638212 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 12:20:30.641941 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 12:20:30.648449 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 12:20:30.651417 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 12:20:30.654814 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 12:20:30.662022 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 12:20:30.665119 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 12:20:30.668145 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 12:20:30.671826 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 12:20:30.678335 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1470 12:20:30.681784 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1471 12:20:30.684964 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1472 12:20:30.688461 Total UI for P1: 0, mck2ui 16
1473 12:20:30.691532 best dqsien dly found for B0: ( 0, 9, 30)
1474 12:20:30.695155 Total UI for P1: 0, mck2ui 16
1475 12:20:30.698017 best dqsien dly found for B1: ( 0, 10, 0)
1476 12:20:30.701547 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1477 12:20:30.704787 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1478 12:20:30.705199
1479 12:20:30.711666 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1480 12:20:30.714757 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1481 12:20:30.718237 [Gating] SW calibration Done
1482 12:20:30.718755 ==
1483 12:20:30.721608 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 12:20:30.724687 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1485 12:20:30.725103 ==
1486 12:20:30.725430 RX Vref Scan: 0
1487 12:20:30.725733
1488 12:20:30.728243 RX Vref 0 -> 0, step: 1
1489 12:20:30.728771
1490 12:20:30.731477 RX Delay -130 -> 252, step: 16
1491 12:20:30.734995 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1492 12:20:30.738556 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1493 12:20:30.744893 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1494 12:20:30.748380 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1495 12:20:30.751590 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1496 12:20:30.754644 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1497 12:20:30.758429 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1498 12:20:30.765064 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1499 12:20:30.768130 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1500 12:20:30.771825 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1501 12:20:30.775114 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1502 12:20:30.778710 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1503 12:20:30.782263 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1504 12:20:30.785893 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1505 12:20:30.793155 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1506 12:20:30.796799 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1507 12:20:30.796882 ==
1508 12:20:30.800472 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 12:20:30.804095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1510 12:20:30.804191 ==
1511 12:20:30.804263 DQS Delay:
1512 12:20:30.804349 DQS0 = 0, DQS1 = 0
1513 12:20:30.808417 DQM Delay:
1514 12:20:30.808511 DQM0 = 85, DQM1 = 75
1515 12:20:30.811649 DQ Delay:
1516 12:20:30.811833 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1517 12:20:30.815252 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1518 12:20:30.818253 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =69
1519 12:20:30.821961 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1520 12:20:30.822164
1521 12:20:30.822270
1522 12:20:30.825067 ==
1523 12:20:30.825269 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 12:20:30.831958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1525 12:20:30.832217 ==
1526 12:20:30.832360
1527 12:20:30.832481
1528 12:20:30.835192 TX Vref Scan disable
1529 12:20:30.835427 == TX Byte 0 ==
1530 12:20:30.838313 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1531 12:20:30.845316 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1532 12:20:30.845660 == TX Byte 1 ==
1533 12:20:30.848335 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1534 12:20:30.855338 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1535 12:20:30.855814 ==
1536 12:20:30.858847 Dram Type= 6, Freq= 0, CH_1, rank 0
1537 12:20:30.862179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1538 12:20:30.862712 ==
1539 12:20:30.875232 TX Vref=22, minBit 9, minWin=27, winSum=448
1540 12:20:30.878371 TX Vref=24, minBit 0, minWin=28, winSum=451
1541 12:20:30.881486 TX Vref=26, minBit 0, minWin=28, winSum=453
1542 12:20:30.884902 TX Vref=28, minBit 0, minWin=28, winSum=457
1543 12:20:30.888261 TX Vref=30, minBit 0, minWin=28, winSum=457
1544 12:20:30.895082 TX Vref=32, minBit 0, minWin=28, winSum=454
1545 12:20:30.898143 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1546 12:20:30.898564
1547 12:20:30.901187 Final TX Range 1 Vref 28
1548 12:20:30.901603
1549 12:20:30.901929 ==
1550 12:20:30.904874 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 12:20:30.907852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1552 12:20:30.908304 ==
1553 12:20:30.911280
1554 12:20:30.911693
1555 12:20:30.912023 TX Vref Scan disable
1556 12:20:30.914814 == TX Byte 0 ==
1557 12:20:30.918006 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1558 12:20:30.921418 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1559 12:20:30.924735 == TX Byte 1 ==
1560 12:20:30.928118 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1561 12:20:30.935055 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1562 12:20:30.935575
1563 12:20:30.935905 [DATLAT]
1564 12:20:30.936251 Freq=800, CH1 RK0
1565 12:20:30.936554
1566 12:20:30.937863 DATLAT Default: 0xa
1567 12:20:30.938275 0, 0xFFFF, sum = 0
1568 12:20:30.941426 1, 0xFFFF, sum = 0
1569 12:20:30.941952 2, 0xFFFF, sum = 0
1570 12:20:30.944694 3, 0xFFFF, sum = 0
1571 12:20:30.945117 4, 0xFFFF, sum = 0
1572 12:20:30.948301 5, 0xFFFF, sum = 0
1573 12:20:30.948836 6, 0xFFFF, sum = 0
1574 12:20:30.951837 7, 0xFFFF, sum = 0
1575 12:20:30.952355 8, 0x0, sum = 1
1576 12:20:30.954703 9, 0x0, sum = 2
1577 12:20:30.955125 10, 0x0, sum = 3
1578 12:20:30.958394 11, 0x0, sum = 4
1579 12:20:30.958922 best_step = 9
1580 12:20:30.959255
1581 12:20:30.959557 ==
1582 12:20:30.961598 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 12:20:30.968124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1584 12:20:30.968682 ==
1585 12:20:30.969014 RX Vref Scan: 1
1586 12:20:30.969321
1587 12:20:30.971637 Set Vref Range= 32 -> 127
1588 12:20:30.972214
1589 12:20:30.975033 RX Vref 32 -> 127, step: 1
1590 12:20:30.975449
1591 12:20:30.975776 RX Delay -111 -> 252, step: 8
1592 12:20:30.978624
1593 12:20:30.979139 Set Vref, RX VrefLevel [Byte0]: 32
1594 12:20:30.981318 [Byte1]: 32
1595 12:20:30.985822
1596 12:20:30.986350 Set Vref, RX VrefLevel [Byte0]: 33
1597 12:20:30.989039 [Byte1]: 33
1598 12:20:30.993161
1599 12:20:30.993572 Set Vref, RX VrefLevel [Byte0]: 34
1600 12:20:30.996416 [Byte1]: 34
1601 12:20:31.001006
1602 12:20:31.001423 Set Vref, RX VrefLevel [Byte0]: 35
1603 12:20:31.004323 [Byte1]: 35
1604 12:20:31.008989
1605 12:20:31.009506 Set Vref, RX VrefLevel [Byte0]: 36
1606 12:20:31.012098 [Byte1]: 36
1607 12:20:31.016523
1608 12:20:31.017058 Set Vref, RX VrefLevel [Byte0]: 37
1609 12:20:31.019631 [Byte1]: 37
1610 12:20:31.023945
1611 12:20:31.024512 Set Vref, RX VrefLevel [Byte0]: 38
1612 12:20:31.027372 [Byte1]: 38
1613 12:20:31.031925
1614 12:20:31.032491 Set Vref, RX VrefLevel [Byte0]: 39
1615 12:20:31.035385 [Byte1]: 39
1616 12:20:31.039430
1617 12:20:31.039946 Set Vref, RX VrefLevel [Byte0]: 40
1618 12:20:31.042810 [Byte1]: 40
1619 12:20:31.047002
1620 12:20:31.047519 Set Vref, RX VrefLevel [Byte0]: 41
1621 12:20:31.050460 [Byte1]: 41
1622 12:20:31.054488
1623 12:20:31.055006 Set Vref, RX VrefLevel [Byte0]: 42
1624 12:20:31.057940 [Byte1]: 42
1625 12:20:31.062305
1626 12:20:31.062820 Set Vref, RX VrefLevel [Byte0]: 43
1627 12:20:31.065699 [Byte1]: 43
1628 12:20:31.069783
1629 12:20:31.070366 Set Vref, RX VrefLevel [Byte0]: 44
1630 12:20:31.073269 [Byte1]: 44
1631 12:20:31.077472
1632 12:20:31.077887 Set Vref, RX VrefLevel [Byte0]: 45
1633 12:20:31.081143 [Byte1]: 45
1634 12:20:31.085486
1635 12:20:31.086044 Set Vref, RX VrefLevel [Byte0]: 46
1636 12:20:31.088953 [Byte1]: 46
1637 12:20:31.092870
1638 12:20:31.093345 Set Vref, RX VrefLevel [Byte0]: 47
1639 12:20:31.096100 [Byte1]: 47
1640 12:20:31.100493
1641 12:20:31.100951 Set Vref, RX VrefLevel [Byte0]: 48
1642 12:20:31.103883 [Byte1]: 48
1643 12:20:31.107786
1644 12:20:31.108244 Set Vref, RX VrefLevel [Byte0]: 49
1645 12:20:31.111283 [Byte1]: 49
1646 12:20:31.115790
1647 12:20:31.116231 Set Vref, RX VrefLevel [Byte0]: 50
1648 12:20:31.118862 [Byte1]: 50
1649 12:20:31.123207
1650 12:20:31.123623 Set Vref, RX VrefLevel [Byte0]: 51
1651 12:20:31.126462 [Byte1]: 51
1652 12:20:31.130853
1653 12:20:31.131267 Set Vref, RX VrefLevel [Byte0]: 52
1654 12:20:31.134070 [Byte1]: 52
1655 12:20:31.138503
1656 12:20:31.138923 Set Vref, RX VrefLevel [Byte0]: 53
1657 12:20:31.141836 [Byte1]: 53
1658 12:20:31.146133
1659 12:20:31.146551 Set Vref, RX VrefLevel [Byte0]: 54
1660 12:20:31.149432 [Byte1]: 54
1661 12:20:31.153963
1662 12:20:31.154381 Set Vref, RX VrefLevel [Byte0]: 55
1663 12:20:31.157268 [Byte1]: 55
1664 12:20:31.161908
1665 12:20:31.162325 Set Vref, RX VrefLevel [Byte0]: 56
1666 12:20:31.165018 [Byte1]: 56
1667 12:20:31.169066
1668 12:20:31.169483 Set Vref, RX VrefLevel [Byte0]: 57
1669 12:20:31.172264 [Byte1]: 57
1670 12:20:31.176610
1671 12:20:31.177040 Set Vref, RX VrefLevel [Byte0]: 58
1672 12:20:31.180099 [Byte1]: 58
1673 12:20:31.184526
1674 12:20:31.184939 Set Vref, RX VrefLevel [Byte0]: 59
1675 12:20:31.187620 [Byte1]: 59
1676 12:20:31.191853
1677 12:20:31.192438 Set Vref, RX VrefLevel [Byte0]: 60
1678 12:20:31.195218 [Byte1]: 60
1679 12:20:31.199650
1680 12:20:31.200068 Set Vref, RX VrefLevel [Byte0]: 61
1681 12:20:31.203200 [Byte1]: 61
1682 12:20:31.207438
1683 12:20:31.207858 Set Vref, RX VrefLevel [Byte0]: 62
1684 12:20:31.210638 [Byte1]: 62
1685 12:20:31.214931
1686 12:20:31.215349 Set Vref, RX VrefLevel [Byte0]: 63
1687 12:20:31.218346 [Byte1]: 63
1688 12:20:31.222637
1689 12:20:31.222936 Set Vref, RX VrefLevel [Byte0]: 64
1690 12:20:31.225767 [Byte1]: 64
1691 12:20:31.230030
1692 12:20:31.230256 Set Vref, RX VrefLevel [Byte0]: 65
1693 12:20:31.233251 [Byte1]: 65
1694 12:20:31.237538
1695 12:20:31.237692 Set Vref, RX VrefLevel [Byte0]: 66
1696 12:20:31.240915 [Byte1]: 66
1697 12:20:31.245429
1698 12:20:31.245561 Set Vref, RX VrefLevel [Byte0]: 67
1699 12:20:31.251845 [Byte1]: 67
1700 12:20:31.252041
1701 12:20:31.255150 Set Vref, RX VrefLevel [Byte0]: 68
1702 12:20:31.258568 [Byte1]: 68
1703 12:20:31.258765
1704 12:20:31.262077 Set Vref, RX VrefLevel [Byte0]: 69
1705 12:20:31.265306 [Byte1]: 69
1706 12:20:31.265502
1707 12:20:31.268485 Set Vref, RX VrefLevel [Byte0]: 70
1708 12:20:31.272035 [Byte1]: 70
1709 12:20:31.276251
1710 12:20:31.276476 Set Vref, RX VrefLevel [Byte0]: 71
1711 12:20:31.279448 [Byte1]: 71
1712 12:20:31.283862
1713 12:20:31.284102 Set Vref, RX VrefLevel [Byte0]: 72
1714 12:20:31.287003 [Byte1]: 72
1715 12:20:31.291548
1716 12:20:31.292124 Set Vref, RX VrefLevel [Byte0]: 73
1717 12:20:31.294799 [Byte1]: 73
1718 12:20:31.299122
1719 12:20:31.299547 Set Vref, RX VrefLevel [Byte0]: 74
1720 12:20:31.302985 [Byte1]: 74
1721 12:20:31.306844
1722 12:20:31.307303 Set Vref, RX VrefLevel [Byte0]: 75
1723 12:20:31.310235 [Byte1]: 75
1724 12:20:31.315147
1725 12:20:31.315658 Set Vref, RX VrefLevel [Byte0]: 76
1726 12:20:31.318531 [Byte1]: 76
1727 12:20:31.322448
1728 12:20:31.323003 Set Vref, RX VrefLevel [Byte0]: 77
1729 12:20:31.325491 [Byte1]: 77
1730 12:20:31.330108
1731 12:20:31.330764 Set Vref, RX VrefLevel [Byte0]: 78
1732 12:20:31.332928 [Byte1]: 78
1733 12:20:31.338192
1734 12:20:31.338727 Final RX Vref Byte 0 = 58 to rank0
1735 12:20:31.341095 Final RX Vref Byte 1 = 53 to rank0
1736 12:20:31.344480 Final RX Vref Byte 0 = 58 to rank1
1737 12:20:31.347643 Final RX Vref Byte 1 = 53 to rank1==
1738 12:20:31.350902 Dram Type= 6, Freq= 0, CH_1, rank 0
1739 12:20:31.357609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1740 12:20:31.358032 ==
1741 12:20:31.358520 DQS Delay:
1742 12:20:31.358850 DQS0 = 0, DQS1 = 0
1743 12:20:31.361797 DQM Delay:
1744 12:20:31.362426 DQM0 = 81, DQM1 = 75
1745 12:20:31.362765 DQ Delay:
1746 12:20:31.364923 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =76
1747 12:20:31.367989 DQ4 =80, DQ5 =96, DQ6 =88, DQ7 =76
1748 12:20:31.371873 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1749 12:20:31.374349 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1750 12:20:31.374770
1751 12:20:31.375099
1752 12:20:31.384741 [DQSOSCAuto] RK0, (LSB)MR18= 0x5252, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1753 12:20:31.387588 CH1 RK0: MR19=606, MR18=5252
1754 12:20:31.394449 CH1_RK0: MR19=0x606, MR18=0x5252, DQSOSC=389, MR23=63, INC=97, DEC=65
1755 12:20:31.394957
1756 12:20:31.397800 ----->DramcWriteLeveling(PI) begin...
1757 12:20:31.398222 ==
1758 12:20:31.401424 Dram Type= 6, Freq= 0, CH_1, rank 1
1759 12:20:31.404568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1760 12:20:31.405091 ==
1761 12:20:31.407881 Write leveling (Byte 0): 28 => 28
1762 12:20:31.411237 Write leveling (Byte 1): 23 => 23
1763 12:20:31.414715 DramcWriteLeveling(PI) end<-----
1764 12:20:31.415232
1765 12:20:31.415562 ==
1766 12:20:31.418092 Dram Type= 6, Freq= 0, CH_1, rank 1
1767 12:20:31.421357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1768 12:20:31.421876 ==
1769 12:20:31.424877 [Gating] SW mode calibration
1770 12:20:31.431328 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1771 12:20:31.438483 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1772 12:20:31.441114 0 6 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
1773 12:20:31.444444 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1774 12:20:31.451373 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1775 12:20:31.454754 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 12:20:31.458169 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1777 12:20:31.461044 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1778 12:20:31.467843 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1779 12:20:31.471251 0 6 28 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
1780 12:20:31.474763 0 7 0 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
1781 12:20:31.481051 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1782 12:20:31.484892 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1783 12:20:31.487784 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 12:20:31.494586 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1785 12:20:31.497551 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1786 12:20:31.500814 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1787 12:20:31.507650 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1788 12:20:31.511254 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1789 12:20:31.514232 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 12:20:31.521107 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 12:20:31.524563 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 12:20:31.528148 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 12:20:31.534247 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 12:20:31.537936 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 12:20:31.541066 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 12:20:31.547928 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 12:20:31.551321 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 12:20:31.554287 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 12:20:31.561343 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 12:20:31.564653 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 12:20:31.567661 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1802 12:20:31.571034 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1803 12:20:31.577915 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1804 12:20:31.581042 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1805 12:20:31.584527 Total UI for P1: 0, mck2ui 16
1806 12:20:31.587737 best dqsien dly found for B0: ( 0, 9, 28)
1807 12:20:31.590915 Total UI for P1: 0, mck2ui 16
1808 12:20:31.594462 best dqsien dly found for B1: ( 0, 9, 30)
1809 12:20:31.597565 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1810 12:20:31.600838 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1811 12:20:31.601301
1812 12:20:31.604151 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1813 12:20:31.611267 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1814 12:20:31.611791 [Gating] SW calibration Done
1815 12:20:31.612127 ==
1816 12:20:31.614142 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 12:20:31.620852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1818 12:20:31.621273 ==
1819 12:20:31.621603 RX Vref Scan: 0
1820 12:20:31.621907
1821 12:20:31.624540 RX Vref 0 -> 0, step: 1
1822 12:20:31.625053
1823 12:20:31.628013 RX Delay -130 -> 252, step: 16
1824 12:20:31.630811 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1825 12:20:31.634419 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1826 12:20:31.637501 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1827 12:20:31.644319 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1828 12:20:31.648026 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1829 12:20:31.651065 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1830 12:20:31.654184 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1831 12:20:31.657389 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1832 12:20:31.661137 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1833 12:20:31.667836 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1834 12:20:31.671003 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1835 12:20:31.674471 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1836 12:20:31.677869 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1837 12:20:31.684345 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1838 12:20:31.687723 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1839 12:20:31.690956 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1840 12:20:31.691509 ==
1841 12:20:31.694295 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 12:20:31.697490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1843 12:20:31.697954 ==
1844 12:20:31.701079 DQS Delay:
1845 12:20:31.701535 DQS0 = 0, DQS1 = 0
1846 12:20:31.701894 DQM Delay:
1847 12:20:31.704464 DQM0 = 86, DQM1 = 74
1848 12:20:31.705024 DQ Delay:
1849 12:20:31.707815 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1850 12:20:31.711143 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1851 12:20:31.714625 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1852 12:20:31.717940 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1853 12:20:31.718502
1854 12:20:31.718865
1855 12:20:31.719201 ==
1856 12:20:31.721176 Dram Type= 6, Freq= 0, CH_1, rank 1
1857 12:20:31.727782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1858 12:20:31.728333 ==
1859 12:20:31.728668
1860 12:20:31.728971
1861 12:20:31.729262 TX Vref Scan disable
1862 12:20:31.731656 == TX Byte 0 ==
1863 12:20:31.734596 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1864 12:20:31.738104 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1865 12:20:31.741446 == TX Byte 1 ==
1866 12:20:31.745199 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1867 12:20:31.748472 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1868 12:20:31.751461 ==
1869 12:20:31.754740 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 12:20:31.757867 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1871 12:20:31.758286 ==
1872 12:20:31.771094 TX Vref=22, minBit 0, minWin=27, winSum=450
1873 12:20:31.774487 TX Vref=24, minBit 0, minWin=28, winSum=452
1874 12:20:31.777479 TX Vref=26, minBit 11, minWin=27, winSum=453
1875 12:20:31.780945 TX Vref=28, minBit 0, minWin=28, winSum=457
1876 12:20:31.784068 TX Vref=30, minBit 0, minWin=28, winSum=455
1877 12:20:31.787625 TX Vref=32, minBit 9, minWin=27, winSum=452
1878 12:20:31.794292 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1879 12:20:31.794710
1880 12:20:31.797523 Final TX Range 1 Vref 28
1881 12:20:31.797938
1882 12:20:31.798266 ==
1883 12:20:31.800867 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 12:20:31.804224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1885 12:20:31.804778 ==
1886 12:20:31.805130
1887 12:20:31.807594
1888 12:20:31.808003 TX Vref Scan disable
1889 12:20:31.810993 == TX Byte 0 ==
1890 12:20:31.814449 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1891 12:20:31.818100 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1892 12:20:31.821539 == TX Byte 1 ==
1893 12:20:31.824533 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1894 12:20:31.827839 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1895 12:20:31.831157
1896 12:20:31.831673 [DATLAT]
1897 12:20:31.832001 Freq=800, CH1 RK1
1898 12:20:31.832374
1899 12:20:31.834133 DATLAT Default: 0x9
1900 12:20:31.834545 0, 0xFFFF, sum = 0
1901 12:20:31.837809 1, 0xFFFF, sum = 0
1902 12:20:31.838335 2, 0xFFFF, sum = 0
1903 12:20:31.840967 3, 0xFFFF, sum = 0
1904 12:20:31.841426 4, 0xFFFF, sum = 0
1905 12:20:31.844699 5, 0xFFFF, sum = 0
1906 12:20:31.845216 6, 0xFFFF, sum = 0
1907 12:20:31.847809 7, 0xFFFF, sum = 0
1908 12:20:31.848269 8, 0x0, sum = 1
1909 12:20:31.851389 9, 0x0, sum = 2
1910 12:20:31.851908 10, 0x0, sum = 3
1911 12:20:31.854442 11, 0x0, sum = 4
1912 12:20:31.854858 best_step = 9
1913 12:20:31.855186
1914 12:20:31.855488 ==
1915 12:20:31.857566 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 12:20:31.864223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1917 12:20:31.864725 ==
1918 12:20:31.865053 RX Vref Scan: 0
1919 12:20:31.865358
1920 12:20:31.867709 RX Vref 0 -> 0, step: 1
1921 12:20:31.868230
1922 12:20:31.871316 RX Delay -111 -> 252, step: 8
1923 12:20:31.874509 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1924 12:20:31.878235 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1925 12:20:31.884639 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1926 12:20:31.888096 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1927 12:20:31.891138 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1928 12:20:31.894406 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1929 12:20:31.897714 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1930 12:20:31.900897 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1931 12:20:31.907866 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1932 12:20:31.911081 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1933 12:20:31.915040 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1934 12:20:31.918167 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1935 12:20:31.921276 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1936 12:20:31.927995 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1937 12:20:31.931209 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1938 12:20:31.934396 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1939 12:20:31.934814 ==
1940 12:20:31.938098 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 12:20:31.941622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1942 12:20:31.942141 ==
1943 12:20:31.944266 DQS Delay:
1944 12:20:31.944678 DQS0 = 0, DQS1 = 0
1945 12:20:31.948006 DQM Delay:
1946 12:20:31.948591 DQM0 = 84, DQM1 = 75
1947 12:20:31.948989 DQ Delay:
1948 12:20:31.951293 DQ0 =88, DQ1 =76, DQ2 =76, DQ3 =84
1949 12:20:31.954519 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1950 12:20:31.957917 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1951 12:20:31.960917 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1952 12:20:31.961334
1953 12:20:31.961676
1954 12:20:31.970940 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1955 12:20:31.974238 CH1 RK1: MR19=606, MR18=3C3C
1956 12:20:31.980867 CH1_RK1: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1957 12:20:31.981284 [RxdqsGatingPostProcess] freq 800
1958 12:20:31.987407 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1959 12:20:31.990742 Pre-setting of DQS Precalculation
1960 12:20:31.994165 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1961 12:20:32.004239 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1962 12:20:32.011014 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1963 12:20:32.011535
1964 12:20:32.011865
1965 12:20:32.014309 [Calibration Summary] 1600 Mbps
1966 12:20:32.014827 CH 0, Rank 0
1967 12:20:32.017601 SW Impedance : PASS
1968 12:20:32.018122 DUTY Scan : NO K
1969 12:20:32.021201 ZQ Calibration : PASS
1970 12:20:32.024520 Jitter Meter : NO K
1971 12:20:32.025036 CBT Training : PASS
1972 12:20:32.028083 Write leveling : PASS
1973 12:20:32.031067 RX DQS gating : PASS
1974 12:20:32.031594 RX DQ/DQS(RDDQC) : PASS
1975 12:20:32.034186 TX DQ/DQS : PASS
1976 12:20:32.037485 RX DATLAT : PASS
1977 12:20:32.037901 RX DQ/DQS(Engine): PASS
1978 12:20:32.040734 TX OE : NO K
1979 12:20:32.041150 All Pass.
1980 12:20:32.041476
1981 12:20:32.044088 CH 0, Rank 1
1982 12:20:32.044557 SW Impedance : PASS
1983 12:20:32.047627 DUTY Scan : NO K
1984 12:20:32.048145 ZQ Calibration : PASS
1985 12:20:32.051017 Jitter Meter : NO K
1986 12:20:32.054624 CBT Training : PASS
1987 12:20:32.055147 Write leveling : PASS
1988 12:20:32.057413 RX DQS gating : PASS
1989 12:20:32.061048 RX DQ/DQS(RDDQC) : PASS
1990 12:20:32.061568 TX DQ/DQS : PASS
1991 12:20:32.064512 RX DATLAT : PASS
1992 12:20:32.067858 RX DQ/DQS(Engine): PASS
1993 12:20:32.068406 TX OE : NO K
1994 12:20:32.071294 All Pass.
1995 12:20:32.071852
1996 12:20:32.072240 CH 1, Rank 0
1997 12:20:32.074889 SW Impedance : PASS
1998 12:20:32.075432 DUTY Scan : NO K
1999 12:20:32.077856 ZQ Calibration : PASS
2000 12:20:32.081245 Jitter Meter : NO K
2001 12:20:32.081802 CBT Training : PASS
2002 12:20:32.084425 Write leveling : PASS
2003 12:20:32.084975 RX DQS gating : PASS
2004 12:20:32.087691 RX DQ/DQS(RDDQC) : PASS
2005 12:20:32.091407 TX DQ/DQS : PASS
2006 12:20:32.091964 RX DATLAT : PASS
2007 12:20:32.094480 RX DQ/DQS(Engine): PASS
2008 12:20:32.097941 TX OE : NO K
2009 12:20:32.098402 All Pass.
2010 12:20:32.098760
2011 12:20:32.099092 CH 1, Rank 1
2012 12:20:32.101293 SW Impedance : PASS
2013 12:20:32.104405 DUTY Scan : NO K
2014 12:20:32.104817 ZQ Calibration : PASS
2015 12:20:32.107694 Jitter Meter : NO K
2016 12:20:32.110956 CBT Training : PASS
2017 12:20:32.111369 Write leveling : PASS
2018 12:20:32.114259 RX DQS gating : PASS
2019 12:20:32.117651 RX DQ/DQS(RDDQC) : PASS
2020 12:20:32.118063 TX DQ/DQS : PASS
2021 12:20:32.120884 RX DATLAT : PASS
2022 12:20:32.124280 RX DQ/DQS(Engine): PASS
2023 12:20:32.124690 TX OE : NO K
2024 12:20:32.125014 All Pass.
2025 12:20:32.127606
2026 12:20:32.128012 DramC Write-DBI off
2027 12:20:32.131117 PER_BANK_REFRESH: Hybrid Mode
2028 12:20:32.131529 TX_TRACKING: ON
2029 12:20:32.134327 [GetDramInforAfterCalByMRR] Vendor 6.
2030 12:20:32.137781 [GetDramInforAfterCalByMRR] Revision 606.
2031 12:20:32.144344 [GetDramInforAfterCalByMRR] Revision 2 0.
2032 12:20:32.144859 MR0 0x3939
2033 12:20:32.145192 MR8 0x1111
2034 12:20:32.147672 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2035 12:20:32.148236
2036 12:20:32.151081 MR0 0x3939
2037 12:20:32.151594 MR8 0x1111
2038 12:20:32.154275 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2039 12:20:32.154719
2040 12:20:32.164637 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2041 12:20:32.167459 [FAST_K] Save calibration result to emmc
2042 12:20:32.170878 [FAST_K] Save calibration result to emmc
2043 12:20:32.174495 dram_init: config_dvfs: 1
2044 12:20:32.177779 dramc_set_vcore_voltage set vcore to 662500
2045 12:20:32.178239 Read voltage for 1200, 2
2046 12:20:32.180961 Vio18 = 0
2047 12:20:32.181418 Vcore = 662500
2048 12:20:32.181776 Vdram = 0
2049 12:20:32.184738 Vddq = 0
2050 12:20:32.185192 Vmddr = 0
2051 12:20:32.190995 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2052 12:20:32.194059 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2053 12:20:32.197542 MEM_TYPE=3, freq_sel=15
2054 12:20:32.200785 sv_algorithm_assistance_LP4_1600
2055 12:20:32.204054 ============ PULL DRAM RESETB DOWN ============
2056 12:20:32.207614 ========== PULL DRAM RESETB DOWN end =========
2057 12:20:32.214433 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2058 12:20:32.217998 ===================================
2059 12:20:32.218560 LPDDR4 DRAM CONFIGURATION
2060 12:20:32.221153 ===================================
2061 12:20:32.224160 EX_ROW_EN[0] = 0x0
2062 12:20:32.224651 EX_ROW_EN[1] = 0x0
2063 12:20:32.227590 LP4Y_EN = 0x0
2064 12:20:32.228000 WORK_FSP = 0x0
2065 12:20:32.230908 WL = 0x4
2066 12:20:32.231319 RL = 0x4
2067 12:20:32.234230 BL = 0x2
2068 12:20:32.238178 RPST = 0x0
2069 12:20:32.238696 RD_PRE = 0x0
2070 12:20:32.240895 WR_PRE = 0x1
2071 12:20:32.241306 WR_PST = 0x0
2072 12:20:32.244460 DBI_WR = 0x0
2073 12:20:32.244975 DBI_RD = 0x0
2074 12:20:32.247618 OTF = 0x1
2075 12:20:32.251152 ===================================
2076 12:20:32.254121 ===================================
2077 12:20:32.254625 ANA top config
2078 12:20:32.257554 ===================================
2079 12:20:32.261122 DLL_ASYNC_EN = 0
2080 12:20:32.264412 ALL_SLAVE_EN = 0
2081 12:20:32.264870 NEW_RANK_MODE = 1
2082 12:20:32.267623 DLL_IDLE_MODE = 1
2083 12:20:32.270868 LP45_APHY_COMB_EN = 1
2084 12:20:32.274317 TX_ODT_DIS = 1
2085 12:20:32.274730 NEW_8X_MODE = 1
2086 12:20:32.277481 ===================================
2087 12:20:32.281032 ===================================
2088 12:20:32.284231 data_rate = 2400
2089 12:20:32.287412 CKR = 1
2090 12:20:32.290781 DQ_P2S_RATIO = 8
2091 12:20:32.294239 ===================================
2092 12:20:32.297670 CA_P2S_RATIO = 8
2093 12:20:32.301144 DQ_CA_OPEN = 0
2094 12:20:32.301556 DQ_SEMI_OPEN = 0
2095 12:20:32.304292 CA_SEMI_OPEN = 0
2096 12:20:32.307490 CA_FULL_RATE = 0
2097 12:20:32.310774 DQ_CKDIV4_EN = 0
2098 12:20:32.314194 CA_CKDIV4_EN = 0
2099 12:20:32.317407 CA_PREDIV_EN = 0
2100 12:20:32.317823 PH8_DLY = 17
2101 12:20:32.320703 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2102 12:20:32.324445 DQ_AAMCK_DIV = 4
2103 12:20:32.327956 CA_AAMCK_DIV = 4
2104 12:20:32.331212 CA_ADMCK_DIV = 4
2105 12:20:32.334339 DQ_TRACK_CA_EN = 0
2106 12:20:32.334905 CA_PICK = 1200
2107 12:20:32.337728 CA_MCKIO = 1200
2108 12:20:32.341091 MCKIO_SEMI = 0
2109 12:20:32.344854 PLL_FREQ = 2366
2110 12:20:32.348140 DQ_UI_PI_RATIO = 32
2111 12:20:32.351225 CA_UI_PI_RATIO = 0
2112 12:20:32.354262 ===================================
2113 12:20:32.357630 ===================================
2114 12:20:32.358085 memory_type:LPDDR4
2115 12:20:32.360918 GP_NUM : 10
2116 12:20:32.364742 SRAM_EN : 1
2117 12:20:32.365310 MD32_EN : 0
2118 12:20:32.367626 ===================================
2119 12:20:32.371121 [ANA_INIT] >>>>>>>>>>>>>>
2120 12:20:32.374456 <<<<<< [CONFIGURE PHASE]: ANA_TX
2121 12:20:32.377855 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2122 12:20:32.381109 ===================================
2123 12:20:32.384481 data_rate = 2400,PCW = 0X5b00
2124 12:20:32.387825 ===================================
2125 12:20:32.390897 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2126 12:20:32.393868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2127 12:20:32.400692 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2128 12:20:32.404134 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2129 12:20:32.407741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2130 12:20:32.410827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2131 12:20:32.414371 [ANA_INIT] flow start
2132 12:20:32.417374 [ANA_INIT] PLL >>>>>>>>
2133 12:20:32.417806 [ANA_INIT] PLL <<<<<<<<
2134 12:20:32.420876 [ANA_INIT] MIDPI >>>>>>>>
2135 12:20:32.424419 [ANA_INIT] MIDPI <<<<<<<<
2136 12:20:32.427699 [ANA_INIT] DLL >>>>>>>>
2137 12:20:32.428296 [ANA_INIT] DLL <<<<<<<<
2138 12:20:32.430964 [ANA_INIT] flow end
2139 12:20:32.434297 ============ LP4 DIFF to SE enter ============
2140 12:20:32.438003 ============ LP4 DIFF to SE exit ============
2141 12:20:32.440770 [ANA_INIT] <<<<<<<<<<<<<
2142 12:20:32.444479 [Flow] Enable top DCM control >>>>>
2143 12:20:32.447947 [Flow] Enable top DCM control <<<<<
2144 12:20:32.450828 Enable DLL master slave shuffle
2145 12:20:32.454398 ==============================================================
2146 12:20:32.457637 Gating Mode config
2147 12:20:32.464464 ==============================================================
2148 12:20:32.464985 Config description:
2149 12:20:32.474278 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2150 12:20:32.480851 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2151 12:20:32.487771 SELPH_MODE 0: By rank 1: By Phase
2152 12:20:32.491123 ==============================================================
2153 12:20:32.494300 GAT_TRACK_EN = 1
2154 12:20:32.497272 RX_GATING_MODE = 2
2155 12:20:32.500929 RX_GATING_TRACK_MODE = 2
2156 12:20:32.504232 SELPH_MODE = 1
2157 12:20:32.507566 PICG_EARLY_EN = 1
2158 12:20:32.510789 VALID_LAT_VALUE = 1
2159 12:20:32.514065 ==============================================================
2160 12:20:32.517319 Enter into Gating configuration >>>>
2161 12:20:32.520697 Exit from Gating configuration <<<<
2162 12:20:32.523914 Enter into DVFS_PRE_config >>>>>
2163 12:20:32.537243 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2164 12:20:32.537661 Exit from DVFS_PRE_config <<<<<
2165 12:20:32.540490 Enter into PICG configuration >>>>
2166 12:20:32.543874 Exit from PICG configuration <<<<
2167 12:20:32.547659 [RX_INPUT] configuration >>>>>
2168 12:20:32.551198 [RX_INPUT] configuration <<<<<
2169 12:20:32.557217 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2170 12:20:32.560787 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2171 12:20:32.567387 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2172 12:20:32.573683 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2173 12:20:32.580410 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2174 12:20:32.587379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2175 12:20:32.590896 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2176 12:20:32.594344 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2177 12:20:32.597385 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2178 12:20:32.603833 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2179 12:20:32.607112 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2180 12:20:32.610406 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2181 12:20:32.614135 ===================================
2182 12:20:32.617534 LPDDR4 DRAM CONFIGURATION
2183 12:20:32.620555 ===================================
2184 12:20:32.621019 EX_ROW_EN[0] = 0x0
2185 12:20:32.624002 EX_ROW_EN[1] = 0x0
2186 12:20:32.627234 LP4Y_EN = 0x0
2187 12:20:32.627799 WORK_FSP = 0x0
2188 12:20:32.630990 WL = 0x4
2189 12:20:32.631551 RL = 0x4
2190 12:20:32.633982 BL = 0x2
2191 12:20:32.634543 RPST = 0x0
2192 12:20:32.637629 RD_PRE = 0x0
2193 12:20:32.638189 WR_PRE = 0x1
2194 12:20:32.640350 WR_PST = 0x0
2195 12:20:32.640812 DBI_WR = 0x0
2196 12:20:32.643978 DBI_RD = 0x0
2197 12:20:32.644593 OTF = 0x1
2198 12:20:32.646845 ===================================
2199 12:20:32.650579 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2200 12:20:32.657186 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2201 12:20:32.660525 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 12:20:32.663798 ===================================
2203 12:20:32.667084 LPDDR4 DRAM CONFIGURATION
2204 12:20:32.670223 ===================================
2205 12:20:32.670684 EX_ROW_EN[0] = 0x10
2206 12:20:32.673690 EX_ROW_EN[1] = 0x0
2207 12:20:32.674144 LP4Y_EN = 0x0
2208 12:20:32.677042 WORK_FSP = 0x0
2209 12:20:32.680527 WL = 0x4
2210 12:20:32.681083 RL = 0x4
2211 12:20:32.683861 BL = 0x2
2212 12:20:32.684457 RPST = 0x0
2213 12:20:32.687201 RD_PRE = 0x0
2214 12:20:32.687753 WR_PRE = 0x1
2215 12:20:32.690547 WR_PST = 0x0
2216 12:20:32.691103 DBI_WR = 0x0
2217 12:20:32.693569 DBI_RD = 0x0
2218 12:20:32.694028 OTF = 0x1
2219 12:20:32.696743 ===================================
2220 12:20:32.703621 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2221 12:20:32.704083 ==
2222 12:20:32.707021 Dram Type= 6, Freq= 0, CH_0, rank 0
2223 12:20:32.710341 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2224 12:20:32.710802 ==
2225 12:20:32.713848 [Duty_Offset_Calibration]
2226 12:20:32.717085 B0:0 B1:2 CA:1
2227 12:20:32.717542
2228 12:20:32.720281 [DutyScan_Calibration_Flow] k_type=0
2229 12:20:32.728492
2230 12:20:32.729043 ==CLK 0==
2231 12:20:32.731768 Final CLK duty delay cell = 0
2232 12:20:32.735258 [0] MAX Duty = 5093%(X100), DQS PI = 12
2233 12:20:32.738457 [0] MIN Duty = 4938%(X100), DQS PI = 54
2234 12:20:32.738917 [0] AVG Duty = 5015%(X100)
2235 12:20:32.739277
2236 12:20:32.741901 CH0 CLK Duty spec in!! Max-Min= 155%
2237 12:20:32.748578 [DutyScan_Calibration_Flow] ====Done====
2238 12:20:32.749131
2239 12:20:32.751506 [DutyScan_Calibration_Flow] k_type=1
2240 12:20:32.767862
2241 12:20:32.768455 ==DQS 0 ==
2242 12:20:32.770779 Final DQS duty delay cell = 0
2243 12:20:32.774550 [0] MAX Duty = 5125%(X100), DQS PI = 30
2244 12:20:32.777732 [0] MIN Duty = 5031%(X100), DQS PI = 6
2245 12:20:32.778315 [0] AVG Duty = 5078%(X100)
2246 12:20:32.781131
2247 12:20:32.781688 ==DQS 1 ==
2248 12:20:32.784282 Final DQS duty delay cell = 0
2249 12:20:32.787645 [0] MAX Duty = 5062%(X100), DQS PI = 56
2250 12:20:32.790813 [0] MIN Duty = 4906%(X100), DQS PI = 16
2251 12:20:32.791271 [0] AVG Duty = 4984%(X100)
2252 12:20:32.794134
2253 12:20:32.797545 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2254 12:20:32.798002
2255 12:20:32.800608 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2256 12:20:32.804078 [DutyScan_Calibration_Flow] ====Done====
2257 12:20:32.804558
2258 12:20:32.807357 [DutyScan_Calibration_Flow] k_type=3
2259 12:20:32.824721
2260 12:20:32.825256 ==DQM 0 ==
2261 12:20:32.828529 Final DQM duty delay cell = 0
2262 12:20:32.831386 [0] MAX Duty = 5187%(X100), DQS PI = 22
2263 12:20:32.834829 [0] MIN Duty = 4969%(X100), DQS PI = 40
2264 12:20:32.835288 [0] AVG Duty = 5078%(X100)
2265 12:20:32.838226
2266 12:20:32.838679 ==DQM 1 ==
2267 12:20:32.841788 Final DQM duty delay cell = 4
2268 12:20:32.844927 [4] MAX Duty = 5187%(X100), DQS PI = 54
2269 12:20:32.848107 [4] MIN Duty = 5000%(X100), DQS PI = 18
2270 12:20:32.848545 [4] AVG Duty = 5093%(X100)
2271 12:20:32.851504
2272 12:20:32.854802 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2273 12:20:32.855216
2274 12:20:32.858347 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2275 12:20:32.861862 [DutyScan_Calibration_Flow] ====Done====
2276 12:20:32.862273
2277 12:20:32.864749 [DutyScan_Calibration_Flow] k_type=2
2278 12:20:32.879795
2279 12:20:32.880368 ==DQ 0 ==
2280 12:20:32.883457 Final DQ duty delay cell = -4
2281 12:20:32.886800 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2282 12:20:32.889783 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2283 12:20:32.893137 [-4] AVG Duty = 4937%(X100)
2284 12:20:32.893595
2285 12:20:32.893954 ==DQ 1 ==
2286 12:20:32.896434 Final DQ duty delay cell = -4
2287 12:20:32.899678 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2288 12:20:32.903120 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2289 12:20:32.906398 [-4] AVG Duty = 4969%(X100)
2290 12:20:32.906858
2291 12:20:32.909679 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2292 12:20:32.910155
2293 12:20:32.912835 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2294 12:20:32.916493 [DutyScan_Calibration_Flow] ====Done====
2295 12:20:32.916910 ==
2296 12:20:32.919687 Dram Type= 6, Freq= 0, CH_1, rank 0
2297 12:20:32.922981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2298 12:20:32.923399 ==
2299 12:20:32.926337 [Duty_Offset_Calibration]
2300 12:20:32.926754 B0:0 B1:4 CA:-5
2301 12:20:32.927082
2302 12:20:32.929513 [DutyScan_Calibration_Flow] k_type=0
2303 12:20:32.940372
2304 12:20:32.940780 ==CLK 0==
2305 12:20:32.943641 Final CLK duty delay cell = 0
2306 12:20:32.946822 [0] MAX Duty = 5094%(X100), DQS PI = 24
2307 12:20:32.950574 [0] MIN Duty = 4907%(X100), DQS PI = 0
2308 12:20:32.951089 [0] AVG Duty = 5000%(X100)
2309 12:20:32.953559
2310 12:20:32.953970 CH1 CLK Duty spec in!! Max-Min= 187%
2311 12:20:32.960460 [DutyScan_Calibration_Flow] ====Done====
2312 12:20:32.960962
2313 12:20:32.964135 [DutyScan_Calibration_Flow] k_type=1
2314 12:20:32.979080
2315 12:20:32.979641 ==DQS 0 ==
2316 12:20:32.982172 Final DQS duty delay cell = 0
2317 12:20:32.985403 [0] MAX Duty = 5125%(X100), DQS PI = 16
2318 12:20:32.988787 [0] MIN Duty = 4875%(X100), DQS PI = 40
2319 12:20:32.992584 [0] AVG Duty = 5000%(X100)
2320 12:20:32.993144
2321 12:20:32.993506 ==DQS 1 ==
2322 12:20:32.995674 Final DQS duty delay cell = -4
2323 12:20:32.998758 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2324 12:20:33.002163 [-4] MIN Duty = 4907%(X100), DQS PI = 40
2325 12:20:33.005217 [-4] AVG Duty = 4953%(X100)
2326 12:20:33.005826
2327 12:20:33.008483 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2328 12:20:33.008941
2329 12:20:33.011829 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2330 12:20:33.015394 [DutyScan_Calibration_Flow] ====Done====
2331 12:20:33.015979
2332 12:20:33.018575 [DutyScan_Calibration_Flow] k_type=3
2333 12:20:33.033907
2334 12:20:33.034483 ==DQM 0 ==
2335 12:20:33.037366 Final DQM duty delay cell = -4
2336 12:20:33.040485 [-4] MAX Duty = 5062%(X100), DQS PI = 30
2337 12:20:33.044071 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2338 12:20:33.047750 [-4] AVG Duty = 4953%(X100)
2339 12:20:33.048318
2340 12:20:33.048655 ==DQM 1 ==
2341 12:20:33.050755 Final DQM duty delay cell = -4
2342 12:20:33.053706 [-4] MAX Duty = 5062%(X100), DQS PI = 2
2343 12:20:33.057478 [-4] MIN Duty = 4907%(X100), DQS PI = 58
2344 12:20:33.060804 [-4] AVG Duty = 4984%(X100)
2345 12:20:33.061216
2346 12:20:33.063945 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2347 12:20:33.064511
2348 12:20:33.067290 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2349 12:20:33.070336 [DutyScan_Calibration_Flow] ====Done====
2350 12:20:33.070751
2351 12:20:33.073795 [DutyScan_Calibration_Flow] k_type=2
2352 12:20:33.091381
2353 12:20:33.091937 ==DQ 0 ==
2354 12:20:33.094422 Final DQ duty delay cell = 0
2355 12:20:33.097890 [0] MAX Duty = 5062%(X100), DQS PI = 0
2356 12:20:33.101092 [0] MIN Duty = 4938%(X100), DQS PI = 44
2357 12:20:33.101550 [0] AVG Duty = 5000%(X100)
2358 12:20:33.104239
2359 12:20:33.104696 ==DQ 1 ==
2360 12:20:33.107586 Final DQ duty delay cell = 0
2361 12:20:33.110934 [0] MAX Duty = 5000%(X100), DQS PI = 8
2362 12:20:33.114283 [0] MIN Duty = 4875%(X100), DQS PI = 32
2363 12:20:33.114695 [0] AVG Duty = 4937%(X100)
2364 12:20:33.115017
2365 12:20:33.117980 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2366 12:20:33.118390
2367 12:20:33.121144 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2368 12:20:33.127463 [DutyScan_Calibration_Flow] ====Done====
2369 12:20:33.131007 nWR fixed to 30
2370 12:20:33.131419 [ModeRegInit_LP4] CH0 RK0
2371 12:20:33.134600 [ModeRegInit_LP4] CH0 RK1
2372 12:20:33.137455 [ModeRegInit_LP4] CH1 RK0
2373 12:20:33.137862 [ModeRegInit_LP4] CH1 RK1
2374 12:20:33.140814 match AC timing 6
2375 12:20:33.144305 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2376 12:20:33.147822 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2377 12:20:33.154467 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2378 12:20:33.157562 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2379 12:20:33.164291 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2380 12:20:33.164705 ==
2381 12:20:33.167618 Dram Type= 6, Freq= 0, CH_0, rank 0
2382 12:20:33.171250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2383 12:20:33.171770 ==
2384 12:20:33.177460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2385 12:20:33.180873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2386 12:20:33.191144 [CA 0] Center 39 (9~70) winsize 62
2387 12:20:33.194396 [CA 1] Center 39 (8~70) winsize 63
2388 12:20:33.197402 [CA 2] Center 36 (5~67) winsize 63
2389 12:20:33.200746 [CA 3] Center 35 (4~66) winsize 63
2390 12:20:33.204003 [CA 4] Center 34 (3~65) winsize 63
2391 12:20:33.207391 [CA 5] Center 33 (3~64) winsize 62
2392 12:20:33.207843
2393 12:20:33.210783 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2394 12:20:33.211235
2395 12:20:33.213913 [CATrainingPosCal] consider 1 rank data
2396 12:20:33.217158 u2DelayCellTimex100 = 270/100 ps
2397 12:20:33.220550 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2398 12:20:33.227286 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2399 12:20:33.230859 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2400 12:20:33.234224 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2401 12:20:33.237303 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2402 12:20:33.240564 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2403 12:20:33.240975
2404 12:20:33.244150 CA PerBit enable=1, Macro0, CA PI delay=33
2405 12:20:33.244711
2406 12:20:33.247347 [CBTSetCACLKResult] CA Dly = 33
2407 12:20:33.247868 CS Dly: 7 (0~38)
2408 12:20:33.250989 ==
2409 12:20:33.251506 Dram Type= 6, Freq= 0, CH_0, rank 1
2410 12:20:33.257225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2411 12:20:33.257754 ==
2412 12:20:33.260603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2413 12:20:33.267361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2414 12:20:33.276339 [CA 0] Center 39 (9~70) winsize 62
2415 12:20:33.279821 [CA 1] Center 39 (8~70) winsize 63
2416 12:20:33.282908 [CA 2] Center 35 (5~66) winsize 62
2417 12:20:33.286164 [CA 3] Center 35 (4~66) winsize 63
2418 12:20:33.289678 [CA 4] Center 33 (3~64) winsize 62
2419 12:20:33.293305 [CA 5] Center 33 (3~64) winsize 62
2420 12:20:33.293821
2421 12:20:33.296002 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2422 12:20:33.296489
2423 12:20:33.299531 [CATrainingPosCal] consider 2 rank data
2424 12:20:33.302846 u2DelayCellTimex100 = 270/100 ps
2425 12:20:33.306120 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2426 12:20:33.309496 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2427 12:20:33.316145 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2428 12:20:33.319515 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2429 12:20:33.322916 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2430 12:20:33.326061 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2431 12:20:33.326521
2432 12:20:33.329492 CA PerBit enable=1, Macro0, CA PI delay=33
2433 12:20:33.329902
2434 12:20:33.332658 [CBTSetCACLKResult] CA Dly = 33
2435 12:20:33.333065 CS Dly: 7 (0~39)
2436 12:20:33.333387
2437 12:20:33.336004 ----->DramcWriteLeveling(PI) begin...
2438 12:20:33.339327 ==
2439 12:20:33.342975 Dram Type= 6, Freq= 0, CH_0, rank 0
2440 12:20:33.346242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2441 12:20:33.346756 ==
2442 12:20:33.349691 Write leveling (Byte 0): 27 => 27
2443 12:20:33.352874 Write leveling (Byte 1): 25 => 25
2444 12:20:33.356108 DramcWriteLeveling(PI) end<-----
2445 12:20:33.356659
2446 12:20:33.356987 ==
2447 12:20:33.359155 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 12:20:33.363078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2449 12:20:33.363490 ==
2450 12:20:33.366196 [Gating] SW mode calibration
2451 12:20:33.372729 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2452 12:20:33.376514 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2453 12:20:33.383011 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2454 12:20:33.385971 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2455 12:20:33.389853 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2456 12:20:33.396026 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2457 12:20:33.399295 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2458 12:20:33.402815 0 11 20 | B1->B0 | 2c2c 2828 | 0 0 | (1 0) (0 0)
2459 12:20:33.409311 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2460 12:20:33.412646 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2461 12:20:33.416013 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2462 12:20:33.423445 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2463 12:20:33.426174 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 12:20:33.429220 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2465 12:20:33.435903 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2466 12:20:33.439239 0 12 20 | B1->B0 | 3535 4040 | 0 1 | (0 0) (0 0)
2467 12:20:33.442949 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2468 12:20:33.449518 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2469 12:20:33.452648 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2470 12:20:33.456036 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 12:20:33.462369 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2472 12:20:33.465905 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2473 12:20:33.469034 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2474 12:20:33.475567 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2475 12:20:33.479070 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 12:20:33.482675 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 12:20:33.485697 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 12:20:33.492603 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 12:20:33.495850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 12:20:33.499068 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 12:20:33.505966 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 12:20:33.509195 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 12:20:33.512895 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 12:20:33.519025 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 12:20:33.522852 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 12:20:33.526117 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 12:20:33.532732 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 12:20:33.536098 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2489 12:20:33.539290 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2490 12:20:33.546315 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2491 12:20:33.546873 Total UI for P1: 0, mck2ui 16
2492 12:20:33.552801 best dqsien dly found for B0: ( 0, 15, 16)
2493 12:20:33.553354 Total UI for P1: 0, mck2ui 16
2494 12:20:33.556340 best dqsien dly found for B1: ( 0, 15, 18)
2495 12:20:33.563016 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2496 12:20:33.566231 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2497 12:20:33.566787
2498 12:20:33.569339 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2499 12:20:33.572648 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2500 12:20:33.575939 [Gating] SW calibration Done
2501 12:20:33.576423 ==
2502 12:20:33.579512 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 12:20:33.582598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2504 12:20:33.583052 ==
2505 12:20:33.586132 RX Vref Scan: 0
2506 12:20:33.586583
2507 12:20:33.586940 RX Vref 0 -> 0, step: 1
2508 12:20:33.587270
2509 12:20:33.589590 RX Delay -40 -> 252, step: 8
2510 12:20:33.593060 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2511 12:20:33.599570 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2512 12:20:33.602602 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2513 12:20:33.606046 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2514 12:20:33.609198 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2515 12:20:33.612832 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2516 12:20:33.616043 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2517 12:20:33.622649 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2518 12:20:33.625980 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2519 12:20:33.629354 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2520 12:20:33.633056 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2521 12:20:33.636091 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2522 12:20:33.643085 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2523 12:20:33.646155 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2524 12:20:33.649400 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2525 12:20:33.653048 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2526 12:20:33.653565 ==
2527 12:20:33.656287 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 12:20:33.662879 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2529 12:20:33.663382 ==
2530 12:20:33.663706 DQS Delay:
2531 12:20:33.664007 DQS0 = 0, DQS1 = 0
2532 12:20:33.666301 DQM Delay:
2533 12:20:33.666809 DQM0 = 116, DQM1 = 106
2534 12:20:33.669613 DQ Delay:
2535 12:20:33.672940 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =115
2536 12:20:33.676078 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2537 12:20:33.679477 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2538 12:20:33.682963 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2539 12:20:33.683374
2540 12:20:33.683693
2541 12:20:33.683991 ==
2542 12:20:33.686234 Dram Type= 6, Freq= 0, CH_0, rank 0
2543 12:20:33.689605 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2544 12:20:33.690118 ==
2545 12:20:33.692891
2546 12:20:33.693444
2547 12:20:33.693777 TX Vref Scan disable
2548 12:20:33.696021 == TX Byte 0 ==
2549 12:20:33.699530 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2550 12:20:33.703108 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2551 12:20:33.706018 == TX Byte 1 ==
2552 12:20:33.709283 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2553 12:20:33.712697 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2554 12:20:33.713107 ==
2555 12:20:33.715977 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 12:20:33.722586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2557 12:20:33.722997 ==
2558 12:20:33.733218 TX Vref=22, minBit 8, minWin=24, winSum=412
2559 12:20:33.736448 TX Vref=24, minBit 8, minWin=25, winSum=422
2560 12:20:33.739896 TX Vref=26, minBit 10, minWin=25, winSum=423
2561 12:20:33.743328 TX Vref=28, minBit 8, minWin=26, winSum=433
2562 12:20:33.746789 TX Vref=30, minBit 9, minWin=26, winSum=436
2563 12:20:33.753411 TX Vref=32, minBit 4, minWin=26, winSum=433
2564 12:20:33.756453 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
2565 12:20:33.756913
2566 12:20:33.760121 Final TX Range 1 Vref 30
2567 12:20:33.760881
2568 12:20:33.761303 ==
2569 12:20:33.763368 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 12:20:33.766886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2571 12:20:33.767444 ==
2572 12:20:33.769838
2573 12:20:33.770286
2574 12:20:33.770644 TX Vref Scan disable
2575 12:20:33.773337 == TX Byte 0 ==
2576 12:20:33.776644 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2577 12:20:33.779907 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2578 12:20:33.783443 == TX Byte 1 ==
2579 12:20:33.786756 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2580 12:20:33.790178 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2581 12:20:33.790688
2582 12:20:33.793390 [DATLAT]
2583 12:20:33.793905 Freq=1200, CH0 RK0
2584 12:20:33.794235
2585 12:20:33.796401 DATLAT Default: 0xd
2586 12:20:33.796831 0, 0xFFFF, sum = 0
2587 12:20:33.800032 1, 0xFFFF, sum = 0
2588 12:20:33.800601 2, 0xFFFF, sum = 0
2589 12:20:33.803302 3, 0xFFFF, sum = 0
2590 12:20:33.803725 4, 0xFFFF, sum = 0
2591 12:20:33.806760 5, 0xFFFF, sum = 0
2592 12:20:33.807173 6, 0xFFFF, sum = 0
2593 12:20:33.809868 7, 0xFFFF, sum = 0
2594 12:20:33.810291 8, 0xFFFF, sum = 0
2595 12:20:33.813197 9, 0xFFFF, sum = 0
2596 12:20:33.816678 10, 0xFFFF, sum = 0
2597 12:20:33.817139 11, 0x0, sum = 1
2598 12:20:33.817501 12, 0x0, sum = 2
2599 12:20:33.819923 13, 0x0, sum = 3
2600 12:20:33.820418 14, 0x0, sum = 4
2601 12:20:33.823015 best_step = 12
2602 12:20:33.823462
2603 12:20:33.823817 ==
2604 12:20:33.827150 Dram Type= 6, Freq= 0, CH_0, rank 0
2605 12:20:33.829890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2606 12:20:33.830300 ==
2607 12:20:33.833159 RX Vref Scan: 1
2608 12:20:33.833567
2609 12:20:33.833885 Set Vref Range= 32 -> 127
2610 12:20:33.836549
2611 12:20:33.836957 RX Vref 32 -> 127, step: 1
2612 12:20:33.837283
2613 12:20:33.839898 RX Delay -21 -> 252, step: 4
2614 12:20:33.840340
2615 12:20:33.843218 Set Vref, RX VrefLevel [Byte0]: 32
2616 12:20:33.846395 [Byte1]: 32
2617 12:20:33.849627
2618 12:20:33.850037 Set Vref, RX VrefLevel [Byte0]: 33
2619 12:20:33.853151 [Byte1]: 33
2620 12:20:33.857925
2621 12:20:33.858438 Set Vref, RX VrefLevel [Byte0]: 34
2622 12:20:33.860791 [Byte1]: 34
2623 12:20:33.865648
2624 12:20:33.866159 Set Vref, RX VrefLevel [Byte0]: 35
2625 12:20:33.869018 [Byte1]: 35
2626 12:20:33.873825
2627 12:20:33.874338 Set Vref, RX VrefLevel [Byte0]: 36
2628 12:20:33.877216 [Byte1]: 36
2629 12:20:33.881565
2630 12:20:33.882084 Set Vref, RX VrefLevel [Byte0]: 37
2631 12:20:33.885059 [Byte1]: 37
2632 12:20:33.889583
2633 12:20:33.890108 Set Vref, RX VrefLevel [Byte0]: 38
2634 12:20:33.892765 [Byte1]: 38
2635 12:20:33.897290
2636 12:20:33.897765 Set Vref, RX VrefLevel [Byte0]: 39
2637 12:20:33.900886 [Byte1]: 39
2638 12:20:33.905105
2639 12:20:33.905561 Set Vref, RX VrefLevel [Byte0]: 40
2640 12:20:33.908426 [Byte1]: 40
2641 12:20:33.913054
2642 12:20:33.913508 Set Vref, RX VrefLevel [Byte0]: 41
2643 12:20:33.916590 [Byte1]: 41
2644 12:20:33.921069
2645 12:20:33.921522 Set Vref, RX VrefLevel [Byte0]: 42
2646 12:20:33.924065 [Byte1]: 42
2647 12:20:33.929165
2648 12:20:33.929616 Set Vref, RX VrefLevel [Byte0]: 43
2649 12:20:33.932238 [Byte1]: 43
2650 12:20:33.936895
2651 12:20:33.937304 Set Vref, RX VrefLevel [Byte0]: 44
2652 12:20:33.940221 [Byte1]: 44
2653 12:20:33.944830
2654 12:20:33.945240 Set Vref, RX VrefLevel [Byte0]: 45
2655 12:20:33.948029 [Byte1]: 45
2656 12:20:33.952870
2657 12:20:33.953280 Set Vref, RX VrefLevel [Byte0]: 46
2658 12:20:33.955922 [Byte1]: 46
2659 12:20:33.960648
2660 12:20:33.961059 Set Vref, RX VrefLevel [Byte0]: 47
2661 12:20:33.964032 [Byte1]: 47
2662 12:20:33.968813
2663 12:20:33.969224 Set Vref, RX VrefLevel [Byte0]: 48
2664 12:20:33.971858 [Byte1]: 48
2665 12:20:33.976583
2666 12:20:33.976993 Set Vref, RX VrefLevel [Byte0]: 49
2667 12:20:33.980018 [Byte1]: 49
2668 12:20:33.984470
2669 12:20:33.984879 Set Vref, RX VrefLevel [Byte0]: 50
2670 12:20:33.987761 [Byte1]: 50
2671 12:20:33.992773
2672 12:20:33.993299 Set Vref, RX VrefLevel [Byte0]: 51
2673 12:20:33.995926 [Byte1]: 51
2674 12:20:34.000086
2675 12:20:34.000546 Set Vref, RX VrefLevel [Byte0]: 52
2676 12:20:34.003640 [Byte1]: 52
2677 12:20:34.008424
2678 12:20:34.008835 Set Vref, RX VrefLevel [Byte0]: 53
2679 12:20:34.011544 [Byte1]: 53
2680 12:20:34.015952
2681 12:20:34.016458 Set Vref, RX VrefLevel [Byte0]: 54
2682 12:20:34.019350 [Byte1]: 54
2683 12:20:34.023913
2684 12:20:34.024346 Set Vref, RX VrefLevel [Byte0]: 55
2685 12:20:34.027138 [Byte1]: 55
2686 12:20:34.032024
2687 12:20:34.032463 Set Vref, RX VrefLevel [Byte0]: 56
2688 12:20:34.035290 [Byte1]: 56
2689 12:20:34.040239
2690 12:20:34.040651 Set Vref, RX VrefLevel [Byte0]: 57
2691 12:20:34.043256 [Byte1]: 57
2692 12:20:34.047693
2693 12:20:34.048106 Set Vref, RX VrefLevel [Byte0]: 58
2694 12:20:34.050972 [Byte1]: 58
2695 12:20:34.055827
2696 12:20:34.056270 Set Vref, RX VrefLevel [Byte0]: 59
2697 12:20:34.058953 [Byte1]: 59
2698 12:20:34.063690
2699 12:20:34.064101 Set Vref, RX VrefLevel [Byte0]: 60
2700 12:20:34.067246 [Byte1]: 60
2701 12:20:34.071899
2702 12:20:34.072456 Set Vref, RX VrefLevel [Byte0]: 61
2703 12:20:34.074975 [Byte1]: 61
2704 12:20:34.079598
2705 12:20:34.080110 Set Vref, RX VrefLevel [Byte0]: 62
2706 12:20:34.082915 [Byte1]: 62
2707 12:20:34.087575
2708 12:20:34.088089 Set Vref, RX VrefLevel [Byte0]: 63
2709 12:20:34.090738 [Byte1]: 63
2710 12:20:34.095368
2711 12:20:34.095780 Set Vref, RX VrefLevel [Byte0]: 64
2712 12:20:34.098448 [Byte1]: 64
2713 12:20:34.103174
2714 12:20:34.103584 Set Vref, RX VrefLevel [Byte0]: 65
2715 12:20:34.106560 [Byte1]: 65
2716 12:20:34.111164
2717 12:20:34.111522 Set Vref, RX VrefLevel [Byte0]: 66
2718 12:20:34.114095 [Byte1]: 66
2719 12:20:34.118987
2720 12:20:34.119094 Final RX Vref Byte 0 = 50 to rank0
2721 12:20:34.121907 Final RX Vref Byte 1 = 46 to rank0
2722 12:20:34.125579 Final RX Vref Byte 0 = 50 to rank1
2723 12:20:34.128789 Final RX Vref Byte 1 = 46 to rank1==
2724 12:20:34.132298 Dram Type= 6, Freq= 0, CH_0, rank 0
2725 12:20:34.138716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2726 12:20:34.138798 ==
2727 12:20:34.138863 DQS Delay:
2728 12:20:34.138921 DQS0 = 0, DQS1 = 0
2729 12:20:34.142192 DQM Delay:
2730 12:20:34.142271 DQM0 = 114, DQM1 = 105
2731 12:20:34.145367 DQ Delay:
2732 12:20:34.148712 DQ0 =110, DQ1 =114, DQ2 =114, DQ3 =110
2733 12:20:34.151957 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =122
2734 12:20:34.155322 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2735 12:20:34.158608 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2736 12:20:34.158689
2737 12:20:34.158751
2738 12:20:34.165347 [DQSOSCAuto] RK0, (LSB)MR18= 0x404, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
2739 12:20:34.168933 CH0 RK0: MR19=404, MR18=404
2740 12:20:34.175477 CH0_RK0: MR19=0x404, MR18=0x404, DQSOSC=408, MR23=63, INC=39, DEC=26
2741 12:20:34.175557
2742 12:20:34.178432 ----->DramcWriteLeveling(PI) begin...
2743 12:20:34.178514 ==
2744 12:20:34.182066 Dram Type= 6, Freq= 0, CH_0, rank 1
2745 12:20:34.185270 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2746 12:20:34.185350 ==
2747 12:20:34.188968 Write leveling (Byte 0): 27 => 27
2748 12:20:34.192035 Write leveling (Byte 1): 26 => 26
2749 12:20:34.195576 DramcWriteLeveling(PI) end<-----
2750 12:20:34.195656
2751 12:20:34.195719 ==
2752 12:20:34.198540 Dram Type= 6, Freq= 0, CH_0, rank 1
2753 12:20:34.201940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2754 12:20:34.205396 ==
2755 12:20:34.205476 [Gating] SW mode calibration
2756 12:20:34.215392 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2757 12:20:34.218815 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2758 12:20:34.222078 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2759 12:20:34.228704 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2760 12:20:34.232024 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2761 12:20:34.235274 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2762 12:20:34.241994 0 11 16 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
2763 12:20:34.245349 0 11 20 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (1 0)
2764 12:20:34.248932 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2765 12:20:34.255613 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2766 12:20:34.258682 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2767 12:20:34.261990 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2768 12:20:34.268716 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2769 12:20:34.272034 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2770 12:20:34.275253 0 12 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
2771 12:20:34.278685 0 12 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2772 12:20:34.285351 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2773 12:20:34.288652 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2774 12:20:34.291921 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2775 12:20:34.298758 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2776 12:20:34.302042 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2777 12:20:34.305155 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2778 12:20:34.311927 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2779 12:20:34.315325 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2780 12:20:34.318540 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2781 12:20:34.325123 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 12:20:34.328829 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 12:20:34.331827 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 12:20:34.338582 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 12:20:34.341699 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 12:20:34.345051 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2787 12:20:34.351843 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 12:20:34.355354 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 12:20:34.358798 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 12:20:34.364991 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 12:20:34.368522 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 12:20:34.372023 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 12:20:34.378294 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 12:20:34.381990 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2795 12:20:34.384996 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2796 12:20:34.392045 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2797 12:20:34.392127 Total UI for P1: 0, mck2ui 16
2798 12:20:34.395043 best dqsien dly found for B0: ( 0, 15, 18)
2799 12:20:34.398233 Total UI for P1: 0, mck2ui 16
2800 12:20:34.402014 best dqsien dly found for B1: ( 0, 15, 18)
2801 12:20:34.405074 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2802 12:20:34.411759 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2803 12:20:34.411841
2804 12:20:34.415072 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2805 12:20:34.418506 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2806 12:20:34.421711 [Gating] SW calibration Done
2807 12:20:34.421792 ==
2808 12:20:34.424983 Dram Type= 6, Freq= 0, CH_0, rank 1
2809 12:20:34.428485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2810 12:20:34.428567 ==
2811 12:20:34.431956 RX Vref Scan: 0
2812 12:20:34.432037
2813 12:20:34.432100 RX Vref 0 -> 0, step: 1
2814 12:20:34.432160
2815 12:20:34.435133 RX Delay -40 -> 252, step: 8
2816 12:20:34.438600 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2817 12:20:34.441911 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2818 12:20:34.448393 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2819 12:20:34.451823 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2820 12:20:34.455333 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2821 12:20:34.458416 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2822 12:20:34.461822 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2823 12:20:34.468313 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2824 12:20:34.471843 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2825 12:20:34.475063 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2826 12:20:34.478462 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2827 12:20:34.481594 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2828 12:20:34.488555 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2829 12:20:34.491696 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2830 12:20:34.495104 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2831 12:20:34.498490 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2832 12:20:34.498571 ==
2833 12:20:34.501778 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 12:20:34.505279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2835 12:20:34.508641 ==
2836 12:20:34.508721 DQS Delay:
2837 12:20:34.508784 DQS0 = 0, DQS1 = 0
2838 12:20:34.511835 DQM Delay:
2839 12:20:34.511914 DQM0 = 116, DQM1 = 106
2840 12:20:34.515181 DQ Delay:
2841 12:20:34.518626 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =111
2842 12:20:34.521797 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2843 12:20:34.525519 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2844 12:20:34.528412 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2845 12:20:34.528491
2846 12:20:34.528553
2847 12:20:34.528612 ==
2848 12:20:34.532210 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 12:20:34.535205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2850 12:20:34.535284 ==
2851 12:20:34.535347
2852 12:20:34.535405
2853 12:20:34.538691 TX Vref Scan disable
2854 12:20:34.542022 == TX Byte 0 ==
2855 12:20:34.545350 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2856 12:20:34.548692 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2857 12:20:34.551856 == TX Byte 1 ==
2858 12:20:34.555289 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2859 12:20:34.558453 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2860 12:20:34.558533 ==
2861 12:20:34.561817 Dram Type= 6, Freq= 0, CH_0, rank 1
2862 12:20:34.565281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2863 12:20:34.568208 ==
2864 12:20:34.578448 TX Vref=22, minBit 8, minWin=25, winSum=414
2865 12:20:34.582004 TX Vref=24, minBit 1, minWin=26, winSum=424
2866 12:20:34.585192 TX Vref=26, minBit 1, minWin=26, winSum=426
2867 12:20:34.588607 TX Vref=28, minBit 5, minWin=26, winSum=432
2868 12:20:34.591815 TX Vref=30, minBit 12, minWin=26, winSum=436
2869 12:20:34.595397 TX Vref=32, minBit 8, minWin=26, winSum=437
2870 12:20:34.602079 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 32
2871 12:20:34.602159
2872 12:20:34.605080 Final TX Range 1 Vref 32
2873 12:20:34.605160
2874 12:20:34.605222 ==
2875 12:20:34.608665 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 12:20:34.611856 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2877 12:20:34.611938 ==
2878 12:20:34.612002
2879 12:20:34.615495
2880 12:20:34.615575 TX Vref Scan disable
2881 12:20:34.618453 == TX Byte 0 ==
2882 12:20:34.621832 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2883 12:20:34.625012 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2884 12:20:34.628378 == TX Byte 1 ==
2885 12:20:34.631788 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2886 12:20:34.635084 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2887 12:20:34.635166
2888 12:20:34.638533 [DATLAT]
2889 12:20:34.638614 Freq=1200, CH0 RK1
2890 12:20:34.638678
2891 12:20:34.642213 DATLAT Default: 0xc
2892 12:20:34.642293 0, 0xFFFF, sum = 0
2893 12:20:34.645197 1, 0xFFFF, sum = 0
2894 12:20:34.645280 2, 0xFFFF, sum = 0
2895 12:20:34.648422 3, 0xFFFF, sum = 0
2896 12:20:34.648504 4, 0xFFFF, sum = 0
2897 12:20:34.651831 5, 0xFFFF, sum = 0
2898 12:20:34.651913 6, 0xFFFF, sum = 0
2899 12:20:34.655260 7, 0xFFFF, sum = 0
2900 12:20:34.658577 8, 0xFFFF, sum = 0
2901 12:20:34.658659 9, 0xFFFF, sum = 0
2902 12:20:34.661795 10, 0xFFFF, sum = 0
2903 12:20:34.661880 11, 0x0, sum = 1
2904 12:20:34.664954 12, 0x0, sum = 2
2905 12:20:34.665057 13, 0x0, sum = 3
2906 12:20:34.665123 14, 0x0, sum = 4
2907 12:20:34.668463 best_step = 12
2908 12:20:34.668543
2909 12:20:34.668607 ==
2910 12:20:34.671614 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 12:20:34.674914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2912 12:20:34.674996 ==
2913 12:20:34.678180 RX Vref Scan: 0
2914 12:20:34.678261
2915 12:20:34.678325 RX Vref 0 -> 0, step: 1
2916 12:20:34.681474
2917 12:20:34.681554 RX Delay -21 -> 252, step: 4
2918 12:20:34.688776 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2919 12:20:34.692056 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2920 12:20:34.695438 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2921 12:20:34.698859 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2922 12:20:34.702049 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2923 12:20:34.708718 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2924 12:20:34.711943 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2925 12:20:34.715354 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2926 12:20:34.718811 iDelay=199, Bit 8, Center 92 (31 ~ 154) 124
2927 12:20:34.721923 iDelay=199, Bit 9, Center 88 (27 ~ 150) 124
2928 12:20:34.728801 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2929 12:20:34.732085 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2930 12:20:34.735542 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2931 12:20:34.738856 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2932 12:20:34.741958 iDelay=199, Bit 14, Center 116 (55 ~ 178) 124
2933 12:20:34.748676 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2934 12:20:34.748758 ==
2935 12:20:34.751996 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 12:20:34.755321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2937 12:20:34.755403 ==
2938 12:20:34.755467 DQS Delay:
2939 12:20:34.759095 DQS0 = 0, DQS1 = 0
2940 12:20:34.759175 DQM Delay:
2941 12:20:34.761812 DQM0 = 115, DQM1 = 105
2942 12:20:34.761893 DQ Delay:
2943 12:20:34.765201 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2944 12:20:34.768563 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2945 12:20:34.772020 DQ8 =92, DQ9 =88, DQ10 =110, DQ11 =96
2946 12:20:34.775117 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2947 12:20:34.775198
2948 12:20:34.775261
2949 12:20:34.785062 [DQSOSCAuto] RK1, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2950 12:20:34.788319 CH0 RK1: MR19=404, MR18=1414
2951 12:20:34.791983 CH0_RK1: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
2952 12:20:34.795297 [RxdqsGatingPostProcess] freq 1200
2953 12:20:34.802123 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2954 12:20:34.805108 Pre-setting of DQS Precalculation
2955 12:20:34.808331 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2956 12:20:34.812160 ==
2957 12:20:34.815323 Dram Type= 6, Freq= 0, CH_1, rank 0
2958 12:20:34.818323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2959 12:20:34.818405 ==
2960 12:20:34.821702 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2961 12:20:34.828292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2962 12:20:34.837458 [CA 0] Center 37 (7~68) winsize 62
2963 12:20:34.840866 [CA 1] Center 37 (7~68) winsize 62
2964 12:20:34.844221 [CA 2] Center 34 (4~65) winsize 62
2965 12:20:34.847378 [CA 3] Center 33 (3~64) winsize 62
2966 12:20:34.850638 [CA 4] Center 32 (2~63) winsize 62
2967 12:20:34.854158 [CA 5] Center 32 (2~63) winsize 62
2968 12:20:34.854238
2969 12:20:34.857387 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2970 12:20:34.857468
2971 12:20:34.860739 [CATrainingPosCal] consider 1 rank data
2972 12:20:34.864109 u2DelayCellTimex100 = 270/100 ps
2973 12:20:34.867459 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2974 12:20:34.870906 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2975 12:20:34.877387 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2976 12:20:34.880748 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2977 12:20:34.884207 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2978 12:20:34.887178 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2979 12:20:34.887259
2980 12:20:34.890646 CA PerBit enable=1, Macro0, CA PI delay=32
2981 12:20:34.890727
2982 12:20:34.894149 [CBTSetCACLKResult] CA Dly = 32
2983 12:20:34.894230 CS Dly: 6 (0~37)
2984 12:20:34.897297 ==
2985 12:20:34.897378 Dram Type= 6, Freq= 0, CH_1, rank 1
2986 12:20:34.903794 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2987 12:20:34.903876 ==
2988 12:20:34.907201 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2989 12:20:34.913864 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2990 12:20:34.922767 [CA 0] Center 37 (7~68) winsize 62
2991 12:20:34.925902 [CA 1] Center 37 (6~68) winsize 63
2992 12:20:34.929309 [CA 2] Center 34 (3~65) winsize 63
2993 12:20:34.932614 [CA 3] Center 33 (3~64) winsize 62
2994 12:20:34.936000 [CA 4] Center 32 (2~63) winsize 62
2995 12:20:34.939334 [CA 5] Center 32 (1~63) winsize 63
2996 12:20:34.939415
2997 12:20:34.943000 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2998 12:20:34.943081
2999 12:20:34.946212 [CATrainingPosCal] consider 2 rank data
3000 12:20:34.949252 u2DelayCellTimex100 = 270/100 ps
3001 12:20:34.952642 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3002 12:20:34.956067 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3003 12:20:34.962667 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
3004 12:20:34.966205 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3005 12:20:34.969269 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3006 12:20:34.972490 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3007 12:20:34.972571
3008 12:20:34.975790 CA PerBit enable=1, Macro0, CA PI delay=32
3009 12:20:34.975870
3010 12:20:34.979438 [CBTSetCACLKResult] CA Dly = 32
3011 12:20:34.979519 CS Dly: 6 (0~38)
3012 12:20:34.979581
3013 12:20:34.982667 ----->DramcWriteLeveling(PI) begin...
3014 12:20:34.985871 ==
3015 12:20:34.985952 Dram Type= 6, Freq= 0, CH_1, rank 0
3016 12:20:34.992547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3017 12:20:34.992628 ==
3018 12:20:34.995850 Write leveling (Byte 0): 21 => 21
3019 12:20:34.999204 Write leveling (Byte 1): 21 => 21
3020 12:20:35.002784 DramcWriteLeveling(PI) end<-----
3021 12:20:35.002864
3022 12:20:35.002927 ==
3023 12:20:35.006304 Dram Type= 6, Freq= 0, CH_1, rank 0
3024 12:20:35.009236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3025 12:20:35.009425 ==
3026 12:20:35.012659 [Gating] SW mode calibration
3027 12:20:35.019357 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3028 12:20:35.022675 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3029 12:20:35.029370 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3030 12:20:35.032738 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3031 12:20:35.036054 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3032 12:20:35.042678 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3033 12:20:35.045997 0 11 16 | B1->B0 | 3131 2929 | 0 0 | (0 0) (0 1)
3034 12:20:35.049267 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3035 12:20:35.055845 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3036 12:20:35.059277 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3037 12:20:35.062613 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3038 12:20:35.069178 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3039 12:20:35.072618 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3040 12:20:35.076097 0 12 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
3041 12:20:35.082735 0 12 16 | B1->B0 | 3232 4444 | 0 0 | (1 1) (0 0)
3042 12:20:35.086133 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3043 12:20:35.089485 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3044 12:20:35.096104 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3045 12:20:35.099344 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3046 12:20:35.102681 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3047 12:20:35.105947 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3048 12:20:35.112838 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3049 12:20:35.116303 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3050 12:20:35.119268 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 12:20:35.126194 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 12:20:35.129223 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 12:20:35.132721 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 12:20:35.139581 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 12:20:35.142881 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 12:20:35.145913 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 12:20:35.152789 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3058 12:20:35.156040 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 12:20:35.159356 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 12:20:35.165955 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 12:20:35.169310 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 12:20:35.172781 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 12:20:35.179380 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 12:20:35.182857 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3065 12:20:35.186174 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3066 12:20:35.189546 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3067 12:20:35.192803 Total UI for P1: 0, mck2ui 16
3068 12:20:35.196372 best dqsien dly found for B0: ( 0, 15, 14)
3069 12:20:35.202844 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3070 12:20:35.206292 Total UI for P1: 0, mck2ui 16
3071 12:20:35.209386 best dqsien dly found for B1: ( 0, 15, 18)
3072 12:20:35.212777 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3073 12:20:35.216090 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3074 12:20:35.216183
3075 12:20:35.219274 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3076 12:20:35.222606 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3077 12:20:35.225930 [Gating] SW calibration Done
3078 12:20:35.226010 ==
3079 12:20:35.229364 Dram Type= 6, Freq= 0, CH_1, rank 0
3080 12:20:35.232751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3081 12:20:35.232832 ==
3082 12:20:35.236052 RX Vref Scan: 0
3083 12:20:35.236133
3084 12:20:35.239337 RX Vref 0 -> 0, step: 1
3085 12:20:35.239417
3086 12:20:35.239480 RX Delay -40 -> 252, step: 8
3087 12:20:35.246082 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3088 12:20:35.249267 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3089 12:20:35.252791 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3090 12:20:35.256509 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3091 12:20:35.259361 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3092 12:20:35.266082 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3093 12:20:35.269490 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3094 12:20:35.272993 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3095 12:20:35.276075 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3096 12:20:35.279518 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3097 12:20:35.282693 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3098 12:20:35.289732 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3099 12:20:35.292849 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3100 12:20:35.296138 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3101 12:20:35.299454 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3102 12:20:35.306182 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3103 12:20:35.306263 ==
3104 12:20:35.309677 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 12:20:35.312684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3106 12:20:35.312791 ==
3107 12:20:35.312882 DQS Delay:
3108 12:20:35.316362 DQS0 = 0, DQS1 = 0
3109 12:20:35.316442 DQM Delay:
3110 12:20:35.319669 DQM0 = 116, DQM1 = 110
3111 12:20:35.319749 DQ Delay:
3112 12:20:35.322918 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3113 12:20:35.326202 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3114 12:20:35.329647 DQ8 =91, DQ9 =99, DQ10 =111, DQ11 =103
3115 12:20:35.332923 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3116 12:20:35.333003
3117 12:20:35.333066
3118 12:20:35.333125 ==
3119 12:20:35.336098 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 12:20:35.342800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3121 12:20:35.342880 ==
3122 12:20:35.342944
3123 12:20:35.343003
3124 12:20:35.343060 TX Vref Scan disable
3125 12:20:35.346289 == TX Byte 0 ==
3126 12:20:35.349618 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3127 12:20:35.356375 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3128 12:20:35.356456 == TX Byte 1 ==
3129 12:20:35.359671 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3130 12:20:35.366109 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3131 12:20:35.366190 ==
3132 12:20:35.369650 Dram Type= 6, Freq= 0, CH_1, rank 0
3133 12:20:35.372793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3134 12:20:35.372874 ==
3135 12:20:35.384076 TX Vref=22, minBit 1, minWin=25, winSum=413
3136 12:20:35.387047 TX Vref=24, minBit 9, minWin=25, winSum=419
3137 12:20:35.390480 TX Vref=26, minBit 0, minWin=26, winSum=426
3138 12:20:35.393900 TX Vref=28, minBit 3, minWin=26, winSum=432
3139 12:20:35.397169 TX Vref=30, minBit 8, minWin=26, winSum=432
3140 12:20:35.403629 TX Vref=32, minBit 9, minWin=26, winSum=433
3141 12:20:35.407052 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 32
3142 12:20:35.407134
3143 12:20:35.410620 Final TX Range 1 Vref 32
3144 12:20:35.410701
3145 12:20:35.410765 ==
3146 12:20:35.413899 Dram Type= 6, Freq= 0, CH_1, rank 0
3147 12:20:35.417170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3148 12:20:35.417250 ==
3149 12:20:35.417314
3150 12:20:35.420481
3151 12:20:35.420562 TX Vref Scan disable
3152 12:20:35.423765 == TX Byte 0 ==
3153 12:20:35.427222 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3154 12:20:35.430354 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3155 12:20:35.433884 == TX Byte 1 ==
3156 12:20:35.437058 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3157 12:20:35.440523 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3158 12:20:35.440603
3159 12:20:35.443793 [DATLAT]
3160 12:20:35.443873 Freq=1200, CH1 RK0
3161 12:20:35.443937
3162 12:20:35.447371 DATLAT Default: 0xd
3163 12:20:35.447452 0, 0xFFFF, sum = 0
3164 12:20:35.450714 1, 0xFFFF, sum = 0
3165 12:20:35.450795 2, 0xFFFF, sum = 0
3166 12:20:35.453902 3, 0xFFFF, sum = 0
3167 12:20:35.453984 4, 0xFFFF, sum = 0
3168 12:20:35.457357 5, 0xFFFF, sum = 0
3169 12:20:35.457439 6, 0xFFFF, sum = 0
3170 12:20:35.460712 7, 0xFFFF, sum = 0
3171 12:20:35.460794 8, 0xFFFF, sum = 0
3172 12:20:35.463902 9, 0xFFFF, sum = 0
3173 12:20:35.463984 10, 0xFFFF, sum = 0
3174 12:20:35.467173 11, 0x0, sum = 1
3175 12:20:35.467255 12, 0x0, sum = 2
3176 12:20:35.470466 13, 0x0, sum = 3
3177 12:20:35.470547 14, 0x0, sum = 4
3178 12:20:35.473923 best_step = 12
3179 12:20:35.474004
3180 12:20:35.474067 ==
3181 12:20:35.477027 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 12:20:35.480265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3183 12:20:35.480346 ==
3184 12:20:35.483833 RX Vref Scan: 1
3185 12:20:35.483913
3186 12:20:35.483975 Set Vref Range= 32 -> 127
3187 12:20:35.487157
3188 12:20:35.487236 RX Vref 32 -> 127, step: 1
3189 12:20:35.487300
3190 12:20:35.490391 RX Delay -21 -> 252, step: 4
3191 12:20:35.490472
3192 12:20:35.493567 Set Vref, RX VrefLevel [Byte0]: 32
3193 12:20:35.496851 [Byte1]: 32
3194 12:20:35.500107
3195 12:20:35.500195 Set Vref, RX VrefLevel [Byte0]: 33
3196 12:20:35.503498 [Byte1]: 33
3197 12:20:35.508286
3198 12:20:35.508366 Set Vref, RX VrefLevel [Byte0]: 34
3199 12:20:35.511434 [Byte1]: 34
3200 12:20:35.516023
3201 12:20:35.516103 Set Vref, RX VrefLevel [Byte0]: 35
3202 12:20:35.519219 [Byte1]: 35
3203 12:20:35.523946
3204 12:20:35.524026 Set Vref, RX VrefLevel [Byte0]: 36
3205 12:20:35.527119 [Byte1]: 36
3206 12:20:35.531932
3207 12:20:35.532012 Set Vref, RX VrefLevel [Byte0]: 37
3208 12:20:35.535277 [Byte1]: 37
3209 12:20:35.539900
3210 12:20:35.539980 Set Vref, RX VrefLevel [Byte0]: 38
3211 12:20:35.543007 [Byte1]: 38
3212 12:20:35.547749
3213 12:20:35.547830 Set Vref, RX VrefLevel [Byte0]: 39
3214 12:20:35.550970 [Byte1]: 39
3215 12:20:35.555586
3216 12:20:35.555665 Set Vref, RX VrefLevel [Byte0]: 40
3217 12:20:35.559025 [Byte1]: 40
3218 12:20:35.563623
3219 12:20:35.563729 Set Vref, RX VrefLevel [Byte0]: 41
3220 12:20:35.566858 [Byte1]: 41
3221 12:20:35.571563
3222 12:20:35.571643 Set Vref, RX VrefLevel [Byte0]: 42
3223 12:20:35.574766 [Byte1]: 42
3224 12:20:35.579478
3225 12:20:35.579557 Set Vref, RX VrefLevel [Byte0]: 43
3226 12:20:35.582630 [Byte1]: 43
3227 12:20:35.587438
3228 12:20:35.587518 Set Vref, RX VrefLevel [Byte0]: 44
3229 12:20:35.590629 [Byte1]: 44
3230 12:20:35.595234
3231 12:20:35.595314 Set Vref, RX VrefLevel [Byte0]: 45
3232 12:20:35.598487 [Byte1]: 45
3233 12:20:35.603330
3234 12:20:35.603410 Set Vref, RX VrefLevel [Byte0]: 46
3235 12:20:35.606387 [Byte1]: 46
3236 12:20:35.611005
3237 12:20:35.611085 Set Vref, RX VrefLevel [Byte0]: 47
3238 12:20:35.614433 [Byte1]: 47
3239 12:20:35.619007
3240 12:20:35.619086 Set Vref, RX VrefLevel [Byte0]: 48
3241 12:20:35.622288 [Byte1]: 48
3242 12:20:35.626813
3243 12:20:35.626893 Set Vref, RX VrefLevel [Byte0]: 49
3244 12:20:35.630263 [Byte1]: 49
3245 12:20:35.634775
3246 12:20:35.634855 Set Vref, RX VrefLevel [Byte0]: 50
3247 12:20:35.638167 [Byte1]: 50
3248 12:20:35.642812
3249 12:20:35.642892 Set Vref, RX VrefLevel [Byte0]: 51
3250 12:20:35.646129 [Byte1]: 51
3251 12:20:35.650616
3252 12:20:35.650696 Set Vref, RX VrefLevel [Byte0]: 52
3253 12:20:35.653948 [Byte1]: 52
3254 12:20:35.658662
3255 12:20:35.658742 Set Vref, RX VrefLevel [Byte0]: 53
3256 12:20:35.662011 [Byte1]: 53
3257 12:20:35.666349
3258 12:20:35.666429 Set Vref, RX VrefLevel [Byte0]: 54
3259 12:20:35.669682 [Byte1]: 54
3260 12:20:35.674431
3261 12:20:35.674511 Set Vref, RX VrefLevel [Byte0]: 55
3262 12:20:35.677647 [Byte1]: 55
3263 12:20:35.682364
3264 12:20:35.682443 Set Vref, RX VrefLevel [Byte0]: 56
3265 12:20:35.685490 [Byte1]: 56
3266 12:20:35.690331
3267 12:20:35.690411 Set Vref, RX VrefLevel [Byte0]: 57
3268 12:20:35.693474 [Byte1]: 57
3269 12:20:35.698165
3270 12:20:35.698244 Set Vref, RX VrefLevel [Byte0]: 58
3271 12:20:35.701682 [Byte1]: 58
3272 12:20:35.706298
3273 12:20:35.706378 Set Vref, RX VrefLevel [Byte0]: 59
3274 12:20:35.709263 [Byte1]: 59
3275 12:20:35.713835
3276 12:20:35.713941 Set Vref, RX VrefLevel [Byte0]: 60
3277 12:20:35.717373 [Byte1]: 60
3278 12:20:35.722078
3279 12:20:35.722159 Set Vref, RX VrefLevel [Byte0]: 61
3280 12:20:35.725658 [Byte1]: 61
3281 12:20:35.729887
3282 12:20:35.729967 Set Vref, RX VrefLevel [Byte0]: 62
3283 12:20:35.733086 [Byte1]: 62
3284 12:20:35.738085
3285 12:20:35.738165 Set Vref, RX VrefLevel [Byte0]: 63
3286 12:20:35.741098 [Byte1]: 63
3287 12:20:35.745534
3288 12:20:35.745613 Set Vref, RX VrefLevel [Byte0]: 64
3289 12:20:35.748874 [Byte1]: 64
3290 12:20:35.753565
3291 12:20:35.753646 Set Vref, RX VrefLevel [Byte0]: 65
3292 12:20:35.756989 [Byte1]: 65
3293 12:20:35.761413
3294 12:20:35.761493 Set Vref, RX VrefLevel [Byte0]: 66
3295 12:20:35.764961 [Byte1]: 66
3296 12:20:35.769376
3297 12:20:35.769456 Set Vref, RX VrefLevel [Byte0]: 67
3298 12:20:35.772661 [Byte1]: 67
3299 12:20:35.777527
3300 12:20:35.777606 Final RX Vref Byte 0 = 59 to rank0
3301 12:20:35.780812 Final RX Vref Byte 1 = 48 to rank0
3302 12:20:35.784096 Final RX Vref Byte 0 = 59 to rank1
3303 12:20:35.787366 Final RX Vref Byte 1 = 48 to rank1==
3304 12:20:35.790532 Dram Type= 6, Freq= 0, CH_1, rank 0
3305 12:20:35.797335 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3306 12:20:35.797415 ==
3307 12:20:35.797479 DQS Delay:
3308 12:20:35.797538 DQS0 = 0, DQS1 = 0
3309 12:20:35.800489 DQM Delay:
3310 12:20:35.800568 DQM0 = 115, DQM1 = 105
3311 12:20:35.804158 DQ Delay:
3312 12:20:35.807201 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3313 12:20:35.810690 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3314 12:20:35.814280 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3315 12:20:35.817351 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114
3316 12:20:35.817431
3317 12:20:35.817494
3318 12:20:35.824186 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3319 12:20:35.827223 CH1 RK0: MR19=404, MR18=1C1C
3320 12:20:35.833926 CH1_RK0: MR19=0x404, MR18=0x1C1C, DQSOSC=399, MR23=63, INC=41, DEC=27
3321 12:20:35.834007
3322 12:20:35.837294 ----->DramcWriteLeveling(PI) begin...
3323 12:20:35.837376 ==
3324 12:20:35.840475 Dram Type= 6, Freq= 0, CH_1, rank 1
3325 12:20:35.843868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3326 12:20:35.847009 ==
3327 12:20:35.847089 Write leveling (Byte 0): 20 => 20
3328 12:20:35.850738 Write leveling (Byte 1): 20 => 20
3329 12:20:35.853661 DramcWriteLeveling(PI) end<-----
3330 12:20:35.853740
3331 12:20:35.853803 ==
3332 12:20:35.857081 Dram Type= 6, Freq= 0, CH_1, rank 1
3333 12:20:35.863657 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3334 12:20:35.863739 ==
3335 12:20:35.863803 [Gating] SW mode calibration
3336 12:20:35.873742 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3337 12:20:35.876892 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3338 12:20:35.883829 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3339 12:20:35.886966 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3340 12:20:35.890369 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3341 12:20:35.894006 0 11 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
3342 12:20:35.900402 0 11 16 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
3343 12:20:35.903872 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3344 12:20:35.906954 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3345 12:20:35.913628 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3346 12:20:35.916889 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3347 12:20:35.920204 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3348 12:20:35.926906 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3349 12:20:35.930384 0 12 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3350 12:20:35.933868 0 12 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3351 12:20:35.940288 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3352 12:20:35.943821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3353 12:20:35.947279 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3354 12:20:35.953891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3355 12:20:35.957002 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3356 12:20:35.960609 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3357 12:20:35.967123 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3358 12:20:35.970331 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3359 12:20:35.973613 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3360 12:20:35.980332 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 12:20:35.983913 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 12:20:35.986719 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 12:20:35.993448 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 12:20:35.996776 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 12:20:36.000431 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3366 12:20:36.003512 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3367 12:20:36.009934 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 12:20:36.013300 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3369 12:20:36.016840 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3370 12:20:36.023645 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3371 12:20:36.026943 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3372 12:20:36.030011 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3373 12:20:36.037139 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3374 12:20:36.040086 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3375 12:20:36.043340 Total UI for P1: 0, mck2ui 16
3376 12:20:36.046684 best dqsien dly found for B0: ( 0, 15, 12)
3377 12:20:36.050202 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3378 12:20:36.056850 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3379 12:20:36.056934 Total UI for P1: 0, mck2ui 16
3380 12:20:36.063256 best dqsien dly found for B1: ( 0, 15, 16)
3381 12:20:36.066778 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3382 12:20:36.069935 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3383 12:20:36.070015
3384 12:20:36.073230 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3385 12:20:36.076669 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3386 12:20:36.079946 [Gating] SW calibration Done
3387 12:20:36.080025 ==
3388 12:20:36.083355 Dram Type= 6, Freq= 0, CH_1, rank 1
3389 12:20:36.086640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3390 12:20:36.086721 ==
3391 12:20:36.089836 RX Vref Scan: 0
3392 12:20:36.089915
3393 12:20:36.089977 RX Vref 0 -> 0, step: 1
3394 12:20:36.090036
3395 12:20:36.093313 RX Delay -40 -> 252, step: 8
3396 12:20:36.096728 iDelay=208, Bit 0, Center 115 (40 ~ 191) 152
3397 12:20:36.103321 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3398 12:20:36.106636 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3399 12:20:36.109883 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3400 12:20:36.113372 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3401 12:20:36.116663 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3402 12:20:36.123191 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3403 12:20:36.126634 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3404 12:20:36.130092 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3405 12:20:36.133228 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3406 12:20:36.136711 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3407 12:20:36.143184 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3408 12:20:36.146956 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3409 12:20:36.149974 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3410 12:20:36.153510 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3411 12:20:36.156598 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3412 12:20:36.156794 ==
3413 12:20:36.160127 Dram Type= 6, Freq= 0, CH_1, rank 1
3414 12:20:36.166532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3415 12:20:36.166613 ==
3416 12:20:36.166675 DQS Delay:
3417 12:20:36.170106 DQS0 = 0, DQS1 = 0
3418 12:20:36.170185 DQM Delay:
3419 12:20:36.173565 DQM0 = 115, DQM1 = 105
3420 12:20:36.173644 DQ Delay:
3421 12:20:36.176793 DQ0 =115, DQ1 =115, DQ2 =103, DQ3 =115
3422 12:20:36.180012 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3423 12:20:36.183347 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3424 12:20:36.186775 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3425 12:20:36.186854
3426 12:20:36.186915
3427 12:20:36.186973 ==
3428 12:20:36.189945 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 12:20:36.193418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3430 12:20:36.196905 ==
3431 12:20:36.196984
3432 12:20:36.197046
3433 12:20:36.197103 TX Vref Scan disable
3434 12:20:36.200442 == TX Byte 0 ==
3435 12:20:36.203479 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3436 12:20:36.206659 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3437 12:20:36.209998 == TX Byte 1 ==
3438 12:20:36.213431 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3439 12:20:36.216880 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3440 12:20:36.216961 ==
3441 12:20:36.219923 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 12:20:36.226537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3443 12:20:36.226617 ==
3444 12:20:36.237387 TX Vref=22, minBit 9, minWin=25, winSum=419
3445 12:20:36.240474 TX Vref=24, minBit 9, minWin=25, winSum=426
3446 12:20:36.244299 TX Vref=26, minBit 3, minWin=26, winSum=427
3447 12:20:36.247334 TX Vref=28, minBit 0, minWin=26, winSum=429
3448 12:20:36.250529 TX Vref=30, minBit 9, minWin=26, winSum=437
3449 12:20:36.254198 TX Vref=32, minBit 3, minWin=26, winSum=430
3450 12:20:36.260318 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3451 12:20:36.260398
3452 12:20:36.263691 Final TX Range 1 Vref 30
3453 12:20:36.263771
3454 12:20:36.263832 ==
3455 12:20:36.267226 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 12:20:36.270454 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3457 12:20:36.270535 ==
3458 12:20:36.270598
3459 12:20:36.273992
3460 12:20:36.274072 TX Vref Scan disable
3461 12:20:36.277419 == TX Byte 0 ==
3462 12:20:36.280355 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3463 12:20:36.284085 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3464 12:20:36.286933 == TX Byte 1 ==
3465 12:20:36.290485 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3466 12:20:36.293917 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3467 12:20:36.293997
3468 12:20:36.297263 [DATLAT]
3469 12:20:36.297342 Freq=1200, CH1 RK1
3470 12:20:36.297405
3471 12:20:36.300392 DATLAT Default: 0xc
3472 12:20:36.300498 0, 0xFFFF, sum = 0
3473 12:20:36.303741 1, 0xFFFF, sum = 0
3474 12:20:36.303823 2, 0xFFFF, sum = 0
3475 12:20:36.307029 3, 0xFFFF, sum = 0
3476 12:20:36.307110 4, 0xFFFF, sum = 0
3477 12:20:36.310437 5, 0xFFFF, sum = 0
3478 12:20:36.310519 6, 0xFFFF, sum = 0
3479 12:20:36.313706 7, 0xFFFF, sum = 0
3480 12:20:36.317012 8, 0xFFFF, sum = 0
3481 12:20:36.317093 9, 0xFFFF, sum = 0
3482 12:20:36.320302 10, 0xFFFF, sum = 0
3483 12:20:36.320383 11, 0x0, sum = 1
3484 12:20:36.323644 12, 0x0, sum = 2
3485 12:20:36.323725 13, 0x0, sum = 3
3486 12:20:36.323789 14, 0x0, sum = 4
3487 12:20:36.327145 best_step = 12
3488 12:20:36.327224
3489 12:20:36.327287 ==
3490 12:20:36.330330 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 12:20:36.333914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3492 12:20:36.333995 ==
3493 12:20:36.337494 RX Vref Scan: 0
3494 12:20:36.337573
3495 12:20:36.337637 RX Vref 0 -> 0, step: 1
3496 12:20:36.340135
3497 12:20:36.340254 RX Delay -29 -> 252, step: 4
3498 12:20:36.347550 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3499 12:20:36.350890 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3500 12:20:36.354340 iDelay=199, Bit 2, Center 106 (39 ~ 174) 136
3501 12:20:36.357503 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3502 12:20:36.360652 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3503 12:20:36.367616 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3504 12:20:36.370734 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3505 12:20:36.374185 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3506 12:20:36.377456 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3507 12:20:36.380886 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3508 12:20:36.387456 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3509 12:20:36.390686 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3510 12:20:36.393946 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3511 12:20:36.397507 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3512 12:20:36.400688 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3513 12:20:36.407379 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3514 12:20:36.407459 ==
3515 12:20:36.410647 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 12:20:36.414107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3517 12:20:36.414188 ==
3518 12:20:36.414251 DQS Delay:
3519 12:20:36.417341 DQS0 = 0, DQS1 = 0
3520 12:20:36.417420 DQM Delay:
3521 12:20:36.420919 DQM0 = 114, DQM1 = 103
3522 12:20:36.420998 DQ Delay:
3523 12:20:36.424130 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3524 12:20:36.427560 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =112
3525 12:20:36.430963 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3526 12:20:36.434235 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =110
3527 12:20:36.434314
3528 12:20:36.434376
3529 12:20:36.443999 [DQSOSCAuto] RK1, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3530 12:20:36.447487 CH1 RK1: MR19=404, MR18=909
3531 12:20:36.450590 CH1_RK1: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
3532 12:20:36.454044 [RxdqsGatingPostProcess] freq 1200
3533 12:20:36.460781 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3534 12:20:36.464152 Pre-setting of DQS Precalculation
3535 12:20:36.467493 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3536 12:20:36.474207 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3537 12:20:36.484167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3538 12:20:36.484266
3539 12:20:36.484328
3540 12:20:36.487594 [Calibration Summary] 2400 Mbps
3541 12:20:36.487672 CH 0, Rank 0
3542 12:20:36.491202 SW Impedance : PASS
3543 12:20:36.491294 DUTY Scan : NO K
3544 12:20:36.494384 ZQ Calibration : PASS
3545 12:20:36.497404 Jitter Meter : NO K
3546 12:20:36.497483 CBT Training : PASS
3547 12:20:36.500656 Write leveling : PASS
3548 12:20:36.500759 RX DQS gating : PASS
3549 12:20:36.503929 RX DQ/DQS(RDDQC) : PASS
3550 12:20:36.507394 TX DQ/DQS : PASS
3551 12:20:36.507474 RX DATLAT : PASS
3552 12:20:36.510757 RX DQ/DQS(Engine): PASS
3553 12:20:36.514015 TX OE : NO K
3554 12:20:36.514094 All Pass.
3555 12:20:36.514172
3556 12:20:36.514258 CH 0, Rank 1
3557 12:20:36.517371 SW Impedance : PASS
3558 12:20:36.520933 DUTY Scan : NO K
3559 12:20:36.521012 ZQ Calibration : PASS
3560 12:20:36.524208 Jitter Meter : NO K
3561 12:20:36.527325 CBT Training : PASS
3562 12:20:36.527404 Write leveling : PASS
3563 12:20:36.530712 RX DQS gating : PASS
3564 12:20:36.533819 RX DQ/DQS(RDDQC) : PASS
3565 12:20:36.533898 TX DQ/DQS : PASS
3566 12:20:36.537353 RX DATLAT : PASS
3567 12:20:36.540741 RX DQ/DQS(Engine): PASS
3568 12:20:36.540820 TX OE : NO K
3569 12:20:36.540883 All Pass.
3570 12:20:36.543940
3571 12:20:36.544018 CH 1, Rank 0
3572 12:20:36.547210 SW Impedance : PASS
3573 12:20:36.547288 DUTY Scan : NO K
3574 12:20:36.550537 ZQ Calibration : PASS
3575 12:20:36.550615 Jitter Meter : NO K
3576 12:20:36.553874 CBT Training : PASS
3577 12:20:36.557417 Write leveling : PASS
3578 12:20:36.557495 RX DQS gating : PASS
3579 12:20:36.560492 RX DQ/DQS(RDDQC) : PASS
3580 12:20:36.563835 TX DQ/DQS : PASS
3581 12:20:36.563913 RX DATLAT : PASS
3582 12:20:36.567385 RX DQ/DQS(Engine): PASS
3583 12:20:36.570414 TX OE : NO K
3584 12:20:36.570492 All Pass.
3585 12:20:36.570554
3586 12:20:36.570611 CH 1, Rank 1
3587 12:20:36.574046 SW Impedance : PASS
3588 12:20:36.577375 DUTY Scan : NO K
3589 12:20:36.577454 ZQ Calibration : PASS
3590 12:20:36.580517 Jitter Meter : NO K
3591 12:20:36.583998 CBT Training : PASS
3592 12:20:36.584076 Write leveling : PASS
3593 12:20:36.587433 RX DQS gating : PASS
3594 12:20:36.590682 RX DQ/DQS(RDDQC) : PASS
3595 12:20:36.590760 TX DQ/DQS : PASS
3596 12:20:36.593907 RX DATLAT : PASS
3597 12:20:36.593986 RX DQ/DQS(Engine): PASS
3598 12:20:36.597340 TX OE : NO K
3599 12:20:36.597418 All Pass.
3600 12:20:36.597481
3601 12:20:36.600718 DramC Write-DBI off
3602 12:20:36.604100 PER_BANK_REFRESH: Hybrid Mode
3603 12:20:36.604214 TX_TRACKING: ON
3604 12:20:36.613951 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3605 12:20:36.617369 [FAST_K] Save calibration result to emmc
3606 12:20:36.620714 dramc_set_vcore_voltage set vcore to 650000
3607 12:20:36.624037 Read voltage for 600, 5
3608 12:20:36.624116 Vio18 = 0
3609 12:20:36.624205 Vcore = 650000
3610 12:20:36.627404 Vdram = 0
3611 12:20:36.627483 Vddq = 0
3612 12:20:36.627545 Vmddr = 0
3613 12:20:36.634003 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3614 12:20:36.637328 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3615 12:20:36.640747 MEM_TYPE=3, freq_sel=19
3616 12:20:36.644456 sv_algorithm_assistance_LP4_1600
3617 12:20:36.647221 ============ PULL DRAM RESETB DOWN ============
3618 12:20:36.653913 ========== PULL DRAM RESETB DOWN end =========
3619 12:20:36.657251 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3620 12:20:36.660442 ===================================
3621 12:20:36.663903 LPDDR4 DRAM CONFIGURATION
3622 12:20:36.667471 ===================================
3623 12:20:36.667551 EX_ROW_EN[0] = 0x0
3624 12:20:36.670780 EX_ROW_EN[1] = 0x0
3625 12:20:36.670859 LP4Y_EN = 0x0
3626 12:20:36.673655 WORK_FSP = 0x0
3627 12:20:36.673734 WL = 0x2
3628 12:20:36.676996 RL = 0x2
3629 12:20:36.677074 BL = 0x2
3630 12:20:36.680352 RPST = 0x0
3631 12:20:36.680457 RD_PRE = 0x0
3632 12:20:36.683561 WR_PRE = 0x1
3633 12:20:36.683639 WR_PST = 0x0
3634 12:20:36.687106 DBI_WR = 0x0
3635 12:20:36.690636 DBI_RD = 0x0
3636 12:20:36.690714 OTF = 0x1
3637 12:20:36.693725 ===================================
3638 12:20:36.696842 ===================================
3639 12:20:36.696921 ANA top config
3640 12:20:36.700481 ===================================
3641 12:20:36.703686 DLL_ASYNC_EN = 0
3642 12:20:36.706832 ALL_SLAVE_EN = 1
3643 12:20:36.710170 NEW_RANK_MODE = 1
3644 12:20:36.713569 DLL_IDLE_MODE = 1
3645 12:20:36.713649 LP45_APHY_COMB_EN = 1
3646 12:20:36.716908 TX_ODT_DIS = 1
3647 12:20:36.720408 NEW_8X_MODE = 1
3648 12:20:36.723574 ===================================
3649 12:20:36.726637 ===================================
3650 12:20:36.729959 data_rate = 1200
3651 12:20:36.733672 CKR = 1
3652 12:20:36.733752 DQ_P2S_RATIO = 8
3653 12:20:36.736607 ===================================
3654 12:20:36.740631 CA_P2S_RATIO = 8
3655 12:20:36.743315 DQ_CA_OPEN = 0
3656 12:20:36.746636 DQ_SEMI_OPEN = 0
3657 12:20:36.750337 CA_SEMI_OPEN = 0
3658 12:20:36.753334 CA_FULL_RATE = 0
3659 12:20:36.753414 DQ_CKDIV4_EN = 1
3660 12:20:36.756546 CA_CKDIV4_EN = 1
3661 12:20:36.759859 CA_PREDIV_EN = 0
3662 12:20:36.763211 PH8_DLY = 0
3663 12:20:36.766518 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3664 12:20:36.770009 DQ_AAMCK_DIV = 4
3665 12:20:36.770093 CA_AAMCK_DIV = 4
3666 12:20:36.773342 CA_ADMCK_DIV = 4
3667 12:20:36.776452 DQ_TRACK_CA_EN = 0
3668 12:20:36.779678 CA_PICK = 600
3669 12:20:36.783182 CA_MCKIO = 600
3670 12:20:36.786520 MCKIO_SEMI = 0
3671 12:20:36.789859 PLL_FREQ = 2288
3672 12:20:36.789965 DQ_UI_PI_RATIO = 32
3673 12:20:36.793339 CA_UI_PI_RATIO = 0
3674 12:20:36.796574 ===================================
3675 12:20:36.799902 ===================================
3676 12:20:36.803045 memory_type:LPDDR4
3677 12:20:36.806242 GP_NUM : 10
3678 12:20:36.806322 SRAM_EN : 1
3679 12:20:36.809615 MD32_EN : 0
3680 12:20:36.812957 ===================================
3681 12:20:36.816114 [ANA_INIT] >>>>>>>>>>>>>>
3682 12:20:36.816249 <<<<<< [CONFIGURE PHASE]: ANA_TX
3683 12:20:36.819517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3684 12:20:36.822792 ===================================
3685 12:20:36.826262 data_rate = 1200,PCW = 0X5800
3686 12:20:36.829607 ===================================
3687 12:20:36.832942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3688 12:20:36.839253 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3689 12:20:36.846051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3690 12:20:36.849409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3691 12:20:36.852609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3692 12:20:36.856115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3693 12:20:36.859313 [ANA_INIT] flow start
3694 12:20:36.859393 [ANA_INIT] PLL >>>>>>>>
3695 12:20:36.862833 [ANA_INIT] PLL <<<<<<<<
3696 12:20:36.865922 [ANA_INIT] MIDPI >>>>>>>>
3697 12:20:36.866002 [ANA_INIT] MIDPI <<<<<<<<
3698 12:20:36.869494 [ANA_INIT] DLL >>>>>>>>
3699 12:20:36.872614 [ANA_INIT] flow end
3700 12:20:36.875844 ============ LP4 DIFF to SE enter ============
3701 12:20:36.879357 ============ LP4 DIFF to SE exit ============
3702 12:20:36.882656 [ANA_INIT] <<<<<<<<<<<<<
3703 12:20:36.886014 [Flow] Enable top DCM control >>>>>
3704 12:20:36.889229 [Flow] Enable top DCM control <<<<<
3705 12:20:36.892671 Enable DLL master slave shuffle
3706 12:20:36.895876 ==============================================================
3707 12:20:36.899488 Gating Mode config
3708 12:20:36.905703 ==============================================================
3709 12:20:36.905809 Config description:
3710 12:20:36.915751 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3711 12:20:36.922283 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3712 12:20:36.929061 SELPH_MODE 0: By rank 1: By Phase
3713 12:20:36.932427 ==============================================================
3714 12:20:36.935791 GAT_TRACK_EN = 1
3715 12:20:36.939302 RX_GATING_MODE = 2
3716 12:20:36.942415 RX_GATING_TRACK_MODE = 2
3717 12:20:36.945883 SELPH_MODE = 1
3718 12:20:36.949067 PICG_EARLY_EN = 1
3719 12:20:36.952405 VALID_LAT_VALUE = 1
3720 12:20:36.955874 ==============================================================
3721 12:20:36.959158 Enter into Gating configuration >>>>
3722 12:20:36.962476 Exit from Gating configuration <<<<
3723 12:20:36.965652 Enter into DVFS_PRE_config >>>>>
3724 12:20:36.978997 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3725 12:20:36.979079 Exit from DVFS_PRE_config <<<<<
3726 12:20:36.982315 Enter into PICG configuration >>>>
3727 12:20:36.985787 Exit from PICG configuration <<<<
3728 12:20:36.989351 [RX_INPUT] configuration >>>>>
3729 12:20:36.992623 [RX_INPUT] configuration <<<<<
3730 12:20:36.999175 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3731 12:20:37.002413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3732 12:20:37.009010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3733 12:20:37.015667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3734 12:20:37.022260 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3735 12:20:37.028895 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3736 12:20:37.032283 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3737 12:20:37.035476 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3738 12:20:37.039050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3739 12:20:37.045659 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3740 12:20:37.049112 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3741 12:20:37.052137 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3742 12:20:37.055524 ===================================
3743 12:20:37.058877 LPDDR4 DRAM CONFIGURATION
3744 12:20:37.062134 ===================================
3745 12:20:37.062215 EX_ROW_EN[0] = 0x0
3746 12:20:37.065526 EX_ROW_EN[1] = 0x0
3747 12:20:37.068893 LP4Y_EN = 0x0
3748 12:20:37.068973 WORK_FSP = 0x0
3749 12:20:37.072150 WL = 0x2
3750 12:20:37.072240 RL = 0x2
3751 12:20:37.075447 BL = 0x2
3752 12:20:37.075527 RPST = 0x0
3753 12:20:37.078666 RD_PRE = 0x0
3754 12:20:37.078746 WR_PRE = 0x1
3755 12:20:37.081991 WR_PST = 0x0
3756 12:20:37.082071 DBI_WR = 0x0
3757 12:20:37.085327 DBI_RD = 0x0
3758 12:20:37.085407 OTF = 0x1
3759 12:20:37.088934 ===================================
3760 12:20:37.092179 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3761 12:20:37.098684 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3762 12:20:37.101997 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3763 12:20:37.105160 ===================================
3764 12:20:37.108524 LPDDR4 DRAM CONFIGURATION
3765 12:20:37.111850 ===================================
3766 12:20:37.111953 EX_ROW_EN[0] = 0x10
3767 12:20:37.115129 EX_ROW_EN[1] = 0x0
3768 12:20:37.118582 LP4Y_EN = 0x0
3769 12:20:37.118662 WORK_FSP = 0x0
3770 12:20:37.121922 WL = 0x2
3771 12:20:37.122002 RL = 0x2
3772 12:20:37.125293 BL = 0x2
3773 12:20:37.125372 RPST = 0x0
3774 12:20:37.128385 RD_PRE = 0x0
3775 12:20:37.128465 WR_PRE = 0x1
3776 12:20:37.131581 WR_PST = 0x0
3777 12:20:37.131660 DBI_WR = 0x0
3778 12:20:37.134881 DBI_RD = 0x0
3779 12:20:37.134961 OTF = 0x1
3780 12:20:37.138359 ===================================
3781 12:20:37.144787 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3782 12:20:37.149082 nWR fixed to 30
3783 12:20:37.152740 [ModeRegInit_LP4] CH0 RK0
3784 12:20:37.152820 [ModeRegInit_LP4] CH0 RK1
3785 12:20:37.155897 [ModeRegInit_LP4] CH1 RK0
3786 12:20:37.159174 [ModeRegInit_LP4] CH1 RK1
3787 12:20:37.159254 match AC timing 16
3788 12:20:37.165651 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3789 12:20:37.169184 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3790 12:20:37.172342 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3791 12:20:37.178998 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3792 12:20:37.182246 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3793 12:20:37.182326 ==
3794 12:20:37.185602 Dram Type= 6, Freq= 0, CH_0, rank 0
3795 12:20:37.188922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3796 12:20:37.189003 ==
3797 12:20:37.195564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3798 12:20:37.202150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3799 12:20:37.205369 [CA 0] Center 35 (5~66) winsize 62
3800 12:20:37.208796 [CA 1] Center 35 (5~66) winsize 62
3801 12:20:37.212076 [CA 2] Center 34 (4~65) winsize 62
3802 12:20:37.215844 [CA 3] Center 34 (3~65) winsize 63
3803 12:20:37.218542 [CA 4] Center 33 (3~64) winsize 62
3804 12:20:37.222065 [CA 5] Center 33 (3~64) winsize 62
3805 12:20:37.222171
3806 12:20:37.225740 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3807 12:20:37.225819
3808 12:20:37.228670 [CATrainingPosCal] consider 1 rank data
3809 12:20:37.231852 u2DelayCellTimex100 = 270/100 ps
3810 12:20:37.235482 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3811 12:20:37.238779 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3812 12:20:37.241888 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3813 12:20:37.245438 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3814 12:20:37.248826 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3815 12:20:37.255135 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3816 12:20:37.255214
3817 12:20:37.258697 CA PerBit enable=1, Macro0, CA PI delay=33
3818 12:20:37.258775
3819 12:20:37.261824 [CBTSetCACLKResult] CA Dly = 33
3820 12:20:37.261903 CS Dly: 4 (0~35)
3821 12:20:37.261965 ==
3822 12:20:37.265007 Dram Type= 6, Freq= 0, CH_0, rank 1
3823 12:20:37.268448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3824 12:20:37.271794 ==
3825 12:20:37.275005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3826 12:20:37.281839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3827 12:20:37.285097 [CA 0] Center 35 (5~66) winsize 62
3828 12:20:37.288261 [CA 1] Center 35 (5~66) winsize 62
3829 12:20:37.291753 [CA 2] Center 34 (4~65) winsize 62
3830 12:20:37.294925 [CA 3] Center 34 (4~65) winsize 62
3831 12:20:37.298157 [CA 4] Center 33 (3~64) winsize 62
3832 12:20:37.301361 [CA 5] Center 33 (3~64) winsize 62
3833 12:20:37.301489
3834 12:20:37.305251 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3835 12:20:37.305344
3836 12:20:37.308113 [CATrainingPosCal] consider 2 rank data
3837 12:20:37.311296 u2DelayCellTimex100 = 270/100 ps
3838 12:20:37.314836 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3839 12:20:37.318053 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3840 12:20:37.321322 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3841 12:20:37.327916 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3842 12:20:37.331283 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3843 12:20:37.334437 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3844 12:20:37.334541
3845 12:20:37.337829 CA PerBit enable=1, Macro0, CA PI delay=33
3846 12:20:37.337908
3847 12:20:37.341217 [CBTSetCACLKResult] CA Dly = 33
3848 12:20:37.341296 CS Dly: 4 (0~36)
3849 12:20:37.341359
3850 12:20:37.344501 ----->DramcWriteLeveling(PI) begin...
3851 12:20:37.344583 ==
3852 12:20:37.347808 Dram Type= 6, Freq= 0, CH_0, rank 0
3853 12:20:37.354581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3854 12:20:37.354662 ==
3855 12:20:37.357858 Write leveling (Byte 0): 30 => 30
3856 12:20:37.361127 Write leveling (Byte 1): 29 => 29
3857 12:20:37.361207 DramcWriteLeveling(PI) end<-----
3858 12:20:37.364725
3859 12:20:37.364804 ==
3860 12:20:37.367862 Dram Type= 6, Freq= 0, CH_0, rank 0
3861 12:20:37.371446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3862 12:20:37.371526 ==
3863 12:20:37.374750 [Gating] SW mode calibration
3864 12:20:37.381009 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3865 12:20:37.384783 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3866 12:20:37.391078 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3867 12:20:37.394731 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3868 12:20:37.397664 0 5 8 | B1->B0 | 3131 3030 | 1 1 | (1 0) (1 1)
3869 12:20:37.404330 0 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3870 12:20:37.407590 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3871 12:20:37.410930 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3872 12:20:37.417397 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3873 12:20:37.420908 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3874 12:20:37.424149 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3875 12:20:37.430752 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3876 12:20:37.434076 0 6 8 | B1->B0 | 2c2c 3232 | 0 1 | (0 0) (0 0)
3877 12:20:37.437495 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3878 12:20:37.444075 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3879 12:20:37.447367 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3880 12:20:37.450816 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3881 12:20:37.457669 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3882 12:20:37.460631 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3883 12:20:37.463969 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3884 12:20:37.470850 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3885 12:20:37.473981 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 12:20:37.477248 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 12:20:37.483805 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 12:20:37.487208 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 12:20:37.490347 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 12:20:37.497259 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 12:20:37.500416 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3892 12:20:37.503853 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 12:20:37.510862 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 12:20:37.513641 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 12:20:37.517030 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3896 12:20:37.520450 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3897 12:20:37.527130 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3898 12:20:37.530144 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3899 12:20:37.533897 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3900 12:20:37.540320 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3901 12:20:37.543574 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3902 12:20:37.546996 Total UI for P1: 0, mck2ui 16
3903 12:20:37.550299 best dqsien dly found for B0: ( 0, 9, 10)
3904 12:20:37.553620 Total UI for P1: 0, mck2ui 16
3905 12:20:37.556872 best dqsien dly found for B1: ( 0, 9, 10)
3906 12:20:37.560050 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3907 12:20:37.563589 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3908 12:20:37.563667
3909 12:20:37.566787 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3910 12:20:37.573695 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3911 12:20:37.573773 [Gating] SW calibration Done
3912 12:20:37.573835 ==
3913 12:20:37.576830 Dram Type= 6, Freq= 0, CH_0, rank 0
3914 12:20:37.583461 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3915 12:20:37.583540 ==
3916 12:20:37.583601 RX Vref Scan: 0
3917 12:20:37.583658
3918 12:20:37.586747 RX Vref 0 -> 0, step: 1
3919 12:20:37.586825
3920 12:20:37.589810 RX Delay -230 -> 252, step: 16
3921 12:20:37.593115 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3922 12:20:37.596554 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3923 12:20:37.600004 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3924 12:20:37.606579 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3925 12:20:37.609992 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3926 12:20:37.613745 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3927 12:20:37.616694 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3928 12:20:37.623163 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3929 12:20:37.626541 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3930 12:20:37.629801 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3931 12:20:37.633247 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3932 12:20:37.636447 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3933 12:20:37.643141 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3934 12:20:37.646279 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3935 12:20:37.649765 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3936 12:20:37.656349 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3937 12:20:37.656430 ==
3938 12:20:37.659516 Dram Type= 6, Freq= 0, CH_0, rank 0
3939 12:20:37.663013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3940 12:20:37.663094 ==
3941 12:20:37.663157 DQS Delay:
3942 12:20:37.666650 DQS0 = 0, DQS1 = 0
3943 12:20:37.666730 DQM Delay:
3944 12:20:37.669564 DQM0 = 39, DQM1 = 33
3945 12:20:37.669645 DQ Delay:
3946 12:20:37.673125 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
3947 12:20:37.676309 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3948 12:20:37.679632 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3949 12:20:37.682853 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3950 12:20:37.682933
3951 12:20:37.682996
3952 12:20:37.683054 ==
3953 12:20:37.686919 Dram Type= 6, Freq= 0, CH_0, rank 0
3954 12:20:37.689876 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3955 12:20:37.689957 ==
3956 12:20:37.690020
3957 12:20:37.690078
3958 12:20:37.693185 TX Vref Scan disable
3959 12:20:37.696300 == TX Byte 0 ==
3960 12:20:37.699553 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3961 12:20:37.703264 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3962 12:20:37.706421 == TX Byte 1 ==
3963 12:20:37.709455 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3964 12:20:37.712816 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3965 12:20:37.712896 ==
3966 12:20:37.716105 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 12:20:37.722562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3968 12:20:37.722642 ==
3969 12:20:37.722705
3970 12:20:37.722764
3971 12:20:37.722822 TX Vref Scan disable
3972 12:20:37.726873 == TX Byte 0 ==
3973 12:20:37.730179 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3974 12:20:37.736832 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3975 12:20:37.736912 == TX Byte 1 ==
3976 12:20:37.740055 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3977 12:20:37.746627 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3978 12:20:37.746707
3979 12:20:37.746771 [DATLAT]
3980 12:20:37.746830 Freq=600, CH0 RK0
3981 12:20:37.746896
3982 12:20:37.749953 DATLAT Default: 0x9
3983 12:20:37.750033 0, 0xFFFF, sum = 0
3984 12:20:37.753438 1, 0xFFFF, sum = 0
3985 12:20:37.756688 2, 0xFFFF, sum = 0
3986 12:20:37.756769 3, 0xFFFF, sum = 0
3987 12:20:37.760153 4, 0xFFFF, sum = 0
3988 12:20:37.760242 5, 0xFFFF, sum = 0
3989 12:20:37.763286 6, 0xFFFF, sum = 0
3990 12:20:37.763367 7, 0x0, sum = 1
3991 12:20:37.763432 8, 0x0, sum = 2
3992 12:20:37.766624 9, 0x0, sum = 3
3993 12:20:37.766705 10, 0x0, sum = 4
3994 12:20:37.770006 best_step = 8
3995 12:20:37.770086
3996 12:20:37.770149 ==
3997 12:20:37.773280 Dram Type= 6, Freq= 0, CH_0, rank 0
3998 12:20:37.776483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3999 12:20:37.776563 ==
4000 12:20:37.779858 RX Vref Scan: 1
4001 12:20:37.779937
4002 12:20:37.780000 RX Vref 0 -> 0, step: 1
4003 12:20:37.780059
4004 12:20:37.783060 RX Delay -195 -> 252, step: 8
4005 12:20:37.783141
4006 12:20:37.786457 Set Vref, RX VrefLevel [Byte0]: 50
4007 12:20:37.789784 [Byte1]: 46
4008 12:20:37.793997
4009 12:20:37.794076 Final RX Vref Byte 0 = 50 to rank0
4010 12:20:37.797082 Final RX Vref Byte 1 = 46 to rank0
4011 12:20:37.800564 Final RX Vref Byte 0 = 50 to rank1
4012 12:20:37.803923 Final RX Vref Byte 1 = 46 to rank1==
4013 12:20:37.807299 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 12:20:37.813930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4015 12:20:37.814009 ==
4016 12:20:37.814071 DQS Delay:
4017 12:20:37.814128 DQS0 = 0, DQS1 = 0
4018 12:20:37.817247 DQM Delay:
4019 12:20:37.817342 DQM0 = 39, DQM1 = 31
4020 12:20:37.820421 DQ Delay:
4021 12:20:37.823658 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =32
4022 12:20:37.827026 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =48
4023 12:20:37.830386 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =24
4024 12:20:37.833861 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4025 12:20:37.833939
4026 12:20:37.834002
4027 12:20:37.840367 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4028 12:20:37.843460 CH0 RK0: MR19=808, MR18=5454
4029 12:20:37.850042 CH0_RK0: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
4030 12:20:37.850121
4031 12:20:37.853324 ----->DramcWriteLeveling(PI) begin...
4032 12:20:37.853404 ==
4033 12:20:37.856748 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 12:20:37.860057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4035 12:20:37.860137 ==
4036 12:20:37.863979 Write leveling (Byte 0): 29 => 29
4037 12:20:37.866779 Write leveling (Byte 1): 31 => 31
4038 12:20:37.869932 DramcWriteLeveling(PI) end<-----
4039 12:20:37.870010
4040 12:20:37.870071 ==
4041 12:20:37.873266 Dram Type= 6, Freq= 0, CH_0, rank 1
4042 12:20:37.876594 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4043 12:20:37.879880 ==
4044 12:20:37.879958 [Gating] SW mode calibration
4045 12:20:37.886391 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4046 12:20:37.892905 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4047 12:20:37.896763 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 12:20:37.903002 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 12:20:37.906388 0 5 8 | B1->B0 | 3131 3232 | 1 1 | (0 0) (1 0)
4050 12:20:37.909684 0 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
4051 12:20:37.916156 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 12:20:37.919635 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 12:20:37.923203 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 12:20:37.929624 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 12:20:37.933069 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 12:20:37.936358 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 12:20:37.942811 0 6 8 | B1->B0 | 2c2c 3434 | 1 0 | (0 0) (0 0)
4058 12:20:37.946082 0 6 12 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
4059 12:20:37.949443 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 12:20:37.956060 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 12:20:37.959487 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 12:20:37.962714 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 12:20:37.966045 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 12:20:37.972745 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 12:20:37.976166 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4066 12:20:37.979442 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:20:37.986405 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:20:37.989450 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:20:37.992795 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:20:37.999619 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:20:38.002730 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:20:38.006237 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:20:38.012563 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:20:38.016037 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:20:38.019355 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:20:38.025946 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:20:38.029061 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:20:38.032458 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:20:38.039053 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:20:38.042403 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:20:38.045736 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4082 12:20:38.052303 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 12:20:38.052382 Total UI for P1: 0, mck2ui 16
4084 12:20:38.058846 best dqsien dly found for B0: ( 0, 9, 8)
4085 12:20:38.058926 Total UI for P1: 0, mck2ui 16
4086 12:20:38.065567 best dqsien dly found for B1: ( 0, 9, 8)
4087 12:20:38.068899 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4088 12:20:38.072180 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4089 12:20:38.072282
4090 12:20:38.075711 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4091 12:20:38.078810 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4092 12:20:38.082088 [Gating] SW calibration Done
4093 12:20:38.082167 ==
4094 12:20:38.085698 Dram Type= 6, Freq= 0, CH_0, rank 1
4095 12:20:38.088690 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4096 12:20:38.088769 ==
4097 12:20:38.092361 RX Vref Scan: 0
4098 12:20:38.092439
4099 12:20:38.092502 RX Vref 0 -> 0, step: 1
4100 12:20:38.092559
4101 12:20:38.095246 RX Delay -230 -> 252, step: 16
4102 12:20:38.101917 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4103 12:20:38.105182 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4104 12:20:38.108497 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4105 12:20:38.111799 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4106 12:20:38.115148 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4107 12:20:38.121567 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4108 12:20:38.125135 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4109 12:20:38.128294 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4110 12:20:38.131887 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4111 12:20:38.138512 iDelay=218, Bit 9, Center 17 (-134 ~ 169) 304
4112 12:20:38.141575 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4113 12:20:38.144973 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4114 12:20:38.148076 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4115 12:20:38.154731 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4116 12:20:38.158071 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4117 12:20:38.161374 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4118 12:20:38.161453 ==
4119 12:20:38.164726 Dram Type= 6, Freq= 0, CH_0, rank 1
4120 12:20:38.168010 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4121 12:20:38.168104 ==
4122 12:20:38.171237 DQS Delay:
4123 12:20:38.171316 DQS0 = 0, DQS1 = 0
4124 12:20:38.174657 DQM Delay:
4125 12:20:38.174735 DQM0 = 40, DQM1 = 32
4126 12:20:38.174797 DQ Delay:
4127 12:20:38.178044 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4128 12:20:38.181187 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4129 12:20:38.184664 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4130 12:20:38.188023 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4131 12:20:38.188102
4132 12:20:38.188163
4133 12:20:38.191981 ==
4134 12:20:38.194747 Dram Type= 6, Freq= 0, CH_0, rank 1
4135 12:20:38.197855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4136 12:20:38.197934 ==
4137 12:20:38.197996
4138 12:20:38.198054
4139 12:20:38.201170 TX Vref Scan disable
4140 12:20:38.201263 == TX Byte 0 ==
4141 12:20:38.207873 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4142 12:20:38.211129 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4143 12:20:38.211208 == TX Byte 1 ==
4144 12:20:38.217790 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4145 12:20:38.221078 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4146 12:20:38.221157 ==
4147 12:20:38.224361 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 12:20:38.227649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4149 12:20:38.227728 ==
4150 12:20:38.227790
4151 12:20:38.227847
4152 12:20:38.230893 TX Vref Scan disable
4153 12:20:38.234299 == TX Byte 0 ==
4154 12:20:38.237500 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4155 12:20:38.240931 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4156 12:20:38.244243 == TX Byte 1 ==
4157 12:20:38.247721 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4158 12:20:38.250917 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4159 12:20:38.250997
4160 12:20:38.254167 [DATLAT]
4161 12:20:38.254274 Freq=600, CH0 RK1
4162 12:20:38.254424
4163 12:20:38.257749 DATLAT Default: 0x8
4164 12:20:38.257827 0, 0xFFFF, sum = 0
4165 12:20:38.261040 1, 0xFFFF, sum = 0
4166 12:20:38.261120 2, 0xFFFF, sum = 0
4167 12:20:38.264102 3, 0xFFFF, sum = 0
4168 12:20:38.264189 4, 0xFFFF, sum = 0
4169 12:20:38.267391 5, 0xFFFF, sum = 0
4170 12:20:38.267485 6, 0xFFFF, sum = 0
4171 12:20:38.270692 7, 0x0, sum = 1
4172 12:20:38.270772 8, 0x0, sum = 2
4173 12:20:38.274056 9, 0x0, sum = 3
4174 12:20:38.274136 10, 0x0, sum = 4
4175 12:20:38.277573 best_step = 8
4176 12:20:38.277667
4177 12:20:38.277742 ==
4178 12:20:38.280926 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 12:20:38.283908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4180 12:20:38.283987 ==
4181 12:20:38.287452 RX Vref Scan: 0
4182 12:20:38.287530
4183 12:20:38.287592 RX Vref 0 -> 0, step: 1
4184 12:20:38.287649
4185 12:20:38.290659 RX Delay -179 -> 252, step: 8
4186 12:20:38.297369 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4187 12:20:38.300556 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4188 12:20:38.304188 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4189 12:20:38.307186 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4190 12:20:38.314044 iDelay=205, Bit 4, Center 48 (-107 ~ 204) 312
4191 12:20:38.317264 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4192 12:20:38.320418 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4193 12:20:38.323702 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4194 12:20:38.330416 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4195 12:20:38.333766 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4196 12:20:38.336973 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4197 12:20:38.340292 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4198 12:20:38.343824 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4199 12:20:38.350031 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4200 12:20:38.353581 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4201 12:20:38.356833 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4202 12:20:38.356912 ==
4203 12:20:38.360056 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 12:20:38.366649 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4205 12:20:38.366765 ==
4206 12:20:38.366889 DQS Delay:
4207 12:20:38.369977 DQS0 = 0, DQS1 = 0
4208 12:20:38.370059 DQM Delay:
4209 12:20:38.370121 DQM0 = 42, DQM1 = 32
4210 12:20:38.373238 DQ Delay:
4211 12:20:38.376973 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4212 12:20:38.379869 DQ4 =48, DQ5 =32, DQ6 =48, DQ7 =52
4213 12:20:38.383110 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4214 12:20:38.386227 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4215 12:20:38.386306
4216 12:20:38.386368
4217 12:20:38.393037 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c6c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4218 12:20:38.396339 CH0 RK1: MR19=808, MR18=6C6C
4219 12:20:38.403059 CH0_RK1: MR19=0x808, MR18=0x6C6C, DQSOSC=389, MR23=63, INC=173, DEC=115
4220 12:20:38.406300 [RxdqsGatingPostProcess] freq 600
4221 12:20:38.409638 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4222 12:20:38.413031 Pre-setting of DQS Precalculation
4223 12:20:38.419542 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4224 12:20:38.419623 ==
4225 12:20:38.423049 Dram Type= 6, Freq= 0, CH_1, rank 0
4226 12:20:38.426346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4227 12:20:38.426428 ==
4228 12:20:38.432991 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4229 12:20:38.439433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4230 12:20:38.442950 [CA 0] Center 35 (5~66) winsize 62
4231 12:20:38.446076 [CA 1] Center 35 (4~66) winsize 63
4232 12:20:38.449222 [CA 2] Center 33 (3~64) winsize 62
4233 12:20:38.452590 [CA 3] Center 33 (3~64) winsize 62
4234 12:20:38.455996 [CA 4] Center 33 (2~64) winsize 63
4235 12:20:38.459406 [CA 5] Center 33 (2~64) winsize 63
4236 12:20:38.459487
4237 12:20:38.462357 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4238 12:20:38.462437
4239 12:20:38.465865 [CATrainingPosCal] consider 1 rank data
4240 12:20:38.469182 u2DelayCellTimex100 = 270/100 ps
4241 12:20:38.472575 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4242 12:20:38.475828 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4243 12:20:38.478933 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4244 12:20:38.482201 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4245 12:20:38.485484 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4246 12:20:38.489227 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4247 12:20:38.489308
4248 12:20:38.495708 CA PerBit enable=1, Macro0, CA PI delay=33
4249 12:20:38.495789
4250 12:20:38.495853 [CBTSetCACLKResult] CA Dly = 33
4251 12:20:38.498772 CS Dly: 3 (0~34)
4252 12:20:38.498853 ==
4253 12:20:38.502173 Dram Type= 6, Freq= 0, CH_1, rank 1
4254 12:20:38.505504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4255 12:20:38.505597 ==
4256 12:20:38.512105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4257 12:20:38.518718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4258 12:20:38.522232 [CA 0] Center 35 (4~66) winsize 63
4259 12:20:38.525291 [CA 1] Center 34 (4~65) winsize 62
4260 12:20:38.528576 [CA 2] Center 33 (3~64) winsize 62
4261 12:20:38.532096 [CA 3] Center 33 (3~64) winsize 62
4262 12:20:38.535313 [CA 4] Center 32 (2~63) winsize 62
4263 12:20:38.538811 [CA 5] Center 32 (2~63) winsize 62
4264 12:20:38.538890
4265 12:20:38.542005 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4266 12:20:38.542085
4267 12:20:38.545167 [CATrainingPosCal] consider 2 rank data
4268 12:20:38.548696 u2DelayCellTimex100 = 270/100 ps
4269 12:20:38.551923 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4270 12:20:38.554956 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4271 12:20:38.558499 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4272 12:20:38.561844 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4273 12:20:38.565020 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4274 12:20:38.571751 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4275 12:20:38.571860
4276 12:20:38.575062 CA PerBit enable=1, Macro0, CA PI delay=32
4277 12:20:38.575173
4278 12:20:38.578384 [CBTSetCACLKResult] CA Dly = 32
4279 12:20:38.578467 CS Dly: 4 (0~36)
4280 12:20:38.578560
4281 12:20:38.581523 ----->DramcWriteLeveling(PI) begin...
4282 12:20:38.581620 ==
4283 12:20:38.585053 Dram Type= 6, Freq= 0, CH_1, rank 0
4284 12:20:38.591404 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4285 12:20:38.591487 ==
4286 12:20:38.594698 Write leveling (Byte 0): 27 => 27
4287 12:20:38.594780 Write leveling (Byte 1): 27 => 27
4288 12:20:38.597973 DramcWriteLeveling(PI) end<-----
4289 12:20:38.598054
4290 12:20:38.601459 ==
4291 12:20:38.601553 Dram Type= 6, Freq= 0, CH_1, rank 0
4292 12:20:38.607813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4293 12:20:38.607894 ==
4294 12:20:38.611070 [Gating] SW mode calibration
4295 12:20:38.617742 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4296 12:20:38.621063 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4297 12:20:38.627740 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4298 12:20:38.630990 0 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4299 12:20:38.634528 0 5 8 | B1->B0 | 2f2f 2a2a | 0 0 | (0 1) (0 0)
4300 12:20:38.641037 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4301 12:20:38.644110 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4302 12:20:38.647565 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4303 12:20:38.654370 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4304 12:20:38.657871 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4305 12:20:38.660852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4306 12:20:38.667562 0 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
4307 12:20:38.670832 0 6 8 | B1->B0 | 3838 4444 | 0 0 | (0 0) (1 1)
4308 12:20:38.674326 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4309 12:20:38.680807 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4310 12:20:38.683845 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4311 12:20:38.687255 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4312 12:20:38.693972 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4313 12:20:38.697304 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4314 12:20:38.700613 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4315 12:20:38.707218 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4316 12:20:38.710556 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 12:20:38.713921 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 12:20:38.717103 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 12:20:38.723956 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 12:20:38.727464 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 12:20:38.730569 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 12:20:38.737212 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 12:20:38.740616 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 12:20:38.743973 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 12:20:38.750561 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 12:20:38.753857 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4327 12:20:38.757363 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4328 12:20:38.763915 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4329 12:20:38.767301 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4330 12:20:38.770516 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4331 12:20:38.777332 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4332 12:20:38.777482 Total UI for P1: 0, mck2ui 16
4333 12:20:38.783879 best dqsien dly found for B0: ( 0, 9, 4)
4334 12:20:38.783979 Total UI for P1: 0, mck2ui 16
4335 12:20:38.790455 best dqsien dly found for B1: ( 0, 9, 6)
4336 12:20:38.793657 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4337 12:20:38.797043 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4338 12:20:38.797149
4339 12:20:38.800805 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4340 12:20:38.803615 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4341 12:20:38.806888 [Gating] SW calibration Done
4342 12:20:38.806997 ==
4343 12:20:38.810324 Dram Type= 6, Freq= 0, CH_1, rank 0
4344 12:20:38.813522 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4345 12:20:38.813622 ==
4346 12:20:38.816664 RX Vref Scan: 0
4347 12:20:38.816761
4348 12:20:38.816853 RX Vref 0 -> 0, step: 1
4349 12:20:38.816939
4350 12:20:38.819986 RX Delay -230 -> 252, step: 16
4351 12:20:38.826787 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4352 12:20:38.830003 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4353 12:20:38.833297 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4354 12:20:38.836567 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4355 12:20:38.839931 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4356 12:20:38.846465 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4357 12:20:38.850046 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4358 12:20:38.853428 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4359 12:20:38.856614 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4360 12:20:38.863249 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4361 12:20:38.866429 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4362 12:20:38.869911 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4363 12:20:38.873227 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4364 12:20:38.879642 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4365 12:20:38.882873 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4366 12:20:38.886324 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4367 12:20:38.886404 ==
4368 12:20:38.889613 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 12:20:38.892924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4370 12:20:38.893056 ==
4371 12:20:38.896033 DQS Delay:
4372 12:20:38.896163 DQS0 = 0, DQS1 = 0
4373 12:20:38.899509 DQM Delay:
4374 12:20:38.899641 DQM0 = 38, DQM1 = 32
4375 12:20:38.899763 DQ Delay:
4376 12:20:38.902810 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4377 12:20:38.906316 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4378 12:20:38.909700 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4379 12:20:38.912647 DQ12 =33, DQ13 =49, DQ14 =33, DQ15 =41
4380 12:20:38.912778
4381 12:20:38.912897
4382 12:20:38.916591 ==
4383 12:20:38.919275 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 12:20:38.922618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4385 12:20:38.922721 ==
4386 12:20:38.922812
4387 12:20:38.922898
4388 12:20:38.926301 TX Vref Scan disable
4389 12:20:38.926398 == TX Byte 0 ==
4390 12:20:38.932630 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4391 12:20:38.936003 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4392 12:20:38.936100 == TX Byte 1 ==
4393 12:20:38.942658 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4394 12:20:38.946030 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4395 12:20:38.946139 ==
4396 12:20:38.949210 Dram Type= 6, Freq= 0, CH_1, rank 0
4397 12:20:38.952545 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4398 12:20:38.952626 ==
4399 12:20:38.952692
4400 12:20:38.952757
4401 12:20:38.955759 TX Vref Scan disable
4402 12:20:38.959323 == TX Byte 0 ==
4403 12:20:38.962581 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4404 12:20:38.965675 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4405 12:20:38.968997 == TX Byte 1 ==
4406 12:20:38.972168 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4407 12:20:38.975567 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4408 12:20:38.975694
4409 12:20:38.979219 [DATLAT]
4410 12:20:38.979354 Freq=600, CH1 RK0
4411 12:20:38.979478
4412 12:20:38.982783 DATLAT Default: 0x9
4413 12:20:38.982910 0, 0xFFFF, sum = 0
4414 12:20:38.985788 1, 0xFFFF, sum = 0
4415 12:20:38.985919 2, 0xFFFF, sum = 0
4416 12:20:38.989302 3, 0xFFFF, sum = 0
4417 12:20:38.989431 4, 0xFFFF, sum = 0
4418 12:20:38.992253 5, 0xFFFF, sum = 0
4419 12:20:38.992376 6, 0xFFFF, sum = 0
4420 12:20:38.995784 7, 0x0, sum = 1
4421 12:20:38.995911 8, 0x0, sum = 2
4422 12:20:38.998844 9, 0x0, sum = 3
4423 12:20:38.998929 10, 0x0, sum = 4
4424 12:20:39.002144 best_step = 8
4425 12:20:39.002224
4426 12:20:39.002287 ==
4427 12:20:39.005436 Dram Type= 6, Freq= 0, CH_1, rank 0
4428 12:20:39.008618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4429 12:20:39.008699 ==
4430 12:20:39.011921 RX Vref Scan: 1
4431 12:20:39.012001
4432 12:20:39.012063 RX Vref 0 -> 0, step: 1
4433 12:20:39.012122
4434 12:20:39.015468 RX Delay -195 -> 252, step: 8
4435 12:20:39.015548
4436 12:20:39.018563 Set Vref, RX VrefLevel [Byte0]: 59
4437 12:20:39.021879 [Byte1]: 48
4438 12:20:39.025522
4439 12:20:39.025625 Final RX Vref Byte 0 = 59 to rank0
4440 12:20:39.028951 Final RX Vref Byte 1 = 48 to rank0
4441 12:20:39.032358 Final RX Vref Byte 0 = 59 to rank1
4442 12:20:39.035804 Final RX Vref Byte 1 = 48 to rank1==
4443 12:20:39.039057 Dram Type= 6, Freq= 0, CH_1, rank 0
4444 12:20:39.045675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4445 12:20:39.045779 ==
4446 12:20:39.045870 DQS Delay:
4447 12:20:39.045957 DQS0 = 0, DQS1 = 0
4448 12:20:39.048778 DQM Delay:
4449 12:20:39.048854 DQM0 = 37, DQM1 = 30
4450 12:20:39.052138 DQ Delay:
4451 12:20:39.055400 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4452 12:20:39.058793 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4453 12:20:39.058865 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4454 12:20:39.065568 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4455 12:20:39.065668
4456 12:20:39.065759
4457 12:20:39.072049 [DQSOSCAuto] RK0, (LSB)MR18= 0x7b7b, (MSB)MR19= 0x808, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
4458 12:20:39.075389 CH1 RK0: MR19=808, MR18=7B7B
4459 12:20:39.082065 CH1_RK0: MR19=0x808, MR18=0x7B7B, DQSOSC=386, MR23=63, INC=176, DEC=117
4460 12:20:39.082184
4461 12:20:39.085265 ----->DramcWriteLeveling(PI) begin...
4462 12:20:39.085340 ==
4463 12:20:39.088586 Dram Type= 6, Freq= 0, CH_1, rank 1
4464 12:20:39.092096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4465 12:20:39.092200 ==
4466 12:20:39.095425 Write leveling (Byte 0): 28 => 28
4467 12:20:39.098601 Write leveling (Byte 1): 28 => 28
4468 12:20:39.101920 DramcWriteLeveling(PI) end<-----
4469 12:20:39.101999
4470 12:20:39.102061 ==
4471 12:20:39.105125 Dram Type= 6, Freq= 0, CH_1, rank 1
4472 12:20:39.108351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4473 12:20:39.108431 ==
4474 12:20:39.111703 [Gating] SW mode calibration
4475 12:20:39.118262 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 12:20:39.125118 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4477 12:20:39.128442 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 12:20:39.135069 0 5 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
4479 12:20:39.138191 0 5 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
4480 12:20:39.141827 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 12:20:39.148489 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 12:20:39.151561 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 12:20:39.154839 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 12:20:39.161492 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 12:20:39.164667 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 12:20:39.167963 0 6 4 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
4487 12:20:39.174651 0 6 8 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
4488 12:20:39.178271 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 12:20:39.181250 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 12:20:39.184705 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 12:20:39.191479 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 12:20:39.194817 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 12:20:39.198272 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 12:20:39.204597 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 12:20:39.207833 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:20:39.211171 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:20:39.217848 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:20:39.221104 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:20:39.224477 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:20:39.231167 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:20:39.234677 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:20:39.237953 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:20:39.244565 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:20:39.247648 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:20:39.250958 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:20:39.257690 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:20:39.260922 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:20:39.264362 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:20:39.270794 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:20:39.274209 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4511 12:20:39.277500 Total UI for P1: 0, mck2ui 16
4512 12:20:39.280797 best dqsien dly found for B0: ( 0, 9, 2)
4513 12:20:39.284128 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 12:20:39.287360 Total UI for P1: 0, mck2ui 16
4515 12:20:39.290742 best dqsien dly found for B1: ( 0, 9, 4)
4516 12:20:39.294200 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4517 12:20:39.297652 best DQS1 dly(MCK, UI, PI) = (0, 9, 4)
4518 12:20:39.297730
4519 12:20:39.301017 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4520 12:20:39.307330 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 4)
4521 12:20:39.307408 [Gating] SW calibration Done
4522 12:20:39.307470 ==
4523 12:20:39.310871 Dram Type= 6, Freq= 0, CH_1, rank 1
4524 12:20:39.317565 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4525 12:20:39.317644 ==
4526 12:20:39.317706 RX Vref Scan: 0
4527 12:20:39.317764
4528 12:20:39.320618 RX Vref 0 -> 0, step: 1
4529 12:20:39.320696
4530 12:20:39.324137 RX Delay -230 -> 252, step: 16
4531 12:20:39.327596 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4532 12:20:39.331147 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4533 12:20:39.337327 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4534 12:20:39.340513 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4535 12:20:39.344140 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4536 12:20:39.347091 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4537 12:20:39.350359 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4538 12:20:39.357071 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4539 12:20:39.360454 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4540 12:20:39.363720 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4541 12:20:39.367118 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4542 12:20:39.374507 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4543 12:20:39.377009 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4544 12:20:39.380229 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4545 12:20:39.383424 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4546 12:20:39.390633 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4547 12:20:39.390712 ==
4548 12:20:39.393644 Dram Type= 6, Freq= 0, CH_1, rank 1
4549 12:20:39.396846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4550 12:20:39.396925 ==
4551 12:20:39.396987 DQS Delay:
4552 12:20:39.400284 DQS0 = 0, DQS1 = 0
4553 12:20:39.400362 DQM Delay:
4554 12:20:39.403644 DQM0 = 40, DQM1 = 34
4555 12:20:39.403722 DQ Delay:
4556 12:20:39.406953 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4557 12:20:39.410237 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4558 12:20:39.413480 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4559 12:20:39.416758 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4560 12:20:39.416835
4561 12:20:39.416896
4562 12:20:39.416953 ==
4563 12:20:39.420123 Dram Type= 6, Freq= 0, CH_1, rank 1
4564 12:20:39.423246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4565 12:20:39.423325 ==
4566 12:20:39.423386
4567 12:20:39.426626
4568 12:20:39.426703 TX Vref Scan disable
4569 12:20:39.430231 == TX Byte 0 ==
4570 12:20:39.433368 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4571 12:20:39.436749 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4572 12:20:39.440171 == TX Byte 1 ==
4573 12:20:39.443154 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4574 12:20:39.446529 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4575 12:20:39.446608 ==
4576 12:20:39.450069 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 12:20:39.456616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4578 12:20:39.456695 ==
4579 12:20:39.456756
4580 12:20:39.456813
4581 12:20:39.456867 TX Vref Scan disable
4582 12:20:39.461139 == TX Byte 0 ==
4583 12:20:39.464617 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4584 12:20:39.467770 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4585 12:20:39.471068 == TX Byte 1 ==
4586 12:20:39.474389 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4587 12:20:39.477978 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4588 12:20:39.481093
4589 12:20:39.481171 [DATLAT]
4590 12:20:39.481247 Freq=600, CH1 RK1
4591 12:20:39.481332
4592 12:20:39.484363 DATLAT Default: 0x8
4593 12:20:39.484441 0, 0xFFFF, sum = 0
4594 12:20:39.487528 1, 0xFFFF, sum = 0
4595 12:20:39.487607 2, 0xFFFF, sum = 0
4596 12:20:39.490970 3, 0xFFFF, sum = 0
4597 12:20:39.494285 4, 0xFFFF, sum = 0
4598 12:20:39.494364 5, 0xFFFF, sum = 0
4599 12:20:39.497529 6, 0xFFFF, sum = 0
4600 12:20:39.497608 7, 0x0, sum = 1
4601 12:20:39.497671 8, 0x0, sum = 2
4602 12:20:39.500730 9, 0x0, sum = 3
4603 12:20:39.500809 10, 0x0, sum = 4
4604 12:20:39.504165 best_step = 8
4605 12:20:39.504280
4606 12:20:39.504342 ==
4607 12:20:39.507511 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 12:20:39.510847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4609 12:20:39.510928 ==
4610 12:20:39.514348 RX Vref Scan: 0
4611 12:20:39.514429
4612 12:20:39.514493 RX Vref 0 -> 0, step: 1
4613 12:20:39.514554
4614 12:20:39.517255 RX Delay -195 -> 252, step: 8
4615 12:20:39.524741 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4616 12:20:39.527876 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4617 12:20:39.531353 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4618 12:20:39.534455 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4619 12:20:39.541249 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4620 12:20:39.544607 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4621 12:20:39.547869 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4622 12:20:39.551507 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4623 12:20:39.554390 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4624 12:20:39.560987 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4625 12:20:39.564518 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4626 12:20:39.567727 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4627 12:20:39.570941 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4628 12:20:39.577948 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4629 12:20:39.581033 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4630 12:20:39.584361 iDelay=205, Bit 15, Center 36 (-115 ~ 188) 304
4631 12:20:39.584479 ==
4632 12:20:39.587627 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 12:20:39.594397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4634 12:20:39.594478 ==
4635 12:20:39.594542 DQS Delay:
4636 12:20:39.594601 DQS0 = 0, DQS1 = 0
4637 12:20:39.597594 DQM Delay:
4638 12:20:39.597674 DQM0 = 37, DQM1 = 29
4639 12:20:39.600943 DQ Delay:
4640 12:20:39.604418 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4641 12:20:39.604498 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4642 12:20:39.607580 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4643 12:20:39.614290 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =36
4644 12:20:39.614369
4645 12:20:39.614430
4646 12:20:39.620880 [DQSOSCAuto] RK1, (LSB)MR18= 0x6060, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4647 12:20:39.624068 CH1 RK1: MR19=808, MR18=6060
4648 12:20:39.630809 CH1_RK1: MR19=0x808, MR18=0x6060, DQSOSC=391, MR23=63, INC=171, DEC=114
4649 12:20:39.634265 [RxdqsGatingPostProcess] freq 600
4650 12:20:39.637595 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4651 12:20:39.640649 Pre-setting of DQS Precalculation
4652 12:20:39.647331 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4653 12:20:39.654064 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4654 12:20:39.660843 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4655 12:20:39.660922
4656 12:20:39.660984
4657 12:20:39.663956 [Calibration Summary] 1200 Mbps
4658 12:20:39.664034 CH 0, Rank 0
4659 12:20:39.667490 SW Impedance : PASS
4660 12:20:39.670691 DUTY Scan : NO K
4661 12:20:39.670770 ZQ Calibration : PASS
4662 12:20:39.673834 Jitter Meter : NO K
4663 12:20:39.677206 CBT Training : PASS
4664 12:20:39.677284 Write leveling : PASS
4665 12:20:39.680462 RX DQS gating : PASS
4666 12:20:39.683676 RX DQ/DQS(RDDQC) : PASS
4667 12:20:39.683755 TX DQ/DQS : PASS
4668 12:20:39.687296 RX DATLAT : PASS
4669 12:20:39.687375 RX DQ/DQS(Engine): PASS
4670 12:20:39.690331 TX OE : NO K
4671 12:20:39.690410 All Pass.
4672 12:20:39.690472
4673 12:20:39.693737 CH 0, Rank 1
4674 12:20:39.693816 SW Impedance : PASS
4675 12:20:39.697215 DUTY Scan : NO K
4676 12:20:39.700245 ZQ Calibration : PASS
4677 12:20:39.700337 Jitter Meter : NO K
4678 12:20:39.703507 CBT Training : PASS
4679 12:20:39.707404 Write leveling : PASS
4680 12:20:39.707482 RX DQS gating : PASS
4681 12:20:39.710320 RX DQ/DQS(RDDQC) : PASS
4682 12:20:39.713491 TX DQ/DQS : PASS
4683 12:20:39.713571 RX DATLAT : PASS
4684 12:20:39.716963 RX DQ/DQS(Engine): PASS
4685 12:20:39.720356 TX OE : NO K
4686 12:20:39.720435 All Pass.
4687 12:20:39.720497
4688 12:20:39.720555 CH 1, Rank 0
4689 12:20:39.723544 SW Impedance : PASS
4690 12:20:39.726781 DUTY Scan : NO K
4691 12:20:39.726860 ZQ Calibration : PASS
4692 12:20:39.730274 Jitter Meter : NO K
4693 12:20:39.733319 CBT Training : PASS
4694 12:20:39.733398 Write leveling : PASS
4695 12:20:39.736905 RX DQS gating : PASS
4696 12:20:39.740123 RX DQ/DQS(RDDQC) : PASS
4697 12:20:39.740257 TX DQ/DQS : PASS
4698 12:20:39.743534 RX DATLAT : PASS
4699 12:20:39.743612 RX DQ/DQS(Engine): PASS
4700 12:20:39.747358 TX OE : NO K
4701 12:20:39.747437 All Pass.
4702 12:20:39.747500
4703 12:20:39.749964 CH 1, Rank 1
4704 12:20:39.750043 SW Impedance : PASS
4705 12:20:39.753379 DUTY Scan : NO K
4706 12:20:39.756702 ZQ Calibration : PASS
4707 12:20:39.756781 Jitter Meter : NO K
4708 12:20:39.760303 CBT Training : PASS
4709 12:20:39.764005 Write leveling : PASS
4710 12:20:39.764083 RX DQS gating : PASS
4711 12:20:39.766652 RX DQ/DQS(RDDQC) : PASS
4712 12:20:39.770282 TX DQ/DQS : PASS
4713 12:20:39.770360 RX DATLAT : PASS
4714 12:20:39.773267 RX DQ/DQS(Engine): PASS
4715 12:20:39.776754 TX OE : NO K
4716 12:20:39.776832 All Pass.
4717 12:20:39.776894
4718 12:20:39.776952 DramC Write-DBI off
4719 12:20:39.779926 PER_BANK_REFRESH: Hybrid Mode
4720 12:20:39.783449 TX_TRACKING: ON
4721 12:20:39.790177 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4722 12:20:39.793279 [FAST_K] Save calibration result to emmc
4723 12:20:39.799795 dramc_set_vcore_voltage set vcore to 662500
4724 12:20:39.799874 Read voltage for 933, 3
4725 12:20:39.803175 Vio18 = 0
4726 12:20:39.803253 Vcore = 662500
4727 12:20:39.803316 Vdram = 0
4728 12:20:39.806603 Vddq = 0
4729 12:20:39.806682 Vmddr = 0
4730 12:20:39.809874 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4731 12:20:39.816427 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4732 12:20:39.819887 MEM_TYPE=3, freq_sel=17
4733 12:20:39.819967 sv_algorithm_assistance_LP4_1600
4734 12:20:39.826573 ============ PULL DRAM RESETB DOWN ============
4735 12:20:39.829940 ========== PULL DRAM RESETB DOWN end =========
4736 12:20:39.833079 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4737 12:20:39.836392 ===================================
4738 12:20:39.839693 LPDDR4 DRAM CONFIGURATION
4739 12:20:39.843215 ===================================
4740 12:20:39.846368 EX_ROW_EN[0] = 0x0
4741 12:20:39.846446 EX_ROW_EN[1] = 0x0
4742 12:20:39.849945 LP4Y_EN = 0x0
4743 12:20:39.850088 WORK_FSP = 0x0
4744 12:20:39.852896 WL = 0x3
4745 12:20:39.852974 RL = 0x3
4746 12:20:39.856751 BL = 0x2
4747 12:20:39.856830 RPST = 0x0
4748 12:20:39.860025 RD_PRE = 0x0
4749 12:20:39.860103 WR_PRE = 0x1
4750 12:20:39.862945 WR_PST = 0x0
4751 12:20:39.863024 DBI_WR = 0x0
4752 12:20:39.866277 DBI_RD = 0x0
4753 12:20:39.869667 OTF = 0x1
4754 12:20:39.869746 ===================================
4755 12:20:39.872940 ===================================
4756 12:20:39.876169 ANA top config
4757 12:20:39.879554 ===================================
4758 12:20:39.882962 DLL_ASYNC_EN = 0
4759 12:20:39.883041 ALL_SLAVE_EN = 1
4760 12:20:39.886173 NEW_RANK_MODE = 1
4761 12:20:39.889397 DLL_IDLE_MODE = 1
4762 12:20:39.892767 LP45_APHY_COMB_EN = 1
4763 12:20:39.896186 TX_ODT_DIS = 1
4764 12:20:39.896286 NEW_8X_MODE = 1
4765 12:20:39.899632 ===================================
4766 12:20:39.903079 ===================================
4767 12:20:39.906319 data_rate = 1866
4768 12:20:39.909536 CKR = 1
4769 12:20:39.912998 DQ_P2S_RATIO = 8
4770 12:20:39.916244 ===================================
4771 12:20:39.919658 CA_P2S_RATIO = 8
4772 12:20:39.919756 DQ_CA_OPEN = 0
4773 12:20:39.923056 DQ_SEMI_OPEN = 0
4774 12:20:39.926196 CA_SEMI_OPEN = 0
4775 12:20:39.929477 CA_FULL_RATE = 0
4776 12:20:39.932593 DQ_CKDIV4_EN = 1
4777 12:20:39.936045 CA_CKDIV4_EN = 1
4778 12:20:39.936128 CA_PREDIV_EN = 0
4779 12:20:39.939285 PH8_DLY = 0
4780 12:20:39.942656 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4781 12:20:39.945898 DQ_AAMCK_DIV = 4
4782 12:20:39.949408 CA_AAMCK_DIV = 4
4783 12:20:39.952742 CA_ADMCK_DIV = 4
4784 12:20:39.952822 DQ_TRACK_CA_EN = 0
4785 12:20:39.956230 CA_PICK = 933
4786 12:20:39.959393 CA_MCKIO = 933
4787 12:20:39.962777 MCKIO_SEMI = 0
4788 12:20:39.965961 PLL_FREQ = 3732
4789 12:20:39.969203 DQ_UI_PI_RATIO = 32
4790 12:20:39.972616 CA_UI_PI_RATIO = 0
4791 12:20:39.976035 ===================================
4792 12:20:39.979681 ===================================
4793 12:20:39.979761 memory_type:LPDDR4
4794 12:20:39.982814 GP_NUM : 10
4795 12:20:39.985673 SRAM_EN : 1
4796 12:20:39.985752 MD32_EN : 0
4797 12:20:39.989244 ===================================
4798 12:20:39.992354 [ANA_INIT] >>>>>>>>>>>>>>
4799 12:20:39.995648 <<<<<< [CONFIGURE PHASE]: ANA_TX
4800 12:20:39.999099 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4801 12:20:40.002450 ===================================
4802 12:20:40.005717 data_rate = 1866,PCW = 0X8f00
4803 12:20:40.009030 ===================================
4804 12:20:40.012420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4805 12:20:40.015745 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4806 12:20:40.022780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4807 12:20:40.025894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4808 12:20:40.029112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4809 12:20:40.032322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4810 12:20:40.035739 [ANA_INIT] flow start
4811 12:20:40.039370 [ANA_INIT] PLL >>>>>>>>
4812 12:20:40.039449 [ANA_INIT] PLL <<<<<<<<
4813 12:20:40.042455 [ANA_INIT] MIDPI >>>>>>>>
4814 12:20:40.045854 [ANA_INIT] MIDPI <<<<<<<<
4815 12:20:40.049081 [ANA_INIT] DLL >>>>>>>>
4816 12:20:40.049161 [ANA_INIT] flow end
4817 12:20:40.052356 ============ LP4 DIFF to SE enter ============
4818 12:20:40.059020 ============ LP4 DIFF to SE exit ============
4819 12:20:40.059101 [ANA_INIT] <<<<<<<<<<<<<
4820 12:20:40.062424 [Flow] Enable top DCM control >>>>>
4821 12:20:40.065811 [Flow] Enable top DCM control <<<<<
4822 12:20:40.069047 Enable DLL master slave shuffle
4823 12:20:40.075721 ==============================================================
4824 12:20:40.075802 Gating Mode config
4825 12:20:40.082388 ==============================================================
4826 12:20:40.085461 Config description:
4827 12:20:40.092157 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4828 12:20:40.098780 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4829 12:20:40.105727 SELPH_MODE 0: By rank 1: By Phase
4830 12:20:40.112183 ==============================================================
4831 12:20:40.112308 GAT_TRACK_EN = 1
4832 12:20:40.115400 RX_GATING_MODE = 2
4833 12:20:40.118768 RX_GATING_TRACK_MODE = 2
4834 12:20:40.122171 SELPH_MODE = 1
4835 12:20:40.125338 PICG_EARLY_EN = 1
4836 12:20:40.128665 VALID_LAT_VALUE = 1
4837 12:20:40.135424 ==============================================================
4838 12:20:40.138586 Enter into Gating configuration >>>>
4839 12:20:40.142030 Exit from Gating configuration <<<<
4840 12:20:40.145162 Enter into DVFS_PRE_config >>>>>
4841 12:20:40.155209 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4842 12:20:40.158628 Exit from DVFS_PRE_config <<<<<
4843 12:20:40.161783 Enter into PICG configuration >>>>
4844 12:20:40.165205 Exit from PICG configuration <<<<
4845 12:20:40.168343 [RX_INPUT] configuration >>>>>
4846 12:20:40.171680 [RX_INPUT] configuration <<<<<
4847 12:20:40.175219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4848 12:20:40.181638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4849 12:20:40.188587 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4850 12:20:40.191662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4851 12:20:40.198343 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4852 12:20:40.205094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4853 12:20:40.208428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4854 12:20:40.211863 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4855 12:20:40.218325 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4856 12:20:40.221477 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4857 12:20:40.224769 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4858 12:20:40.231958 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4859 12:20:40.234772 ===================================
4860 12:20:40.234851 LPDDR4 DRAM CONFIGURATION
4861 12:20:40.238247 ===================================
4862 12:20:40.241530 EX_ROW_EN[0] = 0x0
4863 12:20:40.244624 EX_ROW_EN[1] = 0x0
4864 12:20:40.244703 LP4Y_EN = 0x0
4865 12:20:40.248044 WORK_FSP = 0x0
4866 12:20:40.248149 WL = 0x3
4867 12:20:40.251210 RL = 0x3
4868 12:20:40.251288 BL = 0x2
4869 12:20:40.254612 RPST = 0x0
4870 12:20:40.254690 RD_PRE = 0x0
4871 12:20:40.258067 WR_PRE = 0x1
4872 12:20:40.258145 WR_PST = 0x0
4873 12:20:40.261353 DBI_WR = 0x0
4874 12:20:40.261432 DBI_RD = 0x0
4875 12:20:40.264557 OTF = 0x1
4876 12:20:40.267779 ===================================
4877 12:20:40.271033 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4878 12:20:40.274820 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4879 12:20:40.281170 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4880 12:20:40.284602 ===================================
4881 12:20:40.284698 LPDDR4 DRAM CONFIGURATION
4882 12:20:40.287816 ===================================
4883 12:20:40.291420 EX_ROW_EN[0] = 0x10
4884 12:20:40.294661 EX_ROW_EN[1] = 0x0
4885 12:20:40.294740 LP4Y_EN = 0x0
4886 12:20:40.297716 WORK_FSP = 0x0
4887 12:20:40.297795 WL = 0x3
4888 12:20:40.301197 RL = 0x3
4889 12:20:40.301276 BL = 0x2
4890 12:20:40.304165 RPST = 0x0
4891 12:20:40.304289 RD_PRE = 0x0
4892 12:20:40.307785 WR_PRE = 0x1
4893 12:20:40.307863 WR_PST = 0x0
4894 12:20:40.311289 DBI_WR = 0x0
4895 12:20:40.311367 DBI_RD = 0x0
4896 12:20:40.314307 OTF = 0x1
4897 12:20:40.317737 ===================================
4898 12:20:40.324325 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4899 12:20:40.327919 nWR fixed to 30
4900 12:20:40.327998 [ModeRegInit_LP4] CH0 RK0
4901 12:20:40.330960 [ModeRegInit_LP4] CH0 RK1
4902 12:20:40.334205 [ModeRegInit_LP4] CH1 RK0
4903 12:20:40.334284 [ModeRegInit_LP4] CH1 RK1
4904 12:20:40.337626 match AC timing 8
4905 12:20:40.341038 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4906 12:20:40.344138 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4907 12:20:40.351012 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4908 12:20:40.354179 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4909 12:20:40.360877 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4910 12:20:40.360956 ==
4911 12:20:40.364118 Dram Type= 6, Freq= 0, CH_0, rank 0
4912 12:20:40.367343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4913 12:20:40.367422 ==
4914 12:20:40.373942 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4915 12:20:40.380654 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4916 12:20:40.384034 [CA 0] Center 38 (8~69) winsize 62
4917 12:20:40.387188 [CA 1] Center 38 (8~69) winsize 62
4918 12:20:40.390634 [CA 2] Center 36 (6~67) winsize 62
4919 12:20:40.393933 [CA 3] Center 36 (5~67) winsize 63
4920 12:20:40.394011 [CA 4] Center 35 (5~65) winsize 61
4921 12:20:40.397376 [CA 5] Center 34 (4~65) winsize 62
4922 12:20:40.397455
4923 12:20:40.403988 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4924 12:20:40.404066
4925 12:20:40.407172 [CATrainingPosCal] consider 1 rank data
4926 12:20:40.410822 u2DelayCellTimex100 = 270/100 ps
4927 12:20:40.413906 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4928 12:20:40.417037 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4929 12:20:40.420439 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4930 12:20:40.424092 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4931 12:20:40.427378 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4932 12:20:40.430525 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4933 12:20:40.430604
4934 12:20:40.433768 CA PerBit enable=1, Macro0, CA PI delay=34
4935 12:20:40.433847
4936 12:20:40.436990 [CBTSetCACLKResult] CA Dly = 34
4937 12:20:40.440378 CS Dly: 7 (0~38)
4938 12:20:40.440456 ==
4939 12:20:40.443781 Dram Type= 6, Freq= 0, CH_0, rank 1
4940 12:20:40.447180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4941 12:20:40.447260 ==
4942 12:20:40.453647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4943 12:20:40.460321 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4944 12:20:40.463811 [CA 0] Center 38 (8~69) winsize 62
4945 12:20:40.467016 [CA 1] Center 38 (8~69) winsize 62
4946 12:20:40.470458 [CA 2] Center 36 (5~67) winsize 63
4947 12:20:40.473519 [CA 3] Center 35 (5~66) winsize 62
4948 12:20:40.476701 [CA 4] Center 34 (4~65) winsize 62
4949 12:20:40.480137 [CA 5] Center 34 (4~65) winsize 62
4950 12:20:40.480271
4951 12:20:40.483582 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4952 12:20:40.483660
4953 12:20:40.486951 [CATrainingPosCal] consider 2 rank data
4954 12:20:40.490189 u2DelayCellTimex100 = 270/100 ps
4955 12:20:40.493500 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4956 12:20:40.496749 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4957 12:20:40.500086 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4958 12:20:40.503504 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4959 12:20:40.506666 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
4960 12:20:40.510064 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4961 12:20:40.510144
4962 12:20:40.516836 CA PerBit enable=1, Macro0, CA PI delay=34
4963 12:20:40.516916
4964 12:20:40.516978 [CBTSetCACLKResult] CA Dly = 34
4965 12:20:40.520056 CS Dly: 7 (0~39)
4966 12:20:40.520135
4967 12:20:40.523330 ----->DramcWriteLeveling(PI) begin...
4968 12:20:40.523410 ==
4969 12:20:40.526636 Dram Type= 6, Freq= 0, CH_0, rank 0
4970 12:20:40.530094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4971 12:20:40.530174 ==
4972 12:20:40.533409 Write leveling (Byte 0): 28 => 28
4973 12:20:40.536961 Write leveling (Byte 1): 28 => 28
4974 12:20:40.540132 DramcWriteLeveling(PI) end<-----
4975 12:20:40.540255
4976 12:20:40.540318 ==
4977 12:20:40.543311 Dram Type= 6, Freq= 0, CH_0, rank 0
4978 12:20:40.546421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4979 12:20:40.549738 ==
4980 12:20:40.549836 [Gating] SW mode calibration
4981 12:20:40.559887 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4982 12:20:40.563053 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4983 12:20:40.566322 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4984 12:20:40.573000 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4985 12:20:40.576307 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4986 12:20:40.579681 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4987 12:20:40.586283 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4988 12:20:40.589653 0 10 20 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
4989 12:20:40.592858 0 10 24 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4990 12:20:40.599469 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4991 12:20:40.602896 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4992 12:20:40.606201 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4993 12:20:40.612699 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4994 12:20:40.616109 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4995 12:20:40.619507 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4996 12:20:40.626384 0 11 20 | B1->B0 | 2424 3333 | 1 0 | (0 0) (0 0)
4997 12:20:40.629493 0 11 24 | B1->B0 | 3939 3d3d | 0 0 | (0 0) (0 0)
4998 12:20:40.632819 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4999 12:20:40.639554 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5000 12:20:40.642869 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5001 12:20:40.645979 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5002 12:20:40.652635 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5003 12:20:40.656101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5004 12:20:40.659280 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5005 12:20:40.665789 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5006 12:20:40.669265 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 12:20:40.672493 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 12:20:40.679073 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 12:20:40.682493 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 12:20:40.685945 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 12:20:40.692382 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 12:20:40.695759 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 12:20:40.698841 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 12:20:40.705410 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 12:20:40.708843 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 12:20:40.712230 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5017 12:20:40.715768 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5018 12:20:40.722028 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5019 12:20:40.725361 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5020 12:20:40.728752 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5021 12:20:40.732296 Total UI for P1: 0, mck2ui 16
5022 12:20:40.735505 best dqsien dly found for B0: ( 0, 14, 18)
5023 12:20:40.739108 Total UI for P1: 0, mck2ui 16
5024 12:20:40.741947 best dqsien dly found for B1: ( 0, 14, 18)
5025 12:20:40.745457 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5026 12:20:40.752015 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5027 12:20:40.752093
5028 12:20:40.755142 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5029 12:20:40.758369 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5030 12:20:40.761896 [Gating] SW calibration Done
5031 12:20:40.761973 ==
5032 12:20:40.765121 Dram Type= 6, Freq= 0, CH_0, rank 0
5033 12:20:40.768413 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5034 12:20:40.768491 ==
5035 12:20:40.771796 RX Vref Scan: 0
5036 12:20:40.771889
5037 12:20:40.771964 RX Vref 0 -> 0, step: 1
5038 12:20:40.772021
5039 12:20:40.775042 RX Delay -80 -> 252, step: 8
5040 12:20:40.778312 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5041 12:20:40.785042 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5042 12:20:40.788348 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5043 12:20:40.791820 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5044 12:20:40.794908 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5045 12:20:40.798184 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5046 12:20:40.801449 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5047 12:20:40.807935 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5048 12:20:40.811502 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5049 12:20:40.814607 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5050 12:20:40.818183 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5051 12:20:40.821417 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5052 12:20:40.827689 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5053 12:20:40.831023 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5054 12:20:40.834474 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5055 12:20:40.837958 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5056 12:20:40.838037 ==
5057 12:20:40.841247 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 12:20:40.844585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5059 12:20:40.844666 ==
5060 12:20:40.847940 DQS Delay:
5061 12:20:40.848019 DQS0 = 0, DQS1 = 0
5062 12:20:40.851064 DQM Delay:
5063 12:20:40.851143 DQM0 = 95, DQM1 = 86
5064 12:20:40.851206 DQ Delay:
5065 12:20:40.854461 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =87
5066 12:20:40.857837 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5067 12:20:40.860957 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5068 12:20:40.864162 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5069 12:20:40.867457
5070 12:20:40.867535
5071 12:20:40.867598 ==
5072 12:20:40.870761 Dram Type= 6, Freq= 0, CH_0, rank 0
5073 12:20:40.874162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5074 12:20:40.874242 ==
5075 12:20:40.874305
5076 12:20:40.874363
5077 12:20:40.877431 TX Vref Scan disable
5078 12:20:40.877510 == TX Byte 0 ==
5079 12:20:40.883961 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5080 12:20:40.887316 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5081 12:20:40.887396 == TX Byte 1 ==
5082 12:20:40.893780 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5083 12:20:40.897432 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5084 12:20:40.897512 ==
5085 12:20:40.900389 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 12:20:40.903760 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5087 12:20:40.903839 ==
5088 12:20:40.903902
5089 12:20:40.903960
5090 12:20:40.907156 TX Vref Scan disable
5091 12:20:40.910364 == TX Byte 0 ==
5092 12:20:40.913789 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5093 12:20:40.916974 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5094 12:20:40.920592 == TX Byte 1 ==
5095 12:20:40.923715 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5096 12:20:40.926748 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5097 12:20:40.926826
5098 12:20:40.930294 [DATLAT]
5099 12:20:40.930371 Freq=933, CH0 RK0
5100 12:20:40.930433
5101 12:20:40.933478 DATLAT Default: 0xd
5102 12:20:40.933555 0, 0xFFFF, sum = 0
5103 12:20:40.936570 1, 0xFFFF, sum = 0
5104 12:20:40.936648 2, 0xFFFF, sum = 0
5105 12:20:40.940104 3, 0xFFFF, sum = 0
5106 12:20:40.940203 4, 0xFFFF, sum = 0
5107 12:20:40.943199 5, 0xFFFF, sum = 0
5108 12:20:40.946851 6, 0xFFFF, sum = 0
5109 12:20:40.946930 7, 0xFFFF, sum = 0
5110 12:20:40.950170 8, 0xFFFF, sum = 0
5111 12:20:40.950250 9, 0xFFFF, sum = 0
5112 12:20:40.953367 10, 0x0, sum = 1
5113 12:20:40.953446 11, 0x0, sum = 2
5114 12:20:40.953508 12, 0x0, sum = 3
5115 12:20:40.956584 13, 0x0, sum = 4
5116 12:20:40.956663 best_step = 11
5117 12:20:40.956725
5118 12:20:40.956782 ==
5119 12:20:40.963054 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 12:20:40.966594 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5121 12:20:40.966672 ==
5122 12:20:40.966749 RX Vref Scan: 1
5123 12:20:40.966821
5124 12:20:40.969615 RX Vref 0 -> 0, step: 1
5125 12:20:40.969692
5126 12:20:40.973028 RX Delay -69 -> 252, step: 4
5127 12:20:40.973106
5128 12:20:40.976437 Set Vref, RX VrefLevel [Byte0]: 50
5129 12:20:40.979882 [Byte1]: 46
5130 12:20:40.979960
5131 12:20:40.983080 Final RX Vref Byte 0 = 50 to rank0
5132 12:20:40.986298 Final RX Vref Byte 1 = 46 to rank0
5133 12:20:40.990022 Final RX Vref Byte 0 = 50 to rank1
5134 12:20:40.993229 Final RX Vref Byte 1 = 46 to rank1==
5135 12:20:40.996091 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 12:20:40.999259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5137 12:20:41.002733 ==
5138 12:20:41.002812 DQS Delay:
5139 12:20:41.002873 DQS0 = 0, DQS1 = 0
5140 12:20:41.005942 DQM Delay:
5141 12:20:41.006021 DQM0 = 96, DQM1 = 86
5142 12:20:41.009275 DQ Delay:
5143 12:20:41.012948 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =92
5144 12:20:41.016034 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =102
5145 12:20:41.019367 DQ8 =76, DQ9 =72, DQ10 =86, DQ11 =78
5146 12:20:41.022750 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =98
5147 12:20:41.022830
5148 12:20:41.022892
5149 12:20:41.029184 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5150 12:20:41.032785 CH0 RK0: MR19=505, MR18=1E1E
5151 12:20:41.039182 CH0_RK0: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5152 12:20:41.039262
5153 12:20:41.042481 ----->DramcWriteLeveling(PI) begin...
5154 12:20:41.042562 ==
5155 12:20:41.045864 Dram Type= 6, Freq= 0, CH_0, rank 1
5156 12:20:41.049088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5157 12:20:41.049168 ==
5158 12:20:41.052340 Write leveling (Byte 0): 30 => 30
5159 12:20:41.055778 Write leveling (Byte 1): 28 => 28
5160 12:20:41.058937 DramcWriteLeveling(PI) end<-----
5161 12:20:41.059016
5162 12:20:41.059078 ==
5163 12:20:41.062074 Dram Type= 6, Freq= 0, CH_0, rank 1
5164 12:20:41.065384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5165 12:20:41.065464 ==
5166 12:20:41.068794 [Gating] SW mode calibration
5167 12:20:41.075566 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5168 12:20:41.082339 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5169 12:20:41.085731 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 12:20:41.092084 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 12:20:41.095427 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 12:20:41.098642 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 12:20:41.105609 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 12:20:41.108685 0 10 20 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 1)
5175 12:20:41.111988 0 10 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5176 12:20:41.118594 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 12:20:41.121949 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 12:20:41.125514 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 12:20:41.131794 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 12:20:41.135121 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 12:20:41.138577 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5182 12:20:41.145108 0 11 20 | B1->B0 | 2c2c 3434 | 0 0 | (1 1) (0 0)
5183 12:20:41.148336 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5184 12:20:41.151889 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 12:20:41.158040 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 12:20:41.161336 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 12:20:41.164615 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 12:20:41.171529 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 12:20:41.174623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 12:20:41.178001 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5191 12:20:41.184763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:20:41.187932 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 12:20:41.191446 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:20:41.197935 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:20:41.201006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:20:41.204516 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:20:41.210884 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:20:41.214290 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:20:41.217589 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:20:41.224008 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:20:41.227371 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:20:41.230698 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:20:41.233989 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:20:41.240716 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:20:41.244093 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:20:41.247650 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5207 12:20:41.253986 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5208 12:20:41.257368 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 12:20:41.260407 Total UI for P1: 0, mck2ui 16
5210 12:20:41.263645 best dqsien dly found for B0: ( 0, 14, 22)
5211 12:20:41.266998 Total UI for P1: 0, mck2ui 16
5212 12:20:41.270659 best dqsien dly found for B1: ( 0, 14, 22)
5213 12:20:41.273833 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5214 12:20:41.277225 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5215 12:20:41.277303
5216 12:20:41.280393 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5217 12:20:41.286905 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5218 12:20:41.286983 [Gating] SW calibration Done
5219 12:20:41.287046 ==
5220 12:20:41.290229 Dram Type= 6, Freq= 0, CH_0, rank 1
5221 12:20:41.296895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5222 12:20:41.296974 ==
5223 12:20:41.297036 RX Vref Scan: 0
5224 12:20:41.297093
5225 12:20:41.300369 RX Vref 0 -> 0, step: 1
5226 12:20:41.300447
5227 12:20:41.303735 RX Delay -80 -> 252, step: 8
5228 12:20:41.306747 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5229 12:20:41.310096 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5230 12:20:41.313501 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5231 12:20:41.319985 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5232 12:20:41.323182 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5233 12:20:41.326670 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5234 12:20:41.329954 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5235 12:20:41.333430 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5236 12:20:41.336583 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5237 12:20:41.343074 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5238 12:20:41.346502 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5239 12:20:41.349872 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5240 12:20:41.353056 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5241 12:20:41.356485 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5242 12:20:41.363295 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5243 12:20:41.366410 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5244 12:20:41.366489 ==
5245 12:20:41.369658 Dram Type= 6, Freq= 0, CH_0, rank 1
5246 12:20:41.372809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5247 12:20:41.372889 ==
5248 12:20:41.372952 DQS Delay:
5249 12:20:41.376183 DQS0 = 0, DQS1 = 0
5250 12:20:41.376263 DQM Delay:
5251 12:20:41.379422 DQM0 = 96, DQM1 = 86
5252 12:20:41.379501 DQ Delay:
5253 12:20:41.383328 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =87
5254 12:20:41.386103 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5255 12:20:41.389518 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =75
5256 12:20:41.392641 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5257 12:20:41.392720
5258 12:20:41.392783
5259 12:20:41.392841 ==
5260 12:20:41.396116 Dram Type= 6, Freq= 0, CH_0, rank 1
5261 12:20:41.402562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5262 12:20:41.402642 ==
5263 12:20:41.402705
5264 12:20:41.402763
5265 12:20:41.402819 TX Vref Scan disable
5266 12:20:41.405865 == TX Byte 0 ==
5267 12:20:41.409455 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5268 12:20:41.412692 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5269 12:20:41.415968 == TX Byte 1 ==
5270 12:20:41.419114 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5271 12:20:41.422700 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5272 12:20:41.425917 ==
5273 12:20:41.429226 Dram Type= 6, Freq= 0, CH_0, rank 1
5274 12:20:41.432589 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5275 12:20:41.432685 ==
5276 12:20:41.432747
5277 12:20:41.432805
5278 12:20:41.435808 TX Vref Scan disable
5279 12:20:41.435912 == TX Byte 0 ==
5280 12:20:41.442279 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5281 12:20:41.445922 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5282 12:20:41.446001 == TX Byte 1 ==
5283 12:20:41.452155 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5284 12:20:41.455573 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5285 12:20:41.455653
5286 12:20:41.455716 [DATLAT]
5287 12:20:41.458910 Freq=933, CH0 RK1
5288 12:20:41.458990
5289 12:20:41.459053 DATLAT Default: 0xb
5290 12:20:41.462374 0, 0xFFFF, sum = 0
5291 12:20:41.462455 1, 0xFFFF, sum = 0
5292 12:20:41.465397 2, 0xFFFF, sum = 0
5293 12:20:41.465478 3, 0xFFFF, sum = 0
5294 12:20:41.469003 4, 0xFFFF, sum = 0
5295 12:20:41.469084 5, 0xFFFF, sum = 0
5296 12:20:41.472404 6, 0xFFFF, sum = 0
5297 12:20:41.475522 7, 0xFFFF, sum = 0
5298 12:20:41.475603 8, 0xFFFF, sum = 0
5299 12:20:41.478798 9, 0xFFFF, sum = 0
5300 12:20:41.478878 10, 0x0, sum = 1
5301 12:20:41.478942 11, 0x0, sum = 2
5302 12:20:41.482058 12, 0x0, sum = 3
5303 12:20:41.482139 13, 0x0, sum = 4
5304 12:20:41.485647 best_step = 11
5305 12:20:41.485727
5306 12:20:41.485789 ==
5307 12:20:41.488573 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 12:20:41.492114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5309 12:20:41.492250 ==
5310 12:20:41.495415 RX Vref Scan: 0
5311 12:20:41.495495
5312 12:20:41.495557 RX Vref 0 -> 0, step: 1
5313 12:20:41.498610
5314 12:20:41.498689 RX Delay -69 -> 252, step: 4
5315 12:20:41.506355 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5316 12:20:41.509824 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5317 12:20:41.512959 iDelay=203, Bit 2, Center 96 (3 ~ 190) 188
5318 12:20:41.516370 iDelay=203, Bit 3, Center 94 (7 ~ 182) 176
5319 12:20:41.519295 iDelay=203, Bit 4, Center 100 (7 ~ 194) 188
5320 12:20:41.522850 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5321 12:20:41.529800 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5322 12:20:41.532842 iDelay=203, Bit 7, Center 110 (19 ~ 202) 184
5323 12:20:41.536246 iDelay=203, Bit 8, Center 74 (-13 ~ 162) 176
5324 12:20:41.539532 iDelay=203, Bit 9, Center 72 (-17 ~ 162) 180
5325 12:20:41.543060 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5326 12:20:41.549625 iDelay=203, Bit 11, Center 78 (-9 ~ 166) 176
5327 12:20:41.552651 iDelay=203, Bit 12, Center 94 (7 ~ 182) 176
5328 12:20:41.556094 iDelay=203, Bit 13, Center 90 (-1 ~ 182) 184
5329 12:20:41.559410 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5330 12:20:41.562691 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5331 12:20:41.562771 ==
5332 12:20:41.565866 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 12:20:41.572523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5334 12:20:41.572604 ==
5335 12:20:41.572667 DQS Delay:
5336 12:20:41.575901 DQS0 = 0, DQS1 = 0
5337 12:20:41.575980 DQM Delay:
5338 12:20:41.576042 DQM0 = 97, DQM1 = 86
5339 12:20:41.579349 DQ Delay:
5340 12:20:41.582406 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5341 12:20:41.585798 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =110
5342 12:20:41.589214 DQ8 =74, DQ9 =72, DQ10 =88, DQ11 =78
5343 12:20:41.592472 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =96
5344 12:20:41.592551
5345 12:20:41.592613
5346 12:20:41.599319 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5347 12:20:41.602739 CH0 RK1: MR19=505, MR18=2A2A
5348 12:20:41.609110 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5349 12:20:41.612219 [RxdqsGatingPostProcess] freq 933
5350 12:20:41.615548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5351 12:20:41.619310 Pre-setting of DQS Precalculation
5352 12:20:41.625576 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5353 12:20:41.625660 ==
5354 12:20:41.628786 Dram Type= 6, Freq= 0, CH_1, rank 0
5355 12:20:41.632309 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5356 12:20:41.632393 ==
5357 12:20:41.638977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5358 12:20:41.645633 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5359 12:20:41.648601 [CA 0] Center 37 (7~68) winsize 62
5360 12:20:41.652036 [CA 1] Center 37 (6~68) winsize 63
5361 12:20:41.655412 [CA 2] Center 34 (4~65) winsize 62
5362 12:20:41.658657 [CA 3] Center 34 (4~65) winsize 62
5363 12:20:41.661929 [CA 4] Center 33 (2~64) winsize 63
5364 12:20:41.665542 [CA 5] Center 33 (2~64) winsize 63
5365 12:20:41.665621
5366 12:20:41.668765 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5367 12:20:41.668870
5368 12:20:41.671932 [CATrainingPosCal] consider 1 rank data
5369 12:20:41.675376 u2DelayCellTimex100 = 270/100 ps
5370 12:20:41.678796 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5371 12:20:41.681954 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5372 12:20:41.685265 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5373 12:20:41.688607 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5374 12:20:41.691965 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5375 12:20:41.695357 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5376 12:20:41.695437
5377 12:20:41.701772 CA PerBit enable=1, Macro0, CA PI delay=33
5378 12:20:41.701852
5379 12:20:41.701914 [CBTSetCACLKResult] CA Dly = 33
5380 12:20:41.705218 CS Dly: 5 (0~36)
5381 12:20:41.705296 ==
5382 12:20:41.708652 Dram Type= 6, Freq= 0, CH_1, rank 1
5383 12:20:41.711848 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5384 12:20:41.711928 ==
5385 12:20:41.718596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5386 12:20:41.724923 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5387 12:20:41.728196 [CA 0] Center 37 (6~68) winsize 63
5388 12:20:41.731528 [CA 1] Center 37 (6~68) winsize 63
5389 12:20:41.735010 [CA 2] Center 34 (4~65) winsize 62
5390 12:20:41.738616 [CA 3] Center 33 (3~64) winsize 62
5391 12:20:41.741614 [CA 4] Center 33 (2~64) winsize 63
5392 12:20:41.744876 [CA 5] Center 32 (2~63) winsize 62
5393 12:20:41.744954
5394 12:20:41.748226 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5395 12:20:41.748305
5396 12:20:41.751511 [CATrainingPosCal] consider 2 rank data
5397 12:20:41.754923 u2DelayCellTimex100 = 270/100 ps
5398 12:20:41.758559 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5399 12:20:41.761561 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5400 12:20:41.764779 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5401 12:20:41.768098 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5402 12:20:41.771317 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5403 12:20:41.777997 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5404 12:20:41.778076
5405 12:20:41.781395 CA PerBit enable=1, Macro0, CA PI delay=32
5406 12:20:41.781473
5407 12:20:41.784642 [CBTSetCACLKResult] CA Dly = 32
5408 12:20:41.784721 CS Dly: 5 (0~37)
5409 12:20:41.784783
5410 12:20:41.787817 ----->DramcWriteLeveling(PI) begin...
5411 12:20:41.787899 ==
5412 12:20:41.791205 Dram Type= 6, Freq= 0, CH_1, rank 0
5413 12:20:41.797824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5414 12:20:41.797905 ==
5415 12:20:41.801219 Write leveling (Byte 0): 26 => 26
5416 12:20:41.801299 Write leveling (Byte 1): 26 => 26
5417 12:20:41.804383 DramcWriteLeveling(PI) end<-----
5418 12:20:41.804464
5419 12:20:41.804527 ==
5420 12:20:41.807821 Dram Type= 6, Freq= 0, CH_1, rank 0
5421 12:20:41.814422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5422 12:20:41.814502 ==
5423 12:20:41.817919 [Gating] SW mode calibration
5424 12:20:41.824411 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5425 12:20:41.827746 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5426 12:20:41.834647 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 12:20:41.837735 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5428 12:20:41.840891 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5429 12:20:41.847481 0 10 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5430 12:20:41.850983 0 10 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5431 12:20:41.853893 0 10 20 | B1->B0 | 3434 2424 | 0 0 | (0 1) (0 0)
5432 12:20:41.860787 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5433 12:20:41.864076 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 12:20:41.867389 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 12:20:41.874011 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5436 12:20:41.877489 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5437 12:20:41.880789 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5438 12:20:41.887087 0 11 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
5439 12:20:41.890415 0 11 20 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
5440 12:20:41.894053 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5441 12:20:41.900445 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 12:20:41.903936 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 12:20:41.907271 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 12:20:41.910487 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5445 12:20:41.917018 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5446 12:20:41.920433 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5447 12:20:41.923693 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5448 12:20:41.930433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 12:20:41.933710 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 12:20:41.936854 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 12:20:41.943917 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 12:20:41.947161 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 12:20:41.950398 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 12:20:41.957332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 12:20:41.960328 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 12:20:41.963557 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 12:20:41.970239 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 12:20:41.973692 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 12:20:41.976821 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 12:20:41.983585 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 12:20:41.986728 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5462 12:20:41.990281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5463 12:20:41.993345 Total UI for P1: 0, mck2ui 16
5464 12:20:41.996838 best dqsien dly found for B0: ( 0, 14, 14)
5465 12:20:42.003390 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5466 12:20:42.006728 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5467 12:20:42.010087 Total UI for P1: 0, mck2ui 16
5468 12:20:42.013310 best dqsien dly found for B1: ( 0, 14, 18)
5469 12:20:42.016574 best DQS0 dly(MCK, UI, PI) = (0, 14, 14)
5470 12:20:42.019780 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5471 12:20:42.019858
5472 12:20:42.023099 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 14)
5473 12:20:42.026410 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5474 12:20:42.029655 [Gating] SW calibration Done
5475 12:20:42.029734 ==
5476 12:20:42.033398 Dram Type= 6, Freq= 0, CH_1, rank 0
5477 12:20:42.039769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5478 12:20:42.039848 ==
5479 12:20:42.039910 RX Vref Scan: 0
5480 12:20:42.039969
5481 12:20:42.043048 RX Vref 0 -> 0, step: 1
5482 12:20:42.043127
5483 12:20:42.046438 RX Delay -80 -> 252, step: 8
5484 12:20:42.049807 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5485 12:20:42.053153 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5486 12:20:42.056342 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5487 12:20:42.059612 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5488 12:20:42.066107 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5489 12:20:42.069547 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5490 12:20:42.072905 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5491 12:20:42.076098 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5492 12:20:42.079725 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5493 12:20:42.082740 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5494 12:20:42.089414 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5495 12:20:42.092667 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5496 12:20:42.096192 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5497 12:20:42.099491 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5498 12:20:42.102835 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5499 12:20:42.109331 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5500 12:20:42.109409 ==
5501 12:20:42.112731 Dram Type= 6, Freq= 0, CH_1, rank 0
5502 12:20:42.116481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5503 12:20:42.116561 ==
5504 12:20:42.116623 DQS Delay:
5505 12:20:42.119456 DQS0 = 0, DQS1 = 0
5506 12:20:42.119534 DQM Delay:
5507 12:20:42.122791 DQM0 = 94, DQM1 = 87
5508 12:20:42.122871 DQ Delay:
5509 12:20:42.126098 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5510 12:20:42.129468 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5511 12:20:42.132818 DQ8 =71, DQ9 =79, DQ10 =87, DQ11 =79
5512 12:20:42.136487 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =99
5513 12:20:42.136565
5514 12:20:42.136627
5515 12:20:42.136685 ==
5516 12:20:42.139445 Dram Type= 6, Freq= 0, CH_1, rank 0
5517 12:20:42.142716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5518 12:20:42.142800 ==
5519 12:20:42.142861
5520 12:20:42.142918
5521 12:20:42.146108 TX Vref Scan disable
5522 12:20:42.149182 == TX Byte 0 ==
5523 12:20:42.152514 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5524 12:20:42.156124 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5525 12:20:42.159263 == TX Byte 1 ==
5526 12:20:42.162672 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5527 12:20:42.165974 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5528 12:20:42.166052 ==
5529 12:20:42.169263 Dram Type= 6, Freq= 0, CH_1, rank 0
5530 12:20:42.175905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5531 12:20:42.175984 ==
5532 12:20:42.176046
5533 12:20:42.176102
5534 12:20:42.176157 TX Vref Scan disable
5535 12:20:42.179840 == TX Byte 0 ==
5536 12:20:42.183085 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5537 12:20:42.186595 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5538 12:20:42.189863 == TX Byte 1 ==
5539 12:20:42.193234 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5540 12:20:42.199650 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5541 12:20:42.199730
5542 12:20:42.199792 [DATLAT]
5543 12:20:42.199850 Freq=933, CH1 RK0
5544 12:20:42.199906
5545 12:20:42.203041 DATLAT Default: 0xd
5546 12:20:42.203120 0, 0xFFFF, sum = 0
5547 12:20:42.206303 1, 0xFFFF, sum = 0
5548 12:20:42.206384 2, 0xFFFF, sum = 0
5549 12:20:42.209766 3, 0xFFFF, sum = 0
5550 12:20:42.213225 4, 0xFFFF, sum = 0
5551 12:20:42.213308 5, 0xFFFF, sum = 0
5552 12:20:42.216145 6, 0xFFFF, sum = 0
5553 12:20:42.216242 7, 0xFFFF, sum = 0
5554 12:20:42.219553 8, 0xFFFF, sum = 0
5555 12:20:42.219636 9, 0xFFFF, sum = 0
5556 12:20:42.223149 10, 0x0, sum = 1
5557 12:20:42.223230 11, 0x0, sum = 2
5558 12:20:42.226302 12, 0x0, sum = 3
5559 12:20:42.226384 13, 0x0, sum = 4
5560 12:20:42.226449 best_step = 11
5561 12:20:42.226508
5562 12:20:42.229541 ==
5563 12:20:42.232935 Dram Type= 6, Freq= 0, CH_1, rank 0
5564 12:20:42.236191 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5565 12:20:42.236273 ==
5566 12:20:42.236337 RX Vref Scan: 1
5567 12:20:42.236398
5568 12:20:42.239490 RX Vref 0 -> 0, step: 1
5569 12:20:42.239571
5570 12:20:42.242698 RX Delay -69 -> 252, step: 4
5571 12:20:42.242779
5572 12:20:42.246084 Set Vref, RX VrefLevel [Byte0]: 59
5573 12:20:42.249644 [Byte1]: 48
5574 12:20:42.249725
5575 12:20:42.252503 Final RX Vref Byte 0 = 59 to rank0
5576 12:20:42.256053 Final RX Vref Byte 1 = 48 to rank0
5577 12:20:42.259187 Final RX Vref Byte 0 = 59 to rank1
5578 12:20:42.262484 Final RX Vref Byte 1 = 48 to rank1==
5579 12:20:42.265953 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 12:20:42.272457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5581 12:20:42.272538 ==
5582 12:20:42.272602 DQS Delay:
5583 12:20:42.272662 DQS0 = 0, DQS1 = 0
5584 12:20:42.275763 DQM Delay:
5585 12:20:42.275843 DQM0 = 94, DQM1 = 88
5586 12:20:42.279048 DQ Delay:
5587 12:20:42.282512 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5588 12:20:42.285691 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5589 12:20:42.289018 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5590 12:20:42.292209 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5591 12:20:42.292304
5592 12:20:42.292368
5593 12:20:42.299121 [DQSOSCAuto] RK0, (LSB)MR18= 0x3737, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5594 12:20:42.302495 CH1 RK0: MR19=505, MR18=3737
5595 12:20:42.308812 CH1_RK0: MR19=0x505, MR18=0x3737, DQSOSC=404, MR23=63, INC=66, DEC=44
5596 12:20:42.308894
5597 12:20:42.312154 ----->DramcWriteLeveling(PI) begin...
5598 12:20:42.312279 ==
5599 12:20:42.315374 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 12:20:42.318793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5601 12:20:42.318874 ==
5602 12:20:42.322280 Write leveling (Byte 0): 26 => 26
5603 12:20:42.325487 Write leveling (Byte 1): 24 => 24
5604 12:20:42.328663 DramcWriteLeveling(PI) end<-----
5605 12:20:42.328743
5606 12:20:42.328806 ==
5607 12:20:42.332127 Dram Type= 6, Freq= 0, CH_1, rank 1
5608 12:20:42.335399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5609 12:20:42.335480 ==
5610 12:20:42.338566 [Gating] SW mode calibration
5611 12:20:42.345203 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5612 12:20:42.352406 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5613 12:20:42.355119 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 12:20:42.361875 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 12:20:42.365182 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 12:20:42.368393 0 10 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5617 12:20:42.375276 0 10 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
5618 12:20:42.378279 0 10 20 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5619 12:20:42.381620 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 12:20:42.388469 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 12:20:42.391870 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 12:20:42.394939 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 12:20:42.401471 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 12:20:42.404851 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5625 12:20:42.408087 0 11 16 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5626 12:20:42.414900 0 11 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5627 12:20:42.418141 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 12:20:42.421587 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 12:20:42.424704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 12:20:42.431686 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 12:20:42.434764 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 12:20:42.438086 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 12:20:42.444796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 12:20:42.447904 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5635 12:20:42.451450 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:20:42.457867 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:20:42.461107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:20:42.464584 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:20:42.471561 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:20:42.474581 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:20:42.477839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:20:42.484467 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:20:42.487983 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 12:20:42.491347 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 12:20:42.497749 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:20:42.501290 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:20:42.504511 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 12:20:42.511113 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 12:20:42.514460 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5650 12:20:42.518054 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5651 12:20:42.521274 Total UI for P1: 0, mck2ui 16
5652 12:20:42.524395 best dqsien dly found for B0: ( 0, 14, 16)
5653 12:20:42.531068 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 12:20:42.531148 Total UI for P1: 0, mck2ui 16
5655 12:20:42.534299 best dqsien dly found for B1: ( 0, 14, 20)
5656 12:20:42.541319 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5657 12:20:42.544291 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5658 12:20:42.544370
5659 12:20:42.547680 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5660 12:20:42.550770 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5661 12:20:42.554242 [Gating] SW calibration Done
5662 12:20:42.554322 ==
5663 12:20:42.557609 Dram Type= 6, Freq= 0, CH_1, rank 1
5664 12:20:42.560670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5665 12:20:42.560752 ==
5666 12:20:42.563940 RX Vref Scan: 0
5667 12:20:42.564021
5668 12:20:42.564084 RX Vref 0 -> 0, step: 1
5669 12:20:42.564144
5670 12:20:42.567605 RX Delay -80 -> 252, step: 8
5671 12:20:42.570689 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5672 12:20:42.577345 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5673 12:20:42.580646 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5674 12:20:42.584063 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5675 12:20:42.587316 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5676 12:20:42.590589 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5677 12:20:42.594051 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5678 12:20:42.600518 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5679 12:20:42.603926 iDelay=208, Bit 8, Center 71 (-32 ~ 175) 208
5680 12:20:42.607240 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5681 12:20:42.610510 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5682 12:20:42.614034 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5683 12:20:42.620608 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5684 12:20:42.623880 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5685 12:20:42.627129 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5686 12:20:42.630424 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5687 12:20:42.630506 ==
5688 12:20:42.633746 Dram Type= 6, Freq= 0, CH_1, rank 1
5689 12:20:42.636991 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5690 12:20:42.640407 ==
5691 12:20:42.640487 DQS Delay:
5692 12:20:42.640550 DQS0 = 0, DQS1 = 0
5693 12:20:42.643649 DQM Delay:
5694 12:20:42.643730 DQM0 = 95, DQM1 = 86
5695 12:20:42.647079 DQ Delay:
5696 12:20:42.647160 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5697 12:20:42.650311 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5698 12:20:42.653755 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =75
5699 12:20:42.657052 DQ12 =99, DQ13 =95, DQ14 =91, DQ15 =95
5700 12:20:42.660335
5701 12:20:42.660416
5702 12:20:42.660480 ==
5703 12:20:42.663739 Dram Type= 6, Freq= 0, CH_1, rank 1
5704 12:20:42.666846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5705 12:20:42.666927 ==
5706 12:20:42.666991
5707 12:20:42.667049
5708 12:20:42.670341 TX Vref Scan disable
5709 12:20:42.670422 == TX Byte 0 ==
5710 12:20:42.676920 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5711 12:20:42.680209 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5712 12:20:42.680302 == TX Byte 1 ==
5713 12:20:42.687044 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5714 12:20:42.690103 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5715 12:20:42.690183 ==
5716 12:20:42.693604 Dram Type= 6, Freq= 0, CH_1, rank 1
5717 12:20:42.696823 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5718 12:20:42.696903 ==
5719 12:20:42.696965
5720 12:20:42.697022
5721 12:20:42.700146 TX Vref Scan disable
5722 12:20:42.703775 == TX Byte 0 ==
5723 12:20:42.707100 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 12:20:42.710409 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 12:20:42.713338 == TX Byte 1 ==
5726 12:20:42.717073 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5727 12:20:42.719999 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5728 12:20:42.720107
5729 12:20:42.723484 [DATLAT]
5730 12:20:42.723563 Freq=933, CH1 RK1
5731 12:20:42.723627
5732 12:20:42.726724 DATLAT Default: 0xb
5733 12:20:42.726803 0, 0xFFFF, sum = 0
5734 12:20:42.730335 1, 0xFFFF, sum = 0
5735 12:20:42.730416 2, 0xFFFF, sum = 0
5736 12:20:42.733531 3, 0xFFFF, sum = 0
5737 12:20:42.733611 4, 0xFFFF, sum = 0
5738 12:20:42.736725 5, 0xFFFF, sum = 0
5739 12:20:42.736806 6, 0xFFFF, sum = 0
5740 12:20:42.740059 7, 0xFFFF, sum = 0
5741 12:20:42.740140 8, 0xFFFF, sum = 0
5742 12:20:42.743426 9, 0xFFFF, sum = 0
5743 12:20:42.743506 10, 0x0, sum = 1
5744 12:20:42.746619 11, 0x0, sum = 2
5745 12:20:42.746700 12, 0x0, sum = 3
5746 12:20:42.749962 13, 0x0, sum = 4
5747 12:20:42.750043 best_step = 11
5748 12:20:42.750106
5749 12:20:42.750164 ==
5750 12:20:42.753293 Dram Type= 6, Freq= 0, CH_1, rank 1
5751 12:20:42.760031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5752 12:20:42.760112 ==
5753 12:20:42.760182 RX Vref Scan: 0
5754 12:20:42.760243
5755 12:20:42.763262 RX Vref 0 -> 0, step: 1
5756 12:20:42.763342
5757 12:20:42.766493 RX Delay -77 -> 252, step: 4
5758 12:20:42.769937 iDelay=203, Bit 0, Center 96 (3 ~ 190) 188
5759 12:20:42.773331 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5760 12:20:42.779713 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5761 12:20:42.783103 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5762 12:20:42.786333 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5763 12:20:42.790003 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5764 12:20:42.793051 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5765 12:20:42.796475 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5766 12:20:42.803032 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5767 12:20:42.806335 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5768 12:20:42.809774 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5769 12:20:42.813137 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5770 12:20:42.816583 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5771 12:20:42.822912 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5772 12:20:42.826095 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5773 12:20:42.829419 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5774 12:20:42.829500 ==
5775 12:20:42.832887 Dram Type= 6, Freq= 0, CH_1, rank 1
5776 12:20:42.836135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5777 12:20:42.836254 ==
5778 12:20:42.839505 DQS Delay:
5779 12:20:42.839584 DQS0 = 0, DQS1 = 0
5780 12:20:42.843012 DQM Delay:
5781 12:20:42.843091 DQM0 = 95, DQM1 = 87
5782 12:20:42.843153 DQ Delay:
5783 12:20:42.846360 DQ0 =96, DQ1 =92, DQ2 =86, DQ3 =92
5784 12:20:42.849612 DQ4 =94, DQ5 =106, DQ6 =104, DQ7 =94
5785 12:20:42.853150 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =80
5786 12:20:42.856406 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5787 12:20:42.856486
5788 12:20:42.856548
5789 12:20:42.866270 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5790 12:20:42.869692 CH1 RK1: MR19=505, MR18=2424
5791 12:20:42.872858 CH1_RK1: MR19=0x505, MR18=0x2424, DQSOSC=410, MR23=63, INC=64, DEC=42
5792 12:20:42.876331 [RxdqsGatingPostProcess] freq 933
5793 12:20:42.883055 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5794 12:20:42.886093 Pre-setting of DQS Precalculation
5795 12:20:42.889308 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5796 12:20:42.899340 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5797 12:20:42.906358 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5798 12:20:42.906439
5799 12:20:42.906501
5800 12:20:42.909297 [Calibration Summary] 1866 Mbps
5801 12:20:42.909376 CH 0, Rank 0
5802 12:20:42.912620 SW Impedance : PASS
5803 12:20:42.912699 DUTY Scan : NO K
5804 12:20:42.915819 ZQ Calibration : PASS
5805 12:20:42.919131 Jitter Meter : NO K
5806 12:20:42.919211 CBT Training : PASS
5807 12:20:42.922442 Write leveling : PASS
5808 12:20:42.926055 RX DQS gating : PASS
5809 12:20:42.926135 RX DQ/DQS(RDDQC) : PASS
5810 12:20:42.929026 TX DQ/DQS : PASS
5811 12:20:42.932604 RX DATLAT : PASS
5812 12:20:42.932683 RX DQ/DQS(Engine): PASS
5813 12:20:42.935839 TX OE : NO K
5814 12:20:42.935919 All Pass.
5815 12:20:42.935982
5816 12:20:42.939314 CH 0, Rank 1
5817 12:20:42.939393 SW Impedance : PASS
5818 12:20:42.942503 DUTY Scan : NO K
5819 12:20:42.945623 ZQ Calibration : PASS
5820 12:20:42.945702 Jitter Meter : NO K
5821 12:20:42.949037 CBT Training : PASS
5822 12:20:42.952287 Write leveling : PASS
5823 12:20:42.952366 RX DQS gating : PASS
5824 12:20:42.955819 RX DQ/DQS(RDDQC) : PASS
5825 12:20:42.955898 TX DQ/DQS : PASS
5826 12:20:42.959028 RX DATLAT : PASS
5827 12:20:42.962320 RX DQ/DQS(Engine): PASS
5828 12:20:42.962399 TX OE : NO K
5829 12:20:42.965441 All Pass.
5830 12:20:42.965520
5831 12:20:42.965582 CH 1, Rank 0
5832 12:20:42.968854 SW Impedance : PASS
5833 12:20:42.968932 DUTY Scan : NO K
5834 12:20:42.972293 ZQ Calibration : PASS
5835 12:20:42.975333 Jitter Meter : NO K
5836 12:20:42.975412 CBT Training : PASS
5837 12:20:42.978867 Write leveling : PASS
5838 12:20:42.981969 RX DQS gating : PASS
5839 12:20:42.982048 RX DQ/DQS(RDDQC) : PASS
5840 12:20:42.985295 TX DQ/DQS : PASS
5841 12:20:42.988472 RX DATLAT : PASS
5842 12:20:42.988551 RX DQ/DQS(Engine): PASS
5843 12:20:42.991883 TX OE : NO K
5844 12:20:42.991962 All Pass.
5845 12:20:42.992024
5846 12:20:42.995230 CH 1, Rank 1
5847 12:20:42.995309 SW Impedance : PASS
5848 12:20:42.998483 DUTY Scan : NO K
5849 12:20:43.001775 ZQ Calibration : PASS
5850 12:20:43.001854 Jitter Meter : NO K
5851 12:20:43.005194 CBT Training : PASS
5852 12:20:43.008386 Write leveling : PASS
5853 12:20:43.008466 RX DQS gating : PASS
5854 12:20:43.011755 RX DQ/DQS(RDDQC) : PASS
5855 12:20:43.015144 TX DQ/DQS : PASS
5856 12:20:43.015224 RX DATLAT : PASS
5857 12:20:43.018427 RX DQ/DQS(Engine): PASS
5858 12:20:43.018506 TX OE : NO K
5859 12:20:43.021710 All Pass.
5860 12:20:43.021789
5861 12:20:43.021852 DramC Write-DBI off
5862 12:20:43.025117 PER_BANK_REFRESH: Hybrid Mode
5863 12:20:43.028294 TX_TRACKING: ON
5864 12:20:43.035486 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5865 12:20:43.038315 [FAST_K] Save calibration result to emmc
5866 12:20:43.044968 dramc_set_vcore_voltage set vcore to 650000
5867 12:20:43.045047 Read voltage for 400, 6
5868 12:20:43.048109 Vio18 = 0
5869 12:20:43.048230 Vcore = 650000
5870 12:20:43.048294 Vdram = 0
5871 12:20:43.048358 Vddq = 0
5872 12:20:43.051783 Vmddr = 0
5873 12:20:43.054983 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5874 12:20:43.061352 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5875 12:20:43.064746 MEM_TYPE=3, freq_sel=20
5876 12:20:43.064825 sv_algorithm_assistance_LP4_800
5877 12:20:43.071256 ============ PULL DRAM RESETB DOWN ============
5878 12:20:43.074523 ========== PULL DRAM RESETB DOWN end =========
5879 12:20:43.078042 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5880 12:20:43.081316 ===================================
5881 12:20:43.084533 LPDDR4 DRAM CONFIGURATION
5882 12:20:43.087958 ===================================
5883 12:20:43.091201 EX_ROW_EN[0] = 0x0
5884 12:20:43.091281 EX_ROW_EN[1] = 0x0
5885 12:20:43.094699 LP4Y_EN = 0x0
5886 12:20:43.094778 WORK_FSP = 0x0
5887 12:20:43.097885 WL = 0x2
5888 12:20:43.097964 RL = 0x2
5889 12:20:43.101274 BL = 0x2
5890 12:20:43.101353 RPST = 0x0
5891 12:20:43.104435 RD_PRE = 0x0
5892 12:20:43.104513 WR_PRE = 0x1
5893 12:20:43.107946 WR_PST = 0x0
5894 12:20:43.108025 DBI_WR = 0x0
5895 12:20:43.110899 DBI_RD = 0x0
5896 12:20:43.114188 OTF = 0x1
5897 12:20:43.117504 ===================================
5898 12:20:43.121146 ===================================
5899 12:20:43.121225 ANA top config
5900 12:20:43.124150 ===================================
5901 12:20:43.127530 DLL_ASYNC_EN = 0
5902 12:20:43.127609 ALL_SLAVE_EN = 1
5903 12:20:43.131016 NEW_RANK_MODE = 1
5904 12:20:43.134141 DLL_IDLE_MODE = 1
5905 12:20:43.137560 LP45_APHY_COMB_EN = 1
5906 12:20:43.140613 TX_ODT_DIS = 1
5907 12:20:43.140693 NEW_8X_MODE = 1
5908 12:20:43.144031 ===================================
5909 12:20:43.147186 ===================================
5910 12:20:43.150568 data_rate = 800
5911 12:20:43.153925 CKR = 1
5912 12:20:43.157224 DQ_P2S_RATIO = 4
5913 12:20:43.160669 ===================================
5914 12:20:43.163755 CA_P2S_RATIO = 4
5915 12:20:43.167184 DQ_CA_OPEN = 0
5916 12:20:43.167263 DQ_SEMI_OPEN = 1
5917 12:20:43.170464 CA_SEMI_OPEN = 1
5918 12:20:43.173709 CA_FULL_RATE = 0
5919 12:20:43.177024 DQ_CKDIV4_EN = 0
5920 12:20:43.180454 CA_CKDIV4_EN = 1
5921 12:20:43.183805 CA_PREDIV_EN = 0
5922 12:20:43.183884 PH8_DLY = 0
5923 12:20:43.187026 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5924 12:20:43.190530 DQ_AAMCK_DIV = 0
5925 12:20:43.193763 CA_AAMCK_DIV = 0
5926 12:20:43.197091 CA_ADMCK_DIV = 4
5927 12:20:43.200393 DQ_TRACK_CA_EN = 0
5928 12:20:43.200472 CA_PICK = 800
5929 12:20:43.203525 CA_MCKIO = 400
5930 12:20:43.206823 MCKIO_SEMI = 400
5931 12:20:43.210020 PLL_FREQ = 3016
5932 12:20:43.213478 DQ_UI_PI_RATIO = 32
5933 12:20:43.216830 CA_UI_PI_RATIO = 32
5934 12:20:43.220092 ===================================
5935 12:20:43.223385 ===================================
5936 12:20:43.226591 memory_type:LPDDR4
5937 12:20:43.226670 GP_NUM : 10
5938 12:20:43.230173 SRAM_EN : 1
5939 12:20:43.230254 MD32_EN : 0
5940 12:20:43.233475 ===================================
5941 12:20:43.236706 [ANA_INIT] >>>>>>>>>>>>>>
5942 12:20:43.240059 <<<<<< [CONFIGURE PHASE]: ANA_TX
5943 12:20:43.243307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5944 12:20:43.246803 ===================================
5945 12:20:43.249915 data_rate = 800,PCW = 0X7400
5946 12:20:43.253128 ===================================
5947 12:20:43.256660 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5948 12:20:43.263254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5949 12:20:43.273046 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5950 12:20:43.276374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5951 12:20:43.279568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5952 12:20:43.286213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5953 12:20:43.286294 [ANA_INIT] flow start
5954 12:20:43.289481 [ANA_INIT] PLL >>>>>>>>
5955 12:20:43.292692 [ANA_INIT] PLL <<<<<<<<
5956 12:20:43.292772 [ANA_INIT] MIDPI >>>>>>>>
5957 12:20:43.296026 [ANA_INIT] MIDPI <<<<<<<<
5958 12:20:43.299317 [ANA_INIT] DLL >>>>>>>>
5959 12:20:43.299398 [ANA_INIT] flow end
5960 12:20:43.302965 ============ LP4 DIFF to SE enter ============
5961 12:20:43.309040 ============ LP4 DIFF to SE exit ============
5962 12:20:43.309135 [ANA_INIT] <<<<<<<<<<<<<
5963 12:20:43.312511 [Flow] Enable top DCM control >>>>>
5964 12:20:43.315735 [Flow] Enable top DCM control <<<<<
5965 12:20:43.319257 Enable DLL master slave shuffle
5966 12:20:43.325807 ==============================================================
5967 12:20:43.329187 Gating Mode config
5968 12:20:43.332432 ==============================================================
5969 12:20:43.336036 Config description:
5970 12:20:43.345468 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5971 12:20:43.352086 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5972 12:20:43.355588 SELPH_MODE 0: By rank 1: By Phase
5973 12:20:43.362172 ==============================================================
5974 12:20:43.365462 GAT_TRACK_EN = 0
5975 12:20:43.368790 RX_GATING_MODE = 2
5976 12:20:43.372113 RX_GATING_TRACK_MODE = 2
5977 12:20:43.372199 SELPH_MODE = 1
5978 12:20:43.375664 PICG_EARLY_EN = 1
5979 12:20:43.378756 VALID_LAT_VALUE = 1
5980 12:20:43.385240 ==============================================================
5981 12:20:43.388647 Enter into Gating configuration >>>>
5982 12:20:43.391789 Exit from Gating configuration <<<<
5983 12:20:43.395082 Enter into DVFS_PRE_config >>>>>
5984 12:20:43.404861 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5985 12:20:43.408442 Exit from DVFS_PRE_config <<<<<
5986 12:20:43.411823 Enter into PICG configuration >>>>
5987 12:20:43.414872 Exit from PICG configuration <<<<
5988 12:20:43.418435 [RX_INPUT] configuration >>>>>
5989 12:20:43.421641 [RX_INPUT] configuration <<<<<
5990 12:20:43.425205 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5991 12:20:43.431275 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5992 12:20:43.438085 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5993 12:20:43.444750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5994 12:20:43.451279 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5995 12:20:43.454736 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5996 12:20:43.461351 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5997 12:20:43.464648 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5998 12:20:43.467912 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5999 12:20:43.471304 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6000 12:20:43.477659 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6001 12:20:43.481010 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6002 12:20:43.484286 ===================================
6003 12:20:43.487755 LPDDR4 DRAM CONFIGURATION
6004 12:20:43.491089 ===================================
6005 12:20:43.491169 EX_ROW_EN[0] = 0x0
6006 12:20:43.494287 EX_ROW_EN[1] = 0x0
6007 12:20:43.494367 LP4Y_EN = 0x0
6008 12:20:43.497642 WORK_FSP = 0x0
6009 12:20:43.497721 WL = 0x2
6010 12:20:43.501150 RL = 0x2
6011 12:20:43.504183 BL = 0x2
6012 12:20:43.504295 RPST = 0x0
6013 12:20:43.507693 RD_PRE = 0x0
6014 12:20:43.507773 WR_PRE = 0x1
6015 12:20:43.510793 WR_PST = 0x0
6016 12:20:43.510873 DBI_WR = 0x0
6017 12:20:43.514218 DBI_RD = 0x0
6018 12:20:43.514298 OTF = 0x1
6019 12:20:43.517588 ===================================
6020 12:20:43.521275 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6021 12:20:43.527586 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6022 12:20:43.531027 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6023 12:20:43.534012 ===================================
6024 12:20:43.537219 LPDDR4 DRAM CONFIGURATION
6025 12:20:43.540444 ===================================
6026 12:20:43.540524 EX_ROW_EN[0] = 0x10
6027 12:20:43.543942 EX_ROW_EN[1] = 0x0
6028 12:20:43.544022 LP4Y_EN = 0x0
6029 12:20:43.547066 WORK_FSP = 0x0
6030 12:20:43.547145 WL = 0x2
6031 12:20:43.550336 RL = 0x2
6032 12:20:43.553695 BL = 0x2
6033 12:20:43.553775 RPST = 0x0
6034 12:20:43.557183 RD_PRE = 0x0
6035 12:20:43.557264 WR_PRE = 0x1
6036 12:20:43.560519 WR_PST = 0x0
6037 12:20:43.560598 DBI_WR = 0x0
6038 12:20:43.563739 DBI_RD = 0x0
6039 12:20:43.563818 OTF = 0x1
6040 12:20:43.567105 ===================================
6041 12:20:43.573798 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6042 12:20:43.577550 nWR fixed to 30
6043 12:20:43.580939 [ModeRegInit_LP4] CH0 RK0
6044 12:20:43.581019 [ModeRegInit_LP4] CH0 RK1
6045 12:20:43.583976 [ModeRegInit_LP4] CH1 RK0
6046 12:20:43.587476 [ModeRegInit_LP4] CH1 RK1
6047 12:20:43.587556 match AC timing 18
6048 12:20:43.594179 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6049 12:20:43.597480 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6050 12:20:43.600684 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6051 12:20:43.607426 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6052 12:20:43.610720 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6053 12:20:43.610800 ==
6054 12:20:43.613988 Dram Type= 6, Freq= 0, CH_0, rank 0
6055 12:20:43.617182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6056 12:20:43.617263 ==
6057 12:20:43.624157 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6058 12:20:43.630676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6059 12:20:43.633886 [CA 0] Center 36 (8~64) winsize 57
6060 12:20:43.637208 [CA 1] Center 36 (8~64) winsize 57
6061 12:20:43.640800 [CA 2] Center 36 (8~64) winsize 57
6062 12:20:43.644023 [CA 3] Center 36 (8~64) winsize 57
6063 12:20:43.644103 [CA 4] Center 36 (8~64) winsize 57
6064 12:20:43.647001 [CA 5] Center 36 (8~64) winsize 57
6065 12:20:43.647081
6066 12:20:43.653837 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6067 12:20:43.653918
6068 12:20:43.657290 [CATrainingPosCal] consider 1 rank data
6069 12:20:43.660378 u2DelayCellTimex100 = 270/100 ps
6070 12:20:43.663601 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6071 12:20:43.666987 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6072 12:20:43.670388 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6073 12:20:43.673898 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6074 12:20:43.676958 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6075 12:20:43.680123 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6076 12:20:43.680244
6077 12:20:43.683393 CA PerBit enable=1, Macro0, CA PI delay=36
6078 12:20:43.683483
6079 12:20:43.686952 [CBTSetCACLKResult] CA Dly = 36
6080 12:20:43.690288 CS Dly: 1 (0~32)
6081 12:20:43.690376 ==
6082 12:20:43.693556 Dram Type= 6, Freq= 0, CH_0, rank 1
6083 12:20:43.696940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6084 12:20:43.697027 ==
6085 12:20:43.703347 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6086 12:20:43.710161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6087 12:20:43.710246 [CA 0] Center 36 (8~64) winsize 57
6088 12:20:43.713676 [CA 1] Center 36 (8~64) winsize 57
6089 12:20:43.716996 [CA 2] Center 36 (8~64) winsize 57
6090 12:20:43.720153 [CA 3] Center 36 (8~64) winsize 57
6091 12:20:43.723403 [CA 4] Center 36 (8~64) winsize 57
6092 12:20:43.726716 [CA 5] Center 36 (8~64) winsize 57
6093 12:20:43.726798
6094 12:20:43.730319 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6095 12:20:43.730400
6096 12:20:43.733518 [CATrainingPosCal] consider 2 rank data
6097 12:20:43.737519 u2DelayCellTimex100 = 270/100 ps
6098 12:20:43.740369 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6099 12:20:43.743282 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6100 12:20:43.750455 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6101 12:20:43.753227 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6102 12:20:43.756615 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6103 12:20:43.760298 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6104 12:20:43.760380
6105 12:20:43.763398 CA PerBit enable=1, Macro0, CA PI delay=36
6106 12:20:43.763478
6107 12:20:43.766688 [CBTSetCACLKResult] CA Dly = 36
6108 12:20:43.766769 CS Dly: 1 (0~32)
6109 12:20:43.766832
6110 12:20:43.770152 ----->DramcWriteLeveling(PI) begin...
6111 12:20:43.773319 ==
6112 12:20:43.773400 Dram Type= 6, Freq= 0, CH_0, rank 0
6113 12:20:43.780201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6114 12:20:43.780339 ==
6115 12:20:43.783281 Write leveling (Byte 0): 32 => 0
6116 12:20:43.786837 Write leveling (Byte 1): 32 => 0
6117 12:20:43.786918 DramcWriteLeveling(PI) end<-----
6118 12:20:43.790156
6119 12:20:43.790264 ==
6120 12:20:43.793315 Dram Type= 6, Freq= 0, CH_0, rank 0
6121 12:20:43.796520 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6122 12:20:43.796627 ==
6123 12:20:43.799885 [Gating] SW mode calibration
6124 12:20:43.806449 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6125 12:20:43.809904 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6126 12:20:43.816528 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6127 12:20:43.819830 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6128 12:20:43.823064 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6129 12:20:43.829641 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6130 12:20:43.833050 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6131 12:20:43.836291 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6132 12:20:43.842981 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6133 12:20:43.846534 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6134 12:20:43.849628 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6135 12:20:43.853263 Total UI for P1: 0, mck2ui 16
6136 12:20:43.856468 best dqsien dly found for B0: ( 0, 10, 16)
6137 12:20:43.859661 Total UI for P1: 0, mck2ui 16
6138 12:20:43.863015 best dqsien dly found for B1: ( 0, 10, 16)
6139 12:20:43.866470 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6140 12:20:43.869810 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6141 12:20:43.869893
6142 12:20:43.876239 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6143 12:20:43.879587 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6144 12:20:43.883003 [Gating] SW calibration Done
6145 12:20:43.883086 ==
6146 12:20:43.886067 Dram Type= 6, Freq= 0, CH_0, rank 0
6147 12:20:43.889496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6148 12:20:43.889578 ==
6149 12:20:43.889642 RX Vref Scan: 0
6150 12:20:43.889702
6151 12:20:43.892973 RX Vref 0 -> 0, step: 1
6152 12:20:43.893054
6153 12:20:43.896282 RX Delay -410 -> 252, step: 16
6154 12:20:43.899443 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6155 12:20:43.906422 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6156 12:20:43.910065 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6157 12:20:43.912802 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6158 12:20:43.916110 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6159 12:20:43.922681 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6160 12:20:43.926204 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6161 12:20:43.929564 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6162 12:20:43.932852 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6163 12:20:43.939367 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6164 12:20:43.942548 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6165 12:20:43.945851 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6166 12:20:43.949359 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6167 12:20:43.956061 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6168 12:20:43.959166 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6169 12:20:43.962365 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6170 12:20:43.962462 ==
6171 12:20:43.965852 Dram Type= 6, Freq= 0, CH_0, rank 0
6172 12:20:43.972405 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6173 12:20:43.972491 ==
6174 12:20:43.972555 DQS Delay:
6175 12:20:43.975707 DQS0 = 43, DQS1 = 59
6176 12:20:43.975790 DQM Delay:
6177 12:20:43.975854 DQM0 = 5, DQM1 = 16
6178 12:20:43.978994 DQ Delay:
6179 12:20:43.979075 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6180 12:20:43.982427 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6181 12:20:43.985582 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6182 12:20:43.988923 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6183 12:20:43.989062
6184 12:20:43.989137
6185 12:20:43.992165 ==
6186 12:20:43.992302 Dram Type= 6, Freq= 0, CH_0, rank 0
6187 12:20:43.999162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6188 12:20:43.999251 ==
6189 12:20:43.999339
6190 12:20:43.999411
6191 12:20:43.999467 TX Vref Scan disable
6192 12:20:44.002429 == TX Byte 0 ==
6193 12:20:44.005939 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6194 12:20:44.009385 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6195 12:20:44.012686 == TX Byte 1 ==
6196 12:20:44.015757 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6197 12:20:44.019142 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6198 12:20:44.022396 ==
6199 12:20:44.026430 Dram Type= 6, Freq= 0, CH_0, rank 0
6200 12:20:44.029400 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6201 12:20:44.029485 ==
6202 12:20:44.029550
6203 12:20:44.029609
6204 12:20:44.032404 TX Vref Scan disable
6205 12:20:44.032486 == TX Byte 0 ==
6206 12:20:44.035553 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6207 12:20:44.042385 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6208 12:20:44.042471 == TX Byte 1 ==
6209 12:20:44.045947 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6210 12:20:44.052389 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6211 12:20:44.052476
6212 12:20:44.052540 [DATLAT]
6213 12:20:44.052600 Freq=400, CH0 RK0
6214 12:20:44.055664
6215 12:20:44.055745 DATLAT Default: 0xf
6216 12:20:44.059214 0, 0xFFFF, sum = 0
6217 12:20:44.059296 1, 0xFFFF, sum = 0
6218 12:20:44.062267 2, 0xFFFF, sum = 0
6219 12:20:44.062355 3, 0xFFFF, sum = 0
6220 12:20:44.065470 4, 0xFFFF, sum = 0
6221 12:20:44.065554 5, 0xFFFF, sum = 0
6222 12:20:44.068986 6, 0xFFFF, sum = 0
6223 12:20:44.069070 7, 0xFFFF, sum = 0
6224 12:20:44.072324 8, 0xFFFF, sum = 0
6225 12:20:44.072407 9, 0xFFFF, sum = 0
6226 12:20:44.075336 10, 0xFFFF, sum = 0
6227 12:20:44.075421 11, 0xFFFF, sum = 0
6228 12:20:44.078587 12, 0x0, sum = 1
6229 12:20:44.078669 13, 0x0, sum = 2
6230 12:20:44.081983 14, 0x0, sum = 3
6231 12:20:44.082066 15, 0x0, sum = 4
6232 12:20:44.085337 best_step = 13
6233 12:20:44.085420
6234 12:20:44.085484 ==
6235 12:20:44.088650 Dram Type= 6, Freq= 0, CH_0, rank 0
6236 12:20:44.092013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6237 12:20:44.092096 ==
6238 12:20:44.095416 RX Vref Scan: 1
6239 12:20:44.095499
6240 12:20:44.095562 RX Vref 0 -> 0, step: 1
6241 12:20:44.095621
6242 12:20:44.098420 RX Delay -359 -> 252, step: 8
6243 12:20:44.098501
6244 12:20:44.101858 Set Vref, RX VrefLevel [Byte0]: 50
6245 12:20:44.105070 [Byte1]: 46
6246 12:20:44.109995
6247 12:20:44.110087 Final RX Vref Byte 0 = 50 to rank0
6248 12:20:44.113259 Final RX Vref Byte 1 = 46 to rank0
6249 12:20:44.116377 Final RX Vref Byte 0 = 50 to rank1
6250 12:20:44.119897 Final RX Vref Byte 1 = 46 to rank1==
6251 12:20:44.123097 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 12:20:44.129640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6253 12:20:44.129738 ==
6254 12:20:44.129803 DQS Delay:
6255 12:20:44.132961 DQS0 = 52, DQS1 = 68
6256 12:20:44.133043 DQM Delay:
6257 12:20:44.133107 DQM0 = 9, DQM1 = 17
6258 12:20:44.136289 DQ Delay:
6259 12:20:44.136376 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6260 12:20:44.139642 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6261 12:20:44.143186 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6262 12:20:44.146398 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6263 12:20:44.146481
6264 12:20:44.146545
6265 12:20:44.156458 [DQSOSCAuto] RK0, (LSB)MR18= 0xa3a3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6266 12:20:44.159633 CH0 RK0: MR19=C0C, MR18=A3A3
6267 12:20:44.166258 CH0_RK0: MR19=0xC0C, MR18=0xA3A3, DQSOSC=389, MR23=63, INC=390, DEC=260
6268 12:20:44.166347 ==
6269 12:20:44.169504 Dram Type= 6, Freq= 0, CH_0, rank 1
6270 12:20:44.173261 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6271 12:20:44.173346 ==
6272 12:20:44.176752 [Gating] SW mode calibration
6273 12:20:44.182697 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 12:20:44.185980 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6275 12:20:44.192693 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 12:20:44.196187 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 12:20:44.199494 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 12:20:44.206341 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6279 12:20:44.209378 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 12:20:44.212737 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 12:20:44.219401 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 12:20:44.222734 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6283 12:20:44.226115 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 12:20:44.229466 Total UI for P1: 0, mck2ui 16
6285 12:20:44.232690 best dqsien dly found for B0: ( 0, 10, 16)
6286 12:20:44.235851 Total UI for P1: 0, mck2ui 16
6287 12:20:44.239394 best dqsien dly found for B1: ( 0, 10, 16)
6288 12:20:44.242410 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6289 12:20:44.245893 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6290 12:20:44.249299
6291 12:20:44.252482 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6292 12:20:44.256014 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6293 12:20:44.259353 [Gating] SW calibration Done
6294 12:20:44.259438 ==
6295 12:20:44.262837 Dram Type= 6, Freq= 0, CH_0, rank 1
6296 12:20:44.265662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6297 12:20:44.265745 ==
6298 12:20:44.265809 RX Vref Scan: 0
6299 12:20:44.269112
6300 12:20:44.269194 RX Vref 0 -> 0, step: 1
6301 12:20:44.269259
6302 12:20:44.272149 RX Delay -410 -> 252, step: 16
6303 12:20:44.275723 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6304 12:20:44.282443 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6305 12:20:44.285508 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6306 12:20:44.288862 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6307 12:20:44.292112 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6308 12:20:44.298667 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6309 12:20:44.302325 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6310 12:20:44.305249 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6311 12:20:44.308761 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6312 12:20:44.315304 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6313 12:20:44.318575 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6314 12:20:44.322172 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6315 12:20:44.325233 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6316 12:20:44.332020 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6317 12:20:44.335287 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6318 12:20:44.338663 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6319 12:20:44.338757 ==
6320 12:20:44.341765 Dram Type= 6, Freq= 0, CH_0, rank 1
6321 12:20:44.348618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6322 12:20:44.348713 ==
6323 12:20:44.348782 DQS Delay:
6324 12:20:44.352025 DQS0 = 43, DQS1 = 59
6325 12:20:44.352134 DQM Delay:
6326 12:20:44.352239 DQM0 = 7, DQM1 = 15
6327 12:20:44.355213 DQ Delay:
6328 12:20:44.358359 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6329 12:20:44.358443 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6330 12:20:44.361752 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6331 12:20:44.365028 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6332 12:20:44.365111
6333 12:20:44.368456
6334 12:20:44.368540 ==
6335 12:20:44.371777 Dram Type= 6, Freq= 0, CH_0, rank 1
6336 12:20:44.374824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6337 12:20:44.374972 ==
6338 12:20:44.375049
6339 12:20:44.375111
6340 12:20:44.378341 TX Vref Scan disable
6341 12:20:44.378424 == TX Byte 0 ==
6342 12:20:44.381814 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6343 12:20:44.388323 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6344 12:20:44.388413 == TX Byte 1 ==
6345 12:20:44.391533 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6346 12:20:44.398550 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6347 12:20:44.398642 ==
6348 12:20:44.402051 Dram Type= 6, Freq= 0, CH_0, rank 1
6349 12:20:44.405003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6350 12:20:44.405087 ==
6351 12:20:44.405153
6352 12:20:44.405219
6353 12:20:44.408354 TX Vref Scan disable
6354 12:20:44.408438 == TX Byte 0 ==
6355 12:20:44.411506 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6356 12:20:44.418291 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6357 12:20:44.418386 == TX Byte 1 ==
6358 12:20:44.421601 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6359 12:20:44.428115 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6360 12:20:44.428286
6361 12:20:44.428354 [DATLAT]
6362 12:20:44.428415 Freq=400, CH0 RK1
6363 12:20:44.428474
6364 12:20:44.431447 DATLAT Default: 0xd
6365 12:20:44.434982 0, 0xFFFF, sum = 0
6366 12:20:44.435069 1, 0xFFFF, sum = 0
6367 12:20:44.438065 2, 0xFFFF, sum = 0
6368 12:20:44.438149 3, 0xFFFF, sum = 0
6369 12:20:44.441257 4, 0xFFFF, sum = 0
6370 12:20:44.441341 5, 0xFFFF, sum = 0
6371 12:20:44.444669 6, 0xFFFF, sum = 0
6372 12:20:44.444752 7, 0xFFFF, sum = 0
6373 12:20:44.448106 8, 0xFFFF, sum = 0
6374 12:20:44.448239 9, 0xFFFF, sum = 0
6375 12:20:44.451456 10, 0xFFFF, sum = 0
6376 12:20:44.451540 11, 0xFFFF, sum = 0
6377 12:20:44.454690 12, 0x0, sum = 1
6378 12:20:44.454780 13, 0x0, sum = 2
6379 12:20:44.457957 14, 0x0, sum = 3
6380 12:20:44.458041 15, 0x0, sum = 4
6381 12:20:44.461103 best_step = 13
6382 12:20:44.461185
6383 12:20:44.461249 ==
6384 12:20:44.464386 Dram Type= 6, Freq= 0, CH_0, rank 1
6385 12:20:44.467772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6386 12:20:44.467854 ==
6387 12:20:44.471212 RX Vref Scan: 0
6388 12:20:44.471294
6389 12:20:44.471358 RX Vref 0 -> 0, step: 1
6390 12:20:44.471417
6391 12:20:44.474288 RX Delay -359 -> 252, step: 8
6392 12:20:44.482255 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6393 12:20:44.485602 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6394 12:20:44.488938 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6395 12:20:44.491956 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6396 12:20:44.498523 iDelay=217, Bit 4, Center -36 (-287 ~ 216) 504
6397 12:20:44.501921 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6398 12:20:44.505206 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6399 12:20:44.508809 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6400 12:20:44.515150 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6401 12:20:44.518764 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6402 12:20:44.521824 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6403 12:20:44.528555 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6404 12:20:44.531912 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6405 12:20:44.535070 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6406 12:20:44.538508 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6407 12:20:44.545242 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6408 12:20:44.545350 ==
6409 12:20:44.548417 Dram Type= 6, Freq= 0, CH_0, rank 1
6410 12:20:44.551553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6411 12:20:44.551640 ==
6412 12:20:44.551703 DQS Delay:
6413 12:20:44.554931 DQS0 = 52, DQS1 = 64
6414 12:20:44.555016 DQM Delay:
6415 12:20:44.558184 DQM0 = 10, DQM1 = 13
6416 12:20:44.558268 DQ Delay:
6417 12:20:44.561861 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6418 12:20:44.564736 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =20
6419 12:20:44.568135 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6420 12:20:44.571420 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6421 12:20:44.571505
6422 12:20:44.571569
6423 12:20:44.578317 [DQSOSCAuto] RK1, (LSB)MR18= 0xc2c2, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6424 12:20:44.581313 CH0 RK1: MR19=C0C, MR18=C2C2
6425 12:20:44.587931 CH0_RK1: MR19=0xC0C, MR18=0xC2C2, DQSOSC=385, MR23=63, INC=398, DEC=265
6426 12:20:44.591272 [RxdqsGatingPostProcess] freq 400
6427 12:20:44.597911 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6428 12:20:44.601156 Pre-setting of DQS Precalculation
6429 12:20:44.604573 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6430 12:20:44.604661 ==
6431 12:20:44.607863 Dram Type= 6, Freq= 0, CH_1, rank 0
6432 12:20:44.611167 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6433 12:20:44.611253 ==
6434 12:20:44.617759 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6435 12:20:44.624406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6436 12:20:44.627668 [CA 0] Center 36 (8~64) winsize 57
6437 12:20:44.630894 [CA 1] Center 36 (8~64) winsize 57
6438 12:20:44.634229 [CA 2] Center 36 (8~64) winsize 57
6439 12:20:44.637674 [CA 3] Center 36 (8~64) winsize 57
6440 12:20:44.641098 [CA 4] Center 36 (8~64) winsize 57
6441 12:20:44.641185 [CA 5] Center 36 (8~64) winsize 57
6442 12:20:44.644408
6443 12:20:44.647769 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6444 12:20:44.647856
6445 12:20:44.650900 [CATrainingPosCal] consider 1 rank data
6446 12:20:44.654267 u2DelayCellTimex100 = 270/100 ps
6447 12:20:44.657562 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6448 12:20:44.660912 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6449 12:20:44.664388 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6450 12:20:44.667541 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6451 12:20:44.670754 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6452 12:20:44.674379 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6453 12:20:44.674467
6454 12:20:44.677707 CA PerBit enable=1, Macro0, CA PI delay=36
6455 12:20:44.677794
6456 12:20:44.681001 [CBTSetCACLKResult] CA Dly = 36
6457 12:20:44.684099 CS Dly: 1 (0~32)
6458 12:20:44.684192 ==
6459 12:20:44.687367 Dram Type= 6, Freq= 0, CH_1, rank 1
6460 12:20:44.690651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6461 12:20:44.690736 ==
6462 12:20:44.697290 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6463 12:20:44.704448 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6464 12:20:44.707347 [CA 0] Center 36 (8~64) winsize 57
6465 12:20:44.707436 [CA 1] Center 36 (8~64) winsize 57
6466 12:20:44.710775 [CA 2] Center 36 (8~64) winsize 57
6467 12:20:44.714106 [CA 3] Center 36 (8~64) winsize 57
6468 12:20:44.717302 [CA 4] Center 36 (8~64) winsize 57
6469 12:20:44.721167 [CA 5] Center 36 (8~64) winsize 57
6470 12:20:44.721251
6471 12:20:44.723814 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6472 12:20:44.723959
6473 12:20:44.727431 [CATrainingPosCal] consider 2 rank data
6474 12:20:44.730856 u2DelayCellTimex100 = 270/100 ps
6475 12:20:44.734068 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6476 12:20:44.740720 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6477 12:20:44.743948 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6478 12:20:44.747176 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6479 12:20:44.750496 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6480 12:20:44.753734 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6481 12:20:44.753820
6482 12:20:44.757038 CA PerBit enable=1, Macro0, CA PI delay=36
6483 12:20:44.757121
6484 12:20:44.760446 [CBTSetCACLKResult] CA Dly = 36
6485 12:20:44.760529 CS Dly: 1 (0~32)
6486 12:20:44.763688
6487 12:20:44.767073 ----->DramcWriteLeveling(PI) begin...
6488 12:20:44.767160 ==
6489 12:20:44.770276 Dram Type= 6, Freq= 0, CH_1, rank 0
6490 12:20:44.773809 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6491 12:20:44.773895 ==
6492 12:20:44.777119 Write leveling (Byte 0): 32 => 0
6493 12:20:44.780516 Write leveling (Byte 1): 32 => 0
6494 12:20:44.783737 DramcWriteLeveling(PI) end<-----
6495 12:20:44.783823
6496 12:20:44.783886 ==
6497 12:20:44.787026 Dram Type= 6, Freq= 0, CH_1, rank 0
6498 12:20:44.790275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6499 12:20:44.790393 ==
6500 12:20:44.793835 [Gating] SW mode calibration
6501 12:20:44.800357 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6502 12:20:44.806977 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6503 12:20:44.810370 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6504 12:20:44.813418 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6505 12:20:44.820216 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 12:20:44.823423 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6507 12:20:44.826899 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6508 12:20:44.833266 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 12:20:44.836736 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 12:20:44.840110 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6511 12:20:44.846732 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6512 12:20:44.846837 Total UI for P1: 0, mck2ui 16
6513 12:20:44.849887 best dqsien dly found for B0: ( 0, 10, 16)
6514 12:20:44.853210 Total UI for P1: 0, mck2ui 16
6515 12:20:44.856700 best dqsien dly found for B1: ( 0, 10, 16)
6516 12:20:44.863005 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6517 12:20:44.866406 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6518 12:20:44.866497
6519 12:20:44.869750 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6520 12:20:44.873039 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6521 12:20:44.876267 [Gating] SW calibration Done
6522 12:20:44.876388 ==
6523 12:20:44.879555 Dram Type= 6, Freq= 0, CH_1, rank 0
6524 12:20:44.883165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6525 12:20:44.883256 ==
6526 12:20:44.886358 RX Vref Scan: 0
6527 12:20:44.886478
6528 12:20:44.886543 RX Vref 0 -> 0, step: 1
6529 12:20:44.886602
6530 12:20:44.889581 RX Delay -410 -> 252, step: 16
6531 12:20:44.896519 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6532 12:20:44.899730 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6533 12:20:44.903198 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6534 12:20:44.906302 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6535 12:20:44.912862 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6536 12:20:44.916769 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6537 12:20:44.919565 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6538 12:20:44.923105 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6539 12:20:44.929596 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6540 12:20:44.932848 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6541 12:20:44.936025 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6542 12:20:44.939335 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6543 12:20:44.946183 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6544 12:20:44.949562 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6545 12:20:44.952805 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6546 12:20:44.956036 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6547 12:20:44.956124 ==
6548 12:20:44.959521 Dram Type= 6, Freq= 0, CH_1, rank 0
6549 12:20:44.966020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6550 12:20:44.966120 ==
6551 12:20:44.966190 DQS Delay:
6552 12:20:44.969520 DQS0 = 43, DQS1 = 59
6553 12:20:44.969604 DQM Delay:
6554 12:20:44.972760 DQM0 = 6, DQM1 = 15
6555 12:20:44.972845 DQ Delay:
6556 12:20:44.975993 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6557 12:20:44.979542 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6558 12:20:44.979630 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6559 12:20:44.985878 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6560 12:20:44.985980
6561 12:20:44.986047
6562 12:20:44.986106 ==
6563 12:20:44.989205 Dram Type= 6, Freq= 0, CH_1, rank 0
6564 12:20:44.992530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6565 12:20:44.992643 ==
6566 12:20:44.992723
6567 12:20:44.992783
6568 12:20:44.996374 TX Vref Scan disable
6569 12:20:44.996458 == TX Byte 0 ==
6570 12:20:44.999096 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6571 12:20:45.005833 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6572 12:20:45.005930 == TX Byte 1 ==
6573 12:20:45.009261 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6574 12:20:45.015954 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6575 12:20:45.016061 ==
6576 12:20:45.019156 Dram Type= 6, Freq= 0, CH_1, rank 0
6577 12:20:45.022585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6578 12:20:45.022674 ==
6579 12:20:45.022740
6580 12:20:45.022800
6581 12:20:45.025821 TX Vref Scan disable
6582 12:20:45.025908 == TX Byte 0 ==
6583 12:20:45.032334 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6584 12:20:45.035739 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6585 12:20:45.035828 == TX Byte 1 ==
6586 12:20:45.042459 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6587 12:20:45.045583 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6588 12:20:45.045678
6589 12:20:45.045745 [DATLAT]
6590 12:20:45.048931 Freq=400, CH1 RK0
6591 12:20:45.049030
6592 12:20:45.049097 DATLAT Default: 0xf
6593 12:20:45.052337 0, 0xFFFF, sum = 0
6594 12:20:45.052421 1, 0xFFFF, sum = 0
6595 12:20:45.055489 2, 0xFFFF, sum = 0
6596 12:20:45.055573 3, 0xFFFF, sum = 0
6597 12:20:45.058850 4, 0xFFFF, sum = 0
6598 12:20:45.058935 5, 0xFFFF, sum = 0
6599 12:20:45.062481 6, 0xFFFF, sum = 0
6600 12:20:45.065610 7, 0xFFFF, sum = 0
6601 12:20:45.065696 8, 0xFFFF, sum = 0
6602 12:20:45.068805 9, 0xFFFF, sum = 0
6603 12:20:45.068890 10, 0xFFFF, sum = 0
6604 12:20:45.072189 11, 0xFFFF, sum = 0
6605 12:20:45.072277 12, 0x0, sum = 1
6606 12:20:45.075272 13, 0x0, sum = 2
6607 12:20:45.075356 14, 0x0, sum = 3
6608 12:20:45.078820 15, 0x0, sum = 4
6609 12:20:45.078911 best_step = 13
6610 12:20:45.078977
6611 12:20:45.079037 ==
6612 12:20:45.082113 Dram Type= 6, Freq= 0, CH_1, rank 0
6613 12:20:45.085279 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6614 12:20:45.085365 ==
6615 12:20:45.088738 RX Vref Scan: 1
6616 12:20:45.088822
6617 12:20:45.092010 RX Vref 0 -> 0, step: 1
6618 12:20:45.092093
6619 12:20:45.092157 RX Delay -359 -> 252, step: 8
6620 12:20:45.092228
6621 12:20:45.095280 Set Vref, RX VrefLevel [Byte0]: 59
6622 12:20:45.098356 [Byte1]: 48
6623 12:20:45.103995
6624 12:20:45.104091 Final RX Vref Byte 0 = 59 to rank0
6625 12:20:45.107424 Final RX Vref Byte 1 = 48 to rank0
6626 12:20:45.110662 Final RX Vref Byte 0 = 59 to rank1
6627 12:20:45.113924 Final RX Vref Byte 1 = 48 to rank1==
6628 12:20:45.117372 Dram Type= 6, Freq= 0, CH_1, rank 0
6629 12:20:45.123813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6630 12:20:45.123918 ==
6631 12:20:45.123987 DQS Delay:
6632 12:20:45.127116 DQS0 = 52, DQS1 = 64
6633 12:20:45.127231 DQM Delay:
6634 12:20:45.127326 DQM0 = 11, DQM1 = 16
6635 12:20:45.130739 DQ Delay:
6636 12:20:45.133945 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =12
6637 12:20:45.137250 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6638 12:20:45.137337 DQ8 =0, DQ9 =8, DQ10 =20, DQ11 =8
6639 12:20:45.140479 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6640 12:20:45.143710
6641 12:20:45.143797
6642 12:20:45.150401 [DQSOSCAuto] RK0, (LSB)MR18= 0xd5d5, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6643 12:20:45.153597 CH1 RK0: MR19=C0C, MR18=D5D5
6644 12:20:45.160321 CH1_RK0: MR19=0xC0C, MR18=0xD5D5, DQSOSC=383, MR23=63, INC=402, DEC=268
6645 12:20:45.160419 ==
6646 12:20:45.163691 Dram Type= 6, Freq= 0, CH_1, rank 1
6647 12:20:45.167361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6648 12:20:45.167447 ==
6649 12:20:45.170428 [Gating] SW mode calibration
6650 12:20:45.176972 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6651 12:20:45.183794 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6652 12:20:45.186807 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6653 12:20:45.190270 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6654 12:20:45.196884 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 12:20:45.200080 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6656 12:20:45.203501 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6657 12:20:45.210053 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 12:20:45.213339 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 12:20:45.216680 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6660 12:20:45.223224 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 12:20:45.223372 Total UI for P1: 0, mck2ui 16
6662 12:20:45.229829 best dqsien dly found for B0: ( 0, 10, 16)
6663 12:20:45.229938 Total UI for P1: 0, mck2ui 16
6664 12:20:45.233382 best dqsien dly found for B1: ( 0, 10, 16)
6665 12:20:45.239777 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6666 12:20:45.243240 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6667 12:20:45.243328
6668 12:20:45.246513 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6669 12:20:45.250116 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6670 12:20:45.253179 [Gating] SW calibration Done
6671 12:20:45.253264 ==
6672 12:20:45.256380 Dram Type= 6, Freq= 0, CH_1, rank 1
6673 12:20:45.259559 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6674 12:20:45.259643 ==
6675 12:20:45.263117 RX Vref Scan: 0
6676 12:20:45.263200
6677 12:20:45.263264 RX Vref 0 -> 0, step: 1
6678 12:20:45.263323
6679 12:20:45.266257 RX Delay -410 -> 252, step: 16
6680 12:20:45.273233 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6681 12:20:45.276522 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6682 12:20:45.279637 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6683 12:20:45.282775 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6684 12:20:45.289640 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6685 12:20:45.292658 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6686 12:20:45.296421 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6687 12:20:45.299478 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6688 12:20:45.306024 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6689 12:20:45.309470 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6690 12:20:45.312752 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6691 12:20:45.315874 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6692 12:20:45.322638 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6693 12:20:45.325905 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6694 12:20:45.329331 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6695 12:20:45.332438 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6696 12:20:45.336105 ==
6697 12:20:45.339132 Dram Type= 6, Freq= 0, CH_1, rank 1
6698 12:20:45.342638 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6699 12:20:45.342728 ==
6700 12:20:45.342794 DQS Delay:
6701 12:20:45.346024 DQS0 = 43, DQS1 = 59
6702 12:20:45.346107 DQM Delay:
6703 12:20:45.349080 DQM0 = 10, DQM1 = 18
6704 12:20:45.349162 DQ Delay:
6705 12:20:45.352395 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6706 12:20:45.355754 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6707 12:20:45.359556 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6708 12:20:45.362559 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6709 12:20:45.362657
6710 12:20:45.362723
6711 12:20:45.362782 ==
6712 12:20:45.365707 Dram Type= 6, Freq= 0, CH_1, rank 1
6713 12:20:45.369247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6714 12:20:45.369340 ==
6715 12:20:45.369428
6716 12:20:45.369516
6717 12:20:45.372314 TX Vref Scan disable
6718 12:20:45.372397 == TX Byte 0 ==
6719 12:20:45.378989 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6720 12:20:45.382411 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6721 12:20:45.382520 == TX Byte 1 ==
6722 12:20:45.385960 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6723 12:20:45.392401 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6724 12:20:45.392497 ==
6725 12:20:45.395684 Dram Type= 6, Freq= 0, CH_1, rank 1
6726 12:20:45.398864 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6727 12:20:45.398950 ==
6728 12:20:45.399014
6729 12:20:45.399073
6730 12:20:45.402571 TX Vref Scan disable
6731 12:20:45.402654 == TX Byte 0 ==
6732 12:20:45.408732 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6733 12:20:45.412079 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6734 12:20:45.412170 == TX Byte 1 ==
6735 12:20:45.418784 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6736 12:20:45.422076 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6737 12:20:45.422164
6738 12:20:45.422229 [DATLAT]
6739 12:20:45.425552 Freq=400, CH1 RK1
6740 12:20:45.425639
6741 12:20:45.425704 DATLAT Default: 0xd
6742 12:20:45.428709 0, 0xFFFF, sum = 0
6743 12:20:45.428795 1, 0xFFFF, sum = 0
6744 12:20:45.432383 2, 0xFFFF, sum = 0
6745 12:20:45.432473 3, 0xFFFF, sum = 0
6746 12:20:45.435377 4, 0xFFFF, sum = 0
6747 12:20:45.435463 5, 0xFFFF, sum = 0
6748 12:20:45.438700 6, 0xFFFF, sum = 0
6749 12:20:45.438786 7, 0xFFFF, sum = 0
6750 12:20:45.442187 8, 0xFFFF, sum = 0
6751 12:20:45.442274 9, 0xFFFF, sum = 0
6752 12:20:45.445410 10, 0xFFFF, sum = 0
6753 12:20:45.445496 11, 0xFFFF, sum = 0
6754 12:20:45.448752 12, 0x0, sum = 1
6755 12:20:45.448838 13, 0x0, sum = 2
6756 12:20:45.451842 14, 0x0, sum = 3
6757 12:20:45.451929 15, 0x0, sum = 4
6758 12:20:45.455123 best_step = 13
6759 12:20:45.455208
6760 12:20:45.455273 ==
6761 12:20:45.458405 Dram Type= 6, Freq= 0, CH_1, rank 1
6762 12:20:45.461925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6763 12:20:45.462013 ==
6764 12:20:45.465163 RX Vref Scan: 0
6765 12:20:45.465246
6766 12:20:45.465311 RX Vref 0 -> 0, step: 1
6767 12:20:45.465372
6768 12:20:45.468457 RX Delay -359 -> 252, step: 8
6769 12:20:45.476622 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6770 12:20:45.480028 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6771 12:20:45.483553 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6772 12:20:45.486804 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6773 12:20:45.493310 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6774 12:20:45.496637 iDelay=217, Bit 5, Center -32 (-279 ~ 216) 496
6775 12:20:45.500270 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6776 12:20:45.503189 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6777 12:20:45.509929 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6778 12:20:45.513161 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6779 12:20:45.516466 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6780 12:20:45.522975 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6781 12:20:45.526239 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6782 12:20:45.529653 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6783 12:20:45.533089 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6784 12:20:45.540076 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6785 12:20:45.540213 ==
6786 12:20:45.543092 Dram Type= 6, Freq= 0, CH_1, rank 1
6787 12:20:45.546278 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6788 12:20:45.546368 ==
6789 12:20:45.546433 DQS Delay:
6790 12:20:45.549579 DQS0 = 48, DQS1 = 64
6791 12:20:45.549662 DQM Delay:
6792 12:20:45.553159 DQM0 = 9, DQM1 = 15
6793 12:20:45.553241 DQ Delay:
6794 12:20:45.556673 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6795 12:20:45.559623 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6796 12:20:45.562883 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6797 12:20:45.566556 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6798 12:20:45.566646
6799 12:20:45.566709
6800 12:20:45.572963 [DQSOSCAuto] RK1, (LSB)MR18= 0xa8a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6801 12:20:45.576131 CH1 RK1: MR19=C0C, MR18=A8A8
6802 12:20:45.582696 CH1_RK1: MR19=0xC0C, MR18=0xA8A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6803 12:20:45.585988 [RxdqsGatingPostProcess] freq 400
6804 12:20:45.592952 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6805 12:20:45.593058 Pre-setting of DQS Precalculation
6806 12:20:45.599357 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6807 12:20:45.605858 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6808 12:20:45.612480 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6809 12:20:45.612592
6810 12:20:45.612667
6811 12:20:45.615902 [Calibration Summary] 800 Mbps
6812 12:20:45.619328 CH 0, Rank 0
6813 12:20:45.619418 SW Impedance : PASS
6814 12:20:45.622524 DUTY Scan : NO K
6815 12:20:45.625959 ZQ Calibration : PASS
6816 12:20:45.626050 Jitter Meter : NO K
6817 12:20:45.629237 CBT Training : PASS
6818 12:20:45.629323 Write leveling : PASS
6819 12:20:45.632515 RX DQS gating : PASS
6820 12:20:45.635782 RX DQ/DQS(RDDQC) : PASS
6821 12:20:45.635868 TX DQ/DQS : PASS
6822 12:20:45.639139 RX DATLAT : PASS
6823 12:20:45.642489 RX DQ/DQS(Engine): PASS
6824 12:20:45.642574 TX OE : NO K
6825 12:20:45.645657 All Pass.
6826 12:20:45.645741
6827 12:20:45.645806 CH 0, Rank 1
6828 12:20:45.648993 SW Impedance : PASS
6829 12:20:45.649076 DUTY Scan : NO K
6830 12:20:45.652471 ZQ Calibration : PASS
6831 12:20:45.655830 Jitter Meter : NO K
6832 12:20:45.655914 CBT Training : PASS
6833 12:20:45.659268 Write leveling : NO K
6834 12:20:45.662226 RX DQS gating : PASS
6835 12:20:45.662310 RX DQ/DQS(RDDQC) : PASS
6836 12:20:45.665824 TX DQ/DQS : PASS
6837 12:20:45.668844 RX DATLAT : PASS
6838 12:20:45.668927 RX DQ/DQS(Engine): PASS
6839 12:20:45.674092 TX OE : NO K
6840 12:20:45.674180 All Pass.
6841 12:20:45.674244
6842 12:20:45.675904 CH 1, Rank 0
6843 12:20:45.675984 SW Impedance : PASS
6844 12:20:45.678946 DUTY Scan : NO K
6845 12:20:45.682225 ZQ Calibration : PASS
6846 12:20:45.682310 Jitter Meter : NO K
6847 12:20:45.685569 CBT Training : PASS
6848 12:20:45.688909 Write leveling : PASS
6849 12:20:45.688994 RX DQS gating : PASS
6850 12:20:45.692120 RX DQ/DQS(RDDQC) : PASS
6851 12:20:45.692208 TX DQ/DQS : PASS
6852 12:20:45.695458 RX DATLAT : PASS
6853 12:20:45.698750 RX DQ/DQS(Engine): PASS
6854 12:20:45.698834 TX OE : NO K
6855 12:20:45.702042 All Pass.
6856 12:20:45.702122
6857 12:20:45.702209 CH 1, Rank 1
6858 12:20:45.705561 SW Impedance : PASS
6859 12:20:45.705643 DUTY Scan : NO K
6860 12:20:45.708678 ZQ Calibration : PASS
6861 12:20:45.711902 Jitter Meter : NO K
6862 12:20:45.711986 CBT Training : PASS
6863 12:20:45.715257 Write leveling : NO K
6864 12:20:45.718701 RX DQS gating : PASS
6865 12:20:45.718788 RX DQ/DQS(RDDQC) : PASS
6866 12:20:45.721969 TX DQ/DQS : PASS
6867 12:20:45.725291 RX DATLAT : PASS
6868 12:20:45.725377 RX DQ/DQS(Engine): PASS
6869 12:20:45.728710 TX OE : NO K
6870 12:20:45.728800 All Pass.
6871 12:20:45.728866
6872 12:20:45.731821 DramC Write-DBI off
6873 12:20:45.735009 PER_BANK_REFRESH: Hybrid Mode
6874 12:20:45.735094 TX_TRACKING: ON
6875 12:20:45.745122 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6876 12:20:45.748311 [FAST_K] Save calibration result to emmc
6877 12:20:45.752070 dramc_set_vcore_voltage set vcore to 725000
6878 12:20:45.755175 Read voltage for 1600, 0
6879 12:20:45.755262 Vio18 = 0
6880 12:20:45.755326 Vcore = 725000
6881 12:20:45.758498 Vdram = 0
6882 12:20:45.758580 Vddq = 0
6883 12:20:45.758644 Vmddr = 0
6884 12:20:45.765006 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6885 12:20:45.768377 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6886 12:20:45.771590 MEM_TYPE=3, freq_sel=13
6887 12:20:45.774846 sv_algorithm_assistance_LP4_3733
6888 12:20:45.778234 ============ PULL DRAM RESETB DOWN ============
6889 12:20:45.781562 ========== PULL DRAM RESETB DOWN end =========
6890 12:20:45.788523 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6891 12:20:45.791590 ===================================
6892 12:20:45.794720 LPDDR4 DRAM CONFIGURATION
6893 12:20:45.798200 ===================================
6894 12:20:45.798286 EX_ROW_EN[0] = 0x0
6895 12:20:45.801630 EX_ROW_EN[1] = 0x0
6896 12:20:45.801713 LP4Y_EN = 0x0
6897 12:20:45.804983 WORK_FSP = 0x1
6898 12:20:45.805066 WL = 0x5
6899 12:20:45.808564 RL = 0x5
6900 12:20:45.808653 BL = 0x2
6901 12:20:45.811369 RPST = 0x0
6902 12:20:45.811451 RD_PRE = 0x0
6903 12:20:45.814922 WR_PRE = 0x1
6904 12:20:45.815004 WR_PST = 0x1
6905 12:20:45.818359 DBI_WR = 0x0
6906 12:20:45.818441 DBI_RD = 0x0
6907 12:20:45.821414 OTF = 0x1
6908 12:20:45.824582 ===================================
6909 12:20:45.827944 ===================================
6910 12:20:45.828037 ANA top config
6911 12:20:45.831392 ===================================
6912 12:20:45.834674 DLL_ASYNC_EN = 0
6913 12:20:45.838045 ALL_SLAVE_EN = 0
6914 12:20:45.841571 NEW_RANK_MODE = 1
6915 12:20:45.841662 DLL_IDLE_MODE = 1
6916 12:20:45.844913 LP45_APHY_COMB_EN = 1
6917 12:20:45.847923 TX_ODT_DIS = 0
6918 12:20:45.851316 NEW_8X_MODE = 1
6919 12:20:45.854526 ===================================
6920 12:20:45.857982 ===================================
6921 12:20:45.861468 data_rate = 3200
6922 12:20:45.861556 CKR = 1
6923 12:20:45.864641 DQ_P2S_RATIO = 8
6924 12:20:45.867887 ===================================
6925 12:20:45.871313 CA_P2S_RATIO = 8
6926 12:20:45.874307 DQ_CA_OPEN = 0
6927 12:20:45.877855 DQ_SEMI_OPEN = 0
6928 12:20:45.881162 CA_SEMI_OPEN = 0
6929 12:20:45.881250 CA_FULL_RATE = 0
6930 12:20:45.884529 DQ_CKDIV4_EN = 0
6931 12:20:45.887737 CA_CKDIV4_EN = 0
6932 12:20:45.891090 CA_PREDIV_EN = 0
6933 12:20:45.894419 PH8_DLY = 12
6934 12:20:45.897876 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6935 12:20:45.897962 DQ_AAMCK_DIV = 4
6936 12:20:45.900902 CA_AAMCK_DIV = 4
6937 12:20:45.904303 CA_ADMCK_DIV = 4
6938 12:20:45.907801 DQ_TRACK_CA_EN = 0
6939 12:20:45.910947 CA_PICK = 1600
6940 12:20:45.914239 CA_MCKIO = 1600
6941 12:20:45.917637 MCKIO_SEMI = 0
6942 12:20:45.920805 PLL_FREQ = 3068
6943 12:20:45.920891 DQ_UI_PI_RATIO = 32
6944 12:20:45.924162 CA_UI_PI_RATIO = 0
6945 12:20:45.927587 ===================================
6946 12:20:45.930882 ===================================
6947 12:20:45.934017 memory_type:LPDDR4
6948 12:20:45.937435 GP_NUM : 10
6949 12:20:45.937537 SRAM_EN : 1
6950 12:20:45.940648 MD32_EN : 0
6951 12:20:45.943991 ===================================
6952 12:20:45.947288 [ANA_INIT] >>>>>>>>>>>>>>
6953 12:20:45.947374 <<<<<< [CONFIGURE PHASE]: ANA_TX
6954 12:20:45.950668 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6955 12:20:45.953863 ===================================
6956 12:20:45.957203 data_rate = 3200,PCW = 0X7600
6957 12:20:45.960509 ===================================
6958 12:20:45.963782 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6959 12:20:45.970465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6960 12:20:45.977148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6961 12:20:45.980448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6962 12:20:45.983603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6963 12:20:45.987046 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6964 12:20:45.990578 [ANA_INIT] flow start
6965 12:20:45.990667 [ANA_INIT] PLL >>>>>>>>
6966 12:20:45.993563 [ANA_INIT] PLL <<<<<<<<
6967 12:20:45.996962 [ANA_INIT] MIDPI >>>>>>>>
6968 12:20:45.997045 [ANA_INIT] MIDPI <<<<<<<<
6969 12:20:46.000302 [ANA_INIT] DLL >>>>>>>>
6970 12:20:46.003664 [ANA_INIT] DLL <<<<<<<<
6971 12:20:46.003752 [ANA_INIT] flow end
6972 12:20:46.010352 ============ LP4 DIFF to SE enter ============
6973 12:20:46.013445 ============ LP4 DIFF to SE exit ============
6974 12:20:46.016979 [ANA_INIT] <<<<<<<<<<<<<
6975 12:20:46.020125 [Flow] Enable top DCM control >>>>>
6976 12:20:46.023695 [Flow] Enable top DCM control <<<<<
6977 12:20:46.023789 Enable DLL master slave shuffle
6978 12:20:46.030170 ==============================================================
6979 12:20:46.033509 Gating Mode config
6980 12:20:46.037173 ==============================================================
6981 12:20:46.040138 Config description:
6982 12:20:46.049874 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6983 12:20:46.056723 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6984 12:20:46.060064 SELPH_MODE 0: By rank 1: By Phase
6985 12:20:46.066713 ==============================================================
6986 12:20:46.070049 GAT_TRACK_EN = 1
6987 12:20:46.073227 RX_GATING_MODE = 2
6988 12:20:46.076587 RX_GATING_TRACK_MODE = 2
6989 12:20:46.079645 SELPH_MODE = 1
6990 12:20:46.083132 PICG_EARLY_EN = 1
6991 12:20:46.083223 VALID_LAT_VALUE = 1
6992 12:20:46.089851 ==============================================================
6993 12:20:46.092936 Enter into Gating configuration >>>>
6994 12:20:46.096300 Exit from Gating configuration <<<<
6995 12:20:46.099622 Enter into DVFS_PRE_config >>>>>
6996 12:20:46.109782 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6997 12:20:46.112667 Exit from DVFS_PRE_config <<<<<
6998 12:20:46.116020 Enter into PICG configuration >>>>
6999 12:20:46.119354 Exit from PICG configuration <<<<
7000 12:20:46.122764 [RX_INPUT] configuration >>>>>
7001 12:20:46.125800 [RX_INPUT] configuration <<<<<
7002 12:20:46.132879 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7003 12:20:46.135867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7004 12:20:46.142472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7005 12:20:46.148881 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7006 12:20:46.155401 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7007 12:20:46.162296 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7008 12:20:46.165533 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7009 12:20:46.168941 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7010 12:20:46.172097 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7011 12:20:46.178546 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7012 12:20:46.182182 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7013 12:20:46.185186 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7014 12:20:46.188573 ===================================
7015 12:20:46.191899 LPDDR4 DRAM CONFIGURATION
7016 12:20:46.195385 ===================================
7017 12:20:46.195476 EX_ROW_EN[0] = 0x0
7018 12:20:46.198613 EX_ROW_EN[1] = 0x0
7019 12:20:46.202350 LP4Y_EN = 0x0
7020 12:20:46.202436 WORK_FSP = 0x1
7021 12:20:46.205197 WL = 0x5
7022 12:20:46.205281 RL = 0x5
7023 12:20:46.208890 BL = 0x2
7024 12:20:46.208974 RPST = 0x0
7025 12:20:46.211899 RD_PRE = 0x0
7026 12:20:46.211984 WR_PRE = 0x1
7027 12:20:46.215201 WR_PST = 0x1
7028 12:20:46.215285 DBI_WR = 0x0
7029 12:20:46.218178 DBI_RD = 0x0
7030 12:20:46.218262 OTF = 0x1
7031 12:20:46.221649 ===================================
7032 12:20:46.228360 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7033 12:20:46.231760 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7034 12:20:46.234845 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7035 12:20:46.238418 ===================================
7036 12:20:46.241640 LPDDR4 DRAM CONFIGURATION
7037 12:20:46.244646 ===================================
7038 12:20:46.247848 EX_ROW_EN[0] = 0x10
7039 12:20:46.247939 EX_ROW_EN[1] = 0x0
7040 12:20:46.251591 LP4Y_EN = 0x0
7041 12:20:46.251676 WORK_FSP = 0x1
7042 12:20:46.254744 WL = 0x5
7043 12:20:46.254830 RL = 0x5
7044 12:20:46.258085 BL = 0x2
7045 12:20:46.258171 RPST = 0x0
7046 12:20:46.261168 RD_PRE = 0x0
7047 12:20:46.261252 WR_PRE = 0x1
7048 12:20:46.264376 WR_PST = 0x1
7049 12:20:46.264460 DBI_WR = 0x0
7050 12:20:46.267678 DBI_RD = 0x0
7051 12:20:46.267819 OTF = 0x1
7052 12:20:46.271168 ===================================
7053 12:20:46.277789 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7054 12:20:46.277909 ==
7055 12:20:46.280999 Dram Type= 6, Freq= 0, CH_0, rank 0
7056 12:20:46.287708 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7057 12:20:46.287817 ==
7058 12:20:46.287906 [Duty_Offset_Calibration]
7059 12:20:46.290959 B0:0 B1:2 CA:1
7060 12:20:46.291043
7061 12:20:46.294150 [DutyScan_Calibration_Flow] k_type=0
7062 12:20:46.303510
7063 12:20:46.303623 ==CLK 0==
7064 12:20:46.306832 Final CLK duty delay cell = 0
7065 12:20:46.310059 [0] MAX Duty = 5187%(X100), DQS PI = 24
7066 12:20:46.313383 [0] MIN Duty = 4938%(X100), DQS PI = 50
7067 12:20:46.316806 [0] AVG Duty = 5062%(X100)
7068 12:20:46.316896
7069 12:20:46.319831 CH0 CLK Duty spec in!! Max-Min= 249%
7070 12:20:46.323274 [DutyScan_Calibration_Flow] ====Done====
7071 12:20:46.323362
7072 12:20:46.326415 [DutyScan_Calibration_Flow] k_type=1
7073 12:20:46.342696
7074 12:20:46.342851 ==DQS 0 ==
7075 12:20:46.346115 Final DQS duty delay cell = -4
7076 12:20:46.349229 [-4] MAX Duty = 4969%(X100), DQS PI = 2
7077 12:20:46.352658 [-4] MIN Duty = 4875%(X100), DQS PI = 8
7078 12:20:46.356097 [-4] AVG Duty = 4922%(X100)
7079 12:20:46.356195
7080 12:20:46.356283 ==DQS 1 ==
7081 12:20:46.359355 Final DQS duty delay cell = 0
7082 12:20:46.362824 [0] MAX Duty = 5031%(X100), DQS PI = 2
7083 12:20:46.365947 [0] MIN Duty = 4876%(X100), DQS PI = 16
7084 12:20:46.369155 [0] AVG Duty = 4953%(X100)
7085 12:20:46.369244
7086 12:20:46.372652 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7087 12:20:46.372740
7088 12:20:46.375731 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7089 12:20:46.379152 [DutyScan_Calibration_Flow] ====Done====
7090 12:20:46.379242
7091 12:20:46.382296 [DutyScan_Calibration_Flow] k_type=3
7092 12:20:46.399863
7093 12:20:46.400047 ==DQM 0 ==
7094 12:20:46.403157 Final DQM duty delay cell = 0
7095 12:20:46.406635 [0] MAX Duty = 5218%(X100), DQS PI = 24
7096 12:20:46.410077 [0] MIN Duty = 4907%(X100), DQS PI = 56
7097 12:20:46.413357 [0] AVG Duty = 5062%(X100)
7098 12:20:46.413446
7099 12:20:46.413530 ==DQM 1 ==
7100 12:20:46.416849 Final DQM duty delay cell = 0
7101 12:20:46.419921 [0] MAX Duty = 5031%(X100), DQS PI = 52
7102 12:20:46.423217 [0] MIN Duty = 4782%(X100), DQS PI = 14
7103 12:20:46.426553 [0] AVG Duty = 4906%(X100)
7104 12:20:46.426639
7105 12:20:46.429951 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7106 12:20:46.430041
7107 12:20:46.433297 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7108 12:20:46.436471 [DutyScan_Calibration_Flow] ====Done====
7109 12:20:46.436556
7110 12:20:46.439502 [DutyScan_Calibration_Flow] k_type=2
7111 12:20:46.456366
7112 12:20:46.456513 ==DQ 0 ==
7113 12:20:46.459615 Final DQ duty delay cell = 0
7114 12:20:46.462956 [0] MAX Duty = 5218%(X100), DQS PI = 18
7115 12:20:46.466299 [0] MIN Duty = 4969%(X100), DQS PI = 54
7116 12:20:46.466387 [0] AVG Duty = 5093%(X100)
7117 12:20:46.469538
7118 12:20:46.469623 ==DQ 1 ==
7119 12:20:46.472876 Final DQ duty delay cell = -4
7120 12:20:46.476201 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7121 12:20:46.479322 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7122 12:20:46.482636 [-4] AVG Duty = 4953%(X100)
7123 12:20:46.482725
7124 12:20:46.486033 CH0 DQ 0 Duty spec in!! Max-Min= 249%
7125 12:20:46.486119
7126 12:20:46.489487 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7127 12:20:46.492967 [DutyScan_Calibration_Flow] ====Done====
7128 12:20:46.493053 ==
7129 12:20:46.496057 Dram Type= 6, Freq= 0, CH_1, rank 0
7130 12:20:46.499497 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7131 12:20:46.499584 ==
7132 12:20:46.502947 [Duty_Offset_Calibration]
7133 12:20:46.503031 B0:0 B1:4 CA:-5
7134 12:20:46.503117
7135 12:20:46.506344 [DutyScan_Calibration_Flow] k_type=0
7136 12:20:46.516977
7137 12:20:46.517100 ==CLK 0==
7138 12:20:46.520157 Final CLK duty delay cell = 0
7139 12:20:46.523438 [0] MAX Duty = 5156%(X100), DQS PI = 20
7140 12:20:46.527151 [0] MIN Duty = 4875%(X100), DQS PI = 50
7141 12:20:46.530132 [0] AVG Duty = 5015%(X100)
7142 12:20:46.530224
7143 12:20:46.533546 CH1 CLK Duty spec in!! Max-Min= 281%
7144 12:20:46.536674 [DutyScan_Calibration_Flow] ====Done====
7145 12:20:46.536760
7146 12:20:46.539953 [DutyScan_Calibration_Flow] k_type=1
7147 12:20:46.555867
7148 12:20:46.556012 ==DQS 0 ==
7149 12:20:46.559153 Final DQS duty delay cell = 0
7150 12:20:46.562513 [0] MAX Duty = 5156%(X100), DQS PI = 18
7151 12:20:46.565821 [0] MIN Duty = 4876%(X100), DQS PI = 42
7152 12:20:46.569218 [0] AVG Duty = 5016%(X100)
7153 12:20:46.569303
7154 12:20:46.569367 ==DQS 1 ==
7155 12:20:46.572451 Final DQS duty delay cell = -4
7156 12:20:46.575883 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7157 12:20:46.579320 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7158 12:20:46.582385 [-4] AVG Duty = 4922%(X100)
7159 12:20:46.582471
7160 12:20:46.585803 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7161 12:20:46.585885
7162 12:20:46.589026 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7163 12:20:46.592394 [DutyScan_Calibration_Flow] ====Done====
7164 12:20:46.592524
7165 12:20:46.595784 [DutyScan_Calibration_Flow] k_type=3
7166 12:20:46.611922
7167 12:20:46.612074 ==DQM 0 ==
7168 12:20:46.614872 Final DQM duty delay cell = -4
7169 12:20:46.618223 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7170 12:20:46.621544 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7171 12:20:46.624889 [-4] AVG Duty = 4937%(X100)
7172 12:20:46.624974
7173 12:20:46.625038 ==DQM 1 ==
7174 12:20:46.628113 Final DQM duty delay cell = -4
7175 12:20:46.631434 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7176 12:20:46.634674 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7177 12:20:46.638149 [-4] AVG Duty = 5000%(X100)
7178 12:20:46.638236
7179 12:20:46.641170 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7180 12:20:46.641254
7181 12:20:46.644552 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7182 12:20:46.647850 [DutyScan_Calibration_Flow] ====Done====
7183 12:20:46.647936
7184 12:20:46.651102 [DutyScan_Calibration_Flow] k_type=2
7185 12:20:46.669381
7186 12:20:46.669533 ==DQ 0 ==
7187 12:20:46.672518 Final DQ duty delay cell = 0
7188 12:20:46.675774 [0] MAX Duty = 5062%(X100), DQS PI = 0
7189 12:20:46.679359 [0] MIN Duty = 4938%(X100), DQS PI = 48
7190 12:20:46.679448 [0] AVG Duty = 5000%(X100)
7191 12:20:46.679513
7192 12:20:46.682257 ==DQ 1 ==
7193 12:20:46.685798 Final DQ duty delay cell = 0
7194 12:20:46.689134 [0] MAX Duty = 5031%(X100), DQS PI = 4
7195 12:20:46.692517 [0] MIN Duty = 4907%(X100), DQS PI = 14
7196 12:20:46.692605 [0] AVG Duty = 4969%(X100)
7197 12:20:46.692671
7198 12:20:46.695875 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7199 12:20:46.695959
7200 12:20:46.702269 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7201 12:20:46.705520 [DutyScan_Calibration_Flow] ====Done====
7202 12:20:46.709073 nWR fixed to 30
7203 12:20:46.709195 [ModeRegInit_LP4] CH0 RK0
7204 12:20:46.712168 [ModeRegInit_LP4] CH0 RK1
7205 12:20:46.715576 [ModeRegInit_LP4] CH1 RK0
7206 12:20:46.715674 [ModeRegInit_LP4] CH1 RK1
7207 12:20:46.719221 match AC timing 4
7208 12:20:46.722284 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7209 12:20:46.725632 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7210 12:20:46.732315 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7211 12:20:46.735727 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7212 12:20:46.742043 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7213 12:20:46.742154 [MiockJmeterHQA]
7214 12:20:46.742219
7215 12:20:46.745304 [DramcMiockJmeter] u1RxGatingPI = 0
7216 12:20:46.748663 0 : 4255, 4029
7217 12:20:46.748802 4 : 4252, 4027
7218 12:20:46.748866 8 : 4250, 4026
7219 12:20:46.752406 12 : 4363, 4137
7220 12:20:46.752489 16 : 4363, 4137
7221 12:20:46.755215 20 : 4253, 4027
7222 12:20:46.755297 24 : 4253, 4026
7223 12:20:46.758504 28 : 4252, 4027
7224 12:20:46.758587 32 : 4255, 4029
7225 12:20:46.762277 36 : 4363, 4137
7226 12:20:46.762362 40 : 4253, 4026
7227 12:20:46.762427 44 : 4252, 4027
7228 12:20:46.765260 48 : 4253, 4027
7229 12:20:46.765343 52 : 4255, 4029
7230 12:20:46.768943 56 : 4250, 4027
7231 12:20:46.769026 60 : 4361, 4138
7232 12:20:46.771765 64 : 4360, 4138
7233 12:20:46.771847 68 : 4250, 4027
7234 12:20:46.775190 72 : 4250, 4027
7235 12:20:46.775273 76 : 4250, 4026
7236 12:20:46.775336 80 : 4250, 4027
7237 12:20:46.778768 84 : 4252, 4029
7238 12:20:46.778854 88 : 4360, 4138
7239 12:20:46.781898 92 : 4250, 4027
7240 12:20:46.781982 96 : 4250, 4027
7241 12:20:46.785266 100 : 4250, 2239
7242 12:20:46.785350 104 : 4250, 0
7243 12:20:46.785415 108 : 4250, 0
7244 12:20:46.788867 112 : 4251, 0
7245 12:20:46.788949 116 : 4251, 0
7246 12:20:46.792011 120 : 4250, 0
7247 12:20:46.792094 124 : 4250, 0
7248 12:20:46.792159 128 : 4252, 0
7249 12:20:46.795592 132 : 4250, 0
7250 12:20:46.795674 136 : 4250, 0
7251 12:20:46.798868 140 : 4250, 0
7252 12:20:46.798951 144 : 4361, 0
7253 12:20:46.799017 148 : 4250, 0
7254 12:20:46.801739 152 : 4250, 0
7255 12:20:46.801822 156 : 4252, 0
7256 12:20:46.801887 160 : 4361, 0
7257 12:20:46.805079 164 : 4250, 0
7258 12:20:46.805161 168 : 4249, 0
7259 12:20:46.808408 172 : 4250, 0
7260 12:20:46.808492 176 : 4360, 0
7261 12:20:46.808557 180 : 4361, 0
7262 12:20:46.811723 184 : 4250, 0
7263 12:20:46.811806 188 : 4250, 0
7264 12:20:46.815090 192 : 4250, 0
7265 12:20:46.815175 196 : 4361, 0
7266 12:20:46.815241 200 : 4361, 0
7267 12:20:46.818324 204 : 4363, 0
7268 12:20:46.818409 208 : 4250, 0
7269 12:20:46.821826 212 : 4250, 0
7270 12:20:46.821909 216 : 4250, 0
7271 12:20:46.821975 220 : 4252, 642
7272 12:20:46.825009 224 : 4250, 4011
7273 12:20:46.825094 228 : 4250, 4027
7274 12:20:46.828412 232 : 4360, 4138
7275 12:20:46.828500 236 : 4250, 4027
7276 12:20:46.831684 240 : 4250, 4026
7277 12:20:46.831769 244 : 4361, 4137
7278 12:20:46.834932 248 : 4250, 4027
7279 12:20:46.835017 252 : 4250, 4027
7280 12:20:46.838187 256 : 4363, 4140
7281 12:20:46.838270 260 : 4250, 4027
7282 12:20:46.841559 264 : 4250, 4027
7283 12:20:46.841643 268 : 4250, 4027
7284 12:20:46.841708 272 : 4252, 4029
7285 12:20:46.844963 276 : 4250, 4026
7286 12:20:46.845047 280 : 4250, 4027
7287 12:20:46.848321 284 : 4360, 4138
7288 12:20:46.848405 288 : 4250, 4027
7289 12:20:46.851482 292 : 4250, 4026
7290 12:20:46.851566 296 : 4361, 4137
7291 12:20:46.854904 300 : 4250, 4027
7292 12:20:46.854988 304 : 4250, 4027
7293 12:20:46.858347 308 : 4363, 4140
7294 12:20:46.858431 312 : 4250, 4027
7295 12:20:46.861512 316 : 4250, 4027
7296 12:20:46.861595 320 : 4250, 4027
7297 12:20:46.864670 324 : 4252, 4029
7298 12:20:46.864754 328 : 4250, 4027
7299 12:20:46.868076 332 : 4250, 4027
7300 12:20:46.868159 336 : 4361, 4022
7301 12:20:46.868267 340 : 4250, 1924
7302 12:20:46.868328
7303 12:20:46.871475 MIOCK jitter meter ch=0
7304 12:20:46.871556
7305 12:20:46.874689 1T = (340-104) = 236 dly cells
7306 12:20:46.881312 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7307 12:20:46.881415 ==
7308 12:20:46.884931 Dram Type= 6, Freq= 0, CH_0, rank 0
7309 12:20:46.887968 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7310 12:20:46.888054 ==
7311 12:20:46.894756 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7312 12:20:46.897818 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7313 12:20:46.901247 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7314 12:20:46.907717 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7315 12:20:46.916082 [CA 0] Center 41 (11~72) winsize 62
7316 12:20:46.919422 [CA 1] Center 41 (11~72) winsize 62
7317 12:20:46.922738 [CA 2] Center 37 (7~67) winsize 61
7318 12:20:46.926167 [CA 3] Center 37 (7~67) winsize 61
7319 12:20:46.929317 [CA 4] Center 35 (5~66) winsize 62
7320 12:20:46.932712 [CA 5] Center 35 (5~65) winsize 61
7321 12:20:46.932802
7322 12:20:46.935990 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7323 12:20:46.936101
7324 12:20:46.939309 [CATrainingPosCal] consider 1 rank data
7325 12:20:46.942736 u2DelayCellTimex100 = 275/100 ps
7326 12:20:46.949401 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7327 12:20:46.952500 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7328 12:20:46.955924 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7329 12:20:46.959183 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7330 12:20:46.962444 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7331 12:20:46.965816 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7332 12:20:46.965901
7333 12:20:46.969094 CA PerBit enable=1, Macro0, CA PI delay=35
7334 12:20:46.969177
7335 12:20:46.972498 [CBTSetCACLKResult] CA Dly = 35
7336 12:20:46.975966 CS Dly: 11 (0~42)
7337 12:20:46.979088 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7338 12:20:46.982536 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7339 12:20:46.982623 ==
7340 12:20:46.985656 Dram Type= 6, Freq= 0, CH_0, rank 1
7341 12:20:46.992297 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7342 12:20:46.992396 ==
7343 12:20:46.995597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7344 12:20:46.998951 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7345 12:20:47.005483 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7346 12:20:47.012101 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7347 12:20:47.018782 [CA 0] Center 42 (12~73) winsize 62
7348 12:20:47.022229 [CA 1] Center 42 (12~73) winsize 62
7349 12:20:47.025498 [CA 2] Center 38 (9~68) winsize 60
7350 12:20:47.028682 [CA 3] Center 37 (8~67) winsize 60
7351 12:20:47.032158 [CA 4] Center 36 (6~66) winsize 61
7352 12:20:47.035395 [CA 5] Center 36 (6~66) winsize 61
7353 12:20:47.035507
7354 12:20:47.038875 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7355 12:20:47.038962
7356 12:20:47.042081 [CATrainingPosCal] consider 2 rank data
7357 12:20:47.045257 u2DelayCellTimex100 = 275/100 ps
7358 12:20:47.048895 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7359 12:20:47.055883 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7360 12:20:47.058833 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7361 12:20:47.062117 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7362 12:20:47.065310 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7363 12:20:47.068718 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7364 12:20:47.068803
7365 12:20:47.072468 CA PerBit enable=1, Macro0, CA PI delay=35
7366 12:20:47.072552
7367 12:20:47.075393 [CBTSetCACLKResult] CA Dly = 35
7368 12:20:47.078804 CS Dly: 11 (0~42)
7369 12:20:47.081979 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7370 12:20:47.085556 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7371 12:20:47.085660
7372 12:20:47.088668 ----->DramcWriteLeveling(PI) begin...
7373 12:20:47.088753 ==
7374 12:20:47.092161 Dram Type= 6, Freq= 0, CH_0, rank 0
7375 12:20:47.095422 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7376 12:20:47.098738 ==
7377 12:20:47.098823 Write leveling (Byte 0): 29 => 29
7378 12:20:47.101864 Write leveling (Byte 1): 27 => 27
7379 12:20:47.105250 DramcWriteLeveling(PI) end<-----
7380 12:20:47.105334
7381 12:20:47.105397 ==
7382 12:20:47.108413 Dram Type= 6, Freq= 0, CH_0, rank 0
7383 12:20:47.115080 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7384 12:20:47.115182 ==
7385 12:20:47.118413 [Gating] SW mode calibration
7386 12:20:47.125101 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7387 12:20:47.128434 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7388 12:20:47.134902 0 12 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (1 1)
7389 12:20:47.138242 0 12 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7390 12:20:47.141912 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7391 12:20:47.148479 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7392 12:20:47.151635 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7393 12:20:47.155052 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7394 12:20:47.161600 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7395 12:20:47.164865 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7396 12:20:47.168296 0 13 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7397 12:20:47.175095 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
7398 12:20:47.178114 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 12:20:47.181673 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7400 12:20:47.184777 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7401 12:20:47.191466 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7402 12:20:47.194764 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7403 12:20:47.198264 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7404 12:20:47.204594 0 14 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7405 12:20:47.207870 0 14 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7406 12:20:47.211204 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7407 12:20:47.217910 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7408 12:20:47.221186 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7409 12:20:47.224445 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7410 12:20:47.231183 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7411 12:20:47.234332 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7412 12:20:47.238043 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7413 12:20:47.244436 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7414 12:20:47.247696 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7415 12:20:47.251144 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 12:20:47.257735 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 12:20:47.260981 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 12:20:47.264201 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 12:20:47.271213 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 12:20:47.274458 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 12:20:47.277880 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 12:20:47.284120 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 12:20:47.287740 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 12:20:47.291132 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7425 12:20:47.297891 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7426 12:20:47.300894 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7427 12:20:47.304006 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7428 12:20:47.311050 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7429 12:20:47.314338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7430 12:20:47.317601 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7431 12:20:47.320691 Total UI for P1: 0, mck2ui 16
7432 12:20:47.324157 best dqsien dly found for B0: ( 1, 1, 2)
7433 12:20:47.327896 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7434 12:20:47.330980 Total UI for P1: 0, mck2ui 16
7435 12:20:47.334286 best dqsien dly found for B1: ( 1, 1, 4)
7436 12:20:47.337669 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7437 12:20:47.341196 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7438 12:20:47.344688
7439 12:20:47.347394 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7440 12:20:47.350697 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7441 12:20:47.353966 [Gating] SW calibration Done
7442 12:20:47.354104 ==
7443 12:20:47.357612 Dram Type= 6, Freq= 0, CH_0, rank 0
7444 12:20:47.360749 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7445 12:20:47.360838 ==
7446 12:20:47.360902 RX Vref Scan: 0
7447 12:20:47.360962
7448 12:20:47.364004 RX Vref 0 -> 0, step: 1
7449 12:20:47.364087
7450 12:20:47.367280 RX Delay 0 -> 252, step: 8
7451 12:20:47.370847 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7452 12:20:47.374180 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7453 12:20:47.377215 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7454 12:20:47.383966 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7455 12:20:47.387451 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7456 12:20:47.390770 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7457 12:20:47.393984 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7458 12:20:47.397567 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7459 12:20:47.403978 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7460 12:20:47.407452 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7461 12:20:47.410509 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7462 12:20:47.413925 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7463 12:20:47.420504 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7464 12:20:47.423906 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7465 12:20:47.427169 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7466 12:20:47.430341 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7467 12:20:47.430434 ==
7468 12:20:47.433837 Dram Type= 6, Freq= 0, CH_0, rank 0
7469 12:20:47.437526 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7470 12:20:47.440830 ==
7471 12:20:47.440922 DQS Delay:
7472 12:20:47.440986 DQS0 = 0, DQS1 = 0
7473 12:20:47.443967 DQM Delay:
7474 12:20:47.444048 DQM0 = 130, DQM1 = 124
7475 12:20:47.447193 DQ Delay:
7476 12:20:47.450522 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7477 12:20:47.453692 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7478 12:20:47.457101 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7479 12:20:47.460672 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7480 12:20:47.460761
7481 12:20:47.460827
7482 12:20:47.460886 ==
7483 12:20:47.463553 Dram Type= 6, Freq= 0, CH_0, rank 0
7484 12:20:47.467042 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7485 12:20:47.467127 ==
7486 12:20:47.470151
7487 12:20:47.470233
7488 12:20:47.470297 TX Vref Scan disable
7489 12:20:47.473632 == TX Byte 0 ==
7490 12:20:47.477174 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7491 12:20:47.480289 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7492 12:20:47.483560 == TX Byte 1 ==
7493 12:20:47.487201 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7494 12:20:47.490343 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7495 12:20:47.490430 ==
7496 12:20:47.493563 Dram Type= 6, Freq= 0, CH_0, rank 0
7497 12:20:47.500127 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7498 12:20:47.500229 ==
7499 12:20:47.511704
7500 12:20:47.515105 TX Vref early break, caculate TX vref
7501 12:20:47.518349 TX Vref=16, minBit 7, minWin=22, winSum=371
7502 12:20:47.521840 TX Vref=18, minBit 0, minWin=23, winSum=380
7503 12:20:47.525401 TX Vref=20, minBit 8, minWin=23, winSum=391
7504 12:20:47.528458 TX Vref=22, minBit 8, minWin=23, winSum=391
7505 12:20:47.531596 TX Vref=24, minBit 1, minWin=24, winSum=400
7506 12:20:47.538375 TX Vref=26, minBit 9, minWin=24, winSum=410
7507 12:20:47.541876 TX Vref=28, minBit 2, minWin=25, winSum=413
7508 12:20:47.544913 TX Vref=30, minBit 0, minWin=25, winSum=407
7509 12:20:47.548941 TX Vref=32, minBit 7, minWin=23, winSum=395
7510 12:20:47.551527 TX Vref=34, minBit 1, minWin=23, winSum=389
7511 12:20:47.558301 [TxChooseVref] Worse bit 2, Min win 25, Win sum 413, Final Vref 28
7512 12:20:47.558411
7513 12:20:47.561553 Final TX Range 0 Vref 28
7514 12:20:47.561639
7515 12:20:47.561722 ==
7516 12:20:47.565071 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 12:20:47.568166 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7518 12:20:47.568262 ==
7519 12:20:47.568346
7520 12:20:47.568425
7521 12:20:47.571400 TX Vref Scan disable
7522 12:20:47.578115 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7523 12:20:47.578215 == TX Byte 0 ==
7524 12:20:47.581451 u2DelayCellOfst[0]=10 cells (3 PI)
7525 12:20:47.584792 u2DelayCellOfst[1]=14 cells (4 PI)
7526 12:20:47.588015 u2DelayCellOfst[2]=10 cells (3 PI)
7527 12:20:47.591343 u2DelayCellOfst[3]=10 cells (3 PI)
7528 12:20:47.594761 u2DelayCellOfst[4]=7 cells (2 PI)
7529 12:20:47.598187 u2DelayCellOfst[5]=0 cells (0 PI)
7530 12:20:47.601509 u2DelayCellOfst[6]=17 cells (5 PI)
7531 12:20:47.601601 u2DelayCellOfst[7]=14 cells (4 PI)
7532 12:20:47.608251 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7533 12:20:47.611490 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7534 12:20:47.611577 == TX Byte 1 ==
7535 12:20:47.614912 u2DelayCellOfst[8]=0 cells (0 PI)
7536 12:20:47.618179 u2DelayCellOfst[9]=0 cells (0 PI)
7537 12:20:47.621310 u2DelayCellOfst[10]=7 cells (2 PI)
7538 12:20:47.624613 u2DelayCellOfst[11]=0 cells (0 PI)
7539 12:20:47.628027 u2DelayCellOfst[12]=14 cells (4 PI)
7540 12:20:47.631682 u2DelayCellOfst[13]=10 cells (3 PI)
7541 12:20:47.634932 u2DelayCellOfst[14]=17 cells (5 PI)
7542 12:20:47.637871 u2DelayCellOfst[15]=10 cells (3 PI)
7543 12:20:47.641837 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7544 12:20:47.647809 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7545 12:20:47.647911 DramC Write-DBI on
7546 12:20:47.647997 ==
7547 12:20:47.651341 Dram Type= 6, Freq= 0, CH_0, rank 0
7548 12:20:47.654412 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7549 12:20:47.654501 ==
7550 12:20:47.657767
7551 12:20:47.657852
7552 12:20:47.657934 TX Vref Scan disable
7553 12:20:47.661268 == TX Byte 0 ==
7554 12:20:47.664649 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7555 12:20:47.667753 == TX Byte 1 ==
7556 12:20:47.671033 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7557 12:20:47.674316 DramC Write-DBI off
7558 12:20:47.674399
7559 12:20:47.674461 [DATLAT]
7560 12:20:47.674519 Freq=1600, CH0 RK0
7561 12:20:47.674574
7562 12:20:47.677516 DATLAT Default: 0xf
7563 12:20:47.677595 0, 0xFFFF, sum = 0
7564 12:20:47.681102 1, 0xFFFF, sum = 0
7565 12:20:47.684435 2, 0xFFFF, sum = 0
7566 12:20:47.684518 3, 0xFFFF, sum = 0
7567 12:20:47.687571 4, 0xFFFF, sum = 0
7568 12:20:47.687667 5, 0xFFFF, sum = 0
7569 12:20:47.690778 6, 0xFFFF, sum = 0
7570 12:20:47.690860 7, 0xFFFF, sum = 0
7571 12:20:47.694059 8, 0xFFFF, sum = 0
7572 12:20:47.694142 9, 0xFFFF, sum = 0
7573 12:20:47.697408 10, 0xFFFF, sum = 0
7574 12:20:47.697490 11, 0xFFFF, sum = 0
7575 12:20:47.700781 12, 0xBFF, sum = 0
7576 12:20:47.700881 13, 0x0, sum = 1
7577 12:20:47.704147 14, 0x0, sum = 2
7578 12:20:47.704258 15, 0x0, sum = 3
7579 12:20:47.707639 16, 0x0, sum = 4
7580 12:20:47.707723 best_step = 14
7581 12:20:47.707787
7582 12:20:47.707846 ==
7583 12:20:47.710728 Dram Type= 6, Freq= 0, CH_0, rank 0
7584 12:20:47.714175 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7585 12:20:47.717753 ==
7586 12:20:47.717844 RX Vref Scan: 1
7587 12:20:47.717929
7588 12:20:47.720724 Set Vref Range= 24 -> 127
7589 12:20:47.720808
7590 12:20:47.724097 RX Vref 24 -> 127, step: 1
7591 12:20:47.724187
7592 12:20:47.724272 RX Delay 11 -> 252, step: 4
7593 12:20:47.724351
7594 12:20:47.727258 Set Vref, RX VrefLevel [Byte0]: 24
7595 12:20:47.730558 [Byte1]: 24
7596 12:20:47.734383
7597 12:20:47.734474 Set Vref, RX VrefLevel [Byte0]: 25
7598 12:20:47.737593 [Byte1]: 25
7599 12:20:47.741877
7600 12:20:47.741966 Set Vref, RX VrefLevel [Byte0]: 26
7601 12:20:47.745220 [Byte1]: 26
7602 12:20:47.749562
7603 12:20:47.749650 Set Vref, RX VrefLevel [Byte0]: 27
7604 12:20:47.752729 [Byte1]: 27
7605 12:20:47.757095
7606 12:20:47.757186 Set Vref, RX VrefLevel [Byte0]: 28
7607 12:20:47.760381 [Byte1]: 28
7608 12:20:47.764764
7609 12:20:47.764853 Set Vref, RX VrefLevel [Byte0]: 29
7610 12:20:47.768108 [Byte1]: 29
7611 12:20:47.772540
7612 12:20:47.772631 Set Vref, RX VrefLevel [Byte0]: 30
7613 12:20:47.775609 [Byte1]: 30
7614 12:20:47.780057
7615 12:20:47.780152 Set Vref, RX VrefLevel [Byte0]: 31
7616 12:20:47.783319 [Byte1]: 31
7617 12:20:47.787585
7618 12:20:47.787675 Set Vref, RX VrefLevel [Byte0]: 32
7619 12:20:47.790924 [Byte1]: 32
7620 12:20:47.795371
7621 12:20:47.795461 Set Vref, RX VrefLevel [Byte0]: 33
7622 12:20:47.798513 [Byte1]: 33
7623 12:20:47.802722
7624 12:20:47.802810 Set Vref, RX VrefLevel [Byte0]: 34
7625 12:20:47.806005 [Byte1]: 34
7626 12:20:47.810372
7627 12:20:47.810462 Set Vref, RX VrefLevel [Byte0]: 35
7628 12:20:47.813748 [Byte1]: 35
7629 12:20:47.818087
7630 12:20:47.818177 Set Vref, RX VrefLevel [Byte0]: 36
7631 12:20:47.821312 [Byte1]: 36
7632 12:20:47.825625
7633 12:20:47.825714 Set Vref, RX VrefLevel [Byte0]: 37
7634 12:20:47.829088 [Byte1]: 37
7635 12:20:47.833395
7636 12:20:47.833487 Set Vref, RX VrefLevel [Byte0]: 38
7637 12:20:47.836845 [Byte1]: 38
7638 12:20:47.841213
7639 12:20:47.841302 Set Vref, RX VrefLevel [Byte0]: 39
7640 12:20:47.844155 [Byte1]: 39
7641 12:20:47.848621
7642 12:20:47.848706 Set Vref, RX VrefLevel [Byte0]: 40
7643 12:20:47.851844 [Byte1]: 40
7644 12:20:47.856107
7645 12:20:47.856218 Set Vref, RX VrefLevel [Byte0]: 41
7646 12:20:47.859707 [Byte1]: 41
7647 12:20:47.863752
7648 12:20:47.863837 Set Vref, RX VrefLevel [Byte0]: 42
7649 12:20:47.866997 [Byte1]: 42
7650 12:20:47.871251
7651 12:20:47.871396 Set Vref, RX VrefLevel [Byte0]: 43
7652 12:20:47.874558 [Byte1]: 43
7653 12:20:47.879220
7654 12:20:47.879309 Set Vref, RX VrefLevel [Byte0]: 44
7655 12:20:47.882483 [Byte1]: 44
7656 12:20:47.886560
7657 12:20:47.886648 Set Vref, RX VrefLevel [Byte0]: 45
7658 12:20:47.889965 [Byte1]: 45
7659 12:20:47.894153
7660 12:20:47.894239 Set Vref, RX VrefLevel [Byte0]: 46
7661 12:20:47.897471 [Byte1]: 46
7662 12:20:47.901842
7663 12:20:47.901928 Set Vref, RX VrefLevel [Byte0]: 47
7664 12:20:47.904962 [Byte1]: 47
7665 12:20:47.909523
7666 12:20:47.909625 Set Vref, RX VrefLevel [Byte0]: 48
7667 12:20:47.912834 [Byte1]: 48
7668 12:20:47.916895
7669 12:20:47.916983 Set Vref, RX VrefLevel [Byte0]: 49
7670 12:20:47.920166 [Byte1]: 49
7671 12:20:47.924573
7672 12:20:47.924660 Set Vref, RX VrefLevel [Byte0]: 50
7673 12:20:47.927875 [Byte1]: 50
7674 12:20:47.932221
7675 12:20:47.932342 Set Vref, RX VrefLevel [Byte0]: 51
7676 12:20:47.935518 [Byte1]: 51
7677 12:20:47.939749
7678 12:20:47.939838 Set Vref, RX VrefLevel [Byte0]: 52
7679 12:20:47.943020 [Byte1]: 52
7680 12:20:47.947683
7681 12:20:47.947774 Set Vref, RX VrefLevel [Byte0]: 53
7682 12:20:47.950844 [Byte1]: 53
7683 12:20:47.955046
7684 12:20:47.955131 Set Vref, RX VrefLevel [Byte0]: 54
7685 12:20:47.958596 [Byte1]: 54
7686 12:20:47.962911
7687 12:20:47.962998 Set Vref, RX VrefLevel [Byte0]: 55
7688 12:20:47.966254 [Byte1]: 55
7689 12:20:47.970404
7690 12:20:47.970490 Set Vref, RX VrefLevel [Byte0]: 56
7691 12:20:47.973571 [Byte1]: 56
7692 12:20:47.977785
7693 12:20:47.977870 Set Vref, RX VrefLevel [Byte0]: 57
7694 12:20:47.981093 [Byte1]: 57
7695 12:20:47.985375
7696 12:20:47.985455 Set Vref, RX VrefLevel [Byte0]: 58
7697 12:20:47.988732 [Byte1]: 58
7698 12:20:47.993113
7699 12:20:47.993199 Set Vref, RX VrefLevel [Byte0]: 59
7700 12:20:47.996297 [Byte1]: 59
7701 12:20:48.000815
7702 12:20:48.000901 Set Vref, RX VrefLevel [Byte0]: 60
7703 12:20:48.004063 [Byte1]: 60
7704 12:20:48.008194
7705 12:20:48.008293 Set Vref, RX VrefLevel [Byte0]: 61
7706 12:20:48.011537 [Byte1]: 61
7707 12:20:48.016030
7708 12:20:48.016115 Set Vref, RX VrefLevel [Byte0]: 62
7709 12:20:48.019289 [Byte1]: 62
7710 12:20:48.023764
7711 12:20:48.023852 Set Vref, RX VrefLevel [Byte0]: 63
7712 12:20:48.026897 [Byte1]: 63
7713 12:20:48.031157
7714 12:20:48.031247 Set Vref, RX VrefLevel [Byte0]: 64
7715 12:20:48.034500 [Byte1]: 64
7716 12:20:48.038906
7717 12:20:48.038999 Set Vref, RX VrefLevel [Byte0]: 65
7718 12:20:48.042337 [Byte1]: 65
7719 12:20:48.046759
7720 12:20:48.046846 Set Vref, RX VrefLevel [Byte0]: 66
7721 12:20:48.049718 [Byte1]: 66
7722 12:20:48.053975
7723 12:20:48.054064 Set Vref, RX VrefLevel [Byte0]: 67
7724 12:20:48.057240 [Byte1]: 67
7725 12:20:48.061716
7726 12:20:48.061804 Set Vref, RX VrefLevel [Byte0]: 68
7727 12:20:48.065176 [Byte1]: 68
7728 12:20:48.069250
7729 12:20:48.069337 Set Vref, RX VrefLevel [Byte0]: 69
7730 12:20:48.072719 [Byte1]: 69
7731 12:20:48.076980
7732 12:20:48.077065 Set Vref, RX VrefLevel [Byte0]: 70
7733 12:20:48.080130 [Byte1]: 70
7734 12:20:48.084506
7735 12:20:48.084595 Set Vref, RX VrefLevel [Byte0]: 71
7736 12:20:48.087817 [Byte1]: 71
7737 12:20:48.092029
7738 12:20:48.092116 Final RX Vref Byte 0 = 51 to rank0
7739 12:20:48.095361 Final RX Vref Byte 1 = 57 to rank0
7740 12:20:48.098687 Final RX Vref Byte 0 = 51 to rank1
7741 12:20:48.102076 Final RX Vref Byte 1 = 57 to rank1==
7742 12:20:48.105235 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 12:20:48.112048 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7744 12:20:48.112145 ==
7745 12:20:48.112266 DQS Delay:
7746 12:20:48.115210 DQS0 = 0, DQS1 = 0
7747 12:20:48.115305 DQM Delay:
7748 12:20:48.115367 DQM0 = 127, DQM1 = 121
7749 12:20:48.118500 DQ Delay:
7750 12:20:48.121945 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7751 12:20:48.125309 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7752 12:20:48.128402 DQ8 =110, DQ9 =104, DQ10 =122, DQ11 =112
7753 12:20:48.131700 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7754 12:20:48.131787
7755 12:20:48.131851
7756 12:20:48.131909
7757 12:20:48.134907 [DramC_TX_OE_Calibration] TA2
7758 12:20:48.138247 Original DQ_B0 (3 6) =30, OEN = 27
7759 12:20:48.141667 Original DQ_B1 (3 6) =30, OEN = 27
7760 12:20:48.145115 24, 0x0, End_B0=24 End_B1=24
7761 12:20:48.145200 25, 0x0, End_B0=25 End_B1=25
7762 12:20:48.148295 26, 0x0, End_B0=26 End_B1=26
7763 12:20:48.151631 27, 0x0, End_B0=27 End_B1=27
7764 12:20:48.155027 28, 0x0, End_B0=28 End_B1=28
7765 12:20:48.158590 29, 0x0, End_B0=29 End_B1=29
7766 12:20:48.158674 30, 0x0, End_B0=30 End_B1=30
7767 12:20:48.161775 31, 0x5151, End_B0=30 End_B1=30
7768 12:20:48.164962 Byte0 end_step=30 best_step=27
7769 12:20:48.168413 Byte1 end_step=30 best_step=27
7770 12:20:48.171578 Byte0 TX OE(2T, 0.5T) = (3, 3)
7771 12:20:48.175053 Byte1 TX OE(2T, 0.5T) = (3, 3)
7772 12:20:48.175139
7773 12:20:48.175202
7774 12:20:48.181553 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7775 12:20:48.184914 CH0 RK0: MR19=303, MR18=1F1F
7776 12:20:48.191543 CH0_RK0: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
7777 12:20:48.191644
7778 12:20:48.194840 ----->DramcWriteLeveling(PI) begin...
7779 12:20:48.194924 ==
7780 12:20:48.198037 Dram Type= 6, Freq= 0, CH_0, rank 1
7781 12:20:48.201569 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7782 12:20:48.201657 ==
7783 12:20:48.204787 Write leveling (Byte 0): 29 => 29
7784 12:20:48.208140 Write leveling (Byte 1): 27 => 27
7785 12:20:48.211416 DramcWriteLeveling(PI) end<-----
7786 12:20:48.211502
7787 12:20:48.211566 ==
7788 12:20:48.214583 Dram Type= 6, Freq= 0, CH_0, rank 1
7789 12:20:48.218184 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7790 12:20:48.218269 ==
7791 12:20:48.221518 [Gating] SW mode calibration
7792 12:20:48.228064 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7793 12:20:48.234879 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7794 12:20:48.238169 0 12 0 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7795 12:20:48.241372 0 12 4 | B1->B0 | 2524 3434 | 1 1 | (1 1) (1 1)
7796 12:20:48.248104 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7797 12:20:48.251098 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7798 12:20:48.254692 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7799 12:20:48.261260 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7800 12:20:48.264747 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7801 12:20:48.267828 0 12 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7802 12:20:48.274743 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7803 12:20:48.277814 0 13 4 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
7804 12:20:48.281077 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7805 12:20:48.287769 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7806 12:20:48.291152 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7807 12:20:48.294697 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7808 12:20:48.301112 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7809 12:20:48.304261 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7810 12:20:48.307394 0 14 0 | B1->B0 | 2424 4141 | 0 1 | (0 0) (0 0)
7811 12:20:48.314110 0 14 4 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
7812 12:20:48.317589 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7813 12:20:48.320822 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7814 12:20:48.327364 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 12:20:48.330767 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7816 12:20:48.333991 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7817 12:20:48.340756 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7818 12:20:48.343888 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7819 12:20:48.347256 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7820 12:20:48.353880 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 12:20:48.357157 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 12:20:48.360588 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 12:20:48.367118 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 12:20:48.370432 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 12:20:48.373782 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 12:20:48.380753 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 12:20:48.383729 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 12:20:48.387019 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7829 12:20:48.393628 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7830 12:20:48.396979 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 12:20:48.400396 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7832 12:20:48.406914 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7833 12:20:48.410765 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7834 12:20:48.413704 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7835 12:20:48.420215 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7836 12:20:48.420358 Total UI for P1: 0, mck2ui 16
7837 12:20:48.426900 best dqsien dly found for B0: ( 1, 0, 30)
7838 12:20:48.430031 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7839 12:20:48.433515 Total UI for P1: 0, mck2ui 16
7840 12:20:48.436809 best dqsien dly found for B1: ( 1, 1, 2)
7841 12:20:48.440289 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7842 12:20:48.443354 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7843 12:20:48.443462
7844 12:20:48.446671 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7845 12:20:48.449965 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7846 12:20:48.453240 [Gating] SW calibration Done
7847 12:20:48.453349 ==
7848 12:20:48.456784 Dram Type= 6, Freq= 0, CH_0, rank 1
7849 12:20:48.460031 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7850 12:20:48.460138 ==
7851 12:20:48.463193 RX Vref Scan: 0
7852 12:20:48.463295
7853 12:20:48.466405 RX Vref 0 -> 0, step: 1
7854 12:20:48.466509
7855 12:20:48.466599 RX Delay 0 -> 252, step: 8
7856 12:20:48.472980 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7857 12:20:48.476408 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7858 12:20:48.479688 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7859 12:20:48.483101 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7860 12:20:48.486192 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7861 12:20:48.492898 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7862 12:20:48.496395 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7863 12:20:48.499678 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7864 12:20:48.503294 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7865 12:20:48.506255 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7866 12:20:48.513360 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7867 12:20:48.516193 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7868 12:20:48.519694 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7869 12:20:48.522846 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7870 12:20:48.526248 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7871 12:20:48.532889 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7872 12:20:48.533024 ==
7873 12:20:48.536032 Dram Type= 6, Freq= 0, CH_0, rank 1
7874 12:20:48.539560 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7875 12:20:48.539672 ==
7876 12:20:48.539764 DQS Delay:
7877 12:20:48.542849 DQS0 = 0, DQS1 = 0
7878 12:20:48.542953 DQM Delay:
7879 12:20:48.546346 DQM0 = 131, DQM1 = 125
7880 12:20:48.546450 DQ Delay:
7881 12:20:48.549471 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7882 12:20:48.552744 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7883 12:20:48.556294 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7884 12:20:48.559368 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7885 12:20:48.559475
7886 12:20:48.562910
7887 12:20:48.563017 ==
7888 12:20:48.565930 Dram Type= 6, Freq= 0, CH_0, rank 1
7889 12:20:48.569432 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7890 12:20:48.569539 ==
7891 12:20:48.569629
7892 12:20:48.569715
7893 12:20:48.572510 TX Vref Scan disable
7894 12:20:48.572614 == TX Byte 0 ==
7895 12:20:48.579213 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7896 12:20:48.582535 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7897 12:20:48.582648 == TX Byte 1 ==
7898 12:20:48.589278 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7899 12:20:48.592653 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7900 12:20:48.592768 ==
7901 12:20:48.596231 Dram Type= 6, Freq= 0, CH_0, rank 1
7902 12:20:48.599009 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7903 12:20:48.599115 ==
7904 12:20:48.613908
7905 12:20:48.616814 TX Vref early break, caculate TX vref
7906 12:20:48.620260 TX Vref=16, minBit 1, minWin=22, winSum=366
7907 12:20:48.623664 TX Vref=18, minBit 1, minWin=22, winSum=379
7908 12:20:48.626924 TX Vref=20, minBit 1, minWin=23, winSum=386
7909 12:20:48.630256 TX Vref=22, minBit 1, minWin=23, winSum=394
7910 12:20:48.633367 TX Vref=24, minBit 8, minWin=23, winSum=397
7911 12:20:48.639971 TX Vref=26, minBit 1, minWin=23, winSum=404
7912 12:20:48.643494 TX Vref=28, minBit 1, minWin=24, winSum=407
7913 12:20:48.646986 TX Vref=30, minBit 0, minWin=24, winSum=405
7914 12:20:48.650182 TX Vref=32, minBit 1, minWin=23, winSum=395
7915 12:20:48.653399 TX Vref=34, minBit 1, minWin=23, winSum=392
7916 12:20:48.656828 TX Vref=36, minBit 7, minWin=22, winSum=379
7917 12:20:48.663558 [TxChooseVref] Worse bit 1, Min win 24, Win sum 407, Final Vref 28
7918 12:20:48.663691
7919 12:20:48.666820 Final TX Range 0 Vref 28
7920 12:20:48.666931
7921 12:20:48.667023 ==
7922 12:20:48.670090 Dram Type= 6, Freq= 0, CH_0, rank 1
7923 12:20:48.673395 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7924 12:20:48.673503 ==
7925 12:20:48.673595
7926 12:20:48.673683
7927 12:20:48.676626 TX Vref Scan disable
7928 12:20:48.683303 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7929 12:20:48.683431 == TX Byte 0 ==
7930 12:20:48.686760 u2DelayCellOfst[0]=10 cells (3 PI)
7931 12:20:48.689994 u2DelayCellOfst[1]=14 cells (4 PI)
7932 12:20:48.693225 u2DelayCellOfst[2]=14 cells (4 PI)
7933 12:20:48.696499 u2DelayCellOfst[3]=14 cells (4 PI)
7934 12:20:48.699785 u2DelayCellOfst[4]=7 cells (2 PI)
7935 12:20:48.703312 u2DelayCellOfst[5]=0 cells (0 PI)
7936 12:20:48.706649 u2DelayCellOfst[6]=17 cells (5 PI)
7937 12:20:48.709839 u2DelayCellOfst[7]=17 cells (5 PI)
7938 12:20:48.713266 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7939 12:20:48.716552 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7940 12:20:48.719817 == TX Byte 1 ==
7941 12:20:48.723192 u2DelayCellOfst[8]=0 cells (0 PI)
7942 12:20:48.726285 u2DelayCellOfst[9]=0 cells (0 PI)
7943 12:20:48.726373 u2DelayCellOfst[10]=10 cells (3 PI)
7944 12:20:48.729633 u2DelayCellOfst[11]=3 cells (1 PI)
7945 12:20:48.732975 u2DelayCellOfst[12]=14 cells (4 PI)
7946 12:20:48.736321 u2DelayCellOfst[13]=14 cells (4 PI)
7947 12:20:48.739540 u2DelayCellOfst[14]=17 cells (5 PI)
7948 12:20:48.743222 u2DelayCellOfst[15]=14 cells (4 PI)
7949 12:20:48.749612 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7950 12:20:48.753009 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7951 12:20:48.753104 DramC Write-DBI on
7952 12:20:48.753168 ==
7953 12:20:48.756089 Dram Type= 6, Freq= 0, CH_0, rank 1
7954 12:20:48.762712 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7955 12:20:48.762840 ==
7956 12:20:48.762937
7957 12:20:48.763025
7958 12:20:48.763112 TX Vref Scan disable
7959 12:20:48.766801 == TX Byte 0 ==
7960 12:20:48.770367 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7961 12:20:48.773452 == TX Byte 1 ==
7962 12:20:48.776865 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7963 12:20:48.780011 DramC Write-DBI off
7964 12:20:48.780095
7965 12:20:48.780159 [DATLAT]
7966 12:20:48.780264 Freq=1600, CH0 RK1
7967 12:20:48.780324
7968 12:20:48.783462 DATLAT Default: 0xe
7969 12:20:48.786795 0, 0xFFFF, sum = 0
7970 12:20:48.786880 1, 0xFFFF, sum = 0
7971 12:20:48.790249 2, 0xFFFF, sum = 0
7972 12:20:48.790334 3, 0xFFFF, sum = 0
7973 12:20:48.793556 4, 0xFFFF, sum = 0
7974 12:20:48.793640 5, 0xFFFF, sum = 0
7975 12:20:48.796838 6, 0xFFFF, sum = 0
7976 12:20:48.796921 7, 0xFFFF, sum = 0
7977 12:20:48.799988 8, 0xFFFF, sum = 0
7978 12:20:48.800071 9, 0xFFFF, sum = 0
7979 12:20:48.803202 10, 0xFFFF, sum = 0
7980 12:20:48.803286 11, 0xFFFF, sum = 0
7981 12:20:48.806714 12, 0x8FFF, sum = 0
7982 12:20:48.806798 13, 0x0, sum = 1
7983 12:20:48.809922 14, 0x0, sum = 2
7984 12:20:48.810007 15, 0x0, sum = 3
7985 12:20:48.813238 16, 0x0, sum = 4
7986 12:20:48.813323 best_step = 14
7987 12:20:48.813387
7988 12:20:48.813446 ==
7989 12:20:48.816956 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 12:20:48.819839 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7991 12:20:48.823145 ==
7992 12:20:48.823230 RX Vref Scan: 0
7993 12:20:48.823294
7994 12:20:48.826384 RX Vref 0 -> 0, step: 1
7995 12:20:48.826468
7996 12:20:48.829786 RX Delay 11 -> 252, step: 4
7997 12:20:48.833319 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7998 12:20:48.836409 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7999 12:20:48.839683 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8000 12:20:48.846333 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8001 12:20:48.849782 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8002 12:20:48.852859 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8003 12:20:48.856132 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8004 12:20:48.859659 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8005 12:20:48.866162 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8006 12:20:48.869536 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8007 12:20:48.873029 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8008 12:20:48.876191 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8009 12:20:48.879473 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8010 12:20:48.886501 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8011 12:20:48.889573 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8012 12:20:48.892777 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8013 12:20:48.892893 ==
8014 12:20:48.896084 Dram Type= 6, Freq= 0, CH_0, rank 1
8015 12:20:48.899352 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8016 12:20:48.899460 ==
8017 12:20:48.902680 DQS Delay:
8018 12:20:48.902786 DQS0 = 0, DQS1 = 0
8019 12:20:48.906075 DQM Delay:
8020 12:20:48.906180 DQM0 = 128, DQM1 = 120
8021 12:20:48.909404 DQ Delay:
8022 12:20:48.912572 DQ0 =122, DQ1 =132, DQ2 =126, DQ3 =124
8023 12:20:48.915980 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138
8024 12:20:48.919649 DQ8 =110, DQ9 =106, DQ10 =122, DQ11 =112
8025 12:20:48.922573 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
8026 12:20:48.922690
8027 12:20:48.922785
8028 12:20:48.922873
8029 12:20:48.925834 [DramC_TX_OE_Calibration] TA2
8030 12:20:48.929301 Original DQ_B0 (3 6) =30, OEN = 27
8031 12:20:48.932659 Original DQ_B1 (3 6) =30, OEN = 27
8032 12:20:48.932778 24, 0x0, End_B0=24 End_B1=24
8033 12:20:48.935866 25, 0x0, End_B0=25 End_B1=25
8034 12:20:48.939283 26, 0x0, End_B0=26 End_B1=26
8035 12:20:48.942685 27, 0x0, End_B0=27 End_B1=27
8036 12:20:48.945934 28, 0x0, End_B0=28 End_B1=28
8037 12:20:48.946048 29, 0x0, End_B0=29 End_B1=29
8038 12:20:48.949372 30, 0x0, End_B0=30 End_B1=30
8039 12:20:48.952674 31, 0x5151, End_B0=30 End_B1=30
8040 12:20:48.956140 Byte0 end_step=30 best_step=27
8041 12:20:48.959520 Byte1 end_step=30 best_step=27
8042 12:20:48.959632 Byte0 TX OE(2T, 0.5T) = (3, 3)
8043 12:20:48.962484 Byte1 TX OE(2T, 0.5T) = (3, 3)
8044 12:20:48.962591
8045 12:20:48.962682
8046 12:20:48.972491 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8047 12:20:48.975918 CH0 RK1: MR19=303, MR18=2121
8048 12:20:48.979048 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
8049 12:20:48.982939 [RxdqsGatingPostProcess] freq 1600
8050 12:20:48.989205 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8051 12:20:48.992483 Pre-setting of DQS Precalculation
8052 12:20:48.995916 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8053 12:20:48.999100 ==
8054 12:20:49.002369 Dram Type= 6, Freq= 0, CH_1, rank 0
8055 12:20:49.005851 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8056 12:20:49.005962 ==
8057 12:20:49.008977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8058 12:20:49.015608 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8059 12:20:49.018716 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8060 12:20:49.025293 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8061 12:20:49.033228 [CA 0] Center 42 (12~72) winsize 61
8062 12:20:49.036165 [CA 1] Center 41 (11~72) winsize 62
8063 12:20:49.039543 [CA 2] Center 37 (7~67) winsize 61
8064 12:20:49.042861 [CA 3] Center 36 (7~66) winsize 60
8065 12:20:49.046187 [CA 4] Center 34 (4~64) winsize 61
8066 12:20:49.050031 [CA 5] Center 34 (5~64) winsize 60
8067 12:20:49.050143
8068 12:20:49.053099 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8069 12:20:49.053205
8070 12:20:49.056069 [CATrainingPosCal] consider 1 rank data
8071 12:20:49.059333 u2DelayCellTimex100 = 275/100 ps
8072 12:20:49.062782 CA0 delay=42 (12~72),Diff = 8 PI (28 cell)
8073 12:20:49.069295 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
8074 12:20:49.072801 CA2 delay=37 (7~67),Diff = 3 PI (10 cell)
8075 12:20:49.076205 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8076 12:20:49.079260 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8077 12:20:49.082498 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8078 12:20:49.082609
8079 12:20:49.086033 CA PerBit enable=1, Macro0, CA PI delay=34
8080 12:20:49.086137
8081 12:20:49.089474 [CBTSetCACLKResult] CA Dly = 34
8082 12:20:49.092529 CS Dly: 8 (0~39)
8083 12:20:49.096170 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8084 12:20:49.098955 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8085 12:20:49.099061 ==
8086 12:20:49.102444 Dram Type= 6, Freq= 0, CH_1, rank 1
8087 12:20:49.109200 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8088 12:20:49.109317 ==
8089 12:20:49.112572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8090 12:20:49.116008 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8091 12:20:49.122341 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8092 12:20:49.128856 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8093 12:20:49.135374 [CA 0] Center 40 (10~70) winsize 61
8094 12:20:49.138629 [CA 1] Center 39 (9~70) winsize 62
8095 12:20:49.141892 [CA 2] Center 35 (6~65) winsize 60
8096 12:20:49.145282 [CA 3] Center 35 (6~64) winsize 59
8097 12:20:49.148986 [CA 4] Center 33 (4~63) winsize 60
8098 12:20:49.151808 [CA 5] Center 33 (4~63) winsize 60
8099 12:20:49.151895
8100 12:20:49.155281 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8101 12:20:49.155380
8102 12:20:49.158781 [CATrainingPosCal] consider 2 rank data
8103 12:20:49.161860 u2DelayCellTimex100 = 275/100 ps
8104 12:20:49.165156 CA0 delay=41 (12~70),Diff = 8 PI (28 cell)
8105 12:20:49.171946 CA1 delay=40 (11~70),Diff = 7 PI (24 cell)
8106 12:20:49.175105 CA2 delay=36 (7~65),Diff = 3 PI (10 cell)
8107 12:20:49.178248 CA3 delay=35 (7~64),Diff = 2 PI (7 cell)
8108 12:20:49.181742 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8109 12:20:49.184945 CA5 delay=34 (5~63),Diff = 1 PI (3 cell)
8110 12:20:49.185032
8111 12:20:49.188475 CA PerBit enable=1, Macro0, CA PI delay=33
8112 12:20:49.188558
8113 12:20:49.191841 [CBTSetCACLKResult] CA Dly = 33
8114 12:20:49.194870 CS Dly: 9 (0~41)
8115 12:20:49.198032 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8116 12:20:49.201484 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8117 12:20:49.201567
8118 12:20:49.204792 ----->DramcWriteLeveling(PI) begin...
8119 12:20:49.204875 ==
8120 12:20:49.208311 Dram Type= 6, Freq= 0, CH_1, rank 0
8121 12:20:49.211562 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8122 12:20:49.214927 ==
8123 12:20:49.218203 Write leveling (Byte 0): 23 => 23
8124 12:20:49.218288 Write leveling (Byte 1): 22 => 22
8125 12:20:49.221507 DramcWriteLeveling(PI) end<-----
8126 12:20:49.221590
8127 12:20:49.221655 ==
8128 12:20:49.224827 Dram Type= 6, Freq= 0, CH_1, rank 0
8129 12:20:49.231515 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8130 12:20:49.231611 ==
8131 12:20:49.235077 [Gating] SW mode calibration
8132 12:20:49.241462 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8133 12:20:49.244708 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8134 12:20:49.251772 0 12 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
8135 12:20:49.254681 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8136 12:20:49.257943 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8137 12:20:49.264635 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8138 12:20:49.267980 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8139 12:20:49.271188 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8140 12:20:49.277902 0 12 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8141 12:20:49.281271 0 12 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8142 12:20:49.284470 0 13 0 | B1->B0 | 3131 2323 | 1 0 | (1 0) (1 0)
8143 12:20:49.291093 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8144 12:20:49.294711 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8145 12:20:49.297641 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8146 12:20:49.304416 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8147 12:20:49.307540 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8148 12:20:49.311187 0 13 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8149 12:20:49.317397 0 13 28 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
8150 12:20:49.320921 0 14 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8151 12:20:49.324375 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8152 12:20:49.327442 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 12:20:49.334056 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 12:20:49.337564 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8155 12:20:49.340963 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 12:20:49.347363 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8157 12:20:49.350656 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8158 12:20:49.353967 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8159 12:20:49.360685 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8160 12:20:49.363964 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 12:20:49.367441 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 12:20:49.373911 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 12:20:49.377493 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 12:20:49.380495 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 12:20:49.387055 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 12:20:49.390445 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8167 12:20:49.393776 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8168 12:20:49.400384 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8169 12:20:49.403822 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 12:20:49.407004 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 12:20:49.413834 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8172 12:20:49.417118 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8173 12:20:49.420272 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8174 12:20:49.427080 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8175 12:20:49.430395 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8176 12:20:49.433822 Total UI for P1: 0, mck2ui 16
8177 12:20:49.436924 best dqsien dly found for B0: ( 1, 0, 30)
8178 12:20:49.440617 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8179 12:20:49.443712 Total UI for P1: 0, mck2ui 16
8180 12:20:49.447418 best dqsien dly found for B1: ( 1, 1, 4)
8181 12:20:49.450243 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
8182 12:20:49.453510 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8183 12:20:49.453621
8184 12:20:49.456940 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
8185 12:20:49.463581 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8186 12:20:49.463709 [Gating] SW calibration Done
8187 12:20:49.463806 ==
8188 12:20:49.466929 Dram Type= 6, Freq= 0, CH_1, rank 0
8189 12:20:49.473634 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8190 12:20:49.473763 ==
8191 12:20:49.473858 RX Vref Scan: 0
8192 12:20:49.473945
8193 12:20:49.476993 RX Vref 0 -> 0, step: 1
8194 12:20:49.477099
8195 12:20:49.479990 RX Delay 0 -> 252, step: 8
8196 12:20:49.483422 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8197 12:20:49.486726 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8198 12:20:49.490120 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8199 12:20:49.496493 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8200 12:20:49.499769 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8201 12:20:49.503489 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8202 12:20:49.506507 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8203 12:20:49.509700 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8204 12:20:49.516292 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8205 12:20:49.519882 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8206 12:20:49.523271 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8207 12:20:49.526491 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8208 12:20:49.529695 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8209 12:20:49.536400 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8210 12:20:49.540080 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8211 12:20:49.542954 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8212 12:20:49.543063 ==
8213 12:20:49.546166 Dram Type= 6, Freq= 0, CH_1, rank 0
8214 12:20:49.549604 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8215 12:20:49.549711 ==
8216 12:20:49.552918 DQS Delay:
8217 12:20:49.553021 DQS0 = 0, DQS1 = 0
8218 12:20:49.556485 DQM Delay:
8219 12:20:49.556588 DQM0 = 130, DQM1 = 125
8220 12:20:49.559621 DQ Delay:
8221 12:20:49.562750 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8222 12:20:49.566465 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8223 12:20:49.569470 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8224 12:20:49.572721 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8225 12:20:49.572828
8226 12:20:49.572918
8227 12:20:49.573006 ==
8228 12:20:49.576212 Dram Type= 6, Freq= 0, CH_1, rank 0
8229 12:20:49.579304 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8230 12:20:49.579408 ==
8231 12:20:49.579499
8232 12:20:49.582648
8233 12:20:49.582752 TX Vref Scan disable
8234 12:20:49.585935 == TX Byte 0 ==
8235 12:20:49.589132 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8236 12:20:49.593002 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8237 12:20:49.595799 == TX Byte 1 ==
8238 12:20:49.599268 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8239 12:20:49.602489 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8240 12:20:49.602596 ==
8241 12:20:49.605667 Dram Type= 6, Freq= 0, CH_1, rank 0
8242 12:20:49.612389 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8243 12:20:49.612513 ==
8244 12:20:49.623335
8245 12:20:49.626567 TX Vref early break, caculate TX vref
8246 12:20:49.630391 TX Vref=16, minBit 3, minWin=21, winSum=366
8247 12:20:49.633393 TX Vref=18, minBit 3, minWin=22, winSum=377
8248 12:20:49.636673 TX Vref=20, minBit 3, minWin=22, winSum=386
8249 12:20:49.640443 TX Vref=22, minBit 3, minWin=22, winSum=392
8250 12:20:49.643227 TX Vref=24, minBit 0, minWin=24, winSum=402
8251 12:20:49.649803 TX Vref=26, minBit 3, minWin=24, winSum=408
8252 12:20:49.653171 TX Vref=28, minBit 0, minWin=25, winSum=411
8253 12:20:49.656472 TX Vref=30, minBit 3, minWin=24, winSum=405
8254 12:20:49.659707 TX Vref=32, minBit 3, minWin=23, winSum=395
8255 12:20:49.663037 TX Vref=34, minBit 2, minWin=23, winSum=389
8256 12:20:49.669589 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 28
8257 12:20:49.669715
8258 12:20:49.672935 Final TX Range 0 Vref 28
8259 12:20:49.673046
8260 12:20:49.673137 ==
8261 12:20:49.676257 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 12:20:49.679710 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8263 12:20:49.679821 ==
8264 12:20:49.679914
8265 12:20:49.680001
8266 12:20:49.682861 TX Vref Scan disable
8267 12:20:49.689495 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8268 12:20:49.689615 == TX Byte 0 ==
8269 12:20:49.692887 u2DelayCellOfst[0]=14 cells (4 PI)
8270 12:20:49.696266 u2DelayCellOfst[1]=10 cells (3 PI)
8271 12:20:49.699500 u2DelayCellOfst[2]=0 cells (0 PI)
8272 12:20:49.702970 u2DelayCellOfst[3]=7 cells (2 PI)
8273 12:20:49.706237 u2DelayCellOfst[4]=7 cells (2 PI)
8274 12:20:49.709347 u2DelayCellOfst[5]=14 cells (4 PI)
8275 12:20:49.712811 u2DelayCellOfst[6]=14 cells (4 PI)
8276 12:20:49.716117 u2DelayCellOfst[7]=7 cells (2 PI)
8277 12:20:49.719295 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8278 12:20:49.722673 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8279 12:20:49.725950 == TX Byte 1 ==
8280 12:20:49.726059 u2DelayCellOfst[8]=0 cells (0 PI)
8281 12:20:49.729554 u2DelayCellOfst[9]=7 cells (2 PI)
8282 12:20:49.732641 u2DelayCellOfst[10]=10 cells (3 PI)
8283 12:20:49.735720 u2DelayCellOfst[11]=3 cells (1 PI)
8284 12:20:49.739200 u2DelayCellOfst[12]=17 cells (5 PI)
8285 12:20:49.742532 u2DelayCellOfst[13]=21 cells (6 PI)
8286 12:20:49.745662 u2DelayCellOfst[14]=17 cells (5 PI)
8287 12:20:49.748996 u2DelayCellOfst[15]=21 cells (6 PI)
8288 12:20:49.752466 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8289 12:20:49.758997 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8290 12:20:49.759128 DramC Write-DBI on
8291 12:20:49.759224 ==
8292 12:20:49.762321 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 12:20:49.768713 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8294 12:20:49.768836 ==
8295 12:20:49.768931
8296 12:20:49.769018
8297 12:20:49.769104 TX Vref Scan disable
8298 12:20:49.772362 == TX Byte 0 ==
8299 12:20:49.775722 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8300 12:20:49.779020 == TX Byte 1 ==
8301 12:20:49.782281 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8302 12:20:49.785785 DramC Write-DBI off
8303 12:20:49.785897
8304 12:20:49.785990 [DATLAT]
8305 12:20:49.786078 Freq=1600, CH1 RK0
8306 12:20:49.786168
8307 12:20:49.789041 DATLAT Default: 0xf
8308 12:20:49.792322 0, 0xFFFF, sum = 0
8309 12:20:49.792430 1, 0xFFFF, sum = 0
8310 12:20:49.795553 2, 0xFFFF, sum = 0
8311 12:20:49.795660 3, 0xFFFF, sum = 0
8312 12:20:49.799075 4, 0xFFFF, sum = 0
8313 12:20:49.799183 5, 0xFFFF, sum = 0
8314 12:20:49.802123 6, 0xFFFF, sum = 0
8315 12:20:49.802232 7, 0xFFFF, sum = 0
8316 12:20:49.805512 8, 0xFFFF, sum = 0
8317 12:20:49.805617 9, 0xFFFF, sum = 0
8318 12:20:49.808750 10, 0xFFFF, sum = 0
8319 12:20:49.808860 11, 0xFFFF, sum = 0
8320 12:20:49.812304 12, 0xF7F, sum = 0
8321 12:20:49.812409 13, 0x0, sum = 1
8322 12:20:49.815304 14, 0x0, sum = 2
8323 12:20:49.815410 15, 0x0, sum = 3
8324 12:20:49.818760 16, 0x0, sum = 4
8325 12:20:49.818867 best_step = 14
8326 12:20:49.818961
8327 12:20:49.819049 ==
8328 12:20:49.822168 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 12:20:49.825447 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8330 12:20:49.828568 ==
8331 12:20:49.828673 RX Vref Scan: 1
8332 12:20:49.828763
8333 12:20:49.831909 Set Vref Range= 24 -> 127
8334 12:20:49.832010
8335 12:20:49.835263 RX Vref 24 -> 127, step: 1
8336 12:20:49.835371
8337 12:20:49.835463 RX Delay 3 -> 252, step: 4
8338 12:20:49.835551
8339 12:20:49.838822 Set Vref, RX VrefLevel [Byte0]: 24
8340 12:20:49.841948 [Byte1]: 24
8341 12:20:49.845557
8342 12:20:49.845662 Set Vref, RX VrefLevel [Byte0]: 25
8343 12:20:49.849011 [Byte1]: 25
8344 12:20:49.853417
8345 12:20:49.853526 Set Vref, RX VrefLevel [Byte0]: 26
8346 12:20:49.856977 [Byte1]: 26
8347 12:20:49.861060
8348 12:20:49.861168 Set Vref, RX VrefLevel [Byte0]: 27
8349 12:20:49.864373 [Byte1]: 27
8350 12:20:49.868674
8351 12:20:49.868785 Set Vref, RX VrefLevel [Byte0]: 28
8352 12:20:49.871975 [Byte1]: 28
8353 12:20:49.876327
8354 12:20:49.876436 Set Vref, RX VrefLevel [Byte0]: 29
8355 12:20:49.879640 [Byte1]: 29
8356 12:20:49.883976
8357 12:20:49.884088 Set Vref, RX VrefLevel [Byte0]: 30
8358 12:20:49.887465 [Byte1]: 30
8359 12:20:49.891691
8360 12:20:49.891812 Set Vref, RX VrefLevel [Byte0]: 31
8361 12:20:49.895026 [Byte1]: 31
8362 12:20:49.899245
8363 12:20:49.899354 Set Vref, RX VrefLevel [Byte0]: 32
8364 12:20:49.902713 [Byte1]: 32
8365 12:20:49.906987
8366 12:20:49.907097 Set Vref, RX VrefLevel [Byte0]: 33
8367 12:20:49.910161 [Byte1]: 33
8368 12:20:49.915123
8369 12:20:49.915234 Set Vref, RX VrefLevel [Byte0]: 34
8370 12:20:49.917866 [Byte1]: 34
8371 12:20:49.922175
8372 12:20:49.922283 Set Vref, RX VrefLevel [Byte0]: 35
8373 12:20:49.925451 [Byte1]: 35
8374 12:20:49.929931
8375 12:20:49.930040 Set Vref, RX VrefLevel [Byte0]: 36
8376 12:20:49.933391 [Byte1]: 36
8377 12:20:49.937636
8378 12:20:49.937756 Set Vref, RX VrefLevel [Byte0]: 37
8379 12:20:49.940899 [Byte1]: 37
8380 12:20:49.945222
8381 12:20:49.945331 Set Vref, RX VrefLevel [Byte0]: 38
8382 12:20:49.948677 [Byte1]: 38
8383 12:20:49.952728
8384 12:20:49.952835 Set Vref, RX VrefLevel [Byte0]: 39
8385 12:20:49.956039 [Byte1]: 39
8386 12:20:49.960476
8387 12:20:49.960583 Set Vref, RX VrefLevel [Byte0]: 40
8388 12:20:49.963660 [Byte1]: 40
8389 12:20:49.968196
8390 12:20:49.968304 Set Vref, RX VrefLevel [Byte0]: 41
8391 12:20:49.971494 [Byte1]: 41
8392 12:20:49.975726
8393 12:20:49.975836 Set Vref, RX VrefLevel [Byte0]: 42
8394 12:20:49.978989 [Byte1]: 42
8395 12:20:49.983554
8396 12:20:49.983664 Set Vref, RX VrefLevel [Byte0]: 43
8397 12:20:49.986764 [Byte1]: 43
8398 12:20:49.991142
8399 12:20:49.991251 Set Vref, RX VrefLevel [Byte0]: 44
8400 12:20:49.994575 [Byte1]: 44
8401 12:20:49.998750
8402 12:20:49.998857 Set Vref, RX VrefLevel [Byte0]: 45
8403 12:20:50.002176 [Byte1]: 45
8404 12:20:50.006638
8405 12:20:50.006723 Set Vref, RX VrefLevel [Byte0]: 46
8406 12:20:50.012859 [Byte1]: 46
8407 12:20:50.012952
8408 12:20:50.016516 Set Vref, RX VrefLevel [Byte0]: 47
8409 12:20:50.019583 [Byte1]: 47
8410 12:20:50.019666
8411 12:20:50.023022 Set Vref, RX VrefLevel [Byte0]: 48
8412 12:20:50.026117 [Byte1]: 48
8413 12:20:50.029373
8414 12:20:50.029455 Set Vref, RX VrefLevel [Byte0]: 49
8415 12:20:50.032651 [Byte1]: 49
8416 12:20:50.037025
8417 12:20:50.037123 Set Vref, RX VrefLevel [Byte0]: 50
8418 12:20:50.040377 [Byte1]: 50
8419 12:20:50.045001
8420 12:20:50.045091 Set Vref, RX VrefLevel [Byte0]: 51
8421 12:20:50.047891 [Byte1]: 51
8422 12:20:50.052422
8423 12:20:50.052509 Set Vref, RX VrefLevel [Byte0]: 52
8424 12:20:50.055626 [Byte1]: 52
8425 12:20:50.060016
8426 12:20:50.060102 Set Vref, RX VrefLevel [Byte0]: 53
8427 12:20:50.063430 [Byte1]: 53
8428 12:20:50.067750
8429 12:20:50.067835 Set Vref, RX VrefLevel [Byte0]: 54
8430 12:20:50.071124 [Byte1]: 54
8431 12:20:50.075800
8432 12:20:50.075886 Set Vref, RX VrefLevel [Byte0]: 55
8433 12:20:50.078653 [Byte1]: 55
8434 12:20:50.083160
8435 12:20:50.083272 Set Vref, RX VrefLevel [Byte0]: 56
8436 12:20:50.086308 [Byte1]: 56
8437 12:20:50.090764
8438 12:20:50.090851 Set Vref, RX VrefLevel [Byte0]: 57
8439 12:20:50.094048 [Byte1]: 57
8440 12:20:50.098139
8441 12:20:50.098223 Set Vref, RX VrefLevel [Byte0]: 58
8442 12:20:50.101567 [Byte1]: 58
8443 12:20:50.105957
8444 12:20:50.106043 Set Vref, RX VrefLevel [Byte0]: 59
8445 12:20:50.109313 [Byte1]: 59
8446 12:20:50.113607
8447 12:20:50.113694 Set Vref, RX VrefLevel [Byte0]: 60
8448 12:20:50.117156 [Byte1]: 60
8449 12:20:50.121262
8450 12:20:50.121349 Set Vref, RX VrefLevel [Byte0]: 61
8451 12:20:50.124407 [Byte1]: 61
8452 12:20:50.128917
8453 12:20:50.129003 Set Vref, RX VrefLevel [Byte0]: 62
8454 12:20:50.132299 [Byte1]: 62
8455 12:20:50.136706
8456 12:20:50.136794 Set Vref, RX VrefLevel [Byte0]: 63
8457 12:20:50.139767 [Byte1]: 63
8458 12:20:50.144077
8459 12:20:50.144163 Set Vref, RX VrefLevel [Byte0]: 64
8460 12:20:50.147367 [Byte1]: 64
8461 12:20:50.151717
8462 12:20:50.151803 Set Vref, RX VrefLevel [Byte0]: 65
8463 12:20:50.154992 [Byte1]: 65
8464 12:20:50.159424
8465 12:20:50.159508 Set Vref, RX VrefLevel [Byte0]: 66
8466 12:20:50.162921 [Byte1]: 66
8467 12:20:50.167352
8468 12:20:50.167435 Set Vref, RX VrefLevel [Byte0]: 67
8469 12:20:50.170532 [Byte1]: 67
8470 12:20:50.174743
8471 12:20:50.177957 Set Vref, RX VrefLevel [Byte0]: 68
8472 12:20:50.181116 [Byte1]: 68
8473 12:20:50.181199
8474 12:20:50.184572 Set Vref, RX VrefLevel [Byte0]: 69
8475 12:20:50.188122 [Byte1]: 69
8476 12:20:50.188217
8477 12:20:50.191285 Set Vref, RX VrefLevel [Byte0]: 70
8478 12:20:50.194408 [Byte1]: 70
8479 12:20:50.197688
8480 12:20:50.197768 Set Vref, RX VrefLevel [Byte0]: 71
8481 12:20:50.201093 [Byte1]: 71
8482 12:20:50.205453
8483 12:20:50.205537 Set Vref, RX VrefLevel [Byte0]: 72
8484 12:20:50.208604 [Byte1]: 72
8485 12:20:50.213064
8486 12:20:50.213153 Set Vref, RX VrefLevel [Byte0]: 73
8487 12:20:50.216654 [Byte1]: 73
8488 12:20:50.220782
8489 12:20:50.220869 Set Vref, RX VrefLevel [Byte0]: 74
8490 12:20:50.224112 [Byte1]: 74
8491 12:20:50.228369
8492 12:20:50.228452 Final RX Vref Byte 0 = 59 to rank0
8493 12:20:50.231992 Final RX Vref Byte 1 = 55 to rank0
8494 12:20:50.234959 Final RX Vref Byte 0 = 59 to rank1
8495 12:20:50.238523 Final RX Vref Byte 1 = 55 to rank1==
8496 12:20:50.241805 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 12:20:50.248116 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8498 12:20:50.248282 ==
8499 12:20:50.248349 DQS Delay:
8500 12:20:50.248408 DQS0 = 0, DQS1 = 0
8501 12:20:50.251478 DQM Delay:
8502 12:20:50.251558 DQM0 = 128, DQM1 = 123
8503 12:20:50.254803 DQ Delay:
8504 12:20:50.258225 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
8505 12:20:50.261563 DQ4 =128, DQ5 =140, DQ6 =138, DQ7 =124
8506 12:20:50.264859 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =110
8507 12:20:50.267960 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =132
8508 12:20:50.268067
8509 12:20:50.268158
8510 12:20:50.268305
8511 12:20:50.271299 [DramC_TX_OE_Calibration] TA2
8512 12:20:50.274606 Original DQ_B0 (3 6) =30, OEN = 27
8513 12:20:50.277852 Original DQ_B1 (3 6) =30, OEN = 27
8514 12:20:50.281398 24, 0x0, End_B0=24 End_B1=24
8515 12:20:50.281506 25, 0x0, End_B0=25 End_B1=25
8516 12:20:50.284704 26, 0x0, End_B0=26 End_B1=26
8517 12:20:50.288031 27, 0x0, End_B0=27 End_B1=27
8518 12:20:50.291067 28, 0x0, End_B0=28 End_B1=28
8519 12:20:50.294385 29, 0x0, End_B0=29 End_B1=29
8520 12:20:50.294494 30, 0x0, End_B0=30 End_B1=30
8521 12:20:50.298283 31, 0x4141, End_B0=30 End_B1=30
8522 12:20:50.301027 Byte0 end_step=30 best_step=27
8523 12:20:50.304576 Byte1 end_step=30 best_step=27
8524 12:20:50.307814 Byte0 TX OE(2T, 0.5T) = (3, 3)
8525 12:20:50.311309 Byte1 TX OE(2T, 0.5T) = (3, 3)
8526 12:20:50.311418
8527 12:20:50.311509
8528 12:20:50.317779 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8529 12:20:50.321144 CH1 RK0: MR19=303, MR18=2525
8530 12:20:50.327935 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8531 12:20:50.328065
8532 12:20:50.330939 ----->DramcWriteLeveling(PI) begin...
8533 12:20:50.331050 ==
8534 12:20:50.334117 Dram Type= 6, Freq= 0, CH_1, rank 1
8535 12:20:50.337489 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8536 12:20:50.337612 ==
8537 12:20:50.341135 Write leveling (Byte 0): 23 => 23
8538 12:20:50.344160 Write leveling (Byte 1): 20 => 20
8539 12:20:50.347278 DramcWriteLeveling(PI) end<-----
8540 12:20:50.347388
8541 12:20:50.347480 ==
8542 12:20:50.350600 Dram Type= 6, Freq= 0, CH_1, rank 1
8543 12:20:50.354065 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8544 12:20:50.354172 ==
8545 12:20:50.357485 [Gating] SW mode calibration
8546 12:20:50.363872 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8547 12:20:50.370612 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8548 12:20:50.374000 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8549 12:20:50.380950 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8550 12:20:50.383886 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8551 12:20:50.387223 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8552 12:20:50.394005 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8553 12:20:50.397197 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8554 12:20:50.400568 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8555 12:20:50.407431 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8556 12:20:50.410536 0 13 0 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
8557 12:20:50.413868 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8558 12:20:50.417274 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8559 12:20:50.423868 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8560 12:20:50.427279 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8561 12:20:50.430397 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8562 12:20:50.437276 0 13 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
8563 12:20:50.440469 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8564 12:20:50.443780 0 14 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8565 12:20:50.450501 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8566 12:20:50.453748 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8567 12:20:50.457232 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8568 12:20:50.463670 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8569 12:20:50.466875 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8570 12:20:50.470187 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8571 12:20:50.476919 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8572 12:20:50.480098 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8573 12:20:50.483308 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 12:20:50.490011 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 12:20:50.493304 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 12:20:50.496610 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 12:20:50.503282 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 12:20:50.506584 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 12:20:50.509760 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 12:20:50.516695 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 12:20:50.519954 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 12:20:50.522979 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 12:20:50.529825 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 12:20:50.533196 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 12:20:50.536475 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 12:20:50.543113 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8587 12:20:50.546355 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8588 12:20:50.549586 Total UI for P1: 0, mck2ui 16
8589 12:20:50.552985 best dqsien dly found for B0: ( 1, 0, 24)
8590 12:20:50.556305 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8591 12:20:50.562873 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8592 12:20:50.562982 Total UI for P1: 0, mck2ui 16
8593 12:20:50.566406 best dqsien dly found for B1: ( 1, 0, 30)
8594 12:20:50.572793 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8595 12:20:50.576157 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8596 12:20:50.576297
8597 12:20:50.579624 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8598 12:20:50.582850 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8599 12:20:50.586241 [Gating] SW calibration Done
8600 12:20:50.586345 ==
8601 12:20:50.589488 Dram Type= 6, Freq= 0, CH_1, rank 1
8602 12:20:50.592655 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8603 12:20:50.592759 ==
8604 12:20:50.596106 RX Vref Scan: 0
8605 12:20:50.596241
8606 12:20:50.596326 RX Vref 0 -> 0, step: 1
8607 12:20:50.596408
8608 12:20:50.599334 RX Delay 0 -> 252, step: 8
8609 12:20:50.602805 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8610 12:20:50.609458 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8611 12:20:50.612829 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8612 12:20:50.616114 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8613 12:20:50.619420 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8614 12:20:50.622743 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8615 12:20:50.629347 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8616 12:20:50.632481 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8617 12:20:50.635865 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8618 12:20:50.639414 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8619 12:20:50.642837 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8620 12:20:50.649411 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8621 12:20:50.652732 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8622 12:20:50.655979 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8623 12:20:50.659116 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8624 12:20:50.662421 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8625 12:20:50.665719 ==
8626 12:20:50.665797 Dram Type= 6, Freq= 0, CH_1, rank 1
8627 12:20:50.672497 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8628 12:20:50.672579 ==
8629 12:20:50.672643 DQS Delay:
8630 12:20:50.675921 DQS0 = 0, DQS1 = 0
8631 12:20:50.676000 DQM Delay:
8632 12:20:50.679077 DQM0 = 131, DQM1 = 124
8633 12:20:50.679155 DQ Delay:
8634 12:20:50.682668 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8635 12:20:50.685858 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8636 12:20:50.689023 DQ8 =107, DQ9 =111, DQ10 =123, DQ11 =115
8637 12:20:50.692438 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8638 12:20:50.692516
8639 12:20:50.692579
8640 12:20:50.692636 ==
8641 12:20:50.695626 Dram Type= 6, Freq= 0, CH_1, rank 1
8642 12:20:50.702262 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8643 12:20:50.702342 ==
8644 12:20:50.702404
8645 12:20:50.702461
8646 12:20:50.702516 TX Vref Scan disable
8647 12:20:50.705602 == TX Byte 0 ==
8648 12:20:50.708872 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8649 12:20:50.715565 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8650 12:20:50.715645 == TX Byte 1 ==
8651 12:20:50.718883 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8652 12:20:50.725511 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8653 12:20:50.725590 ==
8654 12:20:50.728645 Dram Type= 6, Freq= 0, CH_1, rank 1
8655 12:20:50.732321 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8656 12:20:50.732400 ==
8657 12:20:50.745665
8658 12:20:50.748920 TX Vref early break, caculate TX vref
8659 12:20:50.752146 TX Vref=16, minBit 0, minWin=21, winSum=373
8660 12:20:50.755680 TX Vref=18, minBit 5, minWin=22, winSum=388
8661 12:20:50.758787 TX Vref=20, minBit 0, minWin=22, winSum=393
8662 12:20:50.762136 TX Vref=22, minBit 0, minWin=23, winSum=399
8663 12:20:50.765470 TX Vref=24, minBit 0, minWin=23, winSum=410
8664 12:20:50.772162 TX Vref=26, minBit 0, minWin=24, winSum=417
8665 12:20:50.775620 TX Vref=28, minBit 0, minWin=24, winSum=417
8666 12:20:50.778630 TX Vref=30, minBit 0, minWin=23, winSum=413
8667 12:20:50.782189 TX Vref=32, minBit 0, minWin=23, winSum=410
8668 12:20:50.785344 TX Vref=34, minBit 0, minWin=22, winSum=401
8669 12:20:50.788684 TX Vref=36, minBit 0, minWin=21, winSum=394
8670 12:20:50.795280 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 26
8671 12:20:50.795359
8672 12:20:50.798604 Final TX Range 0 Vref 26
8673 12:20:50.798682
8674 12:20:50.798743 ==
8675 12:20:50.802238 Dram Type= 6, Freq= 0, CH_1, rank 1
8676 12:20:50.805454 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8677 12:20:50.805532 ==
8678 12:20:50.805593
8679 12:20:50.805651
8680 12:20:50.808506 TX Vref Scan disable
8681 12:20:50.815190 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8682 12:20:50.815268 == TX Byte 0 ==
8683 12:20:50.818557 u2DelayCellOfst[0]=14 cells (4 PI)
8684 12:20:50.821919 u2DelayCellOfst[1]=7 cells (2 PI)
8685 12:20:50.825138 u2DelayCellOfst[2]=0 cells (0 PI)
8686 12:20:50.828695 u2DelayCellOfst[3]=7 cells (2 PI)
8687 12:20:50.832210 u2DelayCellOfst[4]=7 cells (2 PI)
8688 12:20:50.835148 u2DelayCellOfst[5]=14 cells (4 PI)
8689 12:20:50.838487 u2DelayCellOfst[6]=14 cells (4 PI)
8690 12:20:50.841780 u2DelayCellOfst[7]=3 cells (1 PI)
8691 12:20:50.845042 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8692 12:20:50.848461 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8693 12:20:50.851798 == TX Byte 1 ==
8694 12:20:50.855451 u2DelayCellOfst[8]=0 cells (0 PI)
8695 12:20:50.855531 u2DelayCellOfst[9]=7 cells (2 PI)
8696 12:20:50.858289 u2DelayCellOfst[10]=14 cells (4 PI)
8697 12:20:50.861661 u2DelayCellOfst[11]=7 cells (2 PI)
8698 12:20:50.864929 u2DelayCellOfst[12]=17 cells (5 PI)
8699 12:20:50.868193 u2DelayCellOfst[13]=21 cells (6 PI)
8700 12:20:50.871487 u2DelayCellOfst[14]=21 cells (6 PI)
8701 12:20:50.875066 u2DelayCellOfst[15]=21 cells (6 PI)
8702 12:20:50.878313 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8703 12:20:50.884722 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8704 12:20:50.884802 DramC Write-DBI on
8705 12:20:50.884864 ==
8706 12:20:50.888080 Dram Type= 6, Freq= 0, CH_1, rank 1
8707 12:20:50.894596 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8708 12:20:50.894676 ==
8709 12:20:50.894739
8710 12:20:50.894796
8711 12:20:50.894851 TX Vref Scan disable
8712 12:20:50.898452 == TX Byte 0 ==
8713 12:20:50.901820 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8714 12:20:50.905227 == TX Byte 1 ==
8715 12:20:50.908641 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8716 12:20:50.911804 DramC Write-DBI off
8717 12:20:50.911883
8718 12:20:50.911946 [DATLAT]
8719 12:20:50.912004 Freq=1600, CH1 RK1
8720 12:20:50.912060
8721 12:20:50.915188 DATLAT Default: 0xe
8722 12:20:50.915267 0, 0xFFFF, sum = 0
8723 12:20:50.918387 1, 0xFFFF, sum = 0
8724 12:20:50.921937 2, 0xFFFF, sum = 0
8725 12:20:50.922019 3, 0xFFFF, sum = 0
8726 12:20:50.925221 4, 0xFFFF, sum = 0
8727 12:20:50.925302 5, 0xFFFF, sum = 0
8728 12:20:50.928704 6, 0xFFFF, sum = 0
8729 12:20:50.928785 7, 0xFFFF, sum = 0
8730 12:20:50.931630 8, 0xFFFF, sum = 0
8731 12:20:50.931711 9, 0xFFFF, sum = 0
8732 12:20:50.935049 10, 0xFFFF, sum = 0
8733 12:20:50.935129 11, 0xFFFF, sum = 0
8734 12:20:50.938344 12, 0xF7F, sum = 0
8735 12:20:50.938426 13, 0x0, sum = 1
8736 12:20:50.941775 14, 0x0, sum = 2
8737 12:20:50.941872 15, 0x0, sum = 3
8738 12:20:50.945195 16, 0x0, sum = 4
8739 12:20:50.945276 best_step = 14
8740 12:20:50.945338
8741 12:20:50.945396 ==
8742 12:20:50.948506 Dram Type= 6, Freq= 0, CH_1, rank 1
8743 12:20:50.951574 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8744 12:20:50.954843 ==
8745 12:20:50.954923 RX Vref Scan: 0
8746 12:20:50.954986
8747 12:20:50.957969 RX Vref 0 -> 0, step: 1
8748 12:20:50.958049
8749 12:20:50.958113 RX Delay 3 -> 252, step: 4
8750 12:20:50.965542 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8751 12:20:50.968669 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8752 12:20:50.972145 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8753 12:20:50.975353 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8754 12:20:50.978701 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8755 12:20:50.985540 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8756 12:20:50.989078 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8757 12:20:50.992353 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8758 12:20:50.995271 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8759 12:20:50.998734 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8760 12:20:51.005393 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8761 12:20:51.008805 iDelay=195, Bit 11, Center 112 (55 ~ 170) 116
8762 12:20:51.011998 iDelay=195, Bit 12, Center 130 (71 ~ 190) 120
8763 12:20:51.015186 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8764 12:20:51.021912 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8765 12:20:51.025144 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8766 12:20:51.025226 ==
8767 12:20:51.028653 Dram Type= 6, Freq= 0, CH_1, rank 1
8768 12:20:51.031924 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8769 12:20:51.032004 ==
8770 12:20:51.032066 DQS Delay:
8771 12:20:51.035162 DQS0 = 0, DQS1 = 0
8772 12:20:51.035240 DQM Delay:
8773 12:20:51.038416 DQM0 = 127, DQM1 = 122
8774 12:20:51.038495 DQ Delay:
8775 12:20:51.041669 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8776 12:20:51.045242 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8777 12:20:51.048423 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =112
8778 12:20:51.055150 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =132
8779 12:20:51.055229
8780 12:20:51.055292
8781 12:20:51.055350
8782 12:20:51.058604 [DramC_TX_OE_Calibration] TA2
8783 12:20:51.058682 Original DQ_B0 (3 6) =30, OEN = 27
8784 12:20:51.061704 Original DQ_B1 (3 6) =30, OEN = 27
8785 12:20:51.064984 24, 0x0, End_B0=24 End_B1=24
8786 12:20:51.068363 25, 0x0, End_B0=25 End_B1=25
8787 12:20:51.071562 26, 0x0, End_B0=26 End_B1=26
8788 12:20:51.074977 27, 0x0, End_B0=27 End_B1=27
8789 12:20:51.075057 28, 0x0, End_B0=28 End_B1=28
8790 12:20:51.078295 29, 0x0, End_B0=29 End_B1=29
8791 12:20:51.081744 30, 0x0, End_B0=30 End_B1=30
8792 12:20:51.085175 31, 0x4141, End_B0=30 End_B1=30
8793 12:20:51.088308 Byte0 end_step=30 best_step=27
8794 12:20:51.088402 Byte1 end_step=30 best_step=27
8795 12:20:51.091421 Byte0 TX OE(2T, 0.5T) = (3, 3)
8796 12:20:51.094736 Byte1 TX OE(2T, 0.5T) = (3, 3)
8797 12:20:51.094860
8798 12:20:51.094924
8799 12:20:51.104684 [DQSOSCAuto] RK1, (LSB)MR18= 0x2020, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
8800 12:20:51.104780 CH1 RK1: MR19=303, MR18=2020
8801 12:20:51.111239 CH1_RK1: MR19=0x303, MR18=0x2020, DQSOSC=393, MR23=63, INC=23, DEC=15
8802 12:20:51.114638 [RxdqsGatingPostProcess] freq 1600
8803 12:20:51.121322 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8804 12:20:51.124811 Pre-setting of DQS Precalculation
8805 12:20:51.128082 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8806 12:20:51.134494 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8807 12:20:51.144504 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8808 12:20:51.144598
8809 12:20:51.144665
8810 12:20:51.147744 [Calibration Summary] 3200 Mbps
8811 12:20:51.147826 CH 0, Rank 0
8812 12:20:51.151218 SW Impedance : PASS
8813 12:20:51.151298 DUTY Scan : NO K
8814 12:20:51.154566 ZQ Calibration : PASS
8815 12:20:51.157762 Jitter Meter : NO K
8816 12:20:51.157842 CBT Training : PASS
8817 12:20:51.161068 Write leveling : PASS
8818 12:20:51.161148 RX DQS gating : PASS
8819 12:20:51.164483 RX DQ/DQS(RDDQC) : PASS
8820 12:20:51.168035 TX DQ/DQS : PASS
8821 12:20:51.168115 RX DATLAT : PASS
8822 12:20:51.171243 RX DQ/DQS(Engine): PASS
8823 12:20:51.174513 TX OE : PASS
8824 12:20:51.174594 All Pass.
8825 12:20:51.174657
8826 12:20:51.174715 CH 0, Rank 1
8827 12:20:51.177777 SW Impedance : PASS
8828 12:20:51.181087 DUTY Scan : NO K
8829 12:20:51.181170 ZQ Calibration : PASS
8830 12:20:51.184451 Jitter Meter : NO K
8831 12:20:51.187775 CBT Training : PASS
8832 12:20:51.187856 Write leveling : PASS
8833 12:20:51.191078 RX DQS gating : PASS
8834 12:20:51.194689 RX DQ/DQS(RDDQC) : PASS
8835 12:20:51.194770 TX DQ/DQS : PASS
8836 12:20:51.197808 RX DATLAT : PASS
8837 12:20:51.201284 RX DQ/DQS(Engine): PASS
8838 12:20:51.201365 TX OE : PASS
8839 12:20:51.201429 All Pass.
8840 12:20:51.204464
8841 12:20:51.204574 CH 1, Rank 0
8842 12:20:51.207912 SW Impedance : PASS
8843 12:20:51.208018 DUTY Scan : NO K
8844 12:20:51.211037 ZQ Calibration : PASS
8845 12:20:51.211142 Jitter Meter : NO K
8846 12:20:51.214353 CBT Training : PASS
8847 12:20:51.217924 Write leveling : PASS
8848 12:20:51.218010 RX DQS gating : PASS
8849 12:20:51.221003 RX DQ/DQS(RDDQC) : PASS
8850 12:20:51.224424 TX DQ/DQS : PASS
8851 12:20:51.224505 RX DATLAT : PASS
8852 12:20:51.227508 RX DQ/DQS(Engine): PASS
8853 12:20:51.230898 TX OE : PASS
8854 12:20:51.230978 All Pass.
8855 12:20:51.231041
8856 12:20:51.231099 CH 1, Rank 1
8857 12:20:51.234404 SW Impedance : PASS
8858 12:20:51.237437 DUTY Scan : NO K
8859 12:20:51.237518 ZQ Calibration : PASS
8860 12:20:51.240728 Jitter Meter : NO K
8861 12:20:51.244017 CBT Training : PASS
8862 12:20:51.244124 Write leveling : PASS
8863 12:20:51.247525 RX DQS gating : PASS
8864 12:20:51.250834 RX DQ/DQS(RDDQC) : PASS
8865 12:20:51.250914 TX DQ/DQS : PASS
8866 12:20:51.254268 RX DATLAT : PASS
8867 12:20:51.257616 RX DQ/DQS(Engine): PASS
8868 12:20:51.257697 TX OE : PASS
8869 12:20:51.257761 All Pass.
8870 12:20:51.260611
8871 12:20:51.260690 DramC Write-DBI on
8872 12:20:51.263919 PER_BANK_REFRESH: Hybrid Mode
8873 12:20:51.263999 TX_TRACKING: ON
8874 12:20:51.273935 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8875 12:20:51.281095 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8876 12:20:51.290467 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8877 12:20:51.293913 [FAST_K] Save calibration result to emmc
8878 12:20:51.297072 sync common calibartion params.
8879 12:20:51.297179 sync cbt_mode0:0, 1:0
8880 12:20:51.300269 dram_init: ddr_geometry: 0
8881 12:20:51.303729 dram_init: ddr_geometry: 0
8882 12:20:51.303839 dram_init: ddr_geometry: 0
8883 12:20:51.307029 0:dram_rank_size:80000000
8884 12:20:51.310528 1:dram_rank_size:80000000
8885 12:20:51.313634 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8886 12:20:51.317153 DFS_SHUFFLE_HW_MODE: ON
8887 12:20:51.320287 dramc_set_vcore_voltage set vcore to 725000
8888 12:20:51.323343 Read voltage for 1600, 0
8889 12:20:51.323455 Vio18 = 0
8890 12:20:51.326832 Vcore = 725000
8891 12:20:51.326946 Vdram = 0
8892 12:20:51.327036 Vddq = 0
8893 12:20:51.330095 Vmddr = 0
8894 12:20:51.330198 switch to 3200 Mbps bootup
8895 12:20:51.333219 [DramcRunTimeConfig]
8896 12:20:51.333322 PHYPLL
8897 12:20:51.336614 DPM_CONTROL_AFTERK: ON
8898 12:20:51.336719 PER_BANK_REFRESH: ON
8899 12:20:51.339826 REFRESH_OVERHEAD_REDUCTION: ON
8900 12:20:51.343220 CMD_PICG_NEW_MODE: OFF
8901 12:20:51.343315 XRTWTW_NEW_MODE: ON
8902 12:20:51.346719 XRTRTR_NEW_MODE: ON
8903 12:20:51.346804 TX_TRACKING: ON
8904 12:20:51.349854 RDSEL_TRACKING: OFF
8905 12:20:51.353421 DQS Precalculation for DVFS: ON
8906 12:20:51.353510 RX_TRACKING: OFF
8907 12:20:51.356744 HW_GATING DBG: ON
8908 12:20:51.356830 ZQCS_ENABLE_LP4: ON
8909 12:20:51.359752 RX_PICG_NEW_MODE: ON
8910 12:20:51.359835 TX_PICG_NEW_MODE: ON
8911 12:20:51.363245 ENABLE_RX_DCM_DPHY: ON
8912 12:20:51.366476 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8913 12:20:51.369582 DUMMY_READ_FOR_TRACKING: OFF
8914 12:20:51.369672 !!! SPM_CONTROL_AFTERK: OFF
8915 12:20:51.373083 !!! SPM could not control APHY
8916 12:20:51.376178 IMPEDANCE_TRACKING: ON
8917 12:20:51.376271 TEMP_SENSOR: ON
8918 12:20:51.379650 HW_SAVE_FOR_SR: OFF
8919 12:20:51.382871 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8920 12:20:51.386783 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8921 12:20:51.386916 Read ODT Tracking: ON
8922 12:20:51.389484 Refresh Rate DeBounce: ON
8923 12:20:51.392844 DFS_NO_QUEUE_FLUSH: ON
8924 12:20:51.396404 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8925 12:20:51.396510 ENABLE_DFS_RUNTIME_MRW: OFF
8926 12:20:51.400039 DDR_RESERVE_NEW_MODE: ON
8927 12:20:51.403050 MR_CBT_SWITCH_FREQ: ON
8928 12:20:51.403156 =========================
8929 12:20:51.422869 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8930 12:20:51.426154 dram_init: ddr_geometry: 0
8931 12:20:51.444330 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8932 12:20:51.447871 dram_init: dram init end (result: 0)
8933 12:20:51.454385 DRAM-K: Full calibration passed in 23427 msecs
8934 12:20:51.457604 MRC: failed to locate region type 0.
8935 12:20:51.457714 DRAM rank0 size:0x80000000,
8936 12:20:51.460838 DRAM rank1 size=0x80000000
8937 12:20:51.470890 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8938 12:20:51.477485 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8939 12:20:51.484115 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8940 12:20:51.490711 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8941 12:20:51.494041 DRAM rank0 size:0x80000000,
8942 12:20:51.497292 DRAM rank1 size=0x80000000
8943 12:20:51.497399 CBMEM:
8944 12:20:51.500858 IMD: root @ 0xfffff000 254 entries.
8945 12:20:51.504376 IMD: root @ 0xffffec00 62 entries.
8946 12:20:51.507325 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8947 12:20:51.510785 WARNING: RO_VPD is uninitialized or empty.
8948 12:20:51.517200 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8949 12:20:51.524132 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8950 12:20:51.536736 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8951 12:20:51.547998 BS: romstage times (exec / console): total (unknown) / 22963 ms
8952 12:20:51.548134
8953 12:20:51.548271
8954 12:20:51.557926 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8955 12:20:51.561493 ARM64: Exception handlers installed.
8956 12:20:51.564597 ARM64: Testing exception
8957 12:20:51.568287 ARM64: Done test exception
8958 12:20:51.568389 Enumerating buses...
8959 12:20:51.571227 Show all devs... Before device enumeration.
8960 12:20:51.574592 Root Device: enabled 1
8961 12:20:51.577822 CPU_CLUSTER: 0: enabled 1
8962 12:20:51.577924 CPU: 00: enabled 1
8963 12:20:51.581416 Compare with tree...
8964 12:20:51.581519 Root Device: enabled 1
8965 12:20:51.584684 CPU_CLUSTER: 0: enabled 1
8966 12:20:51.588099 CPU: 00: enabled 1
8967 12:20:51.588194 Root Device scanning...
8968 12:20:51.591226 scan_static_bus for Root Device
8969 12:20:51.594854 CPU_CLUSTER: 0 enabled
8970 12:20:51.597880 scan_static_bus for Root Device done
8971 12:20:51.601361 scan_bus: bus Root Device finished in 8 msecs
8972 12:20:51.601444 done
8973 12:20:51.607745 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8974 12:20:51.611135 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8975 12:20:51.618073 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8976 12:20:51.621090 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8977 12:20:51.624353 Allocating resources...
8978 12:20:51.627580 Reading resources...
8979 12:20:51.631344 Root Device read_resources bus 0 link: 0
8980 12:20:51.631427 DRAM rank0 size:0x80000000,
8981 12:20:51.634104 DRAM rank1 size=0x80000000
8982 12:20:51.637641 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8983 12:20:51.640772 CPU: 00 missing read_resources
8984 12:20:51.644029 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8985 12:20:51.650832 Root Device read_resources bus 0 link: 0 done
8986 12:20:51.650917 Done reading resources.
8987 12:20:51.657451 Show resources in subtree (Root Device)...After reading.
8988 12:20:51.660694 Root Device child on link 0 CPU_CLUSTER: 0
8989 12:20:51.663920 CPU_CLUSTER: 0 child on link 0 CPU: 00
8990 12:20:51.673962 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8991 12:20:51.674047 CPU: 00
8992 12:20:51.677678 Root Device assign_resources, bus 0 link: 0
8993 12:20:51.680545 CPU_CLUSTER: 0 missing set_resources
8994 12:20:51.686989 Root Device assign_resources, bus 0 link: 0 done
8995 12:20:51.687076 Done setting resources.
8996 12:20:51.694136 Show resources in subtree (Root Device)...After assigning values.
8997 12:20:51.697074 Root Device child on link 0 CPU_CLUSTER: 0
8998 12:20:51.700353 CPU_CLUSTER: 0 child on link 0 CPU: 00
8999 12:20:51.710236 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9000 12:20:51.710321 CPU: 00
9001 12:20:51.713439 Done allocating resources.
9002 12:20:51.720386 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9003 12:20:51.720471 Enabling resources...
9004 12:20:51.720555 done.
9005 12:20:51.726575 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9006 12:20:51.726658 Initializing devices...
9007 12:20:51.730089 Root Device init
9008 12:20:51.730170 init hardware done!
9009 12:20:51.733531 0x00000018: ctrlr->caps
9010 12:20:51.736705 52.000 MHz: ctrlr->f_max
9011 12:20:51.736790 0.400 MHz: ctrlr->f_min
9012 12:20:51.739877 0x40ff8080: ctrlr->voltages
9013 12:20:51.743133 sclk: 390625
9014 12:20:51.743215 Bus Width = 1
9015 12:20:51.743301 sclk: 390625
9016 12:20:51.746809 Bus Width = 1
9017 12:20:51.746916 Early init status = 3
9018 12:20:51.753012 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9019 12:20:51.756458 in-header: 03 fc 00 00 01 00 00 00
9020 12:20:51.759648 in-data: 00
9021 12:20:51.763021 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9022 12:20:51.766625 in-header: 03 fd 00 00 00 00 00 00
9023 12:20:51.769870 in-data:
9024 12:20:51.773575 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9025 12:20:51.777378 in-header: 03 fc 00 00 01 00 00 00
9026 12:20:51.780106 in-data: 00
9027 12:20:51.783423 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9028 12:20:51.788889 in-header: 03 fd 00 00 00 00 00 00
9029 12:20:51.792042 in-data:
9030 12:20:51.795290 [SSUSB] Setting up USB HOST controller...
9031 12:20:51.798612 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9032 12:20:51.802026 [SSUSB] phy power-on done.
9033 12:20:51.805227 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9034 12:20:51.811991 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9035 12:20:51.815225 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9036 12:20:51.821704 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9037 12:20:51.828348 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9038 12:20:51.835385 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9039 12:20:51.841849 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9040 12:20:51.848339 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9041 12:20:51.851702 SPM: binary array size = 0x9dc
9042 12:20:51.854911 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9043 12:20:51.861649 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9044 12:20:51.868348 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9045 12:20:51.871680 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9046 12:20:51.878382 configure_display: Starting display init
9047 12:20:51.912097 anx7625_power_on_init: Init interface.
9048 12:20:51.915261 anx7625_disable_pd_protocol: Disabled PD feature.
9049 12:20:51.918747 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9050 12:20:51.946275 anx7625_start_dp_work: Secure OCM version=00
9051 12:20:51.949456 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9052 12:20:51.964410 sp_tx_get_edid_block: EDID Block = 1
9053 12:20:52.067161 Extracted contents:
9054 12:20:52.070160 header: 00 ff ff ff ff ff ff 00
9055 12:20:52.073517 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9056 12:20:52.077020 version: 01 04
9057 12:20:52.080123 basic params: 95 1f 11 78 0a
9058 12:20:52.083531 chroma info: 76 90 94 55 54 90 27 21 50 54
9059 12:20:52.086726 established: 00 00 00
9060 12:20:52.093427 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9061 12:20:52.096932 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9062 12:20:52.103455 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9063 12:20:52.110047 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9064 12:20:52.116540 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9065 12:20:52.119935 extensions: 00
9066 12:20:52.120077 checksum: fb
9067 12:20:52.120171
9068 12:20:52.123110 Manufacturer: IVO Model 57d Serial Number 0
9069 12:20:52.126943 Made week 0 of 2020
9070 12:20:52.127064 EDID version: 1.4
9071 12:20:52.129861 Digital display
9072 12:20:52.133135 6 bits per primary color channel
9073 12:20:52.133240 DisplayPort interface
9074 12:20:52.136393 Maximum image size: 31 cm x 17 cm
9075 12:20:52.139814 Gamma: 220%
9076 12:20:52.139921 Check DPMS levels
9077 12:20:52.143120 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9078 12:20:52.149706 First detailed timing is preferred timing
9079 12:20:52.149816 Established timings supported:
9080 12:20:52.153263 Standard timings supported:
9081 12:20:52.156745 Detailed timings
9082 12:20:52.160032 Hex of detail: 383680a07038204018303c0035ae10000019
9083 12:20:52.163114 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9084 12:20:52.169859 0780 0798 07c8 0820 hborder 0
9085 12:20:52.173051 0438 043b 0447 0458 vborder 0
9086 12:20:52.176443 -hsync -vsync
9087 12:20:52.176548 Did detailed timing
9088 12:20:52.183029 Hex of detail: 000000000000000000000000000000000000
9089 12:20:52.183136 Manufacturer-specified data, tag 0
9090 12:20:52.189975 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9091 12:20:52.192848 ASCII string: InfoVision
9092 12:20:52.196401 Hex of detail: 000000fe00523134304e574635205248200a
9093 12:20:52.199711 ASCII string: R140NWF5 RH
9094 12:20:52.199817 Checksum
9095 12:20:52.202788 Checksum: 0xfb (valid)
9096 12:20:52.206227 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9097 12:20:52.209409 DSI data_rate: 832800000 bps
9098 12:20:52.216151 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9099 12:20:52.219284 anx7625_parse_edid: pixelclock(138800).
9100 12:20:52.222734 hactive(1920), hsync(48), hfp(24), hbp(88)
9101 12:20:52.225890 vactive(1080), vsync(12), vfp(3), vbp(17)
9102 12:20:52.229136 anx7625_dsi_config: config dsi.
9103 12:20:52.235725 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9104 12:20:52.248868 anx7625_dsi_config: success to config DSI
9105 12:20:52.252379 anx7625_dp_start: MIPI phy setup OK.
9106 12:20:52.255538 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9107 12:20:52.258989 mtk_ddp_mode_set invalid vrefresh 60
9108 12:20:52.262418 main_disp_path_setup
9109 12:20:52.262524 ovl_layer_smi_id_en
9110 12:20:52.266028 ovl_layer_smi_id_en
9111 12:20:52.266134 ccorr_config
9112 12:20:52.266227 aal_config
9113 12:20:52.268849 gamma_config
9114 12:20:52.268953 postmask_config
9115 12:20:52.272097 dither_config
9116 12:20:52.275591 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9117 12:20:52.282399 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9118 12:20:52.285505 Root Device init finished in 552 msecs
9119 12:20:52.285610 CPU_CLUSTER: 0 init
9120 12:20:52.295583 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9121 12:20:52.298857 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9122 12:20:52.302420 APU_MBOX 0x190000b0 = 0x10001
9123 12:20:52.305662 APU_MBOX 0x190001b0 = 0x10001
9124 12:20:52.308850 APU_MBOX 0x190005b0 = 0x10001
9125 12:20:52.312134 APU_MBOX 0x190006b0 = 0x10001
9126 12:20:52.315561 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9127 12:20:52.328159 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9128 12:20:52.340476 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9129 12:20:52.346911 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9130 12:20:52.359033 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9131 12:20:52.367603 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9132 12:20:52.371103 CPU_CLUSTER: 0 init finished in 81 msecs
9133 12:20:52.374460 Devices initialized
9134 12:20:52.377595 Show all devs... After init.
9135 12:20:52.377677 Root Device: enabled 1
9136 12:20:52.381188 CPU_CLUSTER: 0: enabled 1
9137 12:20:52.384384 CPU: 00: enabled 1
9138 12:20:52.387771 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9139 12:20:52.390867 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9140 12:20:52.394025 ELOG: NV offset 0x57f000 size 0x1000
9141 12:20:52.400861 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9142 12:20:52.407269 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9143 12:20:52.410612 ELOG: Event(17) added with size 13 at 2023-10-27 12:20:53 UTC
9144 12:20:52.417407 out: cmd=0x121: 03 db 21 01 00 00 00 00
9145 12:20:52.420677 in-header: 03 ed 00 00 2c 00 00 00
9146 12:20:52.433689 in-data: 76 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9147 12:20:52.437656 ELOG: Event(A1) added with size 10 at 2023-10-27 12:20:53 UTC
9148 12:20:52.443843 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9149 12:20:52.450180 ELOG: Event(A0) added with size 9 at 2023-10-27 12:20:53 UTC
9150 12:20:52.453429 elog_add_boot_reason: Logged dev mode boot
9151 12:20:52.460210 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9152 12:20:52.460315 Finalize devices...
9153 12:20:52.463520 Devices finalized
9154 12:20:52.466902 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9155 12:20:52.470209 Writing coreboot table at 0xffe64000
9156 12:20:52.476743 0. 000000000010a000-0000000000113fff: RAMSTAGE
9157 12:20:52.480138 1. 0000000040000000-00000000400fffff: RAM
9158 12:20:52.483360 2. 0000000040100000-000000004032afff: RAMSTAGE
9159 12:20:52.486614 3. 000000004032b000-00000000545fffff: RAM
9160 12:20:52.490183 4. 0000000054600000-000000005465ffff: BL31
9161 12:20:52.493152 5. 0000000054660000-00000000ffe63fff: RAM
9162 12:20:52.499928 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9163 12:20:52.503280 7. 0000000100000000-000000013fffffff: RAM
9164 12:20:52.506433 Passing 5 GPIOs to payload:
9165 12:20:52.509840 NAME | PORT | POLARITY | VALUE
9166 12:20:52.516564 EC in RW | 0x000000aa | low | undefined
9167 12:20:52.519823 EC interrupt | 0x00000005 | low | undefined
9168 12:20:52.526522 TPM interrupt | 0x000000ab | high | undefined
9169 12:20:52.529765 SD card detect | 0x00000011 | high | undefined
9170 12:20:52.533050 speaker enable | 0x00000093 | high | undefined
9171 12:20:52.536180 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9172 12:20:52.539793 in-header: 03 f8 00 00 02 00 00 00
9173 12:20:52.543068 in-data: 03 00
9174 12:20:52.546453 ADC[4]: Raw value=668958 ID=5
9175 12:20:52.549648 ADC[3]: Raw value=212917 ID=1
9176 12:20:52.549754 RAM Code: 0x51
9177 12:20:52.552998 ADC[6]: Raw value=74410 ID=0
9178 12:20:52.556463 ADC[5]: Raw value=211444 ID=1
9179 12:20:52.556570 SKU Code: 0x1
9180 12:20:52.562942 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 356b
9181 12:20:52.563050 coreboot table: 964 bytes.
9182 12:20:52.566166 IMD ROOT 0. 0xfffff000 0x00001000
9183 12:20:52.569425 IMD SMALL 1. 0xffffe000 0x00001000
9184 12:20:52.572830 RO MCACHE 2. 0xffffc000 0x00001104
9185 12:20:52.576138 CONSOLE 3. 0xfff7c000 0x00080000
9186 12:20:52.579563 FMAP 4. 0xfff7b000 0x00000452
9187 12:20:52.582836 TIME STAMP 5. 0xfff7a000 0x00000910
9188 12:20:52.586171 VBOOT WORK 6. 0xfff66000 0x00014000
9189 12:20:52.589394 RAMOOPS 7. 0xffe66000 0x00100000
9190 12:20:52.592802 COREBOOT 8. 0xffe64000 0x00002000
9191 12:20:52.595833 IMD small region:
9192 12:20:52.599186 IMD ROOT 0. 0xffffec00 0x00000400
9193 12:20:52.602416 VPD 1. 0xffffeb80 0x0000006c
9194 12:20:52.605829 MMC STATUS 2. 0xffffeb60 0x00000004
9195 12:20:52.612408 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9196 12:20:52.612523 Probing TPM: done!
9197 12:20:52.616117 Connected to device vid:did:rid of 1ae0:0028:00
9198 12:20:52.627341 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9199 12:20:52.630668 Initialized TPM device CR50 revision 0
9200 12:20:52.634307 Checking cr50 for pending updates
9201 12:20:52.637881 Reading cr50 TPM mode
9202 12:20:52.646338 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9203 12:20:52.653271 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9204 12:20:52.693480 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9205 12:20:52.696770 Checking segment from ROM address 0x40100000
9206 12:20:52.699869 Checking segment from ROM address 0x4010001c
9207 12:20:52.706813 Loading segment from ROM address 0x40100000
9208 12:20:52.706928 code (compression=0)
9209 12:20:52.716721 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9210 12:20:52.723666 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9211 12:20:52.723792 it's not compressed!
9212 12:20:52.730041 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9213 12:20:52.733563 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9214 12:20:52.753871 Loading segment from ROM address 0x4010001c
9215 12:20:52.754030 Entry Point 0x80000000
9216 12:20:52.757483 Loaded segments
9217 12:20:52.760483 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9218 12:20:52.767292 Jumping to boot code at 0x80000000(0xffe64000)
9219 12:20:52.774216 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9220 12:20:52.780358 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9221 12:20:52.788089 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9222 12:20:52.791444 Checking segment from ROM address 0x40100000
9223 12:20:52.794776 Checking segment from ROM address 0x4010001c
9224 12:20:52.801378 Loading segment from ROM address 0x40100000
9225 12:20:52.801501 code (compression=1)
9226 12:20:52.808157 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9227 12:20:52.818043 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9228 12:20:52.818177 using LZMA
9229 12:20:52.826786 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9230 12:20:52.833200 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9231 12:20:52.836588 Loading segment from ROM address 0x4010001c
9232 12:20:52.836704 Entry Point 0x54601000
9233 12:20:52.840027 Loaded segments
9234 12:20:52.843210 NOTICE: MT8192 bl31_setup
9235 12:20:52.850067 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9236 12:20:52.853779 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9237 12:20:52.856957 WARNING: region 0:
9238 12:20:52.860155 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9239 12:20:52.860284 WARNING: region 1:
9240 12:20:52.866675 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9241 12:20:52.870193 WARNING: region 2:
9242 12:20:52.873487 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9243 12:20:52.877015 WARNING: region 3:
9244 12:20:52.880063 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9245 12:20:52.883794 WARNING: region 4:
9246 12:20:52.890742 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9247 12:20:52.890849 WARNING: region 5:
9248 12:20:52.893637 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9249 12:20:52.897004 WARNING: region 6:
9250 12:20:52.900135 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9251 12:20:52.900298 WARNING: region 7:
9252 12:20:52.906822 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9253 12:20:52.913425 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9254 12:20:52.917009 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9255 12:20:52.919904 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9256 12:20:52.926720 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9257 12:20:52.930111 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9258 12:20:52.933359 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9259 12:20:52.940059 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9260 12:20:52.943311 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9261 12:20:52.950083 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9262 12:20:52.953545 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9263 12:20:52.956688 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9264 12:20:52.963518 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9265 12:20:52.966928 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9266 12:20:52.969971 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9267 12:20:52.976618 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9268 12:20:52.979931 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9269 12:20:52.986860 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9270 12:20:52.990010 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9271 12:20:52.993645 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9272 12:20:53.000102 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9273 12:20:53.003214 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9274 12:20:53.006497 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9275 12:20:53.013200 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9276 12:20:53.016451 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9277 12:20:53.023319 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9278 12:20:53.027135 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9279 12:20:53.030004 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9280 12:20:53.036620 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9281 12:20:53.040050 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9282 12:20:53.046666 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9283 12:20:53.050216 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9284 12:20:53.053260 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9285 12:20:53.060107 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9286 12:20:53.063345 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9287 12:20:53.066531 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9288 12:20:53.069842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9289 12:20:53.076633 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9290 12:20:53.080171 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9291 12:20:53.083518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9292 12:20:53.086747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9293 12:20:53.090156 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9294 12:20:53.097053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9295 12:20:53.100091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9296 12:20:53.103675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9297 12:20:53.110102 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9298 12:20:53.113340 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9299 12:20:53.116626 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9300 12:20:53.119924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9301 12:20:53.126624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9302 12:20:53.130133 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9303 12:20:53.136721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9304 12:20:53.139882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9305 12:20:53.143243 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9306 12:20:53.149669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9307 12:20:53.153232 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9308 12:20:53.159765 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9309 12:20:53.162998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9310 12:20:53.169835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9311 12:20:53.172980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9312 12:20:53.179507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9313 12:20:53.183059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9314 12:20:53.186402 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9315 12:20:53.193089 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9316 12:20:53.196072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9317 12:20:53.202893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9318 12:20:53.206135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9319 12:20:53.212772 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9320 12:20:53.216359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9321 12:20:53.219565 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9322 12:20:53.226168 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9323 12:20:53.229854 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9324 12:20:53.236225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9325 12:20:53.239538 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9326 12:20:53.246215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9327 12:20:53.249452 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9328 12:20:53.256022 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9329 12:20:53.259365 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9330 12:20:53.262720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9331 12:20:53.269410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9332 12:20:53.272738 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9333 12:20:53.279586 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9334 12:20:53.282997 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9335 12:20:53.289611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9336 12:20:53.292542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9337 12:20:53.296045 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9338 12:20:53.302656 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9339 12:20:53.305955 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9340 12:20:53.312620 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9341 12:20:53.315998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9342 12:20:53.322706 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9343 12:20:53.325836 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9344 12:20:53.329339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9345 12:20:53.335821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9346 12:20:53.339140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9347 12:20:53.345698 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9348 12:20:53.349093 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9349 12:20:53.355681 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9350 12:20:53.359431 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9351 12:20:53.362542 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9352 12:20:53.365804 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9353 12:20:53.369288 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9354 12:20:53.375751 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9355 12:20:53.379036 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9356 12:20:53.385797 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9357 12:20:53.389197 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9358 12:20:53.392339 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9359 12:20:53.399024 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9360 12:20:53.402408 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9361 12:20:53.408982 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9362 12:20:53.412358 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9363 12:20:53.416107 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9364 12:20:53.422336 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9365 12:20:53.425754 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9366 12:20:53.432327 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9367 12:20:53.435805 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9368 12:20:53.439079 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9369 12:20:53.445808 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9370 12:20:53.449089 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9371 12:20:53.452571 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9372 12:20:53.459038 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9373 12:20:53.462331 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9374 12:20:53.465951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9375 12:20:53.469393 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9376 12:20:53.475743 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9377 12:20:53.478932 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9378 12:20:53.482688 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9379 12:20:53.489232 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9380 12:20:53.492577 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9381 12:20:53.499246 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9382 12:20:53.502525 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9383 12:20:53.505801 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9384 12:20:53.512456 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9385 12:20:53.515761 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9386 12:20:53.519048 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9387 12:20:53.525648 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9388 12:20:53.529301 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9389 12:20:53.535707 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9390 12:20:53.539046 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9391 12:20:53.542564 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9392 12:20:53.548980 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9393 12:20:53.552638 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9394 12:20:53.559134 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9395 12:20:53.562322 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9396 12:20:53.566179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9397 12:20:53.572695 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9398 12:20:53.575720 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9399 12:20:53.579095 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9400 12:20:53.585643 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9401 12:20:53.589315 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9402 12:20:53.595678 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9403 12:20:53.599020 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9404 12:20:53.602487 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9405 12:20:53.609133 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9406 12:20:53.612399 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9407 12:20:53.619118 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9408 12:20:53.622549 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9409 12:20:53.626232 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9410 12:20:53.632577 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9411 12:20:53.635775 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9412 12:20:53.639396 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9413 12:20:53.645996 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9414 12:20:53.649273 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9415 12:20:53.655659 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9416 12:20:53.658928 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9417 12:20:53.662341 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9418 12:20:53.669338 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9419 12:20:53.672286 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9420 12:20:53.678879 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9421 12:20:53.682070 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9422 12:20:53.685399 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9423 12:20:53.692291 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9424 12:20:53.695481 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9425 12:20:53.698816 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9426 12:20:53.705293 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9427 12:20:53.708480 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9428 12:20:53.715086 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9429 12:20:53.718450 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9430 12:20:53.725391 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9431 12:20:53.728589 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9432 12:20:53.731945 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9433 12:20:53.738469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9434 12:20:53.741877 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9435 12:20:53.745074 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9436 12:20:53.751710 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9437 12:20:53.754978 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9438 12:20:53.761689 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9439 12:20:53.764856 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9440 12:20:53.768072 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9441 12:20:53.774935 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9442 12:20:53.778094 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9443 12:20:53.784784 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9444 12:20:53.788094 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9445 12:20:53.794903 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9446 12:20:53.798231 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9447 12:20:53.801570 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9448 12:20:53.808012 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9449 12:20:53.811502 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9450 12:20:53.817910 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9451 12:20:53.821241 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9452 12:20:53.827870 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9453 12:20:53.831199 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9454 12:20:53.834670 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9455 12:20:53.841112 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9456 12:20:53.844596 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9457 12:20:53.851055 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9458 12:20:53.854477 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9459 12:20:53.857871 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9460 12:20:53.864723 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9461 12:20:53.867803 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9462 12:20:53.874366 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9463 12:20:53.877448 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9464 12:20:53.884318 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9465 12:20:53.887628 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9466 12:20:53.890814 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9467 12:20:53.897534 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9468 12:20:53.901109 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9469 12:20:53.907323 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9470 12:20:53.910603 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9471 12:20:53.917374 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9472 12:20:53.920815 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9473 12:20:53.923906 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9474 12:20:53.930720 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9475 12:20:53.934058 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9476 12:20:53.940734 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9477 12:20:53.944068 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9478 12:20:53.947338 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9479 12:20:53.953944 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9480 12:20:53.957474 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9481 12:20:53.963902 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9482 12:20:53.967189 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9483 12:20:53.970501 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9484 12:20:53.973847 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9485 12:20:53.977108 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9486 12:20:53.983768 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9487 12:20:53.986986 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9488 12:20:53.993668 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9489 12:20:53.997014 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9490 12:20:54.000373 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9491 12:20:54.007014 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9492 12:20:54.010433 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9493 12:20:54.013770 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9494 12:20:54.020156 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9495 12:20:54.023722 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9496 12:20:54.027072 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9497 12:20:54.033528 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9498 12:20:54.036667 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9499 12:20:54.043368 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9500 12:20:54.046860 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9501 12:20:54.049877 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9502 12:20:54.056484 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9503 12:20:54.059937 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9504 12:20:54.063093 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9505 12:20:54.069974 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9506 12:20:54.073369 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9507 12:20:54.079773 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9508 12:20:54.083279 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9509 12:20:54.086891 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9510 12:20:54.093027 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9511 12:20:54.096299 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9512 12:20:54.099518 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9513 12:20:54.106212 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9514 12:20:54.109513 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9515 12:20:54.115978 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9516 12:20:54.119366 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9517 12:20:54.122614 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9518 12:20:54.129405 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9519 12:20:54.132727 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9520 12:20:54.136090 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9521 12:20:54.142706 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9522 12:20:54.145978 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9523 12:20:54.149184 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9524 12:20:54.152779 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9525 12:20:54.159128 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9526 12:20:54.162353 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9527 12:20:54.165717 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9528 12:20:54.169153 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9529 12:20:54.175743 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9530 12:20:54.178919 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9531 12:20:54.182280 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9532 12:20:54.185697 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9533 12:20:54.192194 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9534 12:20:54.195472 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9535 12:20:54.198964 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9536 12:20:54.205604 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9537 12:20:54.209161 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9538 12:20:54.215403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9539 12:20:54.218708 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9540 12:20:54.222470 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9541 12:20:54.228913 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9542 12:20:54.232090 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9543 12:20:54.238608 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9544 12:20:54.242109 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9545 12:20:54.245318 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9546 12:20:54.252085 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9547 12:20:54.255320 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9548 12:20:54.261960 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9549 12:20:54.265375 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9550 12:20:54.268913 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9551 12:20:54.275368 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9552 12:20:54.278558 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9553 12:20:54.285156 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9554 12:20:54.288642 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9555 12:20:54.295214 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9556 12:20:54.298633 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9557 12:20:54.302266 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9558 12:20:54.308440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9559 12:20:54.311697 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9560 12:20:54.318690 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9561 12:20:54.321926 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9562 12:20:54.325025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9563 12:20:54.331830 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9564 12:20:54.335398 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9565 12:20:54.341795 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9566 12:20:54.345155 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9567 12:20:54.348420 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9568 12:20:54.354802 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9569 12:20:54.358133 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9570 12:20:54.364788 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9571 12:20:54.368017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9572 12:20:54.374817 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9573 12:20:54.378036 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9574 12:20:54.381732 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9575 12:20:54.388028 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9576 12:20:54.391397 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9577 12:20:54.398088 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9578 12:20:54.401273 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9579 12:20:54.404690 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9580 12:20:54.411211 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9581 12:20:54.414644 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9582 12:20:54.418078 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9583 12:20:54.424749 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9584 12:20:54.427843 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9585 12:20:54.434436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9586 12:20:54.437919 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9587 12:20:54.444380 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9588 12:20:54.447727 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9589 12:20:54.454330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9590 12:20:54.457647 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9591 12:20:54.461360 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9592 12:20:54.467766 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9593 12:20:54.470952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9594 12:20:54.477535 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9595 12:20:54.481095 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9596 12:20:54.484195 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9597 12:20:54.490868 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9598 12:20:54.494254 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9599 12:20:54.497675 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9600 12:20:54.504123 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9601 12:20:54.507469 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9602 12:20:54.514248 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9603 12:20:54.517616 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9604 12:20:54.523809 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9605 12:20:54.527572 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9606 12:20:54.530688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9607 12:20:54.536911 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9608 12:20:54.540204 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9609 12:20:54.546937 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9610 12:20:54.550115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9611 12:20:54.556756 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9612 12:20:54.560067 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9613 12:20:54.566893 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9614 12:20:54.570048 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9615 12:20:54.573460 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9616 12:20:54.579850 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9617 12:20:54.583200 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9618 12:20:54.590214 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9619 12:20:54.593194 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9620 12:20:54.599924 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9621 12:20:54.603401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9622 12:20:54.606571 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9623 12:20:54.613330 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9624 12:20:54.616356 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9625 12:20:54.623056 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9626 12:20:54.626258 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9627 12:20:54.632698 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9628 12:20:54.636316 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9629 12:20:54.642982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9630 12:20:54.646294 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9631 12:20:54.649746 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9632 12:20:54.656101 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9633 12:20:54.659492 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9634 12:20:54.665805 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9635 12:20:54.669369 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9636 12:20:54.675995 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9637 12:20:54.679023 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9638 12:20:54.685682 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9639 12:20:54.689070 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9640 12:20:54.692233 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9641 12:20:54.699220 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9642 12:20:54.702213 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9643 12:20:54.709086 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9644 12:20:54.712270 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9645 12:20:54.718791 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9646 12:20:54.722278 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9647 12:20:54.725440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9648 12:20:54.732203 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9649 12:20:54.735399 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9650 12:20:54.741957 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9651 12:20:54.745266 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9652 12:20:54.751825 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9653 12:20:54.755232 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9654 12:20:54.761731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9655 12:20:54.765218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9656 12:20:54.768497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9657 12:20:54.775105 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9658 12:20:54.778337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9659 12:20:54.785111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9660 12:20:54.788172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9661 12:20:54.794811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9662 12:20:54.798165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9663 12:20:54.804644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9664 12:20:54.808336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9665 12:20:54.814632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9666 12:20:54.817856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9667 12:20:54.824542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9668 12:20:54.827834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9669 12:20:54.834219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9670 12:20:54.837416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9671 12:20:54.844382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9672 12:20:54.847362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9673 12:20:54.854213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9674 12:20:54.857321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9675 12:20:54.863815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9676 12:20:54.867261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9677 12:20:54.873979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9678 12:20:54.877160 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9679 12:20:54.884113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9680 12:20:54.887184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9681 12:20:54.893783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9682 12:20:54.897190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9683 12:20:54.903612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9684 12:20:54.907212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9685 12:20:54.913661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9686 12:20:54.916914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9687 12:20:54.920662 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9688 12:20:54.923679 INFO: [APUAPC] vio 0
9689 12:20:54.930228 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9690 12:20:54.933680 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9691 12:20:54.936811 INFO: [APUAPC] D0_APC_0: 0x400510
9692 12:20:54.940141 INFO: [APUAPC] D0_APC_1: 0x0
9693 12:20:54.943292 INFO: [APUAPC] D0_APC_2: 0x1540
9694 12:20:54.947055 INFO: [APUAPC] D0_APC_3: 0x0
9695 12:20:54.950076 INFO: [APUAPC] D1_APC_0: 0xffffffff
9696 12:20:54.953358 INFO: [APUAPC] D1_APC_1: 0xffffffff
9697 12:20:54.956895 INFO: [APUAPC] D1_APC_2: 0x3fffff
9698 12:20:54.960144 INFO: [APUAPC] D1_APC_3: 0x0
9699 12:20:54.963174 INFO: [APUAPC] D2_APC_0: 0xffffffff
9700 12:20:54.966328 INFO: [APUAPC] D2_APC_1: 0xffffffff
9701 12:20:54.969697 INFO: [APUAPC] D2_APC_2: 0x3fffff
9702 12:20:54.973128 INFO: [APUAPC] D2_APC_3: 0x0
9703 12:20:54.976364 INFO: [APUAPC] D3_APC_0: 0xffffffff
9704 12:20:54.979603 INFO: [APUAPC] D3_APC_1: 0xffffffff
9705 12:20:54.982942 INFO: [APUAPC] D3_APC_2: 0x3fffff
9706 12:20:54.986765 INFO: [APUAPC] D3_APC_3: 0x0
9707 12:20:54.989707 INFO: [APUAPC] D4_APC_0: 0xffffffff
9708 12:20:54.992892 INFO: [APUAPC] D4_APC_1: 0xffffffff
9709 12:20:54.996299 INFO: [APUAPC] D4_APC_2: 0x3fffff
9710 12:20:54.996382 INFO: [APUAPC] D4_APC_3: 0x0
9711 12:20:55.002854 INFO: [APUAPC] D5_APC_0: 0xffffffff
9712 12:20:55.006239 INFO: [APUAPC] D5_APC_1: 0xffffffff
9713 12:20:55.009310 INFO: [APUAPC] D5_APC_2: 0x3fffff
9714 12:20:55.009394 INFO: [APUAPC] D5_APC_3: 0x0
9715 12:20:55.013120 INFO: [APUAPC] D6_APC_0: 0xffffffff
9716 12:20:55.019288 INFO: [APUAPC] D6_APC_1: 0xffffffff
9717 12:20:55.022675 INFO: [APUAPC] D6_APC_2: 0x3fffff
9718 12:20:55.022760 INFO: [APUAPC] D6_APC_3: 0x0
9719 12:20:55.025898 INFO: [APUAPC] D7_APC_0: 0xffffffff
9720 12:20:55.029284 INFO: [APUAPC] D7_APC_1: 0xffffffff
9721 12:20:55.032786 INFO: [APUAPC] D7_APC_2: 0x3fffff
9722 12:20:55.035777 INFO: [APUAPC] D7_APC_3: 0x0
9723 12:20:55.039638 INFO: [APUAPC] D8_APC_0: 0xffffffff
9724 12:20:55.042767 INFO: [APUAPC] D8_APC_1: 0xffffffff
9725 12:20:55.045962 INFO: [APUAPC] D8_APC_2: 0x3fffff
9726 12:20:55.049331 INFO: [APUAPC] D8_APC_3: 0x0
9727 12:20:55.052516 INFO: [APUAPC] D9_APC_0: 0xffffffff
9728 12:20:55.056000 INFO: [APUAPC] D9_APC_1: 0xffffffff
9729 12:20:55.059220 INFO: [APUAPC] D9_APC_2: 0x3fffff
9730 12:20:55.062394 INFO: [APUAPC] D9_APC_3: 0x0
9731 12:20:55.065770 INFO: [APUAPC] D10_APC_0: 0xffffffff
9732 12:20:55.068835 INFO: [APUAPC] D10_APC_1: 0xffffffff
9733 12:20:55.072302 INFO: [APUAPC] D10_APC_2: 0x3fffff
9734 12:20:55.075385 INFO: [APUAPC] D10_APC_3: 0x0
9735 12:20:55.078772 INFO: [APUAPC] D11_APC_0: 0xffffffff
9736 12:20:55.082278 INFO: [APUAPC] D11_APC_1: 0xffffffff
9737 12:20:55.085497 INFO: [APUAPC] D11_APC_2: 0x3fffff
9738 12:20:55.088989 INFO: [APUAPC] D11_APC_3: 0x0
9739 12:20:55.092128 INFO: [APUAPC] D12_APC_0: 0xffffffff
9740 12:20:55.095287 INFO: [APUAPC] D12_APC_1: 0xffffffff
9741 12:20:55.098646 INFO: [APUAPC] D12_APC_2: 0x3fffff
9742 12:20:55.101832 INFO: [APUAPC] D12_APC_3: 0x0
9743 12:20:55.105511 INFO: [APUAPC] D13_APC_0: 0xffffffff
9744 12:20:55.108510 INFO: [APUAPC] D13_APC_1: 0xffffffff
9745 12:20:55.111875 INFO: [APUAPC] D13_APC_2: 0x3fffff
9746 12:20:55.114972 INFO: [APUAPC] D13_APC_3: 0x0
9747 12:20:55.118687 INFO: [APUAPC] D14_APC_0: 0xffffffff
9748 12:20:55.121729 INFO: [APUAPC] D14_APC_1: 0xffffffff
9749 12:20:55.128300 INFO: [APUAPC] D14_APC_2: 0x3fffff
9750 12:20:55.128384 INFO: [APUAPC] D14_APC_3: 0x0
9751 12:20:55.131845 INFO: [APUAPC] D15_APC_0: 0xffffffff
9752 12:20:55.138351 INFO: [APUAPC] D15_APC_1: 0xffffffff
9753 12:20:55.141475 INFO: [APUAPC] D15_APC_2: 0x3fffff
9754 12:20:55.141557 INFO: [APUAPC] D15_APC_3: 0x0
9755 12:20:55.145300 INFO: [APUAPC] APC_CON: 0x4
9756 12:20:55.148520 INFO: [NOCDAPC] D0_APC_0: 0x0
9757 12:20:55.151631 INFO: [NOCDAPC] D0_APC_1: 0x0
9758 12:20:55.155034 INFO: [NOCDAPC] D1_APC_0: 0x0
9759 12:20:55.158167 INFO: [NOCDAPC] D1_APC_1: 0xfff
9760 12:20:55.161364 INFO: [NOCDAPC] D2_APC_0: 0x0
9761 12:20:55.164632 INFO: [NOCDAPC] D2_APC_1: 0xfff
9762 12:20:55.168039 INFO: [NOCDAPC] D3_APC_0: 0x0
9763 12:20:55.171356 INFO: [NOCDAPC] D3_APC_1: 0xfff
9764 12:20:55.171438 INFO: [NOCDAPC] D4_APC_0: 0x0
9765 12:20:55.174680 INFO: [NOCDAPC] D4_APC_1: 0xfff
9766 12:20:55.178095 INFO: [NOCDAPC] D5_APC_0: 0x0
9767 12:20:55.181234 INFO: [NOCDAPC] D5_APC_1: 0xfff
9768 12:20:55.184550 INFO: [NOCDAPC] D6_APC_0: 0x0
9769 12:20:55.187839 INFO: [NOCDAPC] D6_APC_1: 0xfff
9770 12:20:55.191127 INFO: [NOCDAPC] D7_APC_0: 0x0
9771 12:20:55.194481 INFO: [NOCDAPC] D7_APC_1: 0xfff
9772 12:20:55.198182 INFO: [NOCDAPC] D8_APC_0: 0x0
9773 12:20:55.201065 INFO: [NOCDAPC] D8_APC_1: 0xfff
9774 12:20:55.204375 INFO: [NOCDAPC] D9_APC_0: 0x0
9775 12:20:55.204458 INFO: [NOCDAPC] D9_APC_1: 0xfff
9776 12:20:55.208047 INFO: [NOCDAPC] D10_APC_0: 0x0
9777 12:20:55.211108 INFO: [NOCDAPC] D10_APC_1: 0xfff
9778 12:20:55.214305 INFO: [NOCDAPC] D11_APC_0: 0x0
9779 12:20:55.217425 INFO: [NOCDAPC] D11_APC_1: 0xfff
9780 12:20:55.220887 INFO: [NOCDAPC] D12_APC_0: 0x0
9781 12:20:55.224298 INFO: [NOCDAPC] D12_APC_1: 0xfff
9782 12:20:55.227547 INFO: [NOCDAPC] D13_APC_0: 0x0
9783 12:20:55.230872 INFO: [NOCDAPC] D13_APC_1: 0xfff
9784 12:20:55.234267 INFO: [NOCDAPC] D14_APC_0: 0x0
9785 12:20:55.237436 INFO: [NOCDAPC] D14_APC_1: 0xfff
9786 12:20:55.241180 INFO: [NOCDAPC] D15_APC_0: 0x0
9787 12:20:55.244105 INFO: [NOCDAPC] D15_APC_1: 0xfff
9788 12:20:55.247377 INFO: [NOCDAPC] APC_CON: 0x4
9789 12:20:55.251010 INFO: [APUAPC] set_apusys_apc done
9790 12:20:55.251094 INFO: [DEVAPC] devapc_init done
9791 12:20:55.257458 INFO: GICv3 without legacy support detected.
9792 12:20:55.260909 INFO: ARM GICv3 driver initialized in EL3
9793 12:20:55.263933 INFO: Maximum SPI INTID supported: 639
9794 12:20:55.267325 INFO: BL31: Initializing runtime services
9795 12:20:55.273792 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9796 12:20:55.277129 INFO: SPM: enable CPC mode
9797 12:20:55.280552 INFO: mcdi ready for mcusys-off-idle and system suspend
9798 12:20:55.287134 INFO: BL31: Preparing for EL3 exit to normal world
9799 12:20:55.290512 INFO: Entry point address = 0x80000000
9800 12:20:55.293978 INFO: SPSR = 0x8
9801 12:20:55.298044
9802 12:20:55.298127
9803 12:20:55.298211
9804 12:20:55.301145 Starting depthcharge on Spherion...
9805 12:20:55.301227
9806 12:20:55.301311 Wipe memory regions:
9807 12:20:55.301390
9808 12:20:55.302052 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9809 12:20:55.302165 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9810 12:20:55.302257 Setting prompt string to ['asurada:']
9811 12:20:55.302376 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9812 12:20:55.304553 [0x00000040000000, 0x00000054600000)
9813 12:20:55.426941
9814 12:20:55.427100 [0x00000054660000, 0x00000080000000)
9815 12:20:55.687569
9816 12:20:55.687728 [0x000000821a7280, 0x000000ffe64000)
9817 12:20:56.432375
9818 12:20:56.432538 [0x00000100000000, 0x00000140000000)
9819 12:20:56.813338
9820 12:20:56.816603 Initializing XHCI USB controller at 0x11200000.
9821 12:20:57.855362
9822 12:20:57.858631 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9823 12:20:57.859212
9824 12:20:57.859694
9825 12:20:57.860296
9826 12:20:57.861193 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9828 12:20:57.962585 asurada: tftpboot 192.168.201.1 11893132/tftp-deploy-l4a7eacn/kernel/image.itb 11893132/tftp-deploy-l4a7eacn/kernel/cmdline
9829 12:20:57.962788 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9830 12:20:57.962905 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9831 12:20:57.967058 tftpboot 192.168.201.1 11893132/tftp-deploy-l4a7eacn/kernel/image.itp-deploy-l4a7eacn/kernel/cmdline
9832 12:20:57.967163
9833 12:20:57.967232 Waiting for link
9834 12:20:58.128270
9835 12:20:58.128880 R8152: Initializing
9836 12:20:58.129218
9837 12:20:58.131489 Version 9 (ocp_data = 6010)
9838 12:20:58.132036
9839 12:20:58.135085 R8152: Done initializing
9840 12:20:58.135640
9841 12:20:58.136091 Adding net device
9842 12:21:00.195264
9843 12:21:00.195836 done.
9844 12:21:00.196445
9845 12:21:00.197008 MAC: 00:e0:4c:68:03:bd
9846 12:21:00.197565
9847 12:21:00.198485 Sending DHCP discover... done.
9848 12:21:00.199014
9849 12:21:00.201405 Waiting for reply... done.
9850 12:21:00.201515
9851 12:21:00.204505 Sending DHCP request... done.
9852 12:21:00.204590
9853 12:21:00.204657 Waiting for reply... done.
9854 12:21:00.204718
9855 12:21:00.208280 My ip is 192.168.201.16
9856 12:21:00.208727
9857 12:21:00.211508 The DHCP server ip is 192.168.201.1
9858 12:21:00.212067
9859 12:21:00.214993 TFTP server IP predefined by user: 192.168.201.1
9860 12:21:00.215548
9861 12:21:00.221826 Bootfile predefined by user: 11893132/tftp-deploy-l4a7eacn/kernel/image.itb
9862 12:21:00.222390
9863 12:21:00.224925 Sending tftp read request... done.
9864 12:21:00.225377
9865 12:21:00.233619 Waiting for the transfer...
9866 12:21:00.234200
9867 12:21:00.631610 00000000 ################################################################
9868 12:21:00.631775
9869 12:21:00.926797 00080000 ################################################################
9870 12:21:00.926935
9871 12:21:01.218595 00100000 ################################################################
9872 12:21:01.218727
9873 12:21:01.495154 00180000 ################################################################
9874 12:21:01.495321
9875 12:21:01.765462 00200000 ################################################################
9876 12:21:01.765591
9877 12:21:02.043839 00280000 ################################################################
9878 12:21:02.044000
9879 12:21:02.294522 00300000 ################################################################
9880 12:21:02.294647
9881 12:21:02.572321 00380000 ################################################################
9882 12:21:02.572459
9883 12:21:02.869390 00400000 ################################################################
9884 12:21:02.869540
9885 12:21:03.172098 00480000 ################################################################
9886 12:21:03.172267
9887 12:21:03.474642 00500000 ################################################################
9888 12:21:03.474797
9889 12:21:03.778087 00580000 ################################################################
9890 12:21:03.778224
9891 12:21:04.080474 00600000 ################################################################
9892 12:21:04.080604
9893 12:21:04.377449 00680000 ################################################################
9894 12:21:04.377582
9895 12:21:04.665846 00700000 ################################################################
9896 12:21:04.665982
9897 12:21:04.921034 00780000 ################################################################
9898 12:21:04.921171
9899 12:21:05.185925 00800000 ################################################################
9900 12:21:05.186054
9901 12:21:05.464473 00880000 ################################################################
9902 12:21:05.464600
9903 12:21:05.838348 00900000 ################################################################
9904 12:21:05.839028
9905 12:21:06.221589 00980000 ################################################################
9906 12:21:06.222110
9907 12:21:06.638980 00a00000 ################################################################
9908 12:21:06.639491
9909 12:21:07.039209 00a80000 ################################################################
9910 12:21:07.039735
9911 12:21:07.353220 00b00000 ################################################################
9912 12:21:07.353357
9913 12:21:07.620019 00b80000 ################################################################
9914 12:21:07.620183
9915 12:21:07.879868 00c00000 ################################################################
9916 12:21:07.879998
9917 12:21:08.133286 00c80000 ################################################################
9918 12:21:08.133440
9919 12:21:08.388193 00d00000 ################################################################
9920 12:21:08.388373
9921 12:21:08.638728 00d80000 ################################################################
9922 12:21:08.638850
9923 12:21:08.888257 00e00000 ################################################################
9924 12:21:08.888395
9925 12:21:09.139727 00e80000 ################################################################
9926 12:21:09.139865
9927 12:21:09.394907 00f00000 ################################################################
9928 12:21:09.395069
9929 12:21:09.663127 00f80000 ################################################################
9930 12:21:09.663267
9931 12:21:09.920800 01000000 ################################################################
9932 12:21:09.920971
9933 12:21:10.177437 01080000 ################################################################
9934 12:21:10.177595
9935 12:21:10.442342 01100000 ################################################################
9936 12:21:10.442474
9937 12:21:10.709883 01180000 ################################################################
9938 12:21:10.710012
9939 12:21:10.970057 01200000 ################################################################
9940 12:21:10.970184
9941 12:21:11.231213 01280000 ################################################################
9942 12:21:11.231340
9943 12:21:11.478112 01300000 ################################################################
9944 12:21:11.478251
9945 12:21:11.746047 01380000 ################################################################
9946 12:21:11.746178
9947 12:21:12.017105 01400000 ################################################################
9948 12:21:12.017252
9949 12:21:12.279461 01480000 ################################################################
9950 12:21:12.279619
9951 12:21:12.541205 01500000 ################################################################
9952 12:21:12.541356
9953 12:21:12.799176 01580000 ################################################################
9954 12:21:12.799305
9955 12:21:13.062766 01600000 ################################################################
9956 12:21:13.062926
9957 12:21:13.325259 01680000 ################################################################
9958 12:21:13.325391
9959 12:21:13.581390 01700000 ################################################################
9960 12:21:13.581545
9961 12:21:13.847531 01780000 ################################################################
9962 12:21:13.847669
9963 12:21:14.109076 01800000 ################################################################
9964 12:21:14.109226
9965 12:21:14.371695 01880000 ################################################################
9966 12:21:14.371845
9967 12:21:14.633895 01900000 ################################################################
9968 12:21:14.634054
9969 12:21:14.891480 01980000 ################################################################
9970 12:21:14.891644
9971 12:21:15.150953 01a00000 ################################################################
9972 12:21:15.151105
9973 12:21:15.405526 01a80000 ################################################################
9974 12:21:15.405686
9975 12:21:15.665287 01b00000 ################################################################
9976 12:21:15.665426
9977 12:21:15.942528 01b80000 ################################################################
9978 12:21:15.942685
9979 12:21:16.205082 01c00000 ############################################################ done.
9980 12:21:16.205238
9981 12:21:16.208425 The bootfile was 29848750 bytes long.
9982 12:21:16.208530
9983 12:21:16.208625 Sending tftp read request... done.
9984 12:21:16.211807
9985 12:21:16.211907 Waiting for the transfer...
9986 12:21:16.211997
9987 12:21:16.215419 00000000 # done.
9988 12:21:16.215520
9989 12:21:16.221439 Command line loaded dynamically from TFTP file: 11893132/tftp-deploy-l4a7eacn/kernel/cmdline
9990 12:21:16.221542
9991 12:21:16.244873 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893132/extract-nfsrootfs-up4tc3au,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9992 12:21:16.244979
9993 12:21:16.245075 Loading FIT.
9994 12:21:16.245165
9995 12:21:16.248190 Image ramdisk-1 has 18751442 bytes.
9996 12:21:16.248264
9997 12:21:16.251293 Image fdt-1 has 47278 bytes.
9998 12:21:16.251392
9999 12:21:16.254642 Image kernel-1 has 11047994 bytes.
10000 12:21:16.254740
10001 12:21:16.264236 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10002 12:21:16.264316
10003 12:21:16.280918 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10004 12:21:16.281027
10005 12:21:16.287239 Choosing best match conf-1 for compat google,spherion-rev3.
10006 12:21:16.287341
10007 12:21:16.294559 Connected to device vid:did:rid of 1ae0:0028:00
10008 12:21:16.301361
10009 12:21:16.304819 tpm_get_response: command 0x17b, return code 0x0
10010 12:21:16.304920
10011 12:21:16.308007 ec_init: CrosEC protocol v3 supported (256, 248)
10012 12:21:16.312110
10013 12:21:16.315604 tpm_cleanup: add release locality here.
10014 12:21:16.315704
10015 12:21:16.315797 Shutting down all USB controllers.
10016 12:21:16.318883
10017 12:21:16.318980 Removing current net device
10018 12:21:16.319073
10019 12:21:16.325550 Exiting depthcharge with code 4 at timestamp: 49260293
10020 12:21:16.325651
10021 12:21:16.328933 LZMA decompressing kernel-1 to 0x821a6718
10022 12:21:16.329033
10023 12:21:16.331936 LZMA decompressing kernel-1 to 0x40000000
10024 12:21:17.719987
10025 12:21:17.720154 jumping to kernel
10026 12:21:17.721022 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10027 12:21:17.721149 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10028 12:21:17.721251 Setting prompt string to ['Linux version [0-9]']
10029 12:21:17.721384 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 12:21:17.721498 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10031 12:21:17.770128
10032 12:21:17.773653 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10033 12:21:17.777242 start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10034 12:21:17.777333 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10035 12:21:17.777402 Setting prompt string to []
10036 12:21:17.777477 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10037 12:21:17.777547 Using line separator: #'\n'#
10038 12:21:17.777637 No login prompt set.
10039 12:21:17.777721 Parsing kernel messages
10040 12:21:17.777842 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10041 12:21:17.777959 [login-action] Waiting for messages, (timeout 00:04:04)
10042 12:21:17.796867 [ 0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023
10043 12:21:17.799967 [ 0.000000] random: crng init done
10044 12:21:17.806530 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10045 12:21:17.809885 [ 0.000000] efi: UEFI not found.
10046 12:21:17.816353 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10047 12:21:17.822918 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10048 12:21:17.832935 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10049 12:21:17.842710 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10050 12:21:17.849510 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10051 12:21:17.855772 [ 0.000000] printk: bootconsole [mtk8250] enabled
10052 12:21:17.862461 [ 0.000000] NUMA: No NUMA configuration found
10053 12:21:17.869236 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10054 12:21:17.872492 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10055 12:21:17.875873 [ 0.000000] Zone ranges:
10056 12:21:17.882372 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10057 12:21:17.885684 [ 0.000000] DMA32 empty
10058 12:21:17.892209 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10059 12:21:17.895339 [ 0.000000] Movable zone start for each node
10060 12:21:17.898986 [ 0.000000] Early memory node ranges
10061 12:21:17.905433 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10062 12:21:17.912213 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10063 12:21:17.918604 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10064 12:21:17.925092 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10065 12:21:17.931898 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10066 12:21:17.938463 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10067 12:21:17.969081 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10068 12:21:17.975395 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10069 12:21:17.982123 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10070 12:21:17.985166 [ 0.000000] psci: probing for conduit method from DT.
10071 12:21:17.991896 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10072 12:21:17.994926 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10073 12:21:18.001557 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10074 12:21:18.004944 [ 0.000000] psci: SMC Calling Convention v1.2
10075 12:21:18.011556 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10076 12:21:18.015210 [ 0.000000] Detected VIPT I-cache on CPU0
10077 12:21:18.021595 [ 0.000000] CPU features: detected: GIC system register CPU interface
10078 12:21:18.028352 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10079 12:21:18.034826 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10080 12:21:18.041736 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10081 12:21:18.048138 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10082 12:21:18.058348 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10083 12:21:18.061291 [ 0.000000] alternatives: applying boot alternatives
10084 12:21:18.068070 [ 0.000000] Fallback order for Node 0: 0
10085 12:21:18.074753 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10086 12:21:18.077875 [ 0.000000] Policy zone: Normal
10087 12:21:18.101211 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893132/extract-nfsrootfs-up4tc3au,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10088 12:21:18.111247 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10089 12:21:18.121329 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10090 12:21:18.127471 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10091 12:21:18.134087 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10092 12:21:18.140696 <6>[ 0.000000] software IO TLB: area num 8.
10093 12:21:18.195408 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10094 12:21:18.275709 <6>[ 0.000000] Memory: 3836768K/4191232K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 321696K reserved, 32768K cma-reserved)
10095 12:21:18.282197 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10096 12:21:18.288573 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10097 12:21:18.291964 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10098 12:21:18.298589 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10099 12:21:18.305660 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10100 12:21:18.308477 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10101 12:21:18.318618 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10102 12:21:18.325144 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10103 12:21:18.331493 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10104 12:21:18.338555 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10105 12:21:18.341805 <6>[ 0.000000] GICv3: 608 SPIs implemented
10106 12:21:18.345000 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10107 12:21:18.351906 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10108 12:21:18.354992 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10109 12:21:18.361545 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10110 12:21:18.375088 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10111 12:21:18.388004 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10112 12:21:18.394585 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10113 12:21:18.402581 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10114 12:21:18.415801 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10115 12:21:18.422119 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10116 12:21:18.429148 <6>[ 0.009177] Console: colour dummy device 80x25
10117 12:21:18.438857 <6>[ 0.013931] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10118 12:21:18.445435 <6>[ 0.024374] pid_max: default: 32768 minimum: 301
10119 12:21:18.448695 <6>[ 0.029245] LSM: Security Framework initializing
10120 12:21:18.455124 <6>[ 0.034157] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10121 12:21:18.465454 <6>[ 0.041812] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10122 12:21:18.472023 <6>[ 0.051042] cblist_init_generic: Setting adjustable number of callback queues.
10123 12:21:18.478543 <6>[ 0.058482] cblist_init_generic: Setting shift to 3 and lim to 1.
10124 12:21:18.488308 <6>[ 0.064861] cblist_init_generic: Setting adjustable number of callback queues.
10125 12:21:18.491769 <6>[ 0.072288] cblist_init_generic: Setting shift to 3 and lim to 1.
10126 12:21:18.498213 <6>[ 0.078726] rcu: Hierarchical SRCU implementation.
10127 12:21:18.505248 <6>[ 0.083773] rcu: Max phase no-delay instances is 1000.
10128 12:21:18.511500 <6>[ 0.090789] EFI services will not be available.
10129 12:21:18.514940 <6>[ 0.095771] smp: Bringing up secondary CPUs ...
10130 12:21:18.522771 <6>[ 0.100818] Detected VIPT I-cache on CPU1
10131 12:21:18.529182 <6>[ 0.100887] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10132 12:21:18.535958 <6>[ 0.100916] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10133 12:21:18.539245 <6>[ 0.101250] Detected VIPT I-cache on CPU2
10134 12:21:18.546464 <6>[ 0.101299] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10135 12:21:18.555881 <6>[ 0.101314] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10136 12:21:18.558923 <6>[ 0.101574] Detected VIPT I-cache on CPU3
10137 12:21:18.565900 <6>[ 0.101620] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10138 12:21:18.572473 <6>[ 0.101633] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10139 12:21:18.575413 <6>[ 0.101939] CPU features: detected: Spectre-v4
10140 12:21:18.581981 <6>[ 0.101945] CPU features: detected: Spectre-BHB
10141 12:21:18.585576 <6>[ 0.101949] Detected PIPT I-cache on CPU4
10142 12:21:18.591940 <6>[ 0.102006] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10143 12:21:18.598876 <6>[ 0.102023] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10144 12:21:18.605095 <6>[ 0.102314] Detected PIPT I-cache on CPU5
10145 12:21:18.612021 <6>[ 0.102377] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10146 12:21:18.618488 <6>[ 0.102394] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10147 12:21:18.621590 <6>[ 0.102675] Detected PIPT I-cache on CPU6
10148 12:21:18.627959 <6>[ 0.102737] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10149 12:21:18.635288 <6>[ 0.102753] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10150 12:21:18.641429 <6>[ 0.103051] Detected PIPT I-cache on CPU7
10151 12:21:18.647894 <6>[ 0.103117] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10152 12:21:18.654879 <6>[ 0.103133] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10153 12:21:18.657982 <6>[ 0.103180] smp: Brought up 1 node, 8 CPUs
10154 12:21:18.664638 <6>[ 0.244585] SMP: Total of 8 processors activated.
10155 12:21:18.668128 <6>[ 0.249537] CPU features: detected: 32-bit EL0 Support
10156 12:21:18.677766 <6>[ 0.254899] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10157 12:21:18.684425 <6>[ 0.263754] CPU features: detected: Common not Private translations
10158 12:21:18.691132 <6>[ 0.270231] CPU features: detected: CRC32 instructions
10159 12:21:18.694451 <6>[ 0.275582] CPU features: detected: RCpc load-acquire (LDAPR)
10160 12:21:18.701119 <6>[ 0.281542] CPU features: detected: LSE atomic instructions
10161 12:21:18.707514 <6>[ 0.287324] CPU features: detected: Privileged Access Never
10162 12:21:18.714350 <6>[ 0.293104] CPU features: detected: RAS Extension Support
10163 12:21:18.720986 <6>[ 0.298714] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10164 12:21:18.724015 <6>[ 0.305934] CPU: All CPU(s) started at EL2
10165 12:21:18.730967 <6>[ 0.310250] alternatives: applying system-wide alternatives
10166 12:21:18.739485 <6>[ 0.320146] devtmpfs: initialized
10167 12:21:18.754517 <6>[ 0.328316] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10168 12:21:18.760874 <6>[ 0.338276] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10169 12:21:18.767512 <6>[ 0.346451] pinctrl core: initialized pinctrl subsystem
10170 12:21:18.770601 <6>[ 0.353140] DMI not present or invalid.
10171 12:21:18.777547 <6>[ 0.357543] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10172 12:21:18.787252 <6>[ 0.364398] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10173 12:21:18.793970 <6>[ 0.371837] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10174 12:21:18.803863 <6>[ 0.379928] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10175 12:21:18.807155 <6>[ 0.388083] audit: initializing netlink subsys (disabled)
10176 12:21:18.817099 <5>[ 0.393777] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10177 12:21:18.823616 <6>[ 0.394473] thermal_sys: Registered thermal governor 'step_wise'
10178 12:21:18.830279 <6>[ 0.401744] thermal_sys: Registered thermal governor 'power_allocator'
10179 12:21:18.833589 <6>[ 0.407999] cpuidle: using governor menu
10180 12:21:18.840255 <6>[ 0.418962] NET: Registered PF_QIPCRTR protocol family
10181 12:21:18.846939 <6>[ 0.424451] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10182 12:21:18.853236 <6>[ 0.431555] ASID allocator initialised with 32768 entries
10183 12:21:18.856378 <6>[ 0.438106] Serial: AMBA PL011 UART driver
10184 12:21:18.866341 <4>[ 0.446925] Trying to register duplicate clock ID: 134
10185 12:21:18.920920 <6>[ 0.504104] KASLR enabled
10186 12:21:18.934521 <6>[ 0.511789] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10187 12:21:18.941436 <6>[ 0.518803] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10188 12:21:18.947731 <6>[ 0.525294] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10189 12:21:18.954498 <6>[ 0.532299] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10190 12:21:18.961105 <6>[ 0.538788] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10191 12:21:18.967367 <6>[ 0.545794] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10192 12:21:18.974213 <6>[ 0.552281] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10193 12:21:18.980694 <6>[ 0.559287] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10194 12:21:18.983773 <6>[ 0.566733] ACPI: Interpreter disabled.
10195 12:21:18.992738 <6>[ 0.573094] iommu: Default domain type: Translated
10196 12:21:18.999383 <6>[ 0.578249] iommu: DMA domain TLB invalidation policy: strict mode
10197 12:21:19.002404 <5>[ 0.584913] SCSI subsystem initialized
10198 12:21:19.009193 <6>[ 0.589172] usbcore: registered new interface driver usbfs
10199 12:21:19.015560 <6>[ 0.594905] usbcore: registered new interface driver hub
10200 12:21:19.018883 <6>[ 0.600460] usbcore: registered new device driver usb
10201 12:21:19.026047 <6>[ 0.606577] pps_core: LinuxPPS API ver. 1 registered
10202 12:21:19.036149 <6>[ 0.611770] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10203 12:21:19.039255 <6>[ 0.621115] PTP clock support registered
10204 12:21:19.042486 <6>[ 0.625357] EDAC MC: Ver: 3.0.0
10205 12:21:19.049986 <6>[ 0.630532] FPGA manager framework
10206 12:21:19.056459 <6>[ 0.634209] Advanced Linux Sound Architecture Driver Initialized.
10207 12:21:19.059747 <6>[ 0.640987] vgaarb: loaded
10208 12:21:19.066416 <6>[ 0.644174] clocksource: Switched to clocksource arch_sys_counter
10209 12:21:19.069858 <5>[ 0.650625] VFS: Disk quotas dquot_6.6.0
10210 12:21:19.076413 <6>[ 0.654808] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10211 12:21:19.079925 <6>[ 0.662000] pnp: PnP ACPI: disabled
10212 12:21:19.088529 <6>[ 0.668681] NET: Registered PF_INET protocol family
10213 12:21:19.094530 <6>[ 0.674064] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10214 12:21:19.106815 <6>[ 0.684081] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10215 12:21:19.116892 <6>[ 0.692869] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10216 12:21:19.123223 <6>[ 0.700842] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10217 12:21:19.129862 <6>[ 0.709246] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10218 12:21:19.140580 <6>[ 0.717907] TCP: Hash tables configured (established 32768 bind 32768)
10219 12:21:19.147069 <6>[ 0.724767] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10220 12:21:19.153729 <6>[ 0.731786] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10221 12:21:19.160153 <6>[ 0.739312] NET: Registered PF_UNIX/PF_LOCAL protocol family
10222 12:21:19.166935 <6>[ 0.745459] RPC: Registered named UNIX socket transport module.
10223 12:21:19.170221 <6>[ 0.751614] RPC: Registered udp transport module.
10224 12:21:19.176752 <6>[ 0.756548] RPC: Registered tcp transport module.
10225 12:21:19.183255 <6>[ 0.761481] RPC: Registered tcp NFSv4.1 backchannel transport module.
10226 12:21:19.186936 <6>[ 0.768147] PCI: CLS 0 bytes, default 64
10227 12:21:19.190241 <6>[ 0.772477] Unpacking initramfs...
10228 12:21:19.199872 <6>[ 0.776621] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10229 12:21:19.206304 <6>[ 0.785258] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10230 12:21:19.213432 <6>[ 0.794106] kvm [1]: IPA Size Limit: 40 bits
10231 12:21:19.216937 <6>[ 0.798634] kvm [1]: GICv3: no GICV resource entry
10232 12:21:19.223299 <6>[ 0.803657] kvm [1]: disabling GICv2 emulation
10233 12:21:19.229822 <6>[ 0.808348] kvm [1]: GIC system register CPU interface enabled
10234 12:21:19.233634 <6>[ 0.814513] kvm [1]: vgic interrupt IRQ18
10235 12:21:19.239685 <6>[ 0.818869] kvm [1]: VHE mode initialized successfully
10236 12:21:19.243080 <5>[ 0.825355] Initialise system trusted keyrings
10237 12:21:19.249792 <6>[ 0.830169] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10238 12:21:19.259625 <6>[ 0.840108] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10239 12:21:19.266221 <5>[ 0.846481] NFS: Registering the id_resolver key type
10240 12:21:19.269328 <5>[ 0.851780] Key type id_resolver registered
10241 12:21:19.275969 <5>[ 0.856197] Key type id_legacy registered
10242 12:21:19.282638 <6>[ 0.860474] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10243 12:21:19.289094 <6>[ 0.867396] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10244 12:21:19.296022 <6>[ 0.875094] 9p: Installing v9fs 9p2000 file system support
10245 12:21:19.332077 <5>[ 0.912622] Key type asymmetric registered
10246 12:21:19.335423 <5>[ 0.916952] Asymmetric key parser 'x509' registered
10247 12:21:19.345522 <6>[ 0.922086] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10248 12:21:19.348404 <6>[ 0.929702] io scheduler mq-deadline registered
10249 12:21:19.351625 <6>[ 0.934461] io scheduler kyber registered
10250 12:21:19.370911 <6>[ 0.951571] EINJ: ACPI disabled.
10251 12:21:19.403889 <4>[ 0.977265] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10252 12:21:19.413136 <4>[ 0.987888] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10253 12:21:19.427876 <6>[ 1.008588] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10254 12:21:19.436038 <6>[ 1.016581] printk: console [ttyS0] disabled
10255 12:21:19.464016 <6>[ 1.041223] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10256 12:21:19.470762 <6>[ 1.050696] printk: console [ttyS0] enabled
10257 12:21:19.473774 <6>[ 1.050696] printk: console [ttyS0] enabled
10258 12:21:19.480521 <6>[ 1.059589] printk: bootconsole [mtk8250] disabled
10259 12:21:19.483604 <6>[ 1.059589] printk: bootconsole [mtk8250] disabled
10260 12:21:19.490350 <6>[ 1.070604] SuperH (H)SCI(F) driver initialized
10261 12:21:19.493800 <6>[ 1.075861] msm_serial: driver initialized
10262 12:21:19.507367 <6>[ 1.084820] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10263 12:21:19.517227 <6>[ 1.093363] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10264 12:21:19.524319 <6>[ 1.101906] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10265 12:21:19.534145 <6>[ 1.110533] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10266 12:21:19.544082 <6>[ 1.119244] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10267 12:21:19.550536 <6>[ 1.127962] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10268 12:21:19.560466 <6>[ 1.136503] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10269 12:21:19.566945 <6>[ 1.145296] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10270 12:21:19.576954 <6>[ 1.153837] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10271 12:21:19.588739 <6>[ 1.169282] loop: module loaded
10272 12:21:19.594974 <6>[ 1.175237] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10273 12:21:19.617814 <4>[ 1.198468] mtk-pmic-keys: Failed to locate of_node [id: -1]
10274 12:21:19.624669 <6>[ 1.205310] megasas: 07.719.03.00-rc1
10275 12:21:19.634374 <6>[ 1.214768] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10276 12:21:19.643046 <6>[ 1.223557] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10277 12:21:19.659618 <6>[ 1.240130] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10278 12:21:19.715269 <6>[ 1.289193] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10279 12:21:19.972805 <6>[ 1.553648] Freeing initrd memory: 18308K
10280 12:21:19.984559 <6>[ 1.565270] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10281 12:21:19.995905 <6>[ 1.576198] tun: Universal TUN/TAP device driver, 1.6
10282 12:21:19.998808 <6>[ 1.582257] thunder_xcv, ver 1.0
10283 12:21:20.002273 <6>[ 1.585762] thunder_bgx, ver 1.0
10284 12:21:20.005507 <6>[ 1.589255] nicpf, ver 1.0
10285 12:21:20.016044 <6>[ 1.593277] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10286 12:21:20.019130 <6>[ 1.600753] hns3: Copyright (c) 2017 Huawei Corporation.
10287 12:21:20.025850 <6>[ 1.606340] hclge is initializing
10288 12:21:20.029346 <6>[ 1.609919] e1000: Intel(R) PRO/1000 Network Driver
10289 12:21:20.035936 <6>[ 1.615049] e1000: Copyright (c) 1999-2006 Intel Corporation.
10290 12:21:20.039157 <6>[ 1.621061] e1000e: Intel(R) PRO/1000 Network Driver
10291 12:21:20.046151 <6>[ 1.626277] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10292 12:21:20.052648 <6>[ 1.632465] igb: Intel(R) Gigabit Ethernet Network Driver
10293 12:21:20.059227 <6>[ 1.638115] igb: Copyright (c) 2007-2014 Intel Corporation.
10294 12:21:20.065718 <6>[ 1.643950] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10295 12:21:20.072663 <6>[ 1.650469] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10296 12:21:20.076047 <6>[ 1.656937] sky2: driver version 1.30
10297 12:21:20.082539 <6>[ 1.661924] VFIO - User Level meta-driver version: 0.3
10298 12:21:20.089429 <6>[ 1.670188] usbcore: registered new interface driver usb-storage
10299 12:21:20.096076 <6>[ 1.676631] usbcore: registered new device driver onboard-usb-hub
10300 12:21:20.105005 <6>[ 1.685751] mt6397-rtc mt6359-rtc: registered as rtc0
10301 12:21:20.114944 <6>[ 1.691218] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:21:20 UTC (1698409280)
10302 12:21:20.118123 <6>[ 1.700780] i2c_dev: i2c /dev entries driver
10303 12:21:20.135350 <6>[ 1.712465] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10304 12:21:20.154823 <6>[ 1.735445] cpu cpu0: EM: created perf domain
10305 12:21:20.158093 <6>[ 1.740367] cpu cpu4: EM: created perf domain
10306 12:21:20.165037 <6>[ 1.745803] sdhci: Secure Digital Host Controller Interface driver
10307 12:21:20.171771 <6>[ 1.752236] sdhci: Copyright(c) Pierre Ossman
10308 12:21:20.178359 <6>[ 1.757165] Synopsys Designware Multimedia Card Interface Driver
10309 12:21:20.185312 <6>[ 1.763764] sdhci-pltfm: SDHCI platform and OF driver helper
10310 12:21:20.188567 <6>[ 1.763834] mmc0: CQHCI version 5.10
10311 12:21:20.195085 <6>[ 1.774103] ledtrig-cpu: registered to indicate activity on CPUs
10312 12:21:20.201401 <6>[ 1.781156] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10313 12:21:20.208093 <6>[ 1.788199] usbcore: registered new interface driver usbhid
10314 12:21:20.211519 <6>[ 1.794019] usbhid: USB HID core driver
10315 12:21:20.217961 <6>[ 1.798208] spi_master spi0: will run message pump with realtime priority
10316 12:21:20.260694 <6>[ 1.834973] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10317 12:21:20.276135 <6>[ 1.849902] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10318 12:21:20.284780 <6>[ 1.865454] cros-ec-spi spi0.0: Chrome EC device registered
10319 12:21:20.291793 <6>[ 1.871504] mmc0: Command Queue Engine enabled
10320 12:21:20.298169 <6>[ 1.876242] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10321 12:21:20.301338 <6>[ 1.883866] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10322 12:21:20.312338 <6>[ 1.893211] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10323 12:21:20.319689 <6>[ 1.900550] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10324 12:21:20.329602 <6>[ 1.903605] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10325 12:21:20.333201 <6>[ 1.906463] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10326 12:21:20.339529 <6>[ 1.916044] NET: Registered PF_PACKET protocol family
10327 12:21:20.346350 <6>[ 1.920947] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10328 12:21:20.349594 <6>[ 1.925668] 9pnet: Installing 9P2000 support
10329 12:21:20.356656 <5>[ 1.936675] Key type dns_resolver registered
10330 12:21:20.359668 <6>[ 1.941601] registered taskstats version 1
10331 12:21:20.366282 <5>[ 1.945976] Loading compiled-in X.509 certificates
10332 12:21:20.393264 <4>[ 1.967401] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10333 12:21:20.403478 <4>[ 1.978101] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10334 12:21:20.409866 <3>[ 1.988632] debugfs: File 'uA_load' in directory '/' already present!
10335 12:21:20.416681 <3>[ 1.995401] debugfs: File 'min_uV' in directory '/' already present!
10336 12:21:20.423388 <3>[ 2.002023] debugfs: File 'max_uV' in directory '/' already present!
10337 12:21:20.429838 <3>[ 2.008637] debugfs: File 'constraint_flags' in directory '/' already present!
10338 12:21:20.441039 <3>[ 2.018598] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10339 12:21:20.451000 <6>[ 2.031773] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10340 12:21:20.457932 <6>[ 2.038766] xhci-mtk 11200000.usb: xHCI Host Controller
10341 12:21:20.465173 <6>[ 2.044308] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10342 12:21:20.474917 <6>[ 2.052174] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10343 12:21:20.481508 <6>[ 2.061595] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10344 12:21:20.488319 <6>[ 2.067679] xhci-mtk 11200000.usb: xHCI Host Controller
10345 12:21:20.495136 <6>[ 2.073158] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10346 12:21:20.501331 <6>[ 2.080805] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10347 12:21:20.508150 <6>[ 2.088650] hub 1-0:1.0: USB hub found
10348 12:21:20.511325 <6>[ 2.092693] hub 1-0:1.0: 1 port detected
10349 12:21:20.517999 <6>[ 2.096977] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10350 12:21:20.524918 <6>[ 2.105761] hub 2-0:1.0: USB hub found
10351 12:21:20.528258 <6>[ 2.109799] hub 2-0:1.0: 1 port detected
10352 12:21:20.534750 <6>[ 2.115746] mtk-msdc 11f70000.mmc: Got CD GPIO
10353 12:21:20.546742 <6>[ 2.124401] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10354 12:21:20.553476 <6>[ 2.132434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10355 12:21:20.563484 <4>[ 2.140396] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10356 12:21:20.573431 <6>[ 2.149923] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10357 12:21:20.580160 <6>[ 2.157999] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10358 12:21:20.586696 <6>[ 2.166011] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10359 12:21:20.596869 <6>[ 2.173940] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10360 12:21:20.603521 <6>[ 2.181758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10361 12:21:20.614191 <6>[ 2.189573] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10362 12:21:20.623279 <6>[ 2.199892] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10363 12:21:20.630003 <6>[ 2.208258] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10364 12:21:20.639915 <6>[ 2.216606] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10365 12:21:20.646677 <6>[ 2.224946] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10366 12:21:20.656970 <6>[ 2.233283] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10367 12:21:20.663220 <6>[ 2.241621] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10368 12:21:20.673249 <6>[ 2.249958] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10369 12:21:20.679740 <6>[ 2.258302] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10370 12:21:20.689650 <6>[ 2.266640] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10371 12:21:20.696232 <6>[ 2.274977] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10372 12:21:20.706173 <6>[ 2.283314] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10373 12:21:20.712989 <6>[ 2.291662] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10374 12:21:20.723034 <6>[ 2.300000] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10375 12:21:20.729258 <6>[ 2.308337] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10376 12:21:20.738999 <6>[ 2.316674] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10377 12:21:20.746086 <6>[ 2.325445] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10378 12:21:20.752375 <6>[ 2.332376] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10379 12:21:20.758952 <6>[ 2.339117] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10380 12:21:20.765712 <6>[ 2.345855] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10381 12:21:20.772147 <6>[ 2.352758] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10382 12:21:20.782404 <6>[ 2.359594] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10383 12:21:20.792116 <6>[ 2.368726] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10384 12:21:20.802149 <6>[ 2.377846] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10385 12:21:20.812197 <6>[ 2.387140] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10386 12:21:20.821849 <6>[ 2.396607] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10387 12:21:20.828660 <6>[ 2.406076] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10388 12:21:20.838378 <6>[ 2.415196] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10389 12:21:20.848326 <6>[ 2.424662] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10390 12:21:20.858226 <6>[ 2.433781] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10391 12:21:20.868077 <6>[ 2.443076] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10392 12:21:20.877874 <6>[ 2.453235] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10393 12:21:20.887895 <6>[ 2.464796] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10394 12:21:20.894447 <6>[ 2.474627] Trying to probe devices needed for running init ...
10395 12:21:20.919135 <6>[ 2.496523] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10396 12:21:20.947194 <6>[ 2.527939] hub 2-1:1.0: USB hub found
10397 12:21:20.950542 <6>[ 2.532421] hub 2-1:1.0: 3 ports detected
10398 12:21:21.071008 <6>[ 2.648497] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10399 12:21:21.225814 <6>[ 2.806527] hub 1-1:1.0: USB hub found
10400 12:21:21.229061 <6>[ 2.811044] hub 1-1:1.0: 4 ports detected
10401 12:21:21.303230 <6>[ 2.880784] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10402 12:21:21.550687 <6>[ 3.128484] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10403 12:21:21.682659 <6>[ 3.263592] hub 1-1.4:1.0: USB hub found
10404 12:21:21.685786 <6>[ 3.268209] hub 1-1.4:1.0: 2 ports detected
10405 12:21:21.983018 <6>[ 3.560463] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10406 12:21:22.174977 <6>[ 3.752462] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10407 12:21:33.187897 <6>[ 14.773465] ALSA device list:
10408 12:21:33.194484 <6>[ 14.776756] No soundcards found.
10409 12:21:33.202251 <6>[ 14.784545] Freeing unused kernel memory: 8384K
10410 12:21:33.205945 <6>[ 14.789598] Run /init as init process
10411 12:21:33.217419 Loading, please wait...
10412 12:21:33.246514 Starting systemd-udevd version 252.6-1
10413 12:21:33.449431 <6>[ 15.028251] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10414 12:21:33.461272 <6>[ 15.040271] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10415 12:21:33.464726 <6>[ 15.041219] remoteproc remoteproc0: scp is available
10416 12:21:33.474613 <6>[ 15.048297] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10417 12:21:33.481421 <6>[ 15.053583] remoteproc remoteproc0: powering up scp
10418 12:21:33.487909 <6>[ 15.062201] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10419 12:21:33.497574 <6>[ 15.068684] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10420 12:21:33.504755 <3>[ 15.077105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10421 12:21:33.514742 <6>[ 15.081571] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10422 12:21:33.517735 <6>[ 15.084545] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10423 12:21:33.524387 <6>[ 15.088460] mc: Linux media interface: v0.10
10424 12:21:33.531161 <3>[ 15.092642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 12:21:33.540859 <3>[ 15.092649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10426 12:21:33.547355 <3>[ 15.092708] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 12:21:33.554786 <6>[ 15.097387] usbcore: registered new interface driver r8152
10428 12:21:33.561559 <4>[ 15.110561] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10429 12:21:33.568113 <4>[ 15.110561] Fallback method does not support PEC.
10430 12:21:33.574623 <3>[ 15.119451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10431 12:21:33.581260 <4>[ 15.120527] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10432 12:21:33.591673 <4>[ 15.120745] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10433 12:21:33.594802 <6>[ 15.122517] videodev: Linux video capture interface: v2.00
10434 12:21:33.604987 <3>[ 15.142647] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10435 12:21:33.611821 <3>[ 15.154410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10436 12:21:33.621500 <3>[ 15.182649] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10437 12:21:33.628058 <3>[ 15.182876] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10438 12:21:33.637893 <6>[ 15.192182] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10439 12:21:33.644770 <3>[ 15.199696] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10440 12:21:33.651351 <6>[ 15.205291] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10441 12:21:33.657927 <6>[ 15.205296] pci_bus 0000:00: root bus resource [bus 00-ff]
10442 12:21:33.664400 <6>[ 15.205300] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10443 12:21:33.674316 <6>[ 15.205302] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10444 12:21:33.680919 <6>[ 15.205331] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10445 12:21:33.687828 <6>[ 15.205344] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10446 12:21:33.691174 <6>[ 15.205417] pci 0000:00:00.0: supports D1 D2
10447 12:21:33.701047 <6>[ 15.205420] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10448 12:21:33.707351 <6>[ 15.206356] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10449 12:21:33.714080 <6>[ 15.206439] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10450 12:21:33.720687 <6>[ 15.206463] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10451 12:21:33.730767 <6>[ 15.206479] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10452 12:21:33.737277 <6>[ 15.206494] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10453 12:21:33.740690 <6>[ 15.206605] pci 0000:01:00.0: supports D1 D2
10454 12:21:33.747245 <6>[ 15.206606] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10455 12:21:33.753691 <6>[ 15.210252] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10456 12:21:33.763802 <6>[ 15.210300] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10457 12:21:33.770499 <6>[ 15.210307] remoteproc remoteproc0: remote processor scp is now up
10458 12:21:33.777097 <6>[ 15.212201] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10459 12:21:33.783731 <6>[ 15.212224] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10460 12:21:33.793372 <6>[ 15.212227] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10461 12:21:33.800183 <6>[ 15.212236] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10462 12:21:33.809823 <6>[ 15.212249] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10463 12:21:33.816709 <6>[ 15.212263] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10464 12:21:33.823025 <6>[ 15.212275] pci 0000:00:00.0: PCI bridge to [bus 01]
10465 12:21:33.830168 <6>[ 15.212282] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10466 12:21:33.836703 <6>[ 15.212435] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10467 12:21:33.843076 <6>[ 15.212873] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10468 12:21:33.849607 <6>[ 15.213348] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10469 12:21:33.856214 <3>[ 15.216579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10470 12:21:33.866152 <6>[ 15.231743] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10471 12:21:33.872865 <3>[ 15.231789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10472 12:21:33.882670 <4>[ 15.235521] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10473 12:21:33.892962 <4>[ 15.235533] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10474 12:21:33.899403 <6>[ 15.239916] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10475 12:21:33.905736 <3>[ 15.244346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10476 12:21:33.916102 <3>[ 15.244350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10477 12:21:33.922267 <3>[ 15.244384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10478 12:21:33.932106 <6>[ 15.248870] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10479 12:21:33.942330 <6>[ 15.249249] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10480 12:21:33.948838 <6>[ 15.261934] usbcore: registered new interface driver cdc_ether
10481 12:21:33.955263 <3>[ 15.267652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10482 12:21:33.965265 <3>[ 15.267663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10483 12:21:33.971796 <3>[ 15.267673] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10484 12:21:33.981590 <3>[ 15.267681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10485 12:21:33.988498 <3>[ 15.267770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10486 12:21:33.998457 <5>[ 15.272538] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10487 12:21:34.004947 <6>[ 15.275737] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10488 12:21:34.011351 <6>[ 15.280419] usbcore: registered new interface driver r8153_ecm
10489 12:21:34.018474 <5>[ 15.285973] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10490 12:21:34.028071 <4>[ 15.286025] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10491 12:21:34.031140 <6>[ 15.286029] cfg80211: failed to load regulatory.db
10492 12:21:34.034638 <6>[ 15.288118] Bluetooth: Core ver 2.22
10493 12:21:34.041233 <6>[ 15.296467] r8152 2-1.3:1.0 eth0: v1.12.13
10494 12:21:34.047669 <6>[ 15.297168] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10495 12:21:34.061356 <6>[ 15.299115] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10496 12:21:34.064386 <6>[ 15.299224] usbcore: registered new interface driver uvcvideo
10497 12:21:34.070742 <6>[ 15.301634] NET: Registered PF_BLUETOOTH protocol family
10498 12:21:34.077357 <6>[ 15.313299] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10499 12:21:34.084251 <6>[ 15.316369] Bluetooth: HCI device and connection manager initialized
10500 12:21:34.090929 <6>[ 15.336734] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10501 12:21:34.093954 <6>[ 15.342436] Bluetooth: HCI socket layer initialized
10502 12:21:34.103885 <6>[ 15.356418] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10503 12:21:34.107224 <6>[ 15.357402] Bluetooth: L2CAP socket layer initialized
10504 12:21:34.113870 <6>[ 15.364258] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10505 12:21:34.120494 <6>[ 15.372258] Bluetooth: SCO socket layer initialized
10506 12:21:34.124118 <6>[ 15.400373] mt7921e 0000:01:00.0: ASIC revision: 79610010
10507 12:21:34.130219 <6>[ 15.478798] usbcore: registered new interface driver btusb
10508 12:21:34.140298 <4>[ 15.479582] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10509 12:21:34.146982 <3>[ 15.479588] Bluetooth: hci0: Failed to load firmware file (-2)
10510 12:21:34.153418 <3>[ 15.479589] Bluetooth: hci0: Failed to set up firmware (-2)
10511 12:21:34.163504 <4>[ 15.479591] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10512 12:21:34.177051 <4>[ 15.578942] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10513 12:21:34.180051 Begin: Loading essential drivers ... done.
10514 12:21:34.183414 Begin: Running /scripts/init-premount ... done.
10515 12:21:34.189869 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10516 12:21:34.200195 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10517 12:21:34.202967 Device /sys/class/net/enx00e04c6803bd found
10518 12:21:34.203067 done.
10519 12:21:34.233848 Begin: Waiting up to 180 secs for any network device to become available ... done.
10520 12:21:34.277472 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10521 12:21:34.294966 <4>[ 15.870700] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10522 12:21:34.409700 <4>[ 15.985258] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10523 12:21:34.525215 <4>[ 16.101050] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10524 12:21:34.640976 <4>[ 16.216976] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10525 12:21:34.757023 <4>[ 16.332877] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10526 12:21:34.873102 <4>[ 16.448902] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10527 12:21:34.989054 <4>[ 16.564807] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10528 12:21:35.104895 <4>[ 16.680879] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10529 12:21:35.221091 <4>[ 16.796716] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10530 12:21:35.294746 <6>[ 16.877003] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10531 12:21:35.328356 <3>[ 16.910746] mt7921e 0000:01:00.0: hardware init failed
10532 12:21:35.608937 IP-Config: no response after 2 secs - giving up
10533 12:21:35.645258 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10534 12:21:35.648780 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10535 12:21:35.655210 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10536 12:21:35.664775 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10537 12:21:35.671799 host : mt8192-asurada-spherion-r0-cbg-4
10538 12:21:35.678420 domain : lava-rack
10539 12:21:35.681470 rootserver: 192.168.201.1 rootpath:
10540 12:21:35.681563 filename :
10541 12:21:35.705743 done.
10542 12:21:35.712838 Begin: Running /scripts/nfs-bottom ... done.
10543 12:21:35.732155 Begin: Running /scripts/init-bottom ... done.
10544 12:21:37.030218 <6>[ 18.612931] NET: Registered PF_INET6 protocol family
10545 12:21:37.037563 <6>[ 18.620108] Segment Routing with IPv6
10546 12:21:37.040598 <6>[ 18.624095] In-situ OAM (IOAM) with IPv6
10547 12:21:37.205426 <30>[ 18.761483] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10548 12:21:37.211967 <30>[ 18.793881] systemd[1]: Detected architecture arm64.
10549 12:21:37.218936
10550 12:21:37.221965 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10551 12:21:37.222045
10552 12:21:37.246782 <30>[ 18.829244] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10553 12:21:38.197998 <30>[ 19.777608] systemd[1]: Queued start job for default target graphical.target.
10554 12:21:38.237786 <30>[ 19.817353] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10555 12:21:38.244471 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10556 12:21:38.267071 <30>[ 19.846412] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10557 12:21:38.276888 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10558 12:21:38.294879 <30>[ 19.874177] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10559 12:21:38.304418 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10560 12:21:38.323084 <30>[ 19.902646] systemd[1]: Created slice user.slice - User and Session Slice.
10561 12:21:38.329574 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10562 12:21:38.352755 <30>[ 19.928833] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10563 12:21:38.359185 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10564 12:21:38.380467 <30>[ 19.956691] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10565 12:21:38.386811 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10566 12:21:38.415368 <30>[ 19.985105] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10567 12:21:38.425617 <30>[ 20.005166] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10568 12:21:38.432285 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10569 12:21:38.452738 <30>[ 20.032505] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10570 12:21:38.462720 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10571 12:21:38.477845 <30>[ 20.060663] systemd[1]: Reached target paths.target - Path Units.
10572 12:21:38.484396 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10573 12:21:38.504995 <30>[ 20.084692] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10574 12:21:38.511651 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10575 12:21:38.525593 <30>[ 20.108499] systemd[1]: Reached target slices.target - Slice Units.
10576 12:21:38.535592 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10577 12:21:38.549956 <30>[ 20.132953] systemd[1]: Reached target swap.target - Swaps.
10578 12:21:38.556883 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10579 12:21:38.577190 <30>[ 20.156943] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10580 12:21:38.587420 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10581 12:21:38.605256 <30>[ 20.184940] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10582 12:21:38.615088 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10583 12:21:38.635406 <30>[ 20.214805] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10584 12:21:38.645254 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10585 12:21:38.663140 <30>[ 20.242643] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10586 12:21:38.673173 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10587 12:21:38.689436 <30>[ 20.269099] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10588 12:21:38.696206 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10589 12:21:38.714426 <30>[ 20.293929] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10590 12:21:38.724019 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10591 12:21:38.743268 <30>[ 20.323057] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10592 12:21:38.753404 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10593 12:21:38.769986 <30>[ 20.349544] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10594 12:21:38.777010 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10595 12:21:38.833228 <30>[ 20.412696] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10596 12:21:38.839916 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10597 12:21:38.861452 <30>[ 20.441139] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10598 12:21:38.867923 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10599 12:21:38.896385 <30>[ 20.475907] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10600 12:21:38.903016 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10601 12:21:38.928131 <30>[ 20.501148] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10602 12:21:38.973560 <30>[ 20.553288] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10603 12:21:38.983431 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10604 12:21:39.006334 <30>[ 20.585907] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10605 12:21:39.012811 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10606 12:21:39.038401 <30>[ 20.617863] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10607 12:21:39.044707 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10608 12:21:39.070793 <30>[ 20.650313] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10609 12:21:39.080568 Startin<6>[ 20.659451] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10610 12:21:39.087397 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10611 12:21:39.101020 <30>[ 20.680720] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10612 12:21:39.111015 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10613 12:21:39.134830 <30>[ 20.714320] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10614 12:21:39.141158 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10615 12:21:39.166848 <30>[ 20.746492] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10616 12:21:39.173545 Startin<6>[ 20.755362] fuse: init (API version 7.37)
10617 12:21:39.179809 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10618 12:21:39.206903 <30>[ 20.786504] systemd[1]: Starting systemd-journald.service - Journal Service...
10619 12:21:39.213257 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10620 12:21:39.242747 <30>[ 20.822331] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10621 12:21:39.249083 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10622 12:21:39.278565 <30>[ 20.854806] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10623 12:21:39.285051 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10624 12:21:39.334047 <3>[ 20.913637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10625 12:21:39.345600 <30>[ 20.925326] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10626 12:21:39.353145 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10627 12:21:39.364007 <3>[ 20.943427] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10628 12:21:39.379839 <30>[ 20.959187] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10629 12:21:39.386130 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10630 12:21:39.408085 <3>[ 20.987904] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10631 12:21:39.414928 <30>[ 20.990392] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10632 12:21:39.425127 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10633 12:21:39.437126 <3>[ 21.016671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10634 12:21:39.447156 <30>[ 21.026124] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10635 12:21:39.453880 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10636 12:21:39.467402 <3>[ 21.047059] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10637 12:21:39.477326 <30>[ 21.056662] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10638 12:21:39.484388 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10639 12:21:39.497259 <3>[ 21.077174] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10640 12:21:39.507871 <30>[ 21.087499] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10641 12:21:39.518275 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10642 12:21:39.528685 <3>[ 21.107325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10643 12:21:39.538844 <30>[ 21.118343] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10644 12:21:39.548775 <30>[ 21.126495] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10645 12:21:39.555332 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10646 12:21:39.573741 <30>[ 21.153397] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10647 12:21:39.580400 <3>[ 21.153467] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10648 12:21:39.590643 <30>[ 21.161127] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10649 12:21:39.597237 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10650 12:21:39.610733 <3>[ 21.190199] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10651 12:21:39.621158 <30>[ 21.200867] systemd[1]: modprobe@drm.service: Deactivated successfully.
10652 12:21:39.628183 <30>[ 21.208792] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10653 12:21:39.642328 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m -<3>[ 21.222290] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10654 12:21:39.644980 Load Kernel Module drm.
10655 12:21:39.667090 <30>[ 21.245955] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10656 12:21:39.673907 <30>[ 21.254352] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10657 12:21:39.683773 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10658 12:21:39.705788 <30>[ 21.285315] systemd[1]: Started systemd-journald.service - Journal Service.
10659 12:21:39.712128 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10660 12:21:39.734816 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10661 12:21:39.762178 <4>[ 21.334778] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10662 12:21:39.771846 <3>[ 21.350442] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10663 12:21:39.778426 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10664 12:21:39.798507 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10665 12:21:39.818642 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10666 12:21:39.838224 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10667 12:21:39.858373 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10668 12:21:39.879614 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10669 12:21:39.937590 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10670 12:21:39.962247 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10671 12:21:39.986905 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10672 12:21:40.015208 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10673 12:21:40.037739 <46>[ 21.617333] systemd-journald[296]: Received client request to flush runtime journal.
10674 12:21:40.070105 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10675 12:21:40.298345 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10676 12:21:40.630352 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10677 12:21:40.649690 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10678 12:21:40.669702 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10679 12:21:41.154211 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10680 12:21:41.484130 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10681 12:21:41.501840 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10682 12:21:41.561736 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10683 12:21:41.627407 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10684 12:21:41.645048 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10685 12:21:41.664707 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10686 12:21:41.721642 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10687 12:21:41.750641 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10688 12:21:41.777142 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10689 12:21:41.803905 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10690 12:21:41.817771 See 'systemctl status systemd-binfmt.service' for details.
10691 12:21:41.988578 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10692 12:21:42.059774 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10693 12:21:42.119208 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10694 12:21:42.274039 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10695 12:21:42.354950 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10696 12:21:42.385438 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10697 12:21:42.531791 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10698 12:21:42.552414 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10699 12:21:42.613993 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10700 12:21:42.636877 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10701 12:21:42.690841 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10702 12:21:42.709776 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10703 12:21:42.734095 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10704 12:21:42.760392 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10705 12:21:42.780923 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10706 12:21:42.837485 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10707 12:21:42.859018 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10708 12:21:42.881943 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10709 12:21:42.905527 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10710 12:21:42.927044 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10711 12:21:42.944940 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10712 12:21:42.966355 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10713 12:21:42.987504 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10714 12:21:43.004831 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10715 12:21:43.020720 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10716 12:21:43.038644 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10717 12:21:43.056680 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10718 12:21:43.072966 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10719 12:21:43.109670 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10720 12:21:43.142924 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10721 12:21:43.233519 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10722 12:21:43.258528 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10723 12:21:43.277423 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10724 12:21:43.426018 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10725 12:21:43.447476 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10726 12:21:43.501864 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10727 12:21:43.532766 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10728 12:21:43.549141 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10729 12:21:43.565818 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10730 12:21:43.602856 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10731 12:21:43.632596 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10732 12:21:43.651180 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10733 12:21:43.702735 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10734 12:21:43.724619 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10735 12:21:43.768900 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10736 12:21:43.793081 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10737 12:21:43.876631
10738 12:21:43.876744
10739 12:21:43.879848 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10740 12:21:43.879931
10741 12:21:43.883119 debian-bookworm-arm64 login: root (automatic login)
10742 12:21:43.883201
10743 12:21:43.883265
10744 12:21:44.165696 Linux debian-bookworm-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64
10745 12:21:44.165851
10746 12:21:44.172591 The programs included with the Debian GNU/Linux system are free software;
10747 12:21:44.178790 the exact distribution terms for each program are described in the
10748 12:21:44.182471 individual files in /usr/share/doc/*/copyright.
10749 12:21:44.182553
10750 12:21:44.189010 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10751 12:21:44.192306 permitted by applicable law.
10752 12:21:44.929159 Matched prompt #10: / #
10754 12:21:44.929430 Setting prompt string to ['/ #']
10755 12:21:44.929526 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10757 12:21:44.929720 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10758 12:21:44.929807 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
10759 12:21:44.929891 Setting prompt string to ['/ #']
10760 12:21:44.929958 Forcing a shell prompt, looking for ['/ #']
10762 12:21:44.980182 / #
10763 12:21:44.980340 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10764 12:21:44.980443 Waiting using forced prompt support (timeout 00:02:30)
10765 12:21:44.985084
10766 12:21:44.985359 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10767 12:21:44.985457 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
10769 12:21:45.085804 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893132/extract-nfsrootfs-up4tc3au'
10770 12:21:45.091217 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893132/extract-nfsrootfs-up4tc3au'
10772 12:21:45.191725 / # export NFS_SERVER_IP='192.168.201.1'
10773 12:21:45.196791 export NFS_SERVER_IP='192.168.201.1'
10774 12:21:45.197077 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10775 12:21:45.197180 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
10776 12:21:45.197286 end: 2 depthcharge-action (duration 00:01:24) [common]
10777 12:21:45.197420 start: 3 lava-test-retry (timeout 00:07:57) [common]
10778 12:21:45.197513 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
10779 12:21:45.197588 Using namespace: common
10781 12:21:45.297920 / # #
10782 12:21:45.298053 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10783 12:21:45.302814 #
10784 12:21:45.303083 Using /lava-11893132
10786 12:21:45.403421 / # export SHELL=/bin/bash
10787 12:21:45.408827 export SHELL=/bin/bash
10789 12:21:45.509373 / # . /lava-11893132/environment
10790 12:21:45.514477 . /lava-11893132/environment
10792 12:21:45.619266 / # /lava-11893132/bin/lava-test-runner /lava-11893132/0
10793 12:21:45.619404 Test shell timeout: 10s (minimum of the action and connection timeout)
10794 12:21:45.624302 /lava-11893132/bin/lava-test-runner /lava-11893132/0
10795 12:21:45.832911 + export TESTRUN_ID=0_timesync-off
10796 12:21:45.836276 + TESTRUN_ID=0_timesync-off
10797 12:21:45.839085 + cd /lava-11893132/0/tests/0_timesync-off
10798 12:21:45.842200 ++ cat uuid
10799 12:21:45.842318 + UUID=11893132_1.6.2.3.1
10800 12:21:45.845882 + set +x
10801 12:21:45.849115 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11893132_1.6.2.3.1>
10802 12:21:45.849402 Received signal: <STARTRUN> 0_timesync-off 11893132_1.6.2.3.1
10803 12:21:45.849508 Starting test lava.0_timesync-off (11893132_1.6.2.3.1)
10804 12:21:45.849672 Skipping test definition patterns.
10805 12:21:45.852280 + systemctl stop systemd-timesyncd
10806 12:21:45.902841 + set +x
10807 12:21:45.905801 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11893132_1.6.2.3.1>
10808 12:21:45.906058 Received signal: <ENDRUN> 0_timesync-off 11893132_1.6.2.3.1
10809 12:21:45.906143 Ending use of test pattern.
10810 12:21:45.906216 Ending test lava.0_timesync-off (11893132_1.6.2.3.1), duration 0.06
10812 12:21:45.955836 + export TESTRUN_ID=1_kselftest-alsa
10813 12:21:45.959259 + TESTRUN_ID=1_kselftest-alsa
10814 12:21:45.965887 + cd /lava-11893132/0/tests/1_kselftest-alsa
10815 12:21:45.965970 ++ cat uuid
10816 12:21:45.969241 + UUID=11893132_1.6.2.3.5
10817 12:21:45.969323 + set +x
10818 12:21:45.972546 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 11893132_1.6.2.3.5>
10819 12:21:45.972802 Received signal: <STARTRUN> 1_kselftest-alsa 11893132_1.6.2.3.5
10820 12:21:45.972872 Starting test lava.1_kselftest-alsa (11893132_1.6.2.3.5)
10821 12:21:45.972953 Skipping test definition patterns.
10822 12:21:45.975518 + cd ./automated/linux/kselftest/
10823 12:21:46.005565 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10824 12:21:46.024052 INFO: install_deps skipped
10825 12:21:46.505292 --2023-10-27 12:21:46-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10826 12:21:46.511654 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10827 12:21:46.645091 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10828 12:21:46.777663 HTTP request sent, awaiting response... 200 OK
10829 12:21:46.781042 Length: 2956332 (2.8M) [application/octet-stream]
10830 12:21:46.784422 Saving to: 'kselftest.tar.xz'
10831 12:21:46.784503
10832 12:21:46.784567
10833 12:21:47.043228 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10834 12:21:47.308890 kselftest.tar.xz 1%[ ] 49.22K 193KB/s
10835 12:21:47.655555 kselftest.tar.xz 7%[> ] 216.08K 422KB/s
10836 12:21:47.975221 kselftest.tar.xz 26%[====> ] 760.50K 898KB/s
10837 12:21:48.026532 kselftest.tar.xz 48%[========> ] 1.35M 1.17MB/s
10838 12:21:48.033487 kselftest.tar.xz 100%[===================>] 2.82M 2.34MB/s in 1.2s
10839 12:21:48.033572
10840 12:21:48.289949 2023-10-27 12:21:48 (2.34 MB/s) - 'kselftest.tar.xz' saved [2956332/2956332]
10841 12:21:48.290087
10842 12:21:53.613894 skiplist:
10843 12:21:53.617220 ========================================
10844 12:21:53.620349 ========================================
10845 12:21:53.658638 alsa:mixer-test
10846 12:21:53.676974 ============== Tests to run ===============
10847 12:21:53.677065 alsa:mixer-test
10848 12:21:53.680089 ===========End Tests to run ===============
10849 12:21:53.683569 shardfile-alsa pass
10850 12:21:53.771997 <12>[ 35.356959] kselftest: Running tests in alsa
10851 12:21:53.780415 TAP version 13
10852 12:21:53.792853 1..1
10853 12:21:53.804788 # selftests: alsa: mixer-test
10854 12:21:54.290167 # TAP version 13
10855 12:21:54.290306 # 1..0
10856 12:21:54.296894 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
10857 12:21:54.300104 ok 1 selftests: alsa: mixer-test
10858 12:21:54.989972 alsa_mixer-test pass
10859 12:21:55.032865 + ../../utils/send-to-lava.sh ./output/result.txt
10860 12:21:55.081574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
10861 12:21:55.081875 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
10863 12:21:55.115208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10864 12:21:55.115297 + set +x
10865 12:21:55.115534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10867 12:21:55.121880 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 11893132_1.6.2.3.5>
10868 12:21:55.122132 Received signal: <ENDRUN> 1_kselftest-alsa 11893132_1.6.2.3.5
10869 12:21:55.122204 Ending use of test pattern.
10870 12:21:55.122265 Ending test lava.1_kselftest-alsa (11893132_1.6.2.3.5), duration 9.15
10872 12:21:55.124784 <LAVA_TEST_RUNNER EXIT>
10873 12:21:55.125034 ok: lava_test_shell seems to have completed
10874 12:21:55.125132 alsa_mixer-test: pass
shardfile-alsa: pass
10875 12:21:55.125223 end: 3.1 lava-test-shell (duration 00:00:10) [common]
10876 12:21:55.125307 end: 3 lava-test-retry (duration 00:00:10) [common]
10877 12:21:55.125393 start: 4 finalize (timeout 00:07:47) [common]
10878 12:21:55.125481 start: 4.1 power-off (timeout 00:00:30) [common]
10879 12:21:55.125627 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10880 12:21:55.201987 >> Command sent successfully.
10881 12:21:55.204484 Returned 0 in 0 seconds
10882 12:21:55.304900 end: 4.1 power-off (duration 00:00:00) [common]
10884 12:21:55.305219 start: 4.2 read-feedback (timeout 00:07:47) [common]
10885 12:21:55.305487 Listened to connection for namespace 'common' for up to 1s
10886 12:21:56.306437 Finalising connection for namespace 'common'
10887 12:21:56.306602 Disconnecting from shell: Finalise
10888 12:21:56.306677 / #
10889 12:21:56.406973 end: 4.2 read-feedback (duration 00:00:01) [common]
10890 12:21:56.407123 end: 4 finalize (duration 00:00:01) [common]
10891 12:21:56.407239 Cleaning after the job
10892 12:21:56.407341 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/ramdisk
10893 12:21:56.410387 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/kernel
10894 12:21:56.422930 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/dtb
10895 12:21:56.423104 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/nfsrootfs
10896 12:21:56.525873 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893132/tftp-deploy-l4a7eacn/modules
10897 12:21:56.533422 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893132
10898 12:21:57.204295 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893132
10899 12:21:57.204457 Job finished correctly