Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 35
- Errors: 0
- Boot result: PASS
1 12:22:40.879366 lava-dispatcher, installed at version: 2023.08
2 12:22:40.879564 start: 0 validate
3 12:22:40.879692 Start time: 2023-10-27 12:22:40.879684+00:00 (UTC)
4 12:22:40.879809 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:22:40.879937 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:22:41.150732 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:22:41.151453 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:22:41.422993 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:22:41.423803 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:22:41.694845 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:22:41.695591 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:22:41.966532 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:22:41.967317 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:22:42.243194 validate duration: 1.36
16 12:22:42.243443 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:22:42.243536 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:22:42.243625 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:22:42.243746 Not decompressing ramdisk as can be used compressed.
20 12:22:42.243832 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:22:42.243894 saving as /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/ramdisk/initrd.cpio.gz
22 12:22:42.243958 total size: 4665395 (4 MB)
23 12:22:42.245048 progress 0 % (0 MB)
24 12:22:42.246535 progress 5 % (0 MB)
25 12:22:42.247773 progress 10 % (0 MB)
26 12:22:42.249058 progress 15 % (0 MB)
27 12:22:42.250279 progress 20 % (0 MB)
28 12:22:42.251483 progress 25 % (1 MB)
29 12:22:42.252752 progress 30 % (1 MB)
30 12:22:42.253955 progress 35 % (1 MB)
31 12:22:42.255152 progress 40 % (1 MB)
32 12:22:42.256566 progress 45 % (2 MB)
33 12:22:42.257767 progress 50 % (2 MB)
34 12:22:42.258971 progress 55 % (2 MB)
35 12:22:42.260180 progress 60 % (2 MB)
36 12:22:42.261438 progress 65 % (2 MB)
37 12:22:42.262638 progress 70 % (3 MB)
38 12:22:42.263832 progress 75 % (3 MB)
39 12:22:42.265090 progress 80 % (3 MB)
40 12:22:42.266504 progress 85 % (3 MB)
41 12:22:42.267703 progress 90 % (4 MB)
42 12:22:42.268943 progress 95 % (4 MB)
43 12:22:42.270153 progress 100 % (4 MB)
44 12:22:42.270298 4 MB downloaded in 0.03 s (168.91 MB/s)
45 12:22:42.270431 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:22:42.270655 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:22:42.270738 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:22:42.270818 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:22:42.270939 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:22:42.271009 saving as /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/kernel/Image
52 12:22:42.271068 total size: 49236480 (46 MB)
53 12:22:42.271126 No compression specified
54 12:22:42.272446 progress 0 % (0 MB)
55 12:22:42.285286 progress 5 % (2 MB)
56 12:22:42.298200 progress 10 % (4 MB)
57 12:22:42.311148 progress 15 % (7 MB)
58 12:22:42.323810 progress 20 % (9 MB)
59 12:22:42.336530 progress 25 % (11 MB)
60 12:22:42.349292 progress 30 % (14 MB)
61 12:22:42.361982 progress 35 % (16 MB)
62 12:22:42.374885 progress 40 % (18 MB)
63 12:22:42.387575 progress 45 % (21 MB)
64 12:22:42.400378 progress 50 % (23 MB)
65 12:22:42.412938 progress 55 % (25 MB)
66 12:22:42.425521 progress 60 % (28 MB)
67 12:22:42.438546 progress 65 % (30 MB)
68 12:22:42.451098 progress 70 % (32 MB)
69 12:22:42.463596 progress 75 % (35 MB)
70 12:22:42.476418 progress 80 % (37 MB)
71 12:22:42.489057 progress 85 % (39 MB)
72 12:22:42.501612 progress 90 % (42 MB)
73 12:22:42.513981 progress 95 % (44 MB)
74 12:22:42.526722 progress 100 % (46 MB)
75 12:22:42.526919 46 MB downloaded in 0.26 s (183.53 MB/s)
76 12:22:42.527068 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:22:42.527294 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:22:42.527380 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:22:42.527464 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:22:42.527590 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:22:42.527658 saving as /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/dtb/mt8192-asurada-spherion-r0.dtb
83 12:22:42.527718 total size: 47278 (0 MB)
84 12:22:42.527778 No compression specified
85 12:22:42.528936 progress 69 % (0 MB)
86 12:22:42.529203 progress 100 % (0 MB)
87 12:22:42.529357 0 MB downloaded in 0.00 s (27.55 MB/s)
88 12:22:42.529477 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:22:42.529690 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:22:42.529771 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:22:42.529851 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:22:42.529959 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:22:42.530029 saving as /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/nfsrootfs/full.rootfs.tar
95 12:22:42.530090 total size: 200813988 (191 MB)
96 12:22:42.530184 Using unxz to decompress xz
97 12:22:42.534416 progress 0 % (0 MB)
98 12:22:43.054471 progress 5 % (9 MB)
99 12:22:43.561912 progress 10 % (19 MB)
100 12:22:44.135957 progress 15 % (28 MB)
101 12:22:44.504564 progress 20 % (38 MB)
102 12:22:44.822788 progress 25 % (47 MB)
103 12:22:45.403127 progress 30 % (57 MB)
104 12:22:45.941583 progress 35 % (67 MB)
105 12:22:46.523259 progress 40 % (76 MB)
106 12:22:47.074587 progress 45 % (86 MB)
107 12:22:47.652399 progress 50 % (95 MB)
108 12:22:48.276520 progress 55 % (105 MB)
109 12:22:48.927923 progress 60 % (114 MB)
110 12:22:49.043668 progress 65 % (124 MB)
111 12:22:49.181246 progress 70 % (134 MB)
112 12:22:49.275865 progress 75 % (143 MB)
113 12:22:49.345865 progress 80 % (153 MB)
114 12:22:49.413638 progress 85 % (162 MB)
115 12:22:49.513182 progress 90 % (172 MB)
116 12:22:49.785993 progress 95 % (181 MB)
117 12:22:50.350979 progress 100 % (191 MB)
118 12:22:50.356220 191 MB downloaded in 7.83 s (24.47 MB/s)
119 12:22:50.356480 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:22:50.356738 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:22:50.356827 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:22:50.356911 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:22:50.357065 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:22:50.357134 saving as /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/modules/modules.tar
126 12:22:50.357195 total size: 8625084 (8 MB)
127 12:22:50.357255 Using unxz to decompress xz
128 12:22:50.361429 progress 0 % (0 MB)
129 12:22:50.382774 progress 5 % (0 MB)
130 12:22:50.405111 progress 10 % (0 MB)
131 12:22:50.430708 progress 15 % (1 MB)
132 12:22:50.455572 progress 20 % (1 MB)
133 12:22:50.480861 progress 25 % (2 MB)
134 12:22:50.506942 progress 30 % (2 MB)
135 12:22:50.533360 progress 35 % (2 MB)
136 12:22:50.557630 progress 40 % (3 MB)
137 12:22:50.581163 progress 45 % (3 MB)
138 12:22:50.606956 progress 50 % (4 MB)
139 12:22:50.631696 progress 55 % (4 MB)
140 12:22:50.656017 progress 60 % (4 MB)
141 12:22:50.680041 progress 65 % (5 MB)
142 12:22:50.704430 progress 70 % (5 MB)
143 12:22:50.728057 progress 75 % (6 MB)
144 12:22:50.753986 progress 80 % (6 MB)
145 12:22:50.783110 progress 85 % (7 MB)
146 12:22:50.809625 progress 90 % (7 MB)
147 12:22:50.835017 progress 95 % (7 MB)
148 12:22:50.858017 progress 100 % (8 MB)
149 12:22:50.862810 8 MB downloaded in 0.51 s (16.27 MB/s)
150 12:22:50.863050 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:22:50.863362 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:22:50.863485 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:22:50.863614 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:22:54.335877 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11893158/extract-nfsrootfs-9jokrc83
156 12:22:54.336078 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 12:22:54.336289 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 12:22:54.336467 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten
159 12:22:54.336606 makedir: /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin
160 12:22:54.336713 makedir: /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/tests
161 12:22:54.336816 makedir: /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/results
162 12:22:54.336918 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-add-keys
163 12:22:54.337063 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-add-sources
164 12:22:54.337196 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-background-process-start
165 12:22:54.337326 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-background-process-stop
166 12:22:54.337455 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-common-functions
167 12:22:54.337581 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-echo-ipv4
168 12:22:54.337708 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-install-packages
169 12:22:54.337834 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-installed-packages
170 12:22:54.337957 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-os-build
171 12:22:54.338082 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-probe-channel
172 12:22:54.338210 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-probe-ip
173 12:22:54.338338 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-target-ip
174 12:22:54.338465 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-target-mac
175 12:22:54.338591 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-target-storage
176 12:22:54.338718 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-test-case
177 12:22:54.338845 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-test-event
178 12:22:54.338970 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-test-feedback
179 12:22:54.339096 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-test-raise
180 12:22:54.339221 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-test-reference
181 12:22:54.339347 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-test-runner
182 12:22:54.339472 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-test-set
183 12:22:54.339600 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-test-shell
184 12:22:54.339727 Updating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-add-keys (debian)
185 12:22:54.339883 Updating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-add-sources (debian)
186 12:22:54.340026 Updating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-install-packages (debian)
187 12:22:54.340167 Updating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-installed-packages (debian)
188 12:22:54.340324 Updating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/bin/lava-os-build (debian)
189 12:22:54.340448 Creating /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/environment
190 12:22:54.340544 LAVA metadata
191 12:22:54.340615 - LAVA_JOB_ID=11893158
192 12:22:54.340678 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:22:54.340778 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 12:22:54.340845 skipped lava-vland-overlay
195 12:22:54.340919 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:22:54.341008 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 12:22:54.341069 skipped lava-multinode-overlay
198 12:22:54.341141 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:22:54.341218 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 12:22:54.341289 Loading test definitions
201 12:22:54.341377 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 12:22:54.341447 Using /lava-11893158 at stage 0
203 12:22:54.341742 uuid=11893158_1.6.2.3.1 testdef=None
204 12:22:54.341830 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:22:54.341914 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 12:22:54.342368 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:22:54.342584 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 12:22:54.343140 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:22:54.343366 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 12:22:54.343908 runner path: /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/0/tests/0_timesync-off test_uuid 11893158_1.6.2.3.1
213 12:22:54.344065 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:22:54.344408 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 12:22:54.344481 Using /lava-11893158 at stage 0
217 12:22:54.344576 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:22:54.344653 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/0/tests/1_kselftest-arm64'
219 12:22:57.250734 Running '/usr/bin/git checkout kernelci.org
220 12:22:57.399669 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 12:22:57.400473 uuid=11893158_1.6.2.3.5 testdef=None
222 12:22:57.400637 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 12:22:57.400910 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 12:22:57.401738 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:22:57.402003 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 12:22:57.415075 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:22:57.416336 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 12:22:57.419113 runner path: /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/0/tests/1_kselftest-arm64 test_uuid 11893158_1.6.2.3.5
232 12:22:57.419206 BOARD='mt8192-asurada-spherion-r0'
233 12:22:57.419270 BRANCH='cip-gitlab'
234 12:22:57.419328 SKIPFILE='/dev/null'
235 12:22:57.419385 SKIP_INSTALL='True'
236 12:22:57.419439 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:22:57.419495 TST_CASENAME=''
238 12:22:57.419548 TST_CMDFILES='arm64'
239 12:22:57.419689 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:22:57.419900 Creating lava-test-runner.conf files
242 12:22:57.419981 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893158/lava-overlay-37_dvten/lava-11893158/0 for stage 0
243 12:22:57.420075 - 0_timesync-off
244 12:22:57.420144 - 1_kselftest-arm64
245 12:22:57.420288 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 12:22:57.420377 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 12:23:04.792092 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 12:23:04.792320 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 12:23:04.792445 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:23:04.792543 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 12:23:04.792632 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 12:23:04.911948 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:23:04.912411 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 12:23:04.912528 extracting modules file /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893158/extract-nfsrootfs-9jokrc83
255 12:23:05.131489 extracting modules file /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893158/extract-overlay-ramdisk-lc8iv2y3/ramdisk
256 12:23:05.355674 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:23:05.355837 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 12:23:05.355931 [common] Applying overlay to NFS
259 12:23:05.356001 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893158/compress-overlay-3cmkp64x/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893158/extract-nfsrootfs-9jokrc83
260 12:23:06.261650 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:23:06.261816 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 12:23:06.261912 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:23:06.262003 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 12:23:06.262083 Building ramdisk /var/lib/lava/dispatcher/tmp/11893158/extract-overlay-ramdisk-lc8iv2y3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893158/extract-overlay-ramdisk-lc8iv2y3/ramdisk
265 12:23:06.592951 >> 119370 blocks
266 12:23:08.467481 rename /var/lib/lava/dispatcher/tmp/11893158/extract-overlay-ramdisk-lc8iv2y3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/ramdisk/ramdisk.cpio.gz
267 12:23:08.467936 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:23:08.468058 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 12:23:08.468157 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 12:23:08.468268 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/kernel/Image'
271 12:23:20.389667 Returned 0 in 11 seconds
272 12:23:20.490721 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/kernel/image.itb
273 12:23:20.850533 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:23:20.850931 output: Created: Fri Oct 27 13:23:20 2023
275 12:23:20.851008 output: Image 0 (kernel-1)
276 12:23:20.851072 output: Description:
277 12:23:20.851135 output: Created: Fri Oct 27 13:23:20 2023
278 12:23:20.851196 output: Type: Kernel Image
279 12:23:20.851256 output: Compression: lzma compressed
280 12:23:20.851312 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
281 12:23:20.851368 output: Architecture: AArch64
282 12:23:20.851424 output: OS: Linux
283 12:23:20.851478 output: Load Address: 0x00000000
284 12:23:20.851532 output: Entry Point: 0x00000000
285 12:23:20.851587 output: Hash algo: crc32
286 12:23:20.851641 output: Hash value: d33b93ae
287 12:23:20.851695 output: Image 1 (fdt-1)
288 12:23:20.851748 output: Description: mt8192-asurada-spherion-r0
289 12:23:20.851798 output: Created: Fri Oct 27 13:23:20 2023
290 12:23:20.851849 output: Type: Flat Device Tree
291 12:23:20.851899 output: Compression: uncompressed
292 12:23:20.851949 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:23:20.851999 output: Architecture: AArch64
294 12:23:20.852049 output: Hash algo: crc32
295 12:23:20.852099 output: Hash value: cc4352de
296 12:23:20.852149 output: Image 2 (ramdisk-1)
297 12:23:20.852238 output: Description: unavailable
298 12:23:20.852289 output: Created: Fri Oct 27 13:23:20 2023
299 12:23:20.852339 output: Type: RAMDisk Image
300 12:23:20.852388 output: Compression: Unknown Compression
301 12:23:20.852438 output: Data Size: 17792522 Bytes = 17375.51 KiB = 16.97 MiB
302 12:23:20.852488 output: Architecture: AArch64
303 12:23:20.852537 output: OS: Linux
304 12:23:20.852587 output: Load Address: unavailable
305 12:23:20.852638 output: Entry Point: unavailable
306 12:23:20.852687 output: Hash algo: crc32
307 12:23:20.852737 output: Hash value: db6a225e
308 12:23:20.852792 output: Default Configuration: 'conf-1'
309 12:23:20.852856 output: Configuration 0 (conf-1)
310 12:23:20.852907 output: Description: mt8192-asurada-spherion-r0
311 12:23:20.852957 output: Kernel: kernel-1
312 12:23:20.853007 output: Init Ramdisk: ramdisk-1
313 12:23:20.853057 output: FDT: fdt-1
314 12:23:20.853107 output: Loadables: kernel-1
315 12:23:20.853156 output:
316 12:23:20.853357 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 12:23:20.853451 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 12:23:20.853557 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 12:23:20.853650 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 12:23:20.853726 No LXC device requested
321 12:23:20.853800 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:23:20.853883 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 12:23:20.853958 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:23:20.854029 Checking files for TFTP limit of 4294967296 bytes.
325 12:23:20.854526 end: 1 tftp-deploy (duration 00:00:39) [common]
326 12:23:20.854627 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:23:20.854718 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:23:20.854847 substitutions:
329 12:23:20.854912 - {DTB}: 11893158/tftp-deploy-cjli5no0/dtb/mt8192-asurada-spherion-r0.dtb
330 12:23:20.854973 - {INITRD}: 11893158/tftp-deploy-cjli5no0/ramdisk/ramdisk.cpio.gz
331 12:23:20.855030 - {KERNEL}: 11893158/tftp-deploy-cjli5no0/kernel/Image
332 12:23:20.855085 - {LAVA_MAC}: None
333 12:23:20.855138 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11893158/extract-nfsrootfs-9jokrc83
334 12:23:20.855192 - {NFS_SERVER_IP}: 192.168.201.1
335 12:23:20.855244 - {PRESEED_CONFIG}: None
336 12:23:20.855296 - {PRESEED_LOCAL}: None
337 12:23:20.855349 - {RAMDISK}: 11893158/tftp-deploy-cjli5no0/ramdisk/ramdisk.cpio.gz
338 12:23:20.855400 - {ROOT_PART}: None
339 12:23:20.855453 - {ROOT}: None
340 12:23:20.855504 - {SERVER_IP}: 192.168.201.1
341 12:23:20.855555 - {TEE}: None
342 12:23:20.855606 Parsed boot commands:
343 12:23:20.855658 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:23:20.855838 Parsed boot commands: tftpboot 192.168.201.1 11893158/tftp-deploy-cjli5no0/kernel/image.itb 11893158/tftp-deploy-cjli5no0/kernel/cmdline
345 12:23:20.855922 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:23:20.856002 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:23:20.856092 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:23:20.856172 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:23:20.856273 Not connected, no need to disconnect.
350 12:23:20.856343 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:23:20.856420 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:23:20.856483 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 12:23:20.860528 Setting prompt string to ['lava-test: # ']
354 12:23:20.860883 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:23:20.861017 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:23:20.861148 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:23:20.861236 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:23:20.861468 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
359 12:23:26.003333 >> Command sent successfully.
360 12:23:26.009795 Returned 0 in 5 seconds
361 12:23:26.110654 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:23:26.112495 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:23:26.113149 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:23:26.113699 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:23:26.114158 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:23:26.114667 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:23:26.116146 [Enter `^Ec?' for help]
369 12:23:26.285419
370 12:23:26.286026
371 12:23:26.286537 F0: 102B 0000
372 12:23:26.287019
373 12:23:26.287463 F3: 1001 0000 [0200]
374 12:23:26.287899
375 12:23:26.289092 F3: 1001 0000
376 12:23:26.289573
377 12:23:26.290059 F7: 102D 0000
378 12:23:26.290520
379 12:23:26.293040 F1: 0000 0000
380 12:23:26.293600
381 12:23:26.294086 V0: 0000 0000 [0001]
382 12:23:26.294541
383 12:23:26.294987 00: 0007 8000
384 12:23:26.295568
385 12:23:26.296323 01: 0000 0000
386 12:23:26.296727
387 12:23:26.297167 BP: 0C00 0209 [0000]
388 12:23:26.297598
389 12:23:26.300326 G0: 1182 0000
390 12:23:26.300892
391 12:23:26.301381 EC: 0000 0021 [4000]
392 12:23:26.301833
393 12:23:26.303467 S7: 0000 0000 [0000]
394 12:23:26.303940
395 12:23:26.304486 CC: 0000 0000 [0001]
396 12:23:26.304947
397 12:23:26.306417 T0: 0000 0040 [010F]
398 12:23:26.306895
399 12:23:26.307373 Jump to BL
400 12:23:26.307827
401 12:23:26.332360
402 12:23:26.333038
403 12:23:26.333535
404 12:23:26.339808 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:23:26.343781 ARM64: Exception handlers installed.
406 12:23:26.346906 ARM64: Testing exception
407 12:23:26.350582 ARM64: Done test exception
408 12:23:26.357999 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:23:26.365160 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:23:26.372496 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:23:26.383512 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:23:26.389613 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:23:26.400057 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:23:26.410763 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:23:26.416929 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:23:26.435366 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:23:26.438403 WDT: Last reset was cold boot
418 12:23:26.442149 SPI1(PAD0) initialized at 2873684 Hz
419 12:23:26.445035 SPI5(PAD0) initialized at 992727 Hz
420 12:23:26.448563 VBOOT: Loading verstage.
421 12:23:26.455518 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:23:26.458925 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:23:26.461717 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:23:26.465159 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:23:26.472834 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:23:26.479351 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:23:26.490265 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 12:23:26.490838
429 12:23:26.491213
430 12:23:26.500420 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:23:26.503722 ARM64: Exception handlers installed.
432 12:23:26.506936 ARM64: Testing exception
433 12:23:26.507514 ARM64: Done test exception
434 12:23:26.513727 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:23:26.517011 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:23:26.531563 Probing TPM: . done!
437 12:23:26.532134 TPM ready after 0 ms
438 12:23:26.539254 Connected to device vid:did:rid of 1ae0:0028:00
439 12:23:26.545824 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
440 12:23:26.592669 Initialized TPM device CR50 revision 0
441 12:23:26.608167 tlcl_send_startup: Startup return code is 0
442 12:23:26.608798 TPM: setup succeeded
443 12:23:26.618513 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:23:26.628004 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:23:26.636950 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:23:26.646197 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:23:26.649136 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:23:26.652501 in-header: 03 07 00 00 08 00 00 00
449 12:23:26.656016 in-data: aa e4 47 04 13 02 00 00
450 12:23:26.659199 Chrome EC: UHEPI supported
451 12:23:26.666135 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:23:26.669288 in-header: 03 95 00 00 08 00 00 00
453 12:23:26.672788 in-data: 18 20 20 08 00 00 00 00
454 12:23:26.673350 Phase 1
455 12:23:26.676034 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:23:26.683557 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:23:26.690749 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:23:26.691330 Recovery requested (1009000e)
459 12:23:26.701094 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:23:26.706619 tlcl_extend: response is 0
461 12:23:26.715906 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:23:26.721514 tlcl_extend: response is 0
463 12:23:26.728222 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:23:26.748825 read SPI 0x210d4 0x2173b: 15144 us, 9047 KB/s, 72.376 Mbps
465 12:23:26.755787 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:23:26.756366
467 12:23:26.756759
468 12:23:26.766298 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:23:26.770142 ARM64: Exception handlers installed.
470 12:23:26.770566 ARM64: Testing exception
471 12:23:26.773313 ARM64: Done test exception
472 12:23:26.793895 pmic_efuse_setting: Set efuses in 11 msecs
473 12:23:26.796991 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:23:26.804044 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:23:26.807490 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:23:26.814180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:23:26.817504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:23:26.823958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:23:26.827422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:23:26.830619 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:23:26.837383 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:23:26.840559 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:23:26.847155 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:23:26.851024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:23:26.854229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:23:26.861075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:23:26.867300 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:23:26.870934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:23:26.878385 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:23:26.881895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:23:26.889304 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:23:26.896372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:23:26.900293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:23:26.903883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:23:26.911272 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:23:26.918906 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:23:26.922888 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:23:26.926014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:23:26.933304 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:23:26.937745 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:23:26.944544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:23:26.948296 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:23:26.952029 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:23:26.959030 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:23:26.963042 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:23:26.966726 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:23:26.974118 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:23:26.977390 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:23:26.984672 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:23:26.988381 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:23:26.992010 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:23:26.995785 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:23:27.003117 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:23:27.006311 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:23:27.009952 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:23:27.013572 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:23:27.021268 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:23:27.024257 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:23:27.028034 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:23:27.031680 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:23:27.035593 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:23:27.042635 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:23:27.046459 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:23:27.050437 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:23:27.057067 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:23:27.064713 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:23:27.068156 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:23:27.079304 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:23:27.086585 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:23:27.090596 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:23:27.093761 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:23:27.100798 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:23:27.108531 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 12:23:27.111681 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:23:27.118636 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 12:23:27.121983 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:23:27.131161 [RTC]rtc_get_frequency_meter,154: input=15, output=765
538 12:23:27.140749 [RTC]rtc_get_frequency_meter,154: input=23, output=949
539 12:23:27.150255 [RTC]rtc_get_frequency_meter,154: input=19, output=857
540 12:23:27.160070 [RTC]rtc_get_frequency_meter,154: input=17, output=810
541 12:23:27.169721 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 12:23:27.178770 [RTC]rtc_get_frequency_meter,154: input=16, output=786
543 12:23:27.188676 [RTC]rtc_get_frequency_meter,154: input=17, output=811
544 12:23:27.192019 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 12:23:27.199082 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 12:23:27.202962 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:23:27.206975 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:23:27.210454 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:23:27.213960 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:23:27.217490 ADC[4]: Raw value=671168 ID=5
551 12:23:27.221738 ADC[3]: Raw value=212549 ID=1
552 12:23:27.222309 RAM Code: 0x51
553 12:23:27.225071 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:23:27.232535 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:23:27.240023 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
556 12:23:27.243578 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
557 12:23:27.246571 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:23:27.252162 in-header: 03 07 00 00 08 00 00 00
559 12:23:27.254842 in-data: aa e4 47 04 13 02 00 00
560 12:23:27.258839 Chrome EC: UHEPI supported
561 12:23:27.265442 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:23:27.269442 in-header: 03 95 00 00 08 00 00 00
563 12:23:27.272944 in-data: 18 20 20 08 00 00 00 00
564 12:23:27.276368 MRC: failed to locate region type 0.
565 12:23:27.279973 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:23:27.283579 DRAM-K: Running full calibration
567 12:23:27.291034 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
568 12:23:27.291605 header.status = 0x0
569 12:23:27.295089 header.version = 0x6 (expected: 0x6)
570 12:23:27.298622 header.size = 0xd00 (expected: 0xd00)
571 12:23:27.302356 header.flags = 0x0
572 12:23:27.305778 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:23:27.324739 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
574 12:23:27.332590 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:23:27.336342 dram_init: ddr_geometry: 0
576 12:23:27.336930 [EMI] MDL number = 0
577 12:23:27.339585 [EMI] Get MDL freq = 0
578 12:23:27.340047 dram_init: ddr_type: 0
579 12:23:27.343292 is_discrete_lpddr4: 1
580 12:23:27.347221 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:23:27.347726
582 12:23:27.348433
583 12:23:27.348959 [Bian_co] ETT version 0.0.0.1
584 12:23:27.354258 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
585 12:23:27.354746
586 12:23:27.357787 dramc_set_vcore_voltage set vcore to 650000
587 12:23:27.358253 Read voltage for 800, 4
588 12:23:27.361772 Vio18 = 0
589 12:23:27.362343 Vcore = 650000
590 12:23:27.362714 Vdram = 0
591 12:23:27.365446 Vddq = 0
592 12:23:27.366021 Vmddr = 0
593 12:23:27.366398 dram_init: config_dvfs: 1
594 12:23:27.372864 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:23:27.376501 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:23:27.379915 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 12:23:27.383649 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 12:23:27.387513 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 12:23:27.390843 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 12:23:27.394879 MEM_TYPE=3, freq_sel=18
601 12:23:27.398432 sv_algorithm_assistance_LP4_1600
602 12:23:27.402202 ============ PULL DRAM RESETB DOWN ============
603 12:23:27.405831 ========== PULL DRAM RESETB DOWN end =========
604 12:23:27.409446 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:23:27.413175 ===================================
606 12:23:27.416652 LPDDR4 DRAM CONFIGURATION
607 12:23:27.420357 ===================================
608 12:23:27.420958 EX_ROW_EN[0] = 0x0
609 12:23:27.423788 EX_ROW_EN[1] = 0x0
610 12:23:27.424290 LP4Y_EN = 0x0
611 12:23:27.427279 WORK_FSP = 0x0
612 12:23:27.427746 WL = 0x2
613 12:23:27.431039 RL = 0x2
614 12:23:27.431505 BL = 0x2
615 12:23:27.434621 RPST = 0x0
616 12:23:27.435092 RD_PRE = 0x0
617 12:23:27.438358 WR_PRE = 0x1
618 12:23:27.438826 WR_PST = 0x0
619 12:23:27.442077 DBI_WR = 0x0
620 12:23:27.442645 DBI_RD = 0x0
621 12:23:27.446126 OTF = 0x1
622 12:23:27.446874 ===================================
623 12:23:27.449770 ===================================
624 12:23:27.453219 ANA top config
625 12:23:27.456827 ===================================
626 12:23:27.457483 DLL_ASYNC_EN = 0
627 12:23:27.459908 ALL_SLAVE_EN = 1
628 12:23:27.463802 NEW_RANK_MODE = 1
629 12:23:27.466998 DLL_IDLE_MODE = 1
630 12:23:27.467465 LP45_APHY_COMB_EN = 1
631 12:23:27.470489 TX_ODT_DIS = 1
632 12:23:27.473605 NEW_8X_MODE = 1
633 12:23:27.477087 ===================================
634 12:23:27.480546 ===================================
635 12:23:27.483476 data_rate = 1600
636 12:23:27.486941 CKR = 1
637 12:23:27.487406 DQ_P2S_RATIO = 8
638 12:23:27.490852 ===================================
639 12:23:27.494283 CA_P2S_RATIO = 8
640 12:23:27.497790 DQ_CA_OPEN = 0
641 12:23:27.501307 DQ_SEMI_OPEN = 0
642 12:23:27.501831 CA_SEMI_OPEN = 0
643 12:23:27.504750 CA_FULL_RATE = 0
644 12:23:27.508308 DQ_CKDIV4_EN = 1
645 12:23:27.511703 CA_CKDIV4_EN = 1
646 12:23:27.515025 CA_PREDIV_EN = 0
647 12:23:27.518270 PH8_DLY = 0
648 12:23:27.518834 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:23:27.521819 DQ_AAMCK_DIV = 4
650 12:23:27.525851 CA_AAMCK_DIV = 4
651 12:23:27.530045 CA_ADMCK_DIV = 4
652 12:23:27.530845 DQ_TRACK_CA_EN = 0
653 12:23:27.532582 CA_PICK = 800
654 12:23:27.536610 CA_MCKIO = 800
655 12:23:27.539683 MCKIO_SEMI = 0
656 12:23:27.543332 PLL_FREQ = 3068
657 12:23:27.543894 DQ_UI_PI_RATIO = 32
658 12:23:27.546273 CA_UI_PI_RATIO = 0
659 12:23:27.550070 ===================================
660 12:23:27.553351 ===================================
661 12:23:27.556862 memory_type:LPDDR4
662 12:23:27.557476 GP_NUM : 10
663 12:23:27.560366 SRAM_EN : 1
664 12:23:27.564399 MD32_EN : 0
665 12:23:27.565201 ===================================
666 12:23:27.567951 [ANA_INIT] >>>>>>>>>>>>>>
667 12:23:27.571849 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:23:27.575363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:23:27.579167 ===================================
670 12:23:27.579761 data_rate = 1600,PCW = 0X7600
671 12:23:27.582541 ===================================
672 12:23:27.586215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:23:27.593706 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:23:27.597078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:23:27.603962 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:23:27.607064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:23:27.610528 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:23:27.611105 [ANA_INIT] flow start
679 12:23:27.613948 [ANA_INIT] PLL >>>>>>>>
680 12:23:27.616936 [ANA_INIT] PLL <<<<<<<<
681 12:23:27.620646 [ANA_INIT] MIDPI >>>>>>>>
682 12:23:27.621218 [ANA_INIT] MIDPI <<<<<<<<
683 12:23:27.624103 [ANA_INIT] DLL >>>>>>>>
684 12:23:27.624758 [ANA_INIT] flow end
685 12:23:27.630511 ============ LP4 DIFF to SE enter ============
686 12:23:27.633820 ============ LP4 DIFF to SE exit ============
687 12:23:27.637004 [ANA_INIT] <<<<<<<<<<<<<
688 12:23:27.640104 [Flow] Enable top DCM control >>>>>
689 12:23:27.643764 [Flow] Enable top DCM control <<<<<
690 12:23:27.646934 Enable DLL master slave shuffle
691 12:23:27.650530 ==============================================================
692 12:23:27.653445 Gating Mode config
693 12:23:27.656910 ==============================================================
694 12:23:27.660021 Config description:
695 12:23:27.670183 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:23:27.677052 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:23:27.680411 SELPH_MODE 0: By rank 1: By Phase
698 12:23:27.686918 ==============================================================
699 12:23:27.690267 GAT_TRACK_EN = 1
700 12:23:27.693480 RX_GATING_MODE = 2
701 12:23:27.696779 RX_GATING_TRACK_MODE = 2
702 12:23:27.700480 SELPH_MODE = 1
703 12:23:27.700982 PICG_EARLY_EN = 1
704 12:23:27.704038 VALID_LAT_VALUE = 1
705 12:23:27.710405 ==============================================================
706 12:23:27.713546 Enter into Gating configuration >>>>
707 12:23:27.716935 Exit from Gating configuration <<<<
708 12:23:27.720364 Enter into DVFS_PRE_config >>>>>
709 12:23:27.730372 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:23:27.733746 Exit from DVFS_PRE_config <<<<<
711 12:23:27.736775 Enter into PICG configuration >>>>
712 12:23:27.739975 Exit from PICG configuration <<<<
713 12:23:27.743524 [RX_INPUT] configuration >>>>>
714 12:23:27.746879 [RX_INPUT] configuration <<<<<
715 12:23:27.749921 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:23:27.756823 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:23:27.763512 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:23:27.770093 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:23:27.776885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:23:27.780453 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:23:27.786647 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:23:27.789724 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:23:27.793691 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:23:27.796685 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:23:27.799844 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:23:27.806717 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:23:27.809893 ===================================
728 12:23:27.813629 LPDDR4 DRAM CONFIGURATION
729 12:23:27.816765 ===================================
730 12:23:27.817191 EX_ROW_EN[0] = 0x0
731 12:23:27.819824 EX_ROW_EN[1] = 0x0
732 12:23:27.820282 LP4Y_EN = 0x0
733 12:23:27.823280 WORK_FSP = 0x0
734 12:23:27.823749 WL = 0x2
735 12:23:27.826632 RL = 0x2
736 12:23:27.827099 BL = 0x2
737 12:23:27.830000 RPST = 0x0
738 12:23:27.830429 RD_PRE = 0x0
739 12:23:27.833229 WR_PRE = 0x1
740 12:23:27.833656 WR_PST = 0x0
741 12:23:27.836841 DBI_WR = 0x0
742 12:23:27.837266 DBI_RD = 0x0
743 12:23:27.839835 OTF = 0x1
744 12:23:27.843575 ===================================
745 12:23:27.846828 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:23:27.850159 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:23:27.856725 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:23:27.859930 ===================================
749 12:23:27.860448 LPDDR4 DRAM CONFIGURATION
750 12:23:27.863232 ===================================
751 12:23:27.866972 EX_ROW_EN[0] = 0x10
752 12:23:27.869794 EX_ROW_EN[1] = 0x0
753 12:23:27.870317 LP4Y_EN = 0x0
754 12:23:27.873138 WORK_FSP = 0x0
755 12:23:27.873622 WL = 0x2
756 12:23:27.876746 RL = 0x2
757 12:23:27.877171 BL = 0x2
758 12:23:27.879872 RPST = 0x0
759 12:23:27.880439 RD_PRE = 0x0
760 12:23:27.883147 WR_PRE = 0x1
761 12:23:27.883591 WR_PST = 0x0
762 12:23:27.886745 DBI_WR = 0x0
763 12:23:27.887164 DBI_RD = 0x0
764 12:23:27.890007 OTF = 0x1
765 12:23:27.893430 ===================================
766 12:23:27.899955 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:23:27.903575 nWR fixed to 40
768 12:23:27.904138 [ModeRegInit_LP4] CH0 RK0
769 12:23:27.906613 [ModeRegInit_LP4] CH0 RK1
770 12:23:27.910020 [ModeRegInit_LP4] CH1 RK0
771 12:23:27.910441 [ModeRegInit_LP4] CH1 RK1
772 12:23:27.913605 match AC timing 12
773 12:23:27.916669 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
774 12:23:27.923357 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:23:27.926594 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:23:27.930062 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:23:27.937140 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:23:27.937681 [EMI DOE] emi_dcm 0
779 12:23:27.943506 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:23:27.944030 ==
781 12:23:27.946383 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:23:27.949866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
783 12:23:27.950291 ==
784 12:23:27.956401 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:23:27.959591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:23:27.970057 [CA 0] Center 37 (7~68) winsize 62
787 12:23:27.973449 [CA 1] Center 37 (7~68) winsize 62
788 12:23:27.976843 [CA 2] Center 35 (4~66) winsize 63
789 12:23:27.980342 [CA 3] Center 35 (5~66) winsize 62
790 12:23:27.983541 [CA 4] Center 34 (4~65) winsize 62
791 12:23:27.986626 [CA 5] Center 34 (3~65) winsize 63
792 12:23:27.987097
793 12:23:27.990028 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:23:27.990588
795 12:23:27.993324 [CATrainingPosCal] consider 1 rank data
796 12:23:27.996915 u2DelayCellTimex100 = 270/100 ps
797 12:23:28.000041 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
798 12:23:28.003310 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
799 12:23:28.009980 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
800 12:23:28.013626 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
801 12:23:28.017102 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
802 12:23:28.020641 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
803 12:23:28.021206
804 12:23:28.023328 CA PerBit enable=1, Macro0, CA PI delay=34
805 12:23:28.023908
806 12:23:28.026724 [CBTSetCACLKResult] CA Dly = 34
807 12:23:28.027302 CS Dly: 5 (0~36)
808 12:23:28.027680 ==
809 12:23:28.030255 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:23:28.036542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
811 12:23:28.037107 ==
812 12:23:28.040089 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:23:28.046547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:23:28.055752 [CA 0] Center 37 (7~68) winsize 62
815 12:23:28.059548 [CA 1] Center 37 (6~68) winsize 63
816 12:23:28.062747 [CA 2] Center 35 (5~66) winsize 62
817 12:23:28.066072 [CA 3] Center 35 (4~66) winsize 63
818 12:23:28.069428 [CA 4] Center 33 (3~64) winsize 62
819 12:23:28.072596 [CA 5] Center 34 (3~65) winsize 63
820 12:23:28.073066
821 12:23:28.076038 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:23:28.076645
823 12:23:28.079593 [CATrainingPosCal] consider 2 rank data
824 12:23:28.082541 u2DelayCellTimex100 = 270/100 ps
825 12:23:28.085982 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
826 12:23:28.089098 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
827 12:23:28.095983 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
828 12:23:28.099193 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
829 12:23:28.102319 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
830 12:23:28.105742 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
831 12:23:28.106311
832 12:23:28.108851 CA PerBit enable=1, Macro0, CA PI delay=34
833 12:23:28.109318
834 12:23:28.112411 [CBTSetCACLKResult] CA Dly = 34
835 12:23:28.112986 CS Dly: 5 (0~37)
836 12:23:28.113360
837 12:23:28.115463 ----->DramcWriteLeveling(PI) begin...
838 12:23:28.119245 ==
839 12:23:28.122258 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:23:28.126498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
841 12:23:28.127061 ==
842 12:23:28.129030 Write leveling (Byte 0): 30 => 30
843 12:23:28.132268 Write leveling (Byte 1): 30 => 30
844 12:23:28.136117 DramcWriteLeveling(PI) end<-----
845 12:23:28.136751
846 12:23:28.137127 ==
847 12:23:28.139673 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:23:28.143775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
849 12:23:28.144407 ==
850 12:23:28.147019 [Gating] SW mode calibration
851 12:23:28.153946 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:23:28.157675 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:23:28.160591 0 6 0 | B1->B0 | 3434 3030 | 1 0 | (0 0) (0 0)
854 12:23:28.168288 0 6 4 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
855 12:23:28.171280 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:23:28.174473 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:23:28.177610 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:23:28.184474 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:23:28.187507 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:23:28.191055 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:23:28.198038 0 7 0 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
862 12:23:28.201171 0 7 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
863 12:23:28.204538 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 12:23:28.211086 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 12:23:28.214329 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 12:23:28.217461 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 12:23:28.224229 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 12:23:28.227820 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 12:23:28.230585 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
870 12:23:28.237606 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
871 12:23:28.240749 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 12:23:28.243840 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 12:23:28.250688 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 12:23:28.253801 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 12:23:28.257495 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 12:23:28.263824 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 12:23:28.267568 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 12:23:28.270490 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 12:23:28.277256 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 12:23:28.280566 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 12:23:28.283856 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 12:23:28.291153 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 12:23:28.294197 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 12:23:28.297508 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 12:23:28.301129 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 12:23:28.307533 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 12:23:28.310921 Total UI for P1: 0, mck2ui 16
888 12:23:28.314116 best dqsien dly found for B0: ( 0, 10, 0)
889 12:23:28.317303 Total UI for P1: 0, mck2ui 16
890 12:23:28.320699 best dqsien dly found for B1: ( 0, 10, 0)
891 12:23:28.324119 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
892 12:23:28.327422 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
893 12:23:28.327980
894 12:23:28.330707 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 12:23:28.334580 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
896 12:23:28.337412 [Gating] SW calibration Done
897 12:23:28.337881 ==
898 12:23:28.340917 Dram Type= 6, Freq= 0, CH_0, rank 0
899 12:23:28.344138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 12:23:28.344743 ==
901 12:23:28.347406 RX Vref Scan: 0
902 12:23:28.347870
903 12:23:28.348537 RX Vref 0 -> 0, step: 1
904 12:23:28.349051
905 12:23:28.350544 RX Delay -130 -> 252, step: 16
906 12:23:28.357106 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
907 12:23:28.360778 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
908 12:23:28.364490 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
909 12:23:28.367348 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
910 12:23:28.370521 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
911 12:23:28.374094 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
912 12:23:28.380428 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
913 12:23:28.384209 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
914 12:23:28.387584 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
915 12:23:28.390776 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
916 12:23:28.394232 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
917 12:23:28.401083 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
918 12:23:28.404461 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
919 12:23:28.407743 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
920 12:23:28.410865 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
921 12:23:28.414682 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
922 12:23:28.417578 ==
923 12:23:28.421179 Dram Type= 6, Freq= 0, CH_0, rank 0
924 12:23:28.424346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
925 12:23:28.424913 ==
926 12:23:28.425285 DQS Delay:
927 12:23:28.427522 DQS0 = 0, DQS1 = 0
928 12:23:28.428081 DQM Delay:
929 12:23:28.430700 DQM0 = 82, DQM1 = 74
930 12:23:28.431262 DQ Delay:
931 12:23:28.434056 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
932 12:23:28.437605 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
933 12:23:28.440531 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
934 12:23:28.444047 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
935 12:23:28.444653
936 12:23:28.445029
937 12:23:28.445375 ==
938 12:23:28.447349 Dram Type= 6, Freq= 0, CH_0, rank 0
939 12:23:28.450491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
940 12:23:28.451004 ==
941 12:23:28.451388
942 12:23:28.451967
943 12:23:28.453904 TX Vref Scan disable
944 12:23:28.457445 == TX Byte 0 ==
945 12:23:28.460833 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 12:23:28.464111 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 12:23:28.467263 == TX Byte 1 ==
948 12:23:28.470553 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
949 12:23:28.473975 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
950 12:23:28.474542 ==
951 12:23:28.477335 Dram Type= 6, Freq= 0, CH_0, rank 0
952 12:23:28.480414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
953 12:23:28.483734 ==
954 12:23:28.494834 TX Vref=22, minBit 0, minWin=27, winSum=444
955 12:23:28.498520 TX Vref=24, minBit 2, minWin=27, winSum=445
956 12:23:28.501783 TX Vref=26, minBit 4, minWin=27, winSum=453
957 12:23:28.505175 TX Vref=28, minBit 2, minWin=28, winSum=458
958 12:23:28.508409 TX Vref=30, minBit 0, minWin=28, winSum=457
959 12:23:28.511597 TX Vref=32, minBit 0, minWin=28, winSum=456
960 12:23:28.518627 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 28
961 12:23:28.519190
962 12:23:28.521956 Final TX Range 1 Vref 28
963 12:23:28.522518
964 12:23:28.522888 ==
965 12:23:28.525391 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:23:28.528619 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
967 12:23:28.529184 ==
968 12:23:28.529557
969 12:23:28.532284
970 12:23:28.532854 TX Vref Scan disable
971 12:23:28.535658 == TX Byte 0 ==
972 12:23:28.539385 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 12:23:28.542508 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 12:23:28.545783 == TX Byte 1 ==
975 12:23:28.548844 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
976 12:23:28.552640 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
977 12:23:28.553245
978 12:23:28.555866 [DATLAT]
979 12:23:28.556482 Freq=800, CH0 RK0
980 12:23:28.556872
981 12:23:28.559221 DATLAT Default: 0xa
982 12:23:28.559683 0, 0xFFFF, sum = 0
983 12:23:28.562192 1, 0xFFFF, sum = 0
984 12:23:28.562677 2, 0xFFFF, sum = 0
985 12:23:28.565611 3, 0xFFFF, sum = 0
986 12:23:28.566179 4, 0xFFFF, sum = 0
987 12:23:28.568765 5, 0xFFFF, sum = 0
988 12:23:28.569235 6, 0xFFFF, sum = 0
989 12:23:28.572271 7, 0xFFFF, sum = 0
990 12:23:28.572742 8, 0x0, sum = 1
991 12:23:28.576292 9, 0x0, sum = 2
992 12:23:28.576860 10, 0x0, sum = 3
993 12:23:28.578815 11, 0x0, sum = 4
994 12:23:28.579283 best_step = 9
995 12:23:28.579696
996 12:23:28.580047 ==
997 12:23:28.582248 Dram Type= 6, Freq= 0, CH_0, rank 0
998 12:23:28.585636 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
999 12:23:28.586241 ==
1000 12:23:28.588785 RX Vref Scan: 1
1001 12:23:28.589248
1002 12:23:28.592277 Set Vref Range= 32 -> 127
1003 12:23:28.592741
1004 12:23:28.593108 RX Vref 32 -> 127, step: 1
1005 12:23:28.593458
1006 12:23:28.595728 RX Delay -111 -> 252, step: 8
1007 12:23:28.596234
1008 12:23:28.599226 Set Vref, RX VrefLevel [Byte0]: 32
1009 12:23:28.602031 [Byte1]: 32
1010 12:23:28.606231
1011 12:23:28.606745 Set Vref, RX VrefLevel [Byte0]: 33
1012 12:23:28.609154 [Byte1]: 33
1013 12:23:28.613555
1014 12:23:28.614071 Set Vref, RX VrefLevel [Byte0]: 34
1015 12:23:28.616693 [Byte1]: 34
1016 12:23:28.621098
1017 12:23:28.621562 Set Vref, RX VrefLevel [Byte0]: 35
1018 12:23:28.624352 [Byte1]: 35
1019 12:23:28.629069
1020 12:23:28.629582 Set Vref, RX VrefLevel [Byte0]: 36
1021 12:23:28.631999 [Byte1]: 36
1022 12:23:28.636540
1023 12:23:28.637061 Set Vref, RX VrefLevel [Byte0]: 37
1024 12:23:28.639983 [Byte1]: 37
1025 12:23:28.644450
1026 12:23:28.644970 Set Vref, RX VrefLevel [Byte0]: 38
1027 12:23:28.647724 [Byte1]: 38
1028 12:23:28.651693
1029 12:23:28.652106 Set Vref, RX VrefLevel [Byte0]: 39
1030 12:23:28.655336 [Byte1]: 39
1031 12:23:28.659362
1032 12:23:28.659867 Set Vref, RX VrefLevel [Byte0]: 40
1033 12:23:28.662734 [Byte1]: 40
1034 12:23:28.667297
1035 12:23:28.667818 Set Vref, RX VrefLevel [Byte0]: 41
1036 12:23:28.670724 [Byte1]: 41
1037 12:23:28.674977
1038 12:23:28.675488 Set Vref, RX VrefLevel [Byte0]: 42
1039 12:23:28.678254 [Byte1]: 42
1040 12:23:28.682628
1041 12:23:28.683140 Set Vref, RX VrefLevel [Byte0]: 43
1042 12:23:28.686040 [Byte1]: 43
1043 12:23:28.690024
1044 12:23:28.690660 Set Vref, RX VrefLevel [Byte0]: 44
1045 12:23:28.693518 [Byte1]: 44
1046 12:23:28.697570
1047 12:23:28.698120 Set Vref, RX VrefLevel [Byte0]: 45
1048 12:23:28.701312 [Byte1]: 45
1049 12:23:28.705549
1050 12:23:28.706101 Set Vref, RX VrefLevel [Byte0]: 46
1051 12:23:28.708726 [Byte1]: 46
1052 12:23:28.713173
1053 12:23:28.713729 Set Vref, RX VrefLevel [Byte0]: 47
1054 12:23:28.716304 [Byte1]: 47
1055 12:23:28.720603
1056 12:23:28.721153 Set Vref, RX VrefLevel [Byte0]: 48
1057 12:23:28.724035 [Byte1]: 48
1058 12:23:28.728355
1059 12:23:28.728906 Set Vref, RX VrefLevel [Byte0]: 49
1060 12:23:28.731440 [Byte1]: 49
1061 12:23:28.735982
1062 12:23:28.736584 Set Vref, RX VrefLevel [Byte0]: 50
1063 12:23:28.739253 [Byte1]: 50
1064 12:23:28.744048
1065 12:23:28.744666 Set Vref, RX VrefLevel [Byte0]: 51
1066 12:23:28.746657 [Byte1]: 51
1067 12:23:28.751052
1068 12:23:28.751506 Set Vref, RX VrefLevel [Byte0]: 52
1069 12:23:28.754345 [Byte1]: 52
1070 12:23:28.758810
1071 12:23:28.759264 Set Vref, RX VrefLevel [Byte0]: 53
1072 12:23:28.761997 [Byte1]: 53
1073 12:23:28.766813
1074 12:23:28.767553 Set Vref, RX VrefLevel [Byte0]: 54
1075 12:23:28.769871 [Byte1]: 54
1076 12:23:28.774070
1077 12:23:28.774617 Set Vref, RX VrefLevel [Byte0]: 55
1078 12:23:28.777702 [Byte1]: 55
1079 12:23:28.781804
1080 12:23:28.782351 Set Vref, RX VrefLevel [Byte0]: 56
1081 12:23:28.785320 [Byte1]: 56
1082 12:23:28.789350
1083 12:23:28.789896 Set Vref, RX VrefLevel [Byte0]: 57
1084 12:23:28.792567 [Byte1]: 57
1085 12:23:28.796910
1086 12:23:28.797465 Set Vref, RX VrefLevel [Byte0]: 58
1087 12:23:28.800416 [Byte1]: 58
1088 12:23:28.804715
1089 12:23:28.805172 Set Vref, RX VrefLevel [Byte0]: 59
1090 12:23:28.808133 [Byte1]: 59
1091 12:23:28.812446
1092 12:23:28.813180 Set Vref, RX VrefLevel [Byte0]: 60
1093 12:23:28.816360 [Byte1]: 60
1094 12:23:28.820147
1095 12:23:28.820643 Set Vref, RX VrefLevel [Byte0]: 61
1096 12:23:28.823602 [Byte1]: 61
1097 12:23:28.827663
1098 12:23:28.830923 Set Vref, RX VrefLevel [Byte0]: 62
1099 12:23:28.831571 [Byte1]: 62
1100 12:23:28.835928
1101 12:23:28.836529 Set Vref, RX VrefLevel [Byte0]: 63
1102 12:23:28.838996 [Byte1]: 63
1103 12:23:28.842901
1104 12:23:28.843459 Set Vref, RX VrefLevel [Byte0]: 64
1105 12:23:28.846175 [Byte1]: 64
1106 12:23:28.850452
1107 12:23:28.850912 Set Vref, RX VrefLevel [Byte0]: 65
1108 12:23:28.853621 [Byte1]: 65
1109 12:23:28.857901
1110 12:23:28.858373 Set Vref, RX VrefLevel [Byte0]: 66
1111 12:23:28.861584 [Byte1]: 66
1112 12:23:28.865774
1113 12:23:28.866250 Set Vref, RX VrefLevel [Byte0]: 67
1114 12:23:28.868776 [Byte1]: 67
1115 12:23:28.873316
1116 12:23:28.873786 Set Vref, RX VrefLevel [Byte0]: 68
1117 12:23:28.876385 [Byte1]: 68
1118 12:23:28.881032
1119 12:23:28.881714 Set Vref, RX VrefLevel [Byte0]: 69
1120 12:23:28.884038 [Byte1]: 69
1121 12:23:28.888470
1122 12:23:28.888913 Set Vref, RX VrefLevel [Byte0]: 70
1123 12:23:28.891760 [Byte1]: 70
1124 12:23:28.896034
1125 12:23:28.896525 Set Vref, RX VrefLevel [Byte0]: 71
1126 12:23:28.899389 [Byte1]: 71
1127 12:23:28.903900
1128 12:23:28.904224 Set Vref, RX VrefLevel [Byte0]: 72
1129 12:23:28.907301 [Byte1]: 72
1130 12:23:28.910988
1131 12:23:28.911294 Set Vref, RX VrefLevel [Byte0]: 73
1132 12:23:28.914661 [Byte1]: 73
1133 12:23:28.918865
1134 12:23:28.919014 Set Vref, RX VrefLevel [Byte0]: 74
1135 12:23:28.922233 [Byte1]: 74
1136 12:23:28.926393
1137 12:23:28.926540 Final RX Vref Byte 0 = 53 to rank0
1138 12:23:28.929910 Final RX Vref Byte 1 = 55 to rank0
1139 12:23:28.933015 Final RX Vref Byte 0 = 53 to rank1
1140 12:23:28.936264 Final RX Vref Byte 1 = 55 to rank1==
1141 12:23:28.939715 Dram Type= 6, Freq= 0, CH_0, rank 0
1142 12:23:28.946179 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1143 12:23:28.946284 ==
1144 12:23:28.946363 DQS Delay:
1145 12:23:28.946494 DQS0 = 0, DQS1 = 0
1146 12:23:28.949741 DQM Delay:
1147 12:23:28.949840 DQM0 = 83, DQM1 = 73
1148 12:23:28.952761 DQ Delay:
1149 12:23:28.956337 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1150 12:23:28.956470 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1151 12:23:28.959748 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1152 12:23:28.966631 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1153 12:23:28.966731
1154 12:23:28.966811
1155 12:23:28.972998 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
1156 12:23:28.976478 CH0 RK0: MR19=606, MR18=3131
1157 12:23:28.983139 CH0_RK0: MR19=0x606, MR18=0x3131, DQSOSC=397, MR23=63, INC=93, DEC=62
1158 12:23:28.983241
1159 12:23:28.986489 ----->DramcWriteLeveling(PI) begin...
1160 12:23:28.986591 ==
1161 12:23:28.990158 Dram Type= 6, Freq= 0, CH_0, rank 1
1162 12:23:28.992940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1163 12:23:28.993042 ==
1164 12:23:28.996760 Write leveling (Byte 0): 31 => 31
1165 12:23:28.999880 Write leveling (Byte 1): 27 => 27
1166 12:23:29.003645 DramcWriteLeveling(PI) end<-----
1167 12:23:29.004057
1168 12:23:29.004416 ==
1169 12:23:29.006672 Dram Type= 6, Freq= 0, CH_0, rank 1
1170 12:23:29.010201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1171 12:23:29.010783 ==
1172 12:23:29.013575 [Gating] SW mode calibration
1173 12:23:29.020290 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1174 12:23:29.026589 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1175 12:23:29.029912 0 6 0 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
1176 12:23:29.033189 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1177 12:23:29.039936 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:23:29.043128 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:23:29.046276 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:23:29.053329 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:23:29.056302 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:23:29.059850 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:23:29.066114 0 7 0 | B1->B0 | 2929 2d2d | 1 0 | (0 0) (0 0)
1184 12:23:29.070071 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1185 12:23:29.072798 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 12:23:29.079714 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 12:23:29.083212 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 12:23:29.086214 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 12:23:29.092971 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 12:23:29.096381 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 12:23:29.099512 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1192 12:23:29.106063 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1193 12:23:29.109521 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 12:23:29.112868 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 12:23:29.119247 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 12:23:29.122799 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 12:23:29.125850 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 12:23:29.132378 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:23:29.135671 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:23:29.138939 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:23:29.145602 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:23:29.148834 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:23:29.152603 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:23:29.158970 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:23:29.162110 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:23:29.165694 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:23:29.169139 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1208 12:23:29.175613 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1209 12:23:29.178866 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 12:23:29.182135 Total UI for P1: 0, mck2ui 16
1211 12:23:29.185399 best dqsien dly found for B0: ( 0, 10, 2)
1212 12:23:29.188922 Total UI for P1: 0, mck2ui 16
1213 12:23:29.192287 best dqsien dly found for B1: ( 0, 10, 2)
1214 12:23:29.195660 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1215 12:23:29.199168 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1216 12:23:29.199580
1217 12:23:29.202428 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1218 12:23:29.205862 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1219 12:23:29.208838 [Gating] SW calibration Done
1220 12:23:29.209293 ==
1221 12:23:29.212522 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 12:23:29.256603 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1223 12:23:29.257167 ==
1224 12:23:29.257530 RX Vref Scan: 0
1225 12:23:29.258229
1226 12:23:29.258585 RX Vref 0 -> 0, step: 1
1227 12:23:29.258910
1228 12:23:29.259223 RX Delay -130 -> 252, step: 16
1229 12:23:29.259540 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1230 12:23:29.259850 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1231 12:23:29.260157 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1232 12:23:29.260506 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1233 12:23:29.260808 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1234 12:23:29.261105 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1235 12:23:29.261402 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1236 12:23:29.261765 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1237 12:23:29.296652 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1238 12:23:29.297593 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1239 12:23:29.298069 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1240 12:23:29.298442 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1241 12:23:29.298777 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1242 12:23:29.299165 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1243 12:23:29.299495 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1244 12:23:29.299806 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1245 12:23:29.300110 ==
1246 12:23:29.300465 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 12:23:29.300777 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1248 12:23:29.301094 ==
1249 12:23:29.301561 DQS Delay:
1250 12:23:29.301883 DQS0 = 0, DQS1 = 0
1251 12:23:29.302188 DQM Delay:
1252 12:23:29.304990 DQM0 = 82, DQM1 = 73
1253 12:23:29.305548 DQ Delay:
1254 12:23:29.305911 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1255 12:23:29.308490 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1256 12:23:29.311639 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1257 12:23:29.315023 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1258 12:23:29.315583
1259 12:23:29.318143
1260 12:23:29.318596 ==
1261 12:23:29.321651 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 12:23:29.325028 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1263 12:23:29.325594 ==
1264 12:23:29.325961
1265 12:23:29.326296
1266 12:23:29.328359 TX Vref Scan disable
1267 12:23:29.328909 == TX Byte 0 ==
1268 12:23:29.334816 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1269 12:23:29.338194 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1270 12:23:29.338651 == TX Byte 1 ==
1271 12:23:29.345405 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1272 12:23:29.348739 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1273 12:23:29.349297 ==
1274 12:23:29.351672 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 12:23:29.355027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1276 12:23:29.355499 ==
1277 12:23:29.369026 TX Vref=22, minBit 0, minWin=27, winSum=448
1278 12:23:29.372034 TX Vref=24, minBit 13, minWin=27, winSum=447
1279 12:23:29.376015 TX Vref=26, minBit 14, minWin=27, winSum=452
1280 12:23:29.379030 TX Vref=28, minBit 2, minWin=28, winSum=455
1281 12:23:29.382595 TX Vref=30, minBit 4, minWin=28, winSum=457
1282 12:23:29.386446 TX Vref=32, minBit 2, minWin=28, winSum=454
1283 12:23:29.393619 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 30
1284 12:23:29.394407
1285 12:23:29.396791 Final TX Range 1 Vref 30
1286 12:23:29.397266
1287 12:23:29.397625 ==
1288 12:23:29.400633 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 12:23:29.403526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1290 12:23:29.403985 ==
1291 12:23:29.404384
1292 12:23:29.404715
1293 12:23:29.407554 TX Vref Scan disable
1294 12:23:29.408106 == TX Byte 0 ==
1295 12:23:29.414595 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1296 12:23:29.417932 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1297 12:23:29.418490 == TX Byte 1 ==
1298 12:23:29.424567 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1299 12:23:29.428015 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1300 12:23:29.428630
1301 12:23:29.428995 [DATLAT]
1302 12:23:29.431080 Freq=800, CH0 RK1
1303 12:23:29.431531
1304 12:23:29.431885 DATLAT Default: 0x9
1305 12:23:29.434707 0, 0xFFFF, sum = 0
1306 12:23:29.435265 1, 0xFFFF, sum = 0
1307 12:23:29.438094 2, 0xFFFF, sum = 0
1308 12:23:29.438652 3, 0xFFFF, sum = 0
1309 12:23:29.441061 4, 0xFFFF, sum = 0
1310 12:23:29.441521 5, 0xFFFF, sum = 0
1311 12:23:29.444669 6, 0xFFFF, sum = 0
1312 12:23:29.445225 7, 0xFFFF, sum = 0
1313 12:23:29.447894 8, 0x0, sum = 1
1314 12:23:29.448390 9, 0x0, sum = 2
1315 12:23:29.451026 10, 0x0, sum = 3
1316 12:23:29.451585 11, 0x0, sum = 4
1317 12:23:29.454496 best_step = 9
1318 12:23:29.454945
1319 12:23:29.455305 ==
1320 12:23:29.457752 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 12:23:29.461305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1322 12:23:29.461766 ==
1323 12:23:29.462126 RX Vref Scan: 0
1324 12:23:29.462460
1325 12:23:29.464253 RX Vref 0 -> 0, step: 1
1326 12:23:29.464711
1327 12:23:29.467820 RX Delay -111 -> 252, step: 8
1328 12:23:29.471275 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1329 12:23:29.477676 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1330 12:23:29.481468 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1331 12:23:29.484582 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1332 12:23:29.488003 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1333 12:23:29.491564 iDelay=217, Bit 5, Center 72 (-47 ~ 192) 240
1334 12:23:29.498075 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1335 12:23:29.501182 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1336 12:23:29.504581 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1337 12:23:29.508000 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1338 12:23:29.511148 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1339 12:23:29.518132 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1340 12:23:29.521169 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1341 12:23:29.524931 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1342 12:23:29.528272 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1343 12:23:29.531296 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1344 12:23:29.531746 ==
1345 12:23:29.535183 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 12:23:29.541473 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1347 12:23:29.542025 ==
1348 12:23:29.542389 DQS Delay:
1349 12:23:29.545051 DQS0 = 0, DQS1 = 0
1350 12:23:29.545612 DQM Delay:
1351 12:23:29.545977 DQM0 = 85, DQM1 = 73
1352 12:23:29.548137 DQ Delay:
1353 12:23:29.551591 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1354 12:23:29.554751 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =96
1355 12:23:29.558174 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =64
1356 12:23:29.561112 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1357 12:23:29.561565
1358 12:23:29.561920
1359 12:23:29.567626 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
1360 12:23:29.570958 CH0 RK1: MR19=606, MR18=4C4C
1361 12:23:29.577685 CH0_RK1: MR19=0x606, MR18=0x4C4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1362 12:23:29.581002 [RxdqsGatingPostProcess] freq 800
1363 12:23:29.584224 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1364 12:23:29.587715 Pre-setting of DQS Precalculation
1365 12:23:29.594379 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1366 12:23:29.594764 ==
1367 12:23:29.597165 Dram Type= 6, Freq= 0, CH_1, rank 0
1368 12:23:29.600679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1369 12:23:29.601071 ==
1370 12:23:29.607251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1371 12:23:29.614010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1372 12:23:29.621736 [CA 0] Center 36 (6~67) winsize 62
1373 12:23:29.624832 [CA 1] Center 36 (6~67) winsize 62
1374 12:23:29.627870 [CA 2] Center 34 (4~65) winsize 62
1375 12:23:29.631731 [CA 3] Center 34 (4~65) winsize 62
1376 12:23:29.635114 [CA 4] Center 33 (3~64) winsize 62
1377 12:23:29.638044 [CA 5] Center 33 (3~64) winsize 62
1378 12:23:29.638493
1379 12:23:29.641875 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1380 12:23:29.642426
1381 12:23:29.644919 [CATrainingPosCal] consider 1 rank data
1382 12:23:29.648322 u2DelayCellTimex100 = 270/100 ps
1383 12:23:29.651820 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1384 12:23:29.655063 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1385 12:23:29.661584 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 12:23:29.664867 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1387 12:23:29.668282 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 12:23:29.671451 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1389 12:23:29.671902
1390 12:23:29.675044 CA PerBit enable=1, Macro0, CA PI delay=33
1391 12:23:29.675598
1392 12:23:29.678613 [CBTSetCACLKResult] CA Dly = 33
1393 12:23:29.679168 CS Dly: 4 (0~35)
1394 12:23:29.679524 ==
1395 12:23:29.682089 Dram Type= 6, Freq= 0, CH_1, rank 1
1396 12:23:29.688209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1397 12:23:29.688756 ==
1398 12:23:29.691479 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1399 12:23:29.698075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1400 12:23:29.707585 [CA 0] Center 36 (6~67) winsize 62
1401 12:23:29.711001 [CA 1] Center 36 (5~67) winsize 63
1402 12:23:29.713989 [CA 2] Center 34 (4~65) winsize 62
1403 12:23:29.717375 [CA 3] Center 34 (4~65) winsize 62
1404 12:23:29.720858 [CA 4] Center 33 (3~63) winsize 61
1405 12:23:29.723988 [CA 5] Center 32 (2~63) winsize 62
1406 12:23:29.724580
1407 12:23:29.727616 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1408 12:23:29.728168
1409 12:23:29.730951 [CATrainingPosCal] consider 2 rank data
1410 12:23:29.733839 u2DelayCellTimex100 = 270/100 ps
1411 12:23:29.737348 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1412 12:23:29.740873 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1413 12:23:29.747897 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 12:23:29.750381 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1415 12:23:29.753899 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
1416 12:23:29.757167 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
1417 12:23:29.757755
1418 12:23:29.760574 CA PerBit enable=1, Macro0, CA PI delay=33
1419 12:23:29.761026
1420 12:23:29.763697 [CBTSetCACLKResult] CA Dly = 33
1421 12:23:29.764159 CS Dly: 4 (0~36)
1422 12:23:29.764566
1423 12:23:29.767140 ----->DramcWriteLeveling(PI) begin...
1424 12:23:29.770879 ==
1425 12:23:29.774202 Dram Type= 6, Freq= 0, CH_1, rank 0
1426 12:23:29.777018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1427 12:23:29.777474 ==
1428 12:23:29.781100 Write leveling (Byte 0): 23 => 23
1429 12:23:29.783629 Write leveling (Byte 1): 26 => 26
1430 12:23:29.786997 DramcWriteLeveling(PI) end<-----
1431 12:23:29.787456
1432 12:23:29.787812 ==
1433 12:23:29.790278 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 12:23:29.793773 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1435 12:23:29.794230 ==
1436 12:23:29.797149 [Gating] SW mode calibration
1437 12:23:29.803733 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1438 12:23:29.807205 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1439 12:23:29.814170 0 6 0 | B1->B0 | 2e2e 2424 | 1 0 | (0 0) (1 0)
1440 12:23:29.817934 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 12:23:29.820600 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 12:23:29.827314 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 12:23:29.830845 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 12:23:29.833988 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 12:23:29.840495 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 12:23:29.844321 0 6 28 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
1447 12:23:29.847547 0 7 0 | B1->B0 | 2a2a 4141 | 0 0 | (1 1) (0 0)
1448 12:23:29.854325 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1449 12:23:29.857345 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 12:23:29.860657 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 12:23:29.867249 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 12:23:29.870611 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 12:23:29.873997 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 12:23:29.880615 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 12:23:29.883715 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1456 12:23:29.887358 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 12:23:29.890757 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 12:23:29.897324 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 12:23:29.900382 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 12:23:29.903938 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 12:23:29.910467 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 12:23:29.913999 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 12:23:29.917397 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 12:23:29.923831 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 12:23:29.927401 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 12:23:29.930597 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 12:23:29.937159 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 12:23:29.940462 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 12:23:29.943871 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 12:23:29.950740 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1471 12:23:29.953932 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1472 12:23:29.957463 Total UI for P1: 0, mck2ui 16
1473 12:23:29.960928 best dqsien dly found for B0: ( 0, 9, 28)
1474 12:23:29.963965 Total UI for P1: 0, mck2ui 16
1475 12:23:29.967571 best dqsien dly found for B1: ( 0, 9, 28)
1476 12:23:29.970971 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1477 12:23:29.974128 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1478 12:23:29.974669
1479 12:23:29.977442 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1480 12:23:29.980709 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1481 12:23:29.984121 [Gating] SW calibration Done
1482 12:23:29.984850 ==
1483 12:23:29.987494 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 12:23:29.990686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1485 12:23:29.991153 ==
1486 12:23:29.993946 RX Vref Scan: 0
1487 12:23:29.994400
1488 12:23:29.997210 RX Vref 0 -> 0, step: 1
1489 12:23:29.997666
1490 12:23:29.998061 RX Delay -130 -> 252, step: 16
1491 12:23:30.004013 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1492 12:23:30.007189 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1493 12:23:30.010492 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1494 12:23:30.014121 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1495 12:23:30.017372 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1496 12:23:30.023843 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1497 12:23:30.027615 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1498 12:23:30.030975 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1499 12:23:30.033886 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1500 12:23:30.037882 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1501 12:23:30.044110 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1502 12:23:30.048248 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1503 12:23:30.051808 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1504 12:23:30.055472 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1505 12:23:30.058944 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1506 12:23:30.063273 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1507 12:23:30.063806 ==
1508 12:23:30.066525 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 12:23:30.070426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1510 12:23:30.070843 ==
1511 12:23:30.071171 DQS Delay:
1512 12:23:30.074131 DQS0 = 0, DQS1 = 0
1513 12:23:30.074551 DQM Delay:
1514 12:23:30.077769 DQM0 = 81, DQM1 = 70
1515 12:23:30.078503 DQ Delay:
1516 12:23:30.081421 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1517 12:23:30.084826 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1518 12:23:30.087954 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1519 12:23:30.091225 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1520 12:23:30.091638
1521 12:23:30.091962
1522 12:23:30.092307 ==
1523 12:23:30.095017 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 12:23:30.098072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1525 12:23:30.098489 ==
1526 12:23:30.098817
1527 12:23:30.099118
1528 12:23:30.101398 TX Vref Scan disable
1529 12:23:30.104814 == TX Byte 0 ==
1530 12:23:30.108093 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1531 12:23:30.111398 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1532 12:23:30.114879 == TX Byte 1 ==
1533 12:23:30.117985 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1534 12:23:30.121386 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1535 12:23:30.121944 ==
1536 12:23:30.124688 Dram Type= 6, Freq= 0, CH_1, rank 0
1537 12:23:30.128083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1538 12:23:30.128743 ==
1539 12:23:30.142613 TX Vref=22, minBit 10, minWin=27, winSum=447
1540 12:23:30.145754 TX Vref=24, minBit 0, minWin=28, winSum=452
1541 12:23:30.149244 TX Vref=26, minBit 8, minWin=27, winSum=454
1542 12:23:30.152430 TX Vref=28, minBit 2, minWin=28, winSum=456
1543 12:23:30.156130 TX Vref=30, minBit 3, minWin=28, winSum=455
1544 12:23:30.162634 TX Vref=32, minBit 9, minWin=27, winSum=454
1545 12:23:30.165788 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 28
1546 12:23:30.166245
1547 12:23:30.169524 Final TX Range 1 Vref 28
1548 12:23:30.170084
1549 12:23:30.170442 ==
1550 12:23:30.172590 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 12:23:30.175796 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1552 12:23:30.176289 ==
1553 12:23:30.176653
1554 12:23:30.179414
1555 12:23:30.179943 TX Vref Scan disable
1556 12:23:30.182542 == TX Byte 0 ==
1557 12:23:30.186105 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1558 12:23:30.189553 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1559 12:23:30.192727 == TX Byte 1 ==
1560 12:23:30.195946 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1561 12:23:30.199534 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1562 12:23:30.202767
1563 12:23:30.203218 [DATLAT]
1564 12:23:30.203574 Freq=800, CH1 RK0
1565 12:23:30.203909
1566 12:23:30.205970 DATLAT Default: 0xa
1567 12:23:30.206423 0, 0xFFFF, sum = 0
1568 12:23:30.209186 1, 0xFFFF, sum = 0
1569 12:23:30.209645 2, 0xFFFF, sum = 0
1570 12:23:30.213001 3, 0xFFFF, sum = 0
1571 12:23:30.213541 4, 0xFFFF, sum = 0
1572 12:23:30.215959 5, 0xFFFF, sum = 0
1573 12:23:30.219509 6, 0xFFFF, sum = 0
1574 12:23:30.220070 7, 0xFFFF, sum = 0
1575 12:23:30.220480 8, 0x0, sum = 1
1576 12:23:30.222747 9, 0x0, sum = 2
1577 12:23:30.223376 10, 0x0, sum = 3
1578 12:23:30.226101 11, 0x0, sum = 4
1579 12:23:30.226666 best_step = 9
1580 12:23:30.227030
1581 12:23:30.227359 ==
1582 12:23:30.228773 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 12:23:30.235841 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1584 12:23:30.236387 ==
1585 12:23:30.236755 RX Vref Scan: 1
1586 12:23:30.237088
1587 12:23:30.238976 Set Vref Range= 32 -> 127
1588 12:23:30.239428
1589 12:23:30.243060 RX Vref 32 -> 127, step: 1
1590 12:23:30.243765
1591 12:23:30.246016 RX Delay -111 -> 252, step: 8
1592 12:23:30.246582
1593 12:23:30.246962 Set Vref, RX VrefLevel [Byte0]: 32
1594 12:23:30.249146 [Byte1]: 32
1595 12:23:30.253849
1596 12:23:30.254332 Set Vref, RX VrefLevel [Byte0]: 33
1597 12:23:30.256814 [Byte1]: 33
1598 12:23:30.261141
1599 12:23:30.261713 Set Vref, RX VrefLevel [Byte0]: 34
1600 12:23:30.264524 [Byte1]: 34
1601 12:23:30.269034
1602 12:23:30.269588 Set Vref, RX VrefLevel [Byte0]: 35
1603 12:23:30.272230 [Byte1]: 35
1604 12:23:30.276619
1605 12:23:30.277141 Set Vref, RX VrefLevel [Byte0]: 36
1606 12:23:30.280012 [Byte1]: 36
1607 12:23:30.284271
1608 12:23:30.285085 Set Vref, RX VrefLevel [Byte0]: 37
1609 12:23:30.287321 [Byte1]: 37
1610 12:23:30.291670
1611 12:23:30.292122 Set Vref, RX VrefLevel [Byte0]: 38
1612 12:23:30.295312 [Byte1]: 38
1613 12:23:30.299385
1614 12:23:30.299930 Set Vref, RX VrefLevel [Byte0]: 39
1615 12:23:30.302787 [Byte1]: 39
1616 12:23:30.307175
1617 12:23:30.307729 Set Vref, RX VrefLevel [Byte0]: 40
1618 12:23:30.310402 [Byte1]: 40
1619 12:23:30.314890
1620 12:23:30.315447 Set Vref, RX VrefLevel [Byte0]: 41
1621 12:23:30.318333 [Byte1]: 41
1622 12:23:30.322258
1623 12:23:30.322710 Set Vref, RX VrefLevel [Byte0]: 42
1624 12:23:30.325635 [Byte1]: 42
1625 12:23:30.330065
1626 12:23:30.330616 Set Vref, RX VrefLevel [Byte0]: 43
1627 12:23:30.333273 [Byte1]: 43
1628 12:23:30.337663
1629 12:23:30.338210 Set Vref, RX VrefLevel [Byte0]: 44
1630 12:23:30.340833 [Byte1]: 44
1631 12:23:30.345469
1632 12:23:30.346024 Set Vref, RX VrefLevel [Byte0]: 45
1633 12:23:30.348717 [Byte1]: 45
1634 12:23:30.352979
1635 12:23:30.353559 Set Vref, RX VrefLevel [Byte0]: 46
1636 12:23:30.356375 [Byte1]: 46
1637 12:23:30.360538
1638 12:23:30.360991 Set Vref, RX VrefLevel [Byte0]: 47
1639 12:23:30.363650 [Byte1]: 47
1640 12:23:30.368515
1641 12:23:30.369060 Set Vref, RX VrefLevel [Byte0]: 48
1642 12:23:30.371905 [Byte1]: 48
1643 12:23:30.376564
1644 12:23:30.377112 Set Vref, RX VrefLevel [Byte0]: 49
1645 12:23:30.379011 [Byte1]: 49
1646 12:23:30.383564
1647 12:23:30.384114 Set Vref, RX VrefLevel [Byte0]: 50
1648 12:23:30.386713 [Byte1]: 50
1649 12:23:30.391315
1650 12:23:30.391938 Set Vref, RX VrefLevel [Byte0]: 51
1651 12:23:30.394589 [Byte1]: 51
1652 12:23:30.398987
1653 12:23:30.399557 Set Vref, RX VrefLevel [Byte0]: 52
1654 12:23:30.402156 [Byte1]: 52
1655 12:23:30.406469
1656 12:23:30.407029 Set Vref, RX VrefLevel [Byte0]: 53
1657 12:23:30.409866 [Byte1]: 53
1658 12:23:30.414571
1659 12:23:30.415115 Set Vref, RX VrefLevel [Byte0]: 54
1660 12:23:30.417718 [Byte1]: 54
1661 12:23:30.421522
1662 12:23:30.421980 Set Vref, RX VrefLevel [Byte0]: 55
1663 12:23:30.425049 [Byte1]: 55
1664 12:23:30.429742
1665 12:23:30.430291 Set Vref, RX VrefLevel [Byte0]: 56
1666 12:23:30.432938 [Byte1]: 56
1667 12:23:30.437068
1668 12:23:30.437616 Set Vref, RX VrefLevel [Byte0]: 57
1669 12:23:30.440586 [Byte1]: 57
1670 12:23:30.445044
1671 12:23:30.445590 Set Vref, RX VrefLevel [Byte0]: 58
1672 12:23:30.448016 [Byte1]: 58
1673 12:23:30.452516
1674 12:23:30.453254 Set Vref, RX VrefLevel [Byte0]: 59
1675 12:23:30.455646 [Byte1]: 59
1676 12:23:30.459931
1677 12:23:30.460440 Set Vref, RX VrefLevel [Byte0]: 60
1678 12:23:30.463218 [Byte1]: 60
1679 12:23:30.467639
1680 12:23:30.468094 Set Vref, RX VrefLevel [Byte0]: 61
1681 12:23:30.471145 [Byte1]: 61
1682 12:23:30.475517
1683 12:23:30.476058 Set Vref, RX VrefLevel [Byte0]: 62
1684 12:23:30.478816 [Byte1]: 62
1685 12:23:30.483255
1686 12:23:30.483806 Set Vref, RX VrefLevel [Byte0]: 63
1687 12:23:30.486311 [Byte1]: 63
1688 12:23:30.490919
1689 12:23:30.491466 Set Vref, RX VrefLevel [Byte0]: 64
1690 12:23:30.494201 [Byte1]: 64
1691 12:23:30.498644
1692 12:23:30.499204 Set Vref, RX VrefLevel [Byte0]: 65
1693 12:23:30.501859 [Byte1]: 65
1694 12:23:30.505778
1695 12:23:30.506244 Set Vref, RX VrefLevel [Byte0]: 66
1696 12:23:30.509243 [Byte1]: 66
1697 12:23:30.513725
1698 12:23:30.514274 Set Vref, RX VrefLevel [Byte0]: 67
1699 12:23:30.517085 [Byte1]: 67
1700 12:23:30.521139
1701 12:23:30.521687 Set Vref, RX VrefLevel [Byte0]: 68
1702 12:23:30.524593 [Byte1]: 68
1703 12:23:30.528893
1704 12:23:30.529440 Set Vref, RX VrefLevel [Byte0]: 69
1705 12:23:30.532567 [Byte1]: 69
1706 12:23:30.536697
1707 12:23:30.537248 Set Vref, RX VrefLevel [Byte0]: 70
1708 12:23:30.539894 [Byte1]: 70
1709 12:23:30.544342
1710 12:23:30.544885 Set Vref, RX VrefLevel [Byte0]: 71
1711 12:23:30.547656 [Byte1]: 71
1712 12:23:30.551959
1713 12:23:30.552563 Set Vref, RX VrefLevel [Byte0]: 72
1714 12:23:30.555108 [Byte1]: 72
1715 12:23:30.559679
1716 12:23:30.560277 Set Vref, RX VrefLevel [Byte0]: 73
1717 12:23:30.562630 [Byte1]: 73
1718 12:23:30.567134
1719 12:23:30.567603 Set Vref, RX VrefLevel [Byte0]: 74
1720 12:23:30.570439 [Byte1]: 74
1721 12:23:30.574997
1722 12:23:30.575541 Set Vref, RX VrefLevel [Byte0]: 75
1723 12:23:30.578152 [Byte1]: 75
1724 12:23:30.582496
1725 12:23:30.582954 Final RX Vref Byte 0 = 58 to rank0
1726 12:23:30.585749 Final RX Vref Byte 1 = 51 to rank0
1727 12:23:30.588858 Final RX Vref Byte 0 = 58 to rank1
1728 12:23:30.592537 Final RX Vref Byte 1 = 51 to rank1==
1729 12:23:30.596093 Dram Type= 6, Freq= 0, CH_1, rank 0
1730 12:23:30.602528 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1731 12:23:30.603084 ==
1732 12:23:30.603450 DQS Delay:
1733 12:23:30.603784 DQS0 = 0, DQS1 = 0
1734 12:23:30.605504 DQM Delay:
1735 12:23:30.605974 DQM0 = 79, DQM1 = 72
1736 12:23:30.609080 DQ Delay:
1737 12:23:30.612564 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1738 12:23:30.613115 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1739 12:23:30.616213 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1740 12:23:30.619186 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1741 12:23:30.622501
1742 12:23:30.623050
1743 12:23:30.629876 [DQSOSCAuto] RK0, (LSB)MR18= 0x5050, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1744 12:23:30.633039 CH1 RK0: MR19=606, MR18=5050
1745 12:23:30.636424 CH1_RK0: MR19=0x606, MR18=0x5050, DQSOSC=389, MR23=63, INC=97, DEC=65
1746 12:23:30.639713
1747 12:23:30.643329 ----->DramcWriteLeveling(PI) begin...
1748 12:23:30.643885 ==
1749 12:23:30.646731 Dram Type= 6, Freq= 0, CH_1, rank 1
1750 12:23:30.649813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1751 12:23:30.650366 ==
1752 12:23:30.653275 Write leveling (Byte 0): 26 => 26
1753 12:23:30.656498 Write leveling (Byte 1): 28 => 28
1754 12:23:30.659598 DramcWriteLeveling(PI) end<-----
1755 12:23:30.660054
1756 12:23:30.660671 ==
1757 12:23:30.662749 Dram Type= 6, Freq= 0, CH_1, rank 1
1758 12:23:30.666098 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1759 12:23:30.666551 ==
1760 12:23:30.669655 [Gating] SW mode calibration
1761 12:23:30.676131 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1762 12:23:30.683009 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1763 12:23:30.686572 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
1764 12:23:30.689408 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1765 12:23:30.693028 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1766 12:23:30.699932 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1767 12:23:30.703151 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1768 12:23:30.706524 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1769 12:23:30.713148 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1770 12:23:30.716605 0 6 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
1771 12:23:30.719669 0 7 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1772 12:23:30.726365 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1773 12:23:30.729642 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1774 12:23:30.733241 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1775 12:23:30.739720 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1776 12:23:30.743566 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1777 12:23:30.746391 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1778 12:23:30.753136 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1779 12:23:30.756709 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1780 12:23:30.759468 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1781 12:23:30.766537 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1782 12:23:30.769956 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1783 12:23:30.772951 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1784 12:23:30.779881 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1785 12:23:30.782899 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1786 12:23:30.786501 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1787 12:23:30.792849 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1788 12:23:30.796044 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1789 12:23:30.799531 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1790 12:23:30.802793 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1791 12:23:30.809614 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 12:23:30.813442 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 12:23:30.816353 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 12:23:30.823065 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1795 12:23:30.826064 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1796 12:23:30.829458 Total UI for P1: 0, mck2ui 16
1797 12:23:30.833143 best dqsien dly found for B0: ( 0, 9, 28)
1798 12:23:30.836111 Total UI for P1: 0, mck2ui 16
1799 12:23:30.839619 best dqsien dly found for B1: ( 0, 9, 28)
1800 12:23:30.842770 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1801 12:23:30.846225 best DQS1 dly(MCK, UI, PI) = (0, 9, 28)
1802 12:23:30.846775
1803 12:23:30.849796 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1804 12:23:30.852818 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 28)
1805 12:23:30.856349 [Gating] SW calibration Done
1806 12:23:30.856896 ==
1807 12:23:30.859374 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 12:23:30.865898 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1809 12:23:30.866395 ==
1810 12:23:30.866762 RX Vref Scan: 0
1811 12:23:30.867101
1812 12:23:30.869797 RX Vref 0 -> 0, step: 1
1813 12:23:30.870345
1814 12:23:30.872580 RX Delay -130 -> 252, step: 16
1815 12:23:30.876879 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1816 12:23:30.879642 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1817 12:23:30.882969 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1818 12:23:30.886423 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1819 12:23:30.892896 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1820 12:23:30.896143 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1821 12:23:30.899542 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1822 12:23:30.902906 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1823 12:23:30.906073 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1824 12:23:30.912945 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1825 12:23:30.916419 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1826 12:23:30.919471 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1827 12:23:30.922574 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1828 12:23:30.926006 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1829 12:23:30.932919 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1830 12:23:30.936164 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1831 12:23:30.936754 ==
1832 12:23:30.939445 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 12:23:30.943422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1834 12:23:30.943974 ==
1835 12:23:30.946268 DQS Delay:
1836 12:23:30.946815 DQS0 = 0, DQS1 = 0
1837 12:23:30.947183 DQM Delay:
1838 12:23:30.949686 DQM0 = 81, DQM1 = 71
1839 12:23:30.950141 DQ Delay:
1840 12:23:30.953075 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1841 12:23:30.956008 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1842 12:23:30.959222 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1843 12:23:30.962742 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =85
1844 12:23:30.963200
1845 12:23:30.963558
1846 12:23:30.963893 ==
1847 12:23:30.965858 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 12:23:30.972575 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1849 12:23:30.973140 ==
1850 12:23:30.973502
1851 12:23:30.973829
1852 12:23:30.974142 TX Vref Scan disable
1853 12:23:30.975893 == TX Byte 0 ==
1854 12:23:30.979629 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1855 12:23:30.982552 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1856 12:23:30.986198 == TX Byte 1 ==
1857 12:23:30.989141 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1858 12:23:30.992957 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1859 12:23:30.996043 ==
1860 12:23:30.999614 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 12:23:31.002705 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1862 12:23:31.003274 ==
1863 12:23:31.015270 TX Vref=22, minBit 8, minWin=27, winSum=448
1864 12:23:31.018634 TX Vref=24, minBit 8, minWin=27, winSum=450
1865 12:23:31.021727 TX Vref=26, minBit 0, minWin=28, winSum=455
1866 12:23:31.025146 TX Vref=28, minBit 0, minWin=28, winSum=459
1867 12:23:31.028837 TX Vref=30, minBit 9, minWin=27, winSum=457
1868 12:23:31.031850 TX Vref=32, minBit 8, minWin=27, winSum=454
1869 12:23:31.038541 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1870 12:23:31.039095
1871 12:23:31.041803 Final TX Range 1 Vref 28
1872 12:23:31.042355
1873 12:23:31.042713 ==
1874 12:23:31.045226 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 12:23:31.048384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1876 12:23:31.048935 ==
1877 12:23:31.049296
1878 12:23:31.051868
1879 12:23:31.052467 TX Vref Scan disable
1880 12:23:31.054863 == TX Byte 0 ==
1881 12:23:31.058381 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1882 12:23:31.064997 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1883 12:23:31.065618 == TX Byte 1 ==
1884 12:23:31.068136 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1885 12:23:31.075008 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1886 12:23:31.075565
1887 12:23:31.075922 [DATLAT]
1888 12:23:31.076313 Freq=800, CH1 RK1
1889 12:23:31.076647
1890 12:23:31.078064 DATLAT Default: 0x9
1891 12:23:31.078519 0, 0xFFFF, sum = 0
1892 12:23:31.081419 1, 0xFFFF, sum = 0
1893 12:23:31.084661 2, 0xFFFF, sum = 0
1894 12:23:31.085120 3, 0xFFFF, sum = 0
1895 12:23:31.087895 4, 0xFFFF, sum = 0
1896 12:23:31.088473 5, 0xFFFF, sum = 0
1897 12:23:31.091536 6, 0xFFFF, sum = 0
1898 12:23:31.091994 7, 0xFFFF, sum = 0
1899 12:23:31.094563 8, 0x0, sum = 1
1900 12:23:31.095022 9, 0x0, sum = 2
1901 12:23:31.095385 10, 0x0, sum = 3
1902 12:23:31.098333 11, 0x0, sum = 4
1903 12:23:31.098894 best_step = 9
1904 12:23:31.099254
1905 12:23:31.099583 ==
1906 12:23:31.101958 Dram Type= 6, Freq= 0, CH_1, rank 1
1907 12:23:31.107969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1908 12:23:31.108505 ==
1909 12:23:31.108866 RX Vref Scan: 0
1910 12:23:31.109202
1911 12:23:31.111334 RX Vref 0 -> 0, step: 1
1912 12:23:31.111783
1913 12:23:31.114812 RX Delay -111 -> 252, step: 8
1914 12:23:31.118346 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1915 12:23:31.121202 iDelay=217, Bit 1, Center 80 (-39 ~ 200) 240
1916 12:23:31.128316 iDelay=217, Bit 2, Center 72 (-47 ~ 192) 240
1917 12:23:31.131629 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1918 12:23:31.134755 iDelay=217, Bit 4, Center 80 (-39 ~ 200) 240
1919 12:23:31.138011 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1920 12:23:31.141531 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1921 12:23:31.148087 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1922 12:23:31.151582 iDelay=217, Bit 8, Center 56 (-63 ~ 176) 240
1923 12:23:31.154513 iDelay=217, Bit 9, Center 56 (-63 ~ 176) 240
1924 12:23:31.157939 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1925 12:23:31.161037 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1926 12:23:31.167776 iDelay=217, Bit 12, Center 80 (-39 ~ 200) 240
1927 12:23:31.171130 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1928 12:23:31.174996 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1929 12:23:31.178038 iDelay=217, Bit 15, Center 80 (-39 ~ 200) 240
1930 12:23:31.178596 ==
1931 12:23:31.181061 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 12:23:31.187699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1933 12:23:31.188157 ==
1934 12:23:31.188575 DQS Delay:
1935 12:23:31.191394 DQS0 = 0, DQS1 = 0
1936 12:23:31.191845 DQM Delay:
1937 12:23:31.192245 DQM0 = 83, DQM1 = 71
1938 12:23:31.194359 DQ Delay:
1939 12:23:31.198037 DQ0 =84, DQ1 =80, DQ2 =72, DQ3 =80
1940 12:23:31.200843 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1941 12:23:31.204521 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1942 12:23:31.208273 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =80
1943 12:23:31.208838
1944 12:23:31.209204
1945 12:23:31.214652 [DQSOSCAuto] RK1, (LSB)MR18= 0x4040, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1946 12:23:31.217610 CH1 RK1: MR19=606, MR18=4040
1947 12:23:31.224484 CH1_RK1: MR19=0x606, MR18=0x4040, DQSOSC=393, MR23=63, INC=95, DEC=63
1948 12:23:31.227972 [RxdqsGatingPostProcess] freq 800
1949 12:23:31.231253 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1950 12:23:31.234145 Pre-setting of DQS Precalculation
1951 12:23:31.241509 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1952 12:23:31.248063 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1953 12:23:31.254286 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1954 12:23:31.254746
1955 12:23:31.255339
1956 12:23:31.257967 [Calibration Summary] 1600 Mbps
1957 12:23:31.258524 CH 0, Rank 0
1958 12:23:31.260763 SW Impedance : PASS
1959 12:23:31.264376 DUTY Scan : NO K
1960 12:23:31.264928 ZQ Calibration : PASS
1961 12:23:31.267657 Jitter Meter : NO K
1962 12:23:31.270953 CBT Training : PASS
1963 12:23:31.271369 Write leveling : PASS
1964 12:23:31.274697 RX DQS gating : PASS
1965 12:23:31.275253 RX DQ/DQS(RDDQC) : PASS
1966 12:23:31.277586 TX DQ/DQS : PASS
1967 12:23:31.280914 RX DATLAT : PASS
1968 12:23:31.281371 RX DQ/DQS(Engine): PASS
1969 12:23:31.283937 TX OE : NO K
1970 12:23:31.284496 All Pass.
1971 12:23:31.284862
1972 12:23:31.287512 CH 0, Rank 1
1973 12:23:31.288060 SW Impedance : PASS
1974 12:23:31.290749 DUTY Scan : NO K
1975 12:23:31.294672 ZQ Calibration : PASS
1976 12:23:31.295222 Jitter Meter : NO K
1977 12:23:31.297899 CBT Training : PASS
1978 12:23:31.301029 Write leveling : PASS
1979 12:23:31.301578 RX DQS gating : PASS
1980 12:23:31.304468 RX DQ/DQS(RDDQC) : PASS
1981 12:23:31.307726 TX DQ/DQS : PASS
1982 12:23:31.308341 RX DATLAT : PASS
1983 12:23:31.311006 RX DQ/DQS(Engine): PASS
1984 12:23:31.314548 TX OE : NO K
1985 12:23:31.315283 All Pass.
1986 12:23:31.315659
1987 12:23:31.315993 CH 1, Rank 0
1988 12:23:31.317390 SW Impedance : PASS
1989 12:23:31.321264 DUTY Scan : NO K
1990 12:23:31.321810 ZQ Calibration : PASS
1991 12:23:31.324341 Jitter Meter : NO K
1992 12:23:31.324904 CBT Training : PASS
1993 12:23:31.327510 Write leveling : PASS
1994 12:23:31.331152 RX DQS gating : PASS
1995 12:23:31.331702 RX DQ/DQS(RDDQC) : PASS
1996 12:23:31.334099 TX DQ/DQS : PASS
1997 12:23:31.337546 RX DATLAT : PASS
1998 12:23:31.338099 RX DQ/DQS(Engine): PASS
1999 12:23:31.340734 TX OE : NO K
2000 12:23:31.341201 All Pass.
2001 12:23:31.341557
2002 12:23:31.344317 CH 1, Rank 1
2003 12:23:31.344872 SW Impedance : PASS
2004 12:23:31.347666 DUTY Scan : NO K
2005 12:23:31.350927 ZQ Calibration : PASS
2006 12:23:31.351474 Jitter Meter : NO K
2007 12:23:31.354229 CBT Training : PASS
2008 12:23:31.357675 Write leveling : PASS
2009 12:23:31.358225 RX DQS gating : PASS
2010 12:23:31.360441 RX DQ/DQS(RDDQC) : PASS
2011 12:23:31.364323 TX DQ/DQS : PASS
2012 12:23:31.364872 RX DATLAT : PASS
2013 12:23:31.367187 RX DQ/DQS(Engine): PASS
2014 12:23:31.367857 TX OE : NO K
2015 12:23:31.370666 All Pass.
2016 12:23:31.371112
2017 12:23:31.371464 DramC Write-DBI off
2018 12:23:31.374002 PER_BANK_REFRESH: Hybrid Mode
2019 12:23:31.377608 TX_TRACKING: ON
2020 12:23:31.380921 [GetDramInforAfterCalByMRR] Vendor 6.
2021 12:23:31.384198 [GetDramInforAfterCalByMRR] Revision 606.
2022 12:23:31.387600 [GetDramInforAfterCalByMRR] Revision 2 0.
2023 12:23:31.388153 MR0 0x3939
2024 12:23:31.388577 MR8 0x1111
2025 12:23:31.394036 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2026 12:23:31.394485
2027 12:23:31.394835 MR0 0x3939
2028 12:23:31.395171 MR8 0x1111
2029 12:23:31.397576 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2030 12:23:31.398129
2031 12:23:31.407944 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2032 12:23:31.411054 [FAST_K] Save calibration result to emmc
2033 12:23:31.414215 [FAST_K] Save calibration result to emmc
2034 12:23:31.417555 dram_init: config_dvfs: 1
2035 12:23:31.420939 dramc_set_vcore_voltage set vcore to 662500
2036 12:23:31.424278 Read voltage for 1200, 2
2037 12:23:31.424838 Vio18 = 0
2038 12:23:31.425202 Vcore = 662500
2039 12:23:31.427401 Vdram = 0
2040 12:23:31.427873 Vddq = 0
2041 12:23:31.428255 Vmddr = 0
2042 12:23:31.434515 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2043 12:23:31.437214 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2044 12:23:31.440679 MEM_TYPE=3, freq_sel=15
2045 12:23:31.443803 sv_algorithm_assistance_LP4_1600
2046 12:23:31.447356 ============ PULL DRAM RESETB DOWN ============
2047 12:23:31.450765 ========== PULL DRAM RESETB DOWN end =========
2048 12:23:31.457049 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2049 12:23:31.460531 ===================================
2050 12:23:31.464026 LPDDR4 DRAM CONFIGURATION
2051 12:23:31.467709 ===================================
2052 12:23:31.468507 EX_ROW_EN[0] = 0x0
2053 12:23:31.470914 EX_ROW_EN[1] = 0x0
2054 12:23:31.471481 LP4Y_EN = 0x0
2055 12:23:31.474086 WORK_FSP = 0x0
2056 12:23:31.474633 WL = 0x4
2057 12:23:31.477496 RL = 0x4
2058 12:23:31.478055 BL = 0x2
2059 12:23:31.480676 RPST = 0x0
2060 12:23:31.481125 RD_PRE = 0x0
2061 12:23:31.484335 WR_PRE = 0x1
2062 12:23:31.484882 WR_PST = 0x0
2063 12:23:31.487363 DBI_WR = 0x0
2064 12:23:31.487913 DBI_RD = 0x0
2065 12:23:31.490759 OTF = 0x1
2066 12:23:31.493756 ===================================
2067 12:23:31.497351 ===================================
2068 12:23:31.497903 ANA top config
2069 12:23:31.500772 ===================================
2070 12:23:31.504012 DLL_ASYNC_EN = 0
2071 12:23:31.507826 ALL_SLAVE_EN = 0
2072 12:23:31.510863 NEW_RANK_MODE = 1
2073 12:23:31.511421 DLL_IDLE_MODE = 1
2074 12:23:31.514446 LP45_APHY_COMB_EN = 1
2075 12:23:31.517482 TX_ODT_DIS = 1
2076 12:23:31.521124 NEW_8X_MODE = 1
2077 12:23:31.524226 ===================================
2078 12:23:31.527823 ===================================
2079 12:23:31.531238 data_rate = 2400
2080 12:23:31.531786 CKR = 1
2081 12:23:31.534215 DQ_P2S_RATIO = 8
2082 12:23:31.537423 ===================================
2083 12:23:31.540880 CA_P2S_RATIO = 8
2084 12:23:31.544119 DQ_CA_OPEN = 0
2085 12:23:31.547720 DQ_SEMI_OPEN = 0
2086 12:23:31.550700 CA_SEMI_OPEN = 0
2087 12:23:31.551251 CA_FULL_RATE = 0
2088 12:23:31.553935 DQ_CKDIV4_EN = 0
2089 12:23:31.557437 CA_CKDIV4_EN = 0
2090 12:23:31.560781 CA_PREDIV_EN = 0
2091 12:23:31.563699 PH8_DLY = 17
2092 12:23:31.567301 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2093 12:23:31.567862 DQ_AAMCK_DIV = 4
2094 12:23:31.570736 CA_AAMCK_DIV = 4
2095 12:23:31.573722 CA_ADMCK_DIV = 4
2096 12:23:31.577045 DQ_TRACK_CA_EN = 0
2097 12:23:31.580271 CA_PICK = 1200
2098 12:23:31.583865 CA_MCKIO = 1200
2099 12:23:31.587373 MCKIO_SEMI = 0
2100 12:23:31.587920 PLL_FREQ = 2366
2101 12:23:31.590383 DQ_UI_PI_RATIO = 32
2102 12:23:31.593845 CA_UI_PI_RATIO = 0
2103 12:23:31.596917 ===================================
2104 12:23:31.600893 ===================================
2105 12:23:31.604017 memory_type:LPDDR4
2106 12:23:31.604619 GP_NUM : 10
2107 12:23:31.607296 SRAM_EN : 1
2108 12:23:31.610046 MD32_EN : 0
2109 12:23:31.613847 ===================================
2110 12:23:31.614399 [ANA_INIT] >>>>>>>>>>>>>>
2111 12:23:31.617414 <<<<<< [CONFIGURE PHASE]: ANA_TX
2112 12:23:31.620446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2113 12:23:31.623916 ===================================
2114 12:23:31.627435 data_rate = 2400,PCW = 0X5b00
2115 12:23:31.630472 ===================================
2116 12:23:31.633753 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2117 12:23:31.640218 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2118 12:23:31.643883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2119 12:23:31.650389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2120 12:23:31.653859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2121 12:23:31.657330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2122 12:23:31.657887 [ANA_INIT] flow start
2123 12:23:31.660012 [ANA_INIT] PLL >>>>>>>>
2124 12:23:31.663630 [ANA_INIT] PLL <<<<<<<<
2125 12:23:31.667129 [ANA_INIT] MIDPI >>>>>>>>
2126 12:23:31.667681 [ANA_INIT] MIDPI <<<<<<<<
2127 12:23:31.670071 [ANA_INIT] DLL >>>>>>>>
2128 12:23:31.673618 [ANA_INIT] DLL <<<<<<<<
2129 12:23:31.674068 [ANA_INIT] flow end
2130 12:23:31.676805 ============ LP4 DIFF to SE enter ============
2131 12:23:31.683734 ============ LP4 DIFF to SE exit ============
2132 12:23:31.684341 [ANA_INIT] <<<<<<<<<<<<<
2133 12:23:31.687430 [Flow] Enable top DCM control >>>>>
2134 12:23:31.690392 [Flow] Enable top DCM control <<<<<
2135 12:23:31.693584 Enable DLL master slave shuffle
2136 12:23:31.700286 ==============================================================
2137 12:23:31.700844 Gating Mode config
2138 12:23:31.707394 ==============================================================
2139 12:23:31.710577 Config description:
2140 12:23:31.716853 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2141 12:23:31.727032 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2142 12:23:31.730681 SELPH_MODE 0: By rank 1: By Phase
2143 12:23:31.737192 ==============================================================
2144 12:23:31.737748 GAT_TRACK_EN = 1
2145 12:23:31.740278 RX_GATING_MODE = 2
2146 12:23:31.743765 RX_GATING_TRACK_MODE = 2
2147 12:23:31.747214 SELPH_MODE = 1
2148 12:23:31.750448 PICG_EARLY_EN = 1
2149 12:23:31.753526 VALID_LAT_VALUE = 1
2150 12:23:31.760332 ==============================================================
2151 12:23:31.763504 Enter into Gating configuration >>>>
2152 12:23:31.766680 Exit from Gating configuration <<<<
2153 12:23:31.770139 Enter into DVFS_PRE_config >>>>>
2154 12:23:31.780351 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2155 12:23:31.783711 Exit from DVFS_PRE_config <<<<<
2156 12:23:31.786923 Enter into PICG configuration >>>>
2157 12:23:31.790158 Exit from PICG configuration <<<<
2158 12:23:31.793489 [RX_INPUT] configuration >>>>>
2159 12:23:31.794037 [RX_INPUT] configuration <<<<<
2160 12:23:31.800574 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2161 12:23:31.806864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2162 12:23:31.810256 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2163 12:23:31.816940 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2164 12:23:31.823613 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2165 12:23:31.830142 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2166 12:23:31.833853 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2167 12:23:31.836726 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2168 12:23:31.843853 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2169 12:23:31.847017 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2170 12:23:31.850315 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2171 12:23:31.856890 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2172 12:23:31.860327 ===================================
2173 12:23:31.860880 LPDDR4 DRAM CONFIGURATION
2174 12:23:31.863287 ===================================
2175 12:23:31.867129 EX_ROW_EN[0] = 0x0
2176 12:23:31.867670 EX_ROW_EN[1] = 0x0
2177 12:23:31.869737 LP4Y_EN = 0x0
2178 12:23:31.870189 WORK_FSP = 0x0
2179 12:23:31.873333 WL = 0x4
2180 12:23:31.876754 RL = 0x4
2181 12:23:31.877211 BL = 0x2
2182 12:23:31.880048 RPST = 0x0
2183 12:23:31.880566 RD_PRE = 0x0
2184 12:23:31.883124 WR_PRE = 0x1
2185 12:23:31.883579 WR_PST = 0x0
2186 12:23:31.886915 DBI_WR = 0x0
2187 12:23:31.887465 DBI_RD = 0x0
2188 12:23:31.890051 OTF = 0x1
2189 12:23:31.893357 ===================================
2190 12:23:31.896690 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2191 12:23:31.900092 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2192 12:23:31.903258 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2193 12:23:31.906574 ===================================
2194 12:23:31.910098 LPDDR4 DRAM CONFIGURATION
2195 12:23:31.913414 ===================================
2196 12:23:31.916703 EX_ROW_EN[0] = 0x10
2197 12:23:31.917162 EX_ROW_EN[1] = 0x0
2198 12:23:31.920374 LP4Y_EN = 0x0
2199 12:23:31.920919 WORK_FSP = 0x0
2200 12:23:31.923606 WL = 0x4
2201 12:23:31.924154 RL = 0x4
2202 12:23:31.926711 BL = 0x2
2203 12:23:31.927256 RPST = 0x0
2204 12:23:31.930166 RD_PRE = 0x0
2205 12:23:31.930716 WR_PRE = 0x1
2206 12:23:31.933331 WR_PST = 0x0
2207 12:23:31.933878 DBI_WR = 0x0
2208 12:23:31.936812 DBI_RD = 0x0
2209 12:23:31.937361 OTF = 0x1
2210 12:23:31.940294 ===================================
2211 12:23:31.946781 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2212 12:23:31.947328 ==
2213 12:23:31.950110 Dram Type= 6, Freq= 0, CH_0, rank 0
2214 12:23:31.956440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2215 12:23:31.957038 ==
2216 12:23:31.957405 [Duty_Offset_Calibration]
2217 12:23:31.960115 B0:0 B1:2 CA:1
2218 12:23:31.960726
2219 12:23:31.963132 [DutyScan_Calibration_Flow] k_type=0
2220 12:23:31.972225
2221 12:23:31.972690 ==CLK 0==
2222 12:23:31.975644 Final CLK duty delay cell = 0
2223 12:23:31.979404 [0] MAX Duty = 5093%(X100), DQS PI = 12
2224 12:23:31.982367 [0] MIN Duty = 4938%(X100), DQS PI = 52
2225 12:23:31.982926 [0] AVG Duty = 5015%(X100)
2226 12:23:31.986051
2227 12:23:31.989063 CH0 CLK Duty spec in!! Max-Min= 155%
2228 12:23:31.992027 [DutyScan_Calibration_Flow] ====Done====
2229 12:23:31.992509
2230 12:23:31.995578 [DutyScan_Calibration_Flow] k_type=1
2231 12:23:32.011542
2232 12:23:32.012089 ==DQS 0 ==
2233 12:23:32.015321 Final DQS duty delay cell = 0
2234 12:23:32.019258 [0] MAX Duty = 5125%(X100), DQS PI = 30
2235 12:23:32.021412 [0] MIN Duty = 5031%(X100), DQS PI = 6
2236 12:23:32.021862 [0] AVG Duty = 5078%(X100)
2237 12:23:32.024920
2238 12:23:32.025465 ==DQS 1 ==
2239 12:23:32.028317 Final DQS duty delay cell = 0
2240 12:23:32.031675 [0] MAX Duty = 5031%(X100), DQS PI = 10
2241 12:23:32.035270 [0] MIN Duty = 4906%(X100), DQS PI = 14
2242 12:23:32.035824 [0] AVG Duty = 4968%(X100)
2243 12:23:32.038514
2244 12:23:32.041657 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2245 12:23:32.042205
2246 12:23:32.044922 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2247 12:23:32.048426 [DutyScan_Calibration_Flow] ====Done====
2248 12:23:32.048975
2249 12:23:32.051610 [DutyScan_Calibration_Flow] k_type=3
2250 12:23:32.067930
2251 12:23:32.068532 ==DQM 0 ==
2252 12:23:32.071264 Final DQM duty delay cell = 0
2253 12:23:32.074765 [0] MAX Duty = 5187%(X100), DQS PI = 20
2254 12:23:32.078061 [0] MIN Duty = 4969%(X100), DQS PI = 40
2255 12:23:32.081473 [0] AVG Duty = 5078%(X100)
2256 12:23:32.082025
2257 12:23:32.082382 ==DQM 1 ==
2258 12:23:32.084786 Final DQM duty delay cell = 0
2259 12:23:32.087709 [0] MAX Duty = 5000%(X100), DQS PI = 56
2260 12:23:32.091438 [0] MIN Duty = 4844%(X100), DQS PI = 0
2261 12:23:32.094353 [0] AVG Duty = 4922%(X100)
2262 12:23:32.094804
2263 12:23:32.098002 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2264 12:23:32.098585
2265 12:23:32.100925 CH0 DQM 1 Duty spec in!! Max-Min= 156%
2266 12:23:32.104697 [DutyScan_Calibration_Flow] ====Done====
2267 12:23:32.105260
2268 12:23:32.107757 [DutyScan_Calibration_Flow] k_type=2
2269 12:23:32.122945
2270 12:23:32.123491 ==DQ 0 ==
2271 12:23:32.126408 Final DQ duty delay cell = -4
2272 12:23:32.129760 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2273 12:23:32.132930 [-4] MIN Duty = 4813%(X100), DQS PI = 56
2274 12:23:32.136158 [-4] AVG Duty = 4937%(X100)
2275 12:23:32.136748
2276 12:23:32.137104 ==DQ 1 ==
2277 12:23:32.140090 Final DQ duty delay cell = -4
2278 12:23:32.143288 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2279 12:23:32.146454 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2280 12:23:32.150053 [-4] AVG Duty = 4969%(X100)
2281 12:23:32.150604
2282 12:23:32.153105 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2283 12:23:32.153655
2284 12:23:32.156786 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2285 12:23:32.159828 [DutyScan_Calibration_Flow] ====Done====
2286 12:23:32.160410 ==
2287 12:23:32.163171 Dram Type= 6, Freq= 0, CH_1, rank 0
2288 12:23:32.166269 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2289 12:23:32.166720 ==
2290 12:23:32.169964 [Duty_Offset_Calibration]
2291 12:23:32.170511 B0:0 B1:4 CA:-5
2292 12:23:32.170872
2293 12:23:32.173086 [DutyScan_Calibration_Flow] k_type=0
2294 12:23:32.183505
2295 12:23:32.184053 ==CLK 0==
2296 12:23:32.186669 Final CLK duty delay cell = 0
2297 12:23:32.190066 [0] MAX Duty = 5125%(X100), DQS PI = 16
2298 12:23:32.193466 [0] MIN Duty = 4875%(X100), DQS PI = 46
2299 12:23:32.193923 [0] AVG Duty = 5000%(X100)
2300 12:23:32.196875
2301 12:23:32.199898 CH1 CLK Duty spec in!! Max-Min= 250%
2302 12:23:32.203450 [DutyScan_Calibration_Flow] ====Done====
2303 12:23:32.204001
2304 12:23:32.206796 [DutyScan_Calibration_Flow] k_type=1
2305 12:23:32.222050
2306 12:23:32.222610 ==DQS 0 ==
2307 12:23:32.225361 Final DQS duty delay cell = 0
2308 12:23:32.228887 [0] MAX Duty = 5125%(X100), DQS PI = 16
2309 12:23:32.231657 [0] MIN Duty = 4875%(X100), DQS PI = 40
2310 12:23:32.235071 [0] AVG Duty = 5000%(X100)
2311 12:23:32.235528
2312 12:23:32.235885 ==DQS 1 ==
2313 12:23:32.238309 Final DQS duty delay cell = -4
2314 12:23:32.241555 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2315 12:23:32.244814 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2316 12:23:32.248738 [-4] AVG Duty = 4953%(X100)
2317 12:23:32.249285
2318 12:23:32.252012 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2319 12:23:32.252606
2320 12:23:32.255004 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2321 12:23:32.258157 [DutyScan_Calibration_Flow] ====Done====
2322 12:23:32.258615
2323 12:23:32.261577 [DutyScan_Calibration_Flow] k_type=3
2324 12:23:32.276982
2325 12:23:32.277521 ==DQM 0 ==
2326 12:23:32.280532 Final DQM duty delay cell = -4
2327 12:23:32.283576 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2328 12:23:32.286992 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2329 12:23:32.290358 [-4] AVG Duty = 4969%(X100)
2330 12:23:32.290910
2331 12:23:32.291273 ==DQM 1 ==
2332 12:23:32.293456 Final DQM duty delay cell = -4
2333 12:23:32.296689 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2334 12:23:32.300262 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2335 12:23:32.303867 [-4] AVG Duty = 4968%(X100)
2336 12:23:32.304472
2337 12:23:32.306840 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2338 12:23:32.307388
2339 12:23:32.310376 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2340 12:23:32.314105 [DutyScan_Calibration_Flow] ====Done====
2341 12:23:32.314658
2342 12:23:32.317363 [DutyScan_Calibration_Flow] k_type=2
2343 12:23:32.334377
2344 12:23:32.334962 ==DQ 0 ==
2345 12:23:32.337481 Final DQ duty delay cell = 0
2346 12:23:32.340797 [0] MAX Duty = 5093%(X100), DQS PI = 0
2347 12:23:32.344850 [0] MIN Duty = 4938%(X100), DQS PI = 44
2348 12:23:32.345411 [0] AVG Duty = 5015%(X100)
2349 12:23:32.345778
2350 12:23:32.347964 ==DQ 1 ==
2351 12:23:32.350807 Final DQ duty delay cell = 0
2352 12:23:32.354101 [0] MAX Duty = 5000%(X100), DQS PI = 8
2353 12:23:32.357318 [0] MIN Duty = 4875%(X100), DQS PI = 0
2354 12:23:32.357921 [0] AVG Duty = 4937%(X100)
2355 12:23:32.358397
2356 12:23:32.360945 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2357 12:23:32.361413
2358 12:23:32.364019 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2359 12:23:32.370941 [DutyScan_Calibration_Flow] ====Done====
2360 12:23:32.374237 nWR fixed to 30
2361 12:23:32.374819 [ModeRegInit_LP4] CH0 RK0
2362 12:23:32.377566 [ModeRegInit_LP4] CH0 RK1
2363 12:23:32.380874 [ModeRegInit_LP4] CH1 RK0
2364 12:23:32.381358 [ModeRegInit_LP4] CH1 RK1
2365 12:23:32.384044 match AC timing 6
2366 12:23:32.387403 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2367 12:23:32.390721 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2368 12:23:32.397598 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2369 12:23:32.400645 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2370 12:23:32.407362 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2371 12:23:32.408027 ==
2372 12:23:32.410785 Dram Type= 6, Freq= 0, CH_0, rank 0
2373 12:23:32.413866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2374 12:23:32.414474 ==
2375 12:23:32.420717 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2376 12:23:32.424055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2377 12:23:32.434039 [CA 0] Center 39 (9~70) winsize 62
2378 12:23:32.437170 [CA 1] Center 39 (8~70) winsize 63
2379 12:23:32.440353 [CA 2] Center 36 (5~67) winsize 63
2380 12:23:32.443635 [CA 3] Center 35 (4~66) winsize 63
2381 12:23:32.447212 [CA 4] Center 34 (3~65) winsize 63
2382 12:23:32.450827 [CA 5] Center 33 (3~64) winsize 62
2383 12:23:32.451373
2384 12:23:32.454035 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2385 12:23:32.454577
2386 12:23:32.456793 [CATrainingPosCal] consider 1 rank data
2387 12:23:32.460473 u2DelayCellTimex100 = 270/100 ps
2388 12:23:32.463544 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2389 12:23:32.467029 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2390 12:23:32.473863 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2391 12:23:32.477030 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2392 12:23:32.480451 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2393 12:23:32.483913 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2394 12:23:32.484503
2395 12:23:32.487131 CA PerBit enable=1, Macro0, CA PI delay=33
2396 12:23:32.487674
2397 12:23:32.490492 [CBTSetCACLKResult] CA Dly = 33
2398 12:23:32.491036 CS Dly: 7 (0~38)
2399 12:23:32.493663 ==
2400 12:23:32.494112 Dram Type= 6, Freq= 0, CH_0, rank 1
2401 12:23:32.500621 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2402 12:23:32.501169 ==
2403 12:23:32.503840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2404 12:23:32.510615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2405 12:23:32.519111 [CA 0] Center 39 (8~70) winsize 63
2406 12:23:32.522455 [CA 1] Center 39 (8~70) winsize 63
2407 12:23:32.525807 [CA 2] Center 35 (5~66) winsize 62
2408 12:23:32.529369 [CA 3] Center 35 (4~66) winsize 63
2409 12:23:32.532641 [CA 4] Center 33 (3~64) winsize 62
2410 12:23:32.536019 [CA 5] Center 34 (3~65) winsize 63
2411 12:23:32.536625
2412 12:23:32.539095 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2413 12:23:32.539636
2414 12:23:32.542568 [CATrainingPosCal] consider 2 rank data
2415 12:23:32.545770 u2DelayCellTimex100 = 270/100 ps
2416 12:23:32.548768 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2417 12:23:32.552389 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2418 12:23:32.559052 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2419 12:23:32.562274 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2420 12:23:32.565959 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2421 12:23:32.569139 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2422 12:23:32.569587
2423 12:23:32.572709 CA PerBit enable=1, Macro0, CA PI delay=33
2424 12:23:32.573283
2425 12:23:32.575624 [CBTSetCACLKResult] CA Dly = 33
2426 12:23:32.576068 CS Dly: 7 (0~39)
2427 12:23:32.576510
2428 12:23:32.579110 ----->DramcWriteLeveling(PI) begin...
2429 12:23:32.582747 ==
2430 12:23:32.585652 Dram Type= 6, Freq= 0, CH_0, rank 0
2431 12:23:32.588935 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2432 12:23:32.589383 ==
2433 12:23:32.592300 Write leveling (Byte 0): 27 => 27
2434 12:23:32.595843 Write leveling (Byte 1): 25 => 25
2435 12:23:32.598963 DramcWriteLeveling(PI) end<-----
2436 12:23:32.599425
2437 12:23:32.599774 ==
2438 12:23:32.602405 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 12:23:32.605710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2440 12:23:32.606264 ==
2441 12:23:32.609219 [Gating] SW mode calibration
2442 12:23:32.615777 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2443 12:23:32.619035 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2444 12:23:32.625846 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2445 12:23:32.629168 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2446 12:23:32.632595 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2447 12:23:32.639008 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2448 12:23:32.642575 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2449 12:23:32.646128 0 11 20 | B1->B0 | 3131 2b2b | 1 0 | (1 0) (1 0)
2450 12:23:32.652649 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2451 12:23:32.656269 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2452 12:23:32.659020 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2453 12:23:32.665608 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2454 12:23:32.669166 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2455 12:23:32.672158 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2456 12:23:32.679426 0 12 16 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
2457 12:23:32.682384 0 12 20 | B1->B0 | 3f3f 4545 | 0 0 | (1 1) (0 0)
2458 12:23:32.686033 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2459 12:23:32.692814 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2460 12:23:32.696376 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2461 12:23:32.699666 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2462 12:23:32.706087 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2463 12:23:32.709169 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2464 12:23:32.712934 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2465 12:23:32.716100 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2466 12:23:32.722388 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2467 12:23:32.726414 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2468 12:23:32.729123 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2469 12:23:32.735881 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2470 12:23:32.739366 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2471 12:23:32.742654 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2472 12:23:32.749404 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2473 12:23:32.752807 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2474 12:23:32.756363 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2475 12:23:32.762891 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2476 12:23:32.765703 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2477 12:23:32.769179 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2478 12:23:32.775990 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 12:23:32.779535 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 12:23:32.782518 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2481 12:23:32.789825 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2482 12:23:32.792288 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2483 12:23:32.795528 Total UI for P1: 0, mck2ui 16
2484 12:23:32.798980 best dqsien dly found for B0: ( 0, 15, 18)
2485 12:23:32.802745 Total UI for P1: 0, mck2ui 16
2486 12:23:32.805526 best dqsien dly found for B1: ( 0, 15, 18)
2487 12:23:32.809333 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2488 12:23:32.812598 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2489 12:23:32.813153
2490 12:23:32.815937 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2491 12:23:32.819352 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2492 12:23:32.822512 [Gating] SW calibration Done
2493 12:23:32.822968 ==
2494 12:23:32.825802 Dram Type= 6, Freq= 0, CH_0, rank 0
2495 12:23:32.829316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2496 12:23:32.829874 ==
2497 12:23:32.832476 RX Vref Scan: 0
2498 12:23:32.833100
2499 12:23:32.835506 RX Vref 0 -> 0, step: 1
2500 12:23:32.835964
2501 12:23:32.836376 RX Delay -40 -> 252, step: 8
2502 12:23:32.841957 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2503 12:23:32.845559 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2504 12:23:32.849038 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2505 12:23:32.852321 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2506 12:23:32.855726 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2507 12:23:32.862477 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2508 12:23:32.865729 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2509 12:23:32.868765 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2510 12:23:32.872650 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2511 12:23:32.875671 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2512 12:23:32.882244 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2513 12:23:32.886019 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2514 12:23:32.888849 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2515 12:23:32.892492 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2516 12:23:32.895833 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2517 12:23:32.902190 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2518 12:23:32.902755 ==
2519 12:23:32.905648 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 12:23:32.908624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2521 12:23:32.909077 ==
2522 12:23:32.909444 DQS Delay:
2523 12:23:32.912010 DQS0 = 0, DQS1 = 0
2524 12:23:32.912500 DQM Delay:
2525 12:23:32.915602 DQM0 = 115, DQM1 = 106
2526 12:23:32.916153 DQ Delay:
2527 12:23:32.919159 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2528 12:23:32.922321 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2529 12:23:32.925724 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2530 12:23:32.928990 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =119
2531 12:23:32.929540
2532 12:23:32.929895
2533 12:23:32.932354 ==
2534 12:23:32.935867 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 12:23:32.939139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2536 12:23:32.939690 ==
2537 12:23:32.940046
2538 12:23:32.940453
2539 12:23:32.941875 TX Vref Scan disable
2540 12:23:32.942323 == TX Byte 0 ==
2541 12:23:32.945939 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2542 12:23:32.952761 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2543 12:23:32.953327 == TX Byte 1 ==
2544 12:23:32.955571 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2545 12:23:32.962263 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2546 12:23:32.962819 ==
2547 12:23:32.965665 Dram Type= 6, Freq= 0, CH_0, rank 0
2548 12:23:32.968938 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2549 12:23:32.969391 ==
2550 12:23:32.980718 TX Vref=22, minBit 10, minWin=24, winSum=411
2551 12:23:32.984400 TX Vref=24, minBit 9, minWin=25, winSum=419
2552 12:23:32.987275 TX Vref=26, minBit 9, minWin=25, winSum=428
2553 12:23:32.990691 TX Vref=28, minBit 8, minWin=26, winSum=432
2554 12:23:32.994512 TX Vref=30, minBit 8, minWin=26, winSum=437
2555 12:23:33.000580 TX Vref=32, minBit 8, minWin=26, winSum=436
2556 12:23:33.004316 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 30
2557 12:23:33.004875
2558 12:23:33.007562 Final TX Range 1 Vref 30
2559 12:23:33.008110
2560 12:23:33.008574 ==
2561 12:23:33.010438 Dram Type= 6, Freq= 0, CH_0, rank 0
2562 12:23:33.014048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2563 12:23:33.014600 ==
2564 12:23:33.016991
2565 12:23:33.017448
2566 12:23:33.017804 TX Vref Scan disable
2567 12:23:33.020844 == TX Byte 0 ==
2568 12:23:33.024028 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2569 12:23:33.027685 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2570 12:23:33.030921 == TX Byte 1 ==
2571 12:23:33.034274 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2572 12:23:33.037674 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2573 12:23:33.038222
2574 12:23:33.041171 [DATLAT]
2575 12:23:33.041717 Freq=1200, CH0 RK0
2576 12:23:33.042083
2577 12:23:33.044352 DATLAT Default: 0xd
2578 12:23:33.044900 0, 0xFFFF, sum = 0
2579 12:23:33.047586 1, 0xFFFF, sum = 0
2580 12:23:33.048141 2, 0xFFFF, sum = 0
2581 12:23:33.050998 3, 0xFFFF, sum = 0
2582 12:23:33.051556 4, 0xFFFF, sum = 0
2583 12:23:33.054368 5, 0xFFFF, sum = 0
2584 12:23:33.054923 6, 0xFFFF, sum = 0
2585 12:23:33.057698 7, 0xFFFF, sum = 0
2586 12:23:33.058160 8, 0xFFFF, sum = 0
2587 12:23:33.061008 9, 0xFFFF, sum = 0
2588 12:23:33.063902 10, 0xFFFF, sum = 0
2589 12:23:33.064452 11, 0x0, sum = 1
2590 12:23:33.064832 12, 0x0, sum = 2
2591 12:23:33.067668 13, 0x0, sum = 3
2592 12:23:33.068132 14, 0x0, sum = 4
2593 12:23:33.070498 best_step = 12
2594 12:23:33.071021
2595 12:23:33.071385 ==
2596 12:23:33.074134 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 12:23:33.077316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2598 12:23:33.077914 ==
2599 12:23:33.080638 RX Vref Scan: 1
2600 12:23:33.081292
2601 12:23:33.081663 Set Vref Range= 32 -> 127
2602 12:23:33.084336
2603 12:23:33.084886 RX Vref 32 -> 127, step: 1
2604 12:23:33.085250
2605 12:23:33.087210 RX Delay -21 -> 252, step: 4
2606 12:23:33.087660
2607 12:23:33.090991 Set Vref, RX VrefLevel [Byte0]: 32
2608 12:23:33.094184 [Byte1]: 32
2609 12:23:33.094741
2610 12:23:33.097404 Set Vref, RX VrefLevel [Byte0]: 33
2611 12:23:33.100486 [Byte1]: 33
2612 12:23:33.105210
2613 12:23:33.105763 Set Vref, RX VrefLevel [Byte0]: 34
2614 12:23:33.108929 [Byte1]: 34
2615 12:23:33.113332
2616 12:23:33.113903 Set Vref, RX VrefLevel [Byte0]: 35
2617 12:23:33.116450 [Byte1]: 35
2618 12:23:33.120988
2619 12:23:33.121543 Set Vref, RX VrefLevel [Byte0]: 36
2620 12:23:33.124639 [Byte1]: 36
2621 12:23:33.129003
2622 12:23:33.129560 Set Vref, RX VrefLevel [Byte0]: 37
2623 12:23:33.132244 [Byte1]: 37
2624 12:23:33.137146
2625 12:23:33.137701 Set Vref, RX VrefLevel [Byte0]: 38
2626 12:23:33.140339 [Byte1]: 38
2627 12:23:33.144754
2628 12:23:33.145206 Set Vref, RX VrefLevel [Byte0]: 39
2629 12:23:33.148108 [Byte1]: 39
2630 12:23:33.152675
2631 12:23:33.153157 Set Vref, RX VrefLevel [Byte0]: 40
2632 12:23:33.156220 [Byte1]: 40
2633 12:23:33.160505
2634 12:23:33.160955 Set Vref, RX VrefLevel [Byte0]: 41
2635 12:23:33.164061 [Byte1]: 41
2636 12:23:33.168514
2637 12:23:33.168965 Set Vref, RX VrefLevel [Byte0]: 42
2638 12:23:33.172031 [Byte1]: 42
2639 12:23:33.176575
2640 12:23:33.177129 Set Vref, RX VrefLevel [Byte0]: 43
2641 12:23:33.179479 [Byte1]: 43
2642 12:23:33.184344
2643 12:23:33.184888 Set Vref, RX VrefLevel [Byte0]: 44
2644 12:23:33.187827 [Byte1]: 44
2645 12:23:33.192366
2646 12:23:33.192916 Set Vref, RX VrefLevel [Byte0]: 45
2647 12:23:33.195657 [Byte1]: 45
2648 12:23:33.200168
2649 12:23:33.200772 Set Vref, RX VrefLevel [Byte0]: 46
2650 12:23:33.203523 [Byte1]: 46
2651 12:23:33.208138
2652 12:23:33.208735 Set Vref, RX VrefLevel [Byte0]: 47
2653 12:23:33.211363 [Byte1]: 47
2654 12:23:33.216047
2655 12:23:33.216628 Set Vref, RX VrefLevel [Byte0]: 48
2656 12:23:33.219313 [Byte1]: 48
2657 12:23:33.224102
2658 12:23:33.224709 Set Vref, RX VrefLevel [Byte0]: 49
2659 12:23:33.227020 [Byte1]: 49
2660 12:23:33.231906
2661 12:23:33.232502 Set Vref, RX VrefLevel [Byte0]: 50
2662 12:23:33.235303 [Byte1]: 50
2663 12:23:33.239902
2664 12:23:33.240502 Set Vref, RX VrefLevel [Byte0]: 51
2665 12:23:33.242994 [Byte1]: 51
2666 12:23:33.247841
2667 12:23:33.248607 Set Vref, RX VrefLevel [Byte0]: 52
2668 12:23:33.251164 [Byte1]: 52
2669 12:23:33.255744
2670 12:23:33.256372 Set Vref, RX VrefLevel [Byte0]: 53
2671 12:23:33.258952 [Byte1]: 53
2672 12:23:33.263830
2673 12:23:33.264431 Set Vref, RX VrefLevel [Byte0]: 54
2674 12:23:33.266736 [Byte1]: 54
2675 12:23:33.271861
2676 12:23:33.272458 Set Vref, RX VrefLevel [Byte0]: 55
2677 12:23:33.275098 [Byte1]: 55
2678 12:23:33.279129
2679 12:23:33.279598 Set Vref, RX VrefLevel [Byte0]: 56
2680 12:23:33.282807 [Byte1]: 56
2681 12:23:33.287237
2682 12:23:33.287793 Set Vref, RX VrefLevel [Byte0]: 57
2683 12:23:33.290376 [Byte1]: 57
2684 12:23:33.295086
2685 12:23:33.298164 Set Vref, RX VrefLevel [Byte0]: 58
2686 12:23:33.301772 [Byte1]: 58
2687 12:23:33.302326
2688 12:23:33.305101 Set Vref, RX VrefLevel [Byte0]: 59
2689 12:23:33.308453 [Byte1]: 59
2690 12:23:33.309003
2691 12:23:33.311756 Set Vref, RX VrefLevel [Byte0]: 60
2692 12:23:33.315142 [Byte1]: 60
2693 12:23:33.318798
2694 12:23:33.319248 Set Vref, RX VrefLevel [Byte0]: 61
2695 12:23:33.322230 [Byte1]: 61
2696 12:23:33.327445
2697 12:23:33.327995 Set Vref, RX VrefLevel [Byte0]: 62
2698 12:23:33.330288 [Byte1]: 62
2699 12:23:33.334589
2700 12:23:33.335040 Set Vref, RX VrefLevel [Byte0]: 63
2701 12:23:33.338403 [Byte1]: 63
2702 12:23:33.342899
2703 12:23:33.343444 Set Vref, RX VrefLevel [Byte0]: 64
2704 12:23:33.346074 [Byte1]: 64
2705 12:23:33.350889
2706 12:23:33.351438 Set Vref, RX VrefLevel [Byte0]: 65
2707 12:23:33.354036 [Byte1]: 65
2708 12:23:33.358663
2709 12:23:33.359221 Set Vref, RX VrefLevel [Byte0]: 66
2710 12:23:33.361888 [Byte1]: 66
2711 12:23:33.366751
2712 12:23:33.367210 Final RX Vref Byte 0 = 45 to rank0
2713 12:23:33.369806 Final RX Vref Byte 1 = 46 to rank0
2714 12:23:33.373291 Final RX Vref Byte 0 = 45 to rank1
2715 12:23:33.376703 Final RX Vref Byte 1 = 46 to rank1==
2716 12:23:33.379524 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 12:23:33.386241 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2718 12:23:33.386782 ==
2719 12:23:33.387143 DQS Delay:
2720 12:23:33.387481 DQS0 = 0, DQS1 = 0
2721 12:23:33.389746 DQM Delay:
2722 12:23:33.390292 DQM0 = 114, DQM1 = 105
2723 12:23:33.392913 DQ Delay:
2724 12:23:33.396382 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2725 12:23:33.400031 DQ4 =120, DQ5 =106, DQ6 =124, DQ7 =120
2726 12:23:33.403233 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2727 12:23:33.406439 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2728 12:23:33.406898
2729 12:23:33.407256
2730 12:23:33.413071 [DQSOSCAuto] RK0, (LSB)MR18= 0x909, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2731 12:23:33.416695 CH0 RK0: MR19=404, MR18=909
2732 12:23:33.423151 CH0_RK0: MR19=0x404, MR18=0x909, DQSOSC=406, MR23=63, INC=39, DEC=26
2733 12:23:33.423704
2734 12:23:33.426495 ----->DramcWriteLeveling(PI) begin...
2735 12:23:33.427048 ==
2736 12:23:33.429592 Dram Type= 6, Freq= 0, CH_0, rank 1
2737 12:23:33.433184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2738 12:23:33.433738 ==
2739 12:23:33.436345 Write leveling (Byte 0): 28 => 28
2740 12:23:33.440127 Write leveling (Byte 1): 25 => 25
2741 12:23:33.443278 DramcWriteLeveling(PI) end<-----
2742 12:23:33.443830
2743 12:23:33.444252 ==
2744 12:23:33.446397 Dram Type= 6, Freq= 0, CH_0, rank 1
2745 12:23:33.449896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2746 12:23:33.452870 ==
2747 12:23:33.453343 [Gating] SW mode calibration
2748 12:23:33.463300 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2749 12:23:33.465993 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2750 12:23:33.469800 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2751 12:23:33.476378 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2752 12:23:33.479795 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2753 12:23:33.483225 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2754 12:23:33.489466 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2755 12:23:33.492757 0 11 20 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (1 0)
2756 12:23:33.496126 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2757 12:23:33.503178 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2758 12:23:33.506809 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2759 12:23:33.509656 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2760 12:23:33.516442 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2761 12:23:33.519708 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2762 12:23:33.523135 0 12 16 | B1->B0 | 2626 3232 | 0 1 | (0 0) (0 0)
2763 12:23:33.529715 0 12 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2764 12:23:33.533111 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2765 12:23:33.536431 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2766 12:23:33.539788 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2767 12:23:33.546493 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2768 12:23:33.549600 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2769 12:23:33.552898 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2770 12:23:33.559541 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2771 12:23:33.562871 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2772 12:23:33.566047 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2773 12:23:33.572824 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2774 12:23:33.576276 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2775 12:23:33.579331 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2776 12:23:33.586186 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2777 12:23:33.589450 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2778 12:23:33.592383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2779 12:23:33.599425 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2780 12:23:33.603239 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2781 12:23:33.606087 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2782 12:23:33.612474 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2783 12:23:33.615774 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2784 12:23:33.619072 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2785 12:23:33.626332 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2786 12:23:33.629378 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2787 12:23:33.632800 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2788 12:23:33.639347 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2789 12:23:33.639952 Total UI for P1: 0, mck2ui 16
2790 12:23:33.646181 best dqsien dly found for B0: ( 0, 15, 18)
2791 12:23:33.646731 Total UI for P1: 0, mck2ui 16
2792 12:23:33.652948 best dqsien dly found for B1: ( 0, 15, 20)
2793 12:23:33.656862 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2794 12:23:33.659161 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2795 12:23:33.659709
2796 12:23:33.662728 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2797 12:23:33.665446 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2798 12:23:33.669160 [Gating] SW calibration Done
2799 12:23:33.669717 ==
2800 12:23:33.672309 Dram Type= 6, Freq= 0, CH_0, rank 1
2801 12:23:33.675891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2802 12:23:33.676505 ==
2803 12:23:33.678921 RX Vref Scan: 0
2804 12:23:33.679374
2805 12:23:33.679730 RX Vref 0 -> 0, step: 1
2806 12:23:33.680063
2807 12:23:33.681988 RX Delay -40 -> 252, step: 8
2808 12:23:33.685492 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2809 12:23:33.692355 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2810 12:23:33.696058 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2811 12:23:33.699391 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2812 12:23:33.702923 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2813 12:23:33.705605 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2814 12:23:33.712839 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2815 12:23:33.715700 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2816 12:23:33.719213 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2817 12:23:33.722478 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2818 12:23:33.725877 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2819 12:23:33.729164 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2820 12:23:33.736029 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2821 12:23:33.738978 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2822 12:23:33.742803 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2823 12:23:33.746311 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2824 12:23:33.746863 ==
2825 12:23:33.749111 Dram Type= 6, Freq= 0, CH_0, rank 1
2826 12:23:33.756392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2827 12:23:33.756938 ==
2828 12:23:33.757304 DQS Delay:
2829 12:23:33.758986 DQS0 = 0, DQS1 = 0
2830 12:23:33.759441 DQM Delay:
2831 12:23:33.759802 DQM0 = 113, DQM1 = 106
2832 12:23:33.762761 DQ Delay:
2833 12:23:33.765774 DQ0 =107, DQ1 =115, DQ2 =111, DQ3 =107
2834 12:23:33.769498 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2835 12:23:33.772514 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2836 12:23:33.776162 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2837 12:23:33.776771
2838 12:23:33.777131
2839 12:23:33.777465 ==
2840 12:23:33.778976 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 12:23:33.782157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2842 12:23:33.785589 ==
2843 12:23:33.786046
2844 12:23:33.786405
2845 12:23:33.786738 TX Vref Scan disable
2846 12:23:33.788877 == TX Byte 0 ==
2847 12:23:33.792533 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2848 12:23:33.795669 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2849 12:23:33.798813 == TX Byte 1 ==
2850 12:23:33.802323 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2851 12:23:33.805438 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2852 12:23:33.806001 ==
2853 12:23:33.808571 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 12:23:33.815652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2855 12:23:33.816296 ==
2856 12:23:33.826684 TX Vref=22, minBit 8, minWin=25, winSum=421
2857 12:23:33.830142 TX Vref=24, minBit 1, minWin=26, winSum=427
2858 12:23:33.833246 TX Vref=26, minBit 1, minWin=26, winSum=429
2859 12:23:33.836689 TX Vref=28, minBit 1, minWin=26, winSum=432
2860 12:23:33.839815 TX Vref=30, minBit 9, minWin=26, winSum=433
2861 12:23:33.843707 TX Vref=32, minBit 8, minWin=26, winSum=433
2862 12:23:33.850485 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
2863 12:23:33.851037
2864 12:23:33.853551 Final TX Range 1 Vref 30
2865 12:23:33.854101
2866 12:23:33.854462 ==
2867 12:23:33.856874 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 12:23:33.859797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2869 12:23:33.860335 ==
2870 12:23:33.860971
2871 12:23:33.861332
2872 12:23:33.863463 TX Vref Scan disable
2873 12:23:33.866512 == TX Byte 0 ==
2874 12:23:33.870059 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2875 12:23:33.873172 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2876 12:23:33.876894 == TX Byte 1 ==
2877 12:23:33.880586 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2878 12:23:33.883813 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2879 12:23:33.884314
2880 12:23:33.886693 [DATLAT]
2881 12:23:33.887139 Freq=1200, CH0 RK1
2882 12:23:33.887496
2883 12:23:33.889981 DATLAT Default: 0xc
2884 12:23:33.890428 0, 0xFFFF, sum = 0
2885 12:23:33.893072 1, 0xFFFF, sum = 0
2886 12:23:33.893529 2, 0xFFFF, sum = 0
2887 12:23:33.896695 3, 0xFFFF, sum = 0
2888 12:23:33.897254 4, 0xFFFF, sum = 0
2889 12:23:33.899761 5, 0xFFFF, sum = 0
2890 12:23:33.900262 6, 0xFFFF, sum = 0
2891 12:23:33.903545 7, 0xFFFF, sum = 0
2892 12:23:33.904101 8, 0xFFFF, sum = 0
2893 12:23:33.906978 9, 0xFFFF, sum = 0
2894 12:23:33.909729 10, 0xFFFF, sum = 0
2895 12:23:33.910195 11, 0x0, sum = 1
2896 12:23:33.910562 12, 0x0, sum = 2
2897 12:23:33.913192 13, 0x0, sum = 3
2898 12:23:33.913678 14, 0x0, sum = 4
2899 12:23:33.916739 best_step = 12
2900 12:23:33.917288
2901 12:23:33.917711 ==
2902 12:23:33.920085 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 12:23:33.922962 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2904 12:23:33.923518 ==
2905 12:23:33.926390 RX Vref Scan: 0
2906 12:23:33.926941
2907 12:23:33.927304 RX Vref 0 -> 0, step: 1
2908 12:23:33.929594
2909 12:23:33.930059 RX Delay -21 -> 252, step: 4
2910 12:23:33.937129 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2911 12:23:33.940259 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2912 12:23:33.943553 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2913 12:23:33.947056 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2914 12:23:33.950325 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2915 12:23:33.956420 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2916 12:23:33.960093 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
2917 12:23:33.963529 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2918 12:23:33.966742 iDelay=195, Bit 8, Center 92 (31 ~ 154) 124
2919 12:23:33.969942 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2920 12:23:33.976875 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2921 12:23:33.979992 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2922 12:23:33.983280 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2923 12:23:33.986738 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2924 12:23:33.990263 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
2925 12:23:33.996925 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2926 12:23:33.997384 ==
2927 12:23:34.000576 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 12:23:34.003793 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2929 12:23:34.004396 ==
2930 12:23:34.004765 DQS Delay:
2931 12:23:34.006808 DQS0 = 0, DQS1 = 0
2932 12:23:34.007266 DQM Delay:
2933 12:23:34.010299 DQM0 = 114, DQM1 = 105
2934 12:23:34.010855 DQ Delay:
2935 12:23:34.013411 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2936 12:23:34.016940 DQ4 =118, DQ5 =106, DQ6 =122, DQ7 =122
2937 12:23:34.019919 DQ8 =92, DQ9 =90, DQ10 =110, DQ11 =96
2938 12:23:34.024287 DQ12 =112, DQ13 =112, DQ14 =116, DQ15 =114
2939 12:23:34.024844
2940 12:23:34.025208
2941 12:23:34.033572 [DQSOSCAuto] RK1, (LSB)MR18= 0x1212, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2942 12:23:34.036908 CH0 RK1: MR19=404, MR18=1212
2943 12:23:34.040327 CH0_RK1: MR19=0x404, MR18=0x1212, DQSOSC=403, MR23=63, INC=40, DEC=26
2944 12:23:34.043961 [RxdqsGatingPostProcess] freq 1200
2945 12:23:34.050517 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2946 12:23:34.053721 Pre-setting of DQS Precalculation
2947 12:23:34.057078 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2948 12:23:34.057630 ==
2949 12:23:34.060028 Dram Type= 6, Freq= 0, CH_1, rank 0
2950 12:23:34.067272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2951 12:23:34.067831 ==
2952 12:23:34.070438 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2953 12:23:34.076534 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2954 12:23:34.085360 [CA 0] Center 37 (7~68) winsize 62
2955 12:23:34.088901 [CA 1] Center 37 (7~68) winsize 62
2956 12:23:34.092160 [CA 2] Center 34 (4~65) winsize 62
2957 12:23:34.095942 [CA 3] Center 33 (3~64) winsize 62
2958 12:23:34.098873 [CA 4] Center 32 (2~63) winsize 62
2959 12:23:34.102243 [CA 5] Center 32 (1~63) winsize 63
2960 12:23:34.102795
2961 12:23:34.105640 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2962 12:23:34.106187
2963 12:23:34.108861 [CATrainingPosCal] consider 1 rank data
2964 12:23:34.112334 u2DelayCellTimex100 = 270/100 ps
2965 12:23:34.115991 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2966 12:23:34.118973 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2967 12:23:34.125468 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2968 12:23:34.129082 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2969 12:23:34.131888 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2970 12:23:34.135388 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2971 12:23:34.135843
2972 12:23:34.139207 CA PerBit enable=1, Macro0, CA PI delay=32
2973 12:23:34.139765
2974 12:23:34.142453 [CBTSetCACLKResult] CA Dly = 32
2975 12:23:34.142999 CS Dly: 6 (0~37)
2976 12:23:34.143362 ==
2977 12:23:34.145331 Dram Type= 6, Freq= 0, CH_1, rank 1
2978 12:23:34.152250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2979 12:23:34.152807 ==
2980 12:23:34.155735 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2981 12:23:34.161624 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2982 12:23:34.170887 [CA 0] Center 37 (7~68) winsize 62
2983 12:23:34.173843 [CA 1] Center 37 (6~68) winsize 63
2984 12:23:34.177126 [CA 2] Center 34 (3~65) winsize 63
2985 12:23:34.180741 [CA 3] Center 33 (3~64) winsize 62
2986 12:23:34.183877 [CA 4] Center 32 (2~63) winsize 62
2987 12:23:34.187107 [CA 5] Center 32 (1~63) winsize 63
2988 12:23:34.187568
2989 12:23:34.190707 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2990 12:23:34.191316
2991 12:23:34.193726 [CATrainingPosCal] consider 2 rank data
2992 12:23:34.197077 u2DelayCellTimex100 = 270/100 ps
2993 12:23:34.200556 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2994 12:23:34.203956 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2995 12:23:34.210751 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2996 12:23:34.213587 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2997 12:23:34.217099 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2998 12:23:34.220734 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2999 12:23:34.221279
3000 12:23:34.223937 CA PerBit enable=1, Macro0, CA PI delay=32
3001 12:23:34.224570
3002 12:23:34.227498 [CBTSetCACLKResult] CA Dly = 32
3003 12:23:34.228134 CS Dly: 6 (0~38)
3004 12:23:34.228559
3005 12:23:34.230410 ----->DramcWriteLeveling(PI) begin...
3006 12:23:34.233796 ==
3007 12:23:34.237069 Dram Type= 6, Freq= 0, CH_1, rank 0
3008 12:23:34.240310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3009 12:23:34.240765 ==
3010 12:23:34.243925 Write leveling (Byte 0): 21 => 21
3011 12:23:34.247200 Write leveling (Byte 1): 22 => 22
3012 12:23:34.250597 DramcWriteLeveling(PI) end<-----
3013 12:23:34.251142
3014 12:23:34.251496 ==
3015 12:23:34.253988 Dram Type= 6, Freq= 0, CH_1, rank 0
3016 12:23:34.256899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3017 12:23:34.257351 ==
3018 12:23:34.260311 [Gating] SW mode calibration
3019 12:23:34.266867 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3020 12:23:34.273677 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3021 12:23:34.277124 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3022 12:23:34.280553 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3023 12:23:34.283835 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3024 12:23:34.290555 0 11 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3025 12:23:34.293974 0 11 16 | B1->B0 | 3232 2727 | 1 0 | (1 1) (1 0)
3026 12:23:34.296970 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3027 12:23:34.304018 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 12:23:34.306959 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3029 12:23:34.310539 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3030 12:23:34.317099 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3031 12:23:34.320403 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3032 12:23:34.323626 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
3033 12:23:34.330246 0 12 16 | B1->B0 | 3434 4444 | 0 0 | (1 1) (0 0)
3034 12:23:34.333709 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 12:23:34.336971 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 12:23:34.343485 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3037 12:23:34.346851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3038 12:23:34.350353 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3039 12:23:34.357449 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3040 12:23:34.360341 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3041 12:23:34.363682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3042 12:23:34.370292 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3043 12:23:34.373297 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 12:23:34.376902 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 12:23:34.383547 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 12:23:34.386794 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 12:23:34.389972 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 12:23:34.396572 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 12:23:34.399990 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 12:23:34.403189 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 12:23:34.406977 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3052 12:23:34.413413 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3053 12:23:34.416877 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3054 12:23:34.420246 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3055 12:23:34.426851 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3056 12:23:34.430354 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3057 12:23:34.433231 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3058 12:23:34.440097 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3059 12:23:34.443813 Total UI for P1: 0, mck2ui 16
3060 12:23:34.446486 best dqsien dly found for B0: ( 0, 15, 16)
3061 12:23:34.450300 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3062 12:23:34.453872 Total UI for P1: 0, mck2ui 16
3063 12:23:34.456793 best dqsien dly found for B1: ( 0, 15, 18)
3064 12:23:34.460352 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3065 12:23:34.463540 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3066 12:23:34.464080
3067 12:23:34.466515 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3068 12:23:34.470195 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3069 12:23:34.473479 [Gating] SW calibration Done
3070 12:23:34.473935 ==
3071 12:23:34.476546 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 12:23:34.480015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3073 12:23:34.483080 ==
3074 12:23:34.483539 RX Vref Scan: 0
3075 12:23:34.483902
3076 12:23:34.486476 RX Vref 0 -> 0, step: 1
3077 12:23:34.486927
3078 12:23:34.489693 RX Delay -40 -> 252, step: 8
3079 12:23:34.493037 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3080 12:23:34.496807 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3081 12:23:34.499775 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3082 12:23:34.503395 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3083 12:23:34.509778 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3084 12:23:34.512978 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3085 12:23:34.516697 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3086 12:23:34.519824 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3087 12:23:34.523449 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3088 12:23:34.526764 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3089 12:23:34.532955 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3090 12:23:34.536814 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3091 12:23:34.539984 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3092 12:23:34.543479 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3093 12:23:34.550148 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3094 12:23:34.553257 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3095 12:23:34.553814 ==
3096 12:23:34.556915 Dram Type= 6, Freq= 0, CH_1, rank 0
3097 12:23:34.560061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3098 12:23:34.560664 ==
3099 12:23:34.563279 DQS Delay:
3100 12:23:34.563732 DQS0 = 0, DQS1 = 0
3101 12:23:34.564089 DQM Delay:
3102 12:23:34.566619 DQM0 = 116, DQM1 = 107
3103 12:23:34.567188 DQ Delay:
3104 12:23:34.569889 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3105 12:23:34.573016 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3106 12:23:34.576656 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =103
3107 12:23:34.579947 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =115
3108 12:23:34.583416
3109 12:23:34.583966
3110 12:23:34.584463 ==
3111 12:23:34.586473 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 12:23:34.589711 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3113 12:23:34.590170 ==
3114 12:23:34.590523
3115 12:23:34.590898
3116 12:23:34.593445 TX Vref Scan disable
3117 12:23:34.594001 == TX Byte 0 ==
3118 12:23:34.599601 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3119 12:23:34.603273 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3120 12:23:34.603825 == TX Byte 1 ==
3121 12:23:34.610063 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3122 12:23:34.612900 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3123 12:23:34.613453 ==
3124 12:23:34.616577 Dram Type= 6, Freq= 0, CH_1, rank 0
3125 12:23:34.619595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3126 12:23:34.620142 ==
3127 12:23:34.632085 TX Vref=22, minBit 3, minWin=25, winSum=410
3128 12:23:34.635566 TX Vref=24, minBit 11, minWin=25, winSum=418
3129 12:23:34.638613 TX Vref=26, minBit 15, minWin=25, winSum=422
3130 12:23:34.642002 TX Vref=28, minBit 3, minWin=26, winSum=430
3131 12:23:34.645240 TX Vref=30, minBit 0, minWin=26, winSum=429
3132 12:23:34.652099 TX Vref=32, minBit 9, minWin=26, winSum=430
3133 12:23:34.655234 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 28
3134 12:23:34.655780
3135 12:23:34.658544 Final TX Range 1 Vref 28
3136 12:23:34.659089
3137 12:23:34.659449 ==
3138 12:23:34.661525 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 12:23:34.665128 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3140 12:23:34.665680 ==
3141 12:23:34.668546
3142 12:23:34.669001
3143 12:23:34.669360 TX Vref Scan disable
3144 12:23:34.671849 == TX Byte 0 ==
3145 12:23:34.675559 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3146 12:23:34.678778 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3147 12:23:34.681655 == TX Byte 1 ==
3148 12:23:34.685198 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3149 12:23:34.688405 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3150 12:23:34.691763
3151 12:23:34.692346 [DATLAT]
3152 12:23:34.692716 Freq=1200, CH1 RK0
3153 12:23:34.693056
3154 12:23:34.694651 DATLAT Default: 0xd
3155 12:23:34.695106 0, 0xFFFF, sum = 0
3156 12:23:34.697959 1, 0xFFFF, sum = 0
3157 12:23:34.701913 2, 0xFFFF, sum = 0
3158 12:23:34.702469 3, 0xFFFF, sum = 0
3159 12:23:34.704882 4, 0xFFFF, sum = 0
3160 12:23:34.705345 5, 0xFFFF, sum = 0
3161 12:23:34.708288 6, 0xFFFF, sum = 0
3162 12:23:34.708850 7, 0xFFFF, sum = 0
3163 12:23:34.711800 8, 0xFFFF, sum = 0
3164 12:23:34.712402 9, 0xFFFF, sum = 0
3165 12:23:34.714910 10, 0xFFFF, sum = 0
3166 12:23:34.715465 11, 0x0, sum = 1
3167 12:23:34.718112 12, 0x0, sum = 2
3168 12:23:34.718579 13, 0x0, sum = 3
3169 12:23:34.721434 14, 0x0, sum = 4
3170 12:23:34.721995 best_step = 12
3171 12:23:34.722354
3172 12:23:34.722690 ==
3173 12:23:34.724636 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 12:23:34.728218 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3175 12:23:34.728777 ==
3176 12:23:34.731509 RX Vref Scan: 1
3177 12:23:34.731964
3178 12:23:34.735549 Set Vref Range= 32 -> 127
3179 12:23:34.736323
3180 12:23:34.736708 RX Vref 32 -> 127, step: 1
3181 12:23:34.737047
3182 12:23:34.738021 RX Delay -29 -> 252, step: 4
3183 12:23:34.738478
3184 12:23:34.741596 Set Vref, RX VrefLevel [Byte0]: 32
3185 12:23:34.744881 [Byte1]: 32
3186 12:23:34.748688
3187 12:23:34.749235 Set Vref, RX VrefLevel [Byte0]: 33
3188 12:23:34.751579 [Byte1]: 33
3189 12:23:34.756365
3190 12:23:34.756819 Set Vref, RX VrefLevel [Byte0]: 34
3191 12:23:34.760078 [Byte1]: 34
3192 12:23:34.764736
3193 12:23:34.765282 Set Vref, RX VrefLevel [Byte0]: 35
3194 12:23:34.767811 [Byte1]: 35
3195 12:23:34.772567
3196 12:23:34.773115 Set Vref, RX VrefLevel [Byte0]: 36
3197 12:23:34.775760 [Byte1]: 36
3198 12:23:34.780584
3199 12:23:34.781127 Set Vref, RX VrefLevel [Byte0]: 37
3200 12:23:34.783816 [Byte1]: 37
3201 12:23:34.788301
3202 12:23:34.788841 Set Vref, RX VrefLevel [Byte0]: 38
3203 12:23:34.791495 [Byte1]: 38
3204 12:23:34.796343
3205 12:23:34.796885 Set Vref, RX VrefLevel [Byte0]: 39
3206 12:23:34.799480 [Byte1]: 39
3207 12:23:34.804156
3208 12:23:34.804780 Set Vref, RX VrefLevel [Byte0]: 40
3209 12:23:34.807661 [Byte1]: 40
3210 12:23:34.812010
3211 12:23:34.812605 Set Vref, RX VrefLevel [Byte0]: 41
3212 12:23:34.815606 [Byte1]: 41
3213 12:23:34.820216
3214 12:23:34.820769 Set Vref, RX VrefLevel [Byte0]: 42
3215 12:23:34.823843 [Byte1]: 42
3216 12:23:34.828326
3217 12:23:34.828878 Set Vref, RX VrefLevel [Byte0]: 43
3218 12:23:34.831428 [Byte1]: 43
3219 12:23:34.836031
3220 12:23:34.836526 Set Vref, RX VrefLevel [Byte0]: 44
3221 12:23:34.839208 [Byte1]: 44
3222 12:23:34.844033
3223 12:23:34.844634 Set Vref, RX VrefLevel [Byte0]: 45
3224 12:23:34.847183 [Byte1]: 45
3225 12:23:34.851885
3226 12:23:34.852586 Set Vref, RX VrefLevel [Byte0]: 46
3227 12:23:34.855146 [Byte1]: 46
3228 12:23:34.860102
3229 12:23:34.860704 Set Vref, RX VrefLevel [Byte0]: 47
3230 12:23:34.863265 [Byte1]: 47
3231 12:23:34.867868
3232 12:23:34.868467 Set Vref, RX VrefLevel [Byte0]: 48
3233 12:23:34.871075 [Byte1]: 48
3234 12:23:34.875922
3235 12:23:34.876530 Set Vref, RX VrefLevel [Byte0]: 49
3236 12:23:34.879000 [Byte1]: 49
3237 12:23:34.883847
3238 12:23:34.884433 Set Vref, RX VrefLevel [Byte0]: 50
3239 12:23:34.886933 [Byte1]: 50
3240 12:23:34.891880
3241 12:23:34.892486 Set Vref, RX VrefLevel [Byte0]: 51
3242 12:23:34.895045 [Byte1]: 51
3243 12:23:34.899799
3244 12:23:34.900471 Set Vref, RX VrefLevel [Byte0]: 52
3245 12:23:34.902780 [Byte1]: 52
3246 12:23:34.908011
3247 12:23:34.908641 Set Vref, RX VrefLevel [Byte0]: 53
3248 12:23:34.910662 [Byte1]: 53
3249 12:23:34.915899
3250 12:23:34.916501 Set Vref, RX VrefLevel [Byte0]: 54
3251 12:23:34.918925 [Byte1]: 54
3252 12:23:34.923615
3253 12:23:34.924165 Set Vref, RX VrefLevel [Byte0]: 55
3254 12:23:34.926928 [Byte1]: 55
3255 12:23:34.931234
3256 12:23:34.934896 Set Vref, RX VrefLevel [Byte0]: 56
3257 12:23:34.935443 [Byte1]: 56
3258 12:23:34.939758
3259 12:23:34.940340 Set Vref, RX VrefLevel [Byte0]: 57
3260 12:23:34.942908 [Byte1]: 57
3261 12:23:34.947428
3262 12:23:34.950826 Set Vref, RX VrefLevel [Byte0]: 58
3263 12:23:34.951378 [Byte1]: 58
3264 12:23:34.955582
3265 12:23:34.956129 Set Vref, RX VrefLevel [Byte0]: 59
3266 12:23:34.958752 [Byte1]: 59
3267 12:23:34.963162
3268 12:23:34.963772 Set Vref, RX VrefLevel [Byte0]: 60
3269 12:23:34.966400 [Byte1]: 60
3270 12:23:34.971397
3271 12:23:34.971945 Set Vref, RX VrefLevel [Byte0]: 61
3272 12:23:34.974386 [Byte1]: 61
3273 12:23:34.979208
3274 12:23:34.979753 Set Vref, RX VrefLevel [Byte0]: 62
3275 12:23:34.982595 [Byte1]: 62
3276 12:23:34.987072
3277 12:23:34.987526 Set Vref, RX VrefLevel [Byte0]: 63
3278 12:23:34.990171 [Byte1]: 63
3279 12:23:34.995615
3280 12:23:34.996163 Set Vref, RX VrefLevel [Byte0]: 64
3281 12:23:34.998679 [Byte1]: 64
3282 12:23:35.003268
3283 12:23:35.003816 Set Vref, RX VrefLevel [Byte0]: 65
3284 12:23:35.006535 [Byte1]: 65
3285 12:23:35.010894
3286 12:23:35.011351 Set Vref, RX VrefLevel [Byte0]: 66
3287 12:23:35.014570 [Byte1]: 66
3288 12:23:35.019410
3289 12:23:35.019963 Set Vref, RX VrefLevel [Byte0]: 67
3290 12:23:35.022714 [Byte1]: 67
3291 12:23:35.027157
3292 12:23:35.027705 Final RX Vref Byte 0 = 52 to rank0
3293 12:23:35.030514 Final RX Vref Byte 1 = 49 to rank0
3294 12:23:35.033380 Final RX Vref Byte 0 = 52 to rank1
3295 12:23:35.037154 Final RX Vref Byte 1 = 49 to rank1==
3296 12:23:35.040231 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 12:23:35.046981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3298 12:23:35.047538 ==
3299 12:23:35.047908 DQS Delay:
3300 12:23:35.048289 DQS0 = 0, DQS1 = 0
3301 12:23:35.050544 DQM Delay:
3302 12:23:35.051090 DQM0 = 115, DQM1 = 105
3303 12:23:35.053837 DQ Delay:
3304 12:23:35.057079 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3305 12:23:35.060235 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3306 12:23:35.063316 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3307 12:23:35.066749 DQ12 =114, DQ13 =116, DQ14 =114, DQ15 =116
3308 12:23:35.067261
3309 12:23:35.067632
3310 12:23:35.073497 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
3311 12:23:35.077104 CH1 RK0: MR19=404, MR18=1414
3312 12:23:35.083476 CH1_RK0: MR19=0x404, MR18=0x1414, DQSOSC=402, MR23=63, INC=40, DEC=27
3313 12:23:35.084013
3314 12:23:35.086938 ----->DramcWriteLeveling(PI) begin...
3315 12:23:35.087440 ==
3316 12:23:35.090197 Dram Type= 6, Freq= 0, CH_1, rank 1
3317 12:23:35.093392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3318 12:23:35.093853 ==
3319 12:23:35.096892 Write leveling (Byte 0): 23 => 23
3320 12:23:35.100048 Write leveling (Byte 1): 21 => 21
3321 12:23:35.103554 DramcWriteLeveling(PI) end<-----
3322 12:23:35.104005
3323 12:23:35.104421 ==
3324 12:23:35.106680 Dram Type= 6, Freq= 0, CH_1, rank 1
3325 12:23:35.114172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3326 12:23:35.114731 ==
3327 12:23:35.115095 [Gating] SW mode calibration
3328 12:23:35.123639 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3329 12:23:35.127231 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3330 12:23:35.130533 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3331 12:23:35.136755 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3332 12:23:35.140306 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3333 12:23:35.143574 0 11 12 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
3334 12:23:35.150770 0 11 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3335 12:23:35.153765 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3336 12:23:35.157186 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3337 12:23:35.163879 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3338 12:23:35.167236 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3339 12:23:35.170550 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3340 12:23:35.176850 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3341 12:23:35.180487 0 12 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
3342 12:23:35.183868 0 12 16 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
3343 12:23:35.190181 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3344 12:23:35.194160 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3345 12:23:35.196936 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3346 12:23:35.203613 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3347 12:23:35.206719 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3348 12:23:35.210362 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3349 12:23:35.213490 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3350 12:23:35.220142 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3351 12:23:35.223891 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3352 12:23:35.226973 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3353 12:23:35.233816 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3354 12:23:35.236777 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3355 12:23:35.240778 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3356 12:23:35.247045 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3357 12:23:35.250962 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3358 12:23:35.254132 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3359 12:23:35.260115 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3360 12:23:35.263490 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3361 12:23:35.266913 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3362 12:23:35.273557 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3363 12:23:35.277036 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3364 12:23:35.279927 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3365 12:23:35.287128 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3366 12:23:35.290219 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3367 12:23:35.293230 Total UI for P1: 0, mck2ui 16
3368 12:23:35.296747 best dqsien dly found for B0: ( 0, 15, 12)
3369 12:23:35.299897 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3370 12:23:35.303585 Total UI for P1: 0, mck2ui 16
3371 12:23:35.306484 best dqsien dly found for B1: ( 0, 15, 16)
3372 12:23:35.309954 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3373 12:23:35.313430 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3374 12:23:35.313878
3375 12:23:35.316545 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3376 12:23:35.323508 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3377 12:23:35.324063 [Gating] SW calibration Done
3378 12:23:35.327314 ==
3379 12:23:35.327853 Dram Type= 6, Freq= 0, CH_1, rank 1
3380 12:23:35.333671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3381 12:23:35.334218 ==
3382 12:23:35.334575 RX Vref Scan: 0
3383 12:23:35.334904
3384 12:23:35.336755 RX Vref 0 -> 0, step: 1
3385 12:23:35.337216
3386 12:23:35.340230 RX Delay -40 -> 252, step: 8
3387 12:23:35.343248 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3388 12:23:35.346401 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3389 12:23:35.350151 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3390 12:23:35.356812 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3391 12:23:35.360257 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3392 12:23:35.363420 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3393 12:23:35.367061 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3394 12:23:35.370073 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3395 12:23:35.373647 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3396 12:23:35.380154 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3397 12:23:35.383603 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3398 12:23:35.386644 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3399 12:23:35.389976 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3400 12:23:35.393074 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3401 12:23:35.400322 iDelay=200, Bit 14, Center 111 (32 ~ 191) 160
3402 12:23:35.403885 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3403 12:23:35.404520 ==
3404 12:23:35.406816 Dram Type= 6, Freq= 0, CH_1, rank 1
3405 12:23:35.410073 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3406 12:23:35.410623 ==
3407 12:23:35.413438 DQS Delay:
3408 12:23:35.413886 DQS0 = 0, DQS1 = 0
3409 12:23:35.414236 DQM Delay:
3410 12:23:35.416322 DQM0 = 116, DQM1 = 107
3411 12:23:35.416773 DQ Delay:
3412 12:23:35.419769 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =119
3413 12:23:35.423266 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =115
3414 12:23:35.426551 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
3415 12:23:35.433069 DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =115
3416 12:23:35.433601
3417 12:23:35.434060
3418 12:23:35.434588 ==
3419 12:23:35.436311 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 12:23:35.440050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3421 12:23:35.440628 ==
3422 12:23:35.440990
3423 12:23:35.441319
3424 12:23:35.443085 TX Vref Scan disable
3425 12:23:35.443534 == TX Byte 0 ==
3426 12:23:35.449958 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3427 12:23:35.453327 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3428 12:23:35.453785 == TX Byte 1 ==
3429 12:23:35.459888 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3430 12:23:35.462865 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3431 12:23:35.463370 ==
3432 12:23:35.466218 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 12:23:35.470210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3434 12:23:35.470666 ==
3435 12:23:35.482881 TX Vref=22, minBit 3, minWin=25, winSum=419
3436 12:23:35.485768 TX Vref=24, minBit 0, minWin=26, winSum=424
3437 12:23:35.489118 TX Vref=26, minBit 3, minWin=26, winSum=426
3438 12:23:35.492638 TX Vref=28, minBit 3, minWin=26, winSum=432
3439 12:23:35.495732 TX Vref=30, minBit 0, minWin=26, winSum=433
3440 12:23:35.499422 TX Vref=32, minBit 0, minWin=26, winSum=431
3441 12:23:35.506172 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 30
3442 12:23:35.506716
3443 12:23:35.509366 Final TX Range 1 Vref 30
3444 12:23:35.509914
3445 12:23:35.510270 ==
3446 12:23:35.512509 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 12:23:35.515910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3448 12:23:35.516405 ==
3449 12:23:35.516766
3450 12:23:35.519029
3451 12:23:35.519478 TX Vref Scan disable
3452 12:23:35.522842 == TX Byte 0 ==
3453 12:23:35.526052 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3454 12:23:35.529147 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3455 12:23:35.532552 == TX Byte 1 ==
3456 12:23:35.535861 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3457 12:23:35.539334 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3458 12:23:35.539883
3459 12:23:35.542470 [DATLAT]
3460 12:23:35.543024 Freq=1200, CH1 RK1
3461 12:23:35.543390
3462 12:23:35.545512 DATLAT Default: 0xc
3463 12:23:35.546227 0, 0xFFFF, sum = 0
3464 12:23:35.548715 1, 0xFFFF, sum = 0
3465 12:23:35.549172 2, 0xFFFF, sum = 0
3466 12:23:35.552741 3, 0xFFFF, sum = 0
3467 12:23:35.553291 4, 0xFFFF, sum = 0
3468 12:23:35.555651 5, 0xFFFF, sum = 0
3469 12:23:35.559326 6, 0xFFFF, sum = 0
3470 12:23:35.559874 7, 0xFFFF, sum = 0
3471 12:23:35.562415 8, 0xFFFF, sum = 0
3472 12:23:35.562872 9, 0xFFFF, sum = 0
3473 12:23:35.565539 10, 0xFFFF, sum = 0
3474 12:23:35.565995 11, 0x0, sum = 1
3475 12:23:35.568847 12, 0x0, sum = 2
3476 12:23:35.569322 13, 0x0, sum = 3
3477 12:23:35.569683 14, 0x0, sum = 4
3478 12:23:35.572205 best_step = 12
3479 12:23:35.572824
3480 12:23:35.573200 ==
3481 12:23:35.575775 Dram Type= 6, Freq= 0, CH_1, rank 1
3482 12:23:35.579242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3483 12:23:35.579787 ==
3484 12:23:35.582727 RX Vref Scan: 0
3485 12:23:35.583270
3486 12:23:35.583632 RX Vref 0 -> 0, step: 1
3487 12:23:35.585750
3488 12:23:35.586288 RX Delay -29 -> 252, step: 4
3489 12:23:35.593262 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3490 12:23:35.596379 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3491 12:23:35.599697 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3492 12:23:35.603418 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3493 12:23:35.606785 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3494 12:23:35.613050 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3495 12:23:35.616152 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3496 12:23:35.619839 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3497 12:23:35.623290 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3498 12:23:35.626605 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3499 12:23:35.630063 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3500 12:23:35.636799 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3501 12:23:35.639656 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3502 12:23:35.643149 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3503 12:23:35.646431 iDelay=199, Bit 14, Center 114 (43 ~ 186) 144
3504 12:23:35.652958 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3505 12:23:35.653529 ==
3506 12:23:35.656363 Dram Type= 6, Freq= 0, CH_1, rank 1
3507 12:23:35.659494 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3508 12:23:35.660081 ==
3509 12:23:35.660625 DQS Delay:
3510 12:23:35.663429 DQS0 = 0, DQS1 = 0
3511 12:23:35.663998 DQM Delay:
3512 12:23:35.666145 DQM0 = 114, DQM1 = 103
3513 12:23:35.666595 DQ Delay:
3514 12:23:35.669590 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3515 12:23:35.673029 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3516 12:23:35.676347 DQ8 =88, DQ9 =90, DQ10 =106, DQ11 =98
3517 12:23:35.679841 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =110
3518 12:23:35.680428
3519 12:23:35.680789
3520 12:23:35.689836 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3521 12:23:35.690387 CH1 RK1: MR19=404, MR18=D0D
3522 12:23:35.696241 CH1_RK1: MR19=0x404, MR18=0xD0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3523 12:23:35.700038 [RxdqsGatingPostProcess] freq 1200
3524 12:23:35.706609 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3525 12:23:35.709761 Pre-setting of DQS Precalculation
3526 12:23:35.713042 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3527 12:23:35.719767 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3528 12:23:35.729782 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3529 12:23:35.730332
3530 12:23:35.730690
3531 12:23:35.733294 [Calibration Summary] 2400 Mbps
3532 12:23:35.733841 CH 0, Rank 0
3533 12:23:35.736280 SW Impedance : PASS
3534 12:23:35.736730 DUTY Scan : NO K
3535 12:23:35.739836 ZQ Calibration : PASS
3536 12:23:35.743316 Jitter Meter : NO K
3537 12:23:35.743914 CBT Training : PASS
3538 12:23:35.746287 Write leveling : PASS
3539 12:23:35.746831 RX DQS gating : PASS
3540 12:23:35.749482 RX DQ/DQS(RDDQC) : PASS
3541 12:23:35.753594 TX DQ/DQS : PASS
3542 12:23:35.754146 RX DATLAT : PASS
3543 12:23:35.756220 RX DQ/DQS(Engine): PASS
3544 12:23:35.759556 TX OE : NO K
3545 12:23:35.760009 All Pass.
3546 12:23:35.760427
3547 12:23:35.760765 CH 0, Rank 1
3548 12:23:35.762822 SW Impedance : PASS
3549 12:23:35.766253 DUTY Scan : NO K
3550 12:23:35.766706 ZQ Calibration : PASS
3551 12:23:35.769992 Jitter Meter : NO K
3552 12:23:35.773272 CBT Training : PASS
3553 12:23:35.773814 Write leveling : PASS
3554 12:23:35.776420 RX DQS gating : PASS
3555 12:23:35.776870 RX DQ/DQS(RDDQC) : PASS
3556 12:23:35.779827 TX DQ/DQS : PASS
3557 12:23:35.783288 RX DATLAT : PASS
3558 12:23:35.783837 RX DQ/DQS(Engine): PASS
3559 12:23:35.786746 TX OE : NO K
3560 12:23:35.787288 All Pass.
3561 12:23:35.787646
3562 12:23:35.789948 CH 1, Rank 0
3563 12:23:35.790486 SW Impedance : PASS
3564 12:23:35.792899 DUTY Scan : NO K
3565 12:23:35.796501 ZQ Calibration : PASS
3566 12:23:35.796948 Jitter Meter : NO K
3567 12:23:35.799903 CBT Training : PASS
3568 12:23:35.803657 Write leveling : PASS
3569 12:23:35.804246 RX DQS gating : PASS
3570 12:23:35.806745 RX DQ/DQS(RDDQC) : PASS
3571 12:23:35.809815 TX DQ/DQS : PASS
3572 12:23:35.810360 RX DATLAT : PASS
3573 12:23:35.812876 RX DQ/DQS(Engine): PASS
3574 12:23:35.816564 TX OE : NO K
3575 12:23:35.817112 All Pass.
3576 12:23:35.817470
3577 12:23:35.817796 CH 1, Rank 1
3578 12:23:35.819564 SW Impedance : PASS
3579 12:23:35.823165 DUTY Scan : NO K
3580 12:23:35.823716 ZQ Calibration : PASS
3581 12:23:35.826320 Jitter Meter : NO K
3582 12:23:35.829684 CBT Training : PASS
3583 12:23:35.830231 Write leveling : PASS
3584 12:23:35.833313 RX DQS gating : PASS
3585 12:23:35.833858 RX DQ/DQS(RDDQC) : PASS
3586 12:23:35.836382 TX DQ/DQS : PASS
3587 12:23:35.839309 RX DATLAT : PASS
3588 12:23:35.839762 RX DQ/DQS(Engine): PASS
3589 12:23:35.843233 TX OE : NO K
3590 12:23:35.843797 All Pass.
3591 12:23:35.844310
3592 12:23:35.846552 DramC Write-DBI off
3593 12:23:35.849542 PER_BANK_REFRESH: Hybrid Mode
3594 12:23:35.850047 TX_TRACKING: ON
3595 12:23:35.859772 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3596 12:23:35.862867 [FAST_K] Save calibration result to emmc
3597 12:23:35.866234 dramc_set_vcore_voltage set vcore to 650000
3598 12:23:35.869663 Read voltage for 600, 5
3599 12:23:35.870115 Vio18 = 0
3600 12:23:35.870475 Vcore = 650000
3601 12:23:35.872716 Vdram = 0
3602 12:23:35.873284 Vddq = 0
3603 12:23:35.873704 Vmddr = 0
3604 12:23:35.879512 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3605 12:23:35.882787 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3606 12:23:35.886300 MEM_TYPE=3, freq_sel=19
3607 12:23:35.889746 sv_algorithm_assistance_LP4_1600
3608 12:23:35.892817 ============ PULL DRAM RESETB DOWN ============
3609 12:23:35.895999 ========== PULL DRAM RESETB DOWN end =========
3610 12:23:35.902690 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3611 12:23:35.906334 ===================================
3612 12:23:35.909326 LPDDR4 DRAM CONFIGURATION
3613 12:23:35.912722 ===================================
3614 12:23:35.913182 EX_ROW_EN[0] = 0x0
3615 12:23:35.916930 EX_ROW_EN[1] = 0x0
3616 12:23:35.917515 LP4Y_EN = 0x0
3617 12:23:35.919850 WORK_FSP = 0x0
3618 12:23:35.920440 WL = 0x2
3619 12:23:35.922901 RL = 0x2
3620 12:23:35.923355 BL = 0x2
3621 12:23:35.926673 RPST = 0x0
3622 12:23:35.927232 RD_PRE = 0x0
3623 12:23:35.929535 WR_PRE = 0x1
3624 12:23:35.930092 WR_PST = 0x0
3625 12:23:35.932846 DBI_WR = 0x0
3626 12:23:35.933400 DBI_RD = 0x0
3627 12:23:35.936006 OTF = 0x1
3628 12:23:35.939804 ===================================
3629 12:23:35.942972 ===================================
3630 12:23:35.943528 ANA top config
3631 12:23:35.946208 ===================================
3632 12:23:35.949754 DLL_ASYNC_EN = 0
3633 12:23:35.953136 ALL_SLAVE_EN = 1
3634 12:23:35.956115 NEW_RANK_MODE = 1
3635 12:23:35.956617 DLL_IDLE_MODE = 1
3636 12:23:35.959407 LP45_APHY_COMB_EN = 1
3637 12:23:35.962922 TX_ODT_DIS = 1
3638 12:23:35.965712 NEW_8X_MODE = 1
3639 12:23:35.969230 ===================================
3640 12:23:35.972660 ===================================
3641 12:23:35.975862 data_rate = 1200
3642 12:23:35.976356 CKR = 1
3643 12:23:35.979518 DQ_P2S_RATIO = 8
3644 12:23:35.982705 ===================================
3645 12:23:35.985785 CA_P2S_RATIO = 8
3646 12:23:35.989149 DQ_CA_OPEN = 0
3647 12:23:35.992793 DQ_SEMI_OPEN = 0
3648 12:23:35.995540 CA_SEMI_OPEN = 0
3649 12:23:35.995996 CA_FULL_RATE = 0
3650 12:23:35.999073 DQ_CKDIV4_EN = 1
3651 12:23:36.002257 CA_CKDIV4_EN = 1
3652 12:23:36.005839 CA_PREDIV_EN = 0
3653 12:23:36.009153 PH8_DLY = 0
3654 12:23:36.012087 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3655 12:23:36.012623 DQ_AAMCK_DIV = 4
3656 12:23:36.015966 CA_AAMCK_DIV = 4
3657 12:23:36.018956 CA_ADMCK_DIV = 4
3658 12:23:36.022402 DQ_TRACK_CA_EN = 0
3659 12:23:36.025789 CA_PICK = 600
3660 12:23:36.028831 CA_MCKIO = 600
3661 12:23:36.031994 MCKIO_SEMI = 0
3662 12:23:36.032545 PLL_FREQ = 2288
3663 12:23:36.035656 DQ_UI_PI_RATIO = 32
3664 12:23:36.038954 CA_UI_PI_RATIO = 0
3665 12:23:36.042338 ===================================
3666 12:23:36.045502 ===================================
3667 12:23:36.048738 memory_type:LPDDR4
3668 12:23:36.052267 GP_NUM : 10
3669 12:23:36.052817 SRAM_EN : 1
3670 12:23:36.055478 MD32_EN : 0
3671 12:23:36.058465 ===================================
3672 12:23:36.058925 [ANA_INIT] >>>>>>>>>>>>>>
3673 12:23:36.061853 <<<<<< [CONFIGURE PHASE]: ANA_TX
3674 12:23:36.065331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3675 12:23:36.068789 ===================================
3676 12:23:36.072108 data_rate = 1200,PCW = 0X5800
3677 12:23:36.075121 ===================================
3678 12:23:36.078704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3679 12:23:36.084937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3680 12:23:36.091914 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3681 12:23:36.094892 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3682 12:23:36.098603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3683 12:23:36.101512 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3684 12:23:36.104820 [ANA_INIT] flow start
3685 12:23:36.105275 [ANA_INIT] PLL >>>>>>>>
3686 12:23:36.108234 [ANA_INIT] PLL <<<<<<<<
3687 12:23:36.111613 [ANA_INIT] MIDPI >>>>>>>>
3688 12:23:36.112158 [ANA_INIT] MIDPI <<<<<<<<
3689 12:23:36.115348 [ANA_INIT] DLL >>>>>>>>
3690 12:23:36.118565 [ANA_INIT] flow end
3691 12:23:36.121439 ============ LP4 DIFF to SE enter ============
3692 12:23:36.124855 ============ LP4 DIFF to SE exit ============
3693 12:23:36.128384 [ANA_INIT] <<<<<<<<<<<<<
3694 12:23:36.131423 [Flow] Enable top DCM control >>>>>
3695 12:23:36.135028 [Flow] Enable top DCM control <<<<<
3696 12:23:36.138160 Enable DLL master slave shuffle
3697 12:23:36.141500 ==============================================================
3698 12:23:36.144851 Gating Mode config
3699 12:23:36.151318 ==============================================================
3700 12:23:36.151877 Config description:
3701 12:23:36.161096 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3702 12:23:36.167969 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3703 12:23:36.174265 SELPH_MODE 0: By rank 1: By Phase
3704 12:23:36.177876 ==============================================================
3705 12:23:36.181000 GAT_TRACK_EN = 1
3706 12:23:36.184881 RX_GATING_MODE = 2
3707 12:23:36.187697 RX_GATING_TRACK_MODE = 2
3708 12:23:36.191161 SELPH_MODE = 1
3709 12:23:36.194360 PICG_EARLY_EN = 1
3710 12:23:36.197746 VALID_LAT_VALUE = 1
3711 12:23:36.200936 ==============================================================
3712 12:23:36.204154 Enter into Gating configuration >>>>
3713 12:23:36.207669 Exit from Gating configuration <<<<
3714 12:23:36.210681 Enter into DVFS_PRE_config >>>>>
3715 12:23:36.224060 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3716 12:23:36.227211 Exit from DVFS_PRE_config <<<<<
3717 12:23:36.230896 Enter into PICG configuration >>>>
3718 12:23:36.231447 Exit from PICG configuration <<<<
3719 12:23:36.234063 [RX_INPUT] configuration >>>>>
3720 12:23:36.237320 [RX_INPUT] configuration <<<<<
3721 12:23:36.243945 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3722 12:23:36.247409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3723 12:23:36.254317 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3724 12:23:36.260647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3725 12:23:36.267416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3726 12:23:36.273981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3727 12:23:36.276846 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3728 12:23:36.280747 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3729 12:23:36.287139 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3730 12:23:36.290522 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3731 12:23:36.293507 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3732 12:23:36.296770 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3733 12:23:36.300230 ===================================
3734 12:23:36.303689 LPDDR4 DRAM CONFIGURATION
3735 12:23:36.307023 ===================================
3736 12:23:36.310704 EX_ROW_EN[0] = 0x0
3737 12:23:36.311253 EX_ROW_EN[1] = 0x0
3738 12:23:36.313510 LP4Y_EN = 0x0
3739 12:23:36.313966 WORK_FSP = 0x0
3740 12:23:36.316932 WL = 0x2
3741 12:23:36.317386 RL = 0x2
3742 12:23:36.320090 BL = 0x2
3743 12:23:36.320594 RPST = 0x0
3744 12:23:36.323535 RD_PRE = 0x0
3745 12:23:36.323988 WR_PRE = 0x1
3746 12:23:36.326930 WR_PST = 0x0
3747 12:23:36.327478 DBI_WR = 0x0
3748 12:23:36.329887 DBI_RD = 0x0
3749 12:23:36.330343 OTF = 0x1
3750 12:23:36.333709 ===================================
3751 12:23:36.340514 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3752 12:23:36.343430 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3753 12:23:36.346635 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3754 12:23:36.349993 ===================================
3755 12:23:36.353329 LPDDR4 DRAM CONFIGURATION
3756 12:23:36.356947 ===================================
3757 12:23:36.360142 EX_ROW_EN[0] = 0x10
3758 12:23:36.360724 EX_ROW_EN[1] = 0x0
3759 12:23:36.363244 LP4Y_EN = 0x0
3760 12:23:36.363698 WORK_FSP = 0x0
3761 12:23:36.366451 WL = 0x2
3762 12:23:36.366909 RL = 0x2
3763 12:23:36.370162 BL = 0x2
3764 12:23:36.370775 RPST = 0x0
3765 12:23:36.373245 RD_PRE = 0x0
3766 12:23:36.373699 WR_PRE = 0x1
3767 12:23:36.376597 WR_PST = 0x0
3768 12:23:36.377144 DBI_WR = 0x0
3769 12:23:36.379826 DBI_RD = 0x0
3770 12:23:36.380422 OTF = 0x1
3771 12:23:36.383008 ===================================
3772 12:23:36.389843 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3773 12:23:36.394812 nWR fixed to 30
3774 12:23:36.397703 [ModeRegInit_LP4] CH0 RK0
3775 12:23:36.398163 [ModeRegInit_LP4] CH0 RK1
3776 12:23:36.400884 [ModeRegInit_LP4] CH1 RK0
3777 12:23:36.404212 [ModeRegInit_LP4] CH1 RK1
3778 12:23:36.404678 match AC timing 16
3779 12:23:36.410862 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3780 12:23:36.414478 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3781 12:23:36.417813 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3782 12:23:36.424093 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3783 12:23:36.427831 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3784 12:23:36.428424 ==
3785 12:23:36.430951 Dram Type= 6, Freq= 0, CH_0, rank 0
3786 12:23:36.434662 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3787 12:23:36.435217 ==
3788 12:23:36.440838 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3789 12:23:36.447383 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3790 12:23:36.450633 [CA 0] Center 36 (6~66) winsize 61
3791 12:23:36.453895 [CA 1] Center 35 (5~66) winsize 62
3792 12:23:36.457350 [CA 2] Center 34 (4~65) winsize 62
3793 12:23:36.460945 [CA 3] Center 34 (4~65) winsize 62
3794 12:23:36.464117 [CA 4] Center 33 (3~64) winsize 62
3795 12:23:36.467318 [CA 5] Center 33 (3~64) winsize 62
3796 12:23:36.467774
3797 12:23:36.470768 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3798 12:23:36.471320
3799 12:23:36.474048 [CATrainingPosCal] consider 1 rank data
3800 12:23:36.477237 u2DelayCellTimex100 = 270/100 ps
3801 12:23:36.480656 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3802 12:23:36.483692 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3803 12:23:36.487417 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3804 12:23:36.490779 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3805 12:23:36.497364 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3806 12:23:36.500397 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3807 12:23:36.500861
3808 12:23:36.503721 CA PerBit enable=1, Macro0, CA PI delay=33
3809 12:23:36.504207
3810 12:23:36.507087 [CBTSetCACLKResult] CA Dly = 33
3811 12:23:36.507637 CS Dly: 5 (0~36)
3812 12:23:36.508002 ==
3813 12:23:36.510463 Dram Type= 6, Freq= 0, CH_0, rank 1
3814 12:23:36.516772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3815 12:23:36.517681 ==
3816 12:23:36.520054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3817 12:23:36.526826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3818 12:23:36.530174 [CA 0] Center 36 (6~66) winsize 61
3819 12:23:36.533314 [CA 1] Center 35 (5~66) winsize 62
3820 12:23:36.536653 [CA 2] Center 34 (4~65) winsize 62
3821 12:23:36.540090 [CA 3] Center 34 (4~65) winsize 62
3822 12:23:36.543301 [CA 4] Center 33 (3~64) winsize 62
3823 12:23:36.546871 [CA 5] Center 33 (3~64) winsize 62
3824 12:23:36.547421
3825 12:23:36.550294 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3826 12:23:36.550841
3827 12:23:36.553275 [CATrainingPosCal] consider 2 rank data
3828 12:23:36.556295 u2DelayCellTimex100 = 270/100 ps
3829 12:23:36.559969 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3830 12:23:36.563254 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3831 12:23:36.569885 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3832 12:23:36.573192 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3833 12:23:36.576563 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3834 12:23:36.579653 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3835 12:23:36.580110
3836 12:23:36.583287 CA PerBit enable=1, Macro0, CA PI delay=33
3837 12:23:36.583834
3838 12:23:36.586469 [CBTSetCACLKResult] CA Dly = 33
3839 12:23:36.587016 CS Dly: 5 (0~36)
3840 12:23:36.587380
3841 12:23:36.592749 ----->DramcWriteLeveling(PI) begin...
3842 12:23:36.593291 ==
3843 12:23:36.596145 Dram Type= 6, Freq= 0, CH_0, rank 0
3844 12:23:36.599581 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3845 12:23:36.600170 ==
3846 12:23:36.602642 Write leveling (Byte 0): 31 => 31
3847 12:23:36.606450 Write leveling (Byte 1): 31 => 31
3848 12:23:36.610146 DramcWriteLeveling(PI) end<-----
3849 12:23:36.610698
3850 12:23:36.611062 ==
3851 12:23:36.612753 Dram Type= 6, Freq= 0, CH_0, rank 0
3852 12:23:36.616233 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3853 12:23:36.616798 ==
3854 12:23:36.619299 [Gating] SW mode calibration
3855 12:23:36.626067 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3856 12:23:36.632285 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3857 12:23:36.636103 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3858 12:23:36.639308 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3859 12:23:36.646249 0 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
3860 12:23:36.649124 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
3861 12:23:36.652322 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3862 12:23:36.659081 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3863 12:23:36.662399 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3864 12:23:36.665459 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3865 12:23:36.671867 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3866 12:23:36.675307 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3867 12:23:36.678941 0 6 8 | B1->B0 | 2c2c 3636 | 0 0 | (0 0) (0 0)
3868 12:23:36.685291 0 6 12 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
3869 12:23:36.688686 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3870 12:23:36.692428 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3871 12:23:36.698537 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3872 12:23:36.702368 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3873 12:23:36.705866 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3874 12:23:36.712131 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3875 12:23:36.715409 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3876 12:23:36.718721 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3877 12:23:36.722050 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3878 12:23:36.728947 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3879 12:23:36.732028 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3880 12:23:36.738302 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3881 12:23:36.741776 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3882 12:23:36.745179 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3883 12:23:36.748248 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3884 12:23:36.755480 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3885 12:23:36.758448 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3886 12:23:36.761819 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3887 12:23:36.767830 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3888 12:23:36.771444 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3889 12:23:36.774726 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3890 12:23:36.781311 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3891 12:23:36.784736 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3892 12:23:36.787920 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3893 12:23:36.790836 Total UI for P1: 0, mck2ui 16
3894 12:23:36.794657 best dqsien dly found for B0: ( 0, 9, 8)
3895 12:23:36.797870 Total UI for P1: 0, mck2ui 16
3896 12:23:36.800925 best dqsien dly found for B1: ( 0, 9, 8)
3897 12:23:36.804159 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3898 12:23:36.807546 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3899 12:23:36.810799
3900 12:23:36.814822 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3901 12:23:36.817351 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3902 12:23:36.821120 [Gating] SW calibration Done
3903 12:23:36.821668 ==
3904 12:23:36.824114 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 12:23:36.827552 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3906 12:23:36.828101 ==
3907 12:23:36.828581 RX Vref Scan: 0
3908 12:23:36.830816
3909 12:23:36.831269 RX Vref 0 -> 0, step: 1
3910 12:23:36.831632
3911 12:23:36.833802 RX Delay -230 -> 252, step: 16
3912 12:23:36.837336 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3913 12:23:36.844238 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3914 12:23:36.847090 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3915 12:23:36.850816 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3916 12:23:36.854110 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3917 12:23:36.857281 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3918 12:23:36.863947 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3919 12:23:36.867138 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3920 12:23:36.870690 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3921 12:23:36.873632 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3922 12:23:36.880591 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3923 12:23:36.883412 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3924 12:23:36.887249 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3925 12:23:36.890354 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3926 12:23:36.897342 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3927 12:23:36.900291 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3928 12:23:36.900813 ==
3929 12:23:36.903555 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 12:23:36.907055 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3931 12:23:36.907587 ==
3932 12:23:36.910221 DQS Delay:
3933 12:23:36.910676 DQS0 = 0, DQS1 = 0
3934 12:23:36.911037 DQM Delay:
3935 12:23:36.913585 DQM0 = 38, DQM1 = 33
3936 12:23:36.914139 DQ Delay:
3937 12:23:36.916489 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3938 12:23:36.919956 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3939 12:23:36.923567 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3940 12:23:36.926760 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3941 12:23:36.927313
3942 12:23:36.927680
3943 12:23:36.928015 ==
3944 12:23:36.930008 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 12:23:36.936436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3946 12:23:36.936976 ==
3947 12:23:36.937339
3948 12:23:36.937672
3949 12:23:36.937990 TX Vref Scan disable
3950 12:23:36.940632 == TX Byte 0 ==
3951 12:23:36.943541 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3952 12:23:36.950224 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3953 12:23:36.950754 == TX Byte 1 ==
3954 12:23:36.953574 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3955 12:23:36.960151 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3956 12:23:36.960759 ==
3957 12:23:36.963421 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 12:23:36.966830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3959 12:23:36.967312 ==
3960 12:23:36.967741
3961 12:23:36.968074
3962 12:23:36.969997 TX Vref Scan disable
3963 12:23:36.973481 == TX Byte 0 ==
3964 12:23:36.976688 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3965 12:23:36.980326 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3966 12:23:36.980908 == TX Byte 1 ==
3967 12:23:36.987174 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3968 12:23:36.990089 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3969 12:23:36.990648
3970 12:23:36.991010 [DATLAT]
3971 12:23:36.993226 Freq=600, CH0 RK0
3972 12:23:36.993681
3973 12:23:36.994039 DATLAT Default: 0x9
3974 12:23:36.996574 0, 0xFFFF, sum = 0
3975 12:23:37.000032 1, 0xFFFF, sum = 0
3976 12:23:37.000592 2, 0xFFFF, sum = 0
3977 12:23:37.003235 3, 0xFFFF, sum = 0
3978 12:23:37.003702 4, 0xFFFF, sum = 0
3979 12:23:37.006699 5, 0xFFFF, sum = 0
3980 12:23:37.007203 6, 0xFFFF, sum = 0
3981 12:23:37.009954 7, 0x0, sum = 1
3982 12:23:37.010415 8, 0x0, sum = 2
3983 12:23:37.010778 9, 0x0, sum = 3
3984 12:23:37.013242 10, 0x0, sum = 4
3985 12:23:37.013700 best_step = 8
3986 12:23:37.014056
3987 12:23:37.014385 ==
3988 12:23:37.016512 Dram Type= 6, Freq= 0, CH_0, rank 0
3989 12:23:37.023456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3990 12:23:37.023914 ==
3991 12:23:37.024333 RX Vref Scan: 1
3992 12:23:37.024680
3993 12:23:37.026602 RX Vref 0 -> 0, step: 1
3994 12:23:37.027050
3995 12:23:37.030033 RX Delay -195 -> 252, step: 8
3996 12:23:37.030586
3997 12:23:37.033291 Set Vref, RX VrefLevel [Byte0]: 45
3998 12:23:37.036662 [Byte1]: 46
3999 12:23:37.037224
4000 12:23:37.040022 Final RX Vref Byte 0 = 45 to rank0
4001 12:23:37.043083 Final RX Vref Byte 1 = 46 to rank0
4002 12:23:37.046689 Final RX Vref Byte 0 = 45 to rank1
4003 12:23:37.050209 Final RX Vref Byte 1 = 46 to rank1==
4004 12:23:37.053114 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 12:23:37.056392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4006 12:23:37.056851 ==
4007 12:23:37.059856 DQS Delay:
4008 12:23:37.060356 DQS0 = 0, DQS1 = 0
4009 12:23:37.062993 DQM Delay:
4010 12:23:37.063490 DQM0 = 39, DQM1 = 30
4011 12:23:37.063843 DQ Delay:
4012 12:23:37.066308 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4013 12:23:37.069978 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =44
4014 12:23:37.073107 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4015 12:23:37.076386 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4016 12:23:37.076989
4017 12:23:37.077438
4018 12:23:37.086495 [DQSOSCAuto] RK0, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4019 12:23:37.089603 CH0 RK0: MR19=808, MR18=5959
4020 12:23:37.092940 CH0_RK0: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
4021 12:23:37.096150
4022 12:23:37.099787 ----->DramcWriteLeveling(PI) begin...
4023 12:23:37.100488 ==
4024 12:23:37.102716 Dram Type= 6, Freq= 0, CH_0, rank 1
4025 12:23:37.106261 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4026 12:23:37.106732 ==
4027 12:23:37.109360 Write leveling (Byte 0): 30 => 30
4028 12:23:37.112661 Write leveling (Byte 1): 28 => 28
4029 12:23:37.116143 DramcWriteLeveling(PI) end<-----
4030 12:23:37.116639
4031 12:23:37.116995 ==
4032 12:23:37.119483 Dram Type= 6, Freq= 0, CH_0, rank 1
4033 12:23:37.123042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4034 12:23:37.123588 ==
4035 12:23:37.126047 [Gating] SW mode calibration
4036 12:23:37.132854 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4037 12:23:37.139528 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4038 12:23:37.143092 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4039 12:23:37.146246 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4040 12:23:37.152881 0 5 8 | B1->B0 | 3333 2f2f | 1 0 | (1 0) (0 1)
4041 12:23:37.156337 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4042 12:23:37.159363 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 12:23:37.165784 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 12:23:37.169270 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 12:23:37.172667 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 12:23:37.179429 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 12:23:37.182693 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 12:23:37.186123 0 6 8 | B1->B0 | 2828 3333 | 0 0 | (0 0) (0 0)
4049 12:23:37.189277 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4050 12:23:37.196018 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 12:23:37.199061 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 12:23:37.202131 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 12:23:37.209106 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 12:23:37.212529 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 12:23:37.215713 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 12:23:37.222230 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4057 12:23:37.225572 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:23:37.229397 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:23:37.235377 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:23:37.239422 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 12:23:37.242105 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:23:37.249129 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:23:37.252020 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:23:37.255613 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:23:37.262031 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:23:37.265176 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:23:37.268717 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:23:37.274983 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:23:37.278478 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:23:37.281977 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:23:37.288551 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:23:37.291779 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4073 12:23:37.295238 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 12:23:37.298261 Total UI for P1: 0, mck2ui 16
4075 12:23:37.302013 best dqsien dly found for B0: ( 0, 9, 8)
4076 12:23:37.304844 Total UI for P1: 0, mck2ui 16
4077 12:23:37.308761 best dqsien dly found for B1: ( 0, 9, 10)
4078 12:23:37.312279 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4079 12:23:37.315137 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4080 12:23:37.315584
4081 12:23:37.322092 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4082 12:23:37.325141 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4083 12:23:37.325700 [Gating] SW calibration Done
4084 12:23:37.328807 ==
4085 12:23:37.331696 Dram Type= 6, Freq= 0, CH_0, rank 1
4086 12:23:37.335222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4087 12:23:37.335906 ==
4088 12:23:37.336333 RX Vref Scan: 0
4089 12:23:37.336676
4090 12:23:37.338311 RX Vref 0 -> 0, step: 1
4091 12:23:37.338759
4092 12:23:37.341890 RX Delay -230 -> 252, step: 16
4093 12:23:37.344954 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4094 12:23:37.348327 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4095 12:23:37.355146 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4096 12:23:37.358419 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4097 12:23:37.362121 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4098 12:23:37.365334 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4099 12:23:37.368297 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4100 12:23:37.374955 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4101 12:23:37.378073 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4102 12:23:37.382022 iDelay=218, Bit 9, Center 17 (-134 ~ 169) 304
4103 12:23:37.385061 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4104 12:23:37.391366 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4105 12:23:37.394829 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4106 12:23:37.398097 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4107 12:23:37.401162 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4108 12:23:37.407934 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4109 12:23:37.408568 ==
4110 12:23:37.411428 Dram Type= 6, Freq= 0, CH_0, rank 1
4111 12:23:37.414885 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4112 12:23:37.415448 ==
4113 12:23:37.415813 DQS Delay:
4114 12:23:37.417646 DQS0 = 0, DQS1 = 0
4115 12:23:37.418103 DQM Delay:
4116 12:23:37.421470 DQM0 = 44, DQM1 = 33
4117 12:23:37.422027 DQ Delay:
4118 12:23:37.424357 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4119 12:23:37.427818 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =57
4120 12:23:37.431210 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4121 12:23:37.434427 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4122 12:23:37.434995
4123 12:23:37.435361
4124 12:23:37.435695 ==
4125 12:23:37.437610 Dram Type= 6, Freq= 0, CH_0, rank 1
4126 12:23:37.440899 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4127 12:23:37.444547 ==
4128 12:23:37.445112
4129 12:23:37.445478
4130 12:23:37.445815 TX Vref Scan disable
4131 12:23:37.447846 == TX Byte 0 ==
4132 12:23:37.450993 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4133 12:23:37.454491 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4134 12:23:37.457388 == TX Byte 1 ==
4135 12:23:37.460964 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4136 12:23:37.464338 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4137 12:23:37.467390 ==
4138 12:23:37.471061 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 12:23:37.474330 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4140 12:23:37.474803 ==
4141 12:23:37.475201
4142 12:23:37.475534
4143 12:23:37.477354 TX Vref Scan disable
4144 12:23:37.477803 == TX Byte 0 ==
4145 12:23:37.484313 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4146 12:23:37.487423 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4147 12:23:37.490647 == TX Byte 1 ==
4148 12:23:37.493975 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4149 12:23:37.497450 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4150 12:23:37.498000
4151 12:23:37.498358 [DATLAT]
4152 12:23:37.500440 Freq=600, CH0 RK1
4153 12:23:37.500891
4154 12:23:37.501258 DATLAT Default: 0x8
4155 12:23:37.503693 0, 0xFFFF, sum = 0
4156 12:23:37.504238 1, 0xFFFF, sum = 0
4157 12:23:37.507212 2, 0xFFFF, sum = 0
4158 12:23:37.510908 3, 0xFFFF, sum = 0
4159 12:23:37.511463 4, 0xFFFF, sum = 0
4160 12:23:37.513582 5, 0xFFFF, sum = 0
4161 12:23:37.514044 6, 0xFFFF, sum = 0
4162 12:23:37.517037 7, 0x0, sum = 1
4163 12:23:37.517501 8, 0x0, sum = 2
4164 12:23:37.517867 9, 0x0, sum = 3
4165 12:23:37.520573 10, 0x0, sum = 4
4166 12:23:37.521131 best_step = 8
4167 12:23:37.521493
4168 12:23:37.521828 ==
4169 12:23:37.523762 Dram Type= 6, Freq= 0, CH_0, rank 1
4170 12:23:37.530670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4171 12:23:37.531225 ==
4172 12:23:37.531606 RX Vref Scan: 0
4173 12:23:37.531946
4174 12:23:37.533620 RX Vref 0 -> 0, step: 1
4175 12:23:37.534075
4176 12:23:37.537554 RX Delay -179 -> 252, step: 8
4177 12:23:37.540014 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4178 12:23:37.547097 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4179 12:23:37.550392 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4180 12:23:37.553427 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4181 12:23:37.557113 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4182 12:23:37.563278 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4183 12:23:37.566509 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4184 12:23:37.570580 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4185 12:23:37.573347 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4186 12:23:37.576629 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4187 12:23:37.583602 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4188 12:23:37.586523 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4189 12:23:37.590241 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4190 12:23:37.593554 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4191 12:23:37.600350 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4192 12:23:37.603507 iDelay=205, Bit 15, Center 40 (-107 ~ 188) 296
4193 12:23:37.604004 ==
4194 12:23:37.606409 Dram Type= 6, Freq= 0, CH_0, rank 1
4195 12:23:37.610130 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4196 12:23:37.610684 ==
4197 12:23:37.612926 DQS Delay:
4198 12:23:37.613384 DQS0 = 0, DQS1 = 0
4199 12:23:37.613747 DQM Delay:
4200 12:23:37.616394 DQM0 = 41, DQM1 = 31
4201 12:23:37.616853 DQ Delay:
4202 12:23:37.619860 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4203 12:23:37.623440 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =52
4204 12:23:37.626500 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4205 12:23:37.629752 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =40
4206 12:23:37.630299
4207 12:23:37.630657
4208 12:23:37.639773 [DQSOSCAuto] RK1, (LSB)MR18= 0x7171, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4209 12:23:37.642673 CH0 RK1: MR19=808, MR18=7171
4210 12:23:37.646291 CH0_RK1: MR19=0x808, MR18=0x7171, DQSOSC=388, MR23=63, INC=174, DEC=116
4211 12:23:37.649435 [RxdqsGatingPostProcess] freq 600
4212 12:23:37.656025 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4213 12:23:37.659327 Pre-setting of DQS Precalculation
4214 12:23:37.662975 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4215 12:23:37.663538 ==
4216 12:23:37.666181 Dram Type= 6, Freq= 0, CH_1, rank 0
4217 12:23:37.672832 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4218 12:23:37.673400 ==
4219 12:23:37.675877 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4220 12:23:37.682724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4221 12:23:37.685956 [CA 0] Center 35 (5~66) winsize 62
4222 12:23:37.690304 [CA 1] Center 35 (5~66) winsize 62
4223 12:23:37.692819 [CA 2] Center 33 (3~64) winsize 62
4224 12:23:37.696273 [CA 3] Center 33 (3~64) winsize 62
4225 12:23:37.699254 [CA 4] Center 33 (2~64) winsize 63
4226 12:23:37.702540 [CA 5] Center 33 (2~64) winsize 63
4227 12:23:37.703087
4228 12:23:37.705751 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4229 12:23:37.706198
4230 12:23:37.709257 [CATrainingPosCal] consider 1 rank data
4231 12:23:37.712371 u2DelayCellTimex100 = 270/100 ps
4232 12:23:37.716236 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4233 12:23:37.722525 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4234 12:23:37.725726 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4235 12:23:37.728918 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4236 12:23:37.732489 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4237 12:23:37.735890 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4238 12:23:37.736500
4239 12:23:37.738895 CA PerBit enable=1, Macro0, CA PI delay=33
4240 12:23:37.739351
4241 12:23:37.742507 [CBTSetCACLKResult] CA Dly = 33
4242 12:23:37.745690 CS Dly: 5 (0~36)
4243 12:23:37.746254 ==
4244 12:23:37.749071 Dram Type= 6, Freq= 0, CH_1, rank 1
4245 12:23:37.752316 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4246 12:23:37.752881 ==
4247 12:23:37.755853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4248 12:23:37.762406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4249 12:23:37.766488 [CA 0] Center 35 (4~66) winsize 63
4250 12:23:37.769495 [CA 1] Center 34 (4~65) winsize 62
4251 12:23:37.772937 [CA 2] Center 33 (3~64) winsize 62
4252 12:23:37.776247 [CA 3] Center 33 (3~64) winsize 62
4253 12:23:37.779644 [CA 4] Center 32 (2~63) winsize 62
4254 12:23:37.782850 [CA 5] Center 32 (2~63) winsize 62
4255 12:23:37.783400
4256 12:23:37.786057 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4257 12:23:37.786604
4258 12:23:37.789648 [CATrainingPosCal] consider 2 rank data
4259 12:23:37.792951 u2DelayCellTimex100 = 270/100 ps
4260 12:23:37.796110 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4261 12:23:37.802840 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4262 12:23:37.805792 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4263 12:23:37.809619 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4264 12:23:37.812326 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4265 12:23:37.815842 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4266 12:23:37.816445
4267 12:23:37.819279 CA PerBit enable=1, Macro0, CA PI delay=32
4268 12:23:37.819838
4269 12:23:37.822534 [CBTSetCACLKResult] CA Dly = 32
4270 12:23:37.823088 CS Dly: 5 (0~36)
4271 12:23:37.825462
4272 12:23:37.829227 ----->DramcWriteLeveling(PI) begin...
4273 12:23:37.829780 ==
4274 12:23:37.832229 Dram Type= 6, Freq= 0, CH_1, rank 0
4275 12:23:37.835736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4276 12:23:37.836352 ==
4277 12:23:37.838769 Write leveling (Byte 0): 28 => 28
4278 12:23:37.842299 Write leveling (Byte 1): 28 => 28
4279 12:23:37.845493 DramcWriteLeveling(PI) end<-----
4280 12:23:37.846039
4281 12:23:37.846398 ==
4282 12:23:37.848807 Dram Type= 6, Freq= 0, CH_1, rank 0
4283 12:23:37.852090 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4284 12:23:37.852678 ==
4285 12:23:37.855576 [Gating] SW mode calibration
4286 12:23:37.862519 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4287 12:23:37.868881 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4288 12:23:37.872120 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4289 12:23:37.875294 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4290 12:23:37.882292 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4291 12:23:37.885300 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 12:23:37.888887 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 12:23:37.895109 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 12:23:37.898791 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 12:23:37.901896 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4296 12:23:37.908315 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 12:23:37.911923 0 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
4298 12:23:37.915038 0 6 8 | B1->B0 | 3333 3e3e | 0 1 | (0 0) (0 0)
4299 12:23:37.921517 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 12:23:37.924806 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 12:23:37.928146 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 12:23:37.935087 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 12:23:37.938358 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 12:23:37.941872 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 12:23:37.948316 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 12:23:37.951699 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4307 12:23:37.954676 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 12:23:37.958373 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 12:23:37.965123 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 12:23:37.968104 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 12:23:37.971872 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 12:23:37.978011 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 12:23:37.981367 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 12:23:37.984842 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 12:23:37.991575 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 12:23:37.994278 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 12:23:37.998074 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 12:23:38.004230 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 12:23:38.007570 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 12:23:38.011236 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 12:23:38.018063 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4322 12:23:38.021040 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4323 12:23:38.024141 Total UI for P1: 0, mck2ui 16
4324 12:23:38.027532 best dqsien dly found for B0: ( 0, 9, 4)
4325 12:23:38.031167 Total UI for P1: 0, mck2ui 16
4326 12:23:38.034243 best dqsien dly found for B1: ( 0, 9, 6)
4327 12:23:38.037654 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4328 12:23:38.041160 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4329 12:23:38.041708
4330 12:23:38.044339 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4331 12:23:38.047780 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4332 12:23:38.050918 [Gating] SW calibration Done
4333 12:23:38.051467 ==
4334 12:23:38.054223 Dram Type= 6, Freq= 0, CH_1, rank 0
4335 12:23:38.060859 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4336 12:23:38.061460 ==
4337 12:23:38.061829 RX Vref Scan: 0
4338 12:23:38.062165
4339 12:23:38.064218 RX Vref 0 -> 0, step: 1
4340 12:23:38.064788
4341 12:23:38.067348 RX Delay -230 -> 252, step: 16
4342 12:23:38.070556 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4343 12:23:38.073714 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4344 12:23:38.077410 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4345 12:23:38.084273 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4346 12:23:38.087164 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4347 12:23:38.090972 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4348 12:23:38.094288 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4349 12:23:38.097204 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4350 12:23:38.103843 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4351 12:23:38.107130 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4352 12:23:38.110770 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4353 12:23:38.114020 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4354 12:23:38.120434 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4355 12:23:38.123816 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4356 12:23:38.127256 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4357 12:23:38.130849 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4358 12:23:38.131396 ==
4359 12:23:38.133967 Dram Type= 6, Freq= 0, CH_1, rank 0
4360 12:23:38.140075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4361 12:23:38.140565 ==
4362 12:23:38.140924 DQS Delay:
4363 12:23:38.143647 DQS0 = 0, DQS1 = 0
4364 12:23:38.144094 DQM Delay:
4365 12:23:38.147139 DQM0 = 39, DQM1 = 33
4366 12:23:38.147587 DQ Delay:
4367 12:23:38.150143 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4368 12:23:38.153490 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4369 12:23:38.156724 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4370 12:23:38.160394 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4371 12:23:38.160940
4372 12:23:38.161297
4373 12:23:38.161626 ==
4374 12:23:38.163491 Dram Type= 6, Freq= 0, CH_1, rank 0
4375 12:23:38.167210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4376 12:23:38.167999 ==
4377 12:23:38.168440
4378 12:23:38.168784
4379 12:23:38.170169 TX Vref Scan disable
4380 12:23:38.173293 == TX Byte 0 ==
4381 12:23:38.176909 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4382 12:23:38.180419 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4383 12:23:38.183214 == TX Byte 1 ==
4384 12:23:38.186839 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4385 12:23:38.190231 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4386 12:23:38.190682 ==
4387 12:23:38.193483 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 12:23:38.196498 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4389 12:23:38.199976 ==
4390 12:23:38.200704
4391 12:23:38.201222
4392 12:23:38.201714 TX Vref Scan disable
4393 12:23:38.203749 == TX Byte 0 ==
4394 12:23:38.207112 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4395 12:23:38.213531 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4396 12:23:38.214068 == TX Byte 1 ==
4397 12:23:38.217083 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4398 12:23:38.223973 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4399 12:23:38.224584
4400 12:23:38.224947 [DATLAT]
4401 12:23:38.225277 Freq=600, CH1 RK0
4402 12:23:38.225594
4403 12:23:38.227185 DATLAT Default: 0x9
4404 12:23:38.227702 0, 0xFFFF, sum = 0
4405 12:23:38.230633 1, 0xFFFF, sum = 0
4406 12:23:38.233700 2, 0xFFFF, sum = 0
4407 12:23:38.234155 3, 0xFFFF, sum = 0
4408 12:23:38.237037 4, 0xFFFF, sum = 0
4409 12:23:38.237494 5, 0xFFFF, sum = 0
4410 12:23:38.240377 6, 0xFFFF, sum = 0
4411 12:23:38.240933 7, 0x0, sum = 1
4412 12:23:38.241300 8, 0x0, sum = 2
4413 12:23:38.243787 9, 0x0, sum = 3
4414 12:23:38.244378 10, 0x0, sum = 4
4415 12:23:38.247317 best_step = 8
4416 12:23:38.247856
4417 12:23:38.248251 ==
4418 12:23:38.250351 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 12:23:38.253762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4420 12:23:38.254310 ==
4421 12:23:38.256814 RX Vref Scan: 1
4422 12:23:38.257262
4423 12:23:38.257614 RX Vref 0 -> 0, step: 1
4424 12:23:38.257941
4425 12:23:38.260341 RX Delay -195 -> 252, step: 8
4426 12:23:38.260884
4427 12:23:38.263440 Set Vref, RX VrefLevel [Byte0]: 52
4428 12:23:38.266921 [Byte1]: 49
4429 12:23:38.270865
4430 12:23:38.271314 Final RX Vref Byte 0 = 52 to rank0
4431 12:23:38.274499 Final RX Vref Byte 1 = 49 to rank0
4432 12:23:38.277653 Final RX Vref Byte 0 = 52 to rank1
4433 12:23:38.280915 Final RX Vref Byte 1 = 49 to rank1==
4434 12:23:38.284259 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 12:23:38.290586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4436 12:23:38.291128 ==
4437 12:23:38.291483 DQS Delay:
4438 12:23:38.293794 DQS0 = 0, DQS1 = 0
4439 12:23:38.294242 DQM Delay:
4440 12:23:38.294599 DQM0 = 37, DQM1 = 31
4441 12:23:38.297120 DQ Delay:
4442 12:23:38.300832 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4443 12:23:38.303777 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4444 12:23:38.307615 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =24
4445 12:23:38.310784 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4446 12:23:38.311323
4447 12:23:38.311683
4448 12:23:38.317470 [DQSOSCAuto] RK0, (LSB)MR18= 0x7474, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4449 12:23:38.321167 CH1 RK0: MR19=808, MR18=7474
4450 12:23:38.327744 CH1_RK0: MR19=0x808, MR18=0x7474, DQSOSC=388, MR23=63, INC=174, DEC=116
4451 12:23:38.328334
4452 12:23:38.330808 ----->DramcWriteLeveling(PI) begin...
4453 12:23:38.331360 ==
4454 12:23:38.333995 Dram Type= 6, Freq= 0, CH_1, rank 1
4455 12:23:38.337572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4456 12:23:38.338119 ==
4457 12:23:38.340654 Write leveling (Byte 0): 28 => 28
4458 12:23:38.344049 Write leveling (Byte 1): 27 => 27
4459 12:23:38.347224 DramcWriteLeveling(PI) end<-----
4460 12:23:38.347765
4461 12:23:38.348117 ==
4462 12:23:38.350787 Dram Type= 6, Freq= 0, CH_1, rank 1
4463 12:23:38.354345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4464 12:23:38.354890 ==
4465 12:23:38.356915 [Gating] SW mode calibration
4466 12:23:38.364153 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4467 12:23:38.370228 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4468 12:23:38.374023 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 12:23:38.380493 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4470 12:23:38.383593 0 5 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4471 12:23:38.386697 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 12:23:38.394003 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 12:23:38.396990 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 12:23:38.400698 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 12:23:38.403650 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 12:23:38.410313 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 12:23:38.413865 0 6 4 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
4478 12:23:38.416645 0 6 8 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
4479 12:23:38.423659 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 12:23:38.427121 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 12:23:38.429943 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 12:23:38.436870 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 12:23:38.440542 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 12:23:38.443686 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 12:23:38.450390 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 12:23:38.453317 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 12:23:38.456436 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:23:38.463177 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:23:38.466451 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:23:38.469586 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 12:23:38.476355 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 12:23:38.479948 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:23:38.483236 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 12:23:38.489662 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 12:23:38.493173 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:23:38.496421 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:23:38.502968 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:23:38.506182 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:23:38.509173 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:23:38.516026 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:23:38.519137 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4502 12:23:38.522480 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4503 12:23:38.528902 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 12:23:38.529464 Total UI for P1: 0, mck2ui 16
4505 12:23:38.535755 best dqsien dly found for B0: ( 0, 9, 6)
4506 12:23:38.536342 Total UI for P1: 0, mck2ui 16
4507 12:23:38.542706 best dqsien dly found for B1: ( 0, 9, 8)
4508 12:23:38.546015 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4509 12:23:38.549048 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4510 12:23:38.549506
4511 12:23:38.552086 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4512 12:23:38.555677 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4513 12:23:38.558822 [Gating] SW calibration Done
4514 12:23:38.559376 ==
4515 12:23:38.562292 Dram Type= 6, Freq= 0, CH_1, rank 1
4516 12:23:38.565632 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4517 12:23:38.566193 ==
4518 12:23:38.568541 RX Vref Scan: 0
4519 12:23:38.568995
4520 12:23:38.569355 RX Vref 0 -> 0, step: 1
4521 12:23:38.569687
4522 12:23:38.571597 RX Delay -230 -> 252, step: 16
4523 12:23:38.578661 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4524 12:23:38.581944 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4525 12:23:38.584827 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4526 12:23:38.588738 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4527 12:23:38.595315 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4528 12:23:38.598229 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4529 12:23:38.602290 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4530 12:23:38.605082 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4531 12:23:38.608489 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4532 12:23:38.614867 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4533 12:23:38.618397 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4534 12:23:38.621463 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4535 12:23:38.624774 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4536 12:23:38.631647 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4537 12:23:38.634857 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4538 12:23:38.637935 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4539 12:23:38.638391 ==
4540 12:23:38.641354 Dram Type= 6, Freq= 0, CH_1, rank 1
4541 12:23:38.644843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4542 12:23:38.648255 ==
4543 12:23:38.648816 DQS Delay:
4544 12:23:38.649176 DQS0 = 0, DQS1 = 0
4545 12:23:38.651323 DQM Delay:
4546 12:23:38.651878 DQM0 = 43, DQM1 = 35
4547 12:23:38.654690 DQ Delay:
4548 12:23:38.657733 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4549 12:23:38.658208 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4550 12:23:38.661266 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4551 12:23:38.664698 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4552 12:23:38.667787
4553 12:23:38.668375
4554 12:23:38.668738 ==
4555 12:23:38.670842 Dram Type= 6, Freq= 0, CH_1, rank 1
4556 12:23:38.674550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4557 12:23:38.675126 ==
4558 12:23:38.675490
4559 12:23:38.675822
4560 12:23:38.677657 TX Vref Scan disable
4561 12:23:38.678109 == TX Byte 0 ==
4562 12:23:38.684285 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4563 12:23:38.687598 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4564 12:23:38.688144 == TX Byte 1 ==
4565 12:23:38.694197 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4566 12:23:38.697504 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4567 12:23:38.698052 ==
4568 12:23:38.701110 Dram Type= 6, Freq= 0, CH_1, rank 1
4569 12:23:38.704200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4570 12:23:38.704760 ==
4571 12:23:38.705121
4572 12:23:38.705454
4573 12:23:38.707493 TX Vref Scan disable
4574 12:23:38.710507 == TX Byte 0 ==
4575 12:23:38.714211 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4576 12:23:38.720235 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4577 12:23:38.720705 == TX Byte 1 ==
4578 12:23:38.723687 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4579 12:23:38.730897 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4580 12:23:38.731474
4581 12:23:38.731836 [DATLAT]
4582 12:23:38.732218 Freq=600, CH1 RK1
4583 12:23:38.732582
4584 12:23:38.733829 DATLAT Default: 0x8
4585 12:23:38.734287 0, 0xFFFF, sum = 0
4586 12:23:38.737363 1, 0xFFFF, sum = 0
4587 12:23:38.740354 2, 0xFFFF, sum = 0
4588 12:23:38.740836 3, 0xFFFF, sum = 0
4589 12:23:38.743882 4, 0xFFFF, sum = 0
4590 12:23:38.744496 5, 0xFFFF, sum = 0
4591 12:23:38.747259 6, 0xFFFF, sum = 0
4592 12:23:38.747828 7, 0x0, sum = 1
4593 12:23:38.750493 8, 0x0, sum = 2
4594 12:23:38.751063 9, 0x0, sum = 3
4595 12:23:38.751434 10, 0x0, sum = 4
4596 12:23:38.753666 best_step = 8
4597 12:23:38.754123
4598 12:23:38.754484 ==
4599 12:23:38.757104 Dram Type= 6, Freq= 0, CH_1, rank 1
4600 12:23:38.760394 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4601 12:23:38.760942 ==
4602 12:23:38.763458 RX Vref Scan: 0
4603 12:23:38.763913
4604 12:23:38.764339 RX Vref 0 -> 0, step: 1
4605 12:23:38.764782
4606 12:23:38.766663 RX Delay -195 -> 252, step: 8
4607 12:23:38.774068 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4608 12:23:38.777572 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4609 12:23:38.780810 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4610 12:23:38.784783 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4611 12:23:38.790873 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4612 12:23:38.794548 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4613 12:23:38.797376 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4614 12:23:38.800583 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4615 12:23:38.804277 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4616 12:23:38.810447 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4617 12:23:38.814356 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4618 12:23:38.817498 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4619 12:23:38.820900 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4620 12:23:38.827611 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4621 12:23:38.830668 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4622 12:23:38.834295 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4623 12:23:38.834859 ==
4624 12:23:38.837094 Dram Type= 6, Freq= 0, CH_1, rank 1
4625 12:23:38.840624 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4626 12:23:38.843759 ==
4627 12:23:38.844243 DQS Delay:
4628 12:23:38.844613 DQS0 = 0, DQS1 = 0
4629 12:23:38.847242 DQM Delay:
4630 12:23:38.847713 DQM0 = 36, DQM1 = 29
4631 12:23:38.850830 DQ Delay:
4632 12:23:38.854250 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4633 12:23:38.854810 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4634 12:23:38.857040 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =20
4635 12:23:38.860735 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4636 12:23:38.863917
4637 12:23:38.864504
4638 12:23:38.870648 [DQSOSCAuto] RK1, (LSB)MR18= 0x5959, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4639 12:23:38.873733 CH1 RK1: MR19=808, MR18=5959
4640 12:23:38.880738 CH1_RK1: MR19=0x808, MR18=0x5959, DQSOSC=393, MR23=63, INC=169, DEC=113
4641 12:23:38.883815 [RxdqsGatingPostProcess] freq 600
4642 12:23:38.887028 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4643 12:23:38.890338 Pre-setting of DQS Precalculation
4644 12:23:38.897131 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4645 12:23:38.903765 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4646 12:23:38.910044 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4647 12:23:38.910507
4648 12:23:38.911163
4649 12:23:38.913594 [Calibration Summary] 1200 Mbps
4650 12:23:38.914069 CH 0, Rank 0
4651 12:23:38.916903 SW Impedance : PASS
4652 12:23:38.920362 DUTY Scan : NO K
4653 12:23:38.920934 ZQ Calibration : PASS
4654 12:23:38.923720 Jitter Meter : NO K
4655 12:23:38.926883 CBT Training : PASS
4656 12:23:38.927461 Write leveling : PASS
4657 12:23:38.930221 RX DQS gating : PASS
4658 12:23:38.933432 RX DQ/DQS(RDDQC) : PASS
4659 12:23:38.934006 TX DQ/DQS : PASS
4660 12:23:38.936988 RX DATLAT : PASS
4661 12:23:38.937462 RX DQ/DQS(Engine): PASS
4662 12:23:38.940140 TX OE : NO K
4663 12:23:38.940779 All Pass.
4664 12:23:38.941269
4665 12:23:38.943509 CH 0, Rank 1
4666 12:23:38.944083 SW Impedance : PASS
4667 12:23:38.946656 DUTY Scan : NO K
4668 12:23:38.950592 ZQ Calibration : PASS
4669 12:23:38.951167 Jitter Meter : NO K
4670 12:23:38.953590 CBT Training : PASS
4671 12:23:38.956643 Write leveling : PASS
4672 12:23:38.957217 RX DQS gating : PASS
4673 12:23:38.959948 RX DQ/DQS(RDDQC) : PASS
4674 12:23:38.963273 TX DQ/DQS : PASS
4675 12:23:38.963851 RX DATLAT : PASS
4676 12:23:38.966542 RX DQ/DQS(Engine): PASS
4677 12:23:38.970015 TX OE : NO K
4678 12:23:38.970592 All Pass.
4679 12:23:38.971086
4680 12:23:38.971542 CH 1, Rank 0
4681 12:23:38.973183 SW Impedance : PASS
4682 12:23:38.976354 DUTY Scan : NO K
4683 12:23:38.976847 ZQ Calibration : PASS
4684 12:23:38.980015 Jitter Meter : NO K
4685 12:23:38.982967 CBT Training : PASS
4686 12:23:38.983443 Write leveling : PASS
4687 12:23:38.986375 RX DQS gating : PASS
4688 12:23:38.989699 RX DQ/DQS(RDDQC) : PASS
4689 12:23:38.990282 TX DQ/DQS : PASS
4690 12:23:38.993178 RX DATLAT : PASS
4691 12:23:38.993748 RX DQ/DQS(Engine): PASS
4692 12:23:38.996345 TX OE : NO K
4693 12:23:38.996920 All Pass.
4694 12:23:38.997411
4695 12:23:39.000047 CH 1, Rank 1
4696 12:23:39.000674 SW Impedance : PASS
4697 12:23:39.003355 DUTY Scan : NO K
4698 12:23:39.006218 ZQ Calibration : PASS
4699 12:23:39.006691 Jitter Meter : NO K
4700 12:23:39.009508 CBT Training : PASS
4701 12:23:39.012761 Write leveling : PASS
4702 12:23:39.013235 RX DQS gating : PASS
4703 12:23:39.016229 RX DQ/DQS(RDDQC) : PASS
4704 12:23:39.019453 TX DQ/DQS : PASS
4705 12:23:39.020052 RX DATLAT : PASS
4706 12:23:39.022822 RX DQ/DQS(Engine): PASS
4707 12:23:39.026255 TX OE : NO K
4708 12:23:39.026843 All Pass.
4709 12:23:39.027333
4710 12:23:39.029147 DramC Write-DBI off
4711 12:23:39.029617 PER_BANK_REFRESH: Hybrid Mode
4712 12:23:39.032746 TX_TRACKING: ON
4713 12:23:39.039539 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4714 12:23:39.046078 [FAST_K] Save calibration result to emmc
4715 12:23:39.048969 dramc_set_vcore_voltage set vcore to 662500
4716 12:23:39.049444 Read voltage for 933, 3
4717 12:23:39.052912 Vio18 = 0
4718 12:23:39.053489 Vcore = 662500
4719 12:23:39.053979 Vdram = 0
4720 12:23:39.055951 Vddq = 0
4721 12:23:39.056577 Vmddr = 0
4722 12:23:39.059336 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4723 12:23:39.065894 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4724 12:23:39.069316 MEM_TYPE=3, freq_sel=17
4725 12:23:39.072210 sv_algorithm_assistance_LP4_1600
4726 12:23:39.075891 ============ PULL DRAM RESETB DOWN ============
4727 12:23:39.079545 ========== PULL DRAM RESETB DOWN end =========
4728 12:23:39.085706 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4729 12:23:39.088856 ===================================
4730 12:23:39.089318 LPDDR4 DRAM CONFIGURATION
4731 12:23:39.092399 ===================================
4732 12:23:39.095709 EX_ROW_EN[0] = 0x0
4733 12:23:39.096315 EX_ROW_EN[1] = 0x0
4734 12:23:39.099044 LP4Y_EN = 0x0
4735 12:23:39.099604 WORK_FSP = 0x0
4736 12:23:39.102445 WL = 0x3
4737 12:23:39.103005 RL = 0x3
4738 12:23:39.106002 BL = 0x2
4739 12:23:39.108842 RPST = 0x0
4740 12:23:39.109406 RD_PRE = 0x0
4741 12:23:39.112000 WR_PRE = 0x1
4742 12:23:39.112566 WR_PST = 0x0
4743 12:23:39.115739 DBI_WR = 0x0
4744 12:23:39.116355 DBI_RD = 0x0
4745 12:23:39.119083 OTF = 0x1
4746 12:23:39.121762 ===================================
4747 12:23:39.125387 ===================================
4748 12:23:39.125941 ANA top config
4749 12:23:39.128470 ===================================
4750 12:23:39.131832 DLL_ASYNC_EN = 0
4751 12:23:39.135411 ALL_SLAVE_EN = 1
4752 12:23:39.135964 NEW_RANK_MODE = 1
4753 12:23:39.138869 DLL_IDLE_MODE = 1
4754 12:23:39.141957 LP45_APHY_COMB_EN = 1
4755 12:23:39.145186 TX_ODT_DIS = 1
4756 12:23:39.145655 NEW_8X_MODE = 1
4757 12:23:39.148502 ===================================
4758 12:23:39.152139 ===================================
4759 12:23:39.155686 data_rate = 1866
4760 12:23:39.158749 CKR = 1
4761 12:23:39.162233 DQ_P2S_RATIO = 8
4762 12:23:39.164932 ===================================
4763 12:23:39.168919 CA_P2S_RATIO = 8
4764 12:23:39.171870 DQ_CA_OPEN = 0
4765 12:23:39.175125 DQ_SEMI_OPEN = 0
4766 12:23:39.175582 CA_SEMI_OPEN = 0
4767 12:23:39.178269 CA_FULL_RATE = 0
4768 12:23:39.181768 DQ_CKDIV4_EN = 1
4769 12:23:39.184878 CA_CKDIV4_EN = 1
4770 12:23:39.188439 CA_PREDIV_EN = 0
4771 12:23:39.191664 PH8_DLY = 0
4772 12:23:39.192239 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4773 12:23:39.195047 DQ_AAMCK_DIV = 4
4774 12:23:39.198167 CA_AAMCK_DIV = 4
4775 12:23:39.201733 CA_ADMCK_DIV = 4
4776 12:23:39.205069 DQ_TRACK_CA_EN = 0
4777 12:23:39.208140 CA_PICK = 933
4778 12:23:39.208854 CA_MCKIO = 933
4779 12:23:39.211507 MCKIO_SEMI = 0
4780 12:23:39.215216 PLL_FREQ = 3732
4781 12:23:39.218202 DQ_UI_PI_RATIO = 32
4782 12:23:39.221445 CA_UI_PI_RATIO = 0
4783 12:23:39.224681 ===================================
4784 12:23:39.228083 ===================================
4785 12:23:39.231798 memory_type:LPDDR4
4786 12:23:39.232399 GP_NUM : 10
4787 12:23:39.234506 SRAM_EN : 1
4788 12:23:39.234963 MD32_EN : 0
4789 12:23:39.237803 ===================================
4790 12:23:39.241441 [ANA_INIT] >>>>>>>>>>>>>>
4791 12:23:39.244881 <<<<<< [CONFIGURE PHASE]: ANA_TX
4792 12:23:39.247866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4793 12:23:39.251653 ===================================
4794 12:23:39.254390 data_rate = 1866,PCW = 0X8f00
4795 12:23:39.257744 ===================================
4796 12:23:39.261088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4797 12:23:39.268276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4798 12:23:39.270955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4799 12:23:39.277728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4800 12:23:39.281168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4801 12:23:39.284336 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4802 12:23:39.284891 [ANA_INIT] flow start
4803 12:23:39.287778 [ANA_INIT] PLL >>>>>>>>
4804 12:23:39.290780 [ANA_INIT] PLL <<<<<<<<
4805 12:23:39.291329 [ANA_INIT] MIDPI >>>>>>>>
4806 12:23:39.294462 [ANA_INIT] MIDPI <<<<<<<<
4807 12:23:39.297234 [ANA_INIT] DLL >>>>>>>>
4808 12:23:39.297687 [ANA_INIT] flow end
4809 12:23:39.304140 ============ LP4 DIFF to SE enter ============
4810 12:23:39.307173 ============ LP4 DIFF to SE exit ============
4811 12:23:39.310753 [ANA_INIT] <<<<<<<<<<<<<
4812 12:23:39.313849 [Flow] Enable top DCM control >>>>>
4813 12:23:39.317613 [Flow] Enable top DCM control <<<<<
4814 12:23:39.320503 Enable DLL master slave shuffle
4815 12:23:39.323940 ==============================================================
4816 12:23:39.327715 Gating Mode config
4817 12:23:39.330629 ==============================================================
4818 12:23:39.334145 Config description:
4819 12:23:39.344085 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4820 12:23:39.350227 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4821 12:23:39.353938 SELPH_MODE 0: By rank 1: By Phase
4822 12:23:39.360646 ==============================================================
4823 12:23:39.363815 GAT_TRACK_EN = 1
4824 12:23:39.366672 RX_GATING_MODE = 2
4825 12:23:39.370164 RX_GATING_TRACK_MODE = 2
4826 12:23:39.373457 SELPH_MODE = 1
4827 12:23:39.376699 PICG_EARLY_EN = 1
4828 12:23:39.377158 VALID_LAT_VALUE = 1
4829 12:23:39.383382 ==============================================================
4830 12:23:39.386547 Enter into Gating configuration >>>>
4831 12:23:39.389912 Exit from Gating configuration <<<<
4832 12:23:39.393624 Enter into DVFS_PRE_config >>>>>
4833 12:23:39.403015 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4834 12:23:39.406080 Exit from DVFS_PRE_config <<<<<
4835 12:23:39.409641 Enter into PICG configuration >>>>
4836 12:23:39.412758 Exit from PICG configuration <<<<
4837 12:23:39.416130 [RX_INPUT] configuration >>>>>
4838 12:23:39.419445 [RX_INPUT] configuration <<<<<
4839 12:23:39.422909 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4840 12:23:39.429437 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4841 12:23:39.436311 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4842 12:23:39.443624 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4843 12:23:39.449880 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4844 12:23:39.456280 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4845 12:23:39.459355 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4846 12:23:39.462736 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4847 12:23:39.465989 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4848 12:23:39.472802 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4849 12:23:39.476390 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4850 12:23:39.479290 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4851 12:23:39.482926 ===================================
4852 12:23:39.485838 LPDDR4 DRAM CONFIGURATION
4853 12:23:39.489223 ===================================
4854 12:23:39.489337 EX_ROW_EN[0] = 0x0
4855 12:23:39.492710 EX_ROW_EN[1] = 0x0
4856 12:23:39.492826 LP4Y_EN = 0x0
4857 12:23:39.495902 WORK_FSP = 0x0
4858 12:23:39.496093 WL = 0x3
4859 12:23:39.499531 RL = 0x3
4860 12:23:39.502678 BL = 0x2
4861 12:23:39.502835 RPST = 0x0
4862 12:23:39.506261 RD_PRE = 0x0
4863 12:23:39.506385 WR_PRE = 0x1
4864 12:23:39.509159 WR_PST = 0x0
4865 12:23:39.509284 DBI_WR = 0x0
4866 12:23:39.512665 DBI_RD = 0x0
4867 12:23:39.512804 OTF = 0x1
4868 12:23:39.515909 ===================================
4869 12:23:39.519402 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4870 12:23:39.525913 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4871 12:23:39.529211 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4872 12:23:39.532686 ===================================
4873 12:23:39.535861 LPDDR4 DRAM CONFIGURATION
4874 12:23:39.539354 ===================================
4875 12:23:39.539491 EX_ROW_EN[0] = 0x10
4876 12:23:39.542662 EX_ROW_EN[1] = 0x0
4877 12:23:39.542800 LP4Y_EN = 0x0
4878 12:23:39.545785 WORK_FSP = 0x0
4879 12:23:39.545924 WL = 0x3
4880 12:23:39.549004 RL = 0x3
4881 12:23:39.549142 BL = 0x2
4882 12:23:39.552644 RPST = 0x0
4883 12:23:39.552782 RD_PRE = 0x0
4884 12:23:39.556037 WR_PRE = 0x1
4885 12:23:39.559034 WR_PST = 0x0
4886 12:23:39.559190 DBI_WR = 0x0
4887 12:23:39.562434 DBI_RD = 0x0
4888 12:23:39.562589 OTF = 0x1
4889 12:23:39.566354 ===================================
4890 12:23:39.572732 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4891 12:23:39.576125 nWR fixed to 30
4892 12:23:39.579343 [ModeRegInit_LP4] CH0 RK0
4893 12:23:39.579757 [ModeRegInit_LP4] CH0 RK1
4894 12:23:39.582915 [ModeRegInit_LP4] CH1 RK0
4895 12:23:39.586055 [ModeRegInit_LP4] CH1 RK1
4896 12:23:39.586470 match AC timing 8
4897 12:23:39.592815 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4898 12:23:39.596349 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4899 12:23:39.599972 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4900 12:23:39.605767 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4901 12:23:39.609342 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4902 12:23:39.609862 ==
4903 12:23:39.612884 Dram Type= 6, Freq= 0, CH_0, rank 0
4904 12:23:39.615918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4905 12:23:39.616432 ==
4906 12:23:39.622917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4907 12:23:39.629143 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4908 12:23:39.632506 [CA 0] Center 38 (8~69) winsize 62
4909 12:23:39.636096 [CA 1] Center 38 (8~69) winsize 62
4910 12:23:39.639243 [CA 2] Center 36 (6~67) winsize 62
4911 12:23:39.642218 [CA 3] Center 36 (6~66) winsize 61
4912 12:23:39.645842 [CA 4] Center 34 (4~65) winsize 62
4913 12:23:39.649036 [CA 5] Center 34 (4~65) winsize 62
4914 12:23:39.649495
4915 12:23:39.652690 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4916 12:23:39.653258
4917 12:23:39.655582 [CATrainingPosCal] consider 1 rank data
4918 12:23:39.659231 u2DelayCellTimex100 = 270/100 ps
4919 12:23:39.662462 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4920 12:23:39.665787 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4921 12:23:39.668905 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4922 12:23:39.672330 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4923 12:23:39.678632 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4924 12:23:39.682168 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4925 12:23:39.682624
4926 12:23:39.685700 CA PerBit enable=1, Macro0, CA PI delay=34
4927 12:23:39.686249
4928 12:23:39.688595 [CBTSetCACLKResult] CA Dly = 34
4929 12:23:39.689049 CS Dly: 7 (0~38)
4930 12:23:39.689410 ==
4931 12:23:39.691805 Dram Type= 6, Freq= 0, CH_0, rank 1
4932 12:23:39.698878 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4933 12:23:39.699494 ==
4934 12:23:39.701999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4935 12:23:39.708655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4936 12:23:39.711943 [CA 0] Center 38 (8~69) winsize 62
4937 12:23:39.715071 [CA 1] Center 38 (8~69) winsize 62
4938 12:23:39.718920 [CA 2] Center 36 (5~67) winsize 63
4939 12:23:39.721835 [CA 3] Center 35 (5~66) winsize 62
4940 12:23:39.725015 [CA 4] Center 34 (4~65) winsize 62
4941 12:23:39.729121 [CA 5] Center 34 (4~65) winsize 62
4942 12:23:39.729671
4943 12:23:39.732108 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4944 12:23:39.732709
4945 12:23:39.735344 [CATrainingPosCal] consider 2 rank data
4946 12:23:39.738923 u2DelayCellTimex100 = 270/100 ps
4947 12:23:39.741686 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4948 12:23:39.745299 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4949 12:23:39.748600 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4950 12:23:39.755259 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4951 12:23:39.758492 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4952 12:23:39.762340 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4953 12:23:39.762901
4954 12:23:39.765275 CA PerBit enable=1, Macro0, CA PI delay=34
4955 12:23:39.765850
4956 12:23:39.768531 [CBTSetCACLKResult] CA Dly = 34
4957 12:23:39.768989 CS Dly: 7 (0~39)
4958 12:23:39.769349
4959 12:23:39.771646 ----->DramcWriteLeveling(PI) begin...
4960 12:23:39.772111 ==
4961 12:23:39.774914 Dram Type= 6, Freq= 0, CH_0, rank 0
4962 12:23:39.781866 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4963 12:23:39.782430 ==
4964 12:23:39.784690 Write leveling (Byte 0): 29 => 29
4965 12:23:39.788580 Write leveling (Byte 1): 25 => 25
4966 12:23:39.791972 DramcWriteLeveling(PI) end<-----
4967 12:23:39.792567
4968 12:23:39.792933 ==
4969 12:23:39.794879 Dram Type= 6, Freq= 0, CH_0, rank 0
4970 12:23:39.798447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4971 12:23:39.799033 ==
4972 12:23:39.801265 [Gating] SW mode calibration
4973 12:23:39.808307 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4974 12:23:39.811553 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4975 12:23:39.818299 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4976 12:23:39.821313 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4977 12:23:39.824859 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4978 12:23:39.831228 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4979 12:23:39.834556 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4980 12:23:39.838089 0 10 20 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 1)
4981 12:23:39.844905 0 10 24 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4982 12:23:39.847610 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4983 12:23:39.851489 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4984 12:23:39.857919 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4985 12:23:39.860950 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4986 12:23:39.864591 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4987 12:23:39.871231 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4988 12:23:39.874505 0 11 20 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
4989 12:23:39.877682 0 11 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4990 12:23:39.884215 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4991 12:23:39.887849 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4992 12:23:39.891363 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4993 12:23:39.897905 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4994 12:23:39.900958 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4995 12:23:39.904079 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4996 12:23:39.910609 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4997 12:23:39.914657 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4998 12:23:39.917224 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4999 12:23:39.924449 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5000 12:23:39.927659 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5001 12:23:39.930840 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5002 12:23:39.937540 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5003 12:23:39.940666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5004 12:23:39.944760 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5005 12:23:39.950860 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5006 12:23:39.954185 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5007 12:23:39.957781 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5008 12:23:39.964282 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5009 12:23:39.967089 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5010 12:23:39.970657 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5011 12:23:39.976969 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5012 12:23:39.980270 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5013 12:23:39.983844 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5014 12:23:39.990714 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5015 12:23:39.991280 Total UI for P1: 0, mck2ui 16
5016 12:23:39.993957 best dqsien dly found for B0: ( 0, 14, 20)
5017 12:23:39.997069 Total UI for P1: 0, mck2ui 16
5018 12:23:40.000366 best dqsien dly found for B1: ( 0, 14, 22)
5019 12:23:40.006917 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5020 12:23:40.010382 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5021 12:23:40.010840
5022 12:23:40.013801 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5023 12:23:40.017092 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5024 12:23:40.020222 [Gating] SW calibration Done
5025 12:23:40.020682 ==
5026 12:23:40.023662 Dram Type= 6, Freq= 0, CH_0, rank 0
5027 12:23:40.027135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5028 12:23:40.027690 ==
5029 12:23:40.030290 RX Vref Scan: 0
5030 12:23:40.030840
5031 12:23:40.031198 RX Vref 0 -> 0, step: 1
5032 12:23:40.031536
5033 12:23:40.033501 RX Delay -80 -> 252, step: 8
5034 12:23:40.036759 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5035 12:23:40.043702 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5036 12:23:40.047075 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5037 12:23:40.050194 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5038 12:23:40.053288 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5039 12:23:40.056870 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5040 12:23:40.060171 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5041 12:23:40.063499 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5042 12:23:40.070125 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5043 12:23:40.073476 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5044 12:23:40.076829 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5045 12:23:40.080038 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5046 12:23:40.083640 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5047 12:23:40.089966 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5048 12:23:40.093463 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5049 12:23:40.096636 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5050 12:23:40.097186 ==
5051 12:23:40.100040 Dram Type= 6, Freq= 0, CH_0, rank 0
5052 12:23:40.102933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5053 12:23:40.103468 ==
5054 12:23:40.106250 DQS Delay:
5055 12:23:40.106796 DQS0 = 0, DQS1 = 0
5056 12:23:40.109649 DQM Delay:
5057 12:23:40.110257 DQM0 = 97, DQM1 = 86
5058 12:23:40.110645 DQ Delay:
5059 12:23:40.113152 DQ0 =91, DQ1 =99, DQ2 =95, DQ3 =91
5060 12:23:40.116251 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5061 12:23:40.119413 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5062 12:23:40.122921 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5063 12:23:40.123480
5064 12:23:40.123844
5065 12:23:40.126059 ==
5066 12:23:40.129712 Dram Type= 6, Freq= 0, CH_0, rank 0
5067 12:23:40.132679 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5068 12:23:40.133137 ==
5069 12:23:40.133536
5070 12:23:40.133872
5071 12:23:40.136000 TX Vref Scan disable
5072 12:23:40.136520 == TX Byte 0 ==
5073 12:23:40.143093 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5074 12:23:40.146456 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5075 12:23:40.147004 == TX Byte 1 ==
5076 12:23:40.153208 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5077 12:23:40.156416 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5078 12:23:40.156976 ==
5079 12:23:40.159358 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 12:23:40.162860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5081 12:23:40.163410 ==
5082 12:23:40.163773
5083 12:23:40.164103
5084 12:23:40.166145 TX Vref Scan disable
5085 12:23:40.169263 == TX Byte 0 ==
5086 12:23:40.173007 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5087 12:23:40.176220 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5088 12:23:40.179257 == TX Byte 1 ==
5089 12:23:40.182564 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5090 12:23:40.186021 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5091 12:23:40.186585
5092 12:23:40.189523 [DATLAT]
5093 12:23:40.190069 Freq=933, CH0 RK0
5094 12:23:40.190427
5095 12:23:40.192996 DATLAT Default: 0xd
5096 12:23:40.193544 0, 0xFFFF, sum = 0
5097 12:23:40.196473 1, 0xFFFF, sum = 0
5098 12:23:40.197026 2, 0xFFFF, sum = 0
5099 12:23:40.199381 3, 0xFFFF, sum = 0
5100 12:23:40.199933 4, 0xFFFF, sum = 0
5101 12:23:40.202658 5, 0xFFFF, sum = 0
5102 12:23:40.203216 6, 0xFFFF, sum = 0
5103 12:23:40.205948 7, 0xFFFF, sum = 0
5104 12:23:40.206507 8, 0xFFFF, sum = 0
5105 12:23:40.209212 9, 0xFFFF, sum = 0
5106 12:23:40.209671 10, 0x0, sum = 1
5107 12:23:40.212604 11, 0x0, sum = 2
5108 12:23:40.213167 12, 0x0, sum = 3
5109 12:23:40.215788 13, 0x0, sum = 4
5110 12:23:40.216385 best_step = 11
5111 12:23:40.216750
5112 12:23:40.217084 ==
5113 12:23:40.218942 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 12:23:40.225847 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5115 12:23:40.226388 ==
5116 12:23:40.226748 RX Vref Scan: 1
5117 12:23:40.227079
5118 12:23:40.229567 RX Vref 0 -> 0, step: 1
5119 12:23:40.230133
5120 12:23:40.232267 RX Delay -69 -> 252, step: 4
5121 12:23:40.232718
5122 12:23:40.235680 Set Vref, RX VrefLevel [Byte0]: 45
5123 12:23:40.239364 [Byte1]: 46
5124 12:23:40.239914
5125 12:23:40.242177 Final RX Vref Byte 0 = 45 to rank0
5126 12:23:40.245963 Final RX Vref Byte 1 = 46 to rank0
5127 12:23:40.248940 Final RX Vref Byte 0 = 45 to rank1
5128 12:23:40.252312 Final RX Vref Byte 1 = 46 to rank1==
5129 12:23:40.255788 Dram Type= 6, Freq= 0, CH_0, rank 0
5130 12:23:40.259135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5131 12:23:40.259717 ==
5132 12:23:40.262648 DQS Delay:
5133 12:23:40.263213 DQS0 = 0, DQS1 = 0
5134 12:23:40.263572 DQM Delay:
5135 12:23:40.265424 DQM0 = 97, DQM1 = 87
5136 12:23:40.265872 DQ Delay:
5137 12:23:40.268710 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5138 12:23:40.272364 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =106
5139 12:23:40.275542 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =80
5140 12:23:40.278639 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =96
5141 12:23:40.279090
5142 12:23:40.279444
5143 12:23:40.288677 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5144 12:23:40.292251 CH0 RK0: MR19=505, MR18=1C1C
5145 12:23:40.295409 CH0_RK0: MR19=0x505, MR18=0x1C1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5146 12:23:40.295963
5147 12:23:40.298869 ----->DramcWriteLeveling(PI) begin...
5148 12:23:40.302155 ==
5149 12:23:40.305671 Dram Type= 6, Freq= 0, CH_0, rank 1
5150 12:23:40.308419 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5151 12:23:40.308872 ==
5152 12:23:40.312482 Write leveling (Byte 0): 28 => 28
5153 12:23:40.315679 Write leveling (Byte 1): 25 => 25
5154 12:23:40.318832 DramcWriteLeveling(PI) end<-----
5155 12:23:40.319295
5156 12:23:40.319652 ==
5157 12:23:40.322027 Dram Type= 6, Freq= 0, CH_0, rank 1
5158 12:23:40.325407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5159 12:23:40.325864 ==
5160 12:23:40.328733 [Gating] SW mode calibration
5161 12:23:40.335301 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5162 12:23:40.342220 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5163 12:23:40.345161 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 12:23:40.348554 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 12:23:40.355336 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 12:23:40.358662 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 12:23:40.361450 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 12:23:40.365149 0 10 20 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
5169 12:23:40.371898 0 10 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5170 12:23:40.375221 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 12:23:40.378352 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 12:23:40.384934 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 12:23:40.388345 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 12:23:40.391465 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 12:23:40.398096 0 11 16 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
5176 12:23:40.401681 0 11 20 | B1->B0 | 2a2a 3232 | 1 0 | (0 0) (0 0)
5177 12:23:40.405155 0 11 24 | B1->B0 | 3c3c 4545 | 0 1 | (0 0) (0 0)
5178 12:23:40.411282 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 12:23:40.414893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 12:23:40.418231 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 12:23:40.424890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 12:23:40.428225 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 12:23:40.431791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 12:23:40.438080 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5185 12:23:40.441006 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 12:23:40.444870 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:23:40.451607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 12:23:40.455336 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:23:40.457938 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 12:23:40.464910 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 12:23:40.467889 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:23:40.471114 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 12:23:40.477825 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:23:40.481058 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:23:40.484559 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:23:40.491108 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:23:40.494699 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:23:40.497762 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:23:40.504132 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:23:40.507736 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5201 12:23:40.510758 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5202 12:23:40.517538 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 12:23:40.518104 Total UI for P1: 0, mck2ui 16
5204 12:23:40.524629 best dqsien dly found for B0: ( 0, 14, 22)
5205 12:23:40.525185 Total UI for P1: 0, mck2ui 16
5206 12:23:40.527694 best dqsien dly found for B1: ( 0, 14, 22)
5207 12:23:40.533747 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5208 12:23:40.537266 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5209 12:23:40.537824
5210 12:23:40.540585 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5211 12:23:40.544239 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5212 12:23:40.547384 [Gating] SW calibration Done
5213 12:23:40.547940 ==
5214 12:23:40.551043 Dram Type= 6, Freq= 0, CH_0, rank 1
5215 12:23:40.554095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5216 12:23:40.554652 ==
5217 12:23:40.557393 RX Vref Scan: 0
5218 12:23:40.557948
5219 12:23:40.558308 RX Vref 0 -> 0, step: 1
5220 12:23:40.558644
5221 12:23:40.560649 RX Delay -80 -> 252, step: 8
5222 12:23:40.564033 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5223 12:23:40.571115 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5224 12:23:40.573593 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5225 12:23:40.577218 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5226 12:23:40.580242 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5227 12:23:40.583805 iDelay=200, Bit 5, Center 87 (-16 ~ 191) 208
5228 12:23:40.587276 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5229 12:23:40.594203 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5230 12:23:40.596934 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5231 12:23:40.600625 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5232 12:23:40.603578 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5233 12:23:40.606973 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5234 12:23:40.613621 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5235 12:23:40.616738 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5236 12:23:40.620213 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5237 12:23:40.623655 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5238 12:23:40.624255 ==
5239 12:23:40.626857 Dram Type= 6, Freq= 0, CH_0, rank 1
5240 12:23:40.629928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5241 12:23:40.630387 ==
5242 12:23:40.633229 DQS Delay:
5243 12:23:40.633682 DQS0 = 0, DQS1 = 0
5244 12:23:40.636683 DQM Delay:
5245 12:23:40.637133 DQM0 = 95, DQM1 = 86
5246 12:23:40.639785 DQ Delay:
5247 12:23:40.640265 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5248 12:23:40.643282 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5249 12:23:40.646974 DQ8 =75, DQ9 =71, DQ10 =87, DQ11 =79
5250 12:23:40.649881 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5251 12:23:40.650336
5252 12:23:40.653446
5253 12:23:40.654005 ==
5254 12:23:40.656827 Dram Type= 6, Freq= 0, CH_0, rank 1
5255 12:23:40.660289 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5256 12:23:40.660749 ==
5257 12:23:40.661109
5258 12:23:40.661543
5259 12:23:40.663575 TX Vref Scan disable
5260 12:23:40.664129 == TX Byte 0 ==
5261 12:23:40.669840 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5262 12:23:40.673787 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5263 12:23:40.674356 == TX Byte 1 ==
5264 12:23:40.679757 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5265 12:23:40.683421 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5266 12:23:40.683975 ==
5267 12:23:40.686299 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 12:23:40.690074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5269 12:23:40.690633 ==
5270 12:23:40.690996
5271 12:23:40.691327
5272 12:23:40.693445 TX Vref Scan disable
5273 12:23:40.696764 == TX Byte 0 ==
5274 12:23:40.699706 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5275 12:23:40.703291 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5276 12:23:40.706753 == TX Byte 1 ==
5277 12:23:40.709493 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5278 12:23:40.712784 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5279 12:23:40.713240
5280 12:23:40.716280 [DATLAT]
5281 12:23:40.716731 Freq=933, CH0 RK1
5282 12:23:40.717092
5283 12:23:40.719507 DATLAT Default: 0xb
5284 12:23:40.719960 0, 0xFFFF, sum = 0
5285 12:23:40.722697 1, 0xFFFF, sum = 0
5286 12:23:40.723154 2, 0xFFFF, sum = 0
5287 12:23:40.726214 3, 0xFFFF, sum = 0
5288 12:23:40.726674 4, 0xFFFF, sum = 0
5289 12:23:40.729423 5, 0xFFFF, sum = 0
5290 12:23:40.729881 6, 0xFFFF, sum = 0
5291 12:23:40.733159 7, 0xFFFF, sum = 0
5292 12:23:40.733618 8, 0xFFFF, sum = 0
5293 12:23:40.735983 9, 0xFFFF, sum = 0
5294 12:23:40.736482 10, 0x0, sum = 1
5295 12:23:40.739684 11, 0x0, sum = 2
5296 12:23:40.740139 12, 0x0, sum = 3
5297 12:23:40.742665 13, 0x0, sum = 4
5298 12:23:40.743121 best_step = 11
5299 12:23:40.743471
5300 12:23:40.743800 ==
5301 12:23:40.745937 Dram Type= 6, Freq= 0, CH_0, rank 1
5302 12:23:40.752693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5303 12:23:40.753147 ==
5304 12:23:40.753501 RX Vref Scan: 0
5305 12:23:40.753831
5306 12:23:40.755977 RX Vref 0 -> 0, step: 1
5307 12:23:40.756461
5308 12:23:40.759665 RX Delay -69 -> 252, step: 4
5309 12:23:40.762616 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5310 12:23:40.766163 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5311 12:23:40.772579 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5312 12:23:40.776129 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5313 12:23:40.779433 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5314 12:23:40.782425 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5315 12:23:40.785958 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5316 12:23:40.792725 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5317 12:23:40.796002 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5318 12:23:40.799362 iDelay=199, Bit 9, Center 74 (-13 ~ 162) 176
5319 12:23:40.802614 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5320 12:23:40.806144 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5321 12:23:40.809150 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5322 12:23:40.816139 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5323 12:23:40.819116 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5324 12:23:40.822190 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5325 12:23:40.822645 ==
5326 12:23:40.825670 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 12:23:40.829017 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5328 12:23:40.829476 ==
5329 12:23:40.832141 DQS Delay:
5330 12:23:40.832637 DQS0 = 0, DQS1 = 0
5331 12:23:40.835775 DQM Delay:
5332 12:23:40.836388 DQM0 = 97, DQM1 = 86
5333 12:23:40.836755 DQ Delay:
5334 12:23:40.838997 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =92
5335 12:23:40.842309 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =106
5336 12:23:40.845360 DQ8 =74, DQ9 =74, DQ10 =88, DQ11 =78
5337 12:23:40.849202 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =94
5338 12:23:40.849755
5339 12:23:40.852334
5340 12:23:40.858961 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5341 12:23:40.862200 CH0 RK1: MR19=505, MR18=2929
5342 12:23:40.868680 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5343 12:23:40.872071 [RxdqsGatingPostProcess] freq 933
5344 12:23:40.875225 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5345 12:23:40.878874 Pre-setting of DQS Precalculation
5346 12:23:40.885471 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5347 12:23:40.886018 ==
5348 12:23:40.888440 Dram Type= 6, Freq= 0, CH_1, rank 0
5349 12:23:40.891975 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5350 12:23:40.892585 ==
5351 12:23:40.898789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5352 12:23:40.901607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5353 12:23:40.905811 [CA 0] Center 37 (7~68) winsize 62
5354 12:23:40.909479 [CA 1] Center 37 (7~68) winsize 62
5355 12:23:40.912576 [CA 2] Center 35 (5~65) winsize 61
5356 12:23:40.915746 [CA 3] Center 35 (5~65) winsize 61
5357 12:23:40.919228 [CA 4] Center 33 (3~64) winsize 62
5358 12:23:40.922877 [CA 5] Center 33 (3~64) winsize 62
5359 12:23:40.923333
5360 12:23:40.925772 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5361 12:23:40.926223
5362 12:23:40.929025 [CATrainingPosCal] consider 1 rank data
5363 12:23:40.932544 u2DelayCellTimex100 = 270/100 ps
5364 12:23:40.935637 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5365 12:23:40.942282 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5366 12:23:40.945423 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5367 12:23:40.948783 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5368 12:23:40.952603 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5369 12:23:40.955937 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5370 12:23:40.956500
5371 12:23:40.958989 CA PerBit enable=1, Macro0, CA PI delay=33
5372 12:23:40.959501
5373 12:23:40.962659 [CBTSetCACLKResult] CA Dly = 33
5374 12:23:40.963121 CS Dly: 5 (0~36)
5375 12:23:40.965828 ==
5376 12:23:40.968971 Dram Type= 6, Freq= 0, CH_1, rank 1
5377 12:23:40.972085 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5378 12:23:40.972577 ==
5379 12:23:40.978789 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5380 12:23:40.981997 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5381 12:23:40.986033 [CA 0] Center 37 (7~68) winsize 62
5382 12:23:40.989455 [CA 1] Center 37 (7~68) winsize 62
5383 12:23:40.992470 [CA 2] Center 34 (4~65) winsize 62
5384 12:23:40.995970 [CA 3] Center 34 (4~65) winsize 62
5385 12:23:40.999321 [CA 4] Center 33 (3~64) winsize 62
5386 12:23:41.002347 [CA 5] Center 33 (3~64) winsize 62
5387 12:23:41.002798
5388 12:23:41.006036 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5389 12:23:41.006586
5390 12:23:41.009361 [CATrainingPosCal] consider 2 rank data
5391 12:23:41.012244 u2DelayCellTimex100 = 270/100 ps
5392 12:23:41.016070 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5393 12:23:41.022323 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5394 12:23:41.026036 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5395 12:23:41.028928 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5396 12:23:41.032664 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5397 12:23:41.036041 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5398 12:23:41.036632
5399 12:23:41.039008 CA PerBit enable=1, Macro0, CA PI delay=33
5400 12:23:41.039558
5401 12:23:41.042691 [CBTSetCACLKResult] CA Dly = 33
5402 12:23:41.045936 CS Dly: 5 (0~37)
5403 12:23:41.046487
5404 12:23:41.048753 ----->DramcWriteLeveling(PI) begin...
5405 12:23:41.049208 ==
5406 12:23:41.052363 Dram Type= 6, Freq= 0, CH_1, rank 0
5407 12:23:41.055913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5408 12:23:41.056526 ==
5409 12:23:41.058800 Write leveling (Byte 0): 21 => 21
5410 12:23:41.062330 Write leveling (Byte 1): 22 => 22
5411 12:23:41.065542 DramcWriteLeveling(PI) end<-----
5412 12:23:41.066104
5413 12:23:41.066464 ==
5414 12:23:41.069011 Dram Type= 6, Freq= 0, CH_1, rank 0
5415 12:23:41.072658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5416 12:23:41.073206 ==
5417 12:23:41.075659 [Gating] SW mode calibration
5418 12:23:41.082210 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5419 12:23:41.088868 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5420 12:23:41.092277 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5421 12:23:41.096100 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5422 12:23:41.102007 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5423 12:23:41.105636 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 12:23:41.108894 0 10 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5425 12:23:41.115305 0 10 20 | B1->B0 | 3131 2525 | 0 0 | (0 0) (0 0)
5426 12:23:41.118826 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5427 12:23:41.121935 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5428 12:23:41.128726 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5429 12:23:41.132164 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5430 12:23:41.135065 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5431 12:23:41.141491 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 12:23:41.145174 0 11 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5433 12:23:41.148760 0 11 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
5434 12:23:41.154913 0 11 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5435 12:23:41.158226 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5436 12:23:41.161912 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5437 12:23:41.168344 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5438 12:23:41.172076 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 12:23:41.174927 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 12:23:41.181397 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5441 12:23:41.184602 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5442 12:23:41.188378 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 12:23:41.194786 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 12:23:41.197973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 12:23:41.201101 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 12:23:41.207978 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 12:23:41.211558 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 12:23:41.214640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 12:23:41.218022 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 12:23:41.225302 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 12:23:41.227607 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 12:23:41.231066 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 12:23:41.238153 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 12:23:41.240946 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 12:23:41.244297 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 12:23:41.251406 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5457 12:23:41.254190 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5458 12:23:41.257476 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5459 12:23:41.260880 Total UI for P1: 0, mck2ui 16
5460 12:23:41.264312 best dqsien dly found for B0: ( 0, 14, 18)
5461 12:23:41.267775 Total UI for P1: 0, mck2ui 16
5462 12:23:41.271163 best dqsien dly found for B1: ( 0, 14, 20)
5463 12:23:41.274425 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5464 12:23:41.280775 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5465 12:23:41.281235
5466 12:23:41.284048 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5467 12:23:41.287214 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5468 12:23:41.291110 [Gating] SW calibration Done
5469 12:23:41.291674 ==
5470 12:23:41.294119 Dram Type= 6, Freq= 0, CH_1, rank 0
5471 12:23:41.297448 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5472 12:23:41.298001 ==
5473 12:23:41.301161 RX Vref Scan: 0
5474 12:23:41.301709
5475 12:23:41.302070 RX Vref 0 -> 0, step: 1
5476 12:23:41.302405
5477 12:23:41.304020 RX Delay -80 -> 252, step: 8
5478 12:23:41.307288 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5479 12:23:41.311139 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5480 12:23:41.317276 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5481 12:23:41.321001 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5482 12:23:41.323575 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5483 12:23:41.327023 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5484 12:23:41.330873 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5485 12:23:41.333943 iDelay=208, Bit 7, Center 99 (0 ~ 199) 200
5486 12:23:41.340817 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5487 12:23:41.343849 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5488 12:23:41.347408 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5489 12:23:41.350384 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5490 12:23:41.353676 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5491 12:23:41.357373 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5492 12:23:41.363953 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5493 12:23:41.367291 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5494 12:23:41.367839 ==
5495 12:23:41.370283 Dram Type= 6, Freq= 0, CH_1, rank 0
5496 12:23:41.373519 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5497 12:23:41.374074 ==
5498 12:23:41.376610 DQS Delay:
5499 12:23:41.377060 DQS0 = 0, DQS1 = 0
5500 12:23:41.377578 DQM Delay:
5501 12:23:41.380159 DQM0 = 96, DQM1 = 88
5502 12:23:41.380651 DQ Delay:
5503 12:23:41.383359 DQ0 =99, DQ1 =87, DQ2 =87, DQ3 =95
5504 12:23:41.386581 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =99
5505 12:23:41.390112 DQ8 =71, DQ9 =75, DQ10 =95, DQ11 =79
5506 12:23:41.393560 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5507 12:23:41.394108
5508 12:23:41.394465
5509 12:23:41.394793 ==
5510 12:23:41.396722 Dram Type= 6, Freq= 0, CH_1, rank 0
5511 12:23:41.403541 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5512 12:23:41.404096 ==
5513 12:23:41.404520
5514 12:23:41.404856
5515 12:23:41.405174 TX Vref Scan disable
5516 12:23:41.407203 == TX Byte 0 ==
5517 12:23:41.409850 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5518 12:23:41.416831 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5519 12:23:41.417281 == TX Byte 1 ==
5520 12:23:41.420395 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5521 12:23:41.423497 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5522 12:23:41.426681 ==
5523 12:23:41.430223 Dram Type= 6, Freq= 0, CH_1, rank 0
5524 12:23:41.433941 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5525 12:23:41.434491 ==
5526 12:23:41.434848
5527 12:23:41.435177
5528 12:23:41.436624 TX Vref Scan disable
5529 12:23:41.437075 == TX Byte 0 ==
5530 12:23:41.443266 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5531 12:23:41.447116 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5532 12:23:41.447676 == TX Byte 1 ==
5533 12:23:41.453198 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5534 12:23:41.456388 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5535 12:23:41.456841
5536 12:23:41.457195 [DATLAT]
5537 12:23:41.460292 Freq=933, CH1 RK0
5538 12:23:41.460875
5539 12:23:41.461248 DATLAT Default: 0xd
5540 12:23:41.463515 0, 0xFFFF, sum = 0
5541 12:23:41.463976 1, 0xFFFF, sum = 0
5542 12:23:41.466649 2, 0xFFFF, sum = 0
5543 12:23:41.467217 3, 0xFFFF, sum = 0
5544 12:23:41.470033 4, 0xFFFF, sum = 0
5545 12:23:41.473051 5, 0xFFFF, sum = 0
5546 12:23:41.473517 6, 0xFFFF, sum = 0
5547 12:23:41.476632 7, 0xFFFF, sum = 0
5548 12:23:41.477199 8, 0xFFFF, sum = 0
5549 12:23:41.479775 9, 0xFFFF, sum = 0
5550 12:23:41.480284 10, 0x0, sum = 1
5551 12:23:41.483585 11, 0x0, sum = 2
5552 12:23:41.484154 12, 0x0, sum = 3
5553 12:23:41.484575 13, 0x0, sum = 4
5554 12:23:41.486395 best_step = 11
5555 12:23:41.486865
5556 12:23:41.487224 ==
5557 12:23:41.489749 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 12:23:41.493180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5559 12:23:41.493753 ==
5560 12:23:41.496519 RX Vref Scan: 1
5561 12:23:41.497075
5562 12:23:41.500262 RX Vref 0 -> 0, step: 1
5563 12:23:41.500830
5564 12:23:41.501191 RX Delay -69 -> 252, step: 4
5565 12:23:41.501529
5566 12:23:41.502880 Set Vref, RX VrefLevel [Byte0]: 52
5567 12:23:41.506371 [Byte1]: 49
5568 12:23:41.510808
5569 12:23:41.511361 Final RX Vref Byte 0 = 52 to rank0
5570 12:23:41.513938 Final RX Vref Byte 1 = 49 to rank0
5571 12:23:41.517579 Final RX Vref Byte 0 = 52 to rank1
5572 12:23:41.521036 Final RX Vref Byte 1 = 49 to rank1==
5573 12:23:41.524648 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 12:23:41.531036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5575 12:23:41.531626 ==
5576 12:23:41.531993 DQS Delay:
5577 12:23:41.532376 DQS0 = 0, DQS1 = 0
5578 12:23:41.534405 DQM Delay:
5579 12:23:41.534959 DQM0 = 95, DQM1 = 90
5580 12:23:41.537451 DQ Delay:
5581 12:23:41.540638 DQ0 =100, DQ1 =90, DQ2 =88, DQ3 =92
5582 12:23:41.544041 DQ4 =94, DQ5 =106, DQ6 =102, DQ7 =94
5583 12:23:41.547754 DQ8 =72, DQ9 =80, DQ10 =92, DQ11 =82
5584 12:23:41.551131 DQ12 =98, DQ13 =102, DQ14 =98, DQ15 =100
5585 12:23:41.551685
5586 12:23:41.552044
5587 12:23:41.557787 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5588 12:23:41.560778 CH1 RK0: MR19=505, MR18=3838
5589 12:23:41.567533 CH1_RK0: MR19=0x505, MR18=0x3838, DQSOSC=404, MR23=63, INC=66, DEC=44
5590 12:23:41.568088
5591 12:23:41.571003 ----->DramcWriteLeveling(PI) begin...
5592 12:23:41.571586 ==
5593 12:23:41.574182 Dram Type= 6, Freq= 0, CH_1, rank 1
5594 12:23:41.577623 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5595 12:23:41.578199 ==
5596 12:23:41.580756 Write leveling (Byte 0): 23 => 23
5597 12:23:41.584374 Write leveling (Byte 1): 23 => 23
5598 12:23:41.587511 DramcWriteLeveling(PI) end<-----
5599 12:23:41.588065
5600 12:23:41.588471 ==
5601 12:23:41.591021 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 12:23:41.594714 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5603 12:23:41.595176 ==
5604 12:23:41.597547 [Gating] SW mode calibration
5605 12:23:41.604226 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5606 12:23:41.610755 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5607 12:23:41.614036 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 12:23:41.620476 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 12:23:41.623909 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 12:23:41.627937 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5611 12:23:41.633926 0 10 16 | B1->B0 | 3333 2626 | 0 0 | (0 0) (1 0)
5612 12:23:41.637200 0 10 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)
5613 12:23:41.640225 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 12:23:41.646978 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 12:23:41.650223 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 12:23:41.653213 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 12:23:41.660123 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 12:23:41.663848 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 12:23:41.667044 0 11 16 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
5620 12:23:41.673179 0 11 20 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)
5621 12:23:41.676669 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 12:23:41.679783 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 12:23:41.686431 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 12:23:41.690108 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 12:23:41.693517 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 12:23:41.699881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5627 12:23:41.703065 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5628 12:23:41.706663 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5629 12:23:41.712917 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 12:23:41.716565 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 12:23:41.720430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 12:23:41.726548 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 12:23:41.729402 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:23:41.732542 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 12:23:41.736416 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:23:41.742952 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:23:41.746321 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:23:41.749525 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:23:41.756033 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:23:41.759023 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:23:41.762707 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:23:41.769189 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:23:41.772901 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5644 12:23:41.775909 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5645 12:23:41.782573 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 12:23:41.785571 Total UI for P1: 0, mck2ui 16
5647 12:23:41.789126 best dqsien dly found for B0: ( 0, 14, 18)
5648 12:23:41.792581 Total UI for P1: 0, mck2ui 16
5649 12:23:41.795836 best dqsien dly found for B1: ( 0, 14, 20)
5650 12:23:41.799127 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5651 12:23:41.802278 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5652 12:23:41.802837
5653 12:23:41.805596 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5654 12:23:41.809079 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5655 12:23:41.812509 [Gating] SW calibration Done
5656 12:23:41.813110 ==
5657 12:23:41.815581 Dram Type= 6, Freq= 0, CH_1, rank 1
5658 12:23:41.818965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5659 12:23:41.819526 ==
5660 12:23:41.822479 RX Vref Scan: 0
5661 12:23:41.823106
5662 12:23:41.825056 RX Vref 0 -> 0, step: 1
5663 12:23:41.825550
5664 12:23:41.825914 RX Delay -80 -> 252, step: 8
5665 12:23:41.831794 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5666 12:23:41.835106 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5667 12:23:41.839064 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5668 12:23:41.842210 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5669 12:23:41.845035 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5670 12:23:41.848317 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5671 12:23:41.855256 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5672 12:23:41.858742 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5673 12:23:41.861842 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5674 12:23:41.865327 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5675 12:23:41.868449 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5676 12:23:41.875266 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5677 12:23:41.878233 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5678 12:23:41.881427 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5679 12:23:41.884666 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5680 12:23:41.887997 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5681 12:23:41.888499 ==
5682 12:23:41.891670 Dram Type= 6, Freq= 0, CH_1, rank 1
5683 12:23:41.898140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5684 12:23:41.898698 ==
5685 12:23:41.899229 DQS Delay:
5686 12:23:41.901559 DQS0 = 0, DQS1 = 0
5687 12:23:41.902112 DQM Delay:
5688 12:23:41.902480 DQM0 = 95, DQM1 = 89
5689 12:23:41.904624 DQ Delay:
5690 12:23:41.908165 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5691 12:23:41.911390 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5692 12:23:41.914581 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5693 12:23:41.918007 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =95
5694 12:23:41.918558
5695 12:23:41.918922
5696 12:23:41.919256 ==
5697 12:23:41.920870 Dram Type= 6, Freq= 0, CH_1, rank 1
5698 12:23:41.924578 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5699 12:23:41.925159 ==
5700 12:23:41.925555
5701 12:23:41.925893
5702 12:23:41.927802 TX Vref Scan disable
5703 12:23:41.930837 == TX Byte 0 ==
5704 12:23:41.934631 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5705 12:23:41.937590 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5706 12:23:41.940880 == TX Byte 1 ==
5707 12:23:41.944361 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5708 12:23:41.947839 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5709 12:23:41.948344 ==
5710 12:23:41.950910 Dram Type= 6, Freq= 0, CH_1, rank 1
5711 12:23:41.954175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5712 12:23:41.957444 ==
5713 12:23:41.957997
5714 12:23:41.958357
5715 12:23:41.958687 TX Vref Scan disable
5716 12:23:41.961017 == TX Byte 0 ==
5717 12:23:41.964642 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5718 12:23:41.971044 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5719 12:23:41.971591 == TX Byte 1 ==
5720 12:23:41.974320 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5721 12:23:41.981295 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5722 12:23:41.981757
5723 12:23:41.982114 [DATLAT]
5724 12:23:41.982449 Freq=933, CH1 RK1
5725 12:23:41.982772
5726 12:23:41.984075 DATLAT Default: 0xb
5727 12:23:41.984577 0, 0xFFFF, sum = 0
5728 12:23:41.987542 1, 0xFFFF, sum = 0
5729 12:23:41.988020 2, 0xFFFF, sum = 0
5730 12:23:41.991002 3, 0xFFFF, sum = 0
5731 12:23:41.994148 4, 0xFFFF, sum = 0
5732 12:23:41.994611 5, 0xFFFF, sum = 0
5733 12:23:41.997889 6, 0xFFFF, sum = 0
5734 12:23:41.998455 7, 0xFFFF, sum = 0
5735 12:23:42.000939 8, 0xFFFF, sum = 0
5736 12:23:42.001405 9, 0xFFFF, sum = 0
5737 12:23:42.004418 10, 0x0, sum = 1
5738 12:23:42.004982 11, 0x0, sum = 2
5739 12:23:42.008022 12, 0x0, sum = 3
5740 12:23:42.008648 13, 0x0, sum = 4
5741 12:23:42.009025 best_step = 11
5742 12:23:42.009364
5743 12:23:42.010770 ==
5744 12:23:42.014062 Dram Type= 6, Freq= 0, CH_1, rank 1
5745 12:23:42.017393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5746 12:23:42.017955 ==
5747 12:23:42.018316 RX Vref Scan: 0
5748 12:23:42.018649
5749 12:23:42.020456 RX Vref 0 -> 0, step: 1
5750 12:23:42.020910
5751 12:23:42.024603 RX Delay -61 -> 252, step: 4
5752 12:23:42.027454 iDelay=203, Bit 0, Center 98 (11 ~ 186) 176
5753 12:23:42.034380 iDelay=203, Bit 1, Center 92 (3 ~ 182) 180
5754 12:23:42.037421 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5755 12:23:42.040622 iDelay=203, Bit 3, Center 96 (7 ~ 186) 180
5756 12:23:42.044319 iDelay=203, Bit 4, Center 98 (7 ~ 190) 184
5757 12:23:42.047542 iDelay=203, Bit 5, Center 110 (19 ~ 202) 184
5758 12:23:42.050757 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5759 12:23:42.057779 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5760 12:23:42.060582 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5761 12:23:42.064225 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5762 12:23:42.067167 iDelay=203, Bit 10, Center 88 (-1 ~ 178) 180
5763 12:23:42.070842 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5764 12:23:42.077377 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5765 12:23:42.080696 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5766 12:23:42.083964 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5767 12:23:42.087358 iDelay=203, Bit 15, Center 98 (11 ~ 186) 176
5768 12:23:42.087909 ==
5769 12:23:42.090507 Dram Type= 6, Freq= 0, CH_1, rank 1
5770 12:23:42.093954 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5771 12:23:42.096900 ==
5772 12:23:42.097352 DQS Delay:
5773 12:23:42.097705 DQS0 = 0, DQS1 = 0
5774 12:23:42.100469 DQM Delay:
5775 12:23:42.100917 DQM0 = 98, DQM1 = 89
5776 12:23:42.103699 DQ Delay:
5777 12:23:42.104290 DQ0 =98, DQ1 =92, DQ2 =90, DQ3 =96
5778 12:23:42.107597 DQ4 =98, DQ5 =110, DQ6 =106, DQ7 =96
5779 12:23:42.110430 DQ8 =76, DQ9 =78, DQ10 =88, DQ11 =84
5780 12:23:42.113489 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5781 12:23:42.117159
5782 12:23:42.117715
5783 12:23:42.123508 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5784 12:23:42.126797 CH1 RK1: MR19=505, MR18=2929
5785 12:23:42.134237 CH1_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5786 12:23:42.136933 [RxdqsGatingPostProcess] freq 933
5787 12:23:42.140294 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5788 12:23:42.143602 Pre-setting of DQS Precalculation
5789 12:23:42.149971 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5790 12:23:42.156578 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5791 12:23:42.163511 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5792 12:23:42.164061
5793 12:23:42.164454
5794 12:23:42.166496 [Calibration Summary] 1866 Mbps
5795 12:23:42.166945 CH 0, Rank 0
5796 12:23:42.170142 SW Impedance : PASS
5797 12:23:42.173128 DUTY Scan : NO K
5798 12:23:42.173578 ZQ Calibration : PASS
5799 12:23:42.176872 Jitter Meter : NO K
5800 12:23:42.179806 CBT Training : PASS
5801 12:23:42.180291 Write leveling : PASS
5802 12:23:42.183105 RX DQS gating : PASS
5803 12:23:42.186813 RX DQ/DQS(RDDQC) : PASS
5804 12:23:42.187379 TX DQ/DQS : PASS
5805 12:23:42.189577 RX DATLAT : PASS
5806 12:23:42.190025 RX DQ/DQS(Engine): PASS
5807 12:23:42.193122 TX OE : NO K
5808 12:23:42.193668 All Pass.
5809 12:23:42.194030
5810 12:23:42.197002 CH 0, Rank 1
5811 12:23:42.197546 SW Impedance : PASS
5812 12:23:42.199677 DUTY Scan : NO K
5813 12:23:42.203429 ZQ Calibration : PASS
5814 12:23:42.203980 Jitter Meter : NO K
5815 12:23:42.206462 CBT Training : PASS
5816 12:23:42.209878 Write leveling : PASS
5817 12:23:42.210426 RX DQS gating : PASS
5818 12:23:42.212958 RX DQ/DQS(RDDQC) : PASS
5819 12:23:42.216355 TX DQ/DQS : PASS
5820 12:23:42.216937 RX DATLAT : PASS
5821 12:23:42.219682 RX DQ/DQS(Engine): PASS
5822 12:23:42.223110 TX OE : NO K
5823 12:23:42.223667 All Pass.
5824 12:23:42.224030
5825 12:23:42.224438 CH 1, Rank 0
5826 12:23:42.226313 SW Impedance : PASS
5827 12:23:42.229461 DUTY Scan : NO K
5828 12:23:42.230020 ZQ Calibration : PASS
5829 12:23:42.232777 Jitter Meter : NO K
5830 12:23:42.236525 CBT Training : PASS
5831 12:23:42.236981 Write leveling : PASS
5832 12:23:42.239559 RX DQS gating : PASS
5833 12:23:42.243179 RX DQ/DQS(RDDQC) : PASS
5834 12:23:42.243736 TX DQ/DQS : PASS
5835 12:23:42.246560 RX DATLAT : PASS
5836 12:23:42.249190 RX DQ/DQS(Engine): PASS
5837 12:23:42.249665 TX OE : NO K
5838 12:23:42.250030 All Pass.
5839 12:23:42.250369
5840 12:23:42.252592 CH 1, Rank 1
5841 12:23:42.256313 SW Impedance : PASS
5842 12:23:42.256881 DUTY Scan : NO K
5843 12:23:42.259359 ZQ Calibration : PASS
5844 12:23:42.259912 Jitter Meter : NO K
5845 12:23:42.262871 CBT Training : PASS
5846 12:23:42.266000 Write leveling : PASS
5847 12:23:42.266458 RX DQS gating : PASS
5848 12:23:42.269840 RX DQ/DQS(RDDQC) : PASS
5849 12:23:42.272650 TX DQ/DQS : PASS
5850 12:23:42.273216 RX DATLAT : PASS
5851 12:23:42.276024 RX DQ/DQS(Engine): PASS
5852 12:23:42.279238 TX OE : NO K
5853 12:23:42.279766 All Pass.
5854 12:23:42.280142
5855 12:23:42.282172 DramC Write-DBI off
5856 12:23:42.282627 PER_BANK_REFRESH: Hybrid Mode
5857 12:23:42.285511 TX_TRACKING: ON
5858 12:23:42.295571 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5859 12:23:42.299123 [FAST_K] Save calibration result to emmc
5860 12:23:42.301958 dramc_set_vcore_voltage set vcore to 650000
5861 12:23:42.302419 Read voltage for 400, 6
5862 12:23:42.305361 Vio18 = 0
5863 12:23:42.305817 Vcore = 650000
5864 12:23:42.306173 Vdram = 0
5865 12:23:42.308903 Vddq = 0
5866 12:23:42.309359 Vmddr = 0
5867 12:23:42.311870 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5868 12:23:42.318840 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5869 12:23:42.322319 MEM_TYPE=3, freq_sel=20
5870 12:23:42.325403 sv_algorithm_assistance_LP4_800
5871 12:23:42.328857 ============ PULL DRAM RESETB DOWN ============
5872 12:23:42.332288 ========== PULL DRAM RESETB DOWN end =========
5873 12:23:42.338833 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5874 12:23:42.342019 ===================================
5875 12:23:42.342771 LPDDR4 DRAM CONFIGURATION
5876 12:23:42.345284 ===================================
5877 12:23:42.348921 EX_ROW_EN[0] = 0x0
5878 12:23:42.349380 EX_ROW_EN[1] = 0x0
5879 12:23:42.352299 LP4Y_EN = 0x0
5880 12:23:42.352757 WORK_FSP = 0x0
5881 12:23:42.355303 WL = 0x2
5882 12:23:42.358693 RL = 0x2
5883 12:23:42.359248 BL = 0x2
5884 12:23:42.362470 RPST = 0x0
5885 12:23:42.363023 RD_PRE = 0x0
5886 12:23:42.364964 WR_PRE = 0x1
5887 12:23:42.365420 WR_PST = 0x0
5888 12:23:42.368659 DBI_WR = 0x0
5889 12:23:42.369115 DBI_RD = 0x0
5890 12:23:42.372105 OTF = 0x1
5891 12:23:42.375208 ===================================
5892 12:23:42.378356 ===================================
5893 12:23:42.378814 ANA top config
5894 12:23:42.381630 ===================================
5895 12:23:42.385002 DLL_ASYNC_EN = 0
5896 12:23:42.388321 ALL_SLAVE_EN = 1
5897 12:23:42.388791 NEW_RANK_MODE = 1
5898 12:23:42.391811 DLL_IDLE_MODE = 1
5899 12:23:42.395573 LP45_APHY_COMB_EN = 1
5900 12:23:42.398847 TX_ODT_DIS = 1
5901 12:23:42.399399 NEW_8X_MODE = 1
5902 12:23:42.401866 ===================================
5903 12:23:42.404831 ===================================
5904 12:23:42.408554 data_rate = 800
5905 12:23:42.412002 CKR = 1
5906 12:23:42.414736 DQ_P2S_RATIO = 4
5907 12:23:42.418697 ===================================
5908 12:23:42.421855 CA_P2S_RATIO = 4
5909 12:23:42.424961 DQ_CA_OPEN = 0
5910 12:23:42.428494 DQ_SEMI_OPEN = 1
5911 12:23:42.429081 CA_SEMI_OPEN = 1
5912 12:23:42.431484 CA_FULL_RATE = 0
5913 12:23:42.435280 DQ_CKDIV4_EN = 0
5914 12:23:42.438553 CA_CKDIV4_EN = 1
5915 12:23:42.441622 CA_PREDIV_EN = 0
5916 12:23:42.444616 PH8_DLY = 0
5917 12:23:42.445075 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5918 12:23:42.447910 DQ_AAMCK_DIV = 0
5919 12:23:42.451289 CA_AAMCK_DIV = 0
5920 12:23:42.454808 CA_ADMCK_DIV = 4
5921 12:23:42.458046 DQ_TRACK_CA_EN = 0
5922 12:23:42.461419 CA_PICK = 800
5923 12:23:42.461963 CA_MCKIO = 400
5924 12:23:42.464873 MCKIO_SEMI = 400
5925 12:23:42.468138 PLL_FREQ = 3016
5926 12:23:42.471339 DQ_UI_PI_RATIO = 32
5927 12:23:42.474889 CA_UI_PI_RATIO = 32
5928 12:23:42.477968 ===================================
5929 12:23:42.481048 ===================================
5930 12:23:42.484692 memory_type:LPDDR4
5931 12:23:42.485147 GP_NUM : 10
5932 12:23:42.488260 SRAM_EN : 1
5933 12:23:42.491480 MD32_EN : 0
5934 12:23:42.494722 ===================================
5935 12:23:42.495274 [ANA_INIT] >>>>>>>>>>>>>>
5936 12:23:42.497956 <<<<<< [CONFIGURE PHASE]: ANA_TX
5937 12:23:42.501115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5938 12:23:42.504454 ===================================
5939 12:23:42.507876 data_rate = 800,PCW = 0X7400
5940 12:23:42.511181 ===================================
5941 12:23:42.514401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5942 12:23:42.521054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5943 12:23:42.531125 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5944 12:23:42.534076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5945 12:23:42.540673 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5946 12:23:42.544430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5947 12:23:42.544981 [ANA_INIT] flow start
5948 12:23:42.547835 [ANA_INIT] PLL >>>>>>>>
5949 12:23:42.551566 [ANA_INIT] PLL <<<<<<<<
5950 12:23:42.552113 [ANA_INIT] MIDPI >>>>>>>>
5951 12:23:42.554052 [ANA_INIT] MIDPI <<<<<<<<
5952 12:23:42.557589 [ANA_INIT] DLL >>>>>>>>
5953 12:23:42.558329 [ANA_INIT] flow end
5954 12:23:42.560756 ============ LP4 DIFF to SE enter ============
5955 12:23:42.567431 ============ LP4 DIFF to SE exit ============
5956 12:23:42.567970 [ANA_INIT] <<<<<<<<<<<<<
5957 12:23:42.570340 [Flow] Enable top DCM control >>>>>
5958 12:23:42.574290 [Flow] Enable top DCM control <<<<<
5959 12:23:42.577712 Enable DLL master slave shuffle
5960 12:23:42.584077 ==============================================================
5961 12:23:42.584681 Gating Mode config
5962 12:23:42.590693 ==============================================================
5963 12:23:42.593854 Config description:
5964 12:23:42.603786 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5965 12:23:42.610738 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5966 12:23:42.613932 SELPH_MODE 0: By rank 1: By Phase
5967 12:23:42.620141 ==============================================================
5968 12:23:42.623511 GAT_TRACK_EN = 0
5969 12:23:42.626840 RX_GATING_MODE = 2
5970 12:23:42.627300 RX_GATING_TRACK_MODE = 2
5971 12:23:42.630400 SELPH_MODE = 1
5972 12:23:42.633654 PICG_EARLY_EN = 1
5973 12:23:42.637055 VALID_LAT_VALUE = 1
5974 12:23:42.643619 ==============================================================
5975 12:23:42.646896 Enter into Gating configuration >>>>
5976 12:23:42.650278 Exit from Gating configuration <<<<
5977 12:23:42.653344 Enter into DVFS_PRE_config >>>>>
5978 12:23:42.664020 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5979 12:23:42.667083 Exit from DVFS_PRE_config <<<<<
5980 12:23:42.670283 Enter into PICG configuration >>>>
5981 12:23:42.673491 Exit from PICG configuration <<<<
5982 12:23:42.677035 [RX_INPUT] configuration >>>>>
5983 12:23:42.679937 [RX_INPUT] configuration <<<<<
5984 12:23:42.683550 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5985 12:23:42.689906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5986 12:23:42.696910 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5987 12:23:42.703559 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5988 12:23:42.706942 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5989 12:23:42.713479 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5990 12:23:42.716941 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5991 12:23:42.723543 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5992 12:23:42.726875 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5993 12:23:42.730256 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5994 12:23:42.733355 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5995 12:23:42.739934 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5996 12:23:42.743510 ===================================
5997 12:23:42.744071 LPDDR4 DRAM CONFIGURATION
5998 12:23:42.746621 ===================================
5999 12:23:42.750099 EX_ROW_EN[0] = 0x0
6000 12:23:42.753000 EX_ROW_EN[1] = 0x0
6001 12:23:42.753458 LP4Y_EN = 0x0
6002 12:23:42.756542 WORK_FSP = 0x0
6003 12:23:42.757104 WL = 0x2
6004 12:23:42.760027 RL = 0x2
6005 12:23:42.760627 BL = 0x2
6006 12:23:42.763208 RPST = 0x0
6007 12:23:42.763767 RD_PRE = 0x0
6008 12:23:42.766462 WR_PRE = 0x1
6009 12:23:42.767021 WR_PST = 0x0
6010 12:23:42.769747 DBI_WR = 0x0
6011 12:23:42.770364 DBI_RD = 0x0
6012 12:23:42.773028 OTF = 0x1
6013 12:23:42.776305 ===================================
6014 12:23:42.779562 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6015 12:23:42.782813 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6016 12:23:42.789490 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6017 12:23:42.793157 ===================================
6018 12:23:42.793615 LPDDR4 DRAM CONFIGURATION
6019 12:23:42.796543 ===================================
6020 12:23:42.799522 EX_ROW_EN[0] = 0x10
6021 12:23:42.802971 EX_ROW_EN[1] = 0x0
6022 12:23:42.803528 LP4Y_EN = 0x0
6023 12:23:42.806135 WORK_FSP = 0x0
6024 12:23:42.806593 WL = 0x2
6025 12:23:42.809752 RL = 0x2
6026 12:23:42.810304 BL = 0x2
6027 12:23:42.813067 RPST = 0x0
6028 12:23:42.813626 RD_PRE = 0x0
6029 12:23:42.815798 WR_PRE = 0x1
6030 12:23:42.816318 WR_PST = 0x0
6031 12:23:42.819703 DBI_WR = 0x0
6032 12:23:42.820302 DBI_RD = 0x0
6033 12:23:42.822971 OTF = 0x1
6034 12:23:42.826468 ===================================
6035 12:23:42.832656 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6036 12:23:42.835987 nWR fixed to 30
6037 12:23:42.839304 [ModeRegInit_LP4] CH0 RK0
6038 12:23:42.839882 [ModeRegInit_LP4] CH0 RK1
6039 12:23:42.842865 [ModeRegInit_LP4] CH1 RK0
6040 12:23:42.845969 [ModeRegInit_LP4] CH1 RK1
6041 12:23:42.846426 match AC timing 18
6042 12:23:42.852867 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6043 12:23:42.856132 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6044 12:23:42.859634 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6045 12:23:42.866334 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6046 12:23:42.869508 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6047 12:23:42.870066 ==
6048 12:23:42.872869 Dram Type= 6, Freq= 0, CH_0, rank 0
6049 12:23:42.876061 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6050 12:23:42.876660 ==
6051 12:23:42.882334 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6052 12:23:42.888963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6053 12:23:42.892498 [CA 0] Center 36 (8~64) winsize 57
6054 12:23:42.893072 [CA 1] Center 36 (8~64) winsize 57
6055 12:23:42.896116 [CA 2] Center 36 (8~64) winsize 57
6056 12:23:42.899153 [CA 3] Center 36 (8~64) winsize 57
6057 12:23:42.902233 [CA 4] Center 36 (8~64) winsize 57
6058 12:23:42.905560 [CA 5] Center 36 (8~64) winsize 57
6059 12:23:42.906016
6060 12:23:42.908819 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6061 12:23:42.909374
6062 12:23:42.915523 [CATrainingPosCal] consider 1 rank data
6063 12:23:42.916076 u2DelayCellTimex100 = 270/100 ps
6064 12:23:42.922048 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6065 12:23:42.925597 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6066 12:23:42.929006 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6067 12:23:42.932400 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6068 12:23:42.935098 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6069 12:23:42.938982 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6070 12:23:42.939532
6071 12:23:42.941918 CA PerBit enable=1, Macro0, CA PI delay=36
6072 12:23:42.942467
6073 12:23:42.945012 [CBTSetCACLKResult] CA Dly = 36
6074 12:23:42.948829 CS Dly: 1 (0~32)
6075 12:23:42.949377 ==
6076 12:23:42.951968 Dram Type= 6, Freq= 0, CH_0, rank 1
6077 12:23:42.955259 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6078 12:23:42.955819 ==
6079 12:23:42.961993 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6080 12:23:42.964853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6081 12:23:42.968636 [CA 0] Center 36 (8~64) winsize 57
6082 12:23:42.972017 [CA 1] Center 36 (8~64) winsize 57
6083 12:23:42.974948 [CA 2] Center 36 (8~64) winsize 57
6084 12:23:42.978281 [CA 3] Center 36 (8~64) winsize 57
6085 12:23:42.981276 [CA 4] Center 36 (8~64) winsize 57
6086 12:23:42.984641 [CA 5] Center 36 (8~64) winsize 57
6087 12:23:42.985145
6088 12:23:42.988133 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6089 12:23:42.988746
6090 12:23:42.991460 [CATrainingPosCal] consider 2 rank data
6091 12:23:42.995106 u2DelayCellTimex100 = 270/100 ps
6092 12:23:42.998175 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6093 12:23:43.001411 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6094 12:23:43.008108 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6095 12:23:43.011256 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6096 12:23:43.014466 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6097 12:23:43.018180 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6098 12:23:43.018743
6099 12:23:43.021212 CA PerBit enable=1, Macro0, CA PI delay=36
6100 12:23:43.021670
6101 12:23:43.024263 [CBTSetCACLKResult] CA Dly = 36
6102 12:23:43.024723 CS Dly: 1 (0~32)
6103 12:23:43.027753
6104 12:23:43.031068 ----->DramcWriteLeveling(PI) begin...
6105 12:23:43.031640 ==
6106 12:23:43.034281 Dram Type= 6, Freq= 0, CH_0, rank 0
6107 12:23:43.037651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6108 12:23:43.038113 ==
6109 12:23:43.040758 Write leveling (Byte 0): 32 => 0
6110 12:23:43.044237 Write leveling (Byte 1): 32 => 0
6111 12:23:43.047508 DramcWriteLeveling(PI) end<-----
6112 12:23:43.048059
6113 12:23:43.048484 ==
6114 12:23:43.051047 Dram Type= 6, Freq= 0, CH_0, rank 0
6115 12:23:43.054374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6116 12:23:43.054930 ==
6117 12:23:43.057852 [Gating] SW mode calibration
6118 12:23:43.064286 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6119 12:23:43.070763 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6120 12:23:43.074139 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6121 12:23:43.077495 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6122 12:23:43.084100 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6123 12:23:43.087337 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6124 12:23:43.090511 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6125 12:23:43.097235 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6126 12:23:43.100620 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6127 12:23:43.103786 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6128 12:23:43.110517 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6129 12:23:43.111183 Total UI for P1: 0, mck2ui 16
6130 12:23:43.113568 best dqsien dly found for B0: ( 0, 10, 16)
6131 12:23:43.116714 Total UI for P1: 0, mck2ui 16
6132 12:23:43.120356 best dqsien dly found for B1: ( 0, 10, 24)
6133 12:23:43.126887 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6134 12:23:43.130184 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6135 12:23:43.130784
6136 12:23:43.133398 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6137 12:23:43.137212 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6138 12:23:43.139778 [Gating] SW calibration Done
6139 12:23:43.140264 ==
6140 12:23:43.143400 Dram Type= 6, Freq= 0, CH_0, rank 0
6141 12:23:43.146969 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6142 12:23:43.147521 ==
6143 12:23:43.150014 RX Vref Scan: 0
6144 12:23:43.150506
6145 12:23:43.150873 RX Vref 0 -> 0, step: 1
6146 12:23:43.151203
6147 12:23:43.153734 RX Delay -410 -> 252, step: 16
6148 12:23:43.160108 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6149 12:23:43.163641 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6150 12:23:43.166674 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6151 12:23:43.169784 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6152 12:23:43.176369 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6153 12:23:43.179821 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6154 12:23:43.182768 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6155 12:23:43.186143 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6156 12:23:43.193011 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6157 12:23:43.196376 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6158 12:23:43.200071 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6159 12:23:43.203214 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6160 12:23:43.209660 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6161 12:23:43.213160 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6162 12:23:43.216555 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6163 12:23:43.223035 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6164 12:23:43.223735 ==
6165 12:23:43.226202 Dram Type= 6, Freq= 0, CH_0, rank 0
6166 12:23:43.229802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6167 12:23:43.230361 ==
6168 12:23:43.230727 DQS Delay:
6169 12:23:43.232623 DQS0 = 51, DQS1 = 59
6170 12:23:43.233077 DQM Delay:
6171 12:23:43.236019 DQM0 = 12, DQM1 = 16
6172 12:23:43.236511 DQ Delay:
6173 12:23:43.240121 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6174 12:23:43.242497 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6175 12:23:43.246115 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6176 12:23:43.249127 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6177 12:23:43.249589
6178 12:23:43.249950
6179 12:23:43.250282 ==
6180 12:23:43.252517 Dram Type= 6, Freq= 0, CH_0, rank 0
6181 12:23:43.255671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6182 12:23:43.256128 ==
6183 12:23:43.256542
6184 12:23:43.256879
6185 12:23:43.259063 TX Vref Scan disable
6186 12:23:43.259609 == TX Byte 0 ==
6187 12:23:43.266024 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6188 12:23:43.268773 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6189 12:23:43.269229 == TX Byte 1 ==
6190 12:23:43.275729 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6191 12:23:43.279018 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6192 12:23:43.279578 ==
6193 12:23:43.281986 Dram Type= 6, Freq= 0, CH_0, rank 0
6194 12:23:43.285416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6195 12:23:43.285876 ==
6196 12:23:43.286237
6197 12:23:43.289142
6198 12:23:43.289693 TX Vref Scan disable
6199 12:23:43.292755 == TX Byte 0 ==
6200 12:23:43.295826 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6201 12:23:43.298876 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6202 12:23:43.302685 == TX Byte 1 ==
6203 12:23:43.305229 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6204 12:23:43.308889 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6205 12:23:43.309442
6206 12:23:43.312341 [DATLAT]
6207 12:23:43.312896 Freq=400, CH0 RK0
6208 12:23:43.313263
6209 12:23:43.315500 DATLAT Default: 0xf
6210 12:23:43.316069 0, 0xFFFF, sum = 0
6211 12:23:43.318645 1, 0xFFFF, sum = 0
6212 12:23:43.319201 2, 0xFFFF, sum = 0
6213 12:23:43.321817 3, 0xFFFF, sum = 0
6214 12:23:43.322281 4, 0xFFFF, sum = 0
6215 12:23:43.325378 5, 0xFFFF, sum = 0
6216 12:23:43.325937 6, 0xFFFF, sum = 0
6217 12:23:43.328622 7, 0xFFFF, sum = 0
6218 12:23:43.329188 8, 0xFFFF, sum = 0
6219 12:23:43.332023 9, 0xFFFF, sum = 0
6220 12:23:43.332633 10, 0xFFFF, sum = 0
6221 12:23:43.335276 11, 0xFFFF, sum = 0
6222 12:23:43.335987 12, 0x0, sum = 1
6223 12:23:43.338364 13, 0x0, sum = 2
6224 12:23:43.339033 14, 0x0, sum = 3
6225 12:23:43.341617 15, 0x0, sum = 4
6226 12:23:43.342233 best_step = 13
6227 12:23:43.342679
6228 12:23:43.343027 ==
6229 12:23:43.344783 Dram Type= 6, Freq= 0, CH_0, rank 0
6230 12:23:43.351523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6231 12:23:43.352077 ==
6232 12:23:43.352494 RX Vref Scan: 1
6233 12:23:43.352829
6234 12:23:43.354645 RX Vref 0 -> 0, step: 1
6235 12:23:43.355101
6236 12:23:43.358097 RX Delay -359 -> 252, step: 8
6237 12:23:43.358664
6238 12:23:43.361482 Set Vref, RX VrefLevel [Byte0]: 45
6239 12:23:43.364819 [Byte1]: 46
6240 12:23:43.367973
6241 12:23:43.368466 Final RX Vref Byte 0 = 45 to rank0
6242 12:23:43.371667 Final RX Vref Byte 1 = 46 to rank0
6243 12:23:43.374570 Final RX Vref Byte 0 = 45 to rank1
6244 12:23:43.377980 Final RX Vref Byte 1 = 46 to rank1==
6245 12:23:43.381716 Dram Type= 6, Freq= 0, CH_0, rank 0
6246 12:23:43.387974 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6247 12:23:43.388580 ==
6248 12:23:43.388946 DQS Delay:
6249 12:23:43.391172 DQS0 = 52, DQS1 = 68
6250 12:23:43.391631 DQM Delay:
6251 12:23:43.391990 DQM0 = 8, DQM1 = 17
6252 12:23:43.394556 DQ Delay:
6253 12:23:43.395108 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6254 12:23:43.398305 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6255 12:23:43.401417 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6256 12:23:43.404799 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6257 12:23:43.405359
6258 12:23:43.405723
6259 12:23:43.414703 [DQSOSCAuto] RK0, (LSB)MR18= 0xa8a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6260 12:23:43.417793 CH0 RK0: MR19=C0C, MR18=A8A8
6261 12:23:43.424626 CH0_RK0: MR19=0xC0C, MR18=0xA8A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6262 12:23:43.425184 ==
6263 12:23:43.428327 Dram Type= 6, Freq= 0, CH_0, rank 1
6264 12:23:43.431180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6265 12:23:43.431741 ==
6266 12:23:43.434403 [Gating] SW mode calibration
6267 12:23:43.440773 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6268 12:23:43.444323 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6269 12:23:43.451118 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 12:23:43.454919 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 12:23:43.457850 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 12:23:43.464645 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6273 12:23:43.467571 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 12:23:43.470819 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 12:23:43.477233 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 12:23:43.480437 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6277 12:23:43.484053 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 12:23:43.487353 Total UI for P1: 0, mck2ui 16
6279 12:23:43.490591 best dqsien dly found for B0: ( 0, 10, 16)
6280 12:23:43.494279 Total UI for P1: 0, mck2ui 16
6281 12:23:43.497113 best dqsien dly found for B1: ( 0, 10, 16)
6282 12:23:43.500675 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6283 12:23:43.507115 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6284 12:23:43.507659
6285 12:23:43.510536 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6286 12:23:43.513947 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6287 12:23:43.517164 [Gating] SW calibration Done
6288 12:23:43.517731 ==
6289 12:23:43.520850 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 12:23:43.524030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6291 12:23:43.524629 ==
6292 12:23:43.527903 RX Vref Scan: 0
6293 12:23:43.528504
6294 12:23:43.528865 RX Vref 0 -> 0, step: 1
6295 12:23:43.529204
6296 12:23:43.531054 RX Delay -410 -> 252, step: 16
6297 12:23:43.533934 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6298 12:23:43.540623 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6299 12:23:43.543680 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6300 12:23:43.547102 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6301 12:23:43.550691 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6302 12:23:43.557025 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6303 12:23:43.560457 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6304 12:23:43.563693 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6305 12:23:43.567082 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6306 12:23:43.573622 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6307 12:23:43.577159 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6308 12:23:43.580464 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6309 12:23:43.583776 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6310 12:23:43.589990 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6311 12:23:43.593555 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6312 12:23:43.596833 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6313 12:23:43.597407 ==
6314 12:23:43.600665 Dram Type= 6, Freq= 0, CH_0, rank 1
6315 12:23:43.606697 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6316 12:23:43.607245 ==
6317 12:23:43.607611 DQS Delay:
6318 12:23:43.610248 DQS0 = 43, DQS1 = 59
6319 12:23:43.610799 DQM Delay:
6320 12:23:43.611163 DQM0 = 7, DQM1 = 15
6321 12:23:43.613499 DQ Delay:
6322 12:23:43.617142 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6323 12:23:43.620093 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6324 12:23:43.620706 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6325 12:23:43.623006 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6326 12:23:43.627047
6327 12:23:43.627601
6328 12:23:43.627960 ==
6329 12:23:43.630152 Dram Type= 6, Freq= 0, CH_0, rank 1
6330 12:23:43.633334 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6331 12:23:43.633898 ==
6332 12:23:43.634264
6333 12:23:43.634596
6334 12:23:43.636622 TX Vref Scan disable
6335 12:23:43.637177 == TX Byte 0 ==
6336 12:23:43.639605 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6337 12:23:43.646474 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6338 12:23:43.647032 == TX Byte 1 ==
6339 12:23:43.649885 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6340 12:23:43.656659 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6341 12:23:43.657219 ==
6342 12:23:43.660152 Dram Type= 6, Freq= 0, CH_0, rank 1
6343 12:23:43.663065 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6344 12:23:43.663660 ==
6345 12:23:43.664034
6346 12:23:43.664418
6347 12:23:43.666490 TX Vref Scan disable
6348 12:23:43.667044 == TX Byte 0 ==
6349 12:23:43.669625 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6350 12:23:43.676769 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6351 12:23:43.677330 == TX Byte 1 ==
6352 12:23:43.679771 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6353 12:23:43.686032 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6354 12:23:43.686540
6355 12:23:43.686903 [DATLAT]
6356 12:23:43.687248 Freq=400, CH0 RK1
6357 12:23:43.689332
6358 12:23:43.689787 DATLAT Default: 0xd
6359 12:23:43.692788 0, 0xFFFF, sum = 0
6360 12:23:43.693247 1, 0xFFFF, sum = 0
6361 12:23:43.696076 2, 0xFFFF, sum = 0
6362 12:23:43.696569 3, 0xFFFF, sum = 0
6363 12:23:43.699388 4, 0xFFFF, sum = 0
6364 12:23:43.699848 5, 0xFFFF, sum = 0
6365 12:23:43.702385 6, 0xFFFF, sum = 0
6366 12:23:43.702845 7, 0xFFFF, sum = 0
6367 12:23:43.706232 8, 0xFFFF, sum = 0
6368 12:23:43.706689 9, 0xFFFF, sum = 0
6369 12:23:43.709314 10, 0xFFFF, sum = 0
6370 12:23:43.709804 11, 0xFFFF, sum = 0
6371 12:23:43.712580 12, 0x0, sum = 1
6372 12:23:43.712993 13, 0x0, sum = 2
6373 12:23:43.716473 14, 0x0, sum = 3
6374 12:23:43.717037 15, 0x0, sum = 4
6375 12:23:43.719041 best_step = 13
6376 12:23:43.719452
6377 12:23:43.719826 ==
6378 12:23:43.722728 Dram Type= 6, Freq= 0, CH_0, rank 1
6379 12:23:43.726502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6380 12:23:43.727020 ==
6381 12:23:43.729466 RX Vref Scan: 0
6382 12:23:43.729978
6383 12:23:43.730300 RX Vref 0 -> 0, step: 1
6384 12:23:43.730606
6385 12:23:43.732718 RX Delay -359 -> 252, step: 8
6386 12:23:43.740255 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6387 12:23:43.743589 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6388 12:23:43.747177 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6389 12:23:43.753570 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6390 12:23:43.756630 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6391 12:23:43.760240 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6392 12:23:43.763623 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6393 12:23:43.770209 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6394 12:23:43.773522 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6395 12:23:43.776831 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6396 12:23:43.780144 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6397 12:23:43.786382 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6398 12:23:43.790131 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6399 12:23:43.793516 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6400 12:23:43.796824 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6401 12:23:43.803361 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6402 12:23:43.803911 ==
6403 12:23:43.806737 Dram Type= 6, Freq= 0, CH_0, rank 1
6404 12:23:43.809797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6405 12:23:43.810257 ==
6406 12:23:43.810615 DQS Delay:
6407 12:23:43.812861 DQS0 = 52, DQS1 = 64
6408 12:23:43.813312 DQM Delay:
6409 12:23:43.816280 DQM0 = 9, DQM1 = 13
6410 12:23:43.816826 DQ Delay:
6411 12:23:43.819592 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6412 12:23:43.823201 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6413 12:23:43.826718 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6414 12:23:43.829799 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6415 12:23:43.830355
6416 12:23:43.830746
6417 12:23:43.836692 [DQSOSCAuto] RK1, (LSB)MR18= 0xc9c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6418 12:23:43.839591 CH0 RK1: MR19=C0C, MR18=C9C9
6419 12:23:43.845949 CH0_RK1: MR19=0xC0C, MR18=0xC9C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6420 12:23:43.849824 [RxdqsGatingPostProcess] freq 400
6421 12:23:43.856026 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6422 12:23:43.859785 Pre-setting of DQS Precalculation
6423 12:23:43.863176 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6424 12:23:43.863719 ==
6425 12:23:43.866226 Dram Type= 6, Freq= 0, CH_1, rank 0
6426 12:23:43.869339 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6427 12:23:43.869801 ==
6428 12:23:43.876274 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6429 12:23:43.882295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6430 12:23:43.885697 [CA 0] Center 36 (8~64) winsize 57
6431 12:23:43.888996 [CA 1] Center 36 (8~64) winsize 57
6432 12:23:43.892538 [CA 2] Center 36 (8~64) winsize 57
6433 12:23:43.895930 [CA 3] Center 36 (8~64) winsize 57
6434 12:23:43.899279 [CA 4] Center 36 (8~64) winsize 57
6435 12:23:43.899734 [CA 5] Center 36 (8~64) winsize 57
6436 12:23:43.902510
6437 12:23:43.905850 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6438 12:23:43.906307
6439 12:23:43.909606 [CATrainingPosCal] consider 1 rank data
6440 12:23:43.912323 u2DelayCellTimex100 = 270/100 ps
6441 12:23:43.915619 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6442 12:23:43.918781 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6443 12:23:43.922120 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6444 12:23:43.925860 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6445 12:23:43.928856 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6446 12:23:43.932300 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6447 12:23:43.932763
6448 12:23:43.935647 CA PerBit enable=1, Macro0, CA PI delay=36
6449 12:23:43.936215
6450 12:23:43.939301 [CBTSetCACLKResult] CA Dly = 36
6451 12:23:43.942350 CS Dly: 1 (0~32)
6452 12:23:43.942947 ==
6453 12:23:43.945673 Dram Type= 6, Freq= 0, CH_1, rank 1
6454 12:23:43.948934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6455 12:23:43.949565 ==
6456 12:23:43.955633 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6457 12:23:43.962097 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6458 12:23:43.965504 [CA 0] Center 36 (8~64) winsize 57
6459 12:23:43.965960 [CA 1] Center 36 (8~64) winsize 57
6460 12:23:43.968857 [CA 2] Center 36 (8~64) winsize 57
6461 12:23:43.971941 [CA 3] Center 36 (8~64) winsize 57
6462 12:23:43.975397 [CA 4] Center 36 (8~64) winsize 57
6463 12:23:43.978702 [CA 5] Center 36 (8~64) winsize 57
6464 12:23:43.979261
6465 12:23:43.981785 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6466 12:23:43.982283
6467 12:23:43.985422 [CATrainingPosCal] consider 2 rank data
6468 12:23:43.988829 u2DelayCellTimex100 = 270/100 ps
6469 12:23:43.992374 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6470 12:23:43.998567 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6471 12:23:44.002202 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6472 12:23:44.005087 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6473 12:23:44.008743 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6474 12:23:44.011887 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6475 12:23:44.012488
6476 12:23:44.014880 CA PerBit enable=1, Macro0, CA PI delay=36
6477 12:23:44.015337
6478 12:23:44.018543 [CBTSetCACLKResult] CA Dly = 36
6479 12:23:44.021844 CS Dly: 1 (0~32)
6480 12:23:44.022609
6481 12:23:44.024998 ----->DramcWriteLeveling(PI) begin...
6482 12:23:44.025462 ==
6483 12:23:44.028535 Dram Type= 6, Freq= 0, CH_1, rank 0
6484 12:23:44.031426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6485 12:23:44.031988 ==
6486 12:23:44.035581 Write leveling (Byte 0): 32 => 0
6487 12:23:44.038342 Write leveling (Byte 1): 32 => 0
6488 12:23:44.041519 DramcWriteLeveling(PI) end<-----
6489 12:23:44.042075
6490 12:23:44.042435 ==
6491 12:23:44.044776 Dram Type= 6, Freq= 0, CH_1, rank 0
6492 12:23:44.048120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6493 12:23:44.048724 ==
6494 12:23:44.051685 [Gating] SW mode calibration
6495 12:23:44.058190 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6496 12:23:44.064696 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6497 12:23:44.067741 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 12:23:44.071227 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 12:23:44.077896 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 12:23:44.081150 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6501 12:23:44.084287 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 12:23:44.091499 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 12:23:44.094294 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 12:23:44.097771 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6505 12:23:44.104616 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 12:23:44.105185 Total UI for P1: 0, mck2ui 16
6507 12:23:44.111010 best dqsien dly found for B0: ( 0, 10, 16)
6508 12:23:44.111571 Total UI for P1: 0, mck2ui 16
6509 12:23:44.117951 best dqsien dly found for B1: ( 0, 10, 16)
6510 12:23:44.121153 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6511 12:23:44.124594 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6512 12:23:44.125155
6513 12:23:44.127660 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6514 12:23:44.131388 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6515 12:23:44.133797 [Gating] SW calibration Done
6516 12:23:44.134253 ==
6517 12:23:44.137757 Dram Type= 6, Freq= 0, CH_1, rank 0
6518 12:23:44.140819 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6519 12:23:44.141386 ==
6520 12:23:44.144331 RX Vref Scan: 0
6521 12:23:44.145013
6522 12:23:44.145495 RX Vref 0 -> 0, step: 1
6523 12:23:44.147617
6524 12:23:44.148083 RX Delay -410 -> 252, step: 16
6525 12:23:44.154033 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6526 12:23:44.157426 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6527 12:23:44.160966 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6528 12:23:44.167229 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6529 12:23:44.170618 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6530 12:23:44.173991 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6531 12:23:44.176794 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6532 12:23:44.183418 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6533 12:23:44.186950 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6534 12:23:44.190294 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6535 12:23:44.193207 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6536 12:23:44.200336 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6537 12:23:44.203828 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6538 12:23:44.207086 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6539 12:23:44.210282 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6540 12:23:44.216656 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6541 12:23:44.217219 ==
6542 12:23:44.220292 Dram Type= 6, Freq= 0, CH_1, rank 0
6543 12:23:44.223378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6544 12:23:44.223962 ==
6545 12:23:44.224499 DQS Delay:
6546 12:23:44.226746 DQS0 = 43, DQS1 = 59
6547 12:23:44.227307 DQM Delay:
6548 12:23:44.229824 DQM0 = 6, DQM1 = 14
6549 12:23:44.230294 DQ Delay:
6550 12:23:44.232810 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6551 12:23:44.236090 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6552 12:23:44.239751 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6553 12:23:44.242876 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6554 12:23:44.243344
6555 12:23:44.243835
6556 12:23:44.244412 ==
6557 12:23:44.246195 Dram Type= 6, Freq= 0, CH_1, rank 0
6558 12:23:44.249386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6559 12:23:44.249978 ==
6560 12:23:44.250483
6561 12:23:44.251039
6562 12:23:44.252989 TX Vref Scan disable
6563 12:23:44.256080 == TX Byte 0 ==
6564 12:23:44.259716 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6565 12:23:44.262904 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6566 12:23:44.266173 == TX Byte 1 ==
6567 12:23:44.269496 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6568 12:23:44.272737 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6569 12:23:44.273303 ==
6570 12:23:44.275956 Dram Type= 6, Freq= 0, CH_1, rank 0
6571 12:23:44.279474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6572 12:23:44.282452 ==
6573 12:23:44.282920
6574 12:23:44.283395
6575 12:23:44.283846 TX Vref Scan disable
6576 12:23:44.285974 == TX Byte 0 ==
6577 12:23:44.289174 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6578 12:23:44.292402 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6579 12:23:44.296012 == TX Byte 1 ==
6580 12:23:44.299350 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6581 12:23:44.302331 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6582 12:23:44.302904
6583 12:23:44.305750 [DATLAT]
6584 12:23:44.306316 Freq=400, CH1 RK0
6585 12:23:44.306805
6586 12:23:44.308810 DATLAT Default: 0xf
6587 12:23:44.309277 0, 0xFFFF, sum = 0
6588 12:23:44.312556 1, 0xFFFF, sum = 0
6589 12:23:44.313125 2, 0xFFFF, sum = 0
6590 12:23:44.315595 3, 0xFFFF, sum = 0
6591 12:23:44.316166 4, 0xFFFF, sum = 0
6592 12:23:44.318990 5, 0xFFFF, sum = 0
6593 12:23:44.319467 6, 0xFFFF, sum = 0
6594 12:23:44.322114 7, 0xFFFF, sum = 0
6595 12:23:44.322686 8, 0xFFFF, sum = 0
6596 12:23:44.325245 9, 0xFFFF, sum = 0
6597 12:23:44.328798 10, 0xFFFF, sum = 0
6598 12:23:44.329276 11, 0xFFFF, sum = 0
6599 12:23:44.331983 12, 0x0, sum = 1
6600 12:23:44.332560 13, 0x0, sum = 2
6601 12:23:44.333005 14, 0x0, sum = 3
6602 12:23:44.336039 15, 0x0, sum = 4
6603 12:23:44.336664 best_step = 13
6604 12:23:44.337106
6605 12:23:44.338605 ==
6606 12:23:44.339032 Dram Type= 6, Freq= 0, CH_1, rank 0
6607 12:23:44.345507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6608 12:23:44.346354 ==
6609 12:23:44.346737 RX Vref Scan: 1
6610 12:23:44.347046
6611 12:23:44.348645 RX Vref 0 -> 0, step: 1
6612 12:23:44.349056
6613 12:23:44.352017 RX Delay -359 -> 252, step: 8
6614 12:23:44.352472
6615 12:23:44.355427 Set Vref, RX VrefLevel [Byte0]: 52
6616 12:23:44.358825 [Byte1]: 49
6617 12:23:44.362005
6618 12:23:44.362417 Final RX Vref Byte 0 = 52 to rank0
6619 12:23:44.365889 Final RX Vref Byte 1 = 49 to rank0
6620 12:23:44.369209 Final RX Vref Byte 0 = 52 to rank1
6621 12:23:44.372079 Final RX Vref Byte 1 = 49 to rank1==
6622 12:23:44.375603 Dram Type= 6, Freq= 0, CH_1, rank 0
6623 12:23:44.381827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6624 12:23:44.382364 ==
6625 12:23:44.382705 DQS Delay:
6626 12:23:44.385107 DQS0 = 48, DQS1 = 64
6627 12:23:44.385518 DQM Delay:
6628 12:23:44.385841 DQM0 = 8, DQM1 = 15
6629 12:23:44.388754 DQ Delay:
6630 12:23:44.392423 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6631 12:23:44.392943 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6632 12:23:44.395168 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6633 12:23:44.398574 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6634 12:23:44.399092
6635 12:23:44.401813
6636 12:23:44.408592 [DQSOSCAuto] RK0, (LSB)MR18= 0xd4d4, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6637 12:23:44.411673 CH1 RK0: MR19=C0C, MR18=D4D4
6638 12:23:44.418212 CH1_RK0: MR19=0xC0C, MR18=0xD4D4, DQSOSC=383, MR23=63, INC=402, DEC=268
6639 12:23:44.418723 ==
6640 12:23:44.421660 Dram Type= 6, Freq= 0, CH_1, rank 1
6641 12:23:44.425153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6642 12:23:44.425678 ==
6643 12:23:44.428439 [Gating] SW mode calibration
6644 12:23:44.434886 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6645 12:23:44.441818 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6646 12:23:44.444905 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6647 12:23:44.448155 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6648 12:23:44.454906 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6649 12:23:44.458332 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6650 12:23:44.461083 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 12:23:44.468334 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 12:23:44.471517 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6653 12:23:44.474781 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6654 12:23:44.481431 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6655 12:23:44.481958 Total UI for P1: 0, mck2ui 16
6656 12:23:44.484428 best dqsien dly found for B0: ( 0, 10, 16)
6657 12:23:44.487553 Total UI for P1: 0, mck2ui 16
6658 12:23:44.491107 best dqsien dly found for B1: ( 0, 10, 16)
6659 12:23:44.497891 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6660 12:23:44.501149 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6661 12:23:44.501655
6662 12:23:44.504941 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6663 12:23:44.507698 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6664 12:23:44.511187 [Gating] SW calibration Done
6665 12:23:44.511695 ==
6666 12:23:44.514476 Dram Type= 6, Freq= 0, CH_1, rank 1
6667 12:23:44.517738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6668 12:23:44.518156 ==
6669 12:23:44.521116 RX Vref Scan: 0
6670 12:23:44.521620
6671 12:23:44.521948 RX Vref 0 -> 0, step: 1
6672 12:23:44.522255
6673 12:23:44.524462 RX Delay -410 -> 252, step: 16
6674 12:23:44.531239 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6675 12:23:44.534285 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6676 12:23:44.537637 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6677 12:23:44.541158 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6678 12:23:44.544573 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6679 12:23:44.551147 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6680 12:23:44.554299 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6681 12:23:44.557626 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6682 12:23:44.561412 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6683 12:23:44.567733 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6684 12:23:44.571030 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6685 12:23:44.574404 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6686 12:23:44.581146 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6687 12:23:44.584114 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6688 12:23:44.587268 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6689 12:23:44.590926 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6690 12:23:44.591429 ==
6691 12:23:44.594296 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 12:23:44.600719 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6693 12:23:44.601227 ==
6694 12:23:44.601551 DQS Delay:
6695 12:23:44.604170 DQS0 = 35, DQS1 = 59
6696 12:23:44.604733 DQM Delay:
6697 12:23:44.607138 DQM0 = 2, DQM1 = 18
6698 12:23:44.607544 DQ Delay:
6699 12:23:44.610559 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6700 12:23:44.610970 DQ4 =0, DQ5 =8, DQ6 =8, DQ7 =0
6701 12:23:44.613892 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6702 12:23:44.617494 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6703 12:23:44.618004
6704 12:23:44.620316
6705 12:23:44.620726 ==
6706 12:23:44.624153 Dram Type= 6, Freq= 0, CH_1, rank 1
6707 12:23:44.627107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6708 12:23:44.627525 ==
6709 12:23:44.627850
6710 12:23:44.628152
6711 12:23:44.630250 TX Vref Scan disable
6712 12:23:44.630661 == TX Byte 0 ==
6713 12:23:44.633751 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6714 12:23:44.640483 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6715 12:23:44.640990 == TX Byte 1 ==
6716 12:23:44.643640 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6717 12:23:44.650181 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6718 12:23:44.650701 ==
6719 12:23:44.653740 Dram Type= 6, Freq= 0, CH_1, rank 1
6720 12:23:44.656728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6721 12:23:44.657141 ==
6722 12:23:44.657464
6723 12:23:44.657765
6724 12:23:44.660246 TX Vref Scan disable
6725 12:23:44.660659 == TX Byte 0 ==
6726 12:23:44.663485 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6727 12:23:44.670671 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6728 12:23:44.671176 == TX Byte 1 ==
6729 12:23:44.673865 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6730 12:23:44.680262 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6731 12:23:44.680777
6732 12:23:44.681265 [DATLAT]
6733 12:23:44.681654 Freq=400, CH1 RK1
6734 12:23:44.683307
6735 12:23:44.683713 DATLAT Default: 0xd
6736 12:23:44.686450 0, 0xFFFF, sum = 0
6737 12:23:44.686868 1, 0xFFFF, sum = 0
6738 12:23:44.690176 2, 0xFFFF, sum = 0
6739 12:23:44.690687 3, 0xFFFF, sum = 0
6740 12:23:44.693160 4, 0xFFFF, sum = 0
6741 12:23:44.693581 5, 0xFFFF, sum = 0
6742 12:23:44.696567 6, 0xFFFF, sum = 0
6743 12:23:44.696942 7, 0xFFFF, sum = 0
6744 12:23:44.700039 8, 0xFFFF, sum = 0
6745 12:23:44.700595 9, 0xFFFF, sum = 0
6746 12:23:44.703480 10, 0xFFFF, sum = 0
6747 12:23:44.703988 11, 0xFFFF, sum = 0
6748 12:23:44.706794 12, 0x0, sum = 1
6749 12:23:44.707306 13, 0x0, sum = 2
6750 12:23:44.709885 14, 0x0, sum = 3
6751 12:23:44.710303 15, 0x0, sum = 4
6752 12:23:44.713320 best_step = 13
6753 12:23:44.713828
6754 12:23:44.714152 ==
6755 12:23:44.716406 Dram Type= 6, Freq= 0, CH_1, rank 1
6756 12:23:44.719665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6757 12:23:44.720213 ==
6758 12:23:44.723300 RX Vref Scan: 0
6759 12:23:44.723805
6760 12:23:44.724132 RX Vref 0 -> 0, step: 1
6761 12:23:44.724480
6762 12:23:44.726240 RX Delay -359 -> 252, step: 8
6763 12:23:44.734118 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6764 12:23:44.737965 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6765 12:23:44.740915 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6766 12:23:44.747695 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6767 12:23:44.750646 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6768 12:23:44.754051 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6769 12:23:44.757538 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6770 12:23:44.760501 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6771 12:23:44.767348 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6772 12:23:44.770724 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6773 12:23:44.774033 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6774 12:23:44.780419 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6775 12:23:44.783818 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6776 12:23:44.787245 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6777 12:23:44.791058 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6778 12:23:44.797714 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6779 12:23:44.798221 ==
6780 12:23:44.800614 Dram Type= 6, Freq= 0, CH_1, rank 1
6781 12:23:44.803993 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6782 12:23:44.804546 ==
6783 12:23:44.804879 DQS Delay:
6784 12:23:44.806871 DQS0 = 48, DQS1 = 64
6785 12:23:44.807280 DQM Delay:
6786 12:23:44.810617 DQM0 = 9, DQM1 = 15
6787 12:23:44.811123 DQ Delay:
6788 12:23:44.814198 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6789 12:23:44.817500 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6790 12:23:44.820612 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6791 12:23:44.824105 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6792 12:23:44.824663
6793 12:23:44.824995
6794 12:23:44.830512 [DQSOSCAuto] RK1, (LSB)MR18= 0xb6b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6795 12:23:44.833466 CH1 RK1: MR19=C0C, MR18=B6B6
6796 12:23:44.840263 CH1_RK1: MR19=0xC0C, MR18=0xB6B6, DQSOSC=387, MR23=63, INC=394, DEC=262
6797 12:23:44.843715 [RxdqsGatingPostProcess] freq 400
6798 12:23:44.850041 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6799 12:23:44.850536 Pre-setting of DQS Precalculation
6800 12:23:44.856722 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6801 12:23:44.863347 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6802 12:23:44.870454 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6803 12:23:44.870960
6804 12:23:44.871325
6805 12:23:44.873096 [Calibration Summary] 800 Mbps
6806 12:23:44.876633 CH 0, Rank 0
6807 12:23:44.877135 SW Impedance : PASS
6808 12:23:44.880069 DUTY Scan : NO K
6809 12:23:44.883204 ZQ Calibration : PASS
6810 12:23:44.883631 Jitter Meter : NO K
6811 12:23:44.886560 CBT Training : PASS
6812 12:23:44.890194 Write leveling : PASS
6813 12:23:44.890699 RX DQS gating : PASS
6814 12:23:44.892946 RX DQ/DQS(RDDQC) : PASS
6815 12:23:44.893356 TX DQ/DQS : PASS
6816 12:23:44.896515 RX DATLAT : PASS
6817 12:23:44.899996 RX DQ/DQS(Engine): PASS
6818 12:23:44.900432 TX OE : NO K
6819 12:23:44.903400 All Pass.
6820 12:23:44.903905
6821 12:23:44.904271 CH 0, Rank 1
6822 12:23:44.907000 SW Impedance : PASS
6823 12:23:44.907505 DUTY Scan : NO K
6824 12:23:44.910005 ZQ Calibration : PASS
6825 12:23:44.913336 Jitter Meter : NO K
6826 12:23:44.913842 CBT Training : PASS
6827 12:23:44.916489 Write leveling : NO K
6828 12:23:44.919900 RX DQS gating : PASS
6829 12:23:44.920448 RX DQ/DQS(RDDQC) : PASS
6830 12:23:44.923653 TX DQ/DQS : PASS
6831 12:23:44.926773 RX DATLAT : PASS
6832 12:23:44.927279 RX DQ/DQS(Engine): PASS
6833 12:23:44.929831 TX OE : NO K
6834 12:23:44.930335 All Pass.
6835 12:23:44.930660
6836 12:23:44.932886 CH 1, Rank 0
6837 12:23:44.933295 SW Impedance : PASS
6838 12:23:44.936413 DUTY Scan : NO K
6839 12:23:44.939996 ZQ Calibration : PASS
6840 12:23:44.940564 Jitter Meter : NO K
6841 12:23:44.942940 CBT Training : PASS
6842 12:23:44.946554 Write leveling : PASS
6843 12:23:44.947059 RX DQS gating : PASS
6844 12:23:44.949512 RX DQ/DQS(RDDQC) : PASS
6845 12:23:44.949924 TX DQ/DQS : PASS
6846 12:23:44.952914 RX DATLAT : PASS
6847 12:23:44.955930 RX DQ/DQS(Engine): PASS
6848 12:23:44.956383 TX OE : NO K
6849 12:23:44.959131 All Pass.
6850 12:23:44.959535
6851 12:23:44.959855 CH 1, Rank 1
6852 12:23:44.962829 SW Impedance : PASS
6853 12:23:44.963340 DUTY Scan : NO K
6854 12:23:44.966235 ZQ Calibration : PASS
6855 12:23:44.969597 Jitter Meter : NO K
6856 12:23:44.970104 CBT Training : PASS
6857 12:23:44.972928 Write leveling : NO K
6858 12:23:44.976059 RX DQS gating : PASS
6859 12:23:44.976609 RX DQ/DQS(RDDQC) : PASS
6860 12:23:44.979314 TX DQ/DQS : PASS
6861 12:23:44.982669 RX DATLAT : PASS
6862 12:23:44.983177 RX DQ/DQS(Engine): PASS
6863 12:23:44.986180 TX OE : NO K
6864 12:23:44.986590 All Pass.
6865 12:23:44.986911
6866 12:23:44.988753 DramC Write-DBI off
6867 12:23:44.992513 PER_BANK_REFRESH: Hybrid Mode
6868 12:23:44.993019 TX_TRACKING: ON
6869 12:23:45.002386 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6870 12:23:45.005691 [FAST_K] Save calibration result to emmc
6871 12:23:45.008995 dramc_set_vcore_voltage set vcore to 725000
6872 12:23:45.012542 Read voltage for 1600, 0
6873 12:23:45.012948 Vio18 = 0
6874 12:23:45.013269 Vcore = 725000
6875 12:23:45.015967 Vdram = 0
6876 12:23:45.016505 Vddq = 0
6877 12:23:45.016834 Vmddr = 0
6878 12:23:45.022202 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6879 12:23:45.025696 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6880 12:23:45.028861 MEM_TYPE=3, freq_sel=13
6881 12:23:45.032096 sv_algorithm_assistance_LP4_3733
6882 12:23:45.035967 ============ PULL DRAM RESETB DOWN ============
6883 12:23:45.038940 ========== PULL DRAM RESETB DOWN end =========
6884 12:23:45.045453 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6885 12:23:45.048545 ===================================
6886 12:23:45.051836 LPDDR4 DRAM CONFIGURATION
6887 12:23:45.055403 ===================================
6888 12:23:45.055811 EX_ROW_EN[0] = 0x0
6889 12:23:45.058761 EX_ROW_EN[1] = 0x0
6890 12:23:45.059272 LP4Y_EN = 0x0
6891 12:23:45.061853 WORK_FSP = 0x1
6892 12:23:45.062256 WL = 0x5
6893 12:23:45.065690 RL = 0x5
6894 12:23:45.066196 BL = 0x2
6895 12:23:45.068603 RPST = 0x0
6896 12:23:45.069007 RD_PRE = 0x0
6897 12:23:45.072274 WR_PRE = 0x1
6898 12:23:45.072789 WR_PST = 0x1
6899 12:23:45.075304 DBI_WR = 0x0
6900 12:23:45.075806 DBI_RD = 0x0
6901 12:23:45.078747 OTF = 0x1
6902 12:23:45.081974 ===================================
6903 12:23:45.085188 ===================================
6904 12:23:45.085592 ANA top config
6905 12:23:45.088515 ===================================
6906 12:23:45.092045 DLL_ASYNC_EN = 0
6907 12:23:45.095574 ALL_SLAVE_EN = 0
6908 12:23:45.098517 NEW_RANK_MODE = 1
6909 12:23:45.102099 DLL_IDLE_MODE = 1
6910 12:23:45.102603 LP45_APHY_COMB_EN = 1
6911 12:23:45.104994 TX_ODT_DIS = 0
6912 12:23:45.108477 NEW_8X_MODE = 1
6913 12:23:45.111689 ===================================
6914 12:23:45.115444 ===================================
6915 12:23:45.118441 data_rate = 3200
6916 12:23:45.121714 CKR = 1
6917 12:23:45.122221 DQ_P2S_RATIO = 8
6918 12:23:45.124919 ===================================
6919 12:23:45.128395 CA_P2S_RATIO = 8
6920 12:23:45.131456 DQ_CA_OPEN = 0
6921 12:23:45.134829 DQ_SEMI_OPEN = 0
6922 12:23:45.138466 CA_SEMI_OPEN = 0
6923 12:23:45.141814 CA_FULL_RATE = 0
6924 12:23:45.142320 DQ_CKDIV4_EN = 0
6925 12:23:45.144824 CA_CKDIV4_EN = 0
6926 12:23:45.147959 CA_PREDIV_EN = 0
6927 12:23:45.151168 PH8_DLY = 12
6928 12:23:45.154922 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6929 12:23:45.158090 DQ_AAMCK_DIV = 4
6930 12:23:45.158593 CA_AAMCK_DIV = 4
6931 12:23:45.161251 CA_ADMCK_DIV = 4
6932 12:23:45.164718 DQ_TRACK_CA_EN = 0
6933 12:23:45.167993 CA_PICK = 1600
6934 12:23:45.171130 CA_MCKIO = 1600
6935 12:23:45.174726 MCKIO_SEMI = 0
6936 12:23:45.177707 PLL_FREQ = 3068
6937 12:23:45.181113 DQ_UI_PI_RATIO = 32
6938 12:23:45.181560 CA_UI_PI_RATIO = 0
6939 12:23:45.184483 ===================================
6940 12:23:45.187768 ===================================
6941 12:23:45.191372 memory_type:LPDDR4
6942 12:23:45.194429 GP_NUM : 10
6943 12:23:45.194864 SRAM_EN : 1
6944 12:23:45.197890 MD32_EN : 0
6945 12:23:45.201130 ===================================
6946 12:23:45.204554 [ANA_INIT] >>>>>>>>>>>>>>
6947 12:23:45.205058 <<<<<< [CONFIGURE PHASE]: ANA_TX
6948 12:23:45.208409 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6949 12:23:45.211405 ===================================
6950 12:23:45.214481 data_rate = 3200,PCW = 0X7600
6951 12:23:45.217808 ===================================
6952 12:23:45.221223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6953 12:23:45.227455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6954 12:23:45.234462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6955 12:23:45.237771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6956 12:23:45.241121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6957 12:23:45.244219 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6958 12:23:45.247462 [ANA_INIT] flow start
6959 12:23:45.247870 [ANA_INIT] PLL >>>>>>>>
6960 12:23:45.250718 [ANA_INIT] PLL <<<<<<<<
6961 12:23:45.253930 [ANA_INIT] MIDPI >>>>>>>>
6962 12:23:45.257605 [ANA_INIT] MIDPI <<<<<<<<
6963 12:23:45.258154 [ANA_INIT] DLL >>>>>>>>
6964 12:23:45.260540 [ANA_INIT] DLL <<<<<<<<
6965 12:23:45.260945 [ANA_INIT] flow end
6966 12:23:45.267619 ============ LP4 DIFF to SE enter ============
6967 12:23:45.271015 ============ LP4 DIFF to SE exit ============
6968 12:23:45.273830 [ANA_INIT] <<<<<<<<<<<<<
6969 12:23:45.277469 [Flow] Enable top DCM control >>>>>
6970 12:23:45.280612 [Flow] Enable top DCM control <<<<<
6971 12:23:45.284079 Enable DLL master slave shuffle
6972 12:23:45.287235 ==============================================================
6973 12:23:45.291074 Gating Mode config
6974 12:23:45.294002 ==============================================================
6975 12:23:45.297134 Config description:
6976 12:23:45.307238 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6977 12:23:45.313823 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6978 12:23:45.317512 SELPH_MODE 0: By rank 1: By Phase
6979 12:23:45.323694 ==============================================================
6980 12:23:45.327365 GAT_TRACK_EN = 1
6981 12:23:45.330484 RX_GATING_MODE = 2
6982 12:23:45.334028 RX_GATING_TRACK_MODE = 2
6983 12:23:45.337166 SELPH_MODE = 1
6984 12:23:45.340312 PICG_EARLY_EN = 1
6985 12:23:45.340720 VALID_LAT_VALUE = 1
6986 12:23:45.346938 ==============================================================
6987 12:23:45.350568 Enter into Gating configuration >>>>
6988 12:23:45.353533 Exit from Gating configuration <<<<
6989 12:23:45.356840 Enter into DVFS_PRE_config >>>>>
6990 12:23:45.366855 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6991 12:23:45.369868 Exit from DVFS_PRE_config <<<<<
6992 12:23:45.373554 Enter into PICG configuration >>>>
6993 12:23:45.376601 Exit from PICG configuration <<<<
6994 12:23:45.380134 [RX_INPUT] configuration >>>>>
6995 12:23:45.383654 [RX_INPUT] configuration <<<<<
6996 12:23:45.389963 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6997 12:23:45.393389 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6998 12:23:45.400431 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6999 12:23:45.406741 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7000 12:23:45.413149 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7001 12:23:45.420004 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7002 12:23:45.423212 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7003 12:23:45.426257 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7004 12:23:45.430150 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7005 12:23:45.436578 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7006 12:23:45.440165 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7007 12:23:45.443152 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7008 12:23:45.446642 ===================================
7009 12:23:45.450020 LPDDR4 DRAM CONFIGURATION
7010 12:23:45.453120 ===================================
7011 12:23:45.453581 EX_ROW_EN[0] = 0x0
7012 12:23:45.456441 EX_ROW_EN[1] = 0x0
7013 12:23:45.460225 LP4Y_EN = 0x0
7014 12:23:45.460781 WORK_FSP = 0x1
7015 12:23:45.463300 WL = 0x5
7016 12:23:45.463848 RL = 0x5
7017 12:23:45.466436 BL = 0x2
7018 12:23:45.466986 RPST = 0x0
7019 12:23:45.470075 RD_PRE = 0x0
7020 12:23:45.470620 WR_PRE = 0x1
7021 12:23:45.473398 WR_PST = 0x1
7022 12:23:45.473856 DBI_WR = 0x0
7023 12:23:45.476065 DBI_RD = 0x0
7024 12:23:45.476563 OTF = 0x1
7025 12:23:45.479906 ===================================
7026 12:23:45.482965 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7027 12:23:45.489422 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7028 12:23:45.492781 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7029 12:23:45.496477 ===================================
7030 12:23:45.499808 LPDDR4 DRAM CONFIGURATION
7031 12:23:45.503139 ===================================
7032 12:23:45.503692 EX_ROW_EN[0] = 0x10
7033 12:23:45.506013 EX_ROW_EN[1] = 0x0
7034 12:23:45.506564 LP4Y_EN = 0x0
7035 12:23:45.509420 WORK_FSP = 0x1
7036 12:23:45.512642 WL = 0x5
7037 12:23:45.513213 RL = 0x5
7038 12:23:45.515784 BL = 0x2
7039 12:23:45.516283 RPST = 0x0
7040 12:23:45.519459 RD_PRE = 0x0
7041 12:23:45.520025 WR_PRE = 0x1
7042 12:23:45.522462 WR_PST = 0x1
7043 12:23:45.523011 DBI_WR = 0x0
7044 12:23:45.525984 DBI_RD = 0x0
7045 12:23:45.526545 OTF = 0x1
7046 12:23:45.528966 ===================================
7047 12:23:45.535822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7048 12:23:45.536422 ==
7049 12:23:45.539144 Dram Type= 6, Freq= 0, CH_0, rank 0
7050 12:23:45.542293 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7051 12:23:45.542772 ==
7052 12:23:45.545947 [Duty_Offset_Calibration]
7053 12:23:45.548779 B0:0 B1:2 CA:1
7054 12:23:45.549238
7055 12:23:45.552335 [DutyScan_Calibration_Flow] k_type=0
7056 12:23:45.561171
7057 12:23:45.561717 ==CLK 0==
7058 12:23:45.564393 Final CLK duty delay cell = 0
7059 12:23:45.567732 [0] MAX Duty = 5156%(X100), DQS PI = 22
7060 12:23:45.571670 [0] MIN Duty = 4938%(X100), DQS PI = 50
7061 12:23:45.574533 [0] AVG Duty = 5047%(X100)
7062 12:23:45.575085
7063 12:23:45.577429 CH0 CLK Duty spec in!! Max-Min= 218%
7064 12:23:45.580767 [DutyScan_Calibration_Flow] ====Done====
7065 12:23:45.581312
7066 12:23:45.583746 [DutyScan_Calibration_Flow] k_type=1
7067 12:23:45.601075
7068 12:23:45.601618 ==DQS 0 ==
7069 12:23:45.604480 Final DQS duty delay cell = 0
7070 12:23:45.607667 [0] MAX Duty = 5156%(X100), DQS PI = 32
7071 12:23:45.611362 [0] MIN Duty = 5031%(X100), DQS PI = 10
7072 12:23:45.614261 [0] AVG Duty = 5093%(X100)
7073 12:23:45.614813
7074 12:23:45.615172 ==DQS 1 ==
7075 12:23:45.617415 Final DQS duty delay cell = 0
7076 12:23:45.620846 [0] MAX Duty = 5031%(X100), DQS PI = 2
7077 12:23:45.624115 [0] MIN Duty = 4876%(X100), DQS PI = 16
7078 12:23:45.627156 [0] AVG Duty = 4953%(X100)
7079 12:23:45.627697
7080 12:23:45.630903 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7081 12:23:45.631460
7082 12:23:45.633924 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7083 12:23:45.637286 [DutyScan_Calibration_Flow] ====Done====
7084 12:23:45.637831
7085 12:23:45.640317 [DutyScan_Calibration_Flow] k_type=3
7086 12:23:45.658177
7087 12:23:45.658724 ==DQM 0 ==
7088 12:23:45.661508 Final DQM duty delay cell = 0
7089 12:23:45.664945 [0] MAX Duty = 5187%(X100), DQS PI = 24
7090 12:23:45.668080 [0] MIN Duty = 4907%(X100), DQS PI = 56
7091 12:23:45.671268 [0] AVG Duty = 5047%(X100)
7092 12:23:45.671816
7093 12:23:45.672227 ==DQM 1 ==
7094 12:23:45.674671 Final DQM duty delay cell = 0
7095 12:23:45.678400 [0] MAX Duty = 5062%(X100), DQS PI = 52
7096 12:23:45.681859 [0] MIN Duty = 4782%(X100), DQS PI = 14
7097 12:23:45.684894 [0] AVG Duty = 4922%(X100)
7098 12:23:45.685446
7099 12:23:45.687740 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7100 12:23:45.688245
7101 12:23:45.691511 CH0 DQM 1 Duty spec in!! Max-Min= 280%
7102 12:23:45.694600 [DutyScan_Calibration_Flow] ====Done====
7103 12:23:45.695059
7104 12:23:45.697654 [DutyScan_Calibration_Flow] k_type=2
7105 12:23:45.714585
7106 12:23:45.715129 ==DQ 0 ==
7107 12:23:45.717849 Final DQ duty delay cell = 0
7108 12:23:45.721144 [0] MAX Duty = 5218%(X100), DQS PI = 18
7109 12:23:45.724470 [0] MIN Duty = 4938%(X100), DQS PI = 56
7110 12:23:45.725041 [0] AVG Duty = 5078%(X100)
7111 12:23:45.727461
7112 12:23:45.727915 ==DQ 1 ==
7113 12:23:45.731099 Final DQ duty delay cell = -4
7114 12:23:45.734302 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7115 12:23:45.737555 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7116 12:23:45.741198 [-4] AVG Duty = 4953%(X100)
7117 12:23:45.741753
7118 12:23:45.744074 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7119 12:23:45.744603
7120 12:23:45.747626 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7121 12:23:45.750934 [DutyScan_Calibration_Flow] ====Done====
7122 12:23:45.751489 ==
7123 12:23:45.753956 Dram Type= 6, Freq= 0, CH_1, rank 0
7124 12:23:45.757385 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7125 12:23:45.757847 ==
7126 12:23:45.760751 [Duty_Offset_Calibration]
7127 12:23:45.761207 B0:0 B1:4 CA:-5
7128 12:23:45.761575
7129 12:23:45.763835 [DutyScan_Calibration_Flow] k_type=0
7130 12:23:45.775196
7131 12:23:45.775763 ==CLK 0==
7132 12:23:45.778226 Final CLK duty delay cell = 0
7133 12:23:45.781897 [0] MAX Duty = 5156%(X100), DQS PI = 26
7134 12:23:45.785044 [0] MIN Duty = 4906%(X100), DQS PI = 52
7135 12:23:45.785514 [0] AVG Duty = 5031%(X100)
7136 12:23:45.788427
7137 12:23:45.791732 CH1 CLK Duty spec in!! Max-Min= 250%
7138 12:23:45.795328 [DutyScan_Calibration_Flow] ====Done====
7139 12:23:45.795914
7140 12:23:45.798512 [DutyScan_Calibration_Flow] k_type=1
7141 12:23:45.814151
7142 12:23:45.814698 ==DQS 0 ==
7143 12:23:45.817229 Final DQS duty delay cell = 0
7144 12:23:45.821178 [0] MAX Duty = 5156%(X100), DQS PI = 18
7145 12:23:45.823945 [0] MIN Duty = 4844%(X100), DQS PI = 44
7146 12:23:45.827144 [0] AVG Duty = 5000%(X100)
7147 12:23:45.827726
7148 12:23:45.828105 ==DQS 1 ==
7149 12:23:45.830557 Final DQS duty delay cell = -4
7150 12:23:45.833927 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7151 12:23:45.837457 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7152 12:23:45.840851 [-4] AVG Duty = 4922%(X100)
7153 12:23:45.841402
7154 12:23:45.843816 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7155 12:23:45.844423
7156 12:23:45.847263 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7157 12:23:45.850837 [DutyScan_Calibration_Flow] ====Done====
7158 12:23:45.851443
7159 12:23:45.853737 [DutyScan_Calibration_Flow] k_type=3
7160 12:23:45.869870
7161 12:23:45.870429 ==DQM 0 ==
7162 12:23:45.872775 Final DQM duty delay cell = -4
7163 12:23:45.876552 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7164 12:23:45.879563 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7165 12:23:45.882875 [-4] AVG Duty = 4922%(X100)
7166 12:23:45.883331
7167 12:23:45.883686 ==DQM 1 ==
7168 12:23:45.885939 Final DQM duty delay cell = -4
7169 12:23:45.889157 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7170 12:23:45.892698 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7171 12:23:45.895979 [-4] AVG Duty = 5000%(X100)
7172 12:23:45.896570
7173 12:23:45.899916 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7174 12:23:45.900516
7175 12:23:45.902957 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7176 12:23:45.905812 [DutyScan_Calibration_Flow] ====Done====
7177 12:23:45.906331
7178 12:23:45.909059 [DutyScan_Calibration_Flow] k_type=2
7179 12:23:45.927680
7180 12:23:45.928268 ==DQ 0 ==
7181 12:23:45.930918 Final DQ duty delay cell = 0
7182 12:23:45.934002 [0] MAX Duty = 5093%(X100), DQS PI = 36
7183 12:23:45.937142 [0] MIN Duty = 4969%(X100), DQS PI = 44
7184 12:23:45.937696 [0] AVG Duty = 5031%(X100)
7185 12:23:45.940811
7186 12:23:45.941356 ==DQ 1 ==
7187 12:23:45.944119 Final DQ duty delay cell = 0
7188 12:23:45.947066 [0] MAX Duty = 5031%(X100), DQS PI = 4
7189 12:23:45.950457 [0] MIN Duty = 4876%(X100), DQS PI = 30
7190 12:23:45.954104 [0] AVG Duty = 4953%(X100)
7191 12:23:45.954651
7192 12:23:45.956725 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7193 12:23:45.957183
7194 12:23:45.960352 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7195 12:23:45.963855 [DutyScan_Calibration_Flow] ====Done====
7196 12:23:45.966784 nWR fixed to 30
7197 12:23:45.967334 [ModeRegInit_LP4] CH0 RK0
7198 12:23:45.970353 [ModeRegInit_LP4] CH0 RK1
7199 12:23:45.973352 [ModeRegInit_LP4] CH1 RK0
7200 12:23:45.976550 [ModeRegInit_LP4] CH1 RK1
7201 12:23:45.977008 match AC timing 4
7202 12:23:45.983412 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7203 12:23:45.986498 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7204 12:23:45.989752 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7205 12:23:45.996592 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7206 12:23:45.999797 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7207 12:23:46.000296 [MiockJmeterHQA]
7208 12:23:46.000665
7209 12:23:46.002961 [DramcMiockJmeter] u1RxGatingPI = 0
7210 12:23:46.006553 0 : 4253, 4027
7211 12:23:46.007018 4 : 4252, 4027
7212 12:23:46.009824 8 : 4252, 4027
7213 12:23:46.010380 12 : 4253, 4026
7214 12:23:46.010752 16 : 4255, 4029
7215 12:23:46.012899 20 : 4252, 4027
7216 12:23:46.013363 24 : 4253, 4027
7217 12:23:46.016364 28 : 4363, 4137
7218 12:23:46.016912 32 : 4258, 4029
7219 12:23:46.019858 36 : 4363, 4137
7220 12:23:46.020475 40 : 4255, 4029
7221 12:23:46.023269 44 : 4366, 4140
7222 12:23:46.023823 48 : 4363, 4137
7223 12:23:46.026286 52 : 4253, 4027
7224 12:23:46.026843 56 : 4363, 4137
7225 12:23:46.027212 60 : 4252, 4027
7226 12:23:46.029565 64 : 4365, 4140
7227 12:23:46.030132 68 : 4363, 4140
7228 12:23:46.033111 72 : 4250, 4027
7229 12:23:46.033668 76 : 4252, 4029
7230 12:23:46.036623 80 : 4360, 4138
7231 12:23:46.037180 84 : 4250, 4027
7232 12:23:46.037611 88 : 4363, 4139
7233 12:23:46.039662 92 : 4250, 4026
7234 12:23:46.040447 96 : 4249, 4027
7235 12:23:46.043180 100 : 4250, 2382
7236 12:23:46.043737 104 : 4250, 0
7237 12:23:46.046155 108 : 4250, 0
7238 12:23:46.046713 112 : 4360, 0
7239 12:23:46.047087 116 : 4250, 0
7240 12:23:46.049872 120 : 4250, 0
7241 12:23:46.050427 124 : 4360, 0
7242 12:23:46.052568 128 : 4250, 0
7243 12:23:46.053031 132 : 4250, 0
7244 12:23:46.053403 136 : 4250, 0
7245 12:23:46.055943 140 : 4252, 0
7246 12:23:46.056709 144 : 4361, 0
7247 12:23:46.059051 148 : 4361, 0
7248 12:23:46.059531 152 : 4250, 0
7249 12:23:46.060021 156 : 4255, 0
7250 12:23:46.062299 160 : 4360, 0
7251 12:23:46.062775 164 : 4360, 0
7252 12:23:46.065672 168 : 4250, 0
7253 12:23:46.066153 172 : 4250, 0
7254 12:23:46.066638 176 : 4250, 0
7255 12:23:46.069033 180 : 4250, 0
7256 12:23:46.069519 184 : 4250, 0
7257 12:23:46.070007 188 : 4249, 0
7258 12:23:46.072607 192 : 4250, 0
7259 12:23:46.073088 196 : 4361, 0
7260 12:23:46.075577 200 : 4365, 0
7261 12:23:46.076056 204 : 4250, 0
7262 12:23:46.076594 208 : 4250, 0
7263 12:23:46.078925 212 : 4250, 0
7264 12:23:46.079403 216 : 4361, 0
7265 12:23:46.082633 220 : 4250, 679
7266 12:23:46.083232 224 : 4249, 4007
7267 12:23:46.085464 228 : 4360, 4137
7268 12:23:46.085957 232 : 4361, 4137
7269 12:23:46.088789 236 : 4252, 4029
7270 12:23:46.089284 240 : 4250, 4026
7271 12:23:46.089776 244 : 4360, 4137
7272 12:23:46.091990 248 : 4360, 4137
7273 12:23:46.092531 252 : 4250, 4027
7274 12:23:46.095673 256 : 4250, 4027
7275 12:23:46.096309 260 : 4249, 4027
7276 12:23:46.098558 264 : 4250, 4027
7277 12:23:46.099037 268 : 4250, 4027
7278 12:23:46.102431 272 : 4253, 4029
7279 12:23:46.103010 276 : 4250, 4027
7280 12:23:46.105812 280 : 4360, 4137
7281 12:23:46.106409 284 : 4250, 4026
7282 12:23:46.108610 288 : 4250, 4027
7283 12:23:46.109132 292 : 4250, 4027
7284 12:23:46.111807 296 : 4363, 4139
7285 12:23:46.112325 300 : 4360, 4137
7286 12:23:46.115193 304 : 4250, 4027
7287 12:23:46.115742 308 : 4250, 4027
7288 12:23:46.116111 312 : 4250, 4027
7289 12:23:46.118620 316 : 4250, 4027
7290 12:23:46.119171 320 : 4250, 4027
7291 12:23:46.122219 324 : 4252, 4029
7292 12:23:46.122686 328 : 4249, 4027
7293 12:23:46.125037 332 : 4360, 4137
7294 12:23:46.125501 336 : 4250, 3977
7295 12:23:46.128837 340 : 4250, 2229
7296 12:23:46.129391 344 : 4250, 2
7297 12:23:46.129757
7298 12:23:46.131840 MIOCK jitter meter ch=0
7299 12:23:46.132331
7300 12:23:46.135327 1T = (344-104) = 240 dly cells
7301 12:23:46.138638 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7302 12:23:46.141946 ==
7303 12:23:46.145009 Dram Type= 6, Freq= 0, CH_0, rank 0
7304 12:23:46.148535 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7305 12:23:46.149086 ==
7306 12:23:46.152067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7307 12:23:46.158382 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7308 12:23:46.161519 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7309 12:23:46.168921 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7310 12:23:46.175748 [CA 0] Center 42 (12~72) winsize 61
7311 12:23:46.179207 [CA 1] Center 41 (11~72) winsize 62
7312 12:23:46.182568 [CA 2] Center 37 (7~67) winsize 61
7313 12:23:46.185373 [CA 3] Center 37 (7~67) winsize 61
7314 12:23:46.188741 [CA 4] Center 35 (5~66) winsize 62
7315 12:23:46.192270 [CA 5] Center 35 (5~65) winsize 61
7316 12:23:46.192823
7317 12:23:46.195510 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7318 12:23:46.196339
7319 12:23:46.202291 [CATrainingPosCal] consider 1 rank data
7320 12:23:46.202845 u2DelayCellTimex100 = 271/100 ps
7321 12:23:46.208837 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7322 12:23:46.212349 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7323 12:23:46.215201 CA2 delay=37 (7~67),Diff = 2 PI (7 cell)
7324 12:23:46.218799 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7325 12:23:46.221798 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7326 12:23:46.225441 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7327 12:23:46.225990
7328 12:23:46.228786 CA PerBit enable=1, Macro0, CA PI delay=35
7329 12:23:46.229337
7330 12:23:46.232069 [CBTSetCACLKResult] CA Dly = 35
7331 12:23:46.235291 CS Dly: 11 (0~42)
7332 12:23:46.238450 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7333 12:23:46.242124 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7334 12:23:46.242675 ==
7335 12:23:46.245256 Dram Type= 6, Freq= 0, CH_0, rank 1
7336 12:23:46.248459 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7337 12:23:46.252319 ==
7338 12:23:46.255627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7339 12:23:46.258319 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7340 12:23:46.265126 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7341 12:23:46.271970 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7342 12:23:46.278521 [CA 0] Center 42 (12~73) winsize 62
7343 12:23:46.282288 [CA 1] Center 41 (11~72) winsize 62
7344 12:23:46.284667 [CA 2] Center 38 (9~68) winsize 60
7345 12:23:46.288351 [CA 3] Center 37 (7~67) winsize 61
7346 12:23:46.291607 [CA 4] Center 35 (5~65) winsize 61
7347 12:23:46.295068 [CA 5] Center 35 (5~66) winsize 62
7348 12:23:46.295614
7349 12:23:46.298339 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7350 12:23:46.298888
7351 12:23:46.301945 [CATrainingPosCal] consider 2 rank data
7352 12:23:46.304802 u2DelayCellTimex100 = 271/100 ps
7353 12:23:46.308400 CA0 delay=42 (12~72),Diff = 7 PI (25 cell)
7354 12:23:46.314952 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7355 12:23:46.318286 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7356 12:23:46.321283 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7357 12:23:46.325178 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7358 12:23:46.328195 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7359 12:23:46.328757
7360 12:23:46.331422 CA PerBit enable=1, Macro0, CA PI delay=35
7361 12:23:46.331877
7362 12:23:46.334322 [CBTSetCACLKResult] CA Dly = 35
7363 12:23:46.337628 CS Dly: 11 (0~43)
7364 12:23:46.341312 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7365 12:23:46.344300 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7366 12:23:46.344755
7367 12:23:46.347732 ----->DramcWriteLeveling(PI) begin...
7368 12:23:46.348144 ==
7369 12:23:46.350975 Dram Type= 6, Freq= 0, CH_0, rank 0
7370 12:23:46.357911 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7371 12:23:46.358477 ==
7372 12:23:46.361616 Write leveling (Byte 0): 29 => 29
7373 12:23:46.362493 Write leveling (Byte 1): 24 => 24
7374 12:23:46.364264 DramcWriteLeveling(PI) end<-----
7375 12:23:46.364640
7376 12:23:46.367730 ==
7377 12:23:46.368303 Dram Type= 6, Freq= 0, CH_0, rank 0
7378 12:23:46.373878 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7379 12:23:46.374415 ==
7380 12:23:46.377725 [Gating] SW mode calibration
7381 12:23:46.384123 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7382 12:23:46.387231 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7383 12:23:46.393996 0 12 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7384 12:23:46.397313 0 12 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7385 12:23:46.400876 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7386 12:23:46.407190 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7387 12:23:46.410557 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7388 12:23:46.414127 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7389 12:23:46.420737 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7390 12:23:46.423756 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7391 12:23:46.427797 0 13 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7392 12:23:46.433938 0 13 4 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7393 12:23:46.437124 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7394 12:23:46.440748 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7395 12:23:46.447417 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7396 12:23:46.451082 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7397 12:23:46.453690 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7398 12:23:46.460256 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7399 12:23:46.464153 0 14 0 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7400 12:23:46.466924 0 14 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7401 12:23:46.474218 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7402 12:23:46.476990 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7403 12:23:46.480262 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7404 12:23:46.483868 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7405 12:23:46.490134 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7406 12:23:46.493412 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7407 12:23:46.497099 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7408 12:23:46.504134 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7409 12:23:46.507360 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7410 12:23:46.510351 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7411 12:23:46.516892 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7412 12:23:46.520283 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7413 12:23:46.523344 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7414 12:23:46.529793 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7415 12:23:46.533311 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7416 12:23:46.536513 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7417 12:23:46.543226 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7418 12:23:46.546582 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7419 12:23:46.549571 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7420 12:23:46.556636 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 12:23:46.559600 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 12:23:46.563248 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7423 12:23:46.569540 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7424 12:23:46.573305 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7425 12:23:46.576206 Total UI for P1: 0, mck2ui 16
7426 12:23:46.580013 best dqsien dly found for B0: ( 1, 0, 30)
7427 12:23:46.583081 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7428 12:23:46.586044 Total UI for P1: 0, mck2ui 16
7429 12:23:46.589775 best dqsien dly found for B1: ( 1, 1, 4)
7430 12:23:46.593172 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7431 12:23:46.596306 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7432 12:23:46.596882
7433 12:23:46.603197 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7434 12:23:46.606302 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7435 12:23:46.606846 [Gating] SW calibration Done
7436 12:23:46.609854 ==
7437 12:23:46.613153 Dram Type= 6, Freq= 0, CH_0, rank 0
7438 12:23:46.616005 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7439 12:23:46.616489 ==
7440 12:23:46.616850 RX Vref Scan: 0
7441 12:23:46.617184
7442 12:23:46.619654 RX Vref 0 -> 0, step: 1
7443 12:23:46.620238
7444 12:23:46.622590 RX Delay 0 -> 252, step: 8
7445 12:23:46.626254 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7446 12:23:46.629456 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7447 12:23:46.632513 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7448 12:23:46.639028 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7449 12:23:46.642505 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7450 12:23:46.646126 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7451 12:23:46.648917 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7452 12:23:46.652312 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7453 12:23:46.658781 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7454 12:23:46.662459 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7455 12:23:46.665729 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7456 12:23:46.669020 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7457 12:23:46.676040 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7458 12:23:46.678976 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7459 12:23:46.682348 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7460 12:23:46.685618 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7461 12:23:46.686071 ==
7462 12:23:46.689062 Dram Type= 6, Freq= 0, CH_0, rank 0
7463 12:23:46.692150 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7464 12:23:46.695801 ==
7465 12:23:46.696399 DQS Delay:
7466 12:23:46.696766 DQS0 = 0, DQS1 = 0
7467 12:23:46.698914 DQM Delay:
7468 12:23:46.699381 DQM0 = 129, DQM1 = 124
7469 12:23:46.702366 DQ Delay:
7470 12:23:46.705648 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7471 12:23:46.709012 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7472 12:23:46.712221 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7473 12:23:46.715968 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7474 12:23:46.716568
7475 12:23:46.716930
7476 12:23:46.717262 ==
7477 12:23:46.718706 Dram Type= 6, Freq= 0, CH_0, rank 0
7478 12:23:46.721996 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7479 12:23:46.725199 ==
7480 12:23:46.725743
7481 12:23:46.726098
7482 12:23:46.726427 TX Vref Scan disable
7483 12:23:46.728719 == TX Byte 0 ==
7484 12:23:46.732081 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7485 12:23:46.735523 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7486 12:23:46.738329 == TX Byte 1 ==
7487 12:23:46.742132 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7488 12:23:46.744998 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
7489 12:23:46.748122 ==
7490 12:23:46.748624 Dram Type= 6, Freq= 0, CH_0, rank 0
7491 12:23:46.755163 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7492 12:23:46.755713 ==
7493 12:23:46.768610
7494 12:23:46.772318 TX Vref early break, caculate TX vref
7495 12:23:46.775139 TX Vref=16, minBit 8, minWin=22, winSum=370
7496 12:23:46.778207 TX Vref=18, minBit 8, minWin=23, winSum=383
7497 12:23:46.781879 TX Vref=20, minBit 9, minWin=23, winSum=389
7498 12:23:46.784797 TX Vref=22, minBit 4, minWin=24, winSum=397
7499 12:23:46.788312 TX Vref=24, minBit 8, minWin=24, winSum=408
7500 12:23:46.795230 TX Vref=26, minBit 4, minWin=25, winSum=413
7501 12:23:46.798616 TX Vref=28, minBit 4, minWin=25, winSum=415
7502 12:23:46.801495 TX Vref=30, minBit 8, minWin=24, winSum=411
7503 12:23:46.804806 TX Vref=32, minBit 6, minWin=24, winSum=400
7504 12:23:46.808357 TX Vref=34, minBit 1, minWin=24, winSum=394
7505 12:23:46.811652 TX Vref=36, minBit 6, minWin=23, winSum=383
7506 12:23:46.818471 [TxChooseVref] Worse bit 4, Min win 25, Win sum 415, Final Vref 28
7507 12:23:46.819017
7508 12:23:46.821696 Final TX Range 0 Vref 28
7509 12:23:46.822243
7510 12:23:46.822604 ==
7511 12:23:46.824948 Dram Type= 6, Freq= 0, CH_0, rank 0
7512 12:23:46.828430 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7513 12:23:46.828982 ==
7514 12:23:46.829344
7515 12:23:46.829675
7516 12:23:46.831490 TX Vref Scan disable
7517 12:23:46.838280 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7518 12:23:46.838813 == TX Byte 0 ==
7519 12:23:46.841648 u2DelayCellOfst[0]=10 cells (3 PI)
7520 12:23:46.844893 u2DelayCellOfst[1]=18 cells (5 PI)
7521 12:23:46.847937 u2DelayCellOfst[2]=14 cells (4 PI)
7522 12:23:46.851597 u2DelayCellOfst[3]=10 cells (3 PI)
7523 12:23:46.854857 u2DelayCellOfst[4]=10 cells (3 PI)
7524 12:23:46.857917 u2DelayCellOfst[5]=0 cells (0 PI)
7525 12:23:46.861275 u2DelayCellOfst[6]=18 cells (5 PI)
7526 12:23:46.864778 u2DelayCellOfst[7]=18 cells (5 PI)
7527 12:23:46.868151 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7528 12:23:46.871421 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7529 12:23:46.875046 == TX Byte 1 ==
7530 12:23:46.877849 u2DelayCellOfst[8]=0 cells (0 PI)
7531 12:23:46.881227 u2DelayCellOfst[9]=0 cells (0 PI)
7532 12:23:46.881680 u2DelayCellOfst[10]=7 cells (2 PI)
7533 12:23:46.884582 u2DelayCellOfst[11]=3 cells (1 PI)
7534 12:23:46.887963 u2DelayCellOfst[12]=14 cells (4 PI)
7535 12:23:46.891168 u2DelayCellOfst[13]=14 cells (4 PI)
7536 12:23:46.894400 u2DelayCellOfst[14]=18 cells (5 PI)
7537 12:23:46.897747 u2DelayCellOfst[15]=14 cells (4 PI)
7538 12:23:46.904745 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
7539 12:23:46.907578 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
7540 12:23:46.908032 DramC Write-DBI on
7541 12:23:46.908436 ==
7542 12:23:46.911336 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 12:23:46.917885 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7544 12:23:46.918434 ==
7545 12:23:46.918794
7546 12:23:46.919126
7547 12:23:46.919441 TX Vref Scan disable
7548 12:23:46.922033 == TX Byte 0 ==
7549 12:23:46.925121 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7550 12:23:46.928827 == TX Byte 1 ==
7551 12:23:46.931834 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
7552 12:23:46.935258 DramC Write-DBI off
7553 12:23:46.935802
7554 12:23:46.936159 [DATLAT]
7555 12:23:46.936536 Freq=1600, CH0 RK0
7556 12:23:46.936862
7557 12:23:46.938423 DATLAT Default: 0xf
7558 12:23:46.938879 0, 0xFFFF, sum = 0
7559 12:23:46.942619 1, 0xFFFF, sum = 0
7560 12:23:46.943167 2, 0xFFFF, sum = 0
7561 12:23:46.945149 3, 0xFFFF, sum = 0
7562 12:23:46.948551 4, 0xFFFF, sum = 0
7563 12:23:46.949100 5, 0xFFFF, sum = 0
7564 12:23:46.951736 6, 0xFFFF, sum = 0
7565 12:23:46.952329 7, 0xFFFF, sum = 0
7566 12:23:46.955470 8, 0xFFFF, sum = 0
7567 12:23:46.956025 9, 0xFFFF, sum = 0
7568 12:23:46.958533 10, 0xFFFF, sum = 0
7569 12:23:46.959086 11, 0xFFFF, sum = 0
7570 12:23:46.961492 12, 0xBFF, sum = 0
7571 12:23:46.961953 13, 0x0, sum = 1
7572 12:23:46.965390 14, 0x0, sum = 2
7573 12:23:46.965944 15, 0x0, sum = 3
7574 12:23:46.968216 16, 0x0, sum = 4
7575 12:23:46.968688 best_step = 14
7576 12:23:46.969047
7577 12:23:46.969380 ==
7578 12:23:46.971742 Dram Type= 6, Freq= 0, CH_0, rank 0
7579 12:23:46.975060 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7580 12:23:46.975607 ==
7581 12:23:46.978584 RX Vref Scan: 1
7582 12:23:46.979129
7583 12:23:46.981882 Set Vref Range= 24 -> 127
7584 12:23:46.982447
7585 12:23:46.982813 RX Vref 24 -> 127, step: 1
7586 12:23:46.983152
7587 12:23:46.984863 RX Delay 11 -> 252, step: 4
7588 12:23:46.985316
7589 12:23:46.988135 Set Vref, RX VrefLevel [Byte0]: 24
7590 12:23:46.991373 [Byte1]: 24
7591 12:23:46.995147
7592 12:23:46.995694 Set Vref, RX VrefLevel [Byte0]: 25
7593 12:23:46.998180 [Byte1]: 25
7594 12:23:47.002977
7595 12:23:47.003430 Set Vref, RX VrefLevel [Byte0]: 26
7596 12:23:47.006790 [Byte1]: 26
7597 12:23:47.010565
7598 12:23:47.011109 Set Vref, RX VrefLevel [Byte0]: 27
7599 12:23:47.013497 [Byte1]: 27
7600 12:23:47.018530
7601 12:23:47.019074 Set Vref, RX VrefLevel [Byte0]: 28
7602 12:23:47.022773 [Byte1]: 28
7603 12:23:47.025547
7604 12:23:47.026002 Set Vref, RX VrefLevel [Byte0]: 29
7605 12:23:47.029152 [Byte1]: 29
7606 12:23:47.033481
7607 12:23:47.034029 Set Vref, RX VrefLevel [Byte0]: 30
7608 12:23:47.036288 [Byte1]: 30
7609 12:23:47.040796
7610 12:23:47.041268 Set Vref, RX VrefLevel [Byte0]: 31
7611 12:23:47.044300 [Byte1]: 31
7612 12:23:47.048787
7613 12:23:47.049334 Set Vref, RX VrefLevel [Byte0]: 32
7614 12:23:47.051961 [Byte1]: 32
7615 12:23:47.056328
7616 12:23:47.056872 Set Vref, RX VrefLevel [Byte0]: 33
7617 12:23:47.059287 [Byte1]: 33
7618 12:23:47.063839
7619 12:23:47.064454 Set Vref, RX VrefLevel [Byte0]: 34
7620 12:23:47.067045 [Byte1]: 34
7621 12:23:47.071361
7622 12:23:47.071908 Set Vref, RX VrefLevel [Byte0]: 35
7623 12:23:47.075102 [Byte1]: 35
7624 12:23:47.078812
7625 12:23:47.079361 Set Vref, RX VrefLevel [Byte0]: 36
7626 12:23:47.082076 [Byte1]: 36
7627 12:23:47.086854
7628 12:23:47.087400 Set Vref, RX VrefLevel [Byte0]: 37
7629 12:23:47.089676 [Byte1]: 37
7630 12:23:47.093961
7631 12:23:47.094514 Set Vref, RX VrefLevel [Byte0]: 38
7632 12:23:47.097354 [Byte1]: 38
7633 12:23:47.101710
7634 12:23:47.102286 Set Vref, RX VrefLevel [Byte0]: 39
7635 12:23:47.105251 [Byte1]: 39
7636 12:23:47.109468
7637 12:23:47.110013 Set Vref, RX VrefLevel [Byte0]: 40
7638 12:23:47.112608 [Byte1]: 40
7639 12:23:47.117125
7640 12:23:47.117672 Set Vref, RX VrefLevel [Byte0]: 41
7641 12:23:47.120155 [Byte1]: 41
7642 12:23:47.124527
7643 12:23:47.125209 Set Vref, RX VrefLevel [Byte0]: 42
7644 12:23:47.127851 [Byte1]: 42
7645 12:23:47.132220
7646 12:23:47.132770 Set Vref, RX VrefLevel [Byte0]: 43
7647 12:23:47.135393 [Byte1]: 43
7648 12:23:47.139845
7649 12:23:47.140335 Set Vref, RX VrefLevel [Byte0]: 44
7650 12:23:47.142997 [Byte1]: 44
7651 12:23:47.147481
7652 12:23:47.148023 Set Vref, RX VrefLevel [Byte0]: 45
7653 12:23:47.150657 [Byte1]: 45
7654 12:23:47.155565
7655 12:23:47.156105 Set Vref, RX VrefLevel [Byte0]: 46
7656 12:23:47.158686 [Byte1]: 46
7657 12:23:47.162664
7658 12:23:47.163115 Set Vref, RX VrefLevel [Byte0]: 47
7659 12:23:47.166235 [Byte1]: 47
7660 12:23:47.170254
7661 12:23:47.170795 Set Vref, RX VrefLevel [Byte0]: 48
7662 12:23:47.173566 [Byte1]: 48
7663 12:23:47.178108
7664 12:23:47.178649 Set Vref, RX VrefLevel [Byte0]: 49
7665 12:23:47.181369 [Byte1]: 49
7666 12:23:47.185542
7667 12:23:47.186080 Set Vref, RX VrefLevel [Byte0]: 50
7668 12:23:47.188485 [Byte1]: 50
7669 12:23:47.193021
7670 12:23:47.193471 Set Vref, RX VrefLevel [Byte0]: 51
7671 12:23:47.196248 [Byte1]: 51
7672 12:23:47.200744
7673 12:23:47.201209 Set Vref, RX VrefLevel [Byte0]: 52
7674 12:23:47.204244 [Byte1]: 52
7675 12:23:47.208285
7676 12:23:47.208958 Set Vref, RX VrefLevel [Byte0]: 53
7677 12:23:47.211236 [Byte1]: 53
7678 12:23:47.215613
7679 12:23:47.216064 Set Vref, RX VrefLevel [Byte0]: 54
7680 12:23:47.219222 [Byte1]: 54
7681 12:23:47.223537
7682 12:23:47.224123 Set Vref, RX VrefLevel [Byte0]: 55
7683 12:23:47.227114 [Byte1]: 55
7684 12:23:47.231081
7685 12:23:47.231625 Set Vref, RX VrefLevel [Byte0]: 56
7686 12:23:47.234239 [Byte1]: 56
7687 12:23:47.238608
7688 12:23:47.239153 Set Vref, RX VrefLevel [Byte0]: 57
7689 12:23:47.242250 [Byte1]: 57
7690 12:23:47.246386
7691 12:23:47.246928 Set Vref, RX VrefLevel [Byte0]: 58
7692 12:23:47.249777 [Byte1]: 58
7693 12:23:47.254011
7694 12:23:47.254462 Set Vref, RX VrefLevel [Byte0]: 59
7695 12:23:47.257337 [Byte1]: 59
7696 12:23:47.261902
7697 12:23:47.262582 Set Vref, RX VrefLevel [Byte0]: 60
7698 12:23:47.264763 [Byte1]: 60
7699 12:23:47.268891
7700 12:23:47.269344 Set Vref, RX VrefLevel [Byte0]: 61
7701 12:23:47.272606 [Byte1]: 61
7702 12:23:47.276557
7703 12:23:47.277010 Set Vref, RX VrefLevel [Byte0]: 62
7704 12:23:47.279890 [Byte1]: 62
7705 12:23:47.284627
7706 12:23:47.285174 Set Vref, RX VrefLevel [Byte0]: 63
7707 12:23:47.287932 [Byte1]: 63
7708 12:23:47.291951
7709 12:23:47.292446 Set Vref, RX VrefLevel [Byte0]: 64
7710 12:23:47.295342 [Byte1]: 64
7711 12:23:47.299535
7712 12:23:47.300083 Set Vref, RX VrefLevel [Byte0]: 65
7713 12:23:47.302653 [Byte1]: 65
7714 12:23:47.307046
7715 12:23:47.307599 Set Vref, RX VrefLevel [Byte0]: 66
7716 12:23:47.310849 [Byte1]: 66
7717 12:23:47.314596
7718 12:23:47.315048 Set Vref, RX VrefLevel [Byte0]: 67
7719 12:23:47.318045 [Byte1]: 67
7720 12:23:47.322798
7721 12:23:47.323341 Set Vref, RX VrefLevel [Byte0]: 68
7722 12:23:47.325634 [Byte1]: 68
7723 12:23:47.329829
7724 12:23:47.330277 Set Vref, RX VrefLevel [Byte0]: 69
7725 12:23:47.333240 [Byte1]: 69
7726 12:23:47.338028
7727 12:23:47.338573 Set Vref, RX VrefLevel [Byte0]: 70
7728 12:23:47.341212 [Byte1]: 70
7729 12:23:47.345362
7730 12:23:47.345908 Set Vref, RX VrefLevel [Byte0]: 71
7731 12:23:47.348532 [Byte1]: 71
7732 12:23:47.352709
7733 12:23:47.353157 Final RX Vref Byte 0 = 54 to rank0
7734 12:23:47.356500 Final RX Vref Byte 1 = 54 to rank0
7735 12:23:47.359533 Final RX Vref Byte 0 = 54 to rank1
7736 12:23:47.363152 Final RX Vref Byte 1 = 54 to rank1==
7737 12:23:47.366152 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 12:23:47.372766 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7739 12:23:47.373224 ==
7740 12:23:47.373587 DQS Delay:
7741 12:23:47.373921 DQS0 = 0, DQS1 = 0
7742 12:23:47.376241 DQM Delay:
7743 12:23:47.376694 DQM0 = 126, DQM1 = 120
7744 12:23:47.379327 DQ Delay:
7745 12:23:47.383021 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7746 12:23:47.386158 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7747 12:23:47.389583 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7748 12:23:47.392616 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7749 12:23:47.393070
7750 12:23:47.393428
7751 12:23:47.393758
7752 12:23:47.395900 [DramC_TX_OE_Calibration] TA2
7753 12:23:47.399773 Original DQ_B0 (3 6) =30, OEN = 27
7754 12:23:47.402786 Original DQ_B1 (3 6) =30, OEN = 27
7755 12:23:47.406036 24, 0x0, End_B0=24 End_B1=24
7756 12:23:47.406593 25, 0x0, End_B0=25 End_B1=25
7757 12:23:47.409381 26, 0x0, End_B0=26 End_B1=26
7758 12:23:47.412471 27, 0x0, End_B0=27 End_B1=27
7759 12:23:47.416049 28, 0x0, End_B0=28 End_B1=28
7760 12:23:47.419826 29, 0x0, End_B0=29 End_B1=29
7761 12:23:47.420431 30, 0x0, End_B0=30 End_B1=30
7762 12:23:47.422672 31, 0x4141, End_B0=30 End_B1=30
7763 12:23:47.425926 Byte0 end_step=30 best_step=27
7764 12:23:47.429654 Byte1 end_step=30 best_step=27
7765 12:23:47.433021 Byte0 TX OE(2T, 0.5T) = (3, 3)
7766 12:23:47.433568 Byte1 TX OE(2T, 0.5T) = (3, 3)
7767 12:23:47.436097
7768 12:23:47.436683
7769 12:23:47.442883 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7770 12:23:47.446240 CH0 RK0: MR19=303, MR18=1919
7771 12:23:47.452786 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7772 12:23:47.453325
7773 12:23:47.456477 ----->DramcWriteLeveling(PI) begin...
7774 12:23:47.457049 ==
7775 12:23:47.459708 Dram Type= 6, Freq= 0, CH_0, rank 1
7776 12:23:47.462632 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7777 12:23:47.463088 ==
7778 12:23:47.465911 Write leveling (Byte 0): 27 => 27
7779 12:23:47.469110 Write leveling (Byte 1): 25 => 25
7780 12:23:47.472158 DramcWriteLeveling(PI) end<-----
7781 12:23:47.472641
7782 12:23:47.473000 ==
7783 12:23:47.475985 Dram Type= 6, Freq= 0, CH_0, rank 1
7784 12:23:47.478998 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7785 12:23:47.479454 ==
7786 12:23:47.483134 [Gating] SW mode calibration
7787 12:23:47.488843 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7788 12:23:47.495720 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7789 12:23:47.498793 0 12 0 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7790 12:23:47.502393 0 12 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7791 12:23:47.508588 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7792 12:23:47.512277 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7793 12:23:47.515443 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7794 12:23:47.522517 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7795 12:23:47.525398 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7796 12:23:47.528706 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7797 12:23:47.535427 0 13 0 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
7798 12:23:47.538709 0 13 4 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
7799 12:23:47.541844 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7800 12:23:47.548710 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7801 12:23:47.552300 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7802 12:23:47.555805 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7803 12:23:47.561941 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7804 12:23:47.564853 0 13 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7805 12:23:47.568162 0 14 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7806 12:23:47.575139 0 14 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7807 12:23:47.578292 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7808 12:23:47.581607 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7809 12:23:47.589012 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7810 12:23:47.591701 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7811 12:23:47.595284 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7812 12:23:47.601123 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7813 12:23:47.604474 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7814 12:23:47.608043 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7815 12:23:47.614526 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7816 12:23:47.617739 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7817 12:23:47.621126 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7818 12:23:47.627708 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7819 12:23:47.631351 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7820 12:23:47.634133 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7821 12:23:47.641019 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7822 12:23:47.644143 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7823 12:23:47.647422 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 12:23:47.654420 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 12:23:47.657814 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 12:23:47.660634 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 12:23:47.667548 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7828 12:23:47.670567 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7829 12:23:47.674135 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7830 12:23:47.680696 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7831 12:23:47.681245 Total UI for P1: 0, mck2ui 16
7832 12:23:47.687310 best dqsien dly found for B0: ( 1, 0, 28)
7833 12:23:47.690852 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7834 12:23:47.693687 Total UI for P1: 0, mck2ui 16
7835 12:23:47.696956 best dqsien dly found for B1: ( 1, 1, 2)
7836 12:23:47.700567 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7837 12:23:47.703733 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7838 12:23:47.704341
7839 12:23:47.707151 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7840 12:23:47.710620 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7841 12:23:47.714300 [Gating] SW calibration Done
7842 12:23:47.714866 ==
7843 12:23:47.716640 Dram Type= 6, Freq= 0, CH_0, rank 1
7844 12:23:47.720370 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7845 12:23:47.723816 ==
7846 12:23:47.724503 RX Vref Scan: 0
7847 12:23:47.724924
7848 12:23:47.727173 RX Vref 0 -> 0, step: 1
7849 12:23:47.727727
7850 12:23:47.729924 RX Delay 0 -> 252, step: 8
7851 12:23:47.733290 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7852 12:23:47.736704 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7853 12:23:47.740426 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7854 12:23:47.743506 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7855 12:23:47.750019 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7856 12:23:47.753176 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7857 12:23:47.756563 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7858 12:23:47.759929 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7859 12:23:47.763475 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7860 12:23:47.769634 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7861 12:23:47.773144 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7862 12:23:47.776469 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7863 12:23:47.779886 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7864 12:23:47.783162 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7865 12:23:47.789627 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7866 12:23:47.793105 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7867 12:23:47.793657 ==
7868 12:23:47.795983 Dram Type= 6, Freq= 0, CH_0, rank 1
7869 12:23:47.799628 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7870 12:23:47.800235 ==
7871 12:23:47.802615 DQS Delay:
7872 12:23:47.803164 DQS0 = 0, DQS1 = 0
7873 12:23:47.803526 DQM Delay:
7874 12:23:47.806370 DQM0 = 130, DQM1 = 124
7875 12:23:47.806922 DQ Delay:
7876 12:23:47.809606 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7877 12:23:47.812923 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7878 12:23:47.819378 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7879 12:23:47.822632 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7880 12:23:47.823195
7881 12:23:47.823555
7882 12:23:47.823889 ==
7883 12:23:47.825777 Dram Type= 6, Freq= 0, CH_0, rank 1
7884 12:23:47.829048 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7885 12:23:47.829505 ==
7886 12:23:47.829865
7887 12:23:47.830194
7888 12:23:47.832273 TX Vref Scan disable
7889 12:23:47.835547 == TX Byte 0 ==
7890 12:23:47.839231 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7891 12:23:47.842365 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7892 12:23:47.845723 == TX Byte 1 ==
7893 12:23:47.849076 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7894 12:23:47.852536 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7895 12:23:47.853216 ==
7896 12:23:47.856161 Dram Type= 6, Freq= 0, CH_0, rank 1
7897 12:23:47.859022 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7898 12:23:47.862749 ==
7899 12:23:47.873464
7900 12:23:47.876675 TX Vref early break, caculate TX vref
7901 12:23:47.880021 TX Vref=16, minBit 8, minWin=22, winSum=376
7902 12:23:47.883299 TX Vref=18, minBit 8, minWin=22, winSum=385
7903 12:23:47.886483 TX Vref=20, minBit 11, minWin=23, winSum=395
7904 12:23:47.889653 TX Vref=22, minBit 1, minWin=24, winSum=402
7905 12:23:47.893265 TX Vref=24, minBit 1, minWin=25, winSum=409
7906 12:23:47.899617 TX Vref=26, minBit 8, minWin=25, winSum=416
7907 12:23:47.903326 TX Vref=28, minBit 8, minWin=24, winSum=420
7908 12:23:47.906425 TX Vref=30, minBit 8, minWin=25, winSum=413
7909 12:23:47.909966 TX Vref=32, minBit 8, minWin=24, winSum=408
7910 12:23:47.913125 TX Vref=34, minBit 8, minWin=23, winSum=398
7911 12:23:47.919827 [TxChooseVref] Worse bit 8, Min win 25, Win sum 416, Final Vref 26
7912 12:23:47.920415
7913 12:23:47.923118 Final TX Range 0 Vref 26
7914 12:23:47.923671
7915 12:23:47.924032 ==
7916 12:23:47.926110 Dram Type= 6, Freq= 0, CH_0, rank 1
7917 12:23:47.929689 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7918 12:23:47.930145 ==
7919 12:23:47.930502
7920 12:23:47.930834
7921 12:23:47.932873 TX Vref Scan disable
7922 12:23:47.939979 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7923 12:23:47.940657 == TX Byte 0 ==
7924 12:23:47.943350 u2DelayCellOfst[0]=14 cells (4 PI)
7925 12:23:47.946144 u2DelayCellOfst[1]=21 cells (6 PI)
7926 12:23:47.949894 u2DelayCellOfst[2]=14 cells (4 PI)
7927 12:23:47.952862 u2DelayCellOfst[3]=10 cells (3 PI)
7928 12:23:47.956340 u2DelayCellOfst[4]=10 cells (3 PI)
7929 12:23:47.959803 u2DelayCellOfst[5]=0 cells (0 PI)
7930 12:23:47.962946 u2DelayCellOfst[6]=18 cells (5 PI)
7931 12:23:47.966246 u2DelayCellOfst[7]=18 cells (5 PI)
7932 12:23:47.969358 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7933 12:23:47.972739 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7934 12:23:47.976289 == TX Byte 1 ==
7935 12:23:47.979755 u2DelayCellOfst[8]=0 cells (0 PI)
7936 12:23:47.980361 u2DelayCellOfst[9]=0 cells (0 PI)
7937 12:23:47.982919 u2DelayCellOfst[10]=7 cells (2 PI)
7938 12:23:47.986251 u2DelayCellOfst[11]=3 cells (1 PI)
7939 12:23:47.989270 u2DelayCellOfst[12]=14 cells (4 PI)
7940 12:23:47.992873 u2DelayCellOfst[13]=14 cells (4 PI)
7941 12:23:47.996403 u2DelayCellOfst[14]=18 cells (5 PI)
7942 12:23:47.999193 u2DelayCellOfst[15]=14 cells (4 PI)
7943 12:23:48.002703 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7944 12:23:48.009317 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7945 12:23:48.009866 DramC Write-DBI on
7946 12:23:48.010228 ==
7947 12:23:48.012933 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 12:23:48.019198 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7949 12:23:48.019750 ==
7950 12:23:48.020115
7951 12:23:48.020511
7952 12:23:48.020835 TX Vref Scan disable
7953 12:23:48.023046 == TX Byte 0 ==
7954 12:23:48.025842 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7955 12:23:48.029457 == TX Byte 1 ==
7956 12:23:48.032903 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7957 12:23:48.036130 DramC Write-DBI off
7958 12:23:48.036745
7959 12:23:48.037106 [DATLAT]
7960 12:23:48.037441 Freq=1600, CH0 RK1
7961 12:23:48.037767
7962 12:23:48.039235 DATLAT Default: 0xe
7963 12:23:48.039687 0, 0xFFFF, sum = 0
7964 12:23:48.042611 1, 0xFFFF, sum = 0
7965 12:23:48.045906 2, 0xFFFF, sum = 0
7966 12:23:48.046435 3, 0xFFFF, sum = 0
7967 12:23:48.049090 4, 0xFFFF, sum = 0
7968 12:23:48.049574 5, 0xFFFF, sum = 0
7969 12:23:48.053056 6, 0xFFFF, sum = 0
7970 12:23:48.053650 7, 0xFFFF, sum = 0
7971 12:23:48.056433 8, 0xFFFF, sum = 0
7972 12:23:48.057049 9, 0xFFFF, sum = 0
7973 12:23:48.059596 10, 0xFFFF, sum = 0
7974 12:23:48.060168 11, 0xFFFF, sum = 0
7975 12:23:48.062503 12, 0x8FFF, sum = 0
7976 12:23:48.063090 13, 0x0, sum = 1
7977 12:23:48.065802 14, 0x0, sum = 2
7978 12:23:48.066283 15, 0x0, sum = 3
7979 12:23:48.069530 16, 0x0, sum = 4
7980 12:23:48.070112 best_step = 14
7981 12:23:48.070602
7982 12:23:48.071060 ==
7983 12:23:48.072427 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 12:23:48.075838 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7985 12:23:48.079445 ==
7986 12:23:48.080021 RX Vref Scan: 0
7987 12:23:48.080553
7988 12:23:48.082442 RX Vref 0 -> 0, step: 1
7989 12:23:48.082916
7990 12:23:48.083400 RX Delay 11 -> 252, step: 4
7991 12:23:48.089944 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7992 12:23:48.093462 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7993 12:23:48.096761 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7994 12:23:48.100334 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
7995 12:23:48.103523 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7996 12:23:48.110076 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7997 12:23:48.113107 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
7998 12:23:48.116746 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7999 12:23:48.119848 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
8000 12:23:48.123420 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8001 12:23:48.130100 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8002 12:23:48.133281 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8003 12:23:48.136313 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8004 12:23:48.139452 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8005 12:23:48.146728 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8006 12:23:48.149665 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8007 12:23:48.150122 ==
8008 12:23:48.153428 Dram Type= 6, Freq= 0, CH_0, rank 1
8009 12:23:48.156409 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8010 12:23:48.156869 ==
8011 12:23:48.157227 DQS Delay:
8012 12:23:48.160006 DQS0 = 0, DQS1 = 0
8013 12:23:48.160605 DQM Delay:
8014 12:23:48.162885 DQM0 = 128, DQM1 = 120
8015 12:23:48.163339 DQ Delay:
8016 12:23:48.166248 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
8017 12:23:48.169287 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =138
8018 12:23:48.172727 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
8019 12:23:48.179492 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =130
8020 12:23:48.180044
8021 12:23:48.180471
8022 12:23:48.180811
8023 12:23:48.181130 [DramC_TX_OE_Calibration] TA2
8024 12:23:48.182628 Original DQ_B0 (3 6) =30, OEN = 27
8025 12:23:48.186226 Original DQ_B1 (3 6) =30, OEN = 27
8026 12:23:48.189367 24, 0x0, End_B0=24 End_B1=24
8027 12:23:48.192793 25, 0x0, End_B0=25 End_B1=25
8028 12:23:48.196246 26, 0x0, End_B0=26 End_B1=26
8029 12:23:48.199379 27, 0x0, End_B0=27 End_B1=27
8030 12:23:48.199946 28, 0x0, End_B0=28 End_B1=28
8031 12:23:48.202531 29, 0x0, End_B0=29 End_B1=29
8032 12:23:48.206732 30, 0x0, End_B0=30 End_B1=30
8033 12:23:48.209376 31, 0x4545, End_B0=30 End_B1=30
8034 12:23:48.213009 Byte0 end_step=30 best_step=27
8035 12:23:48.213559 Byte1 end_step=30 best_step=27
8036 12:23:48.216158 Byte0 TX OE(2T, 0.5T) = (3, 3)
8037 12:23:48.219388 Byte1 TX OE(2T, 0.5T) = (3, 3)
8038 12:23:48.219980
8039 12:23:48.220405
8040 12:23:48.229602 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8041 12:23:48.230155 CH0 RK1: MR19=303, MR18=1F1F
8042 12:23:48.235988 CH0_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8043 12:23:48.239249 [RxdqsGatingPostProcess] freq 1600
8044 12:23:48.246078 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8045 12:23:48.249015 Pre-setting of DQS Precalculation
8046 12:23:48.252707 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8047 12:23:48.253257 ==
8048 12:23:48.256149 Dram Type= 6, Freq= 0, CH_1, rank 0
8049 12:23:48.259395 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8050 12:23:48.262584 ==
8051 12:23:48.266205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8052 12:23:48.269513 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8053 12:23:48.275649 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8054 12:23:48.282155 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8055 12:23:48.289106 [CA 0] Center 41 (11~71) winsize 61
8056 12:23:48.292077 [CA 1] Center 41 (11~72) winsize 62
8057 12:23:48.295345 [CA 2] Center 37 (8~67) winsize 60
8058 12:23:48.299601 [CA 3] Center 36 (7~66) winsize 60
8059 12:23:48.302152 [CA 4] Center 34 (4~64) winsize 61
8060 12:23:48.305645 [CA 5] Center 34 (5~64) winsize 60
8061 12:23:48.306199
8062 12:23:48.308798 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8063 12:23:48.309255
8064 12:23:48.312048 [CATrainingPosCal] consider 1 rank data
8065 12:23:48.315465 u2DelayCellTimex100 = 271/100 ps
8066 12:23:48.318516 CA0 delay=41 (11~71),Diff = 7 PI (25 cell)
8067 12:23:48.325499 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8068 12:23:48.328245 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8069 12:23:48.332112 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8070 12:23:48.335269 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8071 12:23:48.338592 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8072 12:23:48.339140
8073 12:23:48.342117 CA PerBit enable=1, Macro0, CA PI delay=34
8074 12:23:48.342734
8075 12:23:48.345186 [CBTSetCACLKResult] CA Dly = 34
8076 12:23:48.348573 CS Dly: 8 (0~39)
8077 12:23:48.352081 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8078 12:23:48.355039 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8079 12:23:48.355499 ==
8080 12:23:48.358451 Dram Type= 6, Freq= 0, CH_1, rank 1
8081 12:23:48.362096 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8082 12:23:48.365195 ==
8083 12:23:48.368143 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8084 12:23:48.371603 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8085 12:23:48.378398 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8086 12:23:48.384624 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8087 12:23:48.391374 [CA 0] Center 40 (10~70) winsize 61
8088 12:23:48.394618 [CA 1] Center 39 (9~70) winsize 62
8089 12:23:48.398002 [CA 2] Center 35 (6~65) winsize 60
8090 12:23:48.401444 [CA 3] Center 35 (6~65) winsize 60
8091 12:23:48.404636 [CA 4] Center 33 (4~62) winsize 59
8092 12:23:48.407925 [CA 5] Center 32 (3~62) winsize 60
8093 12:23:48.408529
8094 12:23:48.411117 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8095 12:23:48.411667
8096 12:23:48.414339 [CATrainingPosCal] consider 2 rank data
8097 12:23:48.417860 u2DelayCellTimex100 = 271/100 ps
8098 12:23:48.421523 CA0 delay=40 (11~70),Diff = 7 PI (25 cell)
8099 12:23:48.427844 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8100 12:23:48.431202 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8101 12:23:48.434488 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8102 12:23:48.437770 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8103 12:23:48.441110 CA5 delay=33 (5~62),Diff = 0 PI (0 cell)
8104 12:23:48.441659
8105 12:23:48.444813 CA PerBit enable=1, Macro0, CA PI delay=33
8106 12:23:48.445363
8107 12:23:48.447704 [CBTSetCACLKResult] CA Dly = 33
8108 12:23:48.450678 CS Dly: 9 (0~41)
8109 12:23:48.454053 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8110 12:23:48.457778 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8111 12:23:48.458330
8112 12:23:48.460594 ----->DramcWriteLeveling(PI) begin...
8113 12:23:48.461057 ==
8114 12:23:48.464323 Dram Type= 6, Freq= 0, CH_1, rank 0
8115 12:23:48.470780 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8116 12:23:48.471321 ==
8117 12:23:48.474325 Write leveling (Byte 0): 22 => 22
8118 12:23:48.474880 Write leveling (Byte 1): 22 => 22
8119 12:23:48.477584 DramcWriteLeveling(PI) end<-----
8120 12:23:48.478141
8121 12:23:48.478503 ==
8122 12:23:48.481038 Dram Type= 6, Freq= 0, CH_1, rank 0
8123 12:23:48.487416 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8124 12:23:48.487975 ==
8125 12:23:48.490631 [Gating] SW mode calibration
8126 12:23:48.497549 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8127 12:23:48.500820 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8128 12:23:48.507514 0 12 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8129 12:23:48.510842 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8130 12:23:48.514068 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8131 12:23:48.520594 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8132 12:23:48.523742 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8133 12:23:48.526943 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8134 12:23:48.533729 0 12 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8135 12:23:48.536760 0 12 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)
8136 12:23:48.540552 0 13 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8137 12:23:48.546849 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8138 12:23:48.549996 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8139 12:23:48.553369 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8140 12:23:48.559964 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8141 12:23:48.563742 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8142 12:23:48.567105 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8143 12:23:48.573184 0 13 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8144 12:23:48.576341 0 14 0 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
8145 12:23:48.580297 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8146 12:23:48.587049 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8147 12:23:48.589890 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8148 12:23:48.593087 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8149 12:23:48.599799 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8150 12:23:48.603622 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8151 12:23:48.606381 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8152 12:23:48.609865 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8153 12:23:48.616739 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8154 12:23:48.620160 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 12:23:48.623532 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 12:23:48.629976 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 12:23:48.633189 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 12:23:48.636456 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 12:23:48.642912 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 12:23:48.647308 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8161 12:23:48.649829 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 12:23:48.656334 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 12:23:48.659561 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 12:23:48.663087 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 12:23:48.669304 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 12:23:48.672593 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8167 12:23:48.676241 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8168 12:23:48.682865 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8169 12:23:48.686367 Total UI for P1: 0, mck2ui 16
8170 12:23:48.689635 best dqsien dly found for B0: ( 1, 0, 26)
8171 12:23:48.692817 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8172 12:23:48.696143 Total UI for P1: 0, mck2ui 16
8173 12:23:48.699351 best dqsien dly found for B1: ( 1, 1, 0)
8174 12:23:48.702792 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8175 12:23:48.705755 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
8176 12:23:48.706209
8177 12:23:48.709288 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8178 12:23:48.712519 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
8179 12:23:48.715718 [Gating] SW calibration Done
8180 12:23:48.716308 ==
8181 12:23:48.719275 Dram Type= 6, Freq= 0, CH_1, rank 0
8182 12:23:48.722683 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8183 12:23:48.725914 ==
8184 12:23:48.726460 RX Vref Scan: 0
8185 12:23:48.726818
8186 12:23:48.729869 RX Vref 0 -> 0, step: 1
8187 12:23:48.730419
8188 12:23:48.730781 RX Delay 0 -> 252, step: 8
8189 12:23:48.736073 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8190 12:23:48.739290 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8191 12:23:48.742250 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8192 12:23:48.745472 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8193 12:23:48.749321 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8194 12:23:48.755637 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8195 12:23:48.758729 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8196 12:23:48.762409 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8197 12:23:48.765559 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8198 12:23:48.768874 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8199 12:23:48.775585 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8200 12:23:48.779162 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8201 12:23:48.782121 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8202 12:23:48.785789 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8203 12:23:48.792296 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8204 12:23:48.795191 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8205 12:23:48.795643 ==
8206 12:23:48.798962 Dram Type= 6, Freq= 0, CH_1, rank 0
8207 12:23:48.801871 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8208 12:23:48.802331 ==
8209 12:23:48.805150 DQS Delay:
8210 12:23:48.805603 DQS0 = 0, DQS1 = 0
8211 12:23:48.805959 DQM Delay:
8212 12:23:48.808513 DQM0 = 130, DQM1 = 126
8213 12:23:48.808967 DQ Delay:
8214 12:23:48.811979 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8215 12:23:48.815280 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8216 12:23:48.818347 DQ8 =107, DQ9 =119, DQ10 =127, DQ11 =115
8217 12:23:48.825078 DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =135
8218 12:23:48.825616
8219 12:23:48.826122
8220 12:23:48.826555 ==
8221 12:23:48.828363 Dram Type= 6, Freq= 0, CH_1, rank 0
8222 12:23:48.831893 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8223 12:23:48.832574 ==
8224 12:23:48.832941
8225 12:23:48.833273
8226 12:23:48.834712 TX Vref Scan disable
8227 12:23:48.835164 == TX Byte 0 ==
8228 12:23:48.841975 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8229 12:23:48.845296 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8230 12:23:48.845754 == TX Byte 1 ==
8231 12:23:48.851595 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8232 12:23:48.854837 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8233 12:23:48.855409 ==
8234 12:23:48.858348 Dram Type= 6, Freq= 0, CH_1, rank 0
8235 12:23:48.861607 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8236 12:23:48.862162 ==
8237 12:23:48.875161
8238 12:23:48.878267 TX Vref early break, caculate TX vref
8239 12:23:48.881387 TX Vref=16, minBit 3, minWin=21, winSum=364
8240 12:23:48.884898 TX Vref=18, minBit 3, minWin=22, winSum=376
8241 12:23:48.887847 TX Vref=20, minBit 0, minWin=23, winSum=386
8242 12:23:48.891253 TX Vref=22, minBit 3, minWin=23, winSum=392
8243 12:23:48.895059 TX Vref=24, minBit 3, minWin=24, winSum=406
8244 12:23:48.901380 TX Vref=26, minBit 1, minWin=24, winSum=409
8245 12:23:48.905052 TX Vref=28, minBit 3, minWin=24, winSum=412
8246 12:23:48.908412 TX Vref=30, minBit 5, minWin=24, winSum=405
8247 12:23:48.911431 TX Vref=32, minBit 3, minWin=23, winSum=395
8248 12:23:48.914694 TX Vref=34, minBit 1, minWin=23, winSum=387
8249 12:23:48.921448 [TxChooseVref] Worse bit 3, Min win 24, Win sum 412, Final Vref 28
8250 12:23:48.921984
8251 12:23:48.924523 Final TX Range 0 Vref 28
8252 12:23:48.924980
8253 12:23:48.925333 ==
8254 12:23:48.928013 Dram Type= 6, Freq= 0, CH_1, rank 0
8255 12:23:48.931551 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8256 12:23:48.932101 ==
8257 12:23:48.932510
8258 12:23:48.932918
8259 12:23:48.934659 TX Vref Scan disable
8260 12:23:48.941273 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8261 12:23:48.941816 == TX Byte 0 ==
8262 12:23:48.944662 u2DelayCellOfst[0]=14 cells (4 PI)
8263 12:23:48.947483 u2DelayCellOfst[1]=10 cells (3 PI)
8264 12:23:48.951199 u2DelayCellOfst[2]=0 cells (0 PI)
8265 12:23:48.954325 u2DelayCellOfst[3]=3 cells (1 PI)
8266 12:23:48.957757 u2DelayCellOfst[4]=7 cells (2 PI)
8267 12:23:48.961187 u2DelayCellOfst[5]=14 cells (4 PI)
8268 12:23:48.964298 u2DelayCellOfst[6]=14 cells (4 PI)
8269 12:23:48.964750 u2DelayCellOfst[7]=7 cells (2 PI)
8270 12:23:48.970761 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8271 12:23:48.974123 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8272 12:23:48.974575 == TX Byte 1 ==
8273 12:23:48.977433 u2DelayCellOfst[8]=0 cells (0 PI)
8274 12:23:48.980713 u2DelayCellOfst[9]=3 cells (1 PI)
8275 12:23:48.984165 u2DelayCellOfst[10]=10 cells (3 PI)
8276 12:23:48.987710 u2DelayCellOfst[11]=3 cells (1 PI)
8277 12:23:48.990706 u2DelayCellOfst[12]=18 cells (5 PI)
8278 12:23:48.994386 u2DelayCellOfst[13]=21 cells (6 PI)
8279 12:23:48.997473 u2DelayCellOfst[14]=21 cells (6 PI)
8280 12:23:49.000599 u2DelayCellOfst[15]=18 cells (5 PI)
8281 12:23:49.004122 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8282 12:23:49.010945 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8283 12:23:49.011499 DramC Write-DBI on
8284 12:23:49.011854 ==
8285 12:23:49.014066 Dram Type= 6, Freq= 0, CH_1, rank 0
8286 12:23:49.017415 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8287 12:23:49.021094 ==
8288 12:23:49.021815
8289 12:23:49.022424
8290 12:23:49.022795 TX Vref Scan disable
8291 12:23:49.023924 == TX Byte 0 ==
8292 12:23:49.027476 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8293 12:23:49.030541 == TX Byte 1 ==
8294 12:23:49.034201 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8295 12:23:49.037368 DramC Write-DBI off
8296 12:23:49.037909
8297 12:23:49.038266 [DATLAT]
8298 12:23:49.038597 Freq=1600, CH1 RK0
8299 12:23:49.038920
8300 12:23:49.040518 DATLAT Default: 0xf
8301 12:23:49.040969 0, 0xFFFF, sum = 0
8302 12:23:49.043734 1, 0xFFFF, sum = 0
8303 12:23:49.047114 2, 0xFFFF, sum = 0
8304 12:23:49.047569 3, 0xFFFF, sum = 0
8305 12:23:49.051301 4, 0xFFFF, sum = 0
8306 12:23:49.051855 5, 0xFFFF, sum = 0
8307 12:23:49.053873 6, 0xFFFF, sum = 0
8308 12:23:49.054443 7, 0xFFFF, sum = 0
8309 12:23:49.057475 8, 0xFFFF, sum = 0
8310 12:23:49.058034 9, 0xFFFF, sum = 0
8311 12:23:49.061088 10, 0xFFFF, sum = 0
8312 12:23:49.061641 11, 0xFFFF, sum = 0
8313 12:23:49.063623 12, 0x8F7F, sum = 0
8314 12:23:49.064079 13, 0x0, sum = 1
8315 12:23:49.067598 14, 0x0, sum = 2
8316 12:23:49.068150 15, 0x0, sum = 3
8317 12:23:49.070359 16, 0x0, sum = 4
8318 12:23:49.070818 best_step = 14
8319 12:23:49.071179
8320 12:23:49.071521 ==
8321 12:23:49.073768 Dram Type= 6, Freq= 0, CH_1, rank 0
8322 12:23:49.076795 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8323 12:23:49.080590 ==
8324 12:23:49.081240 RX Vref Scan: 1
8325 12:23:49.081611
8326 12:23:49.083707 Set Vref Range= 24 -> 127
8327 12:23:49.084162
8328 12:23:49.086732 RX Vref 24 -> 127, step: 1
8329 12:23:49.087185
8330 12:23:49.087542 RX Delay 3 -> 252, step: 4
8331 12:23:49.087883
8332 12:23:49.090459 Set Vref, RX VrefLevel [Byte0]: 24
8333 12:23:49.093442 [Byte1]: 24
8334 12:23:49.097111
8335 12:23:49.097561 Set Vref, RX VrefLevel [Byte0]: 25
8336 12:23:49.100648 [Byte1]: 25
8337 12:23:49.105260
8338 12:23:49.105814 Set Vref, RX VrefLevel [Byte0]: 26
8339 12:23:49.108109 [Byte1]: 26
8340 12:23:49.112933
8341 12:23:49.113619 Set Vref, RX VrefLevel [Byte0]: 27
8342 12:23:49.116351 [Byte1]: 27
8343 12:23:49.120605
8344 12:23:49.121156 Set Vref, RX VrefLevel [Byte0]: 28
8345 12:23:49.123700 [Byte1]: 28
8346 12:23:49.128214
8347 12:23:49.128781 Set Vref, RX VrefLevel [Byte0]: 29
8348 12:23:49.131243 [Byte1]: 29
8349 12:23:49.135853
8350 12:23:49.136633 Set Vref, RX VrefLevel [Byte0]: 30
8351 12:23:49.139142 [Byte1]: 30
8352 12:23:49.143324
8353 12:23:49.143876 Set Vref, RX VrefLevel [Byte0]: 31
8354 12:23:49.147344 [Byte1]: 31
8355 12:23:49.151088
8356 12:23:49.151747 Set Vref, RX VrefLevel [Byte0]: 32
8357 12:23:49.154349 [Byte1]: 32
8358 12:23:49.158611
8359 12:23:49.159161 Set Vref, RX VrefLevel [Byte0]: 33
8360 12:23:49.161552 [Byte1]: 33
8361 12:23:49.166030
8362 12:23:49.166474 Set Vref, RX VrefLevel [Byte0]: 34
8363 12:23:49.169544 [Byte1]: 34
8364 12:23:49.173940
8365 12:23:49.174838 Set Vref, RX VrefLevel [Byte0]: 35
8366 12:23:49.177326 [Byte1]: 35
8367 12:23:49.181197
8368 12:23:49.181642 Set Vref, RX VrefLevel [Byte0]: 36
8369 12:23:49.184925 [Byte1]: 36
8370 12:23:49.189079
8371 12:23:49.189528 Set Vref, RX VrefLevel [Byte0]: 37
8372 12:23:49.192320 [Byte1]: 37
8373 12:23:49.196872
8374 12:23:49.197319 Set Vref, RX VrefLevel [Byte0]: 38
8375 12:23:49.200027 [Byte1]: 38
8376 12:23:49.204250
8377 12:23:49.204701 Set Vref, RX VrefLevel [Byte0]: 39
8378 12:23:49.207642 [Byte1]: 39
8379 12:23:49.212374
8380 12:23:49.212921 Set Vref, RX VrefLevel [Byte0]: 40
8381 12:23:49.215967 [Byte1]: 40
8382 12:23:49.219724
8383 12:23:49.220345 Set Vref, RX VrefLevel [Byte0]: 41
8384 12:23:49.223112 [Byte1]: 41
8385 12:23:49.227390
8386 12:23:49.227977 Set Vref, RX VrefLevel [Byte0]: 42
8387 12:23:49.230477 [Byte1]: 42
8388 12:23:49.235197
8389 12:23:49.235761 Set Vref, RX VrefLevel [Byte0]: 43
8390 12:23:49.238722 [Byte1]: 43
8391 12:23:49.243201
8392 12:23:49.243842 Set Vref, RX VrefLevel [Byte0]: 44
8393 12:23:49.245757 [Byte1]: 44
8394 12:23:49.250710
8395 12:23:49.251256 Set Vref, RX VrefLevel [Byte0]: 45
8396 12:23:49.253592 [Byte1]: 45
8397 12:23:49.258031
8398 12:23:49.258577 Set Vref, RX VrefLevel [Byte0]: 46
8399 12:23:49.261932 [Byte1]: 46
8400 12:23:49.265874
8401 12:23:49.266420 Set Vref, RX VrefLevel [Byte0]: 47
8402 12:23:49.269439 [Byte1]: 47
8403 12:23:49.273161
8404 12:23:49.273713 Set Vref, RX VrefLevel [Byte0]: 48
8405 12:23:49.276691 [Byte1]: 48
8406 12:23:49.280919
8407 12:23:49.281366 Set Vref, RX VrefLevel [Byte0]: 49
8408 12:23:49.284146 [Byte1]: 49
8409 12:23:49.288732
8410 12:23:49.289277 Set Vref, RX VrefLevel [Byte0]: 50
8411 12:23:49.292002 [Byte1]: 50
8412 12:23:49.296740
8413 12:23:49.297285 Set Vref, RX VrefLevel [Byte0]: 51
8414 12:23:49.299428 [Byte1]: 51
8415 12:23:49.303976
8416 12:23:49.304576 Set Vref, RX VrefLevel [Byte0]: 52
8417 12:23:49.307256 [Byte1]: 52
8418 12:23:49.311930
8419 12:23:49.312540 Set Vref, RX VrefLevel [Byte0]: 53
8420 12:23:49.315027 [Byte1]: 53
8421 12:23:49.319683
8422 12:23:49.320292 Set Vref, RX VrefLevel [Byte0]: 54
8423 12:23:49.323085 [Byte1]: 54
8424 12:23:49.327533
8425 12:23:49.328097 Set Vref, RX VrefLevel [Byte0]: 55
8426 12:23:49.330032 [Byte1]: 55
8427 12:23:49.334726
8428 12:23:49.335276 Set Vref, RX VrefLevel [Byte0]: 56
8429 12:23:49.337977 [Byte1]: 56
8430 12:23:49.342885
8431 12:23:49.343434 Set Vref, RX VrefLevel [Byte0]: 57
8432 12:23:49.345455 [Byte1]: 57
8433 12:23:49.350227
8434 12:23:49.350768 Set Vref, RX VrefLevel [Byte0]: 58
8435 12:23:49.353019 [Byte1]: 58
8436 12:23:49.357268
8437 12:23:49.357734 Set Vref, RX VrefLevel [Byte0]: 59
8438 12:23:49.360848 [Byte1]: 59
8439 12:23:49.364965
8440 12:23:49.365415 Set Vref, RX VrefLevel [Byte0]: 60
8441 12:23:49.368216 [Byte1]: 60
8442 12:23:49.373137
8443 12:23:49.373686 Set Vref, RX VrefLevel [Byte0]: 61
8444 12:23:49.376013 [Byte1]: 61
8445 12:23:49.380719
8446 12:23:49.381270 Set Vref, RX VrefLevel [Byte0]: 62
8447 12:23:49.383935 [Byte1]: 62
8448 12:23:49.388242
8449 12:23:49.388799 Set Vref, RX VrefLevel [Byte0]: 63
8450 12:23:49.391974 [Byte1]: 63
8451 12:23:49.395932
8452 12:23:49.396637 Set Vref, RX VrefLevel [Byte0]: 64
8453 12:23:49.399129 [Byte1]: 64
8454 12:23:49.403552
8455 12:23:49.404101 Set Vref, RX VrefLevel [Byte0]: 65
8456 12:23:49.406924 [Byte1]: 65
8457 12:23:49.411401
8458 12:23:49.411949 Set Vref, RX VrefLevel [Byte0]: 66
8459 12:23:49.414624 [Byte1]: 66
8460 12:23:49.418969
8461 12:23:49.419543 Set Vref, RX VrefLevel [Byte0]: 67
8462 12:23:49.422155 [Byte1]: 67
8463 12:23:49.426506
8464 12:23:49.427044 Set Vref, RX VrefLevel [Byte0]: 68
8465 12:23:49.429504 [Byte1]: 68
8466 12:23:49.434220
8467 12:23:49.434763 Set Vref, RX VrefLevel [Byte0]: 69
8468 12:23:49.437538 [Byte1]: 69
8469 12:23:49.441875
8470 12:23:49.442416 Set Vref, RX VrefLevel [Byte0]: 70
8471 12:23:49.445180 [Byte1]: 70
8472 12:23:49.449448
8473 12:23:49.449991 Set Vref, RX VrefLevel [Byte0]: 71
8474 12:23:49.452633 [Byte1]: 71
8475 12:23:49.457191
8476 12:23:49.457729 Set Vref, RX VrefLevel [Byte0]: 72
8477 12:23:49.460215 [Byte1]: 72
8478 12:23:49.465053
8479 12:23:49.465595 Set Vref, RX VrefLevel [Byte0]: 73
8480 12:23:49.467955 [Byte1]: 73
8481 12:23:49.472402
8482 12:23:49.472937 Set Vref, RX VrefLevel [Byte0]: 74
8483 12:23:49.475912 [Byte1]: 74
8484 12:23:49.479989
8485 12:23:49.480590 Set Vref, RX VrefLevel [Byte0]: 75
8486 12:23:49.483314 [Byte1]: 75
8487 12:23:49.487719
8488 12:23:49.488321 Final RX Vref Byte 0 = 62 to rank0
8489 12:23:49.490996 Final RX Vref Byte 1 = 53 to rank0
8490 12:23:49.494243 Final RX Vref Byte 0 = 62 to rank1
8491 12:23:49.497489 Final RX Vref Byte 1 = 53 to rank1==
8492 12:23:49.500681 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 12:23:49.507642 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8494 12:23:49.508241 ==
8495 12:23:49.508616 DQS Delay:
8496 12:23:49.508947 DQS0 = 0, DQS1 = 0
8497 12:23:49.510886 DQM Delay:
8498 12:23:49.511424 DQM0 = 128, DQM1 = 123
8499 12:23:49.514393 DQ Delay:
8500 12:23:49.517631 DQ0 =132, DQ1 =122, DQ2 =118, DQ3 =126
8501 12:23:49.520687 DQ4 =128, DQ5 =140, DQ6 =138, DQ7 =126
8502 12:23:49.523926 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =112
8503 12:23:49.527665 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =134
8504 12:23:49.528248
8505 12:23:49.528609
8506 12:23:49.528936
8507 12:23:49.530754 [DramC_TX_OE_Calibration] TA2
8508 12:23:49.534426 Original DQ_B0 (3 6) =30, OEN = 27
8509 12:23:49.537720 Original DQ_B1 (3 6) =30, OEN = 27
8510 12:23:49.541051 24, 0x0, End_B0=24 End_B1=24
8511 12:23:49.541597 25, 0x0, End_B0=25 End_B1=25
8512 12:23:49.544575 26, 0x0, End_B0=26 End_B1=26
8513 12:23:49.547788 27, 0x0, End_B0=27 End_B1=27
8514 12:23:49.551251 28, 0x0, End_B0=28 End_B1=28
8515 12:23:49.552036 29, 0x0, End_B0=29 End_B1=29
8516 12:23:49.554213 30, 0x0, End_B0=30 End_B1=30
8517 12:23:49.557628 31, 0x4545, End_B0=30 End_B1=30
8518 12:23:49.560748 Byte0 end_step=30 best_step=27
8519 12:23:49.564598 Byte1 end_step=30 best_step=27
8520 12:23:49.567719 Byte0 TX OE(2T, 0.5T) = (3, 3)
8521 12:23:49.568340 Byte1 TX OE(2T, 0.5T) = (3, 3)
8522 12:23:49.570866
8523 12:23:49.571360
8524 12:23:49.577536 [DQSOSCAuto] RK0, (LSB)MR18= 0x2727, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8525 12:23:49.580697 CH1 RK0: MR19=303, MR18=2727
8526 12:23:49.587342 CH1_RK0: MR19=0x303, MR18=0x2727, DQSOSC=390, MR23=63, INC=24, DEC=16
8527 12:23:49.587881
8528 12:23:49.590856 ----->DramcWriteLeveling(PI) begin...
8529 12:23:49.591443 ==
8530 12:23:49.593920 Dram Type= 6, Freq= 0, CH_1, rank 1
8531 12:23:49.596992 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8532 12:23:49.597531 ==
8533 12:23:49.600466 Write leveling (Byte 0): 24 => 24
8534 12:23:49.603668 Write leveling (Byte 1): 22 => 22
8535 12:23:49.607197 DramcWriteLeveling(PI) end<-----
8536 12:23:49.607910
8537 12:23:49.608471 ==
8538 12:23:49.610817 Dram Type= 6, Freq= 0, CH_1, rank 1
8539 12:23:49.613937 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8540 12:23:49.614486 ==
8541 12:23:49.617123 [Gating] SW mode calibration
8542 12:23:49.623553 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8543 12:23:49.630260 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8544 12:23:49.633449 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8545 12:23:49.636920 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8546 12:23:49.643746 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8547 12:23:49.647121 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8548 12:23:49.650488 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8549 12:23:49.657421 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8550 12:23:49.660131 0 12 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8551 12:23:49.663969 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8552 12:23:49.670389 0 13 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
8553 12:23:49.673885 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8554 12:23:49.676682 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8555 12:23:49.683549 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8556 12:23:49.687113 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8557 12:23:49.690274 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8558 12:23:49.697086 0 13 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
8559 12:23:49.700653 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8560 12:23:49.703426 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8561 12:23:49.710147 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8562 12:23:49.713923 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8563 12:23:49.716405 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8564 12:23:49.723465 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8565 12:23:49.726461 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8566 12:23:49.729721 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8567 12:23:49.736341 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8568 12:23:49.739719 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8569 12:23:49.743187 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8570 12:23:49.749818 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8571 12:23:49.753188 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8572 12:23:49.756401 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8573 12:23:49.763141 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8574 12:23:49.766527 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 12:23:49.769688 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 12:23:49.776397 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 12:23:49.779567 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 12:23:49.783011 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 12:23:49.789485 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 12:23:49.792824 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 12:23:49.796315 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 12:23:49.799751 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8583 12:23:49.806491 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8584 12:23:49.809376 Total UI for P1: 0, mck2ui 16
8585 12:23:49.813017 best dqsien dly found for B0: ( 1, 0, 24)
8586 12:23:49.816291 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8587 12:23:49.819642 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8588 12:23:49.822411 Total UI for P1: 0, mck2ui 16
8589 12:23:49.826041 best dqsien dly found for B1: ( 1, 0, 30)
8590 12:23:49.829289 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8591 12:23:49.835908 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8592 12:23:49.836505
8593 12:23:49.839486 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8594 12:23:49.842341 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8595 12:23:49.845798 [Gating] SW calibration Done
8596 12:23:49.846339 ==
8597 12:23:49.849143 Dram Type= 6, Freq= 0, CH_1, rank 1
8598 12:23:49.852750 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8599 12:23:49.853323 ==
8600 12:23:49.853732 RX Vref Scan: 0
8601 12:23:49.855731
8602 12:23:49.856218 RX Vref 0 -> 0, step: 1
8603 12:23:49.856590
8604 12:23:49.859127 RX Delay 0 -> 252, step: 8
8605 12:23:49.862251 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8606 12:23:49.865734 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8607 12:23:49.872065 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8608 12:23:49.875556 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8609 12:23:49.878921 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8610 12:23:49.882518 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8611 12:23:49.885522 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8612 12:23:49.892527 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8613 12:23:49.895627 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8614 12:23:49.898863 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8615 12:23:49.902256 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8616 12:23:49.905645 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8617 12:23:49.912272 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8618 12:23:49.915356 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8619 12:23:49.919345 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8620 12:23:49.922045 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8621 12:23:49.922503 ==
8622 12:23:49.925797 Dram Type= 6, Freq= 0, CH_1, rank 1
8623 12:23:49.932550 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8624 12:23:49.933119 ==
8625 12:23:49.933484 DQS Delay:
8626 12:23:49.933823 DQS0 = 0, DQS1 = 0
8627 12:23:49.935721 DQM Delay:
8628 12:23:49.936198 DQM0 = 131, DQM1 = 125
8629 12:23:49.939062 DQ Delay:
8630 12:23:49.942293 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8631 12:23:49.945502 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8632 12:23:49.948924 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8633 12:23:49.952114 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8634 12:23:49.952698
8635 12:23:49.953063
8636 12:23:49.953401 ==
8637 12:23:49.955552 Dram Type= 6, Freq= 0, CH_1, rank 1
8638 12:23:49.958561 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8639 12:23:49.962023 ==
8640 12:23:49.962479
8641 12:23:49.962838
8642 12:23:49.963172 TX Vref Scan disable
8643 12:23:49.965315 == TX Byte 0 ==
8644 12:23:49.968487 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8645 12:23:49.972026 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8646 12:23:49.975001 == TX Byte 1 ==
8647 12:23:49.978649 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8648 12:23:49.982151 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8649 12:23:49.985196 ==
8650 12:23:49.985673 Dram Type= 6, Freq= 0, CH_1, rank 1
8651 12:23:49.991890 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8652 12:23:49.992521 ==
8653 12:23:50.004695
8654 12:23:50.008241 TX Vref early break, caculate TX vref
8655 12:23:50.011303 TX Vref=16, minBit 0, minWin=22, winSum=377
8656 12:23:50.014754 TX Vref=18, minBit 0, minWin=22, winSum=387
8657 12:23:50.017974 TX Vref=20, minBit 0, minWin=23, winSum=390
8658 12:23:50.021468 TX Vref=22, minBit 0, minWin=24, winSum=402
8659 12:23:50.024497 TX Vref=24, minBit 0, minWin=24, winSum=409
8660 12:23:50.030932 TX Vref=26, minBit 0, minWin=23, winSum=415
8661 12:23:50.034748 TX Vref=28, minBit 0, minWin=24, winSum=414
8662 12:23:50.038114 TX Vref=30, minBit 0, minWin=23, winSum=412
8663 12:23:50.041255 TX Vref=32, minBit 0, minWin=23, winSum=405
8664 12:23:50.044582 TX Vref=34, minBit 0, minWin=23, winSum=398
8665 12:23:50.047859 TX Vref=36, minBit 0, minWin=21, winSum=386
8666 12:23:50.054569 [TxChooseVref] Worse bit 0, Min win 24, Win sum 414, Final Vref 28
8667 12:23:50.055124
8668 12:23:50.058042 Final TX Range 0 Vref 28
8669 12:23:50.058601
8670 12:23:50.058989 ==
8671 12:23:50.061042 Dram Type= 6, Freq= 0, CH_1, rank 1
8672 12:23:50.064697 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8673 12:23:50.065255 ==
8674 12:23:50.065621
8675 12:23:50.065955
8676 12:23:50.068003 TX Vref Scan disable
8677 12:23:50.074497 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8678 12:23:50.075053 == TX Byte 0 ==
8679 12:23:50.077826 u2DelayCellOfst[0]=18 cells (5 PI)
8680 12:23:50.080819 u2DelayCellOfst[1]=7 cells (2 PI)
8681 12:23:50.084485 u2DelayCellOfst[2]=0 cells (0 PI)
8682 12:23:50.087744 u2DelayCellOfst[3]=7 cells (2 PI)
8683 12:23:50.091231 u2DelayCellOfst[4]=10 cells (3 PI)
8684 12:23:50.094139 u2DelayCellOfst[5]=14 cells (4 PI)
8685 12:23:50.097828 u2DelayCellOfst[6]=14 cells (4 PI)
8686 12:23:50.100932 u2DelayCellOfst[7]=3 cells (1 PI)
8687 12:23:50.104217 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8688 12:23:50.107603 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8689 12:23:50.111157 == TX Byte 1 ==
8690 12:23:50.114469 u2DelayCellOfst[8]=0 cells (0 PI)
8691 12:23:50.115035 u2DelayCellOfst[9]=3 cells (1 PI)
8692 12:23:50.117403 u2DelayCellOfst[10]=10 cells (3 PI)
8693 12:23:50.120836 u2DelayCellOfst[11]=3 cells (1 PI)
8694 12:23:50.124225 u2DelayCellOfst[12]=14 cells (4 PI)
8695 12:23:50.127951 u2DelayCellOfst[13]=18 cells (5 PI)
8696 12:23:50.130801 u2DelayCellOfst[14]=18 cells (5 PI)
8697 12:23:50.134415 u2DelayCellOfst[15]=14 cells (4 PI)
8698 12:23:50.137800 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8699 12:23:50.144257 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8700 12:23:50.144829 DramC Write-DBI on
8701 12:23:50.145325 ==
8702 12:23:50.147621 Dram Type= 6, Freq= 0, CH_1, rank 1
8703 12:23:50.154219 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8704 12:23:50.154791 ==
8705 12:23:50.155280
8706 12:23:50.155735
8707 12:23:50.156205 TX Vref Scan disable
8708 12:23:50.157666 == TX Byte 0 ==
8709 12:23:50.161418 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8710 12:23:50.164635 == TX Byte 1 ==
8711 12:23:50.167904 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8712 12:23:50.171168 DramC Write-DBI off
8713 12:23:50.171732
8714 12:23:50.172258 [DATLAT]
8715 12:23:50.172717 Freq=1600, CH1 RK1
8716 12:23:50.173165
8717 12:23:50.174245 DATLAT Default: 0xe
8718 12:23:50.174715 0, 0xFFFF, sum = 0
8719 12:23:50.177621 1, 0xFFFF, sum = 0
8720 12:23:50.180982 2, 0xFFFF, sum = 0
8721 12:23:50.181563 3, 0xFFFF, sum = 0
8722 12:23:50.184140 4, 0xFFFF, sum = 0
8723 12:23:50.184648 5, 0xFFFF, sum = 0
8724 12:23:50.187849 6, 0xFFFF, sum = 0
8725 12:23:50.188461 7, 0xFFFF, sum = 0
8726 12:23:50.190982 8, 0xFFFF, sum = 0
8727 12:23:50.191544 9, 0xFFFF, sum = 0
8728 12:23:50.194162 10, 0xFFFF, sum = 0
8729 12:23:50.194632 11, 0xFFFF, sum = 0
8730 12:23:50.197626 12, 0xF7F, sum = 0
8731 12:23:50.198273 13, 0x0, sum = 1
8732 12:23:50.201055 14, 0x0, sum = 2
8733 12:23:50.201546 15, 0x0, sum = 3
8734 12:23:50.203965 16, 0x0, sum = 4
8735 12:23:50.204557 best_step = 14
8736 12:23:50.204929
8737 12:23:50.205318 ==
8738 12:23:50.207506 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 12:23:50.210707 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8740 12:23:50.213923 ==
8741 12:23:50.214378 RX Vref Scan: 0
8742 12:23:50.214741
8743 12:23:50.217304 RX Vref 0 -> 0, step: 1
8744 12:23:50.217758
8745 12:23:50.218116 RX Delay 3 -> 252, step: 4
8746 12:23:50.224776 iDelay=195, Bit 0, Center 130 (79 ~ 182) 104
8747 12:23:50.228118 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8748 12:23:50.231075 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8749 12:23:50.234691 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8750 12:23:50.238244 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8751 12:23:50.244500 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8752 12:23:50.248116 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8753 12:23:50.251879 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8754 12:23:50.254953 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8755 12:23:50.257782 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8756 12:23:50.264757 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8757 12:23:50.268250 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8758 12:23:50.271448 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8759 12:23:50.274826 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8760 12:23:50.281505 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8761 12:23:50.284650 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8762 12:23:50.285202 ==
8763 12:23:50.287860 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 12:23:50.291056 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8765 12:23:50.291611 ==
8766 12:23:50.294682 DQS Delay:
8767 12:23:50.295230 DQS0 = 0, DQS1 = 0
8768 12:23:50.295598 DQM Delay:
8769 12:23:50.297600 DQM0 = 127, DQM1 = 123
8770 12:23:50.298058 DQ Delay:
8771 12:23:50.301377 DQ0 =130, DQ1 =122, DQ2 =116, DQ3 =124
8772 12:23:50.304311 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8773 12:23:50.307640 DQ8 =108, DQ9 =110, DQ10 =124, DQ11 =114
8774 12:23:50.314312 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8775 12:23:50.314862
8776 12:23:50.315224
8777 12:23:50.315562
8778 12:23:50.317618 [DramC_TX_OE_Calibration] TA2
8779 12:23:50.318170 Original DQ_B0 (3 6) =30, OEN = 27
8780 12:23:50.320975 Original DQ_B1 (3 6) =30, OEN = 27
8781 12:23:50.324170 24, 0x0, End_B0=24 End_B1=24
8782 12:23:50.327759 25, 0x0, End_B0=25 End_B1=25
8783 12:23:50.330997 26, 0x0, End_B0=26 End_B1=26
8784 12:23:50.334023 27, 0x0, End_B0=27 End_B1=27
8785 12:23:50.334489 28, 0x0, End_B0=28 End_B1=28
8786 12:23:50.337657 29, 0x0, End_B0=29 End_B1=29
8787 12:23:50.340662 30, 0x0, End_B0=30 End_B1=30
8788 12:23:50.344423 31, 0x4545, End_B0=30 End_B1=30
8789 12:23:50.347419 Byte0 end_step=30 best_step=27
8790 12:23:50.347881 Byte1 end_step=30 best_step=27
8791 12:23:50.350905 Byte0 TX OE(2T, 0.5T) = (3, 3)
8792 12:23:50.354047 Byte1 TX OE(2T, 0.5T) = (3, 3)
8793 12:23:50.354596
8794 12:23:50.354958
8795 12:23:50.363893 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8796 12:23:50.364493 CH1 RK1: MR19=303, MR18=1B1B
8797 12:23:50.370670 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8798 12:23:50.373544 [RxdqsGatingPostProcess] freq 1600
8799 12:23:50.380577 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8800 12:23:50.383554 Pre-setting of DQS Precalculation
8801 12:23:50.386962 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8802 12:23:50.396949 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8803 12:23:50.403977 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8804 12:23:50.404585
8805 12:23:50.404956
8806 12:23:50.406965 [Calibration Summary] 3200 Mbps
8807 12:23:50.407514 CH 0, Rank 0
8808 12:23:50.410476 SW Impedance : PASS
8809 12:23:50.411030 DUTY Scan : NO K
8810 12:23:50.413737 ZQ Calibration : PASS
8811 12:23:50.416970 Jitter Meter : NO K
8812 12:23:50.417516 CBT Training : PASS
8813 12:23:50.420282 Write leveling : PASS
8814 12:23:50.423268 RX DQS gating : PASS
8815 12:23:50.423724 RX DQ/DQS(RDDQC) : PASS
8816 12:23:50.426573 TX DQ/DQS : PASS
8817 12:23:50.430223 RX DATLAT : PASS
8818 12:23:50.430769 RX DQ/DQS(Engine): PASS
8819 12:23:50.433166 TX OE : PASS
8820 12:23:50.433626 All Pass.
8821 12:23:50.433989
8822 12:23:50.436478 CH 0, Rank 1
8823 12:23:50.436935 SW Impedance : PASS
8824 12:23:50.440075 DUTY Scan : NO K
8825 12:23:50.443776 ZQ Calibration : PASS
8826 12:23:50.444372 Jitter Meter : NO K
8827 12:23:50.446619 CBT Training : PASS
8828 12:23:50.447075 Write leveling : PASS
8829 12:23:50.450062 RX DQS gating : PASS
8830 12:23:50.453684 RX DQ/DQS(RDDQC) : PASS
8831 12:23:50.454233 TX DQ/DQS : PASS
8832 12:23:50.456696 RX DATLAT : PASS
8833 12:23:50.460241 RX DQ/DQS(Engine): PASS
8834 12:23:50.460788 TX OE : PASS
8835 12:23:50.463379 All Pass.
8836 12:23:50.463926
8837 12:23:50.464357 CH 1, Rank 0
8838 12:23:50.466428 SW Impedance : PASS
8839 12:23:50.466888 DUTY Scan : NO K
8840 12:23:50.469785 ZQ Calibration : PASS
8841 12:23:50.472901 Jitter Meter : NO K
8842 12:23:50.473368 CBT Training : PASS
8843 12:23:50.476541 Write leveling : PASS
8844 12:23:50.479746 RX DQS gating : PASS
8845 12:23:50.480263 RX DQ/DQS(RDDQC) : PASS
8846 12:23:50.483007 TX DQ/DQS : PASS
8847 12:23:50.486328 RX DATLAT : PASS
8848 12:23:50.486882 RX DQ/DQS(Engine): PASS
8849 12:23:50.489888 TX OE : PASS
8850 12:23:50.490444 All Pass.
8851 12:23:50.490807
8852 12:23:50.492769 CH 1, Rank 1
8853 12:23:50.493220 SW Impedance : PASS
8854 12:23:50.496012 DUTY Scan : NO K
8855 12:23:50.499390 ZQ Calibration : PASS
8856 12:23:50.499962 Jitter Meter : NO K
8857 12:23:50.503314 CBT Training : PASS
8858 12:23:50.506430 Write leveling : PASS
8859 12:23:50.506985 RX DQS gating : PASS
8860 12:23:50.509323 RX DQ/DQS(RDDQC) : PASS
8861 12:23:50.509775 TX DQ/DQS : PASS
8862 12:23:50.512798 RX DATLAT : PASS
8863 12:23:50.516350 RX DQ/DQS(Engine): PASS
8864 12:23:50.516899 TX OE : PASS
8865 12:23:50.519580 All Pass.
8866 12:23:50.520131
8867 12:23:50.520551 DramC Write-DBI on
8868 12:23:50.522876 PER_BANK_REFRESH: Hybrid Mode
8869 12:23:50.526558 TX_TRACKING: ON
8870 12:23:50.532938 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8871 12:23:50.542737 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8872 12:23:50.549710 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8873 12:23:50.552734 [FAST_K] Save calibration result to emmc
8874 12:23:50.556026 sync common calibartion params.
8875 12:23:50.556664 sync cbt_mode0:0, 1:0
8876 12:23:50.559253 dram_init: ddr_geometry: 0
8877 12:23:50.562656 dram_init: ddr_geometry: 0
8878 12:23:50.565687 dram_init: ddr_geometry: 0
8879 12:23:50.566141 0:dram_rank_size:80000000
8880 12:23:50.568895 1:dram_rank_size:80000000
8881 12:23:50.575391 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8882 12:23:50.575848 DFS_SHUFFLE_HW_MODE: ON
8883 12:23:50.579226 dramc_set_vcore_voltage set vcore to 725000
8884 12:23:50.582233 Read voltage for 1600, 0
8885 12:23:50.582687 Vio18 = 0
8886 12:23:50.585651 Vcore = 725000
8887 12:23:50.586199 Vdram = 0
8888 12:23:50.586562 Vddq = 0
8889 12:23:50.588908 Vmddr = 0
8890 12:23:50.589362 switch to 3200 Mbps bootup
8891 12:23:50.592234 [DramcRunTimeConfig]
8892 12:23:50.592700 PHYPLL
8893 12:23:50.595641 DPM_CONTROL_AFTERK: ON
8894 12:23:50.596092 PER_BANK_REFRESH: ON
8895 12:23:50.598564 REFRESH_OVERHEAD_REDUCTION: ON
8896 12:23:50.602292 CMD_PICG_NEW_MODE: OFF
8897 12:23:50.602846 XRTWTW_NEW_MODE: ON
8898 12:23:50.605290 XRTRTR_NEW_MODE: ON
8899 12:23:50.605742 TX_TRACKING: ON
8900 12:23:50.608712 RDSEL_TRACKING: OFF
8901 12:23:50.612007 DQS Precalculation for DVFS: ON
8902 12:23:50.612528 RX_TRACKING: OFF
8903 12:23:50.615718 HW_GATING DBG: ON
8904 12:23:50.616328 ZQCS_ENABLE_LP4: ON
8905 12:23:50.618779 RX_PICG_NEW_MODE: ON
8906 12:23:50.619329 TX_PICG_NEW_MODE: ON
8907 12:23:50.622105 ENABLE_RX_DCM_DPHY: ON
8908 12:23:50.625522 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8909 12:23:50.629147 DUMMY_READ_FOR_TRACKING: OFF
8910 12:23:50.629699 !!! SPM_CONTROL_AFTERK: OFF
8911 12:23:50.631917 !!! SPM could not control APHY
8912 12:23:50.635381 IMPEDANCE_TRACKING: ON
8913 12:23:50.635832 TEMP_SENSOR: ON
8914 12:23:50.638490 HW_SAVE_FOR_SR: OFF
8915 12:23:50.642493 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8916 12:23:50.645748 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8917 12:23:50.648784 Read ODT Tracking: ON
8918 12:23:50.649239 Refresh Rate DeBounce: ON
8919 12:23:50.651972 DFS_NO_QUEUE_FLUSH: ON
8920 12:23:50.655006 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8921 12:23:50.658930 ENABLE_DFS_RUNTIME_MRW: OFF
8922 12:23:50.659485 DDR_RESERVE_NEW_MODE: ON
8923 12:23:50.661969 MR_CBT_SWITCH_FREQ: ON
8924 12:23:50.665146 =========================
8925 12:23:50.682496 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8926 12:23:50.685869 dram_init: ddr_geometry: 0
8927 12:23:50.703896 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8928 12:23:50.707332 dram_init: dram init end (result: 0)
8929 12:23:50.713698 DRAM-K: Full calibration passed in 23417 msecs
8930 12:23:50.716918 MRC: failed to locate region type 0.
8931 12:23:50.717375 DRAM rank0 size:0x80000000,
8932 12:23:50.720066 DRAM rank1 size=0x80000000
8933 12:23:50.730269 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8934 12:23:50.736863 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8935 12:23:50.743310 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8936 12:23:50.750114 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8937 12:23:50.753669 DRAM rank0 size:0x80000000,
8938 12:23:50.756623 DRAM rank1 size=0x80000000
8939 12:23:50.757077 CBMEM:
8940 12:23:50.760549 IMD: root @ 0xfffff000 254 entries.
8941 12:23:50.763428 IMD: root @ 0xffffec00 62 entries.
8942 12:23:50.766544 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8943 12:23:50.769710 WARNING: RO_VPD is uninitialized or empty.
8944 12:23:50.776290 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8945 12:23:50.783243 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8946 12:23:50.796267 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
8947 12:23:50.807750 BS: romstage times (exec / console): total (unknown) / 22955 ms
8948 12:23:50.808364
8949 12:23:50.808739
8950 12:23:50.817512 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8951 12:23:50.820793 ARM64: Exception handlers installed.
8952 12:23:50.824312 ARM64: Testing exception
8953 12:23:50.827549 ARM64: Done test exception
8954 12:23:50.828099 Enumerating buses...
8955 12:23:50.830682 Show all devs... Before device enumeration.
8956 12:23:50.834296 Root Device: enabled 1
8957 12:23:50.837142 CPU_CLUSTER: 0: enabled 1
8958 12:23:50.837697 CPU: 00: enabled 1
8959 12:23:50.840556 Compare with tree...
8960 12:23:50.841112 Root Device: enabled 1
8961 12:23:50.843953 CPU_CLUSTER: 0: enabled 1
8962 12:23:50.847138 CPU: 00: enabled 1
8963 12:23:50.847591 Root Device scanning...
8964 12:23:50.850568 scan_static_bus for Root Device
8965 12:23:50.853713 CPU_CLUSTER: 0 enabled
8966 12:23:50.856997 scan_static_bus for Root Device done
8967 12:23:50.860753 scan_bus: bus Root Device finished in 8 msecs
8968 12:23:50.861416 done
8969 12:23:50.867348 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8970 12:23:50.870384 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8971 12:23:50.876893 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8972 12:23:50.880417 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8973 12:23:50.883512 Allocating resources...
8974 12:23:50.886841 Reading resources...
8975 12:23:50.890457 Root Device read_resources bus 0 link: 0
8976 12:23:50.891006 DRAM rank0 size:0x80000000,
8977 12:23:50.893620 DRAM rank1 size=0x80000000
8978 12:23:50.896887 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8979 12:23:50.899994 CPU: 00 missing read_resources
8980 12:23:50.903600 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8981 12:23:50.910098 Root Device read_resources bus 0 link: 0 done
8982 12:23:50.910634 Done reading resources.
8983 12:23:50.917195 Show resources in subtree (Root Device)...After reading.
8984 12:23:50.920312 Root Device child on link 0 CPU_CLUSTER: 0
8985 12:23:50.923540 CPU_CLUSTER: 0 child on link 0 CPU: 00
8986 12:23:50.933825 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8987 12:23:50.934378 CPU: 00
8988 12:23:50.936865 Root Device assign_resources, bus 0 link: 0
8989 12:23:50.940322 CPU_CLUSTER: 0 missing set_resources
8990 12:23:50.946892 Root Device assign_resources, bus 0 link: 0 done
8991 12:23:50.947437 Done setting resources.
8992 12:23:50.953527 Show resources in subtree (Root Device)...After assigning values.
8993 12:23:50.956859 Root Device child on link 0 CPU_CLUSTER: 0
8994 12:23:50.960016 CPU_CLUSTER: 0 child on link 0 CPU: 00
8995 12:23:50.970107 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8996 12:23:50.970681 CPU: 00
8997 12:23:50.973253 Done allocating resources.
8998 12:23:50.976759 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8999 12:23:50.979941 Enabling resources...
9000 12:23:50.980581 done.
9001 12:23:50.986460 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9002 12:23:50.987000 Initializing devices...
9003 12:23:50.989809 Root Device init
9004 12:23:50.990384 init hardware done!
9005 12:23:50.992887 0x00000018: ctrlr->caps
9006 12:23:50.996455 52.000 MHz: ctrlr->f_max
9007 12:23:50.996954 0.400 MHz: ctrlr->f_min
9008 12:23:50.999590 0x40ff8080: ctrlr->voltages
9009 12:23:51.000070 sclk: 390625
9010 12:23:51.003215 Bus Width = 1
9011 12:23:51.003766 sclk: 390625
9012 12:23:51.006069 Bus Width = 1
9013 12:23:51.006519 Early init status = 3
9014 12:23:51.012825 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9015 12:23:51.016424 in-header: 03 fc 00 00 01 00 00 00
9016 12:23:51.019939 in-data: 00
9017 12:23:51.023447 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9018 12:23:51.028388 in-header: 03 fd 00 00 00 00 00 00
9019 12:23:51.031689 in-data:
9020 12:23:51.035035 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9021 12:23:51.039461 in-header: 03 fc 00 00 01 00 00 00
9022 12:23:51.042736 in-data: 00
9023 12:23:51.045966 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9024 12:23:51.052343 in-header: 03 fd 00 00 00 00 00 00
9025 12:23:51.055030 in-data:
9026 12:23:51.058541 [SSUSB] Setting up USB HOST controller...
9027 12:23:51.061660 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9028 12:23:51.065153 [SSUSB] phy power-on done.
9029 12:23:51.068348 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9030 12:23:51.074969 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9031 12:23:51.078140 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9032 12:23:51.084925 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9033 12:23:51.091300 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9034 12:23:51.097712 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9035 12:23:51.104480 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9036 12:23:51.111133 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9037 12:23:51.114169 SPM: binary array size = 0x9dc
9038 12:23:51.118009 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9039 12:23:51.124253 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9040 12:23:51.131117 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9041 12:23:51.137702 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9042 12:23:51.141107 configure_display: Starting display init
9043 12:23:51.175070 anx7625_power_on_init: Init interface.
9044 12:23:51.178257 anx7625_disable_pd_protocol: Disabled PD feature.
9045 12:23:51.181837 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9046 12:23:51.209791 anx7625_start_dp_work: Secure OCM version=00
9047 12:23:51.212609 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9048 12:23:51.227954 sp_tx_get_edid_block: EDID Block = 1
9049 12:23:51.330007 Extracted contents:
9050 12:23:51.333116 header: 00 ff ff ff ff ff ff 00
9051 12:23:51.336916 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9052 12:23:51.339946 version: 01 04
9053 12:23:51.343188 basic params: 95 1f 11 78 0a
9054 12:23:51.346653 chroma info: 76 90 94 55 54 90 27 21 50 54
9055 12:23:51.349566 established: 00 00 00
9056 12:23:51.356329 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9057 12:23:51.363277 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9058 12:23:51.366572 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9059 12:23:51.372798 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9060 12:23:51.379478 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9061 12:23:51.382816 extensions: 00
9062 12:23:51.383361 checksum: fb
9063 12:23:51.383718
9064 12:23:51.389067 Manufacturer: IVO Model 57d Serial Number 0
9065 12:23:51.389603 Made week 0 of 2020
9066 12:23:51.393105 EDID version: 1.4
9067 12:23:51.393645 Digital display
9068 12:23:51.395809 6 bits per primary color channel
9069 12:23:51.396306 DisplayPort interface
9070 12:23:51.399077 Maximum image size: 31 cm x 17 cm
9071 12:23:51.402439 Gamma: 220%
9072 12:23:51.402889 Check DPMS levels
9073 12:23:51.408894 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9074 12:23:51.412436 First detailed timing is preferred timing
9075 12:23:51.412976 Established timings supported:
9076 12:23:51.415667 Standard timings supported:
9077 12:23:51.418986 Detailed timings
9078 12:23:51.422375 Hex of detail: 383680a07038204018303c0035ae10000019
9079 12:23:51.429147 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9080 12:23:51.432797 0780 0798 07c8 0820 hborder 0
9081 12:23:51.435426 0438 043b 0447 0458 vborder 0
9082 12:23:51.439188 -hsync -vsync
9083 12:23:51.439853 Did detailed timing
9084 12:23:51.445623 Hex of detail: 000000000000000000000000000000000000
9085 12:23:51.449186 Manufacturer-specified data, tag 0
9086 12:23:51.452320 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9087 12:23:51.455363 ASCII string: InfoVision
9088 12:23:51.458575 Hex of detail: 000000fe00523134304e574635205248200a
9089 12:23:51.462055 ASCII string: R140NWF5 RH
9090 12:23:51.462614 Checksum
9091 12:23:51.465246 Checksum: 0xfb (valid)
9092 12:23:51.468560 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9093 12:23:51.471763 DSI data_rate: 832800000 bps
9094 12:23:51.478695 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9095 12:23:51.481976 anx7625_parse_edid: pixelclock(138800).
9096 12:23:51.484914 hactive(1920), hsync(48), hfp(24), hbp(88)
9097 12:23:51.488501 vactive(1080), vsync(12), vfp(3), vbp(17)
9098 12:23:51.491639 anx7625_dsi_config: config dsi.
9099 12:23:51.498526 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9100 12:23:51.511749 anx7625_dsi_config: success to config DSI
9101 12:23:51.515695 anx7625_dp_start: MIPI phy setup OK.
9102 12:23:51.518614 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9103 12:23:51.521859 mtk_ddp_mode_set invalid vrefresh 60
9104 12:23:51.525529 main_disp_path_setup
9105 12:23:51.526069 ovl_layer_smi_id_en
9106 12:23:51.528607 ovl_layer_smi_id_en
9107 12:23:51.529156 ccorr_config
9108 12:23:51.529520 aal_config
9109 12:23:51.532254 gamma_config
9110 12:23:51.532795 postmask_config
9111 12:23:51.535215 dither_config
9112 12:23:51.538866 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9113 12:23:51.545642 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9114 12:23:51.548806 Root Device init finished in 555 msecs
9115 12:23:51.549357 CPU_CLUSTER: 0 init
9116 12:23:51.558751 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9117 12:23:51.561869 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9118 12:23:51.565225 APU_MBOX 0x190000b0 = 0x10001
9119 12:23:51.569013 APU_MBOX 0x190001b0 = 0x10001
9120 12:23:51.572151 APU_MBOX 0x190005b0 = 0x10001
9121 12:23:51.574912 APU_MBOX 0x190006b0 = 0x10001
9122 12:23:51.578646 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9123 12:23:51.590949 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9124 12:23:51.603497 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9125 12:23:51.610365 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9126 12:23:51.622058 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9127 12:23:51.631237 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9128 12:23:51.634521 CPU_CLUSTER: 0 init finished in 81 msecs
9129 12:23:51.637758 Devices initialized
9130 12:23:51.640952 Show all devs... After init.
9131 12:23:51.641493 Root Device: enabled 1
9132 12:23:51.644067 CPU_CLUSTER: 0: enabled 1
9133 12:23:51.647477 CPU: 00: enabled 1
9134 12:23:51.650603 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9135 12:23:51.654008 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9136 12:23:51.657347 ELOG: NV offset 0x57f000 size 0x1000
9137 12:23:51.664276 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9138 12:23:51.670795 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9139 12:23:51.673940 ELOG: Event(17) added with size 13 at 2023-10-27 12:23:52 UTC
9140 12:23:51.676972 out: cmd=0x121: 03 db 21 01 00 00 00 00
9141 12:23:51.681894 in-header: 03 f4 00 00 2c 00 00 00
9142 12:23:51.695414 in-data: 6f 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9143 12:23:51.701670 ELOG: Event(A1) added with size 10 at 2023-10-27 12:23:52 UTC
9144 12:23:51.708330 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9145 12:23:51.715251 ELOG: Event(A0) added with size 9 at 2023-10-27 12:23:52 UTC
9146 12:23:51.718206 elog_add_boot_reason: Logged dev mode boot
9147 12:23:51.721492 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9148 12:23:51.724795 Finalize devices...
9149 12:23:51.725442 Devices finalized
9150 12:23:51.731688 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9151 12:23:51.734875 Writing coreboot table at 0xffe64000
9152 12:23:51.738249 0. 000000000010a000-0000000000113fff: RAMSTAGE
9153 12:23:51.741238 1. 0000000040000000-00000000400fffff: RAM
9154 12:23:51.748103 2. 0000000040100000-000000004032afff: RAMSTAGE
9155 12:23:51.751393 3. 000000004032b000-00000000545fffff: RAM
9156 12:23:51.754359 4. 0000000054600000-000000005465ffff: BL31
9157 12:23:51.758279 5. 0000000054660000-00000000ffe63fff: RAM
9158 12:23:51.764359 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9159 12:23:51.768050 7. 0000000100000000-000000013fffffff: RAM
9160 12:23:51.771265 Passing 5 GPIOs to payload:
9161 12:23:51.774574 NAME | PORT | POLARITY | VALUE
9162 12:23:51.778132 EC in RW | 0x000000aa | low | undefined
9163 12:23:51.784663 EC interrupt | 0x00000005 | low | undefined
9164 12:23:51.787757 TPM interrupt | 0x000000ab | high | undefined
9165 12:23:51.794531 SD card detect | 0x00000011 | high | undefined
9166 12:23:51.797459 speaker enable | 0x00000093 | high | undefined
9167 12:23:51.800934 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9168 12:23:51.804264 in-header: 03 f8 00 00 02 00 00 00
9169 12:23:51.807495 in-data: 03 00
9170 12:23:51.807953 ADC[4]: Raw value=668590 ID=5
9171 12:23:51.810822 ADC[3]: Raw value=212549 ID=1
9172 12:23:51.814338 RAM Code: 0x51
9173 12:23:51.814964 ADC[6]: Raw value=74410 ID=0
9174 12:23:51.817644 ADC[5]: Raw value=211444 ID=1
9175 12:23:51.821155 SKU Code: 0x1
9176 12:23:51.824032 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 356b
9177 12:23:51.827324 coreboot table: 964 bytes.
9178 12:23:51.831136 IMD ROOT 0. 0xfffff000 0x00001000
9179 12:23:51.833983 IMD SMALL 1. 0xffffe000 0x00001000
9180 12:23:51.837645 RO MCACHE 2. 0xffffc000 0x00001104
9181 12:23:51.840490 CONSOLE 3. 0xfff7c000 0x00080000
9182 12:23:51.844130 FMAP 4. 0xfff7b000 0x00000452
9183 12:23:51.847572 TIME STAMP 5. 0xfff7a000 0x00000910
9184 12:23:51.850861 VBOOT WORK 6. 0xfff66000 0x00014000
9185 12:23:51.853738 RAMOOPS 7. 0xffe66000 0x00100000
9186 12:23:51.857175 COREBOOT 8. 0xffe64000 0x00002000
9187 12:23:51.857728 IMD small region:
9188 12:23:51.860639 IMD ROOT 0. 0xffffec00 0x00000400
9189 12:23:51.867536 VPD 1. 0xffffeb80 0x0000006c
9190 12:23:51.870036 MMC STATUS 2. 0xffffeb60 0x00000004
9191 12:23:51.873580 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9192 12:23:51.876987 Probing TPM: done!
9193 12:23:51.880885 Connected to device vid:did:rid of 1ae0:0028:00
9194 12:23:51.890557 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9195 12:23:51.893923 Initialized TPM device CR50 revision 0
9196 12:23:51.897206 Checking cr50 for pending updates
9197 12:23:51.901559 Reading cr50 TPM mode
9198 12:23:51.909759 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9199 12:23:51.916525 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9200 12:23:51.956616 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9201 12:23:51.959683 Checking segment from ROM address 0x40100000
9202 12:23:51.963057 Checking segment from ROM address 0x4010001c
9203 12:23:51.969687 Loading segment from ROM address 0x40100000
9204 12:23:51.970273 code (compression=0)
9205 12:23:51.979640 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9206 12:23:51.986732 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9207 12:23:51.987281 it's not compressed!
9208 12:23:51.992733 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9209 12:23:51.999515 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9210 12:23:52.016892 Loading segment from ROM address 0x4010001c
9211 12:23:52.017439 Entry Point 0x80000000
9212 12:23:52.020308 Loaded segments
9213 12:23:52.023857 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9214 12:23:52.029877 Jumping to boot code at 0x80000000(0xffe64000)
9215 12:23:52.037021 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9216 12:23:52.043671 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9217 12:23:52.051414 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9218 12:23:52.054632 Checking segment from ROM address 0x40100000
9219 12:23:52.058130 Checking segment from ROM address 0x4010001c
9220 12:23:52.064672 Loading segment from ROM address 0x40100000
9221 12:23:52.065203 code (compression=1)
9222 12:23:52.071685 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9223 12:23:52.080947 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9224 12:23:52.081480 using LZMA
9225 12:23:52.089483 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9226 12:23:52.096578 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9227 12:23:52.099395 Loading segment from ROM address 0x4010001c
9228 12:23:52.099853 Entry Point 0x54601000
9229 12:23:52.102782 Loaded segments
9230 12:23:52.106255 NOTICE: MT8192 bl31_setup
9231 12:23:52.113227 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9232 12:23:52.116663 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9233 12:23:52.120311 WARNING: region 0:
9234 12:23:52.123360 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9235 12:23:52.123919 WARNING: region 1:
9236 12:23:52.129727 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9237 12:23:52.133280 WARNING: region 2:
9238 12:23:52.136623 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9239 12:23:52.140275 WARNING: region 3:
9240 12:23:52.143417 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9241 12:23:52.146863 WARNING: region 4:
9242 12:23:52.150504 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9243 12:23:52.153764 WARNING: region 5:
9244 12:23:52.156841 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9245 12:23:52.160254 WARNING: region 6:
9246 12:23:52.163733 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9247 12:23:52.164345 WARNING: region 7:
9248 12:23:52.170233 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9249 12:23:52.176853 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9250 12:23:52.180298 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9251 12:23:52.183471 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9252 12:23:52.189781 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9253 12:23:52.193326 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9254 12:23:52.196857 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9255 12:23:52.203082 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9256 12:23:52.206485 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9257 12:23:52.212990 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9258 12:23:52.216590 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9259 12:23:52.220665 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9260 12:23:52.226693 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9261 12:23:52.229765 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9262 12:23:52.233519 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9263 12:23:52.240284 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9264 12:23:52.243520 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9265 12:23:52.246946 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9266 12:23:52.253250 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9267 12:23:52.257121 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9268 12:23:52.263410 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9269 12:23:52.266646 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9270 12:23:52.269900 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9271 12:23:52.276812 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9272 12:23:52.280450 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9273 12:23:52.286859 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9274 12:23:52.290276 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9275 12:23:52.293117 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9276 12:23:52.299831 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9277 12:23:52.303159 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9278 12:23:52.309856 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9279 12:23:52.313546 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9280 12:23:52.316752 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9281 12:23:52.323285 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9282 12:23:52.326343 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9283 12:23:52.329782 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9284 12:23:52.333059 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9285 12:23:52.336355 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9286 12:23:52.343543 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9287 12:23:52.346510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9288 12:23:52.349984 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9289 12:23:52.353494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9290 12:23:52.360442 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9291 12:23:52.363688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9292 12:23:52.366946 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9293 12:23:52.370425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9294 12:23:52.376785 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9295 12:23:52.380018 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9296 12:23:52.383296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9297 12:23:52.389747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9298 12:23:52.393021 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9299 12:23:52.399555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9300 12:23:52.403438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9301 12:23:52.406724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9302 12:23:52.413632 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9303 12:23:52.416607 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9304 12:23:52.423217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9305 12:23:52.426529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9306 12:23:52.432901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9307 12:23:52.436168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9308 12:23:52.439526 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9309 12:23:52.446498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9310 12:23:52.449664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9311 12:23:52.456494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9312 12:23:52.459850 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9313 12:23:52.466241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9314 12:23:52.469778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9315 12:23:52.476478 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9316 12:23:52.479941 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9317 12:23:52.482824 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9318 12:23:52.489586 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9319 12:23:52.492938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9320 12:23:52.499592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9321 12:23:52.502750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9322 12:23:52.506733 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9323 12:23:52.513290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9324 12:23:52.515994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9325 12:23:52.522901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9326 12:23:52.526583 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9327 12:23:52.532910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9328 12:23:52.536087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9329 12:23:52.543127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9330 12:23:52.546390 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9331 12:23:52.549382 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9332 12:23:52.556041 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9333 12:23:52.559523 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9334 12:23:52.566085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9335 12:23:52.569419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9336 12:23:52.576551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9337 12:23:52.579684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9338 12:23:52.582624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9339 12:23:52.589381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9340 12:23:52.593141 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9341 12:23:52.599530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9342 12:23:52.602619 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9343 12:23:52.609480 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9344 12:23:52.612589 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9345 12:23:52.616286 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9346 12:23:52.622860 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9347 12:23:52.626498 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9348 12:23:52.629233 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9349 12:23:52.632808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9350 12:23:52.639439 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9351 12:23:52.642915 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9352 12:23:52.649901 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9353 12:23:52.653023 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9354 12:23:52.656392 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9355 12:23:52.662700 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9356 12:23:52.666209 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9357 12:23:52.672715 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9358 12:23:52.676319 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9359 12:23:52.679354 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9360 12:23:52.686119 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9361 12:23:52.689582 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9362 12:23:52.696085 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9363 12:23:52.699312 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9364 12:23:52.702719 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9365 12:23:52.706299 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9366 12:23:52.713131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9367 12:23:52.715833 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9368 12:23:52.719105 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9369 12:23:52.725913 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9370 12:23:52.729399 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9371 12:23:52.732696 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9372 12:23:52.736160 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9373 12:23:52.742621 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9374 12:23:52.746220 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9375 12:23:52.752353 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9376 12:23:52.756091 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9377 12:23:52.759262 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9378 12:23:52.766034 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9379 12:23:52.769474 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9380 12:23:52.775986 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9381 12:23:52.779159 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9382 12:23:52.782810 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9383 12:23:52.789279 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9384 12:23:52.793111 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9385 12:23:52.799040 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9386 12:23:52.802379 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9387 12:23:52.806015 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9388 12:23:52.812750 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9389 12:23:52.815866 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9390 12:23:52.819472 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9391 12:23:52.825626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9392 12:23:52.829059 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9393 12:23:52.835782 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9394 12:23:52.838944 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9395 12:23:52.842711 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9396 12:23:52.849140 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9397 12:23:52.853036 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9398 12:23:52.859419 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9399 12:23:52.862570 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9400 12:23:52.866141 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9401 12:23:52.872863 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9402 12:23:52.876103 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9403 12:23:52.879817 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9404 12:23:52.886062 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9405 12:23:52.889039 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9406 12:23:52.895685 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9407 12:23:52.899136 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9408 12:23:52.902810 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9409 12:23:52.909118 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9410 12:23:52.912367 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9411 12:23:52.918973 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9412 12:23:52.922566 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9413 12:23:52.925924 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9414 12:23:52.932404 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9415 12:23:52.935912 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9416 12:23:52.939436 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9417 12:23:52.946025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9418 12:23:52.948880 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9419 12:23:52.955834 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9420 12:23:52.959022 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9421 12:23:52.962762 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9422 12:23:52.968814 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9423 12:23:52.972358 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9424 12:23:52.978902 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9425 12:23:52.982316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9426 12:23:52.985760 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9427 12:23:52.992486 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9428 12:23:52.995538 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9429 12:23:53.002228 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9430 12:23:53.005306 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9431 12:23:53.008709 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9432 12:23:53.015284 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9433 12:23:53.019361 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9434 12:23:53.025537 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9435 12:23:53.028864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9436 12:23:53.032276 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9437 12:23:53.038897 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9438 12:23:53.042153 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9439 12:23:53.049139 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9440 12:23:53.052265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9441 12:23:53.055719 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9442 12:23:53.062265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9443 12:23:53.065335 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9444 12:23:53.072247 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9445 12:23:53.075444 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9446 12:23:53.078945 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9447 12:23:53.085282 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9448 12:23:53.088390 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9449 12:23:53.095296 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9450 12:23:53.098076 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9451 12:23:53.104982 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9452 12:23:53.108157 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9453 12:23:53.111637 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9454 12:23:53.118225 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9455 12:23:53.121504 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9456 12:23:53.128021 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9457 12:23:53.131613 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9458 12:23:53.134796 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9459 12:23:53.141707 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9460 12:23:53.145133 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9461 12:23:53.151601 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9462 12:23:53.154905 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9463 12:23:53.161460 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9464 12:23:53.164554 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9465 12:23:53.167944 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9466 12:23:53.175079 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9467 12:23:53.178442 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9468 12:23:53.184642 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9469 12:23:53.187934 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9470 12:23:53.191120 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9471 12:23:53.197653 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9472 12:23:53.200923 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9473 12:23:53.207924 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9474 12:23:53.211455 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9475 12:23:53.217811 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9476 12:23:53.220740 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9477 12:23:53.224417 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9478 12:23:53.230627 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9479 12:23:53.233901 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9480 12:23:53.237237 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9481 12:23:53.240728 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9482 12:23:53.247777 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9483 12:23:53.250987 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9484 12:23:53.254045 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9485 12:23:53.260777 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9486 12:23:53.264089 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9487 12:23:53.267885 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9488 12:23:53.274411 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9489 12:23:53.277750 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9490 12:23:53.284041 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9491 12:23:53.287191 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9492 12:23:53.290692 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9493 12:23:53.297412 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9494 12:23:53.300336 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9495 12:23:53.304011 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9496 12:23:53.310602 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9497 12:23:53.314058 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9498 12:23:53.317082 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9499 12:23:53.324143 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9500 12:23:53.327434 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9501 12:23:53.333813 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9502 12:23:53.336790 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9503 12:23:53.340347 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9504 12:23:53.347224 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9505 12:23:53.350138 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9506 12:23:53.353553 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9507 12:23:53.360100 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9508 12:23:53.363663 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9509 12:23:53.370590 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9510 12:23:53.374023 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9511 12:23:53.376789 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9512 12:23:53.383471 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9513 12:23:53.386736 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9514 12:23:53.389709 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9515 12:23:53.396551 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9516 12:23:53.400152 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9517 12:23:53.403417 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9518 12:23:53.409811 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9519 12:23:53.412877 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9520 12:23:53.416689 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9521 12:23:53.420103 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9522 12:23:53.423315 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9523 12:23:53.429609 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9524 12:23:53.432916 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9525 12:23:53.436334 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9526 12:23:53.443628 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9527 12:23:53.446449 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9528 12:23:53.449206 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9529 12:23:53.452911 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9530 12:23:53.459360 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9531 12:23:53.462826 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9532 12:23:53.469512 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9533 12:23:53.472734 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9534 12:23:53.476548 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9535 12:23:53.483059 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9536 12:23:53.486390 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9537 12:23:53.492656 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9538 12:23:53.495824 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9539 12:23:53.499324 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9540 12:23:53.505645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9541 12:23:53.509562 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9542 12:23:53.515775 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9543 12:23:53.519169 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9544 12:23:53.525861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9545 12:23:53.528805 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9546 12:23:53.531919 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9547 12:23:53.539109 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9548 12:23:53.542190 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9549 12:23:53.548890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9550 12:23:53.552532 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9551 12:23:53.555679 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9552 12:23:53.562129 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9553 12:23:53.565729 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9554 12:23:53.572330 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9555 12:23:53.575162 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9556 12:23:53.578482 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9557 12:23:53.585086 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9558 12:23:53.588589 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9559 12:23:53.595119 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9560 12:23:53.598703 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9561 12:23:53.605087 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9562 12:23:53.608879 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9563 12:23:53.611747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9564 12:23:53.618064 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9565 12:23:53.621611 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9566 12:23:53.628771 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9567 12:23:53.631537 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9568 12:23:53.635154 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9569 12:23:53.641685 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9570 12:23:53.645009 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9571 12:23:53.651577 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9572 12:23:53.655247 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9573 12:23:53.658464 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9574 12:23:53.664953 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9575 12:23:53.668858 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9576 12:23:53.674680 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9577 12:23:53.677920 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9578 12:23:53.681314 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9579 12:23:53.688265 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9580 12:23:53.691383 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9581 12:23:53.698015 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9582 12:23:53.701502 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9583 12:23:53.707679 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9584 12:23:53.711307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9585 12:23:53.714585 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9586 12:23:53.720906 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9587 12:23:53.724487 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9588 12:23:53.730977 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9589 12:23:53.734451 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9590 12:23:53.740753 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9591 12:23:53.744354 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9592 12:23:53.748273 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9593 12:23:53.754261 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9594 12:23:53.757550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9595 12:23:53.761074 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9596 12:23:53.767459 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9597 12:23:53.770687 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9598 12:23:53.777171 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9599 12:23:53.780650 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9600 12:23:53.787224 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9601 12:23:53.790327 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9602 12:23:53.793591 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9603 12:23:53.800305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9604 12:23:53.803441 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9605 12:23:53.810498 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9606 12:23:53.813548 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9607 12:23:53.820512 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9608 12:23:53.823622 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9609 12:23:53.830008 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9610 12:23:53.833550 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9611 12:23:53.836896 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9612 12:23:53.843269 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9613 12:23:53.846677 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9614 12:23:53.853604 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9615 12:23:53.856310 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9616 12:23:53.863156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9617 12:23:53.866179 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9618 12:23:53.869720 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9619 12:23:53.876328 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9620 12:23:53.879279 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9621 12:23:53.886342 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9622 12:23:53.889434 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9623 12:23:53.896298 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9624 12:23:53.899893 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9625 12:23:53.905872 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9626 12:23:53.909127 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9627 12:23:53.912306 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9628 12:23:53.919242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9629 12:23:53.922590 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9630 12:23:53.928938 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9631 12:23:53.932083 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9632 12:23:53.938958 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9633 12:23:53.942425 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9634 12:23:53.948684 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9635 12:23:53.952116 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9636 12:23:53.955846 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9637 12:23:53.962190 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9638 12:23:53.965576 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9639 12:23:53.972145 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9640 12:23:53.975153 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9641 12:23:53.981909 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9642 12:23:53.985180 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9643 12:23:53.991721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9644 12:23:53.995240 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9645 12:23:53.998273 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9646 12:23:54.005197 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9647 12:23:54.008511 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9648 12:23:54.015408 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9649 12:23:54.018535 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9650 12:23:54.024748 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9651 12:23:54.028165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9652 12:23:54.031727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9653 12:23:54.038193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9654 12:23:54.041928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9655 12:23:54.048074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9656 12:23:54.051706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9657 12:23:54.058337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9658 12:23:54.061306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9659 12:23:54.068148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9660 12:23:54.071455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9661 12:23:54.078073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9662 12:23:54.081406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9663 12:23:54.087977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9664 12:23:54.091492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9665 12:23:54.098216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9666 12:23:54.101196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9667 12:23:54.107666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9668 12:23:54.111415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9669 12:23:54.114680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9670 12:23:54.121187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9671 12:23:54.127704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9672 12:23:54.130869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9673 12:23:54.137890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9674 12:23:54.141170 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9675 12:23:54.148253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9676 12:23:54.151113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9677 12:23:54.158255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9678 12:23:54.161451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9679 12:23:54.167632 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9680 12:23:54.170668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9681 12:23:54.177495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9682 12:23:54.180996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9683 12:23:54.183898 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9684 12:23:54.187338 INFO: [APUAPC] vio 0
9685 12:23:54.190800 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9686 12:23:54.197384 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9687 12:23:54.200966 INFO: [APUAPC] D0_APC_0: 0x400510
9688 12:23:54.203962 INFO: [APUAPC] D0_APC_1: 0x0
9689 12:23:54.207527 INFO: [APUAPC] D0_APC_2: 0x1540
9690 12:23:54.207988 INFO: [APUAPC] D0_APC_3: 0x0
9691 12:23:54.211076 INFO: [APUAPC] D1_APC_0: 0xffffffff
9692 12:23:54.217459 INFO: [APUAPC] D1_APC_1: 0xffffffff
9693 12:23:54.218011 INFO: [APUAPC] D1_APC_2: 0x3fffff
9694 12:23:54.220933 INFO: [APUAPC] D1_APC_3: 0x0
9695 12:23:54.224123 INFO: [APUAPC] D2_APC_0: 0xffffffff
9696 12:23:54.227320 INFO: [APUAPC] D2_APC_1: 0xffffffff
9697 12:23:54.230722 INFO: [APUAPC] D2_APC_2: 0x3fffff
9698 12:23:54.233970 INFO: [APUAPC] D2_APC_3: 0x0
9699 12:23:54.237252 INFO: [APUAPC] D3_APC_0: 0xffffffff
9700 12:23:54.240297 INFO: [APUAPC] D3_APC_1: 0xffffffff
9701 12:23:54.243752 INFO: [APUAPC] D3_APC_2: 0x3fffff
9702 12:23:54.247169 INFO: [APUAPC] D3_APC_3: 0x0
9703 12:23:54.250369 INFO: [APUAPC] D4_APC_0: 0xffffffff
9704 12:23:54.253751 INFO: [APUAPC] D4_APC_1: 0xffffffff
9705 12:23:54.257080 INFO: [APUAPC] D4_APC_2: 0x3fffff
9706 12:23:54.260305 INFO: [APUAPC] D4_APC_3: 0x0
9707 12:23:54.264029 INFO: [APUAPC] D5_APC_0: 0xffffffff
9708 12:23:54.267089 INFO: [APUAPC] D5_APC_1: 0xffffffff
9709 12:23:54.270337 INFO: [APUAPC] D5_APC_2: 0x3fffff
9710 12:23:54.273828 INFO: [APUAPC] D5_APC_3: 0x0
9711 12:23:54.276879 INFO: [APUAPC] D6_APC_0: 0xffffffff
9712 12:23:54.280554 INFO: [APUAPC] D6_APC_1: 0xffffffff
9713 12:23:54.283266 INFO: [APUAPC] D6_APC_2: 0x3fffff
9714 12:23:54.287004 INFO: [APUAPC] D6_APC_3: 0x0
9715 12:23:54.290003 INFO: [APUAPC] D7_APC_0: 0xffffffff
9716 12:23:54.293494 INFO: [APUAPC] D7_APC_1: 0xffffffff
9717 12:23:54.296772 INFO: [APUAPC] D7_APC_2: 0x3fffff
9718 12:23:54.299739 INFO: [APUAPC] D7_APC_3: 0x0
9719 12:23:54.302955 INFO: [APUAPC] D8_APC_0: 0xffffffff
9720 12:23:54.306294 INFO: [APUAPC] D8_APC_1: 0xffffffff
9721 12:23:54.309582 INFO: [APUAPC] D8_APC_2: 0x3fffff
9722 12:23:54.313010 INFO: [APUAPC] D8_APC_3: 0x0
9723 12:23:54.317161 INFO: [APUAPC] D9_APC_0: 0xffffffff
9724 12:23:54.320321 INFO: [APUAPC] D9_APC_1: 0xffffffff
9725 12:23:54.323326 INFO: [APUAPC] D9_APC_2: 0x3fffff
9726 12:23:54.326431 INFO: [APUAPC] D9_APC_3: 0x0
9727 12:23:54.329897 INFO: [APUAPC] D10_APC_0: 0xffffffff
9728 12:23:54.332813 INFO: [APUAPC] D10_APC_1: 0xffffffff
9729 12:23:54.336688 INFO: [APUAPC] D10_APC_2: 0x3fffff
9730 12:23:54.340116 INFO: [APUAPC] D10_APC_3: 0x0
9731 12:23:54.342682 INFO: [APUAPC] D11_APC_0: 0xffffffff
9732 12:23:54.346445 INFO: [APUAPC] D11_APC_1: 0xffffffff
9733 12:23:54.349528 INFO: [APUAPC] D11_APC_2: 0x3fffff
9734 12:23:54.352779 INFO: [APUAPC] D11_APC_3: 0x0
9735 12:23:54.356371 INFO: [APUAPC] D12_APC_0: 0xffffffff
9736 12:23:54.359549 INFO: [APUAPC] D12_APC_1: 0xffffffff
9737 12:23:54.362842 INFO: [APUAPC] D12_APC_2: 0x3fffff
9738 12:23:54.366105 INFO: [APUAPC] D12_APC_3: 0x0
9739 12:23:54.369671 INFO: [APUAPC] D13_APC_0: 0xffffffff
9740 12:23:54.372897 INFO: [APUAPC] D13_APC_1: 0xffffffff
9741 12:23:54.375915 INFO: [APUAPC] D13_APC_2: 0x3fffff
9742 12:23:54.379453 INFO: [APUAPC] D13_APC_3: 0x0
9743 12:23:54.382947 INFO: [APUAPC] D14_APC_0: 0xffffffff
9744 12:23:54.386604 INFO: [APUAPC] D14_APC_1: 0xffffffff
9745 12:23:54.389381 INFO: [APUAPC] D14_APC_2: 0x3fffff
9746 12:23:54.393029 INFO: [APUAPC] D14_APC_3: 0x0
9747 12:23:54.396100 INFO: [APUAPC] D15_APC_0: 0xffffffff
9748 12:23:54.398935 INFO: [APUAPC] D15_APC_1: 0xffffffff
9749 12:23:54.402474 INFO: [APUAPC] D15_APC_2: 0x3fffff
9750 12:23:54.405540 INFO: [APUAPC] D15_APC_3: 0x0
9751 12:23:54.408745 INFO: [APUAPC] APC_CON: 0x4
9752 12:23:54.412514 INFO: [NOCDAPC] D0_APC_0: 0x0
9753 12:23:54.415437 INFO: [NOCDAPC] D0_APC_1: 0x0
9754 12:23:54.419248 INFO: [NOCDAPC] D1_APC_0: 0x0
9755 12:23:54.422323 INFO: [NOCDAPC] D1_APC_1: 0xfff
9756 12:23:54.422889 INFO: [NOCDAPC] D2_APC_0: 0x0
9757 12:23:54.425357 INFO: [NOCDAPC] D2_APC_1: 0xfff
9758 12:23:54.428772 INFO: [NOCDAPC] D3_APC_0: 0x0
9759 12:23:54.432467 INFO: [NOCDAPC] D3_APC_1: 0xfff
9760 12:23:54.435701 INFO: [NOCDAPC] D4_APC_0: 0x0
9761 12:23:54.438522 INFO: [NOCDAPC] D4_APC_1: 0xfff
9762 12:23:54.442403 INFO: [NOCDAPC] D5_APC_0: 0x0
9763 12:23:54.445435 INFO: [NOCDAPC] D5_APC_1: 0xfff
9764 12:23:54.448833 INFO: [NOCDAPC] D6_APC_0: 0x0
9765 12:23:54.452035 INFO: [NOCDAPC] D6_APC_1: 0xfff
9766 12:23:54.455483 INFO: [NOCDAPC] D7_APC_0: 0x0
9767 12:23:54.456033 INFO: [NOCDAPC] D7_APC_1: 0xfff
9768 12:23:54.459465 INFO: [NOCDAPC] D8_APC_0: 0x0
9769 12:23:54.462322 INFO: [NOCDAPC] D8_APC_1: 0xfff
9770 12:23:54.465336 INFO: [NOCDAPC] D9_APC_0: 0x0
9771 12:23:54.469137 INFO: [NOCDAPC] D9_APC_1: 0xfff
9772 12:23:54.472367 INFO: [NOCDAPC] D10_APC_0: 0x0
9773 12:23:54.475710 INFO: [NOCDAPC] D10_APC_1: 0xfff
9774 12:23:54.478683 INFO: [NOCDAPC] D11_APC_0: 0x0
9775 12:23:54.482100 INFO: [NOCDAPC] D11_APC_1: 0xfff
9776 12:23:54.485472 INFO: [NOCDAPC] D12_APC_0: 0x0
9777 12:23:54.488448 INFO: [NOCDAPC] D12_APC_1: 0xfff
9778 12:23:54.491966 INFO: [NOCDAPC] D13_APC_0: 0x0
9779 12:23:54.495280 INFO: [NOCDAPC] D13_APC_1: 0xfff
9780 12:23:54.495857 INFO: [NOCDAPC] D14_APC_0: 0x0
9781 12:23:54.498442 INFO: [NOCDAPC] D14_APC_1: 0xfff
9782 12:23:54.501751 INFO: [NOCDAPC] D15_APC_0: 0x0
9783 12:23:54.504987 INFO: [NOCDAPC] D15_APC_1: 0xfff
9784 12:23:54.508364 INFO: [NOCDAPC] APC_CON: 0x4
9785 12:23:54.511866 INFO: [APUAPC] set_apusys_apc done
9786 12:23:54.515012 INFO: [DEVAPC] devapc_init done
9787 12:23:54.518759 INFO: GICv3 without legacy support detected.
9788 12:23:54.525222 INFO: ARM GICv3 driver initialized in EL3
9789 12:23:54.528672 INFO: Maximum SPI INTID supported: 639
9790 12:23:54.532070 INFO: BL31: Initializing runtime services
9791 12:23:54.538493 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9792 12:23:54.539065 INFO: SPM: enable CPC mode
9793 12:23:54.545178 INFO: mcdi ready for mcusys-off-idle and system suspend
9794 12:23:54.548298 INFO: BL31: Preparing for EL3 exit to normal world
9795 12:23:54.555133 INFO: Entry point address = 0x80000000
9796 12:23:54.555681 INFO: SPSR = 0x8
9797 12:23:54.561063
9798 12:23:54.561623
9799 12:23:54.561983
9800 12:23:54.564709 Starting depthcharge on Spherion...
9801 12:23:54.565256
9802 12:23:54.565615 Wipe memory regions:
9803 12:23:54.565950
9804 12:23:54.568833 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9805 12:23:54.569401 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9806 12:23:54.569852 Setting prompt string to ['asurada:']
9807 12:23:54.570291 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9808 12:23:54.571006 [0x00000040000000, 0x00000054600000)
9809 12:23:54.690088
9810 12:23:54.690635 [0x00000054660000, 0x00000080000000)
9811 12:23:54.950822
9812 12:23:54.951368 [0x000000821a7280, 0x000000ffe64000)
9813 12:23:55.695563
9814 12:23:55.696110 [0x00000100000000, 0x00000140000000)
9815 12:23:56.076900
9816 12:23:56.080055 Initializing XHCI USB controller at 0x11200000.
9817 12:23:57.117855
9818 12:23:57.121754 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9819 12:23:57.122219
9820 12:23:57.122627
9821 12:23:57.122985
9822 12:23:57.123796 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9824 12:23:57.225154 asurada: tftpboot 192.168.201.1 11893158/tftp-deploy-cjli5no0/kernel/image.itb 11893158/tftp-deploy-cjli5no0/kernel/cmdline
9825 12:23:57.225802 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9826 12:23:57.226285 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9827 12:23:57.230456 tftpboot 192.168.201.1 11893158/tftp-deploy-cjli5no0/kernel/image.itp-deploy-cjli5no0/kernel/cmdline
9828 12:23:57.230916
9829 12:23:57.231275 Waiting for link
9830 12:23:57.391304
9831 12:23:57.391847 R8152: Initializing
9832 12:23:57.392271
9833 12:23:57.394740 Version 9 (ocp_data = 6010)
9834 12:23:57.395320
9835 12:23:57.397773 R8152: Done initializing
9836 12:23:57.398329
9837 12:23:57.398688 Adding net device
9838 12:23:59.321343
9839 12:23:59.321909 done.
9840 12:23:59.322269
9841 12:23:59.322602 MAC: 00:e0:4c:68:03:bd
9842 12:23:59.322922
9843 12:23:59.324683 Sending DHCP discover... done.
9844 12:23:59.325193
9845 12:24:09.323627 Waiting for reply... R8152: Bulk read error 0xffffffbf
9846 12:24:09.324220
9847 12:24:09.327314 Receive failed.
9848 12:24:09.327876
9849 12:24:09.328296 done.
9850 12:24:09.328858
9851 12:24:09.330165 Sending DHCP request... done.
9852 12:24:09.330644
9853 12:24:09.333670 Waiting for reply... done.
9854 12:24:09.334128
9855 12:24:09.336986 My ip is 192.168.201.16
9856 12:24:09.337443
9857 12:24:09.340122 The DHCP server ip is 192.168.201.1
9858 12:24:09.340661
9859 12:24:09.343831 TFTP server IP predefined by user: 192.168.201.1
9860 12:24:09.344375
9861 12:24:09.350275 Bootfile predefined by user: 11893158/tftp-deploy-cjli5no0/kernel/image.itb
9862 12:24:09.350830
9863 12:24:09.353947 Sending tftp read request... done.
9864 12:24:09.354535
9865 12:24:09.361793 Waiting for the transfer...
9866 12:24:09.362301
9867 12:24:09.702438 00000000 ################################################################
9868 12:24:09.702575
9869 12:24:10.001807 00080000 ################################################################
9870 12:24:10.001952
9871 12:24:10.301954 00100000 ################################################################
9872 12:24:10.302087
9873 12:24:10.586021 00180000 ################################################################
9874 12:24:10.586178
9875 12:24:10.968787 00200000 ################################################################
9876 12:24:10.969459
9877 12:24:11.349966 00280000 ################################################################
9878 12:24:11.350448
9879 12:24:11.734595 00300000 ################################################################
9880 12:24:11.735297
9881 12:24:12.144321 00380000 ################################################################
9882 12:24:12.144806
9883 12:24:12.550301 00400000 ################################################################
9884 12:24:12.550784
9885 12:24:12.969559 00480000 ################################################################
9886 12:24:12.970085
9887 12:24:13.335951 00500000 ################################################################
9888 12:24:13.336513
9889 12:24:13.661074 00580000 ################################################################
9890 12:24:13.661210
9891 12:24:13.965487 00600000 ################################################################
9892 12:24:13.965614
9893 12:24:14.375506 00680000 ################################################################
9894 12:24:14.376017
9895 12:24:14.777938 00700000 ################################################################
9896 12:24:14.778578
9897 12:24:15.161247 00780000 ################################################################
9898 12:24:15.161384
9899 12:24:15.460827 00800000 ################################################################
9900 12:24:15.460964
9901 12:24:15.721971 00880000 ################################################################
9902 12:24:15.722098
9903 12:24:16.017232 00900000 ################################################################
9904 12:24:16.017366
9905 12:24:16.307472 00980000 ################################################################
9906 12:24:16.307604
9907 12:24:16.562096 00a00000 ################################################################
9908 12:24:16.562225
9909 12:24:16.842919 00a80000 ################################################################
9910 12:24:16.843048
9911 12:24:17.136105 00b00000 ################################################################
9912 12:24:17.136279
9913 12:24:17.439193 00b80000 ################################################################
9914 12:24:17.439348
9915 12:24:17.733969 00c00000 ################################################################
9916 12:24:17.734100
9917 12:24:18.033655 00c80000 ################################################################
9918 12:24:18.033791
9919 12:24:18.325981 00d00000 ################################################################
9920 12:24:18.326116
9921 12:24:18.628810 00d80000 ################################################################
9922 12:24:18.628965
9923 12:24:18.929259 00e00000 ################################################################
9924 12:24:18.929389
9925 12:24:19.230505 00e80000 ################################################################
9926 12:24:19.230639
9927 12:24:19.523349 00f00000 ################################################################
9928 12:24:19.523483
9929 12:24:19.844479 00f80000 ################################################################
9930 12:24:19.844613
9931 12:24:20.157832 01000000 ################################################################
9932 12:24:20.158326
9933 12:24:20.543276 01080000 ################################################################
9934 12:24:20.543575
9935 12:24:20.830973 01100000 ################################################################
9936 12:24:20.831135
9937 12:24:21.103715 01180000 ################################################################
9938 12:24:21.103865
9939 12:24:21.381185 01200000 ################################################################
9940 12:24:21.381350
9941 12:24:21.675644 01280000 ################################################################
9942 12:24:21.675778
9943 12:24:21.957061 01300000 ################################################################
9944 12:24:21.957194
9945 12:24:22.254494 01380000 ################################################################
9946 12:24:22.254626
9947 12:24:22.555116 01400000 ################################################################
9948 12:24:22.555262
9949 12:24:22.921022 01480000 ################################################################
9950 12:24:22.921504
9951 12:24:23.308610 01500000 ################################################################
9952 12:24:23.309097
9953 12:24:23.690462 01580000 ################################################################
9954 12:24:23.691164
9955 12:24:24.084688 01600000 ################################################################
9956 12:24:24.085225
9957 12:24:24.477970 01680000 ################################################################
9958 12:24:24.478505
9959 12:24:24.767131 01700000 ################################################################
9960 12:24:24.767303
9961 12:24:25.064990 01780000 ################################################################
9962 12:24:25.065158
9963 12:24:25.368879 01800000 ################################################################
9964 12:24:25.369016
9965 12:24:25.669738 01880000 ################################################################
9966 12:24:25.669884
9967 12:24:25.954561 01900000 ################################################################
9968 12:24:25.954716
9969 12:24:26.228082 01980000 ################################################################
9970 12:24:26.228220
9971 12:24:26.502106 01a00000 ################################################################
9972 12:24:26.502260
9973 12:24:26.810450 01a80000 ################################################################
9974 12:24:26.810788
9975 12:24:27.218112 01b00000 ################################################################
9976 12:24:27.218625
9977 12:24:27.263154 01b80000 ####### done.
9978 12:24:27.263572
9979 12:24:27.266664 The bootfile was 28889830 bytes long.
9980 12:24:27.267078
9981 12:24:27.269732 Sending tftp read request... done.
9982 12:24:27.270139
9983 12:24:27.273363 Waiting for the transfer...
9984 12:24:27.273835
9985 12:24:27.274159 00000000 # done.
9986 12:24:27.274473
9987 12:24:27.280123 Command line loaded dynamically from TFTP file: 11893158/tftp-deploy-cjli5no0/kernel/cmdline
9988 12:24:27.280578
9989 12:24:27.303555 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893158/extract-nfsrootfs-9jokrc83,tcp,hard ip=dhcp tftpserverip=192.168.201.1
9990 12:24:27.303980
9991 12:24:27.304328 Loading FIT.
9992 12:24:27.304631
9993 12:24:27.306838 Image ramdisk-1 has 17792522 bytes.
9994 12:24:27.307244
9995 12:24:27.310188 Image fdt-1 has 47278 bytes.
9996 12:24:27.310722
9997 12:24:27.313780 Image kernel-1 has 11047994 bytes.
9998 12:24:27.314190
9999 12:24:27.323185 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10000 12:24:27.323685
10001 12:24:27.339978 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10002 12:24:27.340544
10003 12:24:27.346514 Choosing best match conf-1 for compat google,spherion-rev3.
10004 12:24:27.347027
10005 12:24:27.354392 Connected to device vid:did:rid of 1ae0:0028:00
10006 12:24:27.362812
10007 12:24:27.365374 tpm_get_response: command 0x17b, return code 0x0
10008 12:24:27.365785
10009 12:24:27.368846 ec_init: CrosEC protocol v3 supported (256, 248)
10010 12:24:27.372998
10011 12:24:27.376352 tpm_cleanup: add release locality here.
10012 12:24:27.376779
10013 12:24:27.377217 Shutting down all USB controllers.
10014 12:24:27.379391
10015 12:24:27.379814 Removing current net device
10016 12:24:27.380294
10017 12:24:27.386138 Exiting depthcharge with code 4 at timestamp: 61050331
10018 12:24:27.386650
10019 12:24:27.389807 LZMA decompressing kernel-1 to 0x821a6718
10020 12:24:27.390337
10021 12:24:27.392770 LZMA decompressing kernel-1 to 0x40000000
10022 12:24:28.781023
10023 12:24:28.781595 jumping to kernel
10024 12:24:28.785391 end: 2.2.4 bootloader-commands (duration 00:00:34) [common]
10025 12:24:28.786152 start: 2.2.5 auto-login-action (timeout 00:03:52) [common]
10026 12:24:28.786522 Setting prompt string to ['Linux version [0-9]']
10027 12:24:28.786628 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10028 12:24:28.786734 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10029 12:24:28.831008
10030 12:24:28.834829 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10031 12:24:28.837951 start: 2.2.5.1 login-action (timeout 00:03:52) [common]
10032 12:24:28.838218 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10033 12:24:28.838410 Setting prompt string to []
10034 12:24:28.838613 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10035 12:24:28.838806 Using line separator: #'\n'#
10036 12:24:28.838965 No login prompt set.
10037 12:24:28.839138 Parsing kernel messages
10038 12:24:28.839288 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10039 12:24:28.839583 [login-action] Waiting for messages, (timeout 00:03:52)
10040 12:24:28.858133 [ 0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023
10041 12:24:28.860804 [ 0.000000] random: crng init done
10042 12:24:28.867673 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10043 12:24:28.870895 [ 0.000000] efi: UEFI not found.
10044 12:24:28.877376 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10045 12:24:28.883898 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10046 12:24:28.894051 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10047 12:24:28.903756 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10048 12:24:28.910329 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10049 12:24:28.917099 [ 0.000000] printk: bootconsole [mtk8250] enabled
10050 12:24:28.923647 [ 0.000000] NUMA: No NUMA configuration found
10051 12:24:28.930374 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10052 12:24:28.933290 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10053 12:24:28.936746 [ 0.000000] Zone ranges:
10054 12:24:28.943107 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10055 12:24:28.946750 [ 0.000000] DMA32 empty
10056 12:24:28.952953 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10057 12:24:28.956665 [ 0.000000] Movable zone start for each node
10058 12:24:28.960315 [ 0.000000] Early memory node ranges
10059 12:24:28.966440 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10060 12:24:28.972959 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10061 12:24:28.979646 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10062 12:24:28.986171 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10063 12:24:28.993048 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10064 12:24:28.999305 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10065 12:24:29.029432 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10066 12:24:29.036229 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10067 12:24:29.042921 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10068 12:24:29.046640 [ 0.000000] psci: probing for conduit method from DT.
10069 12:24:29.053091 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10070 12:24:29.056367 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10071 12:24:29.062765 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10072 12:24:29.066110 [ 0.000000] psci: SMC Calling Convention v1.2
10073 12:24:29.072481 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10074 12:24:29.075937 [ 0.000000] Detected VIPT I-cache on CPU0
10075 12:24:29.082294 [ 0.000000] CPU features: detected: GIC system register CPU interface
10076 12:24:29.089178 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10077 12:24:29.095898 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10078 12:24:29.102060 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10079 12:24:29.112536 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10080 12:24:29.119135 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10081 12:24:29.121726 [ 0.000000] alternatives: applying boot alternatives
10082 12:24:29.128562 [ 0.000000] Fallback order for Node 0: 0
10083 12:24:29.135254 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10084 12:24:29.138721 [ 0.000000] Policy zone: Normal
10085 12:24:29.161941 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893158/extract-nfsrootfs-9jokrc83,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10086 12:24:29.171302 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10087 12:24:29.181414 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10088 12:24:29.188124 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10089 12:24:29.194650 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10090 12:24:29.201486 <6>[ 0.000000] software IO TLB: area num 8.
10091 12:24:29.256273 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10092 12:24:29.336472 <6>[ 0.000000] Memory: 3837700K/4191232K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 320764K reserved, 32768K cma-reserved)
10093 12:24:29.343005 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10094 12:24:29.349443 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10095 12:24:29.352973 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10096 12:24:29.359523 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10097 12:24:29.366510 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10098 12:24:29.369061 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10099 12:24:29.379832 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10100 12:24:29.385700 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10101 12:24:29.392832 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10102 12:24:29.399148 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10103 12:24:29.402121 <6>[ 0.000000] GICv3: 608 SPIs implemented
10104 12:24:29.405520 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10105 12:24:29.412329 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10106 12:24:29.415547 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10107 12:24:29.421922 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10108 12:24:29.435435 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10109 12:24:29.448165 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10110 12:24:29.454753 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10111 12:24:29.462573 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10112 12:24:29.475905 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10113 12:24:29.482416 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10114 12:24:29.489381 <6>[ 0.009225] Console: colour dummy device 80x25
10115 12:24:29.499605 <6>[ 0.013980] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10116 12:24:29.506096 <6>[ 0.024421] pid_max: default: 32768 minimum: 301
10117 12:24:29.509519 <6>[ 0.029293] LSM: Security Framework initializing
10118 12:24:29.515960 <6>[ 0.034207] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10119 12:24:29.525877 <6>[ 0.041814] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10120 12:24:29.532487 <6>[ 0.051101] cblist_init_generic: Setting adjustable number of callback queues.
10121 12:24:29.539118 <6>[ 0.058543] cblist_init_generic: Setting shift to 3 and lim to 1.
10122 12:24:29.548846 <6>[ 0.064882] cblist_init_generic: Setting adjustable number of callback queues.
10123 12:24:29.555193 <6>[ 0.072356] cblist_init_generic: Setting shift to 3 and lim to 1.
10124 12:24:29.558934 <6>[ 0.078754] rcu: Hierarchical SRCU implementation.
10125 12:24:29.565388 <6>[ 0.083771] rcu: Max phase no-delay instances is 1000.
10126 12:24:29.571618 <6>[ 0.090789] EFI services will not be available.
10127 12:24:29.574972 <6>[ 0.095774] smp: Bringing up secondary CPUs ...
10128 12:24:29.583203 <6>[ 0.100818] Detected VIPT I-cache on CPU1
10129 12:24:29.590030 <6>[ 0.100887] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10130 12:24:29.596468 <6>[ 0.100917] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10131 12:24:29.599793 <6>[ 0.101254] Detected VIPT I-cache on CPU2
10132 12:24:29.609661 <6>[ 0.101305] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10133 12:24:29.616271 <6>[ 0.101323] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10134 12:24:29.619669 <6>[ 0.101582] Detected VIPT I-cache on CPU3
10135 12:24:29.626384 <6>[ 0.101627] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10136 12:24:29.632791 <6>[ 0.101641] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10137 12:24:29.639448 <6>[ 0.101946] CPU features: detected: Spectre-v4
10138 12:24:29.642682 <6>[ 0.101952] CPU features: detected: Spectre-BHB
10139 12:24:29.645967 <6>[ 0.101956] Detected PIPT I-cache on CPU4
10140 12:24:29.652506 <6>[ 0.102014] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10141 12:24:29.658932 <6>[ 0.102030] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10142 12:24:29.665752 <6>[ 0.102313] Detected PIPT I-cache on CPU5
10143 12:24:29.672282 <6>[ 0.102369] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10144 12:24:29.679162 <6>[ 0.102385] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10145 12:24:29.682162 <6>[ 0.102656] Detected PIPT I-cache on CPU6
10146 12:24:29.688973 <6>[ 0.102718] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10147 12:24:29.698654 <6>[ 0.102734] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10148 12:24:29.702198 <6>[ 0.103034] Detected PIPT I-cache on CPU7
10149 12:24:29.708667 <6>[ 0.103101] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10150 12:24:29.715199 <6>[ 0.103118] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10151 12:24:29.718388 <6>[ 0.103166] smp: Brought up 1 node, 8 CPUs
10152 12:24:29.725098 <6>[ 0.244475] SMP: Total of 8 processors activated.
10153 12:24:29.728687 <6>[ 0.249396] CPU features: detected: 32-bit EL0 Support
10154 12:24:29.738638 <6>[ 0.254792] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10155 12:24:29.745202 <6>[ 0.263593] CPU features: detected: Common not Private translations
10156 12:24:29.751602 <6>[ 0.270068] CPU features: detected: CRC32 instructions
10157 12:24:29.758260 <6>[ 0.275419] CPU features: detected: RCpc load-acquire (LDAPR)
10158 12:24:29.761541 <6>[ 0.281380] CPU features: detected: LSE atomic instructions
10159 12:24:29.768325 <6>[ 0.287162] CPU features: detected: Privileged Access Never
10160 12:24:29.774688 <6>[ 0.292941] CPU features: detected: RAS Extension Support
10161 12:24:29.781473 <6>[ 0.298551] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10162 12:24:29.784489 <6>[ 0.305770] CPU: All CPU(s) started at EL2
10163 12:24:29.791059 <6>[ 0.310113] alternatives: applying system-wide alternatives
10164 12:24:29.800507 <6>[ 0.320020] devtmpfs: initialized
10165 12:24:29.815122 <6>[ 0.328208] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10166 12:24:29.821861 <6>[ 0.338169] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10167 12:24:29.827996 <6>[ 0.346363] pinctrl core: initialized pinctrl subsystem
10168 12:24:29.831436 <6>[ 0.353035] DMI not present or invalid.
10169 12:24:29.838159 <6>[ 0.357438] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10170 12:24:29.848084 <6>[ 0.364306] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10171 12:24:29.854486 <6>[ 0.371761] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10172 12:24:29.864856 <6>[ 0.379851] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10173 12:24:29.867939 <6>[ 0.388007] audit: initializing netlink subsys (disabled)
10174 12:24:29.877573 <5>[ 0.393702] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10175 12:24:29.884211 <6>[ 0.394404] thermal_sys: Registered thermal governor 'step_wise'
10176 12:24:29.891164 <6>[ 0.401672] thermal_sys: Registered thermal governor 'power_allocator'
10177 12:24:29.894684 <6>[ 0.407928] cpuidle: using governor menu
10178 12:24:29.900791 <6>[ 0.418890] NET: Registered PF_QIPCRTR protocol family
10179 12:24:29.907742 <6>[ 0.424379] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10180 12:24:29.910676 <6>[ 0.431484] ASID allocator initialised with 32768 entries
10181 12:24:29.918670 <6>[ 0.438015] Serial: AMBA PL011 UART driver
10182 12:24:29.926744 <4>[ 0.446770] Trying to register duplicate clock ID: 134
10183 12:24:29.980628 <6>[ 0.503887] KASLR enabled
10184 12:24:29.994957 <6>[ 0.511560] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10185 12:24:30.001764 <6>[ 0.518576] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10186 12:24:30.008346 <6>[ 0.525065] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10187 12:24:30.015440 <6>[ 0.532070] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10188 12:24:30.021504 <6>[ 0.538560] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10189 12:24:30.028017 <6>[ 0.545565] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10190 12:24:30.034484 <6>[ 0.552054] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10191 12:24:30.040754 <6>[ 0.559059] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10192 12:24:30.044133 <6>[ 0.566485] ACPI: Interpreter disabled.
10193 12:24:30.052694 <6>[ 0.572881] iommu: Default domain type: Translated
10194 12:24:30.059578 <6>[ 0.578036] iommu: DMA domain TLB invalidation policy: strict mode
10195 12:24:30.062878 <5>[ 0.584698] SCSI subsystem initialized
10196 12:24:30.069281 <6>[ 0.588962] usbcore: registered new interface driver usbfs
10197 12:24:30.075903 <6>[ 0.594694] usbcore: registered new interface driver hub
10198 12:24:30.079421 <6>[ 0.600248] usbcore: registered new device driver usb
10199 12:24:30.086436 <6>[ 0.606372] pps_core: LinuxPPS API ver. 1 registered
10200 12:24:30.096435 <6>[ 0.611566] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10201 12:24:30.099668 <6>[ 0.620910] PTP clock support registered
10202 12:24:30.102945 <6>[ 0.625153] EDAC MC: Ver: 3.0.0
10203 12:24:30.110342 <6>[ 0.630315] FPGA manager framework
10204 12:24:30.117446 <6>[ 0.633992] Advanced Linux Sound Architecture Driver Initialized.
10205 12:24:30.120258 <6>[ 0.640764] vgaarb: loaded
10206 12:24:30.126781 <6>[ 0.643938] clocksource: Switched to clocksource arch_sys_counter
10207 12:24:30.130515 <5>[ 0.650388] VFS: Disk quotas dquot_6.6.0
10208 12:24:30.137052 <6>[ 0.654574] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10209 12:24:30.140394 <6>[ 0.661767] pnp: PnP ACPI: disabled
10210 12:24:30.148733 <6>[ 0.668515] NET: Registered PF_INET protocol family
10211 12:24:30.154937 <6>[ 0.673909] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10212 12:24:30.167447 <6>[ 0.683947] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10213 12:24:30.177324 <6>[ 0.692734] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10214 12:24:30.183862 <6>[ 0.700701] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10215 12:24:30.190670 <6>[ 0.709104] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10216 12:24:30.201209 <6>[ 0.717758] TCP: Hash tables configured (established 32768 bind 32768)
10217 12:24:30.208143 <6>[ 0.724608] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10218 12:24:30.214458 <6>[ 0.731631] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10219 12:24:30.221019 <6>[ 0.739124] NET: Registered PF_UNIX/PF_LOCAL protocol family
10220 12:24:30.227709 <6>[ 0.745198] RPC: Registered named UNIX socket transport module.
10221 12:24:30.230989 <6>[ 0.751348] RPC: Registered udp transport module.
10222 12:24:30.237598 <6>[ 0.756279] RPC: Registered tcp transport module.
10223 12:24:30.244224 <6>[ 0.761212] RPC: Registered tcp NFSv4.1 backchannel transport module.
10224 12:24:30.247794 <6>[ 0.767876] PCI: CLS 0 bytes, default 64
10225 12:24:30.250969 <6>[ 0.772213] Unpacking initramfs...
10226 12:24:30.261105 <6>[ 0.776373] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10227 12:24:30.267744 <6>[ 0.785015] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10228 12:24:30.273816 <6>[ 0.793847] kvm [1]: IPA Size Limit: 40 bits
10229 12:24:30.276991 <6>[ 0.798374] kvm [1]: GICv3: no GICV resource entry
10230 12:24:30.283685 <6>[ 0.803396] kvm [1]: disabling GICv2 emulation
10231 12:24:30.290678 <6>[ 0.808084] kvm [1]: GIC system register CPU interface enabled
10232 12:24:30.294054 <6>[ 0.814247] kvm [1]: vgic interrupt IRQ18
10233 12:24:30.300563 <6>[ 0.818623] kvm [1]: VHE mode initialized successfully
10234 12:24:30.303646 <5>[ 0.825087] Initialise system trusted keyrings
10235 12:24:30.309931 <6>[ 0.829878] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10236 12:24:30.320219 <6>[ 0.839813] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10237 12:24:30.326678 <5>[ 0.846191] NFS: Registering the id_resolver key type
10238 12:24:30.329856 <5>[ 0.851494] Key type id_resolver registered
10239 12:24:30.336570 <5>[ 0.855910] Key type id_legacy registered
10240 12:24:30.343279 <6>[ 0.860193] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10241 12:24:30.349836 <6>[ 0.867114] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10242 12:24:30.356626 <6>[ 0.874834] 9p: Installing v9fs 9p2000 file system support
10243 12:24:30.393169 <5>[ 0.912909] Key type asymmetric registered
10244 12:24:30.396274 <5>[ 0.917243] Asymmetric key parser 'x509' registered
10245 12:24:30.406342 <6>[ 0.922388] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10246 12:24:30.409928 <6>[ 0.930000] io scheduler mq-deadline registered
10247 12:24:30.413103 <6>[ 0.934762] io scheduler kyber registered
10248 12:24:30.432340 <6>[ 0.952057] EINJ: ACPI disabled.
10249 12:24:30.464383 <4>[ 0.977690] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10250 12:24:30.474076 <4>[ 0.988299] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10251 12:24:30.489116 <6>[ 1.008887] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10252 12:24:30.496635 <6>[ 1.016823] printk: console [ttyS0] disabled
10253 12:24:30.524979 <6>[ 1.041477] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10254 12:24:30.531581 <6>[ 1.050953] printk: console [ttyS0] enabled
10255 12:24:30.534995 <6>[ 1.050953] printk: console [ttyS0] enabled
10256 12:24:30.541585 <6>[ 1.059857] printk: bootconsole [mtk8250] disabled
10257 12:24:30.544699 <6>[ 1.059857] printk: bootconsole [mtk8250] disabled
10258 12:24:30.551334 <6>[ 1.071124] SuperH (H)SCI(F) driver initialized
10259 12:24:30.554672 <6>[ 1.076422] msm_serial: driver initialized
10260 12:24:30.569117 <6>[ 1.085426] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10261 12:24:30.578598 <6>[ 1.093974] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10262 12:24:30.585099 <6>[ 1.102515] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10263 12:24:30.595319 <6>[ 1.111145] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10264 12:24:30.605211 <6>[ 1.119863] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10265 12:24:30.612238 <6>[ 1.128578] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10266 12:24:30.622039 <6>[ 1.137117] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10267 12:24:30.628845 <6>[ 1.145927] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10268 12:24:30.638427 <6>[ 1.154470] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10269 12:24:30.650738 <6>[ 1.170265] loop: module loaded
10270 12:24:30.657149 <6>[ 1.176182] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10271 12:24:30.679430 <4>[ 1.199540] mtk-pmic-keys: Failed to locate of_node [id: -1]
10272 12:24:30.686447 <6>[ 1.206630] megasas: 07.719.03.00-rc1
10273 12:24:30.696371 <6>[ 1.216336] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10274 12:24:30.703597 <6>[ 1.223329] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10275 12:24:30.719834 <6>[ 1.239797] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10276 12:24:30.775540 <6>[ 1.288851] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10277 12:24:30.990051 <6>[ 1.510107] Freeing initrd memory: 17372K
10278 12:24:31.000442 <6>[ 1.520461] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10279 12:24:31.011503 <6>[ 1.531205] tun: Universal TUN/TAP device driver, 1.6
10280 12:24:31.014287 <6>[ 1.537264] thunder_xcv, ver 1.0
10281 12:24:31.017910 <6>[ 1.540766] thunder_bgx, ver 1.0
10282 12:24:31.021481 <6>[ 1.544262] nicpf, ver 1.0
10283 12:24:31.031892 <6>[ 1.548280] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10284 12:24:31.035222 <6>[ 1.555754] hns3: Copyright (c) 2017 Huawei Corporation.
10285 12:24:31.038130 <6>[ 1.561340] hclge is initializing
10286 12:24:31.045098 <6>[ 1.564918] e1000: Intel(R) PRO/1000 Network Driver
10287 12:24:31.051780 <6>[ 1.570048] e1000: Copyright (c) 1999-2006 Intel Corporation.
10288 12:24:31.055009 <6>[ 1.576062] e1000e: Intel(R) PRO/1000 Network Driver
10289 12:24:31.061529 <6>[ 1.581277] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10290 12:24:31.068405 <6>[ 1.587461] igb: Intel(R) Gigabit Ethernet Network Driver
10291 12:24:31.074713 <6>[ 1.593112] igb: Copyright (c) 2007-2014 Intel Corporation.
10292 12:24:31.081399 <6>[ 1.598947] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10293 12:24:31.087900 <6>[ 1.605464] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10294 12:24:31.091189 <6>[ 1.611939] sky2: driver version 1.30
10295 12:24:31.098613 <6>[ 1.616936] VFIO - User Level meta-driver version: 0.3
10296 12:24:31.105177 <6>[ 1.625197] usbcore: registered new interface driver usb-storage
10297 12:24:31.111912 <6>[ 1.631644] usbcore: registered new device driver onboard-usb-hub
10298 12:24:31.120879 <6>[ 1.640743] mt6397-rtc mt6359-rtc: registered as rtc0
10299 12:24:31.130832 <6>[ 1.646209] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:24:31 UTC (1698409471)
10300 12:24:31.134224 <6>[ 1.655774] i2c_dev: i2c /dev entries driver
10301 12:24:31.150976 <6>[ 1.667483] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10302 12:24:31.171404 <6>[ 1.691486] cpu cpu0: EM: created perf domain
10303 12:24:31.174856 <6>[ 1.696415] cpu cpu4: EM: created perf domain
10304 12:24:31.181706 <6>[ 1.701917] sdhci: Secure Digital Host Controller Interface driver
10305 12:24:31.188292 <6>[ 1.708348] sdhci: Copyright(c) Pierre Ossman
10306 12:24:31.195470 <6>[ 1.713267] Synopsys Designware Multimedia Card Interface Driver
10307 12:24:31.202634 <6>[ 1.719880] sdhci-pltfm: SDHCI platform and OF driver helper
10308 12:24:31.205475 <6>[ 1.720013] mmc0: CQHCI version 5.10
10309 12:24:31.211995 <6>[ 1.729751] ledtrig-cpu: registered to indicate activity on CPUs
10310 12:24:31.218712 <6>[ 1.736687] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10311 12:24:31.225251 <6>[ 1.743716] usbcore: registered new interface driver usbhid
10312 12:24:31.228646 <6>[ 1.749539] usbhid: USB HID core driver
10313 12:24:31.234939 <6>[ 1.753721] spi_master spi0: will run message pump with realtime priority
10314 12:24:31.281015 <6>[ 1.794343] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10315 12:24:31.301375 <6>[ 1.811146] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10316 12:24:31.305014 <6>[ 1.824760] mmc0: Command Queue Engine enabled
10317 12:24:31.311867 <6>[ 1.827120] cros-ec-spi spi0.0: Chrome EC device registered
10318 12:24:31.318065 <6>[ 1.829493] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10319 12:24:31.321556 <6>[ 1.842724] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10320 12:24:31.332570 <6>[ 1.849085] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10321 12:24:31.339233 <6>[ 1.852522] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10322 12:24:31.346251 <6>[ 1.859441] NET: Registered PF_PACKET protocol family
10323 12:24:31.349060 <6>[ 1.865735] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10324 12:24:31.355901 <6>[ 1.869704] 9pnet: Installing 9P2000 support
10325 12:24:31.358844 <6>[ 1.875507] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10326 12:24:31.362240 <5>[ 1.879424] Key type dns_resolver registered
10327 12:24:31.368805 <6>[ 1.885258] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10328 12:24:31.375552 <6>[ 1.889635] registered taskstats version 1
10329 12:24:31.379007 <5>[ 1.900033] Loading compiled-in X.509 certificates
10330 12:24:31.407989 <4>[ 1.921006] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10331 12:24:31.418209 <4>[ 1.931725] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10332 12:24:31.424363 <3>[ 1.942271] debugfs: File 'uA_load' in directory '/' already present!
10333 12:24:31.431131 <3>[ 1.948977] debugfs: File 'min_uV' in directory '/' already present!
10334 12:24:31.437863 <3>[ 1.955585] debugfs: File 'max_uV' in directory '/' already present!
10335 12:24:31.444229 <3>[ 1.962238] debugfs: File 'constraint_flags' in directory '/' already present!
10336 12:24:31.455015 <3>[ 1.971773] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10337 12:24:31.463835 <6>[ 1.983811] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10338 12:24:31.470452 <6>[ 1.990535] xhci-mtk 11200000.usb: xHCI Host Controller
10339 12:24:31.477135 <6>[ 1.996019] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10340 12:24:31.487489 <6>[ 2.003846] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10341 12:24:31.493963 <6>[ 2.013257] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10342 12:24:31.500676 <6>[ 2.019314] xhci-mtk 11200000.usb: xHCI Host Controller
10343 12:24:31.507232 <6>[ 2.024789] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10344 12:24:31.513835 <6>[ 2.032438] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10345 12:24:31.520475 <6>[ 2.040132] hub 1-0:1.0: USB hub found
10346 12:24:31.524009 <6>[ 2.044139] hub 1-0:1.0: 1 port detected
10347 12:24:31.530552 <6>[ 2.048393] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10348 12:24:31.537126 <6>[ 2.057136] hub 2-0:1.0: USB hub found
10349 12:24:31.540694 <6>[ 2.061159] hub 2-0:1.0: 1 port detected
10350 12:24:31.547523 <6>[ 2.067541] mtk-msdc 11f70000.mmc: Got CD GPIO
10351 12:24:31.560461 <6>[ 2.077052] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10352 12:24:31.566964 <6>[ 2.085075] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10353 12:24:31.576858 <4>[ 2.093006] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10354 12:24:31.586844 <6>[ 2.102525] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10355 12:24:31.593337 <6>[ 2.110602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10356 12:24:31.600270 <6>[ 2.118646] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10357 12:24:31.609696 <6>[ 2.126565] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10358 12:24:31.616688 <6>[ 2.134383] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10359 12:24:31.626498 <6>[ 2.142199] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10360 12:24:31.636337 <6>[ 2.152539] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10361 12:24:31.643227 <6>[ 2.160919] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10362 12:24:31.653109 <6>[ 2.169258] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10363 12:24:31.659829 <6>[ 2.177601] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10364 12:24:31.669834 <6>[ 2.185946] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10365 12:24:31.676265 <6>[ 2.194285] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10366 12:24:31.686241 <6>[ 2.202623] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10367 12:24:31.692909 <6>[ 2.210961] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10368 12:24:31.703314 <6>[ 2.219300] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10369 12:24:31.709372 <6>[ 2.227638] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10370 12:24:31.719700 <6>[ 2.235976] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10371 12:24:31.729123 <6>[ 2.244315] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10372 12:24:31.735905 <6>[ 2.252653] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10373 12:24:31.746304 <6>[ 2.260995] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10374 12:24:31.752092 <6>[ 2.269332] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10375 12:24:31.758926 <6>[ 2.278099] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10376 12:24:31.765779 <6>[ 2.285240] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10377 12:24:31.772618 <6>[ 2.291981] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10378 12:24:31.779063 <6>[ 2.298710] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10379 12:24:31.789374 <6>[ 2.305612] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10380 12:24:31.795491 <6>[ 2.312465] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10381 12:24:31.805747 <6>[ 2.321619] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10382 12:24:31.815522 <6>[ 2.330743] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10383 12:24:31.825491 <6>[ 2.340037] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10384 12:24:31.835465 <6>[ 2.349505] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10385 12:24:31.841945 <6>[ 2.358971] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10386 12:24:31.851903 <6>[ 2.368090] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10387 12:24:31.861712 <6>[ 2.377556] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10388 12:24:31.871559 <6>[ 2.386677] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10389 12:24:31.881169 <6>[ 2.395978] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10390 12:24:31.891682 <6>[ 2.406138] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10391 12:24:31.901057 <6>[ 2.417723] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10392 12:24:31.908198 <6>[ 2.427397] Trying to probe devices needed for running init ...
10393 12:24:31.931610 <6>[ 2.448503] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10394 12:24:31.961023 <6>[ 2.480881] hub 2-1:1.0: USB hub found
10395 12:24:31.964224 <6>[ 2.485392] hub 2-1:1.0: 3 ports detected
10396 12:24:32.083422 <6>[ 2.600142] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10397 12:24:32.238653 <6>[ 2.758550] hub 1-1:1.0: USB hub found
10398 12:24:32.241839 <6>[ 2.763029] hub 1-1:1.0: 4 ports detected
10399 12:24:32.315713 <6>[ 2.832526] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10400 12:24:32.563584 <6>[ 3.080253] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10401 12:24:32.696105 <6>[ 3.216145] hub 1-1.4:1.0: USB hub found
10402 12:24:32.699548 <6>[ 3.220816] hub 1-1.4:1.0: 2 ports detected
10403 12:24:32.995555 <6>[ 3.512223] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10404 12:24:33.187020 <6>[ 3.704220] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10405 12:24:44.184383 <6>[ 14.709256] ALSA device list:
10406 12:24:44.190923 <6>[ 14.712552] No soundcards found.
10407 12:24:44.199063 <6>[ 14.720286] Freeing unused kernel memory: 8384K
10408 12:24:44.202042 <6>[ 14.725268] Run /init as init process
10409 12:24:44.213306 Loading, please wait...
10410 12:24:44.233722 Starting version 247.3-7+deb11u2
10411 12:24:44.430661 <6>[ 14.948769] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10412 12:24:44.437136 <6>[ 14.956673] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10413 12:24:44.444022 <6>[ 14.957103] mc: Linux media interface: v0.10
10414 12:24:44.450899 <6>[ 14.965401] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10415 12:24:44.460532 <6>[ 14.968620] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10416 12:24:44.463842 <6>[ 14.972593] remoteproc remoteproc0: scp is available
10417 12:24:44.474376 <4>[ 14.992100] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10418 12:24:44.477509 <6>[ 14.993829] remoteproc remoteproc0: powering up scp
10419 12:24:44.487170 <3>[ 14.993861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10420 12:24:44.493689 <3>[ 14.993872] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10421 12:24:44.503631 <3>[ 14.993875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10422 12:24:44.510461 <3>[ 14.993948] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10423 12:24:44.516596 <3>[ 14.993952] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10424 12:24:44.527035 <3>[ 14.993954] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10425 12:24:44.533403 <3>[ 14.993957] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10426 12:24:44.543309 <3>[ 14.993960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10427 12:24:44.549989 <3>[ 14.993975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10428 12:24:44.560028 <3>[ 14.993998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10429 12:24:44.566615 <3>[ 14.994002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10430 12:24:44.576334 <3>[ 14.994005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10431 12:24:44.582933 <3>[ 14.994024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10432 12:24:44.589619 <3>[ 14.994026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10433 12:24:44.600049 <3>[ 14.994028] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10434 12:24:44.606080 <3>[ 14.994030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10435 12:24:44.616015 <3>[ 14.994032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10436 12:24:44.622463 <3>[ 14.994041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10437 12:24:44.629450 <4>[ 14.999618] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10438 12:24:44.636030 <6>[ 15.002195] videodev: Linux video capture interface: v2.00
10439 12:24:44.642463 <6>[ 15.003730] usbcore: registered new interface driver r8152
10440 12:24:44.652602 <6>[ 15.004882] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10441 12:24:44.659004 <6>[ 15.080336] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10442 12:24:44.662231 <6>[ 15.085466] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10443 12:24:44.672307 <6>[ 15.109298] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10444 12:24:44.682010 <6>[ 15.109316] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10445 12:24:44.685612 <6>[ 15.109321] pci_bus 0000:00: root bus resource [bus 00-ff]
10446 12:24:44.692625 <6>[ 15.109326] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10447 12:24:44.702783 <6>[ 15.109328] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10448 12:24:44.709727 <6>[ 15.109354] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10449 12:24:44.716493 <6>[ 15.109367] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10450 12:24:44.722876 <6>[ 15.109433] pci 0000:00:00.0: supports D1 D2
10451 12:24:44.729403 <6>[ 15.109435] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10452 12:24:44.736889 <6>[ 15.110508] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10453 12:24:44.742626 <6>[ 15.112159] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10454 12:24:44.752672 <4>[ 15.116614] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10455 12:24:44.762718 <4>[ 15.116624] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10456 12:24:44.769680 <6>[ 15.118591] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10457 12:24:44.779199 <6>[ 15.123114] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10458 12:24:44.785887 <6>[ 15.126132] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10459 12:24:44.795794 <4>[ 15.152844] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10460 12:24:44.798843 <4>[ 15.152844] Fallback method does not support PEC.
10461 12:24:44.802137 <6>[ 15.155282] Bluetooth: Core ver 2.22
10462 12:24:44.808898 <6>[ 15.155361] NET: Registered PF_BLUETOOTH protocol family
10463 12:24:44.815654 <6>[ 15.155363] Bluetooth: HCI device and connection manager initialized
10464 12:24:44.821749 <6>[ 15.155379] Bluetooth: HCI socket layer initialized
10465 12:24:44.825553 <6>[ 15.155385] Bluetooth: L2CAP socket layer initialized
10466 12:24:44.832009 <6>[ 15.155426] Bluetooth: SCO socket layer initialized
10467 12:24:44.838605 <6>[ 15.157859] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10468 12:24:44.845067 <6>[ 15.163509] usbcore: registered new interface driver cdc_ether
10469 12:24:44.848252 <6>[ 15.168029] r8152 2-1.3:1.0 eth0: v1.12.13
10470 12:24:44.854967 <6>[ 15.169124] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10471 12:24:44.865110 <6>[ 15.185624] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10472 12:24:44.871298 <6>[ 15.190189] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10473 12:24:44.878209 <6>[ 15.190542] usbcore: registered new interface driver r8153_ecm
10474 12:24:44.884748 <6>[ 15.200036] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10475 12:24:44.894632 <6>[ 15.201717] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10476 12:24:44.901137 <6>[ 15.207230] pci 0000:01:00.0: supports D1 D2
10477 12:24:44.904573 <6>[ 15.207852] usbcore: registered new interface driver btusb
10478 12:24:44.917617 <4>[ 15.208569] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10479 12:24:44.920661 <3>[ 15.208585] Bluetooth: hci0: Failed to load firmware file (-2)
10480 12:24:44.927700 <3>[ 15.208587] Bluetooth: hci0: Failed to set up firmware (-2)
10481 12:24:44.937543 <4>[ 15.208590] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10482 12:24:44.944094 <6>[ 15.213003] usbcore: registered new interface driver uvcvideo
10483 12:24:44.953976 <3>[ 15.213152] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10484 12:24:44.960598 <6>[ 15.219984] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10485 12:24:44.966913 <6>[ 15.220526] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10486 12:24:44.977130 <3>[ 15.233985] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10487 12:24:44.983840 <6>[ 15.237559] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10488 12:24:44.990258 <6>[ 15.237574] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10489 12:24:45.000313 <6>[ 15.244804] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10490 12:24:45.006806 <6>[ 15.248104] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10491 12:24:45.013243 <6>[ 15.248130] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10492 12:24:45.023042 <6>[ 15.248133] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10493 12:24:45.029852 <6>[ 15.248140] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10494 12:24:45.036552 <6>[ 15.248151] remoteproc remoteproc0: remote processor scp is now up
10495 12:24:45.042928 <6>[ 15.248153] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10496 12:24:45.052808 <6>[ 15.248166] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10497 12:24:45.059731 <6>[ 15.256307] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10498 12:24:45.066191 <6>[ 15.263284] pci 0000:00:00.0: PCI bridge to [bus 01]
10499 12:24:45.072459 <6>[ 15.592706] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10500 12:24:45.079585 <6>[ 15.600846] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10501 12:24:45.086070 <6>[ 15.607675] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10502 12:24:45.092888 <6>[ 15.614425] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10503 12:24:45.111490 <5>[ 15.629908] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10504 12:24:45.133250 <5>[ 15.651267] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10505 12:24:45.139864 <4>[ 15.658270] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10506 12:24:45.146108 <6>[ 15.667209] cfg80211: failed to load regulatory.db
10507 12:24:45.193053 <6>[ 15.711527] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10508 12:24:45.200013 <6>[ 15.719308] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10509 12:24:45.224308 <6>[ 15.746035] mt7921e 0000:01:00.0: ASIC revision: 79610010
10510 12:24:45.328866 <4>[ 15.844150] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10511 12:24:45.336852 Begin: Loading essential drivers ... done.
10512 12:24:45.340140 Begin: Running /scripts/init-premount ... done.
10513 12:24:45.346820 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10514 12:24:45.356915 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10515 12:24:45.360320 Device /sys/class/net/enx00e04c6803bd found
10516 12:24:45.360785 done.
10517 12:24:45.397867 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10518 12:24:45.448619 <4>[ 15.963759] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10519 12:24:45.568551 <4>[ 16.083780] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10520 12:24:45.688557 <4>[ 16.203627] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10521 12:24:45.808726 <4>[ 16.323685] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10522 12:24:45.928260 <4>[ 16.443532] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10523 12:24:46.048867 <4>[ 16.563784] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10524 12:24:46.168535 <4>[ 16.683592] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10525 12:24:46.226802 <6>[ 16.748675] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10526 12:24:46.288481 <4>[ 16.803476] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10527 12:24:46.407967 <4>[ 16.923302] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10528 12:24:46.519891 <3>[ 17.041596] mt7921e 0000:01:00.0: hardware init failed
10529 12:24:46.624303 IP-Config: no response after 2 secs - giving up
10530 12:24:46.661851 IP-Config: enx00e04c6803bd hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10531 12:24:46.664911 IP-Config: enx00e04c6803bd complete (dhcp from 192.168.201.1):
10532 12:24:46.672149 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10533 12:24:46.678487 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10534 12:24:46.684793 host : mt8192-asurada-spherion-r0-cbg-4
10535 12:24:46.691563 domain : lava-rack
10536 12:24:46.697901 rootserver: 192.168.201.1 rootpath:
10537 12:24:46.698368 filename :
10538 12:24:46.771832 done.
10539 12:24:46.779288 Begin: Running /scripts/nfs-bottom ... done.
10540 12:24:46.798616 Begin: Running /scripts/init-bottom ... done.
10541 12:24:48.007879 <6>[ 18.530101] NET: Registered PF_INET6 protocol family
10542 12:24:48.015231 <6>[ 18.537150] Segment Routing with IPv6
10543 12:24:48.018450 <6>[ 18.541169] In-situ OAM (IOAM) with IPv6
10544 12:24:48.142981 <30>[ 18.645044] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10545 12:24:48.145926 <30>[ 18.669460] systemd[1]: Detected architecture arm64.
10546 12:24:48.168822
10547 12:24:48.171842 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10548 12:24:48.172342
10549 12:24:48.189023 <30>[ 18.711080] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10550 12:24:49.045341 <30>[ 19.564049] systemd[1]: Queued start job for default target Graphical Interface.
10551 12:24:49.076420 <30>[ 19.598524] systemd[1]: Created slice system-getty.slice.
10552 12:24:49.083007 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10553 12:24:49.099294 <30>[ 19.621593] systemd[1]: Created slice system-modprobe.slice.
10554 12:24:49.106082 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10555 12:24:49.123383 <30>[ 19.645505] systemd[1]: Created slice system-serial\x2dgetty.slice.
10556 12:24:49.133417 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10557 12:24:49.147594 <30>[ 19.669279] systemd[1]: Created slice User and Session Slice.
10558 12:24:49.153591 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10559 12:24:49.174324 <30>[ 19.692950] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10560 12:24:49.183722 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10561 12:24:49.201599 <30>[ 19.720429] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10562 12:24:49.207990 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10563 12:24:49.228863 <30>[ 19.744340] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10564 12:24:49.235504 <30>[ 19.756505] systemd[1]: Reached target Local Encrypted Volumes.
10565 12:24:49.242114 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10566 12:24:49.258845 <30>[ 19.780788] systemd[1]: Reached target Paths.
10567 12:24:49.262121 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10568 12:24:49.278199 <30>[ 19.800213] systemd[1]: Reached target Remote File Systems.
10569 12:24:49.284650 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10570 12:24:49.302227 <30>[ 19.824570] systemd[1]: Reached target Slices.
10571 12:24:49.308784 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10572 12:24:49.322528 <30>[ 19.844245] systemd[1]: Reached target Swap.
10573 12:24:49.325449 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10574 12:24:49.345927 <30>[ 19.864708] systemd[1]: Listening on initctl Compatibility Named Pipe.
10575 12:24:49.352422 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10576 12:24:49.358910 <30>[ 19.880926] systemd[1]: Listening on Journal Audit Socket.
10577 12:24:49.365856 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10578 12:24:49.383633 <30>[ 19.905628] systemd[1]: Listening on Journal Socket (/dev/log).
10579 12:24:49.390150 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10580 12:24:49.406643 <30>[ 19.928806] systemd[1]: Listening on Journal Socket.
10581 12:24:49.412951 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10582 12:24:49.430605 <30>[ 19.949718] systemd[1]: Listening on Network Service Netlink Socket.
10583 12:24:49.437546 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10584 12:24:49.452781 <30>[ 19.974864] systemd[1]: Listening on udev Control Socket.
10585 12:24:49.459031 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10586 12:24:49.474693 <30>[ 19.996683] systemd[1]: Listening on udev Kernel Socket.
10587 12:24:49.481047 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10588 12:24:49.530440 <30>[ 20.052560] systemd[1]: Mounting Huge Pages File System...
10589 12:24:49.536760 Mounting [0;1;39mHuge Pages File System[0m...
10590 12:24:49.554808 <30>[ 20.077150] systemd[1]: Mounting POSIX Message Queue File System...
10591 12:24:49.561818 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10592 12:24:49.582468 <30>[ 20.104772] systemd[1]: Mounting Kernel Debug File System...
10593 12:24:49.589057 Mounting [0;1;39mKernel Debug File System[0m...
10594 12:24:49.605511 <30>[ 20.124709] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10595 12:24:49.657682 <30>[ 20.176743] systemd[1]: Starting Create list of static device nodes for the current kernel...
10596 12:24:49.667674 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10597 12:24:49.686935 <30>[ 20.209184] systemd[1]: Starting Load Kernel Module configfs...
10598 12:24:49.693593 Starting [0;1;39mLoad Kernel Module configfs[0m...
10599 12:24:49.709234 <30>[ 20.231625] systemd[1]: Starting Load Kernel Module drm...
10600 12:24:49.715810 Starting [0;1;39mLoad Kernel Module drm[0m...
10601 12:24:49.735051 <30>[ 20.257390] systemd[1]: Starting Load Kernel Module fuse...
10602 12:24:49.741724 Starting [0;1;39mLoad Kernel Module fuse[0m...
10603 12:24:49.778295 <30>[ 20.296909] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10604 12:24:49.785026 <6>[ 20.307450] fuse: init (API version 7.37)
10605 12:24:49.818629 <30>[ 20.340743] systemd[1]: Starting Journal Service...
10606 12:24:49.821808 Starting [0;1;39mJournal Service[0m...
10607 12:24:49.845716 <30>[ 20.368214] systemd[1]: Starting Load Kernel Modules...
10608 12:24:49.852371 Starting [0;1;39mLoad Kernel Modules[0m...
10609 12:24:49.874082 <30>[ 20.393206] systemd[1]: Starting Remount Root and Kernel File Systems...
10610 12:24:49.881022 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10611 12:24:49.899785 <30>[ 20.422029] systemd[1]: Starting Coldplug All udev Devices...
10612 12:24:49.905988 Starting [0;1;39mColdplug All udev Devices[0m...
10613 12:24:49.929014 <30>[ 20.451464] systemd[1]: Mounted Huge Pages File System.
10614 12:24:49.936256 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10615 12:24:49.942724 <3>[ 20.463037] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10616 12:24:49.950471 <30>[ 20.472786] systemd[1]: Mounted POSIX Message Queue File System.
10617 12:24:49.957129 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10618 12:24:49.976085 <3>[ 20.494959] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10619 12:24:49.982604 <30>[ 20.504282] systemd[1]: Mounted Kernel Debug File System.
10620 12:24:49.989059 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10621 12:24:50.007648 <30>[ 20.526143] systemd[1]: Finished Create list of static device nodes for the current kernel.
10622 12:24:50.021140 [[0;32m OK [0m] Finished [0;1;39mCreate lis<3>[ 20.538464] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10623 12:24:50.024413 t of st… nodes for the current kernel[0m.
10624 12:24:50.043328 <30>[ 20.565247] systemd[1]: modprobe@configfs.service: Succeeded.
10625 12:24:50.053295 <3>[ 20.568859] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10626 12:24:50.059974 <30>[ 20.572166] systemd[1]: Finished Load Kernel Module configfs.
10627 12:24:50.066464 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10628 12:24:50.082273 <3>[ 20.601067] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10629 12:24:50.088637 <30>[ 20.601554] systemd[1]: modprobe@drm.service: Succeeded.
10630 12:24:50.095748 <30>[ 20.616853] systemd[1]: Finished Load Kernel Module drm.
10631 12:24:50.102176 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10632 12:24:50.113449 <3>[ 20.632379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10633 12:24:50.123468 <30>[ 20.645842] systemd[1]: modprobe@fuse.service: Succeeded.
10634 12:24:50.131109 <30>[ 20.652847] systemd[1]: Finished Load Kernel Module fuse.
10635 12:24:50.144644 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 20.662602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10636 12:24:50.147796 l Module fuse[0m.
10637 12:24:50.164611 <30>[ 20.686468] systemd[1]: Finished Load Kernel Modules.
10638 12:24:50.178347 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 20.696197] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10639 12:24:50.179037 l Modules[0m.
10640 12:24:50.196330 <30>[ 20.718143] systemd[1]: Finished Remount Root and Kernel File Systems.
10641 12:24:50.210060 [[0;32m OK [0m] Finished [0;1;39mRemount Ro<3>[ 20.728689] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10642 12:24:50.213023 ot and Kernel File Systems[0m.
10643 12:24:50.244497 <3>[ 20.763715] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10644 12:24:50.252926 <30>[ 20.775224] systemd[1]: Mounting FUSE Control File System...
10645 12:24:50.259209 Mounting [0;1;39mFUSE Control File System[0m...
10646 12:24:50.282676 <30>[ 20.801670] systemd[1]: Mounting Kernel Configuration File System...
10647 12:24:50.285940 Mounting [0;1;39mKernel Configuration File System[0m...
10648 12:24:50.312095 <30>[ 20.830779] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10649 12:24:50.321467 <30>[ 20.840056] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10650 12:24:50.332584 <30>[ 20.854668] systemd[1]: Starting Load/Save Random Seed...
10651 12:24:50.339234 Starting [0;1;39mLoad/Save Random Seed[0m...
10652 12:24:50.359139 <30>[ 20.881688] systemd[1]: Starting Apply Kernel Variables...
10653 12:24:50.366130 Starting [0;1;39mApply Kernel Variables[0m...
10654 12:24:50.384699 <4>[ 20.897012] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10655 12:24:50.391479 <3>[ 20.912694] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10656 12:24:50.397883 <30>[ 20.918333] systemd[1]: Starting Create System Users...
10657 12:24:50.404457 Starting [0;1;39mCreate System Users[0m...
10658 12:24:50.421291 <30>[ 20.943283] systemd[1]: Started Journal Service.
10659 12:24:50.427813 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10660 12:24:50.455109 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10661 12:24:50.473619 See 'systemctl status systemd-udev-trigger.service' for details.
10662 12:24:50.490706 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10663 12:24:50.510970 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10664 12:24:50.527863 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10665 12:24:50.543991 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10666 12:24:50.564550 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10667 12:24:50.614613 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10668 12:24:50.632331 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10669 12:24:50.663252 <46>[ 21.182924] systemd-journald[288]: Received client request to flush runtime journal.
10670 12:24:51.423689 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10671 12:24:51.438770 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10672 12:24:51.454126 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10673 12:24:51.525179 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10674 12:24:52.068208 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10675 12:24:52.121873 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10676 12:24:52.143894 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10677 12:24:52.163840 Starting [0;1;39mNetwork Service[0m...
10678 12:24:52.487852 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10679 12:24:52.510352 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10680 12:24:52.559366 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10681 12:24:52.749362 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10682 12:24:52.773025 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10683 12:24:52.818209 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10684 12:24:52.871822 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10685 12:24:52.886337 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10686 12:24:52.906147 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10687 12:24:52.947152 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10688 12:24:52.998161 Starting [0;1;39mNetwork Name Resolution[0m...
10689 12:24:53.025887 Starting [0;1;39mNetwork Time Synchronization[0m...
10690 12:24:53.047373 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10691 12:24:53.106524 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10692 12:24:53.211428 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10693 12:24:53.226264 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10694 12:24:53.245331 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10695 12:24:53.257454 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10696 12:24:53.273655 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10697 12:24:53.409411 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10698 12:24:53.445924 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10699 12:24:53.487373 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10700 12:24:53.509372 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10701 12:24:53.525700 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10702 12:24:53.546666 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10703 12:24:53.557522 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10704 12:24:53.573413 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10705 12:24:53.635274 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10706 12:24:53.671496 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10707 12:24:53.752660 Starting [0;1;39mUser Login Management[0m...
10708 12:24:53.770742 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10709 12:24:53.786183 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10710 12:24:53.805243 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10711 12:24:53.849368 Starting [0;1;39mPermit User Sessions[0m...
10712 12:24:53.956619 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10713 12:24:53.969027 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10714 12:24:54.014428 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10715 12:24:54.032857 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10716 12:24:54.051317 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10717 12:24:54.068833 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10718 12:24:54.086016 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10719 12:24:54.101722 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10720 12:24:54.160253 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10721 12:24:54.210460 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10722 12:24:54.278951
10723 12:24:54.279102
10724 12:24:54.281842 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10725 12:24:54.281922
10726 12:24:54.285364 debian-bullseye-arm64 login: root (automatic login)
10727 12:24:54.285445
10728 12:24:54.285507
10729 12:24:54.628643 Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64
10730 12:24:54.629183
10731 12:24:54.635254 The programs included with the Debian GNU/Linux system are free software;
10732 12:24:54.642064 the exact distribution terms for each program are described in the
10733 12:24:54.645754 individual files in /usr/share/doc/*/copyright.
10734 12:24:54.646250
10735 12:24:54.651669 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10736 12:24:54.654896 permitted by applicable law.
10737 12:24:55.552493 Matched prompt #10: / #
10739 12:24:55.553684 Setting prompt string to ['/ #']
10740 12:24:55.554119 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10742 12:24:55.555092 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10743 12:24:55.555530 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10744 12:24:55.555880 Setting prompt string to ['/ #']
10745 12:24:55.556224 Forcing a shell prompt, looking for ['/ #']
10747 12:24:55.607122 / #
10748 12:24:55.607762 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10749 12:24:55.608245 Waiting using forced prompt support (timeout 00:02:30)
10750 12:24:55.613369
10751 12:24:55.614293 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10752 12:24:55.614808 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10754 12:24:55.716019 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893158/extract-nfsrootfs-9jokrc83'
10755 12:24:55.722602 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893158/extract-nfsrootfs-9jokrc83'
10757 12:24:55.824270 / # export NFS_SERVER_IP='192.168.201.1'
10758 12:24:55.829507 export NFS_SERVER_IP='192.168.201.1'
10759 12:24:55.829926 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10760 12:24:55.830097 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10761 12:24:55.830245 end: 2 depthcharge-action (duration 00:01:35) [common]
10762 12:24:55.830385 start: 3 lava-test-retry (timeout 00:07:46) [common]
10763 12:24:55.830510 start: 3.1 lava-test-shell (timeout 00:07:46) [common]
10764 12:24:55.830616 Using namespace: common
10766 12:24:55.931332 / # #
10767 12:24:55.932009 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10768 12:24:55.937594 #
10769 12:24:55.938437 Using /lava-11893158
10771 12:24:56.039907 / # export SHELL=/bin/bash
10772 12:24:56.046262 export SHELL=/bin/bash
10774 12:24:56.147940 / # . /lava-11893158/environment
10775 12:24:56.154341 . /lava-11893158/environment
10777 12:24:56.262124 / # /lava-11893158/bin/lava-test-runner /lava-11893158/0
10778 12:24:56.262789 Test shell timeout: 10s (minimum of the action and connection timeout)
10779 12:24:56.268965 /lava-11893158/bin/lava-test-runner /lava-11893158/0
10780 12:24:56.547076 + export TESTRUN_ID=0_timesync-off
10781 12:24:56.549975 + TESTRUN_ID=0_timesync-off
10782 12:24:56.553150 + cd /lava-11893158/0/tests/0_timesync-off
10783 12:24:56.556552 ++ cat uuid
10784 12:24:56.559837 + UUID=11893158_1.6.2.3.1
10785 12:24:56.559917 + set +x
10786 12:24:56.563253 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11893158_1.6.2.3.1>
10787 12:24:56.563516 Received signal: <STARTRUN> 0_timesync-off 11893158_1.6.2.3.1
10788 12:24:56.563591 Starting test lava.0_timesync-off (11893158_1.6.2.3.1)
10789 12:24:56.563686 Skipping test definition patterns.
10790 12:24:56.566705 + systemctl stop systemd-timesyncd
10791 12:24:56.623403 + set +x
10792 12:24:56.626296 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11893158_1.6.2.3.1>
10793 12:24:56.626601 Received signal: <ENDRUN> 0_timesync-off 11893158_1.6.2.3.1
10794 12:24:56.626702 Ending use of test pattern.
10795 12:24:56.626774 Ending test lava.0_timesync-off (11893158_1.6.2.3.1), duration 0.06
10797 12:24:56.694998 + export TESTRUN_ID=1_kselftest-arm64
10798 12:24:56.695120 + TESTRUN_ID=1_kselftest-arm64
10799 12:24:56.701559 + cd /lava-11893158/0/tests/1_kselftest-arm64
10800 12:24:56.701659 ++ cat uuid
10801 12:24:56.704861 + UUID=11893158_1.6.2.3.5
10802 12:24:56.704969 + set +x
10803 12:24:56.708004 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 11893158_1.6.2.3.5>
10804 12:24:56.708304 Received signal: <STARTRUN> 1_kselftest-arm64 11893158_1.6.2.3.5
10805 12:24:56.708407 Starting test lava.1_kselftest-arm64 (11893158_1.6.2.3.5)
10806 12:24:56.708521 Skipping test definition patterns.
10807 12:24:56.711701 + cd ./automated/linux/kselftest/
10808 12:24:56.741468 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10809 12:24:56.775911 INFO: install_deps skipped
10810 12:24:56.891124 --2023-10-27 12:24:57-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10811 12:24:57.904788 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10812 12:24:58.038251 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10813 12:24:58.171465 HTTP request sent, awaiting response... 200 OK
10814 12:24:58.174940 Length: 2956332 (2.8M) [application/octet-stream]
10815 12:24:58.178310 Saving to: 'kselftest.tar.xz'
10816 12:24:58.178862
10817 12:24:58.179225
10818 12:24:58.440308 kselftest.tar.xz 0%[ ] 0 --.-KB/s
10819 12:24:58.708368 kselftest.tar.xz 1%[ ] 47.81K 184KB/s
10820 12:24:59.023060 kselftest.tar.xz 7%[> ] 214.67K 412KB/s
10821 12:24:59.243826 kselftest.tar.xz 27%[====> ] 790.19K 956KB/s
10822 12:24:59.511023 kselftest.tar.xz 63%[===========> ] 1.80M 1.73MB/s
10823 12:24:59.521607 kselftest.tar.xz 96%[==================> ] 2.72M 2.09MB/s
10824 12:24:59.527701 kselftest.tar.xz 100%[===================>] 2.82M 2.15MB/s in 1.3s
10825 12:24:59.528159
10826 12:24:59.784340 2023-10-27 12:24:59 (2.15 MB/s) - 'kselftest.tar.xz' saved [2956332/2956332]
10827 12:24:59.784977
10828 12:25:05.398551 skiplist:
10829 12:25:05.401573 ========================================
10830 12:25:05.404893 ========================================
10831 12:25:05.450369 arm64:tags_test
10832 12:25:05.453811 arm64:run_tags_test.sh
10833 12:25:05.454223 arm64:fake_sigreturn_bad_magic
10834 12:25:05.457259 arm64:fake_sigreturn_bad_size
10835 12:25:05.460111 arm64:fake_sigreturn_bad_size_for_magic0
10836 12:25:05.463552 arm64:fake_sigreturn_duplicated_fpsimd
10837 12:25:05.466794 arm64:fake_sigreturn_misaligned_sp
10838 12:25:05.470094 arm64:fake_sigreturn_missing_fpsimd
10839 12:25:05.473340 arm64:fake_sigreturn_sme_change_vl
10840 12:25:05.476730 arm64:fake_sigreturn_sve_change_vl
10841 12:25:05.479962 arm64:mangle_pstate_invalid_compat_toggle
10842 12:25:05.483323 arm64:mangle_pstate_invalid_daif_bits
10843 12:25:05.486503 arm64:mangle_pstate_invalid_mode_el1h
10844 12:25:05.489950 arm64:mangle_pstate_invalid_mode_el1t
10845 12:25:05.493411 arm64:mangle_pstate_invalid_mode_el2h
10846 12:25:05.496645 arm64:mangle_pstate_invalid_mode_el2t
10847 12:25:05.499865 arm64:mangle_pstate_invalid_mode_el3h
10848 12:25:05.506465 arm64:mangle_pstate_invalid_mode_el3t
10849 12:25:05.506874 arm64:sme_trap_no_sm
10850 12:25:05.509649 arm64:sme_trap_non_streaming
10851 12:25:05.510096 arm64:sme_trap_za
10852 12:25:05.513000 arm64:sme_vl
10853 12:25:05.513412 arm64:ssve_regs
10854 12:25:05.516321 arm64:sve_regs
10855 12:25:05.516734 arm64:sve_vl
10856 12:25:05.517103 arm64:za_no_regs
10857 12:25:05.519627 arm64:za_regs
10858 12:25:05.520055 arm64:pac
10859 12:25:05.522812 arm64:fp-stress
10860 12:25:05.523223 arm64:sve-ptrace
10861 12:25:05.526182 arm64:sve-probe-vls
10862 12:25:05.526597 arm64:vec-syscfg
10863 12:25:05.526957 arm64:za-fork
10864 12:25:05.529686 arm64:za-ptrace
10865 12:25:05.532829 arm64:check_buffer_fill
10866 12:25:05.533276 arm64:check_child_memory
10867 12:25:05.536026 arm64:check_gcr_el1_cswitch
10868 12:25:05.539579 arm64:check_ksm_options
10869 12:25:05.540022 arm64:check_mmap_options
10870 12:25:05.542919 arm64:check_prctl
10871 12:25:05.546014 arm64:check_tags_inclusion
10872 12:25:05.546471 arm64:check_user_mem
10873 12:25:05.549286 arm64:btitest
10874 12:25:05.549696 arm64:nobtitest
10875 12:25:05.550022 arm64:hwcap
10876 12:25:05.552525 arm64:ptrace
10877 12:25:05.552982 arm64:syscall-abi
10878 12:25:05.555854 arm64:tpidr2
10879 12:25:05.559230 ============== Tests to run ===============
10880 12:25:05.559821 arm64:tags_test
10881 12:25:05.562531 arm64:run_tags_test.sh
10882 12:25:05.566306 arm64:fake_sigreturn_bad_magic
10883 12:25:05.569157 arm64:fake_sigreturn_bad_size
10884 12:25:05.572698 arm64:fake_sigreturn_bad_size_for_magic0
10885 12:25:05.575678 arm64:fake_sigreturn_duplicated_fpsimd
10886 12:25:05.578977 arm64:fake_sigreturn_misaligned_sp
10887 12:25:05.582316 arm64:fake_sigreturn_missing_fpsimd
10888 12:25:05.585615 arm64:fake_sigreturn_sme_change_vl
10889 12:25:05.586049 arm64:fake_sigreturn_sve_change_vl
10890 12:25:05.592366 arm64:mangle_pstate_invalid_compat_toggle
10891 12:25:05.595495 arm64:mangle_pstate_invalid_daif_bits
10892 12:25:05.598879 arm64:mangle_pstate_invalid_mode_el1h
10893 12:25:05.602167 arm64:mangle_pstate_invalid_mode_el1t
10894 12:25:05.605510 arm64:mangle_pstate_invalid_mode_el2h
10895 12:25:05.608703 arm64:mangle_pstate_invalid_mode_el2t
10896 12:25:05.611951 arm64:mangle_pstate_invalid_mode_el3h
10897 12:25:05.615156 arm64:mangle_pstate_invalid_mode_el3t
10898 12:25:05.615567 arm64:sme_trap_no_sm
10899 12:25:05.618595 arm64:sme_trap_non_streaming
10900 12:25:05.622063 arm64:sme_trap_za
10901 12:25:05.622524 arm64:sme_vl
10902 12:25:05.622919 arm64:ssve_regs
10903 12:25:05.625305 arm64:sve_regs
10904 12:25:05.625816 arm64:sve_vl
10905 12:25:05.628700 arm64:za_no_regs
10906 12:25:05.629119 arm64:za_regs
10907 12:25:05.629487 arm64:pac
10908 12:25:05.631742 arm64:fp-stress
10909 12:25:05.632235 arm64:sve-ptrace
10910 12:25:05.635063 arm64:sve-probe-vls
10911 12:25:05.635477 arm64:vec-syscfg
10912 12:25:05.638538 arm64:za-fork
10913 12:25:05.638989 arm64:za-ptrace
10914 12:25:05.641648 arm64:check_buffer_fill
10915 12:25:05.644870 arm64:check_child_memory
10916 12:25:05.645301 arm64:check_gcr_el1_cswitch
10917 12:25:05.648644 arm64:check_ksm_options
10918 12:25:05.651459 arm64:check_mmap_options
10919 12:25:05.651883 arm64:check_prctl
10920 12:25:05.654816 arm64:check_tags_inclusion
10921 12:25:05.655227 arm64:check_user_mem
10922 12:25:05.658100 arm64:btitest
10923 12:25:05.658532 arm64:nobtitest
10924 12:25:05.661480 arm64:hwcap
10925 12:25:05.661890 arm64:ptrace
10926 12:25:05.664867 arm64:syscall-abi
10927 12:25:05.665334 arm64:tpidr2
10928 12:25:05.668060 ===========End Tests to run ===============
10929 12:25:05.671194 shardfile-arm64 pass
10930 12:25:05.908464 <12>[ 36.432672] kselftest: Running tests in arm64
10931 12:25:05.919135 TAP version 13
10932 12:25:05.931901 1..48
10933 12:25:05.950641 # selftests: arm64: tags_test
10934 12:25:06.395193 ok 1 selftests: arm64: tags_test
10935 12:25:06.410803 # selftests: arm64: run_tags_test.sh
10936 12:25:06.484316 # --------------------
10937 12:25:06.487355 # running tags test
10938 12:25:06.487735 # --------------------
10939 12:25:06.490736 # [PASS]
10940 12:25:06.494556 ok 2 selftests: arm64: run_tags_test.sh
10941 12:25:06.507503 # selftests: arm64: fake_sigreturn_bad_magic
10942 12:25:06.568448 # Registered handlers for all signals.
10943 12:25:06.568819 # Detected MINSTKSIGSZ:4720
10944 12:25:06.571546 # Testcase initialized.
10945 12:25:06.575072 # uc context validated.
10946 12:25:06.578359 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10947 12:25:06.581820 # Handled SIG_COPYCTX
10948 12:25:06.582272 # Available space:3568
10949 12:25:06.588488 # Using badly built context - ERR: BAD MAGIC !
10950 12:25:06.594901 # SIG_OK -- SP:0xFFFFFF4CD1D0 si_addr@:0xffffff4cd1d0 si_code:2 token@:0xffffff4cbf70 offset:-4704
10951 12:25:06.598280 # ==>> completed. PASS(1)
10952 12:25:06.604690 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
10953 12:25:06.611398 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFF4CBF70
10954 12:25:06.617949 ok 3 selftests: arm64: fake_sigreturn_bad_magic
10955 12:25:06.621481 # selftests: arm64: fake_sigreturn_bad_size
10956 12:25:06.652042 # Registered handlers for all signals.
10957 12:25:06.652619 # Detected MINSTKSIGSZ:4720
10958 12:25:06.655101 # Testcase initialized.
10959 12:25:06.658709 # uc context validated.
10960 12:25:06.661772 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10961 12:25:06.665116 # Handled SIG_COPYCTX
10962 12:25:06.665600 # Available space:3568
10963 12:25:06.668372 # uc context validated.
10964 12:25:06.674972 # Using badly built context - ERR: Bad size for esr_context
10965 12:25:06.681370 # SIG_OK -- SP:0xFFFFFA5B43A0 si_addr@:0xfffffa5b43a0 si_code:2 token@:0xfffffa5b3140 offset:-4704
10966 12:25:06.685009 # ==>> completed. PASS(1)
10967 12:25:06.691467 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
10968 12:25:06.698168 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFA5B3140
10969 12:25:06.701410 ok 4 selftests: arm64: fake_sigreturn_bad_size
10970 12:25:06.708117 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
10971 12:25:06.729818 # Registered handlers for all signals.
10972 12:25:06.730378 # Detected MINSTKSIGSZ:4720
10973 12:25:06.732722 # Testcase initialized.
10974 12:25:06.736413 # uc context validated.
10975 12:25:06.739242 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10976 12:25:06.742511 # Handled SIG_COPYCTX
10977 12:25:06.743000 # Available space:3568
10978 12:25:06.749341 # Using badly built context - ERR: Bad size for terminator
10979 12:25:06.759619 # SIG_OK -- SP:0xFFFFF363AC40 si_addr@:0xfffff363ac40 si_code:2 token@:0xfffff36399e0 offset:-4704
10980 12:25:06.760170 # ==>> completed. PASS(1)
10981 12:25:06.769293 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
10982 12:25:06.775734 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF36399E0
10983 12:25:06.779504 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
10984 12:25:06.785538 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
10985 12:25:06.813983 # Registered handlers for all signals.
10986 12:25:06.814584 # Detected MINSTKSIGSZ:4720
10987 12:25:06.817272 # Testcase initialized.
10988 12:25:06.820590 # uc context validated.
10989 12:25:06.823802 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
10990 12:25:06.827246 # Handled SIG_COPYCTX
10991 12:25:06.827727 # Available space:3568
10992 12:25:06.833811 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
10993 12:25:06.843663 # SIG_OK -- SP:0xFFFFEAE46F20 si_addr@:0xffffeae46f20 si_code:2 token@:0xffffeae45cc0 offset:-4704
10994 12:25:06.844327 # ==>> completed. PASS(1)
10995 12:25:06.853555 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
10996 12:25:06.860268 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEAE45CC0
10997 12:25:06.863459 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
10998 12:25:06.866758 # selftests: arm64: fake_sigreturn_misaligned_sp
10999 12:25:06.892879 # Registered handlers for all signals.
11000 12:25:06.893436 # Detected MINSTKSIGSZ:4720
11001 12:25:06.895950 # Testcase initialized.
11002 12:25:06.899225 # uc context validated.
11003 12:25:06.902342 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11004 12:25:06.906326 # Handled SIG_COPYCTX
11005 12:25:06.912346 # SIG_OK -- SP:0xFFFFCF230093 si_addr@:0xffffcf230093 si_code:2 token@:0xffffcf230093 offset:0
11006 12:25:06.915825 # ==>> completed. PASS(1)
11007 12:25:06.922805 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11008 12:25:06.929051 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCF230093
11009 12:25:06.935730 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11010 12:25:06.939075 # selftests: arm64: fake_sigreturn_missing_fpsimd
11011 12:25:06.957070 # Registered handlers for all signals.
11012 12:25:06.957606 # Detected MINSTKSIGSZ:4720
11013 12:25:06.960333 # Testcase initialized.
11014 12:25:06.964020 # uc context validated.
11015 12:25:06.967008 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11016 12:25:06.970414 # Handled SIG_COPYCTX
11017 12:25:06.973769 # Mangling template header. Spare space:4096
11018 12:25:06.977043 # Using badly built context - ERR: Missing FPSIMD
11019 12:25:06.987228 # SIG_OK -- SP:0xFFFFEB1A0940 si_addr@:0xffffeb1a0940 si_code:2 token@:0xffffeb19f6e0 offset:-4704
11020 12:25:06.989841 # ==>> completed. PASS(1)
11021 12:25:06.996993 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11022 12:25:07.003399 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEB19F6E0
11023 12:25:07.007187 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11024 12:25:07.013035 # selftests: arm64: fake_sigreturn_sme_change_vl
11025 12:25:07.033836 # Registered handlers for all signals.
11026 12:25:07.034372 # Detected MINSTKSIGSZ:4720
11027 12:25:07.037658 # ==>> completed. SKIP.
11028 12:25:07.043738 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11029 12:25:07.046985 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11030 12:25:07.054638 # selftests: arm64: fake_sigreturn_sve_change_vl
11031 12:25:07.111257 # Registered handlers for all signals.
11032 12:25:07.111856 # Detected MINSTKSIGSZ:4720
11033 12:25:07.114185 # ==>> completed. SKIP.
11034 12:25:07.120904 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11035 12:25:07.123853 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11036 12:25:07.131361 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11037 12:25:07.187487 # Registered handlers for all signals.
11038 12:25:07.188048 # Detected MINSTKSIGSZ:4720
11039 12:25:07.191057 # Testcase initialized.
11040 12:25:07.194111 # uc context validated.
11041 12:25:07.194608 # Handled SIG_TRIG
11042 12:25:07.203896 # SIG_OK -- SP:0xFFFFD4299720 si_addr@:0xffffd4299720 si_code:2 token@:(nil) offset:-281474241238816
11043 12:25:07.207187 # ==>> completed. PASS(1)
11044 12:25:07.213681 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11045 12:25:07.220395 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11046 12:25:07.223587 # selftests: arm64: mangle_pstate_invalid_daif_bits
11047 12:25:07.251476 # Registered handlers for all signals.
11048 12:25:07.252010 # Detected MINSTKSIGSZ:4720
11049 12:25:07.254768 # Testcase initialized.
11050 12:25:07.258050 # uc context validated.
11051 12:25:07.258554 # Handled SIG_TRIG
11052 12:25:07.268202 # SIG_OK -- SP:0xFFFFD0E38F60 si_addr@:0xffffd0e38f60 si_code:2 token@:(nil) offset:-281474186317664
11053 12:25:07.271439 # ==>> completed. PASS(1)
11054 12:25:07.278041 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11055 12:25:07.281157 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11056 12:25:07.287860 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11057 12:25:07.330925 # Registered handlers for all signals.
11058 12:25:07.331531 # Detected MINSTKSIGSZ:4720
11059 12:25:07.334309 # Testcase initialized.
11060 12:25:07.337541 # uc context validated.
11061 12:25:07.338166 # Handled SIG_TRIG
11062 12:25:07.347500 # SIG_OK -- SP:0xFFFFC6D232F0 si_addr@:0xffffc6d232f0 si_code:2 token@:(nil) offset:-281474017407728
11063 12:25:07.350729 # ==>> completed. PASS(1)
11064 12:25:07.357973 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11065 12:25:07.360729 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11066 12:25:07.367094 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11067 12:25:07.414456 # Registered handlers for all signals.
11068 12:25:07.415001 # Detected MINSTKSIGSZ:4720
11069 12:25:07.417498 # Testcase initialized.
11070 12:25:07.420760 # uc context validated.
11071 12:25:07.421223 # Handled SIG_TRIG
11072 12:25:07.430590 # SIG_OK -- SP:0xFFFFD7A46F60 si_addr@:0xffffd7a46f60 si_code:2 token@:(nil) offset:-281474299621216
11073 12:25:07.433997 # ==>> completed. PASS(1)
11074 12:25:07.440635 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11075 12:25:07.444085 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11076 12:25:07.450388 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11077 12:25:07.516963 # Registered handlers for all signals.
11078 12:25:07.517519 # Detected MINSTKSIGSZ:4720
11079 12:25:07.520093 # Testcase initialized.
11080 12:25:07.523617 # uc context validated.
11081 12:25:07.524143 # Handled SIG_TRIG
11082 12:25:07.533333 # SIG_OK -- SP:0xFFFFC5FD6E80 si_addr@:0xffffc5fd6e80 si_code:2 token@:(nil) offset:-281474003463808
11083 12:25:07.536687 # ==>> completed. PASS(1)
11084 12:25:07.543548 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11085 12:25:07.546743 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11086 12:25:07.553211 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11087 12:25:07.600910 # Registered handlers for all signals.
11088 12:25:07.601455 # Detected MINSTKSIGSZ:4720
11089 12:25:07.603955 # Testcase initialized.
11090 12:25:07.607222 # uc context validated.
11091 12:25:07.607893 # Handled SIG_TRIG
11092 12:25:07.616859 # SIG_OK -- SP:0xFFFFC1541D00 si_addr@:0xffffc1541d00 si_code:2 token@:(nil) offset:-281473925258496
11093 12:25:07.620270 # ==>> completed. PASS(1)
11094 12:25:07.626367 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11095 12:25:07.629943 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11096 12:25:07.636183 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11097 12:25:07.674857 # Registered handlers for all signals.
11098 12:25:07.675124 # Detected MINSTKSIGSZ:4720
11099 12:25:07.678160 # Testcase initialized.
11100 12:25:07.681318 # uc context validated.
11101 12:25:07.681553 # Handled SIG_TRIG
11102 12:25:07.691548 # SIG_OK -- SP:0xFFFFCAC7F930 si_addr@:0xffffcac7f930 si_code:2 token@:(nil) offset:-281474083846448
11103 12:25:07.694607 # ==>> completed. PASS(1)
11104 12:25:07.701596 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11105 12:25:07.704665 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11106 12:25:07.711092 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11107 12:25:07.748998 # Registered handlers for all signals.
11108 12:25:07.749621 # Detected MINSTKSIGSZ:4720
11109 12:25:07.752119 # Testcase initialized.
11110 12:25:07.755642 # uc context validated.
11111 12:25:07.756169 # Handled SIG_TRIG
11112 12:25:07.765360 # SIG_OK -- SP:0xFFFFC653C600 si_addr@:0xffffc653c600 si_code:2 token@:(nil) offset:-281474009122304
11113 12:25:07.769050 # ==>> completed. PASS(1)
11114 12:25:07.775273 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11115 12:25:07.778504 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11116 12:25:07.781769 # selftests: arm64: sme_trap_no_sm
11117 12:25:07.820151 # Registered handlers for all signals.
11118 12:25:07.820751 # Detected MINSTKSIGSZ:4720
11119 12:25:07.823069 # ==>> completed. SKIP.
11120 12:25:07.832854 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11121 12:25:07.836251 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11122 12:25:07.842710 # selftests: arm64: sme_trap_non_streaming
11123 12:25:07.898768 # Registered handlers for all signals.
11124 12:25:07.899332 # Detected MINSTKSIGSZ:4720
11125 12:25:07.902080 # ==>> completed. SKIP.
11126 12:25:07.911837 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11127 12:25:07.918682 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11128 12:25:07.921704 # selftests: arm64: sme_trap_za
11129 12:25:07.973474 # Registered handlers for all signals.
11130 12:25:07.974059 # Detected MINSTKSIGSZ:4720
11131 12:25:07.976584 # Testcase initialized.
11132 12:25:07.986522 # SIG_OK -- SP:0xFFFFF7EEB010 si_addr@:0xaaaaadcb2510 si_code:1 token@:(nil) offset:-187650036933904
11133 12:25:07.987016 # ==>> completed. PASS(1)
11134 12:25:07.996537 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11135 12:25:07.999418 ok 21 selftests: arm64: sme_trap_za
11136 12:25:07.999991 # selftests: arm64: sme_vl
11137 12:25:08.055161 # Registered handlers for all signals.
11138 12:25:08.055848 # Detected MINSTKSIGSZ:4720
11139 12:25:08.058479 # ==>> completed. SKIP.
11140 12:25:08.064933 # # SME VL :: Check that we get the right SME VL reported
11141 12:25:08.068235 ok 22 selftests: arm64: sme_vl # SKIP
11142 12:25:08.071464 # selftests: arm64: ssve_regs
11143 12:25:08.125608 # Registered handlers for all signals.
11144 12:25:08.126183 # Detected MINSTKSIGSZ:4720
11145 12:25:08.128790 # ==>> completed. SKIP.
11146 12:25:08.135598 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11147 12:25:08.138820 ok 23 selftests: arm64: ssve_regs # SKIP
11148 12:25:08.142073 # selftests: arm64: sve_regs
11149 12:25:08.199690 # Registered handlers for all signals.
11150 12:25:08.200316 # Detected MINSTKSIGSZ:4720
11151 12:25:08.203041 # ==>> completed. SKIP.
11152 12:25:08.209291 # # SVE registers :: Check that we get the right SVE registers reported
11153 12:25:08.212692 ok 24 selftests: arm64: sve_regs # SKIP
11154 12:25:08.215922 # selftests: arm64: sve_vl
11155 12:25:08.276908 # Registered handlers for all signals.
11156 12:25:08.277518 # Detected MINSTKSIGSZ:4720
11157 12:25:08.280004 # ==>> completed. SKIP.
11158 12:25:08.283430 # # SVE VL :: Check that we get the right SVE VL reported
11159 12:25:08.289815 ok 25 selftests: arm64: sve_vl # SKIP
11160 12:25:08.295338 # selftests: arm64: za_no_regs
11161 12:25:08.367837 # Registered handlers for all signals.
11162 12:25:08.368424 # Detected MINSTKSIGSZ:4720
11163 12:25:08.371087 # ==>> completed. SKIP.
11164 12:25:08.377787 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11165 12:25:08.380885 ok 26 selftests: arm64: za_no_regs # SKIP
11166 12:25:08.386377 # selftests: arm64: za_regs
11167 12:25:08.454905 # Registered handlers for all signals.
11168 12:25:08.455526 # Detected MINSTKSIGSZ:4720
11169 12:25:08.457683 # ==>> completed. SKIP.
11170 12:25:08.464338 # # ZA register :: Check that we get the right ZA registers reported
11171 12:25:08.467564 ok 27 selftests: arm64: za_regs # SKIP
11172 12:25:08.472239 # selftests: arm64: pac
11173 12:25:08.531171 # TAP version 13
11174 12:25:08.531716 # 1..7
11175 12:25:08.534527 # # Starting 7 tests from 1 test cases.
11176 12:25:08.537392 # # RUN global.corrupt_pac ...
11177 12:25:08.540741 # # SKIP PAUTH not enabled
11178 12:25:08.544115 # # OK global.corrupt_pac
11179 12:25:08.547484 # ok 1 # SKIP PAUTH not enabled
11180 12:25:08.553983 # # RUN global.pac_instructions_not_nop ...
11181 12:25:08.557388 # # SKIP PAUTH not enabled
11182 12:25:08.560391 # # OK global.pac_instructions_not_nop
11183 12:25:08.563962 # ok 2 # SKIP PAUTH not enabled
11184 12:25:08.570497 # # RUN global.pac_instructions_not_nop_generic ...
11185 12:25:08.573679 # # SKIP Generic PAUTH not enabled
11186 12:25:08.576966 # # OK global.pac_instructions_not_nop_generic
11187 12:25:08.583747 # ok 3 # SKIP Generic PAUTH not enabled
11188 12:25:08.586781 # # RUN global.single_thread_different_keys ...
11189 12:25:08.589986 # # SKIP PAUTH not enabled
11190 12:25:08.596727 # # OK global.single_thread_different_keys
11191 12:25:08.597138 # ok 4 # SKIP PAUTH not enabled
11192 12:25:08.603609 # # RUN global.exec_changed_keys ...
11193 12:25:08.606919 # # SKIP PAUTH not enabled
11194 12:25:08.610208 # # OK global.exec_changed_keys
11195 12:25:08.613588 # ok 5 # SKIP PAUTH not enabled
11196 12:25:08.616864 # # RUN global.context_switch_keep_keys ...
11197 12:25:08.620087 # # SKIP PAUTH not enabled
11198 12:25:08.627131 # # OK global.context_switch_keep_keys
11199 12:25:08.630025 # ok 6 # SKIP PAUTH not enabled
11200 12:25:08.633159 # # RUN global.context_switch_keep_keys_generic ...
11201 12:25:08.637009 # # SKIP Generic PAUTH not enabled
11202 12:25:08.643515 # # OK global.context_switch_keep_keys_generic
11203 12:25:08.646739 # ok 7 # SKIP Generic PAUTH not enabled
11204 12:25:08.649877 # # PASSED: 7 / 7 tests passed.
11205 12:25:08.652892 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11206 12:25:08.656326 ok 28 selftests: arm64: pac
11207 12:25:08.659652 # selftests: arm64: fp-stress
11208 12:25:16.019635 <6>[ 46.548054] vpu: disabling
11209 12:25:16.022668 <6>[ 46.551102] vproc2: disabling
11210 12:25:16.025991 <6>[ 46.554605] vproc1: disabling
11211 12:25:16.029735 <6>[ 46.558344] vaud18: disabling
11212 12:25:16.036298 <6>[ 46.561864] vsram_others: disabling
11213 12:25:16.039578 <6>[ 46.565840] va09: disabling
11214 12:25:16.043209 <6>[ 46.569046] vsram_md: disabling
11215 12:25:16.046497 <6>[ 46.572635] Vgpu: disabling
11216 12:25:18.654448 # TAP version 13
11217 12:25:18.654994 # 1..16
11218 12:25:18.657962 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11219 12:25:18.661044 # # Will run for 10s
11220 12:25:18.661609 # # Started FPSIMD-0-0
11221 12:25:18.664121 # # Started FPSIMD-0-1
11222 12:25:18.667467 # # Started FPSIMD-1-0
11223 12:25:18.668265 # # Started FPSIMD-1-1
11224 12:25:18.671129 # # Started FPSIMD-2-0
11225 12:25:18.671723 # # Started FPSIMD-2-1
11226 12:25:18.674023 # # Started FPSIMD-3-0
11227 12:25:18.677659 # # Started FPSIMD-3-1
11228 12:25:18.678312 # # Started FPSIMD-4-0
11229 12:25:18.680672 # # Started FPSIMD-4-1
11230 12:25:18.684062 # # Started FPSIMD-5-0
11231 12:25:18.684595 # # Started FPSIMD-5-1
11232 12:25:18.687222 # # Started FPSIMD-6-0
11233 12:25:18.690823 # # Started FPSIMD-6-1
11234 12:25:18.691414 # # Started FPSIMD-7-0
11235 12:25:18.694138 # # Started FPSIMD-7-1
11236 12:25:18.697327 # # FPSIMD-1-0: Vector length: 128 bits
11237 12:25:18.700564 # # FPSIMD-1-0: PID: 1149
11238 12:25:18.703754 # # FPSIMD-2-0: Vector length: 128 bits
11239 12:25:18.704257 # # FPSIMD-2-0: PID: 1151
11240 12:25:18.707605 # # FPSIMD-0-1: Vector length: 128 bits
11241 12:25:18.710232 # # FPSIMD-0-1: PID: 1148
11242 12:25:18.713723 # # FPSIMD-1-1: Vector length: 128 bits
11243 12:25:18.717046 # # FPSIMD-1-1: PID: 1150
11244 12:25:18.720575 # # FPSIMD-0-0: Vector length: 128 bits
11245 12:25:18.723748 # # FPSIMD-0-0: PID: 1147
11246 12:25:18.727170 # # FPSIMD-2-1: Vector length: 128 bits
11247 12:25:18.730665 # # FPSIMD-2-1: PID: 1152
11248 12:25:18.734242 # # FPSIMD-6-0: Vector length: 128 bits
11249 12:25:18.734784 # # FPSIMD-6-0: PID: 1159
11250 12:25:18.736753 # # FPSIMD-7-1: Vector length: 128 bits
11251 12:25:18.740284 # # FPSIMD-7-1: PID: 1162
11252 12:25:18.743344 # # FPSIMD-4-1: Vector length: 128 bits
11253 12:25:18.746704 # # FPSIMD-4-1: PID: 1156
11254 12:25:18.750224 # # FPSIMD-4-0: Vector length: 128 bits
11255 12:25:18.753724 # # FPSIMD-4-0: PID: 1155
11256 12:25:18.756673 # # FPSIMD-5-0: Vector length: 128 bits
11257 12:25:18.757316 # # FPSIMD-5-0: PID: 1157
11258 12:25:18.763254 # # FPSIMD-3-1: Vector length: 128 bits
11259 12:25:18.763945 # # FPSIMD-3-1: PID: 1154
11260 12:25:18.766677 # # FPSIMD-5-1: Vector length: 128 bits
11261 12:25:18.769594 # # FPSIMD-5-1: PID: 1158
11262 12:25:18.773097 # # FPSIMD-7-0: Vector length: 128 bits
11263 12:25:18.776323 # # FPSIMD-7-0: PID: 1161
11264 12:25:18.779602 # # FPSIMD-3-0: Vector length: 128 bits
11265 12:25:18.783417 # # FPSIMD-3-0: PID: 1153
11266 12:25:18.786478 # # FPSIMD-6-1: Vector length: 128 bits
11267 12:25:18.787052 # # FPSIMD-6-1: PID: 1160
11268 12:25:18.789884 # # Finishing up...
11269 12:25:18.790428 # ok 1 FPSIMD-0-0
11270 12:25:18.792896 # ok 2 FPSIMD-0-1
11271 12:25:18.793344 # ok 3 FPSIMD-1-0
11272 12:25:18.796132 # ok 4 FPSIMD-1-1
11273 12:25:18.796671 # ok 5 FPSIMD-2-0
11274 12:25:18.799510 # ok 6 FPSIMD-2-1
11275 12:25:18.799959 # ok 7 FPSIMD-3-0
11276 12:25:18.802686 # ok 8 FPSIMD-3-1
11277 12:25:18.803281 # ok 9 FPSIMD-4-0
11278 12:25:18.806253 # ok 10 FPSIMD-4-1
11279 12:25:18.809592 # ok 11 FPSIMD-5-0
11280 12:25:18.810043 # ok 12 FPSIMD-5-1
11281 12:25:18.812685 # ok 13 FPSIMD-6-0
11282 12:25:18.813385 # ok 14 FPSIMD-6-1
11283 12:25:18.815943 # ok 15 FPSIMD-7-0
11284 12:25:18.816512 # ok 16 FPSIMD-7-1
11285 12:25:18.822686 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1296312, signals=10
11286 12:25:18.829573 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1110743, signals=10
11287 12:25:18.838872 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1122256, signals=10
11288 12:25:18.845766 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=2196281, signals=10
11289 12:25:18.852771 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=2197022, signals=10
11290 12:25:18.858866 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=2216453, signals=10
11291 12:25:18.865969 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=2255659, signals=10
11292 12:25:18.875889 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1115597, signals=9
11293 12:25:18.882258 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1114243, signals=10
11294 12:25:18.888734 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1122429, signals=10
11295 12:25:18.895246 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1111446, signals=10
11296 12:25:18.901818 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1160809, signals=9
11297 12:25:18.908506 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1146782, signals=10
11298 12:25:18.918185 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1124718, signals=10
11299 12:25:18.924891 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1102559, signals=10
11300 12:25:18.931571 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1167613, signals=9
11301 12:25:18.938526 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11302 12:25:18.939034 ok 29 selftests: arm64: fp-stress
11303 12:25:18.941576 # selftests: arm64: sve-ptrace
11304 12:25:18.944838 # TAP version 13
11305 12:25:18.945248 # 1..4104
11306 12:25:18.948341 # ok 2 # SKIP SVE not available
11307 12:25:18.951487 # # Planned tests != run tests (4104 != 1)
11308 12:25:18.958112 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11309 12:25:18.961363 ok 30 selftests: arm64: sve-ptrace # SKIP
11310 12:25:18.964608 # selftests: arm64: sve-probe-vls
11311 12:25:18.965065 # TAP version 13
11312 12:25:18.965424 # 1..2
11313 12:25:18.967908 # ok 2 # SKIP SVE not available
11314 12:25:18.970981 # # Planned tests != run tests (2 != 1)
11315 12:25:18.978041 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11316 12:25:18.980968 ok 31 selftests: arm64: sve-probe-vls # SKIP
11317 12:25:18.984531 # selftests: arm64: vec-syscfg
11318 12:25:18.984998 # TAP version 13
11319 12:25:18.987700 # 1..20
11320 12:25:18.988291 # ok 1 # SKIP SVE not supported
11321 12:25:18.990782 # ok 2 # SKIP SVE not supported
11322 12:25:18.994179 # ok 3 # SKIP SVE not supported
11323 12:25:18.997519 # ok 4 # SKIP SVE not supported
11324 12:25:19.000688 # ok 5 # SKIP SVE not supported
11325 12:25:19.003922 # ok 6 # SKIP SVE not supported
11326 12:25:19.007561 # ok 7 # SKIP SVE not supported
11327 12:25:19.010804 # ok 8 # SKIP SVE not supported
11328 12:25:19.011259 # ok 9 # SKIP SVE not supported
11329 12:25:19.014016 # ok 10 # SKIP SVE not supported
11330 12:25:19.017735 # ok 11 # SKIP SME not supported
11331 12:25:19.021006 # ok 12 # SKIP SME not supported
11332 12:25:19.024374 # ok 13 # SKIP SME not supported
11333 12:25:19.027673 # ok 14 # SKIP SME not supported
11334 12:25:19.030660 # ok 15 # SKIP SME not supported
11335 12:25:19.034252 # ok 16 # SKIP SME not supported
11336 12:25:19.034817 # ok 17 # SKIP SME not supported
11337 12:25:19.037159 # ok 18 # SKIP SME not supported
11338 12:25:19.040579 # ok 19 # SKIP SME not supported
11339 12:25:19.043824 # ok 20 # SKIP SME not supported
11340 12:25:19.050560 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11341 12:25:19.053881 ok 32 selftests: arm64: vec-syscfg
11342 12:25:19.054445 # selftests: arm64: za-fork
11343 12:25:19.057066 # TAP version 13
11344 12:25:19.057685 # 1..1
11345 12:25:19.060545 # # PID: 1236
11346 12:25:19.061044 # # SME support not present
11347 12:25:19.063821 # ok 0 skipped
11348 12:25:19.067252 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11349 12:25:19.070293 ok 33 selftests: arm64: za-fork
11350 12:25:19.073449 # selftests: arm64: za-ptrace
11351 12:25:19.074021 # TAP version 13
11352 12:25:19.076716 # 1..1
11353 12:25:19.077318 # ok 2 # SKIP SME not available
11354 12:25:19.083485 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11355 12:25:19.086967 ok 34 selftests: arm64: za-ptrace # SKIP
11356 12:25:19.090392 # selftests: arm64: check_buffer_fill
11357 12:25:19.120272 # # SKIP: MTE features unavailable
11358 12:25:19.127422 ok 35 selftests: arm64: check_buffer_fill # SKIP
11359 12:25:19.143271 # selftests: arm64: check_child_memory
11360 12:25:19.175668 # # SKIP: MTE features unavailable
11361 12:25:19.182431 ok 36 selftests: arm64: check_child_memory # SKIP
11362 12:25:19.198322 # selftests: arm64: check_gcr_el1_cswitch
11363 12:25:19.260162 # # SKIP: MTE features unavailable
11364 12:25:19.267155 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11365 12:25:19.284536 # selftests: arm64: check_ksm_options
11366 12:25:19.336946 # # SKIP: MTE features unavailable
11367 12:25:19.343877 ok 38 selftests: arm64: check_ksm_options # SKIP
11368 12:25:19.361450 # selftests: arm64: check_mmap_options
11369 12:25:19.415936 # # SKIP: MTE features unavailable
11370 12:25:19.422695 ok 39 selftests: arm64: check_mmap_options # SKIP
11371 12:25:19.438059 # selftests: arm64: check_prctl
11372 12:25:19.498798 # TAP version 13
11373 12:25:19.499342 # 1..5
11374 12:25:19.502402 # ok 1 check_basic_read
11375 12:25:19.502948 # ok 2 NONE
11376 12:25:19.505412 # ok 3 # SKIP SYNC
11377 12:25:19.506076 # ok 4 # SKIP ASYNC
11378 12:25:19.508375 # ok 5 # SKIP SYNC+ASYNC
11379 12:25:19.511883 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11380 12:25:19.514886 ok 40 selftests: arm64: check_prctl
11381 12:25:19.522179 # selftests: arm64: check_tags_inclusion
11382 12:25:19.573049 # # SKIP: MTE features unavailable
11383 12:25:19.580292 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11384 12:25:19.594590 # selftests: arm64: check_user_mem
11385 12:25:19.656638 # # SKIP: MTE features unavailable
11386 12:25:19.663897 ok 42 selftests: arm64: check_user_mem # SKIP
11387 12:25:19.677228 # selftests: arm64: btitest
11388 12:25:19.741835 # TAP version 13
11389 12:25:19.742087 # 1..18
11390 12:25:19.744770 # # HWCAP_PACA not present
11391 12:25:19.747985 # # HWCAP2_BTI not present
11392 12:25:19.748204 # # Test binary built for BTI
11393 12:25:19.755178 # ok 1 nohint_func/call_using_br_x0 # SKIP
11394 12:25:19.758332 # ok 1 nohint_func/call_using_br_x16 # SKIP
11395 12:25:19.761548 # ok 1 nohint_func/call_using_blr # SKIP
11396 12:25:19.765018 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11397 12:25:19.768155 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11398 12:25:19.774701 # ok 1 bti_none_func/call_using_blr # SKIP
11399 12:25:19.778020 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11400 12:25:19.781402 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11401 12:25:19.784666 # ok 1 bti_c_func/call_using_blr # SKIP
11402 12:25:19.787909 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11403 12:25:19.791403 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11404 12:25:19.794860 # ok 1 bti_j_func/call_using_blr # SKIP
11405 12:25:19.798074 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11406 12:25:19.804558 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11407 12:25:19.807848 # ok 1 bti_jc_func/call_using_blr # SKIP
11408 12:25:19.811567 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11409 12:25:19.814545 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11410 12:25:19.817476 # ok 1 paciasp_func/call_using_blr # SKIP
11411 12:25:19.824129 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11412 12:25:19.827730 # # WARNING - EXPECTED TEST COUNT WRONG
11413 12:25:19.830937 ok 43 selftests: arm64: btitest
11414 12:25:19.834179 # selftests: arm64: nobtitest
11415 12:25:19.834635 # TAP version 13
11416 12:25:19.834992 # 1..18
11417 12:25:19.837491 # # HWCAP_PACA not present
11418 12:25:19.840696 # # HWCAP2_BTI not present
11419 12:25:19.844338 # # Test binary not built for BTI
11420 12:25:19.847402 # ok 1 nohint_func/call_using_br_x0 # SKIP
11421 12:25:19.850818 # ok 1 nohint_func/call_using_br_x16 # SKIP
11422 12:25:19.853946 # ok 1 nohint_func/call_using_blr # SKIP
11423 12:25:19.857132 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11424 12:25:19.863875 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11425 12:25:19.867252 # ok 1 bti_none_func/call_using_blr # SKIP
11426 12:25:19.871018 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11427 12:25:19.873774 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11428 12:25:19.876929 # ok 1 bti_c_func/call_using_blr # SKIP
11429 12:25:19.880313 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11430 12:25:19.883647 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11431 12:25:19.886920 # ok 1 bti_j_func/call_using_blr # SKIP
11432 12:25:19.893709 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11433 12:25:19.896853 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11434 12:25:19.900253 # ok 1 bti_jc_func/call_using_blr # SKIP
11435 12:25:19.903814 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11436 12:25:19.906599 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11437 12:25:19.909894 # ok 1 paciasp_func/call_using_blr # SKIP
11438 12:25:19.916487 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11439 12:25:19.919793 # # WARNING - EXPECTED TEST COUNT WRONG
11440 12:25:19.922907 ok 44 selftests: arm64: nobtitest
11441 12:25:19.925921 # selftests: arm64: hwcap
11442 12:25:19.925994 # TAP version 13
11443 12:25:19.926056 # 1..28
11444 12:25:19.929289 # ok 1 cpuinfo_match_RNG
11445 12:25:19.932664 # # SIGILL reported for RNG
11446 12:25:19.936063 # ok 2 # SKIP sigill_RNG
11447 12:25:19.936169 # ok 3 cpuinfo_match_SME
11448 12:25:19.939285 # ok 4 sigill_SME
11449 12:25:19.939364 # ok 5 cpuinfo_match_SVE
11450 12:25:19.942884 # ok 6 sigill_SVE
11451 12:25:19.945919 # ok 7 cpuinfo_match_SVE 2
11452 12:25:19.946079 # # SIGILL reported for SVE 2
11453 12:25:19.949223 # ok 8 # SKIP sigill_SVE 2
11454 12:25:19.952635 # ok 9 cpuinfo_match_SVE AES
11455 12:25:19.955947 # # SIGILL reported for SVE AES
11456 12:25:19.959207 # ok 10 # SKIP sigill_SVE AES
11457 12:25:19.962876 # ok 11 cpuinfo_match_SVE2 PMULL
11458 12:25:19.965867 # # SIGILL reported for SVE2 PMULL
11459 12:25:19.966105 # ok 12 # SKIP sigill_SVE2 PMULL
11460 12:25:19.969314 # ok 13 cpuinfo_match_SVE2 BITPERM
11461 12:25:19.972516 # # SIGILL reported for SVE2 BITPERM
11462 12:25:19.975715 # ok 14 # SKIP sigill_SVE2 BITPERM
11463 12:25:19.979096 # ok 15 cpuinfo_match_SVE2 SHA3
11464 12:25:19.982434 # # SIGILL reported for SVE2 SHA3
11465 12:25:19.985690 # ok 16 # SKIP sigill_SVE2 SHA3
11466 12:25:19.988841 # ok 17 cpuinfo_match_SVE2 SM4
11467 12:25:19.992225 # # SIGILL reported for SVE2 SM4
11468 12:25:19.995694 # ok 18 # SKIP sigill_SVE2 SM4
11469 12:25:19.996114 # ok 19 cpuinfo_match_SVE2 I8MM
11470 12:25:19.999043 # # SIGILL reported for SVE2 I8MM
11471 12:25:20.002389 # ok 20 # SKIP sigill_SVE2 I8MM
11472 12:25:20.005459 # ok 21 cpuinfo_match_SVE2 F32MM
11473 12:25:20.009077 # # SIGILL reported for SVE2 F32MM
11474 12:25:20.012162 # ok 22 # SKIP sigill_SVE2 F32MM
11475 12:25:20.015355 # ok 23 cpuinfo_match_SVE2 F64MM
11476 12:25:20.018841 # # SIGILL reported for SVE2 F64MM
11477 12:25:20.022407 # ok 24 # SKIP sigill_SVE2 F64MM
11478 12:25:20.025320 # ok 25 cpuinfo_match_SVE2 BF16
11479 12:25:20.025732 # # SIGILL reported for SVE2 BF16
11480 12:25:20.028893 # ok 26 # SKIP sigill_SVE2 BF16
11481 12:25:20.031922 # ok 27 cpuinfo_match_SVE2 EBF16
11482 12:25:20.035228 # ok 28 # SKIP sigill_SVE2 EBF16
11483 12:25:20.042646 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11484 12:25:20.045212 ok 45 selftests: arm64: hwcap
11485 12:25:20.045630 # selftests: arm64: ptrace
11486 12:25:20.048410 # TAP version 13
11487 12:25:20.048824 # 1..7
11488 12:25:20.051573 # # Parent is 1478, child is 1479
11489 12:25:20.051987 # ok 1 read_tpidr_one
11490 12:25:20.054881 # ok 2 write_tpidr_one
11491 12:25:20.058448 # ok 3 verify_tpidr_one
11492 12:25:20.058945 # ok 4 count_tpidrs
11493 12:25:20.061507 # ok 5 tpidr2_write
11494 12:25:20.061916 # ok 6 tpidr2_read
11495 12:25:20.065071 # ok 7 write_tpidr_only
11496 12:25:20.071513 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11497 12:25:20.072005 ok 46 selftests: arm64: ptrace
11498 12:25:20.074758 # selftests: arm64: syscall-abi
11499 12:25:20.078076 # TAP version 13
11500 12:25:20.078485 # 1..2
11501 12:25:20.081296 # ok 1 getpid() FPSIMD
11502 12:25:20.081709 # ok 2 sched_yield() FPSIMD
11503 12:25:20.088008 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11504 12:25:20.091448 ok 47 selftests: arm64: syscall-abi
11505 12:25:20.094647 # selftests: arm64: tpidr2
11506 12:25:20.126757 # TAP version 13
11507 12:25:20.127312 # 1..5
11508 12:25:20.129947 # # PID: 1515
11509 12:25:20.130515 # # SME support not present
11510 12:25:20.133205 # ok 0 skipped, TPIDR2 not supported
11511 12:25:20.136593 # ok 1 skipped, TPIDR2 not supported
11512 12:25:20.139873 # ok 2 skipped, TPIDR2 not supported
11513 12:25:20.143377 # ok 3 skipped, TPIDR2 not supported
11514 12:25:20.146886 # ok 4 skipped, TPIDR2 not supported
11515 12:25:20.153208 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11516 12:25:20.156137 ok 48 selftests: arm64: tpidr2
11517 12:25:20.775191 arm64_tags_test pass
11518 12:25:20.778427 arm64_run_tags_test_sh pass
11519 12:25:20.781423 arm64_fake_sigreturn_bad_magic pass
11520 12:25:20.784719 arm64_fake_sigreturn_bad_size pass
11521 12:25:20.788136 arm64_fake_sigreturn_bad_size_for_magic0 pass
11522 12:25:20.791451 arm64_fake_sigreturn_duplicated_fpsimd pass
11523 12:25:20.794780 arm64_fake_sigreturn_misaligned_sp pass
11524 12:25:20.797990 arm64_fake_sigreturn_missing_fpsimd pass
11525 12:25:20.801184 arm64_fake_sigreturn_sme_change_vl skip
11526 12:25:20.807875 arm64_fake_sigreturn_sve_change_vl skip
11527 12:25:20.811654 arm64_mangle_pstate_invalid_compat_toggle pass
11528 12:25:20.814681 arm64_mangle_pstate_invalid_daif_bits pass
11529 12:25:20.818089 arm64_mangle_pstate_invalid_mode_el1h pass
11530 12:25:20.820866 arm64_mangle_pstate_invalid_mode_el1t pass
11531 12:25:20.824447 arm64_mangle_pstate_invalid_mode_el2h pass
11532 12:25:20.831096 arm64_mangle_pstate_invalid_mode_el2t pass
11533 12:25:20.834365 arm64_mangle_pstate_invalid_mode_el3h pass
11534 12:25:20.837893 arm64_mangle_pstate_invalid_mode_el3t pass
11535 12:25:20.840846 arm64_sme_trap_no_sm skip
11536 12:25:20.844162 arm64_sme_trap_non_streaming skip
11537 12:25:20.844762 arm64_sme_trap_za pass
11538 12:25:20.847479 arm64_sme_vl skip
11539 12:25:20.848036 arm64_ssve_regs skip
11540 12:25:20.850789 arm64_sve_regs skip
11541 12:25:20.851241 arm64_sve_vl skip
11542 12:25:20.854222 arm64_za_no_regs skip
11543 12:25:20.854775 arm64_za_regs skip
11544 12:25:20.856955 arm64_pac_pauth_not_enabled skip
11545 12:25:20.860455 arm64_pac_pauth_not_enabled skip
11546 12:25:20.863861 arm64_pac_generic_pauth_not_enabled skip
11547 12:25:20.867202 arm64_pac_pauth_not_enabled skip
11548 12:25:20.870478 arm64_pac_pauth_not_enabled skip
11549 12:25:20.873751 arm64_pac_pauth_not_enabled skip
11550 12:25:20.877524 arm64_pac_generic_pauth_not_enabled skip
11551 12:25:20.880312 arm64_pac pass
11552 12:25:20.880852 arm64_fp-stress_FPSIMD-0-0 pass
11553 12:25:20.883401 arm64_fp-stress_FPSIMD-0-1 pass
11554 12:25:20.887121 arm64_fp-stress_FPSIMD-1-0 pass
11555 12:25:20.890248 arm64_fp-stress_FPSIMD-1-1 pass
11556 12:25:20.893696 arm64_fp-stress_FPSIMD-2-0 pass
11557 12:25:20.896777 arm64_fp-stress_FPSIMD-2-1 pass
11558 12:25:20.900248 arm64_fp-stress_FPSIMD-3-0 pass
11559 12:25:20.900796 arm64_fp-stress_FPSIMD-3-1 pass
11560 12:25:20.903739 arm64_fp-stress_FPSIMD-4-0 pass
11561 12:25:20.906762 arm64_fp-stress_FPSIMD-4-1 pass
11562 12:25:20.909813 arm64_fp-stress_FPSIMD-5-0 pass
11563 12:25:20.913304 arm64_fp-stress_FPSIMD-5-1 pass
11564 12:25:20.916403 arm64_fp-stress_FPSIMD-6-0 pass
11565 12:25:20.920075 arm64_fp-stress_FPSIMD-6-1 pass
11566 12:25:20.923663 arm64_fp-stress_FPSIMD-7-0 pass
11567 12:25:20.924256 arm64_fp-stress_FPSIMD-7-1 pass
11568 12:25:20.926549 arm64_fp-stress pass
11569 12:25:20.929844 arm64_sve-ptrace_sve_not_available skip
11570 12:25:20.933483 arm64_sve-ptrace skip
11571 12:25:20.936701 arm64_sve-probe-vls_sve_not_available skip
11572 12:25:20.939503 arm64_sve-probe-vls skip
11573 12:25:20.943278 arm64_vec-syscfg_sve_not_supported skip
11574 12:25:20.946918 arm64_vec-syscfg_sve_not_supported skip
11575 12:25:20.949643 arm64_vec-syscfg_sve_not_supported skip
11576 12:25:20.952776 arm64_vec-syscfg_sve_not_supported skip
11577 12:25:20.956289 arm64_vec-syscfg_sve_not_supported skip
11578 12:25:20.959820 arm64_vec-syscfg_sve_not_supported skip
11579 12:25:20.962907 arm64_vec-syscfg_sve_not_supported skip
11580 12:25:20.966018 arm64_vec-syscfg_sve_not_supported skip
11581 12:25:20.969685 arm64_vec-syscfg_sve_not_supported skip
11582 12:25:20.973109 arm64_vec-syscfg_sve_not_supported skip
11583 12:25:20.975988 arm64_vec-syscfg_sme_not_supported skip
11584 12:25:20.979431 arm64_vec-syscfg_sme_not_supported skip
11585 12:25:20.986053 arm64_vec-syscfg_sme_not_supported skip
11586 12:25:20.988953 arm64_vec-syscfg_sme_not_supported skip
11587 12:25:20.992711 arm64_vec-syscfg_sme_not_supported skip
11588 12:25:20.995958 arm64_vec-syscfg_sme_not_supported skip
11589 12:25:20.999429 arm64_vec-syscfg_sme_not_supported skip
11590 12:25:21.002537 arm64_vec-syscfg_sme_not_supported skip
11591 12:25:21.005918 arm64_vec-syscfg_sme_not_supported skip
11592 12:25:21.008914 arm64_vec-syscfg_sme_not_supported skip
11593 12:25:21.012622 arm64_vec-syscfg pass
11594 12:25:21.013171 arm64_za-fork_skipped pass
11595 12:25:21.015564 arm64_za-fork pass
11596 12:25:21.018985 arm64_za-ptrace_sme_not_available skip
11597 12:25:21.023625 arm64_za-ptrace skip
11598 12:25:21.024170 arm64_check_buffer_fill skip
11599 12:25:21.025374 arm64_check_child_memory skip
11600 12:25:21.028858 arm64_check_gcr_el1_cswitch skip
11601 12:25:21.032239 arm64_check_ksm_options skip
11602 12:25:21.035744 arm64_check_mmap_options skip
11603 12:25:21.038833 arm64_check_prctl_check_basic_read pass
11604 12:25:21.042170 arm64_check_prctl_NONE pass
11605 12:25:21.042727 arm64_check_prctl_sync skip
11606 12:25:21.045552 arm64_check_prctl_async skip
11607 12:25:21.048946 arm64_check_prctl_sync_async skip
11608 12:25:21.051806 arm64_check_prctl pass
11609 12:25:21.055460 arm64_check_tags_inclusion skip
11610 12:25:21.056085 arm64_check_user_mem skip
11611 12:25:21.061816 arm64_btitest_nohint_func_call_using_br_x0 skip
11612 12:25:21.064902 arm64_btitest_nohint_func_call_using_br_x16 skip
11613 12:25:21.068146 arm64_btitest_nohint_func_call_using_blr skip
11614 12:25:21.071864 arm64_btitest_bti_none_func_call_using_br_x0 skip
11615 12:25:21.078497 arm64_btitest_bti_none_func_call_using_br_x16 skip
11616 12:25:21.081824 arm64_btitest_bti_none_func_call_using_blr skip
11617 12:25:21.084761 arm64_btitest_bti_c_func_call_using_br_x0 skip
11618 12:25:21.091533 arm64_btitest_bti_c_func_call_using_br_x16 skip
11619 12:25:21.094851 arm64_btitest_bti_c_func_call_using_blr skip
11620 12:25:21.097965 arm64_btitest_bti_j_func_call_using_br_x0 skip
11621 12:25:21.101209 arm64_btitest_bti_j_func_call_using_br_x16 skip
11622 12:25:21.108006 arm64_btitest_bti_j_func_call_using_blr skip
11623 12:25:21.111534 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11624 12:25:21.114338 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11625 12:25:21.117710 arm64_btitest_bti_jc_func_call_using_blr skip
11626 12:25:21.124608 arm64_btitest_paciasp_func_call_using_br_x0 skip
11627 12:25:21.127853 arm64_btitest_paciasp_func_call_using_br_x16 skip
11628 12:25:21.130796 arm64_btitest_paciasp_func_call_using_blr skip
11629 12:25:21.134528 arm64_btitest pass
11630 12:25:21.137597 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11631 12:25:21.143943 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11632 12:25:21.147220 arm64_nobtitest_nohint_func_call_using_blr skip
11633 12:25:21.150543 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11634 12:25:21.157236 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11635 12:25:21.160689 arm64_nobtitest_bti_none_func_call_using_blr skip
11636 12:25:21.163775 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11637 12:25:21.170415 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11638 12:25:21.173844 arm64_nobtitest_bti_c_func_call_using_blr skip
11639 12:25:21.177108 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11640 12:25:21.183638 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11641 12:25:21.186899 arm64_nobtitest_bti_j_func_call_using_blr skip
11642 12:25:21.190194 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11643 12:25:21.197198 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11644 12:25:21.200038 arm64_nobtitest_bti_jc_func_call_using_blr skip
11645 12:25:21.203346 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11646 12:25:21.209992 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11647 12:25:21.213390 arm64_nobtitest_paciasp_func_call_using_blr skip
11648 12:25:21.216630 arm64_nobtitest pass
11649 12:25:21.219957 arm64_hwcap_cpuinfo_match_RNG pass
11650 12:25:21.220495 arm64_hwcap_sigill_rng skip
11651 12:25:21.223349 arm64_hwcap_cpuinfo_match_SME pass
11652 12:25:21.226435 arm64_hwcap_sigill_SME pass
11653 12:25:21.229933 arm64_hwcap_cpuinfo_match_SVE pass
11654 12:25:21.233208 arm64_hwcap_sigill_SVE pass
11655 12:25:21.236408 arm64_hwcap_cpuinfo_match_SVE_2 pass
11656 12:25:21.236850 arm64_hwcap_sigill_sve_2 skip
11657 12:25:21.243160 arm64_hwcap_cpuinfo_match_SVE_AES pass
11658 12:25:21.243572 arm64_hwcap_sigill_sve_aes skip
11659 12:25:21.249840 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11660 12:25:21.250388 arm64_hwcap_sigill_sve2_pmull skip
11661 12:25:21.256075 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11662 12:25:21.259729 arm64_hwcap_sigill_sve2_bitperm skip
11663 12:25:21.263246 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11664 12:25:21.266043 arm64_hwcap_sigill_sve2_sha3 skip
11665 12:25:21.269425 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11666 12:25:21.272754 arm64_hwcap_sigill_sve2_sm4 skip
11667 12:25:21.276122 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11668 12:25:21.279694 arm64_hwcap_sigill_sve2_i8mm skip
11669 12:25:21.282631 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11670 12:25:21.286033 arm64_hwcap_sigill_sve2_f32mm skip
11671 12:25:21.289474 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11672 12:25:21.292787 arm64_hwcap_sigill_sve2_f64mm skip
11673 12:25:21.296044 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11674 12:25:21.299244 arm64_hwcap_sigill_sve2_bf16 skip
11675 12:25:21.302786 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11676 12:25:21.305930 arm64_hwcap_sigill_sve2_ebf16 skip
11677 12:25:21.306347 arm64_hwcap pass
11678 12:25:21.309167 arm64_ptrace_read_tpidr_one pass
11679 12:25:21.312601 arm64_ptrace_write_tpidr_one pass
11680 12:25:21.315610 arm64_ptrace_verify_tpidr_one pass
11681 12:25:21.318843 arm64_ptrace_count_tpidrs pass
11682 12:25:21.322364 arm64_ptrace_tpidr2_write pass
11683 12:25:21.325565 arm64_ptrace_tpidr2_read pass
11684 12:25:21.329041 arm64_ptrace_write_tpidr_only pass
11685 12:25:21.329450 arm64_ptrace pass
11686 12:25:21.332331 arm64_syscall-abi_getpid_FPSIMD pass
11687 12:25:21.335579 arm64_syscall-abi_sched_yield_FPSIMD pass
11688 12:25:21.338811 arm64_syscall-abi pass
11689 12:25:21.341796 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11690 12:25:21.345176 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11691 12:25:21.351690 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11692 12:25:21.354947 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11693 12:25:21.358317 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11694 12:25:21.361384 arm64_tpidr2 pass
11695 12:25:21.364702 + ../../utils/send-to-lava.sh ./output/result.txt
11696 12:25:21.371461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11697 12:25:21.371740 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11699 12:25:21.374815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11700 12:25:21.375068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11702 12:25:21.381381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11703 12:25:21.381660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11705 12:25:21.388136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11706 12:25:21.388433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11708 12:25:21.394853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11709 12:25:21.395104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11711 12:25:21.422318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11712 12:25:21.422634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11714 12:25:21.462480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11715 12:25:21.462743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11717 12:25:21.503454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11718 12:25:21.503714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11720 12:25:21.551542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11721 12:25:21.552531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11723 12:25:21.603054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11724 12:25:21.603781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11726 12:25:21.651945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11727 12:25:21.652896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11729 12:25:21.703727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11730 12:25:21.704585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11732 12:25:21.756788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11733 12:25:21.757552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11735 12:25:21.807294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11736 12:25:21.808021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11738 12:25:21.856862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11739 12:25:21.857588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11741 12:25:21.910234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11742 12:25:21.910917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11744 12:25:21.964243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11745 12:25:21.964977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11747 12:25:22.019168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11748 12:25:22.019940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11750 12:25:22.073387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11751 12:25:22.074112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11753 12:25:22.121880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11754 12:25:22.122673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11756 12:25:22.178045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11757 12:25:22.178760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11759 12:25:22.221338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11760 12:25:22.222032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11762 12:25:22.273157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11763 12:25:22.273843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
11765 12:25:22.324160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
11766 12:25:22.324429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
11768 12:25:22.369614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
11769 12:25:22.370070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
11771 12:25:22.418281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
11772 12:25:22.419079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
11774 12:25:22.469815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
11775 12:25:22.470571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
11777 12:25:22.518977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
11778 12:25:22.519707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
11780 12:25:22.567785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11782 12:25:22.570660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11783 12:25:22.617876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11785 12:25:22.620364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11786 12:25:22.674552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
11787 12:25:22.675287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
11789 12:25:22.720799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11791 12:25:22.723704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11792 12:25:22.763874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11794 12:25:22.766707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11795 12:25:22.813352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
11797 12:25:22.816492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
11798 12:25:22.882178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
11799 12:25:22.882854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
11801 12:25:22.931324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
11802 12:25:22.931990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
11804 12:25:22.987174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
11805 12:25:22.987853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
11807 12:25:23.040219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
11808 12:25:23.040912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
11810 12:25:23.087473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
11811 12:25:23.088141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
11813 12:25:23.136155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
11814 12:25:23.136844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
11816 12:25:23.186248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
11817 12:25:23.187026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
11819 12:25:23.237611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
11820 12:25:23.238357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
11822 12:25:23.286931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
11823 12:25:23.287278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
11825 12:25:23.334465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
11826 12:25:23.334743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
11828 12:25:23.382156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
11829 12:25:23.382460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
11831 12:25:23.417272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
11832 12:25:23.417529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
11834 12:25:23.456081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
11835 12:25:23.456808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
11837 12:25:23.500976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
11838 12:25:23.501662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
11840 12:25:23.549483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
11841 12:25:23.550171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
11843 12:25:23.591238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
11844 12:25:23.591538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
11846 12:25:23.634110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
11847 12:25:23.634773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
11849 12:25:23.681124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
11850 12:25:23.681792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
11852 12:25:23.729947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
11853 12:25:23.730620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
11855 12:25:23.781821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
11856 12:25:23.782489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
11858 12:25:23.829765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
11859 12:25:23.830428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
11861 12:25:23.883146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
11862 12:25:23.883812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
11864 12:25:23.926273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
11865 12:25:23.926935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
11867 12:25:23.974500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11868 12:25:23.975171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11870 12:25:24.018863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11871 12:25:24.019115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11873 12:25:24.059500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11874 12:25:24.059753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11876 12:25:24.097593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11877 12:25:24.097846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11879 12:25:24.139350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11880 12:25:24.139655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11882 12:25:24.184909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11883 12:25:24.185580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11885 12:25:24.236229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11886 12:25:24.236907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11888 12:25:24.286630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11889 12:25:24.287416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11891 12:25:24.338719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11892 12:25:24.339390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11894 12:25:24.395147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
11895 12:25:24.395816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
11897 12:25:24.445898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11898 12:25:24.446577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11900 12:25:24.495424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11901 12:25:24.496105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11903 12:25:24.542620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11904 12:25:24.543286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11906 12:25:24.590164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11907 12:25:24.590827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11909 12:25:24.640438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11910 12:25:24.641143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11912 12:25:24.685230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11913 12:25:24.685902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11915 12:25:24.735127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11916 12:25:24.735793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11918 12:25:24.785517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11919 12:25:24.786188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11921 12:25:24.835771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11922 12:25:24.836458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11924 12:25:24.889238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
11925 12:25:24.890095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
11927 12:25:24.944370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
11928 12:25:24.945176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
11930 12:25:24.996737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
11931 12:25:24.997460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
11933 12:25:25.045220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
11934 12:25:25.045892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
11936 12:25:25.097318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
11937 12:25:25.097991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
11939 12:25:25.146008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
11940 12:25:25.146676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
11942 12:25:25.198279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
11943 12:25:25.198947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
11945 12:25:25.248482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
11946 12:25:25.249155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
11948 12:25:25.299973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
11950 12:25:25.303119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
11951 12:25:25.348360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
11952 12:25:25.349031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
11954 12:25:25.391978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
11955 12:25:25.392246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
11957 12:25:25.436567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
11958 12:25:25.436822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
11960 12:25:25.469604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
11961 12:25:25.469856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
11963 12:25:25.510897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
11964 12:25:25.511158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
11966 12:25:25.550902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
11967 12:25:25.551569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
11969 12:25:25.597136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
11971 12:25:25.599991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
11972 12:25:25.647441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
11973 12:25:25.648106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
11975 12:25:25.695695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
11976 12:25:25.696377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
11978 12:25:25.743574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
11979 12:25:25.744278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
11981 12:25:25.794778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
11982 12:25:25.795454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
11984 12:25:25.849028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
11985 12:25:25.849700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
11987 12:25:25.900859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
11988 12:25:25.901528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
11990 12:25:25.951871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
11991 12:25:25.952567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
11993 12:25:26.005992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
11994 12:25:26.006660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
11996 12:25:26.058191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
11997 12:25:26.058864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
11999 12:25:26.107940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12000 12:25:26.108660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12002 12:25:26.159706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12003 12:25:26.160407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12005 12:25:26.209135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12006 12:25:26.209804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12008 12:25:26.262440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12009 12:25:26.263116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12011 12:25:26.313112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12012 12:25:26.313790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12014 12:25:26.362777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12015 12:25:26.363450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12017 12:25:26.410690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12018 12:25:26.410955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12020 12:25:26.455095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12021 12:25:26.455903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12023 12:25:26.503400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12024 12:25:26.503674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12026 12:25:26.544689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12027 12:25:26.544977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12029 12:25:26.586836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12030 12:25:26.587158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12032 12:25:26.625107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12033 12:25:26.625359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12035 12:25:26.663339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12036 12:25:26.663667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12038 12:25:26.710851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12039 12:25:26.711121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12041 12:25:26.763302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12042 12:25:26.763841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12044 12:25:26.812016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12045 12:25:26.812493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12047 12:25:26.865320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12048 12:25:26.866034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12050 12:25:26.919907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12051 12:25:26.920729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12053 12:25:26.972592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12054 12:25:26.973267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12056 12:25:27.021426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12057 12:25:27.022106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12059 12:25:27.072745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12060 12:25:27.073417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12062 12:25:27.123870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12063 12:25:27.124580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12065 12:25:27.179073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12066 12:25:27.179747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12068 12:25:27.234203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12069 12:25:27.234735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12071 12:25:27.286497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12072 12:25:27.286956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12074 12:25:27.336445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12075 12:25:27.336729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12077 12:25:27.382908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12078 12:25:27.383581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12080 12:25:27.437810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12081 12:25:27.438489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12083 12:25:27.484082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12084 12:25:27.484396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12086 12:25:27.526468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12087 12:25:27.526743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12089 12:25:27.579011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12090 12:25:27.579824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12092 12:25:27.626153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12093 12:25:27.626877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12095 12:25:27.686998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12096 12:25:27.687690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12098 12:25:27.735015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12099 12:25:27.735740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12101 12:25:27.790784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12102 12:25:27.791535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12104 12:25:27.837331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12105 12:25:27.838006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12107 12:25:27.886036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12108 12:25:27.886449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12110 12:25:27.933805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12111 12:25:27.934544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12113 12:25:27.991392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12114 12:25:27.992146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12116 12:25:28.044342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12117 12:25:28.045081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12119 12:25:28.106415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12120 12:25:28.107340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12122 12:25:28.158312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12123 12:25:28.159038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12125 12:25:28.211627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12126 12:25:28.212295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12128 12:25:28.263894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12129 12:25:28.264617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12131 12:25:28.317706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12132 12:25:28.318416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12134 12:25:28.373081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12135 12:25:28.373772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12137 12:25:28.427170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12138 12:25:28.427852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12140 12:25:28.473471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12142 12:25:28.476116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12143 12:25:28.523221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12144 12:25:28.523546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12146 12:25:28.565168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12148 12:25:28.568256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12149 12:25:28.610987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12150 12:25:28.611871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12152 12:25:28.657827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12154 12:25:28.660561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12155 12:25:28.714077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12156 12:25:28.714882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12158 12:25:28.758348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12160 12:25:28.761147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12161 12:25:28.810478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12162 12:25:28.811408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12164 12:25:28.861356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12165 12:25:28.862104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12167 12:25:28.916866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12168 12:25:28.917583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12170 12:25:28.965856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12172 12:25:28.968856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12173 12:25:29.020823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12174 12:25:29.021550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12176 12:25:29.077027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12177 12:25:29.077753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12179 12:25:29.129205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12180 12:25:29.129959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12182 12:25:29.184231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12184 12:25:29.186915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12185 12:25:29.237088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12187 12:25:29.239766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12188 12:25:29.295629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12189 12:25:29.296295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12191 12:25:29.346533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12192 12:25:29.347209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12194 12:25:29.395635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12195 12:25:29.396308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12197 12:25:29.447086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12198 12:25:29.447758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12200 12:25:29.499730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12201 12:25:29.500416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12203 12:25:29.551379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12204 12:25:29.552122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12206 12:25:29.606110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12207 12:25:29.606791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12209 12:25:29.658785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12210 12:25:29.659457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12212 12:25:29.706130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12213 12:25:29.706805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12215 12:25:29.764341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12216 12:25:29.765105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12218 12:25:29.812682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12219 12:25:29.813439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12221 12:25:29.867262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12222 12:25:29.868004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12224 12:25:29.918680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12225 12:25:29.919354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12227 12:25:29.970243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12228 12:25:29.970923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12230 12:25:30.018569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12231 12:25:30.018992 + set +x
12232 12:25:30.019605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12234 12:25:30.025139 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 11893158_1.6.2.3.5>
12235 12:25:30.025805 Received signal: <ENDRUN> 1_kselftest-arm64 11893158_1.6.2.3.5
12236 12:25:30.026251 Ending use of test pattern.
12237 12:25:30.026582 Ending test lava.1_kselftest-arm64 (11893158_1.6.2.3.5), duration 33.32
12239 12:25:30.028637 <LAVA_TEST_RUNNER EXIT>
12240 12:25:30.029613 ok: lava_test_shell seems to have completed
12241 12:25:30.035034 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12242 12:25:30.035949 end: 3.1 lava-test-shell (duration 00:00:34) [common]
12243 12:25:30.036452 end: 3 lava-test-retry (duration 00:00:34) [common]
12244 12:25:30.036897 start: 4 finalize (timeout 00:07:12) [common]
12245 12:25:30.037338 start: 4.1 power-off (timeout 00:00:30) [common]
12246 12:25:30.038067 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
12247 12:25:30.154797 >> Command sent successfully.
12248 12:25:30.158266 Returned 0 in 0 seconds
12249 12:25:30.259172 end: 4.1 power-off (duration 00:00:00) [common]
12251 12:25:30.260965 start: 4.2 read-feedback (timeout 00:07:12) [common]
12252 12:25:30.262503 Listened to connection for namespace 'common' for up to 1s
12253 12:25:31.262903 Finalising connection for namespace 'common'
12254 12:25:31.263607 Disconnecting from shell: Finalise
12255 12:25:31.264073 / #
12256 12:25:31.365225 end: 4.2 read-feedback (duration 00:00:01) [common]
12257 12:25:31.365958 end: 4 finalize (duration 00:00:01) [common]
12258 12:25:31.366592 Cleaning after the job
12259 12:25:31.367154 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/ramdisk
12260 12:25:31.379734 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/kernel
12261 12:25:31.415897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/dtb
12262 12:25:31.416213 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/nfsrootfs
12263 12:25:31.510343 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893158/tftp-deploy-cjli5no0/modules
12264 12:25:31.517749 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893158
12265 12:25:32.171391 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893158
12266 12:25:32.171573 Job finished correctly