Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 25
- Kernel Errors: 36
- Errors: 0
- Boot result: PASS
1 12:16:21.466994 lava-dispatcher, installed at version: 2023.08
2 12:16:21.467200 start: 0 validate
3 12:16:21.467329 Start time: 2023-10-27 12:16:21.467322+00:00 (UTC)
4 12:16:21.467447 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:16:21.467576 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:16:21.734358 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:16:21.734532 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:16:21.992016 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:16:21.992367 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:16:54.641679 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:16:54.641941 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:16:55.170676 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:16:55.170929 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:16:55.440161 validate duration: 33.97
16 12:16:55.440438 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:16:55.440535 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:16:55.440626 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:16:55.440755 Not decompressing ramdisk as can be used compressed.
20 12:16:55.440843 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:16:55.440907 saving as /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/ramdisk/initrd.cpio.gz
22 12:16:55.440977 total size: 4665395 (4 MB)
23 12:16:57.698528 progress 0 % (0 MB)
24 12:16:57.700811 progress 5 % (0 MB)
25 12:16:57.702831 progress 10 % (0 MB)
26 12:16:57.704768 progress 15 % (0 MB)
27 12:16:57.706708 progress 20 % (0 MB)
28 12:16:57.708689 progress 25 % (1 MB)
29 12:16:57.710651 progress 30 % (1 MB)
30 12:16:57.712244 progress 35 % (1 MB)
31 12:16:57.713693 progress 40 % (1 MB)
32 12:16:57.715208 progress 45 % (2 MB)
33 12:16:57.716532 progress 50 % (2 MB)
34 12:16:57.717905 progress 55 % (2 MB)
35 12:16:57.719243 progress 60 % (2 MB)
36 12:16:57.720485 progress 65 % (2 MB)
37 12:16:57.721711 progress 70 % (3 MB)
38 12:16:57.722992 progress 75 % (3 MB)
39 12:16:57.724369 progress 80 % (3 MB)
40 12:16:57.725970 progress 85 % (3 MB)
41 12:16:57.727405 progress 90 % (4 MB)
42 12:16:57.728839 progress 95 % (4 MB)
43 12:16:57.730553 progress 100 % (4 MB)
44 12:16:57.730827 4 MB downloaded in 2.29 s (1.94 MB/s)
45 12:16:57.731033 end: 1.1.1 http-download (duration 00:00:02) [common]
47 12:16:57.731402 end: 1.1 download-retry (duration 00:00:02) [common]
48 12:16:57.731518 start: 1.2 download-retry (timeout 00:09:58) [common]
49 12:16:57.731632 start: 1.2.1 http-download (timeout 00:09:58) [common]
50 12:16:57.731791 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:16:57.731888 saving as /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/kernel/Image
52 12:16:57.731977 total size: 49236480 (46 MB)
53 12:16:57.732066 No compression specified
54 12:16:57.733708 progress 0 % (0 MB)
55 12:16:57.746914 progress 5 % (2 MB)
56 12:16:57.759907 progress 10 % (4 MB)
57 12:16:57.772947 progress 15 % (7 MB)
58 12:16:57.785823 progress 20 % (9 MB)
59 12:16:57.798683 progress 25 % (11 MB)
60 12:16:57.811594 progress 30 % (14 MB)
61 12:16:57.824369 progress 35 % (16 MB)
62 12:16:57.837368 progress 40 % (18 MB)
63 12:16:57.850225 progress 45 % (21 MB)
64 12:16:57.863282 progress 50 % (23 MB)
65 12:16:57.875949 progress 55 % (25 MB)
66 12:16:57.891630 progress 60 % (28 MB)
67 12:16:57.904529 progress 65 % (30 MB)
68 12:16:57.917624 progress 70 % (32 MB)
69 12:16:57.930435 progress 75 % (35 MB)
70 12:16:57.943429 progress 80 % (37 MB)
71 12:16:57.956219 progress 85 % (39 MB)
72 12:16:57.969247 progress 90 % (42 MB)
73 12:16:57.982095 progress 95 % (44 MB)
74 12:16:57.994829 progress 100 % (46 MB)
75 12:16:57.995114 46 MB downloaded in 0.26 s (178.45 MB/s)
76 12:16:57.995288 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:16:57.995522 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:16:57.995610 start: 1.3 download-retry (timeout 00:09:57) [common]
80 12:16:57.995700 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 12:16:57.995826 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:16:57.995900 saving as /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/dtb/mt8192-asurada-spherion-r0.dtb
83 12:16:57.995961 total size: 47278 (0 MB)
84 12:16:57.996022 No compression specified
85 12:16:57.997187 progress 69 % (0 MB)
86 12:16:57.997468 progress 100 % (0 MB)
87 12:16:57.997625 0 MB downloaded in 0.00 s (27.13 MB/s)
88 12:16:57.997751 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:16:57.997973 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:16:57.998056 start: 1.4 download-retry (timeout 00:09:57) [common]
92 12:16:57.998137 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 12:16:57.998254 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:16:57.998325 saving as /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/nfsrootfs/full.rootfs.tar
95 12:16:57.998386 total size: 200813988 (191 MB)
96 12:16:57.998446 Using unxz to decompress xz
97 12:16:58.002705 progress 0 % (0 MB)
98 12:16:58.551739 progress 5 % (9 MB)
99 12:16:59.096462 progress 10 % (19 MB)
100 12:16:59.700969 progress 15 % (28 MB)
101 12:17:00.101532 progress 20 % (38 MB)
102 12:17:00.444532 progress 25 % (47 MB)
103 12:17:01.046495 progress 30 % (57 MB)
104 12:17:01.607489 progress 35 % (67 MB)
105 12:17:02.248676 progress 40 % (76 MB)
106 12:17:02.881128 progress 45 % (86 MB)
107 12:17:03.501413 progress 50 % (95 MB)
108 12:17:04.168917 progress 55 % (105 MB)
109 12:17:04.866743 progress 60 % (114 MB)
110 12:17:05.013218 progress 65 % (124 MB)
111 12:17:05.170455 progress 70 % (134 MB)
112 12:17:05.286000 progress 75 % (143 MB)
113 12:17:05.366677 progress 80 % (153 MB)
114 12:17:05.635651 progress 85 % (162 MB)
115 12:17:05.768234 progress 90 % (172 MB)
116 12:17:06.115382 progress 95 % (181 MB)
117 12:17:06.791103 progress 100 % (191 MB)
118 12:17:06.796545 191 MB downloaded in 8.80 s (21.77 MB/s)
119 12:17:06.796991 end: 1.4.1 http-download (duration 00:00:09) [common]
121 12:17:06.797446 end: 1.4 download-retry (duration 00:00:09) [common]
122 12:17:06.797591 start: 1.5 download-retry (timeout 00:09:49) [common]
123 12:17:06.797726 start: 1.5.1 http-download (timeout 00:09:49) [common]
124 12:17:06.797954 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:17:06.798087 saving as /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/modules/modules.tar
126 12:17:06.798189 total size: 8625084 (8 MB)
127 12:17:06.798284 Using unxz to decompress xz
128 12:17:07.069378 progress 0 % (0 MB)
129 12:17:07.091881 progress 5 % (0 MB)
130 12:17:07.114809 progress 10 % (0 MB)
131 12:17:07.141666 progress 15 % (1 MB)
132 12:17:07.168177 progress 20 % (1 MB)
133 12:17:07.194965 progress 25 % (2 MB)
134 12:17:07.222280 progress 30 % (2 MB)
135 12:17:07.251396 progress 35 % (2 MB)
136 12:17:07.279571 progress 40 % (3 MB)
137 12:17:07.306001 progress 45 % (3 MB)
138 12:17:07.334824 progress 50 % (4 MB)
139 12:17:07.363088 progress 55 % (4 MB)
140 12:17:07.392207 progress 60 % (4 MB)
141 12:17:07.419634 progress 65 % (5 MB)
142 12:17:07.448300 progress 70 % (5 MB)
143 12:17:07.476123 progress 75 % (6 MB)
144 12:17:07.507159 progress 80 % (6 MB)
145 12:17:07.540319 progress 85 % (7 MB)
146 12:17:07.569609 progress 90 % (7 MB)
147 12:17:07.598383 progress 95 % (7 MB)
148 12:17:07.624290 progress 100 % (8 MB)
149 12:17:07.629534 8 MB downloaded in 0.83 s (9.89 MB/s)
150 12:17:07.629955 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:17:07.630368 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:17:07.630504 start: 1.6 prepare-tftp-overlay (timeout 00:09:48) [common]
154 12:17:07.630658 start: 1.6.1 extract-nfsrootfs (timeout 00:09:48) [common]
155 12:17:11.425188 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11893105/extract-nfsrootfs-gf_o5kdg
156 12:17:11.425394 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:17:11.425495 start: 1.6.2 lava-overlay (timeout 00:09:44) [common]
158 12:17:11.425708 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy
159 12:17:11.425848 makedir: /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin
160 12:17:11.425951 makedir: /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/tests
161 12:17:11.426048 makedir: /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/results
162 12:17:11.426154 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-add-keys
163 12:17:11.426302 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-add-sources
164 12:17:11.426432 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-background-process-start
165 12:17:11.426560 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-background-process-stop
166 12:17:11.426687 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-common-functions
167 12:17:11.426852 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-echo-ipv4
168 12:17:11.426993 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-install-packages
169 12:17:11.427117 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-installed-packages
170 12:17:11.427238 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-os-build
171 12:17:11.427363 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-probe-channel
172 12:17:11.427486 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-probe-ip
173 12:17:11.427644 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-target-ip
174 12:17:11.427816 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-target-mac
175 12:17:11.428021 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-target-storage
176 12:17:11.428163 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-test-case
177 12:17:11.428293 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-test-event
178 12:17:11.428417 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-test-feedback
179 12:17:11.428542 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-test-raise
180 12:17:11.428666 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-test-reference
181 12:17:11.428835 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-test-runner
182 12:17:11.428962 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-test-set
183 12:17:11.429089 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-test-shell
184 12:17:11.429216 Updating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-add-keys (debian)
185 12:17:11.429365 Updating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-add-sources (debian)
186 12:17:11.429509 Updating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-install-packages (debian)
187 12:17:11.429665 Updating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-installed-packages (debian)
188 12:17:11.429818 Updating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/bin/lava-os-build (debian)
189 12:17:11.429940 Creating /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/environment
190 12:17:11.430037 LAVA metadata
191 12:17:11.430108 - LAVA_JOB_ID=11893105
192 12:17:11.430172 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:17:11.430287 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:44) [common]
194 12:17:11.430354 skipped lava-vland-overlay
195 12:17:11.430432 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:17:11.430513 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:44) [common]
197 12:17:11.430574 skipped lava-multinode-overlay
198 12:17:11.430679 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:17:11.430803 start: 1.6.2.3 test-definition (timeout 00:09:44) [common]
200 12:17:11.430881 Loading test definitions
201 12:17:11.430973 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:44) [common]
202 12:17:11.431046 Using /lava-11893105 at stage 0
203 12:17:11.431338 uuid=11893105_1.6.2.3.1 testdef=None
204 12:17:11.431426 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:17:11.431510 start: 1.6.2.3.2 test-overlay (timeout 00:09:44) [common]
206 12:17:11.431967 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:17:11.432185 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:44) [common]
209 12:17:11.432735 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:17:11.432965 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:44) [common]
212 12:17:12.972950 runner path: /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/0/tests/0_timesync-off test_uuid 11893105_1.6.2.3.1
213 12:17:13.301429 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:02) [common]
215 12:17:13.301966 start: 1.6.2.3.5 git-repo-action (timeout 00:09:42) [common]
216 12:17:13.302095 Using /lava-11893105 at stage 0
217 12:17:13.302275 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:17:13.302409 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/0/tests/1_kselftest-rtc'
219 12:17:22.780787 Running '/usr/bin/git checkout kernelci.org
220 12:17:22.927652 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 12:17:22.928402 uuid=11893105_1.6.2.3.5 testdef=None
222 12:17:22.928567 end: 1.6.2.3.5 git-repo-action (duration 00:00:10) [common]
224 12:17:22.928817 start: 1.6.2.3.6 test-overlay (timeout 00:09:33) [common]
225 12:17:22.929567 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:17:22.929803 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:33) [common]
228 12:17:22.930980 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:17:22.931218 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:33) [common]
231 12:17:22.932191 runner path: /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/0/tests/1_kselftest-rtc test_uuid 11893105_1.6.2.3.5
232 12:17:22.932283 BOARD='mt8192-asurada-spherion-r0'
233 12:17:22.932348 BRANCH='cip-gitlab'
234 12:17:22.932407 SKIPFILE='/dev/null'
235 12:17:22.932465 SKIP_INSTALL='True'
236 12:17:22.932522 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:17:22.932580 TST_CASENAME=''
238 12:17:22.932634 TST_CMDFILES='rtc'
239 12:17:22.932777 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:17:22.932980 Creating lava-test-runner.conf files
242 12:17:22.933042 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893105/lava-overlay-ih7wyoqy/lava-11893105/0 for stage 0
243 12:17:22.933137 - 0_timesync-off
244 12:17:22.933205 - 1_kselftest-rtc
245 12:17:22.933302 end: 1.6.2.3 test-definition (duration 00:00:12) [common]
246 12:17:22.933390 start: 1.6.2.4 compress-overlay (timeout 00:09:33) [common]
247 12:17:35.133712 end: 1.6.2.4 compress-overlay (duration 00:00:12) [common]
248 12:17:35.133891 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:20) [common]
249 12:17:35.134027 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:17:35.134127 end: 1.6.2 lava-overlay (duration 00:00:24) [common]
251 12:17:35.134220 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:20) [common]
252 12:17:35.259441 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:17:35.259834 start: 1.6.4 extract-modules (timeout 00:09:20) [common]
254 12:17:35.259954 extracting modules file /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893105/extract-nfsrootfs-gf_o5kdg
255 12:17:35.494759 extracting modules file /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893105/extract-overlay-ramdisk-h7bfy8ds/ramdisk
256 12:17:35.741080 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:17:35.741245 start: 1.6.5 apply-overlay-tftp (timeout 00:09:20) [common]
258 12:17:35.741376 [common] Applying overlay to NFS
259 12:17:35.741476 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893105/compress-overlay-bqhsytgh/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893105/extract-nfsrootfs-gf_o5kdg
260 12:17:36.707181 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:17:36.707343 start: 1.6.6 configure-preseed-file (timeout 00:09:19) [common]
262 12:17:36.707445 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:17:36.707540 start: 1.6.7 compress-ramdisk (timeout 00:09:19) [common]
264 12:17:36.707631 Building ramdisk /var/lib/lava/dispatcher/tmp/11893105/extract-overlay-ramdisk-h7bfy8ds/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893105/extract-overlay-ramdisk-h7bfy8ds/ramdisk
265 12:17:37.013242 >> 119370 blocks
266 12:17:38.983339 rename /var/lib/lava/dispatcher/tmp/11893105/extract-overlay-ramdisk-h7bfy8ds/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/ramdisk/ramdisk.cpio.gz
267 12:17:38.983805 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:17:38.983935 start: 1.6.8 prepare-kernel (timeout 00:09:16) [common]
269 12:17:38.984042 start: 1.6.8.1 prepare-fit (timeout 00:09:16) [common]
270 12:17:38.984155 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/kernel/Image'
271 12:17:56.917348 Returned 0 in 17 seconds
272 12:17:57.018302 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/kernel/image.itb
273 12:17:57.401519 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:17:57.401880 output: Created: Fri Oct 27 13:17:57 2023
275 12:17:57.401956 output: Image 0 (kernel-1)
276 12:17:57.402024 output: Description:
277 12:17:57.402088 output: Created: Fri Oct 27 13:17:57 2023
278 12:17:57.402149 output: Type: Kernel Image
279 12:17:57.402211 output: Compression: lzma compressed
280 12:17:57.402267 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
281 12:17:57.402327 output: Architecture: AArch64
282 12:17:57.402387 output: OS: Linux
283 12:17:57.402450 output: Load Address: 0x00000000
284 12:17:57.402527 output: Entry Point: 0x00000000
285 12:17:57.402585 output: Hash algo: crc32
286 12:17:57.402644 output: Hash value: d33b93ae
287 12:17:57.402700 output: Image 1 (fdt-1)
288 12:17:57.402789 output: Description: mt8192-asurada-spherion-r0
289 12:17:57.402843 output: Created: Fri Oct 27 13:17:57 2023
290 12:17:57.402896 output: Type: Flat Device Tree
291 12:17:57.402949 output: Compression: uncompressed
292 12:17:57.403002 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:17:57.403055 output: Architecture: AArch64
294 12:17:57.403108 output: Hash algo: crc32
295 12:17:57.403161 output: Hash value: cc4352de
296 12:17:57.403213 output: Image 2 (ramdisk-1)
297 12:17:57.403265 output: Description: unavailable
298 12:17:57.403318 output: Created: Fri Oct 27 13:17:57 2023
299 12:17:57.403370 output: Type: RAMDisk Image
300 12:17:57.403423 output: Compression: Unknown Compression
301 12:17:57.403475 output: Data Size: 17792226 Bytes = 17375.22 KiB = 16.97 MiB
302 12:17:57.403528 output: Architecture: AArch64
303 12:17:57.403582 output: OS: Linux
304 12:17:57.403663 output: Load Address: unavailable
305 12:17:57.403718 output: Entry Point: unavailable
306 12:17:57.403772 output: Hash algo: crc32
307 12:17:57.403824 output: Hash value: 019885d4
308 12:17:57.403877 output: Default Configuration: 'conf-1'
309 12:17:57.403930 output: Configuration 0 (conf-1)
310 12:17:57.403982 output: Description: mt8192-asurada-spherion-r0
311 12:17:57.404035 output: Kernel: kernel-1
312 12:17:57.404088 output: Init Ramdisk: ramdisk-1
313 12:17:57.404141 output: FDT: fdt-1
314 12:17:57.404192 output: Loadables: kernel-1
315 12:17:57.404245 output:
316 12:17:57.404453 end: 1.6.8.1 prepare-fit (duration 00:00:18) [common]
317 12:17:57.404551 end: 1.6.8 prepare-kernel (duration 00:00:18) [common]
318 12:17:57.404668 end: 1.6 prepare-tftp-overlay (duration 00:00:50) [common]
319 12:17:57.404803 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:58) [common]
320 12:17:57.404922 No LXC device requested
321 12:17:57.405035 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:17:57.405126 start: 1.8 deploy-device-env (timeout 00:08:58) [common]
323 12:17:57.405206 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:17:57.405281 Checking files for TFTP limit of 4294967296 bytes.
325 12:17:57.405796 end: 1 tftp-deploy (duration 00:01:02) [common]
326 12:17:57.405904 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:17:57.405994 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:17:57.406121 substitutions:
329 12:17:57.406185 - {DTB}: 11893105/tftp-deploy-_84d9rro/dtb/mt8192-asurada-spherion-r0.dtb
330 12:17:57.406249 - {INITRD}: 11893105/tftp-deploy-_84d9rro/ramdisk/ramdisk.cpio.gz
331 12:17:57.406308 - {KERNEL}: 11893105/tftp-deploy-_84d9rro/kernel/Image
332 12:17:57.406364 - {LAVA_MAC}: None
333 12:17:57.406419 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11893105/extract-nfsrootfs-gf_o5kdg
334 12:17:57.406474 - {NFS_SERVER_IP}: 192.168.201.1
335 12:17:57.406528 - {PRESEED_CONFIG}: None
336 12:17:57.406582 - {PRESEED_LOCAL}: None
337 12:17:57.406635 - {RAMDISK}: 11893105/tftp-deploy-_84d9rro/ramdisk/ramdisk.cpio.gz
338 12:17:57.406690 - {ROOT_PART}: None
339 12:17:57.406787 - {ROOT}: None
340 12:17:57.406870 - {SERVER_IP}: 192.168.201.1
341 12:17:57.406923 - {TEE}: None
342 12:17:57.406977 Parsed boot commands:
343 12:17:57.407030 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:17:57.407235 Parsed boot commands: tftpboot 192.168.201.1 11893105/tftp-deploy-_84d9rro/kernel/image.itb 11893105/tftp-deploy-_84d9rro/kernel/cmdline
345 12:17:57.407326 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:17:57.407414 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:17:57.407505 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:17:57.407588 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:17:57.407657 Not connected, no need to disconnect.
350 12:17:57.407731 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:17:57.407814 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:17:57.407880 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 12:17:57.411897 Setting prompt string to ['lava-test: # ']
354 12:17:57.412264 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:17:57.412380 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:17:57.412479 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:17:57.412580 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:17:57.412776 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 12:18:02.558173 >> Command sent successfully.
360 12:18:02.568739 Returned 0 in 5 seconds
361 12:18:02.669981 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:18:02.671433 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:18:02.671961 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:18:02.672416 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:18:02.672756 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:18:02.673115 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:18:02.674334 [Enter `^Ec?' for help]
369 12:18:02.837690
370 12:18:02.838486
371 12:18:02.838942 F0: 102B 0000
372 12:18:02.839346
373 12:18:02.839718 F3: 1001 0000 [0200]
374 12:18:02.841281
375 12:18:02.841729 F3: 1001 0000
376 12:18:02.842096
377 12:18:02.842413 F7: 102D 0000
378 12:18:02.842780
379 12:18:02.843098 F1: 0000 0000
380 12:18:02.843416
381 12:18:02.845342 V0: 0000 0000 [0001]
382 12:18:02.845861
383 12:18:02.846211 00: 0007 8000
384 12:18:02.846553
385 12:18:02.848705 01: 0000 0000
386 12:18:02.849200
387 12:18:02.849561 BP: 0C00 0209 [0000]
388 12:18:02.849883
389 12:18:02.852751 G0: 1182 0000
390 12:18:02.853244
391 12:18:02.853603 EC: 0000 0021 [4000]
392 12:18:02.853920
393 12:18:02.856458 S7: 0000 0000 [0000]
394 12:18:02.856932
395 12:18:02.857271 CC: 0000 0000 [0001]
396 12:18:02.857589
397 12:18:02.859814 T0: 0000 0040 [010F]
398 12:18:02.860380
399 12:18:02.860730 Jump to BL
400 12:18:02.861050
401 12:18:02.884454
402 12:18:02.884982
403 12:18:02.885326
404 12:18:02.891878 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:18:02.896006 ARM64: Exception handlers installed.
406 12:18:02.899430 ARM64: Testing exception
407 12:18:02.903667 ARM64: Done test exception
408 12:18:02.910921 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:18:02.917643 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:18:02.924826 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:18:02.935290 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:18:02.941830 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:18:02.952033 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:18:02.963000 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:18:02.969513 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:18:02.987627 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:18:02.990490 WDT: Last reset was cold boot
418 12:18:02.994035 SPI1(PAD0) initialized at 2873684 Hz
419 12:18:02.997510 SPI5(PAD0) initialized at 992727 Hz
420 12:18:03.001499 VBOOT: Loading verstage.
421 12:18:03.007792 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:18:03.011029 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:18:03.014060 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:18:03.017537 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:18:03.025096 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:18:03.031339 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:18:03.042191 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:18:03.042769
429 12:18:03.043146
430 12:18:03.052289 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:18:03.056025 ARM64: Exception handlers installed.
432 12:18:03.058852 ARM64: Testing exception
433 12:18:03.059289 ARM64: Done test exception
434 12:18:03.065607 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:18:03.069339 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:18:03.083460 Probing TPM: . done!
437 12:18:03.086649 TPM ready after 0 ms
438 12:18:03.090183 Connected to device vid:did:rid of 1ae0:0028:00
439 12:18:03.097497 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 12:18:03.155956 Initialized TPM device CR50 revision 0
441 12:18:03.166633 tlcl_send_startup: Startup return code is 0
442 12:18:03.167263 TPM: setup succeeded
443 12:18:03.177964 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:18:03.187206 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:18:03.199438 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:18:03.207857 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:18:03.211788 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:18:03.218758 in-header: 03 07 00 00 08 00 00 00
449 12:18:03.222418 in-data: aa e4 47 04 13 02 00 00
450 12:18:03.226247 Chrome EC: UHEPI supported
451 12:18:03.233618 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:18:03.237233 in-header: 03 ad 00 00 08 00 00 00
453 12:18:03.240746 in-data: 00 20 20 08 00 00 00 00
454 12:18:03.241176 Phase 1
455 12:18:03.244562 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:18:03.251996 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:18:03.255447 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:18:03.259771 Recovery requested (1009000e)
459 12:18:03.267703 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:18:03.273051 tlcl_extend: response is 0
461 12:18:03.282878 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:18:03.287810 tlcl_extend: response is 0
463 12:18:03.294685 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:18:03.314816 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 12:18:03.321688 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:18:03.322152
467 12:18:03.322508
468 12:18:03.332056 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:18:03.336259 ARM64: Exception handlers installed.
470 12:18:03.336699 ARM64: Testing exception
471 12:18:03.339340 ARM64: Done test exception
472 12:18:03.360211 pmic_efuse_setting: Set efuses in 11 msecs
473 12:18:03.364581 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:18:03.370915 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:18:03.374597 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:18:03.377683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:18:03.385079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:18:03.389190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:18:03.392455 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:18:03.400083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:18:03.403613 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:18:03.407533 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:18:03.411630 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:18:03.418553 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:18:03.422538 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:18:03.426793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:18:03.434659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:18:03.438072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:18:03.445410 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:18:03.449589 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:18:03.457177 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:18:03.460732 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:18:03.468454 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:18:03.472263 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:18:03.479623 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:18:03.483339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:18:03.487213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:18:03.494446 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:18:03.501682 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:18:03.505723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:18:03.509334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:18:03.513049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:18:03.520041 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:18:03.524395 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:18:03.531212 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:18:03.534967 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:18:03.538971 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:18:03.545405 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:18:03.549721 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:18:03.553169 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:18:03.561267 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:18:03.564884 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:18:03.568496 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:18:03.572629 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:18:03.576362 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:18:03.579723 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:18:03.587106 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:18:03.591353 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:18:03.594798 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:18:03.598928 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:18:03.602521 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:18:03.605725 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:18:03.609286 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:18:03.616404 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:18:03.624359 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:18:03.631900 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:18:03.636094 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:18:03.643128 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:18:03.654200 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:18:03.658060 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:18:03.661554 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:18:03.665163 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:18:03.672880 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x2a
534 12:18:03.677045 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:18:03.685404 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:18:03.689019 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:18:03.698016 [RTC]rtc_get_frequency_meter,154: input=15, output=792
538 12:18:03.701973 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 12:18:03.705515 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 12:18:03.708953 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 12:18:03.716487 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 12:18:03.720797 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 12:18:03.721343 ADC[4]: Raw value=901697 ID=7
544 12:18:03.724961 ADC[3]: Raw value=213336 ID=1
545 12:18:03.725407 RAM Code: 0x71
546 12:18:03.732260 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 12:18:03.735708 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 12:18:03.742904 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 12:18:03.750676 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 12:18:03.754386 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 12:18:03.758078 in-header: 03 07 00 00 08 00 00 00
552 12:18:03.761641 in-data: aa e4 47 04 13 02 00 00
553 12:18:03.762090 Chrome EC: UHEPI supported
554 12:18:03.769370 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 12:18:03.772927 in-header: 03 ed 00 00 08 00 00 00
556 12:18:03.776691 in-data: 80 20 60 08 00 00 00 00
557 12:18:03.780485 MRC: failed to locate region type 0.
558 12:18:03.788271 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 12:18:03.788733 DRAM-K: Running full calibration
560 12:18:03.794987 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 12:18:03.798641 header.status = 0x0
562 12:18:03.802338 header.version = 0x6 (expected: 0x6)
563 12:18:03.805729 header.size = 0xd00 (expected: 0xd00)
564 12:18:03.806158 header.flags = 0x0
565 12:18:03.813456 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 12:18:03.830349 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
567 12:18:03.837549 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 12:18:03.837989 dram_init: ddr_geometry: 2
569 12:18:03.841773 [EMI] MDL number = 2
570 12:18:03.845050 [EMI] Get MDL freq = 0
571 12:18:03.845480 dram_init: ddr_type: 0
572 12:18:03.848870 is_discrete_lpddr4: 1
573 12:18:03.849298 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 12:18:03.853147
575 12:18:03.853598
576 12:18:03.853936 [Bian_co] ETT version 0.0.0.1
577 12:18:03.860199 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 12:18:03.860633
579 12:18:03.863842 dramc_set_vcore_voltage set vcore to 650000
580 12:18:03.864274 Read voltage for 800, 4
581 12:18:03.864650 Vio18 = 0
582 12:18:03.867696 Vcore = 650000
583 12:18:03.868126 Vdram = 0
584 12:18:03.868465 Vddq = 0
585 12:18:03.871219 Vmddr = 0
586 12:18:03.871649 dram_init: config_dvfs: 1
587 12:18:03.879093 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 12:18:03.882601 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 12:18:03.886192 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
590 12:18:03.890060 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
591 12:18:03.893662 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
592 12:18:03.897827 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
593 12:18:03.901670 MEM_TYPE=3, freq_sel=18
594 12:18:03.902099 sv_algorithm_assistance_LP4_1600
595 12:18:03.908507 ============ PULL DRAM RESETB DOWN ============
596 12:18:03.912587 ========== PULL DRAM RESETB DOWN end =========
597 12:18:03.915810 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 12:18:03.919193 ===================================
599 12:18:03.923167 LPDDR4 DRAM CONFIGURATION
600 12:18:03.923612 ===================================
601 12:18:03.927453 EX_ROW_EN[0] = 0x0
602 12:18:03.927900 EX_ROW_EN[1] = 0x0
603 12:18:03.930498 LP4Y_EN = 0x0
604 12:18:03.930997 WORK_FSP = 0x0
605 12:18:03.934365 WL = 0x2
606 12:18:03.934854 RL = 0x2
607 12:18:03.938063 BL = 0x2
608 12:18:03.938509 RPST = 0x0
609 12:18:03.941785 RD_PRE = 0x0
610 12:18:03.942227 WR_PRE = 0x1
611 12:18:03.945429 WR_PST = 0x0
612 12:18:03.945869 DBI_WR = 0x0
613 12:18:03.948756 DBI_RD = 0x0
614 12:18:03.949303 OTF = 0x1
615 12:18:03.951851 ===================================
616 12:18:03.955382 ===================================
617 12:18:03.958569 ANA top config
618 12:18:03.962050 ===================================
619 12:18:03.962481 DLL_ASYNC_EN = 0
620 12:18:03.965162 ALL_SLAVE_EN = 1
621 12:18:03.968743 NEW_RANK_MODE = 1
622 12:18:03.972013 DLL_IDLE_MODE = 1
623 12:18:03.972444 LP45_APHY_COMB_EN = 1
624 12:18:03.975185 TX_ODT_DIS = 1
625 12:18:03.978837 NEW_8X_MODE = 1
626 12:18:03.982419 ===================================
627 12:18:03.985738 ===================================
628 12:18:03.989061 data_rate = 1600
629 12:18:03.991927 CKR = 1
630 12:18:03.992360 DQ_P2S_RATIO = 8
631 12:18:03.995471 ===================================
632 12:18:03.999012 CA_P2S_RATIO = 8
633 12:18:04.001907 DQ_CA_OPEN = 0
634 12:18:04.005833 DQ_SEMI_OPEN = 0
635 12:18:04.008963 CA_SEMI_OPEN = 0
636 12:18:04.012527 CA_FULL_RATE = 0
637 12:18:04.012956 DQ_CKDIV4_EN = 1
638 12:18:04.015567 CA_CKDIV4_EN = 1
639 12:18:04.019301 CA_PREDIV_EN = 0
640 12:18:04.022272 PH8_DLY = 0
641 12:18:04.025436 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 12:18:04.025995 DQ_AAMCK_DIV = 4
643 12:18:04.028855 CA_AAMCK_DIV = 4
644 12:18:04.032655 CA_ADMCK_DIV = 4
645 12:18:04.035393 DQ_TRACK_CA_EN = 0
646 12:18:04.039388 CA_PICK = 800
647 12:18:04.042621 CA_MCKIO = 800
648 12:18:04.043075 MCKIO_SEMI = 0
649 12:18:04.046277 PLL_FREQ = 3068
650 12:18:04.049677 DQ_UI_PI_RATIO = 32
651 12:18:04.052410 CA_UI_PI_RATIO = 0
652 12:18:04.055855 ===================================
653 12:18:04.059305 ===================================
654 12:18:04.062461 memory_type:LPDDR4
655 12:18:04.062928 GP_NUM : 10
656 12:18:04.066230 SRAM_EN : 1
657 12:18:04.069384 MD32_EN : 0
658 12:18:04.072852 ===================================
659 12:18:04.073285 [ANA_INIT] >>>>>>>>>>>>>>
660 12:18:04.076410 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 12:18:04.079608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 12:18:04.082675 ===================================
663 12:18:04.086310 data_rate = 1600,PCW = 0X7600
664 12:18:04.089432 ===================================
665 12:18:04.092656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:18:04.099454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 12:18:04.103249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 12:18:04.110126 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 12:18:04.110574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 12:18:04.113636 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 12:18:04.117487 [ANA_INIT] flow start
672 12:18:04.120946 [ANA_INIT] PLL >>>>>>>>
673 12:18:04.121378 [ANA_INIT] PLL <<<<<<<<
674 12:18:04.124724 [ANA_INIT] MIDPI >>>>>>>>
675 12:18:04.125155 [ANA_INIT] MIDPI <<<<<<<<
676 12:18:04.128340 [ANA_INIT] DLL >>>>>>>>
677 12:18:04.132525 [ANA_INIT] flow end
678 12:18:04.136188 ============ LP4 DIFF to SE enter ============
679 12:18:04.140052 ============ LP4 DIFF to SE exit ============
680 12:18:04.140485 [ANA_INIT] <<<<<<<<<<<<<
681 12:18:04.144416 [Flow] Enable top DCM control >>>>>
682 12:18:04.147644 [Flow] Enable top DCM control <<<<<
683 12:18:04.150555 Enable DLL master slave shuffle
684 12:18:04.157209 ==============================================================
685 12:18:04.157661 Gating Mode config
686 12:18:04.164390 ==============================================================
687 12:18:04.164848 Config description:
688 12:18:04.174075 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 12:18:04.180767 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 12:18:04.187487 SELPH_MODE 0: By rank 1: By Phase
691 12:18:04.191312 ==============================================================
692 12:18:04.194131 GAT_TRACK_EN = 1
693 12:18:04.197941 RX_GATING_MODE = 2
694 12:18:04.201179 RX_GATING_TRACK_MODE = 2
695 12:18:04.204785 SELPH_MODE = 1
696 12:18:04.208108 PICG_EARLY_EN = 1
697 12:18:04.211007 VALID_LAT_VALUE = 1
698 12:18:04.214536 ==============================================================
699 12:18:04.218222 Enter into Gating configuration >>>>
700 12:18:04.221631 Exit from Gating configuration <<<<
701 12:18:04.224817 Enter into DVFS_PRE_config >>>>>
702 12:18:04.238168 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 12:18:04.238639 Exit from DVFS_PRE_config <<<<<
704 12:18:04.241645 Enter into PICG configuration >>>>
705 12:18:04.244872 Exit from PICG configuration <<<<
706 12:18:04.248003 [RX_INPUT] configuration >>>>>
707 12:18:04.251881 [RX_INPUT] configuration <<<<<
708 12:18:04.258443 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 12:18:04.261665 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 12:18:04.268287 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 12:18:04.275186 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 12:18:04.282198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 12:18:04.285338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 12:18:04.292037 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 12:18:04.294952 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 12:18:04.298566 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 12:18:04.301743 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 12:18:04.309008 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 12:18:04.312063 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 12:18:04.315719 ===================================
721 12:18:04.318626 LPDDR4 DRAM CONFIGURATION
722 12:18:04.321846 ===================================
723 12:18:04.322289 EX_ROW_EN[0] = 0x0
724 12:18:04.325598 EX_ROW_EN[1] = 0x0
725 12:18:04.326230 LP4Y_EN = 0x0
726 12:18:04.329282 WORK_FSP = 0x0
727 12:18:04.329835 WL = 0x2
728 12:18:04.333130 RL = 0x2
729 12:18:04.333577 BL = 0x2
730 12:18:04.336356 RPST = 0x0
731 12:18:04.336820 RD_PRE = 0x0
732 12:18:04.339613 WR_PRE = 0x1
733 12:18:04.340039 WR_PST = 0x0
734 12:18:04.343115 DBI_WR = 0x0
735 12:18:04.343544 DBI_RD = 0x0
736 12:18:04.346521 OTF = 0x1
737 12:18:04.349463 ===================================
738 12:18:04.353081 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 12:18:04.356546 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 12:18:04.359507 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 12:18:04.363127 ===================================
742 12:18:04.366790 LPDDR4 DRAM CONFIGURATION
743 12:18:04.370088 ===================================
744 12:18:04.372976 EX_ROW_EN[0] = 0x10
745 12:18:04.373455 EX_ROW_EN[1] = 0x0
746 12:18:04.376264 LP4Y_EN = 0x0
747 12:18:04.376695 WORK_FSP = 0x0
748 12:18:04.379906 WL = 0x2
749 12:18:04.380335 RL = 0x2
750 12:18:04.383108 BL = 0x2
751 12:18:04.383543 RPST = 0x0
752 12:18:04.386549 RD_PRE = 0x0
753 12:18:04.387018 WR_PRE = 0x1
754 12:18:04.390151 WR_PST = 0x0
755 12:18:04.390580 DBI_WR = 0x0
756 12:18:04.393251 DBI_RD = 0x0
757 12:18:04.393681 OTF = 0x1
758 12:18:04.397070 ===================================
759 12:18:04.403162 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 12:18:04.408040 nWR fixed to 40
761 12:18:04.411721 [ModeRegInit_LP4] CH0 RK0
762 12:18:04.412299 [ModeRegInit_LP4] CH0 RK1
763 12:18:04.414571 [ModeRegInit_LP4] CH1 RK0
764 12:18:04.418093 [ModeRegInit_LP4] CH1 RK1
765 12:18:04.418557 match AC timing 13
766 12:18:04.424824 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 12:18:04.428178 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 12:18:04.431412 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 12:18:04.438221 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 12:18:04.442142 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 12:18:04.442633 [EMI DOE] emi_dcm 0
772 12:18:04.448775 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 12:18:04.449203 ==
774 12:18:04.451837 Dram Type= 6, Freq= 0, CH_0, rank 0
775 12:18:04.455455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 12:18:04.455913 ==
777 12:18:04.461662 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 12:18:04.465549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 12:18:04.475595 [CA 0] Center 37 (7~68) winsize 62
780 12:18:04.478686 [CA 1] Center 37 (6~68) winsize 63
781 12:18:04.482251 [CA 2] Center 35 (5~66) winsize 62
782 12:18:04.485390 [CA 3] Center 34 (4~65) winsize 62
783 12:18:04.489348 [CA 4] Center 34 (4~65) winsize 62
784 12:18:04.492516 [CA 5] Center 33 (3~64) winsize 62
785 12:18:04.492710
786 12:18:04.496027 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 12:18:04.496211
788 12:18:04.499145 [CATrainingPosCal] consider 1 rank data
789 12:18:04.502108 u2DelayCellTimex100 = 270/100 ps
790 12:18:04.505783 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
791 12:18:04.508730 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
792 12:18:04.512302 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
793 12:18:04.515926 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
794 12:18:04.522713 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
795 12:18:04.525674 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
796 12:18:04.525759
797 12:18:04.528902 CA PerBit enable=1, Macro0, CA PI delay=33
798 12:18:04.528986
799 12:18:04.532481 [CBTSetCACLKResult] CA Dly = 33
800 12:18:04.532564 CS Dly: 5 (0~36)
801 12:18:04.532629 ==
802 12:18:04.536019 Dram Type= 6, Freq= 0, CH_0, rank 1
803 12:18:04.539423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 12:18:04.542892 ==
805 12:18:04.546338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 12:18:04.552584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 12:18:04.561848 [CA 0] Center 37 (6~68) winsize 63
808 12:18:04.564708 [CA 1] Center 37 (7~68) winsize 62
809 12:18:04.568468 [CA 2] Center 35 (5~66) winsize 62
810 12:18:04.571230 [CA 3] Center 34 (4~65) winsize 62
811 12:18:04.575026 [CA 4] Center 34 (3~65) winsize 63
812 12:18:04.578068 [CA 5] Center 33 (3~64) winsize 62
813 12:18:04.578151
814 12:18:04.581427 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 12:18:04.581537
816 12:18:04.585064 [CATrainingPosCal] consider 2 rank data
817 12:18:04.588135 u2DelayCellTimex100 = 270/100 ps
818 12:18:04.591715 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
819 12:18:04.595314 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
820 12:18:04.598465 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
821 12:18:04.604881 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
822 12:18:04.608621 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
823 12:18:04.611598 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
824 12:18:04.611722
825 12:18:04.615502 CA PerBit enable=1, Macro0, CA PI delay=33
826 12:18:04.615758
827 12:18:04.618598 [CBTSetCACLKResult] CA Dly = 33
828 12:18:04.618808 CS Dly: 6 (0~38)
829 12:18:04.618933
830 12:18:04.622182 ----->DramcWriteLeveling(PI) begin...
831 12:18:04.622511 ==
832 12:18:04.625595 Dram Type= 6, Freq= 0, CH_0, rank 0
833 12:18:04.632283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 12:18:04.632527 ==
835 12:18:04.635202 Write leveling (Byte 0): 29 => 29
836 12:18:04.638964 Write leveling (Byte 1): 30 => 30
837 12:18:04.639279 DramcWriteLeveling(PI) end<-----
838 12:18:04.639524
839 12:18:04.642308 ==
840 12:18:04.642696 Dram Type= 6, Freq= 0, CH_0, rank 0
841 12:18:04.649086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 12:18:04.649614 ==
843 12:18:04.652438 [Gating] SW mode calibration
844 12:18:04.659023 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 12:18:04.662503 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 12:18:04.669135 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 12:18:04.672670 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 12:18:04.676012 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 12:18:04.679426 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 12:18:04.685863 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:18:04.689329 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:18:04.692977 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:18:04.700278 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:18:04.704403 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:18:04.707745 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:18:04.711282 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:18:04.714777 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:18:04.720801 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:18:04.724213 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:18:04.727970 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:18:04.734764 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:18:04.737738 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:18:04.741441 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 12:18:04.748214 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
865 12:18:04.751791 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
866 12:18:04.754703 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:18:04.761719 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:18:04.764923 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:18:04.768343 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:18:04.771941 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:18:04.778484 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:18:04.782181 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:18:04.784815 0 9 12 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (1 1)
874 12:18:04.791765 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 12:18:04.795087 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 12:18:04.798556 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 12:18:04.805438 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 12:18:04.808847 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:18:04.811875 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:18:04.818630 0 10 8 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 0)
881 12:18:04.822237 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
882 12:18:04.825403 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 12:18:04.828872 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 12:18:04.835931 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 12:18:04.839343 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 12:18:04.842402 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:18:04.849010 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:18:04.852825 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
889 12:18:04.855775 0 11 12 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
890 12:18:04.862558 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 12:18:04.866194 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 12:18:04.869315 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 12:18:04.872919 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 12:18:04.879707 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:18:04.882652 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 12:18:04.886527 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
897 12:18:04.892848 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 12:18:04.896305 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:18:04.899820 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:18:04.906579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:18:04.909609 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:18:04.913140 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:18:04.916263 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:18:04.923035 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:18:04.926387 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:18:04.929875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:18:04.936884 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:18:04.940405 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:18:04.943352 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:18:04.950150 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:18:04.953907 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:18:04.956788 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
913 12:18:04.963282 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
914 12:18:04.963859 Total UI for P1: 0, mck2ui 16
915 12:18:04.970656 best dqsien dly found for B0: ( 0, 14, 8)
916 12:18:04.971184 Total UI for P1: 0, mck2ui 16
917 12:18:04.973934 best dqsien dly found for B1: ( 0, 14, 8)
918 12:18:04.976685 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
919 12:18:04.983133 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
920 12:18:04.983556
921 12:18:04.986853 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
922 12:18:04.990504 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 12:18:04.993587 [Gating] SW calibration Done
924 12:18:04.994006 ==
925 12:18:04.996715 Dram Type= 6, Freq= 0, CH_0, rank 0
926 12:18:05.000230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 12:18:05.000683 ==
928 12:18:05.001018 RX Vref Scan: 0
929 12:18:05.001327
930 12:18:05.003400 RX Vref 0 -> 0, step: 1
931 12:18:05.003872
932 12:18:05.007132 RX Delay -130 -> 252, step: 16
933 12:18:05.010639 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
934 12:18:05.014160 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
935 12:18:05.020477 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
936 12:18:05.023455 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
937 12:18:05.027210 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
938 12:18:05.030590 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
939 12:18:05.034215 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
940 12:18:05.037541 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
941 12:18:05.044163 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
942 12:18:05.047200 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
943 12:18:05.050579 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
944 12:18:05.054242 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
945 12:18:05.057249 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
946 12:18:05.064162 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
947 12:18:05.067420 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
948 12:18:05.070582 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
949 12:18:05.071081 ==
950 12:18:05.074132 Dram Type= 6, Freq= 0, CH_0, rank 0
951 12:18:05.077875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 12:18:05.078305 ==
953 12:18:05.081270 DQS Delay:
954 12:18:05.081833 DQS0 = 0, DQS1 = 0
955 12:18:05.084230 DQM Delay:
956 12:18:05.084731 DQM0 = 84, DQM1 = 77
957 12:18:05.085233 DQ Delay:
958 12:18:05.087473 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
959 12:18:05.090656 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
960 12:18:05.094468 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
961 12:18:05.097506 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
962 12:18:05.097978
963 12:18:05.098691
964 12:18:05.099157 ==
965 12:18:05.101105 Dram Type= 6, Freq= 0, CH_0, rank 0
966 12:18:05.107794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 12:18:05.108316 ==
968 12:18:05.108679
969 12:18:05.108989
970 12:18:05.109283 TX Vref Scan disable
971 12:18:05.111172 == TX Byte 0 ==
972 12:18:05.114500 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
973 12:18:05.118433 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
974 12:18:05.121590 == TX Byte 1 ==
975 12:18:05.125098 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
976 12:18:05.128624 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
977 12:18:05.131812 ==
978 12:18:05.132276 Dram Type= 6, Freq= 0, CH_0, rank 0
979 12:18:05.138271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 12:18:05.138781 ==
981 12:18:05.150692 TX Vref=22, minBit 0, minWin=27, winSum=437
982 12:18:05.153790 TX Vref=24, minBit 0, minWin=27, winSum=441
983 12:18:05.157057 TX Vref=26, minBit 7, minWin=27, winSum=447
984 12:18:05.160329 TX Vref=28, minBit 0, minWin=28, winSum=453
985 12:18:05.164041 TX Vref=30, minBit 2, minWin=28, winSum=453
986 12:18:05.167070 TX Vref=32, minBit 3, minWin=27, winSum=451
987 12:18:05.173541 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 28
988 12:18:05.173988
989 12:18:05.177336 Final TX Range 1 Vref 28
990 12:18:05.177781
991 12:18:05.178154 ==
992 12:18:05.181041 Dram Type= 6, Freq= 0, CH_0, rank 0
993 12:18:05.183954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 12:18:05.184400 ==
995 12:18:05.184762
996 12:18:05.185083
997 12:18:05.187379 TX Vref Scan disable
998 12:18:05.190661 == TX Byte 0 ==
999 12:18:05.194072 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1000 12:18:05.197425 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1001 12:18:05.200681 == TX Byte 1 ==
1002 12:18:05.204267 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1003 12:18:05.207301 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1004 12:18:05.207721
1005 12:18:05.210846 [DATLAT]
1006 12:18:05.211321 Freq=800, CH0 RK0
1007 12:18:05.211800
1008 12:18:05.213910 DATLAT Default: 0xa
1009 12:18:05.214360 0, 0xFFFF, sum = 0
1010 12:18:05.217422 1, 0xFFFF, sum = 0
1011 12:18:05.217874 2, 0xFFFF, sum = 0
1012 12:18:05.220780 3, 0xFFFF, sum = 0
1013 12:18:05.221249 4, 0xFFFF, sum = 0
1014 12:18:05.224088 5, 0xFFFF, sum = 0
1015 12:18:05.224512 6, 0xFFFF, sum = 0
1016 12:18:05.227709 7, 0xFFFF, sum = 0
1017 12:18:05.228152 8, 0xFFFF, sum = 0
1018 12:18:05.231246 9, 0x0, sum = 1
1019 12:18:05.231670 10, 0x0, sum = 2
1020 12:18:05.234288 11, 0x0, sum = 3
1021 12:18:05.234715 12, 0x0, sum = 4
1022 12:18:05.238042 best_step = 10
1023 12:18:05.238459
1024 12:18:05.238844 ==
1025 12:18:05.241137 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 12:18:05.244905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 12:18:05.245428 ==
1028 12:18:05.245891 RX Vref Scan: 1
1029 12:18:05.246337
1030 12:18:05.247930 Set Vref Range= 32 -> 127
1031 12:18:05.248344
1032 12:18:05.251712 RX Vref 32 -> 127, step: 1
1033 12:18:05.252122
1034 12:18:05.255031 RX Delay -95 -> 252, step: 8
1035 12:18:05.255443
1036 12:18:05.258260 Set Vref, RX VrefLevel [Byte0]: 32
1037 12:18:05.261281 [Byte1]: 32
1038 12:18:05.261693
1039 12:18:05.264886 Set Vref, RX VrefLevel [Byte0]: 33
1040 12:18:05.268148 [Byte1]: 33
1041 12:18:05.268574
1042 12:18:05.271700 Set Vref, RX VrefLevel [Byte0]: 34
1043 12:18:05.274846 [Byte1]: 34
1044 12:18:05.278606
1045 12:18:05.279061 Set Vref, RX VrefLevel [Byte0]: 35
1046 12:18:05.281494 [Byte1]: 35
1047 12:18:05.286011
1048 12:18:05.286524 Set Vref, RX VrefLevel [Byte0]: 36
1049 12:18:05.289607 [Byte1]: 36
1050 12:18:05.293500
1051 12:18:05.293918 Set Vref, RX VrefLevel [Byte0]: 37
1052 12:18:05.297191 [Byte1]: 37
1053 12:18:05.300972
1054 12:18:05.301474 Set Vref, RX VrefLevel [Byte0]: 38
1055 12:18:05.304336 [Byte1]: 38
1056 12:18:05.308623
1057 12:18:05.309034 Set Vref, RX VrefLevel [Byte0]: 39
1058 12:18:05.312229 [Byte1]: 39
1059 12:18:05.316590
1060 12:18:05.317116 Set Vref, RX VrefLevel [Byte0]: 40
1061 12:18:05.320086 [Byte1]: 40
1062 12:18:05.324340
1063 12:18:05.324756 Set Vref, RX VrefLevel [Byte0]: 41
1064 12:18:05.327157 [Byte1]: 41
1065 12:18:05.331912
1066 12:18:05.332395 Set Vref, RX VrefLevel [Byte0]: 42
1067 12:18:05.335761 [Byte1]: 42
1068 12:18:05.339314
1069 12:18:05.339725 Set Vref, RX VrefLevel [Byte0]: 43
1070 12:18:05.342351 [Byte1]: 43
1071 12:18:05.346642
1072 12:18:05.347128 Set Vref, RX VrefLevel [Byte0]: 44
1073 12:18:05.350164 [Byte1]: 44
1074 12:18:05.354441
1075 12:18:05.354957 Set Vref, RX VrefLevel [Byte0]: 45
1076 12:18:05.358063 [Byte1]: 45
1077 12:18:05.362145
1078 12:18:05.362601 Set Vref, RX VrefLevel [Byte0]: 46
1079 12:18:05.365317 [Byte1]: 46
1080 12:18:05.369577
1081 12:18:05.370082 Set Vref, RX VrefLevel [Byte0]: 47
1082 12:18:05.372643 [Byte1]: 47
1083 12:18:05.377552
1084 12:18:05.378114 Set Vref, RX VrefLevel [Byte0]: 48
1085 12:18:05.380592 [Byte1]: 48
1086 12:18:05.384747
1087 12:18:05.385168 Set Vref, RX VrefLevel [Byte0]: 49
1088 12:18:05.387808 [Byte1]: 49
1089 12:18:05.391996
1090 12:18:05.395675 Set Vref, RX VrefLevel [Byte0]: 50
1091 12:18:05.396244 [Byte1]: 50
1092 12:18:05.399820
1093 12:18:05.400255 Set Vref, RX VrefLevel [Byte0]: 51
1094 12:18:05.402912 [Byte1]: 51
1095 12:18:05.407591
1096 12:18:05.408045 Set Vref, RX VrefLevel [Byte0]: 52
1097 12:18:05.411047 [Byte1]: 52
1098 12:18:05.415270
1099 12:18:05.415708 Set Vref, RX VrefLevel [Byte0]: 53
1100 12:18:05.418219 [Byte1]: 53
1101 12:18:05.422619
1102 12:18:05.423110 Set Vref, RX VrefLevel [Byte0]: 54
1103 12:18:05.425739 [Byte1]: 54
1104 12:18:05.430770
1105 12:18:05.431220 Set Vref, RX VrefLevel [Byte0]: 55
1106 12:18:05.433389 [Byte1]: 55
1107 12:18:05.437957
1108 12:18:05.438549 Set Vref, RX VrefLevel [Byte0]: 56
1109 12:18:05.440891 [Byte1]: 56
1110 12:18:05.445181
1111 12:18:05.445592 Set Vref, RX VrefLevel [Byte0]: 57
1112 12:18:05.448740 [Byte1]: 57
1113 12:18:05.453029
1114 12:18:05.453500 Set Vref, RX VrefLevel [Byte0]: 58
1115 12:18:05.456196 [Byte1]: 58
1116 12:18:05.460345
1117 12:18:05.460758 Set Vref, RX VrefLevel [Byte0]: 59
1118 12:18:05.463918 [Byte1]: 59
1119 12:18:05.468081
1120 12:18:05.468495 Set Vref, RX VrefLevel [Byte0]: 60
1121 12:18:05.471457 [Byte1]: 60
1122 12:18:05.475488
1123 12:18:05.475898 Set Vref, RX VrefLevel [Byte0]: 61
1124 12:18:05.478997 [Byte1]: 61
1125 12:18:05.483074
1126 12:18:05.483512 Set Vref, RX VrefLevel [Byte0]: 62
1127 12:18:05.486597 [Byte1]: 62
1128 12:18:05.490975
1129 12:18:05.491426 Set Vref, RX VrefLevel [Byte0]: 63
1130 12:18:05.494190 [Byte1]: 63
1131 12:18:05.498507
1132 12:18:05.499042 Set Vref, RX VrefLevel [Byte0]: 64
1133 12:18:05.502070 [Byte1]: 64
1134 12:18:05.506168
1135 12:18:05.506589 Set Vref, RX VrefLevel [Byte0]: 65
1136 12:18:05.509640 [Byte1]: 65
1137 12:18:05.513807
1138 12:18:05.514241 Set Vref, RX VrefLevel [Byte0]: 66
1139 12:18:05.516624 [Byte1]: 66
1140 12:18:05.521507
1141 12:18:05.521951 Set Vref, RX VrefLevel [Byte0]: 67
1142 12:18:05.524872 [Byte1]: 67
1143 12:18:05.528820
1144 12:18:05.529266 Set Vref, RX VrefLevel [Byte0]: 68
1145 12:18:05.532510 [Byte1]: 68
1146 12:18:05.537009
1147 12:18:05.537444 Set Vref, RX VrefLevel [Byte0]: 69
1148 12:18:05.539666 [Byte1]: 69
1149 12:18:05.544153
1150 12:18:05.544598 Set Vref, RX VrefLevel [Byte0]: 70
1151 12:18:05.547233 [Byte1]: 70
1152 12:18:05.551423
1153 12:18:05.551869 Set Vref, RX VrefLevel [Byte0]: 71
1154 12:18:05.555186 [Byte1]: 71
1155 12:18:05.559352
1156 12:18:05.559879 Set Vref, RX VrefLevel [Byte0]: 72
1157 12:18:05.562683 [Byte1]: 72
1158 12:18:05.566946
1159 12:18:05.567399 Set Vref, RX VrefLevel [Byte0]: 73
1160 12:18:05.570025 [Byte1]: 73
1161 12:18:05.574384
1162 12:18:05.574861 Set Vref, RX VrefLevel [Byte0]: 74
1163 12:18:05.577981 [Byte1]: 74
1164 12:18:05.582397
1165 12:18:05.582874 Set Vref, RX VrefLevel [Byte0]: 75
1166 12:18:05.585249 [Byte1]: 75
1167 12:18:05.589602
1168 12:18:05.590057 Set Vref, RX VrefLevel [Byte0]: 76
1169 12:18:05.592983 [Byte1]: 76
1170 12:18:05.597447
1171 12:18:05.597968 Set Vref, RX VrefLevel [Byte0]: 77
1172 12:18:05.600411 [Byte1]: 77
1173 12:18:05.604878
1174 12:18:05.605301 Set Vref, RX VrefLevel [Byte0]: 78
1175 12:18:05.608369 [Byte1]: 78
1176 12:18:05.612445
1177 12:18:05.612879 Final RX Vref Byte 0 = 58 to rank0
1178 12:18:05.616091 Final RX Vref Byte 1 = 57 to rank0
1179 12:18:05.618949 Final RX Vref Byte 0 = 58 to rank1
1180 12:18:05.622633 Final RX Vref Byte 1 = 57 to rank1==
1181 12:18:05.625604 Dram Type= 6, Freq= 0, CH_0, rank 0
1182 12:18:05.629312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 12:18:05.632676 ==
1184 12:18:05.633100 DQS Delay:
1185 12:18:05.633446 DQS0 = 0, DQS1 = 0
1186 12:18:05.635887 DQM Delay:
1187 12:18:05.636336 DQM0 = 87, DQM1 = 79
1188 12:18:05.639511 DQ Delay:
1189 12:18:05.642424 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1190 12:18:05.642907 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1191 12:18:05.645869 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1192 12:18:05.649183 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =88
1193 12:18:05.649710
1194 12:18:05.652633
1195 12:18:05.659545 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps
1196 12:18:05.662846 CH0 RK0: MR19=606, MR18=2B11
1197 12:18:05.669510 CH0_RK0: MR19=0x606, MR18=0x2B11, DQSOSC=398, MR23=63, INC=93, DEC=62
1198 12:18:05.670040
1199 12:18:05.673035 ----->DramcWriteLeveling(PI) begin...
1200 12:18:05.673611 ==
1201 12:18:05.676408 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 12:18:05.679826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 12:18:05.680256 ==
1204 12:18:05.683150 Write leveling (Byte 0): 28 => 28
1205 12:18:05.686682 Write leveling (Byte 1): 27 => 27
1206 12:18:05.689504 DramcWriteLeveling(PI) end<-----
1207 12:18:05.689985
1208 12:18:05.690318 ==
1209 12:18:05.692951 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 12:18:05.696298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 12:18:05.696731 ==
1212 12:18:05.700204 [Gating] SW mode calibration
1213 12:18:05.706837 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1214 12:18:05.709848 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1215 12:18:05.716719 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1216 12:18:05.720122 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1217 12:18:05.723344 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:18:05.730265 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:18:05.733095 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:18:05.737054 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:18:05.743613 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:18:05.746687 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:18:05.750043 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:18:05.756979 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:18:05.760353 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:18:05.764287 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:18:05.766998 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:18:05.814788 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:18:05.815301 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:18:05.815666 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:18:05.815984 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:18:05.816383 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1233 12:18:05.817030 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1234 12:18:05.817357 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:18:05.817678 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:18:05.817967 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:18:05.818301 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:18:05.846582 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:18:05.847292 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:18:05.847641 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:18:05.848293 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
1242 12:18:05.848633 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 12:18:05.848932 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 12:18:05.849223 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 12:18:05.850486 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 12:18:05.853996 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 12:18:05.856986 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 12:18:05.860622 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1249 12:18:05.863972 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
1250 12:18:05.870520 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1251 12:18:05.874034 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 12:18:05.877040 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 12:18:05.883757 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 12:18:05.887239 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 12:18:05.890825 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 12:18:05.897530 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1257 12:18:05.900894 0 11 8 | B1->B0 | 2929 4545 | 1 0 | (0 0) (0 0)
1258 12:18:05.904085 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1259 12:18:05.910821 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 12:18:05.914094 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 12:18:05.917819 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 12:18:05.920888 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 12:18:05.927546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 12:18:05.931137 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 12:18:05.934451 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1266 12:18:05.941843 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:18:05.945360 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:18:05.948800 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:18:05.952900 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:18:05.956440 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:18:05.963081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:18:05.966556 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:18:05.970290 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:18:05.974139 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:18:05.980845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:18:05.984195 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:18:05.987728 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:18:05.994292 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:18:05.997435 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:18:06.000803 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1281 12:18:06.004361 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 12:18:06.007483 Total UI for P1: 0, mck2ui 16
1283 12:18:06.011068 best dqsien dly found for B0: ( 0, 14, 4)
1284 12:18:06.014336 Total UI for P1: 0, mck2ui 16
1285 12:18:06.018214 best dqsien dly found for B1: ( 0, 14, 6)
1286 12:18:06.021328 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1287 12:18:06.024443 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1288 12:18:06.024863
1289 12:18:06.031410 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1290 12:18:06.035032 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1291 12:18:06.035484 [Gating] SW calibration Done
1292 12:18:06.038119 ==
1293 12:18:06.038532 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 12:18:06.044588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 12:18:06.045006 ==
1296 12:18:06.045333 RX Vref Scan: 0
1297 12:18:06.045635
1298 12:18:06.048127 RX Vref 0 -> 0, step: 1
1299 12:18:06.048539
1300 12:18:06.051255 RX Delay -130 -> 252, step: 16
1301 12:18:06.054755 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1302 12:18:06.058313 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1303 12:18:06.061873 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1304 12:18:06.068722 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1305 12:18:06.071397 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1306 12:18:06.074832 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1307 12:18:06.078320 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1308 12:18:06.081752 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1309 12:18:06.085595 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1310 12:18:06.092026 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1311 12:18:06.095141 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1312 12:18:06.098939 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1313 12:18:06.102450 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1314 12:18:06.105096 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1315 12:18:06.112392 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1316 12:18:06.115424 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1317 12:18:06.115847 ==
1318 12:18:06.119008 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 12:18:06.122204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 12:18:06.122707 ==
1321 12:18:06.123117 DQS Delay:
1322 12:18:06.125628 DQS0 = 0, DQS1 = 0
1323 12:18:06.126063 DQM Delay:
1324 12:18:06.129294 DQM0 = 87, DQM1 = 75
1325 12:18:06.129733 DQ Delay:
1326 12:18:06.132425 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1327 12:18:06.135608 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =101
1328 12:18:06.139234 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1329 12:18:06.142059 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1330 12:18:06.142490
1331 12:18:06.142883
1332 12:18:06.143205 ==
1333 12:18:06.145647 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 12:18:06.148903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 12:18:06.152243 ==
1336 12:18:06.152668
1337 12:18:06.153023
1338 12:18:06.153334 TX Vref Scan disable
1339 12:18:06.155924 == TX Byte 0 ==
1340 12:18:06.158553 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1341 12:18:06.161991 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1342 12:18:06.165243 == TX Byte 1 ==
1343 12:18:06.168844 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1344 12:18:06.171994 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1345 12:18:06.172075 ==
1346 12:18:06.175448 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 12:18:06.182057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 12:18:06.182138 ==
1349 12:18:06.194223 TX Vref=22, minBit 3, minWin=27, winSum=441
1350 12:18:06.197800 TX Vref=24, minBit 12, minWin=26, winSum=444
1351 12:18:06.200959 TX Vref=26, minBit 3, minWin=27, winSum=444
1352 12:18:06.204120 TX Vref=28, minBit 8, minWin=27, winSum=451
1353 12:18:06.207780 TX Vref=30, minBit 0, minWin=28, winSum=453
1354 12:18:06.214030 TX Vref=32, minBit 9, minWin=27, winSum=447
1355 12:18:06.217497 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1356 12:18:06.217576
1357 12:18:06.220984 Final TX Range 1 Vref 30
1358 12:18:06.221058
1359 12:18:06.221118 ==
1360 12:18:06.224503 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 12:18:06.227586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 12:18:06.227666 ==
1363 12:18:06.227728
1364 12:18:06.230631
1365 12:18:06.230709 TX Vref Scan disable
1366 12:18:06.234166 == TX Byte 0 ==
1367 12:18:06.237760 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1368 12:18:06.240852 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1369 12:18:06.244548 == TX Byte 1 ==
1370 12:18:06.247730 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1371 12:18:06.251442 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1372 12:18:06.251522
1373 12:18:06.254192 [DATLAT]
1374 12:18:06.254272 Freq=800, CH0 RK1
1375 12:18:06.254335
1376 12:18:06.257911 DATLAT Default: 0xa
1377 12:18:06.257979 0, 0xFFFF, sum = 0
1378 12:18:06.261039 1, 0xFFFF, sum = 0
1379 12:18:06.261110 2, 0xFFFF, sum = 0
1380 12:18:06.264377 3, 0xFFFF, sum = 0
1381 12:18:06.264457 4, 0xFFFF, sum = 0
1382 12:18:06.267740 5, 0xFFFF, sum = 0
1383 12:18:06.267812 6, 0xFFFF, sum = 0
1384 12:18:06.271028 7, 0xFFFF, sum = 0
1385 12:18:06.271097 8, 0xFFFF, sum = 0
1386 12:18:06.274666 9, 0x0, sum = 1
1387 12:18:06.274780 10, 0x0, sum = 2
1388 12:18:06.278296 11, 0x0, sum = 3
1389 12:18:06.278373 12, 0x0, sum = 4
1390 12:18:06.281458 best_step = 10
1391 12:18:06.281528
1392 12:18:06.281587 ==
1393 12:18:06.284708 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 12:18:06.288108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 12:18:06.288189 ==
1396 12:18:06.291743 RX Vref Scan: 0
1397 12:18:06.291823
1398 12:18:06.291885 RX Vref 0 -> 0, step: 1
1399 12:18:06.291943
1400 12:18:06.294554 RX Delay -95 -> 252, step: 8
1401 12:18:06.298176 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1402 12:18:06.304868 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1403 12:18:06.308134 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1404 12:18:06.311702 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1405 12:18:06.314623 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1406 12:18:06.318350 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1407 12:18:06.324759 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1408 12:18:06.328431 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1409 12:18:06.332039 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1410 12:18:06.335043 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1411 12:18:06.338653 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1412 12:18:06.341734 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1413 12:18:06.348874 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1414 12:18:06.352046 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1415 12:18:06.355602 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1416 12:18:06.359135 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1417 12:18:06.359213 ==
1418 12:18:06.362196 Dram Type= 6, Freq= 0, CH_0, rank 1
1419 12:18:06.369177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 12:18:06.369270 ==
1421 12:18:06.369346 DQS Delay:
1422 12:18:06.372114 DQS0 = 0, DQS1 = 0
1423 12:18:06.372228 DQM Delay:
1424 12:18:06.372317 DQM0 = 87, DQM1 = 77
1425 12:18:06.375804 DQ Delay:
1426 12:18:06.378811 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1427 12:18:06.382480 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1428 12:18:06.382616 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1429 12:18:06.388962 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1430 12:18:06.389107
1431 12:18:06.389221
1432 12:18:06.395602 [DQSOSCAuto] RK1, (LSB)MR18= 0x351c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1433 12:18:06.399496 CH0 RK1: MR19=606, MR18=351C
1434 12:18:06.406067 CH0_RK1: MR19=0x606, MR18=0x351C, DQSOSC=396, MR23=63, INC=94, DEC=62
1435 12:18:06.409247 [RxdqsGatingPostProcess] freq 800
1436 12:18:06.412817 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1437 12:18:06.416185 Pre-setting of DQS Precalculation
1438 12:18:06.422758 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1439 12:18:06.423199 ==
1440 12:18:06.426427 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 12:18:06.429699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 12:18:06.430256 ==
1443 12:18:06.432902 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1444 12:18:06.439827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1445 12:18:06.449512 [CA 0] Center 36 (6~66) winsize 61
1446 12:18:06.453130 [CA 1] Center 36 (6~66) winsize 61
1447 12:18:06.456196 [CA 2] Center 34 (4~65) winsize 62
1448 12:18:06.459704 [CA 3] Center 33 (3~64) winsize 62
1449 12:18:06.463274 [CA 4] Center 34 (4~65) winsize 62
1450 12:18:06.466425 [CA 5] Center 33 (3~64) winsize 62
1451 12:18:06.466896
1452 12:18:06.469422 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1453 12:18:06.469979
1454 12:18:06.472943 [CATrainingPosCal] consider 1 rank data
1455 12:18:06.476536 u2DelayCellTimex100 = 270/100 ps
1456 12:18:06.479730 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1457 12:18:06.482793 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1458 12:18:06.486186 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1459 12:18:06.493576 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1460 12:18:06.496441 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 12:18:06.499590 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1462 12:18:06.500183
1463 12:18:06.502908 CA PerBit enable=1, Macro0, CA PI delay=33
1464 12:18:06.503528
1465 12:18:06.506102 [CBTSetCACLKResult] CA Dly = 33
1466 12:18:06.506664 CS Dly: 4 (0~35)
1467 12:18:06.507160 ==
1468 12:18:06.509724 Dram Type= 6, Freq= 0, CH_1, rank 1
1469 12:18:06.516673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 12:18:06.517132 ==
1471 12:18:06.520170 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1472 12:18:06.526660 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1473 12:18:06.535221 [CA 0] Center 36 (6~66) winsize 61
1474 12:18:06.538780 [CA 1] Center 36 (6~66) winsize 61
1475 12:18:06.542545 [CA 2] Center 34 (4~64) winsize 61
1476 12:18:06.545864 [CA 3] Center 33 (3~64) winsize 62
1477 12:18:06.548761 [CA 4] Center 34 (4~65) winsize 62
1478 12:18:06.552368 [CA 5] Center 33 (3~64) winsize 62
1479 12:18:06.552804
1480 12:18:06.556078 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1481 12:18:06.556504
1482 12:18:06.559160 [CATrainingPosCal] consider 2 rank data
1483 12:18:06.562601 u2DelayCellTimex100 = 270/100 ps
1484 12:18:06.566444 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1485 12:18:06.569485 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1486 12:18:06.572407 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1487 12:18:06.576192 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1488 12:18:06.582829 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1489 12:18:06.586121 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1490 12:18:06.586518
1491 12:18:06.589223 CA PerBit enable=1, Macro0, CA PI delay=33
1492 12:18:06.589670
1493 12:18:06.592946 [CBTSetCACLKResult] CA Dly = 33
1494 12:18:06.593367 CS Dly: 5 (0~37)
1495 12:18:06.593781
1496 12:18:06.595826 ----->DramcWriteLeveling(PI) begin...
1497 12:18:06.596245 ==
1498 12:18:06.599708 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 12:18:06.606290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 12:18:06.606719 ==
1501 12:18:06.609857 Write leveling (Byte 0): 27 => 27
1502 12:18:06.610462 Write leveling (Byte 1): 28 => 28
1503 12:18:06.613497 DramcWriteLeveling(PI) end<-----
1504 12:18:06.613934
1505 12:18:06.614347 ==
1506 12:18:06.617032 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 12:18:06.620623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 12:18:06.621090 ==
1509 12:18:06.624835 [Gating] SW mode calibration
1510 12:18:06.632224 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1511 12:18:06.636043 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1512 12:18:06.643148 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1513 12:18:06.647124 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1514 12:18:06.650227 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:18:06.653212 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:18:06.659843 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:18:06.663304 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:18:06.667041 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:18:06.673560 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:18:06.676780 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:18:06.680336 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:18:06.683532 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:18:06.690294 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:18:06.693721 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:18:06.697531 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:18:06.703818 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:18:06.707546 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:18:06.710345 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:18:06.717312 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1530 12:18:06.720974 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1531 12:18:06.724072 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:18:06.730467 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:18:06.733909 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:18:06.737393 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:18:06.741037 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:18:06.747814 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:18:06.751165 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:18:06.754240 0 9 8 | B1->B0 | 2423 2424 | 1 0 | (0 0) (0 0)
1539 12:18:06.761126 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 12:18:06.764403 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1541 12:18:06.767780 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1542 12:18:06.774617 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 12:18:06.777631 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 12:18:06.781311 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 12:18:06.784719 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1546 12:18:06.791702 0 10 8 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 1)
1547 12:18:06.794718 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:18:06.798484 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1549 12:18:06.804976 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 12:18:06.808212 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 12:18:06.811316 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 12:18:06.818676 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 12:18:06.822154 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 12:18:06.824947 0 11 8 | B1->B0 | 3636 3232 | 0 1 | (0 0) (0 0)
1555 12:18:06.831611 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 12:18:06.835460 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 12:18:06.838393 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 12:18:06.845100 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 12:18:06.847989 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 12:18:06.851673 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 12:18:06.855122 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 12:18:06.861937 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1563 12:18:06.865554 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:18:06.868829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:18:06.875115 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:18:06.878707 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:18:06.882101 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:18:06.888710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:18:06.892308 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:18:06.895806 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:18:06.898689 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:18:06.905661 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:18:06.909101 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:18:06.912519 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:18:06.919116 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:18:06.922693 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:18:06.925662 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1578 12:18:06.932508 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 12:18:06.932936 Total UI for P1: 0, mck2ui 16
1580 12:18:06.939228 best dqsien dly found for B0: ( 0, 14, 4)
1581 12:18:06.939745 Total UI for P1: 0, mck2ui 16
1582 12:18:06.945848 best dqsien dly found for B1: ( 0, 14, 6)
1583 12:18:06.949032 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1584 12:18:06.952453 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1585 12:18:06.952941
1586 12:18:06.955797 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1587 12:18:06.959430 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1588 12:18:06.962883 [Gating] SW calibration Done
1589 12:18:06.963437 ==
1590 12:18:06.965770 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 12:18:06.969291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 12:18:06.969732 ==
1593 12:18:06.970095 RX Vref Scan: 0
1594 12:18:06.972766
1595 12:18:06.973190 RX Vref 0 -> 0, step: 1
1596 12:18:06.973545
1597 12:18:06.976174 RX Delay -130 -> 252, step: 16
1598 12:18:06.979938 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1599 12:18:06.982661 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1600 12:18:06.989358 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1601 12:18:06.992989 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1602 12:18:06.996349 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1603 12:18:06.999305 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1604 12:18:07.002978 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1605 12:18:07.006269 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1606 12:18:07.013382 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1607 12:18:07.016679 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1608 12:18:07.020357 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1609 12:18:07.023463 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1610 12:18:07.027076 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1611 12:18:07.033827 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1612 12:18:07.037153 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1613 12:18:07.040351 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1614 12:18:07.040794 ==
1615 12:18:07.043651 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 12:18:07.047086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 12:18:07.047533 ==
1618 12:18:07.050432 DQS Delay:
1619 12:18:07.050971 DQS0 = 0, DQS1 = 0
1620 12:18:07.051329 DQM Delay:
1621 12:18:07.053837 DQM0 = 81, DQM1 = 73
1622 12:18:07.054268 DQ Delay:
1623 12:18:07.057046 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1624 12:18:07.060298 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1625 12:18:07.063241 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1626 12:18:07.066960 DQ12 =85, DQ13 =77, DQ14 =77, DQ15 =77
1627 12:18:07.067042
1628 12:18:07.067106
1629 12:18:07.067164 ==
1630 12:18:07.070371 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 12:18:07.076907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 12:18:07.076990 ==
1633 12:18:07.077054
1634 12:18:07.077113
1635 12:18:07.077169 TX Vref Scan disable
1636 12:18:07.080255 == TX Byte 0 ==
1637 12:18:07.083560 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1638 12:18:07.087064 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1639 12:18:07.090327 == TX Byte 1 ==
1640 12:18:07.093846 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1641 12:18:07.097136 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1642 12:18:07.100604 ==
1643 12:18:07.100685 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 12:18:07.106909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 12:18:07.106992 ==
1646 12:18:07.119459 TX Vref=22, minBit 13, minWin=26, winSum=438
1647 12:18:07.123075 TX Vref=24, minBit 4, minWin=27, winSum=440
1648 12:18:07.126146 TX Vref=26, minBit 11, minWin=27, winSum=450
1649 12:18:07.129874 TX Vref=28, minBit 0, minWin=28, winSum=452
1650 12:18:07.132710 TX Vref=30, minBit 0, minWin=28, winSum=456
1651 12:18:07.136384 TX Vref=32, minBit 1, minWin=28, winSum=456
1652 12:18:07.143042 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1653 12:18:07.143125
1654 12:18:07.145988 Final TX Range 1 Vref 30
1655 12:18:07.146113
1656 12:18:07.146206 ==
1657 12:18:07.149845 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 12:18:07.153123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 12:18:07.153205 ==
1660 12:18:07.153269
1661 12:18:07.153328
1662 12:18:07.156168 TX Vref Scan disable
1663 12:18:07.159991 == TX Byte 0 ==
1664 12:18:07.162934 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1665 12:18:07.166475 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1666 12:18:07.170013 == TX Byte 1 ==
1667 12:18:07.173163 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1668 12:18:07.176540 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1669 12:18:07.176623
1670 12:18:07.179764 [DATLAT]
1671 12:18:07.179873 Freq=800, CH1 RK0
1672 12:18:07.179997
1673 12:18:07.183395 DATLAT Default: 0xa
1674 12:18:07.183493 0, 0xFFFF, sum = 0
1675 12:18:07.186399 1, 0xFFFF, sum = 0
1676 12:18:07.186482 2, 0xFFFF, sum = 0
1677 12:18:07.190046 3, 0xFFFF, sum = 0
1678 12:18:07.190129 4, 0xFFFF, sum = 0
1679 12:18:07.193614 5, 0xFFFF, sum = 0
1680 12:18:07.193701 6, 0xFFFF, sum = 0
1681 12:18:07.197287 7, 0xFFFF, sum = 0
1682 12:18:07.197396 8, 0xFFFF, sum = 0
1683 12:18:07.200723 9, 0x0, sum = 1
1684 12:18:07.200805 10, 0x0, sum = 2
1685 12:18:07.204229 11, 0x0, sum = 3
1686 12:18:07.204312 12, 0x0, sum = 4
1687 12:18:07.204377 best_step = 10
1688 12:18:07.204436
1689 12:18:07.207349 ==
1690 12:18:07.207431 Dram Type= 6, Freq= 0, CH_1, rank 0
1691 12:18:07.214041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1692 12:18:07.214123 ==
1693 12:18:07.214188 RX Vref Scan: 1
1694 12:18:07.214247
1695 12:18:07.217117 Set Vref Range= 32 -> 127
1696 12:18:07.217199
1697 12:18:07.220770 RX Vref 32 -> 127, step: 1
1698 12:18:07.220852
1699 12:18:07.224222 RX Delay -95 -> 252, step: 8
1700 12:18:07.224329
1701 12:18:07.227366 Set Vref, RX VrefLevel [Byte0]: 32
1702 12:18:07.230410 [Byte1]: 32
1703 12:18:07.230518
1704 12:18:07.233988 Set Vref, RX VrefLevel [Byte0]: 33
1705 12:18:07.237642 [Byte1]: 33
1706 12:18:07.237724
1707 12:18:07.240671 Set Vref, RX VrefLevel [Byte0]: 34
1708 12:18:07.244358 [Byte1]: 34
1709 12:18:07.244440
1710 12:18:07.247512 Set Vref, RX VrefLevel [Byte0]: 35
1711 12:18:07.250522 [Byte1]: 35
1712 12:18:07.254962
1713 12:18:07.255047 Set Vref, RX VrefLevel [Byte0]: 36
1714 12:18:07.257911 [Byte1]: 36
1715 12:18:07.262156
1716 12:18:07.262238 Set Vref, RX VrefLevel [Byte0]: 37
1717 12:18:07.265907 [Byte1]: 37
1718 12:18:07.269809
1719 12:18:07.269895 Set Vref, RX VrefLevel [Byte0]: 38
1720 12:18:07.273264 [Byte1]: 38
1721 12:18:07.277304
1722 12:18:07.277411 Set Vref, RX VrefLevel [Byte0]: 39
1723 12:18:07.280968 [Byte1]: 39
1724 12:18:07.285563
1725 12:18:07.285645 Set Vref, RX VrefLevel [Byte0]: 40
1726 12:18:07.288673 [Byte1]: 40
1727 12:18:07.292652
1728 12:18:07.292764 Set Vref, RX VrefLevel [Byte0]: 41
1729 12:18:07.296418 [Byte1]: 41
1730 12:18:07.300402
1731 12:18:07.300482 Set Vref, RX VrefLevel [Byte0]: 42
1732 12:18:07.304167 [Byte1]: 42
1733 12:18:07.307981
1734 12:18:07.308086 Set Vref, RX VrefLevel [Byte0]: 43
1735 12:18:07.311556 [Byte1]: 43
1736 12:18:07.315602
1737 12:18:07.315683 Set Vref, RX VrefLevel [Byte0]: 44
1738 12:18:07.318631 [Byte1]: 44
1739 12:18:07.323415
1740 12:18:07.323497 Set Vref, RX VrefLevel [Byte0]: 45
1741 12:18:07.326440 [Byte1]: 45
1742 12:18:07.330884
1743 12:18:07.330967 Set Vref, RX VrefLevel [Byte0]: 46
1744 12:18:07.334443 [Byte1]: 46
1745 12:18:07.338158
1746 12:18:07.338258 Set Vref, RX VrefLevel [Byte0]: 47
1747 12:18:07.341466 [Byte1]: 47
1748 12:18:07.346170
1749 12:18:07.346251 Set Vref, RX VrefLevel [Byte0]: 48
1750 12:18:07.349142 [Byte1]: 48
1751 12:18:07.353536
1752 12:18:07.353617 Set Vref, RX VrefLevel [Byte0]: 49
1753 12:18:07.357073 [Byte1]: 49
1754 12:18:07.361393
1755 12:18:07.361478 Set Vref, RX VrefLevel [Byte0]: 50
1756 12:18:07.364500 [Byte1]: 50
1757 12:18:07.368931
1758 12:18:07.369012 Set Vref, RX VrefLevel [Byte0]: 51
1759 12:18:07.371877 [Byte1]: 51
1760 12:18:07.376314
1761 12:18:07.376395 Set Vref, RX VrefLevel [Byte0]: 52
1762 12:18:07.379457 [Byte1]: 52
1763 12:18:07.384032
1764 12:18:07.384114 Set Vref, RX VrefLevel [Byte0]: 53
1765 12:18:07.387163 [Byte1]: 53
1766 12:18:07.391953
1767 12:18:07.392035 Set Vref, RX VrefLevel [Byte0]: 54
1768 12:18:07.394654 [Byte1]: 54
1769 12:18:07.399325
1770 12:18:07.399407 Set Vref, RX VrefLevel [Byte0]: 55
1771 12:18:07.402521 [Byte1]: 55
1772 12:18:07.406843
1773 12:18:07.406924 Set Vref, RX VrefLevel [Byte0]: 56
1774 12:18:07.409978 [Byte1]: 56
1775 12:18:07.414195
1776 12:18:07.414280 Set Vref, RX VrefLevel [Byte0]: 57
1777 12:18:07.417738 [Byte1]: 57
1778 12:18:07.422150
1779 12:18:07.422231 Set Vref, RX VrefLevel [Byte0]: 58
1780 12:18:07.425045 [Byte1]: 58
1781 12:18:07.429347
1782 12:18:07.429429 Set Vref, RX VrefLevel [Byte0]: 59
1783 12:18:07.433090 [Byte1]: 59
1784 12:18:07.437453
1785 12:18:07.437542 Set Vref, RX VrefLevel [Byte0]: 60
1786 12:18:07.440610 [Byte1]: 60
1787 12:18:07.444869
1788 12:18:07.444951 Set Vref, RX VrefLevel [Byte0]: 61
1789 12:18:07.448328 [Byte1]: 61
1790 12:18:07.452083
1791 12:18:07.452164 Set Vref, RX VrefLevel [Byte0]: 62
1792 12:18:07.455522 [Byte1]: 62
1793 12:18:07.460049
1794 12:18:07.460133 Set Vref, RX VrefLevel [Byte0]: 63
1795 12:18:07.463127 [Byte1]: 63
1796 12:18:07.467481
1797 12:18:07.467562 Set Vref, RX VrefLevel [Byte0]: 64
1798 12:18:07.470748 [Byte1]: 64
1799 12:18:07.474820
1800 12:18:07.474902 Set Vref, RX VrefLevel [Byte0]: 65
1801 12:18:07.478687 [Byte1]: 65
1802 12:18:07.482825
1803 12:18:07.482907 Set Vref, RX VrefLevel [Byte0]: 66
1804 12:18:07.485833 [Byte1]: 66
1805 12:18:07.490575
1806 12:18:07.490683 Set Vref, RX VrefLevel [Byte0]: 67
1807 12:18:07.493616 [Byte1]: 67
1808 12:18:07.497930
1809 12:18:07.498037 Set Vref, RX VrefLevel [Byte0]: 68
1810 12:18:07.501393 [Byte1]: 68
1811 12:18:07.505561
1812 12:18:07.505669 Set Vref, RX VrefLevel [Byte0]: 69
1813 12:18:07.509275 [Byte1]: 69
1814 12:18:07.512788
1815 12:18:07.512869 Set Vref, RX VrefLevel [Byte0]: 70
1816 12:18:07.516665 [Byte1]: 70
1817 12:18:07.520812
1818 12:18:07.520894 Set Vref, RX VrefLevel [Byte0]: 71
1819 12:18:07.524065 [Byte1]: 71
1820 12:18:07.528577
1821 12:18:07.528686 Set Vref, RX VrefLevel [Byte0]: 72
1822 12:18:07.531865 [Byte1]: 72
1823 12:18:07.535965
1824 12:18:07.536045 Set Vref, RX VrefLevel [Byte0]: 73
1825 12:18:07.538945 [Byte1]: 73
1826 12:18:07.543439
1827 12:18:07.543520 Set Vref, RX VrefLevel [Byte0]: 74
1828 12:18:07.546941 [Byte1]: 74
1829 12:18:07.551269
1830 12:18:07.551350 Set Vref, RX VrefLevel [Byte0]: 75
1831 12:18:07.554385 [Byte1]: 75
1832 12:18:07.558930
1833 12:18:07.559011 Set Vref, RX VrefLevel [Byte0]: 76
1834 12:18:07.561754 [Byte1]: 76
1835 12:18:07.566094
1836 12:18:07.566176 Set Vref, RX VrefLevel [Byte0]: 77
1837 12:18:07.569534 [Byte1]: 77
1838 12:18:07.573886
1839 12:18:07.573971 Set Vref, RX VrefLevel [Byte0]: 78
1840 12:18:07.577540 [Byte1]: 78
1841 12:18:07.581394
1842 12:18:07.581476 Set Vref, RX VrefLevel [Byte0]: 79
1843 12:18:07.585129 [Byte1]: 79
1844 12:18:07.589219
1845 12:18:07.589301 Set Vref, RX VrefLevel [Byte0]: 80
1846 12:18:07.592133 [Byte1]: 80
1847 12:18:07.596944
1848 12:18:07.597025 Final RX Vref Byte 0 = 57 to rank0
1849 12:18:07.600025 Final RX Vref Byte 1 = 58 to rank0
1850 12:18:07.603029 Final RX Vref Byte 0 = 57 to rank1
1851 12:18:07.606689 Final RX Vref Byte 1 = 58 to rank1==
1852 12:18:07.609713 Dram Type= 6, Freq= 0, CH_1, rank 0
1853 12:18:07.616802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 12:18:07.616883 ==
1855 12:18:07.616947 DQS Delay:
1856 12:18:07.617005 DQS0 = 0, DQS1 = 0
1857 12:18:07.620009 DQM Delay:
1858 12:18:07.620081 DQM0 = 84, DQM1 = 73
1859 12:18:07.623316 DQ Delay:
1860 12:18:07.626787 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1861 12:18:07.626855 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =76
1862 12:18:07.630018 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1863 12:18:07.633716 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1864 12:18:07.633788
1865 12:18:07.636832
1866 12:18:07.643847 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b00, (MSB)MR19= 0x606, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
1867 12:18:07.647348 CH1 RK0: MR19=606, MR18=2B00
1868 12:18:07.654065 CH1_RK0: MR19=0x606, MR18=0x2B00, DQSOSC=398, MR23=63, INC=93, DEC=62
1869 12:18:07.654146
1870 12:18:07.657196 ----->DramcWriteLeveling(PI) begin...
1871 12:18:07.657277 ==
1872 12:18:07.660385 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 12:18:07.663907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 12:18:07.663987 ==
1875 12:18:07.666952 Write leveling (Byte 0): 28 => 28
1876 12:18:07.670572 Write leveling (Byte 1): 27 => 27
1877 12:18:07.673885 DramcWriteLeveling(PI) end<-----
1878 12:18:07.673967
1879 12:18:07.674032 ==
1880 12:18:07.676994 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 12:18:07.680607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 12:18:07.680690 ==
1883 12:18:07.684119 [Gating] SW mode calibration
1884 12:18:07.690615 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1885 12:18:07.694185 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1886 12:18:07.700748 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1887 12:18:07.703870 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1888 12:18:07.707462 0 6 8 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
1889 12:18:07.714229 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:18:07.717745 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:18:07.720759 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:18:07.727520 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:18:07.731244 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:18:07.734224 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:18:07.741057 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:18:07.744290 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:18:07.747854 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:18:07.751237 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:18:07.758318 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:18:07.761071 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:18:07.764437 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:18:07.771261 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1903 12:18:07.774709 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1904 12:18:07.778348 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:18:07.784584 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:18:07.788181 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:18:07.791262 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:18:07.798470 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 12:18:07.801904 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 12:18:07.804905 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 12:18:07.808684 0 9 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
1912 12:18:07.815430 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1913 12:18:07.818609 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 12:18:07.821646 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 12:18:07.828393 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 12:18:07.832072 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 12:18:07.835118 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 12:18:07.841793 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1919 12:18:07.845422 0 10 4 | B1->B0 | 3030 2929 | 0 0 | (0 0) (0 0)
1920 12:18:07.848549 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
1921 12:18:07.855546 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 12:18:07.859054 0 10 16 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1923 12:18:07.862680 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 12:18:07.865853 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 12:18:07.872592 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 12:18:07.876442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 12:18:07.879734 0 11 4 | B1->B0 | 2626 3939 | 0 0 | (0 0) (1 1)
1928 12:18:07.886207 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1929 12:18:07.889607 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 12:18:07.892997 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 12:18:07.899651 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 12:18:07.902659 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 12:18:07.906019 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 12:18:07.912873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 12:18:07.916040 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1936 12:18:07.919680 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:18:07.923066 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:18:07.930044 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:18:07.932801 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:18:07.936616 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:18:07.943228 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:18:07.946337 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:18:07.949947 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:18:07.956719 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 12:18:07.959717 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 12:18:07.963393 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 12:18:07.970192 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 12:18:07.973457 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 12:18:07.976764 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 12:18:07.980095 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1951 12:18:07.986548 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1952 12:18:07.990047 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 12:18:07.993532 Total UI for P1: 0, mck2ui 16
1954 12:18:07.996506 best dqsien dly found for B0: ( 0, 14, 2)
1955 12:18:08.000280 Total UI for P1: 0, mck2ui 16
1956 12:18:08.003632 best dqsien dly found for B1: ( 0, 14, 6)
1957 12:18:08.006587 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1958 12:18:08.010325 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1959 12:18:08.010786
1960 12:18:08.013466 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1961 12:18:08.016825 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1962 12:18:08.020116 [Gating] SW calibration Done
1963 12:18:08.020552 ==
1964 12:18:08.023830 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 12:18:08.027349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 12:18:08.027793 ==
1967 12:18:08.030398 RX Vref Scan: 0
1968 12:18:08.030935
1969 12:18:08.033613 RX Vref 0 -> 0, step: 1
1970 12:18:08.034062
1971 12:18:08.034394 RX Delay -130 -> 252, step: 16
1972 12:18:08.040361 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1973 12:18:08.043951 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1974 12:18:08.047245 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1975 12:18:08.050698 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1976 12:18:08.053706 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1977 12:18:08.060676 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1978 12:18:08.064271 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1979 12:18:08.067216 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1980 12:18:08.070398 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1981 12:18:08.073973 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1982 12:18:08.080556 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1983 12:18:08.084267 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1984 12:18:08.087906 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1985 12:18:08.090682 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1986 12:18:08.094462 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1987 12:18:08.101180 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1988 12:18:08.101784 ==
1989 12:18:08.104475 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 12:18:08.107625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 12:18:08.108084 ==
1992 12:18:08.108420 DQS Delay:
1993 12:18:08.111434 DQS0 = 0, DQS1 = 0
1994 12:18:08.111883 DQM Delay:
1995 12:18:08.114595 DQM0 = 82, DQM1 = 78
1996 12:18:08.115105 DQ Delay:
1997 12:18:08.117648 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1998 12:18:08.120885 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1999 12:18:08.124704 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2000 12:18:08.128078 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2001 12:18:08.128513
2002 12:18:08.128847
2003 12:18:08.129177 ==
2004 12:18:08.131130 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 12:18:08.134276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 12:18:08.134835 ==
2007 12:18:08.135366
2008 12:18:08.135851
2009 12:18:08.138159 TX Vref Scan disable
2010 12:18:08.141183 == TX Byte 0 ==
2011 12:18:08.144763 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2012 12:18:08.147808 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2013 12:18:08.151389 == TX Byte 1 ==
2014 12:18:08.154488 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2015 12:18:08.158255 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2016 12:18:08.158849 ==
2017 12:18:08.161354 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 12:18:08.164824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 12:18:08.165278 ==
2020 12:18:08.178844 TX Vref=22, minBit 8, minWin=27, winSum=440
2021 12:18:08.182348 TX Vref=24, minBit 8, minWin=27, winSum=446
2022 12:18:08.185928 TX Vref=26, minBit 1, minWin=27, winSum=445
2023 12:18:08.189228 TX Vref=28, minBit 0, minWin=28, winSum=449
2024 12:18:08.192678 TX Vref=30, minBit 0, minWin=28, winSum=451
2025 12:18:08.196084 TX Vref=32, minBit 0, minWin=28, winSum=449
2026 12:18:08.202782 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
2027 12:18:08.203214
2028 12:18:08.205883 Final TX Range 1 Vref 30
2029 12:18:08.206319
2030 12:18:08.206654 ==
2031 12:18:08.209135 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 12:18:08.212632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 12:18:08.213084 ==
2034 12:18:08.213417
2035 12:18:08.213744
2036 12:18:08.215930 TX Vref Scan disable
2037 12:18:08.219364 == TX Byte 0 ==
2038 12:18:08.222848 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2039 12:18:08.226383 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2040 12:18:08.229686 == TX Byte 1 ==
2041 12:18:08.232645 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2042 12:18:08.236404 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2043 12:18:08.236845
2044 12:18:08.239346 [DATLAT]
2045 12:18:08.239901 Freq=800, CH1 RK1
2046 12:18:08.240387
2047 12:18:08.243204 DATLAT Default: 0xa
2048 12:18:08.243643 0, 0xFFFF, sum = 0
2049 12:18:08.246347 1, 0xFFFF, sum = 0
2050 12:18:08.246824 2, 0xFFFF, sum = 0
2051 12:18:08.249345 3, 0xFFFF, sum = 0
2052 12:18:08.249769 4, 0xFFFF, sum = 0
2053 12:18:08.252922 5, 0xFFFF, sum = 0
2054 12:18:08.253348 6, 0xFFFF, sum = 0
2055 12:18:08.256192 7, 0xFFFF, sum = 0
2056 12:18:08.256638 8, 0xFFFF, sum = 0
2057 12:18:08.259926 9, 0x0, sum = 1
2058 12:18:08.260383 10, 0x0, sum = 2
2059 12:18:08.262913 11, 0x0, sum = 3
2060 12:18:08.263399 12, 0x0, sum = 4
2061 12:18:08.266516 best_step = 10
2062 12:18:08.267020
2063 12:18:08.267379 ==
2064 12:18:08.269714 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 12:18:08.273389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 12:18:08.273967 ==
2067 12:18:08.274434 RX Vref Scan: 0
2068 12:18:08.274936
2069 12:18:08.276614 RX Vref 0 -> 0, step: 1
2070 12:18:08.277061
2071 12:18:08.279622 RX Delay -95 -> 252, step: 8
2072 12:18:08.282820 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2073 12:18:08.289851 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2074 12:18:08.293731 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2075 12:18:08.296264 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2076 12:18:08.300005 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2077 12:18:08.303258 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2078 12:18:08.306849 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2079 12:18:08.313571 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2080 12:18:08.316570 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2081 12:18:08.320165 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2082 12:18:08.323258 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2083 12:18:08.327162 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2084 12:18:08.333902 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2085 12:18:08.337288 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2086 12:18:08.340081 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2087 12:18:08.343721 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2088 12:18:08.344172 ==
2089 12:18:08.347227 Dram Type= 6, Freq= 0, CH_1, rank 1
2090 12:18:08.350523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2091 12:18:08.353682 ==
2092 12:18:08.354213 DQS Delay:
2093 12:18:08.354589 DQS0 = 0, DQS1 = 0
2094 12:18:08.357041 DQM Delay:
2095 12:18:08.357479 DQM0 = 81, DQM1 = 75
2096 12:18:08.360841 DQ Delay:
2097 12:18:08.361343 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2098 12:18:08.363678 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
2099 12:18:08.367370 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2100 12:18:08.371125 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2101 12:18:08.371672
2102 12:18:08.372013
2103 12:18:08.381285 [DQSOSCAuto] RK1, (LSB)MR18= 0x2531, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2104 12:18:08.383954 CH1 RK1: MR19=606, MR18=2531
2105 12:18:08.387711 CH1_RK1: MR19=0x606, MR18=0x2531, DQSOSC=397, MR23=63, INC=93, DEC=62
2106 12:18:08.390642 [RxdqsGatingPostProcess] freq 800
2107 12:18:08.397451 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2108 12:18:08.400822 Pre-setting of DQS Precalculation
2109 12:18:08.403897 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2110 12:18:08.414426 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2111 12:18:08.420835 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2112 12:18:08.421399
2113 12:18:08.421740
2114 12:18:08.424118 [Calibration Summary] 1600 Mbps
2115 12:18:08.424544 CH 0, Rank 0
2116 12:18:08.427559 SW Impedance : PASS
2117 12:18:08.427981 DUTY Scan : NO K
2118 12:18:08.430973 ZQ Calibration : PASS
2119 12:18:08.434085 Jitter Meter : NO K
2120 12:18:08.434521 CBT Training : PASS
2121 12:18:08.437852 Write leveling : PASS
2122 12:18:08.440785 RX DQS gating : PASS
2123 12:18:08.441221 RX DQ/DQS(RDDQC) : PASS
2124 12:18:08.444411 TX DQ/DQS : PASS
2125 12:18:08.444860 RX DATLAT : PASS
2126 12:18:08.447439 RX DQ/DQS(Engine): PASS
2127 12:18:08.451050 TX OE : NO K
2128 12:18:08.451488 All Pass.
2129 12:18:08.451822
2130 12:18:08.452166 CH 0, Rank 1
2131 12:18:08.454025 SW Impedance : PASS
2132 12:18:08.457343 DUTY Scan : NO K
2133 12:18:08.457828 ZQ Calibration : PASS
2134 12:18:08.460824 Jitter Meter : NO K
2135 12:18:08.464097 CBT Training : PASS
2136 12:18:08.464544 Write leveling : PASS
2137 12:18:08.467861 RX DQS gating : PASS
2138 12:18:08.470954 RX DQ/DQS(RDDQC) : PASS
2139 12:18:08.471564 TX DQ/DQS : PASS
2140 12:18:08.474313 RX DATLAT : PASS
2141 12:18:08.477665 RX DQ/DQS(Engine): PASS
2142 12:18:08.478107 TX OE : NO K
2143 12:18:08.478457 All Pass.
2144 12:18:08.478819
2145 12:18:08.481084 CH 1, Rank 0
2146 12:18:08.481520 SW Impedance : PASS
2147 12:18:08.484394 DUTY Scan : NO K
2148 12:18:08.487912 ZQ Calibration : PASS
2149 12:18:08.488348 Jitter Meter : NO K
2150 12:18:08.491726 CBT Training : PASS
2151 12:18:08.494574 Write leveling : PASS
2152 12:18:08.495150 RX DQS gating : PASS
2153 12:18:08.497820 RX DQ/DQS(RDDQC) : PASS
2154 12:18:08.501179 TX DQ/DQS : PASS
2155 12:18:08.501604 RX DATLAT : PASS
2156 12:18:08.504939 RX DQ/DQS(Engine): PASS
2157 12:18:08.508191 TX OE : NO K
2158 12:18:08.508612 All Pass.
2159 12:18:08.508965
2160 12:18:08.509278 CH 1, Rank 1
2161 12:18:08.511138 SW Impedance : PASS
2162 12:18:08.514751 DUTY Scan : NO K
2163 12:18:08.515248 ZQ Calibration : PASS
2164 12:18:08.518109 Jitter Meter : NO K
2165 12:18:08.518557 CBT Training : PASS
2166 12:18:08.521602 Write leveling : PASS
2167 12:18:08.524735 RX DQS gating : PASS
2168 12:18:08.525310 RX DQ/DQS(RDDQC) : PASS
2169 12:18:08.528172 TX DQ/DQS : PASS
2170 12:18:08.531586 RX DATLAT : PASS
2171 12:18:08.532033 RX DQ/DQS(Engine): PASS
2172 12:18:08.535301 TX OE : NO K
2173 12:18:08.535757 All Pass.
2174 12:18:08.536090
2175 12:18:08.538401 DramC Write-DBI off
2176 12:18:08.542095 PER_BANK_REFRESH: Hybrid Mode
2177 12:18:08.542550 TX_TRACKING: ON
2178 12:18:08.545082 [GetDramInforAfterCalByMRR] Vendor 6.
2179 12:18:08.548195 [GetDramInforAfterCalByMRR] Revision 606.
2180 12:18:08.551562 [GetDramInforAfterCalByMRR] Revision 2 0.
2181 12:18:08.554922 MR0 0x3b3b
2182 12:18:08.555383 MR8 0x5151
2183 12:18:08.558455 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 12:18:08.558951
2185 12:18:08.559323 MR0 0x3b3b
2186 12:18:08.561673 MR8 0x5151
2187 12:18:08.564881 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2188 12:18:08.565346
2189 12:18:08.572016 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2190 12:18:08.578311 [FAST_K] Save calibration result to emmc
2191 12:18:08.582008 [FAST_K] Save calibration result to emmc
2192 12:18:08.582492 dram_init: config_dvfs: 1
2193 12:18:08.585302 dramc_set_vcore_voltage set vcore to 662500
2194 12:18:08.588547 Read voltage for 1200, 2
2195 12:18:08.589005 Vio18 = 0
2196 12:18:08.591746 Vcore = 662500
2197 12:18:08.592173 Vdram = 0
2198 12:18:08.592537 Vddq = 0
2199 12:18:08.595081 Vmddr = 0
2200 12:18:08.598717 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2201 12:18:08.605365 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2202 12:18:08.605955 MEM_TYPE=3, freq_sel=15
2203 12:18:08.608990 sv_algorithm_assistance_LP4_1600
2204 12:18:08.615444 ============ PULL DRAM RESETB DOWN ============
2205 12:18:08.618565 ========== PULL DRAM RESETB DOWN end =========
2206 12:18:08.622306 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2207 12:18:08.625615 ===================================
2208 12:18:08.628848 LPDDR4 DRAM CONFIGURATION
2209 12:18:08.632244 ===================================
2210 12:18:08.632761 EX_ROW_EN[0] = 0x0
2211 12:18:08.635862 EX_ROW_EN[1] = 0x0
2212 12:18:08.636359 LP4Y_EN = 0x0
2213 12:18:08.639016 WORK_FSP = 0x0
2214 12:18:08.639474 WL = 0x4
2215 12:18:08.642681 RL = 0x4
2216 12:18:08.643303 BL = 0x2
2217 12:18:08.645821 RPST = 0x0
2218 12:18:08.649557 RD_PRE = 0x0
2219 12:18:08.650155 WR_PRE = 0x1
2220 12:18:08.652447 WR_PST = 0x0
2221 12:18:08.652972 DBI_WR = 0x0
2222 12:18:08.655642 DBI_RD = 0x0
2223 12:18:08.656079 OTF = 0x1
2224 12:18:08.659201 ===================================
2225 12:18:08.662484 ===================================
2226 12:18:08.663032 ANA top config
2227 12:18:08.666253 ===================================
2228 12:18:08.669324 DLL_ASYNC_EN = 0
2229 12:18:08.672366 ALL_SLAVE_EN = 0
2230 12:18:08.675868 NEW_RANK_MODE = 1
2231 12:18:08.679333 DLL_IDLE_MODE = 1
2232 12:18:08.679756 LP45_APHY_COMB_EN = 1
2233 12:18:08.682465 TX_ODT_DIS = 1
2234 12:18:08.686230 NEW_8X_MODE = 1
2235 12:18:08.689259 ===================================
2236 12:18:08.692987 ===================================
2237 12:18:08.695887 data_rate = 2400
2238 12:18:08.696371 CKR = 1
2239 12:18:08.699482 DQ_P2S_RATIO = 8
2240 12:18:08.702848 ===================================
2241 12:18:08.706187 CA_P2S_RATIO = 8
2242 12:18:08.709737 DQ_CA_OPEN = 0
2243 12:18:08.713155 DQ_SEMI_OPEN = 0
2244 12:18:08.716139 CA_SEMI_OPEN = 0
2245 12:18:08.716755 CA_FULL_RATE = 0
2246 12:18:08.719832 DQ_CKDIV4_EN = 0
2247 12:18:08.723285 CA_CKDIV4_EN = 0
2248 12:18:08.726467 CA_PREDIV_EN = 0
2249 12:18:08.729879 PH8_DLY = 17
2250 12:18:08.730477 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2251 12:18:08.732936 DQ_AAMCK_DIV = 4
2252 12:18:08.736488 CA_AAMCK_DIV = 4
2253 12:18:08.739991 CA_ADMCK_DIV = 4
2254 12:18:08.743749 DQ_TRACK_CA_EN = 0
2255 12:18:08.746985 CA_PICK = 1200
2256 12:18:08.750504 CA_MCKIO = 1200
2257 12:18:08.751103 MCKIO_SEMI = 0
2258 12:18:08.753411 PLL_FREQ = 2366
2259 12:18:08.756434 DQ_UI_PI_RATIO = 32
2260 12:18:08.760446 CA_UI_PI_RATIO = 0
2261 12:18:08.763287 ===================================
2262 12:18:08.767078 ===================================
2263 12:18:08.770225 memory_type:LPDDR4
2264 12:18:08.770846 GP_NUM : 10
2265 12:18:08.773896 SRAM_EN : 1
2266 12:18:08.774502 MD32_EN : 0
2267 12:18:08.776870 ===================================
2268 12:18:08.780456 [ANA_INIT] >>>>>>>>>>>>>>
2269 12:18:08.783298 <<<<<< [CONFIGURE PHASE]: ANA_TX
2270 12:18:08.787087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2271 12:18:08.790201 ===================================
2272 12:18:08.793686 data_rate = 2400,PCW = 0X5b00
2273 12:18:08.797666 ===================================
2274 12:18:08.800381 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2275 12:18:08.804201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2276 12:18:08.810265 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2277 12:18:08.813908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2278 12:18:08.817098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2279 12:18:08.820426 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2280 12:18:08.823995 [ANA_INIT] flow start
2281 12:18:08.827232 [ANA_INIT] PLL >>>>>>>>
2282 12:18:08.827904 [ANA_INIT] PLL <<<<<<<<
2283 12:18:08.830685 [ANA_INIT] MIDPI >>>>>>>>
2284 12:18:08.833834 [ANA_INIT] MIDPI <<<<<<<<
2285 12:18:08.837616 [ANA_INIT] DLL >>>>>>>>
2286 12:18:08.838176 [ANA_INIT] DLL <<<<<<<<
2287 12:18:08.840596 [ANA_INIT] flow end
2288 12:18:08.844440 ============ LP4 DIFF to SE enter ============
2289 12:18:08.847429 ============ LP4 DIFF to SE exit ============
2290 12:18:08.850868 [ANA_INIT] <<<<<<<<<<<<<
2291 12:18:08.854247 [Flow] Enable top DCM control >>>>>
2292 12:18:08.857496 [Flow] Enable top DCM control <<<<<
2293 12:18:08.861006 Enable DLL master slave shuffle
2294 12:18:08.864212 ==============================================================
2295 12:18:08.867997 Gating Mode config
2296 12:18:08.874526 ==============================================================
2297 12:18:08.874822 Config description:
2298 12:18:08.884440 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2299 12:18:08.891088 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2300 12:18:08.894704 SELPH_MODE 0: By rank 1: By Phase
2301 12:18:08.900978 ==============================================================
2302 12:18:08.904549 GAT_TRACK_EN = 1
2303 12:18:08.907464 RX_GATING_MODE = 2
2304 12:18:08.911352 RX_GATING_TRACK_MODE = 2
2305 12:18:08.914248 SELPH_MODE = 1
2306 12:18:08.914399 PICG_EARLY_EN = 1
2307 12:18:08.918103 VALID_LAT_VALUE = 1
2308 12:18:08.925046 ==============================================================
2309 12:18:08.928555 Enter into Gating configuration >>>>
2310 12:18:08.931518 Exit from Gating configuration <<<<
2311 12:18:08.935233 Enter into DVFS_PRE_config >>>>>
2312 12:18:08.945245 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2313 12:18:08.948250 Exit from DVFS_PRE_config <<<<<
2314 12:18:08.951980 Enter into PICG configuration >>>>
2315 12:18:08.955302 Exit from PICG configuration <<<<
2316 12:18:08.958582 [RX_INPUT] configuration >>>>>
2317 12:18:08.962243 [RX_INPUT] configuration <<<<<
2318 12:18:08.965659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2319 12:18:08.971978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2320 12:18:08.979263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 12:18:08.982127 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 12:18:08.988818 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 12:18:08.995349 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 12:18:08.999109 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2325 12:18:09.002109 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2326 12:18:09.009109 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2327 12:18:09.012011 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2328 12:18:09.015708 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2329 12:18:09.022305 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 12:18:09.022396 ===================================
2331 12:18:09.026109 LPDDR4 DRAM CONFIGURATION
2332 12:18:09.029062 ===================================
2333 12:18:09.032194 EX_ROW_EN[0] = 0x0
2334 12:18:09.032292 EX_ROW_EN[1] = 0x0
2335 12:18:09.036119 LP4Y_EN = 0x0
2336 12:18:09.036217 WORK_FSP = 0x0
2337 12:18:09.038959 WL = 0x4
2338 12:18:09.039064 RL = 0x4
2339 12:18:09.042603 BL = 0x2
2340 12:18:09.042718 RPST = 0x0
2341 12:18:09.046092 RD_PRE = 0x0
2342 12:18:09.046207 WR_PRE = 0x1
2343 12:18:09.049159 WR_PST = 0x0
2344 12:18:09.049286 DBI_WR = 0x0
2345 12:18:09.052548 DBI_RD = 0x0
2346 12:18:09.052697 OTF = 0x1
2347 12:18:09.056342 ===================================
2348 12:18:09.062527 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2349 12:18:09.066314 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2350 12:18:09.069572 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2351 12:18:09.072915 ===================================
2352 12:18:09.076015 LPDDR4 DRAM CONFIGURATION
2353 12:18:09.079953 ===================================
2354 12:18:09.080338 EX_ROW_EN[0] = 0x10
2355 12:18:09.083539 EX_ROW_EN[1] = 0x0
2356 12:18:09.086437 LP4Y_EN = 0x0
2357 12:18:09.086978 WORK_FSP = 0x0
2358 12:18:09.090083 WL = 0x4
2359 12:18:09.090628 RL = 0x4
2360 12:18:09.093069 BL = 0x2
2361 12:18:09.093482 RPST = 0x0
2362 12:18:09.096773 RD_PRE = 0x0
2363 12:18:09.097181 WR_PRE = 0x1
2364 12:18:09.099934 WR_PST = 0x0
2365 12:18:09.100340 DBI_WR = 0x0
2366 12:18:09.103414 DBI_RD = 0x0
2367 12:18:09.103819 OTF = 0x1
2368 12:18:09.106433 ===================================
2369 12:18:09.113107 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2370 12:18:09.113518 ==
2371 12:18:09.116610 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 12:18:09.119881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 12:18:09.120171 ==
2374 12:18:09.123692 [Duty_Offset_Calibration]
2375 12:18:09.126506 B0:2 B1:-1 CA:1
2376 12:18:09.126843
2377 12:18:09.129595 [DutyScan_Calibration_Flow] k_type=0
2378 12:18:09.137441
2379 12:18:09.137729 ==CLK 0==
2380 12:18:09.140642 Final CLK duty delay cell = -4
2381 12:18:09.144085 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2382 12:18:09.147563 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2383 12:18:09.150585 [-4] AVG Duty = 4953%(X100)
2384 12:18:09.150901
2385 12:18:09.154524 CH0 CLK Duty spec in!! Max-Min= 156%
2386 12:18:09.157048 [DutyScan_Calibration_Flow] ====Done====
2387 12:18:09.157455
2388 12:18:09.160709 [DutyScan_Calibration_Flow] k_type=1
2389 12:18:09.176261
2390 12:18:09.176864 ==DQS 0 ==
2391 12:18:09.179947 Final DQS duty delay cell = 0
2392 12:18:09.183099 [0] MAX Duty = 5125%(X100), DQS PI = 48
2393 12:18:09.186527 [0] MIN Duty = 5000%(X100), DQS PI = 12
2394 12:18:09.187030 [0] AVG Duty = 5062%(X100)
2395 12:18:09.189660
2396 12:18:09.190067 ==DQS 1 ==
2397 12:18:09.193208 Final DQS duty delay cell = -4
2398 12:18:09.196769 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2399 12:18:09.199827 [-4] MIN Duty = 5031%(X100), DQS PI = 44
2400 12:18:09.203417 [-4] AVG Duty = 5077%(X100)
2401 12:18:09.203930
2402 12:18:09.206821 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2403 12:18:09.207340
2404 12:18:09.209514 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2405 12:18:09.213299 [DutyScan_Calibration_Flow] ====Done====
2406 12:18:09.213711
2407 12:18:09.216211 [DutyScan_Calibration_Flow] k_type=3
2408 12:18:09.232960
2409 12:18:09.233474 ==DQM 0 ==
2410 12:18:09.236451 Final DQM duty delay cell = 0
2411 12:18:09.239763 [0] MAX Duty = 5000%(X100), DQS PI = 54
2412 12:18:09.242816 [0] MIN Duty = 4907%(X100), DQS PI = 2
2413 12:18:09.243433 [0] AVG Duty = 4953%(X100)
2414 12:18:09.243848
2415 12:18:09.246463 ==DQM 1 ==
2416 12:18:09.249593 Final DQM duty delay cell = 0
2417 12:18:09.253354 [0] MAX Duty = 5124%(X100), DQS PI = 32
2418 12:18:09.256890 [0] MIN Duty = 4969%(X100), DQS PI = 10
2419 12:18:09.257303 [0] AVG Duty = 5046%(X100)
2420 12:18:09.257629
2421 12:18:09.259888 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2422 12:18:09.263071
2423 12:18:09.266831 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2424 12:18:09.270137 [DutyScan_Calibration_Flow] ====Done====
2425 12:18:09.270675
2426 12:18:09.273011 [DutyScan_Calibration_Flow] k_type=2
2427 12:18:09.288458
2428 12:18:09.288963 ==DQ 0 ==
2429 12:18:09.292426 Final DQ duty delay cell = -4
2430 12:18:09.295203 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2431 12:18:09.298827 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2432 12:18:09.302491 [-4] AVG Duty = 4969%(X100)
2433 12:18:09.302938
2434 12:18:09.303258 ==DQ 1 ==
2435 12:18:09.305220 Final DQ duty delay cell = 0
2436 12:18:09.308603 [0] MAX Duty = 5031%(X100), DQS PI = 18
2437 12:18:09.312405 [0] MIN Duty = 4907%(X100), DQS PI = 46
2438 12:18:09.312815 [0] AVG Duty = 4969%(X100)
2439 12:18:09.313141
2440 12:18:09.315252 CH0 DQ 0 Duty spec in!! Max-Min= 186%
2441 12:18:09.318633
2442 12:18:09.322372 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2443 12:18:09.325617 [DutyScan_Calibration_Flow] ====Done====
2444 12:18:09.326114 ==
2445 12:18:09.329072 Dram Type= 6, Freq= 0, CH_1, rank 0
2446 12:18:09.332284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 12:18:09.332705 ==
2448 12:18:09.335451 [Duty_Offset_Calibration]
2449 12:18:09.335917 B0:1 B1:1 CA:2
2450 12:18:09.336257
2451 12:18:09.339279 [DutyScan_Calibration_Flow] k_type=0
2452 12:18:09.348947
2453 12:18:09.349386 ==CLK 0==
2454 12:18:09.352630 Final CLK duty delay cell = 0
2455 12:18:09.355398 [0] MAX Duty = 5156%(X100), DQS PI = 24
2456 12:18:09.359025 [0] MIN Duty = 4969%(X100), DQS PI = 38
2457 12:18:09.359499 [0] AVG Duty = 5062%(X100)
2458 12:18:09.359837
2459 12:18:09.362701 CH1 CLK Duty spec in!! Max-Min= 187%
2460 12:18:09.365797 [DutyScan_Calibration_Flow] ====Done====
2461 12:18:09.369524
2462 12:18:09.372631 [DutyScan_Calibration_Flow] k_type=1
2463 12:18:09.388001
2464 12:18:09.388471 ==DQS 0 ==
2465 12:18:09.391649 Final DQS duty delay cell = 0
2466 12:18:09.394650 [0] MAX Duty = 5031%(X100), DQS PI = 18
2467 12:18:09.398286 [0] MIN Duty = 4813%(X100), DQS PI = 50
2468 12:18:09.398702 [0] AVG Duty = 4922%(X100)
2469 12:18:09.401628
2470 12:18:09.402039 ==DQS 1 ==
2471 12:18:09.405476 Final DQS duty delay cell = 0
2472 12:18:09.408229 [0] MAX Duty = 5062%(X100), DQS PI = 36
2473 12:18:09.411848 [0] MIN Duty = 4907%(X100), DQS PI = 14
2474 12:18:09.412352 [0] AVG Duty = 4984%(X100)
2475 12:18:09.415395
2476 12:18:09.418394 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2477 12:18:09.418966
2478 12:18:09.421844 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2479 12:18:09.425164 [DutyScan_Calibration_Flow] ====Done====
2480 12:18:09.425637
2481 12:18:09.428506 [DutyScan_Calibration_Flow] k_type=3
2482 12:18:09.445137
2483 12:18:09.445672 ==DQM 0 ==
2484 12:18:09.447950 Final DQM duty delay cell = 0
2485 12:18:09.451799 [0] MAX Duty = 5093%(X100), DQS PI = 18
2486 12:18:09.454773 [0] MIN Duty = 4876%(X100), DQS PI = 50
2487 12:18:09.455192 [0] AVG Duty = 4984%(X100)
2488 12:18:09.458379
2489 12:18:09.458833 ==DQM 1 ==
2490 12:18:09.461926 Final DQM duty delay cell = 0
2491 12:18:09.465539 [0] MAX Duty = 5156%(X100), DQS PI = 62
2492 12:18:09.468549 [0] MIN Duty = 4938%(X100), DQS PI = 22
2493 12:18:09.468970 [0] AVG Duty = 5047%(X100)
2494 12:18:09.469297
2495 12:18:09.472302 CH1 DQM 0 Duty spec in!! Max-Min= 217%
2496 12:18:09.475362
2497 12:18:09.478851 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2498 12:18:09.482428 [DutyScan_Calibration_Flow] ====Done====
2499 12:18:09.482975
2500 12:18:09.485369 [DutyScan_Calibration_Flow] k_type=2
2501 12:18:09.501084
2502 12:18:09.501607 ==DQ 0 ==
2503 12:18:09.503764 Final DQ duty delay cell = 0
2504 12:18:09.507698 [0] MAX Duty = 5124%(X100), DQS PI = 18
2505 12:18:09.510642 [0] MIN Duty = 4938%(X100), DQS PI = 50
2506 12:18:09.511104 [0] AVG Duty = 5031%(X100)
2507 12:18:09.511434
2508 12:18:09.514168 ==DQ 1 ==
2509 12:18:09.517158 Final DQ duty delay cell = -4
2510 12:18:09.520723 [-4] MAX Duty = 4969%(X100), DQS PI = 42
2511 12:18:09.523921 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2512 12:18:09.524355 [-4] AVG Duty = 4938%(X100)
2513 12:18:09.527323
2514 12:18:09.530924 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2515 12:18:09.531342
2516 12:18:09.534286 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2517 12:18:09.537492 [DutyScan_Calibration_Flow] ====Done====
2518 12:18:09.540827 nWR fixed to 30
2519 12:18:09.541251 [ModeRegInit_LP4] CH0 RK0
2520 12:18:09.543907 [ModeRegInit_LP4] CH0 RK1
2521 12:18:09.547595 [ModeRegInit_LP4] CH1 RK0
2522 12:18:09.547987 [ModeRegInit_LP4] CH1 RK1
2523 12:18:09.550779 match AC timing 7
2524 12:18:09.554335 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2525 12:18:09.557455 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2526 12:18:09.564493 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2527 12:18:09.568052 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2528 12:18:09.574666 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2529 12:18:09.575128 ==
2530 12:18:09.577829 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 12:18:09.581462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 12:18:09.581885 ==
2533 12:18:09.588044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 12:18:09.591234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2535 12:18:09.600929 [CA 0] Center 40 (10~71) winsize 62
2536 12:18:09.604388 [CA 1] Center 39 (9~70) winsize 62
2537 12:18:09.607468 [CA 2] Center 36 (6~67) winsize 62
2538 12:18:09.611277 [CA 3] Center 36 (5~67) winsize 63
2539 12:18:09.614687 [CA 4] Center 35 (5~65) winsize 61
2540 12:18:09.617873 [CA 5] Center 34 (4~65) winsize 62
2541 12:18:09.618286
2542 12:18:09.620781 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2543 12:18:09.621196
2544 12:18:09.624577 [CATrainingPosCal] consider 1 rank data
2545 12:18:09.628186 u2DelayCellTimex100 = 270/100 ps
2546 12:18:09.630975 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2547 12:18:09.634602 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2548 12:18:09.637717 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2549 12:18:09.645094 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2550 12:18:09.648057 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2551 12:18:09.651550 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2552 12:18:09.651971
2553 12:18:09.654836 CA PerBit enable=1, Macro0, CA PI delay=34
2554 12:18:09.655263
2555 12:18:09.657758 [CBTSetCACLKResult] CA Dly = 34
2556 12:18:09.658180 CS Dly: 7 (0~38)
2557 12:18:09.658516 ==
2558 12:18:09.661609 Dram Type= 6, Freq= 0, CH_0, rank 1
2559 12:18:09.668071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 12:18:09.668503 ==
2561 12:18:09.671119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2562 12:18:09.677893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2563 12:18:09.686980 [CA 0] Center 39 (9~70) winsize 62
2564 12:18:09.690557 [CA 1] Center 40 (10~70) winsize 61
2565 12:18:09.693368 [CA 2] Center 36 (6~67) winsize 62
2566 12:18:09.696914 [CA 3] Center 35 (5~66) winsize 62
2567 12:18:09.700758 [CA 4] Center 34 (4~65) winsize 62
2568 12:18:09.703625 [CA 5] Center 34 (4~64) winsize 61
2569 12:18:09.704045
2570 12:18:09.707186 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2571 12:18:09.707611
2572 12:18:09.710173 [CATrainingPosCal] consider 2 rank data
2573 12:18:09.713315 u2DelayCellTimex100 = 270/100 ps
2574 12:18:09.716753 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2575 12:18:09.720217 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2576 12:18:09.727003 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2577 12:18:09.730478 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2578 12:18:09.734262 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2579 12:18:09.737317 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2580 12:18:09.737976
2581 12:18:09.740452 CA PerBit enable=1, Macro0, CA PI delay=34
2582 12:18:09.740919
2583 12:18:09.743582 [CBTSetCACLKResult] CA Dly = 34
2584 12:18:09.744095 CS Dly: 8 (0~41)
2585 12:18:09.744430
2586 12:18:09.747146 ----->DramcWriteLeveling(PI) begin...
2587 12:18:09.747565 ==
2588 12:18:09.750490 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 12:18:09.756910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 12:18:09.757342 ==
2591 12:18:09.760723 Write leveling (Byte 0): 29 => 29
2592 12:18:09.763567 Write leveling (Byte 1): 29 => 29
2593 12:18:09.767233 DramcWriteLeveling(PI) end<-----
2594 12:18:09.767691
2595 12:18:09.768089 ==
2596 12:18:09.770336 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 12:18:09.773703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 12:18:09.774142 ==
2599 12:18:09.776924 [Gating] SW mode calibration
2600 12:18:09.784327 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2601 12:18:09.787002 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2602 12:18:09.794058 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 12:18:09.797057 0 15 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2604 12:18:09.800535 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 12:18:09.807465 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 12:18:09.810606 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 12:18:09.813807 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 12:18:09.820921 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 12:18:09.824314 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 12:18:09.827670 1 0 0 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
2611 12:18:09.830780 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2612 12:18:09.837730 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 12:18:09.841105 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 12:18:09.844753 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 12:18:09.850932 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 12:18:09.854414 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 12:18:09.857546 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 12:18:09.864466 1 1 0 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
2619 12:18:09.868224 1 1 4 | B1->B0 | 3d3d 4545 | 1 0 | (0 0) (0 0)
2620 12:18:09.871302 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 12:18:09.877833 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 12:18:09.881274 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 12:18:09.884842 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 12:18:09.887889 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 12:18:09.894855 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 12:18:09.898016 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2627 12:18:09.901409 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2628 12:18:09.908423 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:18:09.911434 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:18:09.915076 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:18:09.921743 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:18:09.924791 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:18:09.928144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 12:18:09.931445 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 12:18:09.938237 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 12:18:09.941750 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 12:18:09.945481 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 12:18:09.952312 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 12:18:09.955188 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 12:18:09.958801 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 12:18:09.965169 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 12:18:09.969023 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2643 12:18:09.971968 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2644 12:18:09.978877 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2645 12:18:09.979313 Total UI for P1: 0, mck2ui 16
2646 12:18:09.985160 best dqsien dly found for B0: ( 1, 4, 2)
2647 12:18:09.985591 Total UI for P1: 0, mck2ui 16
2648 12:18:09.988495 best dqsien dly found for B1: ( 1, 4, 2)
2649 12:18:09.995476 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2650 12:18:09.998635 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2651 12:18:09.999126
2652 12:18:10.002139 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2653 12:18:10.005636 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2654 12:18:10.008639 [Gating] SW calibration Done
2655 12:18:10.008950 ==
2656 12:18:10.012209 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 12:18:10.015887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 12:18:10.016125 ==
2659 12:18:10.016306 RX Vref Scan: 0
2660 12:18:10.016474
2661 12:18:10.019040 RX Vref 0 -> 0, step: 1
2662 12:18:10.019225
2663 12:18:10.021823 RX Delay -40 -> 252, step: 8
2664 12:18:10.025509 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2665 12:18:10.028539 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2666 12:18:10.032216 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2667 12:18:10.038544 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2668 12:18:10.042216 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2669 12:18:10.046116 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2670 12:18:10.048925 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2671 12:18:10.052320 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2672 12:18:10.058765 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2673 12:18:10.062522 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2674 12:18:10.329097 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2675 12:18:10.329965 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2676 12:18:10.330345 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2677 12:18:10.330675 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2678 12:18:10.331045 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2679 12:18:10.331348 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2680 12:18:10.331829 ==
2681 12:18:10.332140 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 12:18:10.332433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 12:18:10.332722 ==
2684 12:18:10.333006 DQS Delay:
2685 12:18:10.333286 DQS0 = 0, DQS1 = 0
2686 12:18:10.333567 DQM Delay:
2687 12:18:10.333843 DQM0 = 116, DQM1 = 107
2688 12:18:10.334119 DQ Delay:
2689 12:18:10.334395 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2690 12:18:10.334677 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2691 12:18:10.335010 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2692 12:18:10.335290 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2693 12:18:10.335564
2694 12:18:10.335840
2695 12:18:10.336112 ==
2696 12:18:10.336388 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 12:18:10.336825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 12:18:10.337117 ==
2699 12:18:10.337394
2700 12:18:10.337720
2701 12:18:10.337999 TX Vref Scan disable
2702 12:18:10.338272 == TX Byte 0 ==
2703 12:18:10.338548 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2704 12:18:10.338854 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2705 12:18:10.339166 == TX Byte 1 ==
2706 12:18:10.339444 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2707 12:18:10.339723 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2708 12:18:10.339999 ==
2709 12:18:10.340299 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 12:18:10.340584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 12:18:10.340863 ==
2712 12:18:10.341135 TX Vref=22, minBit 0, minWin=26, winSum=423
2713 12:18:10.341412 TX Vref=24, minBit 1, minWin=25, winSum=420
2714 12:18:10.341687 TX Vref=26, minBit 5, minWin=25, winSum=426
2715 12:18:10.342004 TX Vref=28, minBit 1, minWin=26, winSum=430
2716 12:18:10.342314 TX Vref=30, minBit 1, minWin=26, winSum=434
2717 12:18:10.342752 TX Vref=32, minBit 0, minWin=26, winSum=433
2718 12:18:10.343086 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
2719 12:18:10.343376
2720 12:18:10.343656 Final TX Range 1 Vref 30
2721 12:18:10.343929
2722 12:18:10.344203 ==
2723 12:18:10.344607 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 12:18:10.345122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 12:18:10.345617 ==
2726 12:18:10.346115
2727 12:18:10.346604
2728 12:18:10.347131 TX Vref Scan disable
2729 12:18:10.347637 == TX Byte 0 ==
2730 12:18:10.348130 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2731 12:18:10.348631 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2732 12:18:10.349124 == TX Byte 1 ==
2733 12:18:10.349600 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2734 12:18:10.349920 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2735 12:18:10.350243
2736 12:18:10.350537 [DATLAT]
2737 12:18:10.350867 Freq=1200, CH0 RK0
2738 12:18:10.351175
2739 12:18:10.351468 DATLAT Default: 0xd
2740 12:18:10.351747 0, 0xFFFF, sum = 0
2741 12:18:10.352033 1, 0xFFFF, sum = 0
2742 12:18:10.352408 2, 0xFFFF, sum = 0
2743 12:18:10.352790 3, 0xFFFF, sum = 0
2744 12:18:10.353078 4, 0xFFFF, sum = 0
2745 12:18:10.353358 5, 0xFFFF, sum = 0
2746 12:18:10.353636 6, 0xFFFF, sum = 0
2747 12:18:10.353916 7, 0xFFFF, sum = 0
2748 12:18:10.354207 8, 0xFFFF, sum = 0
2749 12:18:10.354486 9, 0xFFFF, sum = 0
2750 12:18:10.354818 10, 0xFFFF, sum = 0
2751 12:18:10.355113 11, 0xFFFF, sum = 0
2752 12:18:10.355391 12, 0x0, sum = 1
2753 12:18:10.355667 13, 0x0, sum = 2
2754 12:18:10.355944 14, 0x0, sum = 3
2755 12:18:10.356221 15, 0x0, sum = 4
2756 12:18:10.356496 best_step = 13
2757 12:18:10.356768
2758 12:18:10.357043 ==
2759 12:18:10.357333 Dram Type= 6, Freq= 0, CH_0, rank 0
2760 12:18:10.357609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2761 12:18:10.357906 ==
2762 12:18:10.358186 RX Vref Scan: 1
2763 12:18:10.358614
2764 12:18:10.358989 Set Vref Range= 32 -> 127
2765 12:18:10.359322
2766 12:18:10.359650 RX Vref 32 -> 127, step: 1
2767 12:18:10.360135
2768 12:18:10.360518 RX Delay -21 -> 252, step: 4
2769 12:18:10.360964
2770 12:18:10.361267 Set Vref, RX VrefLevel [Byte0]: 32
2771 12:18:10.361608 [Byte1]: 32
2772 12:18:10.361904
2773 12:18:10.362240 Set Vref, RX VrefLevel [Byte0]: 33
2774 12:18:10.362534 [Byte1]: 33
2775 12:18:10.362897
2776 12:18:10.363113 Set Vref, RX VrefLevel [Byte0]: 34
2777 12:18:10.363402 [Byte1]: 34
2778 12:18:10.363670
2779 12:18:10.363988 Set Vref, RX VrefLevel [Byte0]: 35
2780 12:18:10.364339 [Byte1]: 35
2781 12:18:10.364587
2782 12:18:10.364863 Set Vref, RX VrefLevel [Byte0]: 36
2783 12:18:10.365066 [Byte1]: 36
2784 12:18:10.365321
2785 12:18:10.365539 Set Vref, RX VrefLevel [Byte0]: 37
2786 12:18:10.365748 [Byte1]: 37
2787 12:18:10.366002
2788 12:18:10.366236 Set Vref, RX VrefLevel [Byte0]: 38
2789 12:18:10.366532 [Byte1]: 38
2790 12:18:10.366972
2791 12:18:10.367199 Set Vref, RX VrefLevel [Byte0]: 39
2792 12:18:10.367404 [Byte1]: 39
2793 12:18:10.367604
2794 12:18:10.367801 Set Vref, RX VrefLevel [Byte0]: 40
2795 12:18:10.367983 [Byte1]: 40
2796 12:18:10.368131
2797 12:18:10.368300 Set Vref, RX VrefLevel [Byte0]: 41
2798 12:18:10.368448 [Byte1]: 41
2799 12:18:10.368595
2800 12:18:10.368743 Set Vref, RX VrefLevel [Byte0]: 42
2801 12:18:10.368890 [Byte1]: 42
2802 12:18:10.369058
2803 12:18:10.369214 Set Vref, RX VrefLevel [Byte0]: 43
2804 12:18:10.369362 [Byte1]: 43
2805 12:18:10.370440
2806 12:18:10.370813 Set Vref, RX VrefLevel [Byte0]: 44
2807 12:18:10.373541 [Byte1]: 44
2808 12:18:10.378609
2809 12:18:10.378958 Set Vref, RX VrefLevel [Byte0]: 45
2810 12:18:10.381997 [Byte1]: 45
2811 12:18:10.386517
2812 12:18:10.386804 Set Vref, RX VrefLevel [Byte0]: 46
2813 12:18:10.389427 [Byte1]: 46
2814 12:18:10.394445
2815 12:18:10.394739 Set Vref, RX VrefLevel [Byte0]: 47
2816 12:18:10.397273 [Byte1]: 47
2817 12:18:10.402017
2818 12:18:10.402194 Set Vref, RX VrefLevel [Byte0]: 48
2819 12:18:10.405678 [Byte1]: 48
2820 12:18:10.409973
2821 12:18:10.410104 Set Vref, RX VrefLevel [Byte0]: 49
2822 12:18:10.413934 [Byte1]: 49
2823 12:18:10.418270
2824 12:18:10.418353 Set Vref, RX VrefLevel [Byte0]: 50
2825 12:18:10.421371 [Byte1]: 50
2826 12:18:10.426258
2827 12:18:10.426340 Set Vref, RX VrefLevel [Byte0]: 51
2828 12:18:10.429193 [Byte1]: 51
2829 12:18:10.434082
2830 12:18:10.434166 Set Vref, RX VrefLevel [Byte0]: 52
2831 12:18:10.437040 [Byte1]: 52
2832 12:18:10.441898
2833 12:18:10.441989 Set Vref, RX VrefLevel [Byte0]: 53
2834 12:18:10.445016 [Byte1]: 53
2835 12:18:10.449851
2836 12:18:10.449956 Set Vref, RX VrefLevel [Byte0]: 54
2837 12:18:10.452918 [Byte1]: 54
2838 12:18:10.457616
2839 12:18:10.457729 Set Vref, RX VrefLevel [Byte0]: 55
2840 12:18:10.461260 [Byte1]: 55
2841 12:18:10.465947
2842 12:18:10.466086 Set Vref, RX VrefLevel [Byte0]: 56
2843 12:18:10.468869 [Byte1]: 56
2844 12:18:10.473489
2845 12:18:10.473680 Set Vref, RX VrefLevel [Byte0]: 57
2846 12:18:10.477058 [Byte1]: 57
2847 12:18:10.481784
2848 12:18:10.482095 Set Vref, RX VrefLevel [Byte0]: 58
2849 12:18:10.485238 [Byte1]: 58
2850 12:18:10.489466
2851 12:18:10.489758 Set Vref, RX VrefLevel [Byte0]: 59
2852 12:18:10.492601 [Byte1]: 59
2853 12:18:10.497427
2854 12:18:10.497649 Set Vref, RX VrefLevel [Byte0]: 60
2855 12:18:10.500850 [Byte1]: 60
2856 12:18:10.505534
2857 12:18:10.505755 Set Vref, RX VrefLevel [Byte0]: 61
2858 12:18:10.508465 [Byte1]: 61
2859 12:18:10.513402
2860 12:18:10.513624 Set Vref, RX VrefLevel [Byte0]: 62
2861 12:18:10.516345 [Byte1]: 62
2862 12:18:10.521255
2863 12:18:10.521462 Set Vref, RX VrefLevel [Byte0]: 63
2864 12:18:10.524512 [Byte1]: 63
2865 12:18:10.529377
2866 12:18:10.529591 Set Vref, RX VrefLevel [Byte0]: 64
2867 12:18:10.532098 [Byte1]: 64
2868 12:18:10.536781
2869 12:18:10.536968 Set Vref, RX VrefLevel [Byte0]: 65
2870 12:18:10.540502 [Byte1]: 65
2871 12:18:10.545075
2872 12:18:10.545245 Set Vref, RX VrefLevel [Byte0]: 66
2873 12:18:10.548294 [Byte1]: 66
2874 12:18:10.553153
2875 12:18:10.553280 Set Vref, RX VrefLevel [Byte0]: 67
2876 12:18:10.556051 [Byte1]: 67
2877 12:18:10.561004
2878 12:18:10.561161 Final RX Vref Byte 0 = 54 to rank0
2879 12:18:10.564344 Final RX Vref Byte 1 = 51 to rank0
2880 12:18:10.567377 Final RX Vref Byte 0 = 54 to rank1
2881 12:18:10.570899 Final RX Vref Byte 1 = 51 to rank1==
2882 12:18:10.573957 Dram Type= 6, Freq= 0, CH_0, rank 0
2883 12:18:10.577686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 12:18:10.580820 ==
2885 12:18:10.580905 DQS Delay:
2886 12:18:10.580968 DQS0 = 0, DQS1 = 0
2887 12:18:10.584598 DQM Delay:
2888 12:18:10.584679 DQM0 = 115, DQM1 = 106
2889 12:18:10.587459 DQ Delay:
2890 12:18:10.591007 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2891 12:18:10.593967 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2892 12:18:10.597359 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2893 12:18:10.601208 DQ12 =114, DQ13 =112, DQ14 =120, DQ15 =114
2894 12:18:10.601352
2895 12:18:10.601446
2896 12:18:10.607867 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2897 12:18:10.610981 CH0 RK0: MR19=303, MR18=FEED
2898 12:18:10.617580 CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26
2899 12:18:10.617714
2900 12:18:10.621351 ----->DramcWriteLeveling(PI) begin...
2901 12:18:10.621441 ==
2902 12:18:10.624428 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 12:18:10.627987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 12:18:10.628070 ==
2905 12:18:10.631091 Write leveling (Byte 0): 30 => 30
2906 12:18:10.634572 Write leveling (Byte 1): 27 => 27
2907 12:18:10.637643 DramcWriteLeveling(PI) end<-----
2908 12:18:10.637727
2909 12:18:10.637792 ==
2910 12:18:10.641259 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 12:18:10.644695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 12:18:10.644793 ==
2913 12:18:10.648241 [Gating] SW mode calibration
2914 12:18:10.654717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2915 12:18:10.661438 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2916 12:18:10.665214 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2917 12:18:10.671953 0 15 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
2918 12:18:10.674687 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 12:18:10.678348 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 12:18:10.681426 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 12:18:10.688052 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 12:18:10.691820 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2923 12:18:10.694750 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2924 12:18:10.701819 1 0 0 | B1->B0 | 2e2e 2525 | 1 0 | (1 1) (0 0)
2925 12:18:10.705375 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 12:18:10.708480 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 12:18:10.714772 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 12:18:10.718688 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 12:18:10.722003 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 12:18:10.728373 1 0 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
2931 12:18:10.732024 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2932 12:18:10.735167 1 1 0 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
2933 12:18:10.738514 1 1 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2934 12:18:10.745727 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 12:18:10.748871 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 12:18:10.752366 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 12:18:10.759018 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 12:18:10.762141 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 12:18:10.765641 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2940 12:18:10.772226 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2941 12:18:10.775556 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:18:10.778924 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 12:18:10.785568 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 12:18:10.789209 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 12:18:10.792212 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 12:18:10.795920 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 12:18:10.802853 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:18:10.806164 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:18:10.809474 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:18:10.815824 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:18:10.819385 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:18:10.822471 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:18:10.829381 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:18:10.832748 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2955 12:18:10.836385 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2956 12:18:10.842929 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2957 12:18:10.843014 Total UI for P1: 0, mck2ui 16
2958 12:18:10.845875 best dqsien dly found for B0: ( 1, 3, 26)
2959 12:18:10.852853 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2960 12:18:10.855873 Total UI for P1: 0, mck2ui 16
2961 12:18:10.859628 best dqsien dly found for B1: ( 1, 3, 30)
2962 12:18:10.862679 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2963 12:18:10.866376 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2964 12:18:10.866487
2965 12:18:10.869346 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2966 12:18:10.872940 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2967 12:18:10.876579 [Gating] SW calibration Done
2968 12:18:10.876681 ==
2969 12:18:10.879594 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 12:18:10.883263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 12:18:10.883350 ==
2972 12:18:10.886156 RX Vref Scan: 0
2973 12:18:10.886243
2974 12:18:10.886310 RX Vref 0 -> 0, step: 1
2975 12:18:10.886374
2976 12:18:10.889876 RX Delay -40 -> 252, step: 8
2977 12:18:10.893034 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2978 12:18:10.899723 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2979 12:18:10.903358 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2980 12:18:10.906700 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2981 12:18:10.909835 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2982 12:18:10.913210 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2983 12:18:10.919681 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2984 12:18:10.923804 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2985 12:18:10.926571 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2986 12:18:10.929961 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2987 12:18:10.933462 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2988 12:18:10.936931 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2989 12:18:10.943314 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2990 12:18:10.947179 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2991 12:18:10.950025 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2992 12:18:10.953363 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2993 12:18:10.953465 ==
2994 12:18:10.956937 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 12:18:10.963381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 12:18:10.963462 ==
2997 12:18:10.963526 DQS Delay:
2998 12:18:10.963585 DQS0 = 0, DQS1 = 0
2999 12:18:10.967050 DQM Delay:
3000 12:18:10.967131 DQM0 = 115, DQM1 = 105
3001 12:18:10.970265 DQ Delay:
3002 12:18:10.973775 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3003 12:18:10.977100 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3004 12:18:10.980283 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3005 12:18:10.983744 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
3006 12:18:10.983826
3007 12:18:10.983890
3008 12:18:10.983949 ==
3009 12:18:10.987392 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 12:18:10.991081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 12:18:10.991176 ==
3012 12:18:10.991240
3013 12:18:10.991298
3014 12:18:10.994198 TX Vref Scan disable
3015 12:18:10.997106 == TX Byte 0 ==
3016 12:18:11.000953 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3017 12:18:11.003924 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3018 12:18:11.007422 == TX Byte 1 ==
3019 12:18:11.010481 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3020 12:18:11.013980 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3021 12:18:11.014061 ==
3022 12:18:11.017621 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 12:18:11.020639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 12:18:11.020720 ==
3025 12:18:11.034268 TX Vref=22, minBit 1, minWin=26, winSum=427
3026 12:18:11.037301 TX Vref=24, minBit 1, minWin=25, winSum=430
3027 12:18:11.040795 TX Vref=26, minBit 6, minWin=26, winSum=435
3028 12:18:11.044000 TX Vref=28, minBit 4, minWin=26, winSum=439
3029 12:18:11.047532 TX Vref=30, minBit 0, minWin=27, winSum=440
3030 12:18:11.051134 TX Vref=32, minBit 0, minWin=27, winSum=442
3031 12:18:11.057559 [TxChooseVref] Worse bit 0, Min win 27, Win sum 442, Final Vref 32
3032 12:18:11.057640
3033 12:18:11.061033 Final TX Range 1 Vref 32
3034 12:18:11.061112
3035 12:18:11.061197 ==
3036 12:18:11.064567 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 12:18:11.067587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 12:18:11.067671 ==
3039 12:18:11.067755
3040 12:18:11.067833
3041 12:18:11.071273 TX Vref Scan disable
3042 12:18:11.074289 == TX Byte 0 ==
3043 12:18:11.077759 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3044 12:18:11.081256 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3045 12:18:11.084997 == TX Byte 1 ==
3046 12:18:11.087917 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3047 12:18:11.091584 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3048 12:18:11.091714
3049 12:18:11.094526 [DATLAT]
3050 12:18:11.094656 Freq=1200, CH0 RK1
3051 12:18:11.094778
3052 12:18:11.098228 DATLAT Default: 0xd
3053 12:18:11.098313 0, 0xFFFF, sum = 0
3054 12:18:11.101308 1, 0xFFFF, sum = 0
3055 12:18:11.101391 2, 0xFFFF, sum = 0
3056 12:18:11.104602 3, 0xFFFF, sum = 0
3057 12:18:11.104684 4, 0xFFFF, sum = 0
3058 12:18:11.108451 5, 0xFFFF, sum = 0
3059 12:18:11.108533 6, 0xFFFF, sum = 0
3060 12:18:11.111269 7, 0xFFFF, sum = 0
3061 12:18:11.111352 8, 0xFFFF, sum = 0
3062 12:18:11.114857 9, 0xFFFF, sum = 0
3063 12:18:11.114939 10, 0xFFFF, sum = 0
3064 12:18:11.118111 11, 0xFFFF, sum = 0
3065 12:18:11.118193 12, 0x0, sum = 1
3066 12:18:11.121721 13, 0x0, sum = 2
3067 12:18:11.121803 14, 0x0, sum = 3
3068 12:18:11.125342 15, 0x0, sum = 4
3069 12:18:11.125424 best_step = 13
3070 12:18:11.125489
3071 12:18:11.125548 ==
3072 12:18:11.128251 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 12:18:11.131548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 12:18:11.135363 ==
3075 12:18:11.135444 RX Vref Scan: 0
3076 12:18:11.135508
3077 12:18:11.138743 RX Vref 0 -> 0, step: 1
3078 12:18:11.138890
3079 12:18:11.138971 RX Delay -21 -> 252, step: 4
3080 12:18:11.145973 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3081 12:18:11.149289 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3082 12:18:11.152865 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3083 12:18:11.155965 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3084 12:18:11.159540 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3085 12:18:11.165995 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3086 12:18:11.169474 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3087 12:18:11.173396 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3088 12:18:11.176445 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3089 12:18:11.179428 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3090 12:18:11.182930 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3091 12:18:11.189778 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3092 12:18:11.193314 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3093 12:18:11.196345 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3094 12:18:11.199887 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3095 12:18:11.203265 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3096 12:18:11.206867 ==
3097 12:18:11.206948 Dram Type= 6, Freq= 0, CH_0, rank 1
3098 12:18:11.213529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 12:18:11.213610 ==
3100 12:18:11.213675 DQS Delay:
3101 12:18:11.216719 DQS0 = 0, DQS1 = 0
3102 12:18:11.216800 DQM Delay:
3103 12:18:11.220068 DQM0 = 114, DQM1 = 104
3104 12:18:11.220148 DQ Delay:
3105 12:18:11.223755 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3106 12:18:11.226762 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3107 12:18:11.229875 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3108 12:18:11.233396 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3109 12:18:11.233476
3110 12:18:11.233540
3111 12:18:11.243524 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3112 12:18:11.243606 CH0 RK1: MR19=403, MR18=F1
3113 12:18:11.250184 CH0_RK1: MR19=0x403, MR18=0xF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3114 12:18:11.253838 [RxdqsGatingPostProcess] freq 1200
3115 12:18:11.260237 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3116 12:18:11.260318 best DQS0 dly(2T, 0.5T) = (0, 12)
3117 12:18:11.264051 best DQS1 dly(2T, 0.5T) = (0, 12)
3118 12:18:11.267149 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3119 12:18:11.270560 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3120 12:18:11.274163 best DQS0 dly(2T, 0.5T) = (0, 11)
3121 12:18:11.277233 best DQS1 dly(2T, 0.5T) = (0, 11)
3122 12:18:11.280516 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3123 12:18:11.284151 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3124 12:18:11.287158 Pre-setting of DQS Precalculation
3125 12:18:11.290900 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3126 12:18:11.290982 ==
3127 12:18:11.293767 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 12:18:11.300960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 12:18:11.301052 ==
3130 12:18:11.304242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3131 12:18:11.311012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3132 12:18:11.319678 [CA 0] Center 38 (8~68) winsize 61
3133 12:18:11.323091 [CA 1] Center 38 (8~68) winsize 61
3134 12:18:11.326028 [CA 2] Center 35 (5~65) winsize 61
3135 12:18:11.329595 [CA 3] Center 34 (4~65) winsize 62
3136 12:18:11.333305 [CA 4] Center 34 (4~65) winsize 62
3137 12:18:11.336212 [CA 5] Center 33 (3~64) winsize 62
3138 12:18:11.336293
3139 12:18:11.339699 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3140 12:18:11.339779
3141 12:18:11.342953 [CATrainingPosCal] consider 1 rank data
3142 12:18:11.346261 u2DelayCellTimex100 = 270/100 ps
3143 12:18:11.349969 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3144 12:18:11.353191 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3145 12:18:11.356766 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3146 12:18:11.359641 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3147 12:18:11.366295 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3148 12:18:11.369673 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3149 12:18:11.369754
3150 12:18:11.373194 CA PerBit enable=1, Macro0, CA PI delay=33
3151 12:18:11.373275
3152 12:18:11.376904 [CBTSetCACLKResult] CA Dly = 33
3153 12:18:11.376985 CS Dly: 5 (0~36)
3154 12:18:11.377068 ==
3155 12:18:11.379819 Dram Type= 6, Freq= 0, CH_1, rank 1
3156 12:18:11.383169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3157 12:18:11.386327 ==
3158 12:18:11.390105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3159 12:18:11.396705 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3160 12:18:11.404743 [CA 0] Center 38 (8~68) winsize 61
3161 12:18:11.408050 [CA 1] Center 37 (8~67) winsize 60
3162 12:18:11.411670 [CA 2] Center 34 (4~65) winsize 62
3163 12:18:11.415210 [CA 3] Center 34 (4~65) winsize 62
3164 12:18:11.418230 [CA 4] Center 34 (4~65) winsize 62
3165 12:18:11.422128 [CA 5] Center 33 (3~64) winsize 62
3166 12:18:11.422210
3167 12:18:11.424995 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3168 12:18:11.425076
3169 12:18:11.428541 [CATrainingPosCal] consider 2 rank data
3170 12:18:11.431684 u2DelayCellTimex100 = 270/100 ps
3171 12:18:11.435052 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3172 12:18:11.438628 CA1 delay=37 (8~67),Diff = 4 PI (19 cell)
3173 12:18:11.441929 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3174 12:18:11.448585 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3175 12:18:11.452151 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3176 12:18:11.455134 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3177 12:18:11.455216
3178 12:18:11.458657 CA PerBit enable=1, Macro0, CA PI delay=33
3179 12:18:11.458781
3180 12:18:11.461821 [CBTSetCACLKResult] CA Dly = 33
3181 12:18:11.461902 CS Dly: 7 (0~40)
3182 12:18:11.461966
3183 12:18:11.465267 ----->DramcWriteLeveling(PI) begin...
3184 12:18:11.465349 ==
3185 12:18:11.468499 Dram Type= 6, Freq= 0, CH_1, rank 0
3186 12:18:11.475206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3187 12:18:11.475288 ==
3188 12:18:11.478697 Write leveling (Byte 0): 27 => 27
3189 12:18:11.478803 Write leveling (Byte 1): 29 => 29
3190 12:18:11.482330 DramcWriteLeveling(PI) end<-----
3191 12:18:11.482411
3192 12:18:11.482474 ==
3193 12:18:11.485267 Dram Type= 6, Freq= 0, CH_1, rank 0
3194 12:18:11.492175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3195 12:18:11.492256 ==
3196 12:18:11.495516 [Gating] SW mode calibration
3197 12:18:11.502383 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3198 12:18:11.505677 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3199 12:18:11.512367 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3200 12:18:11.515752 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 12:18:11.518784 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 12:18:11.522691 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3203 12:18:11.528960 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 12:18:11.532411 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 12:18:11.536117 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 12:18:11.542664 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3207 12:18:11.546493 1 0 0 | B1->B0 | 2626 2828 | 0 0 | (1 0) (1 0)
3208 12:18:11.549518 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 12:18:11.556061 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 12:18:11.559620 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 12:18:11.562638 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 12:18:11.569274 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 12:18:11.572823 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 12:18:11.576302 1 0 28 | B1->B0 | 2a2a 2424 | 0 0 | (1 1) (0 0)
3215 12:18:11.579851 1 1 0 | B1->B0 | 4242 3838 | 0 0 | (0 0) (0 0)
3216 12:18:11.586195 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 12:18:11.589866 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 12:18:11.592775 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 12:18:11.599935 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 12:18:11.602905 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 12:18:11.606669 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 12:18:11.613024 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 12:18:11.616460 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3224 12:18:11.620061 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 12:18:11.626544 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:18:11.630154 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 12:18:11.633241 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 12:18:11.636640 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 12:18:11.643471 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 12:18:11.647029 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:18:11.650180 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:18:11.656774 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:18:11.660251 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:18:11.663821 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:18:11.670532 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 12:18:11.673674 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 12:18:11.677325 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 12:18:11.680849 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3239 12:18:11.687287 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3240 12:18:11.690694 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3241 12:18:11.694411 Total UI for P1: 0, mck2ui 16
3242 12:18:11.697283 best dqsien dly found for B0: ( 1, 3, 30)
3243 12:18:11.700409 Total UI for P1: 0, mck2ui 16
3244 12:18:11.703913 best dqsien dly found for B1: ( 1, 4, 0)
3245 12:18:11.707648 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3246 12:18:11.710640 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3247 12:18:11.710769
3248 12:18:11.714267 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3249 12:18:11.717616 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3250 12:18:11.721173 [Gating] SW calibration Done
3251 12:18:11.721254 ==
3252 12:18:11.724264 Dram Type= 6, Freq= 0, CH_1, rank 0
3253 12:18:11.728093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3254 12:18:11.728175 ==
3255 12:18:11.731245 RX Vref Scan: 0
3256 12:18:11.731326
3257 12:18:11.734323 RX Vref 0 -> 0, step: 1
3258 12:18:11.734403
3259 12:18:11.734467 RX Delay -40 -> 252, step: 8
3260 12:18:11.741470 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3261 12:18:11.744747 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3262 12:18:11.747594 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3263 12:18:11.751441 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3264 12:18:11.754490 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3265 12:18:11.758057 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3266 12:18:11.764661 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3267 12:18:11.767817 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3268 12:18:11.771352 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3269 12:18:11.775075 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3270 12:18:11.777918 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3271 12:18:11.785125 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3272 12:18:11.787980 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3273 12:18:11.791892 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3274 12:18:11.794959 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3275 12:18:11.798086 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3276 12:18:11.801825 ==
3277 12:18:11.801917 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 12:18:11.808373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 12:18:11.808484 ==
3280 12:18:11.808572 DQS Delay:
3281 12:18:11.811807 DQS0 = 0, DQS1 = 0
3282 12:18:11.811916 DQM Delay:
3283 12:18:11.815478 DQM0 = 116, DQM1 = 108
3284 12:18:11.815599 DQ Delay:
3285 12:18:11.818317 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3286 12:18:11.822104 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3287 12:18:11.825352 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3288 12:18:11.828622 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3289 12:18:11.828794
3290 12:18:11.828929
3291 12:18:11.829053 ==
3292 12:18:11.832285 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 12:18:11.835557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 12:18:11.838589 ==
3295 12:18:11.838864
3296 12:18:11.839055
3297 12:18:11.839228 TX Vref Scan disable
3298 12:18:11.842279 == TX Byte 0 ==
3299 12:18:11.845773 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3300 12:18:11.849128 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3301 12:18:11.852248 == TX Byte 1 ==
3302 12:18:11.855743 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3303 12:18:11.859180 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3304 12:18:11.859597 ==
3305 12:18:11.862272 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 12:18:11.869309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 12:18:11.869749 ==
3308 12:18:11.879547 TX Vref=22, minBit 0, minWin=25, winSum=410
3309 12:18:11.883217 TX Vref=24, minBit 1, minWin=25, winSum=413
3310 12:18:11.886079 TX Vref=26, minBit 1, minWin=26, winSum=422
3311 12:18:11.889765 TX Vref=28, minBit 1, minWin=26, winSum=426
3312 12:18:11.892828 TX Vref=30, minBit 1, minWin=26, winSum=426
3313 12:18:11.896588 TX Vref=32, minBit 3, minWin=25, winSum=425
3314 12:18:11.903237 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
3315 12:18:11.903655
3316 12:18:11.906684 Final TX Range 1 Vref 28
3317 12:18:11.907145
3318 12:18:11.907472 ==
3319 12:18:11.909620 Dram Type= 6, Freq= 0, CH_1, rank 0
3320 12:18:11.913127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3321 12:18:11.913550 ==
3322 12:18:11.913878
3323 12:18:11.914181
3324 12:18:11.916607 TX Vref Scan disable
3325 12:18:11.920127 == TX Byte 0 ==
3326 12:18:11.923101 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3327 12:18:11.926710 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3328 12:18:11.930229 == TX Byte 1 ==
3329 12:18:11.933272 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3330 12:18:11.936469 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3331 12:18:11.936886
3332 12:18:11.940312 [DATLAT]
3333 12:18:11.940726 Freq=1200, CH1 RK0
3334 12:18:11.941056
3335 12:18:11.943278 DATLAT Default: 0xd
3336 12:18:11.943692 0, 0xFFFF, sum = 0
3337 12:18:11.946586 1, 0xFFFF, sum = 0
3338 12:18:11.947040 2, 0xFFFF, sum = 0
3339 12:18:11.950074 3, 0xFFFF, sum = 0
3340 12:18:11.950497 4, 0xFFFF, sum = 0
3341 12:18:11.953132 5, 0xFFFF, sum = 0
3342 12:18:11.953214 6, 0xFFFF, sum = 0
3343 12:18:11.956310 7, 0xFFFF, sum = 0
3344 12:18:11.956392 8, 0xFFFF, sum = 0
3345 12:18:11.960082 9, 0xFFFF, sum = 0
3346 12:18:11.960164 10, 0xFFFF, sum = 0
3347 12:18:11.963241 11, 0xFFFF, sum = 0
3348 12:18:11.963323 12, 0x0, sum = 1
3349 12:18:11.966610 13, 0x0, sum = 2
3350 12:18:11.966692 14, 0x0, sum = 3
3351 12:18:11.969699 15, 0x0, sum = 4
3352 12:18:11.969781 best_step = 13
3353 12:18:11.969844
3354 12:18:11.969904 ==
3355 12:18:11.973058 Dram Type= 6, Freq= 0, CH_1, rank 0
3356 12:18:11.979738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3357 12:18:11.979821 ==
3358 12:18:11.979885 RX Vref Scan: 1
3359 12:18:11.979944
3360 12:18:11.983103 Set Vref Range= 32 -> 127
3361 12:18:11.983183
3362 12:18:11.986554 RX Vref 32 -> 127, step: 1
3363 12:18:11.986660
3364 12:18:11.986773 RX Delay -21 -> 252, step: 4
3365 12:18:11.986848
3366 12:18:11.989607 Set Vref, RX VrefLevel [Byte0]: 32
3367 12:18:11.993193 [Byte1]: 32
3368 12:18:11.997538
3369 12:18:11.997618 Set Vref, RX VrefLevel [Byte0]: 33
3370 12:18:12.001014 [Byte1]: 33
3371 12:18:12.005271
3372 12:18:12.005351 Set Vref, RX VrefLevel [Byte0]: 34
3373 12:18:12.008524 [Byte1]: 34
3374 12:18:12.013276
3375 12:18:12.013356 Set Vref, RX VrefLevel [Byte0]: 35
3376 12:18:12.016385 [Byte1]: 35
3377 12:18:12.020863
3378 12:18:12.020943 Set Vref, RX VrefLevel [Byte0]: 36
3379 12:18:12.024396 [Byte1]: 36
3380 12:18:12.029164
3381 12:18:12.029244 Set Vref, RX VrefLevel [Byte0]: 37
3382 12:18:12.032327 [Byte1]: 37
3383 12:18:12.036965
3384 12:18:12.037045 Set Vref, RX VrefLevel [Byte0]: 38
3385 12:18:12.040029 [Byte1]: 38
3386 12:18:12.044987
3387 12:18:12.045066 Set Vref, RX VrefLevel [Byte0]: 39
3388 12:18:12.048055 [Byte1]: 39
3389 12:18:12.052914
3390 12:18:12.052994 Set Vref, RX VrefLevel [Byte0]: 40
3391 12:18:12.056579 [Byte1]: 40
3392 12:18:12.060846
3393 12:18:12.060927 Set Vref, RX VrefLevel [Byte0]: 41
3394 12:18:12.064136 [Byte1]: 41
3395 12:18:12.068516
3396 12:18:12.068596 Set Vref, RX VrefLevel [Byte0]: 42
3397 12:18:12.072078 [Byte1]: 42
3398 12:18:12.076958
3399 12:18:12.077039 Set Vref, RX VrefLevel [Byte0]: 43
3400 12:18:12.079844 [Byte1]: 43
3401 12:18:12.084427
3402 12:18:12.084507 Set Vref, RX VrefLevel [Byte0]: 44
3403 12:18:12.087829 [Byte1]: 44
3404 12:18:12.092373
3405 12:18:12.092454 Set Vref, RX VrefLevel [Byte0]: 45
3406 12:18:12.095526 [Byte1]: 45
3407 12:18:12.100191
3408 12:18:12.100271 Set Vref, RX VrefLevel [Byte0]: 46
3409 12:18:12.104089 [Byte1]: 46
3410 12:18:12.108198
3411 12:18:12.108279 Set Vref, RX VrefLevel [Byte0]: 47
3412 12:18:12.111662 [Byte1]: 47
3413 12:18:12.116249
3414 12:18:12.116329 Set Vref, RX VrefLevel [Byte0]: 48
3415 12:18:12.119174 [Byte1]: 48
3416 12:18:12.124642
3417 12:18:12.124722 Set Vref, RX VrefLevel [Byte0]: 49
3418 12:18:12.127424 [Byte1]: 49
3419 12:18:12.131999
3420 12:18:12.132080 Set Vref, RX VrefLevel [Byte0]: 50
3421 12:18:12.135055 [Byte1]: 50
3422 12:18:12.139879
3423 12:18:12.139959 Set Vref, RX VrefLevel [Byte0]: 51
3424 12:18:12.143333 [Byte1]: 51
3425 12:18:12.147801
3426 12:18:12.147882 Set Vref, RX VrefLevel [Byte0]: 52
3427 12:18:12.151393 [Byte1]: 52
3428 12:18:12.155517
3429 12:18:12.155605 Set Vref, RX VrefLevel [Byte0]: 53
3430 12:18:12.159032 [Byte1]: 53
3431 12:18:12.164117
3432 12:18:12.164198 Set Vref, RX VrefLevel [Byte0]: 54
3433 12:18:12.166921 [Byte1]: 54
3434 12:18:12.171382
3435 12:18:12.171463 Set Vref, RX VrefLevel [Byte0]: 55
3436 12:18:12.174785 [Byte1]: 55
3437 12:18:12.179747
3438 12:18:12.179843 Set Vref, RX VrefLevel [Byte0]: 56
3439 12:18:12.182893 [Byte1]: 56
3440 12:18:12.187877
3441 12:18:12.187958 Set Vref, RX VrefLevel [Byte0]: 57
3442 12:18:12.190684 [Byte1]: 57
3443 12:18:12.195390
3444 12:18:12.195471 Set Vref, RX VrefLevel [Byte0]: 58
3445 12:18:12.198692 [Byte1]: 58
3446 12:18:12.203606
3447 12:18:12.203687 Set Vref, RX VrefLevel [Byte0]: 59
3448 12:18:12.206649 [Byte1]: 59
3449 12:18:12.210969
3450 12:18:12.211051 Set Vref, RX VrefLevel [Byte0]: 60
3451 12:18:12.214726 [Byte1]: 60
3452 12:18:12.218978
3453 12:18:12.219085 Set Vref, RX VrefLevel [Byte0]: 61
3454 12:18:12.222704 [Byte1]: 61
3455 12:18:12.226999
3456 12:18:12.227081 Set Vref, RX VrefLevel [Byte0]: 62
3457 12:18:12.230517 [Byte1]: 62
3458 12:18:12.234799
3459 12:18:12.234880 Set Vref, RX VrefLevel [Byte0]: 63
3460 12:18:12.238747 [Byte1]: 63
3461 12:18:12.242854
3462 12:18:12.242962 Set Vref, RX VrefLevel [Byte0]: 64
3463 12:18:12.246333 [Byte1]: 64
3464 12:18:12.250687
3465 12:18:12.250794 Set Vref, RX VrefLevel [Byte0]: 65
3466 12:18:12.254353 [Byte1]: 65
3467 12:18:12.258671
3468 12:18:12.258775 Set Vref, RX VrefLevel [Byte0]: 66
3469 12:18:12.262412 [Byte1]: 66
3470 12:18:12.266697
3471 12:18:12.266808 Set Vref, RX VrefLevel [Byte0]: 67
3472 12:18:12.270150 [Byte1]: 67
3473 12:18:12.274473
3474 12:18:12.274553 Set Vref, RX VrefLevel [Byte0]: 68
3475 12:18:12.277854 [Byte1]: 68
3476 12:18:12.282279
3477 12:18:12.282360 Final RX Vref Byte 0 = 57 to rank0
3478 12:18:12.285753 Final RX Vref Byte 1 = 52 to rank0
3479 12:18:12.289454 Final RX Vref Byte 0 = 57 to rank1
3480 12:18:12.292861 Final RX Vref Byte 1 = 52 to rank1==
3481 12:18:12.295797 Dram Type= 6, Freq= 0, CH_1, rank 0
3482 12:18:12.299540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 12:18:12.302643 ==
3484 12:18:12.302747 DQS Delay:
3485 12:18:12.302828 DQS0 = 0, DQS1 = 0
3486 12:18:12.305939 DQM Delay:
3487 12:18:12.306019 DQM0 = 116, DQM1 = 109
3488 12:18:12.309602 DQ Delay:
3489 12:18:12.312921 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3490 12:18:12.315926 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3491 12:18:12.319605 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3492 12:18:12.323441 DQ12 =116, DQ13 =118, DQ14 =116, DQ15 =112
3493 12:18:12.323522
3494 12:18:12.323585
3495 12:18:12.330012 [DQSOSCAuto] RK0, (LSB)MR18= 0xe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3496 12:18:12.332934 CH1 RK0: MR19=403, MR18=E5
3497 12:18:12.339855 CH1_RK0: MR19=0x403, MR18=0xE5, DQSOSC=410, MR23=63, INC=39, DEC=26
3498 12:18:12.339936
3499 12:18:12.342938 ----->DramcWriteLeveling(PI) begin...
3500 12:18:12.343021 ==
3501 12:18:12.346528 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 12:18:12.350152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 12:18:12.350233 ==
3504 12:18:12.353049 Write leveling (Byte 0): 28 => 28
3505 12:18:12.356682 Write leveling (Byte 1): 29 => 29
3506 12:18:12.360255 DramcWriteLeveling(PI) end<-----
3507 12:18:12.360335
3508 12:18:12.360400 ==
3509 12:18:12.363319 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 12:18:12.366373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 12:18:12.366457 ==
3512 12:18:12.370078 [Gating] SW mode calibration
3513 12:18:12.376932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3514 12:18:12.383300 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3515 12:18:12.386733 0 15 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
3516 12:18:12.390155 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 12:18:12.397015 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 12:18:12.400640 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 12:18:12.403483 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 12:18:12.410313 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3521 12:18:12.413497 0 15 24 | B1->B0 | 3333 2525 | 1 0 | (1 1) (1 0)
3522 12:18:12.417501 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3523 12:18:12.420360 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 12:18:12.426983 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 12:18:12.430689 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 12:18:12.433973 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 12:18:12.440737 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 12:18:12.443855 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 12:18:12.447285 1 0 24 | B1->B0 | 2525 4040 | 0 0 | (0 0) (0 0)
3530 12:18:12.453996 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)
3531 12:18:12.457075 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 12:18:12.460675 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 12:18:12.467339 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 12:18:12.471074 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 12:18:12.473983 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 12:18:12.477642 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 12:18:12.484541 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3538 12:18:12.487678 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3539 12:18:12.491052 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 12:18:12.497318 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 12:18:12.501022 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 12:18:12.504101 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 12:18:12.510911 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:18:12.513949 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 12:18:12.517341 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:18:12.524084 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 12:18:12.527561 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 12:18:12.531229 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 12:18:12.537855 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 12:18:12.540685 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 12:18:12.544142 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 12:18:12.551018 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3553 12:18:12.554372 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3554 12:18:12.557400 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3555 12:18:12.561087 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 12:18:12.564301 Total UI for P1: 0, mck2ui 16
3557 12:18:12.567379 best dqsien dly found for B0: ( 1, 3, 24)
3558 12:18:12.571055 Total UI for P1: 0, mck2ui 16
3559 12:18:12.574515 best dqsien dly found for B1: ( 1, 3, 28)
3560 12:18:12.577821 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3561 12:18:12.581435 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3562 12:18:12.581517
3563 12:18:12.588071 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3564 12:18:12.591124 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3565 12:18:12.594373 [Gating] SW calibration Done
3566 12:18:12.594455 ==
3567 12:18:12.597967 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 12:18:12.601314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 12:18:12.601396 ==
3570 12:18:12.601461 RX Vref Scan: 0
3571 12:18:12.601522
3572 12:18:12.604579 RX Vref 0 -> 0, step: 1
3573 12:18:12.604660
3574 12:18:12.607953 RX Delay -40 -> 252, step: 8
3575 12:18:12.610992 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3576 12:18:12.614500 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3577 12:18:12.618010 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3578 12:18:12.624263 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3579 12:18:12.627576 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3580 12:18:12.631267 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3581 12:18:12.634569 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3582 12:18:12.638181 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3583 12:18:12.644744 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3584 12:18:12.647786 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3585 12:18:12.651330 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3586 12:18:12.654982 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3587 12:18:12.657904 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3588 12:18:12.664449 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3589 12:18:12.667931 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3590 12:18:12.671572 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3591 12:18:12.671655 ==
3592 12:18:12.674688 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 12:18:12.678336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 12:18:12.678418 ==
3595 12:18:12.681211 DQS Delay:
3596 12:18:12.681292 DQS0 = 0, DQS1 = 0
3597 12:18:12.684903 DQM Delay:
3598 12:18:12.684985 DQM0 = 113, DQM1 = 110
3599 12:18:12.685050 DQ Delay:
3600 12:18:12.688153 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3601 12:18:12.694673 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3602 12:18:12.698017 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =99
3603 12:18:12.701476 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3604 12:18:12.701557
3605 12:18:12.701621
3606 12:18:12.701681 ==
3607 12:18:12.705236 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 12:18:12.708309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 12:18:12.708391 ==
3610 12:18:12.708455
3611 12:18:12.708515
3612 12:18:12.711237 TX Vref Scan disable
3613 12:18:12.711319 == TX Byte 0 ==
3614 12:18:12.718193 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3615 12:18:12.721709 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3616 12:18:12.721791 == TX Byte 1 ==
3617 12:18:12.728433 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3618 12:18:12.732255 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3619 12:18:12.732337 ==
3620 12:18:12.734948 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 12:18:12.738121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 12:18:12.738215 ==
3623 12:18:12.751082 TX Vref=22, minBit 1, minWin=25, winSum=417
3624 12:18:12.754098 TX Vref=24, minBit 3, minWin=25, winSum=425
3625 12:18:12.757535 TX Vref=26, minBit 2, minWin=26, winSum=431
3626 12:18:12.761176 TX Vref=28, minBit 2, minWin=26, winSum=431
3627 12:18:12.764222 TX Vref=30, minBit 2, minWin=26, winSum=430
3628 12:18:12.767917 TX Vref=32, minBit 3, minWin=26, winSum=431
3629 12:18:12.774373 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 26
3630 12:18:12.774644
3631 12:18:12.778635 Final TX Range 1 Vref 26
3632 12:18:12.778944
3633 12:18:12.779210 ==
3634 12:18:12.781683 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 12:18:12.785291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 12:18:12.785589 ==
3637 12:18:12.785821
3638 12:18:12.786036
3639 12:18:12.788488 TX Vref Scan disable
3640 12:18:12.791403 == TX Byte 0 ==
3641 12:18:12.795127 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3642 12:18:12.798039 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3643 12:18:12.801792 == TX Byte 1 ==
3644 12:18:12.804833 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3645 12:18:12.808552 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3646 12:18:12.808971
3647 12:18:12.811591 [DATLAT]
3648 12:18:12.812012 Freq=1200, CH1 RK1
3649 12:18:12.812492
3650 12:18:12.815284 DATLAT Default: 0xd
3651 12:18:12.815700 0, 0xFFFF, sum = 0
3652 12:18:12.818747 1, 0xFFFF, sum = 0
3653 12:18:12.819260 2, 0xFFFF, sum = 0
3654 12:18:12.821582 3, 0xFFFF, sum = 0
3655 12:18:12.822002 4, 0xFFFF, sum = 0
3656 12:18:12.825397 5, 0xFFFF, sum = 0
3657 12:18:12.825820 6, 0xFFFF, sum = 0
3658 12:18:12.828475 7, 0xFFFF, sum = 0
3659 12:18:12.828898 8, 0xFFFF, sum = 0
3660 12:18:12.832005 9, 0xFFFF, sum = 0
3661 12:18:12.832427 10, 0xFFFF, sum = 0
3662 12:18:12.834971 11, 0xFFFF, sum = 0
3663 12:18:12.835395 12, 0x0, sum = 1
3664 12:18:12.838361 13, 0x0, sum = 2
3665 12:18:12.838827 14, 0x0, sum = 3
3666 12:18:12.841925 15, 0x0, sum = 4
3667 12:18:12.842369 best_step = 13
3668 12:18:12.842705
3669 12:18:12.843108 ==
3670 12:18:12.845288 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 12:18:12.852101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 12:18:12.852650 ==
3673 12:18:12.853068 RX Vref Scan: 0
3674 12:18:12.853413
3675 12:18:12.855521 RX Vref 0 -> 0, step: 1
3676 12:18:12.856071
3677 12:18:12.858597 RX Delay -21 -> 252, step: 4
3678 12:18:12.861873 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3679 12:18:12.865412 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3680 12:18:12.868387 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3681 12:18:12.875307 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3682 12:18:12.878392 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3683 12:18:12.882059 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3684 12:18:12.885060 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3685 12:18:12.888736 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3686 12:18:12.895556 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3687 12:18:12.898585 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3688 12:18:12.902274 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3689 12:18:12.905359 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3690 12:18:12.908977 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3691 12:18:12.912650 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3692 12:18:12.919499 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3693 12:18:12.922404 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3694 12:18:12.922962 ==
3695 12:18:12.925468 Dram Type= 6, Freq= 0, CH_1, rank 1
3696 12:18:12.928991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3697 12:18:12.929414 ==
3698 12:18:12.932402 DQS Delay:
3699 12:18:12.932899 DQS0 = 0, DQS1 = 0
3700 12:18:12.933281 DQM Delay:
3701 12:18:12.935588 DQM0 = 113, DQM1 = 109
3702 12:18:12.936052 DQ Delay:
3703 12:18:12.939189 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3704 12:18:12.942317 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3705 12:18:12.945452 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3706 12:18:12.952092 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3707 12:18:12.952518
3708 12:18:12.952897
3709 12:18:12.958904 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc03, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 411 ps
3710 12:18:12.962432 CH1 RK1: MR19=304, MR18=FC03
3711 12:18:12.969135 CH1_RK1: MR19=0x304, MR18=0xFC03, DQSOSC=408, MR23=63, INC=39, DEC=26
3712 12:18:12.972619 [RxdqsGatingPostProcess] freq 1200
3713 12:18:12.975876 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3714 12:18:12.979308 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 12:18:12.982462 best DQS1 dly(2T, 0.5T) = (0, 12)
3716 12:18:12.985942 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 12:18:12.989431 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3718 12:18:12.992355 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 12:18:12.995963 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 12:18:12.998853 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 12:18:13.002425 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 12:18:13.005660 Pre-setting of DQS Precalculation
3723 12:18:13.009245 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3724 12:18:13.015528 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3725 12:18:13.025756 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3726 12:18:13.026183
3727 12:18:13.026546
3728 12:18:13.029041 [Calibration Summary] 2400 Mbps
3729 12:18:13.029482 CH 0, Rank 0
3730 12:18:13.032210 SW Impedance : PASS
3731 12:18:13.032646 DUTY Scan : NO K
3732 12:18:13.035658 ZQ Calibration : PASS
3733 12:18:13.036117 Jitter Meter : NO K
3734 12:18:13.039140 CBT Training : PASS
3735 12:18:13.042613 Write leveling : PASS
3736 12:18:13.043143 RX DQS gating : PASS
3737 12:18:13.045846 RX DQ/DQS(RDDQC) : PASS
3738 12:18:13.049487 TX DQ/DQS : PASS
3739 12:18:13.049908 RX DATLAT : PASS
3740 12:18:13.052780 RX DQ/DQS(Engine): PASS
3741 12:18:13.055735 TX OE : NO K
3742 12:18:13.056161 All Pass.
3743 12:18:13.056521
3744 12:18:13.056831 CH 0, Rank 1
3745 12:18:13.059318 SW Impedance : PASS
3746 12:18:13.062425 DUTY Scan : NO K
3747 12:18:13.062913 ZQ Calibration : PASS
3748 12:18:13.065821 Jitter Meter : NO K
3749 12:18:13.069536 CBT Training : PASS
3750 12:18:13.069981 Write leveling : PASS
3751 12:18:13.072369 RX DQS gating : PASS
3752 12:18:13.072788 RX DQ/DQS(RDDQC) : PASS
3753 12:18:13.076339 TX DQ/DQS : PASS
3754 12:18:13.079040 RX DATLAT : PASS
3755 12:18:13.079525 RX DQ/DQS(Engine): PASS
3756 12:18:13.082514 TX OE : NO K
3757 12:18:13.083093 All Pass.
3758 12:18:13.083487
3759 12:18:13.086263 CH 1, Rank 0
3760 12:18:13.086641 SW Impedance : PASS
3761 12:18:13.089427 DUTY Scan : NO K
3762 12:18:13.092811 ZQ Calibration : PASS
3763 12:18:13.093247 Jitter Meter : NO K
3764 12:18:13.096394 CBT Training : PASS
3765 12:18:13.099606 Write leveling : PASS
3766 12:18:13.100050 RX DQS gating : PASS
3767 12:18:13.102784 RX DQ/DQS(RDDQC) : PASS
3768 12:18:13.103204 TX DQ/DQS : PASS
3769 12:18:13.106017 RX DATLAT : PASS
3770 12:18:13.109647 RX DQ/DQS(Engine): PASS
3771 12:18:13.110064 TX OE : NO K
3772 12:18:13.112631 All Pass.
3773 12:18:13.113077
3774 12:18:13.113430 CH 1, Rank 1
3775 12:18:13.115972 SW Impedance : PASS
3776 12:18:13.116541 DUTY Scan : NO K
3777 12:18:13.119385 ZQ Calibration : PASS
3778 12:18:13.122650 Jitter Meter : NO K
3779 12:18:13.123247 CBT Training : PASS
3780 12:18:13.126162 Write leveling : PASS
3781 12:18:13.129271 RX DQS gating : PASS
3782 12:18:13.129569 RX DQ/DQS(RDDQC) : PASS
3783 12:18:13.132931 TX DQ/DQS : PASS
3784 12:18:13.135947 RX DATLAT : PASS
3785 12:18:13.136186 RX DQ/DQS(Engine): PASS
3786 12:18:13.139028 TX OE : NO K
3787 12:18:13.139301 All Pass.
3788 12:18:13.139527
3789 12:18:13.142526 DramC Write-DBI off
3790 12:18:13.145406 PER_BANK_REFRESH: Hybrid Mode
3791 12:18:13.145632 TX_TRACKING: ON
3792 12:18:13.155984 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3793 12:18:13.159297 [FAST_K] Save calibration result to emmc
3794 12:18:13.162495 dramc_set_vcore_voltage set vcore to 650000
3795 12:18:13.165891 Read voltage for 600, 5
3796 12:18:13.166114 Vio18 = 0
3797 12:18:13.166292 Vcore = 650000
3798 12:18:13.168968 Vdram = 0
3799 12:18:13.169250 Vddq = 0
3800 12:18:13.169514 Vmddr = 0
3801 12:18:13.175723 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3802 12:18:13.179528 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3803 12:18:13.182526 MEM_TYPE=3, freq_sel=19
3804 12:18:13.185946 sv_algorithm_assistance_LP4_1600
3805 12:18:13.189159 ============ PULL DRAM RESETB DOWN ============
3806 12:18:13.192299 ========== PULL DRAM RESETB DOWN end =========
3807 12:18:13.199096 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3808 12:18:13.202746 ===================================
3809 12:18:13.203119 LPDDR4 DRAM CONFIGURATION
3810 12:18:13.205618 ===================================
3811 12:18:13.209138 EX_ROW_EN[0] = 0x0
3812 12:18:13.212635 EX_ROW_EN[1] = 0x0
3813 12:18:13.212958 LP4Y_EN = 0x0
3814 12:18:13.215879 WORK_FSP = 0x0
3815 12:18:13.216167 WL = 0x2
3816 12:18:13.219041 RL = 0x2
3817 12:18:13.219330 BL = 0x2
3818 12:18:13.222562 RPST = 0x0
3819 12:18:13.222984 RD_PRE = 0x0
3820 12:18:13.225660 WR_PRE = 0x1
3821 12:18:13.226038 WR_PST = 0x0
3822 12:18:13.229370 DBI_WR = 0x0
3823 12:18:13.229653 DBI_RD = 0x0
3824 12:18:13.232397 OTF = 0x1
3825 12:18:13.235677 ===================================
3826 12:18:13.239327 ===================================
3827 12:18:13.239660 ANA top config
3828 12:18:13.242782 ===================================
3829 12:18:13.245827 DLL_ASYNC_EN = 0
3830 12:18:13.249486 ALL_SLAVE_EN = 1
3831 12:18:13.249772 NEW_RANK_MODE = 1
3832 12:18:13.252492 DLL_IDLE_MODE = 1
3833 12:18:13.256082 LP45_APHY_COMB_EN = 1
3834 12:18:13.259049 TX_ODT_DIS = 1
3835 12:18:13.259335 NEW_8X_MODE = 1
3836 12:18:13.262482 ===================================
3837 12:18:13.265777 ===================================
3838 12:18:13.269375 data_rate = 1200
3839 12:18:13.272510 CKR = 1
3840 12:18:13.275943 DQ_P2S_RATIO = 8
3841 12:18:13.279307 ===================================
3842 12:18:13.282670 CA_P2S_RATIO = 8
3843 12:18:13.285889 DQ_CA_OPEN = 0
3844 12:18:13.286166 DQ_SEMI_OPEN = 0
3845 12:18:13.289479 CA_SEMI_OPEN = 0
3846 12:18:13.293137 CA_FULL_RATE = 0
3847 12:18:13.296144 DQ_CKDIV4_EN = 1
3848 12:18:13.299303 CA_CKDIV4_EN = 1
3849 12:18:13.303082 CA_PREDIV_EN = 0
3850 12:18:13.303389 PH8_DLY = 0
3851 12:18:13.305812 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3852 12:18:13.309447 DQ_AAMCK_DIV = 4
3853 12:18:13.313281 CA_AAMCK_DIV = 4
3854 12:18:13.316252 CA_ADMCK_DIV = 4
3855 12:18:13.316579 DQ_TRACK_CA_EN = 0
3856 12:18:13.319580 CA_PICK = 600
3857 12:18:13.322814 CA_MCKIO = 600
3858 12:18:13.326003 MCKIO_SEMI = 0
3859 12:18:13.329854 PLL_FREQ = 2288
3860 12:18:13.332824 DQ_UI_PI_RATIO = 32
3861 12:18:13.336364 CA_UI_PI_RATIO = 0
3862 12:18:13.339576 ===================================
3863 12:18:13.342578 ===================================
3864 12:18:13.342947 memory_type:LPDDR4
3865 12:18:13.346395 GP_NUM : 10
3866 12:18:13.349228 SRAM_EN : 1
3867 12:18:13.349546 MD32_EN : 0
3868 12:18:13.352990 ===================================
3869 12:18:13.355856 [ANA_INIT] >>>>>>>>>>>>>>
3870 12:18:13.359526 <<<<<< [CONFIGURE PHASE]: ANA_TX
3871 12:18:13.363201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3872 12:18:13.366258 ===================================
3873 12:18:13.369800 data_rate = 1200,PCW = 0X5800
3874 12:18:13.372880 ===================================
3875 12:18:13.376134 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3876 12:18:13.379255 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3877 12:18:13.386373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 12:18:13.389190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3879 12:18:13.392554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3880 12:18:13.396383 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3881 12:18:13.399365 [ANA_INIT] flow start
3882 12:18:13.402961 [ANA_INIT] PLL >>>>>>>>
3883 12:18:13.403043 [ANA_INIT] PLL <<<<<<<<
3884 12:18:13.406127 [ANA_INIT] MIDPI >>>>>>>>
3885 12:18:13.409499 [ANA_INIT] MIDPI <<<<<<<<
3886 12:18:13.409574 [ANA_INIT] DLL >>>>>>>>
3887 12:18:13.412465 [ANA_INIT] flow end
3888 12:18:13.415876 ============ LP4 DIFF to SE enter ============
3889 12:18:13.419144 ============ LP4 DIFF to SE exit ============
3890 12:18:13.422588 [ANA_INIT] <<<<<<<<<<<<<
3891 12:18:13.426105 [Flow] Enable top DCM control >>>>>
3892 12:18:13.429057 [Flow] Enable top DCM control <<<<<
3893 12:18:13.432727 Enable DLL master slave shuffle
3894 12:18:13.439425 ==============================================================
3895 12:18:13.439508 Gating Mode config
3896 12:18:13.446159 ==============================================================
3897 12:18:13.446240 Config description:
3898 12:18:13.456034 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3899 12:18:13.462749 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3900 12:18:13.469793 SELPH_MODE 0: By rank 1: By Phase
3901 12:18:13.472922 ==============================================================
3902 12:18:13.475915 GAT_TRACK_EN = 1
3903 12:18:13.479417 RX_GATING_MODE = 2
3904 12:18:13.483068 RX_GATING_TRACK_MODE = 2
3905 12:18:13.485964 SELPH_MODE = 1
3906 12:18:13.489717 PICG_EARLY_EN = 1
3907 12:18:13.492956 VALID_LAT_VALUE = 1
3908 12:18:13.496293 ==============================================================
3909 12:18:13.499700 Enter into Gating configuration >>>>
3910 12:18:13.502636 Exit from Gating configuration <<<<
3911 12:18:13.506207 Enter into DVFS_PRE_config >>>>>
3912 12:18:13.519793 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3913 12:18:13.522982 Exit from DVFS_PRE_config <<<<<
3914 12:18:13.526615 Enter into PICG configuration >>>>
3915 12:18:13.526691 Exit from PICG configuration <<<<
3916 12:18:13.529735 [RX_INPUT] configuration >>>>>
3917 12:18:13.533097 [RX_INPUT] configuration <<<<<
3918 12:18:13.539869 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3919 12:18:13.542919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3920 12:18:13.549534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3921 12:18:13.556127 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3922 12:18:13.562690 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3923 12:18:13.569746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3924 12:18:13.572797 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3925 12:18:13.576325 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3926 12:18:13.579497 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3927 12:18:13.586138 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3928 12:18:13.589681 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3929 12:18:13.593244 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 12:18:13.596316 ===================================
3931 12:18:13.599884 LPDDR4 DRAM CONFIGURATION
3932 12:18:13.603100 ===================================
3933 12:18:13.603182 EX_ROW_EN[0] = 0x0
3934 12:18:13.606434 EX_ROW_EN[1] = 0x0
3935 12:18:13.609820 LP4Y_EN = 0x0
3936 12:18:13.609902 WORK_FSP = 0x0
3937 12:18:13.613520 WL = 0x2
3938 12:18:13.613601 RL = 0x2
3939 12:18:13.616287 BL = 0x2
3940 12:18:13.616368 RPST = 0x0
3941 12:18:13.620141 RD_PRE = 0x0
3942 12:18:13.620251 WR_PRE = 0x1
3943 12:18:13.622953 WR_PST = 0x0
3944 12:18:13.623034 DBI_WR = 0x0
3945 12:18:13.626359 DBI_RD = 0x0
3946 12:18:13.626486 OTF = 0x1
3947 12:18:13.630094 ===================================
3948 12:18:13.633304 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3949 12:18:13.639878 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3950 12:18:13.643005 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3951 12:18:13.646686 ===================================
3952 12:18:13.650090 LPDDR4 DRAM CONFIGURATION
3953 12:18:13.652883 ===================================
3954 12:18:13.652994 EX_ROW_EN[0] = 0x10
3955 12:18:13.656264 EX_ROW_EN[1] = 0x0
3956 12:18:13.656357 LP4Y_EN = 0x0
3957 12:18:13.659982 WORK_FSP = 0x0
3958 12:18:13.660070 WL = 0x2
3959 12:18:13.662908 RL = 0x2
3960 12:18:13.662993 BL = 0x2
3961 12:18:13.666806 RPST = 0x0
3962 12:18:13.669858 RD_PRE = 0x0
3963 12:18:13.669967 WR_PRE = 0x1
3964 12:18:13.672867 WR_PST = 0x0
3965 12:18:13.672975 DBI_WR = 0x0
3966 12:18:13.676542 DBI_RD = 0x0
3967 12:18:13.676631 OTF = 0x1
3968 12:18:13.680058 ===================================
3969 12:18:13.686652 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3970 12:18:13.690165 nWR fixed to 30
3971 12:18:13.693128 [ModeRegInit_LP4] CH0 RK0
3972 12:18:13.693210 [ModeRegInit_LP4] CH0 RK1
3973 12:18:13.696812 [ModeRegInit_LP4] CH1 RK0
3974 12:18:13.699959 [ModeRegInit_LP4] CH1 RK1
3975 12:18:13.700042 match AC timing 17
3976 12:18:13.706751 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3977 12:18:13.710256 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3978 12:18:13.713377 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3979 12:18:13.719815 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3980 12:18:13.723250 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3981 12:18:13.723338 ==
3982 12:18:13.726669 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 12:18:13.730187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 12:18:13.730270 ==
3985 12:18:13.736882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3986 12:18:13.743282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3987 12:18:13.746514 [CA 0] Center 36 (6~66) winsize 61
3988 12:18:13.750017 [CA 1] Center 36 (6~66) winsize 61
3989 12:18:13.753186 [CA 2] Center 34 (4~65) winsize 62
3990 12:18:13.756738 [CA 3] Center 34 (4~65) winsize 62
3991 12:18:13.759890 [CA 4] Center 33 (3~64) winsize 62
3992 12:18:13.763146 [CA 5] Center 33 (3~64) winsize 62
3993 12:18:13.763229
3994 12:18:13.766500 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3995 12:18:13.766584
3996 12:18:13.770052 [CATrainingPosCal] consider 1 rank data
3997 12:18:13.773113 u2DelayCellTimex100 = 270/100 ps
3998 12:18:13.776478 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3999 12:18:13.780365 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4000 12:18:13.783236 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4001 12:18:13.786633 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4002 12:18:13.789802 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4003 12:18:13.793213 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4004 12:18:13.793296
4005 12:18:13.799753 CA PerBit enable=1, Macro0, CA PI delay=33
4006 12:18:13.799836
4007 12:18:13.803512 [CBTSetCACLKResult] CA Dly = 33
4008 12:18:13.803595 CS Dly: 4 (0~35)
4009 12:18:13.803659 ==
4010 12:18:13.806466 Dram Type= 6, Freq= 0, CH_0, rank 1
4011 12:18:13.810109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 12:18:13.810193 ==
4013 12:18:13.816809 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4014 12:18:13.823359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4015 12:18:13.826532 [CA 0] Center 36 (6~66) winsize 61
4016 12:18:13.829762 [CA 1] Center 35 (5~66) winsize 62
4017 12:18:13.833447 [CA 2] Center 34 (4~65) winsize 62
4018 12:18:13.836809 [CA 3] Center 34 (4~65) winsize 62
4019 12:18:13.840214 [CA 4] Center 33 (3~64) winsize 62
4020 12:18:13.843189 [CA 5] Center 33 (3~64) winsize 62
4021 12:18:13.843262
4022 12:18:13.846702 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4023 12:18:13.846809
4024 12:18:13.850233 [CATrainingPosCal] consider 2 rank data
4025 12:18:13.853472 u2DelayCellTimex100 = 270/100 ps
4026 12:18:13.856547 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4027 12:18:13.860028 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4028 12:18:13.863439 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4029 12:18:13.867200 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4030 12:18:13.870139 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4031 12:18:13.873456 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4032 12:18:13.873587
4033 12:18:13.880657 CA PerBit enable=1, Macro0, CA PI delay=33
4034 12:18:13.880787
4035 12:18:13.880885 [CBTSetCACLKResult] CA Dly = 33
4036 12:18:13.883633 CS Dly: 4 (0~35)
4037 12:18:13.883729
4038 12:18:13.887224 ----->DramcWriteLeveling(PI) begin...
4039 12:18:13.887302 ==
4040 12:18:13.890011 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 12:18:13.893978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 12:18:13.894063 ==
4043 12:18:13.896771 Write leveling (Byte 0): 31 => 31
4044 12:18:13.900361 Write leveling (Byte 1): 30 => 30
4045 12:18:13.903861 DramcWriteLeveling(PI) end<-----
4046 12:18:13.903935
4047 12:18:13.903997 ==
4048 12:18:13.906966 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 12:18:13.910126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 12:18:13.910238 ==
4051 12:18:13.913759 [Gating] SW mode calibration
4052 12:18:13.920341 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4053 12:18:13.926877 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4054 12:18:13.930172 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 12:18:13.937281 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 12:18:13.940406 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 12:18:13.944042 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4058 12:18:13.950363 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
4059 12:18:13.953786 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 12:18:13.956863 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 12:18:13.960466 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 12:18:13.967163 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 12:18:13.970287 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 12:18:13.974082 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 12:18:13.980247 0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4066 12:18:13.983513 0 10 16 | B1->B0 | 2e2e 3939 | 0 0 | (0 0) (0 0)
4067 12:18:13.987281 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 12:18:13.993949 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 12:18:13.997162 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 12:18:14.000164 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 12:18:14.007268 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 12:18:14.010316 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 12:18:14.013880 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 12:18:14.020522 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4075 12:18:14.023591 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:18:14.027097 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:18:14.033803 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:18:14.037734 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:18:14.040845 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:18:14.043700 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:18:14.050703 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:18:14.054066 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:18:14.057229 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 12:18:14.063843 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 12:18:14.067247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 12:18:14.070643 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 12:18:14.077311 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 12:18:14.080409 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 12:18:14.083957 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 12:18:14.090644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4091 12:18:14.090749 Total UI for P1: 0, mck2ui 16
4092 12:18:14.097193 best dqsien dly found for B0: ( 0, 13, 14)
4093 12:18:14.100828 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 12:18:14.103705 Total UI for P1: 0, mck2ui 16
4095 12:18:14.107175 best dqsien dly found for B1: ( 0, 13, 16)
4096 12:18:14.110792 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4097 12:18:14.113806 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4098 12:18:14.113893
4099 12:18:14.117579 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4100 12:18:14.120607 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4101 12:18:14.124032 [Gating] SW calibration Done
4102 12:18:14.124112 ==
4103 12:18:14.127065 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 12:18:14.130760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 12:18:14.130841 ==
4106 12:18:14.133733 RX Vref Scan: 0
4107 12:18:14.133807
4108 12:18:14.137328 RX Vref 0 -> 0, step: 1
4109 12:18:14.137399
4110 12:18:14.140386 RX Delay -230 -> 252, step: 16
4111 12:18:14.144045 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4112 12:18:14.146987 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4113 12:18:14.150894 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4114 12:18:14.153906 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4115 12:18:14.160966 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4116 12:18:14.164239 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4117 12:18:14.167691 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4118 12:18:14.170401 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4119 12:18:14.173853 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4120 12:18:14.180897 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4121 12:18:14.184338 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4122 12:18:14.187285 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4123 12:18:14.190964 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4124 12:18:14.197312 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4125 12:18:14.200637 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4126 12:18:14.204176 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4127 12:18:14.204250 ==
4128 12:18:14.207315 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 12:18:14.210804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 12:18:14.214182 ==
4131 12:18:14.214259 DQS Delay:
4132 12:18:14.214324 DQS0 = 0, DQS1 = 0
4133 12:18:14.217312 DQM Delay:
4134 12:18:14.217380 DQM0 = 42, DQM1 = 35
4135 12:18:14.217439 DQ Delay:
4136 12:18:14.220979 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4137 12:18:14.224079 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4138 12:18:14.227480 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4139 12:18:14.230624 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4140 12:18:14.230693
4141 12:18:14.230768
4142 12:18:14.234353 ==
4143 12:18:14.237798 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 12:18:14.240942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 12:18:14.241024 ==
4146 12:18:14.241089
4147 12:18:14.241149
4148 12:18:14.244021 TX Vref Scan disable
4149 12:18:14.244090 == TX Byte 0 ==
4150 12:18:14.247681 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4151 12:18:14.254151 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4152 12:18:14.254253 == TX Byte 1 ==
4153 12:18:14.257341 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4154 12:18:14.264492 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4155 12:18:14.264579 ==
4156 12:18:14.267551 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 12:18:14.271202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 12:18:14.271290 ==
4159 12:18:14.271357
4160 12:18:14.271417
4161 12:18:14.274159 TX Vref Scan disable
4162 12:18:14.278151 == TX Byte 0 ==
4163 12:18:14.281119 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4164 12:18:14.284725 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4165 12:18:14.287469 == TX Byte 1 ==
4166 12:18:14.290979 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4167 12:18:14.294424 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4168 12:18:14.294514
4169 12:18:14.297719 [DATLAT]
4170 12:18:14.297792 Freq=600, CH0 RK0
4171 12:18:14.297853
4172 12:18:14.301402 DATLAT Default: 0x9
4173 12:18:14.301490 0, 0xFFFF, sum = 0
4174 12:18:14.304299 1, 0xFFFF, sum = 0
4175 12:18:14.304388 2, 0xFFFF, sum = 0
4176 12:18:14.307849 3, 0xFFFF, sum = 0
4177 12:18:14.307922 4, 0xFFFF, sum = 0
4178 12:18:14.310987 5, 0xFFFF, sum = 0
4179 12:18:14.311060 6, 0xFFFF, sum = 0
4180 12:18:14.314686 7, 0xFFFF, sum = 0
4181 12:18:14.314804 8, 0x0, sum = 1
4182 12:18:14.318061 9, 0x0, sum = 2
4183 12:18:14.318179 10, 0x0, sum = 3
4184 12:18:14.321274 11, 0x0, sum = 4
4185 12:18:14.321365 best_step = 9
4186 12:18:14.321442
4187 12:18:14.321532 ==
4188 12:18:14.324673 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 12:18:14.327782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 12:18:14.327855 ==
4191 12:18:14.331193 RX Vref Scan: 1
4192 12:18:14.331265
4193 12:18:14.331325 RX Vref 0 -> 0, step: 1
4194 12:18:14.335057
4195 12:18:14.335144 RX Delay -195 -> 252, step: 8
4196 12:18:14.335225
4197 12:18:14.337922 Set Vref, RX VrefLevel [Byte0]: 54
4198 12:18:14.341072 [Byte1]: 51
4199 12:18:14.345950
4200 12:18:14.346031 Final RX Vref Byte 0 = 54 to rank0
4201 12:18:14.348870 Final RX Vref Byte 1 = 51 to rank0
4202 12:18:14.352625 Final RX Vref Byte 0 = 54 to rank1
4203 12:18:14.355836 Final RX Vref Byte 1 = 51 to rank1==
4204 12:18:14.358617 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 12:18:14.366001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 12:18:14.366079 ==
4207 12:18:14.366142 DQS Delay:
4208 12:18:14.366201 DQS0 = 0, DQS1 = 0
4209 12:18:14.368962 DQM Delay:
4210 12:18:14.369030 DQM0 = 41, DQM1 = 33
4211 12:18:14.372673 DQ Delay:
4212 12:18:14.375807 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4213 12:18:14.375876 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4214 12:18:14.378692 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4215 12:18:14.382532 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =44
4216 12:18:14.385445
4217 12:18:14.385515
4218 12:18:14.392446 [DQSOSCAuto] RK0, (LSB)MR18= 0x401e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps
4219 12:18:14.395392 CH0 RK0: MR19=808, MR18=401E
4220 12:18:14.402061 CH0_RK0: MR19=0x808, MR18=0x401E, DQSOSC=397, MR23=63, INC=166, DEC=110
4221 12:18:14.402138
4222 12:18:14.405807 ----->DramcWriteLeveling(PI) begin...
4223 12:18:14.405878 ==
4224 12:18:14.409153 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 12:18:14.412113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 12:18:14.412191 ==
4227 12:18:14.415688 Write leveling (Byte 0): 32 => 32
4228 12:18:14.419050 Write leveling (Byte 1): 30 => 30
4229 12:18:14.422390 DramcWriteLeveling(PI) end<-----
4230 12:18:14.422467
4231 12:18:14.422529 ==
4232 12:18:14.425507 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 12:18:14.428928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 12:18:14.429000 ==
4235 12:18:14.432278 [Gating] SW mode calibration
4236 12:18:14.438842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4237 12:18:14.445432 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4238 12:18:14.448725 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 12:18:14.452230 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 12:18:14.459203 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 12:18:14.462133 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4242 12:18:14.465629 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4243 12:18:14.472579 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 12:18:14.475524 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 12:18:14.479184 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 12:18:14.485996 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 12:18:14.489204 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 12:18:14.492718 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 12:18:14.496221 0 10 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
4250 12:18:14.502886 0 10 16 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
4251 12:18:14.505694 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 12:18:14.509302 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 12:18:14.516129 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 12:18:14.519091 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 12:18:14.522680 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 12:18:14.529456 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4257 12:18:14.532786 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4258 12:18:14.536475 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4259 12:18:14.542820 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:18:14.545876 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:18:14.549400 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:18:14.556148 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:18:14.559198 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:18:14.562920 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:18:14.569228 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:18:14.572742 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 12:18:14.576114 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 12:18:14.579657 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 12:18:14.586406 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 12:18:14.589461 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 12:18:14.592969 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 12:18:14.599734 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 12:18:14.603034 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4274 12:18:14.606040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4275 12:18:14.609654 Total UI for P1: 0, mck2ui 16
4276 12:18:14.612566 best dqsien dly found for B0: ( 0, 13, 12)
4277 12:18:14.619530 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 12:18:14.619609 Total UI for P1: 0, mck2ui 16
4279 12:18:14.625920 best dqsien dly found for B1: ( 0, 13, 16)
4280 12:18:14.629247 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4281 12:18:14.632837 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4282 12:18:14.632942
4283 12:18:14.636089 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4284 12:18:14.639633 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4285 12:18:14.642804 [Gating] SW calibration Done
4286 12:18:14.642877 ==
4287 12:18:14.645988 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 12:18:14.649387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 12:18:14.649491 ==
4290 12:18:14.652437 RX Vref Scan: 0
4291 12:18:14.652510
4292 12:18:14.652570 RX Vref 0 -> 0, step: 1
4293 12:18:14.652628
4294 12:18:14.656192 RX Delay -230 -> 252, step: 16
4295 12:18:14.662358 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4296 12:18:14.666033 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4297 12:18:14.669082 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4298 12:18:14.672979 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4299 12:18:14.675697 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4300 12:18:14.682261 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4301 12:18:14.685568 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4302 12:18:14.689268 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4303 12:18:14.692254 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4304 12:18:14.699160 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4305 12:18:14.702572 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4306 12:18:14.705410 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4307 12:18:14.709388 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4308 12:18:14.715680 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4309 12:18:14.719091 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4310 12:18:14.722525 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4311 12:18:14.722605 ==
4312 12:18:14.725741 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 12:18:14.729496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 12:18:14.729574 ==
4315 12:18:14.732427 DQS Delay:
4316 12:18:14.732500 DQS0 = 0, DQS1 = 0
4317 12:18:14.735434 DQM Delay:
4318 12:18:14.735506 DQM0 = 39, DQM1 = 31
4319 12:18:14.735567 DQ Delay:
4320 12:18:14.738981 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4321 12:18:14.742477 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4322 12:18:14.746208 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4323 12:18:14.749208 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4324 12:18:14.749284
4325 12:18:14.749348
4326 12:18:14.749412 ==
4327 12:18:14.752460 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 12:18:14.758879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 12:18:14.758957 ==
4330 12:18:14.759025
4331 12:18:14.759086
4332 12:18:14.759144 TX Vref Scan disable
4333 12:18:14.762967 == TX Byte 0 ==
4334 12:18:14.766039 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4335 12:18:14.769390 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4336 12:18:14.772926 == TX Byte 1 ==
4337 12:18:14.776106 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4338 12:18:14.779637 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4339 12:18:14.783009 ==
4340 12:18:14.786597 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 12:18:14.789823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 12:18:14.789900 ==
4343 12:18:14.789963
4344 12:18:14.790023
4345 12:18:14.792995 TX Vref Scan disable
4346 12:18:14.793068 == TX Byte 0 ==
4347 12:18:14.799844 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4348 12:18:14.803007 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4349 12:18:14.803085 == TX Byte 1 ==
4350 12:18:14.809732 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4351 12:18:14.812846 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4352 12:18:14.812928
4353 12:18:14.812999 [DATLAT]
4354 12:18:14.816187 Freq=600, CH0 RK1
4355 12:18:14.816262
4356 12:18:14.816325 DATLAT Default: 0x9
4357 12:18:14.819706 0, 0xFFFF, sum = 0
4358 12:18:14.819792 1, 0xFFFF, sum = 0
4359 12:18:14.823149 2, 0xFFFF, sum = 0
4360 12:18:14.823233 3, 0xFFFF, sum = 0
4361 12:18:14.826184 4, 0xFFFF, sum = 0
4362 12:18:14.826268 5, 0xFFFF, sum = 0
4363 12:18:14.830042 6, 0xFFFF, sum = 0
4364 12:18:14.830126 7, 0xFFFF, sum = 0
4365 12:18:14.832898 8, 0x0, sum = 1
4366 12:18:14.832983 9, 0x0, sum = 2
4367 12:18:14.836677 10, 0x0, sum = 3
4368 12:18:14.836761 11, 0x0, sum = 4
4369 12:18:14.839540 best_step = 9
4370 12:18:14.839622
4371 12:18:14.839688 ==
4372 12:18:14.843348 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 12:18:14.846259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 12:18:14.846348 ==
4375 12:18:14.849720 RX Vref Scan: 0
4376 12:18:14.849803
4377 12:18:14.849868 RX Vref 0 -> 0, step: 1
4378 12:18:14.849929
4379 12:18:14.853637 RX Delay -195 -> 252, step: 8
4380 12:18:14.860118 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4381 12:18:14.863363 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4382 12:18:14.866877 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4383 12:18:14.870536 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4384 12:18:14.874199 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4385 12:18:14.880588 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4386 12:18:14.883865 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4387 12:18:14.887273 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4388 12:18:14.890311 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4389 12:18:14.896868 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4390 12:18:14.900467 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4391 12:18:14.903560 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4392 12:18:14.907189 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4393 12:18:14.913721 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4394 12:18:14.917202 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4395 12:18:14.920722 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4396 12:18:14.920804 ==
4397 12:18:14.923539 Dram Type= 6, Freq= 0, CH_0, rank 1
4398 12:18:14.927101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 12:18:14.927184 ==
4400 12:18:14.930197 DQS Delay:
4401 12:18:14.930278 DQS0 = 0, DQS1 = 0
4402 12:18:14.933865 DQM Delay:
4403 12:18:14.933938 DQM0 = 39, DQM1 = 33
4404 12:18:14.933999 DQ Delay:
4405 12:18:14.937064 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4406 12:18:14.940296 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4407 12:18:14.943756 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4408 12:18:14.946859 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4409 12:18:14.946930
4410 12:18:14.946990
4411 12:18:14.957087 [DQSOSCAuto] RK1, (LSB)MR18= 0x492a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
4412 12:18:14.960078 CH0 RK1: MR19=808, MR18=492A
4413 12:18:14.966790 CH0_RK1: MR19=0x808, MR18=0x492A, DQSOSC=396, MR23=63, INC=167, DEC=111
4414 12:18:14.966865 [RxdqsGatingPostProcess] freq 600
4415 12:18:14.973501 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4416 12:18:14.976561 Pre-setting of DQS Precalculation
4417 12:18:14.980073 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4418 12:18:14.983683 ==
4419 12:18:14.983755 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 12:18:14.989893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 12:18:14.989974 ==
4422 12:18:14.993519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4423 12:18:15.000005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4424 12:18:15.003443 [CA 0] Center 35 (5~66) winsize 62
4425 12:18:15.007115 [CA 1] Center 35 (5~66) winsize 62
4426 12:18:15.010319 [CA 2] Center 33 (3~64) winsize 62
4427 12:18:15.013926 [CA 3] Center 33 (3~64) winsize 62
4428 12:18:15.017085 [CA 4] Center 34 (3~65) winsize 63
4429 12:18:15.020339 [CA 5] Center 33 (2~64) winsize 63
4430 12:18:15.020420
4431 12:18:15.023577 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4432 12:18:15.023658
4433 12:18:15.027053 [CATrainingPosCal] consider 1 rank data
4434 12:18:15.030300 u2DelayCellTimex100 = 270/100 ps
4435 12:18:15.033818 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4436 12:18:15.036884 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4437 12:18:15.043906 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4438 12:18:15.047348 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 12:18:15.050239 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4440 12:18:15.053807 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4441 12:18:15.053896
4442 12:18:15.056961 CA PerBit enable=1, Macro0, CA PI delay=33
4443 12:18:15.057042
4444 12:18:15.060279 [CBTSetCACLKResult] CA Dly = 33
4445 12:18:15.060370 CS Dly: 4 (0~35)
4446 12:18:15.060435 ==
4447 12:18:15.063642 Dram Type= 6, Freq= 0, CH_1, rank 1
4448 12:18:15.070421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4449 12:18:15.070502 ==
4450 12:18:15.073494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4451 12:18:15.080128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4452 12:18:15.084364 [CA 0] Center 35 (5~66) winsize 62
4453 12:18:15.087684 [CA 1] Center 35 (5~66) winsize 62
4454 12:18:15.090615 [CA 2] Center 34 (3~65) winsize 63
4455 12:18:15.093974 [CA 3] Center 34 (3~65) winsize 63
4456 12:18:15.097400 [CA 4] Center 34 (3~65) winsize 63
4457 12:18:15.100983 [CA 5] Center 33 (3~64) winsize 62
4458 12:18:15.101428
4459 12:18:15.105047 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4460 12:18:15.105488
4461 12:18:15.107303 [CATrainingPosCal] consider 2 rank data
4462 12:18:15.111186 u2DelayCellTimex100 = 270/100 ps
4463 12:18:15.114225 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4464 12:18:15.117547 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4465 12:18:15.124606 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4466 12:18:15.127515 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 12:18:15.131137 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4468 12:18:15.133797 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 12:18:15.134508
4470 12:18:15.137199 CA PerBit enable=1, Macro0, CA PI delay=33
4471 12:18:15.137609
4472 12:18:15.141224 [CBTSetCACLKResult] CA Dly = 33
4473 12:18:15.141737 CS Dly: 4 (0~36)
4474 12:18:15.142137
4475 12:18:15.144402 ----->DramcWriteLeveling(PI) begin...
4476 12:18:15.147452 ==
4477 12:18:15.147906 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 12:18:15.154509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 12:18:15.155022 ==
4480 12:18:15.157727 Write leveling (Byte 0): 30 => 30
4481 12:18:15.160779 Write leveling (Byte 1): 31 => 31
4482 12:18:15.164090 DramcWriteLeveling(PI) end<-----
4483 12:18:15.164512
4484 12:18:15.164874 ==
4485 12:18:15.167740 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 12:18:15.171074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 12:18:15.171558 ==
4488 12:18:15.174508 [Gating] SW mode calibration
4489 12:18:15.180677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4490 12:18:15.184594 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4491 12:18:15.190943 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 12:18:15.194365 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 12:18:15.197504 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4494 12:18:15.204271 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 0)
4495 12:18:15.207665 0 9 16 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
4496 12:18:15.210682 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4497 12:18:15.217309 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 12:18:15.220891 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 12:18:15.224203 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 12:18:15.230753 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 12:18:15.234275 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 12:18:15.237877 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
4503 12:18:15.240766 0 10 16 | B1->B0 | 3a3a 3e3e | 0 0 | (0 0) (0 0)
4504 12:18:15.247978 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 12:18:15.250780 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 12:18:15.254413 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 12:18:15.261154 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 12:18:15.264453 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 12:18:15.267996 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 12:18:15.274369 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4511 12:18:15.277664 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:18:15.281180 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 12:18:15.287973 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 12:18:15.291589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:18:15.294493 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:18:15.301058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:18:15.304348 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 12:18:15.307870 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 12:18:15.311452 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 12:18:15.317529 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 12:18:15.321232 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 12:18:15.324841 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 12:18:15.331460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 12:18:15.335122 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 12:18:15.337744 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 12:18:15.344842 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4527 12:18:15.348096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 12:18:15.351064 Total UI for P1: 0, mck2ui 16
4529 12:18:15.354941 best dqsien dly found for B0: ( 0, 13, 12)
4530 12:18:15.358174 Total UI for P1: 0, mck2ui 16
4531 12:18:15.361191 best dqsien dly found for B1: ( 0, 13, 12)
4532 12:18:15.364683 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4533 12:18:15.367847 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4534 12:18:15.368144
4535 12:18:15.371251 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4536 12:18:15.374681 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4537 12:18:15.378547 [Gating] SW calibration Done
4538 12:18:15.379025 ==
4539 12:18:15.381567 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 12:18:15.385061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 12:18:15.388402 ==
4542 12:18:15.388808 RX Vref Scan: 0
4543 12:18:15.389130
4544 12:18:15.391404 RX Vref 0 -> 0, step: 1
4545 12:18:15.391902
4546 12:18:15.394602 RX Delay -230 -> 252, step: 16
4547 12:18:15.398288 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4548 12:18:15.401562 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4549 12:18:15.404765 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4550 12:18:15.407979 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4551 12:18:15.415141 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4552 12:18:15.418058 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4553 12:18:15.421444 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4554 12:18:15.424810 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4555 12:18:15.431218 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4556 12:18:15.434845 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4557 12:18:15.437885 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4558 12:18:15.441584 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4559 12:18:15.444620 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4560 12:18:15.451421 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4561 12:18:15.454788 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4562 12:18:15.457981 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4563 12:18:15.458446 ==
4564 12:18:15.461295 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 12:18:15.467822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 12:18:15.468206 ==
4567 12:18:15.468510 DQS Delay:
4568 12:18:15.468791 DQS0 = 0, DQS1 = 0
4569 12:18:15.471438 DQM Delay:
4570 12:18:15.471818 DQM0 = 44, DQM1 = 34
4571 12:18:15.474527 DQ Delay:
4572 12:18:15.478226 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4573 12:18:15.478667 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4574 12:18:15.481046 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4575 12:18:15.487967 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4576 12:18:15.488469
4577 12:18:15.488900
4578 12:18:15.489308 ==
4579 12:18:15.491478 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 12:18:15.494299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 12:18:15.494692 ==
4582 12:18:15.495150
4583 12:18:15.495543
4584 12:18:15.497746 TX Vref Scan disable
4585 12:18:15.498329 == TX Byte 0 ==
4586 12:18:15.504527 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4587 12:18:15.507792 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4588 12:18:15.508191 == TX Byte 1 ==
4589 12:18:15.514431 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4590 12:18:15.518248 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4591 12:18:15.518645 ==
4592 12:18:15.520992 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 12:18:15.524737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 12:18:15.525202 ==
4595 12:18:15.525599
4596 12:18:15.525975
4597 12:18:15.527827 TX Vref Scan disable
4598 12:18:15.531349 == TX Byte 0 ==
4599 12:18:15.534433 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4600 12:18:15.537989 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4601 12:18:15.541358 == TX Byte 1 ==
4602 12:18:15.544773 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4603 12:18:15.547843 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4604 12:18:15.548224
4605 12:18:15.551461 [DATLAT]
4606 12:18:15.551838 Freq=600, CH1 RK0
4607 12:18:15.552141
4608 12:18:15.554509 DATLAT Default: 0x9
4609 12:18:15.555027 0, 0xFFFF, sum = 0
4610 12:18:15.557798 1, 0xFFFF, sum = 0
4611 12:18:15.557897 2, 0xFFFF, sum = 0
4612 12:18:15.560807 3, 0xFFFF, sum = 0
4613 12:18:15.560889 4, 0xFFFF, sum = 0
4614 12:18:15.564435 5, 0xFFFF, sum = 0
4615 12:18:15.564517 6, 0xFFFF, sum = 0
4616 12:18:15.567358 7, 0xFFFF, sum = 0
4617 12:18:15.567440 8, 0x0, sum = 1
4618 12:18:15.570696 9, 0x0, sum = 2
4619 12:18:15.570819 10, 0x0, sum = 3
4620 12:18:15.574278 11, 0x0, sum = 4
4621 12:18:15.574359 best_step = 9
4622 12:18:15.574422
4623 12:18:15.574481 ==
4624 12:18:15.577950 Dram Type= 6, Freq= 0, CH_1, rank 0
4625 12:18:15.580771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4626 12:18:15.584238 ==
4627 12:18:15.584319 RX Vref Scan: 1
4628 12:18:15.584383
4629 12:18:15.587370 RX Vref 0 -> 0, step: 1
4630 12:18:15.587452
4631 12:18:15.591185 RX Delay -195 -> 252, step: 8
4632 12:18:15.591291
4633 12:18:15.594447 Set Vref, RX VrefLevel [Byte0]: 57
4634 12:18:15.597813 [Byte1]: 52
4635 12:18:15.597910
4636 12:18:15.601060 Final RX Vref Byte 0 = 57 to rank0
4637 12:18:15.604308 Final RX Vref Byte 1 = 52 to rank0
4638 12:18:15.608025 Final RX Vref Byte 0 = 57 to rank1
4639 12:18:15.610899 Final RX Vref Byte 1 = 52 to rank1==
4640 12:18:15.614592 Dram Type= 6, Freq= 0, CH_1, rank 0
4641 12:18:15.617376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 12:18:15.617513 ==
4643 12:18:15.617611 DQS Delay:
4644 12:18:15.620718 DQS0 = 0, DQS1 = 0
4645 12:18:15.620828 DQM Delay:
4646 12:18:15.624294 DQM0 = 41, DQM1 = 33
4647 12:18:15.624376 DQ Delay:
4648 12:18:15.627893 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4649 12:18:15.630881 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4650 12:18:15.634598 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4651 12:18:15.638284 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4652 12:18:15.638362
4653 12:18:15.638434
4654 12:18:15.647807 [DQSOSCAuto] RK0, (LSB)MR18= 0x450b, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4655 12:18:15.647887 CH1 RK0: MR19=808, MR18=450B
4656 12:18:15.654126 CH1_RK0: MR19=0x808, MR18=0x450B, DQSOSC=396, MR23=63, INC=167, DEC=111
4657 12:18:15.654201
4658 12:18:15.657745 ----->DramcWriteLeveling(PI) begin...
4659 12:18:15.657819 ==
4660 12:18:15.661385 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 12:18:15.668124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 12:18:15.668207 ==
4663 12:18:15.671105 Write leveling (Byte 0): 29 => 29
4664 12:18:15.671187 Write leveling (Byte 1): 32 => 32
4665 12:18:15.674447 DramcWriteLeveling(PI) end<-----
4666 12:18:15.674557
4667 12:18:15.678127 ==
4668 12:18:15.678201 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 12:18:15.684496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 12:18:15.684577 ==
4671 12:18:15.687582 [Gating] SW mode calibration
4672 12:18:15.694638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4673 12:18:15.698012 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4674 12:18:15.704707 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 12:18:15.708056 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4676 12:18:15.711298 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4677 12:18:15.714417 0 9 12 | B1->B0 | 2f2f 2929 | 1 1 | (1 1) (1 0)
4678 12:18:15.721103 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4679 12:18:15.724819 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 12:18:15.728419 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 12:18:15.734681 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 12:18:15.737761 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 12:18:15.741068 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 12:18:15.747830 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 12:18:15.751318 0 10 12 | B1->B0 | 2828 3c3c | 0 0 | (0 0) (1 1)
4686 12:18:15.754880 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 12:18:15.761495 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 12:18:15.764772 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 12:18:15.768232 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 12:18:15.774765 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 12:18:15.778419 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 12:18:15.782113 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4693 12:18:15.785056 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4694 12:18:15.791900 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:18:15.794728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 12:18:15.798161 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:18:15.805109 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:18:15.808532 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:18:15.811589 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:18:15.818147 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:18:15.821797 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:18:15.825332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 12:18:15.832067 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 12:18:15.835283 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 12:18:15.838784 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 12:18:15.842444 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 12:18:15.849124 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 12:18:15.852093 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4709 12:18:15.855022 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4710 12:18:15.861804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4711 12:18:15.865112 Total UI for P1: 0, mck2ui 16
4712 12:18:15.868747 best dqsien dly found for B0: ( 0, 13, 10)
4713 12:18:15.871845 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 12:18:15.875331 Total UI for P1: 0, mck2ui 16
4715 12:18:15.878855 best dqsien dly found for B1: ( 0, 13, 16)
4716 12:18:15.881997 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4717 12:18:15.885544 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4718 12:18:15.885627
4719 12:18:15.888505 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4720 12:18:15.892185 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4721 12:18:15.895577 [Gating] SW calibration Done
4722 12:18:15.895659 ==
4723 12:18:15.898829 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 12:18:15.904985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 12:18:15.905069 ==
4726 12:18:15.905136 RX Vref Scan: 0
4727 12:18:15.905197
4728 12:18:15.908431 RX Vref 0 -> 0, step: 1
4729 12:18:15.908502
4730 12:18:15.911828 RX Delay -230 -> 252, step: 16
4731 12:18:15.915308 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4732 12:18:15.918374 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4733 12:18:15.921688 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4734 12:18:15.928760 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4735 12:18:15.931660 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4736 12:18:15.935003 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4737 12:18:15.938313 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4738 12:18:15.941741 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4739 12:18:15.948662 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4740 12:18:15.951554 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4741 12:18:15.955274 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4742 12:18:15.958986 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4743 12:18:15.964921 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4744 12:18:15.968812 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4745 12:18:15.971886 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4746 12:18:15.975621 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4747 12:18:15.975696 ==
4748 12:18:15.978592 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 12:18:15.985067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 12:18:15.985147 ==
4751 12:18:15.985213 DQS Delay:
4752 12:18:15.988860 DQS0 = 0, DQS1 = 0
4753 12:18:15.988933 DQM Delay:
4754 12:18:15.988999 DQM0 = 39, DQM1 = 36
4755 12:18:15.992167 DQ Delay:
4756 12:18:15.994984 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4757 12:18:15.998709 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4758 12:18:16.002175 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4759 12:18:16.005015 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4760 12:18:16.005089
4761 12:18:16.005151
4762 12:18:16.005209 ==
4763 12:18:16.008598 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 12:18:16.011878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 12:18:16.011955 ==
4766 12:18:16.012018
4767 12:18:16.012090
4768 12:18:16.015459 TX Vref Scan disable
4769 12:18:16.015561 == TX Byte 0 ==
4770 12:18:16.021686 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4771 12:18:16.025195 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4772 12:18:16.025306 == TX Byte 1 ==
4773 12:18:16.032001 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4774 12:18:16.035238 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4775 12:18:16.035348 ==
4776 12:18:16.038581 Dram Type= 6, Freq= 0, CH_1, rank 1
4777 12:18:16.042008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4778 12:18:16.042113 ==
4779 12:18:16.042205
4780 12:18:16.042317
4781 12:18:16.045400 TX Vref Scan disable
4782 12:18:16.048507 == TX Byte 0 ==
4783 12:18:16.051802 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4784 12:18:16.055717 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4785 12:18:16.058383 == TX Byte 1 ==
4786 12:18:16.061794 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4787 12:18:16.065020 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4788 12:18:16.068855
4789 12:18:16.068942 [DATLAT]
4790 12:18:16.069006 Freq=600, CH1 RK1
4791 12:18:16.069066
4792 12:18:16.071899 DATLAT Default: 0x9
4793 12:18:16.071975 0, 0xFFFF, sum = 0
4794 12:18:16.075389 1, 0xFFFF, sum = 0
4795 12:18:16.075468 2, 0xFFFF, sum = 0
4796 12:18:16.078556 3, 0xFFFF, sum = 0
4797 12:18:16.078632 4, 0xFFFF, sum = 0
4798 12:18:16.082072 5, 0xFFFF, sum = 0
4799 12:18:16.082176 6, 0xFFFF, sum = 0
4800 12:18:16.085265 7, 0xFFFF, sum = 0
4801 12:18:16.085339 8, 0x0, sum = 1
4802 12:18:16.088511 9, 0x0, sum = 2
4803 12:18:16.088584 10, 0x0, sum = 3
4804 12:18:16.092033 11, 0x0, sum = 4
4805 12:18:16.092104 best_step = 9
4806 12:18:16.092163
4807 12:18:16.092219 ==
4808 12:18:16.095330 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 12:18:16.101906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 12:18:16.102014 ==
4811 12:18:16.102108 RX Vref Scan: 0
4812 12:18:16.102196
4813 12:18:16.105165 RX Vref 0 -> 0, step: 1
4814 12:18:16.105247
4815 12:18:16.108607 RX Delay -179 -> 252, step: 8
4816 12:18:16.112169 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4817 12:18:16.115755 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4818 12:18:16.122286 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4819 12:18:16.125655 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4820 12:18:16.128828 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4821 12:18:16.131959 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4822 12:18:16.138556 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4823 12:18:16.142059 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4824 12:18:16.145616 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4825 12:18:16.148634 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4826 12:18:16.152048 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4827 12:18:16.158713 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4828 12:18:16.162189 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4829 12:18:16.165801 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4830 12:18:16.169082 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4831 12:18:16.175506 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4832 12:18:16.175585 ==
4833 12:18:16.178647 Dram Type= 6, Freq= 0, CH_1, rank 1
4834 12:18:16.182222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4835 12:18:16.182323 ==
4836 12:18:16.182413 DQS Delay:
4837 12:18:16.185344 DQS0 = 0, DQS1 = 0
4838 12:18:16.185417 DQM Delay:
4839 12:18:16.188899 DQM0 = 38, DQM1 = 32
4840 12:18:16.188976 DQ Delay:
4841 12:18:16.192398 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4842 12:18:16.195979 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4843 12:18:16.199002 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4844 12:18:16.202521 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4845 12:18:16.202640
4846 12:18:16.202742
4847 12:18:16.208725 [DQSOSCAuto] RK1, (LSB)MR18= 0x3847, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4848 12:18:16.212267 CH1 RK1: MR19=808, MR18=3847
4849 12:18:16.218931 CH1_RK1: MR19=0x808, MR18=0x3847, DQSOSC=396, MR23=63, INC=167, DEC=111
4850 12:18:16.222430 [RxdqsGatingPostProcess] freq 600
4851 12:18:16.228927 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4852 12:18:16.229032 Pre-setting of DQS Precalculation
4853 12:18:16.235947 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4854 12:18:16.242306 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4855 12:18:16.248978 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4856 12:18:16.249059
4857 12:18:16.249122
4858 12:18:16.252523 [Calibration Summary] 1200 Mbps
4859 12:18:16.256033 CH 0, Rank 0
4860 12:18:16.256114 SW Impedance : PASS
4861 12:18:16.258921 DUTY Scan : NO K
4862 12:18:16.259029 ZQ Calibration : PASS
4863 12:18:16.262497 Jitter Meter : NO K
4864 12:18:16.265985 CBT Training : PASS
4865 12:18:16.266092 Write leveling : PASS
4866 12:18:16.269473 RX DQS gating : PASS
4867 12:18:16.272531 RX DQ/DQS(RDDQC) : PASS
4868 12:18:16.272638 TX DQ/DQS : PASS
4869 12:18:16.276072 RX DATLAT : PASS
4870 12:18:16.278950 RX DQ/DQS(Engine): PASS
4871 12:18:16.279056 TX OE : NO K
4872 12:18:16.282370 All Pass.
4873 12:18:16.282450
4874 12:18:16.282513 CH 0, Rank 1
4875 12:18:16.286031 SW Impedance : PASS
4876 12:18:16.286138 DUTY Scan : NO K
4877 12:18:16.289014 ZQ Calibration : PASS
4878 12:18:16.292881 Jitter Meter : NO K
4879 12:18:16.292963 CBT Training : PASS
4880 12:18:16.295780 Write leveling : PASS
4881 12:18:16.295860 RX DQS gating : PASS
4882 12:18:16.299262 RX DQ/DQS(RDDQC) : PASS
4883 12:18:16.302391 TX DQ/DQS : PASS
4884 12:18:16.302465 RX DATLAT : PASS
4885 12:18:16.306057 RX DQ/DQS(Engine): PASS
4886 12:18:16.309114 TX OE : NO K
4887 12:18:16.309224 All Pass.
4888 12:18:16.309314
4889 12:18:16.309402 CH 1, Rank 0
4890 12:18:16.312814 SW Impedance : PASS
4891 12:18:16.315823 DUTY Scan : NO K
4892 12:18:16.316060 ZQ Calibration : PASS
4893 12:18:16.318933 Jitter Meter : NO K
4894 12:18:16.322400 CBT Training : PASS
4895 12:18:16.322498 Write leveling : PASS
4896 12:18:16.326047 RX DQS gating : PASS
4897 12:18:16.329453 RX DQ/DQS(RDDQC) : PASS
4898 12:18:16.329550 TX DQ/DQS : PASS
4899 12:18:16.332401 RX DATLAT : PASS
4900 12:18:16.335775 RX DQ/DQS(Engine): PASS
4901 12:18:16.335871 TX OE : NO K
4902 12:18:16.335959 All Pass.
4903 12:18:16.336024
4904 12:18:16.339540 CH 1, Rank 1
4905 12:18:16.342389 SW Impedance : PASS
4906 12:18:16.342484 DUTY Scan : NO K
4907 12:18:16.345866 ZQ Calibration : PASS
4908 12:18:16.345940 Jitter Meter : NO K
4909 12:18:16.349059 CBT Training : PASS
4910 12:18:16.352226 Write leveling : PASS
4911 12:18:16.352322 RX DQS gating : PASS
4912 12:18:16.356098 RX DQ/DQS(RDDQC) : PASS
4913 12:18:16.358920 TX DQ/DQS : PASS
4914 12:18:16.358990 RX DATLAT : PASS
4915 12:18:16.362332 RX DQ/DQS(Engine): PASS
4916 12:18:16.365553 TX OE : NO K
4917 12:18:16.365629 All Pass.
4918 12:18:16.365692
4919 12:18:16.365750 DramC Write-DBI off
4920 12:18:16.369148 PER_BANK_REFRESH: Hybrid Mode
4921 12:18:16.372473 TX_TRACKING: ON
4922 12:18:16.379164 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4923 12:18:16.382650 [FAST_K] Save calibration result to emmc
4924 12:18:16.389392 dramc_set_vcore_voltage set vcore to 662500
4925 12:18:16.389500 Read voltage for 933, 3
4926 12:18:16.392441 Vio18 = 0
4927 12:18:16.392547 Vcore = 662500
4928 12:18:16.392640 Vdram = 0
4929 12:18:16.392728 Vddq = 0
4930 12:18:16.396067 Vmddr = 0
4931 12:18:16.399542 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4932 12:18:16.405917 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4933 12:18:16.408986 MEM_TYPE=3, freq_sel=17
4934 12:18:16.409084 sv_algorithm_assistance_LP4_1600
4935 12:18:16.415747 ============ PULL DRAM RESETB DOWN ============
4936 12:18:16.419266 ========== PULL DRAM RESETB DOWN end =========
4937 12:18:16.422322 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4938 12:18:16.425800 ===================================
4939 12:18:16.429487 LPDDR4 DRAM CONFIGURATION
4940 12:18:16.432404 ===================================
4941 12:18:16.435820 EX_ROW_EN[0] = 0x0
4942 12:18:16.435901 EX_ROW_EN[1] = 0x0
4943 12:18:16.439115 LP4Y_EN = 0x0
4944 12:18:16.439196 WORK_FSP = 0x0
4945 12:18:16.442679 WL = 0x3
4946 12:18:16.442803 RL = 0x3
4947 12:18:16.445711 BL = 0x2
4948 12:18:16.445792 RPST = 0x0
4949 12:18:16.449412 RD_PRE = 0x0
4950 12:18:16.449493 WR_PRE = 0x1
4951 12:18:16.452973 WR_PST = 0x0
4952 12:18:16.453055 DBI_WR = 0x0
4953 12:18:16.456039 DBI_RD = 0x0
4954 12:18:16.456194 OTF = 0x1
4955 12:18:16.459349 ===================================
4956 12:18:16.462642 ===================================
4957 12:18:16.466366 ANA top config
4958 12:18:16.469826 ===================================
4959 12:18:16.469922 DLL_ASYNC_EN = 0
4960 12:18:16.473052 ALL_SLAVE_EN = 1
4961 12:18:16.476248 NEW_RANK_MODE = 1
4962 12:18:16.479414 DLL_IDLE_MODE = 1
4963 12:18:16.482986 LP45_APHY_COMB_EN = 1
4964 12:18:16.483092 TX_ODT_DIS = 1
4965 12:18:16.486163 NEW_8X_MODE = 1
4966 12:18:16.489745 ===================================
4967 12:18:16.492887 ===================================
4968 12:18:16.496057 data_rate = 1866
4969 12:18:16.499370 CKR = 1
4970 12:18:16.502860 DQ_P2S_RATIO = 8
4971 12:18:16.506368 ===================================
4972 12:18:16.506471 CA_P2S_RATIO = 8
4973 12:18:16.509286 DQ_CA_OPEN = 0
4974 12:18:16.512949 DQ_SEMI_OPEN = 0
4975 12:18:16.516042 CA_SEMI_OPEN = 0
4976 12:18:16.519787 CA_FULL_RATE = 0
4977 12:18:16.522884 DQ_CKDIV4_EN = 1
4978 12:18:16.522957 CA_CKDIV4_EN = 1
4979 12:18:16.526389 CA_PREDIV_EN = 0
4980 12:18:16.529423 PH8_DLY = 0
4981 12:18:16.532990 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4982 12:18:16.536150 DQ_AAMCK_DIV = 4
4983 12:18:16.539552 CA_AAMCK_DIV = 4
4984 12:18:16.539623 CA_ADMCK_DIV = 4
4985 12:18:16.543130 DQ_TRACK_CA_EN = 0
4986 12:18:16.546463 CA_PICK = 933
4987 12:18:16.549643 CA_MCKIO = 933
4988 12:18:16.553085 MCKIO_SEMI = 0
4989 12:18:16.556532 PLL_FREQ = 3732
4990 12:18:16.556602 DQ_UI_PI_RATIO = 32
4991 12:18:16.559537 CA_UI_PI_RATIO = 0
4992 12:18:16.562962 ===================================
4993 12:18:16.566566 ===================================
4994 12:18:16.570049 memory_type:LPDDR4
4995 12:18:16.573137 GP_NUM : 10
4996 12:18:16.573243 SRAM_EN : 1
4997 12:18:16.576703 MD32_EN : 0
4998 12:18:16.580056 ===================================
4999 12:18:16.580136 [ANA_INIT] >>>>>>>>>>>>>>
5000 12:18:16.583302 <<<<<< [CONFIGURE PHASE]: ANA_TX
5001 12:18:16.586791 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5002 12:18:16.589977 ===================================
5003 12:18:16.593623 data_rate = 1866,PCW = 0X8f00
5004 12:18:16.596591 ===================================
5005 12:18:16.600280 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5006 12:18:16.607186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5007 12:18:16.609789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5008 12:18:16.616836 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5009 12:18:16.620632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5010 12:18:16.623657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5011 12:18:16.623766 [ANA_INIT] flow start
5012 12:18:16.626779 [ANA_INIT] PLL >>>>>>>>
5013 12:18:16.630395 [ANA_INIT] PLL <<<<<<<<
5014 12:18:16.633932 [ANA_INIT] MIDPI >>>>>>>>
5015 12:18:16.634048 [ANA_INIT] MIDPI <<<<<<<<
5016 12:18:16.636865 [ANA_INIT] DLL >>>>>>>>
5017 12:18:16.636947 [ANA_INIT] flow end
5018 12:18:16.643651 ============ LP4 DIFF to SE enter ============
5019 12:18:16.646847 ============ LP4 DIFF to SE exit ============
5020 12:18:16.649929 [ANA_INIT] <<<<<<<<<<<<<
5021 12:18:16.653595 [Flow] Enable top DCM control >>>>>
5022 12:18:16.656677 [Flow] Enable top DCM control <<<<<
5023 12:18:16.659925 Enable DLL master slave shuffle
5024 12:18:16.663581 ==============================================================
5025 12:18:16.666734 Gating Mode config
5026 12:18:16.670253 ==============================================================
5027 12:18:16.673340 Config description:
5028 12:18:16.683337 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5029 12:18:16.690518 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5030 12:18:16.693872 SELPH_MODE 0: By rank 1: By Phase
5031 12:18:16.700549 ==============================================================
5032 12:18:16.703596 GAT_TRACK_EN = 1
5033 12:18:16.707339 RX_GATING_MODE = 2
5034 12:18:16.710924 RX_GATING_TRACK_MODE = 2
5035 12:18:16.713636 SELPH_MODE = 1
5036 12:18:16.714162 PICG_EARLY_EN = 1
5037 12:18:16.717145 VALID_LAT_VALUE = 1
5038 12:18:16.723952 ==============================================================
5039 12:18:16.727003 Enter into Gating configuration >>>>
5040 12:18:16.730476 Exit from Gating configuration <<<<
5041 12:18:16.733660 Enter into DVFS_PRE_config >>>>>
5042 12:18:16.743790 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5043 12:18:16.747040 Exit from DVFS_PRE_config <<<<<
5044 12:18:16.750538 Enter into PICG configuration >>>>
5045 12:18:16.754377 Exit from PICG configuration <<<<
5046 12:18:16.757118 [RX_INPUT] configuration >>>>>
5047 12:18:16.760552 [RX_INPUT] configuration <<<<<
5048 12:18:16.763990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5049 12:18:16.770693 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5050 12:18:16.777425 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5051 12:18:16.783726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5052 12:18:16.790417 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5053 12:18:16.793870 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5054 12:18:16.800338 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5055 12:18:16.803678 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5056 12:18:16.807269 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5057 12:18:16.810774 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5058 12:18:16.813732 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5059 12:18:16.820527 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5060 12:18:16.823865 ===================================
5061 12:18:16.827085 LPDDR4 DRAM CONFIGURATION
5062 12:18:16.830395 ===================================
5063 12:18:16.830859 EX_ROW_EN[0] = 0x0
5064 12:18:16.834267 EX_ROW_EN[1] = 0x0
5065 12:18:16.834691 LP4Y_EN = 0x0
5066 12:18:16.837351 WORK_FSP = 0x0
5067 12:18:16.837823 WL = 0x3
5068 12:18:16.840925 RL = 0x3
5069 12:18:16.841352 BL = 0x2
5070 12:18:16.843894 RPST = 0x0
5071 12:18:16.844308 RD_PRE = 0x0
5072 12:18:16.847472 WR_PRE = 0x1
5073 12:18:16.847918 WR_PST = 0x0
5074 12:18:16.850489 DBI_WR = 0x0
5075 12:18:16.851157 DBI_RD = 0x0
5076 12:18:16.854143 OTF = 0x1
5077 12:18:16.857871 ===================================
5078 12:18:16.860838 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5079 12:18:16.864229 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5080 12:18:16.871138 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 12:18:16.873911 ===================================
5082 12:18:16.874324 LPDDR4 DRAM CONFIGURATION
5083 12:18:16.877475 ===================================
5084 12:18:16.881065 EX_ROW_EN[0] = 0x10
5085 12:18:16.881479 EX_ROW_EN[1] = 0x0
5086 12:18:16.884614 LP4Y_EN = 0x0
5087 12:18:16.885029 WORK_FSP = 0x0
5088 12:18:16.887505 WL = 0x3
5089 12:18:16.887921 RL = 0x3
5090 12:18:16.891242 BL = 0x2
5091 12:18:16.894182 RPST = 0x0
5092 12:18:16.894596 RD_PRE = 0x0
5093 12:18:16.897916 WR_PRE = 0x1
5094 12:18:16.898330 WR_PST = 0x0
5095 12:18:16.900810 DBI_WR = 0x0
5096 12:18:16.901227 DBI_RD = 0x0
5097 12:18:16.904270 OTF = 0x1
5098 12:18:16.907808 ===================================
5099 12:18:16.911014 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5100 12:18:16.916219 nWR fixed to 30
5101 12:18:16.919766 [ModeRegInit_LP4] CH0 RK0
5102 12:18:16.920179 [ModeRegInit_LP4] CH0 RK1
5103 12:18:16.922872 [ModeRegInit_LP4] CH1 RK0
5104 12:18:16.926460 [ModeRegInit_LP4] CH1 RK1
5105 12:18:16.926905 match AC timing 9
5106 12:18:16.933253 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5107 12:18:16.936303 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5108 12:18:16.939890 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5109 12:18:16.946880 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5110 12:18:16.949879 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5111 12:18:16.950402 ==
5112 12:18:16.953572 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 12:18:16.956951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 12:18:16.957569 ==
5115 12:18:16.963313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5116 12:18:16.969837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5117 12:18:16.973389 [CA 0] Center 38 (8~69) winsize 62
5118 12:18:16.976806 [CA 1] Center 38 (8~69) winsize 62
5119 12:18:16.979864 [CA 2] Center 35 (5~66) winsize 62
5120 12:18:16.983403 [CA 3] Center 35 (4~66) winsize 63
5121 12:18:16.986423 [CA 4] Center 33 (3~64) winsize 62
5122 12:18:16.989806 [CA 5] Center 33 (3~64) winsize 62
5123 12:18:16.990237
5124 12:18:16.993384 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5125 12:18:16.993895
5126 12:18:16.997091 [CATrainingPosCal] consider 1 rank data
5127 12:18:17.000037 u2DelayCellTimex100 = 270/100 ps
5128 12:18:17.003699 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5129 12:18:17.007188 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5130 12:18:17.010316 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5131 12:18:17.013874 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5132 12:18:17.016975 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5133 12:18:17.020254 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5134 12:18:17.020728
5135 12:18:17.023927 CA PerBit enable=1, Macro0, CA PI delay=33
5136 12:18:17.026825
5137 12:18:17.027241 [CBTSetCACLKResult] CA Dly = 33
5138 12:18:17.029684 CS Dly: 6 (0~37)
5139 12:18:17.030325 ==
5140 12:18:17.033476 Dram Type= 6, Freq= 0, CH_0, rank 1
5141 12:18:17.036763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5142 12:18:17.037138 ==
5143 12:18:17.043413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5144 12:18:17.049818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5145 12:18:17.053329 [CA 0] Center 38 (7~69) winsize 63
5146 12:18:17.056320 [CA 1] Center 37 (7~68) winsize 62
5147 12:18:17.059900 [CA 2] Center 35 (5~66) winsize 62
5148 12:18:17.063042 [CA 3] Center 35 (4~66) winsize 63
5149 12:18:17.066548 [CA 4] Center 34 (4~65) winsize 62
5150 12:18:17.069698 [CA 5] Center 33 (3~64) winsize 62
5151 12:18:17.070115
5152 12:18:17.073386 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5153 12:18:17.073849
5154 12:18:17.076485 [CATrainingPosCal] consider 2 rank data
5155 12:18:17.079923 u2DelayCellTimex100 = 270/100 ps
5156 12:18:17.083255 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5157 12:18:17.086605 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5158 12:18:17.090090 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5159 12:18:17.093040 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5160 12:18:17.096133 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5161 12:18:17.099766 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5162 12:18:17.099848
5163 12:18:17.106439 CA PerBit enable=1, Macro0, CA PI delay=33
5164 12:18:17.106547
5165 12:18:17.106639 [CBTSetCACLKResult] CA Dly = 33
5166 12:18:17.109394 CS Dly: 7 (0~39)
5167 12:18:17.109475
5168 12:18:17.113234 ----->DramcWriteLeveling(PI) begin...
5169 12:18:17.113317 ==
5170 12:18:17.116755 Dram Type= 6, Freq= 0, CH_0, rank 0
5171 12:18:17.119807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5172 12:18:17.119890 ==
5173 12:18:17.123076 Write leveling (Byte 0): 28 => 28
5174 12:18:17.126558 Write leveling (Byte 1): 27 => 27
5175 12:18:17.129590 DramcWriteLeveling(PI) end<-----
5176 12:18:17.129671
5177 12:18:17.129735 ==
5178 12:18:17.133161 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 12:18:17.136545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 12:18:17.136627 ==
5181 12:18:17.139572 [Gating] SW mode calibration
5182 12:18:17.146113 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5183 12:18:17.153073 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5184 12:18:17.156194 0 14 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5185 12:18:17.162734 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5186 12:18:17.166581 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 12:18:17.169427 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 12:18:17.176251 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 12:18:17.179719 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 12:18:17.183277 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 12:18:17.186730 0 14 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5192 12:18:17.193168 0 15 0 | B1->B0 | 3333 2c2c | 0 0 | (0 1) (1 0)
5193 12:18:17.196688 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5194 12:18:17.199823 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 12:18:17.206340 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 12:18:17.210174 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 12:18:17.213086 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 12:18:17.219765 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 12:18:17.223455 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
5200 12:18:17.226741 1 0 0 | B1->B0 | 3333 4343 | 0 1 | (1 1) (0 0)
5201 12:18:17.233305 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5202 12:18:17.237109 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 12:18:17.240298 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 12:18:17.246542 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 12:18:17.250285 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 12:18:17.253295 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 12:18:17.260253 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 12:18:17.263568 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5209 12:18:17.267071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 12:18:17.270361 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:18:17.276986 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 12:18:17.279924 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 12:18:17.283698 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 12:18:17.290495 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 12:18:17.293587 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 12:18:17.297092 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 12:18:17.303290 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 12:18:17.306699 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 12:18:17.310000 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 12:18:17.316918 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 12:18:17.320430 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 12:18:17.323374 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 12:18:17.330242 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5224 12:18:17.333622 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5225 12:18:17.337135 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 12:18:17.340409 Total UI for P1: 0, mck2ui 16
5227 12:18:17.343281 best dqsien dly found for B0: ( 1, 2, 30)
5228 12:18:17.347156 Total UI for P1: 0, mck2ui 16
5229 12:18:17.350162 best dqsien dly found for B1: ( 1, 3, 2)
5230 12:18:17.353065 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5231 12:18:17.356769 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5232 12:18:17.357314
5233 12:18:17.363145 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5234 12:18:17.366444 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5235 12:18:17.366941 [Gating] SW calibration Done
5236 12:18:17.370249 ==
5237 12:18:17.370911 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 12:18:17.376513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 12:18:17.377058 ==
5240 12:18:17.377467 RX Vref Scan: 0
5241 12:18:17.377945
5242 12:18:17.379912 RX Vref 0 -> 0, step: 1
5243 12:18:17.380396
5244 12:18:17.383205 RX Delay -80 -> 252, step: 8
5245 12:18:17.386523 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5246 12:18:17.389964 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5247 12:18:17.393257 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5248 12:18:17.396948 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5249 12:18:17.403025 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5250 12:18:17.406037 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5251 12:18:17.409533 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5252 12:18:17.412754 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5253 12:18:17.416150 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5254 12:18:17.419654 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5255 12:18:17.426007 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5256 12:18:17.429784 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5257 12:18:17.432709 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5258 12:18:17.436206 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5259 12:18:17.439797 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5260 12:18:17.446570 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5261 12:18:17.446651 ==
5262 12:18:17.449728 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 12:18:17.453270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 12:18:17.453351 ==
5265 12:18:17.453415 DQS Delay:
5266 12:18:17.456233 DQS0 = 0, DQS1 = 0
5267 12:18:17.456314 DQM Delay:
5268 12:18:17.459412 DQM0 = 99, DQM1 = 88
5269 12:18:17.459492 DQ Delay:
5270 12:18:17.462977 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =91
5271 12:18:17.466101 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =103
5272 12:18:17.469679 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5273 12:18:17.473184 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5274 12:18:17.473264
5275 12:18:17.473328
5276 12:18:17.473387 ==
5277 12:18:17.476161 Dram Type= 6, Freq= 0, CH_0, rank 0
5278 12:18:17.479653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 12:18:17.479734 ==
5280 12:18:17.479832
5281 12:18:17.479891
5282 12:18:17.483400 TX Vref Scan disable
5283 12:18:17.486400 == TX Byte 0 ==
5284 12:18:17.489782 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5285 12:18:17.493085 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5286 12:18:17.496447 == TX Byte 1 ==
5287 12:18:17.499668 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5288 12:18:17.502845 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5289 12:18:17.502927 ==
5290 12:18:17.506500 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 12:18:17.509907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 12:18:17.512791 ==
5293 12:18:17.512872
5294 12:18:17.512935
5295 12:18:17.512994 TX Vref Scan disable
5296 12:18:17.516927 == TX Byte 0 ==
5297 12:18:17.520158 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5298 12:18:17.523712 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5299 12:18:17.526601 == TX Byte 1 ==
5300 12:18:17.530062 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5301 12:18:17.533925 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5302 12:18:17.536799
5303 12:18:17.536879 [DATLAT]
5304 12:18:17.536942 Freq=933, CH0 RK0
5305 12:18:17.537002
5306 12:18:17.540480 DATLAT Default: 0xd
5307 12:18:17.540560 0, 0xFFFF, sum = 0
5308 12:18:17.543460 1, 0xFFFF, sum = 0
5309 12:18:17.543547 2, 0xFFFF, sum = 0
5310 12:18:17.546749 3, 0xFFFF, sum = 0
5311 12:18:17.546837 4, 0xFFFF, sum = 0
5312 12:18:17.550256 5, 0xFFFF, sum = 0
5313 12:18:17.550338 6, 0xFFFF, sum = 0
5314 12:18:17.554026 7, 0xFFFF, sum = 0
5315 12:18:17.554114 8, 0xFFFF, sum = 0
5316 12:18:17.557036 9, 0xFFFF, sum = 0
5317 12:18:17.557124 10, 0x0, sum = 1
5318 12:18:17.560029 11, 0x0, sum = 2
5319 12:18:17.560124 12, 0x0, sum = 3
5320 12:18:17.563595 13, 0x0, sum = 4
5321 12:18:17.563696 best_step = 11
5322 12:18:17.563776
5323 12:18:17.563849 ==
5324 12:18:17.566651 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 12:18:17.573300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 12:18:17.573430 ==
5327 12:18:17.573555 RX Vref Scan: 1
5328 12:18:17.573714
5329 12:18:17.577084 RX Vref 0 -> 0, step: 1
5330 12:18:17.577204
5331 12:18:17.579993 RX Delay -61 -> 252, step: 4
5332 12:18:17.580091
5333 12:18:17.583598 Set Vref, RX VrefLevel [Byte0]: 54
5334 12:18:17.587457 [Byte1]: 51
5335 12:18:17.587539
5336 12:18:17.590606 Final RX Vref Byte 0 = 54 to rank0
5337 12:18:17.594291 Final RX Vref Byte 1 = 51 to rank0
5338 12:18:17.597171 Final RX Vref Byte 0 = 54 to rank1
5339 12:18:17.600822 Final RX Vref Byte 1 = 51 to rank1==
5340 12:18:17.603850 Dram Type= 6, Freq= 0, CH_0, rank 0
5341 12:18:17.607390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5342 12:18:17.607514 ==
5343 12:18:17.610879 DQS Delay:
5344 12:18:17.610999 DQS0 = 0, DQS1 = 0
5345 12:18:17.611094 DQM Delay:
5346 12:18:17.613800 DQM0 = 96, DQM1 = 87
5347 12:18:17.613933 DQ Delay:
5348 12:18:17.617291 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5349 12:18:17.620357 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =102
5350 12:18:17.623839 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =80
5351 12:18:17.627437 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =98
5352 12:18:17.627574
5353 12:18:17.627640
5354 12:18:17.637408 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5355 12:18:17.637497 CH0 RK0: MR19=505, MR18=1601
5356 12:18:17.644165 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5357 12:18:17.644313
5358 12:18:17.647121 ----->DramcWriteLeveling(PI) begin...
5359 12:18:17.647252 ==
5360 12:18:17.650648 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 12:18:17.657749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 12:18:17.657919 ==
5363 12:18:17.660680 Write leveling (Byte 0): 31 => 31
5364 12:18:17.664254 Write leveling (Byte 1): 30 => 30
5365 12:18:17.664388 DramcWriteLeveling(PI) end<-----
5366 12:18:17.664499
5367 12:18:17.667491 ==
5368 12:18:17.671090 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 12:18:17.674157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 12:18:17.674420 ==
5371 12:18:17.677646 [Gating] SW mode calibration
5372 12:18:17.684365 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5373 12:18:17.688036 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5374 12:18:17.694861 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5375 12:18:17.697694 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5376 12:18:17.701567 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 12:18:17.708100 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 12:18:17.711337 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 12:18:17.714571 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 12:18:17.718226 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5381 12:18:17.724811 0 14 28 | B1->B0 | 3232 2525 | 1 0 | (1 0) (1 0)
5382 12:18:17.728150 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
5383 12:18:17.731579 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 12:18:17.738244 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 12:18:17.741594 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 12:18:17.744645 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 12:18:17.751660 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 12:18:17.754920 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5389 12:18:17.758348 0 15 28 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
5390 12:18:17.765139 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5391 12:18:17.768412 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 12:18:17.771855 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 12:18:17.778472 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 12:18:17.781806 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 12:18:17.785228 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 12:18:17.788775 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5397 12:18:17.795263 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5398 12:18:17.798457 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5399 12:18:17.801702 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5400 12:18:17.808277 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:18:17.811796 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 12:18:17.814973 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 12:18:17.822061 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:18:17.824788 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 12:18:17.828662 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 12:18:17.835264 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 12:18:17.838516 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 12:18:17.841905 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 12:18:17.848410 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 12:18:17.851922 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 12:18:17.854930 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 12:18:17.861587 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 12:18:17.865126 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5414 12:18:17.868818 Total UI for P1: 0, mck2ui 16
5415 12:18:17.872036 best dqsien dly found for B0: ( 1, 2, 26)
5416 12:18:17.875449 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5417 12:18:17.878331 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5418 12:18:17.885353 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 12:18:17.889010 Total UI for P1: 0, mck2ui 16
5420 12:18:17.892021 best dqsien dly found for B1: ( 1, 3, 2)
5421 12:18:17.894975 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5422 12:18:17.898542 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5423 12:18:17.899119
5424 12:18:17.902281 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5425 12:18:17.905324 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5426 12:18:17.908852 [Gating] SW calibration Done
5427 12:18:17.909298 ==
5428 12:18:17.912149 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 12:18:17.915505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 12:18:17.915920 ==
5431 12:18:17.919307 RX Vref Scan: 0
5432 12:18:17.919717
5433 12:18:17.920042 RX Vref 0 -> 0, step: 1
5434 12:18:17.920345
5435 12:18:17.922450 RX Delay -80 -> 252, step: 8
5436 12:18:17.925918 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5437 12:18:17.931859 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5438 12:18:17.935718 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5439 12:18:17.938622 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5440 12:18:17.942280 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5441 12:18:17.945416 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5442 12:18:17.948622 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5443 12:18:17.952322 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5444 12:18:17.958575 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5445 12:18:17.961848 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5446 12:18:17.965652 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5447 12:18:17.968693 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5448 12:18:17.971872 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5449 12:18:17.978791 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5450 12:18:17.982203 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5451 12:18:17.985237 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5452 12:18:17.985833 ==
5453 12:18:17.988576 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 12:18:17.992096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 12:18:17.992744 ==
5456 12:18:17.995364 DQS Delay:
5457 12:18:17.995944 DQS0 = 0, DQS1 = 0
5458 12:18:17.996306 DQM Delay:
5459 12:18:17.998870 DQM0 = 97, DQM1 = 86
5460 12:18:17.999258 DQ Delay:
5461 12:18:18.001692 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5462 12:18:18.005603 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5463 12:18:18.008799 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =75
5464 12:18:18.012346 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =95
5465 12:18:18.012725
5466 12:18:18.013056
5467 12:18:18.013536 ==
5468 12:18:18.015959 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 12:18:18.022487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 12:18:18.023048 ==
5471 12:18:18.023414
5472 12:18:18.023726
5473 12:18:18.024062 TX Vref Scan disable
5474 12:18:18.025614 == TX Byte 0 ==
5475 12:18:18.029432 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5476 12:18:18.032408 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5477 12:18:18.035629 == TX Byte 1 ==
5478 12:18:18.038621 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5479 12:18:18.042233 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5480 12:18:18.045445 ==
5481 12:18:18.048544 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 12:18:18.052149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 12:18:18.052517 ==
5484 12:18:18.052852
5485 12:18:18.053188
5486 12:18:18.055485 TX Vref Scan disable
5487 12:18:18.055792 == TX Byte 0 ==
5488 12:18:18.062109 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5489 12:18:18.065486 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5490 12:18:18.065742 == TX Byte 1 ==
5491 12:18:18.072278 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5492 12:18:18.075160 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5493 12:18:18.075315
5494 12:18:18.075471 [DATLAT]
5495 12:18:18.078695 Freq=933, CH0 RK1
5496 12:18:18.078851
5497 12:18:18.078981 DATLAT Default: 0xb
5498 12:18:18.082162 0, 0xFFFF, sum = 0
5499 12:18:18.082335 1, 0xFFFF, sum = 0
5500 12:18:18.085388 2, 0xFFFF, sum = 0
5501 12:18:18.085538 3, 0xFFFF, sum = 0
5502 12:18:18.088818 4, 0xFFFF, sum = 0
5503 12:18:18.088945 5, 0xFFFF, sum = 0
5504 12:18:18.092102 6, 0xFFFF, sum = 0
5505 12:18:18.092225 7, 0xFFFF, sum = 0
5506 12:18:18.095383 8, 0xFFFF, sum = 0
5507 12:18:18.095524 9, 0xFFFF, sum = 0
5508 12:18:18.098515 10, 0x0, sum = 1
5509 12:18:18.098645 11, 0x0, sum = 2
5510 12:18:18.101843 12, 0x0, sum = 3
5511 12:18:18.101932 13, 0x0, sum = 4
5512 12:18:18.105029 best_step = 11
5513 12:18:18.105107
5514 12:18:18.105170 ==
5515 12:18:18.108569 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 12:18:18.112280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 12:18:18.112362 ==
5518 12:18:18.115314 RX Vref Scan: 0
5519 12:18:18.115394
5520 12:18:18.115457 RX Vref 0 -> 0, step: 1
5521 12:18:18.115516
5522 12:18:18.118905 RX Delay -61 -> 252, step: 4
5523 12:18:18.125386 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5524 12:18:18.129028 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5525 12:18:18.132198 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5526 12:18:18.135871 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5527 12:18:18.138869 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5528 12:18:18.142184 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5529 12:18:18.148742 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5530 12:18:18.152006 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5531 12:18:18.155572 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5532 12:18:18.159145 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5533 12:18:18.162304 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5534 12:18:18.168956 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5535 12:18:18.172076 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5536 12:18:18.176008 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5537 12:18:18.179341 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5538 12:18:18.182529 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5539 12:18:18.182631 ==
5540 12:18:18.185373 Dram Type= 6, Freq= 0, CH_0, rank 1
5541 12:18:18.188844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 12:18:18.192441 ==
5543 12:18:18.192544 DQS Delay:
5544 12:18:18.192634 DQS0 = 0, DQS1 = 0
5545 12:18:18.195886 DQM Delay:
5546 12:18:18.195987 DQM0 = 95, DQM1 = 87
5547 12:18:18.199151 DQ Delay:
5548 12:18:18.199250 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5549 12:18:18.202356 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =104
5550 12:18:18.205660 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =78
5551 12:18:18.209113 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5552 12:18:18.212266
5553 12:18:18.212363
5554 12:18:18.218975 [DQSOSCAuto] RK1, (LSB)MR18= 0x1805, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5555 12:18:18.222593 CH0 RK1: MR19=505, MR18=1805
5556 12:18:18.229108 CH0_RK1: MR19=0x505, MR18=0x1805, DQSOSC=414, MR23=63, INC=63, DEC=42
5557 12:18:18.232242 [RxdqsGatingPostProcess] freq 933
5558 12:18:18.235801 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5559 12:18:18.239036 best DQS0 dly(2T, 0.5T) = (0, 10)
5560 12:18:18.242083 best DQS1 dly(2T, 0.5T) = (0, 11)
5561 12:18:18.245484 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5562 12:18:18.248855 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5563 12:18:18.252447 best DQS0 dly(2T, 0.5T) = (0, 10)
5564 12:18:18.256131 best DQS1 dly(2T, 0.5T) = (0, 11)
5565 12:18:18.259049 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5566 12:18:18.262234 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5567 12:18:18.265574 Pre-setting of DQS Precalculation
5568 12:18:18.269115 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5569 12:18:18.269216 ==
5570 12:18:18.272123 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 12:18:18.275556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 12:18:18.278655 ==
5573 12:18:18.282102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5574 12:18:18.288747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5575 12:18:18.292397 [CA 0] Center 36 (6~67) winsize 62
5576 12:18:18.295326 [CA 1] Center 36 (6~67) winsize 62
5577 12:18:18.299013 [CA 2] Center 34 (4~64) winsize 61
5578 12:18:18.302492 [CA 3] Center 33 (3~64) winsize 62
5579 12:18:18.305726 [CA 4] Center 34 (3~65) winsize 63
5580 12:18:18.308695 [CA 5] Center 33 (3~63) winsize 61
5581 12:18:18.308799
5582 12:18:18.312484 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5583 12:18:18.312557
5584 12:18:18.315845 [CATrainingPosCal] consider 1 rank data
5585 12:18:18.319794 u2DelayCellTimex100 = 270/100 ps
5586 12:18:18.322693 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5587 12:18:18.326259 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 12:18:18.329156 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5589 12:18:18.332713 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5590 12:18:18.336346 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5591 12:18:18.339615 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5592 12:18:18.343084
5593 12:18:18.346356 CA PerBit enable=1, Macro0, CA PI delay=33
5594 12:18:18.347037
5595 12:18:18.349183 [CBTSetCACLKResult] CA Dly = 33
5596 12:18:18.349705 CS Dly: 5 (0~36)
5597 12:18:18.350174 ==
5598 12:18:18.352742 Dram Type= 6, Freq= 0, CH_1, rank 1
5599 12:18:18.356516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5600 12:18:18.356958 ==
5601 12:18:18.363092 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5602 12:18:18.369598 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5603 12:18:18.372691 [CA 0] Center 36 (6~67) winsize 62
5604 12:18:18.376160 [CA 1] Center 37 (7~67) winsize 61
5605 12:18:18.379769 [CA 2] Center 34 (4~64) winsize 61
5606 12:18:18.382834 [CA 3] Center 33 (2~64) winsize 63
5607 12:18:18.385764 [CA 4] Center 34 (4~64) winsize 61
5608 12:18:18.389459 [CA 5] Center 32 (2~63) winsize 62
5609 12:18:18.389947
5610 12:18:18.392922 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5611 12:18:18.393352
5612 12:18:18.396010 [CATrainingPosCal] consider 2 rank data
5613 12:18:18.399469 u2DelayCellTimex100 = 270/100 ps
5614 12:18:18.403005 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5615 12:18:18.406388 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5616 12:18:18.410137 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5617 12:18:18.412840 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5618 12:18:18.416467 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5619 12:18:18.419817 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5620 12:18:18.420251
5621 12:18:18.426057 CA PerBit enable=1, Macro0, CA PI delay=33
5622 12:18:18.426486
5623 12:18:18.429765 [CBTSetCACLKResult] CA Dly = 33
5624 12:18:18.430190 CS Dly: 6 (0~38)
5625 12:18:18.430619
5626 12:18:18.433032 ----->DramcWriteLeveling(PI) begin...
5627 12:18:18.433464 ==
5628 12:18:18.436379 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 12:18:18.440233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 12:18:18.440664 ==
5631 12:18:18.443288 Write leveling (Byte 0): 25 => 25
5632 12:18:18.446447 Write leveling (Byte 1): 30 => 30
5633 12:18:18.449575 DramcWriteLeveling(PI) end<-----
5634 12:18:18.450000
5635 12:18:18.450430 ==
5636 12:18:18.453034 Dram Type= 6, Freq= 0, CH_1, rank 0
5637 12:18:18.456323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5638 12:18:18.459767 ==
5639 12:18:18.460193 [Gating] SW mode calibration
5640 12:18:18.466658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5641 12:18:18.473367 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5642 12:18:18.476553 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5643 12:18:18.483118 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 12:18:18.486252 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 12:18:18.489717 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 12:18:18.496472 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 12:18:18.499273 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 12:18:18.502689 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5649 12:18:18.509553 0 14 28 | B1->B0 | 3232 3434 | 0 0 | (0 1) (0 1)
5650 12:18:18.512787 0 15 0 | B1->B0 | 2929 2626 | 0 0 | (1 1) (1 1)
5651 12:18:18.516105 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 12:18:18.522557 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 12:18:18.526320 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 12:18:18.529153 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 12:18:18.535853 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 12:18:18.539151 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 12:18:18.542341 0 15 28 | B1->B0 | 2c2c 2c2c | 0 0 | (0 0) (0 0)
5658 12:18:18.549499 1 0 0 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
5659 12:18:18.552480 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 12:18:18.556227 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 12:18:18.562389 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 12:18:18.565866 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 12:18:18.569392 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 12:18:18.575960 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 12:18:18.579080 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5666 12:18:18.582798 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 12:18:18.586076 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 12:18:18.592416 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 12:18:18.596138 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:18:18.599455 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 12:18:18.605669 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 12:18:18.609450 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 12:18:18.612403 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 12:18:18.618997 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 12:18:18.622492 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 12:18:18.625491 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 12:18:18.632871 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 12:18:18.636060 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 12:18:18.639616 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 12:18:18.646037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5681 12:18:18.649366 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5682 12:18:18.652414 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5683 12:18:18.658886 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 12:18:18.659506 Total UI for P1: 0, mck2ui 16
5685 12:18:18.662650 best dqsien dly found for B0: ( 1, 2, 28)
5686 12:18:18.666335 Total UI for P1: 0, mck2ui 16
5687 12:18:18.669151 best dqsien dly found for B1: ( 1, 2, 30)
5688 12:18:18.672602 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5689 12:18:18.679096 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5690 12:18:18.679775
5691 12:18:18.682674 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5692 12:18:18.686191 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5693 12:18:18.688908 [Gating] SW calibration Done
5694 12:18:18.689340 ==
5695 12:18:18.692398 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 12:18:18.696191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 12:18:18.696635 ==
5698 12:18:18.697021 RX Vref Scan: 0
5699 12:18:18.697404
5700 12:18:18.699054 RX Vref 0 -> 0, step: 1
5701 12:18:18.699412
5702 12:18:18.702328 RX Delay -80 -> 252, step: 8
5703 12:18:18.706452 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5704 12:18:18.709182 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5705 12:18:18.713029 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5706 12:18:18.719352 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5707 12:18:18.722750 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5708 12:18:18.725657 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5709 12:18:18.729151 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5710 12:18:18.732597 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5711 12:18:18.735620 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5712 12:18:18.742812 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5713 12:18:18.745872 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5714 12:18:18.749296 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5715 12:18:18.752546 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5716 12:18:18.756276 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5717 12:18:18.762684 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5718 12:18:18.765961 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5719 12:18:18.766370 ==
5720 12:18:18.769140 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 12:18:18.772742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 12:18:18.773049 ==
5723 12:18:18.773372 DQS Delay:
5724 12:18:18.776225 DQS0 = 0, DQS1 = 0
5725 12:18:18.776570 DQM Delay:
5726 12:18:18.779317 DQM0 = 95, DQM1 = 88
5727 12:18:18.779674 DQ Delay:
5728 12:18:18.783031 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5729 12:18:18.786054 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5730 12:18:18.789563 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5731 12:18:18.793110 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5732 12:18:18.793417
5733 12:18:18.793729
5734 12:18:18.794019 ==
5735 12:18:18.796430 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 12:18:18.799658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 12:18:18.799951 ==
5738 12:18:18.802711
5739 12:18:18.803033
5740 12:18:18.803266 TX Vref Scan disable
5741 12:18:18.806220 == TX Byte 0 ==
5742 12:18:18.809925 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5743 12:18:18.812947 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5744 12:18:18.816688 == TX Byte 1 ==
5745 12:18:18.819548 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5746 12:18:18.822708 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5747 12:18:18.823037 ==
5748 12:18:18.826302 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 12:18:18.833303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 12:18:18.833693 ==
5751 12:18:18.834026
5752 12:18:18.834340
5753 12:18:18.834648 TX Vref Scan disable
5754 12:18:18.837069 == TX Byte 0 ==
5755 12:18:18.840690 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5756 12:18:18.843879 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5757 12:18:18.847153 == TX Byte 1 ==
5758 12:18:18.850331 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5759 12:18:18.853739 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5760 12:18:18.856935
5761 12:18:18.857240 [DATLAT]
5762 12:18:18.857554 Freq=933, CH1 RK0
5763 12:18:18.857905
5764 12:18:18.860239 DATLAT Default: 0xd
5765 12:18:18.860597 0, 0xFFFF, sum = 0
5766 12:18:18.863736 1, 0xFFFF, sum = 0
5767 12:18:18.864044 2, 0xFFFF, sum = 0
5768 12:18:18.867124 3, 0xFFFF, sum = 0
5769 12:18:18.867420 4, 0xFFFF, sum = 0
5770 12:18:18.870629 5, 0xFFFF, sum = 0
5771 12:18:18.870958 6, 0xFFFF, sum = 0
5772 12:18:18.873945 7, 0xFFFF, sum = 0
5773 12:18:18.877306 8, 0xFFFF, sum = 0
5774 12:18:18.877604 9, 0xFFFF, sum = 0
5775 12:18:18.877840 10, 0x0, sum = 1
5776 12:18:18.880838 11, 0x0, sum = 2
5777 12:18:18.881144 12, 0x0, sum = 3
5778 12:18:18.884350 13, 0x0, sum = 4
5779 12:18:18.884656 best_step = 11
5780 12:18:18.884892
5781 12:18:18.885116 ==
5782 12:18:18.887231 Dram Type= 6, Freq= 0, CH_1, rank 0
5783 12:18:18.893811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 12:18:18.894182 ==
5785 12:18:18.894575 RX Vref Scan: 1
5786 12:18:18.894984
5787 12:18:18.897469 RX Vref 0 -> 0, step: 1
5788 12:18:18.897766
5789 12:18:18.900370 RX Delay -69 -> 252, step: 4
5790 12:18:18.900694
5791 12:18:18.903967 Set Vref, RX VrefLevel [Byte0]: 57
5792 12:18:18.907603 [Byte1]: 52
5793 12:18:18.907903
5794 12:18:18.910498 Final RX Vref Byte 0 = 57 to rank0
5795 12:18:18.913768 Final RX Vref Byte 1 = 52 to rank0
5796 12:18:18.917407 Final RX Vref Byte 0 = 57 to rank1
5797 12:18:18.920263 Final RX Vref Byte 1 = 52 to rank1==
5798 12:18:18.924139 Dram Type= 6, Freq= 0, CH_1, rank 0
5799 12:18:18.927155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 12:18:18.927457 ==
5801 12:18:18.930680 DQS Delay:
5802 12:18:18.931014 DQS0 = 0, DQS1 = 0
5803 12:18:18.931246 DQM Delay:
5804 12:18:18.933692 DQM0 = 97, DQM1 = 89
5805 12:18:18.933987 DQ Delay:
5806 12:18:18.937289 DQ0 =100, DQ1 =90, DQ2 =88, DQ3 =96
5807 12:18:18.940211 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5808 12:18:18.944214 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =86
5809 12:18:18.946638 DQ12 =98, DQ13 =96, DQ14 =94, DQ15 =94
5810 12:18:18.946725
5811 12:18:18.946793
5812 12:18:18.956809 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5813 12:18:18.959908 CH1 RK0: MR19=504, MR18=14F0
5814 12:18:18.963312 CH1_RK0: MR19=0x504, MR18=0x14F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5815 12:18:18.966582
5816 12:18:18.970090 ----->DramcWriteLeveling(PI) begin...
5817 12:18:18.970178 ==
5818 12:18:18.973274 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 12:18:18.976708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 12:18:18.976790 ==
5821 12:18:18.980228 Write leveling (Byte 0): 27 => 27
5822 12:18:18.983428 Write leveling (Byte 1): 28 => 28
5823 12:18:18.986689 DramcWriteLeveling(PI) end<-----
5824 12:18:18.986796
5825 12:18:18.986861 ==
5826 12:18:18.990085 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 12:18:18.993471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 12:18:18.993554 ==
5829 12:18:18.997145 [Gating] SW mode calibration
5830 12:18:19.003142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5831 12:18:19.010413 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5832 12:18:19.013296 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 12:18:19.016908 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 12:18:19.023004 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 12:18:19.026682 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 12:18:19.029630 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 12:18:19.036271 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5838 12:18:19.039942 0 14 24 | B1->B0 | 3535 2a2a | 0 0 | (0 1) (0 0)
5839 12:18:19.043476 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 12:18:19.046515 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 12:18:19.053127 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 12:18:19.056647 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 12:18:19.060146 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 12:18:19.066901 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 12:18:19.069915 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 12:18:19.073366 0 15 24 | B1->B0 | 2b2b 3939 | 0 0 | (1 1) (0 0)
5847 12:18:19.079796 0 15 28 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
5848 12:18:19.083215 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 12:18:19.086976 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 12:18:19.093535 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 12:18:19.096617 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 12:18:19.100251 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 12:18:19.106924 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5854 12:18:19.110191 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5855 12:18:19.113619 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5856 12:18:19.116754 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 12:18:19.123374 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:18:19.126615 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 12:18:19.130097 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 12:18:19.136981 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 12:18:19.139935 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 12:18:19.143441 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 12:18:19.150310 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 12:18:19.153831 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 12:18:19.157010 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 12:18:19.163664 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 12:18:19.166659 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 12:18:19.170325 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 12:18:19.177231 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 12:18:19.180173 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5871 12:18:19.183781 Total UI for P1: 0, mck2ui 16
5872 12:18:19.186615 best dqsien dly found for B0: ( 1, 2, 22)
5873 12:18:19.190156 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 12:18:19.193473 Total UI for P1: 0, mck2ui 16
5875 12:18:19.197394 best dqsien dly found for B1: ( 1, 2, 24)
5876 12:18:19.200220 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5877 12:18:19.203688 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5878 12:18:19.203790
5879 12:18:19.206943 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5880 12:18:19.213323 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5881 12:18:19.213431 [Gating] SW calibration Done
5882 12:18:19.213560 ==
5883 12:18:19.216864 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 12:18:19.223526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 12:18:19.223630 ==
5886 12:18:19.223727 RX Vref Scan: 0
5887 12:18:19.223815
5888 12:18:19.226851 RX Vref 0 -> 0, step: 1
5889 12:18:19.226935
5890 12:18:19.230578 RX Delay -80 -> 252, step: 8
5891 12:18:19.233579 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5892 12:18:19.237311 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5893 12:18:19.240227 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5894 12:18:19.248759 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5895 12:18:19.250250 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5896 12:18:19.253552 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5897 12:18:19.257017 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5898 12:18:19.260608 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5899 12:18:19.264106 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5900 12:18:19.267046 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5901 12:18:19.273942 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5902 12:18:19.277018 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5903 12:18:19.280440 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5904 12:18:19.284087 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5905 12:18:19.287649 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5906 12:18:19.290605 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5907 12:18:19.293917 ==
5908 12:18:19.294414 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 12:18:19.300464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 12:18:19.301032 ==
5911 12:18:19.301570 DQS Delay:
5912 12:18:19.304118 DQS0 = 0, DQS1 = 0
5913 12:18:19.304602 DQM Delay:
5914 12:18:19.307547 DQM0 = 94, DQM1 = 89
5915 12:18:19.308219 DQ Delay:
5916 12:18:19.310367 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5917 12:18:19.314398 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5918 12:18:19.317185 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5919 12:18:19.320553 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5920 12:18:19.320946
5921 12:18:19.321306
5922 12:18:19.321592 ==
5923 12:18:19.324283 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 12:18:19.327244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 12:18:19.327626 ==
5926 12:18:19.327906
5927 12:18:19.327964
5928 12:18:19.330976 TX Vref Scan disable
5929 12:18:19.331085 == TX Byte 0 ==
5930 12:18:19.337340 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5931 12:18:19.340878 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5932 12:18:19.340985 == TX Byte 1 ==
5933 12:18:19.347282 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5934 12:18:19.350920 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5935 12:18:19.351009 ==
5936 12:18:19.353659 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 12:18:19.357210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 12:18:19.357297 ==
5939 12:18:19.357381
5940 12:18:19.360913
5941 12:18:19.360997 TX Vref Scan disable
5942 12:18:19.363985 == TX Byte 0 ==
5943 12:18:19.366868 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5944 12:18:19.370348 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5945 12:18:19.373840 == TX Byte 1 ==
5946 12:18:19.376882 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5947 12:18:19.380562 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5948 12:18:19.380647
5949 12:18:19.383942 [DATLAT]
5950 12:18:19.384026 Freq=933, CH1 RK1
5951 12:18:19.384110
5952 12:18:19.386970 DATLAT Default: 0xb
5953 12:18:19.387054 0, 0xFFFF, sum = 0
5954 12:18:19.390290 1, 0xFFFF, sum = 0
5955 12:18:19.390376 2, 0xFFFF, sum = 0
5956 12:18:19.393786 3, 0xFFFF, sum = 0
5957 12:18:19.393871 4, 0xFFFF, sum = 0
5958 12:18:19.397420 5, 0xFFFF, sum = 0
5959 12:18:19.397506 6, 0xFFFF, sum = 0
5960 12:18:19.400687 7, 0xFFFF, sum = 0
5961 12:18:19.400772 8, 0xFFFF, sum = 0
5962 12:18:19.403869 9, 0xFFFF, sum = 0
5963 12:18:19.403969 10, 0x0, sum = 1
5964 12:18:19.407175 11, 0x0, sum = 2
5965 12:18:19.407280 12, 0x0, sum = 3
5966 12:18:19.410962 13, 0x0, sum = 4
5967 12:18:19.411065 best_step = 11
5968 12:18:19.411146
5969 12:18:19.411225 ==
5970 12:18:19.413747 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 12:18:19.420650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 12:18:19.420736 ==
5973 12:18:19.420811 RX Vref Scan: 0
5974 12:18:19.420873
5975 12:18:19.424286 RX Vref 0 -> 0, step: 1
5976 12:18:19.424399
5977 12:18:19.427373 RX Delay -61 -> 252, step: 4
5978 12:18:19.430445 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5979 12:18:19.433903 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5980 12:18:19.440430 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5981 12:18:19.443886 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5982 12:18:19.447598 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5983 12:18:19.450624 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5984 12:18:19.454194 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5985 12:18:19.457281 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5986 12:18:19.464085 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5987 12:18:19.467494 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5988 12:18:19.470520 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5989 12:18:19.474043 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5990 12:18:19.477115 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5991 12:18:19.480692 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5992 12:18:19.487912 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5993 12:18:19.491200 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5994 12:18:19.491335 ==
5995 12:18:19.494046 Dram Type= 6, Freq= 0, CH_1, rank 1
5996 12:18:19.497657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5997 12:18:19.497790 ==
5998 12:18:19.501044 DQS Delay:
5999 12:18:19.501145 DQS0 = 0, DQS1 = 0
6000 12:18:19.501211 DQM Delay:
6001 12:18:19.504112 DQM0 = 94, DQM1 = 90
6002 12:18:19.504199 DQ Delay:
6003 12:18:19.507293 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
6004 12:18:19.510555 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =90
6005 12:18:19.514258 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
6006 12:18:19.517134 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
6007 12:18:19.517216
6008 12:18:19.517279
6009 12:18:19.527088 [DQSOSCAuto] RK1, (LSB)MR18= 0x111a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
6010 12:18:19.527172 CH1 RK1: MR19=505, MR18=111A
6011 12:18:19.533886 CH1_RK1: MR19=0x505, MR18=0x111A, DQSOSC=413, MR23=63, INC=63, DEC=42
6012 12:18:19.537512 [RxdqsGatingPostProcess] freq 933
6013 12:18:19.544167 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6014 12:18:19.547698 best DQS0 dly(2T, 0.5T) = (0, 10)
6015 12:18:19.550920 best DQS1 dly(2T, 0.5T) = (0, 10)
6016 12:18:19.554379 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6017 12:18:19.557671 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6018 12:18:19.560519 best DQS0 dly(2T, 0.5T) = (0, 10)
6019 12:18:19.560604 best DQS1 dly(2T, 0.5T) = (0, 10)
6020 12:18:19.564033 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6021 12:18:19.568105 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6022 12:18:19.571044 Pre-setting of DQS Precalculation
6023 12:18:19.577418 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6024 12:18:19.584371 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6025 12:18:19.590808 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6026 12:18:19.590898
6027 12:18:19.590975
6028 12:18:19.593917 [Calibration Summary] 1866 Mbps
6029 12:18:19.594000 CH 0, Rank 0
6030 12:18:19.597918 SW Impedance : PASS
6031 12:18:19.600786 DUTY Scan : NO K
6032 12:18:19.600865 ZQ Calibration : PASS
6033 12:18:19.604341 Jitter Meter : NO K
6034 12:18:19.607322 CBT Training : PASS
6035 12:18:19.607395 Write leveling : PASS
6036 12:18:19.610973 RX DQS gating : PASS
6037 12:18:19.614004 RX DQ/DQS(RDDQC) : PASS
6038 12:18:19.614078 TX DQ/DQS : PASS
6039 12:18:19.617345 RX DATLAT : PASS
6040 12:18:19.617428 RX DQ/DQS(Engine): PASS
6041 12:18:19.620670 TX OE : NO K
6042 12:18:19.620742 All Pass.
6043 12:18:19.620803
6044 12:18:19.624434 CH 0, Rank 1
6045 12:18:19.624515 SW Impedance : PASS
6046 12:18:19.627884 DUTY Scan : NO K
6047 12:18:19.630854 ZQ Calibration : PASS
6048 12:18:19.630931 Jitter Meter : NO K
6049 12:18:19.634335 CBT Training : PASS
6050 12:18:19.637807 Write leveling : PASS
6051 12:18:19.637890 RX DQS gating : PASS
6052 12:18:19.641248 RX DQ/DQS(RDDQC) : PASS
6053 12:18:19.644260 TX DQ/DQS : PASS
6054 12:18:19.644340 RX DATLAT : PASS
6055 12:18:19.647708 RX DQ/DQS(Engine): PASS
6056 12:18:19.650822 TX OE : NO K
6057 12:18:19.650895 All Pass.
6058 12:18:19.650966
6059 12:18:19.651038 CH 1, Rank 0
6060 12:18:19.654835 SW Impedance : PASS
6061 12:18:19.657713 DUTY Scan : NO K
6062 12:18:19.657784 ZQ Calibration : PASS
6063 12:18:19.661201 Jitter Meter : NO K
6064 12:18:19.661273 CBT Training : PASS
6065 12:18:19.664426 Write leveling : PASS
6066 12:18:19.667498 RX DQS gating : PASS
6067 12:18:19.667585 RX DQ/DQS(RDDQC) : PASS
6068 12:18:19.671128 TX DQ/DQS : PASS
6069 12:18:19.674615 RX DATLAT : PASS
6070 12:18:19.674753 RX DQ/DQS(Engine): PASS
6071 12:18:19.678193 TX OE : NO K
6072 12:18:19.678282 All Pass.
6073 12:18:19.678351
6074 12:18:19.681118 CH 1, Rank 1
6075 12:18:19.681220 SW Impedance : PASS
6076 12:18:19.684361 DUTY Scan : NO K
6077 12:18:19.687824 ZQ Calibration : PASS
6078 12:18:19.687925 Jitter Meter : NO K
6079 12:18:19.690926 CBT Training : PASS
6080 12:18:19.694997 Write leveling : PASS
6081 12:18:19.695103 RX DQS gating : PASS
6082 12:18:19.697792 RX DQ/DQS(RDDQC) : PASS
6083 12:18:19.697866 TX DQ/DQS : PASS
6084 12:18:19.700943 RX DATLAT : PASS
6085 12:18:19.704694 RX DQ/DQS(Engine): PASS
6086 12:18:19.704796 TX OE : NO K
6087 12:18:19.707726 All Pass.
6088 12:18:19.707824
6089 12:18:19.707914 DramC Write-DBI off
6090 12:18:19.711123 PER_BANK_REFRESH: Hybrid Mode
6091 12:18:19.714614 TX_TRACKING: ON
6092 12:18:19.721142 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6093 12:18:19.724691 [FAST_K] Save calibration result to emmc
6094 12:18:19.728181 dramc_set_vcore_voltage set vcore to 650000
6095 12:18:19.731324 Read voltage for 400, 6
6096 12:18:19.731507 Vio18 = 0
6097 12:18:19.734924 Vcore = 650000
6098 12:18:19.735007 Vdram = 0
6099 12:18:19.735100 Vddq = 0
6100 12:18:19.737827 Vmddr = 0
6101 12:18:19.742089 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6102 12:18:19.748303 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6103 12:18:19.748415 MEM_TYPE=3, freq_sel=20
6104 12:18:19.751709 sv_algorithm_assistance_LP4_800
6105 12:18:19.754535 ============ PULL DRAM RESETB DOWN ============
6106 12:18:19.761497 ========== PULL DRAM RESETB DOWN end =========
6107 12:18:19.764951 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6108 12:18:19.768290 ===================================
6109 12:18:19.771746 LPDDR4 DRAM CONFIGURATION
6110 12:18:19.774666 ===================================
6111 12:18:19.774813 EX_ROW_EN[0] = 0x0
6112 12:18:19.778388 EX_ROW_EN[1] = 0x0
6113 12:18:19.778501 LP4Y_EN = 0x0
6114 12:18:19.781908 WORK_FSP = 0x0
6115 12:18:19.782007 WL = 0x2
6116 12:18:19.785378 RL = 0x2
6117 12:18:19.785482 BL = 0x2
6118 12:18:19.788514 RPST = 0x0
6119 12:18:19.791865 RD_PRE = 0x0
6120 12:18:19.791969 WR_PRE = 0x1
6121 12:18:19.795432 WR_PST = 0x0
6122 12:18:19.795543 DBI_WR = 0x0
6123 12:18:19.798143 DBI_RD = 0x0
6124 12:18:19.798255 OTF = 0x1
6125 12:18:19.801665 ===================================
6126 12:18:19.804906 ===================================
6127 12:18:19.805005 ANA top config
6128 12:18:19.808314 ===================================
6129 12:18:19.811432 DLL_ASYNC_EN = 0
6130 12:18:19.815017 ALL_SLAVE_EN = 1
6131 12:18:19.818130 NEW_RANK_MODE = 1
6132 12:18:19.821889 DLL_IDLE_MODE = 1
6133 12:18:19.821988 LP45_APHY_COMB_EN = 1
6134 12:18:19.825367 TX_ODT_DIS = 1
6135 12:18:19.828292 NEW_8X_MODE = 1
6136 12:18:19.831700 ===================================
6137 12:18:19.835166 ===================================
6138 12:18:19.838302 data_rate = 800
6139 12:18:19.841673 CKR = 1
6140 12:18:19.841777 DQ_P2S_RATIO = 4
6141 12:18:19.844805 ===================================
6142 12:18:19.848343 CA_P2S_RATIO = 4
6143 12:18:19.851749 DQ_CA_OPEN = 0
6144 12:18:19.854908 DQ_SEMI_OPEN = 1
6145 12:18:19.858333 CA_SEMI_OPEN = 1
6146 12:18:19.858406 CA_FULL_RATE = 0
6147 12:18:19.862090 DQ_CKDIV4_EN = 0
6148 12:18:19.864999 CA_CKDIV4_EN = 1
6149 12:18:19.868725 CA_PREDIV_EN = 0
6150 12:18:19.871947 PH8_DLY = 0
6151 12:18:19.875491 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6152 12:18:19.875573 DQ_AAMCK_DIV = 0
6153 12:18:19.878383 CA_AAMCK_DIV = 0
6154 12:18:19.882135 CA_ADMCK_DIV = 4
6155 12:18:19.885441 DQ_TRACK_CA_EN = 0
6156 12:18:19.889062 CA_PICK = 800
6157 12:18:19.892108 CA_MCKIO = 400
6158 12:18:19.895353 MCKIO_SEMI = 400
6159 12:18:19.895506 PLL_FREQ = 3016
6160 12:18:19.898869 DQ_UI_PI_RATIO = 32
6161 12:18:19.901893 CA_UI_PI_RATIO = 32
6162 12:18:19.905381 ===================================
6163 12:18:19.909048 ===================================
6164 12:18:19.912039 memory_type:LPDDR4
6165 12:18:19.912188 GP_NUM : 10
6166 12:18:19.915607 SRAM_EN : 1
6167 12:18:19.918863 MD32_EN : 0
6168 12:18:19.921772 ===================================
6169 12:18:19.921980 [ANA_INIT] >>>>>>>>>>>>>>
6170 12:18:19.925459 <<<<<< [CONFIGURE PHASE]: ANA_TX
6171 12:18:19.928604 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6172 12:18:19.931906 ===================================
6173 12:18:19.935861 data_rate = 800,PCW = 0X7400
6174 12:18:19.938845 ===================================
6175 12:18:19.942424 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6176 12:18:19.949087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6177 12:18:19.959196 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6178 12:18:19.962374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6179 12:18:19.969207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6180 12:18:19.972182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6181 12:18:19.972631 [ANA_INIT] flow start
6182 12:18:19.975803 [ANA_INIT] PLL >>>>>>>>
6183 12:18:19.978965 [ANA_INIT] PLL <<<<<<<<
6184 12:18:19.979404 [ANA_INIT] MIDPI >>>>>>>>
6185 12:18:19.982543 [ANA_INIT] MIDPI <<<<<<<<
6186 12:18:19.986032 [ANA_INIT] DLL >>>>>>>>
6187 12:18:19.986449 [ANA_INIT] flow end
6188 12:18:19.988737 ============ LP4 DIFF to SE enter ============
6189 12:18:19.995819 ============ LP4 DIFF to SE exit ============
6190 12:18:19.996241 [ANA_INIT] <<<<<<<<<<<<<
6191 12:18:19.998894 [Flow] Enable top DCM control >>>>>
6192 12:18:20.002247 [Flow] Enable top DCM control <<<<<
6193 12:18:20.005808 Enable DLL master slave shuffle
6194 12:18:20.012556 ==============================================================
6195 12:18:20.012980 Gating Mode config
6196 12:18:20.019419 ==============================================================
6197 12:18:20.022410 Config description:
6198 12:18:20.032320 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6199 12:18:20.035654 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6200 12:18:20.042551 SELPH_MODE 0: By rank 1: By Phase
6201 12:18:20.048987 ==============================================================
6202 12:18:20.049069 GAT_TRACK_EN = 0
6203 12:18:20.052253 RX_GATING_MODE = 2
6204 12:18:20.055705 RX_GATING_TRACK_MODE = 2
6205 12:18:20.058994 SELPH_MODE = 1
6206 12:18:20.062253 PICG_EARLY_EN = 1
6207 12:18:20.066094 VALID_LAT_VALUE = 1
6208 12:18:20.072490 ==============================================================
6209 12:18:20.075995 Enter into Gating configuration >>>>
6210 12:18:20.079031 Exit from Gating configuration <<<<
6211 12:18:20.082372 Enter into DVFS_PRE_config >>>>>
6212 12:18:20.092935 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6213 12:18:20.095777 Exit from DVFS_PRE_config <<<<<
6214 12:18:20.099320 Enter into PICG configuration >>>>
6215 12:18:20.102522 Exit from PICG configuration <<<<
6216 12:18:20.102603 [RX_INPUT] configuration >>>>>
6217 12:18:20.105995 [RX_INPUT] configuration <<<<<
6218 12:18:20.112268 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6219 12:18:20.115985 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6220 12:18:20.123053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6221 12:18:20.129282 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6222 12:18:20.135654 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6223 12:18:20.142728 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6224 12:18:20.146000 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6225 12:18:20.149296 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6226 12:18:20.155866 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6227 12:18:20.159032 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6228 12:18:20.162402 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6229 12:18:20.165861 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 12:18:20.169042 ===================================
6231 12:18:20.172078 LPDDR4 DRAM CONFIGURATION
6232 12:18:20.175709 ===================================
6233 12:18:20.179089 EX_ROW_EN[0] = 0x0
6234 12:18:20.179176 EX_ROW_EN[1] = 0x0
6235 12:18:20.182426 LP4Y_EN = 0x0
6236 12:18:20.182513 WORK_FSP = 0x0
6237 12:18:20.186151 WL = 0x2
6238 12:18:20.186244 RL = 0x2
6239 12:18:20.188976 BL = 0x2
6240 12:18:20.189077 RPST = 0x0
6241 12:18:20.192503 RD_PRE = 0x0
6242 12:18:20.192685 WR_PRE = 0x1
6243 12:18:20.196167 WR_PST = 0x0
6244 12:18:20.196363 DBI_WR = 0x0
6245 12:18:20.199167 DBI_RD = 0x0
6246 12:18:20.199348 OTF = 0x1
6247 12:18:20.202639 ===================================
6248 12:18:20.209036 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6249 12:18:20.212615 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6250 12:18:20.216086 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6251 12:18:20.219073 ===================================
6252 12:18:20.222245 LPDDR4 DRAM CONFIGURATION
6253 12:18:20.225799 ===================================
6254 12:18:20.229533 EX_ROW_EN[0] = 0x10
6255 12:18:20.229630 EX_ROW_EN[1] = 0x0
6256 12:18:20.232831 LP4Y_EN = 0x0
6257 12:18:20.232934 WORK_FSP = 0x0
6258 12:18:20.235962 WL = 0x2
6259 12:18:20.236071 RL = 0x2
6260 12:18:20.239229 BL = 0x2
6261 12:18:20.239342 RPST = 0x0
6262 12:18:20.242258 RD_PRE = 0x0
6263 12:18:20.242370 WR_PRE = 0x1
6264 12:18:20.246030 WR_PST = 0x0
6265 12:18:20.246153 DBI_WR = 0x0
6266 12:18:20.249561 DBI_RD = 0x0
6267 12:18:20.249700 OTF = 0x1
6268 12:18:20.252785 ===================================
6269 12:18:20.259199 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6270 12:18:20.263631 nWR fixed to 30
6271 12:18:20.266759 [ModeRegInit_LP4] CH0 RK0
6272 12:18:20.266971 [ModeRegInit_LP4] CH0 RK1
6273 12:18:20.270710 [ModeRegInit_LP4] CH1 RK0
6274 12:18:20.273877 [ModeRegInit_LP4] CH1 RK1
6275 12:18:20.274201 match AC timing 19
6276 12:18:20.280565 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6277 12:18:20.283576 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6278 12:18:20.286714 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6279 12:18:20.293691 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6280 12:18:20.297512 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6281 12:18:20.298024 ==
6282 12:18:20.300240 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 12:18:20.303785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 12:18:20.304206 ==
6285 12:18:20.310240 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 12:18:20.317197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6287 12:18:20.320648 [CA 0] Center 36 (8~64) winsize 57
6288 12:18:20.323763 [CA 1] Center 36 (8~64) winsize 57
6289 12:18:20.324154 [CA 2] Center 36 (8~64) winsize 57
6290 12:18:20.327160 [CA 3] Center 36 (8~64) winsize 57
6291 12:18:20.330293 [CA 4] Center 36 (8~64) winsize 57
6292 12:18:20.333837 [CA 5] Center 36 (8~64) winsize 57
6293 12:18:20.334261
6294 12:18:20.337256 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6295 12:18:20.337681
6296 12:18:20.343915 [CATrainingPosCal] consider 1 rank data
6297 12:18:20.344359 u2DelayCellTimex100 = 270/100 ps
6298 12:18:20.347270 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 12:18:20.353707 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 12:18:20.356866 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 12:18:20.360429 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 12:18:20.363696 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 12:18:20.367306 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 12:18:20.367730
6305 12:18:20.370339 CA PerBit enable=1, Macro0, CA PI delay=36
6306 12:18:20.370836
6307 12:18:20.374131 [CBTSetCACLKResult] CA Dly = 36
6308 12:18:20.374575 CS Dly: 1 (0~32)
6309 12:18:20.377186 ==
6310 12:18:20.380621 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 12:18:20.383771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 12:18:20.384195 ==
6313 12:18:20.386928 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6314 12:18:20.393916 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6315 12:18:20.397162 [CA 0] Center 36 (8~64) winsize 57
6316 12:18:20.400397 [CA 1] Center 36 (8~64) winsize 57
6317 12:18:20.403492 [CA 2] Center 36 (8~64) winsize 57
6318 12:18:20.407133 [CA 3] Center 36 (8~64) winsize 57
6319 12:18:20.410598 [CA 4] Center 36 (8~64) winsize 57
6320 12:18:20.413794 [CA 5] Center 36 (8~64) winsize 57
6321 12:18:20.414268
6322 12:18:20.417149 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6323 12:18:20.417621
6324 12:18:20.420793 [CATrainingPosCal] consider 2 rank data
6325 12:18:20.423716 u2DelayCellTimex100 = 270/100 ps
6326 12:18:20.427322 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 12:18:20.430972 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 12:18:20.433832 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 12:18:20.437612 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 12:18:20.440597 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 12:18:20.447557 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 12:18:20.448110
6333 12:18:20.450551 CA PerBit enable=1, Macro0, CA PI delay=36
6334 12:18:20.451028
6335 12:18:20.454112 [CBTSetCACLKResult] CA Dly = 36
6336 12:18:20.454547 CS Dly: 1 (0~32)
6337 12:18:20.454956
6338 12:18:20.457497 ----->DramcWriteLeveling(PI) begin...
6339 12:18:20.457942 ==
6340 12:18:20.460682 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 12:18:20.464048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 12:18:20.467302 ==
6343 12:18:20.467722 Write leveling (Byte 0): 40 => 8
6344 12:18:20.470552 Write leveling (Byte 1): 32 => 0
6345 12:18:20.474067 DramcWriteLeveling(PI) end<-----
6346 12:18:20.474485
6347 12:18:20.474944 ==
6348 12:18:20.477513 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 12:18:20.480502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 12:18:20.484377 ==
6351 12:18:20.484794 [Gating] SW mode calibration
6352 12:18:20.493744 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6353 12:18:20.497299 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6354 12:18:20.500498 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6355 12:18:20.507450 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6356 12:18:20.510504 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 12:18:20.514039 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 12:18:20.520867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 12:18:20.524056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 12:18:20.526994 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 12:18:20.533761 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 12:18:20.537277 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6363 12:18:20.540907 Total UI for P1: 0, mck2ui 16
6364 12:18:20.544366 best dqsien dly found for B0: ( 0, 14, 24)
6365 12:18:20.547242 Total UI for P1: 0, mck2ui 16
6366 12:18:20.550831 best dqsien dly found for B1: ( 0, 14, 24)
6367 12:18:20.554345 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6368 12:18:20.557756 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6369 12:18:20.558068
6370 12:18:20.561250 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6371 12:18:20.563954 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6372 12:18:20.567363 [Gating] SW calibration Done
6373 12:18:20.567585 ==
6374 12:18:20.570484 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 12:18:20.574147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 12:18:20.574369 ==
6377 12:18:20.577103 RX Vref Scan: 0
6378 12:18:20.577325
6379 12:18:20.580920 RX Vref 0 -> 0, step: 1
6380 12:18:20.581142
6381 12:18:20.581332 RX Delay -410 -> 252, step: 16
6382 12:18:20.587581 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6383 12:18:20.590894 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6384 12:18:20.594429 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6385 12:18:20.597610 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6386 12:18:20.604256 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6387 12:18:20.607702 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6388 12:18:20.611175 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6389 12:18:20.614481 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6390 12:18:20.621282 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6391 12:18:20.624501 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6392 12:18:20.627830 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6393 12:18:20.631524 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6394 12:18:20.638097 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6395 12:18:20.641030 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6396 12:18:20.644654 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6397 12:18:20.648197 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6398 12:18:20.651395 ==
6399 12:18:20.654617 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 12:18:20.658014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 12:18:20.658446 ==
6402 12:18:20.658823 DQS Delay:
6403 12:18:20.661027 DQS0 = 35, DQS1 = 51
6404 12:18:20.661463 DQM Delay:
6405 12:18:20.664564 DQM0 = 6, DQM1 = 11
6406 12:18:20.664985 DQ Delay:
6407 12:18:20.667947 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6408 12:18:20.670536 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6409 12:18:20.670643 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6410 12:18:20.677794 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6411 12:18:20.677874
6412 12:18:20.677937
6413 12:18:20.677994 ==
6414 12:18:20.680946 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 12:18:20.684641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 12:18:20.684726 ==
6417 12:18:20.684790
6418 12:18:20.684848
6419 12:18:20.687456 TX Vref Scan disable
6420 12:18:20.687536 == TX Byte 0 ==
6421 12:18:20.690630 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 12:18:20.697608 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 12:18:20.697715 == TX Byte 1 ==
6424 12:18:20.701115 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6425 12:18:20.707442 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6426 12:18:20.707576 ==
6427 12:18:20.710682 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 12:18:20.714111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 12:18:20.714234 ==
6430 12:18:20.714323
6431 12:18:20.714403
6432 12:18:20.717904 TX Vref Scan disable
6433 12:18:20.718048 == TX Byte 0 ==
6434 12:18:20.724186 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 12:18:20.727483 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 12:18:20.727564 == TX Byte 1 ==
6437 12:18:20.730859 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6438 12:18:20.738057 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6439 12:18:20.738139
6440 12:18:20.738203 [DATLAT]
6441 12:18:20.740974 Freq=400, CH0 RK0
6442 12:18:20.741073
6443 12:18:20.741167 DATLAT Default: 0xf
6444 12:18:20.744538 0, 0xFFFF, sum = 0
6445 12:18:20.744626 1, 0xFFFF, sum = 0
6446 12:18:20.747921 2, 0xFFFF, sum = 0
6447 12:18:20.748014 3, 0xFFFF, sum = 0
6448 12:18:20.751090 4, 0xFFFF, sum = 0
6449 12:18:20.751185 5, 0xFFFF, sum = 0
6450 12:18:20.754831 6, 0xFFFF, sum = 0
6451 12:18:20.755558 7, 0xFFFF, sum = 0
6452 12:18:20.758650 8, 0xFFFF, sum = 0
6453 12:18:20.759412 9, 0xFFFF, sum = 0
6454 12:18:20.761292 10, 0xFFFF, sum = 0
6455 12:18:20.761724 11, 0xFFFF, sum = 0
6456 12:18:20.764936 12, 0xFFFF, sum = 0
6457 12:18:20.765373 13, 0x0, sum = 1
6458 12:18:20.768105 14, 0x0, sum = 2
6459 12:18:20.768605 15, 0x0, sum = 3
6460 12:18:20.771354 16, 0x0, sum = 4
6461 12:18:20.771775 best_step = 14
6462 12:18:20.772135
6463 12:18:20.772484 ==
6464 12:18:20.774834 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 12:18:20.778561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 12:18:20.781317 ==
6467 12:18:20.781752 RX Vref Scan: 1
6468 12:18:20.782079
6469 12:18:20.785137 RX Vref 0 -> 0, step: 1
6470 12:18:20.785551
6471 12:18:20.788615 RX Delay -343 -> 252, step: 8
6472 12:18:20.789032
6473 12:18:20.791450 Set Vref, RX VrefLevel [Byte0]: 54
6474 12:18:20.794763 [Byte1]: 51
6475 12:18:20.795184
6476 12:18:20.798052 Final RX Vref Byte 0 = 54 to rank0
6477 12:18:20.801860 Final RX Vref Byte 1 = 51 to rank0
6478 12:18:20.805298 Final RX Vref Byte 0 = 54 to rank1
6479 12:18:20.808050 Final RX Vref Byte 1 = 51 to rank1==
6480 12:18:20.811579 Dram Type= 6, Freq= 0, CH_0, rank 0
6481 12:18:20.815308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 12:18:20.815838 ==
6483 12:18:20.818669 DQS Delay:
6484 12:18:20.819151 DQS0 = 44, DQS1 = 60
6485 12:18:20.821645 DQM Delay:
6486 12:18:20.822079 DQM0 = 11, DQM1 = 15
6487 12:18:20.822403 DQ Delay:
6488 12:18:20.825178 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6489 12:18:20.828310 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6490 12:18:20.831281 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6491 12:18:20.835232 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6492 12:18:20.835665
6493 12:18:20.835997
6494 12:18:20.844979 [DQSOSCAuto] RK0, (LSB)MR18= 0x8856, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6495 12:18:20.845064 CH0 RK0: MR19=C0C, MR18=8856
6496 12:18:20.851660 CH0_RK0: MR19=0xC0C, MR18=0x8856, DQSOSC=392, MR23=63, INC=384, DEC=256
6497 12:18:20.851816 ==
6498 12:18:20.854612 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 12:18:20.861060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 12:18:20.861210 ==
6501 12:18:20.864914 [Gating] SW mode calibration
6502 12:18:20.871387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6503 12:18:20.874875 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6504 12:18:20.881518 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6505 12:18:20.885025 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6506 12:18:20.888429 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 12:18:20.891573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 12:18:20.898067 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 12:18:20.901554 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 12:18:20.905072 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 12:18:20.911584 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 12:18:20.915295 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6513 12:18:20.918489 Total UI for P1: 0, mck2ui 16
6514 12:18:20.921515 best dqsien dly found for B0: ( 0, 14, 24)
6515 12:18:20.924908 Total UI for P1: 0, mck2ui 16
6516 12:18:20.928618 best dqsien dly found for B1: ( 0, 14, 24)
6517 12:18:20.931801 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6518 12:18:20.935309 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6519 12:18:20.935776
6520 12:18:20.938409 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6521 12:18:20.942075 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6522 12:18:20.944842 [Gating] SW calibration Done
6523 12:18:20.945262 ==
6524 12:18:20.948111 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 12:18:20.955180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 12:18:20.955621 ==
6527 12:18:20.955969 RX Vref Scan: 0
6528 12:18:20.956287
6529 12:18:20.958718 RX Vref 0 -> 0, step: 1
6530 12:18:20.959193
6531 12:18:20.961975 RX Delay -410 -> 252, step: 16
6532 12:18:20.964961 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6533 12:18:20.968516 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6534 12:18:20.971310 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6535 12:18:20.978539 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6536 12:18:20.982015 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6537 12:18:20.985072 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6538 12:18:20.988476 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6539 12:18:20.994935 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6540 12:18:20.998207 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6541 12:18:21.001624 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6542 12:18:21.005129 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6543 12:18:21.012171 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6544 12:18:21.015012 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6545 12:18:21.018307 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6546 12:18:21.024694 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6547 12:18:21.028128 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6548 12:18:21.028585 ==
6549 12:18:21.031797 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 12:18:21.035131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 12:18:21.035553 ==
6552 12:18:21.035956 DQS Delay:
6553 12:18:21.038443 DQS0 = 43, DQS1 = 51
6554 12:18:21.038999 DQM Delay:
6555 12:18:21.041466 DQM0 = 11, DQM1 = 10
6556 12:18:21.042110 DQ Delay:
6557 12:18:21.044809 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6558 12:18:21.048509 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6559 12:18:21.051635 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6560 12:18:21.055006 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6561 12:18:21.055461
6562 12:18:21.055791
6563 12:18:21.056122 ==
6564 12:18:21.058057 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 12:18:21.062122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 12:18:21.062564 ==
6567 12:18:21.062970
6568 12:18:21.063289
6569 12:18:21.065088 TX Vref Scan disable
6570 12:18:21.068549 == TX Byte 0 ==
6571 12:18:21.071855 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6572 12:18:21.074952 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6573 12:18:21.075376 == TX Byte 1 ==
6574 12:18:21.081621 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6575 12:18:21.085029 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6576 12:18:21.085448 ==
6577 12:18:21.088526 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 12:18:21.091932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 12:18:21.092353 ==
6580 12:18:21.092870
6581 12:18:21.093273
6582 12:18:21.094991 TX Vref Scan disable
6583 12:18:21.095428 == TX Byte 0 ==
6584 12:18:21.102152 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6585 12:18:21.105356 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6586 12:18:21.105793 == TX Byte 1 ==
6587 12:18:21.111983 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6588 12:18:21.114862 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6589 12:18:21.114944
6590 12:18:21.115009 [DATLAT]
6591 12:18:21.118233 Freq=400, CH0 RK1
6592 12:18:21.118314
6593 12:18:21.118377 DATLAT Default: 0xe
6594 12:18:21.121860 0, 0xFFFF, sum = 0
6595 12:18:21.121942 1, 0xFFFF, sum = 0
6596 12:18:21.124751 2, 0xFFFF, sum = 0
6597 12:18:21.124834 3, 0xFFFF, sum = 0
6598 12:18:21.128364 4, 0xFFFF, sum = 0
6599 12:18:21.128447 5, 0xFFFF, sum = 0
6600 12:18:21.131344 6, 0xFFFF, sum = 0
6601 12:18:21.131426 7, 0xFFFF, sum = 0
6602 12:18:21.135101 8, 0xFFFF, sum = 0
6603 12:18:21.135183 9, 0xFFFF, sum = 0
6604 12:18:21.138308 10, 0xFFFF, sum = 0
6605 12:18:21.141659 11, 0xFFFF, sum = 0
6606 12:18:21.141742 12, 0xFFFF, sum = 0
6607 12:18:21.145117 13, 0x0, sum = 1
6608 12:18:21.145209 14, 0x0, sum = 2
6609 12:18:21.145282 15, 0x0, sum = 3
6610 12:18:21.148081 16, 0x0, sum = 4
6611 12:18:21.148176 best_step = 14
6612 12:18:21.148248
6613 12:18:21.148316 ==
6614 12:18:21.152203 Dram Type= 6, Freq= 0, CH_0, rank 1
6615 12:18:21.158278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 12:18:21.158388 ==
6617 12:18:21.158475 RX Vref Scan: 0
6618 12:18:21.158557
6619 12:18:21.161869 RX Vref 0 -> 0, step: 1
6620 12:18:21.161978
6621 12:18:21.164761 RX Delay -343 -> 252, step: 8
6622 12:18:21.171723 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6623 12:18:21.174929 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6624 12:18:21.178763 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6625 12:18:21.182325 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6626 12:18:21.188791 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6627 12:18:21.192282 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6628 12:18:21.195688 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6629 12:18:21.198530 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6630 12:18:21.205253 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6631 12:18:21.209046 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6632 12:18:21.212443 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6633 12:18:21.215304 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6634 12:18:21.222213 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6635 12:18:21.225720 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6636 12:18:21.229219 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6637 12:18:21.232120 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6638 12:18:21.235764 ==
6639 12:18:21.236179 Dram Type= 6, Freq= 0, CH_0, rank 1
6640 12:18:21.242530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 12:18:21.243069 ==
6642 12:18:21.243426 DQS Delay:
6643 12:18:21.245377 DQS0 = 48, DQS1 = 60
6644 12:18:21.245798 DQM Delay:
6645 12:18:21.249142 DQM0 = 14, DQM1 = 13
6646 12:18:21.249578 DQ Delay:
6647 12:18:21.252204 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6648 12:18:21.255638 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =24
6649 12:18:21.258703 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6650 12:18:21.262140 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6651 12:18:21.262557
6652 12:18:21.262975
6653 12:18:21.268900 [DQSOSCAuto] RK1, (LSB)MR18= 0x9365, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6654 12:18:21.271752 CH0 RK1: MR19=C0C, MR18=9365
6655 12:18:21.279021 CH0_RK1: MR19=0xC0C, MR18=0x9365, DQSOSC=391, MR23=63, INC=386, DEC=257
6656 12:18:21.282398 [RxdqsGatingPostProcess] freq 400
6657 12:18:21.285557 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6658 12:18:21.288402 best DQS0 dly(2T, 0.5T) = (0, 10)
6659 12:18:21.292005 best DQS1 dly(2T, 0.5T) = (0, 10)
6660 12:18:21.295381 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6661 12:18:21.298879 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6662 12:18:21.302715 best DQS0 dly(2T, 0.5T) = (0, 10)
6663 12:18:21.305761 best DQS1 dly(2T, 0.5T) = (0, 10)
6664 12:18:21.309334 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6665 12:18:21.311989 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6666 12:18:21.315494 Pre-setting of DQS Precalculation
6667 12:18:21.318825 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6668 12:18:21.319451 ==
6669 12:18:21.322337 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 12:18:21.329013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 12:18:21.329436 ==
6672 12:18:21.332460 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 12:18:21.339090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6674 12:18:21.341947 [CA 0] Center 36 (8~64) winsize 57
6675 12:18:21.345575 [CA 1] Center 36 (8~64) winsize 57
6676 12:18:21.348965 [CA 2] Center 36 (8~64) winsize 57
6677 12:18:21.352412 [CA 3] Center 36 (8~64) winsize 57
6678 12:18:21.355379 [CA 4] Center 36 (8~64) winsize 57
6679 12:18:21.359278 [CA 5] Center 36 (8~64) winsize 57
6680 12:18:21.359695
6681 12:18:21.362150 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6682 12:18:21.362564
6683 12:18:21.365647 [CATrainingPosCal] consider 1 rank data
6684 12:18:21.369299 u2DelayCellTimex100 = 270/100 ps
6685 12:18:21.372730 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 12:18:21.375915 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 12:18:21.379151 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 12:18:21.382710 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 12:18:21.385480 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 12:18:21.389330 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 12:18:21.389827
6692 12:18:21.395564 CA PerBit enable=1, Macro0, CA PI delay=36
6693 12:18:21.395984
6694 12:18:21.396320 [CBTSetCACLKResult] CA Dly = 36
6695 12:18:21.399181 CS Dly: 1 (0~32)
6696 12:18:21.399596 ==
6697 12:18:21.402239 Dram Type= 6, Freq= 0, CH_1, rank 1
6698 12:18:21.405618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 12:18:21.406038 ==
6700 12:18:21.412231 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6701 12:18:21.419001 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6702 12:18:21.422097 [CA 0] Center 36 (8~64) winsize 57
6703 12:18:21.425710 [CA 1] Center 36 (8~64) winsize 57
6704 12:18:21.429320 [CA 2] Center 36 (8~64) winsize 57
6705 12:18:21.429741 [CA 3] Center 36 (8~64) winsize 57
6706 12:18:21.432195 [CA 4] Center 36 (8~64) winsize 57
6707 12:18:21.435414 [CA 5] Center 36 (8~64) winsize 57
6708 12:18:21.435948
6709 12:18:21.442032 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6710 12:18:21.442454
6711 12:18:21.445537 [CATrainingPosCal] consider 2 rank data
6712 12:18:21.448746 u2DelayCellTimex100 = 270/100 ps
6713 12:18:21.452009 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 12:18:21.455527 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 12:18:21.458997 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 12:18:21.462272 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 12:18:21.465514 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 12:18:21.468874 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 12:18:21.469311
6720 12:18:21.472137 CA PerBit enable=1, Macro0, CA PI delay=36
6721 12:18:21.472576
6722 12:18:21.475849 [CBTSetCACLKResult] CA Dly = 36
6723 12:18:21.478859 CS Dly: 1 (0~32)
6724 12:18:21.479300
6725 12:18:21.482167 ----->DramcWriteLeveling(PI) begin...
6726 12:18:21.482649 ==
6727 12:18:21.485511 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 12:18:21.488971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 12:18:21.489411 ==
6730 12:18:21.492086 Write leveling (Byte 0): 40 => 8
6731 12:18:21.495326 Write leveling (Byte 1): 40 => 8
6732 12:18:21.498694 DramcWriteLeveling(PI) end<-----
6733 12:18:21.499155
6734 12:18:21.499617 ==
6735 12:18:21.502118 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 12:18:21.505656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 12:18:21.506077 ==
6738 12:18:21.508750 [Gating] SW mode calibration
6739 12:18:21.515651 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6740 12:18:21.522542 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6741 12:18:21.525591 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6742 12:18:21.529033 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6743 12:18:21.535587 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 12:18:21.538678 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 12:18:21.542317 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 12:18:21.545999 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 12:18:21.552529 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 12:18:21.555960 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 12:18:21.559127 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6750 12:18:21.562648 Total UI for P1: 0, mck2ui 16
6751 12:18:21.565975 best dqsien dly found for B0: ( 0, 14, 24)
6752 12:18:21.569143 Total UI for P1: 0, mck2ui 16
6753 12:18:21.572682 best dqsien dly found for B1: ( 0, 14, 24)
6754 12:18:21.575487 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6755 12:18:21.579093 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6756 12:18:21.582542
6757 12:18:21.585804 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6758 12:18:21.589147 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6759 12:18:21.592386 [Gating] SW calibration Done
6760 12:18:21.592814 ==
6761 12:18:21.595649 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 12:18:21.599002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 12:18:21.599426 ==
6764 12:18:21.599785 RX Vref Scan: 0
6765 12:18:21.600103
6766 12:18:21.602071 RX Vref 0 -> 0, step: 1
6767 12:18:21.602510
6768 12:18:21.605401 RX Delay -410 -> 252, step: 16
6769 12:18:21.608879 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6770 12:18:21.615862 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6771 12:18:21.618979 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6772 12:18:21.622420 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6773 12:18:21.625742 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6774 12:18:21.629323 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6775 12:18:21.635847 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6776 12:18:21.639620 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6777 12:18:21.643018 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6778 12:18:21.646379 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6779 12:18:21.652290 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6780 12:18:21.656078 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6781 12:18:21.659130 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6782 12:18:21.662532 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6783 12:18:21.669093 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6784 12:18:21.672563 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6785 12:18:21.672993 ==
6786 12:18:21.675856 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 12:18:21.679102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 12:18:21.679548 ==
6789 12:18:21.682331 DQS Delay:
6790 12:18:21.682808 DQS0 = 51, DQS1 = 59
6791 12:18:21.685754 DQM Delay:
6792 12:18:21.686168 DQM0 = 19, DQM1 = 17
6793 12:18:21.686526 DQ Delay:
6794 12:18:21.688795 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6795 12:18:21.692544 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6796 12:18:21.695658 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6797 12:18:21.699118 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6798 12:18:21.699562
6799 12:18:21.699900
6800 12:18:21.700231 ==
6801 12:18:21.702459 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 12:18:21.709506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 12:18:21.709949 ==
6804 12:18:21.710284
6805 12:18:21.710700
6806 12:18:21.711082 TX Vref Scan disable
6807 12:18:21.712519 == TX Byte 0 ==
6808 12:18:21.716233 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 12:18:21.719286 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 12:18:21.722605 == TX Byte 1 ==
6811 12:18:21.726059 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 12:18:21.729742 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 12:18:21.730439 ==
6814 12:18:21.732407 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 12:18:21.739179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 12:18:21.739734 ==
6817 12:18:21.740229
6818 12:18:21.740596
6819 12:18:21.740900 TX Vref Scan disable
6820 12:18:21.742766 == TX Byte 0 ==
6821 12:18:21.746229 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 12:18:21.749319 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 12:18:21.752854 == TX Byte 1 ==
6824 12:18:21.755910 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6825 12:18:21.759045 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6826 12:18:21.759460
6827 12:18:21.762505 [DATLAT]
6828 12:18:21.762983 Freq=400, CH1 RK0
6829 12:18:21.763318
6830 12:18:21.766204 DATLAT Default: 0xf
6831 12:18:21.766616 0, 0xFFFF, sum = 0
6832 12:18:21.769802 1, 0xFFFF, sum = 0
6833 12:18:21.770264 2, 0xFFFF, sum = 0
6834 12:18:21.772595 3, 0xFFFF, sum = 0
6835 12:18:21.773012 4, 0xFFFF, sum = 0
6836 12:18:21.775668 5, 0xFFFF, sum = 0
6837 12:18:21.776090 6, 0xFFFF, sum = 0
6838 12:18:21.779290 7, 0xFFFF, sum = 0
6839 12:18:21.779713 8, 0xFFFF, sum = 0
6840 12:18:21.782715 9, 0xFFFF, sum = 0
6841 12:18:21.785729 10, 0xFFFF, sum = 0
6842 12:18:21.786168 11, 0xFFFF, sum = 0
6843 12:18:21.789387 12, 0xFFFF, sum = 0
6844 12:18:21.789809 13, 0x0, sum = 1
6845 12:18:21.792909 14, 0x0, sum = 2
6846 12:18:21.793349 15, 0x0, sum = 3
6847 12:18:21.793754 16, 0x0, sum = 4
6848 12:18:21.795939 best_step = 14
6849 12:18:21.796352
6850 12:18:21.796673 ==
6851 12:18:21.799177 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 12:18:21.802314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 12:18:21.802778 ==
6854 12:18:21.806156 RX Vref Scan: 1
6855 12:18:21.806569
6856 12:18:21.806959 RX Vref 0 -> 0, step: 1
6857 12:18:21.809386
6858 12:18:21.809813 RX Delay -359 -> 252, step: 8
6859 12:18:21.810159
6860 12:18:21.812486 Set Vref, RX VrefLevel [Byte0]: 57
6861 12:18:21.815985 [Byte1]: 52
6862 12:18:21.820894
6863 12:18:21.821306 Final RX Vref Byte 0 = 57 to rank0
6864 12:18:21.824337 Final RX Vref Byte 1 = 52 to rank0
6865 12:18:21.827858 Final RX Vref Byte 0 = 57 to rank1
6866 12:18:21.831200 Final RX Vref Byte 1 = 52 to rank1==
6867 12:18:21.834083 Dram Type= 6, Freq= 0, CH_1, rank 0
6868 12:18:21.840755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 12:18:21.841481 ==
6870 12:18:21.842041 DQS Delay:
6871 12:18:21.844300 DQS0 = 48, DQS1 = 60
6872 12:18:21.844852 DQM Delay:
6873 12:18:21.845367 DQM0 = 12, DQM1 = 13
6874 12:18:21.848054 DQ Delay:
6875 12:18:21.851201 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6876 12:18:21.851767 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6877 12:18:21.854167 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6878 12:18:21.857717 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6879 12:18:21.858163
6880 12:18:21.860663
6881 12:18:21.867720 [DQSOSCAuto] RK0, (LSB)MR18= 0x9138, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6882 12:18:21.871391 CH1 RK0: MR19=C0C, MR18=9138
6883 12:18:21.877705 CH1_RK0: MR19=0xC0C, MR18=0x9138, DQSOSC=391, MR23=63, INC=386, DEC=257
6884 12:18:21.878131 ==
6885 12:18:21.881328 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 12:18:21.884513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 12:18:21.884947 ==
6888 12:18:21.887925 [Gating] SW mode calibration
6889 12:18:21.894686 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6890 12:18:21.897686 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6891 12:18:21.904374 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6892 12:18:21.907689 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6893 12:18:21.911147 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 12:18:21.918193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 12:18:21.920886 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 12:18:21.924478 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 12:18:21.931296 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 12:18:21.934311 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 12:18:21.937571 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6900 12:18:21.941360 Total UI for P1: 0, mck2ui 16
6901 12:18:21.944462 best dqsien dly found for B0: ( 0, 14, 24)
6902 12:18:21.947491 Total UI for P1: 0, mck2ui 16
6903 12:18:21.950965 best dqsien dly found for B1: ( 0, 14, 24)
6904 12:18:21.954574 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6905 12:18:21.957408 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6906 12:18:21.957509
6907 12:18:21.960905 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6908 12:18:21.967619 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6909 12:18:21.967752 [Gating] SW calibration Done
6910 12:18:21.967865 ==
6911 12:18:21.971245 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 12:18:21.977650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 12:18:21.977731 ==
6914 12:18:21.977794 RX Vref Scan: 0
6915 12:18:21.977854
6916 12:18:21.980699 RX Vref 0 -> 0, step: 1
6917 12:18:21.980779
6918 12:18:21.984205 RX Delay -410 -> 252, step: 16
6919 12:18:21.987849 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6920 12:18:21.990744 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6921 12:18:21.997651 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6922 12:18:22.001253 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6923 12:18:22.004211 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6924 12:18:22.007933 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6925 12:18:22.014260 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6926 12:18:22.017641 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6927 12:18:22.021046 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6928 12:18:22.024152 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6929 12:18:22.030911 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6930 12:18:22.034302 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6931 12:18:22.037721 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6932 12:18:22.040690 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6933 12:18:22.047607 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6934 12:18:22.051188 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6935 12:18:22.051350 ==
6936 12:18:22.054464 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 12:18:22.058221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 12:18:22.058459 ==
6939 12:18:22.060756 DQS Delay:
6940 12:18:22.060991 DQS0 = 43, DQS1 = 51
6941 12:18:22.061274 DQM Delay:
6942 12:18:22.064344 DQM0 = 9, DQM1 = 13
6943 12:18:22.064637 DQ Delay:
6944 12:18:22.068136 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6945 12:18:22.071532 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6946 12:18:22.074790 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6947 12:18:22.078073 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6948 12:18:22.078484
6949 12:18:22.078887
6950 12:18:22.079206 ==
6951 12:18:22.081691 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 12:18:22.084688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 12:18:22.085107 ==
6954 12:18:22.085433
6955 12:18:22.088519
6956 12:18:22.088930 TX Vref Scan disable
6957 12:18:22.091546 == TX Byte 0 ==
6958 12:18:22.095133 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6959 12:18:22.098084 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6960 12:18:22.101771 == TX Byte 1 ==
6961 12:18:22.104557 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6962 12:18:22.108026 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6963 12:18:22.108478 ==
6964 12:18:22.111891 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 12:18:22.114857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 12:18:22.115328 ==
6967 12:18:22.115660
6968 12:18:22.115985
6969 12:18:22.118200 TX Vref Scan disable
6970 12:18:22.121511 == TX Byte 0 ==
6971 12:18:22.125195 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6972 12:18:22.127989 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6973 12:18:22.128406 == TX Byte 1 ==
6974 12:18:22.135151 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6975 12:18:22.138700 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6976 12:18:22.139164
6977 12:18:22.139526 [DATLAT]
6978 12:18:22.141730 Freq=400, CH1 RK1
6979 12:18:22.142158
6980 12:18:22.142484 DATLAT Default: 0xe
6981 12:18:22.145212 0, 0xFFFF, sum = 0
6982 12:18:22.145652 1, 0xFFFF, sum = 0
6983 12:18:22.148546 2, 0xFFFF, sum = 0
6984 12:18:22.148967 3, 0xFFFF, sum = 0
6985 12:18:22.151953 4, 0xFFFF, sum = 0
6986 12:18:22.152375 5, 0xFFFF, sum = 0
6987 12:18:22.155110 6, 0xFFFF, sum = 0
6988 12:18:22.155528 7, 0xFFFF, sum = 0
6989 12:18:22.158532 8, 0xFFFF, sum = 0
6990 12:18:22.159034 9, 0xFFFF, sum = 0
6991 12:18:22.161618 10, 0xFFFF, sum = 0
6992 12:18:22.164914 11, 0xFFFF, sum = 0
6993 12:18:22.165356 12, 0xFFFF, sum = 0
6994 12:18:22.168338 13, 0x0, sum = 1
6995 12:18:22.168759 14, 0x0, sum = 2
6996 12:18:22.169093 15, 0x0, sum = 3
6997 12:18:22.172091 16, 0x0, sum = 4
6998 12:18:22.172507 best_step = 14
6999 12:18:22.172831
7000 12:18:22.175461 ==
7001 12:18:22.175873 Dram Type= 6, Freq= 0, CH_1, rank 1
7002 12:18:22.181903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7003 12:18:22.182318 ==
7004 12:18:22.182648 RX Vref Scan: 0
7005 12:18:22.183005
7006 12:18:22.184948 RX Vref 0 -> 0, step: 1
7007 12:18:22.185387
7008 12:18:22.188334 RX Delay -343 -> 252, step: 8
7009 12:18:22.195398 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7010 12:18:22.198388 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7011 12:18:22.201569 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7012 12:18:22.205107 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
7013 12:18:22.212192 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7014 12:18:22.215041 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7015 12:18:22.218574 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7016 12:18:22.221636 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7017 12:18:22.228280 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7018 12:18:22.231653 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7019 12:18:22.235628 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
7020 12:18:22.238765 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7021 12:18:22.245437 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7022 12:18:22.248534 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7023 12:18:22.252239 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7024 12:18:22.255247 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7025 12:18:22.258857 ==
7026 12:18:22.261903 Dram Type= 6, Freq= 0, CH_1, rank 1
7027 12:18:22.265384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7028 12:18:22.265805 ==
7029 12:18:22.266133 DQS Delay:
7030 12:18:22.268317 DQS0 = 52, DQS1 = 56
7031 12:18:22.268733 DQM Delay:
7032 12:18:22.271779 DQM0 = 13, DQM1 = 9
7033 12:18:22.272195 DQ Delay:
7034 12:18:22.275315 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7035 12:18:22.278669 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7036 12:18:22.282074 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7037 12:18:22.285346 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
7038 12:18:22.285895
7039 12:18:22.286413
7040 12:18:22.291945 [DQSOSCAuto] RK1, (LSB)MR18= 0x7e93, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
7041 12:18:22.295555 CH1 RK1: MR19=C0C, MR18=7E93
7042 12:18:22.302207 CH1_RK1: MR19=0xC0C, MR18=0x7E93, DQSOSC=391, MR23=63, INC=386, DEC=257
7043 12:18:22.305582 [RxdqsGatingPostProcess] freq 400
7044 12:18:22.308612 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7045 12:18:22.311664 best DQS0 dly(2T, 0.5T) = (0, 10)
7046 12:18:22.315125 best DQS1 dly(2T, 0.5T) = (0, 10)
7047 12:18:22.318562 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7048 12:18:22.322100 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7049 12:18:22.325398 best DQS0 dly(2T, 0.5T) = (0, 10)
7050 12:18:22.328860 best DQS1 dly(2T, 0.5T) = (0, 10)
7051 12:18:22.332173 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7052 12:18:22.335390 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7053 12:18:22.338542 Pre-setting of DQS Precalculation
7054 12:18:22.341665 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7055 12:18:22.351781 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7056 12:18:22.358465 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7057 12:18:22.359005
7058 12:18:22.359372
7059 12:18:22.361918 [Calibration Summary] 800 Mbps
7060 12:18:22.362362 CH 0, Rank 0
7061 12:18:22.365662 SW Impedance : PASS
7062 12:18:22.366082 DUTY Scan : NO K
7063 12:18:22.368386 ZQ Calibration : PASS
7064 12:18:22.371869 Jitter Meter : NO K
7065 12:18:22.372286 CBT Training : PASS
7066 12:18:22.375369 Write leveling : PASS
7067 12:18:22.375791 RX DQS gating : PASS
7068 12:18:22.378400 RX DQ/DQS(RDDQC) : PASS
7069 12:18:22.381899 TX DQ/DQS : PASS
7070 12:18:22.382318 RX DATLAT : PASS
7071 12:18:22.384952 RX DQ/DQS(Engine): PASS
7072 12:18:22.388367 TX OE : NO K
7073 12:18:22.388807 All Pass.
7074 12:18:22.389140
7075 12:18:22.389484 CH 0, Rank 1
7076 12:18:22.392170 SW Impedance : PASS
7077 12:18:22.395293 DUTY Scan : NO K
7078 12:18:22.395811 ZQ Calibration : PASS
7079 12:18:22.398433 Jitter Meter : NO K
7080 12:18:22.401616 CBT Training : PASS
7081 12:18:22.402034 Write leveling : NO K
7082 12:18:22.405151 RX DQS gating : PASS
7083 12:18:22.408757 RX DQ/DQS(RDDQC) : PASS
7084 12:18:22.409243 TX DQ/DQS : PASS
7085 12:18:22.411831 RX DATLAT : PASS
7086 12:18:22.415068 RX DQ/DQS(Engine): PASS
7087 12:18:22.415160 TX OE : NO K
7088 12:18:22.415233 All Pass.
7089 12:18:22.418031
7090 12:18:22.418111 CH 1, Rank 0
7091 12:18:22.421815 SW Impedance : PASS
7092 12:18:22.421896 DUTY Scan : NO K
7093 12:18:22.424372 ZQ Calibration : PASS
7094 12:18:22.424453 Jitter Meter : NO K
7095 12:18:22.427971 CBT Training : PASS
7096 12:18:22.431514 Write leveling : PASS
7097 12:18:22.431595 RX DQS gating : PASS
7098 12:18:22.435153 RX DQ/DQS(RDDQC) : PASS
7099 12:18:22.437861 TX DQ/DQS : PASS
7100 12:18:22.437941 RX DATLAT : PASS
7101 12:18:22.441347 RX DQ/DQS(Engine): PASS
7102 12:18:22.444776 TX OE : NO K
7103 12:18:22.444857 All Pass.
7104 12:18:22.444922
7105 12:18:22.444981 CH 1, Rank 1
7106 12:18:22.448272 SW Impedance : PASS
7107 12:18:22.451038 DUTY Scan : NO K
7108 12:18:22.451120 ZQ Calibration : PASS
7109 12:18:22.454597 Jitter Meter : NO K
7110 12:18:22.458233 CBT Training : PASS
7111 12:18:22.458313 Write leveling : NO K
7112 12:18:22.461070 RX DQS gating : PASS
7113 12:18:22.464869 RX DQ/DQS(RDDQC) : PASS
7114 12:18:22.464950 TX DQ/DQS : PASS
7115 12:18:22.467682 RX DATLAT : PASS
7116 12:18:22.467763 RX DQ/DQS(Engine): PASS
7117 12:18:22.471351 TX OE : NO K
7118 12:18:22.471432 All Pass.
7119 12:18:22.471496
7120 12:18:22.474834 DramC Write-DBI off
7121 12:18:22.478146 PER_BANK_REFRESH: Hybrid Mode
7122 12:18:22.478227 TX_TRACKING: ON
7123 12:18:22.487992 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7124 12:18:22.490974 [FAST_K] Save calibration result to emmc
7125 12:18:22.494339 dramc_set_vcore_voltage set vcore to 725000
7126 12:18:22.497476 Read voltage for 1600, 0
7127 12:18:22.497556 Vio18 = 0
7128 12:18:22.501097 Vcore = 725000
7129 12:18:22.501183 Vdram = 0
7130 12:18:22.501251 Vddq = 0
7131 12:18:22.501313 Vmddr = 0
7132 12:18:22.507607 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7133 12:18:22.514686 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7134 12:18:22.514815 MEM_TYPE=3, freq_sel=13
7135 12:18:22.517526 sv_algorithm_assistance_LP4_3733
7136 12:18:22.521209 ============ PULL DRAM RESETB DOWN ============
7137 12:18:22.527876 ========== PULL DRAM RESETB DOWN end =========
7138 12:18:22.531296 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7139 12:18:22.534314 ===================================
7140 12:18:22.537815 LPDDR4 DRAM CONFIGURATION
7141 12:18:22.541441 ===================================
7142 12:18:22.541529 EX_ROW_EN[0] = 0x0
7143 12:18:22.544907 EX_ROW_EN[1] = 0x0
7144 12:18:22.544988 LP4Y_EN = 0x0
7145 12:18:22.548115 WORK_FSP = 0x1
7146 12:18:22.548196 WL = 0x5
7147 12:18:22.551372 RL = 0x5
7148 12:18:22.551453 BL = 0x2
7149 12:18:22.554667 RPST = 0x0
7150 12:18:22.554809 RD_PRE = 0x0
7151 12:18:22.557589 WR_PRE = 0x1
7152 12:18:22.557670 WR_PST = 0x1
7153 12:18:22.560689 DBI_WR = 0x0
7154 12:18:22.564711 DBI_RD = 0x0
7155 12:18:22.564793 OTF = 0x1
7156 12:18:22.567990 ===================================
7157 12:18:22.571317 ===================================
7158 12:18:22.571398 ANA top config
7159 12:18:22.574613 ===================================
7160 12:18:22.578252 DLL_ASYNC_EN = 0
7161 12:18:22.581155 ALL_SLAVE_EN = 0
7162 12:18:22.584587 NEW_RANK_MODE = 1
7163 12:18:22.584699 DLL_IDLE_MODE = 1
7164 12:18:22.587995 LP45_APHY_COMB_EN = 1
7165 12:18:22.591286 TX_ODT_DIS = 0
7166 12:18:22.594761 NEW_8X_MODE = 1
7167 12:18:22.598144 ===================================
7168 12:18:22.601176 ===================================
7169 12:18:22.604696 data_rate = 3200
7170 12:18:22.604919 CKR = 1
7171 12:18:22.608202 DQ_P2S_RATIO = 8
7172 12:18:22.611814 ===================================
7173 12:18:22.615060 CA_P2S_RATIO = 8
7174 12:18:22.618478 DQ_CA_OPEN = 0
7175 12:18:22.621555 DQ_SEMI_OPEN = 0
7176 12:18:22.625038 CA_SEMI_OPEN = 0
7177 12:18:22.625341 CA_FULL_RATE = 0
7178 12:18:22.628492 DQ_CKDIV4_EN = 0
7179 12:18:22.632131 CA_CKDIV4_EN = 0
7180 12:18:22.635050 CA_PREDIV_EN = 0
7181 12:18:22.638189 PH8_DLY = 12
7182 12:18:22.641896 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7183 12:18:22.642313 DQ_AAMCK_DIV = 4
7184 12:18:22.645453 CA_AAMCK_DIV = 4
7185 12:18:22.648761 CA_ADMCK_DIV = 4
7186 12:18:22.651754 DQ_TRACK_CA_EN = 0
7187 12:18:22.655785 CA_PICK = 1600
7188 12:18:22.658460 CA_MCKIO = 1600
7189 12:18:22.658987 MCKIO_SEMI = 0
7190 12:18:22.662078 PLL_FREQ = 3068
7191 12:18:22.665551 DQ_UI_PI_RATIO = 32
7192 12:18:22.668853 CA_UI_PI_RATIO = 0
7193 12:18:22.671640 ===================================
7194 12:18:22.675290 ===================================
7195 12:18:22.678537 memory_type:LPDDR4
7196 12:18:22.679145 GP_NUM : 10
7197 12:18:22.681695 SRAM_EN : 1
7198 12:18:22.685020 MD32_EN : 0
7199 12:18:22.688472 ===================================
7200 12:18:22.688892 [ANA_INIT] >>>>>>>>>>>>>>
7201 12:18:22.691998 <<<<<< [CONFIGURE PHASE]: ANA_TX
7202 12:18:22.695021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7203 12:18:22.698472 ===================================
7204 12:18:22.701869 data_rate = 3200,PCW = 0X7600
7205 12:18:22.704916 ===================================
7206 12:18:22.708597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7207 12:18:22.715541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7208 12:18:22.718759 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7209 12:18:22.725360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7210 12:18:22.728701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7211 12:18:22.731980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7212 12:18:22.732403 [ANA_INIT] flow start
7213 12:18:22.735274 [ANA_INIT] PLL >>>>>>>>
7214 12:18:22.738767 [ANA_INIT] PLL <<<<<<<<
7215 12:18:22.739189 [ANA_INIT] MIDPI >>>>>>>>
7216 12:18:22.742241 [ANA_INIT] MIDPI <<<<<<<<
7217 12:18:22.745336 [ANA_INIT] DLL >>>>>>>>
7218 12:18:22.745750 [ANA_INIT] DLL <<<<<<<<
7219 12:18:22.748974 [ANA_INIT] flow end
7220 12:18:22.752043 ============ LP4 DIFF to SE enter ============
7221 12:18:22.755610 ============ LP4 DIFF to SE exit ============
7222 12:18:22.759261 [ANA_INIT] <<<<<<<<<<<<<
7223 12:18:22.762567 [Flow] Enable top DCM control >>>>>
7224 12:18:22.765733 [Flow] Enable top DCM control <<<<<
7225 12:18:22.769225 Enable DLL master slave shuffle
7226 12:18:22.775702 ==============================================================
7227 12:18:22.776148 Gating Mode config
7228 12:18:22.782211 ==============================================================
7229 12:18:22.782652 Config description:
7230 12:18:22.792351 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7231 12:18:22.799191 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7232 12:18:22.805621 SELPH_MODE 0: By rank 1: By Phase
7233 12:18:22.809157 ==============================================================
7234 12:18:22.812501 GAT_TRACK_EN = 1
7235 12:18:22.815647 RX_GATING_MODE = 2
7236 12:18:22.819133 RX_GATING_TRACK_MODE = 2
7237 12:18:22.822795 SELPH_MODE = 1
7238 12:18:22.825807 PICG_EARLY_EN = 1
7239 12:18:22.829234 VALID_LAT_VALUE = 1
7240 12:18:22.832667 ==============================================================
7241 12:18:22.836038 Enter into Gating configuration >>>>
7242 12:18:22.839484 Exit from Gating configuration <<<<
7243 12:18:22.842629 Enter into DVFS_PRE_config >>>>>
7244 12:18:22.855682 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7245 12:18:22.859199 Exit from DVFS_PRE_config <<<<<
7246 12:18:22.859620 Enter into PICG configuration >>>>
7247 12:18:22.862801 Exit from PICG configuration <<<<
7248 12:18:22.865798 [RX_INPUT] configuration >>>>>
7249 12:18:22.869256 [RX_INPUT] configuration <<<<<
7250 12:18:22.875613 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7251 12:18:22.879108 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7252 12:18:22.885561 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7253 12:18:22.892502 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7254 12:18:22.899306 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7255 12:18:22.905900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7256 12:18:22.908890 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7257 12:18:22.912488 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7258 12:18:22.915983 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7259 12:18:22.922347 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7260 12:18:22.925707 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7261 12:18:22.929190 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 12:18:22.932507 ===================================
7263 12:18:22.935904 LPDDR4 DRAM CONFIGURATION
7264 12:18:22.939082 ===================================
7265 12:18:22.939639 EX_ROW_EN[0] = 0x0
7266 12:18:22.942624 EX_ROW_EN[1] = 0x0
7267 12:18:22.945966 LP4Y_EN = 0x0
7268 12:18:22.946387 WORK_FSP = 0x1
7269 12:18:22.949222 WL = 0x5
7270 12:18:22.949879 RL = 0x5
7271 12:18:22.952439 BL = 0x2
7272 12:18:22.952937 RPST = 0x0
7273 12:18:22.956106 RD_PRE = 0x0
7274 12:18:22.956550 WR_PRE = 0x1
7275 12:18:22.959752 WR_PST = 0x1
7276 12:18:22.960191 DBI_WR = 0x0
7277 12:18:22.962694 DBI_RD = 0x0
7278 12:18:22.963148 OTF = 0x1
7279 12:18:22.965680 ===================================
7280 12:18:22.969184 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7281 12:18:22.975673 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7282 12:18:22.979005 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7283 12:18:22.982565 ===================================
7284 12:18:22.985783 LPDDR4 DRAM CONFIGURATION
7285 12:18:22.989010 ===================================
7286 12:18:22.989450 EX_ROW_EN[0] = 0x10
7287 12:18:22.992433 EX_ROW_EN[1] = 0x0
7288 12:18:22.992862 LP4Y_EN = 0x0
7289 12:18:22.996008 WORK_FSP = 0x1
7290 12:18:22.996429 WL = 0x5
7291 12:18:22.999049 RL = 0x5
7292 12:18:22.999508 BL = 0x2
7293 12:18:23.002546 RPST = 0x0
7294 12:18:23.003032 RD_PRE = 0x0
7295 12:18:23.006237 WR_PRE = 0x1
7296 12:18:23.009502 WR_PST = 0x1
7297 12:18:23.009974 DBI_WR = 0x0
7298 12:18:23.012672 DBI_RD = 0x0
7299 12:18:23.013103 OTF = 0x1
7300 12:18:23.015955 ===================================
7301 12:18:23.022403 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7302 12:18:23.022990 ==
7303 12:18:23.025852 Dram Type= 6, Freq= 0, CH_0, rank 0
7304 12:18:23.028785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 12:18:23.028870 ==
7306 12:18:23.032575 [Duty_Offset_Calibration]
7307 12:18:23.032659 B0:2 B1:-1 CA:1
7308 12:18:23.035901
7309 12:18:23.038574 [DutyScan_Calibration_Flow] k_type=0
7310 12:18:23.046025
7311 12:18:23.046128 ==CLK 0==
7312 12:18:23.049796 Final CLK duty delay cell = -4
7313 12:18:23.052855 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7314 12:18:23.056389 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7315 12:18:23.059780 [-4] AVG Duty = 4937%(X100)
7316 12:18:23.059892
7317 12:18:23.063279 CH0 CLK Duty spec in!! Max-Min= 187%
7318 12:18:23.066300 [DutyScan_Calibration_Flow] ====Done====
7319 12:18:23.066395
7320 12:18:23.069897 [DutyScan_Calibration_Flow] k_type=1
7321 12:18:23.085901
7322 12:18:23.085999 ==DQS 0 ==
7323 12:18:23.089164 Final DQS duty delay cell = 0
7324 12:18:23.092526 [0] MAX Duty = 5125%(X100), DQS PI = 20
7325 12:18:23.095885 [0] MIN Duty = 5000%(X100), DQS PI = 14
7326 12:18:23.095976 [0] AVG Duty = 5062%(X100)
7327 12:18:23.099541
7328 12:18:23.099621 ==DQS 1 ==
7329 12:18:23.102572 Final DQS duty delay cell = -4
7330 12:18:23.105686 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7331 12:18:23.109409 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7332 12:18:23.112871 [-4] AVG Duty = 5046%(X100)
7333 12:18:23.112951
7334 12:18:23.115764 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7335 12:18:23.115845
7336 12:18:23.119009 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7337 12:18:23.122309 [DutyScan_Calibration_Flow] ====Done====
7338 12:18:23.122390
7339 12:18:23.125749 [DutyScan_Calibration_Flow] k_type=3
7340 12:18:23.143256
7341 12:18:23.143335 ==DQM 0 ==
7342 12:18:23.146078 Final DQM duty delay cell = 0
7343 12:18:23.149531 [0] MAX Duty = 5000%(X100), DQS PI = 18
7344 12:18:23.153281 [0] MIN Duty = 4875%(X100), DQS PI = 6
7345 12:18:23.153351 [0] AVG Duty = 4937%(X100)
7346 12:18:23.156525
7347 12:18:23.156604 ==DQM 1 ==
7348 12:18:23.159630 Final DQM duty delay cell = 0
7349 12:18:23.162839 [0] MAX Duty = 5187%(X100), DQS PI = 58
7350 12:18:23.166128 [0] MIN Duty = 4969%(X100), DQS PI = 18
7351 12:18:23.166209 [0] AVG Duty = 5078%(X100)
7352 12:18:23.169565
7353 12:18:23.173045 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7354 12:18:23.173119
7355 12:18:23.176725 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7356 12:18:23.179679 [DutyScan_Calibration_Flow] ====Done====
7357 12:18:23.179766
7358 12:18:23.183217 [DutyScan_Calibration_Flow] k_type=2
7359 12:18:23.199387
7360 12:18:23.199517 ==DQ 0 ==
7361 12:18:23.202592 Final DQ duty delay cell = -4
7362 12:18:23.205966 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7363 12:18:23.209129 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7364 12:18:23.212945 [-4] AVG Duty = 4922%(X100)
7365 12:18:23.213026
7366 12:18:23.213089 ==DQ 1 ==
7367 12:18:23.215676 Final DQ duty delay cell = 0
7368 12:18:23.219388 [0] MAX Duty = 5031%(X100), DQS PI = 30
7369 12:18:23.222756 [0] MIN Duty = 4907%(X100), DQS PI = 42
7370 12:18:23.225840 [0] AVG Duty = 4969%(X100)
7371 12:18:23.225919
7372 12:18:23.229366 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7373 12:18:23.229447
7374 12:18:23.232902 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7375 12:18:23.236495 [DutyScan_Calibration_Flow] ====Done====
7376 12:18:23.236575 ==
7377 12:18:23.239250 Dram Type= 6, Freq= 0, CH_1, rank 0
7378 12:18:23.242823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7379 12:18:23.242904 ==
7380 12:18:23.246273 [Duty_Offset_Calibration]
7381 12:18:23.246353 B0:1 B1:1 CA:2
7382 12:18:23.246415
7383 12:18:23.249231 [DutyScan_Calibration_Flow] k_type=0
7384 12:18:23.260137
7385 12:18:23.260217 ==CLK 0==
7386 12:18:23.263443 Final CLK duty delay cell = 0
7387 12:18:23.266444 [0] MAX Duty = 5187%(X100), DQS PI = 24
7388 12:18:23.269757 [0] MIN Duty = 4938%(X100), DQS PI = 48
7389 12:18:23.269850 [0] AVG Duty = 5062%(X100)
7390 12:18:23.273518
7391 12:18:23.276660 CH1 CLK Duty spec in!! Max-Min= 249%
7392 12:18:23.280153 [DutyScan_Calibration_Flow] ====Done====
7393 12:18:23.280262
7394 12:18:23.283316 [DutyScan_Calibration_Flow] k_type=1
7395 12:18:23.299693
7396 12:18:23.299781 ==DQS 0 ==
7397 12:18:23.303048 Final DQS duty delay cell = 0
7398 12:18:23.306749 [0] MAX Duty = 5062%(X100), DQS PI = 20
7399 12:18:23.309748 [0] MIN Duty = 4813%(X100), DQS PI = 52
7400 12:18:23.309882 [0] AVG Duty = 4937%(X100)
7401 12:18:23.312788
7402 12:18:23.312910 ==DQS 1 ==
7403 12:18:23.316184 Final DQS duty delay cell = 0
7404 12:18:23.319373 [0] MAX Duty = 5031%(X100), DQS PI = 36
7405 12:18:23.323357 [0] MIN Duty = 4938%(X100), DQS PI = 14
7406 12:18:23.323440 [0] AVG Duty = 4984%(X100)
7407 12:18:23.326372
7408 12:18:23.329950 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7409 12:18:23.330044
7410 12:18:23.333469 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7411 12:18:23.336394 [DutyScan_Calibration_Flow] ====Done====
7412 12:18:23.336565
7413 12:18:23.339675 [DutyScan_Calibration_Flow] k_type=3
7414 12:18:23.357117
7415 12:18:23.357361 ==DQM 0 ==
7416 12:18:23.360135 Final DQM duty delay cell = 0
7417 12:18:23.363493 [0] MAX Duty = 5187%(X100), DQS PI = 20
7418 12:18:23.366518 [0] MIN Duty = 4844%(X100), DQS PI = 50
7419 12:18:23.366752 [0] AVG Duty = 5015%(X100)
7420 12:18:23.370129
7421 12:18:23.370436 ==DQM 1 ==
7422 12:18:23.373339 Final DQM duty delay cell = 0
7423 12:18:23.377315 [0] MAX Duty = 5125%(X100), DQS PI = 8
7424 12:18:23.380460 [0] MIN Duty = 4907%(X100), DQS PI = 20
7425 12:18:23.380910 [0] AVG Duty = 5016%(X100)
7426 12:18:23.383840
7427 12:18:23.386882 CH1 DQM 0 Duty spec in!! Max-Min= 343%
7428 12:18:23.387306
7429 12:18:23.389922 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7430 12:18:23.393512 [DutyScan_Calibration_Flow] ====Done====
7431 12:18:23.393986
7432 12:18:23.396711 [DutyScan_Calibration_Flow] k_type=2
7433 12:18:23.414142
7434 12:18:23.414564 ==DQ 0 ==
7435 12:18:23.416861 Final DQ duty delay cell = 0
7436 12:18:23.420380 [0] MAX Duty = 5187%(X100), DQS PI = 20
7437 12:18:23.424181 [0] MIN Duty = 4907%(X100), DQS PI = 52
7438 12:18:23.424752 [0] AVG Duty = 5047%(X100)
7439 12:18:23.425131
7440 12:18:23.427409 ==DQ 1 ==
7441 12:18:23.430362 Final DQ duty delay cell = 0
7442 12:18:23.433637 [0] MAX Duty = 5093%(X100), DQS PI = 8
7443 12:18:23.437179 [0] MIN Duty = 5031%(X100), DQS PI = 0
7444 12:18:23.437731 [0] AVG Duty = 5062%(X100)
7445 12:18:23.438156
7446 12:18:23.440105 CH1 DQ 0 Duty spec in!! Max-Min= 280%
7447 12:18:23.440646
7448 12:18:23.443842 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7449 12:18:23.447640 [DutyScan_Calibration_Flow] ====Done====
7450 12:18:23.453060 nWR fixed to 30
7451 12:18:23.456075 [ModeRegInit_LP4] CH0 RK0
7452 12:18:23.456553 [ModeRegInit_LP4] CH0 RK1
7453 12:18:23.459321 [ModeRegInit_LP4] CH1 RK0
7454 12:18:23.462402 [ModeRegInit_LP4] CH1 RK1
7455 12:18:23.463028 match AC timing 5
7456 12:18:23.469248 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7457 12:18:23.472642 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7458 12:18:23.476213 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7459 12:18:23.482833 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7460 12:18:23.485644 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7461 12:18:23.486173 [MiockJmeterHQA]
7462 12:18:23.486512
7463 12:18:23.489347 [DramcMiockJmeter] u1RxGatingPI = 0
7464 12:18:23.492641 0 : 4363, 4138
7465 12:18:23.493108 4 : 4363, 4138
7466 12:18:23.496039 8 : 4252, 4027
7467 12:18:23.496467 12 : 4252, 4027
7468 12:18:23.499483 16 : 4253, 4027
7469 12:18:23.499942 20 : 4252, 4027
7470 12:18:23.500318 24 : 4255, 4030
7471 12:18:23.502538 28 : 4253, 4027
7472 12:18:23.503108 32 : 4252, 4027
7473 12:18:23.505671 36 : 4365, 4140
7474 12:18:23.506185 40 : 4252, 4026
7475 12:18:23.509387 44 : 4255, 4029
7476 12:18:23.509921 48 : 4253, 4027
7477 12:18:23.512801 52 : 4361, 4137
7478 12:18:23.513329 56 : 4250, 4027
7479 12:18:23.513758 60 : 4360, 4137
7480 12:18:23.515834 64 : 4250, 4027
7481 12:18:23.516317 68 : 4250, 4027
7482 12:18:23.519091 72 : 4250, 4026
7483 12:18:23.519542 76 : 4252, 4030
7484 12:18:23.522588 80 : 4250, 4027
7485 12:18:23.523139 84 : 4250, 4027
7486 12:18:23.523511 88 : 4363, 4140
7487 12:18:23.526115 92 : 4250, 4026
7488 12:18:23.526626 96 : 4252, 3147
7489 12:18:23.529537 100 : 4249, 0
7490 12:18:23.530000 104 : 4252, 0
7491 12:18:23.530338 108 : 4252, 0
7492 12:18:23.532551 112 : 4249, 0
7493 12:18:23.532978 116 : 4253, 0
7494 12:18:23.535615 120 : 4250, 0
7495 12:18:23.536084 124 : 4361, 0
7496 12:18:23.536451 128 : 4361, 0
7497 12:18:23.539229 132 : 4250, 0
7498 12:18:23.539656 136 : 4360, 0
7499 12:18:23.542306 140 : 4361, 0
7500 12:18:23.542957 144 : 4250, 0
7501 12:18:23.543427 148 : 4250, 0
7502 12:18:23.546175 152 : 4250, 0
7503 12:18:23.546593 156 : 4253, 0
7504 12:18:23.549036 160 : 4252, 0
7505 12:18:23.549449 164 : 4249, 0
7506 12:18:23.549779 168 : 4252, 0
7507 12:18:23.552591 172 : 4360, 0
7508 12:18:23.553010 176 : 4360, 0
7509 12:18:23.553344 180 : 4363, 0
7510 12:18:23.556295 184 : 4250, 0
7511 12:18:23.556827 188 : 4250, 0
7512 12:18:23.559080 192 : 4249, 0
7513 12:18:23.559501 196 : 4252, 0
7514 12:18:23.559835 200 : 4250, 0
7515 12:18:23.562803 204 : 4250, 0
7516 12:18:23.563221 208 : 4253, 0
7517 12:18:23.566238 212 : 4361, 157
7518 12:18:23.566654 216 : 4250, 3804
7519 12:18:23.569242 220 : 4249, 4027
7520 12:18:23.569663 224 : 4250, 4027
7521 12:18:23.569992 228 : 4250, 4027
7522 12:18:23.572461 232 : 4252, 4030
7523 12:18:23.573041 236 : 4250, 4027
7524 12:18:23.576031 240 : 4360, 4137
7525 12:18:23.576603 244 : 4361, 4137
7526 12:18:23.579387 248 : 4250, 4027
7527 12:18:23.579911 252 : 4363, 4140
7528 12:18:23.582005 256 : 4249, 4027
7529 12:18:23.582094 260 : 4250, 4026
7530 12:18:23.585578 264 : 4250, 4027
7531 12:18:23.585668 268 : 4252, 4029
7532 12:18:23.589010 272 : 4250, 4027
7533 12:18:23.589092 276 : 4250, 4026
7534 12:18:23.589157 280 : 4250, 4027
7535 12:18:23.592181 284 : 4252, 4030
7536 12:18:23.592263 288 : 4250, 4027
7537 12:18:23.595646 292 : 4361, 4137
7538 12:18:23.595727 296 : 4361, 4137
7539 12:18:23.599071 300 : 4250, 4027
7540 12:18:23.599168 304 : 4363, 4140
7541 12:18:23.602583 308 : 4249, 4027
7542 12:18:23.602670 312 : 4250, 4026
7543 12:18:23.605501 316 : 4250, 4027
7544 12:18:23.605596 320 : 4252, 4029
7545 12:18:23.608960 324 : 4249, 4027
7546 12:18:23.609033 328 : 4250, 4026
7547 12:18:23.612332 332 : 4250, 2978
7548 12:18:23.612402 336 : 4252, 31
7549 12:18:23.612461
7550 12:18:23.615867 MIOCK jitter meter ch=0
7551 12:18:23.615947
7552 12:18:23.619026 1T = (336-100) = 236 dly cells
7553 12:18:23.622437 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7554 12:18:23.622523 ==
7555 12:18:23.625757 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 12:18:23.632618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 12:18:23.632719 ==
7558 12:18:23.636187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 12:18:23.639545 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 12:18:23.645896 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 12:18:23.652294 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 12:18:23.659854 [CA 0] Center 44 (14~75) winsize 62
7563 12:18:23.663127 [CA 1] Center 44 (14~74) winsize 61
7564 12:18:23.666527 [CA 2] Center 39 (10~68) winsize 59
7565 12:18:23.670136 [CA 3] Center 39 (10~68) winsize 59
7566 12:18:23.673781 [CA 4] Center 37 (7~67) winsize 61
7567 12:18:23.676746 [CA 5] Center 37 (7~67) winsize 61
7568 12:18:23.677165
7569 12:18:23.680480 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 12:18:23.680986
7571 12:18:23.683919 [CATrainingPosCal] consider 1 rank data
7572 12:18:23.686876 u2DelayCellTimex100 = 275/100 ps
7573 12:18:23.690430 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7574 12:18:23.696735 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7575 12:18:23.700351 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7576 12:18:23.703534 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7577 12:18:23.707073 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7578 12:18:23.710103 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7579 12:18:23.710517
7580 12:18:23.713621 CA PerBit enable=1, Macro0, CA PI delay=37
7581 12:18:23.714036
7582 12:18:23.717300 [CBTSetCACLKResult] CA Dly = 37
7583 12:18:23.720662 CS Dly: 10 (0~41)
7584 12:18:23.723368 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 12:18:23.726985 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 12:18:23.727480 ==
7587 12:18:23.730393 Dram Type= 6, Freq= 0, CH_0, rank 1
7588 12:18:23.733506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 12:18:23.733962 ==
7590 12:18:23.740025 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7591 12:18:23.743544 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7592 12:18:23.750265 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7593 12:18:23.753695 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7594 12:18:23.763997 [CA 0] Center 43 (13~74) winsize 62
7595 12:18:23.767557 [CA 1] Center 43 (13~74) winsize 62
7596 12:18:23.770382 [CA 2] Center 39 (10~69) winsize 60
7597 12:18:23.773825 [CA 3] Center 38 (9~68) winsize 60
7598 12:18:23.777219 [CA 4] Center 37 (7~67) winsize 61
7599 12:18:23.781152 [CA 5] Center 37 (7~67) winsize 61
7600 12:18:23.781571
7601 12:18:23.783932 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7602 12:18:23.784351
7603 12:18:23.787512 [CATrainingPosCal] consider 2 rank data
7604 12:18:23.790624 u2DelayCellTimex100 = 275/100 ps
7605 12:18:23.794101 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7606 12:18:23.800765 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7607 12:18:23.804086 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7608 12:18:23.807657 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7609 12:18:23.811026 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7610 12:18:23.814572 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7611 12:18:23.815061
7612 12:18:23.817322 CA PerBit enable=1, Macro0, CA PI delay=37
7613 12:18:23.817735
7614 12:18:23.820941 [CBTSetCACLKResult] CA Dly = 37
7615 12:18:23.823863 CS Dly: 11 (0~44)
7616 12:18:23.827015 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7617 12:18:23.830296 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7618 12:18:23.830380
7619 12:18:23.833945 ----->DramcWriteLeveling(PI) begin...
7620 12:18:23.834060 ==
7621 12:18:23.837192 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 12:18:23.840533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 12:18:23.844247 ==
7624 12:18:23.844657 Write leveling (Byte 0): 31 => 31
7625 12:18:23.847448 Write leveling (Byte 1): 27 => 27
7626 12:18:23.851038 DramcWriteLeveling(PI) end<-----
7627 12:18:23.851451
7628 12:18:23.851777 ==
7629 12:18:23.854152 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 12:18:23.860934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 12:18:23.861349 ==
7632 12:18:23.861674 [Gating] SW mode calibration
7633 12:18:23.870550 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7634 12:18:23.874377 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7635 12:18:23.877676 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 12:18:23.884118 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 12:18:23.887781 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 12:18:23.890713 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 12:18:23.897452 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7640 12:18:23.900750 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7641 12:18:23.904243 1 4 24 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
7642 12:18:23.911190 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 12:18:23.914566 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 12:18:23.918202 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 12:18:23.924658 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 12:18:23.927802 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 12:18:23.931172 1 5 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7648 12:18:23.934475 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (0 1) (0 0)
7649 12:18:23.941255 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7650 12:18:23.944591 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 12:18:23.947703 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 12:18:23.954708 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 12:18:23.957630 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 12:18:23.961260 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 12:18:23.967901 1 6 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7656 12:18:23.971527 1 6 20 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
7657 12:18:23.974716 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7658 12:18:23.981512 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 12:18:23.984473 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 12:18:23.987875 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 12:18:23.994974 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 12:18:23.997926 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7663 12:18:24.001270 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7664 12:18:24.004464 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7665 12:18:24.011486 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7666 12:18:24.014834 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 12:18:24.018152 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 12:18:24.024683 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 12:18:24.027741 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 12:18:24.031373 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 12:18:24.038167 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 12:18:24.041653 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 12:18:24.045089 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 12:18:24.051390 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 12:18:24.054980 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 12:18:24.057990 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 12:18:24.065217 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 12:18:24.068346 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 12:18:24.071515 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7680 12:18:24.074844 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7681 12:18:24.078317 Total UI for P1: 0, mck2ui 16
7682 12:18:24.081510 best dqsien dly found for B0: ( 1, 9, 16)
7683 12:18:24.088393 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7684 12:18:24.091792 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7685 12:18:24.095243 Total UI for P1: 0, mck2ui 16
7686 12:18:24.098319 best dqsien dly found for B1: ( 1, 9, 22)
7687 12:18:24.101698 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7688 12:18:24.105058 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7689 12:18:24.105476
7690 12:18:24.108684 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7691 12:18:24.111943 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7692 12:18:24.115618 [Gating] SW calibration Done
7693 12:18:24.116035 ==
7694 12:18:24.118306 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 12:18:24.125210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 12:18:24.125668 ==
7697 12:18:24.126024 RX Vref Scan: 0
7698 12:18:24.126339
7699 12:18:24.128216 RX Vref 0 -> 0, step: 1
7700 12:18:24.128636
7701 12:18:24.131599 RX Delay 0 -> 252, step: 8
7702 12:18:24.135286 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7703 12:18:24.138163 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7704 12:18:24.141468 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7705 12:18:24.145065 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7706 12:18:24.151474 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7707 12:18:24.155066 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7708 12:18:24.158473 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7709 12:18:24.161515 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7710 12:18:24.165043 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7711 12:18:24.171554 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7712 12:18:24.175158 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7713 12:18:24.178182 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7714 12:18:24.181420 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7715 12:18:24.184929 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7716 12:18:24.191943 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7717 12:18:24.195006 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7718 12:18:24.195505 ==
7719 12:18:24.198595 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 12:18:24.201845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 12:18:24.202335 ==
7722 12:18:24.202674 DQS Delay:
7723 12:18:24.205235 DQS0 = 0, DQS1 = 0
7724 12:18:24.205678 DQM Delay:
7725 12:18:24.208325 DQM0 = 132, DQM1 = 125
7726 12:18:24.208736 DQ Delay:
7727 12:18:24.211779 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7728 12:18:24.214814 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7729 12:18:24.218359 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7730 12:18:24.225546 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7731 12:18:24.226057
7732 12:18:24.226384
7733 12:18:24.226682 ==
7734 12:18:24.228873 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 12:18:24.231633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 12:18:24.232096 ==
7737 12:18:24.232459
7738 12:18:24.232782
7739 12:18:24.235437 TX Vref Scan disable
7740 12:18:24.235876 == TX Byte 0 ==
7741 12:18:24.241943 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7742 12:18:24.245182 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7743 12:18:24.245621 == TX Byte 1 ==
7744 12:18:24.251716 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7745 12:18:24.255184 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7746 12:18:24.255602 ==
7747 12:18:24.258557 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 12:18:24.261838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 12:18:24.262272 ==
7750 12:18:24.275485
7751 12:18:24.279117 TX Vref early break, caculate TX vref
7752 12:18:24.282302 TX Vref=16, minBit 0, minWin=21, winSum=349
7753 12:18:24.285797 TX Vref=18, minBit 0, minWin=22, winSum=366
7754 12:18:24.288749 TX Vref=20, minBit 7, minWin=21, winSum=373
7755 12:18:24.292308 TX Vref=22, minBit 1, minWin=22, winSum=384
7756 12:18:24.295699 TX Vref=24, minBit 0, minWin=24, winSum=400
7757 12:18:24.302131 TX Vref=26, minBit 1, minWin=24, winSum=408
7758 12:18:24.305826 TX Vref=28, minBit 7, minWin=24, winSum=414
7759 12:18:24.309272 TX Vref=30, minBit 1, minWin=24, winSum=415
7760 12:18:24.312114 TX Vref=32, minBit 4, minWin=23, winSum=405
7761 12:18:24.315938 TX Vref=34, minBit 3, minWin=23, winSum=393
7762 12:18:24.322581 [TxChooseVref] Worse bit 1, Min win 24, Win sum 415, Final Vref 30
7763 12:18:24.323053
7764 12:18:24.325763 Final TX Range 0 Vref 30
7765 12:18:24.326178
7766 12:18:24.326534 ==
7767 12:18:24.329091 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 12:18:24.332267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 12:18:24.332715 ==
7770 12:18:24.333047
7771 12:18:24.333343
7772 12:18:24.336039 TX Vref Scan disable
7773 12:18:24.342354 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7774 12:18:24.342869 == TX Byte 0 ==
7775 12:18:24.346150 u2DelayCellOfst[0]=14 cells (4 PI)
7776 12:18:24.348939 u2DelayCellOfst[1]=21 cells (6 PI)
7777 12:18:24.352370 u2DelayCellOfst[2]=10 cells (3 PI)
7778 12:18:24.355783 u2DelayCellOfst[3]=14 cells (4 PI)
7779 12:18:24.358785 u2DelayCellOfst[4]=10 cells (3 PI)
7780 12:18:24.362164 u2DelayCellOfst[5]=0 cells (0 PI)
7781 12:18:24.362781 u2DelayCellOfst[6]=17 cells (5 PI)
7782 12:18:24.365816 u2DelayCellOfst[7]=17 cells (5 PI)
7783 12:18:24.372283 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7784 12:18:24.375316 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7785 12:18:24.375775 == TX Byte 1 ==
7786 12:18:24.379406 u2DelayCellOfst[8]=3 cells (1 PI)
7787 12:18:24.382384 u2DelayCellOfst[9]=0 cells (0 PI)
7788 12:18:24.385629 u2DelayCellOfst[10]=7 cells (2 PI)
7789 12:18:24.388695 u2DelayCellOfst[11]=0 cells (0 PI)
7790 12:18:24.392276 u2DelayCellOfst[12]=10 cells (3 PI)
7791 12:18:24.395489 u2DelayCellOfst[13]=14 cells (4 PI)
7792 12:18:24.399048 u2DelayCellOfst[14]=17 cells (5 PI)
7793 12:18:24.402582 u2DelayCellOfst[15]=10 cells (3 PI)
7794 12:18:24.405613 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7795 12:18:24.408884 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7796 12:18:24.412053 DramC Write-DBI on
7797 12:18:24.412515 ==
7798 12:18:24.415551 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 12:18:24.418950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 12:18:24.419369 ==
7801 12:18:24.419695
7802 12:18:24.419995
7803 12:18:24.421958 TX Vref Scan disable
7804 12:18:24.425916 == TX Byte 0 ==
7805 12:18:24.429093 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7806 12:18:24.432509 == TX Byte 1 ==
7807 12:18:24.435373 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7808 12:18:24.435795 DramC Write-DBI off
7809 12:18:24.436122
7810 12:18:24.438798 [DATLAT]
7811 12:18:24.439235 Freq=1600, CH0 RK0
7812 12:18:24.439713
7813 12:18:24.442470 DATLAT Default: 0xf
7814 12:18:24.442920 0, 0xFFFF, sum = 0
7815 12:18:24.445771 1, 0xFFFF, sum = 0
7816 12:18:24.446186 2, 0xFFFF, sum = 0
7817 12:18:24.448789 3, 0xFFFF, sum = 0
7818 12:18:24.449207 4, 0xFFFF, sum = 0
7819 12:18:24.452247 5, 0xFFFF, sum = 0
7820 12:18:24.452720 6, 0xFFFF, sum = 0
7821 12:18:24.455869 7, 0xFFFF, sum = 0
7822 12:18:24.456291 8, 0xFFFF, sum = 0
7823 12:18:24.458824 9, 0xFFFF, sum = 0
7824 12:18:24.459246 10, 0xFFFF, sum = 0
7825 12:18:24.462315 11, 0xFFFF, sum = 0
7826 12:18:24.465384 12, 0xFFFF, sum = 0
7827 12:18:24.465804 13, 0xFFFF, sum = 0
7828 12:18:24.468893 14, 0x0, sum = 1
7829 12:18:24.469336 15, 0x0, sum = 2
7830 12:18:24.469667 16, 0x0, sum = 3
7831 12:18:24.472517 17, 0x0, sum = 4
7832 12:18:24.472936 best_step = 15
7833 12:18:24.473258
7834 12:18:24.473562 ==
7835 12:18:24.475613 Dram Type= 6, Freq= 0, CH_0, rank 0
7836 12:18:24.482270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7837 12:18:24.482686 ==
7838 12:18:24.483068 RX Vref Scan: 1
7839 12:18:24.483379
7840 12:18:24.485946 Set Vref Range= 24 -> 127
7841 12:18:24.486427
7842 12:18:24.489205 RX Vref 24 -> 127, step: 1
7843 12:18:24.489631
7844 12:18:24.492501 RX Delay 11 -> 252, step: 4
7845 12:18:24.492928
7846 12:18:24.496420 Set Vref, RX VrefLevel [Byte0]: 24
7847 12:18:24.496849 [Byte1]: 24
7848 12:18:24.500182
7849 12:18:24.500752 Set Vref, RX VrefLevel [Byte0]: 25
7850 12:18:24.503761 [Byte1]: 25
7851 12:18:24.507967
7852 12:18:24.508395 Set Vref, RX VrefLevel [Byte0]: 26
7853 12:18:24.511304 [Byte1]: 26
7854 12:18:24.515687
7855 12:18:24.516114 Set Vref, RX VrefLevel [Byte0]: 27
7856 12:18:24.518862 [Byte1]: 27
7857 12:18:24.523274
7858 12:18:24.523767 Set Vref, RX VrefLevel [Byte0]: 28
7859 12:18:24.526426 [Byte1]: 28
7860 12:18:24.530942
7861 12:18:24.531428 Set Vref, RX VrefLevel [Byte0]: 29
7862 12:18:24.534242 [Byte1]: 29
7863 12:18:24.537919
7864 12:18:24.538345 Set Vref, RX VrefLevel [Byte0]: 30
7865 12:18:24.541219 [Byte1]: 30
7866 12:18:24.545799
7867 12:18:24.546223 Set Vref, RX VrefLevel [Byte0]: 31
7868 12:18:24.549424 [Byte1]: 31
7869 12:18:24.553494
7870 12:18:24.553938 Set Vref, RX VrefLevel [Byte0]: 32
7871 12:18:24.556603 [Byte1]: 32
7872 12:18:24.561409
7873 12:18:24.561888 Set Vref, RX VrefLevel [Byte0]: 33
7874 12:18:24.564679 [Byte1]: 33
7875 12:18:24.568473
7876 12:18:24.568918 Set Vref, RX VrefLevel [Byte0]: 34
7877 12:18:24.572445 [Byte1]: 34
7878 12:18:24.576637
7879 12:18:24.577062 Set Vref, RX VrefLevel [Byte0]: 35
7880 12:18:24.579785 [Byte1]: 35
7881 12:18:24.583731
7882 12:18:24.584155 Set Vref, RX VrefLevel [Byte0]: 36
7883 12:18:24.587537 [Byte1]: 36
7884 12:18:24.591511
7885 12:18:24.591938 Set Vref, RX VrefLevel [Byte0]: 37
7886 12:18:24.594687 [Byte1]: 37
7887 12:18:24.599226
7888 12:18:24.599995 Set Vref, RX VrefLevel [Byte0]: 38
7889 12:18:24.602337 [Byte1]: 38
7890 12:18:24.606680
7891 12:18:24.607398 Set Vref, RX VrefLevel [Byte0]: 39
7892 12:18:24.610110 [Byte1]: 39
7893 12:18:24.614416
7894 12:18:24.614969 Set Vref, RX VrefLevel [Byte0]: 40
7895 12:18:24.617314 [Byte1]: 40
7896 12:18:24.621403
7897 12:18:24.621509 Set Vref, RX VrefLevel [Byte0]: 41
7898 12:18:24.624902 [Byte1]: 41
7899 12:18:24.629049
7900 12:18:24.629156 Set Vref, RX VrefLevel [Byte0]: 42
7901 12:18:24.632719 [Byte1]: 42
7902 12:18:24.636778
7903 12:18:24.636880 Set Vref, RX VrefLevel [Byte0]: 43
7904 12:18:24.640288 [Byte1]: 43
7905 12:18:24.644535
7906 12:18:24.644621 Set Vref, RX VrefLevel [Byte0]: 44
7907 12:18:24.647681 [Byte1]: 44
7908 12:18:24.651894
7909 12:18:24.651995 Set Vref, RX VrefLevel [Byte0]: 45
7910 12:18:24.655363 [Byte1]: 45
7911 12:18:24.659700
7912 12:18:24.659775 Set Vref, RX VrefLevel [Byte0]: 46
7913 12:18:24.662618 [Byte1]: 46
7914 12:18:24.667039
7915 12:18:24.667131 Set Vref, RX VrefLevel [Byte0]: 47
7916 12:18:24.670447 [Byte1]: 47
7917 12:18:24.675167
7918 12:18:24.675272 Set Vref, RX VrefLevel [Byte0]: 48
7919 12:18:24.678663 [Byte1]: 48
7920 12:18:24.682286
7921 12:18:24.682387 Set Vref, RX VrefLevel [Byte0]: 49
7922 12:18:24.685619 [Byte1]: 49
7923 12:18:24.690269
7924 12:18:24.690372 Set Vref, RX VrefLevel [Byte0]: 50
7925 12:18:24.693319 [Byte1]: 50
7926 12:18:24.697651
7927 12:18:24.697728 Set Vref, RX VrefLevel [Byte0]: 51
7928 12:18:24.700989 [Byte1]: 51
7929 12:18:24.705356
7930 12:18:24.705454 Set Vref, RX VrefLevel [Byte0]: 52
7931 12:18:24.708639 [Byte1]: 52
7932 12:18:24.712710
7933 12:18:24.712818 Set Vref, RX VrefLevel [Byte0]: 53
7934 12:18:24.716314 [Byte1]: 53
7935 12:18:24.720542
7936 12:18:24.720648 Set Vref, RX VrefLevel [Byte0]: 54
7937 12:18:24.724015 [Byte1]: 54
7938 12:18:24.728074
7939 12:18:24.728172 Set Vref, RX VrefLevel [Byte0]: 55
7940 12:18:24.731633 [Byte1]: 55
7941 12:18:24.735780
7942 12:18:24.735855 Set Vref, RX VrefLevel [Byte0]: 56
7943 12:18:24.738883 [Byte1]: 56
7944 12:18:24.743118
7945 12:18:24.743195 Set Vref, RX VrefLevel [Byte0]: 57
7946 12:18:24.746596 [Byte1]: 57
7947 12:18:24.751086
7948 12:18:24.751159 Set Vref, RX VrefLevel [Byte0]: 58
7949 12:18:24.754371 [Byte1]: 58
7950 12:18:24.758508
7951 12:18:24.758611 Set Vref, RX VrefLevel [Byte0]: 59
7952 12:18:24.761967 [Byte1]: 59
7953 12:18:24.766240
7954 12:18:24.766342 Set Vref, RX VrefLevel [Byte0]: 60
7955 12:18:24.769398 [Byte1]: 60
7956 12:18:24.774153
7957 12:18:24.774254 Set Vref, RX VrefLevel [Byte0]: 61
7958 12:18:24.776875 [Byte1]: 61
7959 12:18:24.781405
7960 12:18:24.781504 Set Vref, RX VrefLevel [Byte0]: 62
7961 12:18:24.784492 [Byte1]: 62
7962 12:18:24.789106
7963 12:18:24.789186 Set Vref, RX VrefLevel [Byte0]: 63
7964 12:18:24.792271 [Byte1]: 63
7965 12:18:24.796866
7966 12:18:24.796971 Set Vref, RX VrefLevel [Byte0]: 64
7967 12:18:24.800048 [Byte1]: 64
7968 12:18:24.804268
7969 12:18:24.804366 Set Vref, RX VrefLevel [Byte0]: 65
7970 12:18:24.807664 [Byte1]: 65
7971 12:18:24.812059
7972 12:18:24.812137 Set Vref, RX VrefLevel [Byte0]: 66
7973 12:18:24.814971 [Byte1]: 66
7974 12:18:24.819334
7975 12:18:24.819411 Set Vref, RX VrefLevel [Byte0]: 67
7976 12:18:24.822867 [Byte1]: 67
7977 12:18:24.827139
7978 12:18:24.827218 Set Vref, RX VrefLevel [Byte0]: 68
7979 12:18:24.830318 [Byte1]: 68
7980 12:18:24.835315
7981 12:18:24.835392 Set Vref, RX VrefLevel [Byte0]: 69
7982 12:18:24.838269 [Byte1]: 69
7983 12:18:24.842197
7984 12:18:24.842329 Set Vref, RX VrefLevel [Byte0]: 70
7985 12:18:24.845291 [Byte1]: 70
7986 12:18:24.850027
7987 12:18:24.850130 Set Vref, RX VrefLevel [Byte0]: 71
7988 12:18:24.853594 [Byte1]: 71
7989 12:18:24.857646
7990 12:18:24.857728 Set Vref, RX VrefLevel [Byte0]: 72
7991 12:18:24.860819 [Byte1]: 72
7992 12:18:24.865279
7993 12:18:24.865353 Set Vref, RX VrefLevel [Byte0]: 73
7994 12:18:24.868546 [Byte1]: 73
7995 12:18:24.872567
7996 12:18:24.872643 Set Vref, RX VrefLevel [Byte0]: 74
7997 12:18:24.876043 [Byte1]: 74
7998 12:18:24.880337
7999 12:18:24.880442 Set Vref, RX VrefLevel [Byte0]: 75
8000 12:18:24.883720 [Byte1]: 75
8001 12:18:24.888218
8002 12:18:24.888294 Set Vref, RX VrefLevel [Byte0]: 76
8003 12:18:24.891384 [Byte1]: 76
8004 12:18:24.895813
8005 12:18:24.895903 Final RX Vref Byte 0 = 62 to rank0
8006 12:18:24.898971 Final RX Vref Byte 1 = 63 to rank0
8007 12:18:24.902650 Final RX Vref Byte 0 = 62 to rank1
8008 12:18:24.905505 Final RX Vref Byte 1 = 63 to rank1==
8009 12:18:24.908999 Dram Type= 6, Freq= 0, CH_0, rank 0
8010 12:18:24.915703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 12:18:24.915788 ==
8012 12:18:24.915872 DQS Delay:
8013 12:18:24.915950 DQS0 = 0, DQS1 = 0
8014 12:18:24.919124 DQM Delay:
8015 12:18:24.919207 DQM0 = 129, DQM1 = 122
8016 12:18:24.922673 DQ Delay:
8017 12:18:24.925465 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
8018 12:18:24.929203 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8019 12:18:24.932832 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8020 12:18:24.935529 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =132
8021 12:18:24.935612
8022 12:18:24.935695
8023 12:18:24.935773
8024 12:18:24.939233 [DramC_TX_OE_Calibration] TA2
8025 12:18:24.942439 Original DQ_B0 (3 6) =30, OEN = 27
8026 12:18:24.946115 Original DQ_B1 (3 6) =30, OEN = 27
8027 12:18:24.949174 24, 0x0, End_B0=24 End_B1=24
8028 12:18:24.949258 25, 0x0, End_B0=25 End_B1=25
8029 12:18:24.952642 26, 0x0, End_B0=26 End_B1=26
8030 12:18:24.956018 27, 0x0, End_B0=27 End_B1=27
8031 12:18:24.959207 28, 0x0, End_B0=28 End_B1=28
8032 12:18:24.959312 29, 0x0, End_B0=29 End_B1=29
8033 12:18:24.962094 30, 0x0, End_B0=30 End_B1=30
8034 12:18:24.965909 31, 0x4141, End_B0=30 End_B1=30
8035 12:18:24.969132 Byte0 end_step=30 best_step=27
8036 12:18:24.972451 Byte1 end_step=30 best_step=27
8037 12:18:24.975750 Byte0 TX OE(2T, 0.5T) = (3, 3)
8038 12:18:24.975849 Byte1 TX OE(2T, 0.5T) = (3, 3)
8039 12:18:24.975943
8040 12:18:24.976030
8041 12:18:24.985576 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
8042 12:18:24.989126 CH0 RK0: MR19=303, MR18=1408
8043 12:18:24.992490 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
8044 12:18:24.996066
8045 12:18:24.999072 ----->DramcWriteLeveling(PI) begin...
8046 12:18:24.999157 ==
8047 12:18:25.002243 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 12:18:25.005740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 12:18:25.005842 ==
8050 12:18:25.009397 Write leveling (Byte 0): 33 => 33
8051 12:18:25.012386 Write leveling (Byte 1): 27 => 27
8052 12:18:25.015870 DramcWriteLeveling(PI) end<-----
8053 12:18:25.015967
8054 12:18:25.016058 ==
8055 12:18:25.019489 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 12:18:25.022346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 12:18:25.022448 ==
8058 12:18:25.025706 [Gating] SW mode calibration
8059 12:18:25.032609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8060 12:18:25.039693 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8061 12:18:25.042605 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8062 12:18:25.046031 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 12:18:25.049086 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 12:18:25.056209 1 4 12 | B1->B0 | 2323 3332 | 0 1 | (0 0) (1 1)
8065 12:18:25.059183 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8066 12:18:25.062519 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8067 12:18:25.069888 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 12:18:25.072817 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 12:18:25.075825 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 12:18:25.082632 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 12:18:25.085899 1 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
8072 12:18:25.089889 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
8073 12:18:25.096035 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8074 12:18:25.099634 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8075 12:18:25.102944 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
8076 12:18:25.109905 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 12:18:25.112641 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 12:18:25.116526 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 12:18:25.122830 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8080 12:18:25.126217 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8081 12:18:25.129636 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8082 12:18:25.133201 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8083 12:18:25.139649 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 12:18:25.142938 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 12:18:25.146226 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 12:18:25.153013 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 12:18:25.156738 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 12:18:25.159718 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8089 12:18:25.166441 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8090 12:18:25.170090 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8091 12:18:25.172928 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 12:18:25.179764 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 12:18:25.183205 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:18:25.186506 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 12:18:25.192913 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 12:18:25.196475 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 12:18:25.199971 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:18:25.202985 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:18:25.209514 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:18:25.213189 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 12:18:25.216362 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 12:18:25.222892 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 12:18:25.226196 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8104 12:18:25.229607 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8105 12:18:25.233345 Total UI for P1: 0, mck2ui 16
8106 12:18:25.236265 best dqsien dly found for B0: ( 1, 9, 8)
8107 12:18:25.243042 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8108 12:18:25.246566 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8109 12:18:25.250259 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8110 12:18:25.253186 Total UI for P1: 0, mck2ui 16
8111 12:18:25.256112 best dqsien dly found for B1: ( 1, 9, 20)
8112 12:18:25.259678 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8113 12:18:25.262764 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8114 12:18:25.262841
8115 12:18:25.269853 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8116 12:18:25.273303 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8117 12:18:25.273385 [Gating] SW calibration Done
8118 12:18:25.276451 ==
8119 12:18:25.279858 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 12:18:25.282994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 12:18:25.283076 ==
8122 12:18:25.283139 RX Vref Scan: 0
8123 12:18:25.283199
8124 12:18:25.286341 RX Vref 0 -> 0, step: 1
8125 12:18:25.286423
8126 12:18:25.289774 RX Delay 0 -> 252, step: 8
8127 12:18:25.293414 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8128 12:18:25.296877 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8129 12:18:25.299560 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8130 12:18:25.306249 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8131 12:18:25.309917 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8132 12:18:25.313414 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8133 12:18:25.316665 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8134 12:18:25.320232 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8135 12:18:25.323362 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8136 12:18:25.329635 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8137 12:18:25.332973 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8138 12:18:25.336504 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8139 12:18:25.339889 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8140 12:18:25.343126 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8141 12:18:25.349928 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8142 12:18:25.353683 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8143 12:18:25.353763 ==
8144 12:18:25.357236 Dram Type= 6, Freq= 0, CH_0, rank 1
8145 12:18:25.360219 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8146 12:18:25.360301 ==
8147 12:18:25.363916 DQS Delay:
8148 12:18:25.363996 DQS0 = 0, DQS1 = 0
8149 12:18:25.364059 DQM Delay:
8150 12:18:25.366683 DQM0 = 130, DQM1 = 123
8151 12:18:25.366788 DQ Delay:
8152 12:18:25.370386 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8153 12:18:25.373354 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8154 12:18:25.376742 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8155 12:18:25.383324 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8156 12:18:25.383405
8157 12:18:25.383469
8158 12:18:25.383528 ==
8159 12:18:25.386761 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 12:18:25.390363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 12:18:25.390444 ==
8162 12:18:25.390507
8163 12:18:25.390566
8164 12:18:25.393363 TX Vref Scan disable
8165 12:18:25.393444 == TX Byte 0 ==
8166 12:18:25.400325 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8167 12:18:25.403606 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8168 12:18:25.403688 == TX Byte 1 ==
8169 12:18:25.410483 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8170 12:18:25.413318 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8171 12:18:25.413400 ==
8172 12:18:25.416873 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 12:18:25.419692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 12:18:25.419773 ==
8175 12:18:25.435969
8176 12:18:25.439259 TX Vref early break, caculate TX vref
8177 12:18:25.442607 TX Vref=16, minBit 4, minWin=22, winSum=370
8178 12:18:25.446321 TX Vref=18, minBit 9, minWin=22, winSum=381
8179 12:18:25.449264 TX Vref=20, minBit 0, minWin=23, winSum=388
8180 12:18:25.452483 TX Vref=22, minBit 9, minWin=23, winSum=393
8181 12:18:25.455429 TX Vref=24, minBit 4, minWin=24, winSum=402
8182 12:18:25.462593 TX Vref=26, minBit 0, minWin=25, winSum=415
8183 12:18:25.465524 TX Vref=28, minBit 2, minWin=25, winSum=418
8184 12:18:25.469103 TX Vref=30, minBit 4, minWin=25, winSum=418
8185 12:18:25.472812 TX Vref=32, minBit 0, minWin=25, winSum=409
8186 12:18:25.475735 TX Vref=34, minBit 0, minWin=24, winSum=400
8187 12:18:25.479111 TX Vref=36, minBit 0, minWin=23, winSum=390
8188 12:18:25.485615 [TxChooseVref] Worse bit 2, Min win 25, Win sum 418, Final Vref 28
8189 12:18:25.485694
8190 12:18:25.489147 Final TX Range 0 Vref 28
8191 12:18:25.489235
8192 12:18:25.489297 ==
8193 12:18:25.492195 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 12:18:25.495995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 12:18:25.496077 ==
8196 12:18:25.496142
8197 12:18:25.496201
8198 12:18:25.499160 TX Vref Scan disable
8199 12:18:25.506087 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8200 12:18:25.506171 == TX Byte 0 ==
8201 12:18:25.509136 u2DelayCellOfst[0]=14 cells (4 PI)
8202 12:18:25.512545 u2DelayCellOfst[1]=17 cells (5 PI)
8203 12:18:25.515776 u2DelayCellOfst[2]=10 cells (3 PI)
8204 12:18:25.518915 u2DelayCellOfst[3]=10 cells (3 PI)
8205 12:18:25.522549 u2DelayCellOfst[4]=10 cells (3 PI)
8206 12:18:25.525825 u2DelayCellOfst[5]=0 cells (0 PI)
8207 12:18:25.529505 u2DelayCellOfst[6]=17 cells (5 PI)
8208 12:18:25.532532 u2DelayCellOfst[7]=17 cells (5 PI)
8209 12:18:25.535887 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8210 12:18:25.539311 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8211 12:18:25.542869 == TX Byte 1 ==
8212 12:18:25.542953 u2DelayCellOfst[8]=0 cells (0 PI)
8213 12:18:25.545876 u2DelayCellOfst[9]=0 cells (0 PI)
8214 12:18:25.549427 u2DelayCellOfst[10]=7 cells (2 PI)
8215 12:18:25.552818 u2DelayCellOfst[11]=0 cells (0 PI)
8216 12:18:25.556065 u2DelayCellOfst[12]=10 cells (3 PI)
8217 12:18:25.559334 u2DelayCellOfst[13]=10 cells (3 PI)
8218 12:18:25.562219 u2DelayCellOfst[14]=14 cells (4 PI)
8219 12:18:25.565723 u2DelayCellOfst[15]=10 cells (3 PI)
8220 12:18:25.569020 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8221 12:18:25.575759 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8222 12:18:25.575841 DramC Write-DBI on
8223 12:18:25.575906 ==
8224 12:18:25.579611 Dram Type= 6, Freq= 0, CH_0, rank 1
8225 12:18:25.582587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 12:18:25.582695 ==
8227 12:18:25.586285
8228 12:18:25.586366
8229 12:18:25.586430 TX Vref Scan disable
8230 12:18:25.589041 == TX Byte 0 ==
8231 12:18:25.592845 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8232 12:18:25.595694 == TX Byte 1 ==
8233 12:18:25.599132 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8234 12:18:25.599207 DramC Write-DBI off
8235 12:18:25.599268
8236 12:18:25.602932 [DATLAT]
8237 12:18:25.603004 Freq=1600, CH0 RK1
8238 12:18:25.603065
8239 12:18:25.605737 DATLAT Default: 0xf
8240 12:18:25.605808 0, 0xFFFF, sum = 0
8241 12:18:25.609518 1, 0xFFFF, sum = 0
8242 12:18:25.609591 2, 0xFFFF, sum = 0
8243 12:18:25.612469 3, 0xFFFF, sum = 0
8244 12:18:25.612547 4, 0xFFFF, sum = 0
8245 12:18:25.615870 5, 0xFFFF, sum = 0
8246 12:18:25.615943 6, 0xFFFF, sum = 0
8247 12:18:25.619230 7, 0xFFFF, sum = 0
8248 12:18:25.619303 8, 0xFFFF, sum = 0
8249 12:18:25.622693 9, 0xFFFF, sum = 0
8250 12:18:25.626089 10, 0xFFFF, sum = 0
8251 12:18:25.626162 11, 0xFFFF, sum = 0
8252 12:18:25.629290 12, 0xFFFF, sum = 0
8253 12:18:25.629361 13, 0xFFFF, sum = 0
8254 12:18:25.632737 14, 0x0, sum = 1
8255 12:18:25.632810 15, 0x0, sum = 2
8256 12:18:25.636220 16, 0x0, sum = 3
8257 12:18:25.636295 17, 0x0, sum = 4
8258 12:18:25.636358 best_step = 15
8259 12:18:25.639412
8260 12:18:25.639494 ==
8261 12:18:25.643087 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 12:18:25.645922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 12:18:25.646003 ==
8264 12:18:25.646098 RX Vref Scan: 0
8265 12:18:25.646159
8266 12:18:25.649602 RX Vref 0 -> 0, step: 1
8267 12:18:25.649683
8268 12:18:25.652522 RX Delay 11 -> 252, step: 4
8269 12:18:25.656065 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8270 12:18:25.659787 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8271 12:18:25.666347 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8272 12:18:25.669731 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8273 12:18:25.673083 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8274 12:18:25.676210 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8275 12:18:25.679384 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8276 12:18:25.686423 iDelay=195, Bit 7, Center 136 (83 ~ 190) 108
8277 12:18:25.689685 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8278 12:18:25.693023 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8279 12:18:25.696020 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8280 12:18:25.699635 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8281 12:18:25.706278 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8282 12:18:25.709630 iDelay=195, Bit 13, Center 128 (71 ~ 186) 116
8283 12:18:25.713119 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8284 12:18:25.716566 iDelay=195, Bit 15, Center 132 (75 ~ 190) 116
8285 12:18:25.716665 ==
8286 12:18:25.719578 Dram Type= 6, Freq= 0, CH_0, rank 1
8287 12:18:25.726002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8288 12:18:25.726084 ==
8289 12:18:25.726148 DQS Delay:
8290 12:18:25.726207 DQS0 = 0, DQS1 = 0
8291 12:18:25.729423 DQM Delay:
8292 12:18:25.729505 DQM0 = 128, DQM1 = 122
8293 12:18:25.732782 DQ Delay:
8294 12:18:25.736235 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8295 12:18:25.739873 DQ4 =128, DQ5 =116, DQ6 =138, DQ7 =136
8296 12:18:25.742902 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8297 12:18:25.746519 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8298 12:18:25.746601
8299 12:18:25.746665
8300 12:18:25.746732
8301 12:18:25.749925 [DramC_TX_OE_Calibration] TA2
8302 12:18:25.752923 Original DQ_B0 (3 6) =30, OEN = 27
8303 12:18:25.756081 Original DQ_B1 (3 6) =30, OEN = 27
8304 12:18:25.759717 24, 0x0, End_B0=24 End_B1=24
8305 12:18:25.759800 25, 0x0, End_B0=25 End_B1=25
8306 12:18:25.762641 26, 0x0, End_B0=26 End_B1=26
8307 12:18:25.766240 27, 0x0, End_B0=27 End_B1=27
8308 12:18:25.769811 28, 0x0, End_B0=28 End_B1=28
8309 12:18:25.769894 29, 0x0, End_B0=29 End_B1=29
8310 12:18:25.772744 30, 0x0, End_B0=30 End_B1=30
8311 12:18:25.776460 31, 0x4141, End_B0=30 End_B1=30
8312 12:18:25.779475 Byte0 end_step=30 best_step=27
8313 12:18:25.782976 Byte1 end_step=30 best_step=27
8314 12:18:25.786547 Byte0 TX OE(2T, 0.5T) = (3, 3)
8315 12:18:25.786629 Byte1 TX OE(2T, 0.5T) = (3, 3)
8316 12:18:25.786710
8317 12:18:25.786822
8318 12:18:25.796469 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8319 12:18:25.799698 CH0 RK1: MR19=303, MR18=1B10
8320 12:18:25.802932 CH0_RK1: MR19=0x303, MR18=0x1B10, DQSOSC=396, MR23=63, INC=23, DEC=15
8321 12:18:25.806511 [RxdqsGatingPostProcess] freq 1600
8322 12:18:25.813588 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8323 12:18:25.816589 best DQS0 dly(2T, 0.5T) = (1, 1)
8324 12:18:25.820010 best DQS1 dly(2T, 0.5T) = (1, 1)
8325 12:18:25.823371 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8326 12:18:25.826765 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8327 12:18:25.829756 best DQS0 dly(2T, 0.5T) = (1, 1)
8328 12:18:25.829840 best DQS1 dly(2T, 0.5T) = (1, 1)
8329 12:18:25.833292 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8330 12:18:25.836833 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8331 12:18:25.839880 Pre-setting of DQS Precalculation
8332 12:18:25.846624 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8333 12:18:25.846708 ==
8334 12:18:25.849764 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 12:18:25.853407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 12:18:25.853491 ==
8337 12:18:25.860192 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 12:18:25.863553 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 12:18:25.866508 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 12:18:25.873603 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 12:18:25.882682 [CA 0] Center 42 (14~71) winsize 58
8342 12:18:25.885422 [CA 1] Center 42 (13~71) winsize 59
8343 12:18:25.888651 [CA 2] Center 37 (8~66) winsize 59
8344 12:18:25.892465 [CA 3] Center 36 (7~65) winsize 59
8345 12:18:25.895500 [CA 4] Center 37 (7~67) winsize 61
8346 12:18:25.899039 [CA 5] Center 36 (6~66) winsize 61
8347 12:18:25.899168
8348 12:18:25.902298 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 12:18:25.902379
8350 12:18:25.905528 [CATrainingPosCal] consider 1 rank data
8351 12:18:25.908786 u2DelayCellTimex100 = 275/100 ps
8352 12:18:25.912160 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8353 12:18:25.918595 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8354 12:18:25.922273 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8355 12:18:25.925080 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8356 12:18:25.929161 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8357 12:18:25.932006 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8358 12:18:25.932110
8359 12:18:25.935287 CA PerBit enable=1, Macro0, CA PI delay=36
8360 12:18:25.935388
8361 12:18:25.938673 [CBTSetCACLKResult] CA Dly = 36
8362 12:18:25.941829 CS Dly: 9 (0~40)
8363 12:18:25.945575 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 12:18:25.948568 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 12:18:25.948676 ==
8366 12:18:25.952094 Dram Type= 6, Freq= 0, CH_1, rank 1
8367 12:18:25.955075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 12:18:25.958406 ==
8369 12:18:25.961565 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8370 12:18:25.965434 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8371 12:18:25.972012 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8372 12:18:25.975638 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8373 12:18:25.985294 [CA 0] Center 43 (14~72) winsize 59
8374 12:18:25.988754 [CA 1] Center 43 (15~72) winsize 58
8375 12:18:25.991875 [CA 2] Center 38 (9~67) winsize 59
8376 12:18:25.995052 [CA 3] Center 36 (7~66) winsize 60
8377 12:18:25.998324 [CA 4] Center 38 (9~68) winsize 60
8378 12:18:26.001821 [CA 5] Center 36 (7~66) winsize 60
8379 12:18:26.001901
8380 12:18:26.004909 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8381 12:18:26.005015
8382 12:18:26.008359 [CATrainingPosCal] consider 2 rank data
8383 12:18:26.011907 u2DelayCellTimex100 = 275/100 ps
8384 12:18:26.015386 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8385 12:18:26.021911 CA1 delay=43 (15~71),Diff = 7 PI (24 cell)
8386 12:18:26.025185 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8387 12:18:26.028841 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8388 12:18:26.031638 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8389 12:18:26.035295 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8390 12:18:26.035379
8391 12:18:26.038356 CA PerBit enable=1, Macro0, CA PI delay=36
8392 12:18:26.038437
8393 12:18:26.041840 [CBTSetCACLKResult] CA Dly = 36
8394 12:18:26.045153 CS Dly: 11 (0~45)
8395 12:18:26.048834 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8396 12:18:26.051672 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8397 12:18:26.051754
8398 12:18:26.055407 ----->DramcWriteLeveling(PI) begin...
8399 12:18:26.055492 ==
8400 12:18:26.058431 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 12:18:26.061974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 12:18:26.065668 ==
8403 12:18:26.065777 Write leveling (Byte 0): 25 => 25
8404 12:18:26.068833 Write leveling (Byte 1): 29 => 29
8405 12:18:26.072045 DramcWriteLeveling(PI) end<-----
8406 12:18:26.072126
8407 12:18:26.072195 ==
8408 12:18:26.075408 Dram Type= 6, Freq= 0, CH_1, rank 0
8409 12:18:26.082067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8410 12:18:26.082150 ==
8411 12:18:26.082215 [Gating] SW mode calibration
8412 12:18:26.091906 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8413 12:18:26.095303 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8414 12:18:26.099100 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 12:18:26.105313 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 12:18:26.108939 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 12:18:26.112123 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 12:18:26.118551 1 4 16 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
8419 12:18:26.122155 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8420 12:18:26.125098 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 12:18:26.131995 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 12:18:26.135290 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 12:18:26.138422 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 12:18:26.145325 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 12:18:26.148378 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 12:18:26.151796 1 5 16 | B1->B0 | 2f2f 3333 | 0 0 | (1 0) (0 0)
8427 12:18:26.158627 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 12:18:26.162101 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 12:18:26.165727 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 12:18:26.168765 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 12:18:26.175590 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 12:18:26.179062 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 12:18:26.182099 1 6 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8434 12:18:26.189020 1 6 16 | B1->B0 | 3838 3333 | 0 0 | (0 0) (0 0)
8435 12:18:26.191996 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 12:18:26.195453 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 12:18:26.202367 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 12:18:26.205335 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 12:18:26.208635 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 12:18:26.215300 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 12:18:26.218605 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 12:18:26.222136 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8443 12:18:26.228671 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8444 12:18:26.232278 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 12:18:26.235260 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 12:18:26.242516 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 12:18:26.245651 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 12:18:26.249285 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 12:18:26.252303 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 12:18:26.258592 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 12:18:26.262476 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 12:18:26.265478 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 12:18:26.271814 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 12:18:26.275589 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 12:18:26.278992 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 12:18:26.285609 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 12:18:26.288505 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8458 12:18:26.292078 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 12:18:26.298488 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 12:18:26.302381 Total UI for P1: 0, mck2ui 16
8461 12:18:26.305446 best dqsien dly found for B0: ( 1, 9, 14)
8462 12:18:26.305529 Total UI for P1: 0, mck2ui 16
8463 12:18:26.311940 best dqsien dly found for B1: ( 1, 9, 16)
8464 12:18:26.315548 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8465 12:18:26.318524 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8466 12:18:26.318633
8467 12:18:26.322052 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8468 12:18:26.325618 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8469 12:18:26.329139 [Gating] SW calibration Done
8470 12:18:26.329220 ==
8471 12:18:26.332199 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 12:18:26.335878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 12:18:26.335967 ==
8474 12:18:26.338950 RX Vref Scan: 0
8475 12:18:26.339031
8476 12:18:26.339095 RX Vref 0 -> 0, step: 1
8477 12:18:26.339155
8478 12:18:26.342493 RX Delay 0 -> 252, step: 8
8479 12:18:26.345476 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8480 12:18:26.352537 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8481 12:18:26.355727 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8482 12:18:26.359290 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8483 12:18:26.362594 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8484 12:18:26.365595 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8485 12:18:26.369273 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8486 12:18:26.375958 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8487 12:18:26.379319 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8488 12:18:26.382436 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8489 12:18:26.385449 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8490 12:18:26.388919 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8491 12:18:26.395597 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8492 12:18:26.399187 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8493 12:18:26.402830 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8494 12:18:26.405602 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8495 12:18:26.405673 ==
8496 12:18:26.409126 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 12:18:26.416025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 12:18:26.416108 ==
8499 12:18:26.416172 DQS Delay:
8500 12:18:26.416232 DQS0 = 0, DQS1 = 0
8501 12:18:26.418964 DQM Delay:
8502 12:18:26.419045 DQM0 = 135, DQM1 = 127
8503 12:18:26.422284 DQ Delay:
8504 12:18:26.425644 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8505 12:18:26.428953 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8506 12:18:26.432838 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8507 12:18:26.435648 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8508 12:18:26.435733
8509 12:18:26.435819
8510 12:18:26.435901 ==
8511 12:18:26.439186 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 12:18:26.442547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 12:18:26.442632 ==
8514 12:18:26.446096
8515 12:18:26.446180
8516 12:18:26.446265 TX Vref Scan disable
8517 12:18:26.448935 == TX Byte 0 ==
8518 12:18:26.452766 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8519 12:18:26.455986 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8520 12:18:26.459046 == TX Byte 1 ==
8521 12:18:26.462619 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8522 12:18:26.465705 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8523 12:18:26.465788 ==
8524 12:18:26.469344 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 12:18:26.475730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 12:18:26.475812 ==
8527 12:18:26.488452
8528 12:18:26.492103 TX Vref early break, caculate TX vref
8529 12:18:26.495477 TX Vref=16, minBit 5, minWin=21, winSum=358
8530 12:18:26.498610 TX Vref=18, minBit 8, minWin=21, winSum=370
8531 12:18:26.501929 TX Vref=20, minBit 5, minWin=22, winSum=383
8532 12:18:26.505486 TX Vref=22, minBit 8, minWin=23, winSum=393
8533 12:18:26.508603 TX Vref=24, minBit 8, minWin=22, winSum=406
8534 12:18:26.512250 TX Vref=26, minBit 8, minWin=24, winSum=411
8535 12:18:26.518663 TX Vref=28, minBit 9, minWin=25, winSum=419
8536 12:18:26.522238 TX Vref=30, minBit 9, minWin=25, winSum=416
8537 12:18:26.525911 TX Vref=32, minBit 0, minWin=25, winSum=409
8538 12:18:26.528906 TX Vref=34, minBit 0, minWin=24, winSum=400
8539 12:18:26.532374 TX Vref=36, minBit 8, minWin=23, winSum=387
8540 12:18:26.539043 [TxChooseVref] Worse bit 9, Min win 25, Win sum 419, Final Vref 28
8541 12:18:26.539133
8542 12:18:26.541985 Final TX Range 0 Vref 28
8543 12:18:26.542059
8544 12:18:26.542121 ==
8545 12:18:26.545718 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 12:18:26.549276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 12:18:26.549371 ==
8548 12:18:26.549435
8549 12:18:26.549493
8550 12:18:26.552186 TX Vref Scan disable
8551 12:18:26.558919 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8552 12:18:26.558999 == TX Byte 0 ==
8553 12:18:26.562333 u2DelayCellOfst[0]=17 cells (5 PI)
8554 12:18:26.566012 u2DelayCellOfst[1]=14 cells (4 PI)
8555 12:18:26.568767 u2DelayCellOfst[2]=0 cells (0 PI)
8556 12:18:26.572546 u2DelayCellOfst[3]=7 cells (2 PI)
8557 12:18:26.575346 u2DelayCellOfst[4]=10 cells (3 PI)
8558 12:18:26.578960 u2DelayCellOfst[5]=17 cells (5 PI)
8559 12:18:26.582679 u2DelayCellOfst[6]=17 cells (5 PI)
8560 12:18:26.582802 u2DelayCellOfst[7]=3 cells (1 PI)
8561 12:18:26.588599 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8562 12:18:26.592345 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8563 12:18:26.592422 == TX Byte 1 ==
8564 12:18:26.595400 u2DelayCellOfst[8]=0 cells (0 PI)
8565 12:18:26.599058 u2DelayCellOfst[9]=0 cells (0 PI)
8566 12:18:26.602632 u2DelayCellOfst[10]=7 cells (2 PI)
8567 12:18:26.605629 u2DelayCellOfst[11]=3 cells (1 PI)
8568 12:18:26.609026 u2DelayCellOfst[12]=10 cells (3 PI)
8569 12:18:26.612520 u2DelayCellOfst[13]=10 cells (3 PI)
8570 12:18:26.615491 u2DelayCellOfst[14]=14 cells (4 PI)
8571 12:18:26.619144 u2DelayCellOfst[15]=14 cells (4 PI)
8572 12:18:26.622646 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8573 12:18:26.625724 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8574 12:18:26.629219 DramC Write-DBI on
8575 12:18:26.629299 ==
8576 12:18:26.632205 Dram Type= 6, Freq= 0, CH_1, rank 0
8577 12:18:26.635630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8578 12:18:26.635711 ==
8579 12:18:26.635775
8580 12:18:26.635833
8581 12:18:26.638954 TX Vref Scan disable
8582 12:18:26.642210 == TX Byte 0 ==
8583 12:18:26.645849 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8584 12:18:26.649509 == TX Byte 1 ==
8585 12:18:26.652368 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8586 12:18:26.652448 DramC Write-DBI off
8587 12:18:26.652544
8588 12:18:26.656173 [DATLAT]
8589 12:18:26.656244 Freq=1600, CH1 RK0
8590 12:18:26.656362
8591 12:18:26.659058 DATLAT Default: 0xf
8592 12:18:26.659127 0, 0xFFFF, sum = 0
8593 12:18:26.662261 1, 0xFFFF, sum = 0
8594 12:18:26.662343 2, 0xFFFF, sum = 0
8595 12:18:26.665850 3, 0xFFFF, sum = 0
8596 12:18:26.665923 4, 0xFFFF, sum = 0
8597 12:18:26.669421 5, 0xFFFF, sum = 0
8598 12:18:26.669494 6, 0xFFFF, sum = 0
8599 12:18:26.672919 7, 0xFFFF, sum = 0
8600 12:18:26.673001 8, 0xFFFF, sum = 0
8601 12:18:26.675655 9, 0xFFFF, sum = 0
8602 12:18:26.675785 10, 0xFFFF, sum = 0
8603 12:18:26.678974 11, 0xFFFF, sum = 0
8604 12:18:26.682446 12, 0xFFFF, sum = 0
8605 12:18:26.682528 13, 0xFFFF, sum = 0
8606 12:18:26.685939 14, 0x0, sum = 1
8607 12:18:26.686019 15, 0x0, sum = 2
8608 12:18:26.686082 16, 0x0, sum = 3
8609 12:18:26.689342 17, 0x0, sum = 4
8610 12:18:26.689412 best_step = 15
8611 12:18:26.689471
8612 12:18:26.689526 ==
8613 12:18:26.692536 Dram Type= 6, Freq= 0, CH_1, rank 0
8614 12:18:26.699338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8615 12:18:26.699445 ==
8616 12:18:26.699536 RX Vref Scan: 1
8617 12:18:26.699623
8618 12:18:26.702463 Set Vref Range= 24 -> 127
8619 12:18:26.702543
8620 12:18:26.706011 RX Vref 24 -> 127, step: 1
8621 12:18:26.706090
8622 12:18:26.709121 RX Delay 11 -> 252, step: 4
8623 12:18:26.709202
8624 12:18:26.712731 Set Vref, RX VrefLevel [Byte0]: 24
8625 12:18:26.712811 [Byte1]: 24
8626 12:18:26.716647
8627 12:18:26.720181 Set Vref, RX VrefLevel [Byte0]: 25
8628 12:18:26.720267 [Byte1]: 25
8629 12:18:26.724526
8630 12:18:26.724598 Set Vref, RX VrefLevel [Byte0]: 26
8631 12:18:26.728046 [Byte1]: 26
8632 12:18:26.732407
8633 12:18:26.732487 Set Vref, RX VrefLevel [Byte0]: 27
8634 12:18:26.735859 [Byte1]: 27
8635 12:18:26.739931
8636 12:18:26.740011 Set Vref, RX VrefLevel [Byte0]: 28
8637 12:18:26.742958 [Byte1]: 28
8638 12:18:26.747773
8639 12:18:26.747884 Set Vref, RX VrefLevel [Byte0]: 29
8640 12:18:26.750496 [Byte1]: 29
8641 12:18:26.754828
8642 12:18:26.754937 Set Vref, RX VrefLevel [Byte0]: 30
8643 12:18:26.758523 [Byte1]: 30
8644 12:18:26.762735
8645 12:18:26.762829 Set Vref, RX VrefLevel [Byte0]: 31
8646 12:18:26.766073 [Byte1]: 31
8647 12:18:26.770342
8648 12:18:26.770453 Set Vref, RX VrefLevel [Byte0]: 32
8649 12:18:26.773449 [Byte1]: 32
8650 12:18:26.778068
8651 12:18:26.778147 Set Vref, RX VrefLevel [Byte0]: 33
8652 12:18:26.781278 [Byte1]: 33
8653 12:18:26.785724
8654 12:18:26.785804 Set Vref, RX VrefLevel [Byte0]: 34
8655 12:18:26.788598 [Byte1]: 34
8656 12:18:26.792855
8657 12:18:26.792938 Set Vref, RX VrefLevel [Byte0]: 35
8658 12:18:26.796301 [Byte1]: 35
8659 12:18:26.800563
8660 12:18:26.800636 Set Vref, RX VrefLevel [Byte0]: 36
8661 12:18:26.804073 [Byte1]: 36
8662 12:18:26.808141
8663 12:18:26.808221 Set Vref, RX VrefLevel [Byte0]: 37
8664 12:18:26.811860 [Byte1]: 37
8665 12:18:26.815847
8666 12:18:26.815927 Set Vref, RX VrefLevel [Byte0]: 38
8667 12:18:26.819142 [Byte1]: 38
8668 12:18:26.823568
8669 12:18:26.823649 Set Vref, RX VrefLevel [Byte0]: 39
8670 12:18:26.826941 [Byte1]: 39
8671 12:18:26.830917
8672 12:18:26.830998 Set Vref, RX VrefLevel [Byte0]: 40
8673 12:18:26.834485 [Byte1]: 40
8674 12:18:26.838598
8675 12:18:26.838729 Set Vref, RX VrefLevel [Byte0]: 41
8676 12:18:26.842352 [Byte1]: 41
8677 12:18:26.846404
8678 12:18:26.846484 Set Vref, RX VrefLevel [Byte0]: 42
8679 12:18:26.849937 [Byte1]: 42
8680 12:18:26.854161
8681 12:18:26.854241 Set Vref, RX VrefLevel [Byte0]: 43
8682 12:18:26.857675 [Byte1]: 43
8683 12:18:26.861645
8684 12:18:26.861726 Set Vref, RX VrefLevel [Byte0]: 44
8685 12:18:26.865175 [Byte1]: 44
8686 12:18:26.868975
8687 12:18:26.869068 Set Vref, RX VrefLevel [Byte0]: 45
8688 12:18:26.872444 [Byte1]: 45
8689 12:18:26.876609
8690 12:18:26.876723 Set Vref, RX VrefLevel [Byte0]: 46
8691 12:18:26.879890 [Byte1]: 46
8692 12:18:26.884781
8693 12:18:26.884864 Set Vref, RX VrefLevel [Byte0]: 47
8694 12:18:26.887737 [Byte1]: 47
8695 12:18:26.892056
8696 12:18:26.892168 Set Vref, RX VrefLevel [Byte0]: 48
8697 12:18:26.895184 [Byte1]: 48
8698 12:18:26.899816
8699 12:18:26.899907 Set Vref, RX VrefLevel [Byte0]: 49
8700 12:18:26.902897 [Byte1]: 49
8701 12:18:26.907629
8702 12:18:26.907716 Set Vref, RX VrefLevel [Byte0]: 50
8703 12:18:26.910608 [Byte1]: 50
8704 12:18:26.914839
8705 12:18:26.914916 Set Vref, RX VrefLevel [Byte0]: 51
8706 12:18:26.918526 [Byte1]: 51
8707 12:18:26.922588
8708 12:18:26.922700 Set Vref, RX VrefLevel [Byte0]: 52
8709 12:18:26.925874 [Byte1]: 52
8710 12:18:26.930130
8711 12:18:26.930323 Set Vref, RX VrefLevel [Byte0]: 53
8712 12:18:26.933272 [Byte1]: 53
8713 12:18:26.937688
8714 12:18:26.937801 Set Vref, RX VrefLevel [Byte0]: 54
8715 12:18:26.941026 [Byte1]: 54
8716 12:18:26.945214
8717 12:18:26.945330 Set Vref, RX VrefLevel [Byte0]: 55
8718 12:18:26.951981 [Byte1]: 55
8719 12:18:26.952059
8720 12:18:26.955352 Set Vref, RX VrefLevel [Byte0]: 56
8721 12:18:26.958421 [Byte1]: 56
8722 12:18:26.958540
8723 12:18:26.961813 Set Vref, RX VrefLevel [Byte0]: 57
8724 12:18:26.965482 [Byte1]: 57
8725 12:18:26.965595
8726 12:18:26.968859 Set Vref, RX VrefLevel [Byte0]: 58
8727 12:18:26.972303 [Byte1]: 58
8728 12:18:26.975747
8729 12:18:26.975832 Set Vref, RX VrefLevel [Byte0]: 59
8730 12:18:26.979039 [Byte1]: 59
8731 12:18:26.983549
8732 12:18:26.983639 Set Vref, RX VrefLevel [Byte0]: 60
8733 12:18:26.987097 [Byte1]: 60
8734 12:18:26.991081
8735 12:18:26.991156 Set Vref, RX VrefLevel [Byte0]: 61
8736 12:18:26.994252 [Byte1]: 61
8737 12:18:26.998497
8738 12:18:26.998582 Set Vref, RX VrefLevel [Byte0]: 62
8739 12:18:27.001873 [Byte1]: 62
8740 12:18:27.006190
8741 12:18:27.006271 Set Vref, RX VrefLevel [Byte0]: 63
8742 12:18:27.009763 [Byte1]: 63
8743 12:18:27.014004
8744 12:18:27.014080 Set Vref, RX VrefLevel [Byte0]: 64
8745 12:18:27.017354 [Byte1]: 64
8746 12:18:27.021554
8747 12:18:27.021627 Set Vref, RX VrefLevel [Byte0]: 65
8748 12:18:27.025051 [Byte1]: 65
8749 12:18:27.028969
8750 12:18:27.029049 Set Vref, RX VrefLevel [Byte0]: 66
8751 12:18:27.032676 [Byte1]: 66
8752 12:18:27.036652
8753 12:18:27.036763 Set Vref, RX VrefLevel [Byte0]: 67
8754 12:18:27.039806 [Byte1]: 67
8755 12:18:27.044236
8756 12:18:27.044342 Set Vref, RX VrefLevel [Byte0]: 68
8757 12:18:27.047850 [Byte1]: 68
8758 12:18:27.052215
8759 12:18:27.052290 Set Vref, RX VrefLevel [Byte0]: 69
8760 12:18:27.054925 [Byte1]: 69
8761 12:18:27.059392
8762 12:18:27.059460 Set Vref, RX VrefLevel [Byte0]: 70
8763 12:18:27.063064 [Byte1]: 70
8764 12:18:27.067195
8765 12:18:27.067264 Set Vref, RX VrefLevel [Byte0]: 71
8766 12:18:27.070564 [Byte1]: 71
8767 12:18:27.074665
8768 12:18:27.074797 Set Vref, RX VrefLevel [Byte0]: 72
8769 12:18:27.077996 [Byte1]: 72
8770 12:18:27.082318
8771 12:18:27.082400 Set Vref, RX VrefLevel [Byte0]: 73
8772 12:18:27.085703 [Byte1]: 73
8773 12:18:27.089713
8774 12:18:27.089815 Set Vref, RX VrefLevel [Byte0]: 74
8775 12:18:27.093686 [Byte1]: 74
8776 12:18:27.097407
8777 12:18:27.097483 Set Vref, RX VrefLevel [Byte0]: 75
8778 12:18:27.100637 [Byte1]: 75
8779 12:18:27.104884
8780 12:18:27.104957 Final RX Vref Byte 0 = 57 to rank0
8781 12:18:27.108880 Final RX Vref Byte 1 = 55 to rank0
8782 12:18:27.111694 Final RX Vref Byte 0 = 57 to rank1
8783 12:18:27.115586 Final RX Vref Byte 1 = 55 to rank1==
8784 12:18:27.118392 Dram Type= 6, Freq= 0, CH_1, rank 0
8785 12:18:27.125241 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 12:18:27.125319 ==
8787 12:18:27.125419 DQS Delay:
8788 12:18:27.125478 DQS0 = 0, DQS1 = 0
8789 12:18:27.128174 DQM Delay:
8790 12:18:27.128251 DQM0 = 131, DQM1 = 124
8791 12:18:27.131878 DQ Delay:
8792 12:18:27.135576 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8793 12:18:27.138667 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8794 12:18:27.141699 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8795 12:18:27.145222 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8796 12:18:27.145332
8797 12:18:27.145425
8798 12:18:27.145512
8799 12:18:27.148618 [DramC_TX_OE_Calibration] TA2
8800 12:18:27.151703 Original DQ_B0 (3 6) =30, OEN = 27
8801 12:18:27.155312 Original DQ_B1 (3 6) =30, OEN = 27
8802 12:18:27.158326 24, 0x0, End_B0=24 End_B1=24
8803 12:18:27.158426 25, 0x0, End_B0=25 End_B1=25
8804 12:18:27.161941 26, 0x0, End_B0=26 End_B1=26
8805 12:18:27.165401 27, 0x0, End_B0=27 End_B1=27
8806 12:18:27.168419 28, 0x0, End_B0=28 End_B1=28
8807 12:18:27.168489 29, 0x0, End_B0=29 End_B1=29
8808 12:18:27.172175 30, 0x0, End_B0=30 End_B1=30
8809 12:18:27.175547 31, 0x4141, End_B0=30 End_B1=30
8810 12:18:27.178944 Byte0 end_step=30 best_step=27
8811 12:18:27.181768 Byte1 end_step=30 best_step=27
8812 12:18:27.185472 Byte0 TX OE(2T, 0.5T) = (3, 3)
8813 12:18:27.185540 Byte1 TX OE(2T, 0.5T) = (3, 3)
8814 12:18:27.185600
8815 12:18:27.185656
8816 12:18:27.195467 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fd, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8817 12:18:27.198474 CH1 RK0: MR19=302, MR18=13FD
8818 12:18:27.205335 CH1_RK0: MR19=0x302, MR18=0x13FD, DQSOSC=400, MR23=63, INC=23, DEC=15
8819 12:18:27.205416
8820 12:18:27.208806 ----->DramcWriteLeveling(PI) begin...
8821 12:18:27.208887 ==
8822 12:18:27.212068 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 12:18:27.215365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 12:18:27.215461 ==
8825 12:18:27.218877 Write leveling (Byte 0): 25 => 25
8826 12:18:27.222298 Write leveling (Byte 1): 27 => 27
8827 12:18:27.225398 DramcWriteLeveling(PI) end<-----
8828 12:18:27.225479
8829 12:18:27.225577 ==
8830 12:18:27.228798 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 12:18:27.231878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 12:18:27.232014 ==
8833 12:18:27.235349 [Gating] SW mode calibration
8834 12:18:27.242590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8835 12:18:27.249191 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8836 12:18:27.252363 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 12:18:27.255852 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 12:18:27.258659 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
8839 12:18:27.265703 1 4 12 | B1->B0 | 2424 3434 | 0 1 | (1 1) (1 1)
8840 12:18:27.268788 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 12:18:27.272140 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 12:18:27.278850 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 12:18:27.282709 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 12:18:27.285581 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 12:18:27.292478 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8846 12:18:27.295566 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
8847 12:18:27.299015 1 5 12 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
8848 12:18:27.305528 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 12:18:27.308993 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 12:18:27.312398 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 12:18:27.319290 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 12:18:27.322553 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 12:18:27.326004 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8854 12:18:27.329659 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
8855 12:18:27.336177 1 6 12 | B1->B0 | 3030 4444 | 1 0 | (0 0) (0 0)
8856 12:18:27.339523 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 12:18:27.342849 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 12:18:27.349709 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 12:18:27.352550 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 12:18:27.356333 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 12:18:27.362591 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 12:18:27.366208 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8863 12:18:27.369493 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8864 12:18:27.376046 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8865 12:18:27.379616 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8866 12:18:27.383075 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 12:18:27.386650 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 12:18:27.392908 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 12:18:27.396631 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 12:18:27.399878 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 12:18:27.406265 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 12:18:27.409683 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 12:18:27.413095 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 12:18:27.419814 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 12:18:27.422859 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 12:18:27.426299 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 12:18:27.433284 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8878 12:18:27.436725 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8879 12:18:27.440125 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8880 12:18:27.443456 Total UI for P1: 0, mck2ui 16
8881 12:18:27.446557 best dqsien dly found for B0: ( 1, 9, 6)
8882 12:18:27.449885 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 12:18:27.453017 Total UI for P1: 0, mck2ui 16
8884 12:18:27.456616 best dqsien dly found for B1: ( 1, 9, 12)
8885 12:18:27.459780 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8886 12:18:27.463495 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8887 12:18:27.466508
8888 12:18:27.470103 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8889 12:18:27.473219 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8890 12:18:27.476693 [Gating] SW calibration Done
8891 12:18:27.476774 ==
8892 12:18:27.479976 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 12:18:27.483549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 12:18:27.483643 ==
8895 12:18:27.483707 RX Vref Scan: 0
8896 12:18:27.483775
8897 12:18:27.487033 RX Vref 0 -> 0, step: 1
8898 12:18:27.487123
8899 12:18:27.490404 RX Delay 0 -> 252, step: 8
8900 12:18:27.493681 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8901 12:18:27.497210 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8902 12:18:27.499962 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8903 12:18:27.506852 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8904 12:18:27.510308 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8905 12:18:27.513592 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8906 12:18:27.517095 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8907 12:18:27.520504 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8908 12:18:27.526723 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8909 12:18:27.529908 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8910 12:18:27.533942 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8911 12:18:27.537179 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8912 12:18:27.540182 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8913 12:18:27.546664 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8914 12:18:27.550479 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8915 12:18:27.553833 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8916 12:18:27.553908 ==
8917 12:18:27.557031 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 12:18:27.560369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 12:18:27.560449 ==
8920 12:18:27.563740 DQS Delay:
8921 12:18:27.563821 DQS0 = 0, DQS1 = 0
8922 12:18:27.567106 DQM Delay:
8923 12:18:27.567181 DQM0 = 131, DQM1 = 128
8924 12:18:27.570367 DQ Delay:
8925 12:18:27.573820 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8926 12:18:27.577029 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8927 12:18:27.580451 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8928 12:18:27.583448 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8929 12:18:27.583521
8930 12:18:27.583583
8931 12:18:27.583652 ==
8932 12:18:27.587143 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 12:18:27.590046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 12:18:27.590133 ==
8935 12:18:27.590207
8936 12:18:27.590278
8937 12:18:27.594111 TX Vref Scan disable
8938 12:18:27.596665 == TX Byte 0 ==
8939 12:18:27.600069 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8940 12:18:27.603373 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8941 12:18:27.606912 == TX Byte 1 ==
8942 12:18:27.610121 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8943 12:18:27.613511 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8944 12:18:27.613595 ==
8945 12:18:27.617483 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 12:18:27.620338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 12:18:27.623618 ==
8948 12:18:27.635539
8949 12:18:27.639170 TX Vref early break, caculate TX vref
8950 12:18:27.642018 TX Vref=16, minBit 8, minWin=21, winSum=377
8951 12:18:27.645712 TX Vref=18, minBit 8, minWin=23, winSum=389
8952 12:18:27.649000 TX Vref=20, minBit 8, minWin=24, winSum=395
8953 12:18:27.652396 TX Vref=22, minBit 13, minWin=24, winSum=406
8954 12:18:27.655608 TX Vref=24, minBit 0, minWin=25, winSum=417
8955 12:18:27.662536 TX Vref=26, minBit 9, minWin=25, winSum=419
8956 12:18:27.665612 TX Vref=28, minBit 0, minWin=26, winSum=430
8957 12:18:27.668920 TX Vref=30, minBit 13, minWin=25, winSum=428
8958 12:18:27.672166 TX Vref=32, minBit 0, minWin=25, winSum=413
8959 12:18:27.676129 TX Vref=34, minBit 0, minWin=24, winSum=408
8960 12:18:27.678957 TX Vref=36, minBit 0, minWin=23, winSum=395
8961 12:18:27.685831 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8962 12:18:27.685934
8963 12:18:27.688913 Final TX Range 0 Vref 28
8964 12:18:27.689021
8965 12:18:27.689131 ==
8966 12:18:27.692335 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 12:18:27.695861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 12:18:27.695984 ==
8969 12:18:27.696095
8970 12:18:27.696204
8971 12:18:27.699142 TX Vref Scan disable
8972 12:18:27.705491 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8973 12:18:27.705646 == TX Byte 0 ==
8974 12:18:27.708987 u2DelayCellOfst[0]=14 cells (4 PI)
8975 12:18:27.712473 u2DelayCellOfst[1]=10 cells (3 PI)
8976 12:18:27.715814 u2DelayCellOfst[2]=0 cells (0 PI)
8977 12:18:27.719290 u2DelayCellOfst[3]=7 cells (2 PI)
8978 12:18:27.722672 u2DelayCellOfst[4]=10 cells (3 PI)
8979 12:18:27.725523 u2DelayCellOfst[5]=17 cells (5 PI)
8980 12:18:27.728923 u2DelayCellOfst[6]=17 cells (5 PI)
8981 12:18:27.732645 u2DelayCellOfst[7]=7 cells (2 PI)
8982 12:18:27.736122 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8983 12:18:27.738996 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8984 12:18:27.742377 == TX Byte 1 ==
8985 12:18:27.742462 u2DelayCellOfst[8]=0 cells (0 PI)
8986 12:18:27.745936 u2DelayCellOfst[9]=3 cells (1 PI)
8987 12:18:27.749160 u2DelayCellOfst[10]=10 cells (3 PI)
8988 12:18:27.752215 u2DelayCellOfst[11]=3 cells (1 PI)
8989 12:18:27.755573 u2DelayCellOfst[12]=14 cells (4 PI)
8990 12:18:27.759004 u2DelayCellOfst[13]=14 cells (4 PI)
8991 12:18:27.762590 u2DelayCellOfst[14]=17 cells (5 PI)
8992 12:18:27.765812 u2DelayCellOfst[15]=14 cells (4 PI)
8993 12:18:27.769373 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8994 12:18:27.775708 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8995 12:18:27.775790 DramC Write-DBI on
8996 12:18:27.775891 ==
8997 12:18:27.779119 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 12:18:27.782482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 12:18:27.782564 ==
9000 12:18:27.786063
9001 12:18:27.786143
9002 12:18:27.786206 TX Vref Scan disable
9003 12:18:27.789130 == TX Byte 0 ==
9004 12:18:27.792463 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9005 12:18:27.795890 == TX Byte 1 ==
9006 12:18:27.799444 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9007 12:18:27.799526 DramC Write-DBI off
9008 12:18:27.799593
9009 12:18:27.802248 [DATLAT]
9010 12:18:27.802329 Freq=1600, CH1 RK1
9011 12:18:27.802393
9012 12:18:27.805795 DATLAT Default: 0xf
9013 12:18:27.805876 0, 0xFFFF, sum = 0
9014 12:18:27.809628 1, 0xFFFF, sum = 0
9015 12:18:27.809750 2, 0xFFFF, sum = 0
9016 12:18:27.812634 3, 0xFFFF, sum = 0
9017 12:18:27.812743 4, 0xFFFF, sum = 0
9018 12:18:27.815989 5, 0xFFFF, sum = 0
9019 12:18:27.816095 6, 0xFFFF, sum = 0
9020 12:18:27.819214 7, 0xFFFF, sum = 0
9021 12:18:27.819317 8, 0xFFFF, sum = 0
9022 12:18:27.822538 9, 0xFFFF, sum = 0
9023 12:18:27.825781 10, 0xFFFF, sum = 0
9024 12:18:27.825882 11, 0xFFFF, sum = 0
9025 12:18:27.829268 12, 0xFFFF, sum = 0
9026 12:18:27.829370 13, 0xFFFF, sum = 0
9027 12:18:27.832956 14, 0x0, sum = 1
9028 12:18:27.833060 15, 0x0, sum = 2
9029 12:18:27.836435 16, 0x0, sum = 3
9030 12:18:27.836539 17, 0x0, sum = 4
9031 12:18:27.836631 best_step = 15
9032 12:18:27.836731
9033 12:18:27.839400 ==
9034 12:18:27.842856 Dram Type= 6, Freq= 0, CH_1, rank 1
9035 12:18:27.846480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9036 12:18:27.846588 ==
9037 12:18:27.846682 RX Vref Scan: 0
9038 12:18:27.846799
9039 12:18:27.849487 RX Vref 0 -> 0, step: 1
9040 12:18:27.849585
9041 12:18:27.852765 RX Delay 11 -> 252, step: 4
9042 12:18:27.856215 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9043 12:18:27.859206 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9044 12:18:27.865808 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9045 12:18:27.869462 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9046 12:18:27.872699 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
9047 12:18:27.875716 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9048 12:18:27.879536 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9049 12:18:27.885916 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9050 12:18:27.889039 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9051 12:18:27.892405 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9052 12:18:27.895899 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9053 12:18:27.899345 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
9054 12:18:27.906084 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9055 12:18:27.909197 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9056 12:18:27.912493 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9057 12:18:27.916169 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9058 12:18:27.916251 ==
9059 12:18:27.919574 Dram Type= 6, Freq= 0, CH_1, rank 1
9060 12:18:27.926339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9061 12:18:27.926423 ==
9062 12:18:27.926487 DQS Delay:
9063 12:18:27.926546 DQS0 = 0, DQS1 = 0
9064 12:18:27.929592 DQM Delay:
9065 12:18:27.929674 DQM0 = 129, DQM1 = 126
9066 12:18:27.932751 DQ Delay:
9067 12:18:27.935838 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9068 12:18:27.939951 DQ4 =130, DQ5 =144, DQ6 =138, DQ7 =124
9069 12:18:27.942594 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =116
9070 12:18:27.946104 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9071 12:18:27.946180
9072 12:18:27.946243
9073 12:18:27.946323
9074 12:18:27.949725 [DramC_TX_OE_Calibration] TA2
9075 12:18:27.952745 Original DQ_B0 (3 6) =30, OEN = 27
9076 12:18:27.956493 Original DQ_B1 (3 6) =30, OEN = 27
9077 12:18:27.956588 24, 0x0, End_B0=24 End_B1=24
9078 12:18:27.959932 25, 0x0, End_B0=25 End_B1=25
9079 12:18:27.962796 26, 0x0, End_B0=26 End_B1=26
9080 12:18:27.966017 27, 0x0, End_B0=27 End_B1=27
9081 12:18:27.970042 28, 0x0, End_B0=28 End_B1=28
9082 12:18:27.970128 29, 0x0, End_B0=29 End_B1=29
9083 12:18:27.972741 30, 0x0, End_B0=30 End_B1=30
9084 12:18:27.976761 31, 0x5151, End_B0=30 End_B1=30
9085 12:18:27.979678 Byte0 end_step=30 best_step=27
9086 12:18:27.982965 Byte1 end_step=30 best_step=27
9087 12:18:27.983044 Byte0 TX OE(2T, 0.5T) = (3, 3)
9088 12:18:27.986490 Byte1 TX OE(2T, 0.5T) = (3, 3)
9089 12:18:27.986601
9090 12:18:27.986702
9091 12:18:27.996373 [DQSOSCAuto] RK1, (LSB)MR18= 0xe14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9092 12:18:28.000095 CH1 RK1: MR19=303, MR18=E14
9093 12:18:28.002896 CH1_RK1: MR19=0x303, MR18=0xE14, DQSOSC=399, MR23=63, INC=23, DEC=15
9094 12:18:28.006367 [RxdqsGatingPostProcess] freq 1600
9095 12:18:28.013096 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9096 12:18:28.016497 best DQS0 dly(2T, 0.5T) = (1, 1)
9097 12:18:28.020133 best DQS1 dly(2T, 0.5T) = (1, 1)
9098 12:18:28.023420 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9099 12:18:28.026557 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9100 12:18:28.029682 best DQS0 dly(2T, 0.5T) = (1, 1)
9101 12:18:28.029764 best DQS1 dly(2T, 0.5T) = (1, 1)
9102 12:18:28.032943 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9103 12:18:28.036541 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9104 12:18:28.039872 Pre-setting of DQS Precalculation
9105 12:18:28.046314 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9106 12:18:28.053343 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9107 12:18:28.059814 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9108 12:18:28.059919
9109 12:18:28.060012
9110 12:18:28.063286 [Calibration Summary] 3200 Mbps
9111 12:18:28.063392 CH 0, Rank 0
9112 12:18:28.066510 SW Impedance : PASS
9113 12:18:28.070219 DUTY Scan : NO K
9114 12:18:28.070320 ZQ Calibration : PASS
9115 12:18:28.073401 Jitter Meter : NO K
9116 12:18:28.076622 CBT Training : PASS
9117 12:18:28.076728 Write leveling : PASS
9118 12:18:28.080267 RX DQS gating : PASS
9119 12:18:28.080369 RX DQ/DQS(RDDQC) : PASS
9120 12:18:28.083823 TX DQ/DQS : PASS
9121 12:18:28.087114 RX DATLAT : PASS
9122 12:18:28.087213 RX DQ/DQS(Engine): PASS
9123 12:18:28.090362 TX OE : PASS
9124 12:18:28.090471 All Pass.
9125 12:18:28.090563
9126 12:18:28.093498 CH 0, Rank 1
9127 12:18:28.093605 SW Impedance : PASS
9128 12:18:28.096731 DUTY Scan : NO K
9129 12:18:28.100125 ZQ Calibration : PASS
9130 12:18:28.100203 Jitter Meter : NO K
9131 12:18:28.103361 CBT Training : PASS
9132 12:18:28.106857 Write leveling : PASS
9133 12:18:28.106951 RX DQS gating : PASS
9134 12:18:28.110189 RX DQ/DQS(RDDQC) : PASS
9135 12:18:28.113192 TX DQ/DQS : PASS
9136 12:18:28.113320 RX DATLAT : PASS
9137 12:18:28.116789 RX DQ/DQS(Engine): PASS
9138 12:18:28.116902 TX OE : PASS
9139 12:18:28.120132 All Pass.
9140 12:18:28.120233
9141 12:18:28.120325 CH 1, Rank 0
9142 12:18:28.123580 SW Impedance : PASS
9143 12:18:28.123677 DUTY Scan : NO K
9144 12:18:28.127171 ZQ Calibration : PASS
9145 12:18:28.130000 Jitter Meter : NO K
9146 12:18:28.130073 CBT Training : PASS
9147 12:18:28.133314 Write leveling : PASS
9148 12:18:28.137203 RX DQS gating : PASS
9149 12:18:28.137310 RX DQ/DQS(RDDQC) : PASS
9150 12:18:28.140371 TX DQ/DQS : PASS
9151 12:18:28.143519 RX DATLAT : PASS
9152 12:18:28.143620 RX DQ/DQS(Engine): PASS
9153 12:18:28.146866 TX OE : PASS
9154 12:18:28.146948 All Pass.
9155 12:18:28.147012
9156 12:18:28.150421 CH 1, Rank 1
9157 12:18:28.150528 SW Impedance : PASS
9158 12:18:28.153361 DUTY Scan : NO K
9159 12:18:28.156777 ZQ Calibration : PASS
9160 12:18:28.156859 Jitter Meter : NO K
9161 12:18:28.160427 CBT Training : PASS
9162 12:18:28.160508 Write leveling : PASS
9163 12:18:28.163307 RX DQS gating : PASS
9164 12:18:28.166838 RX DQ/DQS(RDDQC) : PASS
9165 12:18:28.166920 TX DQ/DQS : PASS
9166 12:18:28.170073 RX DATLAT : PASS
9167 12:18:28.173647 RX DQ/DQS(Engine): PASS
9168 12:18:28.173759 TX OE : PASS
9169 12:18:28.177398 All Pass.
9170 12:18:28.177499
9171 12:18:28.177596 DramC Write-DBI on
9172 12:18:28.180538 PER_BANK_REFRESH: Hybrid Mode
9173 12:18:28.180647 TX_TRACKING: ON
9174 12:18:28.190145 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9175 12:18:28.200271 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9176 12:18:28.207472 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9177 12:18:28.210218 [FAST_K] Save calibration result to emmc
9178 12:18:28.214123 sync common calibartion params.
9179 12:18:28.214230 sync cbt_mode0:1, 1:1
9180 12:18:28.217131 dram_init: ddr_geometry: 2
9181 12:18:28.220281 dram_init: ddr_geometry: 2
9182 12:18:28.220388 dram_init: ddr_geometry: 2
9183 12:18:28.223948 0:dram_rank_size:100000000
9184 12:18:28.227308 1:dram_rank_size:100000000
9185 12:18:28.230594 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9186 12:18:28.234049 DFS_SHUFFLE_HW_MODE: ON
9187 12:18:28.237278 dramc_set_vcore_voltage set vcore to 725000
9188 12:18:28.240641 Read voltage for 1600, 0
9189 12:18:28.240749 Vio18 = 0
9190 12:18:28.244054 Vcore = 725000
9191 12:18:28.244154 Vdram = 0
9192 12:18:28.244254 Vddq = 0
9193 12:18:28.244343 Vmddr = 0
9194 12:18:28.246971 switch to 3200 Mbps bootup
9195 12:18:28.250336 [DramcRunTimeConfig]
9196 12:18:28.250446 PHYPLL
9197 12:18:28.253867 DPM_CONTROL_AFTERK: ON
9198 12:18:28.253950 PER_BANK_REFRESH: ON
9199 12:18:28.257180 REFRESH_OVERHEAD_REDUCTION: ON
9200 12:18:28.260195 CMD_PICG_NEW_MODE: OFF
9201 12:18:28.260297 XRTWTW_NEW_MODE: ON
9202 12:18:28.263727 XRTRTR_NEW_MODE: ON
9203 12:18:28.263835 TX_TRACKING: ON
9204 12:18:28.267217 RDSEL_TRACKING: OFF
9205 12:18:28.270622 DQS Precalculation for DVFS: ON
9206 12:18:28.270758 RX_TRACKING: OFF
9207 12:18:28.270842 HW_GATING DBG: ON
9208 12:18:28.274093 ZQCS_ENABLE_LP4: ON
9209 12:18:28.277459 RX_PICG_NEW_MODE: ON
9210 12:18:28.277559 TX_PICG_NEW_MODE: ON
9211 12:18:28.280378 ENABLE_RX_DCM_DPHY: ON
9212 12:18:28.283862 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9213 12:18:28.283966 DUMMY_READ_FOR_TRACKING: OFF
9214 12:18:28.287164 !!! SPM_CONTROL_AFTERK: OFF
9215 12:18:28.290371 !!! SPM could not control APHY
9216 12:18:28.293938 IMPEDANCE_TRACKING: ON
9217 12:18:28.294018 TEMP_SENSOR: ON
9218 12:18:28.297249 HW_SAVE_FOR_SR: OFF
9219 12:18:28.300705 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9220 12:18:28.303729 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9221 12:18:28.303911 Read ODT Tracking: ON
9222 12:18:28.307234 Refresh Rate DeBounce: ON
9223 12:18:28.310626 DFS_NO_QUEUE_FLUSH: ON
9224 12:18:28.313882 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9225 12:18:28.313957 ENABLE_DFS_RUNTIME_MRW: OFF
9226 12:18:28.317172 DDR_RESERVE_NEW_MODE: ON
9227 12:18:28.320640 MR_CBT_SWITCH_FREQ: ON
9228 12:18:28.320763 =========================
9229 12:18:28.339910 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9230 12:18:28.343666 dram_init: ddr_geometry: 2
9231 12:18:28.361637 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9232 12:18:28.364950 dram_init: dram init end (result: 0)
9233 12:18:28.372124 DRAM-K: Full calibration passed in 24571 msecs
9234 12:18:28.375077 MRC: failed to locate region type 0.
9235 12:18:28.375180 DRAM rank0 size:0x100000000,
9236 12:18:28.378200 DRAM rank1 size=0x100000000
9237 12:18:28.388500 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9238 12:18:28.394972 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9239 12:18:28.401775 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9240 12:18:28.408815 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9241 12:18:28.412196 DRAM rank0 size:0x100000000,
9242 12:18:28.415333 DRAM rank1 size=0x100000000
9243 12:18:28.415420 CBMEM:
9244 12:18:28.418938 IMD: root @ 0xfffff000 254 entries.
9245 12:18:28.422291 IMD: root @ 0xffffec00 62 entries.
9246 12:18:28.425292 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9247 12:18:28.429048 WARNING: RO_VPD is uninitialized or empty.
9248 12:18:28.432377 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9249 12:18:28.441653 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9250 12:18:28.454612 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9251 12:18:28.466145 BS: romstage times (exec / console): total (unknown) / 24045 ms
9252 12:18:28.466255
9253 12:18:28.466362
9254 12:18:28.476062 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9255 12:18:28.479440 ARM64: Exception handlers installed.
9256 12:18:28.483003 ARM64: Testing exception
9257 12:18:28.485868 ARM64: Done test exception
9258 12:18:28.485970 Enumerating buses...
9259 12:18:28.489150 Show all devs... Before device enumeration.
9260 12:18:28.492720 Root Device: enabled 1
9261 12:18:28.496140 CPU_CLUSTER: 0: enabled 1
9262 12:18:28.496230 CPU: 00: enabled 1
9263 12:18:28.499541 Compare with tree...
9264 12:18:28.499625 Root Device: enabled 1
9265 12:18:28.502519 CPU_CLUSTER: 0: enabled 1
9266 12:18:28.506097 CPU: 00: enabled 1
9267 12:18:28.506172 Root Device scanning...
9268 12:18:28.509417 scan_static_bus for Root Device
9269 12:18:28.512823 CPU_CLUSTER: 0 enabled
9270 12:18:28.516350 scan_static_bus for Root Device done
9271 12:18:28.519147 scan_bus: bus Root Device finished in 8 msecs
9272 12:18:28.519225 done
9273 12:18:28.525902 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9274 12:18:28.529200 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9275 12:18:28.536073 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9276 12:18:28.539121 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9277 12:18:28.542628 Allocating resources...
9278 12:18:28.542736 Reading resources...
9279 12:18:28.549514 Root Device read_resources bus 0 link: 0
9280 12:18:28.549603 DRAM rank0 size:0x100000000,
9281 12:18:28.552521 DRAM rank1 size=0x100000000
9282 12:18:28.556462 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9283 12:18:28.559679 CPU: 00 missing read_resources
9284 12:18:28.562639 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9285 12:18:28.570019 Root Device read_resources bus 0 link: 0 done
9286 12:18:28.570102 Done reading resources.
9287 12:18:28.575928 Show resources in subtree (Root Device)...After reading.
9288 12:18:28.579461 Root Device child on link 0 CPU_CLUSTER: 0
9289 12:18:28.582882 CPU_CLUSTER: 0 child on link 0 CPU: 00
9290 12:18:28.592799 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9291 12:18:28.592882 CPU: 00
9292 12:18:28.596365 Root Device assign_resources, bus 0 link: 0
9293 12:18:28.599234 CPU_CLUSTER: 0 missing set_resources
9294 12:18:28.602619 Root Device assign_resources, bus 0 link: 0 done
9295 12:18:28.606099 Done setting resources.
9296 12:18:28.613165 Show resources in subtree (Root Device)...After assigning values.
9297 12:18:28.615771 Root Device child on link 0 CPU_CLUSTER: 0
9298 12:18:28.619456 CPU_CLUSTER: 0 child on link 0 CPU: 00
9299 12:18:28.629011 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9300 12:18:28.629119 CPU: 00
9301 12:18:28.632604 Done allocating resources.
9302 12:18:28.636086 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9303 12:18:28.639494 Enabling resources...
9304 12:18:28.639571 done.
9305 12:18:28.642900 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9306 12:18:28.646273 Initializing devices...
9307 12:18:28.649682 Root Device init
9308 12:18:28.649785 init hardware done!
9309 12:18:28.653009 0x00000018: ctrlr->caps
9310 12:18:28.653111 52.000 MHz: ctrlr->f_max
9311 12:18:28.656088 0.400 MHz: ctrlr->f_min
9312 12:18:28.659266 0x40ff8080: ctrlr->voltages
9313 12:18:28.659370 sclk: 390625
9314 12:18:28.662668 Bus Width = 1
9315 12:18:28.662770 sclk: 390625
9316 12:18:28.662846 Bus Width = 1
9317 12:18:28.665933 Early init status = 3
9318 12:18:28.669232 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9319 12:18:28.673538 in-header: 03 fc 00 00 01 00 00 00
9320 12:18:28.677050 in-data: 00
9321 12:18:28.680349 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9322 12:18:28.684870 in-header: 03 fd 00 00 00 00 00 00
9323 12:18:28.688267 in-data:
9324 12:18:28.691071 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9325 12:18:28.694733 in-header: 03 fc 00 00 01 00 00 00
9326 12:18:28.698369 in-data: 00
9327 12:18:28.701726 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9328 12:18:28.706311 in-header: 03 fd 00 00 00 00 00 00
9329 12:18:28.709923 in-data:
9330 12:18:28.712752 [SSUSB] Setting up USB HOST controller...
9331 12:18:28.716135 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9332 12:18:28.719589 [SSUSB] phy power-on done.
9333 12:18:28.723026 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9334 12:18:28.730005 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9335 12:18:28.733103 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9336 12:18:28.739656 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9337 12:18:28.746924 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9338 12:18:28.753349 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9339 12:18:28.760296 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9340 12:18:28.763600 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9341 12:18:28.766624 SPM: binary array size = 0x9dc
9342 12:18:28.773667 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9343 12:18:28.780059 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9344 12:18:28.786587 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9345 12:18:28.790076 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9346 12:18:28.793538 configure_display: Starting display init
9347 12:18:28.829655 anx7625_power_on_init: Init interface.
9348 12:18:28.833037 anx7625_disable_pd_protocol: Disabled PD feature.
9349 12:18:28.835975 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9350 12:18:28.864461 anx7625_start_dp_work: Secure OCM version=00
9351 12:18:28.867569 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9352 12:18:28.882259 sp_tx_get_edid_block: EDID Block = 1
9353 12:18:28.984574 Extracted contents:
9354 12:18:28.988144 header: 00 ff ff ff ff ff ff 00
9355 12:18:28.991015 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9356 12:18:28.994374 version: 01 04
9357 12:18:28.997688 basic params: 95 1f 11 78 0a
9358 12:18:29.001273 chroma info: 76 90 94 55 54 90 27 21 50 54
9359 12:18:29.004230 established: 00 00 00
9360 12:18:29.010985 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9361 12:18:29.014659 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9362 12:18:29.020906 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9363 12:18:29.027966 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9364 12:18:29.034632 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9365 12:18:29.038050 extensions: 00
9366 12:18:29.038125 checksum: fb
9367 12:18:29.038189
9368 12:18:29.040817 Manufacturer: IVO Model 57d Serial Number 0
9369 12:18:29.044236 Made week 0 of 2020
9370 12:18:29.044321 EDID version: 1.4
9371 12:18:29.047634 Digital display
9372 12:18:29.051050 6 bits per primary color channel
9373 12:18:29.051125 DisplayPort interface
9374 12:18:29.054465 Maximum image size: 31 cm x 17 cm
9375 12:18:29.057976 Gamma: 220%
9376 12:18:29.058048 Check DPMS levels
9377 12:18:29.060843 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9378 12:18:29.064157 First detailed timing is preferred timing
9379 12:18:29.067834 Established timings supported:
9380 12:18:29.071344 Standard timings supported:
9381 12:18:29.071418 Detailed timings
9382 12:18:29.077824 Hex of detail: 383680a07038204018303c0035ae10000019
9383 12:18:29.081045 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9384 12:18:29.087478 0780 0798 07c8 0820 hborder 0
9385 12:18:29.090793 0438 043b 0447 0458 vborder 0
9386 12:18:29.090866 -hsync -vsync
9387 12:18:29.094594 Did detailed timing
9388 12:18:29.097580 Hex of detail: 000000000000000000000000000000000000
9389 12:18:29.101093 Manufacturer-specified data, tag 0
9390 12:18:29.107945 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9391 12:18:29.108024 ASCII string: InfoVision
9392 12:18:29.114426 Hex of detail: 000000fe00523134304e574635205248200a
9393 12:18:29.114505 ASCII string: R140NWF5 RH
9394 12:18:29.117808 Checksum
9395 12:18:29.117896 Checksum: 0xfb (valid)
9396 12:18:29.124708 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9397 12:18:29.124787 DSI data_rate: 832800000 bps
9398 12:18:29.132166 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9399 12:18:29.135705 anx7625_parse_edid: pixelclock(138800).
9400 12:18:29.139209 hactive(1920), hsync(48), hfp(24), hbp(88)
9401 12:18:29.142606 vactive(1080), vsync(12), vfp(3), vbp(17)
9402 12:18:29.145665 anx7625_dsi_config: config dsi.
9403 12:18:29.152919 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9404 12:18:29.166928 anx7625_dsi_config: success to config DSI
9405 12:18:29.169800 anx7625_dp_start: MIPI phy setup OK.
9406 12:18:29.173461 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9407 12:18:29.176433 mtk_ddp_mode_set invalid vrefresh 60
9408 12:18:29.180306 main_disp_path_setup
9409 12:18:29.180408 ovl_layer_smi_id_en
9410 12:18:29.183107 ovl_layer_smi_id_en
9411 12:18:29.183180 ccorr_config
9412 12:18:29.183240 aal_config
9413 12:18:29.186870 gamma_config
9414 12:18:29.186935 postmask_config
9415 12:18:29.190242 dither_config
9416 12:18:29.193637 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9417 12:18:29.200002 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9418 12:18:29.203600 Root Device init finished in 551 msecs
9419 12:18:29.203764 CPU_CLUSTER: 0 init
9420 12:18:29.213204 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9421 12:18:29.217148 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9422 12:18:29.219989 APU_MBOX 0x190000b0 = 0x10001
9423 12:18:29.223341 APU_MBOX 0x190001b0 = 0x10001
9424 12:18:29.227048 APU_MBOX 0x190005b0 = 0x10001
9425 12:18:29.230174 APU_MBOX 0x190006b0 = 0x10001
9426 12:18:29.233557 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9427 12:18:29.245891 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9428 12:18:29.257844 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9429 12:18:29.264687 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9430 12:18:29.276741 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9431 12:18:29.285592 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9432 12:18:29.288954 CPU_CLUSTER: 0 init finished in 81 msecs
9433 12:18:29.292099 Devices initialized
9434 12:18:29.295564 Show all devs... After init.
9435 12:18:29.295636 Root Device: enabled 1
9436 12:18:29.299002 CPU_CLUSTER: 0: enabled 1
9437 12:18:29.302417 CPU: 00: enabled 1
9438 12:18:29.305589 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9439 12:18:29.308816 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9440 12:18:29.312151 ELOG: NV offset 0x57f000 size 0x1000
9441 12:18:29.318652 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9442 12:18:29.325435 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9443 12:18:29.328962 ELOG: Event(17) added with size 13 at 2023-10-27 12:18:32 UTC
9444 12:18:29.332376 out: cmd=0x121: 03 db 21 01 00 00 00 00
9445 12:18:29.336832 in-header: 03 1d 00 00 2c 00 00 00
9446 12:18:29.350200 in-data: 42 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9447 12:18:29.356865 ELOG: Event(A1) added with size 10 at 2023-10-27 12:18:32 UTC
9448 12:18:29.363136 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9449 12:18:29.370136 ELOG: Event(A0) added with size 9 at 2023-10-27 12:18:32 UTC
9450 12:18:29.373034 elog_add_boot_reason: Logged dev mode boot
9451 12:18:29.376320 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9452 12:18:29.379916 Finalize devices...
9453 12:18:29.379999 Devices finalized
9454 12:18:29.386636 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9455 12:18:29.389697 Writing coreboot table at 0xffe64000
9456 12:18:29.393110 0. 000000000010a000-0000000000113fff: RAMSTAGE
9457 12:18:29.396484 1. 0000000040000000-00000000400fffff: RAM
9458 12:18:29.400001 2. 0000000040100000-000000004032afff: RAMSTAGE
9459 12:18:29.406754 3. 000000004032b000-00000000545fffff: RAM
9460 12:18:29.410096 4. 0000000054600000-000000005465ffff: BL31
9461 12:18:29.413128 5. 0000000054660000-00000000ffe63fff: RAM
9462 12:18:29.416583 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9463 12:18:29.423226 7. 0000000100000000-000000023fffffff: RAM
9464 12:18:29.423338 Passing 5 GPIOs to payload:
9465 12:18:29.430408 NAME | PORT | POLARITY | VALUE
9466 12:18:29.433516 EC in RW | 0x000000aa | low | undefined
9467 12:18:29.439909 EC interrupt | 0x00000005 | low | undefined
9468 12:18:29.443372 TPM interrupt | 0x000000ab | high | undefined
9469 12:18:29.447039 SD card detect | 0x00000011 | high | undefined
9470 12:18:29.453835 speaker enable | 0x00000093 | high | undefined
9471 12:18:29.456883 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9472 12:18:29.459910 in-header: 03 f9 00 00 02 00 00 00
9473 12:18:29.459991 in-data: 02 00
9474 12:18:29.463368 ADC[4]: Raw value=899483 ID=7
9475 12:18:29.466561 ADC[3]: Raw value=213336 ID=1
9476 12:18:29.466663 RAM Code: 0x71
9477 12:18:29.470009 ADC[6]: Raw value=74557 ID=0
9478 12:18:29.473267 ADC[5]: Raw value=212229 ID=1
9479 12:18:29.473364 SKU Code: 0x1
9480 12:18:29.479903 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b065
9481 12:18:29.483263 coreboot table: 964 bytes.
9482 12:18:29.486536 IMD ROOT 0. 0xfffff000 0x00001000
9483 12:18:29.490020 IMD SMALL 1. 0xffffe000 0x00001000
9484 12:18:29.493525 RO MCACHE 2. 0xffffc000 0x00001104
9485 12:18:29.497084 CONSOLE 3. 0xfff7c000 0x00080000
9486 12:18:29.500145 FMAP 4. 0xfff7b000 0x00000452
9487 12:18:29.503705 TIME STAMP 5. 0xfff7a000 0x00000910
9488 12:18:29.506564 VBOOT WORK 6. 0xfff66000 0x00014000
9489 12:18:29.509985 RAMOOPS 7. 0xffe66000 0x00100000
9490 12:18:29.513533 COREBOOT 8. 0xffe64000 0x00002000
9491 12:18:29.513638 IMD small region:
9492 12:18:29.517024 IMD ROOT 0. 0xffffec00 0x00000400
9493 12:18:29.520029 VPD 1. 0xffffeb80 0x0000006c
9494 12:18:29.523615 MMC STATUS 2. 0xffffeb60 0x00000004
9495 12:18:29.530224 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9496 12:18:29.530305 Probing TPM: done!
9497 12:18:29.536770 Connected to device vid:did:rid of 1ae0:0028:00
9498 12:18:29.543362 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9499 12:18:29.547267 Initialized TPM device CR50 revision 0
9500 12:18:29.550716 Checking cr50 for pending updates
9501 12:18:29.556357 Reading cr50 TPM mode
9502 12:18:29.565154 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9503 12:18:29.571623 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9504 12:18:29.611498 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9505 12:18:29.614926 Checking segment from ROM address 0x40100000
9506 12:18:29.618308 Checking segment from ROM address 0x4010001c
9507 12:18:29.625229 Loading segment from ROM address 0x40100000
9508 12:18:29.625311 code (compression=0)
9509 12:18:29.631634 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9510 12:18:29.641672 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9511 12:18:29.641756 it's not compressed!
9512 12:18:29.648727 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9513 12:18:29.652227 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9514 12:18:29.672011 Loading segment from ROM address 0x4010001c
9515 12:18:29.672119 Entry Point 0x80000000
9516 12:18:29.675846 Loaded segments
9517 12:18:29.678862 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9518 12:18:29.685296 Jumping to boot code at 0x80000000(0xffe64000)
9519 12:18:29.692371 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9520 12:18:29.698855 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9521 12:18:29.706413 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9522 12:18:29.710182 Checking segment from ROM address 0x40100000
9523 12:18:29.713136 Checking segment from ROM address 0x4010001c
9524 12:18:29.719630 Loading segment from ROM address 0x40100000
9525 12:18:29.719712 code (compression=1)
9526 12:18:29.726368 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9527 12:18:29.736418 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9528 12:18:29.736500 using LZMA
9529 12:18:29.745071 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9530 12:18:29.751515 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9531 12:18:29.755085 Loading segment from ROM address 0x4010001c
9532 12:18:29.755167 Entry Point 0x54601000
9533 12:18:29.758440 Loaded segments
9534 12:18:29.761798 NOTICE: MT8192 bl31_setup
9535 12:18:29.768434 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9536 12:18:29.771712 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9537 12:18:29.775078 WARNING: region 0:
9538 12:18:29.778531 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 12:18:29.778613 WARNING: region 1:
9540 12:18:29.785113 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9541 12:18:29.788392 WARNING: region 2:
9542 12:18:29.791682 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9543 12:18:29.795068 WARNING: region 3:
9544 12:18:29.798990 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9545 12:18:29.802139 WARNING: region 4:
9546 12:18:29.805260 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9547 12:18:29.808667 WARNING: region 5:
9548 12:18:29.812069 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 12:18:29.815551 WARNING: region 6:
9550 12:18:29.818577 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9551 12:18:29.818685 WARNING: region 7:
9552 12:18:29.825665 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9553 12:18:29.832146 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9554 12:18:29.835641 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9555 12:18:29.838943 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9556 12:18:29.842120 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9557 12:18:29.849019 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9558 12:18:29.852657 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9559 12:18:29.859072 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9560 12:18:29.862418 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9561 12:18:29.865792 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9562 12:18:29.872626 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9563 12:18:29.876418 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9564 12:18:29.879781 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9565 12:18:29.886609 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9566 12:18:29.889940 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9567 12:18:29.893062 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9568 12:18:29.899453 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9569 12:18:29.903516 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9570 12:18:29.906117 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9571 12:18:29.913268 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9572 12:18:29.916704 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9573 12:18:29.923029 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9574 12:18:29.926253 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9575 12:18:29.929707 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9576 12:18:29.936639 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9577 12:18:29.939953 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9578 12:18:29.943419 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9579 12:18:29.950315 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9580 12:18:29.953317 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9581 12:18:29.960201 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9582 12:18:29.963496 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9583 12:18:29.966690 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9584 12:18:29.973523 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9585 12:18:29.977059 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9586 12:18:29.980481 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9587 12:18:29.984053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9588 12:18:29.990335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9589 12:18:29.993822 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9590 12:18:29.996953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9591 12:18:30.000587 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9592 12:18:30.007267 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9593 12:18:30.010905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9594 12:18:30.014040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9595 12:18:30.017395 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9596 12:18:30.023831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9597 12:18:30.027613 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9598 12:18:30.030632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9599 12:18:30.034020 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9600 12:18:30.040679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9601 12:18:30.044318 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9602 12:18:30.047648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9603 12:18:30.054146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9604 12:18:30.057494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9605 12:18:30.064498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9606 12:18:30.068067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9607 12:18:30.071480 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9608 12:18:30.078051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9609 12:18:30.081273 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9610 12:18:30.087979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9611 12:18:30.091105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9612 12:18:30.098058 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9613 12:18:30.101886 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9614 12:18:30.104575 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9615 12:18:30.111690 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9616 12:18:30.115245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9617 12:18:30.121498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9618 12:18:30.125197 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9619 12:18:30.128079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9620 12:18:30.134899 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9621 12:18:30.138421 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9622 12:18:30.144870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9623 12:18:30.148646 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9624 12:18:30.154980 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9625 12:18:30.158586 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9626 12:18:30.161827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9627 12:18:30.168350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9628 12:18:30.171923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9629 12:18:30.179071 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9630 12:18:30.181841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9631 12:18:30.188675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9632 12:18:30.192048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9633 12:18:30.195727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9634 12:18:30.201774 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9635 12:18:30.205399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9636 12:18:30.212030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9637 12:18:30.215434 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9638 12:18:30.219098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9639 12:18:30.225708 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9640 12:18:30.228796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9641 12:18:30.235476 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9642 12:18:30.238674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9643 12:18:30.245887 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9644 12:18:30.248740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9645 12:18:30.252377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9646 12:18:30.258934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9647 12:18:30.262341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9648 12:18:30.269302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9649 12:18:30.272808 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9650 12:18:30.275810 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9651 12:18:30.279200 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9652 12:18:30.285612 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9653 12:18:30.288940 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9654 12:18:30.292481 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9655 12:18:30.299120 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9656 12:18:30.302599 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9657 12:18:30.309435 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9658 12:18:30.312823 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9659 12:18:30.316349 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9660 12:18:30.322641 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9661 12:18:30.326082 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9662 12:18:30.332975 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9663 12:18:30.336660 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9664 12:18:30.339819 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9665 12:18:30.346761 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9666 12:18:30.349588 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9667 12:18:30.353069 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9668 12:18:30.359800 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9669 12:18:30.363672 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9670 12:18:30.366827 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9671 12:18:30.373047 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9672 12:18:30.376518 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9673 12:18:30.380043 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9674 12:18:30.383492 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9675 12:18:30.387024 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9676 12:18:30.393336 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9677 12:18:30.396705 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9678 12:18:30.403434 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9679 12:18:30.406933 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9680 12:18:30.410422 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9681 12:18:30.416635 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9682 12:18:30.419994 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9683 12:18:30.423362 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9684 12:18:30.430218 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9685 12:18:30.433786 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9686 12:18:30.440356 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9687 12:18:30.443394 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9688 12:18:30.446986 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9689 12:18:30.453792 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9690 12:18:30.457015 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9691 12:18:30.460433 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9692 12:18:30.467298 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9693 12:18:30.470531 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9694 12:18:30.477157 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9695 12:18:30.480395 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9696 12:18:30.484153 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9697 12:18:30.490499 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9698 12:18:30.493942 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9699 12:18:30.497548 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9700 12:18:30.503780 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9701 12:18:30.507379 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9702 12:18:30.514190 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9703 12:18:30.517821 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9704 12:18:30.520519 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9705 12:18:30.527866 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9706 12:18:30.531323 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9707 12:18:30.534039 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9708 12:18:30.541063 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9709 12:18:30.544322 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9710 12:18:30.550864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9711 12:18:30.554547 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9712 12:18:30.557603 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9713 12:18:30.564351 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9714 12:18:30.568069 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9715 12:18:30.571122 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9716 12:18:30.577629 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9717 12:18:30.581315 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9718 12:18:30.587739 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9719 12:18:30.591298 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9720 12:18:30.594702 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9721 12:18:30.601056 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9722 12:18:30.604696 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9723 12:18:30.610984 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9724 12:18:30.614210 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9725 12:18:30.617630 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9726 12:18:30.624654 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9727 12:18:30.628166 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9728 12:18:30.631252 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9729 12:18:30.637645 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9730 12:18:30.640932 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9731 12:18:30.648032 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9732 12:18:30.651592 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9733 12:18:30.654565 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9734 12:18:30.661532 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9735 12:18:30.664450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9736 12:18:30.671145 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9737 12:18:30.674344 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9738 12:18:30.678077 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9739 12:18:30.684450 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9740 12:18:30.688111 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9741 12:18:30.691210 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9742 12:18:30.697634 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9743 12:18:30.700989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9744 12:18:30.708220 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9745 12:18:30.711071 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9746 12:18:30.717687 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9747 12:18:30.721277 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9748 12:18:30.724386 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9749 12:18:30.731292 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9750 12:18:30.734261 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9751 12:18:30.740889 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9752 12:18:30.744550 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9753 12:18:30.747922 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9754 12:18:30.754253 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9755 12:18:30.757533 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9756 12:18:30.764287 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9757 12:18:30.768089 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9758 12:18:30.770968 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9759 12:18:30.778078 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9760 12:18:30.781236 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9761 12:18:30.788082 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9762 12:18:30.791334 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9763 12:18:30.798072 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9764 12:18:30.801142 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9765 12:18:30.804423 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9766 12:18:30.811561 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9767 12:18:30.814781 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9768 12:18:30.821162 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9769 12:18:30.824646 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9770 12:18:30.827861 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9771 12:18:30.834671 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9772 12:18:30.837774 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9773 12:18:30.844522 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9774 12:18:30.847989 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9775 12:18:30.851579 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9776 12:18:30.858442 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9777 12:18:30.861425 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9778 12:18:30.868070 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9779 12:18:30.871542 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9780 12:18:30.874503 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9781 12:18:30.881358 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9782 12:18:30.884818 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9783 12:18:30.887849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9784 12:18:30.891375 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9785 12:18:30.897954 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9786 12:18:30.901408 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9787 12:18:30.904893 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9788 12:18:30.911959 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9789 12:18:30.915150 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9790 12:18:30.918400 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9791 12:18:30.925040 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9792 12:18:30.928468 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9793 12:18:30.931638 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9794 12:18:30.938642 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9795 12:18:30.941642 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9796 12:18:30.944971 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9797 12:18:30.951855 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9798 12:18:30.955349 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9799 12:18:30.961760 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9800 12:18:30.965064 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9801 12:18:30.968601 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9802 12:18:30.975271 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9803 12:18:30.978754 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9804 12:18:30.981966 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9805 12:18:30.988774 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9806 12:18:30.991795 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9807 12:18:30.995308 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9808 12:18:31.002069 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9809 12:18:31.005580 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9810 12:18:31.008772 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9811 12:18:31.015405 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9812 12:18:31.019016 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9813 12:18:31.022116 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9814 12:18:31.028651 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9815 12:18:31.031834 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9816 12:18:31.035233 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9817 12:18:31.041943 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9818 12:18:31.045432 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9819 12:18:31.052226 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9820 12:18:31.055630 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9821 12:18:31.058650 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9822 12:18:31.065755 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9823 12:18:31.068729 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9824 12:18:31.071943 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9825 12:18:31.075141 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9826 12:18:31.078627 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9827 12:18:31.085493 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9828 12:18:31.088742 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9829 12:18:31.092060 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9830 12:18:31.095162 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9831 12:18:31.102040 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9832 12:18:31.105588 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9833 12:18:31.108787 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9834 12:18:31.112407 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9835 12:18:31.119264 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9836 12:18:31.122019 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9837 12:18:31.129028 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9838 12:18:31.132338 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9839 12:18:31.135515 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9840 12:18:31.142184 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9841 12:18:31.145360 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9842 12:18:31.152049 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9843 12:18:31.155571 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9844 12:18:31.159147 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9845 12:18:31.165998 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9846 12:18:31.169023 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9847 12:18:31.175723 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9848 12:18:31.178980 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9849 12:18:31.185560 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9850 12:18:31.188978 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9851 12:18:31.192244 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9852 12:18:31.198882 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9853 12:18:31.202367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9854 12:18:31.205919 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9855 12:18:31.212670 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9856 12:18:31.215631 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9857 12:18:31.222684 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9858 12:18:31.225647 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9859 12:18:31.229146 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9860 12:18:31.235933 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9861 12:18:31.239041 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9862 12:18:31.245822 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9863 12:18:31.249058 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9864 12:18:31.252597 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9865 12:18:31.259172 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9866 12:18:31.263123 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9867 12:18:31.269052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9868 12:18:31.272951 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9869 12:18:31.275787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9870 12:18:31.282518 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9871 12:18:31.285806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9872 12:18:31.292802 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9873 12:18:31.296153 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9874 12:18:31.299191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9875 12:18:31.305897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9876 12:18:31.309607 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9877 12:18:31.316087 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9878 12:18:31.319650 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9879 12:18:31.323208 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9880 12:18:31.329577 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9881 12:18:31.333233 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9882 12:18:31.339427 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9883 12:18:31.342933 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9884 12:18:31.346331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9885 12:18:31.352768 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9886 12:18:31.356160 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9887 12:18:31.362819 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9888 12:18:31.366826 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9889 12:18:31.369582 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9890 12:18:31.376415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9891 12:18:31.379901 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9892 12:18:31.386991 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9893 12:18:31.389759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9894 12:18:31.393306 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9895 12:18:31.399750 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9896 12:18:31.402963 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9897 12:18:31.409642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9898 12:18:31.412915 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9899 12:18:31.416612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9900 12:18:31.423148 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9901 12:18:31.426153 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9902 12:18:31.433203 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9903 12:18:31.436725 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9904 12:18:31.439529 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9905 12:18:31.446704 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9906 12:18:31.449635 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9907 12:18:31.456288 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9908 12:18:31.459825 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9909 12:18:31.463028 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9910 12:18:31.469754 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9911 12:18:31.472856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9912 12:18:31.479787 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9913 12:18:31.483052 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9914 12:18:31.489533 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9915 12:18:31.493401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9916 12:18:31.496615 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9917 12:18:31.502760 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9918 12:18:31.506259 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9919 12:18:31.512938 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9920 12:18:31.516324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9921 12:18:31.523156 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9922 12:18:31.526603 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9923 12:18:31.529501 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9924 12:18:31.536350 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9925 12:18:31.539938 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9926 12:18:31.546365 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9927 12:18:31.549717 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9928 12:18:31.556266 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9929 12:18:31.559768 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9930 12:18:31.563327 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9931 12:18:31.569803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9932 12:18:31.573889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9933 12:18:31.579644 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9934 12:18:31.582890 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9935 12:18:31.589968 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9936 12:18:31.593391 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9937 12:18:31.596369 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9938 12:18:31.603437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9939 12:18:31.606850 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9940 12:18:31.613158 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9941 12:18:31.616635 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9942 12:18:31.623348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9943 12:18:31.626641 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9944 12:18:31.630255 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9945 12:18:31.636642 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9946 12:18:31.640189 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9947 12:18:31.647005 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9948 12:18:31.649941 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9949 12:18:31.653306 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9950 12:18:31.660415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9951 12:18:31.663246 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9952 12:18:31.670220 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9953 12:18:31.673360 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9954 12:18:31.680319 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9955 12:18:31.683141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9956 12:18:31.686671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9957 12:18:31.693553 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9958 12:18:31.696864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9959 12:18:31.703242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9960 12:18:31.706918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9961 12:18:31.713445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9962 12:18:31.716777 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9963 12:18:31.723493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9964 12:18:31.726598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9965 12:18:31.733478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9966 12:18:31.737027 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9967 12:18:31.740320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9968 12:18:31.747139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9969 12:18:31.750103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9970 12:18:31.756972 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9971 12:18:31.760302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9972 12:18:31.766676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9973 12:18:31.770208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9974 12:18:31.777038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9975 12:18:31.780190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9976 12:18:31.786891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9977 12:18:31.790175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9978 12:18:31.797252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9979 12:18:31.800093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9980 12:18:31.806701 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9981 12:18:31.810327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9982 12:18:31.817167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9983 12:18:31.820809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9984 12:18:31.826995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9985 12:18:31.830478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9986 12:18:31.837248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9987 12:18:31.840713 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9988 12:18:31.843835 INFO: [APUAPC] vio 0
9989 12:18:31.847101 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9990 12:18:31.853701 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9991 12:18:31.853803 INFO: [APUAPC] D0_APC_0: 0x400510
9992 12:18:31.857001 INFO: [APUAPC] D0_APC_1: 0x0
9993 12:18:31.860385 INFO: [APUAPC] D0_APC_2: 0x1540
9994 12:18:31.863320 INFO: [APUAPC] D0_APC_3: 0x0
9995 12:18:31.867418 INFO: [APUAPC] D1_APC_0: 0xffffffff
9996 12:18:31.870195 INFO: [APUAPC] D1_APC_1: 0xffffffff
9997 12:18:31.873666 INFO: [APUAPC] D1_APC_2: 0x3fffff
9998 12:18:31.876830 INFO: [APUAPC] D1_APC_3: 0x0
9999 12:18:31.880210 INFO: [APUAPC] D2_APC_0: 0xffffffff
10000 12:18:31.883657 INFO: [APUAPC] D2_APC_1: 0xffffffff
10001 12:18:31.886970 INFO: [APUAPC] D2_APC_2: 0x3fffff
10002 12:18:31.890238 INFO: [APUAPC] D2_APC_3: 0x0
10003 12:18:31.893700 INFO: [APUAPC] D3_APC_0: 0xffffffff
10004 12:18:31.897432 INFO: [APUAPC] D3_APC_1: 0xffffffff
10005 12:18:31.900208 INFO: [APUAPC] D3_APC_2: 0x3fffff
10006 12:18:31.903497 INFO: [APUAPC] D3_APC_3: 0x0
10007 12:18:31.907029 INFO: [APUAPC] D4_APC_0: 0xffffffff
10008 12:18:31.910397 INFO: [APUAPC] D4_APC_1: 0xffffffff
10009 12:18:31.914062 INFO: [APUAPC] D4_APC_2: 0x3fffff
10010 12:18:31.917598 INFO: [APUAPC] D4_APC_3: 0x0
10011 12:18:31.921042 INFO: [APUAPC] D5_APC_0: 0xffffffff
10012 12:18:31.923702 INFO: [APUAPC] D5_APC_1: 0xffffffff
10013 12:18:31.927067 INFO: [APUAPC] D5_APC_2: 0x3fffff
10014 12:18:31.930614 INFO: [APUAPC] D5_APC_3: 0x0
10015 12:18:31.933890 INFO: [APUAPC] D6_APC_0: 0xffffffff
10016 12:18:31.937102 INFO: [APUAPC] D6_APC_1: 0xffffffff
10017 12:18:31.940528 INFO: [APUAPC] D6_APC_2: 0x3fffff
10018 12:18:31.940603 INFO: [APUAPC] D6_APC_3: 0x0
10019 12:18:31.944060 INFO: [APUAPC] D7_APC_0: 0xffffffff
10020 12:18:31.950481 INFO: [APUAPC] D7_APC_1: 0xffffffff
10021 12:18:31.950563 INFO: [APUAPC] D7_APC_2: 0x3fffff
10022 12:18:31.953804 INFO: [APUAPC] D7_APC_3: 0x0
10023 12:18:31.957078 INFO: [APUAPC] D8_APC_0: 0xffffffff
10024 12:18:31.960372 INFO: [APUAPC] D8_APC_1: 0xffffffff
10025 12:18:31.963813 INFO: [APUAPC] D8_APC_2: 0x3fffff
10026 12:18:31.966984 INFO: [APUAPC] D8_APC_3: 0x0
10027 12:18:31.970292 INFO: [APUAPC] D9_APC_0: 0xffffffff
10028 12:18:31.973937 INFO: [APUAPC] D9_APC_1: 0xffffffff
10029 12:18:31.977459 INFO: [APUAPC] D9_APC_2: 0x3fffff
10030 12:18:31.980972 INFO: [APUAPC] D9_APC_3: 0x0
10031 12:18:31.983864 INFO: [APUAPC] D10_APC_0: 0xffffffff
10032 12:18:31.987414 INFO: [APUAPC] D10_APC_1: 0xffffffff
10033 12:18:31.990905 INFO: [APUAPC] D10_APC_2: 0x3fffff
10034 12:18:31.994243 INFO: [APUAPC] D10_APC_3: 0x0
10035 12:18:31.997246 INFO: [APUAPC] D11_APC_0: 0xffffffff
10036 12:18:32.000593 INFO: [APUAPC] D11_APC_1: 0xffffffff
10037 12:18:32.003860 INFO: [APUAPC] D11_APC_2: 0x3fffff
10038 12:18:32.007394 INFO: [APUAPC] D11_APC_3: 0x0
10039 12:18:32.010691 INFO: [APUAPC] D12_APC_0: 0xffffffff
10040 12:18:32.013718 INFO: [APUAPC] D12_APC_1: 0xffffffff
10041 12:18:32.017072 INFO: [APUAPC] D12_APC_2: 0x3fffff
10042 12:18:32.020776 INFO: [APUAPC] D12_APC_3: 0x0
10043 12:18:32.024109 INFO: [APUAPC] D13_APC_0: 0xffffffff
10044 12:18:32.027115 INFO: [APUAPC] D13_APC_1: 0xffffffff
10045 12:18:32.030966 INFO: [APUAPC] D13_APC_2: 0x3fffff
10046 12:18:32.034240 INFO: [APUAPC] D13_APC_3: 0x0
10047 12:18:32.037309 INFO: [APUAPC] D14_APC_0: 0xffffffff
10048 12:18:32.040981 INFO: [APUAPC] D14_APC_1: 0xffffffff
10049 12:18:32.044108 INFO: [APUAPC] D14_APC_2: 0x3fffff
10050 12:18:32.047525 INFO: [APUAPC] D14_APC_3: 0x0
10051 12:18:32.050647 INFO: [APUAPC] D15_APC_0: 0xffffffff
10052 12:18:32.054025 INFO: [APUAPC] D15_APC_1: 0xffffffff
10053 12:18:32.057592 INFO: [APUAPC] D15_APC_2: 0x3fffff
10054 12:18:32.061024 INFO: [APUAPC] D15_APC_3: 0x0
10055 12:18:32.064031 INFO: [APUAPC] APC_CON: 0x4
10056 12:18:32.067928 INFO: [NOCDAPC] D0_APC_0: 0x0
10057 12:18:32.070668 INFO: [NOCDAPC] D0_APC_1: 0x0
10058 12:18:32.074304 INFO: [NOCDAPC] D1_APC_0: 0x0
10059 12:18:32.077450 INFO: [NOCDAPC] D1_APC_1: 0xfff
10060 12:18:32.077524 INFO: [NOCDAPC] D2_APC_0: 0x0
10061 12:18:32.080756 INFO: [NOCDAPC] D2_APC_1: 0xfff
10062 12:18:32.084337 INFO: [NOCDAPC] D3_APC_0: 0x0
10063 12:18:32.087875 INFO: [NOCDAPC] D3_APC_1: 0xfff
10064 12:18:32.090620 INFO: [NOCDAPC] D4_APC_0: 0x0
10065 12:18:32.094033 INFO: [NOCDAPC] D4_APC_1: 0xfff
10066 12:18:32.097544 INFO: [NOCDAPC] D5_APC_0: 0x0
10067 12:18:32.101125 INFO: [NOCDAPC] D5_APC_1: 0xfff
10068 12:18:32.104574 INFO: [NOCDAPC] D6_APC_0: 0x0
10069 12:18:32.107588 INFO: [NOCDAPC] D6_APC_1: 0xfff
10070 12:18:32.107670 INFO: [NOCDAPC] D7_APC_0: 0x0
10071 12:18:32.110916 INFO: [NOCDAPC] D7_APC_1: 0xfff
10072 12:18:32.114384 INFO: [NOCDAPC] D8_APC_0: 0x0
10073 12:18:32.117741 INFO: [NOCDAPC] D8_APC_1: 0xfff
10074 12:18:32.120713 INFO: [NOCDAPC] D9_APC_0: 0x0
10075 12:18:32.124206 INFO: [NOCDAPC] D9_APC_1: 0xfff
10076 12:18:32.127384 INFO: [NOCDAPC] D10_APC_0: 0x0
10077 12:18:32.130941 INFO: [NOCDAPC] D10_APC_1: 0xfff
10078 12:18:32.134281 INFO: [NOCDAPC] D11_APC_0: 0x0
10079 12:18:32.137608 INFO: [NOCDAPC] D11_APC_1: 0xfff
10080 12:18:32.140801 INFO: [NOCDAPC] D12_APC_0: 0x0
10081 12:18:32.144536 INFO: [NOCDAPC] D12_APC_1: 0xfff
10082 12:18:32.144618 INFO: [NOCDAPC] D13_APC_0: 0x0
10083 12:18:32.147758 INFO: [NOCDAPC] D13_APC_1: 0xfff
10084 12:18:32.150964 INFO: [NOCDAPC] D14_APC_0: 0x0
10085 12:18:32.154555 INFO: [NOCDAPC] D14_APC_1: 0xfff
10086 12:18:32.158079 INFO: [NOCDAPC] D15_APC_0: 0x0
10087 12:18:32.160969 INFO: [NOCDAPC] D15_APC_1: 0xfff
10088 12:18:32.164464 INFO: [NOCDAPC] APC_CON: 0x4
10089 12:18:32.167971 INFO: [APUAPC] set_apusys_apc done
10090 12:18:32.170617 INFO: [DEVAPC] devapc_init done
10091 12:18:32.174411 INFO: GICv3 without legacy support detected.
10092 12:18:32.177630 INFO: ARM GICv3 driver initialized in EL3
10093 12:18:32.184185 INFO: Maximum SPI INTID supported: 639
10094 12:18:32.187734 INFO: BL31: Initializing runtime services
10095 12:18:32.191056 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10096 12:18:32.194263 INFO: SPM: enable CPC mode
10097 12:18:32.200955 INFO: mcdi ready for mcusys-off-idle and system suspend
10098 12:18:32.204268 INFO: BL31: Preparing for EL3 exit to normal world
10099 12:18:32.207876 INFO: Entry point address = 0x80000000
10100 12:18:32.210657 INFO: SPSR = 0x8
10101 12:18:32.216166
10102 12:18:32.216242
10103 12:18:32.216312
10104 12:18:32.219613 Starting depthcharge on Spherion...
10105 12:18:32.219710
10106 12:18:32.219799 Wipe memory regions:
10107 12:18:32.219887
10108 12:18:32.220607 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10109 12:18:32.220710 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10110 12:18:32.220794 Setting prompt string to ['asurada:']
10111 12:18:32.220873 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10112 12:18:32.222660 [0x00000040000000, 0x00000054600000)
10113 12:18:32.345129
10114 12:18:32.345297 [0x00000054660000, 0x00000080000000)
10115 12:18:32.605603
10116 12:18:32.605750 [0x000000821a7280, 0x000000ffe64000)
10117 12:18:33.350454
10118 12:18:33.350606 [0x00000100000000, 0x00000240000000)
10119 12:18:35.240340
10120 12:18:35.243823 Initializing XHCI USB controller at 0x11200000.
10121 12:18:36.281860
10122 12:18:36.285160 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10123 12:18:36.285264
10124 12:18:36.285333
10125 12:18:36.285396
10126 12:18:36.285685 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10128 12:18:36.385997 asurada: tftpboot 192.168.201.1 11893105/tftp-deploy-_84d9rro/kernel/image.itb 11893105/tftp-deploy-_84d9rro/kernel/cmdline
10129 12:18:36.386151 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10130 12:18:36.386237 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10131 12:18:36.390813 tftpboot 192.168.201.1 11893105/tftp-deploy-_84d9rro/kernel/image.ittp-deploy-_84d9rro/kernel/cmdline
10132 12:18:36.390898
10133 12:18:36.390967 Waiting for link
10134 12:18:36.551354
10135 12:18:36.551519 R8152: Initializing
10136 12:18:36.551595
10137 12:18:36.554286 Version 6 (ocp_data = 5c30)
10138 12:18:36.554370
10139 12:18:36.557412 R8152: Done initializing
10140 12:18:36.557483
10141 12:18:36.557546 Adding net device
10142 12:18:38.522992
10143 12:18:38.523140 done.
10144 12:18:38.523212
10145 12:18:38.523274 MAC: 00:24:32:30:78:52
10146 12:18:38.523332
10147 12:18:38.526201 Sending DHCP discover... done.
10148 12:18:38.526286
10149 12:18:48.238364 Waiting for reply... R8152: Bulk read error 0xffffffbf
10150 12:18:48.238516
10151 12:18:48.241725 Receive failed.
10152 12:18:48.241816
10153 12:18:48.241879 done.
10154 12:18:48.241938
10155 12:18:48.244923 Sending DHCP request... done.
10156 12:18:48.245007
10157 12:18:48.248187 Waiting for reply... done.
10158 12:18:48.248270
10159 12:18:48.251502 My ip is 192.168.201.14
10160 12:18:48.251584
10161 12:18:48.254964 The DHCP server ip is 192.168.201.1
10162 12:18:48.255047
10163 12:18:48.258339 TFTP server IP predefined by user: 192.168.201.1
10164 12:18:48.258458
10165 12:18:48.265003 Bootfile predefined by user: 11893105/tftp-deploy-_84d9rro/kernel/image.itb
10166 12:18:48.265113
10167 12:18:48.268587 Sending tftp read request... done.
10168 12:18:48.268675
10169 12:18:48.271966 Waiting for the transfer...
10170 12:18:48.272070
10171 12:18:48.935857 00000000 ################################################################
10172 12:18:48.936006
10173 12:18:49.597327 00080000 ################################################################
10174 12:18:49.597506
10175 12:18:50.247740 00100000 ################################################################
10176 12:18:50.247881
10177 12:18:50.888725 00180000 ################################################################
10178 12:18:50.888879
10179 12:18:51.538645 00200000 ################################################################
10180 12:18:51.538818
10181 12:18:52.184746 00280000 ################################################################
10182 12:18:52.184927
10183 12:18:52.832209 00300000 ################################################################
10184 12:18:52.832344
10185 12:18:53.489149 00380000 ################################################################
10186 12:18:53.489292
10187 12:18:54.128265 00400000 ################################################################
10188 12:18:54.128416
10189 12:18:54.781896 00480000 ################################################################
10190 12:18:54.782078
10191 12:18:55.428349 00500000 ################################################################
10192 12:18:55.428530
10193 12:18:55.994884 00580000 ################################################################
10194 12:18:55.995025
10195 12:18:56.663150 00600000 ################################################################
10196 12:18:56.663300
10197 12:18:57.327591 00680000 ################################################################
10198 12:18:57.327769
10199 12:18:57.986901 00700000 ################################################################
10200 12:18:57.987043
10201 12:18:58.640156 00780000 ################################################################
10202 12:18:58.640306
10203 12:18:59.261655 00800000 ################################################################
10204 12:18:59.261823
10205 12:18:59.853428 00880000 ################################################################
10206 12:18:59.853581
10207 12:19:00.518363 00900000 ################################################################
10208 12:19:00.518510
10209 12:19:01.167426 00980000 ################################################################
10210 12:19:01.167634
10211 12:19:01.823346 00a00000 ################################################################
10212 12:19:01.823530
10213 12:19:02.473852 00a80000 ################################################################
10214 12:19:02.474000
10215 12:19:03.129069 00b00000 ################################################################
10216 12:19:03.129221
10217 12:19:03.780673 00b80000 ################################################################
10218 12:19:03.780866
10219 12:19:04.443385 00c00000 ################################################################
10220 12:19:04.443540
10221 12:19:05.092595 00c80000 ################################################################
10222 12:19:05.092749
10223 12:19:05.733976 00d00000 ################################################################
10224 12:19:05.734154
10225 12:19:06.371907 00d80000 ################################################################
10226 12:19:06.372056
10227 12:19:07.017074 00e00000 ################################################################
10228 12:19:07.017226
10229 12:19:07.640205 00e80000 ################################################################
10230 12:19:07.640348
10231 12:19:08.291240 00f00000 ################################################################
10232 12:19:08.291387
10233 12:19:08.932975 00f80000 ################################################################
10234 12:19:08.933159
10235 12:19:09.583808 01000000 ################################################################
10236 12:19:09.583954
10237 12:19:10.244056 01080000 ################################################################
10238 12:19:10.244221
10239 12:19:10.886415 01100000 ################################################################
10240 12:19:10.886569
10241 12:19:11.551980 01180000 ################################################################
10242 12:19:11.552122
10243 12:19:12.191886 01200000 ################################################################
10244 12:19:12.192047
10245 12:19:12.858540 01280000 ################################################################
10246 12:19:12.858711
10247 12:19:13.516173 01300000 ################################################################
10248 12:19:13.516343
10249 12:19:14.166656 01380000 ################################################################
10250 12:19:14.166823
10251 12:19:14.821105 01400000 ################################################################
10252 12:19:14.821283
10253 12:19:15.377959 01480000 ################################################################
10254 12:19:15.378111
10255 12:19:15.929062 01500000 ################################################################
10256 12:19:15.929212
10257 12:19:16.486109 01580000 ################################################################
10258 12:19:16.486264
10259 12:19:17.042665 01600000 ################################################################
10260 12:19:17.042883
10261 12:19:17.607081 01680000 ################################################################
10262 12:19:17.607246
10263 12:19:18.147998 01700000 ################################################################
10264 12:19:18.148155
10265 12:19:18.701115 01780000 ################################################################
10266 12:19:18.701273
10267 12:19:19.242321 01800000 ################################################################
10268 12:19:19.242479
10269 12:19:19.782987 01880000 ################################################################
10270 12:19:19.783211
10271 12:19:20.324504 01900000 ################################################################
10272 12:19:20.324707
10273 12:19:20.889823 01980000 ################################################################
10274 12:19:20.890028
10275 12:19:21.450675 01a00000 ################################################################
10276 12:19:21.450908
10277 12:19:22.011973 01a80000 ################################################################
10278 12:19:22.012129
10279 12:19:22.555344 01b00000 ################################################################
10280 12:19:22.555525
10281 12:19:22.611449 01b80000 ####### done.
10282 12:19:22.611602
10283 12:19:22.614732 The bootfile was 28889534 bytes long.
10284 12:19:22.614843
10285 12:19:22.617913 Sending tftp read request... done.
10286 12:19:22.618004
10287 12:19:22.618072 Waiting for the transfer...
10288 12:19:22.618133
10289 12:19:22.621231 00000000 # done.
10290 12:19:22.621327
10291 12:19:22.628188 Command line loaded dynamically from TFTP file: 11893105/tftp-deploy-_84d9rro/kernel/cmdline
10292 12:19:22.628300
10293 12:19:22.651702 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893105/extract-nfsrootfs-gf_o5kdg,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10294 12:19:22.651851
10295 12:19:22.651925 Loading FIT.
10296 12:19:22.651989
10297 12:19:22.655093 Image ramdisk-1 has 17792226 bytes.
10298 12:19:22.655186
10299 12:19:22.658552 Image fdt-1 has 47278 bytes.
10300 12:19:22.658665
10301 12:19:22.661513 Image kernel-1 has 11047994 bytes.
10302 12:19:22.661599
10303 12:19:22.671464 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10304 12:19:22.671593
10305 12:19:22.688264 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10306 12:19:22.688444
10307 12:19:22.691721 Choosing best match conf-1 for compat google,spherion-rev2.
10308 12:19:22.696966
10309 12:19:22.701595 Connected to device vid:did:rid of 1ae0:0028:00
10310 12:19:22.710105
10311 12:19:22.713348 tpm_get_response: command 0x17b, return code 0x0
10312 12:19:22.713474
10313 12:19:22.716369 ec_init: CrosEC protocol v3 supported (256, 248)
10314 12:19:22.720716
10315 12:19:22.723639 tpm_cleanup: add release locality here.
10316 12:19:22.723737
10317 12:19:22.723804 Shutting down all USB controllers.
10318 12:19:22.723866
10319 12:19:22.726997 Removing current net device
10320 12:19:22.727084
10321 12:19:22.734468 Exiting depthcharge with code 4 at timestamp: 79846320
10322 12:19:22.734636
10323 12:19:22.737132 LZMA decompressing kernel-1 to 0x821a6718
10324 12:19:22.737250
10325 12:19:22.740377 LZMA decompressing kernel-1 to 0x40000000
10326 12:19:24.128648
10327 12:19:24.128787 jumping to kernel
10328 12:19:24.129321 end: 2.2.4 bootloader-commands (duration 00:00:52) [common]
10329 12:19:24.129421 start: 2.2.5 auto-login-action (timeout 00:03:33) [common]
10330 12:19:24.129498 Setting prompt string to ['Linux version [0-9]']
10331 12:19:24.129568 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10332 12:19:24.129636 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10333 12:19:24.210290
10334 12:19:24.213407 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10335 12:19:24.216917 start: 2.2.5.1 login-action (timeout 00:03:33) [common]
10336 12:19:24.217016 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10337 12:19:24.217089 Setting prompt string to []
10338 12:19:24.217164 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10339 12:19:24.217239 Using line separator: #'\n'#
10340 12:19:24.217298 No login prompt set.
10341 12:19:24.217361 Parsing kernel messages
10342 12:19:24.217416 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10343 12:19:24.217516 [login-action] Waiting for messages, (timeout 00:03:33)
10344 12:19:24.236624 [ 0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023
10345 12:19:24.240181 [ 0.000000] random: crng init done
10346 12:19:24.246776 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10347 12:19:24.246871 [ 0.000000] efi: UEFI not found.
10348 12:19:24.256709 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10349 12:19:24.263247 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10350 12:19:24.273356 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10351 12:19:24.283319 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10352 12:19:24.290202 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10353 12:19:24.293241 [ 0.000000] printk: bootconsole [mtk8250] enabled
10354 12:19:24.302014 [ 0.000000] NUMA: No NUMA configuration found
10355 12:19:24.308732 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10356 12:19:24.315204 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10357 12:19:24.315314 [ 0.000000] Zone ranges:
10358 12:19:24.321971 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10359 12:19:24.325129 [ 0.000000] DMA32 empty
10360 12:19:24.331736 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10361 12:19:24.335022 [ 0.000000] Movable zone start for each node
10362 12:19:24.338483 [ 0.000000] Early memory node ranges
10363 12:19:24.345019 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10364 12:19:24.351944 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10365 12:19:24.358465 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10366 12:19:24.365124 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10367 12:19:24.372032 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10368 12:19:24.378707 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10369 12:19:24.434717 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10370 12:19:24.441281 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10371 12:19:24.447984 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10372 12:19:24.451806 [ 0.000000] psci: probing for conduit method from DT.
10373 12:19:24.458171 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10374 12:19:24.461538 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10375 12:19:24.468185 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10376 12:19:24.471470 [ 0.000000] psci: SMC Calling Convention v1.2
10377 12:19:24.478389 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10378 12:19:24.481825 [ 0.000000] Detected VIPT I-cache on CPU0
10379 12:19:24.488412 [ 0.000000] CPU features: detected: GIC system register CPU interface
10380 12:19:24.494663 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10381 12:19:24.501799 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10382 12:19:24.509171 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10383 12:19:24.515816 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10384 12:19:24.521741 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10385 12:19:24.528590 [ 0.000000] alternatives: applying boot alternatives
10386 12:19:24.531708 [ 0.000000] Fallback order for Node 0: 0
10387 12:19:24.538125 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10388 12:19:24.541580 [ 0.000000] Policy zone: Normal
10389 12:19:24.565271 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893105/extract-nfsrootfs-gf_o5kdg,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10390 12:19:24.574955 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10391 12:19:24.587552 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10392 12:19:24.597661 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10393 12:19:24.604008 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10394 12:19:24.607579 <6>[ 0.000000] software IO TLB: area num 8.
10395 12:19:24.663747 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10396 12:19:24.813089 <6>[ 0.000000] Memory: 7952116K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 400652K reserved, 32768K cma-reserved)
10397 12:19:24.820105 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10398 12:19:24.826386 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10399 12:19:24.830082 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10400 12:19:24.836797 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10401 12:19:24.842990 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10402 12:19:24.846759 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10403 12:19:24.856676 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10404 12:19:24.863326 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10405 12:19:24.866616 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10406 12:19:24.874060 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10407 12:19:24.877368 <6>[ 0.000000] GICv3: 608 SPIs implemented
10408 12:19:24.884124 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10409 12:19:24.887677 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10410 12:19:24.890678 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10411 12:19:24.900619 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10412 12:19:24.910674 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10413 12:19:24.924408 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10414 12:19:24.931217 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10415 12:19:24.940532 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10416 12:19:24.953311 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10417 12:19:24.960123 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10418 12:19:24.966561 <6>[ 0.009169] Console: colour dummy device 80x25
10419 12:19:24.976761 <6>[ 0.013896] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10420 12:19:24.980120 <6>[ 0.024402] pid_max: default: 32768 minimum: 301
10421 12:19:24.986322 <6>[ 0.029273] LSM: Security Framework initializing
10422 12:19:24.993399 <6>[ 0.034240] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 12:19:25.003599 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 12:19:25.010157 <6>[ 0.051465] cblist_init_generic: Setting adjustable number of callback queues.
10425 12:19:25.016889 <6>[ 0.058904] cblist_init_generic: Setting shift to 3 and lim to 1.
10426 12:19:25.023599 <6>[ 0.065245] cblist_init_generic: Setting adjustable number of callback queues.
10427 12:19:25.030036 <6>[ 0.072672] cblist_init_generic: Setting shift to 3 and lim to 1.
10428 12:19:25.036981 <6>[ 0.079111] rcu: Hierarchical SRCU implementation.
10429 12:19:25.039998 <6>[ 0.084127] rcu: Max phase no-delay instances is 1000.
10430 12:19:25.048269 <6>[ 0.091152] EFI services will not be available.
10431 12:19:25.051544 <6>[ 0.096108] smp: Bringing up secondary CPUs ...
10432 12:19:25.060542 <6>[ 0.101159] Detected VIPT I-cache on CPU1
10433 12:19:25.067286 <6>[ 0.101228] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10434 12:19:25.074168 <6>[ 0.101258] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10435 12:19:25.076908 <6>[ 0.101596] Detected VIPT I-cache on CPU2
10436 12:19:25.083952 <6>[ 0.101649] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10437 12:19:25.090704 <6>[ 0.101666] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10438 12:19:25.097071 <6>[ 0.101928] Detected VIPT I-cache on CPU3
10439 12:19:25.103711 <6>[ 0.101975] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10440 12:19:25.110520 <6>[ 0.101991] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10441 12:19:25.113918 <6>[ 0.102299] CPU features: detected: Spectre-v4
10442 12:19:25.120886 <6>[ 0.102305] CPU features: detected: Spectre-BHB
10443 12:19:25.123782 <6>[ 0.102310] Detected PIPT I-cache on CPU4
10444 12:19:25.130495 <6>[ 0.102369] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10445 12:19:25.137512 <6>[ 0.102386] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10446 12:19:25.140915 <6>[ 0.102678] Detected PIPT I-cache on CPU5
10447 12:19:25.150279 <6>[ 0.102741] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10448 12:19:25.157211 <6>[ 0.102758] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10449 12:19:25.160525 <6>[ 0.103038] Detected PIPT I-cache on CPU6
10450 12:19:25.167358 <6>[ 0.103102] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10451 12:19:25.173611 <6>[ 0.103118] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10452 12:19:25.177047 <6>[ 0.103416] Detected PIPT I-cache on CPU7
10453 12:19:25.186995 <6>[ 0.103481] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10454 12:19:25.193822 <6>[ 0.103497] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10455 12:19:25.197122 <6>[ 0.103544] smp: Brought up 1 node, 8 CPUs
10456 12:19:25.200463 <6>[ 0.244875] SMP: Total of 8 processors activated.
10457 12:19:25.207209 <6>[ 0.249796] CPU features: detected: 32-bit EL0 Support
10458 12:19:25.217077 <6>[ 0.255159] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10459 12:19:25.223895 <6>[ 0.264015] CPU features: detected: Common not Private translations
10460 12:19:25.226954 <6>[ 0.270490] CPU features: detected: CRC32 instructions
10461 12:19:25.233762 <6>[ 0.275842] CPU features: detected: RCpc load-acquire (LDAPR)
10462 12:19:25.240239 <6>[ 0.281802] CPU features: detected: LSE atomic instructions
10463 12:19:25.243961 <6>[ 0.287584] CPU features: detected: Privileged Access Never
10464 12:19:25.250547 <6>[ 0.293364] CPU features: detected: RAS Extension Support
10465 12:19:25.257265 <6>[ 0.298973] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10466 12:19:25.264182 <6>[ 0.306194] CPU: All CPU(s) started at EL2
10467 12:19:25.267485 <6>[ 0.310511] alternatives: applying system-wide alternatives
10468 12:19:25.278219 <6>[ 0.321216] devtmpfs: initialized
10469 12:19:25.290201 <6>[ 0.329990] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10470 12:19:25.300077 <6>[ 0.339952] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10471 12:19:25.306599 <6>[ 0.347958] pinctrl core: initialized pinctrl subsystem
10472 12:19:25.309931 <6>[ 0.354646] DMI not present or invalid.
10473 12:19:25.316799 <6>[ 0.359055] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10474 12:19:25.326705 <6>[ 0.365912] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10475 12:19:25.333749 <6>[ 0.373500] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10476 12:19:25.343364 <6>[ 0.381714] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10477 12:19:25.347341 <6>[ 0.389957] audit: initializing netlink subsys (disabled)
10478 12:19:25.357118 <5>[ 0.395651] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10479 12:19:25.360240 <6>[ 0.396356] thermal_sys: Registered thermal governor 'step_wise'
10480 12:19:25.370474 <6>[ 0.403618] thermal_sys: Registered thermal governor 'power_allocator'
10481 12:19:25.373308 <6>[ 0.409876] cpuidle: using governor menu
10482 12:19:25.376590 <6>[ 0.420836] NET: Registered PF_QIPCRTR protocol family
10483 12:19:25.387055 <6>[ 0.426333] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10484 12:19:25.390255 <6>[ 0.433438] ASID allocator initialised with 32768 entries
10485 12:19:25.396918 <6>[ 0.440007] Serial: AMBA PL011 UART driver
10486 12:19:25.405860 <4>[ 0.448764] Trying to register duplicate clock ID: 134
10487 12:19:25.459486 <6>[ 0.506027] KASLR enabled
10488 12:19:25.473846 <6>[ 0.513678] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10489 12:19:25.480781 <6>[ 0.520694] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10490 12:19:25.487485 <6>[ 0.527185] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10491 12:19:25.493760 <6>[ 0.534192] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10492 12:19:25.500538 <6>[ 0.540682] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10493 12:19:25.507165 <6>[ 0.547687] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10494 12:19:25.513734 <6>[ 0.554176] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10495 12:19:25.520572 <6>[ 0.561181] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10496 12:19:25.523931 <6>[ 0.568651] ACPI: Interpreter disabled.
10497 12:19:25.531822 <6>[ 0.575102] iommu: Default domain type: Translated
10498 12:19:25.538685 <6>[ 0.580215] iommu: DMA domain TLB invalidation policy: strict mode
10499 12:19:25.541833 <5>[ 0.586878] SCSI subsystem initialized
10500 12:19:25.548946 <6>[ 0.591125] usbcore: registered new interface driver usbfs
10501 12:19:25.555239 <6>[ 0.596854] usbcore: registered new interface driver hub
10502 12:19:25.559007 <6>[ 0.602406] usbcore: registered new device driver usb
10503 12:19:25.565626 <6>[ 0.608523] pps_core: LinuxPPS API ver. 1 registered
10504 12:19:25.575702 <6>[ 0.613717] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10505 12:19:25.579150 <6>[ 0.623060] PTP clock support registered
10506 12:19:25.582058 <6>[ 0.627304] EDAC MC: Ver: 3.0.0
10507 12:19:25.589349 <6>[ 0.632500] FPGA manager framework
10508 12:19:25.592606 <6>[ 0.636178] Advanced Linux Sound Architecture Driver Initialized.
10509 12:19:25.596517 <6>[ 0.642943] vgaarb: loaded
10510 12:19:25.603186 <6>[ 0.646122] clocksource: Switched to clocksource arch_sys_counter
10511 12:19:25.609861 <5>[ 0.652569] VFS: Disk quotas dquot_6.6.0
10512 12:19:25.616684 <6>[ 0.656755] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10513 12:19:25.619734 <6>[ 0.663945] pnp: PnP ACPI: disabled
10514 12:19:25.627591 <6>[ 0.670606] NET: Registered PF_INET protocol family
10515 12:19:25.637687 <6>[ 0.676190] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10516 12:19:25.648762 <6>[ 0.688485] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10517 12:19:25.658869 <6>[ 0.697300] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10518 12:19:25.665152 <6>[ 0.705271] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10519 12:19:25.671994 <6>[ 0.713972] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10520 12:19:25.683913 <6>[ 0.723715] TCP: Hash tables configured (established 65536 bind 65536)
10521 12:19:25.690330 <6>[ 0.730579] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10522 12:19:25.697652 <6>[ 0.737778] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10523 12:19:25.703699 <6>[ 0.745479] NET: Registered PF_UNIX/PF_LOCAL protocol family
10524 12:19:25.710910 <6>[ 0.751645] RPC: Registered named UNIX socket transport module.
10525 12:19:25.713772 <6>[ 0.757799] RPC: Registered udp transport module.
10526 12:19:25.720588 <6>[ 0.762732] RPC: Registered tcp transport module.
10527 12:19:25.727097 <6>[ 0.767663] RPC: Registered tcp NFSv4.1 backchannel transport module.
10528 12:19:25.730566 <6>[ 0.774331] PCI: CLS 0 bytes, default 64
10529 12:19:25.733741 <6>[ 0.778736] Unpacking initramfs...
10530 12:19:25.758618 <6>[ 0.798234] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10531 12:19:25.768411 <6>[ 0.806900] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10532 12:19:25.771866 <6>[ 0.815746] kvm [1]: IPA Size Limit: 40 bits
10533 12:19:25.778611 <6>[ 0.820272] kvm [1]: GICv3: no GICV resource entry
10534 12:19:25.782101 <6>[ 0.825295] kvm [1]: disabling GICv2 emulation
10535 12:19:25.788292 <6>[ 0.829980] kvm [1]: GIC system register CPU interface enabled
10536 12:19:25.792015 <6>[ 0.836137] kvm [1]: vgic interrupt IRQ18
10537 12:19:25.798685 <6>[ 0.840486] kvm [1]: VHE mode initialized successfully
10538 12:19:25.802103 <5>[ 0.846892] Initialise system trusted keyrings
10539 12:19:25.811611 <6>[ 0.851677] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10540 12:19:25.818334 <6>[ 0.861650] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10541 12:19:25.825361 <5>[ 0.868016] NFS: Registering the id_resolver key type
10542 12:19:25.828769 <5>[ 0.873316] Key type id_resolver registered
10543 12:19:25.836020 <5>[ 0.877732] Key type id_legacy registered
10544 12:19:25.841844 <6>[ 0.882009] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10545 12:19:25.848922 <6>[ 0.888929] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10546 12:19:25.855354 <6>[ 0.896638] 9p: Installing v9fs 9p2000 file system support
10547 12:19:25.891664 <5>[ 0.934867] Key type asymmetric registered
10548 12:19:25.894993 <5>[ 0.939198] Asymmetric key parser 'x509' registered
10549 12:19:25.904994 <6>[ 0.944341] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10550 12:19:25.908350 <6>[ 0.951955] io scheduler mq-deadline registered
10551 12:19:25.912274 <6>[ 0.956720] io scheduler kyber registered
10552 12:19:25.930483 <6>[ 0.973895] EINJ: ACPI disabled.
10553 12:19:25.962963 <4>[ 0.999491] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 12:19:25.973122 <4>[ 1.010124] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10555 12:19:25.987873 <6>[ 1.030958] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10556 12:19:25.995892 <6>[ 1.038922] printk: console [ttyS0] disabled
10557 12:19:26.023874 <6>[ 1.063599] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10558 12:19:26.030502 <6>[ 1.073091] printk: console [ttyS0] enabled
10559 12:19:26.033877 <6>[ 1.073091] printk: console [ttyS0] enabled
10560 12:19:26.040691 <6>[ 1.081981] printk: bootconsole [mtk8250] disabled
10561 12:19:26.043911 <6>[ 1.081981] printk: bootconsole [mtk8250] disabled
10562 12:19:26.050433 <6>[ 1.093256] SuperH (H)SCI(F) driver initialized
10563 12:19:26.053754 <6>[ 1.098537] msm_serial: driver initialized
10564 12:19:26.067593 <6>[ 1.107591] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10565 12:19:26.078251 <6>[ 1.116138] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10566 12:19:26.084526 <6>[ 1.124680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10567 12:19:26.094309 <6>[ 1.133307] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10568 12:19:26.101037 <6>[ 1.142014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10569 12:19:26.111037 <6>[ 1.150736] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10570 12:19:26.121079 <6>[ 1.159276] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10571 12:19:26.127606 <6>[ 1.168078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10572 12:19:26.137351 <6>[ 1.176623] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10573 12:19:26.149332 <6>[ 1.192204] loop: module loaded
10574 12:19:26.155558 <6>[ 1.198225] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10575 12:19:26.178424 <4>[ 1.221796] mtk-pmic-keys: Failed to locate of_node [id: -1]
10576 12:19:26.185996 <6>[ 1.228954] megasas: 07.719.03.00-rc1
10577 12:19:26.195456 <6>[ 1.238749] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10578 12:19:26.206159 <6>[ 1.245504] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10579 12:19:26.219322 <6>[ 1.262350] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10580 12:19:26.275798 <6>[ 1.312497] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10581 12:19:26.471836 <6>[ 1.515282] Freeing initrd memory: 17372K
10582 12:19:26.482330 <6>[ 1.525642] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10583 12:19:26.493536 <6>[ 1.536731] tun: Universal TUN/TAP device driver, 1.6
10584 12:19:26.497085 <6>[ 1.542822] thunder_xcv, ver 1.0
10585 12:19:26.500243 <6>[ 1.546327] thunder_bgx, ver 1.0
10586 12:19:26.503207 <6>[ 1.549817] nicpf, ver 1.0
10587 12:19:26.514337 <6>[ 1.553859] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10588 12:19:26.517673 <6>[ 1.561334] hns3: Copyright (c) 2017 Huawei Corporation.
10589 12:19:26.520912 <6>[ 1.566923] hclge is initializing
10590 12:19:26.527384 <6>[ 1.570505] e1000: Intel(R) PRO/1000 Network Driver
10591 12:19:26.533985 <6>[ 1.575634] e1000: Copyright (c) 1999-2006 Intel Corporation.
10592 12:19:26.537668 <6>[ 1.581647] e1000e: Intel(R) PRO/1000 Network Driver
10593 12:19:26.544400 <6>[ 1.586862] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10594 12:19:26.551006 <6>[ 1.593051] igb: Intel(R) Gigabit Ethernet Network Driver
10595 12:19:26.557916 <6>[ 1.598701] igb: Copyright (c) 2007-2014 Intel Corporation.
10596 12:19:26.564117 <6>[ 1.604537] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10597 12:19:26.567528 <6>[ 1.611055] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10598 12:19:26.574173 <6>[ 1.617536] sky2: driver version 1.30
10599 12:19:26.580790 <6>[ 1.622587] VFIO - User Level meta-driver version: 0.3
10600 12:19:26.587639 <6>[ 1.630849] usbcore: registered new interface driver usb-storage
10601 12:19:26.594080 <6>[ 1.637297] usbcore: registered new device driver onboard-usb-hub
10602 12:19:26.603476 <6>[ 1.646443] mt6397-rtc mt6359-rtc: registered as rtc0
10603 12:19:26.613407 <6>[ 1.651908] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:19:29 UTC (1698409169)
10604 12:19:26.616613 <6>[ 1.661480] i2c_dev: i2c /dev entries driver
10605 12:19:26.633430 <6>[ 1.673290] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10606 12:19:26.653361 <6>[ 1.696287] cpu cpu0: EM: created perf domain
10607 12:19:26.656457 <6>[ 1.701198] cpu cpu4: EM: created perf domain
10608 12:19:26.663657 <6>[ 1.706810] sdhci: Secure Digital Host Controller Interface driver
10609 12:19:26.670223 <6>[ 1.713242] sdhci: Copyright(c) Pierre Ossman
10610 12:19:26.676994 <6>[ 1.718192] Synopsys Designware Multimedia Card Interface Driver
10611 12:19:26.683537 <6>[ 1.724838] sdhci-pltfm: SDHCI platform and OF driver helper
10612 12:19:26.687212 <6>[ 1.724985] mmc0: CQHCI version 5.10
10613 12:19:26.693790 <6>[ 1.735018] ledtrig-cpu: registered to indicate activity on CPUs
10614 12:19:26.700314 <6>[ 1.742089] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10615 12:19:26.707321 <6>[ 1.749143] usbcore: registered new interface driver usbhid
10616 12:19:26.710085 <6>[ 1.754968] usbhid: USB HID core driver
10617 12:19:26.717032 <6>[ 1.759179] spi_master spi0: will run message pump with realtime priority
10618 12:19:26.761161 <6>[ 1.797531] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10619 12:19:26.777644 <6>[ 1.813674] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10620 12:19:26.784530 <6>[ 1.827256] mmc0: Command Queue Engine enabled
10621 12:19:26.791554 <6>[ 1.832002] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10622 12:19:26.797816 <6>[ 1.839153] cros-ec-spi spi0.0: Chrome EC device registered
10623 12:19:26.801276 <6>[ 1.839373] mmcblk0: mmc0:0001 DA4128 116 GiB
10624 12:19:26.812542 <6>[ 1.855403] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10625 12:19:26.819557 <6>[ 1.862720] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10626 12:19:26.826714 <6>[ 1.868693] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10627 12:19:26.833329 <6>[ 1.874815] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10628 12:19:26.846621 <6>[ 1.886839] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10629 12:19:26.853886 <6>[ 1.897245] NET: Registered PF_PACKET protocol family
10630 12:19:26.857529 <6>[ 1.902607] 9pnet: Installing 9P2000 support
10631 12:19:26.864237 <5>[ 1.907174] Key type dns_resolver registered
10632 12:19:26.867697 <6>[ 1.912246] registered taskstats version 1
10633 12:19:26.873940 <5>[ 1.916641] Loading compiled-in X.509 certificates
10634 12:19:26.904087 <4>[ 1.940538] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 12:19:26.914022 <4>[ 1.951324] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 12:19:26.920354 <3>[ 1.961871] debugfs: File 'uA_load' in directory '/' already present!
10637 12:19:26.927164 <3>[ 1.968574] debugfs: File 'min_uV' in directory '/' already present!
10638 12:19:26.933701 <3>[ 1.975182] debugfs: File 'max_uV' in directory '/' already present!
10639 12:19:26.940661 <3>[ 1.981789] debugfs: File 'constraint_flags' in directory '/' already present!
10640 12:19:26.951211 <3>[ 1.991334] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10641 12:19:26.962432 <6>[ 2.005457] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10642 12:19:26.969192 <6>[ 2.012243] xhci-mtk 11200000.usb: xHCI Host Controller
10643 12:19:26.975820 <6>[ 2.017742] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10644 12:19:26.985705 <6>[ 2.025599] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10645 12:19:26.992498 <6>[ 2.035032] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10646 12:19:26.999477 <6>[ 2.041115] xhci-mtk 11200000.usb: xHCI Host Controller
10647 12:19:27.005733 <6>[ 2.046598] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10648 12:19:27.012725 <6>[ 2.054250] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10649 12:19:27.019352 <6>[ 2.061965] hub 1-0:1.0: USB hub found
10650 12:19:27.022431 <6>[ 2.065981] hub 1-0:1.0: 1 port detected
10651 12:19:27.029581 <6>[ 2.070251] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10652 12:19:27.036006 <6>[ 2.078856] hub 2-0:1.0: USB hub found
10653 12:19:27.039350 <6>[ 2.082877] hub 2-0:1.0: 1 port detected
10654 12:19:27.048359 <6>[ 2.091270] mtk-msdc 11f70000.mmc: Got CD GPIO
10655 12:19:27.060373 <6>[ 2.099838] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10656 12:19:27.066535 <6>[ 2.107875] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10657 12:19:27.076460 <4>[ 2.115806] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10658 12:19:27.086675 <6>[ 2.125340] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10659 12:19:27.093240 <6>[ 2.133418] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10660 12:19:27.100492 <6>[ 2.141442] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10661 12:19:27.110256 <6>[ 2.149364] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10662 12:19:27.116921 <6>[ 2.157182] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10663 12:19:27.126929 <6>[ 2.164998] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10664 12:19:27.136712 <6>[ 2.175428] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10665 12:19:27.143864 <6>[ 2.183815] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10666 12:19:27.154106 <6>[ 2.192166] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10667 12:19:27.160210 <6>[ 2.200506] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10668 12:19:27.170279 <6>[ 2.208844] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10669 12:19:27.176955 <6>[ 2.217183] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10670 12:19:27.187336 <6>[ 2.225521] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10671 12:19:27.194056 <6>[ 2.233860] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10672 12:19:27.203945 <6>[ 2.242198] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10673 12:19:27.210317 <6>[ 2.250540] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10674 12:19:27.220791 <6>[ 2.258879] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10675 12:19:27.227115 <6>[ 2.267217] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10676 12:19:27.237117 <6>[ 2.275555] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10677 12:19:27.243788 <6>[ 2.283893] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10678 12:19:27.253679 <6>[ 2.292230] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10679 12:19:27.260359 <6>[ 2.300957] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10680 12:19:27.267369 <6>[ 2.308112] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10681 12:19:27.274316 <6>[ 2.314880] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10682 12:19:27.280575 <6>[ 2.321627] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10683 12:19:27.287094 <6>[ 2.328564] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10684 12:19:27.296909 <6>[ 2.335424] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10685 12:19:27.307011 <6>[ 2.344562] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10686 12:19:27.313505 <6>[ 2.353682] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10687 12:19:27.323754 <6>[ 2.362976] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10688 12:19:27.333286 <6>[ 2.372444] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10689 12:19:27.343251 <6>[ 2.381912] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10690 12:19:27.353299 <6>[ 2.391034] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10691 12:19:27.360119 <6>[ 2.400501] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10692 12:19:27.369773 <6>[ 2.409621] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10693 12:19:27.379943 <6>[ 2.418920] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10694 12:19:27.390009 <6>[ 2.429081] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10695 12:19:27.400290 <6>[ 2.440489] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10696 12:19:27.407075 <6>[ 2.450477] Trying to probe devices needed for running init ...
10697 12:19:27.454612 <6>[ 2.494397] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10698 12:19:27.609489 <6>[ 2.652481] hub 1-1:1.0: USB hub found
10699 12:19:27.612219 <6>[ 2.656988] hub 1-1:1.0: 4 ports detected
10700 12:19:27.734489 <6>[ 2.774688] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10701 12:19:27.761017 <6>[ 2.804233] hub 2-1:1.0: USB hub found
10702 12:19:27.764227 <6>[ 2.808716] hub 2-1:1.0: 3 ports detected
10703 12:19:27.934541 <6>[ 2.974392] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10704 12:19:28.066836 <6>[ 3.110180] hub 1-1.4:1.0: USB hub found
10705 12:19:28.070170 <6>[ 3.114855] hub 1-1.4:1.0: 2 ports detected
10706 12:19:28.146536 <6>[ 3.186563] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10707 12:19:28.366479 <6>[ 3.406447] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10708 12:19:28.557991 <6>[ 3.598473] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10709 12:19:39.687468 <6>[ 14.735486] ALSA device list:
10710 12:19:39.693713 <6>[ 14.738785] No soundcards found.
10711 12:19:39.701987 <6>[ 14.746856] Freeing unused kernel memory: 8384K
10712 12:19:39.705501 <6>[ 14.751862] Run /init as init process
10713 12:19:39.716694 Loading, please wait...
10714 12:19:39.737462 Starting version 247.3-7+deb11u2
10715 12:19:39.927168 <6>[ 14.968662] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10716 12:19:39.938630 <6>[ 14.983204] remoteproc remoteproc0: scp is available
10717 12:19:39.947476 <6>[ 14.992529] remoteproc remoteproc0: powering up scp
10718 12:19:39.957935 <6>[ 14.997752] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10719 12:19:39.960921 <6>[ 15.006721] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10720 12:19:39.971765 <3>[ 15.012927] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 12:19:39.977902 <3>[ 15.021096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 12:19:39.988114 <3>[ 15.029329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 12:19:39.995387 <6>[ 15.030994] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10724 12:19:40.004805 <6>[ 15.045764] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10725 12:19:40.011522 <4>[ 15.045897] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10726 12:19:40.021714 <3>[ 15.052015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 12:19:40.028138 <3>[ 15.052030] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10728 12:19:40.037752 <3>[ 15.052034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 12:19:40.044495 <3>[ 15.052076] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 12:19:40.051357 <3>[ 15.052080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10731 12:19:40.061536 <3>[ 15.052145] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 12:19:40.067987 <3>[ 15.052204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 12:19:40.078006 <3>[ 15.052209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 12:19:40.084696 <3>[ 15.052213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 12:19:40.094681 <3>[ 15.052272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 12:19:40.101176 <3>[ 15.052275] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 12:19:40.111836 <3>[ 15.052278] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 12:19:40.118845 <3>[ 15.052281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 12:19:40.125233 <3>[ 15.052284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 12:19:40.135331 <3>[ 15.052306] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 12:19:40.141826 <6>[ 15.054467] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10742 12:19:40.148955 <6>[ 15.058989] usbcore: registered new interface driver r8152
10743 12:19:40.155969 <4>[ 15.062284] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10744 12:19:40.162582 <6>[ 15.078718] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10745 12:19:40.169029 <6>[ 15.078785] mc: Linux media interface: v0.10
10746 12:19:40.172231 <6>[ 15.095451] videodev: Linux video capture interface: v2.00
10747 12:19:40.182204 <4>[ 15.129195] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10748 12:19:40.188817 <4>[ 15.129195] Fallback method does not support PEC.
10749 12:19:40.195458 <6>[ 15.133666] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10750 12:19:40.201819 <6>[ 15.133678] remoteproc remoteproc0: remote processor scp is now up
10751 12:19:40.208460 <6>[ 15.133681] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10752 12:19:40.218298 <6>[ 15.144522] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10753 12:19:40.224998 <3>[ 15.166431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10754 12:19:40.232047 <6>[ 15.166539] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10755 12:19:40.241665 <6>[ 15.169475] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10756 12:19:40.248445 <6>[ 15.179693] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10757 12:19:40.258355 <4>[ 15.189790] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10758 12:19:40.264916 <6>[ 15.192852] pci_bus 0000:00: root bus resource [bus 00-ff]
10759 12:19:40.271903 <6>[ 15.193085] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10760 12:19:40.281738 <4>[ 15.198598] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10761 12:19:40.288270 <3>[ 15.201968] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10762 12:19:40.298302 <6>[ 15.203035] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10763 12:19:40.308441 <6>[ 15.203403] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10764 12:19:40.315490 <6>[ 15.205723] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10765 12:19:40.321948 <6>[ 15.246588] usbcore: registered new interface driver cdc_ether
10766 12:19:40.325154 <6>[ 15.246893] Bluetooth: Core ver 2.22
10767 12:19:40.331713 <6>[ 15.247034] NET: Registered PF_BLUETOOTH protocol family
10768 12:19:40.338190 <6>[ 15.247047] Bluetooth: HCI device and connection manager initialized
10769 12:19:40.341836 <6>[ 15.247099] Bluetooth: HCI socket layer initialized
10770 12:19:40.348530 <6>[ 15.247112] Bluetooth: L2CAP socket layer initialized
10771 12:19:40.354909 <6>[ 15.247133] Bluetooth: SCO socket layer initialized
10772 12:19:40.364741 <6>[ 15.266132] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10773 12:19:40.367843 <6>[ 15.276599] usbcore: registered new interface driver r8153_ecm
10774 12:19:40.378249 <6>[ 15.277585] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10775 12:19:40.387745 <6>[ 15.278812] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10776 12:19:40.394606 <6>[ 15.278970] usbcore: registered new interface driver uvcvideo
10777 12:19:40.401304 <6>[ 15.283503] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10778 12:19:40.408212 <6>[ 15.292749] usbcore: registered new interface driver btusb
10779 12:19:40.417977 <4>[ 15.293219] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10780 12:19:40.424394 <3>[ 15.293227] Bluetooth: hci0: Failed to load firmware file (-2)
10781 12:19:40.428061 <3>[ 15.293229] Bluetooth: hci0: Failed to set up firmware (-2)
10782 12:19:40.441084 <4>[ 15.293230] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10783 12:19:40.447606 <6>[ 15.298483] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10784 12:19:40.454315 <6>[ 15.299069] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10785 12:19:40.457254 <6>[ 15.322250] r8152 2-1.3:1.0 eth0: v1.12.13
10786 12:19:40.460807 <6>[ 15.322609] pci 0000:00:00.0: supports D1 D2
10787 12:19:40.467452 <6>[ 15.344244] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10788 12:19:40.474096 <6>[ 15.349463] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10789 12:19:40.484233 <6>[ 15.350409] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10790 12:19:40.490673 <6>[ 15.533595] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10791 12:19:40.497720 <6>[ 15.539877] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10792 12:19:40.504124 <6>[ 15.547373] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10793 12:19:40.514018 <6>[ 15.554855] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10794 12:19:40.517546 <6>[ 15.562429] pci 0000:01:00.0: supports D1 D2
10795 12:19:40.523835 <6>[ 15.566948] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10796 12:19:40.540963 <6>[ 15.582422] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10797 12:19:40.547779 <6>[ 15.589321] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10798 12:19:40.554565 <6>[ 15.597401] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10799 12:19:40.564259 <6>[ 15.605398] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10800 12:19:40.570879 <6>[ 15.613398] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10801 12:19:40.580718 <6>[ 15.621399] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10802 12:19:40.583966 <6>[ 15.629399] pci 0000:00:00.0: PCI bridge to [bus 01]
10803 12:19:40.594106 <6>[ 15.634615] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10804 12:19:40.600807 <6>[ 15.642749] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10805 12:19:40.607259 <6>[ 15.649583] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10806 12:19:40.614099 <6>[ 15.656260] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10807 12:19:40.636176 <5>[ 15.677602] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10808 12:19:40.690259 <5>[ 15.697224] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10809 12:19:40.690403 <4>[ 15.704203] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10810 12:19:40.690477 <6>[ 15.713113] cfg80211: failed to load regulatory.db
10811 12:19:40.721616 <6>[ 15.763254] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10812 12:19:40.728142 <6>[ 15.770920] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10813 12:19:40.752680 <6>[ 15.797769] mt7921e 0000:01:00.0: ASIC revision: 79610010
10814 12:19:40.860120 <4>[ 15.898729] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 12:19:40.874367 Begin: Loading essential drivers ... done.
10816 12:19:40.877650 Begin: Running /scripts/init-premount ... done.
10817 12:19:40.884465 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10818 12:19:40.894612 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10819 12:19:40.897365 Device /sys/class/net/enx002432307852 found
10820 12:19:40.897477 done.
10821 12:19:40.988077 IP-Config: enx00<4>[ 16.026566] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10822 12:19:40.994590 2432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10823 12:19:41.112121 <4>[ 16.150503] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10824 12:19:41.231610 <4>[ 16.269718] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 12:19:41.348381 <4>[ 16.386317] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10826 12:19:41.498142 <4>[ 16.506189] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10827 12:19:41.588135 <4>[ 16.626308] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10828 12:19:41.707798 <4>[ 16.746205] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10829 12:19:41.827841 <4>[ 16.866219] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10830 12:19:41.948198 <4>[ 16.986162] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10831 12:19:41.954872 <6>[ 16.992968] r8152 2-1.3:1.0 enx002432307852: carrier on
10832 12:19:42.067231 <3>[ 17.112105] mt7921e 0000:01:00.0: hardware init failed
10833 12:19:42.106821 IP-Config: no response after 2 secs - giving up
10834 12:19:42.148942 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10835 12:19:42.151902 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10836 12:19:42.158744 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10837 12:19:42.165317 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10838 12:19:42.171729 host : mt8192-asurada-spherion-r0-cbg-3
10839 12:19:42.178734 domain : lava-rack
10840 12:19:42.181763 rootserver: 192.168.201.1 rootpath:
10841 12:19:42.185129 filename :
10842 12:19:42.245864 done.
10843 12:19:42.253412 Begin: Running /scripts/nfs-bottom ... done.
10844 12:19:42.268829 Begin: Running /scripts/init-bottom ... done.
10845 12:19:43.546553 <6>[ 18.591507] NET: Registered PF_INET6 protocol family
10846 12:19:43.553778 <6>[ 18.598979] Segment Routing with IPv6
10847 12:19:43.557015 <6>[ 18.602989] In-situ OAM (IOAM) with IPv6
10848 12:19:43.688549 <30>[ 18.713854] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10849 12:19:43.695232 <30>[ 18.738470] systemd[1]: Detected architecture arm64.
10850 12:19:43.715313
10851 12:19:43.718234 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10852 12:19:43.718340
10853 12:19:43.735983 <30>[ 18.781229] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10854 12:19:44.661064 <30>[ 19.703147] systemd[1]: Queued start job for default target Graphical Interface.
10855 12:19:44.699813 <30>[ 19.745084] systemd[1]: Created slice system-getty.slice.
10856 12:19:44.706654 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10857 12:19:44.722959 <30>[ 19.768020] systemd[1]: Created slice system-modprobe.slice.
10858 12:19:44.729289 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10859 12:19:44.747089 <30>[ 19.792666] systemd[1]: Created slice system-serial\x2dgetty.slice.
10860 12:19:44.757435 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10861 12:19:44.770645 <30>[ 19.815649] systemd[1]: Created slice User and Session Slice.
10862 12:19:44.777251 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10863 12:19:44.797175 <30>[ 19.839309] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10864 12:19:44.806997 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10865 12:19:44.825143 <30>[ 19.867206] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10866 12:19:44.832051 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10867 12:19:44.856198 <30>[ 19.894590] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10868 12:19:44.862392 <30>[ 19.906769] systemd[1]: Reached target Local Encrypted Volumes.
10869 12:19:44.869041 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10870 12:19:44.885669 <30>[ 19.931043] systemd[1]: Reached target Paths.
10871 12:19:44.889084 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10872 12:19:44.905688 <30>[ 19.950679] systemd[1]: Reached target Remote File Systems.
10873 12:19:44.912145 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10874 12:19:44.929233 <30>[ 19.974805] systemd[1]: Reached target Slices.
10875 12:19:44.935845 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10876 12:19:44.949344 <30>[ 19.994462] systemd[1]: Reached target Swap.
10877 12:19:44.952554 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10878 12:19:44.972677 <30>[ 20.014951] systemd[1]: Listening on initctl Compatibility Named Pipe.
10879 12:19:44.979506 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10880 12:19:44.986049 <30>[ 20.031363] systemd[1]: Listening on Journal Audit Socket.
10881 12:19:44.992808 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10882 12:19:45.010574 <30>[ 20.055951] systemd[1]: Listening on Journal Socket (/dev/log).
10883 12:19:45.017149 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10884 12:19:45.033633 <30>[ 20.079147] systemd[1]: Listening on Journal Socket.
10885 12:19:45.040274 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10886 12:19:45.057764 <30>[ 20.100100] systemd[1]: Listening on Network Service Netlink Socket.
10887 12:19:45.064585 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10888 12:19:45.079893 <30>[ 20.125483] systemd[1]: Listening on udev Control Socket.
10889 12:19:45.086847 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10890 12:19:45.101443 <30>[ 20.146941] systemd[1]: Listening on udev Kernel Socket.
10891 12:19:45.108525 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10892 12:19:45.149250 <30>[ 20.194472] systemd[1]: Mounting Huge Pages File System...
10893 12:19:45.155733 Mounting [0;1;39mHuge Pages File System[0m...
10894 12:19:45.173120 <30>[ 20.218723] systemd[1]: Mounting POSIX Message Queue File System...
10895 12:19:45.180117 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10896 12:19:45.202091 <30>[ 20.247330] systemd[1]: Mounting Kernel Debug File System...
10897 12:19:45.208801 Mounting [0;1;39mKernel Debug File System[0m...
10898 12:19:45.224959 <30>[ 20.267106] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10899 12:19:45.247351 <30>[ 20.289116] systemd[1]: Starting Create list of static device nodes for the current kernel...
10900 12:19:45.256957 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10901 12:19:45.271478 <30>[ 20.316942] systemd[1]: Starting Load Kernel Module configfs...
10902 12:19:45.278494 Starting [0;1;39mLoad Kernel Module configfs[0m...
10903 12:19:45.297283 <30>[ 20.342249] systemd[1]: Starting Load Kernel Module drm...
10904 12:19:45.303595 Starting [0;1;39mLoad Kernel Module drm[0m...
10905 12:19:45.320170 <30>[ 20.365683] systemd[1]: Starting Load Kernel Module fuse...
10906 12:19:45.326979 Starting [0;1;39mLoad Kernel Module fuse[0m...
10907 12:19:45.362783 <30>[ 20.405200] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10908 12:19:45.370235 <6>[ 20.415622] fuse: init (API version 7.37)
10909 12:19:45.378551 <30>[ 20.423307] systemd[1]: Starting Journal Service...
10910 12:19:45.381071 Starting [0;1;39mJournal Service[0m...
10911 12:19:45.408338 <30>[ 20.453681] systemd[1]: Starting Load Kernel Modules...
10912 12:19:45.414686 Starting [0;1;39mLoad Kernel Modules[0m...
10913 12:19:45.437693 <30>[ 20.479817] systemd[1]: Starting Remount Root and Kernel File Systems...
10914 12:19:45.444099 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10915 12:19:45.460795 <30>[ 20.506417] systemd[1]: Starting Coldplug All udev Devices...
10916 12:19:45.468176 Starting [0;1;39mColdplug All udev Devices[0m...
10917 12:19:45.487007 <30>[ 20.532127] systemd[1]: Mounted Huge Pages File System.
10918 12:19:45.493569 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10919 12:19:45.506918 <3>[ 20.548937] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 12:19:45.513396 <30>[ 20.558805] systemd[1]: Mounted POSIX Message Queue File System.
10921 12:19:45.519823 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10922 12:19:45.538605 <3>[ 20.580354] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 12:19:45.545295 <30>[ 20.589744] systemd[1]: Mounted Kernel Debug File System.
10924 12:19:45.551878 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10925 12:19:45.570228 <30>[ 20.612298] systemd[1]: Finished Create list of static device nodes for the current kernel.
10926 12:19:45.587219 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current<3>[ 20.627273] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:19:45.587354 kernel[0m.
10928 12:19:45.594600 <30>[ 20.639823] systemd[1]: modprobe@configfs.service: Succeeded.
10929 12:19:45.611255 <30>[ 20.655667] systemd[1]: Finished Load Kernel Module configfs.
10930 12:19:45.620962 [[0;32m OK [<3>[ 20.662875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 12:19:45.627753 0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10932 12:19:45.642247 <30>[ 20.687500] systemd[1]: modprobe@drm.service: Succeeded.
10933 12:19:45.649167 <30>[ 20.694613] systemd[1]: Finished Load Kernel Module drm.
10934 12:19:45.659612 <3>[ 20.695323] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 12:19:45.666210 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10936 12:19:45.683105 <30>[ 20.728173] systemd[1]: modprobe@fuse.service: Succeeded.
10937 12:19:45.693077 <3>[ 20.732810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 12:19:45.696781 <30>[ 20.735535] systemd[1]: Finished Load Kernel Module fuse.
10939 12:19:45.703161 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10940 12:19:45.725188 <3>[ 20.767564] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 12:19:45.734691 <30>[ 20.779594] systemd[1]: Finished Load Kernel Modules.
10942 12:19:45.740912 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10943 12:19:45.758345 <3>[ 20.800050] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 12:19:45.764655 <30>[ 20.800286] systemd[1]: Finished Remount Root and Kernel File Systems.
10945 12:19:45.774562 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10946 12:19:45.793981 <3>[ 20.835996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 12:19:45.811748 <30>[ 20.856958] systemd[1]: Mounting FUSE Control File System...
10948 12:19:45.818535 Mounting [0;1;39mFUSE Control File System[0m...
10949 12:19:45.830407 <3>[ 20.872523] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10950 12:19:45.844599 <30>[ 20.886648] systemd[1]: Mounting Kernel Configuration File System...
10951 12:19:45.847857 Mounting [0;1;39mKernel Configuration File System[0m...
10952 12:19:45.872798 <30>[ 20.914937] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10953 12:19:45.883104 <30>[ 20.924036] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10954 12:19:45.891226 <30>[ 20.936896] systemd[1]: Starting Load/Save Random Seed...
10955 12:19:45.898310 Starting [0;1;39mLoad/Save Random Seed[0m...
10956 12:19:45.917525 <30>[ 20.963323] systemd[1]: Starting Apply Kernel Variables...
10957 12:19:45.924941 Starting [0;1;39mApply Kernel Variables[0m...
10958 12:19:45.941089 <30>[ 20.986815] systemd[1]: Starting Create System Users...
10959 12:19:45.948660 Starting [0;1;39mCreate System Users[0m...
10960 12:19:45.962855 <30>[ 21.008312] systemd[1]: Started Journal Service.
10961 12:19:45.969565 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10962 12:19:46.001518 [[0;32m OK [0m] Mounted [0;<4>[ 21.034964] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10963 12:19:46.011546 1;39mFUSE Contro<3>[ 21.052028] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10964 12:19:46.011680 l File System[0m.
10965 12:19:46.031659 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10966 12:19:46.044743 See 'systemctl status systemd-udev-trigger.service' for details.
10967 12:19:46.065828 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10968 12:19:46.086971 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10969 12:19:46.095167 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10970 12:19:46.119274 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10971 12:19:46.178558 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10972 12:19:46.195486 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10973 12:19:46.232370 <46>[ 21.274775] systemd-journald[296]: Received client request to flush runtime journal.
10974 12:19:46.997115 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10975 12:19:47.009498 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10976 12:19:47.025394 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10977 12:19:47.089537 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10978 12:19:47.648980 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10979 12:19:47.705754 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10980 12:19:47.761115 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10981 12:19:47.821808 Starting [0;1;39mNetwork Service[0m...
10982 12:19:48.142397 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10983 12:19:48.163987 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10984 12:19:48.193568 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10985 12:19:48.470949 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10986 12:19:48.488246 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10987 12:19:48.530116 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10988 12:19:48.576799 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10989 12:19:48.594145 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10990 12:19:48.609721 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10991 12:19:48.630128 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10992 12:19:48.681700 Starting [0;1;39mNetwork Name Resolution[0m...
10993 12:19:48.705264 Starting [0;1;39mNetwork Time Synchronization[0m...
10994 12:19:48.723493 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10995 12:19:48.795335 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10996 12:19:48.928105 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10997 12:19:48.945510 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10998 12:19:48.964327 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10999 12:19:48.977102 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11000 12:19:48.994445 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11001 12:19:49.147108 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11002 12:19:49.185186 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11003 12:19:49.213844 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11004 12:19:49.254062 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11005 12:19:49.268967 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11006 12:19:49.542324 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11007 12:19:49.560542 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11008 12:19:49.576890 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11009 12:19:49.617272 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11010 12:19:50.061670 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11011 12:19:50.447937 Starting [0;1;39mUser Login Management[0m...
11012 12:19:50.468947 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11013 12:19:50.490571 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11014 12:19:50.509306 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11015 12:19:50.551572 Starting [0;1;39mPermit User Sessions[0m...
11016 12:19:50.669103 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11017 12:19:50.719957 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11018 12:19:50.765826 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11019 12:19:50.785800 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11020 12:19:50.813231 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11021 12:19:50.834377 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11022 12:19:50.855167 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11023 12:19:50.877823 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11024 12:19:50.930939 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11025 12:19:50.981377 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11026 12:19:51.056767
11027 12:19:51.056959
11028 12:19:51.060803 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11029 12:19:51.060895
11030 12:19:51.063417 debian-bullseye-arm64 login: root (automatic login)
11031 12:19:51.063499
11032 12:19:51.063568
11033 12:19:51.443903 Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64
11034 12:19:51.444046
11035 12:19:51.450549 The programs included with the Debian GNU/Linux system are free software;
11036 12:19:51.457189 the exact distribution terms for each program are described in the
11037 12:19:51.460518 individual files in /usr/share/doc/*/copyright.
11038 12:19:51.460598
11039 12:19:51.467128 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11040 12:19:51.470225 permitted by applicable law.
11041 12:19:52.395248 Matched prompt #10: / #
11043 12:19:52.395538 Setting prompt string to ['/ #']
11044 12:19:52.395632 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11046 12:19:52.395824 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11047 12:19:52.395911 start: 2.2.6 expect-shell-connection (timeout 00:03:05) [common]
11048 12:19:52.395979 Setting prompt string to ['/ #']
11049 12:19:52.396039 Forcing a shell prompt, looking for ['/ #']
11051 12:19:52.446256 / #
11052 12:19:52.446375 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11053 12:19:52.446452 Waiting using forced prompt support (timeout 00:02:30)
11054 12:19:52.451222
11055 12:19:52.451496 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11056 12:19:52.451596 start: 2.2.7 export-device-env (timeout 00:03:05) [common]
11058 12:19:52.551904 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893105/extract-nfsrootfs-gf_o5kdg'
11059 12:19:52.557405 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893105/extract-nfsrootfs-gf_o5kdg'
11061 12:19:52.657911 / # export NFS_SERVER_IP='192.168.201.1'
11062 12:19:52.663316 export NFS_SERVER_IP='192.168.201.1'
11063 12:19:52.663613 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11064 12:19:52.663720 end: 2.2 depthcharge-retry (duration 00:01:55) [common]
11065 12:19:52.663815 end: 2 depthcharge-action (duration 00:01:55) [common]
11066 12:19:52.663930 start: 3 lava-test-retry (timeout 00:07:03) [common]
11067 12:19:52.664066 start: 3.1 lava-test-shell (timeout 00:07:03) [common]
11068 12:19:52.664182 Using namespace: common
11070 12:19:52.764498 / # #
11071 12:19:52.764676 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11072 12:19:52.769417 #
11073 12:19:52.769684 Using /lava-11893105
11075 12:19:52.870055 / # export SHELL=/bin/bash
11076 12:19:52.875064 export SHELL=/bin/bash
11078 12:19:52.975613 / # . /lava-11893105/environment
11079 12:19:52.980887 . /lava-11893105/environment
11081 12:19:53.087720 / # /lava-11893105/bin/lava-test-runner /lava-11893105/0
11082 12:19:53.087871 Test shell timeout: 10s (minimum of the action and connection timeout)
11083 12:19:53.092926 /lava-11893105/bin/lava-test-runner /lava-11893105/0
11084 12:19:53.423544 + export TESTRUN_ID=0_timesync-off
11085 12:19:53.426934 + TESTRUN_ID=0_timesync-off
11086 12:19:53.430204 + cd /lava-11893105/0/tests/0_timesync-off
11087 12:19:53.433813 ++ cat uuid
11088 12:19:53.439838 + UUID=11893105_1.6.2.3.1
11089 12:19:53.439977 + set +x
11090 12:19:53.446634 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11893105_1.6.2.3.1>
11091 12:19:53.446892 Received signal: <STARTRUN> 0_timesync-off 11893105_1.6.2.3.1
11092 12:19:53.446972 Starting test lava.0_timesync-off (11893105_1.6.2.3.1)
11093 12:19:53.447064 Skipping test definition patterns.
11094 12:19:53.449785 + systemctl stop systemd-timesyncd
11095 12:19:53.518145 + set +x
11096 12:19:53.521215 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11893105_1.6.2.3.1>
11097 12:19:53.521469 Received signal: <ENDRUN> 0_timesync-off 11893105_1.6.2.3.1
11098 12:19:53.521555 Ending use of test pattern.
11099 12:19:53.521618 Ending test lava.0_timesync-off (11893105_1.6.2.3.1), duration 0.07
11101 12:19:53.606139 + export TESTRUN_ID=1_kselftest-rtc
11102 12:19:53.609416 + TESTRUN_ID=1_kselftest-rtc
11103 12:19:53.612857 + cd /lava-11893105/0/tests/1_kselftest-rtc
11104 12:19:53.616050 ++ cat uuid
11105 12:19:53.622892 + UUID=11893105_1.6.2.3.5
11106 12:19:53.622970 + set +x
11107 12:19:53.629454 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 11893105_1.6.2.3.5>
11108 12:19:53.629732 Received signal: <STARTRUN> 1_kselftest-rtc 11893105_1.6.2.3.5
11109 12:19:53.629807 Starting test lava.1_kselftest-rtc (11893105_1.6.2.3.5)
11110 12:19:53.629888 Skipping test definition patterns.
11111 12:19:53.632759 + cd ./automated/linux/kselftest/
11112 12:19:53.659659 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11113 12:19:53.703098 INFO: install_deps skipped
11114 12:19:53.828530 --2023-10-27 12:19:53-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11115 12:19:53.851372 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11116 12:19:53.980645 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11117 12:19:54.109900 HTTP request sent, awaiting response... 200 OK
11118 12:19:54.112957 Length: 2956332 (2.8M) [application/octet-stream]
11119 12:19:54.116360 Saving to: 'kselftest.tar.xz'
11120 12:19:54.116449
11121 12:19:54.116515
11122 12:19:54.368001 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11123 12:19:54.679842 kselftest.tar.xz 1%[ ] 47.81K 186KB/s
11124 12:19:54.886649 kselftest.tar.xz 6%[> ] 187.80K 330KB/s
11125 12:19:55.111543 kselftest.tar.xz 17%[==> ] 512.55K 662KB/s
11126 12:19:55.325474 kselftest.tar.xz 27%[====> ] 790.19K 790KB/s
11127 12:19:55.530667 kselftest.tar.xz 37%[======> ] 1.07M 900KB/s
11128 12:19:55.755780 kselftest.tar.xz 43%[=======> ] 1.23M 888KB/s
11129 12:19:55.969194 kselftest.tar.xz 54%[=========> ] 1.54M 962KB/s
11130 12:19:56.173851 kselftest.tar.xz 66%[============> ] 1.88M 1.01MB/s
11131 12:19:56.401927 kselftest.tar.xz 73%[=============> ] 2.06M 1023KB/s
11132 12:19:56.614238 kselftest.tar.xz 85%[================> ] 2.40M 1.05MB/s
11133 12:19:56.693350 kselftest.tar.xz 97%[==================> ] 2.75M 1.10MB/s
11134 12:19:56.700130 kselftest.tar.xz 100%[===================>] 2.82M 1.09MB/s in 2.6s
11135 12:19:56.700269
11136 12:19:56.957434 2023-10-27 12:19:56 (1.09 MB/s) - 'kselftest.tar.xz' saved [2956332/2956332]
11137 12:19:56.957606
11138 12:20:03.948903 skiplist:
11139 12:20:03.952472 ========================================
11140 12:20:03.955112 ========================================
11141 12:20:04.015037 rtc:rtctest
11142 12:20:04.038386 ============== Tests to run ===============
11143 12:20:04.042345 rtc:rtctest
11144 12:20:04.044756 ===========End Tests to run ===============
11145 12:20:04.048947 shardfile-rtc pass
11146 12:20:04.156957 <12>[ 39.204512] kselftest: Running tests in rtc
11147 12:20:04.167357 TAP version 13
11148 12:20:04.182270 1..1
11149 12:20:04.218545 # selftests: rtc: rtctest
11150 12:20:04.692506 # TAP version 13
11151 12:20:04.692688 # 1..8
11152 12:20:04.695461 # # Starting 8 tests from 2 test cases.
11153 12:20:04.699051 # # RUN rtc.date_read ...
11154 12:20:04.705674 # # rtctest.c:49:date_read:Current RTC date/time is 27/10/2023 12:20:04.
11155 12:20:04.709058 # # OK rtc.date_read
11156 12:20:04.712376 # ok 1 rtc.date_read
11157 12:20:04.715828 # # RUN rtc.date_read_loop ...
11158 12:20:04.725744 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11159 12:20:11.106747 <6>[ 46.158377] vpu: disabling
11160 12:20:11.109942 <6>[ 46.161494] vproc2: disabling
11161 12:20:11.113567 <6>[ 46.164828] vproc1: disabling
11162 12:20:11.116507 <6>[ 46.168145] vaud18: disabling
11163 12:20:11.123413 <6>[ 46.171677] vsram_others: disabling
11164 12:20:11.126615 <6>[ 46.175655] va09: disabling
11165 12:20:11.129732 <6>[ 46.178833] vsram_md: disabling
11166 12:20:11.133687 <6>[ 46.182597] Vgpu: disabling
11167 12:20:35.014577 # # rtctest.c:115:date_read_loop:Performed 2654 RTC time reads.
11168 12:20:35.017954 # # OK rtc.date_read_loop
11169 12:20:35.021253 # ok 2 rtc.date_read_loop
11170 12:20:35.024798 # # RUN rtc.uie_read ...
11171 12:20:37.998459 # # OK rtc.uie_read
11172 12:20:38.001707 # ok 3 rtc.uie_read
11173 12:20:38.005025 # # RUN rtc.uie_select ...
11174 12:20:40.998932 # # OK rtc.uie_select
11175 12:20:41.001347 # ok 4 rtc.uie_select
11176 12:20:41.004569 # # RUN rtc.alarm_alm_set ...
11177 12:20:41.011536 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 12:20:44.
11178 12:20:41.015041 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11179 12:20:41.021435 # # alarm_alm_set: Test terminated by assertion
11180 12:20:41.024923 # # FAIL rtc.alarm_alm_set
11181 12:20:41.025380 # not ok 5 rtc.alarm_alm_set
11182 12:20:41.031459 # # RUN rtc.alarm_wkalm_set ...
11183 12:20:41.038000 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 27/10/2023 12:20:44.
11184 12:20:44.001017 # # OK rtc.alarm_wkalm_set
11185 12:20:44.001594 # ok 6 rtc.alarm_wkalm_set
11186 12:20:44.007203 # # RUN rtc.alarm_alm_set_minute ...
11187 12:20:44.010580 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 12:21:00.
11188 12:20:44.017115 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11189 12:20:44.024324 # # alarm_alm_set_minute: Test terminated by assertion
11190 12:20:44.027113 # # FAIL rtc.alarm_alm_set_minute
11191 12:20:44.030411 # not ok 7 rtc.alarm_alm_set_minute
11192 12:20:44.033942 # # RUN rtc.alarm_wkalm_set_minute ...
11193 12:20:44.040573 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 27/10/2023 12:21:00.
11194 12:20:59.997836 # # OK rtc.alarm_wkalm_set_minute
11195 12:21:00.001748 # ok 8 rtc.alarm_wkalm_set_minute
11196 12:21:00.005240 # # FAILED: 6 / 8 tests passed.
11197 12:21:00.007812 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11198 12:21:00.011135 not ok 1 selftests: rtc: rtctest # exit=1
11199 12:21:00.673251 rtc_rtctest_rtc_date_read pass
11200 12:21:00.676739 rtc_rtctest_rtc_date_read_loop pass
11201 12:21:00.679869 rtc_rtctest_rtc_uie_read pass
11202 12:21:00.683277 rtc_rtctest_rtc_uie_select pass
11203 12:21:00.686824 rtc_rtctest_rtc_alarm_alm_set fail
11204 12:21:00.690016 rtc_rtctest_rtc_alarm_wkalm_set pass
11205 12:21:00.693183 rtc_rtctest_rtc_alarm_alm_set_minute fail
11206 12:21:00.696577 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11207 12:21:00.700276 rtc_rtctest fail
11208 12:21:00.702927 + ../../utils/send-to-lava.sh ./output/result.txt
11209 12:21:00.796080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11210 12:21:00.796408 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11212 12:21:00.860007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11213 12:21:00.860278 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11215 12:21:00.931722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11216 12:21:00.932003 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11218 12:21:00.996624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11219 12:21:00.996903 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11221 12:21:01.065148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11222 12:21:01.065423 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11224 12:21:01.133465 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11226 12:21:01.136525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11227 12:21:01.205412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11228 12:21:01.206165 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11230 12:21:01.283693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11231 12:21:01.284449 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11233 12:21:01.356138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11234 12:21:01.356435 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11236 12:21:01.420106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11237 12:21:01.420217 + set +x
11238 12:21:01.420467 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11240 12:21:01.427131 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 11893105_1.6.2.3.5>
11241 12:21:01.427215 <LAVA_TEST_RUNNER EXIT>
11242 12:21:01.427452 Received signal: <ENDRUN> 1_kselftest-rtc 11893105_1.6.2.3.5
11243 12:21:01.427527 Ending use of test pattern.
11244 12:21:01.427588 Ending test lava.1_kselftest-rtc (11893105_1.6.2.3.5), duration 67.80
11246 12:21:01.427805 ok: lava_test_shell seems to have completed
11247 12:21:01.427935 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11248 12:21:01.428026 end: 3.1 lava-test-shell (duration 00:01:09) [common]
11249 12:21:01.428108 end: 3 lava-test-retry (duration 00:01:09) [common]
11250 12:21:01.428195 start: 4 finalize (timeout 00:05:54) [common]
11251 12:21:01.428284 start: 4.1 power-off (timeout 00:00:30) [common]
11252 12:21:01.428438 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11253 12:21:01.505303 >> Command sent successfully.
11254 12:21:01.507853 Returned 0 in 0 seconds
11255 12:21:01.608251 end: 4.1 power-off (duration 00:00:00) [common]
11257 12:21:01.608596 start: 4.2 read-feedback (timeout 00:05:54) [common]
11258 12:21:01.608854 Listened to connection for namespace 'common' for up to 1s
11259 12:21:01.609169 Listened to connection for namespace 'common' for up to 1s
11260 12:21:02.609584 Finalising connection for namespace 'common'
11261 12:21:02.610474 Disconnecting from shell: Finalise
11262 12:21:02.611166 / #
11263 12:21:02.712364 end: 4.2 read-feedback (duration 00:00:01) [common]
11264 12:21:02.713040 end: 4 finalize (duration 00:00:01) [common]
11265 12:21:02.713591 Cleaning after the job
11266 12:21:02.714212 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/ramdisk
11267 12:21:02.727009 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/kernel
11268 12:21:02.763396 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/dtb
11269 12:21:02.763706 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/nfsrootfs
11270 12:21:02.856193 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893105/tftp-deploy-_84d9rro/modules
11271 12:21:02.863395 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893105
11272 12:21:03.508472 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893105
11273 12:21:03.508680 Job finished correctly