Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 27
- Kernel Errors: 36
- Errors: 0
- Boot result: PASS
1 12:21:41.547522 lava-dispatcher, installed at version: 2023.08
2 12:21:41.547752 start: 0 validate
3 12:21:41.547892 Start time: 2023-10-27 12:21:41.547884+00:00 (UTC)
4 12:21:41.548028 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:21:41.548166 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:21:41.816207 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:21:41.816367 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:21:42.083035 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:21:42.083212 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:21:42.342373 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:21:42.342548 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:21:42.608093 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:21:42.608287 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:21:42.874695 validate duration: 1.33
16 12:21:42.875004 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:21:42.875104 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:21:42.875194 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:21:42.875318 Not decompressing ramdisk as can be used compressed.
20 12:21:42.875404 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:21:42.875467 saving as /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/ramdisk/initrd.cpio.gz
22 12:21:42.875554 total size: 4665395 (4 MB)
23 12:21:42.876629 progress 0 % (0 MB)
24 12:21:42.878336 progress 5 % (0 MB)
25 12:21:42.879698 progress 10 % (0 MB)
26 12:21:42.880972 progress 15 % (0 MB)
27 12:21:42.882290 progress 20 % (0 MB)
28 12:21:42.883585 progress 25 % (1 MB)
29 12:21:42.884884 progress 30 % (1 MB)
30 12:21:42.886182 progress 35 % (1 MB)
31 12:21:42.887483 progress 40 % (1 MB)
32 12:21:42.889014 progress 45 % (2 MB)
33 12:21:42.890278 progress 50 % (2 MB)
34 12:21:42.891613 progress 55 % (2 MB)
35 12:21:42.892880 progress 60 % (2 MB)
36 12:21:42.894147 progress 65 % (2 MB)
37 12:21:42.895486 progress 70 % (3 MB)
38 12:21:42.896793 progress 75 % (3 MB)
39 12:21:42.898093 progress 80 % (3 MB)
40 12:21:42.899586 progress 85 % (3 MB)
41 12:21:42.900859 progress 90 % (4 MB)
42 12:21:42.902282 progress 95 % (4 MB)
43 12:21:42.903625 progress 100 % (4 MB)
44 12:21:42.903796 4 MB downloaded in 0.03 s (157.55 MB/s)
45 12:21:42.903949 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:21:42.904187 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:21:42.904290 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:21:42.904377 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:21:42.904513 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:21:42.904585 saving as /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/kernel/Image
52 12:21:42.904646 total size: 49236480 (46 MB)
53 12:21:42.904711 No compression specified
54 12:21:42.905889 progress 0 % (0 MB)
55 12:21:42.919387 progress 5 % (2 MB)
56 12:21:42.932794 progress 10 % (4 MB)
57 12:21:42.946533 progress 15 % (7 MB)
58 12:21:42.960001 progress 20 % (9 MB)
59 12:21:42.973347 progress 25 % (11 MB)
60 12:21:42.986589 progress 30 % (14 MB)
61 12:21:42.999821 progress 35 % (16 MB)
62 12:21:43.013242 progress 40 % (18 MB)
63 12:21:43.026348 progress 45 % (21 MB)
64 12:21:43.039737 progress 50 % (23 MB)
65 12:21:43.053022 progress 55 % (25 MB)
66 12:21:43.066552 progress 60 % (28 MB)
67 12:21:43.080730 progress 65 % (30 MB)
68 12:21:43.095083 progress 70 % (32 MB)
69 12:21:43.109089 progress 75 % (35 MB)
70 12:21:43.122986 progress 80 % (37 MB)
71 12:21:43.136699 progress 85 % (39 MB)
72 12:21:43.149772 progress 90 % (42 MB)
73 12:21:43.162992 progress 95 % (44 MB)
74 12:21:43.176044 progress 100 % (46 MB)
75 12:21:43.176292 46 MB downloaded in 0.27 s (172.86 MB/s)
76 12:21:43.176444 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:21:43.176677 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:21:43.176786 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:21:43.176875 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:21:43.177017 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:21:43.177086 saving as /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/dtb/mt8192-asurada-spherion-r0.dtb
83 12:21:43.177147 total size: 47278 (0 MB)
84 12:21:43.177208 No compression specified
85 12:21:43.178349 progress 69 % (0 MB)
86 12:21:43.178622 progress 100 % (0 MB)
87 12:21:43.178873 0 MB downloaded in 0.00 s (26.16 MB/s)
88 12:21:43.178999 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:21:43.179220 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:21:43.179303 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:21:43.179410 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:21:43.179525 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:21:43.179595 saving as /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/nfsrootfs/full.rootfs.tar
95 12:21:43.179657 total size: 200813988 (191 MB)
96 12:21:43.179718 Using unxz to decompress xz
97 12:21:43.184181 progress 0 % (0 MB)
98 12:21:43.714899 progress 5 % (9 MB)
99 12:21:44.247512 progress 10 % (19 MB)
100 12:21:44.893064 progress 15 % (28 MB)
101 12:21:45.281728 progress 20 % (38 MB)
102 12:21:45.616145 progress 25 % (47 MB)
103 12:21:46.234270 progress 30 % (57 MB)
104 12:21:46.837320 progress 35 % (67 MB)
105 12:21:47.496331 progress 40 % (76 MB)
106 12:21:48.084304 progress 45 % (86 MB)
107 12:21:48.718864 progress 50 % (95 MB)
108 12:21:49.422990 progress 55 % (105 MB)
109 12:21:50.173293 progress 60 % (114 MB)
110 12:21:50.295692 progress 65 % (124 MB)
111 12:21:50.441805 progress 70 % (134 MB)
112 12:21:50.541294 progress 75 % (143 MB)
113 12:21:50.614825 progress 80 % (153 MB)
114 12:21:50.686635 progress 85 % (162 MB)
115 12:21:50.790304 progress 90 % (172 MB)
116 12:21:51.075022 progress 95 % (181 MB)
117 12:21:51.662133 progress 100 % (191 MB)
118 12:21:51.667538 191 MB downloaded in 8.49 s (22.56 MB/s)
119 12:21:51.667805 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:21:51.668101 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:21:51.668193 start: 1.5 download-retry (timeout 00:09:51) [common]
123 12:21:51.668281 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 12:21:51.668434 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:21:51.668506 saving as /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/modules/modules.tar
126 12:21:51.668585 total size: 8625084 (8 MB)
127 12:21:51.668665 Using unxz to decompress xz
128 12:21:51.673245 progress 0 % (0 MB)
129 12:21:51.695528 progress 5 % (0 MB)
130 12:21:51.718124 progress 10 % (0 MB)
131 12:21:51.744664 progress 15 % (1 MB)
132 12:21:51.770051 progress 20 % (1 MB)
133 12:21:51.796381 progress 25 % (2 MB)
134 12:21:51.822636 progress 30 % (2 MB)
135 12:21:51.850252 progress 35 % (2 MB)
136 12:21:51.875625 progress 40 % (3 MB)
137 12:21:51.900266 progress 45 % (3 MB)
138 12:21:51.926960 progress 50 % (4 MB)
139 12:21:51.957503 progress 55 % (4 MB)
140 12:21:51.987982 progress 60 % (4 MB)
141 12:21:52.017316 progress 65 % (5 MB)
142 12:21:52.048055 progress 70 % (5 MB)
143 12:21:52.075655 progress 75 % (6 MB)
144 12:21:52.108381 progress 80 % (6 MB)
145 12:21:52.145332 progress 85 % (7 MB)
146 12:21:52.178125 progress 90 % (7 MB)
147 12:21:52.206612 progress 95 % (7 MB)
148 12:21:52.230335 progress 100 % (8 MB)
149 12:21:52.235265 8 MB downloaded in 0.57 s (14.52 MB/s)
150 12:21:52.235529 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:21:52.235822 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:21:52.235934 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:21:52.236051 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:21:56.245189 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11893144/extract-nfsrootfs-s136c99f
156 12:21:56.245385 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:21:56.245484 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:21:56.245672 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r
159 12:21:56.245811 makedir: /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin
160 12:21:56.245917 makedir: /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/tests
161 12:21:56.246023 makedir: /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/results
162 12:21:56.246133 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-add-keys
163 12:21:56.246283 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-add-sources
164 12:21:56.246418 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-background-process-start
165 12:21:56.246555 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-background-process-stop
166 12:21:56.246688 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-common-functions
167 12:21:56.246859 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-echo-ipv4
168 12:21:56.246985 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-install-packages
169 12:21:56.247122 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-installed-packages
170 12:21:56.247246 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-os-build
171 12:21:56.247374 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-probe-channel
172 12:21:56.247506 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-probe-ip
173 12:21:56.247637 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-target-ip
174 12:21:56.247764 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-target-mac
175 12:21:56.247890 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-target-storage
176 12:21:56.248027 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-test-case
177 12:21:56.248157 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-test-event
178 12:21:56.248323 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-test-feedback
179 12:21:56.248447 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-test-raise
180 12:21:56.248584 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-test-reference
181 12:21:56.248710 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-test-runner
182 12:21:56.248838 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-test-set
183 12:21:56.249002 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-test-shell
184 12:21:56.249135 Updating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-add-keys (debian)
185 12:21:56.249292 Updating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-add-sources (debian)
186 12:21:56.249441 Updating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-install-packages (debian)
187 12:21:56.249599 Updating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-installed-packages (debian)
188 12:21:56.249747 Updating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/bin/lava-os-build (debian)
189 12:21:56.249874 Creating /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/environment
190 12:21:56.249984 LAVA metadata
191 12:21:56.250059 - LAVA_JOB_ID=11893144
192 12:21:56.250123 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:21:56.250226 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:21:56.250293 skipped lava-vland-overlay
195 12:21:56.250367 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:21:56.250452 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:21:56.250536 skipped lava-multinode-overlay
198 12:21:56.250622 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:21:56.250703 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:21:56.250808 Loading test definitions
201 12:21:56.250898 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:21:56.250980 Using /lava-11893144 at stage 0
203 12:21:56.251267 uuid=11893144_1.6.2.3.1 testdef=None
204 12:21:56.251356 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:21:56.251451 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:21:56.251929 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:21:56.252155 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:21:56.252734 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:21:56.253004 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:21:56.253561 runner path: /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/0/tests/0_timesync-off test_uuid 11893144_1.6.2.3.1
213 12:21:56.253723 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:21:56.253950 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:21:56.254033 Using /lava-11893144 at stage 0
217 12:21:56.254134 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:21:56.254212 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/0/tests/1_kselftest-tpm2'
219 12:22:03.353017 Running '/usr/bin/git checkout kernelci.org
220 12:22:03.508925 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 12:22:03.509714 uuid=11893144_1.6.2.3.5 testdef=None
222 12:22:03.509888 end: 1.6.2.3.5 git-repo-action (duration 00:00:07) [common]
224 12:22:03.510156 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 12:22:03.510964 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:22:03.511206 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 12:22:03.512398 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:22:03.512645 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 12:22:03.513643 runner path: /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/0/tests/1_kselftest-tpm2 test_uuid 11893144_1.6.2.3.5
232 12:22:03.513740 BOARD='mt8192-asurada-spherion-r0'
233 12:22:03.513806 BRANCH='cip-gitlab'
234 12:22:03.513867 SKIPFILE='/dev/null'
235 12:22:03.513930 SKIP_INSTALL='True'
236 12:22:03.514020 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:22:03.514082 TST_CASENAME=''
238 12:22:03.514142 TST_CMDFILES='tpm2'
239 12:22:03.514298 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:22:03.514513 Creating lava-test-runner.conf files
242 12:22:03.514584 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893144/lava-overlay-5399nr4r/lava-11893144/0 for stage 0
243 12:22:03.514681 - 0_timesync-off
244 12:22:03.514768 - 1_kselftest-tpm2
245 12:22:03.514877 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 12:22:03.514968 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 12:22:11.209923 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:22:11.210087 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 12:22:11.210223 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:22:11.210330 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 12:22:11.210422 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 12:22:11.337983 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:22:11.338428 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 12:22:11.338589 extracting modules file /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893144/extract-nfsrootfs-s136c99f
255 12:22:11.616257 extracting modules file /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893144/extract-overlay-ramdisk-sn365ufy/ramdisk
256 12:22:11.866603 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 12:22:11.866865 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 12:22:11.867060 [common] Applying overlay to NFS
259 12:22:11.867165 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893144/compress-overlay-nxhf94gp/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893144/extract-nfsrootfs-s136c99f
260 12:22:12.816361 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:22:12.816557 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 12:22:12.816654 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:22:12.816749 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 12:22:12.816832 Building ramdisk /var/lib/lava/dispatcher/tmp/11893144/extract-overlay-ramdisk-sn365ufy/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893144/extract-overlay-ramdisk-sn365ufy/ramdisk
265 12:22:13.124321 >> 119370 blocks
266 12:22:15.076576 rename /var/lib/lava/dispatcher/tmp/11893144/extract-overlay-ramdisk-sn365ufy/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/ramdisk/ramdisk.cpio.gz
267 12:22:15.077013 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:22:15.077138 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 12:22:15.077242 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 12:22:15.077352 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/kernel/Image'
271 12:22:27.845470 Returned 0 in 12 seconds
272 12:22:27.946108 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/kernel/image.itb
273 12:22:28.295350 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:22:28.295715 output: Created: Fri Oct 27 13:22:28 2023
275 12:22:28.295786 output: Image 0 (kernel-1)
276 12:22:28.295851 output: Description:
277 12:22:28.295916 output: Created: Fri Oct 27 13:22:28 2023
278 12:22:28.295976 output: Type: Kernel Image
279 12:22:28.296038 output: Compression: lzma compressed
280 12:22:28.296096 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
281 12:22:28.296155 output: Architecture: AArch64
282 12:22:28.296213 output: OS: Linux
283 12:22:28.296271 output: Load Address: 0x00000000
284 12:22:28.296326 output: Entry Point: 0x00000000
285 12:22:28.296384 output: Hash algo: crc32
286 12:22:28.296439 output: Hash value: d33b93ae
287 12:22:28.296498 output: Image 1 (fdt-1)
288 12:22:28.296553 output: Description: mt8192-asurada-spherion-r0
289 12:22:28.296605 output: Created: Fri Oct 27 13:22:28 2023
290 12:22:28.296658 output: Type: Flat Device Tree
291 12:22:28.296711 output: Compression: uncompressed
292 12:22:28.296763 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:22:28.296815 output: Architecture: AArch64
294 12:22:28.296866 output: Hash algo: crc32
295 12:22:28.296918 output: Hash value: cc4352de
296 12:22:28.296970 output: Image 2 (ramdisk-1)
297 12:22:28.297021 output: Description: unavailable
298 12:22:28.297073 output: Created: Fri Oct 27 13:22:28 2023
299 12:22:28.297125 output: Type: RAMDisk Image
300 12:22:28.297176 output: Compression: Unknown Compression
301 12:22:28.297228 output: Data Size: 17791311 Bytes = 17374.33 KiB = 16.97 MiB
302 12:22:28.297279 output: Architecture: AArch64
303 12:22:28.297331 output: OS: Linux
304 12:22:28.297407 output: Load Address: unavailable
305 12:22:28.297462 output: Entry Point: unavailable
306 12:22:28.297514 output: Hash algo: crc32
307 12:22:28.297566 output: Hash value: e2563a25
308 12:22:28.297619 output: Default Configuration: 'conf-1'
309 12:22:28.297671 output: Configuration 0 (conf-1)
310 12:22:28.297722 output: Description: mt8192-asurada-spherion-r0
311 12:22:28.297774 output: Kernel: kernel-1
312 12:22:28.297826 output: Init Ramdisk: ramdisk-1
313 12:22:28.297877 output: FDT: fdt-1
314 12:22:28.297929 output: Loadables: kernel-1
315 12:22:28.297980 output:
316 12:22:28.298190 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:22:28.298291 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:22:28.298393 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 12:22:28.298488 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
320 12:22:28.298563 No LXC device requested
321 12:22:28.298640 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:22:28.298731 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
323 12:22:28.298844 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:22:28.298923 Checking files for TFTP limit of 4294967296 bytes.
325 12:22:28.299439 end: 1 tftp-deploy (duration 00:00:45) [common]
326 12:22:28.299555 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:22:28.299652 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:22:28.299780 substitutions:
329 12:22:28.299847 - {DTB}: 11893144/tftp-deploy-1bt2atx6/dtb/mt8192-asurada-spherion-r0.dtb
330 12:22:28.299913 - {INITRD}: 11893144/tftp-deploy-1bt2atx6/ramdisk/ramdisk.cpio.gz
331 12:22:28.299973 - {KERNEL}: 11893144/tftp-deploy-1bt2atx6/kernel/Image
332 12:22:28.300037 - {LAVA_MAC}: None
333 12:22:28.300097 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11893144/extract-nfsrootfs-s136c99f
334 12:22:28.300157 - {NFS_SERVER_IP}: 192.168.201.1
335 12:22:28.300215 - {PRESEED_CONFIG}: None
336 12:22:28.300270 - {PRESEED_LOCAL}: None
337 12:22:28.300324 - {RAMDISK}: 11893144/tftp-deploy-1bt2atx6/ramdisk/ramdisk.cpio.gz
338 12:22:28.300378 - {ROOT_PART}: None
339 12:22:28.300432 - {ROOT}: None
340 12:22:28.300485 - {SERVER_IP}: 192.168.201.1
341 12:22:28.300539 - {TEE}: None
342 12:22:28.300592 Parsed boot commands:
343 12:22:28.300644 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:22:28.300821 Parsed boot commands: tftpboot 192.168.201.1 11893144/tftp-deploy-1bt2atx6/kernel/image.itb 11893144/tftp-deploy-1bt2atx6/kernel/cmdline
345 12:22:28.300909 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:22:28.300991 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:22:28.301081 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:22:28.301166 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:22:28.301237 Not connected, no need to disconnect.
350 12:22:28.301309 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:22:28.301390 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:22:28.301456 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 12:22:28.305640 Setting prompt string to ['lava-test: # ']
354 12:22:28.306010 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:22:28.306114 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:22:28.306216 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:22:28.306330 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:22:28.306589 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 12:22:33.442678 >> Command sent successfully.
360 12:22:33.445157 Returned 0 in 5 seconds
361 12:22:33.545578 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:22:33.545927 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:22:33.546030 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:22:33.546120 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:22:33.546187 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:22:33.546257 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:22:33.546529 [Enter `^Ec?' for help]
369 12:22:33.718691
370 12:22:33.718896
371 12:22:33.719028 F0: 102B 0000
372 12:22:33.719102
373 12:22:33.722102 F3: 1001 0000 [0200]
374 12:22:33.722175
375 12:22:33.722235 F3: 1001 0000
376 12:22:33.722302
377 12:22:33.722360 F7: 102D 0000
378 12:22:33.722415
379 12:22:33.725383 F1: 0000 0000
380 12:22:33.725454
381 12:22:33.725514 V0: 0000 0000 [0001]
382 12:22:33.725587
383 12:22:33.728788 00: 0007 8000
384 12:22:33.728867
385 12:22:33.728926 01: 0000 0000
386 12:22:33.728994
387 12:22:33.732765 BP: 0C00 0209 [0000]
388 12:22:33.732853
389 12:22:33.732916 G0: 1182 0000
390 12:22:33.732973
391 12:22:33.735755 EC: 0000 0021 [4000]
392 12:22:33.735833
393 12:22:33.735895 S7: 0000 0000 [0000]
394 12:22:33.735963
395 12:22:33.739343 CC: 0000 0000 [0001]
396 12:22:33.739438
397 12:22:33.739502 T0: 0000 0040 [010F]
398 12:22:33.739572
399 12:22:33.739630 Jump to BL
400 12:22:33.739686
401 12:22:33.766383
402 12:22:33.766565
403 12:22:33.766666
404 12:22:33.774254 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:22:33.777817 ARM64: Exception handlers installed.
406 12:22:33.781489 ARM64: Testing exception
407 12:22:33.784450 ARM64: Done test exception
408 12:22:33.791382 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:22:33.801624 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:22:33.808224 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:22:33.818364 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:22:33.824966 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:22:33.831879 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:22:33.842479 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:22:33.849624 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:22:33.869001 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:22:33.872149 WDT: Last reset was cold boot
418 12:22:33.875883 SPI1(PAD0) initialized at 2873684 Hz
419 12:22:33.879135 SPI5(PAD0) initialized at 992727 Hz
420 12:22:33.882186 VBOOT: Loading verstage.
421 12:22:33.889032 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:22:33.892532 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:22:33.895608 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:22:33.898874 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:22:33.906288 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:22:33.913437 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:22:33.923921 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:22:33.924066
429 12:22:33.924135
430 12:22:33.934138 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:22:33.937402 ARM64: Exception handlers installed.
432 12:22:33.940802 ARM64: Testing exception
433 12:22:33.940898 ARM64: Done test exception
434 12:22:33.947924 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:22:33.950715 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:22:33.965204 Probing TPM: . done!
437 12:22:33.965363 TPM ready after 0 ms
438 12:22:33.971872 Connected to device vid:did:rid of 1ae0:0028:00
439 12:22:33.978771 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 12:22:34.036786 Initialized TPM device CR50 revision 0
441 12:22:34.048325 tlcl_send_startup: Startup return code is 0
442 12:22:34.048480 TPM: setup succeeded
443 12:22:34.060340 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:22:34.068618 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:22:34.081713 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:22:34.090036 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:22:34.092930 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:22:34.100263 in-header: 03 07 00 00 08 00 00 00
449 12:22:34.103591 in-data: aa e4 47 04 13 02 00 00
450 12:22:34.107494 Chrome EC: UHEPI supported
451 12:22:34.115324 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:22:34.119008 in-header: 03 ad 00 00 08 00 00 00
453 12:22:34.122997 in-data: 00 20 20 08 00 00 00 00
454 12:22:34.123124 Phase 1
455 12:22:34.126269 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:22:34.133678 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:22:34.137552 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:22:34.141069 Recovery requested (1009000e)
459 12:22:34.148982 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:22:34.154621 tlcl_extend: response is 0
461 12:22:34.164402 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:22:34.169599 tlcl_extend: response is 0
463 12:22:34.177058 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:22:34.196544 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:22:34.203379 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:22:34.203506
467 12:22:34.203575
468 12:22:34.213902 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:22:34.217354 ARM64: Exception handlers installed.
470 12:22:34.217459 ARM64: Testing exception
471 12:22:34.220780 ARM64: Done test exception
472 12:22:34.242207 pmic_efuse_setting: Set efuses in 11 msecs
473 12:22:34.245995 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:22:34.252251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:22:34.255990 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:22:34.259075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:22:34.266612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:22:34.270567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:22:34.274190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:22:34.281302 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:22:34.285352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:22:34.288580 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:22:34.292422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:22:34.300872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:22:34.304394 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:22:34.308068 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:22:34.315484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:22:34.319127 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:22:34.326376 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:22:34.330124 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:22:34.337368 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:22:34.341421 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:22:34.348714 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:22:34.352158 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:22:34.359789 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:22:34.363366 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:22:34.370988 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:22:34.375018 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:22:34.382267 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:22:34.386196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:22:34.393469 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:22:34.396936 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:22:34.400111 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:22:34.404641 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:22:34.411938 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:22:34.415560 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:22:34.422821 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:22:34.426653 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:22:34.430537 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:22:34.437613 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:22:34.442103 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:22:34.445593 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:22:34.449349 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:22:34.452724 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:22:34.460240 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:22:34.463886 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:22:34.467677 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:22:34.471664 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:22:34.475309 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:22:34.478855 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:22:34.486352 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:22:34.490246 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:22:34.494272 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:22:34.497527 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:22:34.504897 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:22:34.512495 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:22:34.519951 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:22:34.527263 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:22:34.534878 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:22:34.538586 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:22:34.541848 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:22:34.549558 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:22:34.556829 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
534 12:22:34.560535 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:22:34.563824 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:22:34.570935 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:22:34.579690 [RTC]rtc_get_frequency_meter,154: input=15, output=789
538 12:22:34.589403 [RTC]rtc_get_frequency_meter,154: input=23, output=978
539 12:22:34.598619 [RTC]rtc_get_frequency_meter,154: input=19, output=884
540 12:22:34.607974 [RTC]rtc_get_frequency_meter,154: input=17, output=838
541 12:22:34.617401 [RTC]rtc_get_frequency_meter,154: input=16, output=814
542 12:22:34.627226 [RTC]rtc_get_frequency_meter,154: input=15, output=790
543 12:22:34.637117 [RTC]rtc_get_frequency_meter,154: input=16, output=814
544 12:22:34.641274 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 12:22:34.644622 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 12:22:34.648515 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:22:34.655823 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:22:34.659559 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:22:34.663611 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:22:34.666924 ADC[4]: Raw value=901697 ID=7
551 12:22:34.667033 ADC[3]: Raw value=213336 ID=1
552 12:22:34.670907 RAM Code: 0x71
553 12:22:34.674735 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:22:34.678190 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:22:34.686023 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:22:34.693357 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:22:34.696550 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:22:34.700980 in-header: 03 07 00 00 08 00 00 00
559 12:22:34.704593 in-data: aa e4 47 04 13 02 00 00
560 12:22:34.708990 Chrome EC: UHEPI supported
561 12:22:34.715490 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:22:34.719614 in-header: 03 ed 00 00 08 00 00 00
563 12:22:34.719735 in-data: 80 20 60 08 00 00 00 00
564 12:22:34.723300 MRC: failed to locate region type 0.
565 12:22:34.730949 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:22:34.734783 DRAM-K: Running full calibration
567 12:22:34.738137 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:22:34.741841 header.status = 0x0
569 12:22:34.745265 header.version = 0x6 (expected: 0x6)
570 12:22:34.748853 header.size = 0xd00 (expected: 0xd00)
571 12:22:34.748961 header.flags = 0x0
572 12:22:34.756147 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:22:34.774528 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:22:34.782013 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:22:34.782152 dram_init: ddr_geometry: 2
576 12:22:34.786114 [EMI] MDL number = 2
577 12:22:34.786215 [EMI] Get MDL freq = 0
578 12:22:34.789357 dram_init: ddr_type: 0
579 12:22:34.793423 is_discrete_lpddr4: 1
580 12:22:34.793520 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:22:34.793587
582 12:22:34.797539
583 12:22:34.797647 [Bian_co] ETT version 0.0.0.1
584 12:22:34.801419 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:22:34.801509
586 12:22:34.805090 dramc_set_vcore_voltage set vcore to 650000
587 12:22:34.809154 Read voltage for 800, 4
588 12:22:34.809251 Vio18 = 0
589 12:22:34.812726 Vcore = 650000
590 12:22:34.812812 Vdram = 0
591 12:22:34.812877 Vddq = 0
592 12:22:34.812936 Vmddr = 0
593 12:22:34.816088 dram_init: config_dvfs: 1
594 12:22:34.820061 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:22:34.827398 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:22:34.831527 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 12:22:34.834636 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 12:22:34.837749 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 12:22:34.841475 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 12:22:34.844808 MEM_TYPE=3, freq_sel=18
601 12:22:34.847953 sv_algorithm_assistance_LP4_1600
602 12:22:34.851746 ============ PULL DRAM RESETB DOWN ============
603 12:22:34.854877 ========== PULL DRAM RESETB DOWN end =========
604 12:22:34.858570 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:22:34.861581 ===================================
606 12:22:34.864910 LPDDR4 DRAM CONFIGURATION
607 12:22:34.868596 ===================================
608 12:22:34.872175 EX_ROW_EN[0] = 0x0
609 12:22:34.872273 EX_ROW_EN[1] = 0x0
610 12:22:34.875317 LP4Y_EN = 0x0
611 12:22:34.875397 WORK_FSP = 0x0
612 12:22:34.878665 WL = 0x2
613 12:22:34.878805 RL = 0x2
614 12:22:34.881976 BL = 0x2
615 12:22:34.882056 RPST = 0x0
616 12:22:34.885400 RD_PRE = 0x0
617 12:22:34.885477 WR_PRE = 0x1
618 12:22:34.888554 WR_PST = 0x0
619 12:22:34.888630 DBI_WR = 0x0
620 12:22:34.892396 DBI_RD = 0x0
621 12:22:34.892485 OTF = 0x1
622 12:22:34.895569 ===================================
623 12:22:34.899045 ===================================
624 12:22:34.901984 ANA top config
625 12:22:34.905617 ===================================
626 12:22:34.908709 DLL_ASYNC_EN = 0
627 12:22:34.908801 ALL_SLAVE_EN = 1
628 12:22:34.912367 NEW_RANK_MODE = 1
629 12:22:34.915473 DLL_IDLE_MODE = 1
630 12:22:34.918926 LP45_APHY_COMB_EN = 1
631 12:22:34.919017 TX_ODT_DIS = 1
632 12:22:34.922657 NEW_8X_MODE = 1
633 12:22:34.925965 ===================================
634 12:22:34.929333 ===================================
635 12:22:34.932395 data_rate = 1600
636 12:22:34.936147 CKR = 1
637 12:22:34.938921 DQ_P2S_RATIO = 8
638 12:22:34.942605 ===================================
639 12:22:34.942718 CA_P2S_RATIO = 8
640 12:22:34.946269 DQ_CA_OPEN = 0
641 12:22:34.949053 DQ_SEMI_OPEN = 0
642 12:22:34.952525 CA_SEMI_OPEN = 0
643 12:22:34.955945 CA_FULL_RATE = 0
644 12:22:34.959272 DQ_CKDIV4_EN = 1
645 12:22:34.959370 CA_CKDIV4_EN = 1
646 12:22:34.962420 CA_PREDIV_EN = 0
647 12:22:34.966107 PH8_DLY = 0
648 12:22:34.969462 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:22:34.972703 DQ_AAMCK_DIV = 4
650 12:22:34.972803 CA_AAMCK_DIV = 4
651 12:22:34.976107 CA_ADMCK_DIV = 4
652 12:22:34.979611 DQ_TRACK_CA_EN = 0
653 12:22:34.983023 CA_PICK = 800
654 12:22:34.986359 CA_MCKIO = 800
655 12:22:34.989436 MCKIO_SEMI = 0
656 12:22:34.993791 PLL_FREQ = 3068
657 12:22:34.993894 DQ_UI_PI_RATIO = 32
658 12:22:34.997646 CA_UI_PI_RATIO = 0
659 12:22:35.001024 ===================================
660 12:22:35.004636 ===================================
661 12:22:35.004743 memory_type:LPDDR4
662 12:22:35.008359 GP_NUM : 10
663 12:22:35.012203 SRAM_EN : 1
664 12:22:35.012316 MD32_EN : 0
665 12:22:35.015799 ===================================
666 12:22:35.019774 [ANA_INIT] >>>>>>>>>>>>>>
667 12:22:35.019873 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:22:35.023339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:22:35.026919 ===================================
670 12:22:35.030815 data_rate = 1600,PCW = 0X7600
671 12:22:35.033476 ===================================
672 12:22:35.036855 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:22:35.040575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:22:35.047007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:22:35.053755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:22:35.057102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:22:35.060582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:22:35.060682 [ANA_INIT] flow start
679 12:22:35.063922 [ANA_INIT] PLL >>>>>>>>
680 12:22:35.064018 [ANA_INIT] PLL <<<<<<<<
681 12:22:35.067591 [ANA_INIT] MIDPI >>>>>>>>
682 12:22:35.071058 [ANA_INIT] MIDPI <<<<<<<<
683 12:22:35.074448 [ANA_INIT] DLL >>>>>>>>
684 12:22:35.074540 [ANA_INIT] flow end
685 12:22:35.077282 ============ LP4 DIFF to SE enter ============
686 12:22:35.084522 ============ LP4 DIFF to SE exit ============
687 12:22:35.084641 [ANA_INIT] <<<<<<<<<<<<<
688 12:22:35.087799 [Flow] Enable top DCM control >>>>>
689 12:22:35.090731 [Flow] Enable top DCM control <<<<<
690 12:22:35.094040 Enable DLL master slave shuffle
691 12:22:35.101017 ==============================================================
692 12:22:35.101139 Gating Mode config
693 12:22:35.108020 ==============================================================
694 12:22:35.111032 Config description:
695 12:22:35.117531 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:22:35.124517 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:22:35.131977 SELPH_MODE 0: By rank 1: By Phase
698 12:22:35.135121 ==============================================================
699 12:22:35.138190 GAT_TRACK_EN = 1
700 12:22:35.141581 RX_GATING_MODE = 2
701 12:22:35.145034 RX_GATING_TRACK_MODE = 2
702 12:22:35.148445 SELPH_MODE = 1
703 12:22:35.151339 PICG_EARLY_EN = 1
704 12:22:35.155083 VALID_LAT_VALUE = 1
705 12:22:35.158130 ==============================================================
706 12:22:35.161666 Enter into Gating configuration >>>>
707 12:22:35.165009 Exit from Gating configuration <<<<
708 12:22:35.168483 Enter into DVFS_PRE_config >>>>>
709 12:22:35.182252 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:22:35.185012 Exit from DVFS_PRE_config <<<<<
711 12:22:35.185109 Enter into PICG configuration >>>>
712 12:22:35.188585 Exit from PICG configuration <<<<
713 12:22:35.191786 [RX_INPUT] configuration >>>>>
714 12:22:35.195821 [RX_INPUT] configuration <<<<<
715 12:22:35.201879 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:22:35.205478 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:22:35.212355 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:22:35.220253 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:22:35.222883 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:22:35.229548 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:22:35.233181 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:22:35.239832 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:22:35.243123 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:22:35.246572 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:22:35.250231 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:22:35.256826 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:22:35.260286 ===================================
728 12:22:35.260391 LPDDR4 DRAM CONFIGURATION
729 12:22:35.263545 ===================================
730 12:22:35.266649 EX_ROW_EN[0] = 0x0
731 12:22:35.270131 EX_ROW_EN[1] = 0x0
732 12:22:35.270223 LP4Y_EN = 0x0
733 12:22:35.273720 WORK_FSP = 0x0
734 12:22:35.273815 WL = 0x2
735 12:22:35.277121 RL = 0x2
736 12:22:35.277209 BL = 0x2
737 12:22:35.280056 RPST = 0x0
738 12:22:35.280209 RD_PRE = 0x0
739 12:22:35.284215 WR_PRE = 0x1
740 12:22:35.284342 WR_PST = 0x0
741 12:22:35.286700 DBI_WR = 0x0
742 12:22:35.286873 DBI_RD = 0x0
743 12:22:35.290200 OTF = 0x1
744 12:22:35.294088 ===================================
745 12:22:35.296942 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:22:35.300372 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:22:35.303910 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:22:35.307447 ===================================
749 12:22:35.310507 LPDDR4 DRAM CONFIGURATION
750 12:22:35.313654 ===================================
751 12:22:35.317174 EX_ROW_EN[0] = 0x10
752 12:22:35.317341 EX_ROW_EN[1] = 0x0
753 12:22:35.320848 LP4Y_EN = 0x0
754 12:22:35.320991 WORK_FSP = 0x0
755 12:22:35.323923 WL = 0x2
756 12:22:35.324060 RL = 0x2
757 12:22:35.327213 BL = 0x2
758 12:22:35.327349 RPST = 0x0
759 12:22:35.330511 RD_PRE = 0x0
760 12:22:35.330618 WR_PRE = 0x1
761 12:22:35.334023 WR_PST = 0x0
762 12:22:35.334124 DBI_WR = 0x0
763 12:22:35.337694 DBI_RD = 0x0
764 12:22:35.337820 OTF = 0x1
765 12:22:35.340497 ===================================
766 12:22:35.347101 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:22:35.352183 nWR fixed to 40
768 12:22:35.355486 [ModeRegInit_LP4] CH0 RK0
769 12:22:35.355587 [ModeRegInit_LP4] CH0 RK1
770 12:22:35.358615 [ModeRegInit_LP4] CH1 RK0
771 12:22:35.362243 [ModeRegInit_LP4] CH1 RK1
772 12:22:35.362343 match AC timing 13
773 12:22:35.368869 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:22:35.372691 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:22:35.375518 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:22:35.382388 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:22:35.385609 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:22:35.385710 [EMI DOE] emi_dcm 0
779 12:22:35.392776 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:22:35.392890 ==
781 12:22:35.395824 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:22:35.399259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:22:35.399357 ==
784 12:22:35.405747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:22:35.409106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:22:35.420066 [CA 0] Center 37 (7~68) winsize 62
787 12:22:35.423250 [CA 1] Center 37 (7~68) winsize 62
788 12:22:35.426279 [CA 2] Center 35 (5~65) winsize 61
789 12:22:35.429568 [CA 3] Center 35 (5~65) winsize 61
790 12:22:35.432960 [CA 4] Center 34 (3~65) winsize 63
791 12:22:35.436745 [CA 5] Center 33 (3~64) winsize 62
792 12:22:35.436850
793 12:22:35.439717 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 12:22:35.439832
795 12:22:35.443239 [CATrainingPosCal] consider 1 rank data
796 12:22:35.446629 u2DelayCellTimex100 = 270/100 ps
797 12:22:35.449997 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 12:22:35.452912 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 12:22:35.459878 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
800 12:22:35.463024 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
801 12:22:35.466812 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 12:22:35.469649 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:22:35.469746
804 12:22:35.473602 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:22:35.473701
806 12:22:35.476323 [CBTSetCACLKResult] CA Dly = 33
807 12:22:35.476411 CS Dly: 5 (0~36)
808 12:22:35.476478 ==
809 12:22:35.479928 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:22:35.486609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:22:35.486770 ==
812 12:22:35.490227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:22:35.496671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:22:35.505784 [CA 0] Center 37 (6~68) winsize 63
815 12:22:35.509392 [CA 1] Center 37 (6~68) winsize 63
816 12:22:35.512729 [CA 2] Center 35 (4~66) winsize 63
817 12:22:35.515672 [CA 3] Center 35 (4~66) winsize 63
818 12:22:35.519507 [CA 4] Center 34 (4~64) winsize 61
819 12:22:35.522859 [CA 5] Center 33 (3~64) winsize 62
820 12:22:35.522955
821 12:22:35.525769 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 12:22:35.525857
823 12:22:35.529109 [CATrainingPosCal] consider 2 rank data
824 12:22:35.532894 u2DelayCellTimex100 = 270/100 ps
825 12:22:35.535946 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 12:22:35.539421 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 12:22:35.546297 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
828 12:22:35.549627 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
829 12:22:35.553271 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
830 12:22:35.556021 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:22:35.556129
832 12:22:35.559431 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:22:35.559536
834 12:22:35.562807 [CBTSetCACLKResult] CA Dly = 33
835 12:22:35.562905 CS Dly: 5 (0~37)
836 12:22:35.562974
837 12:22:35.565985 ----->DramcWriteLeveling(PI) begin...
838 12:22:35.566083 ==
839 12:22:35.569826 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:22:35.577019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:22:35.577168 ==
842 12:22:35.577240 Write leveling (Byte 0): 29 => 29
843 12:22:35.580409 Write leveling (Byte 1): 29 => 29
844 12:22:35.585116 DramcWriteLeveling(PI) end<-----
845 12:22:35.585237
846 12:22:35.585308 ==
847 12:22:35.588262 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:22:35.591805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:22:35.591899 ==
850 12:22:35.595231 [Gating] SW mode calibration
851 12:22:35.601971 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:22:35.608946 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:22:35.611971 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:22:35.615689 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 12:22:35.622445 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 12:22:35.625927 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
857 12:22:35.629110 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:22:35.632591 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:22:35.638888 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:22:35.642396 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:22:35.645890 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:22:35.652674 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:22:35.655980 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:22:35.659322 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:22:35.666273 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:22:35.669429 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:22:35.672823 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:22:35.676103 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:22:35.683178 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:22:35.686471 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:22:35.690047 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
872 12:22:35.696089 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 12:22:35.699584 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:22:35.703641 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:22:35.709981 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:22:35.713112 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:22:35.716640 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:22:35.723259 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:22:35.726377 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 12:22:35.729788 0 9 12 | B1->B0 | 2f2f 3434 | 0 0 | (1 1) (0 0)
881 12:22:35.733439 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:22:35.740363 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:22:35.743819 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:22:35.746711 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:22:35.753634 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:22:35.757360 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 12:22:35.760260 0 10 8 | B1->B0 | 3333 3030 | 0 0 | (0 0) (0 1)
888 12:22:35.766903 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
889 12:22:35.770393 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:22:35.773762 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:22:35.780546 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:22:35.783887 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:22:35.786860 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:22:35.790435 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 12:22:35.797110 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
896 12:22:35.800220 0 11 12 | B1->B0 | 3c3c 4545 | 1 0 | (0 0) (0 0)
897 12:22:35.803527 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:22:35.810670 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:22:35.814046 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:22:35.817465 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:22:35.823975 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:22:35.827321 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:22:35.830894 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 12:22:35.837565 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
905 12:22:35.841013 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:22:35.844274 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:22:35.847338 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:22:35.854448 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:22:35.857749 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:22:35.861088 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:22:35.867949 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:22:35.871082 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:22:35.874389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:22:35.881176 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:22:35.884191 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:22:35.888069 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:22:35.894659 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:22:35.897950 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
919 12:22:35.901335 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 12:22:35.907946 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 12:22:35.908065 Total UI for P1: 0, mck2ui 16
922 12:22:35.911377 best dqsien dly found for B0: ( 0, 14, 8)
923 12:22:35.914456 Total UI for P1: 0, mck2ui 16
924 12:22:35.917798 best dqsien dly found for B1: ( 0, 14, 6)
925 12:22:35.921246 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 12:22:35.924625 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
927 12:22:35.924725
928 12:22:35.931311 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 12:22:35.935009 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 12:22:35.935113 [Gating] SW calibration Done
931 12:22:35.938456 ==
932 12:22:35.941565 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:22:35.944765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:22:35.944865 ==
935 12:22:35.944953 RX Vref Scan: 0
936 12:22:35.945035
937 12:22:35.948364 RX Vref 0 -> 0, step: 1
938 12:22:35.948478
939 12:22:35.951606 RX Delay -130 -> 252, step: 16
940 12:22:35.955091 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 12:22:35.958433 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 12:22:35.961358 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 12:22:35.968799 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 12:22:35.971772 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 12:22:35.974864 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 12:22:35.978303 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 12:22:35.981502 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
948 12:22:35.988214 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
949 12:22:35.991529 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 12:22:35.995572 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 12:22:35.998760 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 12:22:36.002234 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 12:22:36.008427 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 12:22:36.011724 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 12:22:36.015312 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 12:22:36.015413 ==
957 12:22:36.018823 Dram Type= 6, Freq= 0, CH_0, rank 0
958 12:22:36.022138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 12:22:36.022235 ==
960 12:22:36.025527 DQS Delay:
961 12:22:36.025618 DQS0 = 0, DQS1 = 0
962 12:22:36.025685 DQM Delay:
963 12:22:36.029306 DQM0 = 84, DQM1 = 77
964 12:22:36.029399 DQ Delay:
965 12:22:36.032626 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 12:22:36.035746 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
967 12:22:36.038816 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
968 12:22:36.042153 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 12:22:36.042254
970 12:22:36.042321
971 12:22:36.042383 ==
972 12:22:36.045498 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:22:36.052114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:22:36.052231 ==
975 12:22:36.052329
976 12:22:36.052421
977 12:22:36.052488 TX Vref Scan disable
978 12:22:36.055964 == TX Byte 0 ==
979 12:22:36.059445 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 12:22:36.062246 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 12:22:36.066018 == TX Byte 1 ==
982 12:22:36.069372 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 12:22:36.072638 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 12:22:36.075880 ==
985 12:22:36.076003 Dram Type= 6, Freq= 0, CH_0, rank 0
986 12:22:36.082651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 12:22:36.082799 ==
988 12:22:36.094699 TX Vref=22, minBit 0, minWin=27, winSum=442
989 12:22:36.097920 TX Vref=24, minBit 5, minWin=27, winSum=446
990 12:22:36.101325 TX Vref=26, minBit 5, minWin=27, winSum=446
991 12:22:36.105116 TX Vref=28, minBit 9, minWin=27, winSum=449
992 12:22:36.108415 TX Vref=30, minBit 0, minWin=28, winSum=450
993 12:22:36.111435 TX Vref=32, minBit 12, minWin=27, winSum=452
994 12:22:36.118217 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 30
995 12:22:36.118341
996 12:22:36.121926 Final TX Range 1 Vref 30
997 12:22:36.122024
998 12:22:36.122096 ==
999 12:22:36.124866 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 12:22:36.128609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 12:22:36.128706 ==
1002 12:22:36.128773
1003 12:22:36.128835
1004 12:22:36.131750 TX Vref Scan disable
1005 12:22:36.135130 == TX Byte 0 ==
1006 12:22:36.138549 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 12:22:36.141923 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 12:22:36.145029 == TX Byte 1 ==
1009 12:22:36.148652 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 12:22:36.152080 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 12:22:36.152178
1012 12:22:36.155018 [DATLAT]
1013 12:22:36.155107 Freq=800, CH0 RK0
1014 12:22:36.155176
1015 12:22:36.158489 DATLAT Default: 0xa
1016 12:22:36.158599 0, 0xFFFF, sum = 0
1017 12:22:36.162283 1, 0xFFFF, sum = 0
1018 12:22:36.162382 2, 0xFFFF, sum = 0
1019 12:22:36.165670 3, 0xFFFF, sum = 0
1020 12:22:36.165760 4, 0xFFFF, sum = 0
1021 12:22:36.168581 5, 0xFFFF, sum = 0
1022 12:22:36.168711 6, 0xFFFF, sum = 0
1023 12:22:36.171956 7, 0xFFFF, sum = 0
1024 12:22:36.172075 8, 0xFFFF, sum = 0
1025 12:22:36.175571 9, 0x0, sum = 1
1026 12:22:36.175663 10, 0x0, sum = 2
1027 12:22:36.179020 11, 0x0, sum = 3
1028 12:22:36.179107 12, 0x0, sum = 4
1029 12:22:36.182100 best_step = 10
1030 12:22:36.182188
1031 12:22:36.182271 ==
1032 12:22:36.186157 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 12:22:36.189294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 12:22:36.189384 ==
1035 12:22:36.189449 RX Vref Scan: 1
1036 12:22:36.189511
1037 12:22:36.192394 Set Vref Range= 32 -> 127
1038 12:22:36.192480
1039 12:22:36.195776 RX Vref 32 -> 127, step: 1
1040 12:22:36.195863
1041 12:22:36.199095 RX Delay -95 -> 252, step: 8
1042 12:22:36.199183
1043 12:22:36.202696 Set Vref, RX VrefLevel [Byte0]: 32
1044 12:22:36.205912 [Byte1]: 32
1045 12:22:36.206002
1046 12:22:36.208864 Set Vref, RX VrefLevel [Byte0]: 33
1047 12:22:36.212346 [Byte1]: 33
1048 12:22:36.212436
1049 12:22:36.216108 Set Vref, RX VrefLevel [Byte0]: 34
1050 12:22:36.219418 [Byte1]: 34
1051 12:22:36.219516
1052 12:22:36.223019 Set Vref, RX VrefLevel [Byte0]: 35
1053 12:22:36.225853 [Byte1]: 35
1054 12:22:36.230095
1055 12:22:36.230224 Set Vref, RX VrefLevel [Byte0]: 36
1056 12:22:36.233464 [Byte1]: 36
1057 12:22:36.238041
1058 12:22:36.238143 Set Vref, RX VrefLevel [Byte0]: 37
1059 12:22:36.241470 [Byte1]: 37
1060 12:22:36.246136
1061 12:22:36.246251 Set Vref, RX VrefLevel [Byte0]: 38
1062 12:22:36.249637 [Byte1]: 38
1063 12:22:36.253484
1064 12:22:36.253581 Set Vref, RX VrefLevel [Byte0]: 39
1065 12:22:36.256932 [Byte1]: 39
1066 12:22:36.260742
1067 12:22:36.260846 Set Vref, RX VrefLevel [Byte0]: 40
1068 12:22:36.264224 [Byte1]: 40
1069 12:22:36.268438
1070 12:22:36.268538 Set Vref, RX VrefLevel [Byte0]: 41
1071 12:22:36.271538 [Byte1]: 41
1072 12:22:36.275492
1073 12:22:36.275621 Set Vref, RX VrefLevel [Byte0]: 42
1074 12:22:36.279203 [Byte1]: 42
1075 12:22:36.283547
1076 12:22:36.283647 Set Vref, RX VrefLevel [Byte0]: 43
1077 12:22:36.286887 [Byte1]: 43
1078 12:22:36.291017
1079 12:22:36.291110 Set Vref, RX VrefLevel [Byte0]: 44
1080 12:22:36.294062 [Byte1]: 44
1081 12:22:36.298280
1082 12:22:36.298384 Set Vref, RX VrefLevel [Byte0]: 45
1083 12:22:36.301679 [Byte1]: 45
1084 12:22:36.306272
1085 12:22:36.306372 Set Vref, RX VrefLevel [Byte0]: 46
1086 12:22:36.309628 [Byte1]: 46
1087 12:22:36.313524
1088 12:22:36.313619 Set Vref, RX VrefLevel [Byte0]: 47
1089 12:22:36.316808 [Byte1]: 47
1090 12:22:36.321419
1091 12:22:36.321517 Set Vref, RX VrefLevel [Byte0]: 48
1092 12:22:36.324699 [Byte1]: 48
1093 12:22:36.328700
1094 12:22:36.328793 Set Vref, RX VrefLevel [Byte0]: 49
1095 12:22:36.332322 [Byte1]: 49
1096 12:22:36.336361
1097 12:22:36.336455 Set Vref, RX VrefLevel [Byte0]: 50
1098 12:22:36.339712 [Byte1]: 50
1099 12:22:36.344279
1100 12:22:36.344382 Set Vref, RX VrefLevel [Byte0]: 51
1101 12:22:36.347674 [Byte1]: 51
1102 12:22:36.351640
1103 12:22:36.351746 Set Vref, RX VrefLevel [Byte0]: 52
1104 12:22:36.355147 [Byte1]: 52
1105 12:22:36.359075
1106 12:22:36.359173 Set Vref, RX VrefLevel [Byte0]: 53
1107 12:22:36.362872 [Byte1]: 53
1108 12:22:36.366653
1109 12:22:36.366791 Set Vref, RX VrefLevel [Byte0]: 54
1110 12:22:36.370089 [Byte1]: 54
1111 12:22:36.374336
1112 12:22:36.374437 Set Vref, RX VrefLevel [Byte0]: 55
1113 12:22:36.377992 [Byte1]: 55
1114 12:22:36.382314
1115 12:22:36.382423 Set Vref, RX VrefLevel [Byte0]: 56
1116 12:22:36.385687 [Byte1]: 56
1117 12:22:36.389596
1118 12:22:36.389691 Set Vref, RX VrefLevel [Byte0]: 57
1119 12:22:36.393201 [Byte1]: 57
1120 12:22:36.397143
1121 12:22:36.397238 Set Vref, RX VrefLevel [Byte0]: 58
1122 12:22:36.400403 [Byte1]: 58
1123 12:22:36.404773
1124 12:22:36.404870 Set Vref, RX VrefLevel [Byte0]: 59
1125 12:22:36.408157 [Byte1]: 59
1126 12:22:36.412398
1127 12:22:36.412530 Set Vref, RX VrefLevel [Byte0]: 60
1128 12:22:36.415813 [Byte1]: 60
1129 12:22:36.419813
1130 12:22:36.419907 Set Vref, RX VrefLevel [Byte0]: 61
1131 12:22:36.423219 [Byte1]: 61
1132 12:22:36.428025
1133 12:22:36.428133 Set Vref, RX VrefLevel [Byte0]: 62
1134 12:22:36.430847 [Byte1]: 62
1135 12:22:36.435524
1136 12:22:36.435625 Set Vref, RX VrefLevel [Byte0]: 63
1137 12:22:36.438670 [Byte1]: 63
1138 12:22:36.442708
1139 12:22:36.442848 Set Vref, RX VrefLevel [Byte0]: 64
1140 12:22:36.446204 [Byte1]: 64
1141 12:22:36.450566
1142 12:22:36.450666 Set Vref, RX VrefLevel [Byte0]: 65
1143 12:22:36.454123 [Byte1]: 65
1144 12:22:36.458028
1145 12:22:36.458121 Set Vref, RX VrefLevel [Byte0]: 66
1146 12:22:36.461293 [Byte1]: 66
1147 12:22:36.465698
1148 12:22:36.465792 Set Vref, RX VrefLevel [Byte0]: 67
1149 12:22:36.468868 [Byte1]: 67
1150 12:22:36.473345
1151 12:22:36.473443 Set Vref, RX VrefLevel [Byte0]: 68
1152 12:22:36.476495 [Byte1]: 68
1153 12:22:36.480589
1154 12:22:36.480682 Set Vref, RX VrefLevel [Byte0]: 69
1155 12:22:36.483913 [Byte1]: 69
1156 12:22:36.488476
1157 12:22:36.488574 Set Vref, RX VrefLevel [Byte0]: 70
1158 12:22:36.491673 [Byte1]: 70
1159 12:22:36.495893
1160 12:22:36.496002 Set Vref, RX VrefLevel [Byte0]: 71
1161 12:22:36.499272 [Byte1]: 71
1162 12:22:36.503597
1163 12:22:36.503696 Set Vref, RX VrefLevel [Byte0]: 72
1164 12:22:36.507032 [Byte1]: 72
1165 12:22:36.511376
1166 12:22:36.511469 Set Vref, RX VrefLevel [Byte0]: 73
1167 12:22:36.514998 [Byte1]: 73
1168 12:22:36.518656
1169 12:22:36.518770 Final RX Vref Byte 0 = 60 to rank0
1170 12:22:36.522135 Final RX Vref Byte 1 = 54 to rank0
1171 12:22:36.525434 Final RX Vref Byte 0 = 60 to rank1
1172 12:22:36.528882 Final RX Vref Byte 1 = 54 to rank1==
1173 12:22:36.532220 Dram Type= 6, Freq= 0, CH_0, rank 0
1174 12:22:36.539013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1175 12:22:36.539131 ==
1176 12:22:36.539198 DQS Delay:
1177 12:22:36.539290 DQS0 = 0, DQS1 = 0
1178 12:22:36.542269 DQM Delay:
1179 12:22:36.542365 DQM0 = 87, DQM1 = 78
1180 12:22:36.545574 DQ Delay:
1181 12:22:36.549114 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1182 12:22:36.549217 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1183 12:22:36.552445 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1184 12:22:36.555767 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1185 12:22:36.555872
1186 12:22:36.558695
1187 12:22:36.565450 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1188 12:22:36.568771 CH0 RK0: MR19=606, MR18=2910
1189 12:22:36.575967 CH0_RK0: MR19=0x606, MR18=0x2910, DQSOSC=399, MR23=63, INC=92, DEC=61
1190 12:22:36.576106
1191 12:22:36.578886 ----->DramcWriteLeveling(PI) begin...
1192 12:22:36.578976 ==
1193 12:22:36.582377 Dram Type= 6, Freq= 0, CH_0, rank 1
1194 12:22:36.585564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1195 12:22:36.585648 ==
1196 12:22:36.588952 Write leveling (Byte 0): 28 => 28
1197 12:22:36.592329 Write leveling (Byte 1): 28 => 28
1198 12:22:36.595786 DramcWriteLeveling(PI) end<-----
1199 12:22:36.595878
1200 12:22:36.595944 ==
1201 12:22:36.599371 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 12:22:36.602951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 12:22:36.603047 ==
1204 12:22:36.605980 [Gating] SW mode calibration
1205 12:22:36.612721 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1206 12:22:36.619698 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1207 12:22:36.623303 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1208 12:22:36.625957 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1209 12:22:36.629561 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1210 12:22:36.636355 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:22:36.639190 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:22:36.642683 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:22:36.649853 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:22:36.653417 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:22:36.696902 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:22:36.697403 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:22:36.697919 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:22:36.698001 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:22:36.698462 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:22:36.699000 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:22:36.699600 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:22:36.700165 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:22:36.700247 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:22:36.701009 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:22:36.729275 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1226 12:22:36.729632 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1227 12:22:36.729706 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:22:36.729768 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:22:36.729827 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:22:36.730380 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:22:36.733110 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:22:36.736718 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:22:36.736835 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1234 12:22:36.739890 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (1 1) (1 1)
1235 12:22:36.746860 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 12:22:36.750154 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 12:22:36.753614 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 12:22:36.760354 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 12:22:36.763291 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 12:22:36.766672 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1241 12:22:36.770200 0 10 8 | B1->B0 | 3030 2424 | 1 1 | (1 1) (1 0)
1242 12:22:36.776786 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1243 12:22:36.780113 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:22:36.783416 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:22:36.790509 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:22:36.793712 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:22:36.796814 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:22:36.803520 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:22:36.807357 0 11 8 | B1->B0 | 2929 3e3e | 0 0 | (0 0) (0 0)
1250 12:22:36.810249 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1251 12:22:36.817100 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 12:22:36.820469 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 12:22:36.824020 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 12:22:36.827899 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 12:22:36.831923 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 12:22:36.839704 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1257 12:22:36.842474 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1258 12:22:36.845994 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1259 12:22:36.849314 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:22:36.856932 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:22:36.860457 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:22:36.863491 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:22:36.866594 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:22:36.873510 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:22:36.877217 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:22:36.879931 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:22:36.886883 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:22:36.890177 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:22:36.893772 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:22:36.900211 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:22:36.904201 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:22:36.906896 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1273 12:22:36.910508 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1274 12:22:36.913862 Total UI for P1: 0, mck2ui 16
1275 12:22:36.917498 best dqsien dly found for B0: ( 0, 14, 4)
1276 12:22:36.924351 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 12:22:36.927547 Total UI for P1: 0, mck2ui 16
1278 12:22:36.930897 best dqsien dly found for B1: ( 0, 14, 8)
1279 12:22:36.933918 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1280 12:22:36.937239 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1281 12:22:36.937329
1282 12:22:36.941314 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1283 12:22:36.944018 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1284 12:22:36.947293 [Gating] SW calibration Done
1285 12:22:36.947382 ==
1286 12:22:36.950652 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:22:36.954163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:22:36.954259 ==
1289 12:22:36.957834 RX Vref Scan: 0
1290 12:22:36.957923
1291 12:22:36.957988 RX Vref 0 -> 0, step: 1
1292 12:22:36.958048
1293 12:22:36.960715 RX Delay -130 -> 252, step: 16
1294 12:22:36.964182 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1295 12:22:36.970885 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1296 12:22:36.974009 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1297 12:22:36.977651 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1298 12:22:36.980835 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1299 12:22:36.984661 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1300 12:22:36.987744 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1301 12:22:36.994401 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1302 12:22:36.997335 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1303 12:22:37.001272 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1304 12:22:37.004340 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1305 12:22:37.007813 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1306 12:22:37.014212 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1307 12:22:37.017617 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1308 12:22:37.021190 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1309 12:22:37.024505 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1310 12:22:37.024598 ==
1311 12:22:37.027396 Dram Type= 6, Freq= 0, CH_0, rank 1
1312 12:22:37.034584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1313 12:22:37.034698 ==
1314 12:22:37.034779 DQS Delay:
1315 12:22:37.038143 DQS0 = 0, DQS1 = 0
1316 12:22:37.038229 DQM Delay:
1317 12:22:37.038295 DQM0 = 84, DQM1 = 77
1318 12:22:37.040990 DQ Delay:
1319 12:22:37.044299 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1320 12:22:37.048049 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1321 12:22:37.050935 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1322 12:22:37.054980 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1323 12:22:37.055070
1324 12:22:37.055135
1325 12:22:37.055195 ==
1326 12:22:37.058075 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 12:22:37.061334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 12:22:37.061425 ==
1329 12:22:37.061492
1330 12:22:37.061552
1331 12:22:37.064514 TX Vref Scan disable
1332 12:22:37.064598 == TX Byte 0 ==
1333 12:22:37.071382 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1334 12:22:37.074995 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1335 12:22:37.075118 == TX Byte 1 ==
1336 12:22:37.081283 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1337 12:22:37.084821 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1338 12:22:37.084922 ==
1339 12:22:37.088098 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 12:22:37.091592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 12:22:37.091687 ==
1342 12:22:37.105107 TX Vref=22, minBit 3, minWin=27, winSum=444
1343 12:22:37.108153 TX Vref=24, minBit 9, minWin=27, winSum=449
1344 12:22:37.111529 TX Vref=26, minBit 2, minWin=27, winSum=446
1345 12:22:37.115334 TX Vref=28, minBit 9, minWin=27, winSum=451
1346 12:22:37.118667 TX Vref=30, minBit 0, minWin=28, winSum=453
1347 12:22:37.121748 TX Vref=32, minBit 0, minWin=28, winSum=452
1348 12:22:37.128381 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1349 12:22:37.128495
1350 12:22:37.132179 Final TX Range 1 Vref 30
1351 12:22:37.132278
1352 12:22:37.132345 ==
1353 12:22:37.135365 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 12:22:37.138605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 12:22:37.138730 ==
1356 12:22:37.138835
1357 12:22:37.138909
1358 12:22:37.142049 TX Vref Scan disable
1359 12:22:37.144974 == TX Byte 0 ==
1360 12:22:37.148804 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1361 12:22:37.152175 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1362 12:22:37.155617 == TX Byte 1 ==
1363 12:22:37.159058 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1364 12:22:37.162230 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1365 12:22:37.162327
1366 12:22:37.165799 [DATLAT]
1367 12:22:37.165889 Freq=800, CH0 RK1
1368 12:22:37.165953
1369 12:22:37.169052 DATLAT Default: 0xa
1370 12:22:37.169137 0, 0xFFFF, sum = 0
1371 12:22:37.172498 1, 0xFFFF, sum = 0
1372 12:22:37.172586 2, 0xFFFF, sum = 0
1373 12:22:37.175893 3, 0xFFFF, sum = 0
1374 12:22:37.175983 4, 0xFFFF, sum = 0
1375 12:22:37.179020 5, 0xFFFF, sum = 0
1376 12:22:37.179119 6, 0xFFFF, sum = 0
1377 12:22:37.182452 7, 0xFFFF, sum = 0
1378 12:22:37.182568 8, 0xFFFF, sum = 0
1379 12:22:37.185681 9, 0x0, sum = 1
1380 12:22:37.185770 10, 0x0, sum = 2
1381 12:22:37.188765 11, 0x0, sum = 3
1382 12:22:37.188853 12, 0x0, sum = 4
1383 12:22:37.192291 best_step = 10
1384 12:22:37.192387
1385 12:22:37.192456 ==
1386 12:22:37.195682 Dram Type= 6, Freq= 0, CH_0, rank 1
1387 12:22:37.199290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 12:22:37.199387 ==
1389 12:22:37.199453 RX Vref Scan: 0
1390 12:22:37.199512
1391 12:22:37.202251 RX Vref 0 -> 0, step: 1
1392 12:22:37.202332
1393 12:22:37.205876 RX Delay -95 -> 252, step: 8
1394 12:22:37.209014 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1395 12:22:37.215780 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1396 12:22:37.219235 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1397 12:22:37.222466 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1398 12:22:37.226268 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1399 12:22:37.229143 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1400 12:22:37.232645 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1401 12:22:37.239073 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1402 12:22:37.242656 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1403 12:22:37.246022 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1404 12:22:37.249458 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1405 12:22:37.252996 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1406 12:22:37.259648 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1407 12:22:37.262984 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1408 12:22:37.266234 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1409 12:22:37.269953 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1410 12:22:37.270054 ==
1411 12:22:37.273233 Dram Type= 6, Freq= 0, CH_0, rank 1
1412 12:22:37.276488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1413 12:22:37.279603 ==
1414 12:22:37.279700 DQS Delay:
1415 12:22:37.279765 DQS0 = 0, DQS1 = 0
1416 12:22:37.283373 DQM Delay:
1417 12:22:37.283465 DQM0 = 87, DQM1 = 77
1418 12:22:37.286518 DQ Delay:
1419 12:22:37.286606 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1420 12:22:37.289973 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1421 12:22:37.293259 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1422 12:22:37.296756 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =84
1423 12:22:37.296869
1424 12:22:37.299907
1425 12:22:37.306867 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1426 12:22:37.310409 CH0 RK1: MR19=606, MR18=2F18
1427 12:22:37.316805 CH0_RK1: MR19=0x606, MR18=0x2F18, DQSOSC=397, MR23=63, INC=93, DEC=62
1428 12:22:37.316948 [RxdqsGatingPostProcess] freq 800
1429 12:22:37.323781 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1430 12:22:37.326963 Pre-setting of DQS Precalculation
1431 12:22:37.330041 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1432 12:22:37.333458 ==
1433 12:22:37.333552 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 12:22:37.340419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 12:22:37.340522 ==
1436 12:22:37.343560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1437 12:22:37.350402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1438 12:22:37.359780 [CA 0] Center 36 (6~66) winsize 61
1439 12:22:37.363011 [CA 1] Center 36 (6~66) winsize 61
1440 12:22:37.366162 [CA 2] Center 34 (4~64) winsize 61
1441 12:22:37.370134 [CA 3] Center 33 (3~64) winsize 62
1442 12:22:37.373555 [CA 4] Center 34 (4~65) winsize 62
1443 12:22:37.376681 [CA 5] Center 33 (3~64) winsize 62
1444 12:22:37.376777
1445 12:22:37.379756 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1446 12:22:37.379845
1447 12:22:37.383017 [CATrainingPosCal] consider 1 rank data
1448 12:22:37.386449 u2DelayCellTimex100 = 270/100 ps
1449 12:22:37.389910 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1450 12:22:37.393268 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1451 12:22:37.396451 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1452 12:22:37.403101 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1453 12:22:37.406689 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1454 12:22:37.409669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1455 12:22:37.409761
1456 12:22:37.413383 CA PerBit enable=1, Macro0, CA PI delay=33
1457 12:22:37.413472
1458 12:22:37.416643 [CBTSetCACLKResult] CA Dly = 33
1459 12:22:37.416728 CS Dly: 4 (0~35)
1460 12:22:37.416793 ==
1461 12:22:37.420297 Dram Type= 6, Freq= 0, CH_1, rank 1
1462 12:22:37.426961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1463 12:22:37.427069 ==
1464 12:22:37.429849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1465 12:22:37.436909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1466 12:22:37.445931 [CA 0] Center 36 (6~66) winsize 61
1467 12:22:37.449230 [CA 1] Center 36 (6~66) winsize 61
1468 12:22:37.452660 [CA 2] Center 34 (4~64) winsize 61
1469 12:22:37.455605 [CA 3] Center 33 (3~64) winsize 62
1470 12:22:37.458984 [CA 4] Center 34 (3~65) winsize 63
1471 12:22:37.462678 [CA 5] Center 33 (3~64) winsize 62
1472 12:22:37.462790
1473 12:22:37.465652 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1474 12:22:37.465738
1475 12:22:37.468965 [CATrainingPosCal] consider 2 rank data
1476 12:22:37.472479 u2DelayCellTimex100 = 270/100 ps
1477 12:22:37.476308 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1478 12:22:37.479014 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1479 12:22:37.482918 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1480 12:22:37.489587 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1481 12:22:37.493249 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1482 12:22:37.496931 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1483 12:22:37.497031
1484 12:22:37.500729 CA PerBit enable=1, Macro0, CA PI delay=33
1485 12:22:37.500825
1486 12:22:37.500891 [CBTSetCACLKResult] CA Dly = 33
1487 12:22:37.504427 CS Dly: 5 (0~37)
1488 12:22:37.504517
1489 12:22:37.508309 ----->DramcWriteLeveling(PI) begin...
1490 12:22:37.508402 ==
1491 12:22:37.512031 Dram Type= 6, Freq= 0, CH_1, rank 0
1492 12:22:37.515586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1493 12:22:37.515687 ==
1494 12:22:37.519662 Write leveling (Byte 0): 28 => 28
1495 12:22:37.523350 Write leveling (Byte 1): 31 => 31
1496 12:22:37.523449 DramcWriteLeveling(PI) end<-----
1497 12:22:37.523515
1498 12:22:37.523575 ==
1499 12:22:37.526394 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 12:22:37.533942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 12:22:37.534064 ==
1502 12:22:37.534130 [Gating] SW mode calibration
1503 12:22:37.543507 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1504 12:22:37.546822 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1505 12:22:37.550028 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1506 12:22:37.556811 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1507 12:22:37.559981 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1508 12:22:37.563393 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:22:37.570150 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:22:37.573802 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:22:37.576974 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:22:37.583530 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:22:37.587026 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:22:37.590528 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:22:37.597318 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:22:37.600519 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:22:37.603906 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1518 12:22:37.606944 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:22:37.613725 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:22:37.617691 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:22:37.620578 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:22:37.627051 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1523 12:22:37.631172 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1524 12:22:37.634075 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:22:37.640676 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:22:37.643913 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:22:37.647135 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:22:37.654153 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:22:37.656993 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:22:37.660835 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:22:37.667108 0 9 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1532 12:22:37.670780 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1533 12:22:37.673829 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 12:22:37.677377 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 12:22:37.684057 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 12:22:37.687725 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 12:22:37.691149 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 12:22:37.697341 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 12:22:37.700718 0 10 8 | B1->B0 | 2f2f 3030 | 0 0 | (1 1) (0 0)
1540 12:22:37.704148 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:22:37.710933 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:22:37.714351 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:22:37.717639 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:22:37.721199 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:22:37.727619 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:22:37.731035 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1547 12:22:37.734700 0 11 8 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (0 0)
1548 12:22:37.741063 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 12:22:37.744561 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 12:22:37.748112 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 12:22:37.754816 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 12:22:37.757777 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 12:22:37.761580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 12:22:37.768132 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 12:22:37.771394 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1556 12:22:37.774748 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:22:37.781610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:22:37.785284 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:22:37.788064 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:22:37.791460 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:22:37.798234 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:22:37.801809 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:22:37.804749 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:22:37.811429 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:22:37.814958 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:22:37.818439 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:22:37.825041 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:22:37.828479 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:22:37.831416 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:22:37.838493 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1571 12:22:37.842077 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1572 12:22:37.845292 Total UI for P1: 0, mck2ui 16
1573 12:22:37.848336 best dqsien dly found for B1: ( 0, 14, 4)
1574 12:22:37.851641 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 12:22:37.855152 Total UI for P1: 0, mck2ui 16
1576 12:22:37.858695 best dqsien dly found for B0: ( 0, 14, 6)
1577 12:22:37.861816 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1578 12:22:37.865170 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1579 12:22:37.865268
1580 12:22:37.868751 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1581 12:22:37.872068 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1582 12:22:37.875626 [Gating] SW calibration Done
1583 12:22:37.875724 ==
1584 12:22:37.878950 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 12:22:37.882096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 12:22:37.885228 ==
1587 12:22:37.885322 RX Vref Scan: 0
1588 12:22:37.885388
1589 12:22:37.889039 RX Vref 0 -> 0, step: 1
1590 12:22:37.889129
1591 12:22:37.892124 RX Delay -130 -> 252, step: 16
1592 12:22:37.895559 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1593 12:22:37.898976 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1594 12:22:37.902383 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1595 12:22:37.905349 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1596 12:22:37.912789 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1597 12:22:37.915611 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1598 12:22:37.919001 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1599 12:22:37.922408 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1600 12:22:37.926086 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1601 12:22:37.928798 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1602 12:22:37.935733 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1603 12:22:37.939278 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1604 12:22:37.942526 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1605 12:22:37.945734 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1606 12:22:37.948979 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1607 12:22:37.955766 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1608 12:22:37.955888 ==
1609 12:22:37.959235 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 12:22:37.962602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 12:22:37.962731 ==
1612 12:22:37.962818 DQS Delay:
1613 12:22:37.965937 DQS0 = 0, DQS1 = 0
1614 12:22:37.966025 DQM Delay:
1615 12:22:37.968967 DQM0 = 80, DQM1 = 76
1616 12:22:37.969060 DQ Delay:
1617 12:22:37.972474 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1618 12:22:37.976021 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =69
1619 12:22:37.979515 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1620 12:22:37.982540 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =77
1621 12:22:37.982659
1622 12:22:37.982785
1623 12:22:37.982849 ==
1624 12:22:37.985810 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 12:22:37.989422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 12:22:37.989539 ==
1627 12:22:37.989656
1628 12:22:37.992513
1629 12:22:37.992616 TX Vref Scan disable
1630 12:22:37.996296 == TX Byte 0 ==
1631 12:22:37.999495 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1632 12:22:38.002906 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1633 12:22:38.006212 == TX Byte 1 ==
1634 12:22:38.009344 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1635 12:22:38.012879 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1636 12:22:38.012977 ==
1637 12:22:38.016344 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 12:22:38.022593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 12:22:38.022711 ==
1640 12:22:38.034477 TX Vref=22, minBit 0, minWin=27, winSum=439
1641 12:22:38.037880 TX Vref=24, minBit 1, minWin=27, winSum=443
1642 12:22:38.041286 TX Vref=26, minBit 4, minWin=27, winSum=444
1643 12:22:38.044642 TX Vref=28, minBit 8, minWin=27, winSum=449
1644 12:22:38.047788 TX Vref=30, minBit 1, minWin=28, winSum=456
1645 12:22:38.051500 TX Vref=32, minBit 3, minWin=28, winSum=457
1646 12:22:38.058411 [TxChooseVref] Worse bit 3, Min win 28, Win sum 457, Final Vref 32
1647 12:22:38.058561
1648 12:22:38.061484 Final TX Range 1 Vref 32
1649 12:22:38.061577
1650 12:22:38.061645 ==
1651 12:22:38.064850 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 12:22:38.068160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 12:22:38.068253 ==
1654 12:22:38.068318
1655 12:22:38.068379
1656 12:22:38.072018 TX Vref Scan disable
1657 12:22:38.075586 == TX Byte 0 ==
1658 12:22:38.079159 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1659 12:22:38.082421 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1660 12:22:38.086011 == TX Byte 1 ==
1661 12:22:38.089078 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1662 12:22:38.092507 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1663 12:22:38.092607
1664 12:22:38.092675 [DATLAT]
1665 12:22:38.095721 Freq=800, CH1 RK0
1666 12:22:38.095809
1667 12:22:38.095873 DATLAT Default: 0xa
1668 12:22:38.099424 0, 0xFFFF, sum = 0
1669 12:22:38.099515 1, 0xFFFF, sum = 0
1670 12:22:38.102397 2, 0xFFFF, sum = 0
1671 12:22:38.102488 3, 0xFFFF, sum = 0
1672 12:22:38.105725 4, 0xFFFF, sum = 0
1673 12:22:38.105818 5, 0xFFFF, sum = 0
1674 12:22:38.109616 6, 0xFFFF, sum = 0
1675 12:22:38.112601 7, 0xFFFF, sum = 0
1676 12:22:38.112705 8, 0xFFFF, sum = 0
1677 12:22:38.112775 9, 0x0, sum = 1
1678 12:22:38.116029 10, 0x0, sum = 2
1679 12:22:38.116115 11, 0x0, sum = 3
1680 12:22:38.119618 12, 0x0, sum = 4
1681 12:22:38.119709 best_step = 10
1682 12:22:38.119774
1683 12:22:38.119834 ==
1684 12:22:38.122787 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 12:22:38.129682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1686 12:22:38.129791 ==
1687 12:22:38.129859 RX Vref Scan: 1
1688 12:22:38.129918
1689 12:22:38.133194 Set Vref Range= 32 -> 127
1690 12:22:38.133279
1691 12:22:38.136037 RX Vref 32 -> 127, step: 1
1692 12:22:38.136121
1693 12:22:38.136186 RX Delay -95 -> 252, step: 8
1694 12:22:38.139811
1695 12:22:38.139898 Set Vref, RX VrefLevel [Byte0]: 32
1696 12:22:38.142712 [Byte1]: 32
1697 12:22:38.147369
1698 12:22:38.147471 Set Vref, RX VrefLevel [Byte0]: 33
1699 12:22:38.150210 [Byte1]: 33
1700 12:22:38.154504
1701 12:22:38.154601 Set Vref, RX VrefLevel [Byte0]: 34
1702 12:22:38.157915 [Byte1]: 34
1703 12:22:38.162418
1704 12:22:38.162522 Set Vref, RX VrefLevel [Byte0]: 35
1705 12:22:38.165533 [Byte1]: 35
1706 12:22:38.169906
1707 12:22:38.170008 Set Vref, RX VrefLevel [Byte0]: 36
1708 12:22:38.173280 [Byte1]: 36
1709 12:22:38.177332
1710 12:22:38.177436 Set Vref, RX VrefLevel [Byte0]: 37
1711 12:22:38.180952 [Byte1]: 37
1712 12:22:38.185029
1713 12:22:38.185144 Set Vref, RX VrefLevel [Byte0]: 38
1714 12:22:38.188278 [Byte1]: 38
1715 12:22:38.192748
1716 12:22:38.192852 Set Vref, RX VrefLevel [Byte0]: 39
1717 12:22:38.195791 [Byte1]: 39
1718 12:22:38.200208
1719 12:22:38.200319 Set Vref, RX VrefLevel [Byte0]: 40
1720 12:22:38.203428 [Byte1]: 40
1721 12:22:38.208003
1722 12:22:38.208101 Set Vref, RX VrefLevel [Byte0]: 41
1723 12:22:38.211346 [Byte1]: 41
1724 12:22:38.215530
1725 12:22:38.215626 Set Vref, RX VrefLevel [Byte0]: 42
1726 12:22:38.218976 [Byte1]: 42
1727 12:22:38.223261
1728 12:22:38.223373 Set Vref, RX VrefLevel [Byte0]: 43
1729 12:22:38.226120 [Byte1]: 43
1730 12:22:38.230410
1731 12:22:38.230502 Set Vref, RX VrefLevel [Byte0]: 44
1732 12:22:38.233864 [Byte1]: 44
1733 12:22:38.238000
1734 12:22:38.238094 Set Vref, RX VrefLevel [Byte0]: 45
1735 12:22:38.241468 [Byte1]: 45
1736 12:22:38.246126
1737 12:22:38.246225 Set Vref, RX VrefLevel [Byte0]: 46
1738 12:22:38.248876 [Byte1]: 46
1739 12:22:38.253809
1740 12:22:38.253903 Set Vref, RX VrefLevel [Byte0]: 47
1741 12:22:38.257104 [Byte1]: 47
1742 12:22:38.260792
1743 12:22:38.260884 Set Vref, RX VrefLevel [Byte0]: 48
1744 12:22:38.264230 [Byte1]: 48
1745 12:22:38.268651
1746 12:22:38.268748 Set Vref, RX VrefLevel [Byte0]: 49
1747 12:22:38.271727 [Byte1]: 49
1748 12:22:38.276415
1749 12:22:38.276522 Set Vref, RX VrefLevel [Byte0]: 50
1750 12:22:38.279645 [Byte1]: 50
1751 12:22:38.283707
1752 12:22:38.283814 Set Vref, RX VrefLevel [Byte0]: 51
1753 12:22:38.287265 [Byte1]: 51
1754 12:22:38.291294
1755 12:22:38.291422 Set Vref, RX VrefLevel [Byte0]: 52
1756 12:22:38.294592 [Byte1]: 52
1757 12:22:38.298994
1758 12:22:38.299102 Set Vref, RX VrefLevel [Byte0]: 53
1759 12:22:38.302143 [Byte1]: 53
1760 12:22:38.306610
1761 12:22:38.306690 Set Vref, RX VrefLevel [Byte0]: 54
1762 12:22:38.309848 [Byte1]: 54
1763 12:22:38.313929
1764 12:22:38.314010 Set Vref, RX VrefLevel [Byte0]: 55
1765 12:22:38.317356 [Byte1]: 55
1766 12:22:38.321641
1767 12:22:38.321724 Set Vref, RX VrefLevel [Byte0]: 56
1768 12:22:38.325009 [Byte1]: 56
1769 12:22:38.329470
1770 12:22:38.329552 Set Vref, RX VrefLevel [Byte0]: 57
1771 12:22:38.332445 [Byte1]: 57
1772 12:22:38.336990
1773 12:22:38.337072 Set Vref, RX VrefLevel [Byte0]: 58
1774 12:22:38.340393 [Byte1]: 58
1775 12:22:38.344696
1776 12:22:38.344777 Set Vref, RX VrefLevel [Byte0]: 59
1777 12:22:38.347644 [Byte1]: 59
1778 12:22:38.352020
1779 12:22:38.352103 Set Vref, RX VrefLevel [Byte0]: 60
1780 12:22:38.355658 [Byte1]: 60
1781 12:22:38.359633
1782 12:22:38.359715 Set Vref, RX VrefLevel [Byte0]: 61
1783 12:22:38.363304 [Byte1]: 61
1784 12:22:38.367306
1785 12:22:38.367389 Set Vref, RX VrefLevel [Byte0]: 62
1786 12:22:38.370912 [Byte1]: 62
1787 12:22:38.375322
1788 12:22:38.375416 Set Vref, RX VrefLevel [Byte0]: 63
1789 12:22:38.378298 [Byte1]: 63
1790 12:22:38.382663
1791 12:22:38.382799 Set Vref, RX VrefLevel [Byte0]: 64
1792 12:22:38.386261 [Byte1]: 64
1793 12:22:38.390059
1794 12:22:38.390140 Set Vref, RX VrefLevel [Byte0]: 65
1795 12:22:38.393250 [Byte1]: 65
1796 12:22:38.397782
1797 12:22:38.397863 Set Vref, RX VrefLevel [Byte0]: 66
1798 12:22:38.400883 [Byte1]: 66
1799 12:22:38.405328
1800 12:22:38.405409 Set Vref, RX VrefLevel [Byte0]: 67
1801 12:22:38.408540 [Byte1]: 67
1802 12:22:38.413049
1803 12:22:38.413130 Set Vref, RX VrefLevel [Byte0]: 68
1804 12:22:38.416129 [Byte1]: 68
1805 12:22:38.420391
1806 12:22:38.420472 Set Vref, RX VrefLevel [Byte0]: 69
1807 12:22:38.423820 [Byte1]: 69
1808 12:22:38.428250
1809 12:22:38.428331 Set Vref, RX VrefLevel [Byte0]: 70
1810 12:22:38.431671 [Byte1]: 70
1811 12:22:38.435754
1812 12:22:38.435834 Set Vref, RX VrefLevel [Byte0]: 71
1813 12:22:38.438859 [Byte1]: 71
1814 12:22:38.443076
1815 12:22:38.443158 Set Vref, RX VrefLevel [Byte0]: 72
1816 12:22:38.446694 [Byte1]: 72
1817 12:22:38.451055
1818 12:22:38.451136 Set Vref, RX VrefLevel [Byte0]: 73
1819 12:22:38.454370 [Byte1]: 73
1820 12:22:38.458961
1821 12:22:38.459041 Set Vref, RX VrefLevel [Byte0]: 74
1822 12:22:38.461572 [Byte1]: 74
1823 12:22:38.466102
1824 12:22:38.466183 Set Vref, RX VrefLevel [Byte0]: 75
1825 12:22:38.469366 [Byte1]: 75
1826 12:22:38.473420
1827 12:22:38.473509 Set Vref, RX VrefLevel [Byte0]: 76
1828 12:22:38.477267 [Byte1]: 76
1829 12:22:38.481338
1830 12:22:38.481419 Set Vref, RX VrefLevel [Byte0]: 77
1831 12:22:38.484491 [Byte1]: 77
1832 12:22:38.488944
1833 12:22:38.489025 Final RX Vref Byte 0 = 62 to rank0
1834 12:22:38.492307 Final RX Vref Byte 1 = 58 to rank0
1835 12:22:38.495709 Final RX Vref Byte 0 = 62 to rank1
1836 12:22:38.499401 Final RX Vref Byte 1 = 58 to rank1==
1837 12:22:38.502123 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 12:22:38.505629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 12:22:38.509093 ==
1840 12:22:38.509174 DQS Delay:
1841 12:22:38.509238 DQS0 = 0, DQS1 = 0
1842 12:22:38.512266 DQM Delay:
1843 12:22:38.512348 DQM0 = 83, DQM1 = 73
1844 12:22:38.515838 DQ Delay:
1845 12:22:38.515918 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =84
1846 12:22:38.519186 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =80
1847 12:22:38.522585 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1848 12:22:38.525794 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =76
1849 12:22:38.525878
1850 12:22:38.529243
1851 12:22:38.535899 [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
1852 12:22:38.539488 CH1 RK0: MR19=605, MR18=26FB
1853 12:22:38.545805 CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61
1854 12:22:38.545969
1855 12:22:38.549126 ----->DramcWriteLeveling(PI) begin...
1856 12:22:38.549212 ==
1857 12:22:38.552873 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 12:22:38.556008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 12:22:38.556105 ==
1860 12:22:38.559278 Write leveling (Byte 0): 28 => 28
1861 12:22:38.563052 Write leveling (Byte 1): 27 => 27
1862 12:22:38.566322 DramcWriteLeveling(PI) end<-----
1863 12:22:38.566404
1864 12:22:38.566468 ==
1865 12:22:38.569708 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 12:22:38.572833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 12:22:38.572915 ==
1868 12:22:38.576339 [Gating] SW mode calibration
1869 12:22:38.583058 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 12:22:38.585980 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 12:22:38.593021 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 12:22:38.596208 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:22:38.599708 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:22:38.606371 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:22:38.609611 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:22:38.612832 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:22:38.620115 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:22:38.623215 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:22:38.626199 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:22:38.633625 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 12:22:38.636663 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:22:38.639726 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:22:38.646865 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:22:38.650037 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:22:38.653768 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:22:38.656530 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1887 12:22:38.663633 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1888 12:22:38.666816 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1889 12:22:38.670282 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:22:38.676868 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:22:38.680278 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:22:38.683736 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:22:38.690616 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:22:38.693695 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:22:38.697492 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:22:38.703909 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:22:38.707279 0 9 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
1898 12:22:38.710702 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 12:22:38.713610 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 12:22:38.721051 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 12:22:38.723697 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 12:22:38.727172 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 12:22:38.733727 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 12:22:38.737242 0 10 4 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 0)
1905 12:22:38.740609 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:22:38.747668 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:22:38.750530 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 12:22:38.754115 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 12:22:38.760497 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 12:22:38.764389 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 12:22:38.767307 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 12:22:38.770704 0 11 4 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
1913 12:22:38.777582 0 11 8 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1914 12:22:38.780845 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 12:22:38.784384 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 12:22:38.791125 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 12:22:38.794340 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 12:22:38.797686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 12:22:38.804493 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 12:22:38.807551 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1921 12:22:38.811453 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:22:38.818535 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:22:38.821094 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:22:38.824856 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:22:38.827959 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:22:38.834645 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:22:38.838107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 12:22:38.841448 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 12:22:38.848085 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 12:22:38.851679 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 12:22:38.854954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 12:22:38.861581 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:22:38.864745 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:22:38.868376 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:22:38.874850 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:22:38.878405 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1937 12:22:38.881584 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 12:22:38.885074 Total UI for P1: 0, mck2ui 16
1939 12:22:38.888201 best dqsien dly found for B0: ( 0, 14, 4)
1940 12:22:38.892055 Total UI for P1: 0, mck2ui 16
1941 12:22:38.895398 best dqsien dly found for B1: ( 0, 14, 4)
1942 12:22:38.898780 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1943 12:22:38.902053 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1944 12:22:38.902130
1945 12:22:38.905376 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1946 12:22:38.908762 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1947 12:22:38.911964 [Gating] SW calibration Done
1948 12:22:38.912046 ==
1949 12:22:38.915081 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 12:22:38.918547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 12:22:38.921783 ==
1952 12:22:38.921858 RX Vref Scan: 0
1953 12:22:38.921920
1954 12:22:38.925101 RX Vref 0 -> 0, step: 1
1955 12:22:38.925170
1956 12:22:38.928912 RX Delay -130 -> 252, step: 16
1957 12:22:38.932578 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1958 12:22:38.935422 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1959 12:22:38.939237 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1960 12:22:38.942126 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1961 12:22:38.945509 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1962 12:22:38.952140 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1963 12:22:38.955787 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1964 12:22:38.959032 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1965 12:22:38.962349 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1966 12:22:38.965774 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1967 12:22:38.972643 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1968 12:22:38.976044 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1969 12:22:38.979245 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1970 12:22:38.982455 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1971 12:22:38.986065 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1972 12:22:38.992560 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1973 12:22:38.992658 ==
1974 12:22:38.996514 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 12:22:38.999731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 12:22:38.999814 ==
1977 12:22:38.999878 DQS Delay:
1978 12:22:39.002657 DQS0 = 0, DQS1 = 0
1979 12:22:39.002800 DQM Delay:
1980 12:22:39.006165 DQM0 = 82, DQM1 = 77
1981 12:22:39.006269 DQ Delay:
1982 12:22:39.009386 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1983 12:22:39.013195 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1984 12:22:39.016241 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1985 12:22:39.019464 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1986 12:22:39.019542
1987 12:22:39.019606
1988 12:22:39.019669 ==
1989 12:22:39.023127 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 12:22:39.026528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 12:22:39.026630 ==
1992 12:22:39.026727
1993 12:22:39.026822
1994 12:22:39.029997 TX Vref Scan disable
1995 12:22:39.032947 == TX Byte 0 ==
1996 12:22:39.036943 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 12:22:39.039915 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 12:22:39.039995 == TX Byte 1 ==
1999 12:22:39.046468 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2000 12:22:39.050153 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2001 12:22:39.050245 ==
2002 12:22:39.053395 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 12:22:39.056801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 12:22:39.056882 ==
2005 12:22:39.070908 TX Vref=22, minBit 1, minWin=27, winSum=442
2006 12:22:39.074210 TX Vref=24, minBit 1, minWin=27, winSum=445
2007 12:22:39.077663 TX Vref=26, minBit 11, minWin=27, winSum=446
2008 12:22:39.081019 TX Vref=28, minBit 0, minWin=28, winSum=450
2009 12:22:39.084112 TX Vref=30, minBit 12, minWin=27, winSum=448
2010 12:22:39.087470 TX Vref=32, minBit 0, minWin=28, winSum=450
2011 12:22:39.094366 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 28
2012 12:22:39.094483
2013 12:22:39.097409 Final TX Range 1 Vref 28
2014 12:22:39.097497
2015 12:22:39.097567 ==
2016 12:22:39.101043 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 12:22:39.104093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 12:22:39.104178 ==
2019 12:22:39.104245
2020 12:22:39.104307
2021 12:22:39.107368 TX Vref Scan disable
2022 12:22:39.110933 == TX Byte 0 ==
2023 12:22:39.114274 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 12:22:39.117879 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 12:22:39.121122 == TX Byte 1 ==
2026 12:22:39.124251 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2027 12:22:39.127993 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2028 12:22:39.128088
2029 12:22:39.131003 [DATLAT]
2030 12:22:39.131092 Freq=800, CH1 RK1
2031 12:22:39.131159
2032 12:22:39.134188 DATLAT Default: 0xa
2033 12:22:39.134275 0, 0xFFFF, sum = 0
2034 12:22:39.137685 1, 0xFFFF, sum = 0
2035 12:22:39.137775 2, 0xFFFF, sum = 0
2036 12:22:39.141399 3, 0xFFFF, sum = 0
2037 12:22:39.141489 4, 0xFFFF, sum = 0
2038 12:22:39.144647 5, 0xFFFF, sum = 0
2039 12:22:39.144736 6, 0xFFFF, sum = 0
2040 12:22:39.148230 7, 0xFFFF, sum = 0
2041 12:22:39.148325 8, 0xFFFF, sum = 0
2042 12:22:39.151025 9, 0x0, sum = 1
2043 12:22:39.151114 10, 0x0, sum = 2
2044 12:22:39.154709 11, 0x0, sum = 3
2045 12:22:39.154813 12, 0x0, sum = 4
2046 12:22:39.158012 best_step = 10
2047 12:22:39.158101
2048 12:22:39.158167 ==
2049 12:22:39.161553 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 12:22:39.164954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 12:22:39.165053 ==
2052 12:22:39.165120 RX Vref Scan: 0
2053 12:22:39.168457
2054 12:22:39.168570 RX Vref 0 -> 0, step: 1
2055 12:22:39.168640
2056 12:22:39.171543 RX Delay -95 -> 252, step: 8
2057 12:22:39.174941 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2058 12:22:39.181670 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2059 12:22:39.184507 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2060 12:22:39.188356 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2061 12:22:39.191408 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
2062 12:22:39.194921 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2063 12:22:39.201531 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2064 12:22:39.204974 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2065 12:22:39.208464 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2066 12:22:39.211935 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2067 12:22:39.215292 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2068 12:22:39.218283 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2069 12:22:39.224940 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2070 12:22:39.228610 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2071 12:22:39.232028 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2072 12:22:39.235207 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2073 12:22:39.235383 ==
2074 12:22:39.238717 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 12:22:39.245420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 12:22:39.245549 ==
2077 12:22:39.245617 DQS Delay:
2078 12:22:39.245677 DQS0 = 0, DQS1 = 0
2079 12:22:39.248807 DQM Delay:
2080 12:22:39.248908 DQM0 = 79, DQM1 = 76
2081 12:22:39.251939 DQ Delay:
2082 12:22:39.255195 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2083 12:22:39.255297 DQ4 =76, DQ5 =88, DQ6 =92, DQ7 =76
2084 12:22:39.258972 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
2085 12:22:39.262410 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2086 12:22:39.265804
2087 12:22:39.265924
2088 12:22:39.271975 [DQSOSCAuto] RK1, (LSB)MR18= 0x232e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2089 12:22:39.275620 CH1 RK1: MR19=606, MR18=232E
2090 12:22:39.282352 CH1_RK1: MR19=0x606, MR18=0x232E, DQSOSC=398, MR23=63, INC=93, DEC=62
2091 12:22:39.285584 [RxdqsGatingPostProcess] freq 800
2092 12:22:39.289015 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 12:22:39.292779 Pre-setting of DQS Precalculation
2094 12:22:39.295422 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 12:22:39.305456 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 12:22:39.312278 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 12:22:39.312377
2098 12:22:39.312443
2099 12:22:39.315539 [Calibration Summary] 1600 Mbps
2100 12:22:39.315622 CH 0, Rank 0
2101 12:22:39.319441 SW Impedance : PASS
2102 12:22:39.319525 DUTY Scan : NO K
2103 12:22:39.322530 ZQ Calibration : PASS
2104 12:22:39.325658 Jitter Meter : NO K
2105 12:22:39.325764 CBT Training : PASS
2106 12:22:39.329184 Write leveling : PASS
2107 12:22:39.332554 RX DQS gating : PASS
2108 12:22:39.332657 RX DQ/DQS(RDDQC) : PASS
2109 12:22:39.335985 TX DQ/DQS : PASS
2110 12:22:39.339201 RX DATLAT : PASS
2111 12:22:39.339289 RX DQ/DQS(Engine): PASS
2112 12:22:39.342647 TX OE : NO K
2113 12:22:39.342760 All Pass.
2114 12:22:39.342869
2115 12:22:39.346119 CH 0, Rank 1
2116 12:22:39.346211 SW Impedance : PASS
2117 12:22:39.349646 DUTY Scan : NO K
2118 12:22:39.349733 ZQ Calibration : PASS
2119 12:22:39.352975 Jitter Meter : NO K
2120 12:22:39.356251 CBT Training : PASS
2121 12:22:39.356335 Write leveling : PASS
2122 12:22:39.359693 RX DQS gating : PASS
2123 12:22:39.362667 RX DQ/DQS(RDDQC) : PASS
2124 12:22:39.362790 TX DQ/DQS : PASS
2125 12:22:39.366284 RX DATLAT : PASS
2126 12:22:39.369377 RX DQ/DQS(Engine): PASS
2127 12:22:39.369461 TX OE : NO K
2128 12:22:39.372673 All Pass.
2129 12:22:39.372754
2130 12:22:39.372818 CH 1, Rank 0
2131 12:22:39.376039 SW Impedance : PASS
2132 12:22:39.376120 DUTY Scan : NO K
2133 12:22:39.379705 ZQ Calibration : PASS
2134 12:22:39.383160 Jitter Meter : NO K
2135 12:22:39.383244 CBT Training : PASS
2136 12:22:39.385988 Write leveling : PASS
2137 12:22:39.386070 RX DQS gating : PASS
2138 12:22:39.389366 RX DQ/DQS(RDDQC) : PASS
2139 12:22:39.392879 TX DQ/DQS : PASS
2140 12:22:39.392962 RX DATLAT : PASS
2141 12:22:39.396228 RX DQ/DQS(Engine): PASS
2142 12:22:39.399846 TX OE : NO K
2143 12:22:39.399929 All Pass.
2144 12:22:39.399994
2145 12:22:39.400053 CH 1, Rank 1
2146 12:22:39.403039 SW Impedance : PASS
2147 12:22:39.406415 DUTY Scan : NO K
2148 12:22:39.406503 ZQ Calibration : PASS
2149 12:22:39.409522 Jitter Meter : NO K
2150 12:22:39.413062 CBT Training : PASS
2151 12:22:39.413161 Write leveling : PASS
2152 12:22:39.416370 RX DQS gating : PASS
2153 12:22:39.416458 RX DQ/DQS(RDDQC) : PASS
2154 12:22:39.419549 TX DQ/DQS : PASS
2155 12:22:39.423266 RX DATLAT : PASS
2156 12:22:39.423375 RX DQ/DQS(Engine): PASS
2157 12:22:39.426488 TX OE : NO K
2158 12:22:39.426616 All Pass.
2159 12:22:39.426710
2160 12:22:39.429819 DramC Write-DBI off
2161 12:22:39.432853 PER_BANK_REFRESH: Hybrid Mode
2162 12:22:39.432941 TX_TRACKING: ON
2163 12:22:39.436167 [GetDramInforAfterCalByMRR] Vendor 6.
2164 12:22:39.439529 [GetDramInforAfterCalByMRR] Revision 606.
2165 12:22:39.443350 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 12:22:39.446652 MR0 0x3b3b
2167 12:22:39.446813 MR8 0x5151
2168 12:22:39.449847 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 12:22:39.449949
2170 12:22:39.453273 MR0 0x3b3b
2171 12:22:39.453396 MR8 0x5151
2172 12:22:39.456444 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 12:22:39.456543
2174 12:22:39.467104 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 12:22:39.469896 [FAST_K] Save calibration result to emmc
2176 12:22:39.473245 [FAST_K] Save calibration result to emmc
2177 12:22:39.473346 dram_init: config_dvfs: 1
2178 12:22:39.480212 dramc_set_vcore_voltage set vcore to 662500
2179 12:22:39.480315 Read voltage for 1200, 2
2180 12:22:39.483637 Vio18 = 0
2181 12:22:39.483737 Vcore = 662500
2182 12:22:39.483833 Vdram = 0
2183 12:22:39.483925 Vddq = 0
2184 12:22:39.487011 Vmddr = 0
2185 12:22:39.490085 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 12:22:39.496965 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 12:22:39.497067 MEM_TYPE=3, freq_sel=15
2188 12:22:39.500392 sv_algorithm_assistance_LP4_1600
2189 12:22:39.507143 ============ PULL DRAM RESETB DOWN ============
2190 12:22:39.510139 ========== PULL DRAM RESETB DOWN end =========
2191 12:22:39.513551 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 12:22:39.517267 ===================================
2193 12:22:39.520284 LPDDR4 DRAM CONFIGURATION
2194 12:22:39.523905 ===================================
2195 12:22:39.526858 EX_ROW_EN[0] = 0x0
2196 12:22:39.526961 EX_ROW_EN[1] = 0x0
2197 12:22:39.530812 LP4Y_EN = 0x0
2198 12:22:39.530898 WORK_FSP = 0x0
2199 12:22:39.533989 WL = 0x4
2200 12:22:39.534072 RL = 0x4
2201 12:22:39.537467 BL = 0x2
2202 12:22:39.537558 RPST = 0x0
2203 12:22:39.540758 RD_PRE = 0x0
2204 12:22:39.540840 WR_PRE = 0x1
2205 12:22:39.543640 WR_PST = 0x0
2206 12:22:39.543723 DBI_WR = 0x0
2207 12:22:39.547428 DBI_RD = 0x0
2208 12:22:39.547509 OTF = 0x1
2209 12:22:39.550238 ===================================
2210 12:22:39.554116 ===================================
2211 12:22:39.557252 ANA top config
2212 12:22:39.560876 ===================================
2213 12:22:39.560959 DLL_ASYNC_EN = 0
2214 12:22:39.564053 ALL_SLAVE_EN = 0
2215 12:22:39.567539 NEW_RANK_MODE = 1
2216 12:22:39.570912 DLL_IDLE_MODE = 1
2217 12:22:39.570997 LP45_APHY_COMB_EN = 1
2218 12:22:39.573882 TX_ODT_DIS = 1
2219 12:22:39.577236 NEW_8X_MODE = 1
2220 12:22:39.580963 ===================================
2221 12:22:39.583976 ===================================
2222 12:22:39.587629 data_rate = 2400
2223 12:22:39.590752 CKR = 1
2224 12:22:39.590852 DQ_P2S_RATIO = 8
2225 12:22:39.594587 ===================================
2226 12:22:39.597523 CA_P2S_RATIO = 8
2227 12:22:39.600829 DQ_CA_OPEN = 0
2228 12:22:39.604326 DQ_SEMI_OPEN = 0
2229 12:22:39.607570 CA_SEMI_OPEN = 0
2230 12:22:39.611223 CA_FULL_RATE = 0
2231 12:22:39.611308 DQ_CKDIV4_EN = 0
2232 12:22:39.614250 CA_CKDIV4_EN = 0
2233 12:22:39.617624 CA_PREDIV_EN = 0
2234 12:22:39.621083 PH8_DLY = 17
2235 12:22:39.624142 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 12:22:39.628083 DQ_AAMCK_DIV = 4
2237 12:22:39.628170 CA_AAMCK_DIV = 4
2238 12:22:39.630957 CA_ADMCK_DIV = 4
2239 12:22:39.634614 DQ_TRACK_CA_EN = 0
2240 12:22:39.637869 CA_PICK = 1200
2241 12:22:39.641231 CA_MCKIO = 1200
2242 12:22:39.644868 MCKIO_SEMI = 0
2243 12:22:39.648056 PLL_FREQ = 2366
2244 12:22:39.648161 DQ_UI_PI_RATIO = 32
2245 12:22:39.651557 CA_UI_PI_RATIO = 0
2246 12:22:39.654637 ===================================
2247 12:22:39.657874 ===================================
2248 12:22:39.661315 memory_type:LPDDR4
2249 12:22:39.664709 GP_NUM : 10
2250 12:22:39.664791 SRAM_EN : 1
2251 12:22:39.667708 MD32_EN : 0
2252 12:22:39.671757 ===================================
2253 12:22:39.671840 [ANA_INIT] >>>>>>>>>>>>>>
2254 12:22:39.674288 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 12:22:39.677905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 12:22:39.681550 ===================================
2257 12:22:39.685092 data_rate = 2400,PCW = 0X5b00
2258 12:22:39.687980 ===================================
2259 12:22:39.691420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 12:22:39.698367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 12:22:39.701287 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 12:22:39.708119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 12:22:39.711608 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 12:22:39.715039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 12:22:39.715156 [ANA_INIT] flow start
2266 12:22:39.718062 [ANA_INIT] PLL >>>>>>>>
2267 12:22:39.721466 [ANA_INIT] PLL <<<<<<<<
2268 12:22:39.721551 [ANA_INIT] MIDPI >>>>>>>>
2269 12:22:39.724712 [ANA_INIT] MIDPI <<<<<<<<
2270 12:22:39.728235 [ANA_INIT] DLL >>>>>>>>
2271 12:22:39.728319 [ANA_INIT] DLL <<<<<<<<
2272 12:22:39.731507 [ANA_INIT] flow end
2273 12:22:39.734964 ============ LP4 DIFF to SE enter ============
2274 12:22:39.741437 ============ LP4 DIFF to SE exit ============
2275 12:22:39.741528 [ANA_INIT] <<<<<<<<<<<<<
2276 12:22:39.745006 [Flow] Enable top DCM control >>>>>
2277 12:22:39.748314 [Flow] Enable top DCM control <<<<<
2278 12:22:39.751683 Enable DLL master slave shuffle
2279 12:22:39.758421 ==============================================================
2280 12:22:39.758520 Gating Mode config
2281 12:22:39.765100 ==============================================================
2282 12:22:39.765206 Config description:
2283 12:22:39.775362 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 12:22:39.782493 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 12:22:39.788740 SELPH_MODE 0: By rank 1: By Phase
2286 12:22:39.791926 ==============================================================
2287 12:22:39.795378 GAT_TRACK_EN = 1
2288 12:22:39.798643 RX_GATING_MODE = 2
2289 12:22:39.801978 RX_GATING_TRACK_MODE = 2
2290 12:22:39.805800 SELPH_MODE = 1
2291 12:22:39.808784 PICG_EARLY_EN = 1
2292 12:22:39.812174 VALID_LAT_VALUE = 1
2293 12:22:39.815561 ==============================================================
2294 12:22:39.819093 Enter into Gating configuration >>>>
2295 12:22:39.822440 Exit from Gating configuration <<<<
2296 12:22:39.825823 Enter into DVFS_PRE_config >>>>>
2297 12:22:39.839037 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 12:22:39.842761 Exit from DVFS_PRE_config <<<<<
2299 12:22:39.842866 Enter into PICG configuration >>>>
2300 12:22:39.845855 Exit from PICG configuration <<<<
2301 12:22:39.849245 [RX_INPUT] configuration >>>>>
2302 12:22:39.852478 [RX_INPUT] configuration <<<<<
2303 12:22:39.859145 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 12:22:39.862616 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 12:22:39.869088 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 12:22:39.876131 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 12:22:39.882815 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 12:22:39.889700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 12:22:39.892487 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 12:22:39.896118 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 12:22:39.900010 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 12:22:39.903451 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 12:22:39.909719 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 12:22:39.912822 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 12:22:39.916508 ===================================
2316 12:22:39.919698 LPDDR4 DRAM CONFIGURATION
2317 12:22:39.923243 ===================================
2318 12:22:39.923337 EX_ROW_EN[0] = 0x0
2319 12:22:39.926583 EX_ROW_EN[1] = 0x0
2320 12:22:39.926682 LP4Y_EN = 0x0
2321 12:22:39.930069 WORK_FSP = 0x0
2322 12:22:39.930141 WL = 0x4
2323 12:22:39.933198 RL = 0x4
2324 12:22:39.933281 BL = 0x2
2325 12:22:39.936721 RPST = 0x0
2326 12:22:39.936793 RD_PRE = 0x0
2327 12:22:39.940050 WR_PRE = 0x1
2328 12:22:39.940121 WR_PST = 0x0
2329 12:22:39.943002 DBI_WR = 0x0
2330 12:22:39.943073 DBI_RD = 0x0
2331 12:22:39.946651 OTF = 0x1
2332 12:22:39.950329 ===================================
2333 12:22:39.952980 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 12:22:39.956813 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 12:22:39.963033 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 12:22:39.966623 ===================================
2337 12:22:39.966771 LPDDR4 DRAM CONFIGURATION
2338 12:22:39.969955 ===================================
2339 12:22:39.973098 EX_ROW_EN[0] = 0x10
2340 12:22:39.976784 EX_ROW_EN[1] = 0x0
2341 12:22:39.976868 LP4Y_EN = 0x0
2342 12:22:39.980097 WORK_FSP = 0x0
2343 12:22:39.980174 WL = 0x4
2344 12:22:39.983440 RL = 0x4
2345 12:22:39.983516 BL = 0x2
2346 12:22:39.986808 RPST = 0x0
2347 12:22:39.986886 RD_PRE = 0x0
2348 12:22:39.990155 WR_PRE = 0x1
2349 12:22:39.990236 WR_PST = 0x0
2350 12:22:39.993515 DBI_WR = 0x0
2351 12:22:39.993585 DBI_RD = 0x0
2352 12:22:39.996522 OTF = 0x1
2353 12:22:40.000029 ===================================
2354 12:22:40.006976 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 12:22:40.007068 ==
2356 12:22:40.010073 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 12:22:40.013466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 12:22:40.013540 ==
2359 12:22:40.016729 [Duty_Offset_Calibration]
2360 12:22:40.016811 B0:2 B1:-1 CA:1
2361 12:22:40.016874
2362 12:22:40.020122 [DutyScan_Calibration_Flow] k_type=0
2363 12:22:40.029062
2364 12:22:40.029157 ==CLK 0==
2365 12:22:40.032729 Final CLK duty delay cell = -4
2366 12:22:40.036166 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2367 12:22:40.039656 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2368 12:22:40.042580 [-4] AVG Duty = 4953%(X100)
2369 12:22:40.042686
2370 12:22:40.045830 CH0 CLK Duty spec in!! Max-Min= 156%
2371 12:22:40.049205 [DutyScan_Calibration_Flow] ====Done====
2372 12:22:40.049283
2373 12:22:40.052427 [DutyScan_Calibration_Flow] k_type=1
2374 12:22:40.068046
2375 12:22:40.068167 ==DQS 0 ==
2376 12:22:40.071645 Final DQS duty delay cell = 0
2377 12:22:40.075210 [0] MAX Duty = 5125%(X100), DQS PI = 46
2378 12:22:40.078229 [0] MIN Duty = 5000%(X100), DQS PI = 14
2379 12:22:40.078305 [0] AVG Duty = 5062%(X100)
2380 12:22:40.078366
2381 12:22:40.081756 ==DQS 1 ==
2382 12:22:40.085144 Final DQS duty delay cell = -4
2383 12:22:40.088719 [-4] MAX Duty = 5124%(X100), DQS PI = 16
2384 12:22:40.091526 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2385 12:22:40.095081 [-4] AVG Duty = 5062%(X100)
2386 12:22:40.095154
2387 12:22:40.098523 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2388 12:22:40.098619
2389 12:22:40.101750 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2390 12:22:40.105597 [DutyScan_Calibration_Flow] ====Done====
2391 12:22:40.105706
2392 12:22:40.108583 [DutyScan_Calibration_Flow] k_type=3
2393 12:22:40.125417
2394 12:22:40.125549 ==DQM 0 ==
2395 12:22:40.128499 Final DQM duty delay cell = 0
2396 12:22:40.131977 [0] MAX Duty = 5000%(X100), DQS PI = 46
2397 12:22:40.135173 [0] MIN Duty = 4907%(X100), DQS PI = 2
2398 12:22:40.135273 [0] AVG Duty = 4953%(X100)
2399 12:22:40.138444
2400 12:22:40.138520 ==DQM 1 ==
2401 12:22:40.142088 Final DQM duty delay cell = 0
2402 12:22:40.144908 [0] MAX Duty = 5156%(X100), DQS PI = 62
2403 12:22:40.148554 [0] MIN Duty = 4969%(X100), DQS PI = 10
2404 12:22:40.148674 [0] AVG Duty = 5062%(X100)
2405 12:22:40.152004
2406 12:22:40.155357 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2407 12:22:40.155434
2408 12:22:40.158606 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2409 12:22:40.161648 [DutyScan_Calibration_Flow] ====Done====
2410 12:22:40.161725
2411 12:22:40.165288 [DutyScan_Calibration_Flow] k_type=2
2412 12:22:40.181025
2413 12:22:40.181164 ==DQ 0 ==
2414 12:22:40.184169 Final DQ duty delay cell = -4
2415 12:22:40.187476 [-4] MAX Duty = 5093%(X100), DQS PI = 54
2416 12:22:40.191121 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2417 12:22:40.194250 [-4] AVG Duty = 4984%(X100)
2418 12:22:40.194332
2419 12:22:40.194404 ==DQ 1 ==
2420 12:22:40.197702 Final DQ duty delay cell = 0
2421 12:22:40.201010 [0] MAX Duty = 5031%(X100), DQS PI = 18
2422 12:22:40.204503 [0] MIN Duty = 4907%(X100), DQS PI = 46
2423 12:22:40.204590 [0] AVG Duty = 4969%(X100)
2424 12:22:40.204660
2425 12:22:40.208228 CH0 DQ 0 Duty spec in!! Max-Min= 217%
2426 12:22:40.208309
2427 12:22:40.211037 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2428 12:22:40.217812 [DutyScan_Calibration_Flow] ====Done====
2429 12:22:40.217906 ==
2430 12:22:40.221426 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 12:22:40.224998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 12:22:40.225085 ==
2433 12:22:40.228052 [Duty_Offset_Calibration]
2434 12:22:40.228136 B0:1 B1:1 CA:2
2435 12:22:40.228200
2436 12:22:40.230994 [DutyScan_Calibration_Flow] k_type=0
2437 12:22:40.241145
2438 12:22:40.241247 ==CLK 0==
2439 12:22:40.244400 Final CLK duty delay cell = 0
2440 12:22:40.247804 [0] MAX Duty = 5156%(X100), DQS PI = 24
2441 12:22:40.250820 [0] MIN Duty = 4969%(X100), DQS PI = 38
2442 12:22:40.250909 [0] AVG Duty = 5062%(X100)
2443 12:22:40.254248
2444 12:22:40.258127 CH1 CLK Duty spec in!! Max-Min= 187%
2445 12:22:40.261323 [DutyScan_Calibration_Flow] ====Done====
2446 12:22:40.261407
2447 12:22:40.264269 [DutyScan_Calibration_Flow] k_type=1
2448 12:22:40.280528
2449 12:22:40.280665 ==DQS 0 ==
2450 12:22:40.283627 Final DQS duty delay cell = 0
2451 12:22:40.287380 [0] MAX Duty = 5031%(X100), DQS PI = 18
2452 12:22:40.290718 [0] MIN Duty = 4844%(X100), DQS PI = 48
2453 12:22:40.290842 [0] AVG Duty = 4937%(X100)
2454 12:22:40.293905
2455 12:22:40.294000 ==DQS 1 ==
2456 12:22:40.297135 Final DQS duty delay cell = 0
2457 12:22:40.300467 [0] MAX Duty = 5062%(X100), DQS PI = 36
2458 12:22:40.303996 [0] MIN Duty = 4907%(X100), DQS PI = 0
2459 12:22:40.304080 [0] AVG Duty = 4984%(X100)
2460 12:22:40.304145
2461 12:22:40.311035 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2462 12:22:40.311126
2463 12:22:40.314272 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2464 12:22:40.316997 [DutyScan_Calibration_Flow] ====Done====
2465 12:22:40.317080
2466 12:22:40.320455 [DutyScan_Calibration_Flow] k_type=3
2467 12:22:40.336947
2468 12:22:40.337077 ==DQM 0 ==
2469 12:22:40.340368 Final DQM duty delay cell = 0
2470 12:22:40.343527 [0] MAX Duty = 5093%(X100), DQS PI = 16
2471 12:22:40.346981 [0] MIN Duty = 4907%(X100), DQS PI = 48
2472 12:22:40.347065 [0] AVG Duty = 5000%(X100)
2473 12:22:40.350148
2474 12:22:40.350232 ==DQM 1 ==
2475 12:22:40.353872 Final DQM duty delay cell = 0
2476 12:22:40.357553 [0] MAX Duty = 5156%(X100), DQS PI = 62
2477 12:22:40.360293 [0] MIN Duty = 4938%(X100), DQS PI = 22
2478 12:22:40.360379 [0] AVG Duty = 5047%(X100)
2479 12:22:40.360443
2480 12:22:40.367558 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2481 12:22:40.367651
2482 12:22:40.370329 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2483 12:22:40.373871 [DutyScan_Calibration_Flow] ====Done====
2484 12:22:40.373955
2485 12:22:40.376867 [DutyScan_Calibration_Flow] k_type=2
2486 12:22:40.393300
2487 12:22:40.393424 ==DQ 0 ==
2488 12:22:40.396785 Final DQ duty delay cell = 0
2489 12:22:40.400211 [0] MAX Duty = 5156%(X100), DQS PI = 18
2490 12:22:40.403721 [0] MIN Duty = 4938%(X100), DQS PI = 50
2491 12:22:40.403803 [0] AVG Duty = 5047%(X100)
2492 12:22:40.403867
2493 12:22:40.406624 ==DQ 1 ==
2494 12:22:40.410106 Final DQ duty delay cell = 0
2495 12:22:40.413683 [0] MAX Duty = 5124%(X100), DQS PI = 58
2496 12:22:40.417014 [0] MIN Duty = 5000%(X100), DQS PI = 2
2497 12:22:40.417098 [0] AVG Duty = 5062%(X100)
2498 12:22:40.417162
2499 12:22:40.420368 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2500 12:22:40.420449
2501 12:22:40.423911 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2502 12:22:40.429962 [DutyScan_Calibration_Flow] ====Done====
2503 12:22:40.433413 nWR fixed to 30
2504 12:22:40.433498 [ModeRegInit_LP4] CH0 RK0
2505 12:22:40.437027 [ModeRegInit_LP4] CH0 RK1
2506 12:22:40.440080 [ModeRegInit_LP4] CH1 RK0
2507 12:22:40.440164 [ModeRegInit_LP4] CH1 RK1
2508 12:22:40.443462 match AC timing 7
2509 12:22:40.447017 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 12:22:40.449986 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 12:22:40.456663 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 12:22:40.460400 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 12:22:40.467121 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 12:22:40.467206 ==
2515 12:22:40.470110 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 12:22:40.473982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 12:22:40.474065 ==
2518 12:22:40.480335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 12:22:40.483446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2520 12:22:40.493622 [CA 0] Center 40 (10~71) winsize 62
2521 12:22:40.496850 [CA 1] Center 39 (9~70) winsize 62
2522 12:22:40.500272 [CA 2] Center 36 (6~67) winsize 62
2523 12:22:40.503613 [CA 3] Center 35 (5~66) winsize 62
2524 12:22:40.506936 [CA 4] Center 35 (5~65) winsize 61
2525 12:22:40.510271 [CA 5] Center 34 (4~65) winsize 62
2526 12:22:40.510358
2527 12:22:40.513802 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2528 12:22:40.513886
2529 12:22:40.517037 [CATrainingPosCal] consider 1 rank data
2530 12:22:40.520369 u2DelayCellTimex100 = 270/100 ps
2531 12:22:40.523874 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2532 12:22:40.527003 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2533 12:22:40.533517 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2534 12:22:40.537202 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2535 12:22:40.540218 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2536 12:22:40.543866 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2537 12:22:40.543950
2538 12:22:40.546983 CA PerBit enable=1, Macro0, CA PI delay=34
2539 12:22:40.547065
2540 12:22:40.550625 [CBTSetCACLKResult] CA Dly = 34
2541 12:22:40.550736 CS Dly: 7 (0~38)
2542 12:22:40.550817 ==
2543 12:22:40.553866 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 12:22:40.560477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 12:22:40.560565 ==
2546 12:22:40.563703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 12:22:40.570456 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2548 12:22:40.579381 [CA 0] Center 39 (9~70) winsize 62
2549 12:22:40.582657 [CA 1] Center 40 (10~70) winsize 61
2550 12:22:40.586050 [CA 2] Center 36 (6~67) winsize 62
2551 12:22:40.589187 [CA 3] Center 35 (5~66) winsize 62
2552 12:22:40.592730 [CA 4] Center 34 (4~65) winsize 62
2553 12:22:40.596076 [CA 5] Center 34 (4~64) winsize 61
2554 12:22:40.596162
2555 12:22:40.599254 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2556 12:22:40.599337
2557 12:22:40.602966 [CATrainingPosCal] consider 2 rank data
2558 12:22:40.606299 u2DelayCellTimex100 = 270/100 ps
2559 12:22:40.609624 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2560 12:22:40.613198 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2561 12:22:40.619565 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2562 12:22:40.622568 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2563 12:22:40.626326 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2564 12:22:40.629359 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2565 12:22:40.629446
2566 12:22:40.632706 CA PerBit enable=1, Macro0, CA PI delay=34
2567 12:22:40.632790
2568 12:22:40.636330 [CBTSetCACLKResult] CA Dly = 34
2569 12:22:40.636417 CS Dly: 8 (0~41)
2570 12:22:40.636482
2571 12:22:40.639392 ----->DramcWriteLeveling(PI) begin...
2572 12:22:40.643085 ==
2573 12:22:40.643176 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 12:22:40.649947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 12:22:40.650071 ==
2576 12:22:40.653084 Write leveling (Byte 0): 32 => 32
2577 12:22:40.656563 Write leveling (Byte 1): 30 => 30
2578 12:22:40.656649 DramcWriteLeveling(PI) end<-----
2579 12:22:40.659975
2580 12:22:40.660058 ==
2581 12:22:40.663079 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 12:22:40.666564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 12:22:40.666653 ==
2584 12:22:40.669867 [Gating] SW mode calibration
2585 12:22:40.676736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 12:22:40.680081 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 12:22:40.686654 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 12:22:40.690243 0 15 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2589 12:22:40.693539 0 15 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2590 12:22:40.700222 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 12:22:40.703558 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 12:22:40.706651 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 12:22:40.710081 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2594 12:22:40.716878 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 12:22:40.720680 1 0 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
2596 12:22:40.723762 1 0 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2597 12:22:40.730264 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 12:22:40.733944 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 12:22:40.736973 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 12:22:40.743948 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 12:22:40.746932 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2602 12:22:40.750804 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 12:22:40.757011 1 1 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2604 12:22:40.760427 1 1 4 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
2605 12:22:40.764348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 12:22:40.767164 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 12:22:40.774280 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 12:22:40.777452 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 12:22:40.780951 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 12:22:40.787843 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 12:22:40.791040 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2612 12:22:40.794377 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2613 12:22:40.801255 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:22:40.804120 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:22:40.807539 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:22:40.814259 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:22:40.817903 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 12:22:40.820970 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 12:22:40.824541 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 12:22:40.830802 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 12:22:40.834404 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 12:22:40.837555 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:22:40.844667 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:22:40.847678 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:22:40.851042 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:22:40.859137 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:22:40.861267 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2628 12:22:40.864498 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2629 12:22:40.867985 Total UI for P1: 0, mck2ui 16
2630 12:22:40.871235 best dqsien dly found for B0: ( 1, 4, 0)
2631 12:22:40.874559 Total UI for P1: 0, mck2ui 16
2632 12:22:40.878039 best dqsien dly found for B1: ( 1, 4, 0)
2633 12:22:40.881267 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2634 12:22:40.884556 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2635 12:22:40.884642
2636 12:22:40.888287 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2637 12:22:40.891750 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 12:22:40.895132 [Gating] SW calibration Done
2639 12:22:40.895219 ==
2640 12:22:40.898526 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 12:22:40.901942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 12:22:40.904722 ==
2643 12:22:40.904806 RX Vref Scan: 0
2644 12:22:40.904872
2645 12:22:40.908434 RX Vref 0 -> 0, step: 1
2646 12:22:40.908516
2647 12:22:40.911434 RX Delay -40 -> 252, step: 8
2648 12:22:40.915014 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2649 12:22:40.918198 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2650 12:22:40.921411 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2651 12:22:40.925139 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2652 12:22:40.931470 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2653 12:22:40.935259 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2654 12:22:40.938969 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2655 12:22:40.942047 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2656 12:22:40.945131 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2657 12:22:40.948850 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2658 12:22:40.955182 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2659 12:22:40.958402 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2660 12:22:40.962158 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2661 12:22:40.965227 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2662 12:22:40.968472 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2663 12:22:40.975552 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2664 12:22:40.975644 ==
2665 12:22:40.978988 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 12:22:40.982291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 12:22:40.982376 ==
2668 12:22:40.982440 DQS Delay:
2669 12:22:40.985850 DQS0 = 0, DQS1 = 0
2670 12:22:40.985932 DQM Delay:
2671 12:22:40.989087 DQM0 = 116, DQM1 = 106
2672 12:22:40.989194 DQ Delay:
2673 12:22:40.992298 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2674 12:22:40.995941 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2675 12:22:40.999093 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2676 12:22:41.002427 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2677 12:22:41.002511
2678 12:22:41.002574
2679 12:22:41.002633 ==
2680 12:22:41.005955 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 12:22:41.009272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 12:22:41.012886 ==
2683 12:22:41.012969
2684 12:22:41.013033
2685 12:22:41.013092 TX Vref Scan disable
2686 12:22:41.016294 == TX Byte 0 ==
2687 12:22:41.019355 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2688 12:22:41.022776 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2689 12:22:41.025987 == TX Byte 1 ==
2690 12:22:41.029470 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2691 12:22:41.032473 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2692 12:22:41.032555 ==
2693 12:22:41.035929 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 12:22:41.042375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 12:22:41.042461 ==
2696 12:22:41.053505 TX Vref=22, minBit 1, minWin=25, winSum=418
2697 12:22:41.057466 TX Vref=24, minBit 7, minWin=25, winSum=421
2698 12:22:41.060811 TX Vref=26, minBit 0, minWin=26, winSum=427
2699 12:22:41.063502 TX Vref=28, minBit 1, minWin=26, winSum=432
2700 12:22:41.066856 TX Vref=30, minBit 0, minWin=26, winSum=433
2701 12:22:41.070268 TX Vref=32, minBit 0, minWin=26, winSum=429
2702 12:22:41.077166 [TxChooseVref] Worse bit 0, Min win 26, Win sum 433, Final Vref 30
2703 12:22:41.077262
2704 12:22:41.080860 Final TX Range 1 Vref 30
2705 12:22:41.080945
2706 12:22:41.081014 ==
2707 12:22:41.083988 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 12:22:41.087242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 12:22:41.087378 ==
2710 12:22:41.087494
2711 12:22:41.087604
2712 12:22:41.090634 TX Vref Scan disable
2713 12:22:41.094235 == TX Byte 0 ==
2714 12:22:41.097336 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2715 12:22:41.100825 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2716 12:22:41.104190 == TX Byte 1 ==
2717 12:22:41.107246 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2718 12:22:41.110807 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2719 12:22:41.110894
2720 12:22:41.114110 [DATLAT]
2721 12:22:41.114242 Freq=1200, CH0 RK0
2722 12:22:41.114336
2723 12:22:41.117674 DATLAT Default: 0xd
2724 12:22:41.117787 0, 0xFFFF, sum = 0
2725 12:22:41.120946 1, 0xFFFF, sum = 0
2726 12:22:41.121057 2, 0xFFFF, sum = 0
2727 12:22:41.124101 3, 0xFFFF, sum = 0
2728 12:22:41.124206 4, 0xFFFF, sum = 0
2729 12:22:41.127543 5, 0xFFFF, sum = 0
2730 12:22:41.127621 6, 0xFFFF, sum = 0
2731 12:22:41.130873 7, 0xFFFF, sum = 0
2732 12:22:41.130956 8, 0xFFFF, sum = 0
2733 12:22:41.134049 9, 0xFFFF, sum = 0
2734 12:22:41.134132 10, 0xFFFF, sum = 0
2735 12:22:41.137405 11, 0xFFFF, sum = 0
2736 12:22:41.137488 12, 0x0, sum = 1
2737 12:22:41.140654 13, 0x0, sum = 2
2738 12:22:41.140737 14, 0x0, sum = 3
2739 12:22:41.144267 15, 0x0, sum = 4
2740 12:22:41.144351 best_step = 13
2741 12:22:41.144415
2742 12:22:41.144475 ==
2743 12:22:41.147581 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 12:22:41.153998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 12:22:41.154082 ==
2746 12:22:41.154147 RX Vref Scan: 1
2747 12:22:41.154207
2748 12:22:41.157451 Set Vref Range= 32 -> 127
2749 12:22:41.157533
2750 12:22:41.160875 RX Vref 32 -> 127, step: 1
2751 12:22:41.160956
2752 12:22:41.161020 RX Delay -21 -> 252, step: 4
2753 12:22:41.161079
2754 12:22:41.164533 Set Vref, RX VrefLevel [Byte0]: 32
2755 12:22:41.167359 [Byte1]: 32
2756 12:22:41.172038
2757 12:22:41.172120 Set Vref, RX VrefLevel [Byte0]: 33
2758 12:22:41.175361 [Byte1]: 33
2759 12:22:41.179734
2760 12:22:41.179816 Set Vref, RX VrefLevel [Byte0]: 34
2761 12:22:41.183070 [Byte1]: 34
2762 12:22:41.187833
2763 12:22:41.187917 Set Vref, RX VrefLevel [Byte0]: 35
2764 12:22:41.191183 [Byte1]: 35
2765 12:22:41.195546
2766 12:22:41.195628 Set Vref, RX VrefLevel [Byte0]: 36
2767 12:22:41.198870 [Byte1]: 36
2768 12:22:41.203645
2769 12:22:41.203729 Set Vref, RX VrefLevel [Byte0]: 37
2770 12:22:41.206896 [Byte1]: 37
2771 12:22:41.211344
2772 12:22:41.211429 Set Vref, RX VrefLevel [Byte0]: 38
2773 12:22:41.214652 [Byte1]: 38
2774 12:22:41.219366
2775 12:22:41.219450 Set Vref, RX VrefLevel [Byte0]: 39
2776 12:22:41.222915 [Byte1]: 39
2777 12:22:41.227386
2778 12:22:41.227470 Set Vref, RX VrefLevel [Byte0]: 40
2779 12:22:41.230886 [Byte1]: 40
2780 12:22:41.235534
2781 12:22:41.235681 Set Vref, RX VrefLevel [Byte0]: 41
2782 12:22:41.238657 [Byte1]: 41
2783 12:22:41.243387
2784 12:22:41.243471 Set Vref, RX VrefLevel [Byte0]: 42
2785 12:22:41.246998 [Byte1]: 42
2786 12:22:41.251345
2787 12:22:41.251429 Set Vref, RX VrefLevel [Byte0]: 43
2788 12:22:41.254647 [Byte1]: 43
2789 12:22:41.259219
2790 12:22:41.259300 Set Vref, RX VrefLevel [Byte0]: 44
2791 12:22:41.262245 [Byte1]: 44
2792 12:22:41.266863
2793 12:22:41.266945 Set Vref, RX VrefLevel [Byte0]: 45
2794 12:22:41.270453 [Byte1]: 45
2795 12:22:41.275016
2796 12:22:41.275098 Set Vref, RX VrefLevel [Byte0]: 46
2797 12:22:41.278191 [Byte1]: 46
2798 12:22:41.282690
2799 12:22:41.282816 Set Vref, RX VrefLevel [Byte0]: 47
2800 12:22:41.286310 [Byte1]: 47
2801 12:22:41.290876
2802 12:22:41.290958 Set Vref, RX VrefLevel [Byte0]: 48
2803 12:22:41.294125 [Byte1]: 48
2804 12:22:41.298518
2805 12:22:41.298601 Set Vref, RX VrefLevel [Byte0]: 49
2806 12:22:41.302009 [Byte1]: 49
2807 12:22:41.307046
2808 12:22:41.307126 Set Vref, RX VrefLevel [Byte0]: 50
2809 12:22:41.310259 [Byte1]: 50
2810 12:22:41.314702
2811 12:22:41.314831 Set Vref, RX VrefLevel [Byte0]: 51
2812 12:22:41.318249 [Byte1]: 51
2813 12:22:41.322571
2814 12:22:41.322652 Set Vref, RX VrefLevel [Byte0]: 52
2815 12:22:41.325636 [Byte1]: 52
2816 12:22:41.330321
2817 12:22:41.330401 Set Vref, RX VrefLevel [Byte0]: 53
2818 12:22:41.333821 [Byte1]: 53
2819 12:22:41.338420
2820 12:22:41.338501 Set Vref, RX VrefLevel [Byte0]: 54
2821 12:22:41.341894 [Byte1]: 54
2822 12:22:41.346549
2823 12:22:41.346630 Set Vref, RX VrefLevel [Byte0]: 55
2824 12:22:41.349521 [Byte1]: 55
2825 12:22:41.354042
2826 12:22:41.354123 Set Vref, RX VrefLevel [Byte0]: 56
2827 12:22:41.357270 [Byte1]: 56
2828 12:22:41.362491
2829 12:22:41.362572 Set Vref, RX VrefLevel [Byte0]: 57
2830 12:22:41.365289 [Byte1]: 57
2831 12:22:41.369833
2832 12:22:41.369913 Set Vref, RX VrefLevel [Byte0]: 58
2833 12:22:41.373319 [Byte1]: 58
2834 12:22:41.377966
2835 12:22:41.378046 Set Vref, RX VrefLevel [Byte0]: 59
2836 12:22:41.381506 [Byte1]: 59
2837 12:22:41.385890
2838 12:22:41.385973 Set Vref, RX VrefLevel [Byte0]: 60
2839 12:22:41.389321 [Byte1]: 60
2840 12:22:41.393951
2841 12:22:41.394058 Set Vref, RX VrefLevel [Byte0]: 61
2842 12:22:41.397321 [Byte1]: 61
2843 12:22:41.401986
2844 12:22:41.402068 Set Vref, RX VrefLevel [Byte0]: 62
2845 12:22:41.405482 [Byte1]: 62
2846 12:22:41.409795
2847 12:22:41.409877 Set Vref, RX VrefLevel [Byte0]: 63
2848 12:22:41.412839 [Byte1]: 63
2849 12:22:41.418050
2850 12:22:41.418131 Set Vref, RX VrefLevel [Byte0]: 64
2851 12:22:41.420775 [Byte1]: 64
2852 12:22:41.426038
2853 12:22:41.426120 Set Vref, RX VrefLevel [Byte0]: 65
2854 12:22:41.429035 [Byte1]: 65
2855 12:22:41.433373
2856 12:22:41.433476 Set Vref, RX VrefLevel [Byte0]: 66
2857 12:22:41.436823 [Byte1]: 66
2858 12:22:41.441144
2859 12:22:41.441246 Set Vref, RX VrefLevel [Byte0]: 67
2860 12:22:41.444993 [Byte1]: 67
2861 12:22:41.449499
2862 12:22:41.449580 Set Vref, RX VrefLevel [Byte0]: 68
2863 12:22:41.453058 [Byte1]: 68
2864 12:22:41.457456
2865 12:22:41.457538 Final RX Vref Byte 0 = 54 to rank0
2866 12:22:41.460670 Final RX Vref Byte 1 = 50 to rank0
2867 12:22:41.463933 Final RX Vref Byte 0 = 54 to rank1
2868 12:22:41.467914 Final RX Vref Byte 1 = 50 to rank1==
2869 12:22:41.470621 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 12:22:41.477531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 12:22:41.477651 ==
2872 12:22:41.477719 DQS Delay:
2873 12:22:41.477779 DQS0 = 0, DQS1 = 0
2874 12:22:41.480513 DQM Delay:
2875 12:22:41.480598 DQM0 = 115, DQM1 = 104
2876 12:22:41.484217 DQ Delay:
2877 12:22:41.487240 DQ0 =116, DQ1 =114, DQ2 =112, DQ3 =114
2878 12:22:41.490969 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2879 12:22:41.494157 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2880 12:22:41.497535 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2881 12:22:41.497625
2882 12:22:41.497689
2883 12:22:41.504445 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2884 12:22:41.507708 CH0 RK0: MR19=303, MR18=FDEC
2885 12:22:41.514698 CH0_RK0: MR19=0x303, MR18=0xFDEC, DQSOSC=411, MR23=63, INC=38, DEC=25
2886 12:22:41.514858
2887 12:22:41.517456 ----->DramcWriteLeveling(PI) begin...
2888 12:22:41.517576 ==
2889 12:22:41.520893 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 12:22:41.524272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 12:22:41.524367 ==
2892 12:22:41.527734 Write leveling (Byte 0): 32 => 32
2893 12:22:41.530976 Write leveling (Byte 1): 26 => 26
2894 12:22:41.534461 DramcWriteLeveling(PI) end<-----
2895 12:22:41.534570
2896 12:22:41.534636 ==
2897 12:22:41.537659 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 12:22:41.540933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 12:22:41.541062 ==
2900 12:22:41.544412 [Gating] SW mode calibration
2901 12:22:41.551609 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 12:22:41.557972 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 12:22:41.561112 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2904 12:22:41.567921 0 15 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2905 12:22:41.571254 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 12:22:41.574923 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 12:22:41.578014 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 12:22:41.584884 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 12:22:41.588194 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 12:22:41.591127 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2911 12:22:41.598018 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
2912 12:22:41.601479 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 12:22:41.605402 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 12:22:41.611560 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 12:22:41.615112 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 12:22:41.618241 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 12:22:41.625264 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2918 12:22:41.628565 1 0 28 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
2919 12:22:41.631467 1 1 0 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
2920 12:22:41.634928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 12:22:41.641672 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 12:22:41.644949 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 12:22:41.648547 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 12:22:41.655081 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 12:22:41.658625 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2926 12:22:41.661966 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2927 12:22:41.668497 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2928 12:22:41.671676 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2929 12:22:41.675111 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:22:41.681932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:22:41.685503 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:22:41.688953 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 12:22:41.695490 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 12:22:41.698546 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 12:22:41.702261 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 12:22:41.705343 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 12:22:41.712377 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 12:22:41.715591 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 12:22:41.719120 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 12:22:41.725595 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 12:22:41.729433 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2942 12:22:41.732280 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2943 12:22:41.739074 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2944 12:22:41.739161 Total UI for P1: 0, mck2ui 16
2945 12:22:41.746033 best dqsien dly found for B0: ( 1, 3, 26)
2946 12:22:41.749585 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2947 12:22:41.752631 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 12:22:41.755929 Total UI for P1: 0, mck2ui 16
2949 12:22:41.759617 best dqsien dly found for B1: ( 1, 4, 0)
2950 12:22:41.762862 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2951 12:22:41.766364 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2952 12:22:41.766446
2953 12:22:41.769953 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2954 12:22:41.772786 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2955 12:22:41.776336 [Gating] SW calibration Done
2956 12:22:41.776419 ==
2957 12:22:41.779743 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 12:22:41.782681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 12:22:41.786519 ==
2960 12:22:41.786626 RX Vref Scan: 0
2961 12:22:41.786728
2962 12:22:41.789500 RX Vref 0 -> 0, step: 1
2963 12:22:41.789581
2964 12:22:41.789644 RX Delay -40 -> 252, step: 8
2965 12:22:41.796755 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2966 12:22:41.799706 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2967 12:22:41.802999 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2968 12:22:41.806802 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2969 12:22:41.810281 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2970 12:22:41.816795 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2971 12:22:41.819851 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2972 12:22:41.823257 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2973 12:22:41.826756 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2974 12:22:41.830556 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2975 12:22:41.833622 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2976 12:22:41.840380 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2977 12:22:41.843612 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2978 12:22:41.847019 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2979 12:22:41.850620 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2980 12:22:41.853545 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2981 12:22:41.856974 ==
2982 12:22:41.860145 Dram Type= 6, Freq= 0, CH_0, rank 1
2983 12:22:41.864178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2984 12:22:41.864261 ==
2985 12:22:41.864325 DQS Delay:
2986 12:22:41.867008 DQS0 = 0, DQS1 = 0
2987 12:22:41.867089 DQM Delay:
2988 12:22:41.870393 DQM0 = 115, DQM1 = 105
2989 12:22:41.870505 DQ Delay:
2990 12:22:41.873578 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2991 12:22:41.876995 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2992 12:22:41.880497 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
2993 12:22:41.883596 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2994 12:22:41.883678
2995 12:22:41.883742
2996 12:22:41.883801 ==
2997 12:22:41.887564 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 12:22:41.890800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 12:22:41.894043 ==
3000 12:22:41.894126
3001 12:22:41.894190
3002 12:22:41.894249 TX Vref Scan disable
3003 12:22:41.897414 == TX Byte 0 ==
3004 12:22:41.900574 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3005 12:22:41.904266 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3006 12:22:41.907538 == TX Byte 1 ==
3007 12:22:41.910629 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3008 12:22:41.914244 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3009 12:22:41.914327 ==
3010 12:22:41.917420 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 12:22:41.924112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 12:22:41.924194 ==
3013 12:22:41.935362 TX Vref=22, minBit 1, minWin=26, winSum=425
3014 12:22:41.938573 TX Vref=24, minBit 0, minWin=26, winSum=426
3015 12:22:41.942008 TX Vref=26, minBit 3, minWin=26, winSum=432
3016 12:22:41.945266 TX Vref=28, minBit 3, minWin=26, winSum=432
3017 12:22:41.948561 TX Vref=30, minBit 3, minWin=26, winSum=434
3018 12:22:41.952041 TX Vref=32, minBit 0, minWin=27, winSum=438
3019 12:22:41.958663 [TxChooseVref] Worse bit 0, Min win 27, Win sum 438, Final Vref 32
3020 12:22:41.958773
3021 12:22:41.962385 Final TX Range 1 Vref 32
3022 12:22:41.962467
3023 12:22:41.962532 ==
3024 12:22:41.965556 Dram Type= 6, Freq= 0, CH_0, rank 1
3025 12:22:41.969056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3026 12:22:41.969139 ==
3027 12:22:41.969205
3028 12:22:41.969265
3029 12:22:41.972317 TX Vref Scan disable
3030 12:22:41.975670 == TX Byte 0 ==
3031 12:22:41.978601 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3032 12:22:41.982065 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3033 12:22:41.985449 == TX Byte 1 ==
3034 12:22:41.988863 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3035 12:22:41.992511 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3036 12:22:41.992593
3037 12:22:41.995617 [DATLAT]
3038 12:22:41.995698 Freq=1200, CH0 RK1
3039 12:22:41.995763
3040 12:22:41.999098 DATLAT Default: 0xd
3041 12:22:41.999180 0, 0xFFFF, sum = 0
3042 12:22:42.002704 1, 0xFFFF, sum = 0
3043 12:22:42.002829 2, 0xFFFF, sum = 0
3044 12:22:42.005653 3, 0xFFFF, sum = 0
3045 12:22:42.005736 4, 0xFFFF, sum = 0
3046 12:22:42.009151 5, 0xFFFF, sum = 0
3047 12:22:42.009235 6, 0xFFFF, sum = 0
3048 12:22:42.012325 7, 0xFFFF, sum = 0
3049 12:22:42.012434 8, 0xFFFF, sum = 0
3050 12:22:42.015739 9, 0xFFFF, sum = 0
3051 12:22:42.015821 10, 0xFFFF, sum = 0
3052 12:22:42.019076 11, 0xFFFF, sum = 0
3053 12:22:42.019158 12, 0x0, sum = 1
3054 12:22:42.022622 13, 0x0, sum = 2
3055 12:22:42.022705 14, 0x0, sum = 3
3056 12:22:42.026076 15, 0x0, sum = 4
3057 12:22:42.026158 best_step = 13
3058 12:22:42.026221
3059 12:22:42.026280 ==
3060 12:22:42.029200 Dram Type= 6, Freq= 0, CH_0, rank 1
3061 12:22:42.032930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 12:22:42.036509 ==
3063 12:22:42.036610 RX Vref Scan: 0
3064 12:22:42.036678
3065 12:22:42.039564 RX Vref 0 -> 0, step: 1
3066 12:22:42.039671
3067 12:22:42.042695 RX Delay -21 -> 252, step: 4
3068 12:22:42.046150 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3069 12:22:42.049586 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3070 12:22:42.052874 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3071 12:22:42.059743 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3072 12:22:42.062603 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3073 12:22:42.066082 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3074 12:22:42.069380 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3075 12:22:42.073263 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3076 12:22:42.076188 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3077 12:22:42.083121 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3078 12:22:42.086380 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3079 12:22:42.089697 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3080 12:22:42.093265 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3081 12:22:42.096503 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3082 12:22:42.102924 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3083 12:22:42.106463 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3084 12:22:42.106545 ==
3085 12:22:42.109863 Dram Type= 6, Freq= 0, CH_0, rank 1
3086 12:22:42.113188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 12:22:42.113270 ==
3088 12:22:42.116430 DQS Delay:
3089 12:22:42.116511 DQS0 = 0, DQS1 = 0
3090 12:22:42.116575 DQM Delay:
3091 12:22:42.119892 DQM0 = 114, DQM1 = 104
3092 12:22:42.119972 DQ Delay:
3093 12:22:42.123546 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3094 12:22:42.126544 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3095 12:22:42.130645 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3096 12:22:42.133359 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3097 12:22:42.133441
3098 12:22:42.137094
3099 12:22:42.143520 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3100 12:22:42.147051 CH0 RK1: MR19=403, MR18=F1
3101 12:22:42.150007 CH0_RK1: MR19=0x403, MR18=0xF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3102 12:22:42.153672 [RxdqsGatingPostProcess] freq 1200
3103 12:22:42.160307 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3104 12:22:42.163655 best DQS0 dly(2T, 0.5T) = (0, 12)
3105 12:22:42.167024 best DQS1 dly(2T, 0.5T) = (0, 12)
3106 12:22:42.170316 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3107 12:22:42.173591 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3108 12:22:42.177083 best DQS0 dly(2T, 0.5T) = (0, 11)
3109 12:22:42.177166 best DQS1 dly(2T, 0.5T) = (0, 12)
3110 12:22:42.180888 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3111 12:22:42.183692 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3112 12:22:42.187290 Pre-setting of DQS Precalculation
3113 12:22:42.193718 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3114 12:22:42.193804 ==
3115 12:22:42.197126 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 12:22:42.200483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 12:22:42.200568 ==
3118 12:22:42.207167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3119 12:22:42.210579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3120 12:22:42.220821 [CA 0] Center 38 (8~68) winsize 61
3121 12:22:42.223968 [CA 1] Center 38 (9~68) winsize 60
3122 12:22:42.227447 [CA 2] Center 35 (5~65) winsize 61
3123 12:22:42.230649 [CA 3] Center 34 (4~65) winsize 62
3124 12:22:42.234096 [CA 4] Center 35 (5~65) winsize 61
3125 12:22:42.237617 [CA 5] Center 33 (3~64) winsize 62
3126 12:22:42.237700
3127 12:22:42.241436 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3128 12:22:42.241520
3129 12:22:42.244032 [CATrainingPosCal] consider 1 rank data
3130 12:22:42.247377 u2DelayCellTimex100 = 270/100 ps
3131 12:22:42.251227 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3132 12:22:42.254461 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3133 12:22:42.257897 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3134 12:22:42.261218 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3135 12:22:42.267690 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3136 12:22:42.271217 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3137 12:22:42.271303
3138 12:22:42.274564 CA PerBit enable=1, Macro0, CA PI delay=33
3139 12:22:42.274647
3140 12:22:42.277603 [CBTSetCACLKResult] CA Dly = 33
3141 12:22:42.277685 CS Dly: 6 (0~37)
3142 12:22:42.277749 ==
3143 12:22:42.281626 Dram Type= 6, Freq= 0, CH_1, rank 1
3144 12:22:42.284743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 12:22:42.288164 ==
3146 12:22:42.291107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3147 12:22:42.297741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3148 12:22:42.305824 [CA 0] Center 38 (8~68) winsize 61
3149 12:22:42.309433 [CA 1] Center 37 (8~67) winsize 60
3150 12:22:42.313061 [CA 2] Center 35 (5~65) winsize 61
3151 12:22:42.316143 [CA 3] Center 34 (4~65) winsize 62
3152 12:22:42.319531 [CA 4] Center 34 (4~65) winsize 62
3153 12:22:42.322830 [CA 5] Center 33 (3~64) winsize 62
3154 12:22:42.323023
3155 12:22:42.326237 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3156 12:22:42.326345
3157 12:22:42.329263 [CATrainingPosCal] consider 2 rank data
3158 12:22:42.332728 u2DelayCellTimex100 = 270/100 ps
3159 12:22:42.336649 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3160 12:22:42.339328 CA1 delay=38 (9~67),Diff = 5 PI (24 cell)
3161 12:22:42.343074 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3162 12:22:42.349716 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3163 12:22:42.353072 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3164 12:22:42.356450 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3165 12:22:42.356536
3166 12:22:42.359921 CA PerBit enable=1, Macro0, CA PI delay=33
3167 12:22:42.360004
3168 12:22:42.363159 [CBTSetCACLKResult] CA Dly = 33
3169 12:22:42.363242 CS Dly: 7 (0~40)
3170 12:22:42.363307
3171 12:22:42.366653 ----->DramcWriteLeveling(PI) begin...
3172 12:22:42.366774 ==
3173 12:22:42.370143 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 12:22:42.376251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 12:22:42.376338 ==
3176 12:22:42.379998 Write leveling (Byte 0): 29 => 29
3177 12:22:42.382926 Write leveling (Byte 1): 30 => 30
3178 12:22:42.383064 DramcWriteLeveling(PI) end<-----
3179 12:22:42.383159
3180 12:22:42.386385 ==
3181 12:22:42.389737 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 12:22:42.393273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 12:22:42.393355 ==
3184 12:22:42.396770 [Gating] SW mode calibration
3185 12:22:42.403207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3186 12:22:42.406587 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3187 12:22:42.413385 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3188 12:22:42.417023 0 15 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
3189 12:22:42.420247 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 12:22:42.427109 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 12:22:42.430311 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 12:22:42.433212 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 12:22:42.436530 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 12:22:42.443536 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3195 12:22:42.446629 1 0 0 | B1->B0 | 2424 2c2c | 0 0 | (1 0) (0 0)
3196 12:22:42.449869 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3197 12:22:42.456882 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 12:22:42.460273 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3199 12:22:42.464023 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 12:22:42.470060 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 12:22:42.473731 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 12:22:42.476956 1 0 28 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
3203 12:22:42.484130 1 1 0 | B1->B0 | 4242 3a3a | 0 1 | (0 0) (0 0)
3204 12:22:42.486894 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 12:22:42.490647 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 12:22:42.497369 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 12:22:42.500241 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 12:22:42.503750 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 12:22:42.507331 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 12:22:42.513727 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 12:22:42.517315 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3212 12:22:42.520658 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:22:42.527624 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:22:42.530855 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 12:22:42.533828 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 12:22:42.540834 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 12:22:42.544373 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 12:22:42.547582 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 12:22:42.551078 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 12:22:42.557517 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 12:22:42.561001 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 12:22:42.564219 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 12:22:42.570675 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:22:42.574544 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 12:22:42.577960 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:22:42.584366 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3227 12:22:42.587700 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3228 12:22:42.590854 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 12:22:42.594525 Total UI for P1: 0, mck2ui 16
3230 12:22:42.598113 best dqsien dly found for B0: ( 1, 3, 30)
3231 12:22:42.600880 Total UI for P1: 0, mck2ui 16
3232 12:22:42.604286 best dqsien dly found for B1: ( 1, 3, 30)
3233 12:22:42.607648 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3234 12:22:42.611407 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3235 12:22:42.611503
3236 12:22:42.614531 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3237 12:22:42.621324 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3238 12:22:42.621421 [Gating] SW calibration Done
3239 12:22:42.621486 ==
3240 12:22:42.624663 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 12:22:42.631325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 12:22:42.631421 ==
3243 12:22:42.631506 RX Vref Scan: 0
3244 12:22:42.631587
3245 12:22:42.634718 RX Vref 0 -> 0, step: 1
3246 12:22:42.634865
3247 12:22:42.638178 RX Delay -40 -> 252, step: 8
3248 12:22:42.641430 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3249 12:22:42.644921 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3250 12:22:42.648384 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3251 12:22:42.651546 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3252 12:22:42.658268 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3253 12:22:42.661558 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3254 12:22:42.664826 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3255 12:22:42.668202 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3256 12:22:42.671589 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3257 12:22:42.675533 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3258 12:22:42.681965 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3259 12:22:42.684838 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3260 12:22:42.688152 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3261 12:22:42.692030 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3262 12:22:42.698323 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3263 12:22:42.706640 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3264 12:22:42.706799 ==
3265 12:22:42.706867 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 12:22:42.708378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 12:22:42.708461 ==
3268 12:22:42.708526 DQS Delay:
3269 12:22:42.711792 DQS0 = 0, DQS1 = 0
3270 12:22:42.711877 DQM Delay:
3271 12:22:42.715171 DQM0 = 116, DQM1 = 109
3272 12:22:42.715256 DQ Delay:
3273 12:22:42.718585 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3274 12:22:42.721719 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3275 12:22:42.725169 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3276 12:22:42.728411 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3277 12:22:42.728498
3278 12:22:42.728562
3279 12:22:42.732054 ==
3280 12:22:42.735260 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 12:22:42.738480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 12:22:42.738566 ==
3283 12:22:42.738632
3284 12:22:42.738709
3285 12:22:42.741813 TX Vref Scan disable
3286 12:22:42.741934 == TX Byte 0 ==
3287 12:22:42.745233 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3288 12:22:42.751883 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3289 12:22:42.751998 == TX Byte 1 ==
3290 12:22:42.755335 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3291 12:22:42.762280 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3292 12:22:42.762379 ==
3293 12:22:42.766214 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 12:22:42.768717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 12:22:42.768801 ==
3296 12:22:42.780580 TX Vref=22, minBit 2, minWin=25, winSum=413
3297 12:22:42.783692 TX Vref=24, minBit 2, minWin=25, winSum=419
3298 12:22:42.787128 TX Vref=26, minBit 2, minWin=25, winSum=424
3299 12:22:42.790687 TX Vref=28, minBit 15, minWin=25, winSum=428
3300 12:22:42.793746 TX Vref=30, minBit 13, minWin=25, winSum=429
3301 12:22:42.797512 TX Vref=32, minBit 15, minWin=25, winSum=426
3302 12:22:42.803817 [TxChooseVref] Worse bit 13, Min win 25, Win sum 429, Final Vref 30
3303 12:22:42.803931
3304 12:22:42.807221 Final TX Range 1 Vref 30
3305 12:22:42.807314
3306 12:22:42.807379 ==
3307 12:22:42.810630 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 12:22:42.814066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 12:22:42.814164 ==
3310 12:22:42.814229
3311 12:22:42.817547
3312 12:22:42.817634 TX Vref Scan disable
3313 12:22:42.821369 == TX Byte 0 ==
3314 12:22:42.824177 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3315 12:22:42.827497 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3316 12:22:42.830864 == TX Byte 1 ==
3317 12:22:42.834359 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3318 12:22:42.837474 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3319 12:22:42.837615
3320 12:22:42.841489 [DATLAT]
3321 12:22:42.841619 Freq=1200, CH1 RK0
3322 12:22:42.841734
3323 12:22:42.844645 DATLAT Default: 0xd
3324 12:22:42.844765 0, 0xFFFF, sum = 0
3325 12:22:42.847737 1, 0xFFFF, sum = 0
3326 12:22:42.847823 2, 0xFFFF, sum = 0
3327 12:22:42.851134 3, 0xFFFF, sum = 0
3328 12:22:42.851276 4, 0xFFFF, sum = 0
3329 12:22:42.854542 5, 0xFFFF, sum = 0
3330 12:22:42.854646 6, 0xFFFF, sum = 0
3331 12:22:42.858075 7, 0xFFFF, sum = 0
3332 12:22:42.858160 8, 0xFFFF, sum = 0
3333 12:22:42.861449 9, 0xFFFF, sum = 0
3334 12:22:42.861588 10, 0xFFFF, sum = 0
3335 12:22:42.864555 11, 0xFFFF, sum = 0
3336 12:22:42.864640 12, 0x0, sum = 1
3337 12:22:42.868113 13, 0x0, sum = 2
3338 12:22:42.868203 14, 0x0, sum = 3
3339 12:22:42.871206 15, 0x0, sum = 4
3340 12:22:42.871296 best_step = 13
3341 12:22:42.871360
3342 12:22:42.871420 ==
3343 12:22:42.874847 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 12:22:42.881393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 12:22:42.881500 ==
3346 12:22:42.881566 RX Vref Scan: 1
3347 12:22:42.881637
3348 12:22:42.884557 Set Vref Range= 32 -> 127
3349 12:22:42.884642
3350 12:22:42.888376 RX Vref 32 -> 127, step: 1
3351 12:22:42.888464
3352 12:22:42.888530 RX Delay -21 -> 252, step: 4
3353 12:22:42.888589
3354 12:22:42.891429 Set Vref, RX VrefLevel [Byte0]: 32
3355 12:22:42.894764 [Byte1]: 32
3356 12:22:42.899371
3357 12:22:42.899467 Set Vref, RX VrefLevel [Byte0]: 33
3358 12:22:42.902464 [Byte1]: 33
3359 12:22:42.906963
3360 12:22:42.907071 Set Vref, RX VrefLevel [Byte0]: 34
3361 12:22:42.910343 [Byte1]: 34
3362 12:22:42.915006
3363 12:22:42.915108 Set Vref, RX VrefLevel [Byte0]: 35
3364 12:22:42.917912 [Byte1]: 35
3365 12:22:42.922971
3366 12:22:42.923068 Set Vref, RX VrefLevel [Byte0]: 36
3367 12:22:42.926127 [Byte1]: 36
3368 12:22:42.930952
3369 12:22:42.931077 Set Vref, RX VrefLevel [Byte0]: 37
3370 12:22:42.934082 [Byte1]: 37
3371 12:22:42.939096
3372 12:22:42.939187 Set Vref, RX VrefLevel [Byte0]: 38
3373 12:22:42.941980 [Byte1]: 38
3374 12:22:42.946446
3375 12:22:42.946535 Set Vref, RX VrefLevel [Byte0]: 39
3376 12:22:42.949775 [Byte1]: 39
3377 12:22:42.954239
3378 12:22:42.954355 Set Vref, RX VrefLevel [Byte0]: 40
3379 12:22:42.961038 [Byte1]: 40
3380 12:22:42.961143
3381 12:22:42.964161 Set Vref, RX VrefLevel [Byte0]: 41
3382 12:22:42.967818 [Byte1]: 41
3383 12:22:42.967920
3384 12:22:42.971367 Set Vref, RX VrefLevel [Byte0]: 42
3385 12:22:42.974227 [Byte1]: 42
3386 12:22:42.978136
3387 12:22:42.978225 Set Vref, RX VrefLevel [Byte0]: 43
3388 12:22:42.982462 [Byte1]: 43
3389 12:22:42.986067
3390 12:22:42.986159 Set Vref, RX VrefLevel [Byte0]: 44
3391 12:22:42.989351 [Byte1]: 44
3392 12:22:42.994331
3393 12:22:42.994464 Set Vref, RX VrefLevel [Byte0]: 45
3394 12:22:42.997721 [Byte1]: 45
3395 12:22:43.001950
3396 12:22:43.002076 Set Vref, RX VrefLevel [Byte0]: 46
3397 12:22:43.005137 [Byte1]: 46
3398 12:22:43.009762
3399 12:22:43.009857 Set Vref, RX VrefLevel [Byte0]: 47
3400 12:22:43.013580 [Byte1]: 47
3401 12:22:43.017990
3402 12:22:43.018085 Set Vref, RX VrefLevel [Byte0]: 48
3403 12:22:43.021125 [Byte1]: 48
3404 12:22:43.026357
3405 12:22:43.026451 Set Vref, RX VrefLevel [Byte0]: 49
3406 12:22:43.029129 [Byte1]: 49
3407 12:22:43.033704
3408 12:22:43.033828 Set Vref, RX VrefLevel [Byte0]: 50
3409 12:22:43.037202 [Byte1]: 50
3410 12:22:43.041327
3411 12:22:43.041420 Set Vref, RX VrefLevel [Byte0]: 51
3412 12:22:43.044807 [Byte1]: 51
3413 12:22:43.049559
3414 12:22:43.049648 Set Vref, RX VrefLevel [Byte0]: 52
3415 12:22:43.052569 [Byte1]: 52
3416 12:22:43.057699
3417 12:22:43.057796 Set Vref, RX VrefLevel [Byte0]: 53
3418 12:22:43.060754 [Byte1]: 53
3419 12:22:43.065554
3420 12:22:43.065643 Set Vref, RX VrefLevel [Byte0]: 54
3421 12:22:43.068723 [Byte1]: 54
3422 12:22:43.073617
3423 12:22:43.073706 Set Vref, RX VrefLevel [Byte0]: 55
3424 12:22:43.076353 [Byte1]: 55
3425 12:22:43.081004
3426 12:22:43.081095 Set Vref, RX VrefLevel [Byte0]: 56
3427 12:22:43.084492 [Byte1]: 56
3428 12:22:43.089397
3429 12:22:43.089486 Set Vref, RX VrefLevel [Byte0]: 57
3430 12:22:43.092463 [Byte1]: 57
3431 12:22:43.096989
3432 12:22:43.097149 Set Vref, RX VrefLevel [Byte0]: 58
3433 12:22:43.100124 [Byte1]: 58
3434 12:22:43.105316
3435 12:22:43.105462 Set Vref, RX VrefLevel [Byte0]: 59
3436 12:22:43.108148 [Byte1]: 59
3437 12:22:43.112594
3438 12:22:43.112737 Set Vref, RX VrefLevel [Byte0]: 60
3439 12:22:43.116099 [Byte1]: 60
3440 12:22:43.120705
3441 12:22:43.120843 Set Vref, RX VrefLevel [Byte0]: 61
3442 12:22:43.124379 [Byte1]: 61
3443 12:22:43.128977
3444 12:22:43.129121 Set Vref, RX VrefLevel [Byte0]: 62
3445 12:22:43.132190 [Byte1]: 62
3446 12:22:43.136313
3447 12:22:43.136452 Set Vref, RX VrefLevel [Byte0]: 63
3448 12:22:43.140180 [Byte1]: 63
3449 12:22:43.144567
3450 12:22:43.144709 Set Vref, RX VrefLevel [Byte0]: 64
3451 12:22:43.147896 [Byte1]: 64
3452 12:22:43.152261
3453 12:22:43.152398 Set Vref, RX VrefLevel [Byte0]: 65
3454 12:22:43.155754 [Byte1]: 65
3455 12:22:43.160652
3456 12:22:43.160800 Set Vref, RX VrefLevel [Byte0]: 66
3457 12:22:43.163818 [Byte1]: 66
3458 12:22:43.167992
3459 12:22:43.168130 Set Vref, RX VrefLevel [Byte0]: 67
3460 12:22:43.171740 [Byte1]: 67
3461 12:22:43.176028
3462 12:22:43.176148 Set Vref, RX VrefLevel [Byte0]: 68
3463 12:22:43.179262 [Byte1]: 68
3464 12:22:43.184232
3465 12:22:43.184324 Set Vref, RX VrefLevel [Byte0]: 69
3466 12:22:43.187569 [Byte1]: 69
3467 12:22:43.192076
3468 12:22:43.192163 Set Vref, RX VrefLevel [Byte0]: 70
3469 12:22:43.195492 [Byte1]: 70
3470 12:22:43.200180
3471 12:22:43.200282 Final RX Vref Byte 0 = 57 to rank0
3472 12:22:43.203306 Final RX Vref Byte 1 = 53 to rank0
3473 12:22:43.206718 Final RX Vref Byte 0 = 57 to rank1
3474 12:22:43.210029 Final RX Vref Byte 1 = 53 to rank1==
3475 12:22:43.213354 Dram Type= 6, Freq= 0, CH_1, rank 0
3476 12:22:43.217070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 12:22:43.220257 ==
3478 12:22:43.220374 DQS Delay:
3479 12:22:43.220440 DQS0 = 0, DQS1 = 0
3480 12:22:43.223619 DQM Delay:
3481 12:22:43.223749 DQM0 = 116, DQM1 = 110
3482 12:22:43.226566 DQ Delay:
3483 12:22:43.230412 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3484 12:22:43.233339 DQ4 =116, DQ5 =126, DQ6 =126, DQ7 =114
3485 12:22:43.237137 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3486 12:22:43.240243 DQ12 =118, DQ13 =114, DQ14 =118, DQ15 =114
3487 12:22:43.240330
3488 12:22:43.240394
3489 12:22:43.247167 [DQSOSCAuto] RK0, (LSB)MR18= 0xffe4, (MSB)MR19= 0x303, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
3490 12:22:43.250343 CH1 RK0: MR19=303, MR18=FFE4
3491 12:22:43.257516 CH1_RK0: MR19=0x303, MR18=0xFFE4, DQSOSC=410, MR23=63, INC=39, DEC=26
3492 12:22:43.257623
3493 12:22:43.261196 ----->DramcWriteLeveling(PI) begin...
3494 12:22:43.261282 ==
3495 12:22:43.264232 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 12:22:43.267494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 12:22:43.267579 ==
3498 12:22:43.270470 Write leveling (Byte 0): 27 => 27
3499 12:22:43.274249 Write leveling (Byte 1): 29 => 29
3500 12:22:43.277537 DramcWriteLeveling(PI) end<-----
3501 12:22:43.277626
3502 12:22:43.277691 ==
3503 12:22:43.281064 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 12:22:43.283828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 12:22:43.283913 ==
3506 12:22:43.287428 [Gating] SW mode calibration
3507 12:22:43.294171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3508 12:22:43.301176 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3509 12:22:43.303959 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3510 12:22:43.307536 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 12:22:43.314617 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 12:22:43.317569 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 12:22:43.321119 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 12:22:43.327558 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 12:22:43.331313 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
3516 12:22:43.334192 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
3517 12:22:43.341210 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 12:22:43.344454 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 12:22:43.347739 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 12:22:43.354580 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 12:22:43.357728 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 12:22:43.361439 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3523 12:22:43.367995 1 0 24 | B1->B0 | 2424 3c3c | 0 0 | (0 0) (0 0)
3524 12:22:43.371880 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3525 12:22:43.374535 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 12:22:43.377912 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 12:22:43.385243 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 12:22:43.388187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 12:22:43.391394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 12:22:43.398386 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 12:22:43.401217 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3532 12:22:43.404779 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3533 12:22:43.411750 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:22:43.414622 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:22:43.417999 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:22:43.424530 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:22:43.427944 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 12:22:43.431247 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 12:22:43.437963 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 12:22:43.441421 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 12:22:43.444990 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 12:22:43.451442 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 12:22:43.454502 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:22:43.458230 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 12:22:43.462220 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:22:43.467926 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3547 12:22:43.471219 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3548 12:22:43.474783 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3549 12:22:43.478395 Total UI for P1: 0, mck2ui 16
3550 12:22:43.481186 best dqsien dly found for B0: ( 1, 3, 22)
3551 12:22:43.488207 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 12:22:43.488334 Total UI for P1: 0, mck2ui 16
3553 12:22:43.494559 best dqsien dly found for B1: ( 1, 3, 26)
3554 12:22:43.498358 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3555 12:22:43.501535 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3556 12:22:43.501627
3557 12:22:43.504898 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3558 12:22:43.508168 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3559 12:22:43.511444 [Gating] SW calibration Done
3560 12:22:43.511532 ==
3561 12:22:43.514655 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 12:22:43.517934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 12:22:43.518022 ==
3564 12:22:43.521257 RX Vref Scan: 0
3565 12:22:43.521341
3566 12:22:43.521405 RX Vref 0 -> 0, step: 1
3567 12:22:43.521465
3568 12:22:43.524700 RX Delay -40 -> 252, step: 8
3569 12:22:43.528110 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3570 12:22:43.535192 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3571 12:22:43.537985 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3572 12:22:43.541579 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3573 12:22:43.544729 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3574 12:22:43.548833 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3575 12:22:43.554921 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3576 12:22:43.558464 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3577 12:22:43.561602 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3578 12:22:43.565275 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3579 12:22:43.568398 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3580 12:22:43.571498 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3581 12:22:43.578149 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3582 12:22:43.581757 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3583 12:22:43.585346 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3584 12:22:43.588346 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3585 12:22:43.588435 ==
3586 12:22:43.591918 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 12:22:43.598419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 12:22:43.598505 ==
3589 12:22:43.598570 DQS Delay:
3590 12:22:43.598631 DQS0 = 0, DQS1 = 0
3591 12:22:43.601481 DQM Delay:
3592 12:22:43.601565 DQM0 = 113, DQM1 = 110
3593 12:22:43.605271 DQ Delay:
3594 12:22:43.608646 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3595 12:22:43.611885 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3596 12:22:43.615010 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3597 12:22:43.618313 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3598 12:22:43.618394
3599 12:22:43.618457
3600 12:22:43.618517 ==
3601 12:22:43.621747 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 12:22:43.625452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 12:22:43.625534 ==
3604 12:22:43.625598
3605 12:22:43.625658
3606 12:22:43.628707 TX Vref Scan disable
3607 12:22:43.632166 == TX Byte 0 ==
3608 12:22:43.635606 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3609 12:22:43.638698 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3610 12:22:43.642214 == TX Byte 1 ==
3611 12:22:43.645545 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3612 12:22:43.648545 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3613 12:22:43.648666 ==
3614 12:22:43.652066 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 12:22:43.658532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 12:22:43.658682 ==
3617 12:22:43.668909 TX Vref=22, minBit 3, minWin=25, winSum=416
3618 12:22:43.672337 TX Vref=24, minBit 0, minWin=26, winSum=422
3619 12:22:43.675560 TX Vref=26, minBit 1, minWin=26, winSum=429
3620 12:22:43.678781 TX Vref=28, minBit 2, minWin=26, winSum=430
3621 12:22:43.682599 TX Vref=30, minBit 2, minWin=26, winSum=432
3622 12:22:43.685481 TX Vref=32, minBit 13, minWin=25, winSum=430
3623 12:22:43.692679 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 30
3624 12:22:43.692766
3625 12:22:43.695849 Final TX Range 1 Vref 30
3626 12:22:43.695931
3627 12:22:43.695995 ==
3628 12:22:43.698793 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 12:22:43.702347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 12:22:43.702429 ==
3631 12:22:43.702493
3632 12:22:43.705603
3633 12:22:43.705683 TX Vref Scan disable
3634 12:22:43.708759 == TX Byte 0 ==
3635 12:22:43.712065 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3636 12:22:43.715540 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3637 12:22:43.718646 == TX Byte 1 ==
3638 12:22:43.722058 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3639 12:22:43.725346 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3640 12:22:43.725427
3641 12:22:43.728733 [DATLAT]
3642 12:22:43.728813 Freq=1200, CH1 RK1
3643 12:22:43.728878
3644 12:22:43.732142 DATLAT Default: 0xd
3645 12:22:43.732224 0, 0xFFFF, sum = 0
3646 12:22:43.735399 1, 0xFFFF, sum = 0
3647 12:22:43.735482 2, 0xFFFF, sum = 0
3648 12:22:43.738925 3, 0xFFFF, sum = 0
3649 12:22:43.739011 4, 0xFFFF, sum = 0
3650 12:22:43.741833 5, 0xFFFF, sum = 0
3651 12:22:43.745531 6, 0xFFFF, sum = 0
3652 12:22:43.745614 7, 0xFFFF, sum = 0
3653 12:22:43.748620 8, 0xFFFF, sum = 0
3654 12:22:43.748704 9, 0xFFFF, sum = 0
3655 12:22:43.752111 10, 0xFFFF, sum = 0
3656 12:22:43.752195 11, 0xFFFF, sum = 0
3657 12:22:43.755621 12, 0x0, sum = 1
3658 12:22:43.755705 13, 0x0, sum = 2
3659 12:22:43.758606 14, 0x0, sum = 3
3660 12:22:43.758688 15, 0x0, sum = 4
3661 12:22:43.758764 best_step = 13
3662 12:22:43.758826
3663 12:22:43.762138 ==
3664 12:22:43.765461 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 12:22:43.768609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 12:22:43.768691 ==
3667 12:22:43.768755 RX Vref Scan: 0
3668 12:22:43.768815
3669 12:22:43.771924 RX Vref 0 -> 0, step: 1
3670 12:22:43.772005
3671 12:22:43.775541 RX Delay -21 -> 252, step: 4
3672 12:22:43.778909 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3673 12:22:43.785354 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3674 12:22:43.788963 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3675 12:22:43.792182 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3676 12:22:43.795857 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3677 12:22:43.798874 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3678 12:22:43.802077 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3679 12:22:43.809036 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3680 12:22:43.812002 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3681 12:22:43.816272 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3682 12:22:43.819030 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3683 12:22:43.822672 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3684 12:22:43.828996 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3685 12:22:43.832090 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3686 12:22:43.835494 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3687 12:22:43.838866 iDelay=191, Bit 15, Center 118 (55 ~ 182) 128
3688 12:22:43.838947 ==
3689 12:22:43.842121 Dram Type= 6, Freq= 0, CH_1, rank 1
3690 12:22:43.848784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3691 12:22:43.848869 ==
3692 12:22:43.848934 DQS Delay:
3693 12:22:43.848994 DQS0 = 0, DQS1 = 0
3694 12:22:43.852253 DQM Delay:
3695 12:22:43.852334 DQM0 = 113, DQM1 = 109
3696 12:22:43.855377 DQ Delay:
3697 12:22:43.858807 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3698 12:22:43.862125 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3699 12:22:43.865743 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =104
3700 12:22:43.869025 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =118
3701 12:22:43.869107
3702 12:22:43.869171
3703 12:22:43.875955 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3704 12:22:43.879308 CH1 RK1: MR19=304, MR18=FB02
3705 12:22:43.885774 CH1_RK1: MR19=0x304, MR18=0xFB02, DQSOSC=409, MR23=63, INC=39, DEC=26
3706 12:22:43.889352 [RxdqsGatingPostProcess] freq 1200
3707 12:22:43.895671 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3708 12:22:43.898955 best DQS0 dly(2T, 0.5T) = (0, 11)
3709 12:22:43.899040 best DQS1 dly(2T, 0.5T) = (0, 11)
3710 12:22:43.902452 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3711 12:22:43.905890 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3712 12:22:43.909196 best DQS0 dly(2T, 0.5T) = (0, 11)
3713 12:22:43.912481 best DQS1 dly(2T, 0.5T) = (0, 11)
3714 12:22:43.916387 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3715 12:22:43.919048 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3716 12:22:43.922435 Pre-setting of DQS Precalculation
3717 12:22:43.925824 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3718 12:22:43.936045 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3719 12:22:43.943014 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3720 12:22:43.943133
3721 12:22:43.943199
3722 12:22:43.946083 [Calibration Summary] 2400 Mbps
3723 12:22:43.946173 CH 0, Rank 0
3724 12:22:43.949420 SW Impedance : PASS
3725 12:22:43.949502 DUTY Scan : NO K
3726 12:22:43.952564 ZQ Calibration : PASS
3727 12:22:43.956554 Jitter Meter : NO K
3728 12:22:43.956636 CBT Training : PASS
3729 12:22:43.959517 Write leveling : PASS
3730 12:22:43.963237 RX DQS gating : PASS
3731 12:22:43.963318 RX DQ/DQS(RDDQC) : PASS
3732 12:22:43.966501 TX DQ/DQS : PASS
3733 12:22:43.969623 RX DATLAT : PASS
3734 12:22:43.969703 RX DQ/DQS(Engine): PASS
3735 12:22:43.972725 TX OE : NO K
3736 12:22:43.972806 All Pass.
3737 12:22:43.972873
3738 12:22:43.976200 CH 0, Rank 1
3739 12:22:43.976280 SW Impedance : PASS
3740 12:22:43.979484 DUTY Scan : NO K
3741 12:22:43.979564 ZQ Calibration : PASS
3742 12:22:43.982889 Jitter Meter : NO K
3743 12:22:43.986326 CBT Training : PASS
3744 12:22:43.986441 Write leveling : PASS
3745 12:22:43.989485 RX DQS gating : PASS
3746 12:22:43.993018 RX DQ/DQS(RDDQC) : PASS
3747 12:22:43.993103 TX DQ/DQS : PASS
3748 12:22:43.996133 RX DATLAT : PASS
3749 12:22:43.999626 RX DQ/DQS(Engine): PASS
3750 12:22:43.999705 TX OE : NO K
3751 12:22:44.002940 All Pass.
3752 12:22:44.003021
3753 12:22:44.003084 CH 1, Rank 0
3754 12:22:44.006695 SW Impedance : PASS
3755 12:22:44.006821 DUTY Scan : NO K
3756 12:22:44.009393 ZQ Calibration : PASS
3757 12:22:44.012716 Jitter Meter : NO K
3758 12:22:44.012795 CBT Training : PASS
3759 12:22:44.016116 Write leveling : PASS
3760 12:22:44.016197 RX DQS gating : PASS
3761 12:22:44.019743 RX DQ/DQS(RDDQC) : PASS
3762 12:22:44.022946 TX DQ/DQS : PASS
3763 12:22:44.023028 RX DATLAT : PASS
3764 12:22:44.026548 RX DQ/DQS(Engine): PASS
3765 12:22:44.029487 TX OE : NO K
3766 12:22:44.029568 All Pass.
3767 12:22:44.029641
3768 12:22:44.029702 CH 1, Rank 1
3769 12:22:44.032870 SW Impedance : PASS
3770 12:22:44.036243 DUTY Scan : NO K
3771 12:22:44.036323 ZQ Calibration : PASS
3772 12:22:44.039922 Jitter Meter : NO K
3773 12:22:44.042999 CBT Training : PASS
3774 12:22:44.043079 Write leveling : PASS
3775 12:22:44.046505 RX DQS gating : PASS
3776 12:22:44.049870 RX DQ/DQS(RDDQC) : PASS
3777 12:22:44.049999 TX DQ/DQS : PASS
3778 12:22:44.053198 RX DATLAT : PASS
3779 12:22:44.053397 RX DQ/DQS(Engine): PASS
3780 12:22:44.056327 TX OE : NO K
3781 12:22:44.056474 All Pass.
3782 12:22:44.056540
3783 12:22:44.059964 DramC Write-DBI off
3784 12:22:44.063098 PER_BANK_REFRESH: Hybrid Mode
3785 12:22:44.063203 TX_TRACKING: ON
3786 12:22:44.073011 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3787 12:22:44.076645 [FAST_K] Save calibration result to emmc
3788 12:22:44.079756 dramc_set_vcore_voltage set vcore to 650000
3789 12:22:44.082978 Read voltage for 600, 5
3790 12:22:44.083067 Vio18 = 0
3791 12:22:44.086174 Vcore = 650000
3792 12:22:44.086295 Vdram = 0
3793 12:22:44.086364 Vddq = 0
3794 12:22:44.086424 Vmddr = 0
3795 12:22:44.093476 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3796 12:22:44.096899 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3797 12:22:44.100209 MEM_TYPE=3, freq_sel=19
3798 12:22:44.103058 sv_algorithm_assistance_LP4_1600
3799 12:22:44.106626 ============ PULL DRAM RESETB DOWN ============
3800 12:22:44.110037 ========== PULL DRAM RESETB DOWN end =========
3801 12:22:44.116101 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3802 12:22:44.119785 ===================================
3803 12:22:44.123413 LPDDR4 DRAM CONFIGURATION
3804 12:22:44.126261 ===================================
3805 12:22:44.126342 EX_ROW_EN[0] = 0x0
3806 12:22:44.130089 EX_ROW_EN[1] = 0x0
3807 12:22:44.130171 LP4Y_EN = 0x0
3808 12:22:44.132988 WORK_FSP = 0x0
3809 12:22:44.133070 WL = 0x2
3810 12:22:44.136426 RL = 0x2
3811 12:22:44.136507 BL = 0x2
3812 12:22:44.140003 RPST = 0x0
3813 12:22:44.140084 RD_PRE = 0x0
3814 12:22:44.143070 WR_PRE = 0x1
3815 12:22:44.143152 WR_PST = 0x0
3816 12:22:44.146732 DBI_WR = 0x0
3817 12:22:44.146828 DBI_RD = 0x0
3818 12:22:44.149872 OTF = 0x1
3819 12:22:44.153315 ===================================
3820 12:22:44.156669 ===================================
3821 12:22:44.156755 ANA top config
3822 12:22:44.159981 ===================================
3823 12:22:44.163170 DLL_ASYNC_EN = 0
3824 12:22:44.166587 ALL_SLAVE_EN = 1
3825 12:22:44.169851 NEW_RANK_MODE = 1
3826 12:22:44.169934 DLL_IDLE_MODE = 1
3827 12:22:44.173777 LP45_APHY_COMB_EN = 1
3828 12:22:44.176337 TX_ODT_DIS = 1
3829 12:22:44.179626 NEW_8X_MODE = 1
3830 12:22:44.183381 ===================================
3831 12:22:44.186616 ===================================
3832 12:22:44.189939 data_rate = 1200
3833 12:22:44.190013 CKR = 1
3834 12:22:44.193013 DQ_P2S_RATIO = 8
3835 12:22:44.196559 ===================================
3836 12:22:44.199777 CA_P2S_RATIO = 8
3837 12:22:44.203340 DQ_CA_OPEN = 0
3838 12:22:44.206702 DQ_SEMI_OPEN = 0
3839 12:22:44.209702 CA_SEMI_OPEN = 0
3840 12:22:44.209783 CA_FULL_RATE = 0
3841 12:22:44.213042 DQ_CKDIV4_EN = 1
3842 12:22:44.216557 CA_CKDIV4_EN = 1
3843 12:22:44.220311 CA_PREDIV_EN = 0
3844 12:22:44.223367 PH8_DLY = 0
3845 12:22:44.223448 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3846 12:22:44.226632 DQ_AAMCK_DIV = 4
3847 12:22:44.230200 CA_AAMCK_DIV = 4
3848 12:22:44.233092 CA_ADMCK_DIV = 4
3849 12:22:44.236512 DQ_TRACK_CA_EN = 0
3850 12:22:44.240306 CA_PICK = 600
3851 12:22:44.243112 CA_MCKIO = 600
3852 12:22:44.243192 MCKIO_SEMI = 0
3853 12:22:44.246840 PLL_FREQ = 2288
3854 12:22:44.250206 DQ_UI_PI_RATIO = 32
3855 12:22:44.253793 CA_UI_PI_RATIO = 0
3856 12:22:44.257102 ===================================
3857 12:22:44.259945 ===================================
3858 12:22:44.263378 memory_type:LPDDR4
3859 12:22:44.263461 GP_NUM : 10
3860 12:22:44.266907 SRAM_EN : 1
3861 12:22:44.266988 MD32_EN : 0
3862 12:22:44.270314 ===================================
3863 12:22:44.273487 [ANA_INIT] >>>>>>>>>>>>>>
3864 12:22:44.277055 <<<<<< [CONFIGURE PHASE]: ANA_TX
3865 12:22:44.280107 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3866 12:22:44.283628 ===================================
3867 12:22:44.286904 data_rate = 1200,PCW = 0X5800
3868 12:22:44.290363 ===================================
3869 12:22:44.294009 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3870 12:22:44.297023 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3871 12:22:44.303836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 12:22:44.307470 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3873 12:22:44.314286 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3874 12:22:44.316866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3875 12:22:44.316946 [ANA_INIT] flow start
3876 12:22:44.320057 [ANA_INIT] PLL >>>>>>>>
3877 12:22:44.324116 [ANA_INIT] PLL <<<<<<<<
3878 12:22:44.324201 [ANA_INIT] MIDPI >>>>>>>>
3879 12:22:44.326929 [ANA_INIT] MIDPI <<<<<<<<
3880 12:22:44.330318 [ANA_INIT] DLL >>>>>>>>
3881 12:22:44.330402 [ANA_INIT] flow end
3882 12:22:44.333404 ============ LP4 DIFF to SE enter ============
3883 12:22:44.340189 ============ LP4 DIFF to SE exit ============
3884 12:22:44.340279 [ANA_INIT] <<<<<<<<<<<<<
3885 12:22:44.343488 [Flow] Enable top DCM control >>>>>
3886 12:22:44.346556 [Flow] Enable top DCM control <<<<<
3887 12:22:44.350171 Enable DLL master slave shuffle
3888 12:22:44.357061 ==============================================================
3889 12:22:44.357147 Gating Mode config
3890 12:22:44.363802 ==============================================================
3891 12:22:44.366631 Config description:
3892 12:22:44.377083 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3893 12:22:44.383952 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3894 12:22:44.386632 SELPH_MODE 0: By rank 1: By Phase
3895 12:22:44.393684 ==============================================================
3896 12:22:44.397055 GAT_TRACK_EN = 1
3897 12:22:44.397142 RX_GATING_MODE = 2
3898 12:22:44.400117 RX_GATING_TRACK_MODE = 2
3899 12:22:44.403476 SELPH_MODE = 1
3900 12:22:44.406727 PICG_EARLY_EN = 1
3901 12:22:44.410282 VALID_LAT_VALUE = 1
3902 12:22:44.416815 ==============================================================
3903 12:22:44.420342 Enter into Gating configuration >>>>
3904 12:22:44.423641 Exit from Gating configuration <<<<
3905 12:22:44.426881 Enter into DVFS_PRE_config >>>>>
3906 12:22:44.437160 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3907 12:22:44.440732 Exit from DVFS_PRE_config <<<<<
3908 12:22:44.443860 Enter into PICG configuration >>>>
3909 12:22:44.446925 Exit from PICG configuration <<<<
3910 12:22:44.450571 [RX_INPUT] configuration >>>>>
3911 12:22:44.450704 [RX_INPUT] configuration <<<<<
3912 12:22:44.457220 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3913 12:22:44.463822 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3914 12:22:44.467018 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 12:22:44.473965 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 12:22:44.480390 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 12:22:44.487382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 12:22:44.490637 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3919 12:22:44.494024 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3920 12:22:44.500240 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3921 12:22:44.503724 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3922 12:22:44.506873 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3923 12:22:44.510429 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3924 12:22:44.517189 ===================================
3925 12:22:44.517272 LPDDR4 DRAM CONFIGURATION
3926 12:22:44.520057 ===================================
3927 12:22:44.523618 EX_ROW_EN[0] = 0x0
3928 12:22:44.523700 EX_ROW_EN[1] = 0x0
3929 12:22:44.527176 LP4Y_EN = 0x0
3930 12:22:44.527257 WORK_FSP = 0x0
3931 12:22:44.530208 WL = 0x2
3932 12:22:44.530289 RL = 0x2
3933 12:22:44.533555 BL = 0x2
3934 12:22:44.533636 RPST = 0x0
3935 12:22:44.536800 RD_PRE = 0x0
3936 12:22:44.536881 WR_PRE = 0x1
3937 12:22:44.540417 WR_PST = 0x0
3938 12:22:44.543806 DBI_WR = 0x0
3939 12:22:44.543888 DBI_RD = 0x0
3940 12:22:44.547325 OTF = 0x1
3941 12:22:44.550223 ===================================
3942 12:22:44.553510 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3943 12:22:44.557190 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3944 12:22:44.560061 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3945 12:22:44.563908 ===================================
3946 12:22:44.567081 LPDDR4 DRAM CONFIGURATION
3947 12:22:44.570235 ===================================
3948 12:22:44.573743 EX_ROW_EN[0] = 0x10
3949 12:22:44.573825 EX_ROW_EN[1] = 0x0
3950 12:22:44.577207 LP4Y_EN = 0x0
3951 12:22:44.577288 WORK_FSP = 0x0
3952 12:22:44.580430 WL = 0x2
3953 12:22:44.580511 RL = 0x2
3954 12:22:44.583850 BL = 0x2
3955 12:22:44.583931 RPST = 0x0
3956 12:22:44.587023 RD_PRE = 0x0
3957 12:22:44.587125 WR_PRE = 0x1
3958 12:22:44.590200 WR_PST = 0x0
3959 12:22:44.590282 DBI_WR = 0x0
3960 12:22:44.593572 DBI_RD = 0x0
3961 12:22:44.593653 OTF = 0x1
3962 12:22:44.596974 ===================================
3963 12:22:44.603430 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3964 12:22:44.608663 nWR fixed to 30
3965 12:22:44.611760 [ModeRegInit_LP4] CH0 RK0
3966 12:22:44.611842 [ModeRegInit_LP4] CH0 RK1
3967 12:22:44.615093 [ModeRegInit_LP4] CH1 RK0
3968 12:22:44.618712 [ModeRegInit_LP4] CH1 RK1
3969 12:22:44.618805 match AC timing 17
3970 12:22:44.625210 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3971 12:22:44.628401 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3972 12:22:44.631850 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3973 12:22:44.638230 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3974 12:22:44.641541 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3975 12:22:44.641627 ==
3976 12:22:44.645056 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 12:22:44.648406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 12:22:44.648489 ==
3979 12:22:44.655145 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 12:22:44.661739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3981 12:22:44.665127 [CA 0] Center 36 (6~67) winsize 62
3982 12:22:44.668331 [CA 1] Center 36 (6~66) winsize 61
3983 12:22:44.672099 [CA 2] Center 34 (4~65) winsize 62
3984 12:22:44.675056 [CA 3] Center 34 (4~65) winsize 62
3985 12:22:44.678695 [CA 4] Center 33 (3~64) winsize 62
3986 12:22:44.681717 [CA 5] Center 33 (3~64) winsize 62
3987 12:22:44.681798
3988 12:22:44.685402 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3989 12:22:44.685484
3990 12:22:44.688764 [CATrainingPosCal] consider 1 rank data
3991 12:22:44.692489 u2DelayCellTimex100 = 270/100 ps
3992 12:22:44.695263 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3993 12:22:44.699079 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3994 12:22:44.702072 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 12:22:44.705304 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 12:22:44.709273 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 12:22:44.712081 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 12:22:44.712162
3999 12:22:44.715520 CA PerBit enable=1, Macro0, CA PI delay=33
4000 12:22:44.715601
4001 12:22:44.718642 [CBTSetCACLKResult] CA Dly = 33
4002 12:22:44.722072 CS Dly: 4 (0~35)
4003 12:22:44.722162 ==
4004 12:22:44.725472 Dram Type= 6, Freq= 0, CH_0, rank 1
4005 12:22:44.728877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 12:22:44.728961 ==
4007 12:22:44.735227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4008 12:22:44.741830 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4009 12:22:44.745546 [CA 0] Center 36 (6~66) winsize 61
4010 12:22:44.748741 [CA 1] Center 35 (5~66) winsize 62
4011 12:22:44.752346 [CA 2] Center 35 (5~65) winsize 61
4012 12:22:44.755307 [CA 3] Center 34 (4~65) winsize 62
4013 12:22:44.758942 [CA 4] Center 33 (3~64) winsize 62
4014 12:22:44.761978 [CA 5] Center 33 (3~64) winsize 62
4015 12:22:44.762061
4016 12:22:44.765575 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4017 12:22:44.765682
4018 12:22:44.768728 [CATrainingPosCal] consider 2 rank data
4019 12:22:44.772162 u2DelayCellTimex100 = 270/100 ps
4020 12:22:44.775295 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4021 12:22:44.778944 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 12:22:44.782202 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4023 12:22:44.785370 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4024 12:22:44.788927 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4025 12:22:44.792171 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 12:22:44.792254
4027 12:22:44.799281 CA PerBit enable=1, Macro0, CA PI delay=33
4028 12:22:44.799364
4029 12:22:44.799447 [CBTSetCACLKResult] CA Dly = 33
4030 12:22:44.802028 CS Dly: 5 (0~37)
4031 12:22:44.802112
4032 12:22:44.805833 ----->DramcWriteLeveling(PI) begin...
4033 12:22:44.805938 ==
4034 12:22:44.809317 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 12:22:44.812349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 12:22:44.812433 ==
4037 12:22:44.815852 Write leveling (Byte 0): 30 => 30
4038 12:22:44.818628 Write leveling (Byte 1): 31 => 31
4039 12:22:44.822241 DramcWriteLeveling(PI) end<-----
4040 12:22:44.822323
4041 12:22:44.822406 ==
4042 12:22:44.825395 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 12:22:44.829267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 12:22:44.829350 ==
4045 12:22:44.832078 [Gating] SW mode calibration
4046 12:22:44.838938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4047 12:22:44.845556 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4048 12:22:44.849406 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 12:22:44.856096 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 12:22:44.859126 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 12:22:44.862295 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4052 12:22:44.865605 0 9 16 | B1->B0 | 3030 2828 | 0 0 | (0 1) (1 0)
4053 12:22:44.872627 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4054 12:22:44.875997 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 12:22:44.879004 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 12:22:44.885891 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 12:22:44.889295 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 12:22:44.892521 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 12:22:44.899306 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4060 12:22:44.902410 0 10 16 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0)
4061 12:22:44.905862 0 10 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4062 12:22:44.912229 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 12:22:44.915792 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 12:22:44.918983 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 12:22:44.925704 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 12:22:44.929444 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 12:22:44.932671 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 12:22:44.939266 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4069 12:22:44.942246 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:22:44.945821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:22:44.949114 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:22:44.955803 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:22:44.959146 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:22:44.962598 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:22:44.968957 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:22:44.972693 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:22:44.975872 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:22:44.982505 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:22:44.985754 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:22:44.989128 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:22:44.995763 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:22:44.998991 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:22:45.002643 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4084 12:22:45.009020 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4085 12:22:45.012386 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 12:22:45.015648 Total UI for P1: 0, mck2ui 16
4087 12:22:45.019009 best dqsien dly found for B0: ( 0, 13, 14)
4088 12:22:45.023021 Total UI for P1: 0, mck2ui 16
4089 12:22:45.025878 best dqsien dly found for B1: ( 0, 13, 14)
4090 12:22:45.028919 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4091 12:22:45.032328 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4092 12:22:45.032409
4093 12:22:45.035678 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4094 12:22:45.039301 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4095 12:22:45.042137 [Gating] SW calibration Done
4096 12:22:45.042250 ==
4097 12:22:45.045723 Dram Type= 6, Freq= 0, CH_0, rank 0
4098 12:22:45.049296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4099 12:22:45.049379 ==
4100 12:22:45.052339 RX Vref Scan: 0
4101 12:22:45.052422
4102 12:22:45.055740 RX Vref 0 -> 0, step: 1
4103 12:22:45.055822
4104 12:22:45.055906 RX Delay -230 -> 252, step: 16
4105 12:22:45.062574 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4106 12:22:45.065837 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4107 12:22:45.069752 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4108 12:22:45.072822 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4109 12:22:45.079377 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4110 12:22:45.082822 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4111 12:22:45.085871 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4112 12:22:45.089358 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4113 12:22:45.093096 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4114 12:22:45.099591 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4115 12:22:45.102858 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4116 12:22:45.105978 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4117 12:22:45.109794 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4118 12:22:45.116103 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4119 12:22:45.119605 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4120 12:22:45.122856 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4121 12:22:45.122937 ==
4122 12:22:45.126331 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 12:22:45.129374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 12:22:45.129456 ==
4125 12:22:45.133346 DQS Delay:
4126 12:22:45.133426 DQS0 = 0, DQS1 = 0
4127 12:22:45.136441 DQM Delay:
4128 12:22:45.136546 DQM0 = 40, DQM1 = 31
4129 12:22:45.136633 DQ Delay:
4130 12:22:45.139400 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4131 12:22:45.142434 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4132 12:22:45.146071 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4133 12:22:45.149453 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4134 12:22:45.149534
4135 12:22:45.149598
4136 12:22:45.152762 ==
4137 12:22:45.152847 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 12:22:45.159521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 12:22:45.159603 ==
4140 12:22:45.159668
4141 12:22:45.159727
4142 12:22:45.162424 TX Vref Scan disable
4143 12:22:45.162506 == TX Byte 0 ==
4144 12:22:45.166129 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4145 12:22:45.172666 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4146 12:22:45.172748 == TX Byte 1 ==
4147 12:22:45.176111 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4148 12:22:45.182641 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4149 12:22:45.182732 ==
4150 12:22:45.186504 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 12:22:45.189014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 12:22:45.189096 ==
4153 12:22:45.189161
4154 12:22:45.189220
4155 12:22:45.192892 TX Vref Scan disable
4156 12:22:45.196004 == TX Byte 0 ==
4157 12:22:45.199194 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4158 12:22:45.202594 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4159 12:22:45.205961 == TX Byte 1 ==
4160 12:22:45.209381 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4161 12:22:45.212815 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4162 12:22:45.212896
4163 12:22:45.215945 [DATLAT]
4164 12:22:45.216026 Freq=600, CH0 RK0
4165 12:22:45.216091
4166 12:22:45.219582 DATLAT Default: 0x9
4167 12:22:45.219663 0, 0xFFFF, sum = 0
4168 12:22:45.222853 1, 0xFFFF, sum = 0
4169 12:22:45.222937 2, 0xFFFF, sum = 0
4170 12:22:45.225787 3, 0xFFFF, sum = 0
4171 12:22:45.225869 4, 0xFFFF, sum = 0
4172 12:22:45.229206 5, 0xFFFF, sum = 0
4173 12:22:45.229289 6, 0xFFFF, sum = 0
4174 12:22:45.232598 7, 0xFFFF, sum = 0
4175 12:22:45.232681 8, 0x0, sum = 1
4176 12:22:45.236199 9, 0x0, sum = 2
4177 12:22:45.236282 10, 0x0, sum = 3
4178 12:22:45.239797 11, 0x0, sum = 4
4179 12:22:45.239880 best_step = 9
4180 12:22:45.239945
4181 12:22:45.240004 ==
4182 12:22:45.243004 Dram Type= 6, Freq= 0, CH_0, rank 0
4183 12:22:45.245963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 12:22:45.246044 ==
4185 12:22:45.250133 RX Vref Scan: 1
4186 12:22:45.250215
4187 12:22:45.250280 RX Vref 0 -> 0, step: 1
4188 12:22:45.253129
4189 12:22:45.253209 RX Delay -195 -> 252, step: 8
4190 12:22:45.253274
4191 12:22:45.256279 Set Vref, RX VrefLevel [Byte0]: 54
4192 12:22:45.259434 [Byte1]: 50
4193 12:22:45.263813
4194 12:22:45.263894 Final RX Vref Byte 0 = 54 to rank0
4195 12:22:45.267217 Final RX Vref Byte 1 = 50 to rank0
4196 12:22:45.271325 Final RX Vref Byte 0 = 54 to rank1
4197 12:22:45.274080 Final RX Vref Byte 1 = 50 to rank1==
4198 12:22:45.277101 Dram Type= 6, Freq= 0, CH_0, rank 0
4199 12:22:45.284067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 12:22:45.284150 ==
4201 12:22:45.284214 DQS Delay:
4202 12:22:45.284273 DQS0 = 0, DQS1 = 0
4203 12:22:45.287024 DQM Delay:
4204 12:22:45.287105 DQM0 = 42, DQM1 = 33
4205 12:22:45.290388 DQ Delay:
4206 12:22:45.294017 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4207 12:22:45.294098 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4208 12:22:45.297184 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4209 12:22:45.303700 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4210 12:22:45.303780
4211 12:22:45.303842
4212 12:22:45.310675 [DQSOSCAuto] RK0, (LSB)MR18= 0x4523, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4213 12:22:45.314431 CH0 RK0: MR19=808, MR18=4523
4214 12:22:45.320524 CH0_RK0: MR19=0x808, MR18=0x4523, DQSOSC=396, MR23=63, INC=167, DEC=111
4215 12:22:45.320620
4216 12:22:45.323650 ----->DramcWriteLeveling(PI) begin...
4217 12:22:45.323732 ==
4218 12:22:45.327171 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 12:22:45.330377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 12:22:45.330457 ==
4221 12:22:45.333823 Write leveling (Byte 0): 31 => 31
4222 12:22:45.337256 Write leveling (Byte 1): 29 => 29
4223 12:22:45.340612 DramcWriteLeveling(PI) end<-----
4224 12:22:45.340694
4225 12:22:45.340758 ==
4226 12:22:45.343934 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 12:22:45.347633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 12:22:45.347715 ==
4229 12:22:45.350689 [Gating] SW mode calibration
4230 12:22:45.357225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4231 12:22:45.364569 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4232 12:22:45.367343 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 12:22:45.370846 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 12:22:45.377697 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4235 12:22:45.380901 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4236 12:22:45.383851 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4237 12:22:45.390545 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 12:22:45.394175 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 12:22:45.397672 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 12:22:45.403836 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 12:22:45.407560 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 12:22:45.411035 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 12:22:45.417193 0 10 12 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)
4244 12:22:45.420534 0 10 16 | B1->B0 | 3333 4646 | 1 0 | (0 0) (0 0)
4245 12:22:45.423894 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 12:22:45.430597 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 12:22:45.433739 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 12:22:45.437233 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 12:22:45.443872 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 12:22:45.447162 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 12:22:45.450385 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4252 12:22:45.454184 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4253 12:22:45.460390 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:22:45.464060 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:22:45.467453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:22:45.473663 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:22:45.477084 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:22:45.480694 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:22:45.487070 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:22:45.490524 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:22:45.493815 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:22:45.500600 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:22:45.503836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:22:45.506920 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:22:45.513512 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:22:45.516827 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4267 12:22:45.520536 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4268 12:22:45.526931 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4269 12:22:45.527036 Total UI for P1: 0, mck2ui 16
4270 12:22:45.530436 best dqsien dly found for B0: ( 0, 13, 10)
4271 12:22:45.537394 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4272 12:22:45.540620 Total UI for P1: 0, mck2ui 16
4273 12:22:45.543781 best dqsien dly found for B1: ( 0, 13, 14)
4274 12:22:45.547062 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4275 12:22:45.550238 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4276 12:22:45.550338
4277 12:22:45.553729 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4278 12:22:45.557011 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4279 12:22:45.560498 [Gating] SW calibration Done
4280 12:22:45.560604 ==
4281 12:22:45.563768 Dram Type= 6, Freq= 0, CH_0, rank 1
4282 12:22:45.567038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 12:22:45.567152 ==
4284 12:22:45.570676 RX Vref Scan: 0
4285 12:22:45.570806
4286 12:22:45.573757 RX Vref 0 -> 0, step: 1
4287 12:22:45.573862
4288 12:22:45.573954 RX Delay -230 -> 252, step: 16
4289 12:22:45.580587 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4290 12:22:45.584080 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4291 12:22:45.587682 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4292 12:22:45.590696 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4293 12:22:45.593960 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4294 12:22:45.600708 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4295 12:22:45.604292 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4296 12:22:45.607409 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4297 12:22:45.610923 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4298 12:22:45.617787 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4299 12:22:45.621063 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4300 12:22:45.624410 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4301 12:22:45.627602 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4302 12:22:45.630690 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4303 12:22:45.637757 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4304 12:22:45.640792 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4305 12:22:45.640873 ==
4306 12:22:45.644307 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 12:22:45.647890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 12:22:45.647971 ==
4309 12:22:45.651240 DQS Delay:
4310 12:22:45.651320 DQS0 = 0, DQS1 = 0
4311 12:22:45.651383 DQM Delay:
4312 12:22:45.654243 DQM0 = 38, DQM1 = 32
4313 12:22:45.654323 DQ Delay:
4314 12:22:45.658004 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4315 12:22:45.660893 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4316 12:22:45.664140 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4317 12:22:45.667590 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4318 12:22:45.667670
4319 12:22:45.667733
4320 12:22:45.667792 ==
4321 12:22:45.670935 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 12:22:45.677658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 12:22:45.677738 ==
4324 12:22:45.677801
4325 12:22:45.677859
4326 12:22:45.677914 TX Vref Scan disable
4327 12:22:45.681232 == TX Byte 0 ==
4328 12:22:45.684902 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4329 12:22:45.688260 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4330 12:22:45.691268 == TX Byte 1 ==
4331 12:22:45.694690 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4332 12:22:45.701094 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4333 12:22:45.701175 ==
4334 12:22:45.704735 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 12:22:45.707873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 12:22:45.707953 ==
4337 12:22:45.708016
4338 12:22:45.708074
4339 12:22:45.711109 TX Vref Scan disable
4340 12:22:45.714430 == TX Byte 0 ==
4341 12:22:45.717996 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4342 12:22:45.721070 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4343 12:22:45.721150 == TX Byte 1 ==
4344 12:22:45.727895 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4345 12:22:45.731309 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4346 12:22:45.731394
4347 12:22:45.731459 [DATLAT]
4348 12:22:45.734490 Freq=600, CH0 RK1
4349 12:22:45.734571
4350 12:22:45.734635 DATLAT Default: 0x9
4351 12:22:45.737732 0, 0xFFFF, sum = 0
4352 12:22:45.737815 1, 0xFFFF, sum = 0
4353 12:22:45.740972 2, 0xFFFF, sum = 0
4354 12:22:45.741053 3, 0xFFFF, sum = 0
4355 12:22:45.745178 4, 0xFFFF, sum = 0
4356 12:22:45.747968 5, 0xFFFF, sum = 0
4357 12:22:45.748050 6, 0xFFFF, sum = 0
4358 12:22:45.751322 7, 0xFFFF, sum = 0
4359 12:22:45.751403 8, 0x0, sum = 1
4360 12:22:45.751467 9, 0x0, sum = 2
4361 12:22:45.754813 10, 0x0, sum = 3
4362 12:22:45.754953 11, 0x0, sum = 4
4363 12:22:45.758222 best_step = 9
4364 12:22:45.758328
4365 12:22:45.758419 ==
4366 12:22:45.761395 Dram Type= 6, Freq= 0, CH_0, rank 1
4367 12:22:45.764675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 12:22:45.764761 ==
4369 12:22:45.768244 RX Vref Scan: 0
4370 12:22:45.768324
4371 12:22:45.768387 RX Vref 0 -> 0, step: 1
4372 12:22:45.768445
4373 12:22:45.771340 RX Delay -195 -> 252, step: 8
4374 12:22:45.778478 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4375 12:22:45.781622 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4376 12:22:45.784859 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4377 12:22:45.788310 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4378 12:22:45.794914 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4379 12:22:45.798391 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4380 12:22:45.801952 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4381 12:22:45.805308 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4382 12:22:45.808559 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4383 12:22:45.815063 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4384 12:22:45.818332 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4385 12:22:45.821748 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4386 12:22:45.825149 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4387 12:22:45.831885 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4388 12:22:45.835107 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4389 12:22:45.838600 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4390 12:22:45.838704 ==
4391 12:22:45.841876 Dram Type= 6, Freq= 0, CH_0, rank 1
4392 12:22:45.845131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 12:22:45.845221 ==
4394 12:22:45.848290 DQS Delay:
4395 12:22:45.848369 DQS0 = 0, DQS1 = 0
4396 12:22:45.852296 DQM Delay:
4397 12:22:45.852378 DQM0 = 39, DQM1 = 33
4398 12:22:45.852442 DQ Delay:
4399 12:22:45.855250 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4400 12:22:45.858471 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4401 12:22:45.861717 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4402 12:22:45.865374 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4403 12:22:45.865455
4404 12:22:45.865518
4405 12:22:45.875074 [DQSOSCAuto] RK1, (LSB)MR18= 0x4627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4406 12:22:45.878586 CH0 RK1: MR19=808, MR18=4627
4407 12:22:45.882733 CH0_RK1: MR19=0x808, MR18=0x4627, DQSOSC=396, MR23=63, INC=167, DEC=111
4408 12:22:45.885557 [RxdqsGatingPostProcess] freq 600
4409 12:22:45.892023 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4410 12:22:45.895479 Pre-setting of DQS Precalculation
4411 12:22:45.898702 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4412 12:22:45.898822 ==
4413 12:22:45.902172 Dram Type= 6, Freq= 0, CH_1, rank 0
4414 12:22:45.908647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4415 12:22:45.908728 ==
4416 12:22:45.912098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4417 12:22:45.918707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4418 12:22:45.922142 [CA 0] Center 35 (5~66) winsize 62
4419 12:22:45.925382 [CA 1] Center 35 (5~65) winsize 61
4420 12:22:45.928763 [CA 2] Center 33 (3~64) winsize 62
4421 12:22:45.931985 [CA 3] Center 33 (3~64) winsize 62
4422 12:22:45.935863 [CA 4] Center 34 (4~65) winsize 62
4423 12:22:45.938653 [CA 5] Center 33 (3~64) winsize 62
4424 12:22:45.938765
4425 12:22:45.942452 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4426 12:22:45.942558
4427 12:22:45.945406 [CATrainingPosCal] consider 1 rank data
4428 12:22:45.949076 u2DelayCellTimex100 = 270/100 ps
4429 12:22:45.951896 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 12:22:45.955453 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4431 12:22:45.958991 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 12:22:45.965573 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 12:22:45.969020 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 12:22:45.972733 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4435 12:22:45.972814
4436 12:22:45.975339 CA PerBit enable=1, Macro0, CA PI delay=33
4437 12:22:45.975420
4438 12:22:45.978677 [CBTSetCACLKResult] CA Dly = 33
4439 12:22:45.978798 CS Dly: 3 (0~34)
4440 12:22:45.978862 ==
4441 12:22:45.982478 Dram Type= 6, Freq= 0, CH_1, rank 1
4442 12:22:45.989405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 12:22:45.989487 ==
4444 12:22:45.991910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 12:22:45.999091 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4446 12:22:46.002404 [CA 0] Center 35 (5~66) winsize 62
4447 12:22:46.005239 [CA 1] Center 35 (5~66) winsize 62
4448 12:22:46.008686 [CA 2] Center 34 (4~65) winsize 62
4449 12:22:46.012590 [CA 3] Center 34 (3~65) winsize 63
4450 12:22:46.015683 [CA 4] Center 34 (3~65) winsize 63
4451 12:22:46.019188 [CA 5] Center 33 (3~64) winsize 62
4452 12:22:46.019269
4453 12:22:46.022125 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4454 12:22:46.022206
4455 12:22:46.025462 [CATrainingPosCal] consider 2 rank data
4456 12:22:46.028820 u2DelayCellTimex100 = 270/100 ps
4457 12:22:46.032262 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 12:22:46.035608 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4459 12:22:46.038969 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4460 12:22:46.045855 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 12:22:46.049273 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 12:22:46.052548 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 12:22:46.052629
4464 12:22:46.055839 CA PerBit enable=1, Macro0, CA PI delay=33
4465 12:22:46.055919
4466 12:22:46.059331 [CBTSetCACLKResult] CA Dly = 33
4467 12:22:46.059412 CS Dly: 4 (0~36)
4468 12:22:46.059476
4469 12:22:46.062291 ----->DramcWriteLeveling(PI) begin...
4470 12:22:46.062374 ==
4471 12:22:46.065892 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 12:22:46.072531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 12:22:46.072613 ==
4474 12:22:46.075948 Write leveling (Byte 0): 31 => 31
4475 12:22:46.078874 Write leveling (Byte 1): 31 => 31
4476 12:22:46.078955 DramcWriteLeveling(PI) end<-----
4477 12:22:46.079020
4478 12:22:46.082191 ==
4479 12:22:46.085545 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 12:22:46.088906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 12:22:46.088989 ==
4482 12:22:46.092626 [Gating] SW mode calibration
4483 12:22:46.098954 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4484 12:22:46.102495 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4485 12:22:46.109094 0 9 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4486 12:22:46.112880 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 12:22:46.116088 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4488 12:22:46.122346 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (0 0) (1 1)
4489 12:22:46.125811 0 9 16 | B1->B0 | 2b2b 2929 | 1 0 | (1 0) (0 0)
4490 12:22:46.129214 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 12:22:46.135852 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 12:22:46.139177 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 12:22:46.142519 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 12:22:46.146427 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 12:22:46.152476 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 12:22:46.156129 0 10 12 | B1->B0 | 2c2c 2c2c | 0 0 | (1 1) (0 0)
4497 12:22:46.159574 0 10 16 | B1->B0 | 4040 3d3d | 0 1 | (0 0) (0 0)
4498 12:22:46.166210 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 12:22:46.169450 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 12:22:46.172333 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 12:22:46.179148 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 12:22:46.182473 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 12:22:46.186000 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 12:22:46.192714 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 12:22:46.196209 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4506 12:22:46.199310 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:22:46.206391 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:22:46.209182 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:22:46.212743 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:22:46.219604 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:22:46.222430 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:22:46.225826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 12:22:46.228979 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 12:22:46.235840 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:22:46.239459 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:22:46.242327 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:22:46.248911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 12:22:46.252359 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 12:22:46.255674 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 12:22:46.262319 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 12:22:46.266051 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 12:22:46.269316 Total UI for P1: 0, mck2ui 16
4523 12:22:46.272595 best dqsien dly found for B0: ( 0, 13, 14)
4524 12:22:46.276048 Total UI for P1: 0, mck2ui 16
4525 12:22:46.279166 best dqsien dly found for B1: ( 0, 13, 14)
4526 12:22:46.282433 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4527 12:22:46.285978 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4528 12:22:46.286082
4529 12:22:46.289426 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4530 12:22:46.292847 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4531 12:22:46.296454 [Gating] SW calibration Done
4532 12:22:46.296535 ==
4533 12:22:46.299297 Dram Type= 6, Freq= 0, CH_1, rank 0
4534 12:22:46.302839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4535 12:22:46.306338 ==
4536 12:22:46.306422 RX Vref Scan: 0
4537 12:22:46.306488
4538 12:22:46.310359 RX Vref 0 -> 0, step: 1
4539 12:22:46.310444
4540 12:22:46.312929 RX Delay -230 -> 252, step: 16
4541 12:22:46.316048 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4542 12:22:46.319541 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4543 12:22:46.322596 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4544 12:22:46.326270 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4545 12:22:46.332870 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4546 12:22:46.335986 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4547 12:22:46.339323 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4548 12:22:46.342733 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4549 12:22:46.349284 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4550 12:22:46.352653 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4551 12:22:46.355979 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4552 12:22:46.359322 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4553 12:22:46.362552 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4554 12:22:46.369283 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4555 12:22:46.372872 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4556 12:22:46.376194 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4557 12:22:46.376307 ==
4558 12:22:46.379620 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 12:22:46.382623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 12:22:46.386429 ==
4561 12:22:46.386510 DQS Delay:
4562 12:22:46.386574 DQS0 = 0, DQS1 = 0
4563 12:22:46.389293 DQM Delay:
4564 12:22:46.389375 DQM0 = 44, DQM1 = 36
4565 12:22:46.392826 DQ Delay:
4566 12:22:46.396310 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4567 12:22:46.396418 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4568 12:22:46.399457 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4569 12:22:46.402729 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4570 12:22:46.406275
4571 12:22:46.406356
4572 12:22:46.406420 ==
4573 12:22:46.409517 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 12:22:46.412902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 12:22:46.412990 ==
4576 12:22:46.413054
4577 12:22:46.413113
4578 12:22:46.416147 TX Vref Scan disable
4579 12:22:46.416256 == TX Byte 0 ==
4580 12:22:46.422595 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4581 12:22:46.426111 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4582 12:22:46.426193 == TX Byte 1 ==
4583 12:22:46.432886 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4584 12:22:46.436363 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4585 12:22:46.436483 ==
4586 12:22:46.439618 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 12:22:46.443010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 12:22:46.443096 ==
4589 12:22:46.443161
4590 12:22:46.443220
4591 12:22:46.446303 TX Vref Scan disable
4592 12:22:46.449478 == TX Byte 0 ==
4593 12:22:46.452883 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4594 12:22:46.456015 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4595 12:22:46.459295 == TX Byte 1 ==
4596 12:22:46.462628 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4597 12:22:46.466520 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4598 12:22:46.466607
4599 12:22:46.469312 [DATLAT]
4600 12:22:46.469396 Freq=600, CH1 RK0
4601 12:22:46.469461
4602 12:22:46.472915 DATLAT Default: 0x9
4603 12:22:46.472998 0, 0xFFFF, sum = 0
4604 12:22:46.476409 1, 0xFFFF, sum = 0
4605 12:22:46.476495 2, 0xFFFF, sum = 0
4606 12:22:46.479697 3, 0xFFFF, sum = 0
4607 12:22:46.479812 4, 0xFFFF, sum = 0
4608 12:22:46.482732 5, 0xFFFF, sum = 0
4609 12:22:46.482830 6, 0xFFFF, sum = 0
4610 12:22:46.486163 7, 0xFFFF, sum = 0
4611 12:22:46.486247 8, 0x0, sum = 1
4612 12:22:46.489779 9, 0x0, sum = 2
4613 12:22:46.489863 10, 0x0, sum = 3
4614 12:22:46.493234 11, 0x0, sum = 4
4615 12:22:46.493318 best_step = 9
4616 12:22:46.493383
4617 12:22:46.493443 ==
4618 12:22:46.496581 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 12:22:46.499859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 12:22:46.499942 ==
4621 12:22:46.503054 RX Vref Scan: 1
4622 12:22:46.503136
4623 12:22:46.506219 RX Vref 0 -> 0, step: 1
4624 12:22:46.506301
4625 12:22:46.506366 RX Delay -195 -> 252, step: 8
4626 12:22:46.509692
4627 12:22:46.509773 Set Vref, RX VrefLevel [Byte0]: 57
4628 12:22:46.513149 [Byte1]: 53
4629 12:22:46.518147
4630 12:22:46.518231 Final RX Vref Byte 0 = 57 to rank0
4631 12:22:46.521033 Final RX Vref Byte 1 = 53 to rank0
4632 12:22:46.524711 Final RX Vref Byte 0 = 57 to rank1
4633 12:22:46.528054 Final RX Vref Byte 1 = 53 to rank1==
4634 12:22:46.530920 Dram Type= 6, Freq= 0, CH_1, rank 0
4635 12:22:46.537725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 12:22:46.537841 ==
4637 12:22:46.537906 DQS Delay:
4638 12:22:46.537995 DQS0 = 0, DQS1 = 0
4639 12:22:46.541217 DQM Delay:
4640 12:22:46.541299 DQM0 = 40, DQM1 = 33
4641 12:22:46.544637 DQ Delay:
4642 12:22:46.547940 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4643 12:22:46.548023 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4644 12:22:46.551323 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =32
4645 12:22:46.554258 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4646 12:22:46.557629
4647 12:22:46.557710
4648 12:22:46.564470 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e04, (MSB)MR19= 0x808, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
4649 12:22:46.568029 CH1 RK0: MR19=808, MR18=3E04
4650 12:22:46.574277 CH1_RK0: MR19=0x808, MR18=0x3E04, DQSOSC=398, MR23=63, INC=165, DEC=110
4651 12:22:46.574359
4652 12:22:46.578224 ----->DramcWriteLeveling(PI) begin...
4653 12:22:46.578308 ==
4654 12:22:46.580864 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 12:22:46.584681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 12:22:46.584764 ==
4657 12:22:46.587908 Write leveling (Byte 0): 30 => 30
4658 12:22:46.591251 Write leveling (Byte 1): 31 => 31
4659 12:22:46.594528 DramcWriteLeveling(PI) end<-----
4660 12:22:46.594608
4661 12:22:46.594691 ==
4662 12:22:46.597859 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 12:22:46.601191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 12:22:46.601277 ==
4665 12:22:46.604629 [Gating] SW mode calibration
4666 12:22:46.611134 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4667 12:22:46.618322 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4668 12:22:46.621330 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 12:22:46.624803 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4670 12:22:46.631360 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4671 12:22:46.634671 0 9 12 | B1->B0 | 3131 2b2b | 0 0 | (0 1) (0 0)
4672 12:22:46.638245 0 9 16 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
4673 12:22:46.644688 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4674 12:22:46.648119 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4675 12:22:46.651646 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 12:22:46.654759 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 12:22:46.661542 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 12:22:46.664597 0 10 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4679 12:22:46.668044 0 10 12 | B1->B0 | 3030 4040 | 0 0 | (0 0) (0 0)
4680 12:22:46.675165 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 12:22:46.678400 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 12:22:46.681606 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 12:22:46.687987 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 12:22:46.691444 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 12:22:46.694980 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 12:22:46.701391 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4687 12:22:46.704885 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 12:22:46.708145 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:22:46.714927 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:22:46.718485 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:22:46.721684 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:22:46.728624 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:22:46.731787 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:22:46.735268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:22:46.741460 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 12:22:46.745143 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:22:46.748474 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:22:46.751669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:22:46.758136 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:22:46.761704 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:22:46.765212 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:22:46.771916 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 12:22:46.775386 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4704 12:22:46.778313 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 12:22:46.781905 Total UI for P1: 0, mck2ui 16
4706 12:22:46.785211 best dqsien dly found for B0: ( 0, 13, 12)
4707 12:22:46.788442 Total UI for P1: 0, mck2ui 16
4708 12:22:46.791802 best dqsien dly found for B1: ( 0, 13, 14)
4709 12:22:46.795147 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4710 12:22:46.798413 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4711 12:22:46.798546
4712 12:22:46.804752 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4713 12:22:46.808269 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4714 12:22:46.811809 [Gating] SW calibration Done
4715 12:22:46.811920 ==
4716 12:22:46.815557 Dram Type= 6, Freq= 0, CH_1, rank 1
4717 12:22:46.818878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4718 12:22:46.818991 ==
4719 12:22:46.819058 RX Vref Scan: 0
4720 12:22:46.819119
4721 12:22:46.821717 RX Vref 0 -> 0, step: 1
4722 12:22:46.821838
4723 12:22:46.825055 RX Delay -230 -> 252, step: 16
4724 12:22:46.828509 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4725 12:22:46.832164 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4726 12:22:46.838409 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4727 12:22:46.841606 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4728 12:22:46.845147 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4729 12:22:46.848478 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4730 12:22:46.852170 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4731 12:22:46.858289 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4732 12:22:46.862046 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4733 12:22:46.864962 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4734 12:22:46.868691 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4735 12:22:46.875424 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4736 12:22:46.878481 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4737 12:22:46.881705 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4738 12:22:46.885164 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4739 12:22:46.891960 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4740 12:22:46.892042 ==
4741 12:22:46.895403 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 12:22:46.898618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 12:22:46.898700 ==
4744 12:22:46.898833 DQS Delay:
4745 12:22:46.902031 DQS0 = 0, DQS1 = 0
4746 12:22:46.902111 DQM Delay:
4747 12:22:46.905387 DQM0 = 39, DQM1 = 38
4748 12:22:46.905468 DQ Delay:
4749 12:22:46.908935 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4750 12:22:46.912214 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =33
4751 12:22:46.914915 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4752 12:22:46.918437 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4753 12:22:46.918517
4754 12:22:46.918581
4755 12:22:46.918640 ==
4756 12:22:46.921725 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 12:22:46.925091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 12:22:46.925173 ==
4759 12:22:46.925237
4760 12:22:46.925297
4761 12:22:46.928455 TX Vref Scan disable
4762 12:22:46.931675 == TX Byte 0 ==
4763 12:22:46.935218 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4764 12:22:46.938700 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4765 12:22:46.941937 == TX Byte 1 ==
4766 12:22:46.945453 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4767 12:22:46.948396 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4768 12:22:46.948477 ==
4769 12:22:46.952134 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 12:22:46.955123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 12:22:46.958305 ==
4772 12:22:46.958386
4773 12:22:46.958449
4774 12:22:46.958507 TX Vref Scan disable
4775 12:22:46.962168 == TX Byte 0 ==
4776 12:22:46.965733 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4777 12:22:46.972225 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4778 12:22:46.972355 == TX Byte 1 ==
4779 12:22:46.976132 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4780 12:22:46.979155 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4781 12:22:46.982487
4782 12:22:46.982618 [DATLAT]
4783 12:22:46.982716 Freq=600, CH1 RK1
4784 12:22:46.982797
4785 12:22:46.985899 DATLAT Default: 0x9
4786 12:22:46.986010 0, 0xFFFF, sum = 0
4787 12:22:46.988935 1, 0xFFFF, sum = 0
4788 12:22:46.989046 2, 0xFFFF, sum = 0
4789 12:22:46.992478 3, 0xFFFF, sum = 0
4790 12:22:46.992598 4, 0xFFFF, sum = 0
4791 12:22:46.995835 5, 0xFFFF, sum = 0
4792 12:22:46.999014 6, 0xFFFF, sum = 0
4793 12:22:46.999166 7, 0xFFFF, sum = 0
4794 12:22:46.999262 8, 0x0, sum = 1
4795 12:22:47.002545 9, 0x0, sum = 2
4796 12:22:47.002655 10, 0x0, sum = 3
4797 12:22:47.006083 11, 0x0, sum = 4
4798 12:22:47.006168 best_step = 9
4799 12:22:47.006233
4800 12:22:47.006293 ==
4801 12:22:47.009496 Dram Type= 6, Freq= 0, CH_1, rank 1
4802 12:22:47.016092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4803 12:22:47.016175 ==
4804 12:22:47.016240 RX Vref Scan: 0
4805 12:22:47.016300
4806 12:22:47.019284 RX Vref 0 -> 0, step: 1
4807 12:22:47.019366
4808 12:22:47.022681 RX Delay -179 -> 252, step: 8
4809 12:22:47.025691 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4810 12:22:47.032284 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4811 12:22:47.035777 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4812 12:22:47.038996 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4813 12:22:47.042376 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4814 12:22:47.045798 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4815 12:22:47.052657 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4816 12:22:47.056116 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4817 12:22:47.059408 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4818 12:22:47.062655 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4819 12:22:47.065872 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4820 12:22:47.072368 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4821 12:22:47.075913 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4822 12:22:47.079066 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4823 12:22:47.082227 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4824 12:22:47.089420 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4825 12:22:47.089502 ==
4826 12:22:47.092811 Dram Type= 6, Freq= 0, CH_1, rank 1
4827 12:22:47.096073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4828 12:22:47.096155 ==
4829 12:22:47.096220 DQS Delay:
4830 12:22:47.099143 DQS0 = 0, DQS1 = 0
4831 12:22:47.099225 DQM Delay:
4832 12:22:47.102480 DQM0 = 38, DQM1 = 33
4833 12:22:47.102562 DQ Delay:
4834 12:22:47.106094 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4835 12:22:47.109258 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4836 12:22:47.112843 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4837 12:22:47.115946 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4838 12:22:47.116028
4839 12:22:47.116092
4840 12:22:47.122755 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b4a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4841 12:22:47.126342 CH1 RK1: MR19=808, MR18=3B4A
4842 12:22:47.132716 CH1_RK1: MR19=0x808, MR18=0x3B4A, DQSOSC=395, MR23=63, INC=168, DEC=112
4843 12:22:47.136382 [RxdqsGatingPostProcess] freq 600
4844 12:22:47.142609 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4845 12:22:47.146521 Pre-setting of DQS Precalculation
4846 12:22:47.149983 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4847 12:22:47.156610 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4848 12:22:47.162992 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4849 12:22:47.163089
4850 12:22:47.163175
4851 12:22:47.166165 [Calibration Summary] 1200 Mbps
4852 12:22:47.169292 CH 0, Rank 0
4853 12:22:47.169376 SW Impedance : PASS
4854 12:22:47.172691 DUTY Scan : NO K
4855 12:22:47.175955 ZQ Calibration : PASS
4856 12:22:47.176038 Jitter Meter : NO K
4857 12:22:47.179538 CBT Training : PASS
4858 12:22:47.179621 Write leveling : PASS
4859 12:22:47.182613 RX DQS gating : PASS
4860 12:22:47.186149 RX DQ/DQS(RDDQC) : PASS
4861 12:22:47.186232 TX DQ/DQS : PASS
4862 12:22:47.189376 RX DATLAT : PASS
4863 12:22:47.192931 RX DQ/DQS(Engine): PASS
4864 12:22:47.193015 TX OE : NO K
4865 12:22:47.196081 All Pass.
4866 12:22:47.196164
4867 12:22:47.196248 CH 0, Rank 1
4868 12:22:47.199298 SW Impedance : PASS
4869 12:22:47.199381 DUTY Scan : NO K
4870 12:22:47.202751 ZQ Calibration : PASS
4871 12:22:47.205875 Jitter Meter : NO K
4872 12:22:47.205958 CBT Training : PASS
4873 12:22:47.209675 Write leveling : PASS
4874 12:22:47.212671 RX DQS gating : PASS
4875 12:22:47.212755 RX DQ/DQS(RDDQC) : PASS
4876 12:22:47.216077 TX DQ/DQS : PASS
4877 12:22:47.219608 RX DATLAT : PASS
4878 12:22:47.219716 RX DQ/DQS(Engine): PASS
4879 12:22:47.223096 TX OE : NO K
4880 12:22:47.223177 All Pass.
4881 12:22:47.223241
4882 12:22:47.223300 CH 1, Rank 0
4883 12:22:47.226013 SW Impedance : PASS
4884 12:22:47.229252 DUTY Scan : NO K
4885 12:22:47.229357 ZQ Calibration : PASS
4886 12:22:47.232543 Jitter Meter : NO K
4887 12:22:47.236590 CBT Training : PASS
4888 12:22:47.236670 Write leveling : PASS
4889 12:22:47.239931 RX DQS gating : PASS
4890 12:22:47.242982 RX DQ/DQS(RDDQC) : PASS
4891 12:22:47.243062 TX DQ/DQS : PASS
4892 12:22:47.245928 RX DATLAT : PASS
4893 12:22:47.249285 RX DQ/DQS(Engine): PASS
4894 12:22:47.249392 TX OE : NO K
4895 12:22:47.252768 All Pass.
4896 12:22:47.252848
4897 12:22:47.252913 CH 1, Rank 1
4898 12:22:47.256622 SW Impedance : PASS
4899 12:22:47.256703 DUTY Scan : NO K
4900 12:22:47.259486 ZQ Calibration : PASS
4901 12:22:47.259567 Jitter Meter : NO K
4902 12:22:47.262785 CBT Training : PASS
4903 12:22:47.266687 Write leveling : PASS
4904 12:22:47.266806 RX DQS gating : PASS
4905 12:22:47.270028 RX DQ/DQS(RDDQC) : PASS
4906 12:22:47.273230 TX DQ/DQS : PASS
4907 12:22:47.273311 RX DATLAT : PASS
4908 12:22:47.276187 RX DQ/DQS(Engine): PASS
4909 12:22:47.279781 TX OE : NO K
4910 12:22:47.279862 All Pass.
4911 12:22:47.279926
4912 12:22:47.282677 DramC Write-DBI off
4913 12:22:47.282800 PER_BANK_REFRESH: Hybrid Mode
4914 12:22:47.286280 TX_TRACKING: ON
4915 12:22:47.292868 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4916 12:22:47.299576 [FAST_K] Save calibration result to emmc
4917 12:22:47.303070 dramc_set_vcore_voltage set vcore to 662500
4918 12:22:47.303150 Read voltage for 933, 3
4919 12:22:47.305923 Vio18 = 0
4920 12:22:47.306004 Vcore = 662500
4921 12:22:47.306067 Vdram = 0
4922 12:22:47.309586 Vddq = 0
4923 12:22:47.309666 Vmddr = 0
4924 12:22:47.312873 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4925 12:22:47.319560 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4926 12:22:47.323077 MEM_TYPE=3, freq_sel=17
4927 12:22:47.326285 sv_algorithm_assistance_LP4_1600
4928 12:22:47.329497 ============ PULL DRAM RESETB DOWN ============
4929 12:22:47.333071 ========== PULL DRAM RESETB DOWN end =========
4930 12:22:47.336159 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4931 12:22:47.340020 ===================================
4932 12:22:47.342682 LPDDR4 DRAM CONFIGURATION
4933 12:22:47.346304 ===================================
4934 12:22:47.349706 EX_ROW_EN[0] = 0x0
4935 12:22:47.349786 EX_ROW_EN[1] = 0x0
4936 12:22:47.353010 LP4Y_EN = 0x0
4937 12:22:47.353091 WORK_FSP = 0x0
4938 12:22:47.356118 WL = 0x3
4939 12:22:47.356198 RL = 0x3
4940 12:22:47.359457 BL = 0x2
4941 12:22:47.359538 RPST = 0x0
4942 12:22:47.362820 RD_PRE = 0x0
4943 12:22:47.362925 WR_PRE = 0x1
4944 12:22:47.366705 WR_PST = 0x0
4945 12:22:47.366791 DBI_WR = 0x0
4946 12:22:47.369380 DBI_RD = 0x0
4947 12:22:47.369460 OTF = 0x1
4948 12:22:47.372869 ===================================
4949 12:22:47.376074 ===================================
4950 12:22:47.379811 ANA top config
4951 12:22:47.382946 ===================================
4952 12:22:47.386495 DLL_ASYNC_EN = 0
4953 12:22:47.386579 ALL_SLAVE_EN = 1
4954 12:22:47.389449 NEW_RANK_MODE = 1
4955 12:22:47.392729 DLL_IDLE_MODE = 1
4956 12:22:47.396110 LP45_APHY_COMB_EN = 1
4957 12:22:47.396190 TX_ODT_DIS = 1
4958 12:22:47.399949 NEW_8X_MODE = 1
4959 12:22:47.402709 ===================================
4960 12:22:47.406590 ===================================
4961 12:22:47.409734 data_rate = 1866
4962 12:22:47.413364 CKR = 1
4963 12:22:47.416321 DQ_P2S_RATIO = 8
4964 12:22:47.419517 ===================================
4965 12:22:47.422942 CA_P2S_RATIO = 8
4966 12:22:47.423035 DQ_CA_OPEN = 0
4967 12:22:47.426238 DQ_SEMI_OPEN = 0
4968 12:22:47.430348 CA_SEMI_OPEN = 0
4969 12:22:47.433086 CA_FULL_RATE = 0
4970 12:22:47.436291 DQ_CKDIV4_EN = 1
4971 12:22:47.436374 CA_CKDIV4_EN = 1
4972 12:22:47.439845 CA_PREDIV_EN = 0
4973 12:22:47.443067 PH8_DLY = 0
4974 12:22:47.446367 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4975 12:22:47.449851 DQ_AAMCK_DIV = 4
4976 12:22:47.453301 CA_AAMCK_DIV = 4
4977 12:22:47.453381 CA_ADMCK_DIV = 4
4978 12:22:47.456756 DQ_TRACK_CA_EN = 0
4979 12:22:47.459990 CA_PICK = 933
4980 12:22:47.463245 CA_MCKIO = 933
4981 12:22:47.466605 MCKIO_SEMI = 0
4982 12:22:47.469622 PLL_FREQ = 3732
4983 12:22:47.472967 DQ_UI_PI_RATIO = 32
4984 12:22:47.473058 CA_UI_PI_RATIO = 0
4985 12:22:47.476806 ===================================
4986 12:22:47.479825 ===================================
4987 12:22:47.483519 memory_type:LPDDR4
4988 12:22:47.486835 GP_NUM : 10
4989 12:22:47.486950 SRAM_EN : 1
4990 12:22:47.489738 MD32_EN : 0
4991 12:22:47.492992 ===================================
4992 12:22:47.496475 [ANA_INIT] >>>>>>>>>>>>>>
4993 12:22:47.499799 <<<<<< [CONFIGURE PHASE]: ANA_TX
4994 12:22:47.503343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4995 12:22:47.506560 ===================================
4996 12:22:47.506639 data_rate = 1866,PCW = 0X8f00
4997 12:22:47.510022 ===================================
4998 12:22:47.513499 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4999 12:22:47.519983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5000 12:22:47.526697 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5001 12:22:47.529823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5002 12:22:47.533162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5003 12:22:47.536525 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5004 12:22:47.540237 [ANA_INIT] flow start
5005 12:22:47.540343 [ANA_INIT] PLL >>>>>>>>
5006 12:22:47.543310 [ANA_INIT] PLL <<<<<<<<
5007 12:22:47.546431 [ANA_INIT] MIDPI >>>>>>>>
5008 12:22:47.550004 [ANA_INIT] MIDPI <<<<<<<<
5009 12:22:47.550083 [ANA_INIT] DLL >>>>>>>>
5010 12:22:47.553206 [ANA_INIT] flow end
5011 12:22:47.556609 ============ LP4 DIFF to SE enter ============
5012 12:22:47.560154 ============ LP4 DIFF to SE exit ============
5013 12:22:47.563268 [ANA_INIT] <<<<<<<<<<<<<
5014 12:22:47.566614 [Flow] Enable top DCM control >>>>>
5015 12:22:47.569827 [Flow] Enable top DCM control <<<<<
5016 12:22:47.573441 Enable DLL master slave shuffle
5017 12:22:47.576537 ==============================================================
5018 12:22:47.580211 Gating Mode config
5019 12:22:47.586619 ==============================================================
5020 12:22:47.586699 Config description:
5021 12:22:47.596750 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5022 12:22:47.603407 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5023 12:22:47.606543 SELPH_MODE 0: By rank 1: By Phase
5024 12:22:47.613226 ==============================================================
5025 12:22:47.616938 GAT_TRACK_EN = 1
5026 12:22:47.619735 RX_GATING_MODE = 2
5027 12:22:47.623179 RX_GATING_TRACK_MODE = 2
5028 12:22:47.626453 SELPH_MODE = 1
5029 12:22:47.629637 PICG_EARLY_EN = 1
5030 12:22:47.632884 VALID_LAT_VALUE = 1
5031 12:22:47.636503 ==============================================================
5032 12:22:47.639698 Enter into Gating configuration >>>>
5033 12:22:47.643149 Exit from Gating configuration <<<<
5034 12:22:47.646351 Enter into DVFS_PRE_config >>>>>
5035 12:22:47.659797 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5036 12:22:47.659879 Exit from DVFS_PRE_config <<<<<
5037 12:22:47.663139 Enter into PICG configuration >>>>
5038 12:22:47.666535 Exit from PICG configuration <<<<
5039 12:22:47.669871 [RX_INPUT] configuration >>>>>
5040 12:22:47.673485 [RX_INPUT] configuration <<<<<
5041 12:22:47.679564 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5042 12:22:47.682956 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5043 12:22:47.690026 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5044 12:22:47.696409 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5045 12:22:47.702943 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5046 12:22:47.709789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5047 12:22:47.713277 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5048 12:22:47.716363 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5049 12:22:47.719956 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5050 12:22:47.726560 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5051 12:22:47.730244 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5052 12:22:47.733127 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5053 12:22:47.736621 ===================================
5054 12:22:47.740011 LPDDR4 DRAM CONFIGURATION
5055 12:22:47.742969 ===================================
5056 12:22:47.743051 EX_ROW_EN[0] = 0x0
5057 12:22:47.746376 EX_ROW_EN[1] = 0x0
5058 12:22:47.746457 LP4Y_EN = 0x0
5059 12:22:47.749685 WORK_FSP = 0x0
5060 12:22:47.749765 WL = 0x3
5061 12:22:47.753176 RL = 0x3
5062 12:22:47.756661 BL = 0x2
5063 12:22:47.756742 RPST = 0x0
5064 12:22:47.760312 RD_PRE = 0x0
5065 12:22:47.760393 WR_PRE = 0x1
5066 12:22:47.763408 WR_PST = 0x0
5067 12:22:47.763490 DBI_WR = 0x0
5068 12:22:47.766748 DBI_RD = 0x0
5069 12:22:47.766843 OTF = 0x1
5070 12:22:47.769731 ===================================
5071 12:22:47.773282 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5072 12:22:47.779809 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5073 12:22:47.783231 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5074 12:22:47.786836 ===================================
5075 12:22:47.789869 LPDDR4 DRAM CONFIGURATION
5076 12:22:47.793069 ===================================
5077 12:22:47.793151 EX_ROW_EN[0] = 0x10
5078 12:22:47.796839 EX_ROW_EN[1] = 0x0
5079 12:22:47.796920 LP4Y_EN = 0x0
5080 12:22:47.800052 WORK_FSP = 0x0
5081 12:22:47.800133 WL = 0x3
5082 12:22:47.803227 RL = 0x3
5083 12:22:47.803308 BL = 0x2
5084 12:22:47.806472 RPST = 0x0
5085 12:22:47.806553 RD_PRE = 0x0
5086 12:22:47.810097 WR_PRE = 0x1
5087 12:22:47.810178 WR_PST = 0x0
5088 12:22:47.813137 DBI_WR = 0x0
5089 12:22:47.813218 DBI_RD = 0x0
5090 12:22:47.817371 OTF = 0x1
5091 12:22:47.820103 ===================================
5092 12:22:47.826537 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5093 12:22:47.829916 nWR fixed to 30
5094 12:22:47.833243 [ModeRegInit_LP4] CH0 RK0
5095 12:22:47.833325 [ModeRegInit_LP4] CH0 RK1
5096 12:22:47.836661 [ModeRegInit_LP4] CH1 RK0
5097 12:22:47.839987 [ModeRegInit_LP4] CH1 RK1
5098 12:22:47.840067 match AC timing 9
5099 12:22:47.846545 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5100 12:22:47.850086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5101 12:22:47.853410 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5102 12:22:47.860378 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5103 12:22:47.863220 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5104 12:22:47.863302 ==
5105 12:22:47.867232 Dram Type= 6, Freq= 0, CH_0, rank 0
5106 12:22:47.870055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 12:22:47.870137 ==
5108 12:22:47.876878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5109 12:22:47.883508 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5110 12:22:47.886906 [CA 0] Center 38 (8~69) winsize 62
5111 12:22:47.890029 [CA 1] Center 38 (8~68) winsize 61
5112 12:22:47.893313 [CA 2] Center 35 (5~66) winsize 62
5113 12:22:47.897089 [CA 3] Center 34 (4~65) winsize 62
5114 12:22:47.899871 [CA 4] Center 34 (4~65) winsize 62
5115 12:22:47.903224 [CA 5] Center 33 (3~64) winsize 62
5116 12:22:47.903335
5117 12:22:47.906668 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5118 12:22:47.906788
5119 12:22:47.910141 [CATrainingPosCal] consider 1 rank data
5120 12:22:47.913584 u2DelayCellTimex100 = 270/100 ps
5121 12:22:47.917037 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5122 12:22:47.920544 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5123 12:22:47.923213 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5124 12:22:47.926676 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5125 12:22:47.930481 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5126 12:22:47.933562 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5127 12:22:47.933643
5128 12:22:47.936959 CA PerBit enable=1, Macro0, CA PI delay=33
5129 12:22:47.940593
5130 12:22:47.940674 [CBTSetCACLKResult] CA Dly = 33
5131 12:22:47.943767 CS Dly: 6 (0~37)
5132 12:22:47.943848 ==
5133 12:22:47.946680 Dram Type= 6, Freq= 0, CH_0, rank 1
5134 12:22:47.950027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 12:22:47.950109 ==
5136 12:22:47.957021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 12:22:47.963395 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5138 12:22:47.966759 [CA 0] Center 38 (8~69) winsize 62
5139 12:22:47.970062 [CA 1] Center 38 (7~69) winsize 63
5140 12:22:47.973832 [CA 2] Center 35 (5~66) winsize 62
5141 12:22:47.977128 [CA 3] Center 35 (5~66) winsize 62
5142 12:22:47.979924 [CA 4] Center 34 (4~64) winsize 61
5143 12:22:47.983514 [CA 5] Center 33 (3~64) winsize 62
5144 12:22:47.983596
5145 12:22:47.987049 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5146 12:22:47.987131
5147 12:22:47.990596 [CATrainingPosCal] consider 2 rank data
5148 12:22:47.993506 u2DelayCellTimex100 = 270/100 ps
5149 12:22:47.996724 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5150 12:22:48.000302 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5151 12:22:48.003993 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5152 12:22:48.006778 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5153 12:22:48.010519 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5154 12:22:48.013808 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5155 12:22:48.013892
5156 12:22:48.017078 CA PerBit enable=1, Macro0, CA PI delay=33
5157 12:22:48.017163
5158 12:22:48.020119 [CBTSetCACLKResult] CA Dly = 33
5159 12:22:48.023551 CS Dly: 7 (0~39)
5160 12:22:48.023678
5161 12:22:48.027062 ----->DramcWriteLeveling(PI) begin...
5162 12:22:48.027182 ==
5163 12:22:48.030524 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 12:22:48.034009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 12:22:48.034099 ==
5166 12:22:48.037381 Write leveling (Byte 0): 32 => 32
5167 12:22:48.040653 Write leveling (Byte 1): 30 => 30
5168 12:22:48.043437 DramcWriteLeveling(PI) end<-----
5169 12:22:48.043522
5170 12:22:48.043587 ==
5171 12:22:48.046873 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 12:22:48.050603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 12:22:48.050686 ==
5174 12:22:48.054163 [Gating] SW mode calibration
5175 12:22:48.060494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5176 12:22:48.066808 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5177 12:22:48.070812 0 14 0 | B1->B0 | 2323 2f2f | 1 1 | (1 1) (1 1)
5178 12:22:48.076870 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
5179 12:22:48.080333 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 12:22:48.083572 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 12:22:48.086644 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5182 12:22:48.093530 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 12:22:48.097077 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 12:22:48.100491 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5185 12:22:48.107574 0 15 0 | B1->B0 | 3131 2c2c | 1 0 | (1 0) (0 0)
5186 12:22:48.110550 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5187 12:22:48.114015 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 12:22:48.120534 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 12:22:48.124066 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 12:22:48.127148 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 12:22:48.134287 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 12:22:48.137787 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5193 12:22:48.141188 1 0 0 | B1->B0 | 2f2f 3c3c | 0 0 | (0 0) (0 0)
5194 12:22:48.148215 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5195 12:22:48.151272 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 12:22:48.154347 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 12:22:48.157551 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 12:22:48.164010 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 12:22:48.167990 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 12:22:48.170995 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 12:22:48.179785 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5202 12:22:48.180865 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5203 12:22:48.184294 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:22:48.190795 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:22:48.194374 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:22:48.197290 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:22:48.204333 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 12:22:48.207712 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 12:22:48.210981 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 12:22:48.217497 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:22:48.221068 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 12:22:48.224349 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 12:22:48.230892 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 12:22:48.234854 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 12:22:48.237828 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 12:22:48.244379 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5217 12:22:48.247362 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5218 12:22:48.250779 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 12:22:48.254506 Total UI for P1: 0, mck2ui 16
5220 12:22:48.258478 best dqsien dly found for B0: ( 1, 2, 30)
5221 12:22:48.261342 Total UI for P1: 0, mck2ui 16
5222 12:22:48.264125 best dqsien dly found for B1: ( 1, 3, 0)
5223 12:22:48.267547 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5224 12:22:48.270822 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5225 12:22:48.271170
5226 12:22:48.274403 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5227 12:22:48.278088 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5228 12:22:48.281133 [Gating] SW calibration Done
5229 12:22:48.281489 ==
5230 12:22:48.284551 Dram Type= 6, Freq= 0, CH_0, rank 0
5231 12:22:48.290986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5232 12:22:48.291337 ==
5233 12:22:48.291619 RX Vref Scan: 0
5234 12:22:48.291878
5235 12:22:48.294431 RX Vref 0 -> 0, step: 1
5236 12:22:48.294817
5237 12:22:48.297660 RX Delay -80 -> 252, step: 8
5238 12:22:48.300752 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5239 12:22:48.304326 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5240 12:22:48.307776 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5241 12:22:48.311016 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5242 12:22:48.314706 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5243 12:22:48.321115 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5244 12:22:48.324400 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5245 12:22:48.327904 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5246 12:22:48.331290 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5247 12:22:48.334490 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5248 12:22:48.337592 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5249 12:22:48.344796 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5250 12:22:48.347634 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5251 12:22:48.351214 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5252 12:22:48.354842 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5253 12:22:48.358031 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5254 12:22:48.358480 ==
5255 12:22:48.361029 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 12:22:48.368212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 12:22:48.368707 ==
5258 12:22:48.369014 DQS Delay:
5259 12:22:48.369293 DQS0 = 0, DQS1 = 0
5260 12:22:48.371450 DQM Delay:
5261 12:22:48.371888 DQM0 = 98, DQM1 = 88
5262 12:22:48.375099 DQ Delay:
5263 12:22:48.378087 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =95
5264 12:22:48.381368 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5265 12:22:48.384525 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5266 12:22:48.388256 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5267 12:22:48.388657
5268 12:22:48.388958
5269 12:22:48.389236 ==
5270 12:22:48.391197 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 12:22:48.394773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 12:22:48.395171 ==
5273 12:22:48.395527
5274 12:22:48.395817
5275 12:22:48.397705 TX Vref Scan disable
5276 12:22:48.398080 == TX Byte 0 ==
5277 12:22:48.404764 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5278 12:22:48.408490 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5279 12:22:48.408974 == TX Byte 1 ==
5280 12:22:48.414855 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5281 12:22:48.418300 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5282 12:22:48.418858 ==
5283 12:22:48.421376 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 12:22:48.424744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 12:22:48.425262 ==
5286 12:22:48.425589
5287 12:22:48.425891
5288 12:22:48.428209 TX Vref Scan disable
5289 12:22:48.431412 == TX Byte 0 ==
5290 12:22:48.434862 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5291 12:22:48.437940 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5292 12:22:48.441388 == TX Byte 1 ==
5293 12:22:48.444775 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5294 12:22:48.447859 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5295 12:22:48.448272
5296 12:22:48.451890 [DATLAT]
5297 12:22:48.452405 Freq=933, CH0 RK0
5298 12:22:48.452734
5299 12:22:48.455232 DATLAT Default: 0xd
5300 12:22:48.455641 0, 0xFFFF, sum = 0
5301 12:22:48.458901 1, 0xFFFF, sum = 0
5302 12:22:48.459431 2, 0xFFFF, sum = 0
5303 12:22:48.461892 3, 0xFFFF, sum = 0
5304 12:22:48.462376 4, 0xFFFF, sum = 0
5305 12:22:48.464706 5, 0xFFFF, sum = 0
5306 12:22:48.465091 6, 0xFFFF, sum = 0
5307 12:22:48.468758 7, 0xFFFF, sum = 0
5308 12:22:48.469251 8, 0xFFFF, sum = 0
5309 12:22:48.471454 9, 0xFFFF, sum = 0
5310 12:22:48.471837 10, 0x0, sum = 1
5311 12:22:48.475130 11, 0x0, sum = 2
5312 12:22:48.475621 12, 0x0, sum = 3
5313 12:22:48.478420 13, 0x0, sum = 4
5314 12:22:48.478840 best_step = 11
5315 12:22:48.479146
5316 12:22:48.479425 ==
5317 12:22:48.481384 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 12:22:48.484829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 12:22:48.488466 ==
5320 12:22:48.488873 RX Vref Scan: 1
5321 12:22:48.489170
5322 12:22:48.491715 RX Vref 0 -> 0, step: 1
5323 12:22:48.492094
5324 12:22:48.494678 RX Delay -61 -> 252, step: 4
5325 12:22:48.495084
5326 12:22:48.497995 Set Vref, RX VrefLevel [Byte0]: 54
5327 12:22:48.501543 [Byte1]: 50
5328 12:22:48.502021
5329 12:22:48.504782 Final RX Vref Byte 0 = 54 to rank0
5330 12:22:48.508315 Final RX Vref Byte 1 = 50 to rank0
5331 12:22:48.511450 Final RX Vref Byte 0 = 54 to rank1
5332 12:22:48.515017 Final RX Vref Byte 1 = 50 to rank1==
5333 12:22:48.518310 Dram Type= 6, Freq= 0, CH_0, rank 0
5334 12:22:48.521779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 12:22:48.522161 ==
5336 12:22:48.524941 DQS Delay:
5337 12:22:48.525434 DQS0 = 0, DQS1 = 0
5338 12:22:48.525738 DQM Delay:
5339 12:22:48.528651 DQM0 = 96, DQM1 = 87
5340 12:22:48.529132 DQ Delay:
5341 12:22:48.531646 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5342 12:22:48.534642 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5343 12:22:48.538008 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
5344 12:22:48.541649 DQ12 =94, DQ13 =90, DQ14 =100, DQ15 =96
5345 12:22:48.542024
5346 12:22:48.542319
5347 12:22:48.551672 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps
5348 12:22:48.552068 CH0 RK0: MR19=504, MR18=12FD
5349 12:22:48.558622 CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41
5350 12:22:48.559235
5351 12:22:48.561575 ----->DramcWriteLeveling(PI) begin...
5352 12:22:48.561987 ==
5353 12:22:48.564906 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 12:22:48.571755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 12:22:48.572135 ==
5356 12:22:48.575288 Write leveling (Byte 0): 34 => 34
5357 12:22:48.578542 Write leveling (Byte 1): 27 => 27
5358 12:22:48.579058 DramcWriteLeveling(PI) end<-----
5359 12:22:48.579374
5360 12:22:48.581716 ==
5361 12:22:48.584771 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 12:22:48.588192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 12:22:48.588567 ==
5364 12:22:48.592013 [Gating] SW mode calibration
5365 12:22:48.598779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5366 12:22:48.601632 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5367 12:22:48.608474 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5368 12:22:48.611847 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5369 12:22:48.615451 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 12:22:48.622441 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 12:22:48.625228 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 12:22:48.628101 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 12:22:48.635097 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5374 12:22:48.638654 0 14 28 | B1->B0 | 3333 2929 | 0 0 | (0 1) (0 0)
5375 12:22:48.642372 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5376 12:22:48.645154 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 12:22:48.651706 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 12:22:48.654992 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 12:22:48.658464 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 12:22:48.664811 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 12:22:48.668406 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 12:22:48.671715 0 15 28 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
5383 12:22:48.678674 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5384 12:22:48.681719 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 12:22:48.684841 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 12:22:48.692252 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 12:22:48.695229 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 12:22:48.698622 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 12:22:48.705093 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 12:22:48.708346 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5391 12:22:48.711568 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5392 12:22:48.718831 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5393 12:22:48.721972 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:22:48.725326 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:22:48.731557 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:22:48.734886 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:22:48.738806 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:22:48.745138 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 12:22:48.748315 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 12:22:48.752249 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:22:48.755033 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 12:22:48.761379 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 12:22:48.764839 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:22:48.768100 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 12:22:48.774980 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5406 12:22:48.778180 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5407 12:22:48.781931 Total UI for P1: 0, mck2ui 16
5408 12:22:48.785344 best dqsien dly found for B0: ( 1, 2, 24)
5409 12:22:48.788300 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5410 12:22:48.795167 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5411 12:22:48.795543 Total UI for P1: 0, mck2ui 16
5412 12:22:48.801743 best dqsien dly found for B1: ( 1, 2, 30)
5413 12:22:48.804989 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5414 12:22:48.808264 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5415 12:22:48.808644
5416 12:22:48.811700 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5417 12:22:48.815166 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5418 12:22:48.818335 [Gating] SW calibration Done
5419 12:22:48.818716 ==
5420 12:22:48.822059 Dram Type= 6, Freq= 0, CH_0, rank 1
5421 12:22:48.825426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5422 12:22:48.825816 ==
5423 12:22:48.828608 RX Vref Scan: 0
5424 12:22:48.828988
5425 12:22:48.829287 RX Vref 0 -> 0, step: 1
5426 12:22:48.829585
5427 12:22:48.832078 RX Delay -80 -> 252, step: 8
5428 12:22:48.835052 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5429 12:22:48.838718 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5430 12:22:48.845866 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5431 12:22:48.848385 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5432 12:22:48.852173 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5433 12:22:48.855216 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5434 12:22:48.858493 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5435 12:22:48.862118 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5436 12:22:48.865175 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5437 12:22:48.872442 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5438 12:22:48.875666 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5439 12:22:48.878855 iDelay=208, Bit 11, Center 79 (-8 ~ 167) 176
5440 12:22:48.882509 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5441 12:22:48.885527 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5442 12:22:48.889127 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5443 12:22:48.895718 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5444 12:22:48.896173 ==
5445 12:22:48.898705 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 12:22:48.902038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 12:22:48.902460 ==
5448 12:22:48.902837 DQS Delay:
5449 12:22:48.906172 DQS0 = 0, DQS1 = 0
5450 12:22:48.906699 DQM Delay:
5451 12:22:48.909847 DQM0 = 97, DQM1 = 88
5452 12:22:48.910393 DQ Delay:
5453 12:22:48.912000 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5454 12:22:48.915927 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =103
5455 12:22:48.918774 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5456 12:22:48.922049 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5457 12:22:48.922499
5458 12:22:48.922900
5459 12:22:48.923220 ==
5460 12:22:48.925493 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 12:22:48.928789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 12:22:48.929210 ==
5463 12:22:48.932398
5464 12:22:48.932814
5465 12:22:48.933147 TX Vref Scan disable
5466 12:22:48.935320 == TX Byte 0 ==
5467 12:22:48.938913 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5468 12:22:48.942349 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5469 12:22:48.945434 == TX Byte 1 ==
5470 12:22:48.949012 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5471 12:22:48.953032 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5472 12:22:48.953532 ==
5473 12:22:48.955305 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 12:22:48.962213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 12:22:48.962602 ==
5476 12:22:48.962965
5477 12:22:48.963255
5478 12:22:48.963529 TX Vref Scan disable
5479 12:22:48.966515 == TX Byte 0 ==
5480 12:22:48.969618 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5481 12:22:48.973499 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5482 12:22:48.977053 == TX Byte 1 ==
5483 12:22:48.979856 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5484 12:22:48.983209 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5485 12:22:48.986435
5486 12:22:48.986883 [DATLAT]
5487 12:22:48.987221 Freq=933, CH0 RK1
5488 12:22:48.987533
5489 12:22:48.989998 DATLAT Default: 0xb
5490 12:22:48.990413 0, 0xFFFF, sum = 0
5491 12:22:48.993579 1, 0xFFFF, sum = 0
5492 12:22:48.994004 2, 0xFFFF, sum = 0
5493 12:22:48.996681 3, 0xFFFF, sum = 0
5494 12:22:48.997107 4, 0xFFFF, sum = 0
5495 12:22:48.999938 5, 0xFFFF, sum = 0
5496 12:22:49.000368 6, 0xFFFF, sum = 0
5497 12:22:49.003191 7, 0xFFFF, sum = 0
5498 12:22:49.006468 8, 0xFFFF, sum = 0
5499 12:22:49.007045 9, 0xFFFF, sum = 0
5500 12:22:49.009591 10, 0x0, sum = 1
5501 12:22:49.009981 11, 0x0, sum = 2
5502 12:22:49.010292 12, 0x0, sum = 3
5503 12:22:49.013081 13, 0x0, sum = 4
5504 12:22:49.013471 best_step = 11
5505 12:22:49.013779
5506 12:22:49.014063 ==
5507 12:22:49.016689 Dram Type= 6, Freq= 0, CH_0, rank 1
5508 12:22:49.022986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5509 12:22:49.023464 ==
5510 12:22:49.023772 RX Vref Scan: 0
5511 12:22:49.024058
5512 12:22:49.026410 RX Vref 0 -> 0, step: 1
5513 12:22:49.026831
5514 12:22:49.030041 RX Delay -61 -> 252, step: 4
5515 12:22:49.033036 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5516 12:22:49.036386 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5517 12:22:49.043347 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5518 12:22:49.046471 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5519 12:22:49.050245 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5520 12:22:49.053255 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5521 12:22:49.056608 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5522 12:22:49.059823 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5523 12:22:49.066840 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5524 12:22:49.069810 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5525 12:22:49.072976 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5526 12:22:49.076708 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5527 12:22:49.079855 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5528 12:22:49.086473 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5529 12:22:49.089945 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5530 12:22:49.093076 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5531 12:22:49.093460 ==
5532 12:22:49.096481 Dram Type= 6, Freq= 0, CH_0, rank 1
5533 12:22:49.100010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 12:22:49.100397 ==
5535 12:22:49.103218 DQS Delay:
5536 12:22:49.103601 DQS0 = 0, DQS1 = 0
5537 12:22:49.103908 DQM Delay:
5538 12:22:49.107000 DQM0 = 96, DQM1 = 88
5539 12:22:49.107382 DQ Delay:
5540 12:22:49.109810 DQ0 =98, DQ1 =96, DQ2 =92, DQ3 =94
5541 12:22:49.113186 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =104
5542 12:22:49.116600 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =80
5543 12:22:49.120172 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5544 12:22:49.120663
5545 12:22:49.120970
5546 12:22:49.129828 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
5547 12:22:49.133031 CH0 RK1: MR19=505, MR18=1C09
5548 12:22:49.136645 CH0_RK1: MR19=0x505, MR18=0x1C09, DQSOSC=412, MR23=63, INC=63, DEC=42
5549 12:22:49.139769 [RxdqsGatingPostProcess] freq 933
5550 12:22:49.146539 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5551 12:22:49.150144 best DQS0 dly(2T, 0.5T) = (0, 10)
5552 12:22:49.153669 best DQS1 dly(2T, 0.5T) = (0, 11)
5553 12:22:49.156835 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5554 12:22:49.160287 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5555 12:22:49.163279 best DQS0 dly(2T, 0.5T) = (0, 10)
5556 12:22:49.163689 best DQS1 dly(2T, 0.5T) = (0, 10)
5557 12:22:49.166951 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5558 12:22:49.169712 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5559 12:22:49.173474 Pre-setting of DQS Precalculation
5560 12:22:49.179832 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5561 12:22:49.180243 ==
5562 12:22:49.183537 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 12:22:49.186750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 12:22:49.187183 ==
5565 12:22:49.193555 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 12:22:49.200104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5567 12:22:49.203532 [CA 0] Center 36 (6~67) winsize 62
5568 12:22:49.206402 [CA 1] Center 36 (6~67) winsize 62
5569 12:22:49.210166 [CA 2] Center 34 (4~64) winsize 61
5570 12:22:49.213415 [CA 3] Center 33 (3~64) winsize 62
5571 12:22:49.216931 [CA 4] Center 34 (4~65) winsize 62
5572 12:22:49.217428 [CA 5] Center 33 (3~64) winsize 62
5573 12:22:49.217855
5574 12:22:49.223814 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5575 12:22:49.224189
5576 12:22:49.227088 [CATrainingPosCal] consider 1 rank data
5577 12:22:49.230286 u2DelayCellTimex100 = 270/100 ps
5578 12:22:49.233473 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5579 12:22:49.236726 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 12:22:49.240558 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 12:22:49.243572 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 12:22:49.247037 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5583 12:22:49.249825 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5584 12:22:49.250200
5585 12:22:49.253894 CA PerBit enable=1, Macro0, CA PI delay=33
5586 12:22:49.254270
5587 12:22:49.256929 [CBTSetCACLKResult] CA Dly = 33
5588 12:22:49.260350 CS Dly: 4 (0~35)
5589 12:22:49.260723 ==
5590 12:22:49.263651 Dram Type= 6, Freq= 0, CH_1, rank 1
5591 12:22:49.266778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 12:22:49.267208 ==
5593 12:22:49.273370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 12:22:49.277227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5595 12:22:49.281320 [CA 0] Center 36 (6~67) winsize 62
5596 12:22:49.284715 [CA 1] Center 36 (6~67) winsize 62
5597 12:22:49.287786 [CA 2] Center 33 (3~64) winsize 62
5598 12:22:49.291114 [CA 3] Center 33 (3~64) winsize 62
5599 12:22:49.294531 [CA 4] Center 34 (4~65) winsize 62
5600 12:22:49.297885 [CA 5] Center 33 (3~63) winsize 61
5601 12:22:49.298277
5602 12:22:49.301261 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5603 12:22:49.301739
5604 12:22:49.304395 [CATrainingPosCal] consider 2 rank data
5605 12:22:49.307732 u2DelayCellTimex100 = 270/100 ps
5606 12:22:49.311612 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5607 12:22:49.314438 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5608 12:22:49.321118 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5609 12:22:49.324559 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 12:22:49.327931 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5611 12:22:49.331459 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5612 12:22:49.331835
5613 12:22:49.334691 CA PerBit enable=1, Macro0, CA PI delay=33
5614 12:22:49.335143
5615 12:22:49.337888 [CBTSetCACLKResult] CA Dly = 33
5616 12:22:49.338320 CS Dly: 5 (0~38)
5617 12:22:49.338628
5618 12:22:49.341022 ----->DramcWriteLeveling(PI) begin...
5619 12:22:49.344610 ==
5620 12:22:49.345038 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 12:22:49.351729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 12:22:49.352108 ==
5623 12:22:49.354766 Write leveling (Byte 0): 24 => 24
5624 12:22:49.358245 Write leveling (Byte 1): 31 => 31
5625 12:22:49.361278 DramcWriteLeveling(PI) end<-----
5626 12:22:49.361693
5627 12:22:49.362041 ==
5628 12:22:49.364375 Dram Type= 6, Freq= 0, CH_1, rank 0
5629 12:22:49.367815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5630 12:22:49.368385 ==
5631 12:22:49.371636 [Gating] SW mode calibration
5632 12:22:49.378064 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5633 12:22:49.381020 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5634 12:22:49.387975 0 14 0 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
5635 12:22:49.391575 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 12:22:49.394505 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 12:22:49.401210 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 12:22:49.404794 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 12:22:49.408026 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 12:22:49.414570 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5641 12:22:49.418238 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5642 12:22:49.421886 0 15 0 | B1->B0 | 2525 2626 | 0 0 | (0 0) (1 1)
5643 12:22:49.428106 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 12:22:49.431572 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 12:22:49.434640 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 12:22:49.438447 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 12:22:49.445104 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 12:22:49.448785 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5649 12:22:49.451706 0 15 28 | B1->B0 | 2b2b 2d2d | 0 0 | (1 1) (0 0)
5650 12:22:49.458683 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
5651 12:22:49.462235 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 12:22:49.465004 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 12:22:49.471815 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 12:22:49.475224 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 12:22:49.478637 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 12:22:49.484847 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5657 12:22:49.488696 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5658 12:22:49.492009 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:22:49.498421 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 12:22:49.502045 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 12:22:49.505355 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 12:22:49.512151 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:22:49.514783 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 12:22:49.518372 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 12:22:49.525015 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 12:22:49.527860 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 12:22:49.531565 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 12:22:49.534661 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 12:22:49.540970 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:22:49.544351 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 12:22:49.547490 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 12:22:49.554298 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 12:22:49.557641 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5674 12:22:49.561366 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5675 12:22:49.567948 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5676 12:22:49.570997 Total UI for P1: 0, mck2ui 16
5677 12:22:49.574357 best dqsien dly found for B0: ( 1, 2, 30)
5678 12:22:49.574554 Total UI for P1: 0, mck2ui 16
5679 12:22:49.581056 best dqsien dly found for B1: ( 1, 2, 30)
5680 12:22:49.585068 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5681 12:22:49.587909 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5682 12:22:49.588449
5683 12:22:49.591447 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5684 12:22:49.594798 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5685 12:22:49.598304 [Gating] SW calibration Done
5686 12:22:49.598872 ==
5687 12:22:49.601448 Dram Type= 6, Freq= 0, CH_1, rank 0
5688 12:22:49.604501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5689 12:22:49.605011 ==
5690 12:22:49.607721 RX Vref Scan: 0
5691 12:22:49.608134
5692 12:22:49.608462 RX Vref 0 -> 0, step: 1
5693 12:22:49.608771
5694 12:22:49.611147 RX Delay -80 -> 252, step: 8
5695 12:22:49.614822 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5696 12:22:49.621341 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5697 12:22:49.624839 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5698 12:22:49.628380 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5699 12:22:49.631270 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5700 12:22:49.634915 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5701 12:22:49.638172 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5702 12:22:49.641425 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5703 12:22:49.648218 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5704 12:22:49.651228 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5705 12:22:49.654773 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5706 12:22:49.657970 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5707 12:22:49.661081 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5708 12:22:49.667925 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5709 12:22:49.671369 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5710 12:22:49.674825 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5711 12:22:49.675246 ==
5712 12:22:49.677961 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 12:22:49.681415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 12:22:49.681835 ==
5715 12:22:49.684635 DQS Delay:
5716 12:22:49.685052 DQS0 = 0, DQS1 = 0
5717 12:22:49.685439 DQM Delay:
5718 12:22:49.688321 DQM0 = 97, DQM1 = 88
5719 12:22:49.688735 DQ Delay:
5720 12:22:49.691858 DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95
5721 12:22:49.694823 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =95
5722 12:22:49.698279 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5723 12:22:49.701083 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5724 12:22:49.701434
5725 12:22:49.701768
5726 12:22:49.702071 ==
5727 12:22:49.704559 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 12:22:49.711345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 12:22:49.711824 ==
5730 12:22:49.712131
5731 12:22:49.712413
5732 12:22:49.712683 TX Vref Scan disable
5733 12:22:49.715231 == TX Byte 0 ==
5734 12:22:49.718526 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5735 12:22:49.721649 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5736 12:22:49.725351 == TX Byte 1 ==
5737 12:22:49.728474 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5738 12:22:49.732076 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5739 12:22:49.735238 ==
5740 12:22:49.738853 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 12:22:49.742092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 12:22:49.742575 ==
5743 12:22:49.742939
5744 12:22:49.743222
5745 12:22:49.745452 TX Vref Scan disable
5746 12:22:49.746034 == TX Byte 0 ==
5747 12:22:49.752421 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5748 12:22:49.755484 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5749 12:22:49.755995 == TX Byte 1 ==
5750 12:22:49.761780 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5751 12:22:49.765266 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5752 12:22:49.765821
5753 12:22:49.766290 [DATLAT]
5754 12:22:49.768675 Freq=933, CH1 RK0
5755 12:22:49.769283
5756 12:22:49.769772 DATLAT Default: 0xd
5757 12:22:49.772207 0, 0xFFFF, sum = 0
5758 12:22:49.772809 1, 0xFFFF, sum = 0
5759 12:22:49.775041 2, 0xFFFF, sum = 0
5760 12:22:49.775636 3, 0xFFFF, sum = 0
5761 12:22:49.778472 4, 0xFFFF, sum = 0
5762 12:22:49.778988 5, 0xFFFF, sum = 0
5763 12:22:49.781970 6, 0xFFFF, sum = 0
5764 12:22:49.782483 7, 0xFFFF, sum = 0
5765 12:22:49.785038 8, 0xFFFF, sum = 0
5766 12:22:49.785554 9, 0xFFFF, sum = 0
5767 12:22:49.788758 10, 0x0, sum = 1
5768 12:22:49.789174 11, 0x0, sum = 2
5769 12:22:49.791629 12, 0x0, sum = 3
5770 12:22:49.792019 13, 0x0, sum = 4
5771 12:22:49.795121 best_step = 11
5772 12:22:49.795504
5773 12:22:49.795808 ==
5774 12:22:49.798778 Dram Type= 6, Freq= 0, CH_1, rank 0
5775 12:22:49.801693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5776 12:22:49.802082 ==
5777 12:22:49.805138 RX Vref Scan: 1
5778 12:22:49.805518
5779 12:22:49.805820 RX Vref 0 -> 0, step: 1
5780 12:22:49.806109
5781 12:22:49.808688 RX Delay -69 -> 252, step: 4
5782 12:22:49.809074
5783 12:22:49.812392 Set Vref, RX VrefLevel [Byte0]: 57
5784 12:22:49.815193 [Byte1]: 53
5785 12:22:49.819432
5786 12:22:49.819924 Final RX Vref Byte 0 = 57 to rank0
5787 12:22:49.822896 Final RX Vref Byte 1 = 53 to rank0
5788 12:22:49.826615 Final RX Vref Byte 0 = 57 to rank1
5789 12:22:49.829027 Final RX Vref Byte 1 = 53 to rank1==
5790 12:22:49.832374 Dram Type= 6, Freq= 0, CH_1, rank 0
5791 12:22:49.839288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 12:22:49.839692 ==
5793 12:22:49.840007 DQS Delay:
5794 12:22:49.840296 DQS0 = 0, DQS1 = 0
5795 12:22:49.842444 DQM Delay:
5796 12:22:49.842873 DQM0 = 97, DQM1 = 90
5797 12:22:49.846076 DQ Delay:
5798 12:22:49.849549 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =98
5799 12:22:49.852414 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5800 12:22:49.852804 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =86
5801 12:22:49.859088 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5802 12:22:49.859475
5803 12:22:49.859779
5804 12:22:49.866150 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f4, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5805 12:22:49.869007 CH1 RK0: MR19=504, MR18=17F4
5806 12:22:49.876077 CH1_RK0: MR19=0x504, MR18=0x17F4, DQSOSC=414, MR23=63, INC=63, DEC=42
5807 12:22:49.876488
5808 12:22:49.879162 ----->DramcWriteLeveling(PI) begin...
5809 12:22:49.879541 ==
5810 12:22:49.882320 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 12:22:49.885547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 12:22:49.886081 ==
5813 12:22:49.889250 Write leveling (Byte 0): 28 => 28
5814 12:22:49.892442 Write leveling (Byte 1): 29 => 29
5815 12:22:49.895806 DramcWriteLeveling(PI) end<-----
5816 12:22:49.896357
5817 12:22:49.896843 ==
5818 12:22:49.898991 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 12:22:49.902587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 12:22:49.903050 ==
5821 12:22:49.905990 [Gating] SW mode calibration
5822 12:22:49.912780 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5823 12:22:49.919334 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5824 12:22:49.922937 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 12:22:49.925741 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 12:22:49.932419 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 12:22:49.935716 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 12:22:49.939001 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 12:22:49.945482 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 12:22:49.949214 0 14 24 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (1 0)
5831 12:22:49.952355 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5832 12:22:49.959154 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 12:22:49.962802 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 12:22:49.965689 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 12:22:49.972441 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 12:22:49.975526 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 12:22:49.979084 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5838 12:22:49.985556 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5839 12:22:49.989163 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
5840 12:22:49.992614 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 12:22:49.999206 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 12:22:50.002303 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 12:22:50.006057 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 12:22:50.009081 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 12:22:50.015807 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 12:22:50.019638 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5847 12:22:50.022811 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5848 12:22:50.029370 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 12:22:50.032711 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 12:22:50.036038 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 12:22:50.042514 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:22:50.046155 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 12:22:50.050263 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 12:22:50.055913 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 12:22:50.059608 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 12:22:50.063000 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 12:22:50.069327 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:22:50.072724 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 12:22:50.076138 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 12:22:50.080123 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 12:22:50.086439 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5862 12:22:50.089546 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5863 12:22:50.093094 Total UI for P1: 0, mck2ui 16
5864 12:22:50.096751 best dqsien dly found for B0: ( 1, 2, 20)
5865 12:22:50.099537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5866 12:22:50.106716 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 12:22:50.107167 Total UI for P1: 0, mck2ui 16
5868 12:22:50.113476 best dqsien dly found for B1: ( 1, 2, 26)
5869 12:22:50.116669 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5870 12:22:50.119842 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5871 12:22:50.120251
5872 12:22:50.123518 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5873 12:22:50.126653 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5874 12:22:50.129785 [Gating] SW calibration Done
5875 12:22:50.130200 ==
5876 12:22:50.132965 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 12:22:50.136399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 12:22:50.136814 ==
5879 12:22:50.140139 RX Vref Scan: 0
5880 12:22:50.140553
5881 12:22:50.140879 RX Vref 0 -> 0, step: 1
5882 12:22:50.141184
5883 12:22:50.143319 RX Delay -80 -> 252, step: 8
5884 12:22:50.146527 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5885 12:22:50.150363 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5886 12:22:50.156765 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5887 12:22:50.160289 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5888 12:22:50.163613 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5889 12:22:50.167048 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5890 12:22:50.170286 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5891 12:22:50.173756 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5892 12:22:50.180561 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5893 12:22:50.183812 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5894 12:22:50.186684 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5895 12:22:50.190319 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5896 12:22:50.194042 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5897 12:22:50.196848 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5898 12:22:50.203289 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5899 12:22:50.206823 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5900 12:22:50.207349 ==
5901 12:22:50.210393 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 12:22:50.213278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 12:22:50.213699 ==
5904 12:22:50.214031 DQS Delay:
5905 12:22:50.216497 DQS0 = 0, DQS1 = 0
5906 12:22:50.216915 DQM Delay:
5907 12:22:50.220218 DQM0 = 94, DQM1 = 88
5908 12:22:50.220634 DQ Delay:
5909 12:22:50.223246 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5910 12:22:50.226699 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5911 12:22:50.229940 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5912 12:22:50.233360 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5913 12:22:50.233780
5914 12:22:50.234113
5915 12:22:50.234422 ==
5916 12:22:50.237382 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 12:22:50.240652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 12:22:50.243797 ==
5919 12:22:50.244221
5920 12:22:50.244553
5921 12:22:50.244860 TX Vref Scan disable
5922 12:22:50.246966 == TX Byte 0 ==
5923 12:22:50.250155 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5924 12:22:50.253368 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5925 12:22:50.256892 == TX Byte 1 ==
5926 12:22:50.260141 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5927 12:22:50.263982 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5928 12:22:50.266838 ==
5929 12:22:50.267262 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 12:22:50.273531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 12:22:50.274048 ==
5932 12:22:50.274386
5933 12:22:50.274961
5934 12:22:50.276637 TX Vref Scan disable
5935 12:22:50.277053 == TX Byte 0 ==
5936 12:22:50.283825 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5937 12:22:50.286510 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5938 12:22:50.287021 == TX Byte 1 ==
5939 12:22:50.293111 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5940 12:22:50.297138 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5941 12:22:50.297670
5942 12:22:50.298004 [DATLAT]
5943 12:22:50.299862 Freq=933, CH1 RK1
5944 12:22:50.300286
5945 12:22:50.300620 DATLAT Default: 0xb
5946 12:22:50.303350 0, 0xFFFF, sum = 0
5947 12:22:50.303779 1, 0xFFFF, sum = 0
5948 12:22:50.306445 2, 0xFFFF, sum = 0
5949 12:22:50.306903 3, 0xFFFF, sum = 0
5950 12:22:50.310348 4, 0xFFFF, sum = 0
5951 12:22:50.310917 5, 0xFFFF, sum = 0
5952 12:22:50.313614 6, 0xFFFF, sum = 0
5953 12:22:50.314137 7, 0xFFFF, sum = 0
5954 12:22:50.316511 8, 0xFFFF, sum = 0
5955 12:22:50.316939 9, 0xFFFF, sum = 0
5956 12:22:50.320054 10, 0x0, sum = 1
5957 12:22:50.320573 11, 0x0, sum = 2
5958 12:22:50.323332 12, 0x0, sum = 3
5959 12:22:50.323849 13, 0x0, sum = 4
5960 12:22:50.326615 best_step = 11
5961 12:22:50.327175
5962 12:22:50.327513 ==
5963 12:22:50.330030 Dram Type= 6, Freq= 0, CH_1, rank 1
5964 12:22:50.333306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5965 12:22:50.333823 ==
5966 12:22:50.336972 RX Vref Scan: 0
5967 12:22:50.337487
5968 12:22:50.337820 RX Vref 0 -> 0, step: 1
5969 12:22:50.338134
5970 12:22:50.340011 RX Delay -61 -> 252, step: 4
5971 12:22:50.347133 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5972 12:22:50.350855 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5973 12:22:50.353968 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5974 12:22:50.356980 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5975 12:22:50.360454 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5976 12:22:50.363662 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5977 12:22:50.370441 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5978 12:22:50.373991 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5979 12:22:50.377081 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5980 12:22:50.380466 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5981 12:22:50.384056 iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192
5982 12:22:50.390182 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5983 12:22:50.393732 iDelay=199, Bit 12, Center 96 (7 ~ 186) 180
5984 12:22:50.396851 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5985 12:22:50.400043 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5986 12:22:50.403395 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5987 12:22:50.403819 ==
5988 12:22:50.407091 Dram Type= 6, Freq= 0, CH_1, rank 1
5989 12:22:50.410692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5990 12:22:50.414140 ==
5991 12:22:50.414557 DQS Delay:
5992 12:22:50.414976 DQS0 = 0, DQS1 = 0
5993 12:22:50.416979 DQM Delay:
5994 12:22:50.417398 DQM0 = 94, DQM1 = 90
5995 12:22:50.420582 DQ Delay:
5996 12:22:50.423923 DQ0 =98, DQ1 =88, DQ2 =86, DQ3 =92
5997 12:22:50.424451 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =90
5998 12:22:50.427193 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =82
5999 12:22:50.433727 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
6000 12:22:50.434258
6001 12:22:50.434651
6002 12:22:50.440477 [DQSOSCAuto] RK1, (LSB)MR18= 0x111a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
6003 12:22:50.443733 CH1 RK1: MR19=505, MR18=111A
6004 12:22:50.450509 CH1_RK1: MR19=0x505, MR18=0x111A, DQSOSC=413, MR23=63, INC=63, DEC=42
6005 12:22:50.454271 [RxdqsGatingPostProcess] freq 933
6006 12:22:50.456796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6007 12:22:50.460497 best DQS0 dly(2T, 0.5T) = (0, 10)
6008 12:22:50.463870 best DQS1 dly(2T, 0.5T) = (0, 10)
6009 12:22:50.467154 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6010 12:22:50.470404 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6011 12:22:50.474004 best DQS0 dly(2T, 0.5T) = (0, 10)
6012 12:22:50.477084 best DQS1 dly(2T, 0.5T) = (0, 10)
6013 12:22:50.480707 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6014 12:22:50.483972 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6015 12:22:50.487312 Pre-setting of DQS Precalculation
6016 12:22:50.490705 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6017 12:22:50.497461 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6018 12:22:50.503995 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6019 12:22:50.507267
6020 12:22:50.507684
6021 12:22:50.508012 [Calibration Summary] 1866 Mbps
6022 12:22:50.510413 CH 0, Rank 0
6023 12:22:50.510875 SW Impedance : PASS
6024 12:22:50.513922 DUTY Scan : NO K
6025 12:22:50.517092 ZQ Calibration : PASS
6026 12:22:50.517510 Jitter Meter : NO K
6027 12:22:50.520992 CBT Training : PASS
6028 12:22:50.524164 Write leveling : PASS
6029 12:22:50.524672 RX DQS gating : PASS
6030 12:22:50.527125 RX DQ/DQS(RDDQC) : PASS
6031 12:22:50.530700 TX DQ/DQS : PASS
6032 12:22:50.531282 RX DATLAT : PASS
6033 12:22:50.534593 RX DQ/DQS(Engine): PASS
6034 12:22:50.537322 TX OE : NO K
6035 12:22:50.537838 All Pass.
6036 12:22:50.538172
6037 12:22:50.538484 CH 0, Rank 1
6038 12:22:50.540584 SW Impedance : PASS
6039 12:22:50.541003 DUTY Scan : NO K
6040 12:22:50.543922 ZQ Calibration : PASS
6041 12:22:50.547434 Jitter Meter : NO K
6042 12:22:50.547854 CBT Training : PASS
6043 12:22:50.550353 Write leveling : PASS
6044 12:22:50.554064 RX DQS gating : PASS
6045 12:22:50.554577 RX DQ/DQS(RDDQC) : PASS
6046 12:22:50.557531 TX DQ/DQS : PASS
6047 12:22:50.561146 RX DATLAT : PASS
6048 12:22:50.561663 RX DQ/DQS(Engine): PASS
6049 12:22:50.564065 TX OE : NO K
6050 12:22:50.564486 All Pass.
6051 12:22:50.564816
6052 12:22:50.566850 CH 1, Rank 0
6053 12:22:50.567399 SW Impedance : PASS
6054 12:22:50.570847 DUTY Scan : NO K
6055 12:22:50.574016 ZQ Calibration : PASS
6056 12:22:50.574555 Jitter Meter : NO K
6057 12:22:50.577622 CBT Training : PASS
6058 12:22:50.580697 Write leveling : PASS
6059 12:22:50.581155 RX DQS gating : PASS
6060 12:22:50.583851 RX DQ/DQS(RDDQC) : PASS
6061 12:22:50.584307 TX DQ/DQS : PASS
6062 12:22:50.587147 RX DATLAT : PASS
6063 12:22:50.590542 RX DQ/DQS(Engine): PASS
6064 12:22:50.591031 TX OE : NO K
6065 12:22:50.593797 All Pass.
6066 12:22:50.594215
6067 12:22:50.594554 CH 1, Rank 1
6068 12:22:50.597604 SW Impedance : PASS
6069 12:22:50.598024 DUTY Scan : NO K
6070 12:22:50.600393 ZQ Calibration : PASS
6071 12:22:50.604150 Jitter Meter : NO K
6072 12:22:50.604645 CBT Training : PASS
6073 12:22:50.607085 Write leveling : PASS
6074 12:22:50.611012 RX DQS gating : PASS
6075 12:22:50.611577 RX DQ/DQS(RDDQC) : PASS
6076 12:22:50.614092 TX DQ/DQS : PASS
6077 12:22:50.617509 RX DATLAT : PASS
6078 12:22:50.617929 RX DQ/DQS(Engine): PASS
6079 12:22:50.620593 TX OE : NO K
6080 12:22:50.621018 All Pass.
6081 12:22:50.621356
6082 12:22:50.623986 DramC Write-DBI off
6083 12:22:50.627167 PER_BANK_REFRESH: Hybrid Mode
6084 12:22:50.627587 TX_TRACKING: ON
6085 12:22:50.637382 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6086 12:22:50.640835 [FAST_K] Save calibration result to emmc
6087 12:22:50.644588 dramc_set_vcore_voltage set vcore to 650000
6088 12:22:50.647318 Read voltage for 400, 6
6089 12:22:50.647739 Vio18 = 0
6090 12:22:50.648075 Vcore = 650000
6091 12:22:50.650686 Vdram = 0
6092 12:22:50.651154 Vddq = 0
6093 12:22:50.651583 Vmddr = 0
6094 12:22:50.657255 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6095 12:22:50.660504 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6096 12:22:50.664458 MEM_TYPE=3, freq_sel=20
6097 12:22:50.667540 sv_algorithm_assistance_LP4_800
6098 12:22:50.671002 ============ PULL DRAM RESETB DOWN ============
6099 12:22:50.674387 ========== PULL DRAM RESETB DOWN end =========
6100 12:22:50.680764 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6101 12:22:50.684140 ===================================
6102 12:22:50.684557 LPDDR4 DRAM CONFIGURATION
6103 12:22:50.687446 ===================================
6104 12:22:50.690834 EX_ROW_EN[0] = 0x0
6105 12:22:50.691254 EX_ROW_EN[1] = 0x0
6106 12:22:50.694317 LP4Y_EN = 0x0
6107 12:22:50.694782 WORK_FSP = 0x0
6108 12:22:50.697840 WL = 0x2
6109 12:22:50.698303 RL = 0x2
6110 12:22:50.700836 BL = 0x2
6111 12:22:50.701337 RPST = 0x0
6112 12:22:50.704150 RD_PRE = 0x0
6113 12:22:50.704660 WR_PRE = 0x1
6114 12:22:50.707401 WR_PST = 0x0
6115 12:22:50.710907 DBI_WR = 0x0
6116 12:22:50.711444 DBI_RD = 0x0
6117 12:22:50.714356 OTF = 0x1
6118 12:22:50.717507 ===================================
6119 12:22:50.721001 ===================================
6120 12:22:50.721368 ANA top config
6121 12:22:50.724247 ===================================
6122 12:22:50.732888 DLL_ASYNC_EN = 0
6123 12:22:50.733315 ALL_SLAVE_EN = 1
6124 12:22:50.733652 NEW_RANK_MODE = 1
6125 12:22:50.734448 DLL_IDLE_MODE = 1
6126 12:22:50.737855 LP45_APHY_COMB_EN = 1
6127 12:22:50.741587 TX_ODT_DIS = 1
6128 12:22:50.742007 NEW_8X_MODE = 1
6129 12:22:50.744859 ===================================
6130 12:22:50.748285 ===================================
6131 12:22:50.751231 data_rate = 800
6132 12:22:50.754267 CKR = 1
6133 12:22:50.758081 DQ_P2S_RATIO = 4
6134 12:22:50.761458 ===================================
6135 12:22:50.764347 CA_P2S_RATIO = 4
6136 12:22:50.764764 DQ_CA_OPEN = 0
6137 12:22:50.767952 DQ_SEMI_OPEN = 1
6138 12:22:50.771445 CA_SEMI_OPEN = 1
6139 12:22:50.774318 CA_FULL_RATE = 0
6140 12:22:50.777708 DQ_CKDIV4_EN = 0
6141 12:22:50.780907 CA_CKDIV4_EN = 1
6142 12:22:50.781426 CA_PREDIV_EN = 0
6143 12:22:50.784377 PH8_DLY = 0
6144 12:22:50.787559 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6145 12:22:50.790858 DQ_AAMCK_DIV = 0
6146 12:22:50.794220 CA_AAMCK_DIV = 0
6147 12:22:50.797608 CA_ADMCK_DIV = 4
6148 12:22:50.798025 DQ_TRACK_CA_EN = 0
6149 12:22:50.801058 CA_PICK = 800
6150 12:22:50.804367 CA_MCKIO = 400
6151 12:22:50.807635 MCKIO_SEMI = 400
6152 12:22:50.811261 PLL_FREQ = 3016
6153 12:22:50.814340 DQ_UI_PI_RATIO = 32
6154 12:22:50.818098 CA_UI_PI_RATIO = 32
6155 12:22:50.821113 ===================================
6156 12:22:50.824733 ===================================
6157 12:22:50.825156 memory_type:LPDDR4
6158 12:22:50.827925 GP_NUM : 10
6159 12:22:50.830914 SRAM_EN : 1
6160 12:22:50.831333 MD32_EN : 0
6161 12:22:50.834545 ===================================
6162 12:22:50.837865 [ANA_INIT] >>>>>>>>>>>>>>
6163 12:22:50.840960 <<<<<< [CONFIGURE PHASE]: ANA_TX
6164 12:22:50.844206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6165 12:22:50.847721 ===================================
6166 12:22:50.851259 data_rate = 800,PCW = 0X7400
6167 12:22:50.854389 ===================================
6168 12:22:50.857634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6169 12:22:50.861071 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6170 12:22:50.874120 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 12:22:50.877215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6172 12:22:50.880620 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6173 12:22:50.883817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6174 12:22:50.887384 [ANA_INIT] flow start
6175 12:22:50.887485 [ANA_INIT] PLL >>>>>>>>
6176 12:22:50.890714 [ANA_INIT] PLL <<<<<<<<
6177 12:22:50.894225 [ANA_INIT] MIDPI >>>>>>>>
6178 12:22:50.897023 [ANA_INIT] MIDPI <<<<<<<<
6179 12:22:50.897105 [ANA_INIT] DLL >>>>>>>>
6180 12:22:50.901121 [ANA_INIT] flow end
6181 12:22:50.903839 ============ LP4 DIFF to SE enter ============
6182 12:22:50.907236 ============ LP4 DIFF to SE exit ============
6183 12:22:50.911024 [ANA_INIT] <<<<<<<<<<<<<
6184 12:22:50.913772 [Flow] Enable top DCM control >>>>>
6185 12:22:50.917449 [Flow] Enable top DCM control <<<<<
6186 12:22:50.920797 Enable DLL master slave shuffle
6187 12:22:50.924295 ==============================================================
6188 12:22:50.927873 Gating Mode config
6189 12:22:50.934032 ==============================================================
6190 12:22:50.934124 Config description:
6191 12:22:50.944017 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6192 12:22:50.950988 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6193 12:22:50.954305 SELPH_MODE 0: By rank 1: By Phase
6194 12:22:50.960752 ==============================================================
6195 12:22:50.964302 GAT_TRACK_EN = 0
6196 12:22:50.967512 RX_GATING_MODE = 2
6197 12:22:50.970908 RX_GATING_TRACK_MODE = 2
6198 12:22:50.973950 SELPH_MODE = 1
6199 12:22:50.977610 PICG_EARLY_EN = 1
6200 12:22:50.980585 VALID_LAT_VALUE = 1
6201 12:22:50.984057 ==============================================================
6202 12:22:50.987711 Enter into Gating configuration >>>>
6203 12:22:50.990691 Exit from Gating configuration <<<<
6204 12:22:50.994410 Enter into DVFS_PRE_config >>>>>
6205 12:22:51.004008 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6206 12:22:51.007668 Exit from DVFS_PRE_config <<<<<
6207 12:22:51.010923 Enter into PICG configuration >>>>
6208 12:22:51.014341 Exit from PICG configuration <<<<
6209 12:22:51.017646 [RX_INPUT] configuration >>>>>
6210 12:22:51.020943 [RX_INPUT] configuration <<<<<
6211 12:22:51.024587 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6212 12:22:51.030931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6213 12:22:51.037988 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6214 12:22:51.044376 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6215 12:22:51.051438 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 12:22:51.054605 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 12:22:51.061175 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6218 12:22:51.064506 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6219 12:22:51.067929 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6220 12:22:51.071537 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6221 12:22:51.074864 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6222 12:22:51.081142 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 12:22:51.084792 ===================================
6224 12:22:51.088146 LPDDR4 DRAM CONFIGURATION
6225 12:22:51.091609 ===================================
6226 12:22:51.091830 EX_ROW_EN[0] = 0x0
6227 12:22:51.094961 EX_ROW_EN[1] = 0x0
6228 12:22:51.095214 LP4Y_EN = 0x0
6229 12:22:51.098796 WORK_FSP = 0x0
6230 12:22:51.099121 WL = 0x2
6231 12:22:51.101687 RL = 0x2
6232 12:22:51.102007 BL = 0x2
6233 12:22:51.104847 RPST = 0x0
6234 12:22:51.105262 RD_PRE = 0x0
6235 12:22:51.108024 WR_PRE = 0x1
6236 12:22:51.108608 WR_PST = 0x0
6237 12:22:51.111263 DBI_WR = 0x0
6238 12:22:51.111690 DBI_RD = 0x0
6239 12:22:51.114582 OTF = 0x1
6240 12:22:51.118539 ===================================
6241 12:22:51.121550 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6242 12:22:51.124636 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6243 12:22:51.131415 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6244 12:22:51.134890 ===================================
6245 12:22:51.135303 LPDDR4 DRAM CONFIGURATION
6246 12:22:51.138491 ===================================
6247 12:22:51.141959 EX_ROW_EN[0] = 0x10
6248 12:22:51.144620 EX_ROW_EN[1] = 0x0
6249 12:22:51.145060 LP4Y_EN = 0x0
6250 12:22:51.148154 WORK_FSP = 0x0
6251 12:22:51.148569 WL = 0x2
6252 12:22:51.151563 RL = 0x2
6253 12:22:51.151988 BL = 0x2
6254 12:22:51.154764 RPST = 0x0
6255 12:22:51.155183 RD_PRE = 0x0
6256 12:22:51.158672 WR_PRE = 0x1
6257 12:22:51.159118 WR_PST = 0x0
6258 12:22:51.161494 DBI_WR = 0x0
6259 12:22:51.161904 DBI_RD = 0x0
6260 12:22:51.164924 OTF = 0x1
6261 12:22:51.168246 ===================================
6262 12:22:51.174977 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6263 12:22:51.178441 nWR fixed to 30
6264 12:22:51.178905 [ModeRegInit_LP4] CH0 RK0
6265 12:22:51.181497 [ModeRegInit_LP4] CH0 RK1
6266 12:22:51.184946 [ModeRegInit_LP4] CH1 RK0
6267 12:22:51.188146 [ModeRegInit_LP4] CH1 RK1
6268 12:22:51.188557 match AC timing 19
6269 12:22:51.194738 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6270 12:22:51.198119 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6271 12:22:51.201764 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6272 12:22:51.208507 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6273 12:22:51.211794 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6274 12:22:51.212230 ==
6275 12:22:51.214549 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 12:22:51.218157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 12:22:51.218704 ==
6278 12:22:51.224787 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6279 12:22:51.231704 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6280 12:22:51.232217 [CA 0] Center 36 (8~64) winsize 57
6281 12:22:51.235005 [CA 1] Center 36 (8~64) winsize 57
6282 12:22:51.238083 [CA 2] Center 36 (8~64) winsize 57
6283 12:22:51.241685 [CA 3] Center 36 (8~64) winsize 57
6284 12:22:51.245248 [CA 4] Center 36 (8~64) winsize 57
6285 12:22:51.248723 [CA 5] Center 36 (8~64) winsize 57
6286 12:22:51.249253
6287 12:22:51.251697 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6288 12:22:51.252114
6289 12:22:51.254904 [CATrainingPosCal] consider 1 rank data
6290 12:22:51.258223 u2DelayCellTimex100 = 270/100 ps
6291 12:22:51.261269 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 12:22:51.265126 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 12:22:51.271375 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 12:22:51.274804 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 12:22:51.278304 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 12:22:51.281678 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 12:22:51.282123
6298 12:22:51.284573 CA PerBit enable=1, Macro0, CA PI delay=36
6299 12:22:51.284998
6300 12:22:51.288242 [CBTSetCACLKResult] CA Dly = 36
6301 12:22:51.288752 CS Dly: 1 (0~32)
6302 12:22:51.289086 ==
6303 12:22:51.291296 Dram Type= 6, Freq= 0, CH_0, rank 1
6304 12:22:51.298061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 12:22:51.298856 ==
6306 12:22:51.301187 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6307 12:22:51.308386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6308 12:22:51.311388 [CA 0] Center 36 (8~64) winsize 57
6309 12:22:51.314803 [CA 1] Center 36 (8~64) winsize 57
6310 12:22:51.318638 [CA 2] Center 36 (8~64) winsize 57
6311 12:22:51.321756 [CA 3] Center 36 (8~64) winsize 57
6312 12:22:51.324845 [CA 4] Center 36 (8~64) winsize 57
6313 12:22:51.328172 [CA 5] Center 36 (8~64) winsize 57
6314 12:22:51.328601
6315 12:22:51.331530 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6316 12:22:51.332148
6317 12:22:51.334957 [CATrainingPosCal] consider 2 rank data
6318 12:22:51.338449 u2DelayCellTimex100 = 270/100 ps
6319 12:22:51.341710 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 12:22:51.345072 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 12:22:51.348681 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 12:22:51.351431 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 12:22:51.354908 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 12:22:51.358273 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 12:22:51.358743
6326 12:22:51.364750 CA PerBit enable=1, Macro0, CA PI delay=36
6327 12:22:51.365432
6328 12:22:51.366029 [CBTSetCACLKResult] CA Dly = 36
6329 12:22:51.368318 CS Dly: 1 (0~32)
6330 12:22:51.368907
6331 12:22:51.371580 ----->DramcWriteLeveling(PI) begin...
6332 12:22:51.372003 ==
6333 12:22:51.375008 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 12:22:51.378542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 12:22:51.378998 ==
6336 12:22:51.381734 Write leveling (Byte 0): 40 => 8
6337 12:22:51.385459 Write leveling (Byte 1): 32 => 0
6338 12:22:51.388263 DramcWriteLeveling(PI) end<-----
6339 12:22:51.388835
6340 12:22:51.389180 ==
6341 12:22:51.391887 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 12:22:51.395526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 12:22:51.395948 ==
6344 12:22:51.398561 [Gating] SW mode calibration
6345 12:22:51.405348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6346 12:22:51.412054 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6347 12:22:51.415455 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6348 12:22:51.422113 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 12:22:51.425488 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 12:22:51.429031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 12:22:51.432478 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 12:22:51.438345 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 12:22:51.442088 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 12:22:51.445121 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 12:22:51.452175 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6356 12:22:51.452693 Total UI for P1: 0, mck2ui 16
6357 12:22:51.458842 best dqsien dly found for B0: ( 0, 14, 24)
6358 12:22:51.459372 Total UI for P1: 0, mck2ui 16
6359 12:22:51.465334 best dqsien dly found for B1: ( 0, 14, 24)
6360 12:22:51.468633 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6361 12:22:51.471858 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6362 12:22:51.472269
6363 12:22:51.475205 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6364 12:22:51.478755 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 12:22:51.481980 [Gating] SW calibration Done
6366 12:22:51.482388 ==
6367 12:22:51.485509 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 12:22:51.488802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 12:22:51.489217 ==
6370 12:22:51.492187 RX Vref Scan: 0
6371 12:22:51.492596
6372 12:22:51.493043 RX Vref 0 -> 0, step: 1
6373 12:22:51.493371
6374 12:22:51.495284 RX Delay -410 -> 252, step: 16
6375 12:22:51.502134 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6376 12:22:51.505034 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6377 12:22:51.509058 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6378 12:22:51.512150 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6379 12:22:51.518589 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6380 12:22:51.521898 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6381 12:22:51.525385 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6382 12:22:51.528387 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6383 12:22:51.535243 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6384 12:22:51.538853 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6385 12:22:51.542543 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6386 12:22:51.545625 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6387 12:22:51.552043 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6388 12:22:51.555529 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6389 12:22:51.558784 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6390 12:22:51.561870 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6391 12:22:51.562295 ==
6392 12:22:51.565398 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 12:22:51.571810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 12:22:51.572226 ==
6395 12:22:51.572554 DQS Delay:
6396 12:22:51.575552 DQS0 = 35, DQS1 = 51
6397 12:22:51.576002 DQM Delay:
6398 12:22:51.576330 DQM0 = 7, DQM1 = 11
6399 12:22:51.578484 DQ Delay:
6400 12:22:51.582294 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6401 12:22:51.582701 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6402 12:22:51.585842 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6403 12:22:51.589236 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6404 12:22:51.589648
6405 12:22:51.589974
6406 12:22:51.592217 ==
6407 12:22:51.595876 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 12:22:51.599065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 12:22:51.599483 ==
6410 12:22:51.599811
6411 12:22:51.600113
6412 12:22:51.601905 TX Vref Scan disable
6413 12:22:51.602315 == TX Byte 0 ==
6414 12:22:51.605206 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 12:22:51.612247 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 12:22:51.612821 == TX Byte 1 ==
6417 12:22:51.615378 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6418 12:22:51.621940 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6419 12:22:51.622482 ==
6420 12:22:51.625434 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 12:22:51.628665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 12:22:51.629087 ==
6423 12:22:51.629472
6424 12:22:51.629779
6425 12:22:51.632135 TX Vref Scan disable
6426 12:22:51.632614 == TX Byte 0 ==
6427 12:22:51.635337 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 12:22:51.642186 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 12:22:51.642502 == TX Byte 1 ==
6430 12:22:51.645484 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6431 12:22:51.651844 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6432 12:22:51.652140
6433 12:22:51.652373 [DATLAT]
6434 12:22:51.652590 Freq=400, CH0 RK0
6435 12:22:51.655585
6436 12:22:51.655876 DATLAT Default: 0xf
6437 12:22:51.659013 0, 0xFFFF, sum = 0
6438 12:22:51.659312 1, 0xFFFF, sum = 0
6439 12:22:51.662164 2, 0xFFFF, sum = 0
6440 12:22:51.662507 3, 0xFFFF, sum = 0
6441 12:22:51.664995 4, 0xFFFF, sum = 0
6442 12:22:51.665292 5, 0xFFFF, sum = 0
6443 12:22:51.668366 6, 0xFFFF, sum = 0
6444 12:22:51.668769 7, 0xFFFF, sum = 0
6445 12:22:51.671764 8, 0xFFFF, sum = 0
6446 12:22:51.672062 9, 0xFFFF, sum = 0
6447 12:22:51.675517 10, 0xFFFF, sum = 0
6448 12:22:51.675815 11, 0xFFFF, sum = 0
6449 12:22:51.678383 12, 0xFFFF, sum = 0
6450 12:22:51.678681 13, 0x0, sum = 1
6451 12:22:51.681813 14, 0x0, sum = 2
6452 12:22:51.682147 15, 0x0, sum = 3
6453 12:22:51.685551 16, 0x0, sum = 4
6454 12:22:51.685885 best_step = 14
6455 12:22:51.686140
6456 12:22:51.686360 ==
6457 12:22:51.688763 Dram Type= 6, Freq= 0, CH_0, rank 0
6458 12:22:51.692228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6459 12:22:51.695535 ==
6460 12:22:51.695979 RX Vref Scan: 1
6461 12:22:51.696263
6462 12:22:51.698853 RX Vref 0 -> 0, step: 1
6463 12:22:51.699148
6464 12:22:51.702336 RX Delay -343 -> 252, step: 8
6465 12:22:51.702631
6466 12:22:51.702913 Set Vref, RX VrefLevel [Byte0]: 54
6467 12:22:51.705472 [Byte1]: 50
6468 12:22:51.711459
6469 12:22:51.711754 Final RX Vref Byte 0 = 54 to rank0
6470 12:22:51.714541 Final RX Vref Byte 1 = 50 to rank0
6471 12:22:51.717542 Final RX Vref Byte 0 = 54 to rank1
6472 12:22:51.721212 Final RX Vref Byte 1 = 50 to rank1==
6473 12:22:51.724553 Dram Type= 6, Freq= 0, CH_0, rank 0
6474 12:22:51.730938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6475 12:22:51.731256 ==
6476 12:22:51.731605 DQS Delay:
6477 12:22:51.734372 DQS0 = 44, DQS1 = 60
6478 12:22:51.734832 DQM Delay:
6479 12:22:51.735190 DQM0 = 11, DQM1 = 15
6480 12:22:51.737996 DQ Delay:
6481 12:22:51.741585 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6482 12:22:51.741880 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6483 12:22:51.744649 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6484 12:22:51.747964 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6485 12:22:51.748269
6486 12:22:51.748526
6487 12:22:51.757953 [DQSOSCAuto] RK0, (LSB)MR18= 0x8855, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
6488 12:22:51.761592 CH0 RK0: MR19=C0C, MR18=8855
6489 12:22:51.767976 CH0_RK0: MR19=0xC0C, MR18=0x8855, DQSOSC=392, MR23=63, INC=384, DEC=256
6490 12:22:51.768373 ==
6491 12:22:51.771479 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 12:22:51.774711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 12:22:51.775066 ==
6494 12:22:51.777908 [Gating] SW mode calibration
6495 12:22:51.784674 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6496 12:22:51.788306 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6497 12:22:51.794568 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6498 12:22:51.798147 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 12:22:51.801712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 12:22:51.808045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 12:22:51.812024 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 12:22:51.814942 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 12:22:51.821473 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 12:22:51.824536 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 12:22:51.827845 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6506 12:22:51.830983 Total UI for P1: 0, mck2ui 16
6507 12:22:51.834596 best dqsien dly found for B0: ( 0, 14, 24)
6508 12:22:51.837651 Total UI for P1: 0, mck2ui 16
6509 12:22:51.841032 best dqsien dly found for B1: ( 0, 14, 24)
6510 12:22:51.844741 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6511 12:22:51.847640 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6512 12:22:51.847722
6513 12:22:51.851037 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6514 12:22:51.857982 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 12:22:51.858064 [Gating] SW calibration Done
6516 12:22:51.858127 ==
6517 12:22:51.861451 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 12:22:51.867704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 12:22:51.867785 ==
6520 12:22:51.867849 RX Vref Scan: 0
6521 12:22:51.867909
6522 12:22:51.871267 RX Vref 0 -> 0, step: 1
6523 12:22:51.871372
6524 12:22:51.874643 RX Delay -410 -> 252, step: 16
6525 12:22:51.877690 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6526 12:22:51.880955 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6527 12:22:51.888022 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6528 12:22:51.890986 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6529 12:22:51.894703 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6530 12:22:51.898071 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6531 12:22:51.904818 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6532 12:22:51.907898 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6533 12:22:51.910997 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6534 12:22:51.914387 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6535 12:22:51.921775 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6536 12:22:51.925009 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6537 12:22:51.927878 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6538 12:22:51.931667 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6539 12:22:51.938451 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6540 12:22:51.941811 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6541 12:22:51.942228 ==
6542 12:22:51.945555 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 12:22:51.948936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 12:22:51.949491 ==
6545 12:22:51.952015 DQS Delay:
6546 12:22:51.952430 DQS0 = 51, DQS1 = 51
6547 12:22:51.952758 DQM Delay:
6548 12:22:51.955310 DQM0 = 18, DQM1 = 9
6549 12:22:51.955720 DQ Delay:
6550 12:22:51.958555 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6551 12:22:51.961654 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6552 12:22:51.964937 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6553 12:22:51.968468 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6554 12:22:51.968883
6555 12:22:51.969285
6556 12:22:51.969606 ==
6557 12:22:51.971887 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 12:22:51.975690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 12:22:51.976214 ==
6560 12:22:51.979292
6561 12:22:51.979809
6562 12:22:51.980142 TX Vref Scan disable
6563 12:22:51.981667 == TX Byte 0 ==
6564 12:22:51.985440 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6565 12:22:51.988523 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6566 12:22:51.991904 == TX Byte 1 ==
6567 12:22:51.995359 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6568 12:22:51.998549 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6569 12:22:51.999007 ==
6570 12:22:52.002154 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 12:22:52.005285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 12:22:52.008448 ==
6573 12:22:52.008865
6574 12:22:52.009191
6575 12:22:52.009515 TX Vref Scan disable
6576 12:22:52.011884 == TX Byte 0 ==
6577 12:22:52.015187 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6578 12:22:52.018346 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6579 12:22:52.021758 == TX Byte 1 ==
6580 12:22:52.025376 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6581 12:22:52.028142 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6582 12:22:52.028559
6583 12:22:52.028891 [DATLAT]
6584 12:22:52.031890 Freq=400, CH0 RK1
6585 12:22:52.032310
6586 12:22:52.035188 DATLAT Default: 0xe
6587 12:22:52.035605 0, 0xFFFF, sum = 0
6588 12:22:52.038453 1, 0xFFFF, sum = 0
6589 12:22:52.038916 2, 0xFFFF, sum = 0
6590 12:22:52.041554 3, 0xFFFF, sum = 0
6591 12:22:52.041978 4, 0xFFFF, sum = 0
6592 12:22:52.045080 5, 0xFFFF, sum = 0
6593 12:22:52.045505 6, 0xFFFF, sum = 0
6594 12:22:52.048687 7, 0xFFFF, sum = 0
6595 12:22:52.049110 8, 0xFFFF, sum = 0
6596 12:22:52.051883 9, 0xFFFF, sum = 0
6597 12:22:52.052308 10, 0xFFFF, sum = 0
6598 12:22:52.055229 11, 0xFFFF, sum = 0
6599 12:22:52.055649 12, 0xFFFF, sum = 0
6600 12:22:52.058504 13, 0x0, sum = 1
6601 12:22:52.058979 14, 0x0, sum = 2
6602 12:22:52.061564 15, 0x0, sum = 3
6603 12:22:52.061864 16, 0x0, sum = 4
6604 12:22:52.065057 best_step = 14
6605 12:22:52.065304
6606 12:22:52.065486 ==
6607 12:22:52.068559 Dram Type= 6, Freq= 0, CH_0, rank 1
6608 12:22:52.071740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6609 12:22:52.071950 ==
6610 12:22:52.072096 RX Vref Scan: 0
6611 12:22:52.072230
6612 12:22:52.075197 RX Vref 0 -> 0, step: 1
6613 12:22:52.075369
6614 12:22:52.078337 RX Delay -343 -> 252, step: 8
6615 12:22:52.085490 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6616 12:22:52.088964 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6617 12:22:52.092334 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6618 12:22:52.095865 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6619 12:22:52.102422 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6620 12:22:52.105237 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6621 12:22:52.108661 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6622 12:22:52.112060 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6623 12:22:52.118565 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6624 12:22:52.122279 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6625 12:22:52.125858 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6626 12:22:52.128906 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6627 12:22:52.136025 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6628 12:22:52.139285 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6629 12:22:52.142798 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6630 12:22:52.146067 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6631 12:22:52.149318 ==
6632 12:22:52.152739 Dram Type= 6, Freq= 0, CH_0, rank 1
6633 12:22:52.155720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 12:22:52.156139 ==
6635 12:22:52.156470 DQS Delay:
6636 12:22:52.159372 DQS0 = 48, DQS1 = 60
6637 12:22:52.159787 DQM Delay:
6638 12:22:52.162915 DQM0 = 13, DQM1 = 13
6639 12:22:52.163329 DQ Delay:
6640 12:22:52.165830 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6641 12:22:52.169477 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6642 12:22:52.172709 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6643 12:22:52.175858 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24
6644 12:22:52.176295
6645 12:22:52.176628
6646 12:22:52.182753 [DQSOSCAuto] RK1, (LSB)MR18= 0x9768, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6647 12:22:52.185942 CH0 RK1: MR19=C0C, MR18=9768
6648 12:22:52.192440 CH0_RK1: MR19=0xC0C, MR18=0x9768, DQSOSC=390, MR23=63, INC=388, DEC=258
6649 12:22:52.195859 [RxdqsGatingPostProcess] freq 400
6650 12:22:52.199172 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6651 12:22:52.202977 best DQS0 dly(2T, 0.5T) = (0, 10)
6652 12:22:52.206118 best DQS1 dly(2T, 0.5T) = (0, 10)
6653 12:22:52.209614 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6654 12:22:52.212464 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6655 12:22:52.215776 best DQS0 dly(2T, 0.5T) = (0, 10)
6656 12:22:52.219200 best DQS1 dly(2T, 0.5T) = (0, 10)
6657 12:22:52.222574 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6658 12:22:52.225765 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6659 12:22:52.229139 Pre-setting of DQS Precalculation
6660 12:22:52.232397 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6661 12:22:52.232573 ==
6662 12:22:52.235991 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 12:22:52.242640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 12:22:52.242869 ==
6665 12:22:52.245567 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6666 12:22:52.252577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6667 12:22:52.255648 [CA 0] Center 36 (8~64) winsize 57
6668 12:22:52.258965 [CA 1] Center 36 (8~64) winsize 57
6669 12:22:52.262241 [CA 2] Center 36 (8~64) winsize 57
6670 12:22:52.265676 [CA 3] Center 36 (8~64) winsize 57
6671 12:22:52.269319 [CA 4] Center 36 (8~64) winsize 57
6672 12:22:52.272235 [CA 5] Center 36 (8~64) winsize 57
6673 12:22:52.272316
6674 12:22:52.276279 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6675 12:22:52.276362
6676 12:22:52.279237 [CATrainingPosCal] consider 1 rank data
6677 12:22:52.282744 u2DelayCellTimex100 = 270/100 ps
6678 12:22:52.285977 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 12:22:52.289509 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 12:22:52.292632 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 12:22:52.295804 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 12:22:52.299478 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 12:22:52.302556 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 12:22:52.302651
6685 12:22:52.306376 CA PerBit enable=1, Macro0, CA PI delay=36
6686 12:22:52.309216
6687 12:22:52.309297 [CBTSetCACLKResult] CA Dly = 36
6688 12:22:52.312867 CS Dly: 1 (0~32)
6689 12:22:52.312947 ==
6690 12:22:52.316362 Dram Type= 6, Freq= 0, CH_1, rank 1
6691 12:22:52.319615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 12:22:52.319697 ==
6693 12:22:52.326343 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6694 12:22:52.333045 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6695 12:22:52.336284 [CA 0] Center 36 (8~64) winsize 57
6696 12:22:52.339325 [CA 1] Center 36 (8~64) winsize 57
6697 12:22:52.339406 [CA 2] Center 36 (8~64) winsize 57
6698 12:22:52.342674 [CA 3] Center 36 (8~64) winsize 57
6699 12:22:52.345826 [CA 4] Center 36 (8~64) winsize 57
6700 12:22:52.349103 [CA 5] Center 36 (8~64) winsize 57
6701 12:22:52.349184
6702 12:22:52.352857 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6703 12:22:52.352938
6704 12:22:52.359380 [CATrainingPosCal] consider 2 rank data
6705 12:22:52.359461 u2DelayCellTimex100 = 270/100 ps
6706 12:22:52.363198 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 12:22:52.366370 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 12:22:52.372743 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 12:22:52.376249 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 12:22:52.379764 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 12:22:52.383238 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 12:22:52.383328
6713 12:22:52.386635 CA PerBit enable=1, Macro0, CA PI delay=36
6714 12:22:52.386767
6715 12:22:52.389727 [CBTSetCACLKResult] CA Dly = 36
6716 12:22:52.389827 CS Dly: 1 (0~32)
6717 12:22:52.389907
6718 12:22:52.393008 ----->DramcWriteLeveling(PI) begin...
6719 12:22:52.396569 ==
6720 12:22:52.396678 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 12:22:52.402707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 12:22:52.402842 ==
6723 12:22:52.406176 Write leveling (Byte 0): 40 => 8
6724 12:22:52.409947 Write leveling (Byte 1): 40 => 8
6725 12:22:52.410097 DramcWriteLeveling(PI) end<-----
6726 12:22:52.413298
6727 12:22:52.413448 ==
6728 12:22:52.416218 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 12:22:52.419771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 12:22:52.419986 ==
6731 12:22:52.422988 [Gating] SW mode calibration
6732 12:22:52.430186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6733 12:22:52.432989 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6734 12:22:52.440053 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6735 12:22:52.443546 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6736 12:22:52.446436 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 12:22:52.453738 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 12:22:52.456549 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 12:22:52.459835 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 12:22:52.466783 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 12:22:52.470656 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 12:22:52.473545 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6743 12:22:52.477051 Total UI for P1: 0, mck2ui 16
6744 12:22:52.480053 best dqsien dly found for B0: ( 0, 14, 24)
6745 12:22:52.483671 Total UI for P1: 0, mck2ui 16
6746 12:22:52.486395 best dqsien dly found for B1: ( 0, 14, 24)
6747 12:22:52.490067 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6748 12:22:52.493412 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6749 12:22:52.493917
6750 12:22:52.500049 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6751 12:22:52.503174 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 12:22:52.503587 [Gating] SW calibration Done
6753 12:22:52.506699 ==
6754 12:22:52.507142 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 12:22:52.513436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 12:22:52.513854 ==
6757 12:22:52.514186 RX Vref Scan: 0
6758 12:22:52.514522
6759 12:22:52.516791 RX Vref 0 -> 0, step: 1
6760 12:22:52.517528
6761 12:22:52.519731 RX Delay -410 -> 252, step: 16
6762 12:22:52.523332 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6763 12:22:52.526537 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6764 12:22:52.533134 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6765 12:22:52.536661 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6766 12:22:52.540132 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6767 12:22:52.543529 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6768 12:22:52.549701 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6769 12:22:52.553245 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6770 12:22:52.556810 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6771 12:22:52.559718 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6772 12:22:52.566800 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6773 12:22:52.570074 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6774 12:22:52.573443 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6775 12:22:52.576894 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6776 12:22:52.583222 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6777 12:22:52.586475 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6778 12:22:52.586934 ==
6779 12:22:52.590219 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 12:22:52.593995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 12:22:52.594601 ==
6782 12:22:52.600786 DQS Delay:
6783 12:22:52.601358 DQS0 = 43, DQS1 = 59
6784 12:22:52.601853 DQM Delay:
6785 12:22:52.602181 DQM0 = 11, DQM1 = 16
6786 12:22:52.602481 DQ Delay:
6787 12:22:52.603186 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6788 12:22:52.606789 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6789 12:22:52.610162 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6790 12:22:52.613587 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6791 12:22:52.614007
6792 12:22:52.614334
6793 12:22:52.614642 ==
6794 12:22:52.616833 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 12:22:52.620196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 12:22:52.623536 ==
6797 12:22:52.623957
6798 12:22:52.624285
6799 12:22:52.624591 TX Vref Scan disable
6800 12:22:52.626792 == TX Byte 0 ==
6801 12:22:52.630272 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 12:22:52.633507 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 12:22:52.636500 == TX Byte 1 ==
6804 12:22:52.640087 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6805 12:22:52.643821 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6806 12:22:52.644288 ==
6807 12:22:52.647035 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 12:22:52.650007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 12:22:52.650586 ==
6810 12:22:52.653501
6811 12:22:52.653958
6812 12:22:52.654335 TX Vref Scan disable
6813 12:22:52.657183 == TX Byte 0 ==
6814 12:22:52.660487 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 12:22:52.663625 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 12:22:52.666975 == TX Byte 1 ==
6817 12:22:52.670649 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6818 12:22:52.673507 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6819 12:22:52.674292
6820 12:22:52.674910 [DATLAT]
6821 12:22:52.676826 Freq=400, CH1 RK0
6822 12:22:52.677268
6823 12:22:52.677714 DATLAT Default: 0xf
6824 12:22:52.680304 0, 0xFFFF, sum = 0
6825 12:22:52.680730 1, 0xFFFF, sum = 0
6826 12:22:52.683947 2, 0xFFFF, sum = 0
6827 12:22:52.687165 3, 0xFFFF, sum = 0
6828 12:22:52.687588 4, 0xFFFF, sum = 0
6829 12:22:52.690157 5, 0xFFFF, sum = 0
6830 12:22:52.690577 6, 0xFFFF, sum = 0
6831 12:22:52.694075 7, 0xFFFF, sum = 0
6832 12:22:52.694498 8, 0xFFFF, sum = 0
6833 12:22:52.697336 9, 0xFFFF, sum = 0
6834 12:22:52.697756 10, 0xFFFF, sum = 0
6835 12:22:52.700657 11, 0xFFFF, sum = 0
6836 12:22:52.701077 12, 0xFFFF, sum = 0
6837 12:22:52.703642 13, 0x0, sum = 1
6838 12:22:52.704092 14, 0x0, sum = 2
6839 12:22:52.707140 15, 0x0, sum = 3
6840 12:22:52.707569 16, 0x0, sum = 4
6841 12:22:52.710455 best_step = 14
6842 12:22:52.710973
6843 12:22:52.711411 ==
6844 12:22:52.713868 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 12:22:52.717624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 12:22:52.718070 ==
6847 12:22:52.718411 RX Vref Scan: 1
6848 12:22:52.718765
6849 12:22:52.720793 RX Vref 0 -> 0, step: 1
6850 12:22:52.721220
6851 12:22:52.723740 RX Delay -359 -> 252, step: 8
6852 12:22:52.724186
6853 12:22:52.727135 Set Vref, RX VrefLevel [Byte0]: 57
6854 12:22:52.730331 [Byte1]: 53
6855 12:22:52.734171
6856 12:22:52.734600 Final RX Vref Byte 0 = 57 to rank0
6857 12:22:52.737750 Final RX Vref Byte 1 = 53 to rank0
6858 12:22:52.741181 Final RX Vref Byte 0 = 57 to rank1
6859 12:22:52.744543 Final RX Vref Byte 1 = 53 to rank1==
6860 12:22:52.747425 Dram Type= 6, Freq= 0, CH_1, rank 0
6861 12:22:52.754159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6862 12:22:52.754590 ==
6863 12:22:52.755057 DQS Delay:
6864 12:22:52.758342 DQS0 = 48, DQS1 = 60
6865 12:22:52.758907 DQM Delay:
6866 12:22:52.759342 DQM0 = 12, DQM1 = 13
6867 12:22:52.761039 DQ Delay:
6868 12:22:52.764378 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6869 12:22:52.764870 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6870 12:22:52.768037 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =12
6871 12:22:52.770986 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6872 12:22:52.771410
6873 12:22:52.771833
6874 12:22:52.781220 [DQSOSCAuto] RK0, (LSB)MR18= 0x8930, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6875 12:22:52.784195 CH1 RK0: MR19=C0C, MR18=8930
6876 12:22:52.791015 CH1_RK0: MR19=0xC0C, MR18=0x8930, DQSOSC=392, MR23=63, INC=384, DEC=256
6877 12:22:52.791454 ==
6878 12:22:52.794239 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 12:22:52.797936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 12:22:52.798401 ==
6881 12:22:52.801052 [Gating] SW mode calibration
6882 12:22:52.808216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6883 12:22:52.811212 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6884 12:22:52.818046 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6885 12:22:52.821015 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 12:22:52.824617 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 12:22:52.831256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 12:22:52.834482 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 12:22:52.837794 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 12:22:52.844201 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 12:22:52.847928 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 12:22:52.851245 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6893 12:22:52.854286 Total UI for P1: 0, mck2ui 16
6894 12:22:52.857725 best dqsien dly found for B0: ( 0, 14, 24)
6895 12:22:52.860905 Total UI for P1: 0, mck2ui 16
6896 12:22:52.864326 best dqsien dly found for B1: ( 0, 14, 24)
6897 12:22:52.867812 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6898 12:22:52.871345 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6899 12:22:52.874196
6900 12:22:52.877479 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6901 12:22:52.881188 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 12:22:52.884328 [Gating] SW calibration Done
6903 12:22:52.884847 ==
6904 12:22:52.887649 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 12:22:52.891038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 12:22:52.891458 ==
6907 12:22:52.891794 RX Vref Scan: 0
6908 12:22:52.892106
6909 12:22:52.894610 RX Vref 0 -> 0, step: 1
6910 12:22:52.895145
6911 12:22:52.897456 RX Delay -410 -> 252, step: 16
6912 12:22:52.901195 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6913 12:22:52.907695 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6914 12:22:52.910880 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6915 12:22:52.914544 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6916 12:22:52.917748 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6917 12:22:52.921173 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6918 12:22:52.927224 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6919 12:22:52.931341 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6920 12:22:52.934035 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6921 12:22:52.937414 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6922 12:22:52.943957 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6923 12:22:52.947369 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6924 12:22:52.951068 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6925 12:22:52.957618 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6926 12:22:52.960931 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6927 12:22:52.964114 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6928 12:22:52.964531 ==
6929 12:22:52.967607 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 12:22:52.970761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 12:22:52.971193 ==
6932 12:22:52.974136 DQS Delay:
6933 12:22:52.974550 DQS0 = 43, DQS1 = 59
6934 12:22:52.977381 DQM Delay:
6935 12:22:52.977796 DQM0 = 9, DQM1 = 20
6936 12:22:52.978169 DQ Delay:
6937 12:22:52.980912 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6938 12:22:52.984216 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6939 12:22:52.987628 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6940 12:22:52.991100 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6941 12:22:52.991560
6942 12:22:52.991893
6943 12:22:52.992198 ==
6944 12:22:52.994494 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 12:22:53.001284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 12:22:53.001700 ==
6947 12:22:53.002035
6948 12:22:53.002338
6949 12:22:53.002634 TX Vref Scan disable
6950 12:22:53.005103 == TX Byte 0 ==
6951 12:22:53.008019 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6952 12:22:53.011258 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6953 12:22:53.014478 == TX Byte 1 ==
6954 12:22:53.018119 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6955 12:22:53.021178 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6956 12:22:53.021594 ==
6957 12:22:53.024676 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 12:22:53.027903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 12:22:53.031487 ==
6960 12:22:53.031904
6961 12:22:53.032285
6962 12:22:53.032687 TX Vref Scan disable
6963 12:22:53.034583 == TX Byte 0 ==
6964 12:22:53.038041 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6965 12:22:53.041208 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6966 12:22:53.044329 == TX Byte 1 ==
6967 12:22:53.047810 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6968 12:22:53.051728 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6969 12:22:53.052176
6970 12:22:53.052515 [DATLAT]
6971 12:22:53.054830 Freq=400, CH1 RK1
6972 12:22:53.055246
6973 12:22:53.058073 DATLAT Default: 0xe
6974 12:22:53.058487 0, 0xFFFF, sum = 0
6975 12:22:53.061446 1, 0xFFFF, sum = 0
6976 12:22:53.061864 2, 0xFFFF, sum = 0
6977 12:22:53.064851 3, 0xFFFF, sum = 0
6978 12:22:53.065274 4, 0xFFFF, sum = 0
6979 12:22:53.067839 5, 0xFFFF, sum = 0
6980 12:22:53.068263 6, 0xFFFF, sum = 0
6981 12:22:53.071319 7, 0xFFFF, sum = 0
6982 12:22:53.071740 8, 0xFFFF, sum = 0
6983 12:22:53.074288 9, 0xFFFF, sum = 0
6984 12:22:53.074710 10, 0xFFFF, sum = 0
6985 12:22:53.078002 11, 0xFFFF, sum = 0
6986 12:22:53.078422 12, 0xFFFF, sum = 0
6987 12:22:53.081016 13, 0x0, sum = 1
6988 12:22:53.081436 14, 0x0, sum = 2
6989 12:22:53.084530 15, 0x0, sum = 3
6990 12:22:53.084953 16, 0x0, sum = 4
6991 12:22:53.088118 best_step = 14
6992 12:22:53.088532
6993 12:22:53.088861 ==
6994 12:22:53.091077 Dram Type= 6, Freq= 0, CH_1, rank 1
6995 12:22:53.094494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6996 12:22:53.094966 ==
6997 12:22:53.098015 RX Vref Scan: 0
6998 12:22:53.098428
6999 12:22:53.098802 RX Vref 0 -> 0, step: 1
7000 12:22:53.099129
7001 12:22:53.101117 RX Delay -359 -> 252, step: 8
7002 12:22:53.108621 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7003 12:22:53.112116 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7004 12:22:53.115360 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7005 12:22:53.118809 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
7006 12:22:53.125528 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7007 12:22:53.128882 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7008 12:22:53.132254 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7009 12:22:53.135497 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7010 12:22:53.142505 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7011 12:22:53.145924 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7012 12:22:53.149103 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7013 12:22:53.152131 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7014 12:22:53.158560 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7015 12:22:53.161866 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7016 12:22:53.165161 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7017 12:22:53.172071 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7018 12:22:53.172532 ==
7019 12:22:53.175471 Dram Type= 6, Freq= 0, CH_1, rank 1
7020 12:22:53.178832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7021 12:22:53.179260 ==
7022 12:22:53.179596 DQS Delay:
7023 12:22:53.181991 DQS0 = 52, DQS1 = 56
7024 12:22:53.182598 DQM Delay:
7025 12:22:53.185399 DQM0 = 13, DQM1 = 9
7026 12:22:53.185841 DQ Delay:
7027 12:22:53.188371 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7028 12:22:53.192071 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7029 12:22:53.195849 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7030 12:22:53.198432 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
7031 12:22:53.198904
7032 12:22:53.199333
7033 12:22:53.205737 [DQSOSCAuto] RK1, (LSB)MR18= 0x7c91, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 394 ps
7034 12:22:53.208710 CH1 RK1: MR19=C0C, MR18=7C91
7035 12:22:53.215298 CH1_RK1: MR19=0xC0C, MR18=0x7C91, DQSOSC=391, MR23=63, INC=386, DEC=257
7036 12:22:53.218837 [RxdqsGatingPostProcess] freq 400
7037 12:22:53.222195 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7038 12:22:53.224969 best DQS0 dly(2T, 0.5T) = (0, 10)
7039 12:22:53.228532 best DQS1 dly(2T, 0.5T) = (0, 10)
7040 12:22:53.231970 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7041 12:22:53.235410 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7042 12:22:53.238353 best DQS0 dly(2T, 0.5T) = (0, 10)
7043 12:22:53.241652 best DQS1 dly(2T, 0.5T) = (0, 10)
7044 12:22:53.244876 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7045 12:22:53.248549 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7046 12:22:53.252063 Pre-setting of DQS Precalculation
7047 12:22:53.255334 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7048 12:22:53.265029 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7049 12:22:53.271948 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7050 12:22:53.272376
7051 12:22:53.272899
7052 12:22:53.275245 [Calibration Summary] 800 Mbps
7053 12:22:53.275685 CH 0, Rank 0
7054 12:22:53.278410 SW Impedance : PASS
7055 12:22:53.278882 DUTY Scan : NO K
7056 12:22:53.281636 ZQ Calibration : PASS
7057 12:22:53.285154 Jitter Meter : NO K
7058 12:22:53.285572 CBT Training : PASS
7059 12:22:53.288386 Write leveling : PASS
7060 12:22:53.291600 RX DQS gating : PASS
7061 12:22:53.292018 RX DQ/DQS(RDDQC) : PASS
7062 12:22:53.295237 TX DQ/DQS : PASS
7063 12:22:53.298397 RX DATLAT : PASS
7064 12:22:53.298862 RX DQ/DQS(Engine): PASS
7065 12:22:53.301859 TX OE : NO K
7066 12:22:53.302304 All Pass.
7067 12:22:53.302641
7068 12:22:53.303035 CH 0, Rank 1
7069 12:22:53.305153 SW Impedance : PASS
7070 12:22:53.308409 DUTY Scan : NO K
7071 12:22:53.308824 ZQ Calibration : PASS
7072 12:22:53.311713 Jitter Meter : NO K
7073 12:22:53.314915 CBT Training : PASS
7074 12:22:53.315331 Write leveling : NO K
7075 12:22:53.318586 RX DQS gating : PASS
7076 12:22:53.321858 RX DQ/DQS(RDDQC) : PASS
7077 12:22:53.322274 TX DQ/DQS : PASS
7078 12:22:53.325431 RX DATLAT : PASS
7079 12:22:53.329019 RX DQ/DQS(Engine): PASS
7080 12:22:53.329452 TX OE : NO K
7081 12:22:53.332066 All Pass.
7082 12:22:53.332480
7083 12:22:53.332808 CH 1, Rank 0
7084 12:22:53.335476 SW Impedance : PASS
7085 12:22:53.335893 DUTY Scan : NO K
7086 12:22:53.338675 ZQ Calibration : PASS
7087 12:22:53.342111 Jitter Meter : NO K
7088 12:22:53.342523 CBT Training : PASS
7089 12:22:53.345266 Write leveling : PASS
7090 12:22:53.345682 RX DQS gating : PASS
7091 12:22:53.349155 RX DQ/DQS(RDDQC) : PASS
7092 12:22:53.352186 TX DQ/DQS : PASS
7093 12:22:53.352609 RX DATLAT : PASS
7094 12:22:53.355596 RX DQ/DQS(Engine): PASS
7095 12:22:53.359168 TX OE : NO K
7096 12:22:53.359590 All Pass.
7097 12:22:53.359925
7098 12:22:53.360231 CH 1, Rank 1
7099 12:22:53.361808 SW Impedance : PASS
7100 12:22:53.365007 DUTY Scan : NO K
7101 12:22:53.365470 ZQ Calibration : PASS
7102 12:22:53.368712 Jitter Meter : NO K
7103 12:22:53.372355 CBT Training : PASS
7104 12:22:53.372775 Write leveling : NO K
7105 12:22:53.375324 RX DQS gating : PASS
7106 12:22:53.378456 RX DQ/DQS(RDDQC) : PASS
7107 12:22:53.378918 TX DQ/DQS : PASS
7108 12:22:53.381902 RX DATLAT : PASS
7109 12:22:53.382319 RX DQ/DQS(Engine): PASS
7110 12:22:53.385288 TX OE : NO K
7111 12:22:53.385762 All Pass.
7112 12:22:53.386106
7113 12:22:53.388720 DramC Write-DBI off
7114 12:22:53.392181 PER_BANK_REFRESH: Hybrid Mode
7115 12:22:53.392599 TX_TRACKING: ON
7116 12:22:53.402432 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7117 12:22:53.405169 [FAST_K] Save calibration result to emmc
7118 12:22:53.409288 dramc_set_vcore_voltage set vcore to 725000
7119 12:22:53.412295 Read voltage for 1600, 0
7120 12:22:53.412711 Vio18 = 0
7121 12:22:53.413043 Vcore = 725000
7122 12:22:53.415751 Vdram = 0
7123 12:22:53.416170 Vddq = 0
7124 12:22:53.416501 Vmddr = 0
7125 12:22:53.422126 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7126 12:22:53.425822 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7127 12:22:53.429221 MEM_TYPE=3, freq_sel=13
7128 12:22:53.432117 sv_algorithm_assistance_LP4_3733
7129 12:22:53.435696 ============ PULL DRAM RESETB DOWN ============
7130 12:22:53.438691 ========== PULL DRAM RESETB DOWN end =========
7131 12:22:53.445572 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7132 12:22:53.448922 ===================================
7133 12:22:53.449336 LPDDR4 DRAM CONFIGURATION
7134 12:22:53.452297 ===================================
7135 12:22:53.455488 EX_ROW_EN[0] = 0x0
7136 12:22:53.459213 EX_ROW_EN[1] = 0x0
7137 12:22:53.459629 LP4Y_EN = 0x0
7138 12:22:53.462783 WORK_FSP = 0x1
7139 12:22:53.463203 WL = 0x5
7140 12:22:53.465993 RL = 0x5
7141 12:22:53.466408 BL = 0x2
7142 12:22:53.469436 RPST = 0x0
7143 12:22:53.469854 RD_PRE = 0x0
7144 12:22:53.472409 WR_PRE = 0x1
7145 12:22:53.472823 WR_PST = 0x1
7146 12:22:53.475720 DBI_WR = 0x0
7147 12:22:53.476141 DBI_RD = 0x0
7148 12:22:53.478995 OTF = 0x1
7149 12:22:53.482307 ===================================
7150 12:22:53.485547 ===================================
7151 12:22:53.485964 ANA top config
7152 12:22:53.489043 ===================================
7153 12:22:53.492580 DLL_ASYNC_EN = 0
7154 12:22:53.495599 ALL_SLAVE_EN = 0
7155 12:22:53.499250 NEW_RANK_MODE = 1
7156 12:22:53.499668 DLL_IDLE_MODE = 1
7157 12:22:53.502080 LP45_APHY_COMB_EN = 1
7158 12:22:53.505676 TX_ODT_DIS = 0
7159 12:22:53.508930 NEW_8X_MODE = 1
7160 12:22:53.512640 ===================================
7161 12:22:53.515889 ===================================
7162 12:22:53.518874 data_rate = 3200
7163 12:22:53.519289 CKR = 1
7164 12:22:53.522608 DQ_P2S_RATIO = 8
7165 12:22:53.526147 ===================================
7166 12:22:53.529127 CA_P2S_RATIO = 8
7167 12:22:53.532531 DQ_CA_OPEN = 0
7168 12:22:53.535925 DQ_SEMI_OPEN = 0
7169 12:22:53.536344 CA_SEMI_OPEN = 0
7170 12:22:53.539392 CA_FULL_RATE = 0
7171 12:22:53.542942 DQ_CKDIV4_EN = 0
7172 12:22:53.546269 CA_CKDIV4_EN = 0
7173 12:22:53.549585 CA_PREDIV_EN = 0
7174 12:22:53.552388 PH8_DLY = 12
7175 12:22:53.552806 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7176 12:22:53.555915 DQ_AAMCK_DIV = 4
7177 12:22:53.559323 CA_AAMCK_DIV = 4
7178 12:22:53.562920 CA_ADMCK_DIV = 4
7179 12:22:53.566102 DQ_TRACK_CA_EN = 0
7180 12:22:53.569333 CA_PICK = 1600
7181 12:22:53.569750 CA_MCKIO = 1600
7182 12:22:53.572719 MCKIO_SEMI = 0
7183 12:22:53.575949 PLL_FREQ = 3068
7184 12:22:53.579144 DQ_UI_PI_RATIO = 32
7185 12:22:53.582513 CA_UI_PI_RATIO = 0
7186 12:22:53.586487 ===================================
7187 12:22:53.589542 ===================================
7188 12:22:53.592677 memory_type:LPDDR4
7189 12:22:53.593095 GP_NUM : 10
7190 12:22:53.595869 SRAM_EN : 1
7191 12:22:53.596287 MD32_EN : 0
7192 12:22:53.599227 ===================================
7193 12:22:53.602594 [ANA_INIT] >>>>>>>>>>>>>>
7194 12:22:53.605855 <<<<<< [CONFIGURE PHASE]: ANA_TX
7195 12:22:53.609125 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7196 12:22:53.612456 ===================================
7197 12:22:53.616049 data_rate = 3200,PCW = 0X7600
7198 12:22:53.619444 ===================================
7199 12:22:53.622892 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7200 12:22:53.626561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7201 12:22:53.632704 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 12:22:53.636264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7203 12:22:53.639278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7204 12:22:53.646314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7205 12:22:53.646779 [ANA_INIT] flow start
7206 12:22:53.649620 [ANA_INIT] PLL >>>>>>>>
7207 12:22:53.650038 [ANA_INIT] PLL <<<<<<<<
7208 12:22:53.653050 [ANA_INIT] MIDPI >>>>>>>>
7209 12:22:53.656515 [ANA_INIT] MIDPI <<<<<<<<
7210 12:22:53.659328 [ANA_INIT] DLL >>>>>>>>
7211 12:22:53.659742 [ANA_INIT] DLL <<<<<<<<
7212 12:22:53.662767 [ANA_INIT] flow end
7213 12:22:53.666088 ============ LP4 DIFF to SE enter ============
7214 12:22:53.669686 ============ LP4 DIFF to SE exit ============
7215 12:22:53.673109 [ANA_INIT] <<<<<<<<<<<<<
7216 12:22:53.676332 [Flow] Enable top DCM control >>>>>
7217 12:22:53.679829 [Flow] Enable top DCM control <<<<<
7218 12:22:53.682708 Enable DLL master slave shuffle
7219 12:22:53.689550 ==============================================================
7220 12:22:53.689970 Gating Mode config
7221 12:22:53.696077 ==============================================================
7222 12:22:53.696507 Config description:
7223 12:22:53.706234 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7224 12:22:53.712689 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7225 12:22:53.719487 SELPH_MODE 0: By rank 1: By Phase
7226 12:22:53.723251 ==============================================================
7227 12:22:53.726561 GAT_TRACK_EN = 1
7228 12:22:53.729562 RX_GATING_MODE = 2
7229 12:22:53.733341 RX_GATING_TRACK_MODE = 2
7230 12:22:53.736547 SELPH_MODE = 1
7231 12:22:53.739508 PICG_EARLY_EN = 1
7232 12:22:53.742991 VALID_LAT_VALUE = 1
7233 12:22:53.746043 ==============================================================
7234 12:22:53.749431 Enter into Gating configuration >>>>
7235 12:22:53.753332 Exit from Gating configuration <<<<
7236 12:22:53.756298 Enter into DVFS_PRE_config >>>>>
7237 12:22:53.769739 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7238 12:22:53.770178 Exit from DVFS_PRE_config <<<<<
7239 12:22:53.773174 Enter into PICG configuration >>>>
7240 12:22:53.776710 Exit from PICG configuration <<<<
7241 12:22:53.779671 [RX_INPUT] configuration >>>>>
7242 12:22:53.783395 [RX_INPUT] configuration <<<<<
7243 12:22:53.789986 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7244 12:22:53.793628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7245 12:22:53.799955 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7246 12:22:53.806743 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7247 12:22:53.813166 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 12:22:53.819707 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 12:22:53.823174 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7250 12:22:53.826845 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7251 12:22:53.829846 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7252 12:22:53.836713 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7253 12:22:53.839778 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7254 12:22:53.843198 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 12:22:53.846578 ===================================
7256 12:22:53.850223 LPDDR4 DRAM CONFIGURATION
7257 12:22:53.853352 ===================================
7258 12:22:53.853812 EX_ROW_EN[0] = 0x0
7259 12:22:53.856317 EX_ROW_EN[1] = 0x0
7260 12:22:53.856731 LP4Y_EN = 0x0
7261 12:22:53.859760 WORK_FSP = 0x1
7262 12:22:53.860173 WL = 0x5
7263 12:22:53.863229 RL = 0x5
7264 12:22:53.863777 BL = 0x2
7265 12:22:53.866772 RPST = 0x0
7266 12:22:53.869751 RD_PRE = 0x0
7267 12:22:53.870181 WR_PRE = 0x1
7268 12:22:53.873530 WR_PST = 0x1
7269 12:22:53.873944 DBI_WR = 0x0
7270 12:22:53.876354 DBI_RD = 0x0
7271 12:22:53.876769 OTF = 0x1
7272 12:22:53.879674 ===================================
7273 12:22:53.883058 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7274 12:22:53.886588 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7275 12:22:53.893305 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7276 12:22:53.896566 ===================================
7277 12:22:53.899950 LPDDR4 DRAM CONFIGURATION
7278 12:22:53.903641 ===================================
7279 12:22:53.904204 EX_ROW_EN[0] = 0x10
7280 12:22:53.906613 EX_ROW_EN[1] = 0x0
7281 12:22:53.907073 LP4Y_EN = 0x0
7282 12:22:53.910074 WORK_FSP = 0x1
7283 12:22:53.910484 WL = 0x5
7284 12:22:53.913559 RL = 0x5
7285 12:22:53.914023 BL = 0x2
7286 12:22:53.917056 RPST = 0x0
7287 12:22:53.917482 RD_PRE = 0x0
7288 12:22:53.920325 WR_PRE = 0x1
7289 12:22:53.920736 WR_PST = 0x1
7290 12:22:53.923195 DBI_WR = 0x0
7291 12:22:53.923656 DBI_RD = 0x0
7292 12:22:53.926363 OTF = 0x1
7293 12:22:53.930050 ===================================
7294 12:22:53.936650 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7295 12:22:53.937151 ==
7296 12:22:53.940213 Dram Type= 6, Freq= 0, CH_0, rank 0
7297 12:22:53.943138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 12:22:53.943555 ==
7299 12:22:53.946547 [Duty_Offset_Calibration]
7300 12:22:53.947033 B0:2 B1:-1 CA:1
7301 12:22:53.947420
7302 12:22:53.949910 [DutyScan_Calibration_Flow] k_type=0
7303 12:22:53.960010
7304 12:22:53.960420 ==CLK 0==
7305 12:22:53.963367 Final CLK duty delay cell = -4
7306 12:22:53.966817 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7307 12:22:53.970366 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7308 12:22:53.973677 [-4] AVG Duty = 4937%(X100)
7309 12:22:53.974107
7310 12:22:53.976912 CH0 CLK Duty spec in!! Max-Min= 187%
7311 12:22:53.980277 [DutyScan_Calibration_Flow] ====Done====
7312 12:22:53.980695
7313 12:22:53.983593 [DutyScan_Calibration_Flow] k_type=1
7314 12:22:53.999876
7315 12:22:54.000294 ==DQS 0 ==
7316 12:22:54.002889 Final DQS duty delay cell = 0
7317 12:22:54.006563 [0] MAX Duty = 5125%(X100), DQS PI = 22
7318 12:22:54.009829 [0] MIN Duty = 5000%(X100), DQS PI = 14
7319 12:22:54.012742 [0] AVG Duty = 5062%(X100)
7320 12:22:54.013180
7321 12:22:54.013510 ==DQS 1 ==
7322 12:22:54.016360 Final DQS duty delay cell = -4
7323 12:22:54.020178 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7324 12:22:54.023229 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7325 12:22:54.026817 [-4] AVG Duty = 5046%(X100)
7326 12:22:54.027235
7327 12:22:54.029940 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7328 12:22:54.030358
7329 12:22:54.032934 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7330 12:22:54.036509 [DutyScan_Calibration_Flow] ====Done====
7331 12:22:54.036927
7332 12:22:54.039866 [DutyScan_Calibration_Flow] k_type=3
7333 12:22:54.057057
7334 12:22:54.057516 ==DQM 0 ==
7335 12:22:54.060167 Final DQM duty delay cell = 0
7336 12:22:54.063715 [0] MAX Duty = 5000%(X100), DQS PI = 20
7337 12:22:54.066782 [0] MIN Duty = 4875%(X100), DQS PI = 6
7338 12:22:54.067208 [0] AVG Duty = 4937%(X100)
7339 12:22:54.070362
7340 12:22:54.070827 ==DQM 1 ==
7341 12:22:54.073467 Final DQM duty delay cell = 0
7342 12:22:54.076963 [0] MAX Duty = 5187%(X100), DQS PI = 58
7343 12:22:54.080150 [0] MIN Duty = 4969%(X100), DQS PI = 18
7344 12:22:54.083935 [0] AVG Duty = 5078%(X100)
7345 12:22:54.084361
7346 12:22:54.087161 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7347 12:22:54.087601
7348 12:22:54.090196 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7349 12:22:54.093391 [DutyScan_Calibration_Flow] ====Done====
7350 12:22:54.093811
7351 12:22:54.096587 [DutyScan_Calibration_Flow] k_type=2
7352 12:22:54.113593
7353 12:22:54.114019 ==DQ 0 ==
7354 12:22:54.116640 Final DQ duty delay cell = -4
7355 12:22:54.120300 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7356 12:22:54.123287 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7357 12:22:54.127350 [-4] AVG Duty = 4922%(X100)
7358 12:22:54.127796
7359 12:22:54.128139 ==DQ 1 ==
7360 12:22:54.129800 Final DQ duty delay cell = 0
7361 12:22:54.133577 [0] MAX Duty = 5031%(X100), DQS PI = 38
7362 12:22:54.136524 [0] MIN Duty = 4907%(X100), DQS PI = 18
7363 12:22:54.136945 [0] AVG Duty = 4969%(X100)
7364 12:22:54.140785
7365 12:22:54.143210 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7366 12:22:54.143641
7367 12:22:54.146636 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7368 12:22:54.150050 [DutyScan_Calibration_Flow] ====Done====
7369 12:22:54.150481 ==
7370 12:22:54.153729 Dram Type= 6, Freq= 0, CH_1, rank 0
7371 12:22:54.156823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7372 12:22:54.157240 ==
7373 12:22:54.159668 [Duty_Offset_Calibration]
7374 12:22:54.160121 B0:1 B1:1 CA:2
7375 12:22:54.160523
7376 12:22:54.163052 [DutyScan_Calibration_Flow] k_type=0
7377 12:22:54.173568
7378 12:22:54.173983 ==CLK 0==
7379 12:22:54.177526 Final CLK duty delay cell = 0
7380 12:22:54.180598 [0] MAX Duty = 5187%(X100), DQS PI = 24
7381 12:22:54.183783 [0] MIN Duty = 4938%(X100), DQS PI = 48
7382 12:22:54.184216 [0] AVG Duty = 5062%(X100)
7383 12:22:54.187320
7384 12:22:54.190598 CH1 CLK Duty spec in!! Max-Min= 249%
7385 12:22:54.193661 [DutyScan_Calibration_Flow] ====Done====
7386 12:22:54.194075
7387 12:22:54.196988 [DutyScan_Calibration_Flow] k_type=1
7388 12:22:54.213528
7389 12:22:54.213941 ==DQS 0 ==
7390 12:22:54.217064 Final DQS duty delay cell = 0
7391 12:22:54.220334 [0] MAX Duty = 5062%(X100), DQS PI = 20
7392 12:22:54.224019 [0] MIN Duty = 4813%(X100), DQS PI = 52
7393 12:22:54.227182 [0] AVG Duty = 4937%(X100)
7394 12:22:54.227636
7395 12:22:54.228011 ==DQS 1 ==
7396 12:22:54.230100 Final DQS duty delay cell = 0
7397 12:22:54.233384 [0] MAX Duty = 5062%(X100), DQS PI = 56
7398 12:22:54.236914 [0] MIN Duty = 4938%(X100), DQS PI = 12
7399 12:22:54.237341 [0] AVG Duty = 5000%(X100)
7400 12:22:54.240267
7401 12:22:54.243770 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7402 12:22:54.244204
7403 12:22:54.247276 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7404 12:22:54.249946 [DutyScan_Calibration_Flow] ====Done====
7405 12:22:54.250487
7406 12:22:54.253488 [DutyScan_Calibration_Flow] k_type=3
7407 12:22:54.270708
7408 12:22:54.271169 ==DQM 0 ==
7409 12:22:54.274061 Final DQM duty delay cell = 0
7410 12:22:54.277056 [0] MAX Duty = 5187%(X100), DQS PI = 20
7411 12:22:54.280565 [0] MIN Duty = 4813%(X100), DQS PI = 50
7412 12:22:54.283662 [0] AVG Duty = 5000%(X100)
7413 12:22:54.284079
7414 12:22:54.284408 ==DQM 1 ==
7415 12:22:54.287404 Final DQM duty delay cell = 0
7416 12:22:54.290228 [0] MAX Duty = 5156%(X100), DQS PI = 60
7417 12:22:54.294013 [0] MIN Duty = 4875%(X100), DQS PI = 20
7418 12:22:54.296870 [0] AVG Duty = 5015%(X100)
7419 12:22:54.297286
7420 12:22:54.300149 CH1 DQM 0 Duty spec in!! Max-Min= 374%
7421 12:22:54.300567
7422 12:22:54.303549 CH1 DQM 1 Duty spec in!! Max-Min= 281%
7423 12:22:54.307280 [DutyScan_Calibration_Flow] ====Done====
7424 12:22:54.307710
7425 12:22:54.310080 [DutyScan_Calibration_Flow] k_type=2
7426 12:22:54.327611
7427 12:22:54.328027 ==DQ 0 ==
7428 12:22:54.330622 Final DQ duty delay cell = 0
7429 12:22:54.334148 [0] MAX Duty = 5156%(X100), DQS PI = 20
7430 12:22:54.337382 [0] MIN Duty = 4907%(X100), DQS PI = 52
7431 12:22:54.337797 [0] AVG Duty = 5031%(X100)
7432 12:22:54.340596
7433 12:22:54.341010 ==DQ 1 ==
7434 12:22:54.344353 Final DQ duty delay cell = 0
7435 12:22:54.347381 [0] MAX Duty = 5093%(X100), DQS PI = 8
7436 12:22:54.350907 [0] MIN Duty = 5031%(X100), DQS PI = 0
7437 12:22:54.351323 [0] AVG Duty = 5062%(X100)
7438 12:22:54.351648
7439 12:22:54.354289 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7440 12:22:54.354699
7441 12:22:54.357142 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7442 12:22:54.363937 [DutyScan_Calibration_Flow] ====Done====
7443 12:22:54.367237 nWR fixed to 30
7444 12:22:54.367669 [ModeRegInit_LP4] CH0 RK0
7445 12:22:54.370798 [ModeRegInit_LP4] CH0 RK1
7446 12:22:54.373882 [ModeRegInit_LP4] CH1 RK0
7447 12:22:54.374350 [ModeRegInit_LP4] CH1 RK1
7448 12:22:54.377137 match AC timing 5
7449 12:22:54.380870 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7450 12:22:54.384175 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7451 12:22:54.391052 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7452 12:22:54.394176 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7453 12:22:54.400781 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7454 12:22:54.401200 [MiockJmeterHQA]
7455 12:22:54.401569
7456 12:22:54.404129 [DramcMiockJmeter] u1RxGatingPI = 0
7457 12:22:54.404546 0 : 4363, 4137
7458 12:22:54.407470 4 : 4252, 4027
7459 12:22:54.407892 8 : 4363, 4138
7460 12:22:54.411170 12 : 4253, 4026
7461 12:22:54.411591 16 : 4363, 4138
7462 12:22:54.414426 20 : 4252, 4027
7463 12:22:54.414921 24 : 4361, 4138
7464 12:22:54.417247 28 : 4253, 4026
7465 12:22:54.417669 32 : 4250, 4027
7466 12:22:54.418002 36 : 4250, 4027
7467 12:22:54.420644 40 : 4363, 4137
7468 12:22:54.421065 44 : 4361, 4138
7469 12:22:54.424224 48 : 4250, 4026
7470 12:22:54.424658 52 : 4250, 4027
7471 12:22:54.427483 56 : 4250, 4027
7472 12:22:54.427902 60 : 4253, 4026
7473 12:22:54.428241 64 : 4252, 4030
7474 12:22:54.430359 68 : 4360, 4138
7475 12:22:54.430854 72 : 4250, 4027
7476 12:22:54.433825 76 : 4250, 4027
7477 12:22:54.434311 80 : 4250, 4026
7478 12:22:54.437540 84 : 4252, 4030
7479 12:22:54.437960 88 : 4250, 4026
7480 12:22:54.441142 92 : 4361, 4137
7481 12:22:54.441564 96 : 4361, 3136
7482 12:22:54.441958 100 : 4250, 0
7483 12:22:54.444287 104 : 4360, 0
7484 12:22:54.444709 108 : 4255, 0
7485 12:22:54.447803 112 : 4250, 0
7486 12:22:54.448224 116 : 4250, 0
7487 12:22:54.448641 120 : 4252, 0
7488 12:22:54.450602 124 : 4250, 0
7489 12:22:54.451068 128 : 4250, 0
7490 12:22:54.454207 132 : 4252, 0
7491 12:22:54.454635 136 : 4361, 0
7492 12:22:54.455037 140 : 4360, 0
7493 12:22:54.457564 144 : 4250, 0
7494 12:22:54.457990 148 : 4250, 0
7495 12:22:54.458342 152 : 4361, 0
7496 12:22:54.461181 156 : 4360, 0
7497 12:22:54.461611 160 : 4250, 0
7498 12:22:54.464090 164 : 4250, 0
7499 12:22:54.464514 168 : 4250, 0
7500 12:22:54.464856 172 : 4249, 0
7501 12:22:54.467387 176 : 4250, 0
7502 12:22:54.467809 180 : 4250, 0
7503 12:22:54.470549 184 : 4252, 0
7504 12:22:54.471015 188 : 4250, 0
7505 12:22:54.471386 192 : 4250, 0
7506 12:22:54.474073 196 : 4252, 0
7507 12:22:54.474500 200 : 4250, 0
7508 12:22:54.474967 204 : 4361, 0
7509 12:22:54.477566 208 : 4250, 0
7510 12:22:54.477986 212 : 4250, 210
7511 12:22:54.480670 216 : 4250, 3835
7512 12:22:54.481089 220 : 4252, 4029
7513 12:22:54.484043 224 : 4361, 4137
7514 12:22:54.484465 228 : 4250, 4027
7515 12:22:54.487600 232 : 4250, 4027
7516 12:22:54.488021 236 : 4360, 4137
7517 12:22:54.490942 240 : 4250, 4026
7518 12:22:54.491364 244 : 4250, 4027
7519 12:22:54.491703 248 : 4363, 4140
7520 12:22:54.493891 252 : 4250, 4027
7521 12:22:54.494378 256 : 4250, 4026
7522 12:22:54.497101 260 : 4250, 4027
7523 12:22:54.497524 264 : 4253, 4030
7524 12:22:54.500944 268 : 4250, 4027
7525 12:22:54.501425 272 : 4250, 4026
7526 12:22:54.504020 276 : 4361, 4137
7527 12:22:54.504443 280 : 4250, 4027
7528 12:22:54.507353 284 : 4250, 4027
7529 12:22:54.507781 288 : 4360, 4137
7530 12:22:54.510609 292 : 4250, 4026
7531 12:22:54.511030 296 : 4252, 4027
7532 12:22:54.514239 300 : 4363, 4140
7533 12:22:54.514687 304 : 4250, 4027
7534 12:22:54.515084 308 : 4249, 4027
7535 12:22:54.517868 312 : 4250, 4027
7536 12:22:54.518291 316 : 4252, 4030
7537 12:22:54.520995 320 : 4250, 4027
7538 12:22:54.521418 324 : 4255, 4029
7539 12:22:54.524538 328 : 4361, 4137
7540 12:22:54.524964 332 : 4250, 3040
7541 12:22:54.527937 336 : 4250, 13
7542 12:22:54.528362
7543 12:22:54.528695 MIOCK jitter meter ch=0
7544 12:22:54.529005
7545 12:22:54.530978 1T = (336-100) = 236 dly cells
7546 12:22:54.537911 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7547 12:22:54.538333 ==
7548 12:22:54.541045 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 12:22:54.544206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 12:22:54.544629 ==
7551 12:22:54.550968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7552 12:22:54.554142 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7553 12:22:54.558198 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7554 12:22:54.564575 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7555 12:22:54.573812 [CA 0] Center 44 (14~75) winsize 62
7556 12:22:54.577292 [CA 1] Center 44 (14~74) winsize 61
7557 12:22:54.580860 [CA 2] Center 39 (10~68) winsize 59
7558 12:22:54.583654 [CA 3] Center 39 (10~68) winsize 59
7559 12:22:54.587578 [CA 4] Center 37 (7~67) winsize 61
7560 12:22:54.590707 [CA 5] Center 37 (7~67) winsize 61
7561 12:22:54.591177
7562 12:22:54.593819 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7563 12:22:54.594239
7564 12:22:54.597384 [CATrainingPosCal] consider 1 rank data
7565 12:22:54.600952 u2DelayCellTimex100 = 275/100 ps
7566 12:22:54.604368 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7567 12:22:54.610688 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7568 12:22:54.614448 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7569 12:22:54.617481 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7570 12:22:54.620878 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7571 12:22:54.623733 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7572 12:22:54.624154
7573 12:22:54.627670 CA PerBit enable=1, Macro0, CA PI delay=37
7574 12:22:54.628091
7575 12:22:54.630891 [CBTSetCACLKResult] CA Dly = 37
7576 12:22:54.633823 CS Dly: 11 (0~42)
7577 12:22:54.637159 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7578 12:22:54.641078 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7579 12:22:54.641501 ==
7580 12:22:54.643590 Dram Type= 6, Freq= 0, CH_0, rank 1
7581 12:22:54.647392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7582 12:22:54.650807 ==
7583 12:22:54.654348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7584 12:22:54.657160 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7585 12:22:54.663619 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7586 12:22:54.666962 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7587 12:22:54.677818 [CA 0] Center 44 (14~74) winsize 61
7588 12:22:54.681115 [CA 1] Center 44 (14~75) winsize 62
7589 12:22:54.684737 [CA 2] Center 40 (11~69) winsize 59
7590 12:22:54.687720 [CA 3] Center 39 (10~69) winsize 60
7591 12:22:54.691045 [CA 4] Center 38 (9~67) winsize 59
7592 12:22:54.694609 [CA 5] Center 37 (8~67) winsize 60
7593 12:22:54.695148
7594 12:22:54.698089 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7595 12:22:54.698587
7596 12:22:54.701145 [CATrainingPosCal] consider 2 rank data
7597 12:22:54.704707 u2DelayCellTimex100 = 275/100 ps
7598 12:22:54.708089 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7599 12:22:54.714046 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7600 12:22:54.717543 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7601 12:22:54.720964 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7602 12:22:54.724157 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
7603 12:22:54.727754 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
7604 12:22:54.728221
7605 12:22:54.730846 CA PerBit enable=1, Macro0, CA PI delay=37
7606 12:22:54.731322
7607 12:22:54.734528 [CBTSetCACLKResult] CA Dly = 37
7608 12:22:54.737543 CS Dly: 11 (0~43)
7609 12:22:54.740716 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7610 12:22:54.744492 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7611 12:22:54.744988
7612 12:22:54.747743 ----->DramcWriteLeveling(PI) begin...
7613 12:22:54.748274 ==
7614 12:22:54.751179 Dram Type= 6, Freq= 0, CH_0, rank 0
7615 12:22:54.754274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7616 12:22:54.757700 ==
7617 12:22:54.758172 Write leveling (Byte 0): 31 => 31
7618 12:22:54.761219 Write leveling (Byte 1): 26 => 26
7619 12:22:54.764248 DramcWriteLeveling(PI) end<-----
7620 12:22:54.764724
7621 12:22:54.765102 ==
7622 12:22:54.767899 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 12:22:54.775027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 12:22:54.775567 ==
7625 12:22:54.775960 [Gating] SW mode calibration
7626 12:22:54.784377 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7627 12:22:54.787861 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7628 12:22:54.791327 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 12:22:54.798044 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 12:22:54.800969 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 12:22:54.804599 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 12:22:54.810989 1 4 16 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7633 12:22:54.814889 1 4 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7634 12:22:54.817910 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7635 12:22:54.824927 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7636 12:22:54.828253 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7637 12:22:54.831272 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7638 12:22:54.837891 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7639 12:22:54.841761 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7640 12:22:54.844588 1 5 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7641 12:22:54.851697 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7642 12:22:54.854243 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7643 12:22:54.857977 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 12:22:54.864357 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 12:22:54.867849 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 12:22:54.871416 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 12:22:54.874669 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7648 12:22:54.881343 1 6 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7649 12:22:54.884348 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7650 12:22:54.887951 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7651 12:22:54.894532 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7652 12:22:54.897874 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7653 12:22:54.901448 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 12:22:54.907720 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7655 12:22:54.911138 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7656 12:22:54.914559 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7657 12:22:54.921380 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7658 12:22:54.924503 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7659 12:22:54.928058 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 12:22:54.934797 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 12:22:54.937780 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 12:22:54.941556 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 12:22:54.947699 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 12:22:54.951138 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 12:22:54.954344 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 12:22:54.961470 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 12:22:54.964323 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 12:22:54.967761 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 12:22:54.970965 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 12:22:54.977627 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 12:22:54.980697 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 12:22:54.984224 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7673 12:22:54.990914 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7674 12:22:54.994077 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7675 12:22:54.997470 Total UI for P1: 0, mck2ui 16
7676 12:22:55.000894 best dqsien dly found for B0: ( 1, 9, 18)
7677 12:22:55.003972 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 12:22:55.007422 Total UI for P1: 0, mck2ui 16
7679 12:22:55.011082 best dqsien dly found for B1: ( 1, 9, 22)
7680 12:22:55.014567 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7681 12:22:55.017483 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7682 12:22:55.017564
7683 12:22:55.023900 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7684 12:22:55.027910 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7685 12:22:55.031096 [Gating] SW calibration Done
7686 12:22:55.031180 ==
7687 12:22:55.033881 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 12:22:55.037464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 12:22:55.037562 ==
7690 12:22:55.037647 RX Vref Scan: 0
7691 12:22:55.037727
7692 12:22:55.041203 RX Vref 0 -> 0, step: 1
7693 12:22:55.041287
7694 12:22:55.044296 RX Delay 0 -> 252, step: 8
7695 12:22:55.047530 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7696 12:22:55.050876 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7697 12:22:55.054001 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7698 12:22:55.060796 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7699 12:22:55.064122 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7700 12:22:55.067417 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7701 12:22:55.070791 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7702 12:22:55.074444 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7703 12:22:55.081032 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7704 12:22:55.084245 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7705 12:22:55.087552 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7706 12:22:55.091082 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7707 12:22:55.094227 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7708 12:22:55.101023 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7709 12:22:55.104458 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7710 12:22:55.107869 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7711 12:22:55.107950 ==
7712 12:22:55.111025 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 12:22:55.114427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 12:22:55.114510 ==
7715 12:22:55.117899 DQS Delay:
7716 12:22:55.117980 DQS0 = 0, DQS1 = 0
7717 12:22:55.121243 DQM Delay:
7718 12:22:55.121324 DQM0 = 132, DQM1 = 123
7719 12:22:55.121389 DQ Delay:
7720 12:22:55.124237 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7721 12:22:55.131121 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7722 12:22:55.134580 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7723 12:22:55.137618 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7724 12:22:55.137700
7725 12:22:55.137763
7726 12:22:55.137822 ==
7727 12:22:55.140977 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 12:22:55.144688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 12:22:55.144769 ==
7730 12:22:55.144833
7731 12:22:55.144891
7732 12:22:55.148147 TX Vref Scan disable
7733 12:22:55.151182 == TX Byte 0 ==
7734 12:22:55.154407 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7735 12:22:55.157869 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7736 12:22:55.157951 == TX Byte 1 ==
7737 12:22:55.164579 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7738 12:22:55.167654 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7739 12:22:55.167735 ==
7740 12:22:55.171013 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 12:22:55.174626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 12:22:55.174707 ==
7743 12:22:55.189065
7744 12:22:55.192572 TX Vref early break, caculate TX vref
7745 12:22:55.195613 TX Vref=16, minBit 1, minWin=21, winSum=351
7746 12:22:55.199387 TX Vref=18, minBit 1, minWin=21, winSum=359
7747 12:22:55.202713 TX Vref=20, minBit 0, minWin=22, winSum=371
7748 12:22:55.206074 TX Vref=22, minBit 0, minWin=23, winSum=386
7749 12:22:55.209295 TX Vref=24, minBit 0, minWin=23, winSum=389
7750 12:22:55.216102 TX Vref=26, minBit 7, minWin=23, winSum=405
7751 12:22:55.219246 TX Vref=28, minBit 1, minWin=25, winSum=415
7752 12:22:55.222493 TX Vref=30, minBit 0, minWin=25, winSum=412
7753 12:22:55.226336 TX Vref=32, minBit 0, minWin=24, winSum=401
7754 12:22:55.229516 TX Vref=34, minBit 0, minWin=23, winSum=391
7755 12:22:55.235892 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 28
7756 12:22:55.235973
7757 12:22:55.239163 Final TX Range 0 Vref 28
7758 12:22:55.239244
7759 12:22:55.239308 ==
7760 12:22:55.242998 Dram Type= 6, Freq= 0, CH_0, rank 0
7761 12:22:55.246218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7762 12:22:55.246299 ==
7763 12:22:55.246363
7764 12:22:55.246423
7765 12:22:55.249581 TX Vref Scan disable
7766 12:22:55.252556 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7767 12:22:55.255958 == TX Byte 0 ==
7768 12:22:55.259318 u2DelayCellOfst[0]=14 cells (4 PI)
7769 12:22:55.262700 u2DelayCellOfst[1]=21 cells (6 PI)
7770 12:22:55.265927 u2DelayCellOfst[2]=10 cells (3 PI)
7771 12:22:55.269684 u2DelayCellOfst[3]=14 cells (4 PI)
7772 12:22:55.272653 u2DelayCellOfst[4]=10 cells (3 PI)
7773 12:22:55.272734 u2DelayCellOfst[5]=0 cells (0 PI)
7774 12:22:55.276026 u2DelayCellOfst[6]=21 cells (6 PI)
7775 12:22:55.279809 u2DelayCellOfst[7]=17 cells (5 PI)
7776 12:22:55.286184 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7777 12:22:55.289487 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7778 12:22:55.289593 == TX Byte 1 ==
7779 12:22:55.293015 u2DelayCellOfst[8]=0 cells (0 PI)
7780 12:22:55.296486 u2DelayCellOfst[9]=0 cells (0 PI)
7781 12:22:55.299500 u2DelayCellOfst[10]=7 cells (2 PI)
7782 12:22:55.303235 u2DelayCellOfst[11]=0 cells (0 PI)
7783 12:22:55.306257 u2DelayCellOfst[12]=10 cells (3 PI)
7784 12:22:55.309674 u2DelayCellOfst[13]=10 cells (3 PI)
7785 12:22:55.312914 u2DelayCellOfst[14]=14 cells (4 PI)
7786 12:22:55.316500 u2DelayCellOfst[15]=10 cells (3 PI)
7787 12:22:55.320012 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7788 12:22:55.323389 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7789 12:22:55.326400 DramC Write-DBI on
7790 12:22:55.326482 ==
7791 12:22:55.329870 Dram Type= 6, Freq= 0, CH_0, rank 0
7792 12:22:55.333462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7793 12:22:55.333545 ==
7794 12:22:55.333645
7795 12:22:55.333720
7796 12:22:55.336770 TX Vref Scan disable
7797 12:22:55.339795 == TX Byte 0 ==
7798 12:22:55.343186 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7799 12:22:55.343268 == TX Byte 1 ==
7800 12:22:55.351004 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7801 12:22:55.351085 DramC Write-DBI off
7802 12:22:55.351150
7803 12:22:55.351209 [DATLAT]
7804 12:22:55.353335 Freq=1600, CH0 RK0
7805 12:22:55.353433
7806 12:22:55.357050 DATLAT Default: 0xf
7807 12:22:55.357133 0, 0xFFFF, sum = 0
7808 12:22:55.359812 1, 0xFFFF, sum = 0
7809 12:22:55.359909 2, 0xFFFF, sum = 0
7810 12:22:55.363627 3, 0xFFFF, sum = 0
7811 12:22:55.363711 4, 0xFFFF, sum = 0
7812 12:22:55.366439 5, 0xFFFF, sum = 0
7813 12:22:55.366522 6, 0xFFFF, sum = 0
7814 12:22:55.370179 7, 0xFFFF, sum = 0
7815 12:22:55.370262 8, 0xFFFF, sum = 0
7816 12:22:55.373601 9, 0xFFFF, sum = 0
7817 12:22:55.373684 10, 0xFFFF, sum = 0
7818 12:22:55.376983 11, 0xFFFF, sum = 0
7819 12:22:55.377066 12, 0xFFFF, sum = 0
7820 12:22:55.380378 13, 0xFFFF, sum = 0
7821 12:22:55.380460 14, 0x0, sum = 1
7822 12:22:55.383722 15, 0x0, sum = 2
7823 12:22:55.383808 16, 0x0, sum = 3
7824 12:22:55.387036 17, 0x0, sum = 4
7825 12:22:55.387118 best_step = 15
7826 12:22:55.387182
7827 12:22:55.387241 ==
7828 12:22:55.390654 Dram Type= 6, Freq= 0, CH_0, rank 0
7829 12:22:55.393577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7830 12:22:55.396805 ==
7831 12:22:55.396915 RX Vref Scan: 1
7832 12:22:55.396982
7833 12:22:55.400327 Set Vref Range= 24 -> 127
7834 12:22:55.400408
7835 12:22:55.403631 RX Vref 24 -> 127, step: 1
7836 12:22:55.403713
7837 12:22:55.403778 RX Delay 11 -> 252, step: 4
7838 12:22:55.403840
7839 12:22:55.407122 Set Vref, RX VrefLevel [Byte0]: 24
7840 12:22:55.410111 [Byte1]: 24
7841 12:22:55.413800
7842 12:22:55.413880 Set Vref, RX VrefLevel [Byte0]: 25
7843 12:22:55.417271 [Byte1]: 25
7844 12:22:55.421787
7845 12:22:55.421868 Set Vref, RX VrefLevel [Byte0]: 26
7846 12:22:55.424684 [Byte1]: 26
7847 12:22:55.429489
7848 12:22:55.429570 Set Vref, RX VrefLevel [Byte0]: 27
7849 12:22:55.432432 [Byte1]: 27
7850 12:22:55.436907
7851 12:22:55.436988 Set Vref, RX VrefLevel [Byte0]: 28
7852 12:22:55.440212 [Byte1]: 28
7853 12:22:55.444355
7854 12:22:55.444436 Set Vref, RX VrefLevel [Byte0]: 29
7855 12:22:55.447603 [Byte1]: 29
7856 12:22:55.452153
7857 12:22:55.452234 Set Vref, RX VrefLevel [Byte0]: 30
7858 12:22:55.455335 [Byte1]: 30
7859 12:22:55.459409
7860 12:22:55.459489 Set Vref, RX VrefLevel [Byte0]: 31
7861 12:22:55.463171 [Byte1]: 31
7862 12:22:55.467117
7863 12:22:55.467197 Set Vref, RX VrefLevel [Byte0]: 32
7864 12:22:55.470532 [Byte1]: 32
7865 12:22:55.475069
7866 12:22:55.475149 Set Vref, RX VrefLevel [Byte0]: 33
7867 12:22:55.477939 [Byte1]: 33
7868 12:22:55.482162
7869 12:22:55.482242 Set Vref, RX VrefLevel [Byte0]: 34
7870 12:22:55.485624 [Byte1]: 34
7871 12:22:55.489952
7872 12:22:55.490032 Set Vref, RX VrefLevel [Byte0]: 35
7873 12:22:55.493065 [Byte1]: 35
7874 12:22:55.497590
7875 12:22:55.497671 Set Vref, RX VrefLevel [Byte0]: 36
7876 12:22:55.501128 [Byte1]: 36
7877 12:22:55.505206
7878 12:22:55.505286 Set Vref, RX VrefLevel [Byte0]: 37
7879 12:22:55.508591 [Byte1]: 37
7880 12:22:55.512785
7881 12:22:55.512866 Set Vref, RX VrefLevel [Byte0]: 38
7882 12:22:55.516063 [Byte1]: 38
7883 12:22:55.520674
7884 12:22:55.520755 Set Vref, RX VrefLevel [Byte0]: 39
7885 12:22:55.523606 [Byte1]: 39
7886 12:22:55.527854
7887 12:22:55.527936 Set Vref, RX VrefLevel [Byte0]: 40
7888 12:22:55.531305 [Byte1]: 40
7889 12:22:55.535642
7890 12:22:55.535723 Set Vref, RX VrefLevel [Byte0]: 41
7891 12:22:55.539012 [Byte1]: 41
7892 12:22:55.543194
7893 12:22:55.543279 Set Vref, RX VrefLevel [Byte0]: 42
7894 12:22:55.546466 [Byte1]: 42
7895 12:22:55.550916
7896 12:22:55.550996 Set Vref, RX VrefLevel [Byte0]: 43
7897 12:22:55.554129 [Byte1]: 43
7898 12:22:55.558668
7899 12:22:55.558802 Set Vref, RX VrefLevel [Byte0]: 44
7900 12:22:55.561797 [Byte1]: 44
7901 12:22:55.565868
7902 12:22:55.565954 Set Vref, RX VrefLevel [Byte0]: 45
7903 12:22:55.569787 [Byte1]: 45
7904 12:22:55.573483
7905 12:22:55.573559 Set Vref, RX VrefLevel [Byte0]: 46
7906 12:22:55.577124 [Byte1]: 46
7907 12:22:55.581203
7908 12:22:55.581280 Set Vref, RX VrefLevel [Byte0]: 47
7909 12:22:55.584368 [Byte1]: 47
7910 12:22:55.589585
7911 12:22:55.589663 Set Vref, RX VrefLevel [Byte0]: 48
7912 12:22:55.592099 [Byte1]: 48
7913 12:22:55.596893
7914 12:22:55.596970 Set Vref, RX VrefLevel [Byte0]: 49
7915 12:22:55.599670 [Byte1]: 49
7916 12:22:55.604306
7917 12:22:55.604380 Set Vref, RX VrefLevel [Byte0]: 50
7918 12:22:55.607789 [Byte1]: 50
7919 12:22:55.611987
7920 12:22:55.612067 Set Vref, RX VrefLevel [Byte0]: 51
7921 12:22:55.615249 [Byte1]: 51
7922 12:22:55.619315
7923 12:22:55.619389 Set Vref, RX VrefLevel [Byte0]: 52
7924 12:22:55.623018 [Byte1]: 52
7925 12:22:55.626877
7926 12:22:55.626953 Set Vref, RX VrefLevel [Byte0]: 53
7927 12:22:55.630059 [Byte1]: 53
7928 12:22:55.634697
7929 12:22:55.634819 Set Vref, RX VrefLevel [Byte0]: 54
7930 12:22:55.638026 [Byte1]: 54
7931 12:22:55.642134
7932 12:22:55.645491 Set Vref, RX VrefLevel [Byte0]: 55
7933 12:22:55.645562 [Byte1]: 55
7934 12:22:55.649539
7935 12:22:55.649613 Set Vref, RX VrefLevel [Byte0]: 56
7936 12:22:55.653000 [Byte1]: 56
7937 12:22:55.657280
7938 12:22:55.657358 Set Vref, RX VrefLevel [Byte0]: 57
7939 12:22:55.660762 [Byte1]: 57
7940 12:22:55.665007
7941 12:22:55.665079 Set Vref, RX VrefLevel [Byte0]: 58
7942 12:22:55.668123 [Byte1]: 58
7943 12:22:55.672537
7944 12:22:55.672614 Set Vref, RX VrefLevel [Byte0]: 59
7945 12:22:55.675786 [Byte1]: 59
7946 12:22:55.680475
7947 12:22:55.680557 Set Vref, RX VrefLevel [Byte0]: 60
7948 12:22:55.684126 [Byte1]: 60
7949 12:22:55.687642
7950 12:22:55.687721 Set Vref, RX VrefLevel [Byte0]: 61
7951 12:22:55.690960 [Byte1]: 61
7952 12:22:55.695395
7953 12:22:55.695473 Set Vref, RX VrefLevel [Byte0]: 62
7954 12:22:55.698938 [Byte1]: 62
7955 12:22:55.702908
7956 12:22:55.702989 Set Vref, RX VrefLevel [Byte0]: 63
7957 12:22:55.706497 [Byte1]: 63
7958 12:22:55.711192
7959 12:22:55.711272 Set Vref, RX VrefLevel [Byte0]: 64
7960 12:22:55.713978 [Byte1]: 64
7961 12:22:55.718381
7962 12:22:55.718448 Set Vref, RX VrefLevel [Byte0]: 65
7963 12:22:55.721274 [Byte1]: 65
7964 12:22:55.726045
7965 12:22:55.726123 Set Vref, RX VrefLevel [Byte0]: 66
7966 12:22:55.729379 [Byte1]: 66
7967 12:22:55.733555
7968 12:22:55.733633 Set Vref, RX VrefLevel [Byte0]: 67
7969 12:22:55.737109 [Byte1]: 67
7970 12:22:55.741275
7971 12:22:55.744548 Set Vref, RX VrefLevel [Byte0]: 68
7972 12:22:55.744621 [Byte1]: 68
7973 12:22:55.748519
7974 12:22:55.748586 Set Vref, RX VrefLevel [Byte0]: 69
7975 12:22:55.752039 [Byte1]: 69
7976 12:22:55.756099
7977 12:22:55.756175 Set Vref, RX VrefLevel [Byte0]: 70
7978 12:22:55.759986 [Byte1]: 70
7979 12:22:55.763939
7980 12:22:55.764019 Set Vref, RX VrefLevel [Byte0]: 71
7981 12:22:55.767328 [Byte1]: 71
7982 12:22:55.772024
7983 12:22:55.772110 Set Vref, RX VrefLevel [Byte0]: 72
7984 12:22:55.774580 [Byte1]: 72
7985 12:22:55.779383
7986 12:22:55.779463 Set Vref, RX VrefLevel [Byte0]: 73
7987 12:22:55.782518 [Byte1]: 73
7988 12:22:55.786990
7989 12:22:55.787062 Set Vref, RX VrefLevel [Byte0]: 74
7990 12:22:55.790181 [Byte1]: 74
7991 12:22:55.794561
7992 12:22:55.794666 Set Vref, RX VrefLevel [Byte0]: 75
7993 12:22:55.797689 [Byte1]: 75
7994 12:22:55.802060
7995 12:22:55.802136 Set Vref, RX VrefLevel [Byte0]: 76
7996 12:22:55.805122 [Byte1]: 76
7997 12:22:55.809675
7998 12:22:55.809752 Final RX Vref Byte 0 = 62 to rank0
7999 12:22:55.813026 Final RX Vref Byte 1 = 61 to rank0
8000 12:22:55.816387 Final RX Vref Byte 0 = 62 to rank1
8001 12:22:55.819802 Final RX Vref Byte 1 = 61 to rank1==
8002 12:22:55.822961 Dram Type= 6, Freq= 0, CH_0, rank 0
8003 12:22:55.829360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 12:22:55.829445 ==
8005 12:22:55.829513 DQS Delay:
8006 12:22:55.829573 DQS0 = 0, DQS1 = 0
8007 12:22:55.832718 DQM Delay:
8008 12:22:55.832791 DQM0 = 130, DQM1 = 121
8009 12:22:55.836506 DQ Delay:
8010 12:22:55.839620 DQ0 =130, DQ1 =134, DQ2 =126, DQ3 =126
8011 12:22:55.843065 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8012 12:22:55.846419 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
8013 12:22:55.849577 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8014 12:22:55.849655
8015 12:22:55.849715
8016 12:22:55.849772
8017 12:22:55.853181 [DramC_TX_OE_Calibration] TA2
8018 12:22:55.856539 Original DQ_B0 (3 6) =30, OEN = 27
8019 12:22:55.859816 Original DQ_B1 (3 6) =30, OEN = 27
8020 12:22:55.862984 24, 0x0, End_B0=24 End_B1=24
8021 12:22:55.863087 25, 0x0, End_B0=25 End_B1=25
8022 12:22:55.866314 26, 0x0, End_B0=26 End_B1=26
8023 12:22:55.869738 27, 0x0, End_B0=27 End_B1=27
8024 12:22:55.873247 28, 0x0, End_B0=28 End_B1=28
8025 12:22:55.873317 29, 0x0, End_B0=29 End_B1=29
8026 12:22:55.876579 30, 0x0, End_B0=30 End_B1=30
8027 12:22:55.879394 31, 0x4141, End_B0=30 End_B1=30
8028 12:22:55.882986 Byte0 end_step=30 best_step=27
8029 12:22:55.886251 Byte1 end_step=30 best_step=27
8030 12:22:55.889564 Byte0 TX OE(2T, 0.5T) = (3, 3)
8031 12:22:55.889638 Byte1 TX OE(2T, 0.5T) = (3, 3)
8032 12:22:55.889700
8033 12:22:55.889757
8034 12:22:55.899667 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8035 12:22:55.902827 CH0 RK0: MR19=303, MR18=1307
8036 12:22:55.906884 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
8037 12:22:55.909788
8038 12:22:55.913330 ----->DramcWriteLeveling(PI) begin...
8039 12:22:55.913410 ==
8040 12:22:55.916541 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 12:22:55.920293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 12:22:55.920382 ==
8043 12:22:55.923242 Write leveling (Byte 0): 32 => 32
8044 12:22:55.926400 Write leveling (Byte 1): 26 => 26
8045 12:22:55.929881 DramcWriteLeveling(PI) end<-----
8046 12:22:55.929967
8047 12:22:55.930030 ==
8048 12:22:55.933324 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 12:22:55.936384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 12:22:55.936455 ==
8051 12:22:55.939608 [Gating] SW mode calibration
8052 12:22:55.946212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8053 12:22:55.953102 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8054 12:22:55.956523 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 12:22:55.959699 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 12:22:55.966186 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
8057 12:22:55.970163 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8058 12:22:55.973016 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8059 12:22:55.979343 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8060 12:22:55.982682 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 12:22:55.986114 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 12:22:55.992729 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 12:22:55.996049 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8064 12:22:55.999568 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8065 12:22:56.003400 1 5 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
8066 12:22:56.009452 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8067 12:22:56.013152 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8068 12:22:56.016754 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8069 12:22:56.023249 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 12:22:56.026280 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 12:22:56.030190 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 12:22:56.036488 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8073 12:22:56.039826 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8074 12:22:56.043464 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8075 12:22:56.049906 1 6 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8076 12:22:56.053273 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 12:22:56.056366 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 12:22:56.063043 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 12:22:56.066405 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 12:22:56.069551 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 12:22:56.073368 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8082 12:22:56.079670 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8083 12:22:56.083126 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8084 12:22:56.086652 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 12:22:56.093071 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 12:22:56.096803 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 12:22:56.099997 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 12:22:56.106950 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 12:22:56.110028 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 12:22:56.113336 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 12:22:56.120031 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 12:22:56.123243 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 12:22:56.126665 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:22:56.133863 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 12:22:56.136883 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 12:22:56.140131 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 12:22:56.146698 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8098 12:22:56.150210 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8099 12:22:56.153296 Total UI for P1: 0, mck2ui 16
8100 12:22:56.156913 best dqsien dly found for B0: ( 1, 9, 12)
8101 12:22:56.160249 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8102 12:22:56.163686 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8103 12:22:56.166516 Total UI for P1: 0, mck2ui 16
8104 12:22:56.170014 best dqsien dly found for B1: ( 1, 9, 18)
8105 12:22:56.173196 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8106 12:22:56.176650 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8107 12:22:56.176728
8108 12:22:56.183513 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8109 12:22:56.186628 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8110 12:22:56.189961 [Gating] SW calibration Done
8111 12:22:56.190032 ==
8112 12:22:56.193711 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 12:22:56.196829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 12:22:56.196911 ==
8115 12:22:56.196973 RX Vref Scan: 0
8116 12:22:56.197029
8117 12:22:56.200277 RX Vref 0 -> 0, step: 1
8118 12:22:56.200348
8119 12:22:56.203441 RX Delay 0 -> 252, step: 8
8120 12:22:56.206658 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8121 12:22:56.210069 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8122 12:22:56.214000 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
8123 12:22:56.220567 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8124 12:22:56.223587 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8125 12:22:56.226878 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8126 12:22:56.230633 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8127 12:22:56.234247 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8128 12:22:56.240557 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8129 12:22:56.244165 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8130 12:22:56.247546 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8131 12:22:56.250564 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8132 12:22:56.253745 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8133 12:22:56.260305 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8134 12:22:56.263890 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8135 12:22:56.267334 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8136 12:22:56.267412 ==
8137 12:22:56.270641 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 12:22:56.274013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 12:22:56.274084 ==
8140 12:22:56.277605 DQS Delay:
8141 12:22:56.277675 DQS0 = 0, DQS1 = 0
8142 12:22:56.277738 DQM Delay:
8143 12:22:56.281058 DQM0 = 131, DQM1 = 126
8144 12:22:56.281134 DQ Delay:
8145 12:22:56.283974 DQ0 =131, DQ1 =131, DQ2 =131, DQ3 =127
8146 12:22:56.287360 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8147 12:22:56.294294 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =119
8148 12:22:56.297292 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
8149 12:22:56.297364
8150 12:22:56.297434
8151 12:22:56.297493 ==
8152 12:22:56.300442 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 12:22:56.304001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 12:22:56.304080 ==
8155 12:22:56.304144
8156 12:22:56.304201
8157 12:22:56.307144 TX Vref Scan disable
8158 12:22:56.310871 == TX Byte 0 ==
8159 12:22:56.314371 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8160 12:22:56.317427 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8161 12:22:56.320636 == TX Byte 1 ==
8162 12:22:56.323834 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8163 12:22:56.327156 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8164 12:22:56.327236 ==
8165 12:22:56.330494 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 12:22:56.334180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 12:22:56.334254 ==
8168 12:22:56.349744
8169 12:22:56.353022 TX Vref early break, caculate TX vref
8170 12:22:56.356441 TX Vref=16, minBit 1, minWin=21, winSum=366
8171 12:22:56.359806 TX Vref=18, minBit 9, minWin=22, winSum=379
8172 12:22:56.363562 TX Vref=20, minBit 2, minWin=23, winSum=385
8173 12:22:56.366414 TX Vref=22, minBit 9, minWin=23, winSum=396
8174 12:22:56.369925 TX Vref=24, minBit 1, minWin=24, winSum=404
8175 12:22:56.373191 TX Vref=26, minBit 0, minWin=25, winSum=412
8176 12:22:56.379938 TX Vref=28, minBit 0, minWin=25, winSum=414
8177 12:22:56.383912 TX Vref=30, minBit 0, minWin=25, winSum=415
8178 12:22:56.386875 TX Vref=32, minBit 1, minWin=24, winSum=405
8179 12:22:56.390129 TX Vref=34, minBit 7, minWin=23, winSum=398
8180 12:22:56.393592 TX Vref=36, minBit 0, minWin=23, winSum=390
8181 12:22:56.400123 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 30
8182 12:22:56.400219
8183 12:22:56.403055 Final TX Range 0 Vref 30
8184 12:22:56.403126
8185 12:22:56.403193 ==
8186 12:22:56.406677 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 12:22:56.409725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 12:22:56.409827 ==
8189 12:22:56.409915
8190 12:22:56.410011
8191 12:22:56.413000 TX Vref Scan disable
8192 12:22:56.419833 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8193 12:22:56.419919 == TX Byte 0 ==
8194 12:22:56.423226 u2DelayCellOfst[0]=17 cells (5 PI)
8195 12:22:56.426560 u2DelayCellOfst[1]=21 cells (6 PI)
8196 12:22:56.429736 u2DelayCellOfst[2]=10 cells (3 PI)
8197 12:22:56.433175 u2DelayCellOfst[3]=14 cells (4 PI)
8198 12:22:56.436782 u2DelayCellOfst[4]=10 cells (3 PI)
8199 12:22:56.440162 u2DelayCellOfst[5]=0 cells (0 PI)
8200 12:22:56.443126 u2DelayCellOfst[6]=17 cells (5 PI)
8201 12:22:56.446571 u2DelayCellOfst[7]=21 cells (6 PI)
8202 12:22:56.449542 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8203 12:22:56.453379 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8204 12:22:56.456326 == TX Byte 1 ==
8205 12:22:56.460037 u2DelayCellOfst[8]=0 cells (0 PI)
8206 12:22:56.460118 u2DelayCellOfst[9]=0 cells (0 PI)
8207 12:22:56.463278 u2DelayCellOfst[10]=7 cells (2 PI)
8208 12:22:56.466476 u2DelayCellOfst[11]=0 cells (0 PI)
8209 12:22:56.469510 u2DelayCellOfst[12]=10 cells (3 PI)
8210 12:22:56.473088 u2DelayCellOfst[13]=10 cells (3 PI)
8211 12:22:56.476493 u2DelayCellOfst[14]=14 cells (4 PI)
8212 12:22:56.480337 u2DelayCellOfst[15]=10 cells (3 PI)
8213 12:22:56.483543 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8214 12:22:56.490178 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8215 12:22:56.490259 DramC Write-DBI on
8216 12:22:56.490323 ==
8217 12:22:56.493741 Dram Type= 6, Freq= 0, CH_0, rank 1
8218 12:22:56.496518 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8219 12:22:56.496600 ==
8220 12:22:56.499840
8221 12:22:56.499921
8222 12:22:56.499985 TX Vref Scan disable
8223 12:22:56.503306 == TX Byte 0 ==
8224 12:22:56.506442 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8225 12:22:56.509863 == TX Byte 1 ==
8226 12:22:56.513405 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8227 12:22:56.516672 DramC Write-DBI off
8228 12:22:56.516753
8229 12:22:56.516817 [DATLAT]
8230 12:22:56.516876 Freq=1600, CH0 RK1
8231 12:22:56.516934
8232 12:22:56.519796 DATLAT Default: 0xf
8233 12:22:56.519878 0, 0xFFFF, sum = 0
8234 12:22:56.523627 1, 0xFFFF, sum = 0
8235 12:22:56.523710 2, 0xFFFF, sum = 0
8236 12:22:56.526658 3, 0xFFFF, sum = 0
8237 12:22:56.529919 4, 0xFFFF, sum = 0
8238 12:22:56.530002 5, 0xFFFF, sum = 0
8239 12:22:56.533547 6, 0xFFFF, sum = 0
8240 12:22:56.533630 7, 0xFFFF, sum = 0
8241 12:22:56.536669 8, 0xFFFF, sum = 0
8242 12:22:56.536751 9, 0xFFFF, sum = 0
8243 12:22:56.540375 10, 0xFFFF, sum = 0
8244 12:22:56.540458 11, 0xFFFF, sum = 0
8245 12:22:56.543296 12, 0xFFFF, sum = 0
8246 12:22:56.543378 13, 0xFFFF, sum = 0
8247 12:22:56.546844 14, 0x0, sum = 1
8248 12:22:56.546926 15, 0x0, sum = 2
8249 12:22:56.550042 16, 0x0, sum = 3
8250 12:22:56.550124 17, 0x0, sum = 4
8251 12:22:56.553659 best_step = 15
8252 12:22:56.553740
8253 12:22:56.553804 ==
8254 12:22:56.556928 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 12:22:56.560447 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 12:22:56.560529 ==
8257 12:22:56.560594 RX Vref Scan: 0
8258 12:22:56.560653
8259 12:22:56.563641 RX Vref 0 -> 0, step: 1
8260 12:22:56.563723
8261 12:22:56.567016 RX Delay 11 -> 252, step: 4
8262 12:22:56.570394 iDelay=191, Bit 0, Center 128 (71 ~ 186) 116
8263 12:22:56.576691 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8264 12:22:56.579923 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8265 12:22:56.583334 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8266 12:22:56.586620 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8267 12:22:56.589971 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8268 12:22:56.593587 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8269 12:22:56.600004 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8270 12:22:56.603498 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8271 12:22:56.607012 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8272 12:22:56.610089 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8273 12:22:56.613564 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8274 12:22:56.620079 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8275 12:22:56.623471 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8276 12:22:56.627037 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8277 12:22:56.630329 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8278 12:22:56.630411 ==
8279 12:22:56.633473 Dram Type= 6, Freq= 0, CH_0, rank 1
8280 12:22:56.640214 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 12:22:56.640295 ==
8282 12:22:56.640359 DQS Delay:
8283 12:22:56.640420 DQS0 = 0, DQS1 = 0
8284 12:22:56.643468 DQM Delay:
8285 12:22:56.643549 DQM0 = 128, DQM1 = 122
8286 12:22:56.646986 DQ Delay:
8287 12:22:56.650090 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8288 12:22:56.653981 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8289 12:22:56.657025 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8290 12:22:56.660203 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8291 12:22:56.660284
8292 12:22:56.660348
8293 12:22:56.660407
8294 12:22:56.663953 [DramC_TX_OE_Calibration] TA2
8295 12:22:56.667227 Original DQ_B0 (3 6) =30, OEN = 27
8296 12:22:56.670406 Original DQ_B1 (3 6) =30, OEN = 27
8297 12:22:56.674115 24, 0x0, End_B0=24 End_B1=24
8298 12:22:56.674198 25, 0x0, End_B0=25 End_B1=25
8299 12:22:56.677073 26, 0x0, End_B0=26 End_B1=26
8300 12:22:56.680549 27, 0x0, End_B0=27 End_B1=27
8301 12:22:56.683897 28, 0x0, End_B0=28 End_B1=28
8302 12:22:56.683989 29, 0x0, End_B0=29 End_B1=29
8303 12:22:56.687418 30, 0x0, End_B0=30 End_B1=30
8304 12:22:56.690332 31, 0x4545, End_B0=30 End_B1=30
8305 12:22:56.693547 Byte0 end_step=30 best_step=27
8306 12:22:56.697388 Byte1 end_step=30 best_step=27
8307 12:22:56.700360 Byte0 TX OE(2T, 0.5T) = (3, 3)
8308 12:22:56.700436 Byte1 TX OE(2T, 0.5T) = (3, 3)
8309 12:22:56.700509
8310 12:22:56.700568
8311 12:22:56.710642 [DQSOSCAuto] RK1, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
8312 12:22:56.714122 CH0 RK1: MR19=303, MR18=190E
8313 12:22:56.720315 CH0_RK1: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
8314 12:22:56.720395 [RxdqsGatingPostProcess] freq 1600
8315 12:22:56.726930 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8316 12:22:56.730364 best DQS0 dly(2T, 0.5T) = (1, 1)
8317 12:22:56.733678 best DQS1 dly(2T, 0.5T) = (1, 1)
8318 12:22:56.737146 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8319 12:22:56.740661 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8320 12:22:56.743643 best DQS0 dly(2T, 0.5T) = (1, 1)
8321 12:22:56.747668 best DQS1 dly(2T, 0.5T) = (1, 1)
8322 12:22:56.747743 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8323 12:22:56.750415 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8324 12:22:56.754079 Pre-setting of DQS Precalculation
8325 12:22:56.760768 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8326 12:22:56.760842 ==
8327 12:22:56.763938 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 12:22:56.767788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 12:22:56.767858 ==
8330 12:22:56.774307 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8331 12:22:56.777789 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8332 12:22:56.780655 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8333 12:22:56.788193 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8334 12:22:56.796356 [CA 0] Center 42 (14~71) winsize 58
8335 12:22:56.800020 [CA 1] Center 42 (13~72) winsize 60
8336 12:22:56.803089 [CA 2] Center 37 (9~66) winsize 58
8337 12:22:56.806468 [CA 3] Center 36 (8~65) winsize 58
8338 12:22:56.809938 [CA 4] Center 37 (8~66) winsize 59
8339 12:22:56.813326 [CA 5] Center 36 (7~66) winsize 60
8340 12:22:56.813409
8341 12:22:56.816683 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8342 12:22:56.816757
8343 12:22:56.819916 [CATrainingPosCal] consider 1 rank data
8344 12:22:56.823435 u2DelayCellTimex100 = 275/100 ps
8345 12:22:56.826266 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8346 12:22:56.833106 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8347 12:22:56.836690 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8348 12:22:56.840145 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8349 12:22:56.843080 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8350 12:22:56.846368 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8351 12:22:56.846443
8352 12:22:56.850204 CA PerBit enable=1, Macro0, CA PI delay=36
8353 12:22:56.850275
8354 12:22:56.853218 [CBTSetCACLKResult] CA Dly = 36
8355 12:22:56.853307 CS Dly: 9 (0~40)
8356 12:22:56.859672 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8357 12:22:56.863097 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8358 12:22:56.863177 ==
8359 12:22:56.866706 Dram Type= 6, Freq= 0, CH_1, rank 1
8360 12:22:56.869736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8361 12:22:56.869820 ==
8362 12:22:56.876777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8363 12:22:56.879905 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8364 12:22:56.883328 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8365 12:22:56.890065 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8366 12:22:56.900126 [CA 0] Center 42 (13~72) winsize 60
8367 12:22:56.902843 [CA 1] Center 42 (13~71) winsize 59
8368 12:22:56.906081 [CA 2] Center 37 (9~66) winsize 58
8369 12:22:56.909575 [CA 3] Center 37 (8~66) winsize 59
8370 12:22:56.912969 [CA 4] Center 37 (8~67) winsize 60
8371 12:22:56.916072 [CA 5] Center 36 (7~66) winsize 60
8372 12:22:56.916151
8373 12:22:56.919957 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8374 12:22:56.920054
8375 12:22:56.923221 [CATrainingPosCal] consider 2 rank data
8376 12:22:56.926157 u2DelayCellTimex100 = 275/100 ps
8377 12:22:56.929674 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8378 12:22:56.936414 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8379 12:22:56.939751 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8380 12:22:56.942893 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8381 12:22:56.946220 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8382 12:22:56.949851 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8383 12:22:56.949931
8384 12:22:56.953109 CA PerBit enable=1, Macro0, CA PI delay=36
8385 12:22:56.953188
8386 12:22:56.956028 [CBTSetCACLKResult] CA Dly = 36
8387 12:22:56.956107 CS Dly: 10 (0~43)
8388 12:22:56.962775 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8389 12:22:56.966408 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8390 12:22:56.966512
8391 12:22:56.969287 ----->DramcWriteLeveling(PI) begin...
8392 12:22:56.969367 ==
8393 12:22:56.972937 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 12:22:56.976432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 12:22:56.979153 ==
8396 12:22:56.979232 Write leveling (Byte 0): 25 => 25
8397 12:22:56.982542 Write leveling (Byte 1): 26 => 26
8398 12:22:56.986103 DramcWriteLeveling(PI) end<-----
8399 12:22:56.986183
8400 12:22:56.986245 ==
8401 12:22:56.989575 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 12:22:56.995973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 12:22:56.996053 ==
8404 12:22:56.996116 [Gating] SW mode calibration
8405 12:22:57.006229 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8406 12:22:57.009262 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8407 12:22:57.012631 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 12:22:57.019400 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 12:22:57.023230 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 12:22:57.026283 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 12:22:57.032891 1 4 16 | B1->B0 | 2f2f 2929 | 1 1 | (1 1) (1 1)
8412 12:22:57.035768 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 12:22:57.039430 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 12:22:57.046226 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 12:22:57.049668 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 12:22:57.053020 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 12:22:57.059387 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 12:22:57.062497 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8419 12:22:57.066168 1 5 16 | B1->B0 | 2d2d 3131 | 0 0 | (0 1) (0 1)
8420 12:22:57.072741 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8421 12:22:57.075963 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 12:22:57.079579 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 12:22:57.086157 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 12:22:57.089717 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 12:22:57.092556 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 12:22:57.099371 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 12:22:57.102665 1 6 16 | B1->B0 | 3d3d 2d2d | 0 0 | (0 0) (0 0)
8428 12:22:57.106026 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 12:22:57.109427 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 12:22:57.116286 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 12:22:57.119342 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 12:22:57.122644 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 12:22:57.129379 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 12:22:57.132521 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8435 12:22:57.135813 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8436 12:22:57.142604 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8437 12:22:57.146370 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 12:22:57.149515 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 12:22:57.155986 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 12:22:57.159580 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 12:22:57.162878 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 12:22:57.169343 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 12:22:57.172540 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 12:22:57.176015 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 12:22:57.182752 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 12:22:57.186349 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 12:22:57.189305 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 12:22:57.193106 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 12:22:57.199259 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 12:22:57.202772 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8451 12:22:57.206469 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8452 12:22:57.212574 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8453 12:22:57.216363 Total UI for P1: 0, mck2ui 16
8454 12:22:57.219303 best dqsien dly found for B0: ( 1, 9, 14)
8455 12:22:57.219375 Total UI for P1: 0, mck2ui 16
8456 12:22:57.225984 best dqsien dly found for B1: ( 1, 9, 16)
8457 12:22:57.229161 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8458 12:22:57.233067 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8459 12:22:57.233144
8460 12:22:57.236218 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8461 12:22:57.239285 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8462 12:22:57.242485 [Gating] SW calibration Done
8463 12:22:57.242558 ==
8464 12:22:57.246160 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 12:22:57.249382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 12:22:57.249465 ==
8467 12:22:57.252536 RX Vref Scan: 0
8468 12:22:57.252615
8469 12:22:57.252678 RX Vref 0 -> 0, step: 1
8470 12:22:57.256199
8471 12:22:57.256278 RX Delay 0 -> 252, step: 8
8472 12:22:57.259714 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8473 12:22:57.266006 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8474 12:22:57.269611 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8475 12:22:57.272894 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8476 12:22:57.276350 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8477 12:22:57.279539 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8478 12:22:57.286278 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8479 12:22:57.289699 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8480 12:22:57.292881 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8481 12:22:57.296180 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8482 12:22:57.299691 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8483 12:22:57.306604 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8484 12:22:57.309427 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8485 12:22:57.312911 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8486 12:22:57.316544 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8487 12:22:57.319544 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8488 12:22:57.319619 ==
8489 12:22:57.323154 Dram Type= 6, Freq= 0, CH_1, rank 0
8490 12:22:57.329804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8491 12:22:57.329881 ==
8492 12:22:57.329942 DQS Delay:
8493 12:22:57.333135 DQS0 = 0, DQS1 = 0
8494 12:22:57.333205 DQM Delay:
8495 12:22:57.336163 DQM0 = 134, DQM1 = 127
8496 12:22:57.336258 DQ Delay:
8497 12:22:57.339377 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8498 12:22:57.342948 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8499 12:22:57.346131 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8500 12:22:57.349482 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8501 12:22:57.349555
8502 12:22:57.349615
8503 12:22:57.349672 ==
8504 12:22:57.353212 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 12:22:57.359644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 12:22:57.359718 ==
8507 12:22:57.359779
8508 12:22:57.359835
8509 12:22:57.359889 TX Vref Scan disable
8510 12:22:57.362877 == TX Byte 0 ==
8511 12:22:57.366372 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8512 12:22:57.369465 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8513 12:22:57.373304 == TX Byte 1 ==
8514 12:22:57.376069 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8515 12:22:57.379771 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8516 12:22:57.382598 ==
8517 12:22:57.386399 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 12:22:57.389570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 12:22:57.389659 ==
8520 12:22:57.402429
8521 12:22:57.405746 TX Vref early break, caculate TX vref
8522 12:22:57.409467 TX Vref=16, minBit 8, minWin=21, winSum=370
8523 12:22:57.412987 TX Vref=18, minBit 11, minWin=22, winSum=378
8524 12:22:57.416480 TX Vref=20, minBit 5, minWin=23, winSum=390
8525 12:22:57.419523 TX Vref=22, minBit 5, minWin=23, winSum=398
8526 12:22:57.422509 TX Vref=24, minBit 5, minWin=24, winSum=410
8527 12:22:57.429391 TX Vref=26, minBit 8, minWin=25, winSum=420
8528 12:22:57.432582 TX Vref=28, minBit 5, minWin=25, winSum=425
8529 12:22:57.436178 TX Vref=30, minBit 1, minWin=25, winSum=423
8530 12:22:57.439223 TX Vref=32, minBit 3, minWin=24, winSum=413
8531 12:22:57.442913 TX Vref=34, minBit 3, minWin=24, winSum=404
8532 12:22:57.445866 TX Vref=36, minBit 0, minWin=24, winSum=393
8533 12:22:57.452658 [TxChooseVref] Worse bit 5, Min win 25, Win sum 425, Final Vref 28
8534 12:22:57.452738
8535 12:22:57.456223 Final TX Range 0 Vref 28
8536 12:22:57.456295
8537 12:22:57.456356 ==
8538 12:22:57.459627 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 12:22:57.462938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 12:22:57.463008 ==
8541 12:22:57.463067
8542 12:22:57.463124
8543 12:22:57.465924 TX Vref Scan disable
8544 12:22:57.472791 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8545 12:22:57.472871 == TX Byte 0 ==
8546 12:22:57.475976 u2DelayCellOfst[0]=17 cells (5 PI)
8547 12:22:57.479591 u2DelayCellOfst[1]=10 cells (3 PI)
8548 12:22:57.482925 u2DelayCellOfst[2]=0 cells (0 PI)
8549 12:22:57.486322 u2DelayCellOfst[3]=7 cells (2 PI)
8550 12:22:57.489990 u2DelayCellOfst[4]=7 cells (2 PI)
8551 12:22:57.493119 u2DelayCellOfst[5]=17 cells (5 PI)
8552 12:22:57.496329 u2DelayCellOfst[6]=17 cells (5 PI)
8553 12:22:57.496414 u2DelayCellOfst[7]=7 cells (2 PI)
8554 12:22:57.503016 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8555 12:22:57.506564 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8556 12:22:57.506666 == TX Byte 1 ==
8557 12:22:57.509686 u2DelayCellOfst[8]=0 cells (0 PI)
8558 12:22:57.512890 u2DelayCellOfst[9]=3 cells (1 PI)
8559 12:22:57.516055 u2DelayCellOfst[10]=10 cells (3 PI)
8560 12:22:57.519440 u2DelayCellOfst[11]=7 cells (2 PI)
8561 12:22:57.522873 u2DelayCellOfst[12]=14 cells (4 PI)
8562 12:22:57.526473 u2DelayCellOfst[13]=14 cells (4 PI)
8563 12:22:57.529839 u2DelayCellOfst[14]=17 cells (5 PI)
8564 12:22:57.533358 u2DelayCellOfst[15]=17 cells (5 PI)
8565 12:22:57.536618 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8566 12:22:57.540068 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8567 12:22:57.543054 DramC Write-DBI on
8568 12:22:57.543133 ==
8569 12:22:57.546342 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 12:22:57.549918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 12:22:57.549998 ==
8572 12:22:57.550061
8573 12:22:57.550118
8574 12:22:57.553270 TX Vref Scan disable
8575 12:22:57.556405 == TX Byte 0 ==
8576 12:22:57.559455 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8577 12:22:57.562844 == TX Byte 1 ==
8578 12:22:57.566116 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8579 12:22:57.566222 DramC Write-DBI off
8580 12:22:57.566314
8581 12:22:57.569553 [DATLAT]
8582 12:22:57.569624 Freq=1600, CH1 RK0
8583 12:22:57.569683
8584 12:22:57.573169 DATLAT Default: 0xf
8585 12:22:57.573248 0, 0xFFFF, sum = 0
8586 12:22:57.576393 1, 0xFFFF, sum = 0
8587 12:22:57.576475 2, 0xFFFF, sum = 0
8588 12:22:57.579687 3, 0xFFFF, sum = 0
8589 12:22:57.579769 4, 0xFFFF, sum = 0
8590 12:22:57.583224 5, 0xFFFF, sum = 0
8591 12:22:57.583305 6, 0xFFFF, sum = 0
8592 12:22:57.586135 7, 0xFFFF, sum = 0
8593 12:22:57.586216 8, 0xFFFF, sum = 0
8594 12:22:57.589993 9, 0xFFFF, sum = 0
8595 12:22:57.590074 10, 0xFFFF, sum = 0
8596 12:22:57.593447 11, 0xFFFF, sum = 0
8597 12:22:57.596164 12, 0xFFFF, sum = 0
8598 12:22:57.596245 13, 0xFFFF, sum = 0
8599 12:22:57.599935 14, 0x0, sum = 1
8600 12:22:57.600016 15, 0x0, sum = 2
8601 12:22:57.600080 16, 0x0, sum = 3
8602 12:22:57.603349 17, 0x0, sum = 4
8603 12:22:57.603429 best_step = 15
8604 12:22:57.603492
8605 12:22:57.606437 ==
8606 12:22:57.606545 Dram Type= 6, Freq= 0, CH_1, rank 0
8607 12:22:57.613327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8608 12:22:57.613408 ==
8609 12:22:57.613471 RX Vref Scan: 1
8610 12:22:57.613530
8611 12:22:57.616264 Set Vref Range= 24 -> 127
8612 12:22:57.616343
8613 12:22:57.619638 RX Vref 24 -> 127, step: 1
8614 12:22:57.619719
8615 12:22:57.622753 RX Delay 19 -> 252, step: 4
8616 12:22:57.622846
8617 12:22:57.626544 Set Vref, RX VrefLevel [Byte0]: 24
8618 12:22:57.629702 [Byte1]: 24
8619 12:22:57.629782
8620 12:22:57.633195 Set Vref, RX VrefLevel [Byte0]: 25
8621 12:22:57.636679 [Byte1]: 25
8622 12:22:57.636759
8623 12:22:57.639736 Set Vref, RX VrefLevel [Byte0]: 26
8624 12:22:57.643239 [Byte1]: 26
8625 12:22:57.643319
8626 12:22:57.646609 Set Vref, RX VrefLevel [Byte0]: 27
8627 12:22:57.649551 [Byte1]: 27
8628 12:22:57.653638
8629 12:22:57.653725 Set Vref, RX VrefLevel [Byte0]: 28
8630 12:22:57.656915 [Byte1]: 28
8631 12:22:57.661537
8632 12:22:57.661616 Set Vref, RX VrefLevel [Byte0]: 29
8633 12:22:57.664300 [Byte1]: 29
8634 12:22:57.668979
8635 12:22:57.669059 Set Vref, RX VrefLevel [Byte0]: 30
8636 12:22:57.672110 [Byte1]: 30
8637 12:22:57.676355
8638 12:22:57.676434 Set Vref, RX VrefLevel [Byte0]: 31
8639 12:22:57.679523 [Byte1]: 31
8640 12:22:57.683969
8641 12:22:57.684048 Set Vref, RX VrefLevel [Byte0]: 32
8642 12:22:57.686990 [Byte1]: 32
8643 12:22:57.691420
8644 12:22:57.691499 Set Vref, RX VrefLevel [Byte0]: 33
8645 12:22:57.695036 [Byte1]: 33
8646 12:22:57.698958
8647 12:22:57.699037 Set Vref, RX VrefLevel [Byte0]: 34
8648 12:22:57.702231 [Byte1]: 34
8649 12:22:57.706866
8650 12:22:57.706946 Set Vref, RX VrefLevel [Byte0]: 35
8651 12:22:57.709791 [Byte1]: 35
8652 12:22:57.714528
8653 12:22:57.714633 Set Vref, RX VrefLevel [Byte0]: 36
8654 12:22:57.717546 [Byte1]: 36
8655 12:22:57.721818
8656 12:22:57.721908 Set Vref, RX VrefLevel [Byte0]: 37
8657 12:22:57.724987 [Byte1]: 37
8658 12:22:57.729444
8659 12:22:57.729523 Set Vref, RX VrefLevel [Byte0]: 38
8660 12:22:57.732737 [Byte1]: 38
8661 12:22:57.737298
8662 12:22:57.737377 Set Vref, RX VrefLevel [Byte0]: 39
8663 12:22:57.740335 [Byte1]: 39
8664 12:22:57.744523
8665 12:22:57.744671 Set Vref, RX VrefLevel [Byte0]: 40
8666 12:22:57.747954 [Byte1]: 40
8667 12:22:57.752123
8668 12:22:57.752202 Set Vref, RX VrefLevel [Byte0]: 41
8669 12:22:57.755220 [Byte1]: 41
8670 12:22:57.759449
8671 12:22:57.759534 Set Vref, RX VrefLevel [Byte0]: 42
8672 12:22:57.762939 [Byte1]: 42
8673 12:22:57.767539
8674 12:22:57.767613 Set Vref, RX VrefLevel [Byte0]: 43
8675 12:22:57.770410 [Byte1]: 43
8676 12:22:57.774973
8677 12:22:57.775045 Set Vref, RX VrefLevel [Byte0]: 44
8678 12:22:57.777866 [Byte1]: 44
8679 12:22:57.782626
8680 12:22:57.782741 Set Vref, RX VrefLevel [Byte0]: 45
8681 12:22:57.785697 [Byte1]: 45
8682 12:22:57.789944
8683 12:22:57.790027 Set Vref, RX VrefLevel [Byte0]: 46
8684 12:22:57.793011 [Byte1]: 46
8685 12:22:57.797645
8686 12:22:57.797717 Set Vref, RX VrefLevel [Byte0]: 47
8687 12:22:57.800856 [Byte1]: 47
8688 12:22:57.804858
8689 12:22:57.804934 Set Vref, RX VrefLevel [Byte0]: 48
8690 12:22:57.808504 [Byte1]: 48
8691 12:22:57.812465
8692 12:22:57.812538 Set Vref, RX VrefLevel [Byte0]: 49
8693 12:22:57.815806 [Byte1]: 49
8694 12:22:57.820056
8695 12:22:57.820132 Set Vref, RX VrefLevel [Byte0]: 50
8696 12:22:57.823498 [Byte1]: 50
8697 12:22:57.828047
8698 12:22:57.828121 Set Vref, RX VrefLevel [Byte0]: 51
8699 12:22:57.831339 [Byte1]: 51
8700 12:22:57.835355
8701 12:22:57.835438 Set Vref, RX VrefLevel [Byte0]: 52
8702 12:22:57.838461 [Byte1]: 52
8703 12:22:57.842614
8704 12:22:57.842734 Set Vref, RX VrefLevel [Byte0]: 53
8705 12:22:57.846201 [Byte1]: 53
8706 12:22:57.850484
8707 12:22:57.850586 Set Vref, RX VrefLevel [Byte0]: 54
8708 12:22:57.853678 [Byte1]: 54
8709 12:22:57.858123
8710 12:22:57.858205 Set Vref, RX VrefLevel [Byte0]: 55
8711 12:22:57.861435 [Byte1]: 55
8712 12:22:57.865563
8713 12:22:57.865638 Set Vref, RX VrefLevel [Byte0]: 56
8714 12:22:57.869351 [Byte1]: 56
8715 12:22:57.873205
8716 12:22:57.873284 Set Vref, RX VrefLevel [Byte0]: 57
8717 12:22:57.876695 [Byte1]: 57
8718 12:22:57.880847
8719 12:22:57.880931 Set Vref, RX VrefLevel [Byte0]: 58
8720 12:22:57.884007 [Byte1]: 58
8721 12:22:57.888653
8722 12:22:57.888728 Set Vref, RX VrefLevel [Byte0]: 59
8723 12:22:57.891987 [Byte1]: 59
8724 12:22:57.896066
8725 12:22:57.896140 Set Vref, RX VrefLevel [Byte0]: 60
8726 12:22:57.899384 [Byte1]: 60
8727 12:22:57.903648
8728 12:22:57.903722 Set Vref, RX VrefLevel [Byte0]: 61
8729 12:22:57.906595 [Byte1]: 61
8730 12:22:57.911058
8731 12:22:57.911137 Set Vref, RX VrefLevel [Byte0]: 62
8732 12:22:57.914387 [Byte1]: 62
8733 12:22:57.918533
8734 12:22:57.918649 Set Vref, RX VrefLevel [Byte0]: 63
8735 12:22:57.921972 [Byte1]: 63
8736 12:22:57.926667
8737 12:22:57.926800 Set Vref, RX VrefLevel [Byte0]: 64
8738 12:22:57.929439 [Byte1]: 64
8739 12:22:57.934028
8740 12:22:57.934108 Set Vref, RX VrefLevel [Byte0]: 65
8741 12:22:57.936850 [Byte1]: 65
8742 12:22:57.941205
8743 12:22:57.941284 Set Vref, RX VrefLevel [Byte0]: 66
8744 12:22:57.944458 [Byte1]: 66
8745 12:22:57.949058
8746 12:22:57.949137 Set Vref, RX VrefLevel [Byte0]: 67
8747 12:22:57.952685 [Byte1]: 67
8748 12:22:57.956550
8749 12:22:57.956629 Set Vref, RX VrefLevel [Byte0]: 68
8750 12:22:57.959848 [Byte1]: 68
8751 12:22:57.964155
8752 12:22:57.964233 Set Vref, RX VrefLevel [Byte0]: 69
8753 12:22:57.967091 [Byte1]: 69
8754 12:22:57.972050
8755 12:22:57.972129 Set Vref, RX VrefLevel [Byte0]: 70
8756 12:22:57.974931 [Byte1]: 70
8757 12:22:57.979248
8758 12:22:57.979327 Set Vref, RX VrefLevel [Byte0]: 71
8759 12:22:57.982888 [Byte1]: 71
8760 12:22:57.987475
8761 12:22:57.987554 Set Vref, RX VrefLevel [Byte0]: 72
8762 12:22:57.990490 [Byte1]: 72
8763 12:22:57.994476
8764 12:22:57.994555 Set Vref, RX VrefLevel [Byte0]: 73
8765 12:22:57.997743 [Byte1]: 73
8766 12:22:58.001875
8767 12:22:58.001955 Set Vref, RX VrefLevel [Byte0]: 74
8768 12:22:58.005333 [Byte1]: 74
8769 12:22:58.009298
8770 12:22:58.009378 Final RX Vref Byte 0 = 58 to rank0
8771 12:22:58.012750 Final RX Vref Byte 1 = 59 to rank0
8772 12:22:58.016168 Final RX Vref Byte 0 = 58 to rank1
8773 12:22:58.019495 Final RX Vref Byte 1 = 59 to rank1==
8774 12:22:58.023121 Dram Type= 6, Freq= 0, CH_1, rank 0
8775 12:22:58.029330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 12:22:58.029411 ==
8777 12:22:58.029475 DQS Delay:
8778 12:22:58.029534 DQS0 = 0, DQS1 = 0
8779 12:22:58.033244 DQM Delay:
8780 12:22:58.033323 DQM0 = 131, DQM1 = 124
8781 12:22:58.036050 DQ Delay:
8782 12:22:58.039389 DQ0 =134, DQ1 =124, DQ2 =120, DQ3 =130
8783 12:22:58.042725 DQ4 =130, DQ5 =142, DQ6 =144, DQ7 =128
8784 12:22:58.045959 DQ8 =110, DQ9 =112, DQ10 =126, DQ11 =118
8785 12:22:58.049487 DQ12 =134, DQ13 =132, DQ14 =130, DQ15 =132
8786 12:22:58.049585
8787 12:22:58.049666
8788 12:22:58.049724
8789 12:22:58.052728 [DramC_TX_OE_Calibration] TA2
8790 12:22:58.056181 Original DQ_B0 (3 6) =30, OEN = 27
8791 12:22:58.059603 Original DQ_B1 (3 6) =30, OEN = 27
8792 12:22:58.062791 24, 0x0, End_B0=24 End_B1=24
8793 12:22:58.062864 25, 0x0, End_B0=25 End_B1=25
8794 12:22:58.066319 26, 0x0, End_B0=26 End_B1=26
8795 12:22:58.069445 27, 0x0, End_B0=27 End_B1=27
8796 12:22:58.072942 28, 0x0, End_B0=28 End_B1=28
8797 12:22:58.073041 29, 0x0, End_B0=29 End_B1=29
8798 12:22:58.076474 30, 0x0, End_B0=30 End_B1=30
8799 12:22:58.079227 31, 0x4141, End_B0=30 End_B1=30
8800 12:22:58.083072 Byte0 end_step=30 best_step=27
8801 12:22:58.085861 Byte1 end_step=30 best_step=27
8802 12:22:58.089403 Byte0 TX OE(2T, 0.5T) = (3, 3)
8803 12:22:58.089500 Byte1 TX OE(2T, 0.5T) = (3, 3)
8804 12:22:58.089586
8805 12:22:58.092867
8806 12:22:58.099461 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8807 12:22:58.102766 CH1 RK0: MR19=303, MR18=1600
8808 12:22:58.109205 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8809 12:22:58.109295
8810 12:22:58.112817 ----->DramcWriteLeveling(PI) begin...
8811 12:22:58.112888 ==
8812 12:22:58.116090 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 12:22:58.119217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 12:22:58.119289 ==
8815 12:22:58.122620 Write leveling (Byte 0): 23 => 23
8816 12:22:58.125925 Write leveling (Byte 1): 25 => 25
8817 12:22:58.129720 DramcWriteLeveling(PI) end<-----
8818 12:22:58.129816
8819 12:22:58.129911 ==
8820 12:22:58.132871 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 12:22:58.136363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 12:22:58.136432 ==
8823 12:22:58.139648 [Gating] SW mode calibration
8824 12:22:58.146085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8825 12:22:58.152598 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8826 12:22:58.156480 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 12:22:58.159531 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 12:22:58.166068 1 4 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
8829 12:22:58.169449 1 4 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
8830 12:22:58.173034 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 12:22:58.180075 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 12:22:58.182643 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 12:22:58.186000 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 12:22:58.189533 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 12:22:58.196423 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8836 12:22:58.199483 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
8837 12:22:58.202926 1 5 12 | B1->B0 | 3030 2626 | 1 0 | (1 0) (0 0)
8838 12:22:58.209804 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8839 12:22:58.212706 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 12:22:58.216392 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 12:22:58.223046 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 12:22:58.226275 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 12:22:58.229913 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 12:22:58.236331 1 6 8 | B1->B0 | 2424 3d3d | 0 1 | (0 0) (0 0)
8845 12:22:58.239557 1 6 12 | B1->B0 | 3636 4545 | 1 0 | (0 0) (0 0)
8846 12:22:58.243384 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 12:22:58.249689 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:22:58.253262 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 12:22:58.256355 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 12:22:58.262999 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 12:22:58.266379 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 12:22:58.270350 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8853 12:22:58.273270 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8854 12:22:58.279818 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8855 12:22:58.283338 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:22:58.286866 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:22:58.293599 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:22:58.296570 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:22:58.300334 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:22:58.306625 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:22:58.310347 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:22:58.313684 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:22:58.320338 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:22:58.323660 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 12:22:58.326856 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 12:22:58.333730 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 12:22:58.336780 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 12:22:58.340315 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8869 12:22:58.343915 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8870 12:22:58.346640 Total UI for P1: 0, mck2ui 16
8871 12:22:58.349980 best dqsien dly found for B0: ( 1, 9, 8)
8872 12:22:58.357128 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8873 12:22:58.357209 Total UI for P1: 0, mck2ui 16
8874 12:22:58.363513 best dqsien dly found for B1: ( 1, 9, 10)
8875 12:22:58.367341 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8876 12:22:58.370286 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8877 12:22:58.370366
8878 12:22:58.374288 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8879 12:22:58.377163 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8880 12:22:58.380731 [Gating] SW calibration Done
8881 12:22:58.380811 ==
8882 12:22:58.384018 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 12:22:58.387011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 12:22:58.387091 ==
8885 12:22:58.390543 RX Vref Scan: 0
8886 12:22:58.390629
8887 12:22:58.390692 RX Vref 0 -> 0, step: 1
8888 12:22:58.390789
8889 12:22:58.393659 RX Delay 0 -> 252, step: 8
8890 12:22:58.397122 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8891 12:22:58.403756 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8892 12:22:58.406690 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8893 12:22:58.410238 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8894 12:22:58.414026 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8895 12:22:58.416766 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8896 12:22:58.420096 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8897 12:22:58.427230 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8898 12:22:58.430191 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8899 12:22:58.433915 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8900 12:22:58.436846 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8901 12:22:58.440246 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8902 12:22:58.447376 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8903 12:22:58.450676 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8904 12:22:58.453772 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8905 12:22:58.456975 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8906 12:22:58.457063 ==
8907 12:22:58.460761 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 12:22:58.467036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 12:22:58.467117 ==
8910 12:22:58.467181 DQS Delay:
8911 12:22:58.469948 DQS0 = 0, DQS1 = 0
8912 12:22:58.470027 DQM Delay:
8913 12:22:58.473383 DQM0 = 131, DQM1 = 128
8914 12:22:58.473507 DQ Delay:
8915 12:22:58.476564 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8916 12:22:58.480600 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8917 12:22:58.483505 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8918 12:22:58.486911 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8919 12:22:58.486993
8920 12:22:58.487055
8921 12:22:58.487113 ==
8922 12:22:58.490442 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 12:22:58.496523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 12:22:58.496597 ==
8925 12:22:58.496700
8926 12:22:58.496757
8927 12:22:58.496820 TX Vref Scan disable
8928 12:22:58.500091 == TX Byte 0 ==
8929 12:22:58.503617 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8930 12:22:58.506836 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8931 12:22:58.509934 == TX Byte 1 ==
8932 12:22:58.513342 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8933 12:22:58.516654 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8934 12:22:58.520237 ==
8935 12:22:58.520314 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 12:22:58.526737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 12:22:58.526840 ==
8938 12:22:58.539919
8939 12:22:58.543096 TX Vref early break, caculate TX vref
8940 12:22:58.546771 TX Vref=16, minBit 8, minWin=23, winSum=385
8941 12:22:58.550022 TX Vref=18, minBit 5, minWin=24, winSum=397
8942 12:22:58.553179 TX Vref=20, minBit 8, minWin=23, winSum=405
8943 12:22:58.556681 TX Vref=22, minBit 0, minWin=25, winSum=413
8944 12:22:58.560500 TX Vref=24, minBit 8, minWin=25, winSum=422
8945 12:22:58.566596 TX Vref=26, minBit 0, minWin=26, winSum=425
8946 12:22:58.570341 TX Vref=28, minBit 0, minWin=25, winSum=433
8947 12:22:58.572958 TX Vref=30, minBit 0, minWin=26, winSum=431
8948 12:22:58.576490 TX Vref=32, minBit 0, minWin=25, winSum=424
8949 12:22:58.579668 TX Vref=34, minBit 0, minWin=24, winSum=413
8950 12:22:58.583082 TX Vref=36, minBit 0, minWin=23, winSum=407
8951 12:22:58.590018 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 30
8952 12:22:58.590104
8953 12:22:58.593072 Final TX Range 0 Vref 30
8954 12:22:58.593156
8955 12:22:58.593220 ==
8956 12:22:58.596579 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 12:22:58.600190 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 12:22:58.600279 ==
8959 12:22:58.600343
8960 12:22:58.600402
8961 12:22:58.603387 TX Vref Scan disable
8962 12:22:58.609817 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8963 12:22:58.609901 == TX Byte 0 ==
8964 12:22:58.613407 u2DelayCellOfst[0]=17 cells (5 PI)
8965 12:22:58.616754 u2DelayCellOfst[1]=14 cells (4 PI)
8966 12:22:58.620218 u2DelayCellOfst[2]=0 cells (0 PI)
8967 12:22:58.623335 u2DelayCellOfst[3]=7 cells (2 PI)
8968 12:22:58.626844 u2DelayCellOfst[4]=7 cells (2 PI)
8969 12:22:58.630076 u2DelayCellOfst[5]=17 cells (5 PI)
8970 12:22:58.633315 u2DelayCellOfst[6]=17 cells (5 PI)
8971 12:22:58.636578 u2DelayCellOfst[7]=7 cells (2 PI)
8972 12:22:58.639790 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8973 12:22:58.643151 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8974 12:22:58.643228 == TX Byte 1 ==
8975 12:22:58.646685 u2DelayCellOfst[8]=0 cells (0 PI)
8976 12:22:58.649707 u2DelayCellOfst[9]=3 cells (1 PI)
8977 12:22:58.653006 u2DelayCellOfst[10]=10 cells (3 PI)
8978 12:22:58.657010 u2DelayCellOfst[11]=3 cells (1 PI)
8979 12:22:58.659609 u2DelayCellOfst[12]=10 cells (3 PI)
8980 12:22:58.663235 u2DelayCellOfst[13]=17 cells (5 PI)
8981 12:22:58.666583 u2DelayCellOfst[14]=14 cells (4 PI)
8982 12:22:58.669981 u2DelayCellOfst[15]=17 cells (5 PI)
8983 12:22:58.673285 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8984 12:22:58.680196 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8985 12:22:58.680281 DramC Write-DBI on
8986 12:22:58.680378 ==
8987 12:22:58.683557 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 12:22:58.686632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 12:22:58.686732 ==
8990 12:22:58.686824
8991 12:22:58.689878
8992 12:22:58.689943 TX Vref Scan disable
8993 12:22:58.693115 == TX Byte 0 ==
8994 12:22:58.696498 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8995 12:22:58.700345 == TX Byte 1 ==
8996 12:22:58.703494 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8997 12:22:58.703565 DramC Write-DBI off
8998 12:22:58.703659
8999 12:22:58.706390 [DATLAT]
9000 12:22:58.706485 Freq=1600, CH1 RK1
9001 12:22:58.706574
9002 12:22:58.709931 DATLAT Default: 0xf
9003 12:22:58.710001 0, 0xFFFF, sum = 0
9004 12:22:58.713448 1, 0xFFFF, sum = 0
9005 12:22:58.713518 2, 0xFFFF, sum = 0
9006 12:22:58.716978 3, 0xFFFF, sum = 0
9007 12:22:58.717087 4, 0xFFFF, sum = 0
9008 12:22:58.720096 5, 0xFFFF, sum = 0
9009 12:22:58.720174 6, 0xFFFF, sum = 0
9010 12:22:58.723511 7, 0xFFFF, sum = 0
9011 12:22:58.723585 8, 0xFFFF, sum = 0
9012 12:22:58.726450 9, 0xFFFF, sum = 0
9013 12:22:58.730087 10, 0xFFFF, sum = 0
9014 12:22:58.730161 11, 0xFFFF, sum = 0
9015 12:22:58.733181 12, 0xFFFF, sum = 0
9016 12:22:58.733256 13, 0xFFFF, sum = 0
9017 12:22:58.736505 14, 0x0, sum = 1
9018 12:22:58.736588 15, 0x0, sum = 2
9019 12:22:58.739965 16, 0x0, sum = 3
9020 12:22:58.740044 17, 0x0, sum = 4
9021 12:22:58.740104 best_step = 15
9022 12:22:58.740161
9023 12:22:58.743300 ==
9024 12:22:58.746675 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 12:22:58.749938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 12:22:58.750047 ==
9027 12:22:58.750139 RX Vref Scan: 0
9028 12:22:58.750236
9029 12:22:58.753112 RX Vref 0 -> 0, step: 1
9030 12:22:58.753181
9031 12:22:58.756472 RX Delay 11 -> 252, step: 4
9032 12:22:58.760256 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
9033 12:22:58.763481 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9034 12:22:58.770020 iDelay=191, Bit 2, Center 116 (63 ~ 170) 108
9035 12:22:58.773107 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
9036 12:22:58.776594 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9037 12:22:58.780289 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9038 12:22:58.783474 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9039 12:22:58.790533 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
9040 12:22:58.793242 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9041 12:22:58.796885 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9042 12:22:58.799913 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
9043 12:22:58.803422 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
9044 12:22:58.810191 iDelay=191, Bit 12, Center 132 (79 ~ 186) 108
9045 12:22:58.813643 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
9046 12:22:58.816880 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
9047 12:22:58.820223 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9048 12:22:58.820298 ==
9049 12:22:58.823646 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 12:22:58.826497 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 12:22:58.830220 ==
9052 12:22:58.830300 DQS Delay:
9053 12:22:58.830362 DQS0 = 0, DQS1 = 0
9054 12:22:58.833616 DQM Delay:
9055 12:22:58.833696 DQM0 = 129, DQM1 = 126
9056 12:22:58.836929 DQ Delay:
9057 12:22:58.840491 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =126
9058 12:22:58.843908 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9059 12:22:58.847282 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =118
9060 12:22:58.850353 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =136
9061 12:22:58.850433
9062 12:22:58.850495
9063 12:22:58.850554
9064 12:22:58.853420 [DramC_TX_OE_Calibration] TA2
9065 12:22:58.856846 Original DQ_B0 (3 6) =30, OEN = 27
9066 12:22:58.860132 Original DQ_B1 (3 6) =30, OEN = 27
9067 12:22:58.860213 24, 0x0, End_B0=24 End_B1=24
9068 12:22:58.863649 25, 0x0, End_B0=25 End_B1=25
9069 12:22:58.866996 26, 0x0, End_B0=26 End_B1=26
9070 12:22:58.870454 27, 0x0, End_B0=27 End_B1=27
9071 12:22:58.873320 28, 0x0, End_B0=28 End_B1=28
9072 12:22:58.873401 29, 0x0, End_B0=29 End_B1=29
9073 12:22:58.877075 30, 0x0, End_B0=30 End_B1=30
9074 12:22:58.880393 31, 0x4141, End_B0=30 End_B1=30
9075 12:22:58.884041 Byte0 end_step=30 best_step=27
9076 12:22:58.887404 Byte1 end_step=30 best_step=27
9077 12:22:58.887485 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 12:22:58.890626 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 12:22:58.890706
9080 12:22:58.890811
9081 12:22:58.900717 [DQSOSCAuto] RK1, (LSB)MR18= 0x1217, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 400 ps
9082 12:22:58.904039 CH1 RK1: MR19=303, MR18=1217
9083 12:22:58.906974 CH1_RK1: MR19=0x303, MR18=0x1217, DQSOSC=398, MR23=63, INC=23, DEC=15
9084 12:22:58.910977 [RxdqsGatingPostProcess] freq 1600
9085 12:22:58.917404 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 12:22:58.920371 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 12:22:58.923814 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 12:22:58.927126 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 12:22:58.930438 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 12:22:58.934400 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 12:22:58.934516 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 12:22:58.937118 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 12:22:58.940410 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 12:22:58.944251 Pre-setting of DQS Precalculation
9095 12:22:58.950626 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 12:22:58.957059 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 12:22:58.963509 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 12:22:58.963594
9099 12:22:58.963656
9100 12:22:58.966847 [Calibration Summary] 3200 Mbps
9101 12:22:58.966927 CH 0, Rank 0
9102 12:22:58.970249 SW Impedance : PASS
9103 12:22:58.973768 DUTY Scan : NO K
9104 12:22:58.973849 ZQ Calibration : PASS
9105 12:22:58.977278 Jitter Meter : NO K
9106 12:22:58.980788 CBT Training : PASS
9107 12:22:58.980868 Write leveling : PASS
9108 12:22:58.983762 RX DQS gating : PASS
9109 12:22:58.986779 RX DQ/DQS(RDDQC) : PASS
9110 12:22:58.986859 TX DQ/DQS : PASS
9111 12:22:58.990216 RX DATLAT : PASS
9112 12:22:58.994062 RX DQ/DQS(Engine): PASS
9113 12:22:58.994141 TX OE : PASS
9114 12:22:58.994204 All Pass.
9115 12:22:58.996892
9116 12:22:58.996971 CH 0, Rank 1
9117 12:22:59.000233 SW Impedance : PASS
9118 12:22:59.000312 DUTY Scan : NO K
9119 12:22:59.004046 ZQ Calibration : PASS
9120 12:22:59.004126 Jitter Meter : NO K
9121 12:22:59.007247 CBT Training : PASS
9122 12:22:59.010321 Write leveling : PASS
9123 12:22:59.010401 RX DQS gating : PASS
9124 12:22:59.014029 RX DQ/DQS(RDDQC) : PASS
9125 12:22:59.016891 TX DQ/DQS : PASS
9126 12:22:59.016971 RX DATLAT : PASS
9127 12:22:59.020763 RX DQ/DQS(Engine): PASS
9128 12:22:59.024132 TX OE : PASS
9129 12:22:59.024206 All Pass.
9130 12:22:59.024269
9131 12:22:59.024326 CH 1, Rank 0
9132 12:22:59.027051 SW Impedance : PASS
9133 12:22:59.030467 DUTY Scan : NO K
9134 12:22:59.030571 ZQ Calibration : PASS
9135 12:22:59.033729 Jitter Meter : NO K
9136 12:22:59.037297 CBT Training : PASS
9137 12:22:59.037377 Write leveling : PASS
9138 12:22:59.040583 RX DQS gating : PASS
9139 12:22:59.043869 RX DQ/DQS(RDDQC) : PASS
9140 12:22:59.043975 TX DQ/DQS : PASS
9141 12:22:59.046847 RX DATLAT : PASS
9142 12:22:59.046930 RX DQ/DQS(Engine): PASS
9143 12:22:59.050365 TX OE : PASS
9144 12:22:59.050445 All Pass.
9145 12:22:59.050508
9146 12:22:59.053802 CH 1, Rank 1
9147 12:22:59.053882 SW Impedance : PASS
9148 12:22:59.057147 DUTY Scan : NO K
9149 12:22:59.060257 ZQ Calibration : PASS
9150 12:22:59.060360 Jitter Meter : NO K
9151 12:22:59.063975 CBT Training : PASS
9152 12:22:59.067536 Write leveling : PASS
9153 12:22:59.067615 RX DQS gating : PASS
9154 12:22:59.070451 RX DQ/DQS(RDDQC) : PASS
9155 12:22:59.074389 TX DQ/DQS : PASS
9156 12:22:59.074470 RX DATLAT : PASS
9157 12:22:59.077377 RX DQ/DQS(Engine): PASS
9158 12:22:59.080894 TX OE : PASS
9159 12:22:59.081000 All Pass.
9160 12:22:59.081082
9161 12:22:59.081154 DramC Write-DBI on
9162 12:22:59.083930 PER_BANK_REFRESH: Hybrid Mode
9163 12:22:59.087770 TX_TRACKING: ON
9164 12:22:59.094081 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 12:22:59.103862 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 12:22:59.110842 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 12:22:59.114409 [FAST_K] Save calibration result to emmc
9168 12:22:59.117613 sync common calibartion params.
9169 12:22:59.117692 sync cbt_mode0:1, 1:1
9170 12:22:59.120632 dram_init: ddr_geometry: 2
9171 12:22:59.123928 dram_init: ddr_geometry: 2
9172 12:22:59.127862 dram_init: ddr_geometry: 2
9173 12:22:59.127943 0:dram_rank_size:100000000
9174 12:22:59.131361 1:dram_rank_size:100000000
9175 12:22:59.137364 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 12:22:59.137442 DFS_SHUFFLE_HW_MODE: ON
9177 12:22:59.140436 dramc_set_vcore_voltage set vcore to 725000
9178 12:22:59.144311 Read voltage for 1600, 0
9179 12:22:59.144391 Vio18 = 0
9180 12:22:59.147143 Vcore = 725000
9181 12:22:59.147222 Vdram = 0
9182 12:22:59.147294 Vddq = 0
9183 12:22:59.150604 Vmddr = 0
9184 12:22:59.150710 switch to 3200 Mbps bootup
9185 12:22:59.154102 [DramcRunTimeConfig]
9186 12:22:59.154190 PHYPLL
9187 12:22:59.157523 DPM_CONTROL_AFTERK: ON
9188 12:22:59.157602 PER_BANK_REFRESH: ON
9189 12:22:59.160830 REFRESH_OVERHEAD_REDUCTION: ON
9190 12:22:59.164462 CMD_PICG_NEW_MODE: OFF
9191 12:22:59.164541 XRTWTW_NEW_MODE: ON
9192 12:22:59.167433 XRTRTR_NEW_MODE: ON
9193 12:22:59.167513 TX_TRACKING: ON
9194 12:22:59.170642 RDSEL_TRACKING: OFF
9195 12:22:59.173874 DQS Precalculation for DVFS: ON
9196 12:22:59.173949 RX_TRACKING: OFF
9197 12:22:59.177354 HW_GATING DBG: ON
9198 12:22:59.177425 ZQCS_ENABLE_LP4: ON
9199 12:22:59.180756 RX_PICG_NEW_MODE: ON
9200 12:22:59.180825 TX_PICG_NEW_MODE: ON
9201 12:22:59.183909 ENABLE_RX_DCM_DPHY: ON
9202 12:22:59.187197 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 12:22:59.190638 DUMMY_READ_FOR_TRACKING: OFF
9204 12:22:59.190783 !!! SPM_CONTROL_AFTERK: OFF
9205 12:22:59.194704 !!! SPM could not control APHY
9206 12:22:59.197303 IMPEDANCE_TRACKING: ON
9207 12:22:59.197384 TEMP_SENSOR: ON
9208 12:22:59.200691 HW_SAVE_FOR_SR: OFF
9209 12:22:59.204033 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 12:22:59.207394 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 12:22:59.207478 Read ODT Tracking: ON
9212 12:22:59.210970 Refresh Rate DeBounce: ON
9213 12:22:59.214281 DFS_NO_QUEUE_FLUSH: ON
9214 12:22:59.217368 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 12:22:59.217448 ENABLE_DFS_RUNTIME_MRW: OFF
9216 12:22:59.221480 DDR_RESERVE_NEW_MODE: ON
9217 12:22:59.224067 MR_CBT_SWITCH_FREQ: ON
9218 12:22:59.224146 =========================
9219 12:22:59.244498 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 12:22:59.247707 dram_init: ddr_geometry: 2
9221 12:22:59.266245 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 12:22:59.269427 dram_init: dram init end (result: 0)
9223 12:22:59.276115 DRAM-K: Full calibration passed in 24530 msecs
9224 12:22:59.279478 MRC: failed to locate region type 0.
9225 12:22:59.279558 DRAM rank0 size:0x100000000,
9226 12:22:59.282419 DRAM rank1 size=0x100000000
9227 12:22:59.292723 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 12:22:59.299259 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 12:22:59.305844 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 12:22:59.312582 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 12:22:59.316298 DRAM rank0 size:0x100000000,
9232 12:22:59.319629 DRAM rank1 size=0x100000000
9233 12:22:59.319709 CBMEM:
9234 12:22:59.322893 IMD: root @ 0xfffff000 254 entries.
9235 12:22:59.325911 IMD: root @ 0xffffec00 62 entries.
9236 12:22:59.329418 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 12:22:59.332644 WARNING: RO_VPD is uninitialized or empty.
9238 12:22:59.339021 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 12:22:59.346168 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 12:22:59.358999 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9241 12:22:59.370014 BS: romstage times (exec / console): total (unknown) / 24045 ms
9242 12:22:59.370098
9243 12:22:59.370170
9244 12:22:59.380242 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 12:22:59.383912 ARM64: Exception handlers installed.
9246 12:22:59.387146 ARM64: Testing exception
9247 12:22:59.390160 ARM64: Done test exception
9248 12:22:59.390232 Enumerating buses...
9249 12:22:59.393424 Show all devs... Before device enumeration.
9250 12:22:59.396926 Root Device: enabled 1
9251 12:22:59.400030 CPU_CLUSTER: 0: enabled 1
9252 12:22:59.400113 CPU: 00: enabled 1
9253 12:22:59.403660 Compare with tree...
9254 12:22:59.403744 Root Device: enabled 1
9255 12:22:59.407468 CPU_CLUSTER: 0: enabled 1
9256 12:22:59.410534 CPU: 00: enabled 1
9257 12:22:59.410637 Root Device scanning...
9258 12:22:59.413314 scan_static_bus for Root Device
9259 12:22:59.416942 CPU_CLUSTER: 0 enabled
9260 12:22:59.420514 scan_static_bus for Root Device done
9261 12:22:59.423820 scan_bus: bus Root Device finished in 8 msecs
9262 12:22:59.423901 done
9263 12:22:59.430244 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 12:22:59.433408 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 12:22:59.440242 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 12:22:59.443747 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 12:22:59.447106 Allocating resources...
9268 12:22:59.447180 Reading resources...
9269 12:22:59.453694 Root Device read_resources bus 0 link: 0
9270 12:22:59.453767 DRAM rank0 size:0x100000000,
9271 12:22:59.457083 DRAM rank1 size=0x100000000
9272 12:22:59.460194 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 12:22:59.463667 CPU: 00 missing read_resources
9274 12:22:59.466930 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 12:22:59.473371 Root Device read_resources bus 0 link: 0 done
9276 12:22:59.473451 Done reading resources.
9277 12:22:59.480288 Show resources in subtree (Root Device)...After reading.
9278 12:22:59.483799 Root Device child on link 0 CPU_CLUSTER: 0
9279 12:22:59.487297 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 12:22:59.497008 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 12:22:59.497106 CPU: 00
9282 12:22:59.500118 Root Device assign_resources, bus 0 link: 0
9283 12:22:59.503652 CPU_CLUSTER: 0 missing set_resources
9284 12:22:59.506822 Root Device assign_resources, bus 0 link: 0 done
9285 12:22:59.510334 Done setting resources.
9286 12:22:59.516837 Show resources in subtree (Root Device)...After assigning values.
9287 12:22:59.520530 Root Device child on link 0 CPU_CLUSTER: 0
9288 12:22:59.523658 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 12:22:59.533562 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 12:22:59.533645 CPU: 00
9291 12:22:59.536619 Done allocating resources.
9292 12:22:59.540470 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 12:22:59.543687 Enabling resources...
9294 12:22:59.543768 done.
9295 12:22:59.546622 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 12:22:59.550116 Initializing devices...
9297 12:22:59.553568 Root Device init
9298 12:22:59.553647 init hardware done!
9299 12:22:59.557063 0x00000018: ctrlr->caps
9300 12:22:59.557167 52.000 MHz: ctrlr->f_max
9301 12:22:59.560118 0.400 MHz: ctrlr->f_min
9302 12:22:59.563296 0x40ff8080: ctrlr->voltages
9303 12:22:59.563406 sclk: 390625
9304 12:22:59.566628 Bus Width = 1
9305 12:22:59.566709 sclk: 390625
9306 12:22:59.566816 Bus Width = 1
9307 12:22:59.570558 Early init status = 3
9308 12:22:59.573989 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 12:22:59.578145 in-header: 03 fc 00 00 01 00 00 00
9310 12:22:59.581596 in-data: 00
9311 12:22:59.584676 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 12:22:59.590483 in-header: 03 fd 00 00 00 00 00 00
9313 12:22:59.593475 in-data:
9314 12:22:59.596849 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 12:22:59.600985 in-header: 03 fc 00 00 01 00 00 00
9316 12:22:59.604107 in-data: 00
9317 12:22:59.607423 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 12:22:59.613313 in-header: 03 fd 00 00 00 00 00 00
9319 12:22:59.616618 in-data:
9320 12:22:59.620014 [SSUSB] Setting up USB HOST controller...
9321 12:22:59.623521 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 12:22:59.626512 [SSUSB] phy power-on done.
9323 12:22:59.629580 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 12:22:59.636644 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 12:22:59.639853 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 12:22:59.646691 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 12:22:59.653169 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9328 12:22:59.659910 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 12:22:59.666927 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 12:22:59.673045 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9331 12:22:59.673130 SPM: binary array size = 0x9dc
9332 12:22:59.679738 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 12:22:59.686849 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 12:22:59.693219 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 12:22:59.696621 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 12:22:59.700013 configure_display: Starting display init
9337 12:22:59.736945 anx7625_power_on_init: Init interface.
9338 12:22:59.739812 anx7625_disable_pd_protocol: Disabled PD feature.
9339 12:22:59.743195 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 12:22:59.771042 anx7625_start_dp_work: Secure OCM version=00
9341 12:22:59.774452 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 12:22:59.789210 sp_tx_get_edid_block: EDID Block = 1
9343 12:22:59.891577 Extracted contents:
9344 12:22:59.894974 header: 00 ff ff ff ff ff ff 00
9345 12:22:59.898359 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 12:22:59.901526 version: 01 04
9347 12:22:59.904706 basic params: 95 1f 11 78 0a
9348 12:22:59.908365 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 12:22:59.911717 established: 00 00 00
9350 12:22:59.918103 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 12:22:59.921546 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 12:22:59.928281 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 12:22:59.935013 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 12:22:59.941532 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 12:22:59.945020 extensions: 00
9356 12:22:59.945101 checksum: fb
9357 12:22:59.945165
9358 12:22:59.948425 Manufacturer: IVO Model 57d Serial Number 0
9359 12:22:59.951269 Made week 0 of 2020
9360 12:22:59.951349 EDID version: 1.4
9361 12:22:59.954493 Digital display
9362 12:22:59.958122 6 bits per primary color channel
9363 12:22:59.958204 DisplayPort interface
9364 12:22:59.961953 Maximum image size: 31 cm x 17 cm
9365 12:22:59.964759 Gamma: 220%
9366 12:22:59.964838 Check DPMS levels
9367 12:22:59.968347 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 12:22:59.971537 First detailed timing is preferred timing
9369 12:22:59.974711 Established timings supported:
9370 12:22:59.977944 Standard timings supported:
9371 12:22:59.978015 Detailed timings
9372 12:22:59.985099 Hex of detail: 383680a07038204018303c0035ae10000019
9373 12:22:59.988125 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 12:22:59.991438 0780 0798 07c8 0820 hborder 0
9375 12:22:59.998522 0438 043b 0447 0458 vborder 0
9376 12:22:59.998602 -hsync -vsync
9377 12:23:00.001716 Did detailed timing
9378 12:23:00.005196 Hex of detail: 000000000000000000000000000000000000
9379 12:23:00.008102 Manufacturer-specified data, tag 0
9380 12:23:00.014906 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 12:23:00.014987 ASCII string: InfoVision
9382 12:23:00.021867 Hex of detail: 000000fe00523134304e574635205248200a
9383 12:23:00.021947 ASCII string: R140NWF5 RH
9384 12:23:00.024929 Checksum
9385 12:23:00.025008 Checksum: 0xfb (valid)
9386 12:23:00.031951 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 12:23:00.032031 DSI data_rate: 832800000 bps
9388 12:23:00.039247 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 12:23:00.042908 anx7625_parse_edid: pixelclock(138800).
9390 12:23:00.046220 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 12:23:00.049110 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 12:23:00.052691 anx7625_dsi_config: config dsi.
9393 12:23:00.059322 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 12:23:00.073396 anx7625_dsi_config: success to config DSI
9395 12:23:00.077436 anx7625_dp_start: MIPI phy setup OK.
9396 12:23:00.080175 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 12:23:00.083660 mtk_ddp_mode_set invalid vrefresh 60
9398 12:23:00.087016 main_disp_path_setup
9399 12:23:00.087096 ovl_layer_smi_id_en
9400 12:23:00.090519 ovl_layer_smi_id_en
9401 12:23:00.090598 ccorr_config
9402 12:23:00.090696 aal_config
9403 12:23:00.093647 gamma_config
9404 12:23:00.093752 postmask_config
9405 12:23:00.093843 dither_config
9406 12:23:00.100844 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 12:23:00.107322 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 12:23:00.110272 Root Device init finished in 554 msecs
9409 12:23:00.110384 CPU_CLUSTER: 0 init
9410 12:23:00.120762 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 12:23:00.123884 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 12:23:00.127322 APU_MBOX 0x190000b0 = 0x10001
9413 12:23:00.130536 APU_MBOX 0x190001b0 = 0x10001
9414 12:23:00.133933 APU_MBOX 0x190005b0 = 0x10001
9415 12:23:00.134015 APU_MBOX 0x190006b0 = 0x10001
9416 12:23:00.140469 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 12:23:00.152435 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9418 12:23:00.164904 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 12:23:00.171852 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 12:23:00.183184 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9421 12:23:00.192110 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 12:23:00.195555 CPU_CLUSTER: 0 init finished in 81 msecs
9423 12:23:00.199259 Devices initialized
9424 12:23:00.202326 Show all devs... After init.
9425 12:23:00.202407 Root Device: enabled 1
9426 12:23:00.206064 CPU_CLUSTER: 0: enabled 1
9427 12:23:00.209097 CPU: 00: enabled 1
9428 12:23:00.212513 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9429 12:23:00.216181 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 12:23:00.219181 ELOG: NV offset 0x57f000 size 0x1000
9431 12:23:00.226251 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9432 12:23:00.232581 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 12:23:00.236216 ELOG: Event(17) added with size 13 at 2023-10-27 12:23:00 UTC
9434 12:23:00.239045 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 12:23:00.243897 in-header: 03 04 00 00 2c 00 00 00
9436 12:23:00.256856 in-data: 5b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 12:23:00.263796 ELOG: Event(A1) added with size 10 at 2023-10-27 12:23:00 UTC
9438 12:23:00.270788 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9439 12:23:00.273735 ELOG: Event(A0) added with size 9 at 2023-10-27 12:23:00 UTC
9440 12:23:00.280501 elog_add_boot_reason: Logged dev mode boot
9441 12:23:00.283894 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9442 12:23:00.287672 Finalize devices...
9443 12:23:00.287745 Devices finalized
9444 12:23:00.293725 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 12:23:00.297217 Writing coreboot table at 0xffe64000
9446 12:23:00.300636 0. 000000000010a000-0000000000113fff: RAMSTAGE
9447 12:23:00.303981 1. 0000000040000000-00000000400fffff: RAM
9448 12:23:00.307686 2. 0000000040100000-000000004032afff: RAMSTAGE
9449 12:23:00.314104 3. 000000004032b000-00000000545fffff: RAM
9450 12:23:00.317380 4. 0000000054600000-000000005465ffff: BL31
9451 12:23:00.320346 5. 0000000054660000-00000000ffe63fff: RAM
9452 12:23:00.323927 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9453 12:23:00.330877 7. 0000000100000000-000000023fffffff: RAM
9454 12:23:00.330958 Passing 5 GPIOs to payload:
9455 12:23:00.337157 NAME | PORT | POLARITY | VALUE
9456 12:23:00.340677 EC in RW | 0x000000aa | low | undefined
9457 12:23:00.343896 EC interrupt | 0x00000005 | low | undefined
9458 12:23:00.350739 TPM interrupt | 0x000000ab | high | undefined
9459 12:23:00.354031 SD card detect | 0x00000011 | high | undefined
9460 12:23:00.360364 speaker enable | 0x00000093 | high | undefined
9461 12:23:00.363739 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9462 12:23:00.367075 in-header: 03 f9 00 00 02 00 00 00
9463 12:23:00.367160 in-data: 02 00
9464 12:23:00.370340 ADC[4]: Raw value=900221 ID=7
9465 12:23:00.374022 ADC[3]: Raw value=213336 ID=1
9466 12:23:00.374103 RAM Code: 0x71
9467 12:23:00.377578 ADC[6]: Raw value=74926 ID=0
9468 12:23:00.380551 ADC[5]: Raw value=212229 ID=1
9469 12:23:00.380632 SKU Code: 0x1
9470 12:23:00.387226 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b065
9471 12:23:00.390368 coreboot table: 964 bytes.
9472 12:23:00.393640 IMD ROOT 0. 0xfffff000 0x00001000
9473 12:23:00.396926 IMD SMALL 1. 0xffffe000 0x00001000
9474 12:23:00.400391 RO MCACHE 2. 0xffffc000 0x00001104
9475 12:23:00.403646 CONSOLE 3. 0xfff7c000 0x00080000
9476 12:23:00.407182 FMAP 4. 0xfff7b000 0x00000452
9477 12:23:00.410468 TIME STAMP 5. 0xfff7a000 0x00000910
9478 12:23:00.414019 VBOOT WORK 6. 0xfff66000 0x00014000
9479 12:23:00.417175 RAMOOPS 7. 0xffe66000 0x00100000
9480 12:23:00.417256 COREBOOT 8. 0xffe64000 0x00002000
9481 12:23:00.420319 IMD small region:
9482 12:23:00.423987 IMD ROOT 0. 0xffffec00 0x00000400
9483 12:23:00.427061 VPD 1. 0xffffeb80 0x0000006c
9484 12:23:00.431276 MMC STATUS 2. 0xffffeb60 0x00000004
9485 12:23:00.437264 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9486 12:23:00.437346 Probing TPM: done!
9487 12:23:00.444120 Connected to device vid:did:rid of 1ae0:0028:00
9488 12:23:00.450553 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9489 12:23:00.454595 Initialized TPM device CR50 revision 0
9490 12:23:00.457739 Checking cr50 for pending updates
9491 12:23:00.462914 Reading cr50 TPM mode
9492 12:23:00.471543 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9493 12:23:00.478673 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9494 12:23:00.518524 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9495 12:23:00.521876 Checking segment from ROM address 0x40100000
9496 12:23:00.525689 Checking segment from ROM address 0x4010001c
9497 12:23:00.531711 Loading segment from ROM address 0x40100000
9498 12:23:00.531794 code (compression=0)
9499 12:23:00.538964 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9500 12:23:00.548710 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9501 12:23:00.548793 it's not compressed!
9502 12:23:00.555463 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9503 12:23:00.558695 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9504 12:23:00.579067 Loading segment from ROM address 0x4010001c
9505 12:23:00.579153 Entry Point 0x80000000
9506 12:23:00.582282 Loaded segments
9507 12:23:00.585643 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9508 12:23:00.592935 Jumping to boot code at 0x80000000(0xffe64000)
9509 12:23:00.598924 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9510 12:23:00.605910 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9511 12:23:00.613467 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9512 12:23:00.616676 Checking segment from ROM address 0x40100000
9513 12:23:00.620141 Checking segment from ROM address 0x4010001c
9514 12:23:00.623588 Loading segment from ROM address 0x40100000
9515 12:23:00.626838 code (compression=1)
9516 12:23:00.633905 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9517 12:23:00.643884 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9518 12:23:00.643967 using LZMA
9519 12:23:00.651611 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9520 12:23:00.658404 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9521 12:23:00.661611 Loading segment from ROM address 0x4010001c
9522 12:23:00.661692 Entry Point 0x54601000
9523 12:23:00.664928 Loaded segments
9524 12:23:00.668200 NOTICE: MT8192 bl31_setup
9525 12:23:00.675300 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9526 12:23:00.678563 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9527 12:23:00.681923 WARNING: region 0:
9528 12:23:00.685307 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 12:23:00.685389 WARNING: region 1:
9530 12:23:00.692430 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9531 12:23:00.695377 WARNING: region 2:
9532 12:23:00.698741 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9533 12:23:00.702253 WARNING: region 3:
9534 12:23:00.705755 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9535 12:23:00.709451 WARNING: region 4:
9536 12:23:00.712041 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9537 12:23:00.715723 WARNING: region 5:
9538 12:23:00.719028 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9539 12:23:00.722100 WARNING: region 6:
9540 12:23:00.726063 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9541 12:23:00.726157 WARNING: region 7:
9542 12:23:00.732126 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 12:23:00.738834 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9544 12:23:00.742655 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9545 12:23:00.746383 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9546 12:23:00.749070 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9547 12:23:00.755581 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9548 12:23:00.759186 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9549 12:23:00.765829 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9550 12:23:00.768974 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9551 12:23:00.772455 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9552 12:23:00.779357 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9553 12:23:00.782647 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9554 12:23:00.786352 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9555 12:23:00.792708 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9556 12:23:00.795770 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9557 12:23:00.799088 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9558 12:23:00.806179 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9559 12:23:00.809237 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9560 12:23:00.816359 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9561 12:23:00.819760 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9562 12:23:00.823337 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9563 12:23:00.829882 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9564 12:23:00.832835 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9565 12:23:00.836541 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9566 12:23:00.842814 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9567 12:23:00.846265 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9568 12:23:00.853236 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9569 12:23:00.856695 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9570 12:23:00.859672 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9571 12:23:00.866527 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9572 12:23:00.869825 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9573 12:23:00.876827 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9574 12:23:00.880006 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9575 12:23:00.883227 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9576 12:23:00.886781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9577 12:23:00.893470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9578 12:23:00.896664 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9579 12:23:00.900118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9580 12:23:00.903300 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9581 12:23:00.906990 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9582 12:23:00.913752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9583 12:23:00.916810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9584 12:23:00.920556 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9585 12:23:00.923908 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9586 12:23:00.930534 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9587 12:23:00.933741 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9588 12:23:00.937280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9589 12:23:00.940435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9590 12:23:00.947224 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9591 12:23:00.950684 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9592 12:23:00.957061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9593 12:23:00.960715 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9594 12:23:00.964409 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9595 12:23:00.970523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9596 12:23:00.974121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9597 12:23:00.980763 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9598 12:23:00.983943 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9599 12:23:00.987617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9600 12:23:00.993955 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9601 12:23:00.997341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9602 12:23:01.004430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9603 12:23:01.007658 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9604 12:23:01.014379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9605 12:23:01.017883 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9606 12:23:01.021297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9607 12:23:01.027948 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9608 12:23:01.030909 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9609 12:23:01.037678 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9610 12:23:01.041309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9611 12:23:01.047910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9612 12:23:01.051318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9613 12:23:01.054687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9614 12:23:01.061498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9615 12:23:01.065152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9616 12:23:01.071541 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9617 12:23:01.075000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9618 12:23:01.078341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9619 12:23:01.085000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9620 12:23:01.088018 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9621 12:23:01.095005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9622 12:23:01.098438 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9623 12:23:01.105383 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9624 12:23:01.108208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9625 12:23:01.111595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9626 12:23:01.118262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9627 12:23:01.121743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9628 12:23:01.128142 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9629 12:23:01.131692 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9630 12:23:01.134985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9631 12:23:01.142129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9632 12:23:01.145607 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9633 12:23:01.152025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9634 12:23:01.155683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9635 12:23:01.161809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9636 12:23:01.165721 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9637 12:23:01.168678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9638 12:23:01.175275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9639 12:23:01.179022 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9640 12:23:01.182218 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9641 12:23:01.188748 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9642 12:23:01.192272 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9643 12:23:01.195399 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9644 12:23:01.202220 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9645 12:23:01.205248 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9646 12:23:01.208607 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9647 12:23:01.216056 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9648 12:23:01.218875 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9649 12:23:01.222372 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9650 12:23:01.228949 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9651 12:23:01.232571 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9652 12:23:01.238855 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9653 12:23:01.242342 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9654 12:23:01.245546 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9655 12:23:01.252700 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9656 12:23:01.256055 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9657 12:23:01.262478 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9658 12:23:01.266013 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9659 12:23:01.269384 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9660 12:23:01.272763 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9661 12:23:01.279130 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9662 12:23:01.282403 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9663 12:23:01.286140 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9664 12:23:01.289222 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9665 12:23:01.296100 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9666 12:23:01.299475 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9667 12:23:01.302948 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9668 12:23:01.309293 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9669 12:23:01.312680 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9670 12:23:01.319507 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9671 12:23:01.322579 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9672 12:23:01.326228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9673 12:23:01.333496 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9674 12:23:01.336874 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9675 12:23:01.339706 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9676 12:23:01.346878 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9677 12:23:01.349945 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9678 12:23:01.356824 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9679 12:23:01.359705 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9680 12:23:01.363195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9681 12:23:01.369970 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9682 12:23:01.373476 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9683 12:23:01.376455 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9684 12:23:01.383049 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9685 12:23:01.386356 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9686 12:23:01.393638 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9687 12:23:01.397003 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9688 12:23:01.400043 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9689 12:23:01.406914 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9690 12:23:01.410661 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9691 12:23:01.413916 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9692 12:23:01.420456 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9693 12:23:01.423964 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9694 12:23:01.427282 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9695 12:23:01.433768 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9696 12:23:01.437108 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9697 12:23:01.443956 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9698 12:23:01.447520 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9699 12:23:01.450598 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9700 12:23:01.457538 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9701 12:23:01.460940 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9702 12:23:01.463983 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9703 12:23:01.471084 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9704 12:23:01.474296 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9705 12:23:01.480594 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9706 12:23:01.484027 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9707 12:23:01.487603 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9708 12:23:01.494074 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9709 12:23:01.497604 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9710 12:23:01.504147 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9711 12:23:01.507784 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9712 12:23:01.510707 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9713 12:23:01.517647 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9714 12:23:01.521025 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9715 12:23:01.524156 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9716 12:23:01.530901 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9717 12:23:01.534288 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9718 12:23:01.540684 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9719 12:23:01.544067 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9720 12:23:01.547759 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9721 12:23:01.554324 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9722 12:23:01.557379 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9723 12:23:01.561069 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9724 12:23:01.567568 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9725 12:23:01.570991 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9726 12:23:01.577632 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9727 12:23:01.581001 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9728 12:23:01.584583 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9729 12:23:01.590935 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9730 12:23:01.594366 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9731 12:23:01.601111 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9732 12:23:01.604338 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9733 12:23:01.607659 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9734 12:23:01.614399 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9735 12:23:01.617655 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9736 12:23:01.624489 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9737 12:23:01.627656 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9738 12:23:01.631377 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9739 12:23:01.637680 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9740 12:23:01.641099 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9741 12:23:01.647709 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9742 12:23:01.651382 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9743 12:23:01.654381 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9744 12:23:01.661361 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9745 12:23:01.664244 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9746 12:23:01.671102 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9747 12:23:01.674235 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9748 12:23:01.681213 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9749 12:23:01.684429 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9750 12:23:01.687792 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9751 12:23:01.694563 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9752 12:23:01.697953 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9753 12:23:01.704479 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9754 12:23:01.707552 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9755 12:23:01.710922 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9756 12:23:01.717374 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9757 12:23:01.721073 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9758 12:23:01.727701 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9759 12:23:01.731224 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9760 12:23:01.734307 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9761 12:23:01.741090 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9762 12:23:01.744542 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9763 12:23:01.751383 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9764 12:23:01.754666 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9765 12:23:01.757962 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9766 12:23:01.764376 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9767 12:23:01.767965 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9768 12:23:01.774263 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9769 12:23:01.777899 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9770 12:23:01.784261 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9771 12:23:01.787987 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9772 12:23:01.791010 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9773 12:23:01.794506 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9774 12:23:01.801448 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9775 12:23:01.804714 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9776 12:23:01.807737 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9777 12:23:01.811317 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9778 12:23:01.818099 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9779 12:23:01.821309 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9780 12:23:01.827864 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9781 12:23:01.831039 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9782 12:23:01.834620 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9783 12:23:01.841341 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9784 12:23:01.844298 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9785 12:23:01.847729 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9786 12:23:01.854187 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9787 12:23:01.857765 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9788 12:23:01.860943 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9789 12:23:01.867433 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9790 12:23:01.870903 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9791 12:23:01.874461 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9792 12:23:01.880903 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9793 12:23:01.884165 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9794 12:23:01.891069 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9795 12:23:01.894390 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9796 12:23:01.897822 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9797 12:23:01.904273 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9798 12:23:01.907546 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9799 12:23:01.911224 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9800 12:23:01.917691 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9801 12:23:01.921188 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9802 12:23:01.924135 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9803 12:23:01.930571 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9804 12:23:01.934294 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9805 12:23:01.940662 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9806 12:23:01.944464 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9807 12:23:01.947912 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9808 12:23:01.954354 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9809 12:23:01.957509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9810 12:23:01.961110 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9811 12:23:01.967444 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9812 12:23:01.971271 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9813 12:23:01.974242 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9814 12:23:01.977521 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9815 12:23:01.984290 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9816 12:23:01.987843 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9817 12:23:01.991261 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9818 12:23:01.994582 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9819 12:23:01.997368 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9820 12:23:02.004129 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9821 12:23:02.008005 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9822 12:23:02.011227 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9823 12:23:02.017530 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9824 12:23:02.021033 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9825 12:23:02.024281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9826 12:23:02.031250 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9827 12:23:02.034543 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9828 12:23:02.041158 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9829 12:23:02.044159 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9830 12:23:02.047387 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9831 12:23:02.054563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9832 12:23:02.057520 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9833 12:23:02.060944 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9834 12:23:02.067734 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9835 12:23:02.071458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9836 12:23:02.077525 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9837 12:23:02.081312 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9838 12:23:02.088141 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9839 12:23:02.090888 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9840 12:23:02.094231 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9841 12:23:02.101288 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9842 12:23:02.104820 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9843 12:23:02.108207 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9844 12:23:02.114616 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9845 12:23:02.117908 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9846 12:23:02.124374 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9847 12:23:02.127746 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9848 12:23:02.131274 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9849 12:23:02.138204 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9850 12:23:02.141179 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9851 12:23:02.148140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9852 12:23:02.151351 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9853 12:23:02.154562 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9854 12:23:02.161439 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9855 12:23:02.164383 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9856 12:23:02.171410 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9857 12:23:02.174974 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9858 12:23:02.178300 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9859 12:23:02.184573 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9860 12:23:02.188073 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9861 12:23:02.195251 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9862 12:23:02.197921 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9863 12:23:02.201554 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9864 12:23:02.208470 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9865 12:23:02.211603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9866 12:23:02.218430 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9867 12:23:02.221498 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9868 12:23:02.225037 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9869 12:23:02.231621 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9870 12:23:02.234790 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9871 12:23:02.241729 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9872 12:23:02.244999 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9873 12:23:02.248201 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9874 12:23:02.255213 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9875 12:23:02.258106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9876 12:23:02.265170 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9877 12:23:02.268647 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9878 12:23:02.271574 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9879 12:23:02.278281 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9880 12:23:02.281485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9881 12:23:02.288452 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9882 12:23:02.291816 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9883 12:23:02.294894 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9884 12:23:02.301759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9885 12:23:02.304909 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9886 12:23:02.311767 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9887 12:23:02.315334 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9888 12:23:02.318556 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9889 12:23:02.324862 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9890 12:23:02.328703 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9891 12:23:02.334829 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9892 12:23:02.338151 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9893 12:23:02.341390 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9894 12:23:02.348360 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9895 12:23:02.352186 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9896 12:23:02.358400 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9897 12:23:02.361741 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9898 12:23:02.365081 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9899 12:23:02.371651 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9900 12:23:02.375114 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9901 12:23:02.381878 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9902 12:23:02.385025 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9903 12:23:02.392295 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9904 12:23:02.394986 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9905 12:23:02.398465 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9906 12:23:02.405452 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9907 12:23:02.408729 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9908 12:23:02.415720 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9909 12:23:02.418524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9910 12:23:02.425490 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9911 12:23:02.428447 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9912 12:23:02.432040 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9913 12:23:02.438570 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9914 12:23:02.442017 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9915 12:23:02.448742 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9916 12:23:02.452417 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9917 12:23:02.458520 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9918 12:23:02.461989 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9919 12:23:02.465639 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9920 12:23:02.471835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9921 12:23:02.475104 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9922 12:23:02.482211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9923 12:23:02.485421 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9924 12:23:02.491817 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9925 12:23:02.495477 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9926 12:23:02.498643 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9927 12:23:02.505244 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9928 12:23:02.508522 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9929 12:23:02.515397 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9930 12:23:02.518675 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9931 12:23:02.521965 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9932 12:23:02.528541 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9933 12:23:02.532598 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9934 12:23:02.538816 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9935 12:23:02.542192 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9936 12:23:02.548710 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9937 12:23:02.552193 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9938 12:23:02.555130 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9939 12:23:02.562217 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9940 12:23:02.565227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9941 12:23:02.572602 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9942 12:23:02.575505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9943 12:23:02.582281 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9944 12:23:02.585365 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9945 12:23:02.588855 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9946 12:23:02.595316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9947 12:23:02.598601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9948 12:23:02.605314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9949 12:23:02.609052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9950 12:23:02.615551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9951 12:23:02.618836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9952 12:23:02.625296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9953 12:23:02.628968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9954 12:23:02.632510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9955 12:23:02.639029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9956 12:23:02.642422 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9957 12:23:02.649351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9958 12:23:02.652520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9959 12:23:02.658962 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9960 12:23:02.662890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9961 12:23:02.669116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9962 12:23:02.672648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9963 12:23:02.679361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9964 12:23:02.682583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9965 12:23:02.688915 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9966 12:23:02.692583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9967 12:23:02.698880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9968 12:23:02.702218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9969 12:23:02.708909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9970 12:23:02.712650 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9971 12:23:02.719082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9972 12:23:02.722542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9973 12:23:02.728901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9974 12:23:02.731982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9975 12:23:02.738824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9976 12:23:02.742360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9977 12:23:02.745543 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9978 12:23:02.748803 INFO: [APUAPC] vio 0
9979 12:23:02.755626 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9980 12:23:02.758918 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9981 12:23:02.761791 INFO: [APUAPC] D0_APC_0: 0x400510
9982 12:23:02.765272 INFO: [APUAPC] D0_APC_1: 0x0
9983 12:23:02.769087 INFO: [APUAPC] D0_APC_2: 0x1540
9984 12:23:02.772228 INFO: [APUAPC] D0_APC_3: 0x0
9985 12:23:02.775557 INFO: [APUAPC] D1_APC_0: 0xffffffff
9986 12:23:02.778528 INFO: [APUAPC] D1_APC_1: 0xffffffff
9987 12:23:02.782308 INFO: [APUAPC] D1_APC_2: 0x3fffff
9988 12:23:02.785328 INFO: [APUAPC] D1_APC_3: 0x0
9989 12:23:02.788942 INFO: [APUAPC] D2_APC_0: 0xffffffff
9990 12:23:02.792162 INFO: [APUAPC] D2_APC_1: 0xffffffff
9991 12:23:02.795390 INFO: [APUAPC] D2_APC_2: 0x3fffff
9992 12:23:02.795519 INFO: [APUAPC] D2_APC_3: 0x0
9993 12:23:02.798835 INFO: [APUAPC] D3_APC_0: 0xffffffff
9994 12:23:02.802245 INFO: [APUAPC] D3_APC_1: 0xffffffff
9995 12:23:02.805576 INFO: [APUAPC] D3_APC_2: 0x3fffff
9996 12:23:02.809108 INFO: [APUAPC] D3_APC_3: 0x0
9997 12:23:02.812165 INFO: [APUAPC] D4_APC_0: 0xffffffff
9998 12:23:02.815492 INFO: [APUAPC] D4_APC_1: 0xffffffff
9999 12:23:02.818926 INFO: [APUAPC] D4_APC_2: 0x3fffff
10000 12:23:02.822528 INFO: [APUAPC] D4_APC_3: 0x0
10001 12:23:02.825493 INFO: [APUAPC] D5_APC_0: 0xffffffff
10002 12:23:02.829060 INFO: [APUAPC] D5_APC_1: 0xffffffff
10003 12:23:02.832580 INFO: [APUAPC] D5_APC_2: 0x3fffff
10004 12:23:02.835574 INFO: [APUAPC] D5_APC_3: 0x0
10005 12:23:02.839170 INFO: [APUAPC] D6_APC_0: 0xffffffff
10006 12:23:02.842485 INFO: [APUAPC] D6_APC_1: 0xffffffff
10007 12:23:02.846124 INFO: [APUAPC] D6_APC_2: 0x3fffff
10008 12:23:02.848897 INFO: [APUAPC] D6_APC_3: 0x0
10009 12:23:02.852356 INFO: [APUAPC] D7_APC_0: 0xffffffff
10010 12:23:02.856038 INFO: [APUAPC] D7_APC_1: 0xffffffff
10011 12:23:02.858964 INFO: [APUAPC] D7_APC_2: 0x3fffff
10012 12:23:02.862499 INFO: [APUAPC] D7_APC_3: 0x0
10013 12:23:02.866199 INFO: [APUAPC] D8_APC_0: 0xffffffff
10014 12:23:02.869203 INFO: [APUAPC] D8_APC_1: 0xffffffff
10015 12:23:02.872645 INFO: [APUAPC] D8_APC_2: 0x3fffff
10016 12:23:02.875683 INFO: [APUAPC] D8_APC_3: 0x0
10017 12:23:02.878998 INFO: [APUAPC] D9_APC_0: 0xffffffff
10018 12:23:02.882332 INFO: [APUAPC] D9_APC_1: 0xffffffff
10019 12:23:02.885743 INFO: [APUAPC] D9_APC_2: 0x3fffff
10020 12:23:02.888927 INFO: [APUAPC] D9_APC_3: 0x0
10021 12:23:02.892834 INFO: [APUAPC] D10_APC_0: 0xffffffff
10022 12:23:02.895677 INFO: [APUAPC] D10_APC_1: 0xffffffff
10023 12:23:02.899150 INFO: [APUAPC] D10_APC_2: 0x3fffff
10024 12:23:02.902629 INFO: [APUAPC] D10_APC_3: 0x0
10025 12:23:02.905940 INFO: [APUAPC] D11_APC_0: 0xffffffff
10026 12:23:02.909377 INFO: [APUAPC] D11_APC_1: 0xffffffff
10027 12:23:02.912499 INFO: [APUAPC] D11_APC_2: 0x3fffff
10028 12:23:02.915937 INFO: [APUAPC] D11_APC_3: 0x0
10029 12:23:02.918980 INFO: [APUAPC] D12_APC_0: 0xffffffff
10030 12:23:02.922804 INFO: [APUAPC] D12_APC_1: 0xffffffff
10031 12:23:02.925710 INFO: [APUAPC] D12_APC_2: 0x3fffff
10032 12:23:02.929004 INFO: [APUAPC] D12_APC_3: 0x0
10033 12:23:02.932539 INFO: [APUAPC] D13_APC_0: 0xffffffff
10034 12:23:02.935877 INFO: [APUAPC] D13_APC_1: 0xffffffff
10035 12:23:02.939196 INFO: [APUAPC] D13_APC_2: 0x3fffff
10036 12:23:02.942835 INFO: [APUAPC] D13_APC_3: 0x0
10037 12:23:02.945751 INFO: [APUAPC] D14_APC_0: 0xffffffff
10038 12:23:02.949051 INFO: [APUAPC] D14_APC_1: 0xffffffff
10039 12:23:02.952504 INFO: [APUAPC] D14_APC_2: 0x3fffff
10040 12:23:02.955540 INFO: [APUAPC] D14_APC_3: 0x0
10041 12:23:02.958894 INFO: [APUAPC] D15_APC_0: 0xffffffff
10042 12:23:02.962849 INFO: [APUAPC] D15_APC_1: 0xffffffff
10043 12:23:02.965612 INFO: [APUAPC] D15_APC_2: 0x3fffff
10044 12:23:02.969097 INFO: [APUAPC] D15_APC_3: 0x0
10045 12:23:02.969168 INFO: [APUAPC] APC_CON: 0x4
10046 12:23:02.972417 INFO: [NOCDAPC] D0_APC_0: 0x0
10047 12:23:02.975785 INFO: [NOCDAPC] D0_APC_1: 0x0
10048 12:23:02.979138 INFO: [NOCDAPC] D1_APC_0: 0x0
10049 12:23:02.982526 INFO: [NOCDAPC] D1_APC_1: 0xfff
10050 12:23:02.985986 INFO: [NOCDAPC] D2_APC_0: 0x0
10051 12:23:02.989398 INFO: [NOCDAPC] D2_APC_1: 0xfff
10052 12:23:02.992676 INFO: [NOCDAPC] D3_APC_0: 0x0
10053 12:23:02.996527 INFO: [NOCDAPC] D3_APC_1: 0xfff
10054 12:23:02.999115 INFO: [NOCDAPC] D4_APC_0: 0x0
10055 12:23:02.999213 INFO: [NOCDAPC] D4_APC_1: 0xfff
10056 12:23:03.002686 INFO: [NOCDAPC] D5_APC_0: 0x0
10057 12:23:03.005736 INFO: [NOCDAPC] D5_APC_1: 0xfff
10058 12:23:03.009889 INFO: [NOCDAPC] D6_APC_0: 0x0
10059 12:23:03.012483 INFO: [NOCDAPC] D6_APC_1: 0xfff
10060 12:23:03.016545 INFO: [NOCDAPC] D7_APC_0: 0x0
10061 12:23:03.019654 INFO: [NOCDAPC] D7_APC_1: 0xfff
10062 12:23:03.022750 INFO: [NOCDAPC] D8_APC_0: 0x0
10063 12:23:03.025967 INFO: [NOCDAPC] D8_APC_1: 0xfff
10064 12:23:03.029289 INFO: [NOCDAPC] D9_APC_0: 0x0
10065 12:23:03.029396 INFO: [NOCDAPC] D9_APC_1: 0xfff
10066 12:23:03.032854 INFO: [NOCDAPC] D10_APC_0: 0x0
10067 12:23:03.036197 INFO: [NOCDAPC] D10_APC_1: 0xfff
10068 12:23:03.039267 INFO: [NOCDAPC] D11_APC_0: 0x0
10069 12:23:03.042432 INFO: [NOCDAPC] D11_APC_1: 0xfff
10070 12:23:03.046146 INFO: [NOCDAPC] D12_APC_0: 0x0
10071 12:23:03.049546 INFO: [NOCDAPC] D12_APC_1: 0xfff
10072 12:23:03.052964 INFO: [NOCDAPC] D13_APC_0: 0x0
10073 12:23:03.056588 INFO: [NOCDAPC] D13_APC_1: 0xfff
10074 12:23:03.059365 INFO: [NOCDAPC] D14_APC_0: 0x0
10075 12:23:03.063110 INFO: [NOCDAPC] D14_APC_1: 0xfff
10076 12:23:03.066549 INFO: [NOCDAPC] D15_APC_0: 0x0
10077 12:23:03.069356 INFO: [NOCDAPC] D15_APC_1: 0xfff
10078 12:23:03.069458 INFO: [NOCDAPC] APC_CON: 0x4
10079 12:23:03.072739 INFO: [APUAPC] set_apusys_apc done
10080 12:23:03.076351 INFO: [DEVAPC] devapc_init done
10081 12:23:03.082837 INFO: GICv3 without legacy support detected.
10082 12:23:03.086662 INFO: ARM GICv3 driver initialized in EL3
10083 12:23:03.089543 INFO: Maximum SPI INTID supported: 639
10084 12:23:03.093184 INFO: BL31: Initializing runtime services
10085 12:23:03.099921 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10086 12:23:03.103342 INFO: SPM: enable CPC mode
10087 12:23:03.106387 INFO: mcdi ready for mcusys-off-idle and system suspend
10088 12:23:03.113353 INFO: BL31: Preparing for EL3 exit to normal world
10089 12:23:03.116436 INFO: Entry point address = 0x80000000
10090 12:23:03.116525 INFO: SPSR = 0x8
10091 12:23:03.122967
10092 12:23:03.123076
10093 12:23:03.123161
10094 12:23:03.126415 Starting depthcharge on Spherion...
10095 12:23:03.126523
10096 12:23:03.126615 Wipe memory regions:
10097 12:23:03.126704
10098 12:23:03.127423 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10099 12:23:03.127563 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10100 12:23:03.127649 Setting prompt string to ['asurada:']
10101 12:23:03.127736 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10102 12:23:03.129362 [0x00000040000000, 0x00000054600000)
10103 12:23:03.251993
10104 12:23:03.252120 [0x00000054660000, 0x00000080000000)
10105 12:23:03.512556
10106 12:23:03.512690 [0x000000821a7280, 0x000000ffe64000)
10107 12:23:04.257066
10108 12:23:04.257223 [0x00000100000000, 0x00000240000000)
10109 12:23:06.148069
10110 12:23:06.150507 Initializing XHCI USB controller at 0x11200000.
10111 12:23:07.189893
10112 12:23:07.193062 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10113 12:23:07.193152
10114 12:23:07.193218
10115 12:23:07.193279
10116 12:23:07.193559 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 12:23:07.293914 asurada: tftpboot 192.168.201.1 11893144/tftp-deploy-1bt2atx6/kernel/image.itb 11893144/tftp-deploy-1bt2atx6/kernel/cmdline
10119 12:23:07.294053 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10120 12:23:07.294139 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10121 12:23:07.298703 tftpboot 192.168.201.1 11893144/tftp-deploy-1bt2atx6/kernel/image.itp-deploy-1bt2atx6/kernel/cmdline
10122 12:23:07.298827
10123 12:23:07.298891 Waiting for link
10124 12:23:07.458480
10125 12:23:07.458633 R8152: Initializing
10126 12:23:07.458752
10127 12:23:07.462117 Version 6 (ocp_data = 5c30)
10128 12:23:07.462219
10129 12:23:07.465595 R8152: Done initializing
10130 12:23:07.465722
10131 12:23:07.465796 Adding net device
10132 12:23:09.431401
10133 12:23:09.431586 done.
10134 12:23:09.431659
10135 12:23:09.431721 MAC: 00:24:32:30:78:52
10136 12:23:09.431781
10137 12:23:09.434674 Sending DHCP discover... done.
10138 12:23:09.434799
10139 12:23:09.437574 Waiting for reply... done.
10140 12:23:09.437656
10141 12:23:09.441148 Sending DHCP request... done.
10142 12:23:09.441230
10143 12:23:09.446562 Waiting for reply... done.
10144 12:23:09.446645
10145 12:23:09.446738 My ip is 192.168.201.14
10146 12:23:09.446818
10147 12:23:09.449823 The DHCP server ip is 192.168.201.1
10148 12:23:09.449905
10149 12:23:09.456157 TFTP server IP predefined by user: 192.168.201.1
10150 12:23:09.456265
10151 12:23:09.462959 Bootfile predefined by user: 11893144/tftp-deploy-1bt2atx6/kernel/image.itb
10152 12:23:09.463049
10153 12:23:09.463115 Sending tftp read request... done.
10154 12:23:09.466463
10155 12:23:09.469899 Waiting for the transfer...
10156 12:23:09.469981
10157 12:23:10.036204 00000000 ################################################################
10158 12:23:10.036358
10159 12:23:10.563888 00080000 ################################################################
10160 12:23:10.564034
10161 12:23:11.090945 00100000 ################################################################
10162 12:23:11.091093
10163 12:23:11.617862 00180000 ################################################################
10164 12:23:11.618000
10165 12:23:12.162405 00200000 ################################################################
10166 12:23:12.162592
10167 12:23:12.689032 00280000 ################################################################
10168 12:23:12.689168
10169 12:23:13.218048 00300000 ################################################################
10170 12:23:13.218183
10171 12:23:13.743445 00380000 ################################################################
10172 12:23:13.743594
10173 12:23:14.269292 00400000 ################################################################
10174 12:23:14.269422
10175 12:23:14.817282 00480000 ################################################################
10176 12:23:14.817416
10177 12:23:15.343428 00500000 ################################################################
10178 12:23:15.343574
10179 12:23:15.867687 00580000 ################################################################
10180 12:23:15.867824
10181 12:23:16.390503 00600000 ################################################################
10182 12:23:16.390639
10183 12:23:16.912844 00680000 ################################################################
10184 12:23:16.912990
10185 12:23:17.437353 00700000 ################################################################
10186 12:23:17.437497
10187 12:23:17.965086 00780000 ################################################################
10188 12:23:17.965225
10189 12:23:18.490816 00800000 ################################################################
10190 12:23:18.490963
10191 12:23:19.015703 00880000 ################################################################
10192 12:23:19.015852
10193 12:23:19.546483 00900000 ################################################################
10194 12:23:19.546658
10195 12:23:20.069040 00980000 ################################################################
10196 12:23:20.069186
10197 12:23:20.597340 00a00000 ################################################################
10198 12:23:20.597486
10199 12:23:21.125002 00a80000 ################################################################
10200 12:23:21.125149
10201 12:23:21.652690 00b00000 ################################################################
10202 12:23:21.652832
10203 12:23:22.177294 00b80000 ################################################################
10204 12:23:22.177465
10205 12:23:22.702680 00c00000 ################################################################
10206 12:23:22.702879
10207 12:23:23.239314 00c80000 ################################################################
10208 12:23:23.239483
10209 12:23:23.766668 00d00000 ################################################################
10210 12:23:23.766879
10211 12:23:24.297944 00d80000 ################################################################
10212 12:23:24.298094
10213 12:23:24.826231 00e00000 ################################################################
10214 12:23:24.826381
10215 12:23:25.350131 00e80000 ################################################################
10216 12:23:25.350275
10217 12:23:25.889469 00f00000 ################################################################
10218 12:23:25.889604
10219 12:23:26.409653 00f80000 ################################################################
10220 12:23:26.409791
10221 12:23:26.934507 01000000 ################################################################
10222 12:23:26.934657
10223 12:23:27.464630 01080000 ################################################################
10224 12:23:27.464780
10225 12:23:27.985009 01100000 ################################################################
10226 12:23:27.985162
10227 12:23:28.513744 01180000 ################################################################
10228 12:23:28.513883
10229 12:23:29.039781 01200000 ################################################################
10230 12:23:29.039920
10231 12:23:29.565250 01280000 ################################################################
10232 12:23:29.565404
10233 12:23:30.087014 01300000 ################################################################
10234 12:23:30.087164
10235 12:23:30.611082 01380000 ################################################################
10236 12:23:30.611232
10237 12:23:31.141386 01400000 ################################################################
10238 12:23:31.141533
10239 12:23:31.710951 01480000 ################################################################
10240 12:23:31.711108
10241 12:23:32.259809 01500000 ################################################################
10242 12:23:32.259947
10243 12:23:32.801834 01580000 ################################################################
10244 12:23:32.801975
10245 12:23:33.329003 01600000 ################################################################
10246 12:23:33.329184
10247 12:23:33.867028 01680000 ################################################################
10248 12:23:33.867164
10249 12:23:34.435080 01700000 ################################################################
10250 12:23:34.435566
10251 12:23:35.050788 01780000 ################################################################
10252 12:23:35.050924
10253 12:23:35.697791 01800000 ################################################################
10254 12:23:35.697929
10255 12:23:36.310203 01880000 ################################################################
10256 12:23:36.310340
10257 12:23:36.860131 01900000 ################################################################
10258 12:23:36.860267
10259 12:23:37.416378 01980000 ################################################################
10260 12:23:37.416526
10261 12:23:37.972896 01a00000 ################################################################
10262 12:23:37.973060
10263 12:23:38.536507 01a80000 ################################################################
10264 12:23:38.536738
10265 12:23:39.100449 01b00000 ################################################################
10266 12:23:39.100587
10267 12:23:39.162484 01b80000 ####### done.
10268 12:23:39.162996
10269 12:23:39.165839 The bootfile was 28888618 bytes long.
10270 12:23:39.166264
10271 12:23:39.169228 Sending tftp read request... done.
10272 12:23:39.169644
10273 12:23:39.172926 Waiting for the transfer...
10274 12:23:39.173340
10275 12:23:39.173670 00000000 # done.
10276 12:23:39.173985
10277 12:23:39.179679 Command line loaded dynamically from TFTP file: 11893144/tftp-deploy-1bt2atx6/kernel/cmdline
10278 12:23:39.180100
10279 12:23:39.203241 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893144/extract-nfsrootfs-s136c99f,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10280 12:23:39.203900
10281 12:23:39.204402 Loading FIT.
10282 12:23:39.204865
10283 12:23:39.206467 Image ramdisk-1 has 17791311 bytes.
10284 12:23:39.206929
10285 12:23:39.210078 Image fdt-1 has 47278 bytes.
10286 12:23:39.210497
10287 12:23:39.213332 Image kernel-1 has 11047994 bytes.
10288 12:23:39.213780
10289 12:23:39.223618 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10290 12:23:39.224049
10291 12:23:39.239691 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10292 12:23:39.240229
10293 12:23:39.246702 Choosing best match conf-1 for compat google,spherion-rev2.
10294 12:23:39.247284
10295 12:23:39.254132 Connected to device vid:did:rid of 1ae0:0028:00
10296 12:23:39.262316
10297 12:23:39.265504 tpm_get_response: command 0x17b, return code 0x0
10298 12:23:39.265925
10299 12:23:39.268571 ec_init: CrosEC protocol v3 supported (256, 248)
10300 12:23:39.272666
10301 12:23:39.276219 tpm_cleanup: add release locality here.
10302 12:23:39.276643
10303 12:23:39.276972 Shutting down all USB controllers.
10304 12:23:39.277282
10305 12:23:39.279653 Removing current net device
10306 12:23:39.280068
10307 12:23:39.286494 Exiting depthcharge with code 4 at timestamp: 65516070
10308 12:23:39.287094
10309 12:23:39.290060 LZMA decompressing kernel-1 to 0x821a6718
10310 12:23:39.290694
10311 12:23:39.292703 LZMA decompressing kernel-1 to 0x40000000
10312 12:23:40.680771
10313 12:23:40.680911 jumping to kernel
10314 12:23:40.681370 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10315 12:23:40.681472 start: 2.2.5 auto-login-action (timeout 00:03:48) [common]
10316 12:23:40.681553 Setting prompt string to ['Linux version [0-9]']
10317 12:23:40.681622 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10318 12:23:40.681692 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10319 12:23:40.762532
10320 12:23:40.765602 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10321 12:23:40.769086 start: 2.2.5.1 login-action (timeout 00:03:48) [common]
10322 12:23:40.769212 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10323 12:23:40.769317 Setting prompt string to []
10324 12:23:40.769411 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10325 12:23:40.769486 Using line separator: #'\n'#
10326 12:23:40.769560 No login prompt set.
10327 12:23:40.769640 Parsing kernel messages
10328 12:23:40.769724 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10329 12:23:40.769826 [login-action] Waiting for messages, (timeout 00:03:48)
10330 12:23:40.789179 [ 0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023
10331 12:23:40.792803 [ 0.000000] random: crng init done
10332 12:23:40.795488 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10333 12:23:40.798948 [ 0.000000] efi: UEFI not found.
10334 12:23:40.809086 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10335 12:23:40.815808 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10336 12:23:40.826036 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10337 12:23:40.835583 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10338 12:23:40.842337 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10339 12:23:40.846024 [ 0.000000] printk: bootconsole [mtk8250] enabled
10340 12:23:40.854677 [ 0.000000] NUMA: No NUMA configuration found
10341 12:23:40.860623 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10342 12:23:40.867284 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10343 12:23:40.867368 [ 0.000000] Zone ranges:
10344 12:23:40.873897 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10345 12:23:40.877354 [ 0.000000] DMA32 empty
10346 12:23:40.884147 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10347 12:23:40.887772 [ 0.000000] Movable zone start for each node
10348 12:23:40.891090 [ 0.000000] Early memory node ranges
10349 12:23:40.897803 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10350 12:23:40.903896 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10351 12:23:40.911017 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10352 12:23:40.917463 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10353 12:23:40.923781 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10354 12:23:40.930850 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10355 12:23:40.986651 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10356 12:23:40.993228 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10357 12:23:41.000329 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10358 12:23:41.003456 [ 0.000000] psci: probing for conduit method from DT.
10359 12:23:41.010272 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10360 12:23:41.013277 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10361 12:23:41.020145 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10362 12:23:41.023042 [ 0.000000] psci: SMC Calling Convention v1.2
10363 12:23:41.029854 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10364 12:23:41.033081 [ 0.000000] Detected VIPT I-cache on CPU0
10365 12:23:41.039978 [ 0.000000] CPU features: detected: GIC system register CPU interface
10366 12:23:41.046716 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10367 12:23:41.053569 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10368 12:23:41.059629 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10369 12:23:41.066676 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10370 12:23:41.073172 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10371 12:23:41.079923 [ 0.000000] alternatives: applying boot alternatives
10372 12:23:41.083280 [ 0.000000] Fallback order for Node 0: 0
10373 12:23:41.089757 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10374 12:23:41.093244 [ 0.000000] Policy zone: Normal
10375 12:23:41.116636 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893144/extract-nfsrootfs-s136c99f,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10376 12:23:41.129855 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10377 12:23:41.139806 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10378 12:23:41.149853 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10379 12:23:41.156456 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10380 12:23:41.159884 <6>[ 0.000000] software IO TLB: area num 8.
10381 12:23:41.216433 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10382 12:23:41.365340 <6>[ 0.000000] Memory: 7952112K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 400656K reserved, 32768K cma-reserved)
10383 12:23:41.372245 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10384 12:23:41.379121 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10385 12:23:41.381898 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10386 12:23:41.389122 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10387 12:23:41.395303 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10388 12:23:41.398881 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10389 12:23:41.408903 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10390 12:23:41.416007 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10391 12:23:41.418661 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10392 12:23:41.426614 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10393 12:23:41.429612 <6>[ 0.000000] GICv3: 608 SPIs implemented
10394 12:23:41.436236 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10395 12:23:41.439597 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10396 12:23:41.443011 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10397 12:23:41.452955 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10398 12:23:41.463170 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10399 12:23:41.476453 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10400 12:23:41.482600 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10401 12:23:41.491523 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10402 12:23:41.505093 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10403 12:23:41.512265 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10404 12:23:41.518474 <6>[ 0.009181] Console: colour dummy device 80x25
10405 12:23:41.528874 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10406 12:23:41.532268 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10407 12:23:41.538862 <6>[ 0.029223] LSM: Security Framework initializing
10408 12:23:41.545582 <6>[ 0.034163] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 12:23:41.555454 <6>[ 0.041977] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 12:23:41.562505 <6>[ 0.051394] cblist_init_generic: Setting adjustable number of callback queues.
10411 12:23:41.568911 <6>[ 0.058838] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 12:23:41.575445 <6>[ 0.065177] cblist_init_generic: Setting adjustable number of callback queues.
10413 12:23:41.582235 <6>[ 0.072604] cblist_init_generic: Setting shift to 3 and lim to 1.
10414 12:23:41.588467 <6>[ 0.079005] rcu: Hierarchical SRCU implementation.
10415 12:23:41.591659 <6>[ 0.084020] rcu: Max phase no-delay instances is 1000.
10416 12:23:41.600265 <6>[ 0.091041] EFI services will not be available.
10417 12:23:41.603258 <6>[ 0.096028] smp: Bringing up secondary CPUs ...
10418 12:23:41.612464 <6>[ 0.101080] Detected VIPT I-cache on CPU1
10419 12:23:41.619181 <6>[ 0.101150] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10420 12:23:41.625585 <6>[ 0.101179] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10421 12:23:41.629396 <6>[ 0.101518] Detected VIPT I-cache on CPU2
10422 12:23:41.635795 <6>[ 0.101570] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10423 12:23:41.642657 <6>[ 0.101588] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10424 12:23:41.649083 <6>[ 0.101847] Detected VIPT I-cache on CPU3
10425 12:23:41.655882 <6>[ 0.101893] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10426 12:23:41.662439 <6>[ 0.101907] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10427 12:23:41.665533 <6>[ 0.102213] CPU features: detected: Spectre-v4
10428 12:23:41.672409 <6>[ 0.102219] CPU features: detected: Spectre-BHB
10429 12:23:41.676066 <6>[ 0.102223] Detected PIPT I-cache on CPU4
10430 12:23:41.682226 <6>[ 0.102281] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10431 12:23:41.689095 <6>[ 0.102297] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10432 12:23:41.695792 <6>[ 0.102594] Detected PIPT I-cache on CPU5
10433 12:23:41.702200 <6>[ 0.102657] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10434 12:23:41.708767 <6>[ 0.102674] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10435 12:23:41.712420 <6>[ 0.102956] Detected PIPT I-cache on CPU6
10436 12:23:41.719089 <6>[ 0.103020] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10437 12:23:41.725310 <6>[ 0.103036] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10438 12:23:41.728808 <6>[ 0.103331] Detected PIPT I-cache on CPU7
10439 12:23:41.738849 <6>[ 0.103398] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10440 12:23:41.745780 <6>[ 0.103414] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10441 12:23:41.749293 <6>[ 0.103461] smp: Brought up 1 node, 8 CPUs
10442 12:23:41.752500 <6>[ 0.244948] SMP: Total of 8 processors activated.
10443 12:23:41.759202 <6>[ 0.249870] CPU features: detected: 32-bit EL0 Support
10444 12:23:41.769344 <6>[ 0.255234] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10445 12:23:41.775952 <6>[ 0.264080] CPU features: detected: Common not Private translations
10446 12:23:41.779057 <6>[ 0.270596] CPU features: detected: CRC32 instructions
10447 12:23:41.785348 <6>[ 0.275981] CPU features: detected: RCpc load-acquire (LDAPR)
10448 12:23:41.792031 <6>[ 0.281941] CPU features: detected: LSE atomic instructions
10449 12:23:41.799027 <6>[ 0.287759] CPU features: detected: Privileged Access Never
10450 12:23:41.802418 <6>[ 0.293539] CPU features: detected: RAS Extension Support
10451 12:23:41.808954 <6>[ 0.299148] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10452 12:23:41.815700 <6>[ 0.306366] CPU: All CPU(s) started at EL2
10453 12:23:41.818950 <6>[ 0.310683] alternatives: applying system-wide alternatives
10454 12:23:41.830439 <6>[ 0.321411] devtmpfs: initialized
10455 12:23:41.843170 <6>[ 0.330317] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10456 12:23:41.852838 <6>[ 0.340280] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10457 12:23:41.859327 <6>[ 0.348289] pinctrl core: initialized pinctrl subsystem
10458 12:23:41.862497 <6>[ 0.354971] DMI not present or invalid.
10459 12:23:41.869250 <6>[ 0.359387] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10460 12:23:41.879678 <6>[ 0.366272] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10461 12:23:41.886272 <6>[ 0.373857] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10462 12:23:41.892914 <6>[ 0.382075] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10463 12:23:41.900359 <6>[ 0.390319] audit: initializing netlink subsys (disabled)
10464 12:23:41.909836 <5>[ 0.396014] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10465 12:23:41.913246 <6>[ 0.396735] thermal_sys: Registered thermal governor 'step_wise'
10466 12:23:41.923162 <6>[ 0.403982] thermal_sys: Registered thermal governor 'power_allocator'
10467 12:23:41.926294 <6>[ 0.410240] cpuidle: using governor menu
10468 12:23:41.929516 <6>[ 0.421202] NET: Registered PF_QIPCRTR protocol family
10469 12:23:41.939827 <6>[ 0.426693] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10470 12:23:41.943208 <6>[ 0.433799] ASID allocator initialised with 32768 entries
10471 12:23:41.949369 <6>[ 0.440394] Serial: AMBA PL011 UART driver
10472 12:23:41.958566 <4>[ 0.449193] Trying to register duplicate clock ID: 134
10473 12:23:42.014824 <6>[ 0.508670] KASLR enabled
10474 12:23:42.028971 <6>[ 0.516422] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10475 12:23:42.035955 <6>[ 0.523433] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10476 12:23:42.042219 <6>[ 0.529924] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10477 12:23:42.049221 <6>[ 0.536929] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10478 12:23:42.055021 <6>[ 0.543419] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10479 12:23:42.061982 <6>[ 0.550426] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10480 12:23:42.068946 <6>[ 0.556913] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10481 12:23:42.075392 <6>[ 0.563920] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10482 12:23:42.078332 <6>[ 0.571430] ACPI: Interpreter disabled.
10483 12:23:42.086838 <6>[ 0.577835] iommu: Default domain type: Translated
10484 12:23:42.093602 <6>[ 0.582950] iommu: DMA domain TLB invalidation policy: strict mode
10485 12:23:42.097185 <5>[ 0.589579] SCSI subsystem initialized
10486 12:23:42.103460 <6>[ 0.593755] usbcore: registered new interface driver usbfs
10487 12:23:42.110285 <6>[ 0.599485] usbcore: registered new interface driver hub
10488 12:23:42.113723 <6>[ 0.605039] usbcore: registered new device driver usb
10489 12:23:42.120492 <6>[ 0.611137] pps_core: LinuxPPS API ver. 1 registered
10490 12:23:42.130429 <6>[ 0.616331] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10491 12:23:42.134030 <6>[ 0.625677] PTP clock support registered
10492 12:23:42.137147 <6>[ 0.629923] EDAC MC: Ver: 3.0.0
10493 12:23:42.144631 <6>[ 0.635090] FPGA manager framework
10494 12:23:42.148061 <6>[ 0.638770] Advanced Linux Sound Architecture Driver Initialized.
10495 12:23:42.152274 <6>[ 0.645558] vgaarb: loaded
10496 12:23:42.158693 <6>[ 0.648753] clocksource: Switched to clocksource arch_sys_counter
10497 12:23:42.165150 <5>[ 0.655188] VFS: Disk quotas dquot_6.6.0
10498 12:23:42.171846 <6>[ 0.659372] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10499 12:23:42.175204 <6>[ 0.666561] pnp: PnP ACPI: disabled
10500 12:23:42.183147 <6>[ 0.673258] NET: Registered PF_INET protocol family
10501 12:23:42.192744 <6>[ 0.678838] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10502 12:23:42.204328 <6>[ 0.691152] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10503 12:23:42.213795 <6>[ 0.699968] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10504 12:23:42.221113 <6>[ 0.707942] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10505 12:23:42.227487 <6>[ 0.716643] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10506 12:23:42.239805 <6>[ 0.726393] TCP: Hash tables configured (established 65536 bind 65536)
10507 12:23:42.246290 <6>[ 0.733251] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 12:23:42.252628 <6>[ 0.740449] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10509 12:23:42.259358 <6>[ 0.748146] NET: Registered PF_UNIX/PF_LOCAL protocol family
10510 12:23:42.266192 <6>[ 0.754318] RPC: Registered named UNIX socket transport module.
10511 12:23:42.269644 <6>[ 0.760475] RPC: Registered udp transport module.
10512 12:23:42.276097 <6>[ 0.765409] RPC: Registered tcp transport module.
10513 12:23:42.282921 <6>[ 0.770342] RPC: Registered tcp NFSv4.1 backchannel transport module.
10514 12:23:42.286134 <6>[ 0.777010] PCI: CLS 0 bytes, default 64
10515 12:23:42.289607 <6>[ 0.781380] Unpacking initramfs...
10516 12:23:42.306238 <6>[ 0.793390] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10517 12:23:42.316113 <6>[ 0.802053] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10518 12:23:42.319704 <6>[ 0.810901] kvm [1]: IPA Size Limit: 40 bits
10519 12:23:42.326214 <6>[ 0.815429] kvm [1]: GICv3: no GICV resource entry
10520 12:23:42.329682 <6>[ 0.820451] kvm [1]: disabling GICv2 emulation
10521 12:23:42.336177 <6>[ 0.825138] kvm [1]: GIC system register CPU interface enabled
10522 12:23:42.342809 <6>[ 0.832807] kvm [1]: vgic interrupt IRQ18
10523 12:23:42.346200 <6>[ 0.837179] kvm [1]: VHE mode initialized successfully
10524 12:23:42.353496 <5>[ 0.843696] Initialise system trusted keyrings
10525 12:23:42.360034 <6>[ 0.848471] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10526 12:23:42.368105 <6>[ 0.858482] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10527 12:23:42.374908 <5>[ 0.864964] NFS: Registering the id_resolver key type
10528 12:23:42.378450 <5>[ 0.870271] Key type id_resolver registered
10529 12:23:42.384723 <5>[ 0.874687] Key type id_legacy registered
10530 12:23:42.391671 <6>[ 0.878966] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10531 12:23:42.397782 <6>[ 0.885888] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10532 12:23:42.404676 <6>[ 0.893655] 9p: Installing v9fs 9p2000 file system support
10533 12:23:42.440489 <5>[ 0.930946] Key type asymmetric registered
10534 12:23:42.444256 <5>[ 0.935281] Asymmetric key parser 'x509' registered
10535 12:23:42.453262 <6>[ 0.940427] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10536 12:23:42.456930 <6>[ 0.948058] io scheduler mq-deadline registered
10537 12:23:42.460345 <6>[ 0.952838] io scheduler kyber registered
10538 12:23:42.479353 <6>[ 0.969902] EINJ: ACPI disabled.
10539 12:23:42.512131 <4>[ 0.995632] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 12:23:42.522241 <4>[ 1.006264] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 12:23:42.536799 <6>[ 1.027306] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10542 12:23:42.545100 <6>[ 1.035370] printk: console [ttyS0] disabled
10543 12:23:42.573166 <6>[ 1.060019] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10544 12:23:42.579605 <6>[ 1.069494] printk: console [ttyS0] enabled
10545 12:23:42.582912 <6>[ 1.069494] printk: console [ttyS0] enabled
10546 12:23:42.590009 <6>[ 1.078386] printk: bootconsole [mtk8250] disabled
10547 12:23:42.592930 <6>[ 1.078386] printk: bootconsole [mtk8250] disabled
10548 12:23:42.599257 <6>[ 1.089704] SuperH (H)SCI(F) driver initialized
10549 12:23:42.602520 <6>[ 1.094985] msm_serial: driver initialized
10550 12:23:42.616925 <6>[ 1.104030] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10551 12:23:42.627132 <6>[ 1.112581] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10552 12:23:42.633318 <6>[ 1.121125] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10553 12:23:42.643339 <6>[ 1.129754] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10554 12:23:42.650300 <6>[ 1.138462] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10555 12:23:42.659787 <6>[ 1.147182] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10556 12:23:42.669836 <6>[ 1.155723] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10557 12:23:42.676576 <6>[ 1.164530] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10558 12:23:42.686240 <6>[ 1.173073] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10559 12:23:42.698709 <6>[ 1.188908] loop: module loaded
10560 12:23:42.705189 <6>[ 1.194654] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10561 12:23:42.728137 <4>[ 1.218351] mtk-pmic-keys: Failed to locate of_node [id: -1]
10562 12:23:42.734594 <6>[ 1.225487] megasas: 07.719.03.00-rc1
10563 12:23:42.744602 <6>[ 1.235290] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10564 12:23:42.753814 <6>[ 1.244143] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10565 12:23:42.770774 <6>[ 1.260853] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10566 12:23:42.827019 <6>[ 1.310956] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10567 12:23:43.031751 <6>[ 1.522635] Freeing initrd memory: 17372K
10568 12:23:43.041455 <6>[ 1.532785] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10569 12:23:43.052426 <6>[ 1.543665] tun: Universal TUN/TAP device driver, 1.6
10570 12:23:43.056250 <6>[ 1.549749] thunder_xcv, ver 1.0
10571 12:23:43.059103 <6>[ 1.553254] thunder_bgx, ver 1.0
10572 12:23:43.062821 <6>[ 1.556750] nicpf, ver 1.0
10573 12:23:43.073359 <6>[ 1.560775] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10574 12:23:43.076933 <6>[ 1.568250] hns3: Copyright (c) 2017 Huawei Corporation.
10575 12:23:43.079731 <6>[ 1.573836] hclge is initializing
10576 12:23:43.086671 <6>[ 1.577417] e1000: Intel(R) PRO/1000 Network Driver
10577 12:23:43.093260 <6>[ 1.582546] e1000: Copyright (c) 1999-2006 Intel Corporation.
10578 12:23:43.097653 <6>[ 1.588562] e1000e: Intel(R) PRO/1000 Network Driver
10579 12:23:43.104180 <6>[ 1.593778] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10580 12:23:43.110266 <6>[ 1.599963] igb: Intel(R) Gigabit Ethernet Network Driver
10581 12:23:43.117253 <6>[ 1.605613] igb: Copyright (c) 2007-2014 Intel Corporation.
10582 12:23:43.123985 <6>[ 1.611449] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10583 12:23:43.126831 <6>[ 1.617966] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10584 12:23:43.134076 <6>[ 1.624434] sky2: driver version 1.30
10585 12:23:43.140197 <6>[ 1.629435] VFIO - User Level meta-driver version: 0.3
10586 12:23:43.147055 <6>[ 1.637665] usbcore: registered new interface driver usb-storage
10587 12:23:43.153790 <6>[ 1.644105] usbcore: registered new device driver onboard-usb-hub
10588 12:23:43.162678 <6>[ 1.653237] mt6397-rtc mt6359-rtc: registered as rtc0
10589 12:23:43.172996 <6>[ 1.658702] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:23:43 UTC (1698409423)
10590 12:23:43.176477 <6>[ 1.668294] i2c_dev: i2c /dev entries driver
10591 12:23:43.192685 <6>[ 1.680042] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10592 12:23:43.214174 <6>[ 1.704053] cpu cpu0: EM: created perf domain
10593 12:23:43.216661 <6>[ 1.708972] cpu cpu4: EM: created perf domain
10594 12:23:43.223929 <6>[ 1.714563] sdhci: Secure Digital Host Controller Interface driver
10595 12:23:43.231130 <6>[ 1.720998] sdhci: Copyright(c) Pierre Ossman
10596 12:23:43.237464 <6>[ 1.725963] Synopsys Designware Multimedia Card Interface Driver
10597 12:23:43.240715 <6>[ 1.732591] mmc0: CQHCI version 5.10
10598 12:23:43.247431 <6>[ 1.732595] sdhci-pltfm: SDHCI platform and OF driver helper
10599 12:23:43.254105 <6>[ 1.743198] ledtrig-cpu: registered to indicate activity on CPUs
10600 12:23:43.260587 <6>[ 1.750178] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10601 12:23:43.267287 <6>[ 1.757242] usbcore: registered new interface driver usbhid
10602 12:23:43.270665 <6>[ 1.763071] usbhid: USB HID core driver
10603 12:23:43.277490 <6>[ 1.767286] spi_master spi0: will run message pump with realtime priority
10604 12:23:43.325149 <6>[ 1.808865] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10605 12:23:43.343848 <6>[ 1.824515] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10606 12:23:43.351393 <6>[ 1.839955] cros-ec-spi spi0.0: Chrome EC device registered
10607 12:23:43.354464 <6>[ 1.845987] mmc0: Command Queue Engine enabled
10608 12:23:43.361796 <6>[ 1.850742] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10609 12:23:43.367960 <6>[ 1.857937] mmcblk0: mmc0:0001 DA4128 116 GiB
10610 12:23:43.377981 <6>[ 1.860101] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10611 12:23:43.381353 <6>[ 1.866897] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10612 12:23:43.388022 <6>[ 1.872990] NET: Registered PF_PACKET protocol family
10613 12:23:43.391406 <6>[ 1.879335] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10614 12:23:43.398177 <6>[ 1.883270] 9pnet: Installing 9P2000 support
10615 12:23:43.401695 <6>[ 1.889009] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10616 12:23:43.408259 <5>[ 1.892959] Key type dns_resolver registered
10617 12:23:43.414296 <6>[ 1.898782] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10618 12:23:43.417682 <6>[ 1.903192] registered taskstats version 1
10619 12:23:43.424215 <5>[ 1.913550] Loading compiled-in X.509 certificates
10620 12:23:43.453643 <4>[ 1.937964] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10621 12:23:43.464131 <4>[ 1.948652] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10622 12:23:43.470691 <3>[ 1.959183] debugfs: File 'uA_load' in directory '/' already present!
10623 12:23:43.477215 <3>[ 1.965886] debugfs: File 'min_uV' in directory '/' already present!
10624 12:23:43.484016 <3>[ 1.972546] debugfs: File 'max_uV' in directory '/' already present!
10625 12:23:43.490500 <3>[ 1.979157] debugfs: File 'constraint_flags' in directory '/' already present!
10626 12:23:43.501453 <3>[ 1.988867] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10627 12:23:43.512399 <6>[ 2.002898] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10628 12:23:43.519021 <6>[ 2.009758] xhci-mtk 11200000.usb: xHCI Host Controller
10629 12:23:43.525554 <6>[ 2.015300] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10630 12:23:43.536063 <6>[ 2.023170] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10631 12:23:43.542688 <6>[ 2.032608] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10632 12:23:43.549910 <6>[ 2.038703] xhci-mtk 11200000.usb: xHCI Host Controller
10633 12:23:43.556387 <6>[ 2.044182] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10634 12:23:43.562927 <6>[ 2.051832] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10635 12:23:43.569381 <6>[ 2.059739] hub 1-0:1.0: USB hub found
10636 12:23:43.573171 <6>[ 2.063768] hub 1-0:1.0: 1 port detected
10637 12:23:43.579350 <6>[ 2.068047] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10638 12:23:43.586433 <6>[ 2.076851] hub 2-0:1.0: USB hub found
10639 12:23:43.590067 <6>[ 2.080868] hub 2-0:1.0: 1 port detected
10640 12:23:43.598219 <6>[ 2.088951] mtk-msdc 11f70000.mmc: Got CD GPIO
10641 12:23:43.609943 <6>[ 2.097155] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10642 12:23:43.616941 <6>[ 2.105178] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10643 12:23:43.626474 <4>[ 2.113101] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10644 12:23:43.636746 <6>[ 2.122640] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10645 12:23:43.643835 <6>[ 2.130719] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10646 12:23:43.650202 <6>[ 2.138726] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10647 12:23:43.659938 <6>[ 2.146660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10648 12:23:43.666867 <6>[ 2.154477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10649 12:23:43.676862 <6>[ 2.162299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10650 12:23:43.686717 <6>[ 2.172669] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10651 12:23:43.693474 <6>[ 2.181032] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10652 12:23:43.703355 <6>[ 2.189381] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10653 12:23:43.710552 <6>[ 2.197721] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10654 12:23:43.717220 <6>[ 2.206060] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10655 12:23:43.727641 <6>[ 2.214400] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10656 12:23:43.734361 <6>[ 2.222738] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10657 12:23:43.744274 <6>[ 2.231076] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10658 12:23:43.750479 <6>[ 2.239414] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10659 12:23:43.760306 <6>[ 2.247753] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10660 12:23:43.767314 <6>[ 2.256112] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10661 12:23:43.777112 <6>[ 2.264454] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10662 12:23:43.783701 <6>[ 2.272795] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10663 12:23:43.793426 <6>[ 2.281134] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10664 12:23:43.800816 <6>[ 2.289473] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10665 12:23:43.807250 <6>[ 2.298200] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10666 12:23:43.814834 <6>[ 2.305363] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10667 12:23:43.821722 <6>[ 2.312128] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10668 12:23:43.831249 <6>[ 2.318876] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10669 12:23:43.838124 <6>[ 2.325808] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10670 12:23:43.844264 <6>[ 2.332585] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10671 12:23:43.854637 <6>[ 2.341712] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10672 12:23:43.864436 <6>[ 2.350831] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10673 12:23:43.874348 <6>[ 2.360128] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10674 12:23:43.884213 <6>[ 2.369597] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10675 12:23:43.891237 <6>[ 2.379071] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10676 12:23:43.900738 <6>[ 2.388191] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10677 12:23:43.911538 <6>[ 2.397658] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10678 12:23:43.921021 <6>[ 2.406778] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10679 12:23:43.931029 <6>[ 2.416073] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10680 12:23:43.940615 <6>[ 2.426233] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10681 12:23:43.950898 <6>[ 2.437713] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10682 12:23:43.957739 <6>[ 2.447448] Trying to probe devices needed for running init ...
10683 12:23:44.001113 <6>[ 2.489050] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10684 12:23:44.156400 <6>[ 2.647175] hub 1-1:1.0: USB hub found
10685 12:23:44.159810 <6>[ 2.651665] hub 1-1:1.0: 4 ports detected
10686 12:23:44.281352 <6>[ 2.769313] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10687 12:23:44.307807 <6>[ 2.798446] hub 2-1:1.0: USB hub found
10688 12:23:44.310902 <6>[ 2.802888] hub 2-1:1.0: 3 ports detected
10689 12:23:44.481384 <6>[ 2.969069] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10690 12:23:44.613888 <6>[ 3.104931] hub 1-1.4:1.0: USB hub found
10691 12:23:44.617281 <6>[ 3.109586] hub 1-1.4:1.0: 2 ports detected
10692 12:23:44.693615 <6>[ 3.181194] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10693 12:23:44.913612 <6>[ 3.401076] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10694 12:23:45.105204 <6>[ 3.593048] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10695 12:23:56.238832 <6>[ 14.734043] ALSA device list:
10696 12:23:56.245027 <6>[ 14.737338] No soundcards found.
10697 12:23:56.253019 <6>[ 14.745273] Freeing unused kernel memory: 8384K
10698 12:23:56.256711 <6>[ 14.750283] Run /init as init process
10699 12:23:56.268068 Loading, please wait...
10700 12:23:56.289290 Starting version 247.3-7+deb11u2
10701 12:23:56.513909 <6>[ 15.001842] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10702 12:23:56.522521 <6>[ 15.014063] remoteproc remoteproc0: scp is available
10703 12:23:56.528658 <6>[ 15.019836] remoteproc remoteproc0: powering up scp
10704 12:23:56.535251 <6>[ 15.025083] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10705 12:23:56.542577 <6>[ 15.034393] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10706 12:23:56.555086 <3>[ 15.043571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 12:23:56.561423 <3>[ 15.052010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 12:23:56.571309 <3>[ 15.060115] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 12:23:56.578846 <6>[ 15.065328] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10710 12:23:56.590202 <3>[ 15.078530] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 12:23:56.599641 <3>[ 15.087119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 12:23:56.606343 <3>[ 15.095317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 12:23:56.613054 <6>[ 15.101258] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10714 12:23:56.623313 <3>[ 15.103450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 12:23:56.629879 <6>[ 15.110994] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10716 12:23:56.639781 <4>[ 15.119063] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10717 12:23:56.643747 <4>[ 15.119063] Fallback method does not support PEC.
10718 12:23:56.652902 <4>[ 15.121486] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10719 12:23:56.656104 <6>[ 15.123473] mc: Linux media interface: v0.10
10720 12:23:56.663333 <4>[ 15.126900] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10721 12:23:56.673729 <6>[ 15.127790] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10722 12:23:56.680979 <3>[ 15.128233] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 12:23:56.687517 <3>[ 15.136675] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 12:23:56.697712 <3>[ 15.142281] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 12:23:56.700892 <6>[ 15.155011] usbcore: registered new interface driver r8152
10726 12:23:56.711019 <3>[ 15.160728] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 12:23:56.721104 <3>[ 15.161449] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10728 12:23:56.727736 <6>[ 15.161654] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10729 12:23:56.734830 <6>[ 15.161674] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10730 12:23:56.740836 <6>[ 15.161683] remoteproc remoteproc0: remote processor scp is now up
10731 12:23:56.747951 <6>[ 15.170613] videodev: Linux video capture interface: v2.00
10732 12:23:56.754216 <3>[ 15.177792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 12:23:56.764890 <3>[ 15.182443] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10734 12:23:56.771247 <6>[ 15.187704] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10735 12:23:56.780616 <3>[ 15.194137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 12:23:56.787255 <6>[ 15.202649] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10737 12:23:56.797166 <3>[ 15.207901] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 12:23:56.804312 <3>[ 15.207905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 12:23:56.813836 <3>[ 15.207911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 12:23:56.820224 <3>[ 15.207915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 12:23:56.830323 <3>[ 15.207948] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 12:23:56.837277 <6>[ 15.237371] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10743 12:23:56.846891 <6>[ 15.256973] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10744 12:23:56.857215 <6>[ 15.261709] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10745 12:23:56.863671 <6>[ 15.278655] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10746 12:23:56.870904 <6>[ 15.286397] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10747 12:23:56.880887 <4>[ 15.292688] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10748 12:23:56.890418 <4>[ 15.292697] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10749 12:23:56.893760 <6>[ 15.294077] pci_bus 0000:00: root bus resource [bus 00-ff]
10750 12:23:56.900483 <6>[ 15.294083] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10751 12:23:56.910129 <6>[ 15.294087] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10752 12:23:56.916760 <6>[ 15.294118] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10753 12:23:56.923708 <6>[ 15.326749] usbcore: registered new interface driver cdc_ether
10754 12:23:56.929980 <6>[ 15.335718] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10755 12:23:56.936928 <6>[ 15.349088] r8152 2-1.3:1.0 eth0: v1.12.13
10756 12:23:56.940949 <6>[ 15.352995] pci 0000:00:00.0: supports D1 D2
10757 12:23:56.946330 <6>[ 15.360559] usbcore: registered new interface driver r8153_ecm
10758 12:23:56.949854 <6>[ 15.360620] Bluetooth: Core ver 2.22
10759 12:23:56.956657 <6>[ 15.361110] NET: Registered PF_BLUETOOTH protocol family
10760 12:23:56.963298 <6>[ 15.361127] Bluetooth: HCI device and connection manager initialized
10761 12:23:56.966426 <6>[ 15.361207] Bluetooth: HCI socket layer initialized
10762 12:23:56.973666 <6>[ 15.361235] Bluetooth: L2CAP socket layer initialized
10763 12:23:56.976221 <6>[ 15.361314] Bluetooth: SCO socket layer initialized
10764 12:23:56.983467 <6>[ 15.368818] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10765 12:23:56.993009 <6>[ 15.369725] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10766 12:23:56.999622 <6>[ 15.379623] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10767 12:23:57.006951 <6>[ 15.386133] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10768 12:23:57.013547 <6>[ 15.387990] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10769 12:23:57.026537 <6>[ 15.393189] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10770 12:23:57.032854 <6>[ 15.398853] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10771 12:23:57.039424 <6>[ 15.408921] usbcore: registered new interface driver uvcvideo
10772 12:23:57.046573 <6>[ 15.409783] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10773 12:23:57.052693 <6>[ 15.415017] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10774 12:23:57.059383 <6>[ 15.415496] usbcore: registered new interface driver btusb
10775 12:23:57.069565 <4>[ 15.416248] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10776 12:23:57.076022 <3>[ 15.416255] Bluetooth: hci0: Failed to load firmware file (-2)
10777 12:23:57.079387 <3>[ 15.416258] Bluetooth: hci0: Failed to set up firmware (-2)
10778 12:23:57.089381 <4>[ 15.416260] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10779 12:23:57.099572 <6>[ 15.587920] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10780 12:23:57.102768 <6>[ 15.595497] pci 0000:01:00.0: supports D1 D2
10781 12:23:57.109357 <6>[ 15.600016] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10782 12:23:57.132028 <6>[ 15.620991] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10783 12:23:57.138990 <6>[ 15.627894] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10784 12:23:57.144925 <6>[ 15.635973] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10785 12:23:57.155260 <6>[ 15.643970] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10786 12:23:57.161506 <6>[ 15.651971] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10787 12:23:57.172246 <6>[ 15.659972] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10788 12:23:57.174958 <6>[ 15.667973] pci 0000:00:00.0: PCI bridge to [bus 01]
10789 12:23:57.185042 <6>[ 15.673189] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10790 12:23:57.191480 <6>[ 15.681308] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10791 12:23:57.198291 <6>[ 15.688134] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10792 12:23:57.204673 <6>[ 15.694771] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10793 12:23:57.219046 <5>[ 15.707832] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10794 12:23:57.235799 <5>[ 15.724434] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10795 12:23:57.242318 <4>[ 15.731340] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10796 12:23:57.248712 <6>[ 15.740231] cfg80211: failed to load regulatory.db
10797 12:23:57.296936 <6>[ 15.785589] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10798 12:23:57.303083 <6>[ 15.793110] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10799 12:23:57.327369 <6>[ 15.819776] mt7921e 0000:01:00.0: ASIC revision: 79610010
10800 12:23:57.436193 <4>[ 15.921426] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 12:23:57.454907 Begin: Loading essential drivers ... done.
10802 12:23:57.458115 Begin: Running /scripts/init-premount ... done.
10803 12:23:57.464700 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10804 12:23:57.475344 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10805 12:23:57.478204 Device /sys/class/net/enx002432307852 found
10806 12:23:57.478632 done.
10807 12:23:57.500541 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10808 12:23:57.555020 <4>[ 16.040889] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 12:23:57.675090 <4>[ 16.160892] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 12:23:57.794534 <4>[ 16.280442] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 12:23:57.914571 <4>[ 16.400466] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10812 12:23:58.034894 <4>[ 16.520390] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 12:23:58.154812 <4>[ 16.640437] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10814 12:23:58.274453 <4>[ 16.760303] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10815 12:23:58.394468 <4>[ 16.880336] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10816 12:23:58.507049 <6>[ 16.999489] r8152 2-1.3:1.0 enx002432307852: carrier on
10817 12:23:58.520588 <4>[ 17.005296] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10818 12:23:58.630039 <3>[ 17.122318] mt7921e 0000:01:00.0: hardware init failed
10819 12:23:58.666123 IP-Config: no response after 2 secs - giving up
10820 12:23:58.707857 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10821 12:23:58.711215 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10822 12:23:58.717933 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10823 12:23:58.724312 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10824 12:23:58.731362 host : mt8192-asurada-spherion-r0-cbg-3
10825 12:23:58.737650 domain : lava-rack
10826 12:23:58.740863 rootserver: 192.168.201.1 rootpath:
10827 12:23:58.744042 filename :
10828 12:23:58.832134 done.
10829 12:23:58.841037 Begin: Running /scripts/nfs-bottom ... done.
10830 12:23:58.859302 Begin: Running /scripts/init-bottom ... done.
10831 12:24:00.137857 <6>[ 18.630259] NET: Registered PF_INET6 protocol family
10832 12:24:00.145306 <6>[ 18.637228] Segment Routing with IPv6
10833 12:24:00.147898 <6>[ 18.641210] In-situ OAM (IOAM) with IPv6
10834 12:24:00.282877 <30>[ 18.758685] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10835 12:24:00.290087 <30>[ 18.783098] systemd[1]: Detected architecture arm64.
10836 12:24:00.313035
10837 12:24:00.316258 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10838 12:24:00.316681
10839 12:24:00.335140 <30>[ 18.827876] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10840 12:24:01.310552 <30>[ 19.800066] systemd[1]: Queued start job for default target Graphical Interface.
10841 12:24:01.342601 <30>[ 19.835503] systemd[1]: Created slice system-getty.slice.
10842 12:24:01.349231 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10843 12:24:01.365691 <30>[ 19.858467] systemd[1]: Created slice system-modprobe.slice.
10844 12:24:01.372498 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10845 12:24:01.390790 <30>[ 19.883197] systemd[1]: Created slice system-serial\x2dgetty.slice.
10846 12:24:01.400758 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10847 12:24:01.413544 <30>[ 19.906115] systemd[1]: Created slice User and Session Slice.
10848 12:24:01.419922 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10849 12:24:01.440874 <30>[ 19.929929] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10850 12:24:01.450138 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10851 12:24:01.468566 <30>[ 19.957796] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10852 12:24:01.475278 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10853 12:24:01.500192 <30>[ 19.985631] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10854 12:24:01.506655 <30>[ 19.997893] systemd[1]: Reached target Local Encrypted Volumes.
10855 12:24:01.512846 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10856 12:24:01.529350 <30>[ 20.021570] systemd[1]: Reached target Paths.
10857 12:24:01.532236 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10858 12:24:01.548685 <30>[ 20.041046] systemd[1]: Reached target Remote File Systems.
10859 12:24:01.555093 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10860 12:24:01.568392 <30>[ 20.061096] systemd[1]: Reached target Slices.
10861 12:24:01.572053 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10862 12:24:01.588143 <30>[ 20.081143] systemd[1]: Reached target Swap.
10863 12:24:01.591924 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10864 12:24:01.611930 <30>[ 20.101508] systemd[1]: Listening on initctl Compatibility Named Pipe.
10865 12:24:01.618482 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10866 12:24:01.625047 <30>[ 20.117780] systemd[1]: Listening on Journal Audit Socket.
10867 12:24:01.632172 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10868 12:24:01.650061 <30>[ 20.142498] systemd[1]: Listening on Journal Socket (/dev/log).
10869 12:24:01.656306 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10870 12:24:01.673115 <30>[ 20.165605] systemd[1]: Listening on Journal Socket.
10871 12:24:01.679123 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10872 12:24:01.697299 <30>[ 20.186744] systemd[1]: Listening on Network Service Netlink Socket.
10873 12:24:01.703567 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10874 12:24:01.719673 <30>[ 20.212346] systemd[1]: Listening on udev Control Socket.
10875 12:24:01.726142 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10876 12:24:01.741164 <30>[ 20.233484] systemd[1]: Listening on udev Kernel Socket.
10877 12:24:01.747640 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10878 12:24:01.800256 <30>[ 20.293248] systemd[1]: Mounting Huge Pages File System...
10879 12:24:01.806965 Mounting [0;1;39mHuge Pages File System[0m...
10880 12:24:01.824616 <30>[ 20.317296] systemd[1]: Mounting POSIX Message Queue File System...
10881 12:24:01.830657 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10882 12:24:01.852020 <30>[ 20.345117] systemd[1]: Mounting Kernel Debug File System...
10883 12:24:01.858252 Mounting [0;1;39mKernel Debug File System[0m...
10884 12:24:01.875594 <30>[ 20.365523] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10885 12:24:01.909273 <30>[ 20.398958] systemd[1]: Starting Create list of static device nodes for the current kernel...
10886 12:24:01.916056 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10887 12:24:01.961193 <30>[ 20.453887] systemd[1]: Starting Load Kernel Module configfs...
10888 12:24:01.967799 Starting [0;1;39mLoad Kernel Module configfs[0m...
10889 12:24:01.985196 <30>[ 20.478086] systemd[1]: Starting Load Kernel Module drm...
10890 12:24:01.991551 Starting [0;1;39mLoad Kernel Module drm[0m...
10891 12:24:02.007605 <30>[ 20.500522] systemd[1]: Starting Load Kernel Module fuse...
10892 12:24:02.014090 Starting [0;1;39mLoad Kernel Module fuse[0m...
10893 12:24:02.053813 <30>[ 20.542846] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10894 12:24:02.060106 <6>[ 20.553031] fuse: init (API version 7.37)
10895 12:24:02.068346 <30>[ 20.561302] systemd[1]: Starting Journal Service...
10896 12:24:02.071741 Starting [0;1;39mJournal Service[0m...
10897 12:24:02.133412 <30>[ 20.625946] systemd[1]: Starting Load Kernel Modules...
10898 12:24:02.139684 Starting [0;1;39mLoad Kernel Modules[0m...
10899 12:24:02.160106 <30>[ 20.649649] systemd[1]: Starting Remount Root and Kernel File Systems...
10900 12:24:02.166516 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10901 12:24:02.183350 <30>[ 20.676118] systemd[1]: Starting Coldplug All udev Devices...
10902 12:24:02.189591 Starting [0;1;39mColdplug All udev Devices[0m...
10903 12:24:02.208374 <30>[ 20.701582] systemd[1]: Mounted Huge Pages File System.
10904 12:24:02.215556 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10905 12:24:02.232979 <30>[ 20.725758] systemd[1]: Mounted POSIX Message Queue File System.
10906 12:24:02.239564 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10907 12:24:02.256896 <30>[ 20.749653] systemd[1]: Mounted Kernel Debug File System.
10908 12:24:02.270417 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0<3>[ 20.760868] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 12:24:02.270503 m.
10910 12:24:02.292495 <30>[ 20.781964] systemd[1]: Finished Create list of static device nodes for the current kernel.
10911 12:24:02.305686 [[0;32m OK [0m] Finished [0<3>[ 20.792366] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 12:24:02.308988 ;1;39mCreate list of st… nodes for the current kernel[0m.
10913 12:24:02.325205 <30>[ 20.818057] systemd[1]: modprobe@configfs.service: Succeeded.
10914 12:24:02.331776 <30>[ 20.824797] systemd[1]: Finished Load Kernel Module configfs.
10915 12:24:02.338237 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10916 12:24:02.357827 <3>[ 20.847327] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 12:24:02.364717 <30>[ 20.857961] systemd[1]: modprobe@drm.service: Succeeded.
10918 12:24:02.371969 <30>[ 20.864816] systemd[1]: Finished Load Kernel Module drm.
10919 12:24:02.378197 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10920 12:24:02.393625 <30>[ 20.886144] systemd[1]: modprobe@fuse.service: Succeeded.
10921 12:24:02.403912 <3>[ 20.888308] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:24:02.407169 <30>[ 20.892923] systemd[1]: Finished Load Kernel Module fuse.
10923 12:24:02.413895 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10924 12:24:02.431931 <3>[ 20.921715] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 12:24:02.439204 <30>[ 20.923125] systemd[1]: Finished Load Kernel Modules.
10926 12:24:02.442354 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10927 12:24:02.458247 <30>[ 20.950795] systemd[1]: Finished Remount Root and Kernel File Systems.
10928 12:24:02.468481 <3>[ 20.953707] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 12:24:02.475117 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10930 12:24:02.500087 <3>[ 20.990129] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 12:24:02.531234 <30>[ 21.024331] systemd[1]: Mounting FUSE Control File System...
10932 12:24:02.541018 <3>[ 21.025565] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 12:24:02.547872 Mounting [0;1;39mFUSE Control File System[0m...
10934 12:24:02.566551 <30>[ 21.058831] systemd[1]: Mounting Kernel Configuration File System...
10935 12:24:02.576759 Mountin<3>[ 21.067240] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 12:24:02.583079 g [0;1;39mKernel Configuration File System[0m...
10937 12:24:02.607055 <30>[ 21.096338] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10938 12:24:02.617507 <3>[ 21.098237] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 12:24:02.627319 <30>[ 21.105742] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10940 12:24:02.635394 <30>[ 21.127889] systemd[1]: Starting Load/Save Random Seed...
10941 12:24:02.641707 Starting [0;1;39mLoad/Save Random Seed[0m...
10942 12:24:02.660870 <30>[ 21.153885] systemd[1]: Starting Apply Kernel Variables...
10943 12:24:02.667481 Starting [0;1;39mApply Kernel Variables[0m...
10944 12:24:02.686836 <30>[ 21.179233] systemd[1]: Starting Create System Users...
10945 12:24:02.690475 Starting [0;1;39mCreate System Users[0m...
10946 12:24:02.710040 <4>[ 21.192192] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10947 12:24:02.716677 <3>[ 21.207890] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10948 12:24:02.723196 <30>[ 21.210312] systemd[1]: Started Journal Service.
10949 12:24:02.726252 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10950 12:24:02.754410 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10951 12:24:02.767995 See 'systemctl status systemd-udev-trigger.service' for details.
10952 12:24:02.784253 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10953 12:24:02.800456 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10954 12:24:02.817389 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10955 12:24:02.833984 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10956 12:24:02.850523 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10957 12:24:02.889254 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10958 12:24:02.907306 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10959 12:24:02.957194 <46>[ 21.446937] systemd-journald[295]: Received client request to flush runtime journal.
10960 12:24:03.463807 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10961 12:24:03.476947 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10962 12:24:03.491756 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10963 12:24:03.547523 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10964 12:24:04.362812 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10965 12:24:04.416236 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10966 12:24:04.474577 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10967 12:24:04.533185 Starting [0;1;39mNetwork Service[0m...
10968 12:24:04.836608 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10969 12:24:04.859353 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10970 12:24:04.906491 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10971 12:24:05.215819 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10972 12:24:05.235963 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10973 12:24:05.276829 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10974 12:24:05.297579 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10975 12:24:05.312036 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10976 12:24:05.355270 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10977 12:24:05.424683 Starting [0;1;39mNetwork Name Resolution[0m...
10978 12:24:05.451173 Starting [0;1;39mNetwork Time Synchronization[0m...
10979 12:24:05.471983 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10980 12:24:05.492458 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10981 12:24:05.523785 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10982 12:24:05.680742 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10983 12:24:05.696280 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10984 12:24:05.714794 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10985 12:24:05.727453 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10986 12:24:05.743693 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10987 12:24:05.784751 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10988 12:24:05.853437 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10989 12:24:05.906840 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10990 12:24:05.941591 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10991 12:24:05.955699 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10992 12:24:05.990030 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10993 12:24:06.003091 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10994 12:24:06.023073 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10995 12:24:06.076135 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10996 12:24:06.171674 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10997 12:24:06.212419 Starting [0;1;39mUser Login Management[0m...
10998 12:24:06.229140 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10999 12:24:06.244075 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11000 12:24:06.263096 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11001 12:24:06.304893 Starting [0;1;39mPermit User Sessions[0m...
11002 12:24:06.464973 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11003 12:24:06.526233 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11004 12:24:06.581290 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11005 12:24:06.587734 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11006 12:24:06.614767 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11007 12:24:06.630016 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11008 12:24:06.653270 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11009 12:24:06.668657 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11010 12:24:06.717973 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11011 12:24:06.790481 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11012 12:24:06.874454
11013 12:24:06.875097
11014 12:24:06.877566 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11015 12:24:06.877989
11016 12:24:06.881289 debian-bullseye-arm64 login: root (automatic login)
11017 12:24:06.881713
11018 12:24:06.882044
11019 12:24:07.305382 Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64
11020 12:24:07.305895
11021 12:24:07.312044 The programs included with the Debian GNU/Linux system are free software;
11022 12:24:07.318981 the exact distribution terms for each program are described in the
11023 12:24:07.321869 individual files in /usr/share/doc/*/copyright.
11024 12:24:07.322309
11025 12:24:07.328830 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11026 12:24:07.331866 permitted by applicable law.
11027 12:24:08.418471 Matched prompt #10: / #
11029 12:24:08.419636 Setting prompt string to ['/ #']
11030 12:24:08.420081 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11032 12:24:08.421078 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11033 12:24:08.421531 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
11034 12:24:08.421893 Setting prompt string to ['/ #']
11035 12:24:08.422249 Forcing a shell prompt, looking for ['/ #']
11037 12:24:08.473296 / #
11038 12:24:08.473957 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11039 12:24:08.474411 Waiting using forced prompt support (timeout 00:02:30)
11040 12:24:08.479619
11041 12:24:08.480561 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11042 12:24:08.481105 start: 2.2.7 export-device-env (timeout 00:03:20) [common]
11044 12:24:08.582420 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893144/extract-nfsrootfs-s136c99f'
11045 12:24:08.588273 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893144/extract-nfsrootfs-s136c99f'
11047 12:24:08.689759 / # export NFS_SERVER_IP='192.168.201.1'
11048 12:24:08.695870 export NFS_SERVER_IP='192.168.201.1'
11049 12:24:08.696693 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11050 12:24:08.697274 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
11051 12:24:08.697823 end: 2 depthcharge-action (duration 00:01:40) [common]
11052 12:24:08.698357 start: 3 lava-test-retry (timeout 00:07:34) [common]
11053 12:24:08.698921 start: 3.1 lava-test-shell (timeout 00:07:34) [common]
11054 12:24:08.699373 Using namespace: common
11056 12:24:08.800813 / # #
11057 12:24:08.801509 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11058 12:24:08.807700 #
11059 12:24:08.808622 Using /lava-11893144
11061 12:24:08.909979 / # export SHELL=/bin/bash
11062 12:24:08.916998 export SHELL=/bin/bash
11064 12:24:09.018911 / # . /lava-11893144/environment
11065 12:24:09.025529 . /lava-11893144/environment
11067 12:24:09.133263 / # /lava-11893144/bin/lava-test-runner /lava-11893144/0
11068 12:24:09.133882 Test shell timeout: 10s (minimum of the action and connection timeout)
11069 12:24:09.140019 /lava-11893144/bin/lava-test-runner /lava-11893144/0
11070 12:24:09.469878 + export TESTRUN_ID=0_timesync-off
11071 12:24:09.473390 + TESTRUN_ID=0_timesync-off
11072 12:24:09.476349 + cd /lava-11893144/0/tests/0_timesync-off
11073 12:24:09.479972 ++ cat uuid
11074 12:24:09.488866 + UUID=11893144_1.6.2.3.1
11075 12:24:09.489307 + set +x
11076 12:24:09.495675 <LAVA_SIGNAL_STARTRUN 0_timesync-off 11893144_1.6.2.3.1>
11077 12:24:09.496406 Received signal: <STARTRUN> 0_timesync-off 11893144_1.6.2.3.1
11078 12:24:09.496820 Starting test lava.0_timesync-off (11893144_1.6.2.3.1)
11079 12:24:09.497354 Skipping test definition patterns.
11080 12:24:09.498854 + systemctl stop systemd-timesyncd
11081 12:24:09.556286 + set +x
11082 12:24:09.559103 <LAVA_SIGNAL_ENDRUN 0_timesync-off 11893144_1.6.2.3.1>
11083 12:24:09.559812 Received signal: <ENDRUN> 0_timesync-off 11893144_1.6.2.3.1
11084 12:24:09.560269 Ending use of test pattern.
11085 12:24:09.560666 Ending test lava.0_timesync-off (11893144_1.6.2.3.1), duration 0.06
11087 12:24:09.666972 + export TESTRUN_ID=1_kselftest-tpm2
11088 12:24:09.667477 + TESTRUN_ID=1_kselftest-tpm2
11089 12:24:09.673379 + cd /lava-11893144/0/tests/1_kselftest-tpm2
11090 12:24:09.673808 ++ cat uuid
11091 12:24:09.681753 + UUID=11893144_1.6.2.3.5
11092 12:24:09.682179 + set +x
11093 12:24:09.688759 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 11893144_1.6.2.3.5>
11094 12:24:09.689443 Received signal: <STARTRUN> 1_kselftest-tpm2 11893144_1.6.2.3.5
11095 12:24:09.689806 Starting test lava.1_kselftest-tpm2 (11893144_1.6.2.3.5)
11096 12:24:09.690205 Skipping test definition patterns.
11097 12:24:09.691782 + cd ./automated/linux/kselftest/
11098 12:24:09.718098 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11099 12:24:09.774060 INFO: install_deps skipped
11100 12:24:09.906043 --2023-10-27 12:24:10-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11101 12:24:11.240443 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11102 12:24:11.371021 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
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11116 12:24:13.070808
11117 12:24:19.808339 skiplist:
11118 12:24:19.811906 ========================================
11119 12:24:19.815195 ========================================
11120 12:24:19.869204 tpm2:test_smoke.sh
11121 12:24:19.872343 tpm2:test_space.sh
11122 12:24:19.891885 ============== Tests to run ===============
11123 12:24:19.895045 tpm2:test_smoke.sh
11124 12:24:19.895492 tpm2:test_space.sh
11125 12:24:19.898555 ===========End Tests to run ===============
11126 12:24:19.903458 shardfile-tpm2 pass
11127 12:24:20.031399 <12>[ 38.526686] kselftest: Running tests in tpm2
11128 12:24:20.042903 TAP version 13
11129 12:24:20.059100 1..2
11130 12:24:20.100407 # selftests: tpm2: test_smoke.sh
11131 12:24:21.621949 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11132 12:24:21.625022 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11133 12:24:21.631530 # Exception ignored in: <function Client.__del__ at 0xffffbcc37d30>
11134 12:24:21.635033 # Traceback (most recent call last):
11135 12:24:21.645319 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11136 12:24:21.645898 # if self.tpm:
11137 12:24:21.652052 # AttributeError: 'Client' object has no attribute 'tpm'
11138 12:24:21.655682 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11139 12:24:21.661990 # Exception ignored in: <function Client.__del__ at 0xffffbcc37d30>
11140 12:24:21.665241 # Traceback (most recent call last):
11141 12:24:21.674859 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11142 12:24:21.678669 # if self.tpm:
11143 12:24:21.682034 # AttributeError: 'Client' object has no attribute 'tpm'
11144 12:24:21.688723 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11145 12:24:21.692175 # Exception ignored in: <function Client.__del__ at 0xffffbcc37d30>
11146 12:24:21.695311 # Traceback (most recent call last):
11147 12:24:21.705425 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11148 12:24:21.708260 # if self.tpm:
11149 12:24:21.711716 # AttributeError: 'Client' object has no attribute 'tpm'
11150 12:24:21.718596 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11151 12:24:21.724999 # Exception ignored in: <function Client.__del__ at 0xffffbcc37d30>
11152 12:24:21.728544 # Traceback (most recent call last):
11153 12:24:21.738652 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11154 12:24:21.739284 # if self.tpm:
11155 12:24:21.745108 # AttributeError: 'Client' object has no attribute 'tpm'
11156 12:24:21.748505 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11157 12:24:21.755546 # Exception ignored in: <function Client.__del__ at 0xffffbcc37d30>
11158 12:24:21.758746 # Traceback (most recent call last):
11159 12:24:21.768541 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11160 12:24:21.772447 # if self.tpm:
11161 12:24:21.775706 # AttributeError: 'Client' object has no attribute 'tpm'
11162 12:24:21.778563 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11163 12:24:21.785420 # Exception ignored in: <function Client.__del__ at 0xffffbcc37d30>
11164 12:24:21.789052 # Traceback (most recent call last):
11165 12:24:21.798802 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11166 12:24:21.801770 # if self.tpm:
11167 12:24:21.805349 # AttributeError: 'Client' object has no attribute 'tpm'
11168 12:24:21.812210 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11169 12:24:21.818898 # Exception ignored in: <function Client.__del__ at 0xffffbcc37d30>
11170 12:24:21.822200 # Traceback (most recent call last):
11171 12:24:21.832647 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11172 12:24:21.833207 # if self.tpm:
11173 12:24:21.839095 # AttributeError: 'Client' object has no attribute 'tpm'
11174 12:24:21.842806 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11175 12:24:21.849143 # Exception ignored in: <function Client.__del__ at 0xffffbcc37d30>
11176 12:24:21.852482 # Traceback (most recent call last):
11177 12:24:21.862554 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11178 12:24:21.866037 # if self.tpm:
11179 12:24:21.869102 # AttributeError: 'Client' object has no attribute 'tpm'
11180 12:24:21.869591 #
11181 12:24:21.875864 # ======================================================================
11182 12:24:21.882576 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11183 12:24:21.889343 # ----------------------------------------------------------------------
11184 12:24:21.892283 # Traceback (most recent call last):
11185 12:24:21.902635 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11186 12:24:21.906026 # self.root_key = self.client.create_root_key()
11187 12:24:21.916422 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11188 12:24:21.922783 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11189 12:24:21.932600 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11190 12:24:21.936341 # raise ProtocolError(cc, rc)
11191 12:24:21.939279 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11192 12:24:21.939702 #
11193 12:24:21.947552 # ======================================================================
11194 12:24:21.952314 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11195 12:24:21.959409 # ----------------------------------------------------------------------
11196 12:24:21.963161 # Traceback (most recent call last):
11197 12:24:21.973042 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11198 12:24:21.976120 # self.client = tpm2.Client()
11199 12:24:21.986226 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11200 12:24:21.989313 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11201 12:24:21.995917 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11202 12:24:21.996347 #
11203 12:24:22.003051 # ======================================================================
11204 12:24:22.006343 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11205 12:24:22.012791 # ----------------------------------------------------------------------
11206 12:24:22.016312 # Traceback (most recent call last):
11207 12:24:22.026094 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11208 12:24:22.029368 # self.client = tpm2.Client()
11209 12:24:22.040005 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11210 12:24:22.042679 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11211 12:24:22.049703 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11212 12:24:22.050249 #
11213 12:24:22.056102 # ======================================================================
11214 12:24:22.059358 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11215 12:24:22.066009 # ----------------------------------------------------------------------
11216 12:24:22.069444 # Traceback (most recent call last):
11217 12:24:22.079839 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11218 12:24:22.083085 # self.client = tpm2.Client()
11219 12:24:22.093320 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11220 12:24:22.099238 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11221 12:24:22.103234 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11222 12:24:22.103358 #
11223 12:24:22.109298 # ======================================================================
11224 12:24:22.116386 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11225 12:24:22.122865 # ----------------------------------------------------------------------
11226 12:24:22.126090 # Traceback (most recent call last):
11227 12:24:22.136530 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11228 12:24:22.139588 # self.client = tpm2.Client()
11229 12:24:22.149842 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11230 12:24:22.153102 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11231 12:24:22.160155 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11232 12:24:22.160745 #
11233 12:24:22.166788 # ======================================================================
11234 12:24:22.170112 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11235 12:24:22.176930 # ----------------------------------------------------------------------
11236 12:24:22.179840 # Traceback (most recent call last):
11237 12:24:22.190249 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11238 12:24:22.193636 # self.client = tpm2.Client()
11239 12:24:22.203471 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11240 12:24:22.206708 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11241 12:24:22.213674 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11242 12:24:22.214104 #
11243 12:24:22.220001 # ======================================================================
11244 12:24:22.223550 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11245 12:24:22.230503 # ----------------------------------------------------------------------
11246 12:24:22.233391 # Traceback (most recent call last):
11247 12:24:22.243537 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11248 12:24:22.247517 # self.client = tpm2.Client()
11249 12:24:22.256783 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11250 12:24:22.260511 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11251 12:24:22.266600 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11252 12:24:22.267083 #
11253 12:24:22.273393 # ======================================================================
11254 12:24:22.280259 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11255 12:24:22.283589 # ----------------------------------------------------------------------
11256 12:24:22.286795 # Traceback (most recent call last):
11257 12:24:22.296687 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11258 12:24:22.300445 # self.client = tpm2.Client()
11259 12:24:22.310786 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11260 12:24:22.317264 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11261 12:24:22.320695 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11262 12:24:22.321159 #
11263 12:24:22.328636 # ======================================================================
11264 12:24:22.332901 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11265 12:24:22.339595 # ----------------------------------------------------------------------
11266 12:24:22.347081 # Traceback (most recent call last):
11267 12:24:22.357897 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11268 12:24:22.358322 # self.client = tpm2.Client()
11269 12:24:22.364942 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11270 12:24:22.371685 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11271 12:24:22.375347 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11272 12:24:22.375894 #
11273 12:24:22.382122 # ----------------------------------------------------------------------
11274 12:24:22.385881 # Ran 9 tests in 0.040s
11275 12:24:22.386295 #
11276 12:24:22.389518 # FAILED (errors=9)
11277 12:24:22.392276 # test_async (tpm2_tests.AsyncTest) ... ok
11278 12:24:22.396109 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11279 12:24:22.396526 #
11280 12:24:22.402636 # ----------------------------------------------------------------------
11281 12:24:22.405884 # Ran 2 tests in 0.030s
11282 12:24:22.406299 #
11283 12:24:22.406624 # OK
11284 12:24:22.409020 ok 1 selftests: tpm2: test_smoke.sh
11285 12:24:22.412206 # selftests: tpm2: test_space.sh
11286 12:24:22.416301 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11287 12:24:22.422697 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11288 12:24:22.426514 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11289 12:24:22.432939 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11290 12:24:22.433464 #
11291 12:24:22.439363 # ======================================================================
11292 12:24:22.442178 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11293 12:24:22.449318 # ----------------------------------------------------------------------
11294 12:24:22.452207 # Traceback (most recent call last):
11295 12:24:22.462707 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11296 12:24:22.466394 # root1 = space1.create_root_key()
11297 12:24:22.476325 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11298 12:24:22.482594 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11299 12:24:22.492444 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11300 12:24:22.496101 # raise ProtocolError(cc, rc)
11301 12:24:22.502591 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11302 12:24:22.503040 #
11303 12:24:22.509315 # ======================================================================
11304 12:24:22.513093 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11305 12:24:22.519739 # ----------------------------------------------------------------------
11306 12:24:22.523388 # Traceback (most recent call last):
11307 12:24:22.533316 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11308 12:24:22.536665 # space1.create_root_key()
11309 12:24:22.546896 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11310 12:24:22.553285 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11311 12:24:22.562838 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11312 12:24:22.566203 # raise ProtocolError(cc, rc)
11313 12:24:22.573339 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11314 12:24:22.573757 #
11315 12:24:22.579757 # ======================================================================
11316 12:24:22.582955 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11317 12:24:22.590469 # ----------------------------------------------------------------------
11318 12:24:22.593590 # Traceback (most recent call last):
11319 12:24:22.603611 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11320 12:24:22.606967 # root1 = space1.create_root_key()
11321 12:24:22.616638 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11322 12:24:22.623105 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11323 12:24:22.633388 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11324 12:24:22.636743 # raise ProtocolError(cc, rc)
11325 12:24:22.643513 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11326 12:24:22.643934 #
11327 12:24:22.650299 # ======================================================================
11328 12:24:22.653535 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11329 12:24:22.660126 # ----------------------------------------------------------------------
11330 12:24:22.663447 # Traceback (most recent call last):
11331 12:24:22.673725 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11332 12:24:22.677466 # root1 = space1.create_root_key()
11333 12:24:22.687272 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11334 12:24:22.693791 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11335 12:24:22.703837 # File "/lava-11893144/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11336 12:24:22.706873 # raise ProtocolError(cc, rc)
11337 12:24:22.714029 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11338 12:24:22.714453 #
11339 12:24:22.720502 # ----------------------------------------------------------------------
11340 12:24:22.720918 # Ran 4 tests in 0.064s
11341 12:24:22.723417 #
11342 12:24:22.723831 # FAILED (errors=4)
11343 12:24:22.726817 not ok 2 selftests: tpm2: test_space.sh # exit=1
11344 12:24:22.730125 tpm2_test_smoke_sh pass
11345 12:24:22.733870 tpm2_test_space_sh fail
11346 12:24:22.736967 + ../../utils/send-to-lava.sh ./output/result.txt
11347 12:24:22.743391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11348 12:24:22.744174 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11350 12:24:22.785293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11351 12:24:22.785978 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11353 12:24:22.849629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11354 12:24:22.850310 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11356 12:24:22.853547 + set +x
11357 12:24:22.857216 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 11893144_1.6.2.3.5>
11358 12:24:22.857883 Received signal: <ENDRUN> 1_kselftest-tpm2 11893144_1.6.2.3.5
11359 12:24:22.858289 Ending use of test pattern.
11360 12:24:22.858604 Ending test lava.1_kselftest-tpm2 (11893144_1.6.2.3.5), duration 13.17
11362 12:24:22.860121 <LAVA_TEST_RUNNER EXIT>
11363 12:24:22.860727 ok: lava_test_shell seems to have completed
11364 12:24:22.861240 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11365 12:24:22.861649 end: 3.1 lava-test-shell (duration 00:00:14) [common]
11366 12:24:22.862051 end: 3 lava-test-retry (duration 00:00:14) [common]
11367 12:24:22.862466 start: 4 finalize (timeout 00:07:20) [common]
11368 12:24:22.862945 start: 4.1 power-off (timeout 00:00:30) [common]
11369 12:24:22.863687 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11370 12:24:22.983479 >> Command sent successfully.
11371 12:24:22.987367 Returned 0 in 0 seconds
11372 12:24:23.088358 end: 4.1 power-off (duration 00:00:00) [common]
11374 12:24:23.090137 start: 4.2 read-feedback (timeout 00:07:20) [common]
11375 12:24:23.091454 Listened to connection for namespace 'common' for up to 1s
11376 12:24:24.091023 Finalising connection for namespace 'common'
11377 12:24:24.091672 Disconnecting from shell: Finalise
11378 12:24:24.092055 / #
11379 12:24:24.193050 end: 4.2 read-feedback (duration 00:00:01) [common]
11380 12:24:24.193746 end: 4 finalize (duration 00:00:01) [common]
11381 12:24:24.194316 Cleaning after the job
11382 12:24:24.194856 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/ramdisk
11383 12:24:24.207084 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/kernel
11384 12:24:24.243621 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/dtb
11385 12:24:24.243971 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/nfsrootfs
11386 12:24:24.338045 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893144/tftp-deploy-1bt2atx6/modules
11387 12:24:24.345309 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893144
11388 12:24:24.977407 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893144
11389 12:24:24.977598 Job finished correctly