Boot log: mt8192-asurada-spherion-r0

    1 12:17:50.526793  lava-dispatcher, installed at version: 2023.08
    2 12:17:50.527026  start: 0 validate
    3 12:17:50.527165  Start time: 2023-10-27 12:17:50.527157+00:00 (UTC)
    4 12:17:50.527292  Using caching service: 'http://localhost/cache/?uri=%s'
    5 12:17:50.527427  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
    6 12:17:50.806372  Using caching service: 'http://localhost/cache/?uri=%s'
    7 12:17:50.806548  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 12:17:51.071933  Using caching service: 'http://localhost/cache/?uri=%s'
    9 12:17:51.072119  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 12:18:18.152179  Using caching service: 'http://localhost/cache/?uri=%s'
   11 12:18:18.152992  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 12:18:18.680913  Using caching service: 'http://localhost/cache/?uri=%s'
   13 12:18:18.681646  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   14 12:18:18.948659  validate duration: 28.42
   16 12:18:18.948919  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 12:18:18.949015  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 12:18:18.949099  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 12:18:18.949224  Not decompressing ramdisk as can be used compressed.
   20 12:18:18.949314  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
   21 12:18:18.949380  saving as /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/ramdisk/initrd.cpio.gz
   22 12:18:18.949444  total size: 4665398 (4 MB)
   23 12:18:23.354399  progress   0 % (0 MB)
   24 12:18:23.356167  progress   5 % (0 MB)
   25 12:18:23.357446  progress  10 % (0 MB)
   26 12:18:23.358711  progress  15 % (0 MB)
   27 12:18:23.359961  progress  20 % (0 MB)
   28 12:18:23.361327  progress  25 % (1 MB)
   29 12:18:23.362584  progress  30 % (1 MB)
   30 12:18:23.363878  progress  35 % (1 MB)
   31 12:18:23.365115  progress  40 % (1 MB)
   32 12:18:23.366502  progress  45 % (2 MB)
   33 12:18:23.367794  progress  50 % (2 MB)
   34 12:18:23.369021  progress  55 % (2 MB)
   35 12:18:23.370268  progress  60 % (2 MB)
   36 12:18:23.371495  progress  65 % (2 MB)
   37 12:18:23.372724  progress  70 % (3 MB)
   38 12:18:23.373960  progress  75 % (3 MB)
   39 12:18:23.375185  progress  80 % (3 MB)
   40 12:18:23.376608  progress  85 % (3 MB)
   41 12:18:23.377830  progress  90 % (4 MB)
   42 12:18:23.379054  progress  95 % (4 MB)
   43 12:18:23.380337  progress 100 % (4 MB)
   44 12:18:23.380506  4 MB downloaded in 4.43 s (1.00 MB/s)
   45 12:18:23.380655  end: 1.1.1 http-download (duration 00:00:04) [common]
   47 12:18:23.380890  end: 1.1 download-retry (duration 00:00:04) [common]
   48 12:18:23.380975  start: 1.2 download-retry (timeout 00:09:56) [common]
   49 12:18:23.381061  start: 1.2.1 http-download (timeout 00:09:56) [common]
   50 12:18:23.381196  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   51 12:18:23.381267  saving as /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/kernel/Image
   52 12:18:23.381326  total size: 49236480 (46 MB)
   53 12:18:23.381387  No compression specified
   54 12:18:23.382508  progress   0 % (0 MB)
   55 12:18:23.395454  progress   5 % (2 MB)
   56 12:18:23.408425  progress  10 % (4 MB)
   57 12:18:23.421256  progress  15 % (7 MB)
   58 12:18:23.434187  progress  20 % (9 MB)
   59 12:18:23.446852  progress  25 % (11 MB)
   60 12:18:23.459991  progress  30 % (14 MB)
   61 12:18:23.473011  progress  35 % (16 MB)
   62 12:18:23.486092  progress  40 % (18 MB)
   63 12:18:23.498922  progress  45 % (21 MB)
   64 12:18:23.511784  progress  50 % (23 MB)
   65 12:18:23.524912  progress  55 % (25 MB)
   66 12:18:23.537933  progress  60 % (28 MB)
   67 12:18:23.550781  progress  65 % (30 MB)
   68 12:18:23.563711  progress  70 % (32 MB)
   69 12:18:23.576857  progress  75 % (35 MB)
   70 12:18:23.589879  progress  80 % (37 MB)
   71 12:18:23.602686  progress  85 % (39 MB)
   72 12:18:23.615911  progress  90 % (42 MB)
   73 12:18:23.629704  progress  95 % (44 MB)
   74 12:18:23.643342  progress 100 % (46 MB)
   75 12:18:23.643609  46 MB downloaded in 0.26 s (179.03 MB/s)
   76 12:18:23.643827  end: 1.2.1 http-download (duration 00:00:00) [common]
   78 12:18:23.644142  end: 1.2 download-retry (duration 00:00:00) [common]
   79 12:18:23.644244  start: 1.3 download-retry (timeout 00:09:55) [common]
   80 12:18:23.644330  start: 1.3.1 http-download (timeout 00:09:55) [common]
   81 12:18:23.644501  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   82 12:18:23.644591  saving as /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/dtb/mt8192-asurada-spherion-r0.dtb
   83 12:18:23.644669  total size: 47278 (0 MB)
   84 12:18:23.644730  No compression specified
   85 12:18:23.646016  progress  69 % (0 MB)
   86 12:18:23.646310  progress 100 % (0 MB)
   87 12:18:23.646499  0 MB downloaded in 0.00 s (24.67 MB/s)
   88 12:18:23.646642  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 12:18:23.646910  end: 1.3 download-retry (duration 00:00:00) [common]
   91 12:18:23.647026  start: 1.4 download-retry (timeout 00:09:55) [common]
   92 12:18:23.647107  start: 1.4.1 http-download (timeout 00:09:55) [common]
   93 12:18:23.647258  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
   94 12:18:23.647325  saving as /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/nfsrootfs/full.rootfs.tar
   95 12:18:23.647412  total size: 89451516 (85 MB)
   96 12:18:23.647474  Using unxz to decompress xz
   97 12:18:23.653215  progress   0 % (0 MB)
   98 12:18:23.869320  progress   5 % (4 MB)
   99 12:18:24.090317  progress  10 % (8 MB)
  100 12:18:24.357891  progress  15 % (12 MB)
  101 12:18:24.565497  progress  20 % (17 MB)
  102 12:18:24.668849  progress  25 % (21 MB)
  103 12:18:24.920308  progress  30 % (25 MB)
  104 12:18:25.216923  progress  35 % (29 MB)
  105 12:18:25.493066  progress  40 % (34 MB)
  106 12:18:25.769235  progress  45 % (38 MB)
  107 12:18:26.019722  progress  50 % (42 MB)
  108 12:18:26.286791  progress  55 % (46 MB)
  109 12:18:26.541286  progress  60 % (51 MB)
  110 12:18:26.813179  progress  65 % (55 MB)
  111 12:18:27.110109  progress  70 % (59 MB)
  112 12:18:27.413938  progress  75 % (64 MB)
  113 12:18:27.712937  progress  80 % (68 MB)
  114 12:18:27.975697  progress  85 % (72 MB)
  115 12:18:28.205300  progress  90 % (76 MB)
  116 12:18:28.461911  progress  95 % (81 MB)
  117 12:18:28.723151  progress 100 % (85 MB)
  118 12:18:28.729326  85 MB downloaded in 5.08 s (16.79 MB/s)
  119 12:18:28.729646  end: 1.4.1 http-download (duration 00:00:05) [common]
  121 12:18:28.730028  end: 1.4 download-retry (duration 00:00:05) [common]
  122 12:18:28.730155  start: 1.5 download-retry (timeout 00:09:50) [common]
  123 12:18:28.730281  start: 1.5.1 http-download (timeout 00:09:50) [common]
  124 12:18:28.730488  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
  125 12:18:28.730592  saving as /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/modules/modules.tar
  126 12:18:28.730685  total size: 8625084 (8 MB)
  127 12:18:28.730780  Using unxz to decompress xz
  128 12:18:28.736047  progress   0 % (0 MB)
  129 12:18:28.758217  progress   5 % (0 MB)
  130 12:18:28.782256  progress  10 % (0 MB)
  131 12:18:28.808227  progress  15 % (1 MB)
  132 12:18:28.833229  progress  20 % (1 MB)
  133 12:18:28.858518  progress  25 % (2 MB)
  134 12:18:28.884452  progress  30 % (2 MB)
  135 12:18:28.911590  progress  35 % (2 MB)
  136 12:18:28.936147  progress  40 % (3 MB)
  137 12:18:28.959858  progress  45 % (3 MB)
  138 12:18:28.986442  progress  50 % (4 MB)
  139 12:18:29.011563  progress  55 % (4 MB)
  140 12:18:29.036439  progress  60 % (4 MB)
  141 12:18:29.060716  progress  65 % (5 MB)
  142 12:18:29.086104  progress  70 % (5 MB)
  143 12:18:29.110172  progress  75 % (6 MB)
  144 12:18:29.136441  progress  80 % (6 MB)
  145 12:18:29.165834  progress  85 % (7 MB)
  146 12:18:29.192844  progress  90 % (7 MB)
  147 12:18:29.218688  progress  95 % (7 MB)
  148 12:18:29.241824  progress 100 % (8 MB)
  149 12:18:29.246641  8 MB downloaded in 0.52 s (15.94 MB/s)
  150 12:18:29.246958  end: 1.5.1 http-download (duration 00:00:01) [common]
  152 12:18:29.247346  end: 1.5 download-retry (duration 00:00:01) [common]
  153 12:18:29.247472  start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
  154 12:18:29.247611  start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
  155 12:18:31.058472  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11893116/extract-nfsrootfs-fmw_h8hb
  156 12:18:31.058676  end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
  157 12:18:31.058782  start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
  158 12:18:31.058967  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz
  159 12:18:31.059102  makedir: /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin
  160 12:18:31.059241  makedir: /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/tests
  161 12:18:31.059345  makedir: /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/results
  162 12:18:31.059452  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-add-keys
  163 12:18:31.059601  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-add-sources
  164 12:18:31.059782  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-background-process-start
  165 12:18:31.059915  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-background-process-stop
  166 12:18:31.060044  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-common-functions
  167 12:18:31.060173  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-echo-ipv4
  168 12:18:31.060301  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-install-packages
  169 12:18:31.060428  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-installed-packages
  170 12:18:31.060556  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-os-build
  171 12:18:31.060730  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-probe-channel
  172 12:18:31.060863  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-probe-ip
  173 12:18:31.060991  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-target-ip
  174 12:18:31.061119  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-target-mac
  175 12:18:31.061248  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-target-storage
  176 12:18:31.061379  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-test-case
  177 12:18:31.061512  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-test-event
  178 12:18:31.061639  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-test-feedback
  179 12:18:31.061767  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-test-raise
  180 12:18:31.061894  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-test-reference
  181 12:18:31.062022  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-test-runner
  182 12:18:31.062149  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-test-set
  183 12:18:31.062276  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-test-shell
  184 12:18:31.062407  Updating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-install-packages (oe)
  185 12:18:31.062568  Updating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/bin/lava-installed-packages (oe)
  186 12:18:31.062754  Creating /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/environment
  187 12:18:31.062855  LAVA metadata
  188 12:18:31.062928  - LAVA_JOB_ID=11893116
  189 12:18:31.062993  - LAVA_DISPATCHER_IP=192.168.201.1
  190 12:18:31.063107  start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
  191 12:18:31.063175  skipped lava-vland-overlay
  192 12:18:31.063253  end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
  193 12:18:31.063333  start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
  194 12:18:31.063396  skipped lava-multinode-overlay
  195 12:18:31.063478  end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  196 12:18:31.063558  start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
  197 12:18:31.063645  Loading test definitions
  198 12:18:31.063771  start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
  199 12:18:31.063842  Using /lava-11893116 at stage 0
  200 12:18:31.064149  uuid=11893116_1.6.2.3.1 testdef=None
  201 12:18:31.064239  end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
  202 12:18:31.064323  start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
  203 12:18:31.064822  end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
  205 12:18:31.065047  start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
  206 12:18:31.065672  end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
  208 12:18:31.065965  start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
  209 12:18:31.066568  runner path: /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/0/tests/0_lc-compliance test_uuid 11893116_1.6.2.3.1
  210 12:18:31.066729  end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  212 12:18:31.066935  Creating lava-test-runner.conf files
  213 12:18:31.066999  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893116/lava-overlay-edsrwznz/lava-11893116/0 for stage 0
  214 12:18:31.067090  - 0_lc-compliance
  215 12:18:31.067188  end: 1.6.2.3 test-definition (duration 00:00:00) [common]
  216 12:18:31.067275  start: 1.6.2.4 compress-overlay (timeout 00:09:48) [common]
  217 12:18:31.073466  end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
  218 12:18:31.073609  start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:48) [common]
  219 12:18:31.073722  end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  220 12:18:31.073828  end: 1.6.2 lava-overlay (duration 00:00:00) [common]
  221 12:18:31.073981  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:48) [common]
  222 12:18:31.196657  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  223 12:18:31.197047  start: 1.6.4 extract-modules (timeout 00:09:48) [common]
  224 12:18:31.197161  extracting modules file /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893116/extract-nfsrootfs-fmw_h8hb
  225 12:18:31.427280  extracting modules file /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893116/extract-overlay-ramdisk-_mbodim3/ramdisk
  226 12:18:31.659967  end: 1.6.4 extract-modules (duration 00:00:00) [common]
  227 12:18:31.660144  start: 1.6.5 apply-overlay-tftp (timeout 00:09:47) [common]
  228 12:18:31.660258  [common] Applying overlay to NFS
  229 12:18:31.660342  [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893116/compress-overlay-mimv9btq/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893116/extract-nfsrootfs-fmw_h8hb
  230 12:18:31.666994  end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
  231 12:18:31.667157  start: 1.6.6 configure-preseed-file (timeout 00:09:47) [common]
  232 12:18:31.667278  end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
  233 12:18:31.667390  start: 1.6.7 compress-ramdisk (timeout 00:09:47) [common]
  234 12:18:31.667486  Building ramdisk /var/lib/lava/dispatcher/tmp/11893116/extract-overlay-ramdisk-_mbodim3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893116/extract-overlay-ramdisk-_mbodim3/ramdisk
  235 12:18:32.006869  >> 119370 blocks

  236 12:18:33.970233  rename /var/lib/lava/dispatcher/tmp/11893116/extract-overlay-ramdisk-_mbodim3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/ramdisk/ramdisk.cpio.gz
  237 12:18:33.970726  end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
  238 12:18:33.970905  start: 1.6.8 prepare-kernel (timeout 00:09:45) [common]
  239 12:18:33.971048  start: 1.6.8.1 prepare-fit (timeout 00:09:45) [common]
  240 12:18:33.971205  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/kernel/Image'
  241 12:18:47.006084  Returned 0 in 13 seconds
  242 12:18:47.106760  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/kernel/image.itb
  243 12:18:47.468377  output: FIT description: Kernel Image image with one or more FDT blobs
  244 12:18:47.468756  output: Created:         Fri Oct 27 13:18:47 2023
  245 12:18:47.468857  output:  Image 0 (kernel-1)
  246 12:18:47.468946  output:   Description:  
  247 12:18:47.469031  output:   Created:      Fri Oct 27 13:18:47 2023
  248 12:18:47.469113  output:   Type:         Kernel Image
  249 12:18:47.469197  output:   Compression:  lzma compressed
  250 12:18:47.469280  output:   Data Size:    11047994 Bytes = 10789.06 KiB = 10.54 MiB
  251 12:18:47.469381  output:   Architecture: AArch64
  252 12:18:47.469478  output:   OS:           Linux
  253 12:18:47.469578  output:   Load Address: 0x00000000
  254 12:18:47.469674  output:   Entry Point:  0x00000000
  255 12:18:47.469771  output:   Hash algo:    crc32
  256 12:18:47.469867  output:   Hash value:   d33b93ae
  257 12:18:47.469962  output:  Image 1 (fdt-1)
  258 12:18:47.470057  output:   Description:  mt8192-asurada-spherion-r0
  259 12:18:47.470149  output:   Created:      Fri Oct 27 13:18:47 2023
  260 12:18:47.470262  output:   Type:         Flat Device Tree
  261 12:18:47.470367  output:   Compression:  uncompressed
  262 12:18:47.470458  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  263 12:18:47.470550  output:   Architecture: AArch64
  264 12:18:47.470641  output:   Hash algo:    crc32
  265 12:18:47.470731  output:   Hash value:   cc4352de
  266 12:18:47.470823  output:  Image 2 (ramdisk-1)
  267 12:18:47.470913  output:   Description:  unavailable
  268 12:18:47.471003  output:   Created:      Fri Oct 27 13:18:47 2023
  269 12:18:47.471094  output:   Type:         RAMDisk Image
  270 12:18:47.471185  output:   Compression:  Unknown Compression
  271 12:18:47.471275  output:   Data Size:    17789041 Bytes = 17372.11 KiB = 16.96 MiB
  272 12:18:47.471366  output:   Architecture: AArch64
  273 12:18:47.471456  output:   OS:           Linux
  274 12:18:47.471547  output:   Load Address: unavailable
  275 12:18:47.471641  output:   Entry Point:  unavailable
  276 12:18:47.471772  output:   Hash algo:    crc32
  277 12:18:47.471862  output:   Hash value:   4f0c027a
  278 12:18:47.471953  output:  Default Configuration: 'conf-1'
  279 12:18:47.472044  output:  Configuration 0 (conf-1)
  280 12:18:47.472134  output:   Description:  mt8192-asurada-spherion-r0
  281 12:18:47.472225  output:   Kernel:       kernel-1
  282 12:18:47.472316  output:   Init Ramdisk: ramdisk-1
  283 12:18:47.472409  output:   FDT:          fdt-1
  284 12:18:47.472500  output:   Loadables:    kernel-1
  285 12:18:47.472590  output: 
  286 12:18:47.472849  end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
  287 12:18:47.472993  end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
  288 12:18:47.473144  end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
  289 12:18:47.473283  start: 1.7 lxc-create-udev-rule-action (timeout 00:09:31) [common]
  290 12:18:47.473406  No LXC device requested
  291 12:18:47.473527  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  292 12:18:47.473660  start: 1.8 deploy-device-env (timeout 00:09:31) [common]
  293 12:18:47.473776  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  294 12:18:47.473883  Checking files for TFTP limit of 4294967296 bytes.
  295 12:18:47.474566  end: 1 tftp-deploy (duration 00:00:29) [common]
  296 12:18:47.474705  start: 2 depthcharge-action (timeout 00:05:00) [common]
  297 12:18:47.474842  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  298 12:18:47.475022  substitutions:
  299 12:18:47.475120  - {DTB}: 11893116/tftp-deploy-xlfix1x7/dtb/mt8192-asurada-spherion-r0.dtb
  300 12:18:47.475226  - {INITRD}: 11893116/tftp-deploy-xlfix1x7/ramdisk/ramdisk.cpio.gz
  301 12:18:47.475325  - {KERNEL}: 11893116/tftp-deploy-xlfix1x7/kernel/Image
  302 12:18:47.475422  - {LAVA_MAC}: None
  303 12:18:47.475520  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11893116/extract-nfsrootfs-fmw_h8hb
  304 12:18:47.475616  - {NFS_SERVER_IP}: 192.168.201.1
  305 12:18:47.475759  - {PRESEED_CONFIG}: None
  306 12:18:47.475856  - {PRESEED_LOCAL}: None
  307 12:18:47.475955  - {RAMDISK}: 11893116/tftp-deploy-xlfix1x7/ramdisk/ramdisk.cpio.gz
  308 12:18:47.476050  - {ROOT_PART}: None
  309 12:18:47.476136  - {ROOT}: None
  310 12:18:47.476222  - {SERVER_IP}: 192.168.201.1
  311 12:18:47.476383  - {TEE}: None
  312 12:18:47.476506  Parsed boot commands:
  313 12:18:47.476595  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  314 12:18:47.476795  Parsed boot commands: tftpboot 192.168.201.1 11893116/tftp-deploy-xlfix1x7/kernel/image.itb 11893116/tftp-deploy-xlfix1x7/kernel/cmdline 
  315 12:18:47.476885  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  316 12:18:47.476971  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  317 12:18:47.477069  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  318 12:18:47.477155  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  319 12:18:47.477227  Not connected, no need to disconnect.
  320 12:18:47.477301  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  321 12:18:47.477384  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  322 12:18:47.477458  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
  323 12:18:47.481698  Setting prompt string to ['lava-test: # ']
  324 12:18:47.482095  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  325 12:18:47.482206  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  326 12:18:47.482303  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  327 12:18:47.482431  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  328 12:18:47.482673  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
  329 12:18:52.618538  >> Command sent successfully.

  330 12:18:52.621168  Returned 0 in 5 seconds
  331 12:18:52.721569  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  333 12:18:52.721936  end: 2.2.2 reset-device (duration 00:00:05) [common]
  334 12:18:52.722045  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  335 12:18:52.722132  Setting prompt string to 'Starting depthcharge on Spherion...'
  336 12:18:52.722198  Changing prompt to 'Starting depthcharge on Spherion...'
  337 12:18:52.722265  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  338 12:18:52.722539  [Enter `^Ec?' for help]

  339 12:18:52.894714  

  340 12:18:52.894879  

  341 12:18:52.894948  F0: 102B 0000

  342 12:18:52.895013  

  343 12:18:52.895077  F3: 1001 0000 [0200]

  344 12:18:52.898186  

  345 12:18:52.898272  F3: 1001 0000

  346 12:18:52.898340  

  347 12:18:52.898401  F7: 102D 0000

  348 12:18:52.898460  

  349 12:18:52.901589  F1: 0000 0000

  350 12:18:52.901737  

  351 12:18:52.901887  V0: 0000 0000 [0001]

  352 12:18:52.901958  

  353 12:18:52.904749  00: 0007 8000

  354 12:18:52.904838  

  355 12:18:52.904903  01: 0000 0000

  356 12:18:52.904965  

  357 12:18:52.908511  BP: 0C00 0209 [0000]

  358 12:18:52.908595  

  359 12:18:52.908661  G0: 1182 0000

  360 12:18:52.908724  

  361 12:18:52.911602  EC: 0000 0021 [4000]

  362 12:18:52.911731  

  363 12:18:52.911818  S7: 0000 0000 [0000]

  364 12:18:52.911920  

  365 12:18:52.915533  CC: 0000 0000 [0001]

  366 12:18:52.915662  

  367 12:18:52.915761  T0: 0000 0040 [010F]

  368 12:18:52.915862  

  369 12:18:52.915961  Jump to BL

  370 12:18:52.916059  

  371 12:18:52.941937  

  372 12:18:52.942097  

  373 12:18:52.942192  

  374 12:18:52.949187  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  375 12:18:52.952908  ARM64: Exception handlers installed.

  376 12:18:52.956809  ARM64: Testing exception

  377 12:18:52.959952  ARM64: Done test exception

  378 12:18:52.966368  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  379 12:18:52.976682  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  380 12:18:52.983592  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  381 12:18:52.993939  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  382 12:18:53.000653  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  383 12:18:53.006731  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  384 12:18:53.018537  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  385 12:18:53.025705  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  386 12:18:53.044891  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  387 12:18:53.047401  WDT: Last reset was cold boot

  388 12:18:53.051154  SPI1(PAD0) initialized at 2873684 Hz

  389 12:18:53.054695  SPI5(PAD0) initialized at 992727 Hz

  390 12:18:53.057576  VBOOT: Loading verstage.

  391 12:18:53.064830  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  392 12:18:53.069307  FMAP: Found "FLASH" version 1.1 at 0x20000.

  393 12:18:53.072478  FMAP: base = 0x0 size = 0x800000 #areas = 25

  394 12:18:53.075533  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  395 12:18:53.082664  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  396 12:18:53.088883  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  397 12:18:53.099608  read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps

  398 12:18:53.099752  

  399 12:18:53.099843  

  400 12:18:53.110442  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  401 12:18:53.113625  ARM64: Exception handlers installed.

  402 12:18:53.116734  ARM64: Testing exception

  403 12:18:53.116823  ARM64: Done test exception

  404 12:18:53.123263  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  405 12:18:53.126669  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  406 12:18:53.140934  Probing TPM: . done!

  407 12:18:53.141059  TPM ready after 0 ms

  408 12:18:53.147608  Connected to device vid:did:rid of 1ae0:0028:00

  409 12:18:53.154323  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  410 12:18:53.215570  Initialized TPM device CR50 revision 0

  411 12:18:53.225738  tlcl_send_startup: Startup return code is 0

  412 12:18:53.225865  TPM: setup succeeded

  413 12:18:53.237026  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  414 12:18:53.245769  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  415 12:18:53.259917  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  416 12:18:53.267404  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  417 12:18:53.271289  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  418 12:18:53.274538  in-header: 03 07 00 00 08 00 00 00 

  419 12:18:53.278392  in-data: aa e4 47 04 13 02 00 00 

  420 12:18:53.282141  Chrome EC: UHEPI supported

  421 12:18:53.288916  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  422 12:18:53.293100  in-header: 03 95 00 00 08 00 00 00 

  423 12:18:53.293224  in-data: 18 20 20 08 00 00 00 00 

  424 12:18:53.296794  Phase 1

  425 12:18:53.300343  FMAP: area GBB found @ 3f5000 (12032 bytes)

  426 12:18:53.304524  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  427 12:18:53.312110  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  428 12:18:53.312263  Recovery requested (1009000e)

  429 12:18:53.323555  TPM: Extending digest for VBOOT: boot mode into PCR 0

  430 12:18:53.328567  tlcl_extend: response is 0

  431 12:18:53.339393  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  432 12:18:53.343789  tlcl_extend: response is 0

  433 12:18:53.350760  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  434 12:18:53.369780  read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps

  435 12:18:53.376413  BS: bootblock times (exec / console): total (unknown) / 148 ms

  436 12:18:53.376557  

  437 12:18:53.376625  

  438 12:18:53.386474  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  439 12:18:53.390212  ARM64: Exception handlers installed.

  440 12:18:53.393288  ARM64: Testing exception

  441 12:18:53.393373  ARM64: Done test exception

  442 12:18:53.415430  pmic_efuse_setting: Set efuses in 11 msecs

  443 12:18:53.419055  pmwrap_interface_init: Select PMIF_VLD_RDY

  444 12:18:53.425423  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  445 12:18:53.428907  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  446 12:18:53.435979  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  447 12:18:53.439855  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  448 12:18:53.443607  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  449 12:18:53.447510  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  450 12:18:53.454616  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  451 12:18:53.458403  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  452 12:18:53.462205  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  453 12:18:53.469039  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  454 12:18:53.472865  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  455 12:18:53.476788  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  456 12:18:53.479619  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  457 12:18:53.487444  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  458 12:18:53.495024  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  459 12:18:53.498937  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  460 12:18:53.505954  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  461 12:18:53.509833  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  462 12:18:53.517669  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  463 12:18:53.520857  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  464 12:18:53.528730  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  465 12:18:53.532107  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  466 12:18:53.539868  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  467 12:18:53.543289  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  468 12:18:53.550654  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  469 12:18:53.554284  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  470 12:18:53.558011  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  471 12:18:53.565660  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  472 12:18:53.569439  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  473 12:18:53.573098  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  474 12:18:53.580294  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  475 12:18:53.584238  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  476 12:18:53.587993  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  477 12:18:53.595610  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  478 12:18:53.598820  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  479 12:18:53.606300  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  480 12:18:53.610216  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  481 12:18:53.613973  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  482 12:18:53.617778  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  483 12:18:53.621498  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  484 12:18:53.628892  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  485 12:18:53.632612  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  486 12:18:53.636427  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  487 12:18:53.640266  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  488 12:18:53.643977  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  489 12:18:53.650924  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  490 12:18:53.654827  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  491 12:18:53.658330  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  492 12:18:53.662281  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  493 12:18:53.665887  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  494 12:18:53.669818  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  495 12:18:53.677164  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  496 12:18:53.688530  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  497 12:18:53.691933  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  498 12:18:53.699682  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  499 12:18:53.706913  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  500 12:18:53.714534  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  501 12:18:53.718284  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  502 12:18:53.721348  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  503 12:18:53.729174  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde71, sec=0x0

  504 12:18:53.732404  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  505 12:18:53.737472  [RTC]rtc_osc_init,62: osc32con val = 0xde71

  506 12:18:53.744374  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  507 12:18:53.753253  [RTC]rtc_get_frequency_meter,154: input=15, output=759

  508 12:18:53.762894  [RTC]rtc_get_frequency_meter,154: input=23, output=942

  509 12:18:53.772322  [RTC]rtc_get_frequency_meter,154: input=19, output=851

  510 12:18:53.781483  [RTC]rtc_get_frequency_meter,154: input=17, output=805

  511 12:18:53.790982  [RTC]rtc_get_frequency_meter,154: input=16, output=780

  512 12:18:53.800883  [RTC]rtc_get_frequency_meter,154: input=16, output=782

  513 12:18:53.810772  [RTC]rtc_get_frequency_meter,154: input=17, output=805

  514 12:18:53.814025  [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17

  515 12:18:53.818011  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70

  516 12:18:53.825391  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  517 12:18:53.828556  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  518 12:18:53.832326  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  519 12:18:53.835912  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  520 12:18:53.840370  ADC[4]: Raw value=905834 ID=7

  521 12:18:53.840492  ADC[3]: Raw value=213810 ID=1

  522 12:18:53.843549  RAM Code: 0x71

  523 12:18:53.847485  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  524 12:18:53.851251  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  525 12:18:53.861991  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  526 12:18:53.866242  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  527 12:18:53.869245  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  528 12:18:53.873726  in-header: 03 07 00 00 08 00 00 00 

  529 12:18:53.877049  in-data: aa e4 47 04 13 02 00 00 

  530 12:18:53.880838  Chrome EC: UHEPI supported

  531 12:18:53.888364  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  532 12:18:53.891966  in-header: 03 95 00 00 08 00 00 00 

  533 12:18:53.892054  in-data: 18 20 20 08 00 00 00 00 

  534 12:18:53.895992  MRC: failed to locate region type 0.

  535 12:18:53.903517  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  536 12:18:53.906914  DRAM-K: Running full calibration

  537 12:18:53.910790  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  538 12:18:53.914605  header.status = 0x0

  539 12:18:53.917917  header.version = 0x6 (expected: 0x6)

  540 12:18:53.921542  header.size = 0xd00 (expected: 0xd00)

  541 12:18:53.921628  header.flags = 0x0

  542 12:18:53.928421  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  543 12:18:53.947221  read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps

  544 12:18:53.954234  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  545 12:18:53.957985  dram_init: ddr_geometry: 2

  546 12:18:53.958077  [EMI] MDL number = 2

  547 12:18:53.961887  [EMI] Get MDL freq = 0

  548 12:18:53.961973  dram_init: ddr_type: 0

  549 12:18:53.965678  is_discrete_lpddr4: 1

  550 12:18:53.970080  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  551 12:18:53.970168  

  552 12:18:53.970235  

  553 12:18:53.970298  [Bian_co] ETT version 0.0.0.1

  554 12:18:53.973539   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  555 12:18:53.973663  

  556 12:18:53.978024  dramc_set_vcore_voltage set vcore to 650000

  557 12:18:53.981858  Read voltage for 800, 4

  558 12:18:53.981944  Vio18 = 0

  559 12:18:53.985123  Vcore = 650000

  560 12:18:53.985274  Vdram = 0

  561 12:18:53.985340  Vddq = 0

  562 12:18:53.985402  Vmddr = 0

  563 12:18:53.989001  dram_init: config_dvfs: 1

  564 12:18:53.992810  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  565 12:18:54.000561  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  566 12:18:54.004363  [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9

  567 12:18:54.008053  freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9

  568 12:18:54.011552  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  569 12:18:54.015516  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  570 12:18:54.015632  MEM_TYPE=3, freq_sel=18

  571 12:18:54.019407  sv_algorithm_assistance_LP4_1600 

  572 12:18:54.022391  ============ PULL DRAM RESETB DOWN ============

  573 12:18:54.029466  ========== PULL DRAM RESETB DOWN end =========

  574 12:18:54.032322  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  575 12:18:54.035706  =================================== 

  576 12:18:54.039815  LPDDR4 DRAM CONFIGURATION

  577 12:18:54.042397  =================================== 

  578 12:18:54.042487  EX_ROW_EN[0]    = 0x0

  579 12:18:54.046658  EX_ROW_EN[1]    = 0x0

  580 12:18:54.046746  LP4Y_EN      = 0x0

  581 12:18:54.049989  WORK_FSP     = 0x0

  582 12:18:54.050074  WL           = 0x2

  583 12:18:54.054016  RL           = 0x2

  584 12:18:54.054132  BL           = 0x2

  585 12:18:54.057702  RPST         = 0x0

  586 12:18:54.057807  RD_PRE       = 0x0

  587 12:18:54.061519  WR_PRE       = 0x1

  588 12:18:54.061607  WR_PST       = 0x0

  589 12:18:54.061675  DBI_WR       = 0x0

  590 12:18:54.064648  DBI_RD       = 0x0

  591 12:18:54.067826  OTF          = 0x1

  592 12:18:54.071014  =================================== 

  593 12:18:54.071100  =================================== 

  594 12:18:54.074826  ANA top config

  595 12:18:54.077815  =================================== 

  596 12:18:54.081462  DLL_ASYNC_EN            =  0

  597 12:18:54.081547  ALL_SLAVE_EN            =  1

  598 12:18:54.084620  NEW_RANK_MODE           =  1

  599 12:18:54.087819  DLL_IDLE_MODE           =  1

  600 12:18:54.091014  LP45_APHY_COMB_EN       =  1

  601 12:18:54.094636  TX_ODT_DIS              =  1

  602 12:18:54.094724  NEW_8X_MODE             =  1

  603 12:18:54.098401  =================================== 

  604 12:18:54.102479  =================================== 

  605 12:18:54.105431  data_rate                  = 1600

  606 12:18:54.108565  CKR                        = 1

  607 12:18:54.111796  DQ_P2S_RATIO               = 8

  608 12:18:54.115566  =================================== 

  609 12:18:54.115716  CA_P2S_RATIO               = 8

  610 12:18:54.118614  DQ_CA_OPEN                 = 0

  611 12:18:54.122312  DQ_SEMI_OPEN               = 0

  612 12:18:54.125361  CA_SEMI_OPEN               = 0

  613 12:18:54.128797  CA_FULL_RATE               = 0

  614 12:18:54.132256  DQ_CKDIV4_EN               = 1

  615 12:18:54.132346  CA_CKDIV4_EN               = 1

  616 12:18:54.135270  CA_PREDIV_EN               = 0

  617 12:18:54.139015  PH8_DLY                    = 0

  618 12:18:54.142077  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  619 12:18:54.145193  DQ_AAMCK_DIV               = 4

  620 12:18:54.145280  CA_AAMCK_DIV               = 4

  621 12:18:54.148926  CA_ADMCK_DIV               = 4

  622 12:18:54.152029  DQ_TRACK_CA_EN             = 0

  623 12:18:54.155777  CA_PICK                    = 800

  624 12:18:54.158843  CA_MCKIO                   = 800

  625 12:18:54.162451  MCKIO_SEMI                 = 0

  626 12:18:54.166309  PLL_FREQ                   = 3068

  627 12:18:54.166410  DQ_UI_PI_RATIO             = 32

  628 12:18:54.169865  CA_UI_PI_RATIO             = 0

  629 12:18:54.173709  =================================== 

  630 12:18:54.177972  =================================== 

  631 12:18:54.178069  memory_type:LPDDR4         

  632 12:18:54.181310  GP_NUM     : 10       

  633 12:18:54.181398  SRAM_EN    : 1       

  634 12:18:54.185121  MD32_EN    : 0       

  635 12:18:54.188935  =================================== 

  636 12:18:54.189050  [ANA_INIT] >>>>>>>>>>>>>> 

  637 12:18:54.192433  <<<<<< [CONFIGURE PHASE]: ANA_TX

  638 12:18:54.196269  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  639 12:18:54.200116  =================================== 

  640 12:18:54.203164  data_rate = 1600,PCW = 0X7600

  641 12:18:54.206954  =================================== 

  642 12:18:54.210290  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  643 12:18:54.217041  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  644 12:18:54.220253  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  645 12:18:54.226893  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  646 12:18:54.230018  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  647 12:18:54.233427  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  648 12:18:54.233519  [ANA_INIT] flow start 

  649 12:18:54.236483  [ANA_INIT] PLL >>>>>>>> 

  650 12:18:54.239886  [ANA_INIT] PLL <<<<<<<< 

  651 12:18:54.239976  [ANA_INIT] MIDPI >>>>>>>> 

  652 12:18:54.243530  [ANA_INIT] MIDPI <<<<<<<< 

  653 12:18:54.246707  [ANA_INIT] DLL >>>>>>>> 

  654 12:18:54.246795  [ANA_INIT] flow end 

  655 12:18:54.250247  ============ LP4 DIFF to SE enter ============

  656 12:18:54.256899  ============ LP4 DIFF to SE exit  ============

  657 12:18:54.256997  [ANA_INIT] <<<<<<<<<<<<< 

  658 12:18:54.260068  [Flow] Enable top DCM control >>>>> 

  659 12:18:54.263902  [Flow] Enable top DCM control <<<<< 

  660 12:18:54.267047  Enable DLL master slave shuffle 

  661 12:18:54.273980  ============================================================== 

  662 12:18:54.274075  Gating Mode config

  663 12:18:54.280460  ============================================================== 

  664 12:18:54.283401  Config description: 

  665 12:18:54.293592  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  666 12:18:54.300269  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  667 12:18:54.303487  SELPH_MODE            0: By rank         1: By Phase 

  668 12:18:54.310383  ============================================================== 

  669 12:18:54.313481  GAT_TRACK_EN                 =  1

  670 12:18:54.313570  RX_GATING_MODE               =  2

  671 12:18:54.316664  RX_GATING_TRACK_MODE         =  2

  672 12:18:54.319924  SELPH_MODE                   =  1

  673 12:18:54.323773  PICG_EARLY_EN                =  1

  674 12:18:54.327023  VALID_LAT_VALUE              =  1

  675 12:18:54.333237  ============================================================== 

  676 12:18:54.336972  Enter into Gating configuration >>>> 

  677 12:18:54.340048  Exit from Gating configuration <<<< 

  678 12:18:54.343717  Enter into  DVFS_PRE_config >>>>> 

  679 12:18:54.353497  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  680 12:18:54.357353  Exit from  DVFS_PRE_config <<<<< 

  681 12:18:54.360327  Enter into PICG configuration >>>> 

  682 12:18:54.364044  Exit from PICG configuration <<<< 

  683 12:18:54.367100  [RX_INPUT] configuration >>>>> 

  684 12:18:54.367192  [RX_INPUT] configuration <<<<< 

  685 12:18:54.374057  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  686 12:18:54.380349  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  687 12:18:54.383948  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  688 12:18:54.390223  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  689 12:18:54.397327  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  690 12:18:54.403714  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  691 12:18:54.407421  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  692 12:18:54.410453  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  693 12:18:54.417329  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  694 12:18:54.420728  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  695 12:18:54.423791  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  696 12:18:54.427214  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  697 12:18:54.430255  =================================== 

  698 12:18:54.433960  LPDDR4 DRAM CONFIGURATION

  699 12:18:54.437246  =================================== 

  700 12:18:54.440250  EX_ROW_EN[0]    = 0x0

  701 12:18:54.440347  EX_ROW_EN[1]    = 0x0

  702 12:18:54.443799  LP4Y_EN      = 0x0

  703 12:18:54.443893  WORK_FSP     = 0x0

  704 12:18:54.446886  WL           = 0x2

  705 12:18:54.446972  RL           = 0x2

  706 12:18:54.450633  BL           = 0x2

  707 12:18:54.450723  RPST         = 0x0

  708 12:18:54.453649  RD_PRE       = 0x0

  709 12:18:54.453737  WR_PRE       = 0x1

  710 12:18:54.457044  WR_PST       = 0x0

  711 12:18:54.457134  DBI_WR       = 0x0

  712 12:18:54.460701  DBI_RD       = 0x0

  713 12:18:54.463707  OTF          = 0x1

  714 12:18:54.463800  =================================== 

  715 12:18:54.470819  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  716 12:18:54.474109  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  717 12:18:54.477138  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  718 12:18:54.480391  =================================== 

  719 12:18:54.484125  LPDDR4 DRAM CONFIGURATION

  720 12:18:54.487180  =================================== 

  721 12:18:54.490847  EX_ROW_EN[0]    = 0x10

  722 12:18:54.490944  EX_ROW_EN[1]    = 0x0

  723 12:18:54.493960  LP4Y_EN      = 0x0

  724 12:18:54.494048  WORK_FSP     = 0x0

  725 12:18:54.497201  WL           = 0x2

  726 12:18:54.497289  RL           = 0x2

  727 12:18:54.500514  BL           = 0x2

  728 12:18:54.500603  RPST         = 0x0

  729 12:18:54.504033  RD_PRE       = 0x0

  730 12:18:54.504122  WR_PRE       = 0x1

  731 12:18:54.507107  WR_PST       = 0x0

  732 12:18:54.507193  DBI_WR       = 0x0

  733 12:18:54.511004  DBI_RD       = 0x0

  734 12:18:54.511091  OTF          = 0x1

  735 12:18:54.514301  =================================== 

  736 12:18:54.520577  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  737 12:18:54.524778  nWR fixed to 40

  738 12:18:54.528331  [ModeRegInit_LP4] CH0 RK0

  739 12:18:54.528424  [ModeRegInit_LP4] CH0 RK1

  740 12:18:54.531783  [ModeRegInit_LP4] CH1 RK0

  741 12:18:54.535207  [ModeRegInit_LP4] CH1 RK1

  742 12:18:54.535298  match AC timing 13

  743 12:18:54.541456  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  744 12:18:54.545205  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  745 12:18:54.548437  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  746 12:18:54.554976  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  747 12:18:54.558088  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  748 12:18:54.558191  [EMI DOE] emi_dcm 0

  749 12:18:54.565245  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  750 12:18:54.565367  ==

  751 12:18:54.568390  Dram Type= 6, Freq= 0, CH_0, rank 0

  752 12:18:54.571986  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  753 12:18:54.572081  ==

  754 12:18:54.578719  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  755 12:18:54.584896  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  756 12:18:54.592852  [CA 0] Center 36 (6~67) winsize 62

  757 12:18:54.595964  [CA 1] Center 36 (6~67) winsize 62

  758 12:18:54.599192  [CA 2] Center 34 (4~65) winsize 62

  759 12:18:54.602831  [CA 3] Center 33 (3~64) winsize 62

  760 12:18:54.605889  [CA 4] Center 33 (3~63) winsize 61

  761 12:18:54.609277  [CA 5] Center 32 (3~62) winsize 60

  762 12:18:54.609389  

  763 12:18:54.612249  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  764 12:18:54.612359  

  765 12:18:54.616066  [CATrainingPosCal] consider 1 rank data

  766 12:18:54.619113  u2DelayCellTimex100 = 270/100 ps

  767 12:18:54.622931  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  768 12:18:54.626078  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  769 12:18:54.632425  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  770 12:18:54.635919  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  771 12:18:54.638934  CA4 delay=33 (3~63),Diff = 1 PI (7 cell)

  772 12:18:54.642632  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

  773 12:18:54.642739  

  774 12:18:54.645854  CA PerBit enable=1, Macro0, CA PI delay=32

  775 12:18:54.645943  

  776 12:18:54.649120  [CBTSetCACLKResult] CA Dly = 32

  777 12:18:54.649212  CS Dly: 5 (0~36)

  778 12:18:54.649281  ==

  779 12:18:54.652900  Dram Type= 6, Freq= 0, CH_0, rank 1

  780 12:18:54.659529  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  781 12:18:54.659679  ==

  782 12:18:54.662393  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  783 12:18:54.669129  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  784 12:18:54.678947  [CA 0] Center 36 (6~67) winsize 62

  785 12:18:54.682389  [CA 1] Center 36 (6~67) winsize 62

  786 12:18:54.685458  [CA 2] Center 34 (4~65) winsize 62

  787 12:18:54.688730  [CA 3] Center 34 (4~65) winsize 62

  788 12:18:54.692134  [CA 4] Center 32 (2~63) winsize 62

  789 12:18:54.695587  [CA 5] Center 32 (2~63) winsize 62

  790 12:18:54.695705  

  791 12:18:54.698740  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  792 12:18:54.698836  

  793 12:18:54.701961  [CATrainingPosCal] consider 2 rank data

  794 12:18:54.705091  u2DelayCellTimex100 = 270/100 ps

  795 12:18:54.708920  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  796 12:18:54.712245  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  797 12:18:54.719069  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  798 12:18:54.722265  CA3 delay=34 (4~64),Diff = 2 PI (14 cell)

  799 12:18:54.725504  CA4 delay=33 (3~63),Diff = 1 PI (7 cell)

  800 12:18:54.728618  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

  801 12:18:54.728713  

  802 12:18:54.732361  CA PerBit enable=1, Macro0, CA PI delay=32

  803 12:18:54.732453  

  804 12:18:54.735570  [CBTSetCACLKResult] CA Dly = 32

  805 12:18:54.735718  CS Dly: 5 (0~37)

  806 12:18:54.735788  

  807 12:18:54.738732  ----->DramcWriteLeveling(PI) begin...

  808 12:18:54.742207  ==

  809 12:18:54.742317  Dram Type= 6, Freq= 0, CH_0, rank 0

  810 12:18:54.749893  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  811 12:18:54.750019  ==

  812 12:18:54.750103  Write leveling (Byte 0): 34 => 34

  813 12:18:54.753704  Write leveling (Byte 1): 31 => 31

  814 12:18:54.757462  DramcWriteLeveling(PI) end<-----

  815 12:18:54.757577  

  816 12:18:54.757661  ==

  817 12:18:54.760614  Dram Type= 6, Freq= 0, CH_0, rank 0

  818 12:18:54.764003  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  819 12:18:54.764093  ==

  820 12:18:54.767133  [Gating] SW mode calibration

  821 12:18:54.775079  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  822 12:18:54.778568  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  823 12:18:54.785281   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  824 12:18:54.788434   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  825 12:18:54.791729   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)

  826 12:18:54.798420   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  827 12:18:54.802104   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  828 12:18:54.805497   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  829 12:18:54.811773   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  830 12:18:54.815082   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  831 12:18:54.818382   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  832 12:18:54.825263   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  833 12:18:54.828761   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  834 12:18:54.831913   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  835 12:18:54.838980   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  836 12:18:54.842171   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  837 12:18:54.845316   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  838 12:18:54.851839   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  839 12:18:54.855521   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  840 12:18:54.858689   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  841 12:18:54.865574   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

  842 12:18:54.868685   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  843 12:18:54.871908   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  844 12:18:54.875156   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  845 12:18:54.881945   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  846 12:18:54.885200   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  847 12:18:54.889012   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  848 12:18:54.895208   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  849 12:18:54.898971   0  9  8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)

  850 12:18:54.901979   0  9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

  851 12:18:54.908504   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  852 12:18:54.912147   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  853 12:18:54.915407   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  854 12:18:54.922380   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  855 12:18:54.925639   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  856 12:18:54.929025   0 10  4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

  857 12:18:54.935572   0 10  8 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)

  858 12:18:54.939206   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  859 12:18:54.942151   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  860 12:18:54.945626   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  861 12:18:54.952207   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  862 12:18:54.955276   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  863 12:18:54.958877   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  864 12:18:54.965719   0 11  4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

  865 12:18:54.968888   0 11  8 | B1->B0 | 2929 4040 | 1 1 | (0 0) (0 0)

  866 12:18:54.972597   0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)

  867 12:18:54.978952   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  868 12:18:54.982030   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  869 12:18:54.985751   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  870 12:18:54.992649   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  871 12:18:54.995765   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  872 12:18:54.998863   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  873 12:18:55.005518   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  874 12:18:55.008687   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  875 12:18:55.012352   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  876 12:18:55.018542   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  877 12:18:55.022313   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  878 12:18:55.025548   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  879 12:18:55.032019   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  880 12:18:55.035583   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  881 12:18:55.038678   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  882 12:18:55.042185   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  883 12:18:55.048724   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  884 12:18:55.052211   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  885 12:18:55.055543   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  886 12:18:55.061991   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  887 12:18:55.065754   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  888 12:18:55.068991   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  889 12:18:55.075553   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

  890 12:18:55.078769   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  891 12:18:55.082616  Total UI for P1: 0, mck2ui 16

  892 12:18:55.085717  best dqsien dly found for B0: ( 0, 14,  6)

  893 12:18:55.088937  Total UI for P1: 0, mck2ui 16

  894 12:18:55.092645  best dqsien dly found for B1: ( 0, 14,  8)

  895 12:18:55.095781  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

  896 12:18:55.099616  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

  897 12:18:55.099728  

  898 12:18:55.103280  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

  899 12:18:55.106279  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

  900 12:18:55.109511  [Gating] SW calibration Done

  901 12:18:55.109601  ==

  902 12:18:55.113331  Dram Type= 6, Freq= 0, CH_0, rank 0

  903 12:18:55.116439  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  904 12:18:55.116537  ==

  905 12:18:55.119516  RX Vref Scan: 0

  906 12:18:55.119632  

  907 12:18:55.119744  RX Vref 0 -> 0, step: 1

  908 12:18:55.119810  

  909 12:18:55.122990  RX Delay -130 -> 252, step: 16

  910 12:18:55.126148  iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224

  911 12:18:55.133114  iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224

  912 12:18:55.136269  iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240

  913 12:18:55.139878  iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240

  914 12:18:55.143406  iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224

  915 12:18:55.146477  iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224

  916 12:18:55.153359  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

  917 12:18:55.156459  iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224

  918 12:18:55.159614  iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224

  919 12:18:55.163306  iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240

  920 12:18:55.166798  iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224

  921 12:18:55.173505  iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224

  922 12:18:55.176670  iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224

  923 12:18:55.179790  iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224

  924 12:18:55.183309  iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224

  925 12:18:55.186774  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

  926 12:18:55.186860  ==

  927 12:18:55.190043  Dram Type= 6, Freq= 0, CH_0, rank 0

  928 12:18:55.196887  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  929 12:18:55.196978  ==

  930 12:18:55.197046  DQS Delay:

  931 12:18:55.200392  DQS0 = 0, DQS1 = 0

  932 12:18:55.200479  DQM Delay:

  933 12:18:55.200547  DQM0 = 89, DQM1 = 83

  934 12:18:55.203503  DQ Delay:

  935 12:18:55.207251  DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85

  936 12:18:55.210056  DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93

  937 12:18:55.213255  DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77

  938 12:18:55.217080  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85

  939 12:18:55.217170  

  940 12:18:55.217236  

  941 12:18:55.217297  ==

  942 12:18:55.220320  Dram Type= 6, Freq= 0, CH_0, rank 0

  943 12:18:55.223380  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  944 12:18:55.223466  ==

  945 12:18:55.223533  

  946 12:18:55.223594  

  947 12:18:55.227018  	TX Vref Scan disable

  948 12:18:55.227121   == TX Byte 0 ==

  949 12:18:55.233607  Update DQ  dly =585 (2 ,1, 41)  DQ  OEN =(1 ,6)

  950 12:18:55.236727  Update DQM dly =585 (2 ,1, 41)  DQM OEN =(1 ,6)

  951 12:18:55.236834   == TX Byte 1 ==

  952 12:18:55.243600  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  953 12:18:55.246656  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  954 12:18:55.246748  ==

  955 12:18:55.250128  Dram Type= 6, Freq= 0, CH_0, rank 0

  956 12:18:55.253271  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  957 12:18:55.253359  ==

  958 12:18:55.268032  TX Vref=22, minBit 8, minWin=27, winSum=446

  959 12:18:55.271057  TX Vref=24, minBit 8, minWin=27, winSum=449

  960 12:18:55.274522  TX Vref=26, minBit 0, minWin=28, winSum=453

  961 12:18:55.277653  TX Vref=28, minBit 8, minWin=28, winSum=458

  962 12:18:55.281012  TX Vref=30, minBit 2, minWin=28, winSum=456

  963 12:18:55.284242  TX Vref=32, minBit 4, minWin=28, winSum=453

  964 12:18:55.291278  [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28

  965 12:18:55.291395  

  966 12:18:55.294538  Final TX Range 1 Vref 28

  967 12:18:55.294641  

  968 12:18:55.294739  ==

  969 12:18:55.297489  Dram Type= 6, Freq= 0, CH_0, rank 0

  970 12:18:55.301106  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  971 12:18:55.301196  ==

  972 12:18:55.301263  

  973 12:18:55.301325  

  974 12:18:55.304244  	TX Vref Scan disable

  975 12:18:55.307606   == TX Byte 0 ==

  976 12:18:55.311012  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

  977 12:18:55.314404  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

  978 12:18:55.317754   == TX Byte 1 ==

  979 12:18:55.321463  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  980 12:18:55.324669  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  981 12:18:55.324763  

  982 12:18:55.327772  [DATLAT]

  983 12:18:55.327880  Freq=800, CH0 RK0

  984 12:18:55.327970  

  985 12:18:55.330986  DATLAT Default: 0xa

  986 12:18:55.331071  0, 0xFFFF, sum = 0

  987 12:18:55.334625  1, 0xFFFF, sum = 0

  988 12:18:55.334717  2, 0xFFFF, sum = 0

  989 12:18:55.337598  3, 0xFFFF, sum = 0

  990 12:18:55.337699  4, 0xFFFF, sum = 0

  991 12:18:55.341473  5, 0xFFFF, sum = 0

  992 12:18:55.341562  6, 0xFFFF, sum = 0

  993 12:18:55.344549  7, 0xFFFF, sum = 0

  994 12:18:55.344638  8, 0xFFFF, sum = 0

  995 12:18:55.347673  9, 0x0, sum = 1

  996 12:18:55.347775  10, 0x0, sum = 2

  997 12:18:55.350953  11, 0x0, sum = 3

  998 12:18:55.351038  12, 0x0, sum = 4

  999 12:18:55.354624  best_step = 10

 1000 12:18:55.354708  

 1001 12:18:55.354774  ==

 1002 12:18:55.358105  Dram Type= 6, Freq= 0, CH_0, rank 0

 1003 12:18:55.361251  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1004 12:18:55.361339  ==

 1005 12:18:55.364904  RX Vref Scan: 1

 1006 12:18:55.364989  

 1007 12:18:55.365055  Set Vref Range= 32 -> 127

 1008 12:18:55.365117  

 1009 12:18:55.367894  RX Vref 32 -> 127, step: 1

 1010 12:18:55.368022  

 1011 12:18:55.371492  RX Delay -95 -> 252, step: 8

 1012 12:18:55.371579  

 1013 12:18:55.374543  Set Vref, RX VrefLevel [Byte0]: 32

 1014 12:18:55.378147                           [Byte1]: 32

 1015 12:18:55.378235  

 1016 12:18:55.381462  Set Vref, RX VrefLevel [Byte0]: 33

 1017 12:18:55.384543                           [Byte1]: 33

 1018 12:18:55.388323  

 1019 12:18:55.388412  Set Vref, RX VrefLevel [Byte0]: 34

 1020 12:18:55.391381                           [Byte1]: 34

 1021 12:18:55.395835  

 1022 12:18:55.395965  Set Vref, RX VrefLevel [Byte0]: 35

 1023 12:18:55.398895                           [Byte1]: 35

 1024 12:18:55.403282  

 1025 12:18:55.403376  Set Vref, RX VrefLevel [Byte0]: 36

 1026 12:18:55.406390                           [Byte1]: 36

 1027 12:18:55.411483  

 1028 12:18:55.411624  Set Vref, RX VrefLevel [Byte0]: 37

 1029 12:18:55.414473                           [Byte1]: 37

 1030 12:18:55.418959  

 1031 12:18:55.419040  Set Vref, RX VrefLevel [Byte0]: 38

 1032 12:18:55.421983                           [Byte1]: 38

 1033 12:18:55.426096  

 1034 12:18:55.426181  Set Vref, RX VrefLevel [Byte0]: 39

 1035 12:18:55.429666                           [Byte1]: 39

 1036 12:18:55.433795  

 1037 12:18:55.433887  Set Vref, RX VrefLevel [Byte0]: 40

 1038 12:18:55.437007                           [Byte1]: 40

 1039 12:18:55.441565  

 1040 12:18:55.441659  Set Vref, RX VrefLevel [Byte0]: 41

 1041 12:18:55.445002                           [Byte1]: 41

 1042 12:18:55.448652  

 1043 12:18:55.448742  Set Vref, RX VrefLevel [Byte0]: 42

 1044 12:18:55.451848                           [Byte1]: 42

 1045 12:18:55.456125  

 1046 12:18:55.456211  Set Vref, RX VrefLevel [Byte0]: 43

 1047 12:18:55.459351                           [Byte1]: 43

 1048 12:18:55.463532  

 1049 12:18:55.467044  Set Vref, RX VrefLevel [Byte0]: 44

 1050 12:18:55.467132                           [Byte1]: 44

 1051 12:18:55.471411  

 1052 12:18:55.471498  Set Vref, RX VrefLevel [Byte0]: 45

 1053 12:18:55.474816                           [Byte1]: 45

 1054 12:18:55.479135  

 1055 12:18:55.479221  Set Vref, RX VrefLevel [Byte0]: 46

 1056 12:18:55.482229                           [Byte1]: 46

 1057 12:18:55.486652  

 1058 12:18:55.486741  Set Vref, RX VrefLevel [Byte0]: 47

 1059 12:18:55.490052                           [Byte1]: 47

 1060 12:18:55.494415  

 1061 12:18:55.494503  Set Vref, RX VrefLevel [Byte0]: 48

 1062 12:18:55.497539                           [Byte1]: 48

 1063 12:18:55.501932  

 1064 12:18:55.502018  Set Vref, RX VrefLevel [Byte0]: 49

 1065 12:18:55.505016                           [Byte1]: 49

 1066 12:18:55.509427  

 1067 12:18:55.509512  Set Vref, RX VrefLevel [Byte0]: 50

 1068 12:18:55.513009                           [Byte1]: 50

 1069 12:18:55.516858  

 1070 12:18:55.516950  Set Vref, RX VrefLevel [Byte0]: 51

 1071 12:18:55.520087                           [Byte1]: 51

 1072 12:18:55.525008  

 1073 12:18:55.525094  Set Vref, RX VrefLevel [Byte0]: 52

 1074 12:18:55.528162                           [Byte1]: 52

 1075 12:18:55.532517  

 1076 12:18:55.532605  Set Vref, RX VrefLevel [Byte0]: 53

 1077 12:18:55.535634                           [Byte1]: 53

 1078 12:18:55.539949  

 1079 12:18:55.540031  Set Vref, RX VrefLevel [Byte0]: 54

 1080 12:18:55.543363                           [Byte1]: 54

 1081 12:18:55.547613  

 1082 12:18:55.547736  Set Vref, RX VrefLevel [Byte0]: 55

 1083 12:18:55.550917                           [Byte1]: 55

 1084 12:18:55.554941  

 1085 12:18:55.555026  Set Vref, RX VrefLevel [Byte0]: 56

 1086 12:18:55.558170                           [Byte1]: 56

 1087 12:18:55.562455  

 1088 12:18:55.562539  Set Vref, RX VrefLevel [Byte0]: 57

 1089 12:18:55.565786                           [Byte1]: 57

 1090 12:18:55.570210  

 1091 12:18:55.570295  Set Vref, RX VrefLevel [Byte0]: 58

 1092 12:18:55.573719                           [Byte1]: 58

 1093 12:18:55.577908  

 1094 12:18:55.577996  Set Vref, RX VrefLevel [Byte0]: 59

 1095 12:18:55.580954                           [Byte1]: 59

 1096 12:18:55.585392  

 1097 12:18:55.585476  Set Vref, RX VrefLevel [Byte0]: 60

 1098 12:18:55.588585                           [Byte1]: 60

 1099 12:18:55.593355  

 1100 12:18:55.593445  Set Vref, RX VrefLevel [Byte0]: 61

 1101 12:18:55.596246                           [Byte1]: 61

 1102 12:18:55.600528  

 1103 12:18:55.600713  Set Vref, RX VrefLevel [Byte0]: 62

 1104 12:18:55.604233                           [Byte1]: 62

 1105 12:18:55.608598  

 1106 12:18:55.608682  Set Vref, RX VrefLevel [Byte0]: 63

 1107 12:18:55.611634                           [Byte1]: 63

 1108 12:18:55.616096  

 1109 12:18:55.616210  Set Vref, RX VrefLevel [Byte0]: 64

 1110 12:18:55.619288                           [Byte1]: 64

 1111 12:18:55.623774  

 1112 12:18:55.623862  Set Vref, RX VrefLevel [Byte0]: 65

 1113 12:18:55.626964                           [Byte1]: 65

 1114 12:18:55.631441  

 1115 12:18:55.631533  Set Vref, RX VrefLevel [Byte0]: 66

 1116 12:18:55.634487                           [Byte1]: 66

 1117 12:18:55.638866  

 1118 12:18:55.639061  Set Vref, RX VrefLevel [Byte0]: 67

 1119 12:18:55.642033                           [Byte1]: 67

 1120 12:18:55.646499  

 1121 12:18:55.646612  Set Vref, RX VrefLevel [Byte0]: 68

 1122 12:18:55.649659                           [Byte1]: 68

 1123 12:18:55.654041  

 1124 12:18:55.654125  Set Vref, RX VrefLevel [Byte0]: 69

 1125 12:18:55.657568                           [Byte1]: 69

 1126 12:18:55.661431  

 1127 12:18:55.661516  Set Vref, RX VrefLevel [Byte0]: 70

 1128 12:18:55.665095                           [Byte1]: 70

 1129 12:18:55.669474  

 1130 12:18:55.669557  Set Vref, RX VrefLevel [Byte0]: 71

 1131 12:18:55.672340                           [Byte1]: 71

 1132 12:18:55.676695  

 1133 12:18:55.676783  Set Vref, RX VrefLevel [Byte0]: 72

 1134 12:18:55.679898                           [Byte1]: 72

 1135 12:18:55.684374  

 1136 12:18:55.684480  Set Vref, RX VrefLevel [Byte0]: 73

 1137 12:18:55.687437                           [Byte1]: 73

 1138 12:18:55.691627  

 1139 12:18:55.691755  Set Vref, RX VrefLevel [Byte0]: 74

 1140 12:18:55.695022                           [Byte1]: 74

 1141 12:18:55.699346  

 1142 12:18:55.699432  Set Vref, RX VrefLevel [Byte0]: 75

 1143 12:18:55.702513                           [Byte1]: 75

 1144 12:18:55.707121  

 1145 12:18:55.707203  Set Vref, RX VrefLevel [Byte0]: 76

 1146 12:18:55.710447                           [Byte1]: 76

 1147 12:18:55.714855  

 1148 12:18:55.714945  Set Vref, RX VrefLevel [Byte0]: 77

 1149 12:18:55.718319                           [Byte1]: 77

 1150 12:18:55.722251  

 1151 12:18:55.722338  Final RX Vref Byte 0 = 54 to rank0

 1152 12:18:55.725442  Final RX Vref Byte 1 = 61 to rank0

 1153 12:18:55.729180  Final RX Vref Byte 0 = 54 to rank1

 1154 12:18:55.732283  Final RX Vref Byte 1 = 61 to rank1==

 1155 12:18:55.735469  Dram Type= 6, Freq= 0, CH_0, rank 0

 1156 12:18:55.742320  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1157 12:18:55.742423  ==

 1158 12:18:55.742492  DQS Delay:

 1159 12:18:55.742554  DQS0 = 0, DQS1 = 0

 1160 12:18:55.745469  DQM Delay:

 1161 12:18:55.745556  DQM0 = 91, DQM1 = 85

 1162 12:18:55.749444  DQ Delay:

 1163 12:18:55.752485  DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88

 1164 12:18:55.752562  DQ4 =92, DQ5 =80, DQ6 =96, DQ7 =100

 1165 12:18:55.755786  DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76

 1166 12:18:55.762520  DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92

 1167 12:18:55.762624  

 1168 12:18:55.762691  

 1169 12:18:55.768864  [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 1170 12:18:55.772116  CH0 RK0: MR19=606, MR18=4B41

 1171 12:18:55.779075  CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64

 1172 12:18:55.779173  

 1173 12:18:55.782307  ----->DramcWriteLeveling(PI) begin...

 1174 12:18:55.782393  ==

 1175 12:18:55.785559  Dram Type= 6, Freq= 0, CH_0, rank 1

 1176 12:18:55.789297  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1177 12:18:55.789384  ==

 1178 12:18:55.792390  Write leveling (Byte 0): 34 => 34

 1179 12:18:55.795569  Write leveling (Byte 1): 31 => 31

 1180 12:18:55.799118  DramcWriteLeveling(PI) end<-----

 1181 12:18:55.799204  

 1182 12:18:55.799298  ==

 1183 12:18:55.802564  Dram Type= 6, Freq= 0, CH_0, rank 1

 1184 12:18:55.805387  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1185 12:18:55.805472  ==

 1186 12:18:55.808792  [Gating] SW mode calibration

 1187 12:18:55.815552  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1188 12:18:55.859610  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1189 12:18:55.860019   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1190 12:18:55.860120   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1191 12:18:55.860229   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1192 12:18:55.860321   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1193 12:18:55.860424   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1194 12:18:55.860825   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1195 12:18:55.861121   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1196 12:18:55.861218   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1197 12:18:55.861346   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1198 12:18:55.864661   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1199 12:18:55.871478   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1200 12:18:55.874633   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1201 12:18:55.877747   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1202 12:18:55.881631   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1203 12:18:55.887962   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1204 12:18:55.891116   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1205 12:18:55.894914   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1206 12:18:55.901354   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1207 12:18:55.904503   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1208 12:18:55.908413   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1209 12:18:55.914619   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1210 12:18:55.918491   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1211 12:18:55.921484   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1212 12:18:55.928271   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1213 12:18:55.931571   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1214 12:18:55.934932   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1215 12:18:55.941551   0  9  8 | B1->B0 | 3131 2929 | 1 1 | (1 1) (1 1)

 1216 12:18:55.944997   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1217 12:18:55.948272   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1218 12:18:55.951397   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1219 12:18:55.958471   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1220 12:18:55.961811   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1221 12:18:55.965048   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1222 12:18:55.971614   0 10  4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)

 1223 12:18:55.974866   0 10  8 | B1->B0 | 2a2a 2929 | 1 0 | (1 1) (1 0)

 1224 12:18:55.978162   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1225 12:18:55.984792   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1226 12:18:55.988555   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1227 12:18:55.992969   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1228 12:18:55.996077   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1229 12:18:55.999959   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1230 12:18:56.006856   0 11  4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)

 1231 12:18:56.010585   0 11  8 | B1->B0 | 3a3a 3939 | 0 0 | (0 0) (0 0)

 1232 12:18:56.014221   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1233 12:18:56.017505   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1234 12:18:56.024449   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1235 12:18:56.027985   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1236 12:18:56.031683   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1237 12:18:56.038070   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1238 12:18:56.041231   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1239 12:18:56.044842   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1240 12:18:56.051302   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1241 12:18:56.054434   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1242 12:18:56.058279   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1243 12:18:56.061176   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1244 12:18:56.067862   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1245 12:18:56.071390   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1246 12:18:56.074491   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1247 12:18:56.081805   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1248 12:18:56.084663   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1249 12:18:56.087965   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1250 12:18:56.094638   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1251 12:18:56.098307   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1252 12:18:56.101602   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1253 12:18:56.108484   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1254 12:18:56.111561   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1255 12:18:56.114765   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1256 12:18:56.121744   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1257 12:18:56.121858  Total UI for P1: 0, mck2ui 16

 1258 12:18:56.124995  best dqsien dly found for B0: ( 0, 14,  6)

 1259 12:18:56.128163  Total UI for P1: 0, mck2ui 16

 1260 12:18:56.131860  best dqsien dly found for B1: ( 0, 14,  8)

 1261 12:18:56.134783  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1262 12:18:56.141810  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1263 12:18:56.141901  

 1264 12:18:56.144978  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1265 12:18:56.148250  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1266 12:18:56.151880  [Gating] SW calibration Done

 1267 12:18:56.151962  ==

 1268 12:18:56.154718  Dram Type= 6, Freq= 0, CH_0, rank 1

 1269 12:18:56.158220  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1270 12:18:56.158304  ==

 1271 12:18:56.158371  RX Vref Scan: 0

 1272 12:18:56.158431  

 1273 12:18:56.161395  RX Vref 0 -> 0, step: 1

 1274 12:18:56.161477  

 1275 12:18:56.165133  RX Delay -130 -> 252, step: 16

 1276 12:18:56.168118  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1277 12:18:56.171822  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

 1278 12:18:56.178235  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1279 12:18:56.181897  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1280 12:18:56.184988  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1281 12:18:56.188381  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

 1282 12:18:56.191317  iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208

 1283 12:18:56.198530  iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224

 1284 12:18:56.201516  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1285 12:18:56.205112  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1286 12:18:56.207937  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

 1287 12:18:56.211772  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1288 12:18:56.218272  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1289 12:18:56.221665  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1290 12:18:56.225196  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1291 12:18:56.228093  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1292 12:18:56.228180  ==

 1293 12:18:56.232052  Dram Type= 6, Freq= 0, CH_0, rank 1

 1294 12:18:56.238292  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1295 12:18:56.238435  ==

 1296 12:18:56.238550  DQS Delay:

 1297 12:18:56.238711  DQS0 = 0, DQS1 = 0

 1298 12:18:56.241859  DQM Delay:

 1299 12:18:56.241971  DQM0 = 92, DQM1 = 80

 1300 12:18:56.245051  DQ Delay:

 1301 12:18:56.248262  DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85

 1302 12:18:56.251903  DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =109

 1303 12:18:56.252016  DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77

 1304 12:18:56.258034  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1305 12:18:56.258173  

 1306 12:18:56.258311  

 1307 12:18:56.258446  ==

 1308 12:18:56.261834  Dram Type= 6, Freq= 0, CH_0, rank 1

 1309 12:18:56.265271  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1310 12:18:56.265401  ==

 1311 12:18:56.265472  

 1312 12:18:56.265538  

 1313 12:18:56.268397  	TX Vref Scan disable

 1314 12:18:56.268492   == TX Byte 0 ==

 1315 12:18:56.275114  Update DQ  dly =585 (2 ,1, 41)  DQ  OEN =(1 ,6)

 1316 12:18:56.278297  Update DQM dly =585 (2 ,1, 41)  DQM OEN =(1 ,6)

 1317 12:18:56.278443   == TX Byte 1 ==

 1318 12:18:56.285013  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1319 12:18:56.288454  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1320 12:18:56.288636  ==

 1321 12:18:56.291523  Dram Type= 6, Freq= 0, CH_0, rank 1

 1322 12:18:56.295288  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1323 12:18:56.295402  ==

 1324 12:18:56.308908  TX Vref=22, minBit 9, minWin=27, winSum=450

 1325 12:18:56.312698  TX Vref=24, minBit 1, minWin=28, winSum=452

 1326 12:18:56.315968  TX Vref=26, minBit 1, minWin=28, winSum=455

 1327 12:18:56.318966  TX Vref=28, minBit 1, minWin=28, winSum=456

 1328 12:18:56.322530  TX Vref=30, minBit 7, minWin=28, winSum=457

 1329 12:18:56.325902  TX Vref=32, minBit 8, minWin=27, winSum=451

 1330 12:18:56.332290  [TxChooseVref] Worse bit 7, Min win 28, Win sum 457, Final Vref 30

 1331 12:18:56.332390  

 1332 12:18:56.335784  Final TX Range 1 Vref 30

 1333 12:18:56.335874  

 1334 12:18:56.335940  ==

 1335 12:18:56.339044  Dram Type= 6, Freq= 0, CH_0, rank 1

 1336 12:18:56.342246  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1337 12:18:56.342333  ==

 1338 12:18:56.342399  

 1339 12:18:56.342460  

 1340 12:18:56.345709  	TX Vref Scan disable

 1341 12:18:56.349499   == TX Byte 0 ==

 1342 12:18:56.352672  Update DQ  dly =585 (2 ,1, 41)  DQ  OEN =(1 ,6)

 1343 12:18:56.355770  Update DQM dly =585 (2 ,1, 41)  DQM OEN =(1 ,6)

 1344 12:18:56.358928   == TX Byte 1 ==

 1345 12:18:56.362622  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1346 12:18:56.365815  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1347 12:18:56.369434  

 1348 12:18:56.369516  [DATLAT]

 1349 12:18:56.369582  Freq=800, CH0 RK1

 1350 12:18:56.369644  

 1351 12:18:56.372390  DATLAT Default: 0xa

 1352 12:18:56.372473  0, 0xFFFF, sum = 0

 1353 12:18:56.375889  1, 0xFFFF, sum = 0

 1354 12:18:56.375975  2, 0xFFFF, sum = 0

 1355 12:18:56.379077  3, 0xFFFF, sum = 0

 1356 12:18:56.379162  4, 0xFFFF, sum = 0

 1357 12:18:56.382606  5, 0xFFFF, sum = 0

 1358 12:18:56.382695  6, 0xFFFF, sum = 0

 1359 12:18:56.385909  7, 0xFFFF, sum = 0

 1360 12:18:56.385993  8, 0xFFFF, sum = 0

 1361 12:18:56.389499  9, 0x0, sum = 1

 1362 12:18:56.389585  10, 0x0, sum = 2

 1363 12:18:56.392549  11, 0x0, sum = 3

 1364 12:18:56.392633  12, 0x0, sum = 4

 1365 12:18:56.396177  best_step = 10

 1366 12:18:56.396261  

 1367 12:18:56.396326  ==

 1368 12:18:56.399327  Dram Type= 6, Freq= 0, CH_0, rank 1

 1369 12:18:56.402482  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1370 12:18:56.402566  ==

 1371 12:18:56.406288  RX Vref Scan: 0

 1372 12:18:56.406371  

 1373 12:18:56.406437  RX Vref 0 -> 0, step: 1

 1374 12:18:56.406499  

 1375 12:18:56.409362  RX Delay -95 -> 252, step: 8

 1376 12:18:56.416362  iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216

 1377 12:18:56.419439  iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208

 1378 12:18:56.422588  iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216

 1379 12:18:56.426443  iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216

 1380 12:18:56.429593  iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224

 1381 12:18:56.432883  iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216

 1382 12:18:56.439795  iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216

 1383 12:18:56.442818  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1384 12:18:56.446428  iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216

 1385 12:18:56.449774  iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208

 1386 12:18:56.452986  iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208

 1387 12:18:56.459811  iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216

 1388 12:18:56.462880  iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216

 1389 12:18:56.466293  iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208

 1390 12:18:56.469659  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1391 12:18:56.473327  iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216

 1392 12:18:56.473411  ==

 1393 12:18:56.476304  Dram Type= 6, Freq= 0, CH_0, rank 1

 1394 12:18:56.483134  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1395 12:18:56.483221  ==

 1396 12:18:56.483317  DQS Delay:

 1397 12:18:56.486776  DQS0 = 0, DQS1 = 0

 1398 12:18:56.486859  DQM Delay:

 1399 12:18:56.486924  DQM0 = 94, DQM1 = 84

 1400 12:18:56.489769  DQ Delay:

 1401 12:18:56.493590  DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =92

 1402 12:18:56.496666  DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100

 1403 12:18:56.499652  DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =76

 1404 12:18:56.503440  DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92

 1405 12:18:56.503522  

 1406 12:18:56.503585  

 1407 12:18:56.509812  [DQSOSCAuto] RK1, (LSB)MR18= 0x4111, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps

 1408 12:18:56.513440  CH0 RK1: MR19=606, MR18=4111

 1409 12:18:56.519950  CH0_RK1: MR19=0x606, MR18=0x4111, DQSOSC=393, MR23=63, INC=95, DEC=63

 1410 12:18:56.523564  [RxdqsGatingPostProcess] freq 800

 1411 12:18:56.526837  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1412 12:18:56.530008  Pre-setting of DQS Precalculation

 1413 12:18:56.536862  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1414 12:18:56.536951  ==

 1415 12:18:56.540056  Dram Type= 6, Freq= 0, CH_1, rank 0

 1416 12:18:56.543918  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1417 12:18:56.544004  ==

 1418 12:18:56.550271  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1419 12:18:56.553403  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1420 12:18:56.563888  [CA 0] Center 36 (6~67) winsize 62

 1421 12:18:56.567678  [CA 1] Center 36 (6~67) winsize 62

 1422 12:18:56.570538  [CA 2] Center 35 (5~66) winsize 62

 1423 12:18:56.574378  [CA 3] Center 34 (4~65) winsize 62

 1424 12:18:56.577211  [CA 4] Center 35 (5~65) winsize 61

 1425 12:18:56.580558  [CA 5] Center 34 (4~65) winsize 62

 1426 12:18:56.580655  

 1427 12:18:56.584081  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1428 12:18:56.584206  

 1429 12:18:56.587346  [CATrainingPosCal] consider 1 rank data

 1430 12:18:56.591039  u2DelayCellTimex100 = 270/100 ps

 1431 12:18:56.593973  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1432 12:18:56.597267  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1433 12:18:56.604394  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1434 12:18:56.607814  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1435 12:18:56.611009  CA4 delay=35 (5~65),Diff = 1 PI (7 cell)

 1436 12:18:56.613893  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 1437 12:18:56.614012  

 1438 12:18:56.617474  CA PerBit enable=1, Macro0, CA PI delay=34

 1439 12:18:56.617558  

 1440 12:18:56.621141  [CBTSetCACLKResult] CA Dly = 34

 1441 12:18:56.621223  CS Dly: 5 (0~36)

 1442 12:18:56.621289  ==

 1443 12:18:56.624335  Dram Type= 6, Freq= 0, CH_1, rank 1

 1444 12:18:56.630659  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1445 12:18:56.630747  ==

 1446 12:18:56.634376  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1447 12:18:56.640866  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1448 12:18:56.650455  [CA 0] Center 36 (6~67) winsize 62

 1449 12:18:56.654627  [CA 1] Center 36 (6~67) winsize 62

 1450 12:18:56.658505  [CA 2] Center 35 (4~66) winsize 63

 1451 12:18:56.662478  [CA 3] Center 34 (4~65) winsize 62

 1452 12:18:56.662580  [CA 4] Center 35 (4~66) winsize 63

 1453 12:18:56.666702  [CA 5] Center 34 (4~65) winsize 62

 1454 12:18:56.666829  

 1455 12:18:56.670639  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1456 12:18:56.670719  

 1457 12:18:56.673881  [CATrainingPosCal] consider 2 rank data

 1458 12:18:56.678309  u2DelayCellTimex100 = 270/100 ps

 1459 12:18:56.681902  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1460 12:18:56.685363  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1461 12:18:56.688492  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1462 12:18:56.692279  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1463 12:18:56.695411  CA4 delay=35 (5~65),Diff = 1 PI (7 cell)

 1464 12:18:56.699199  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 1465 12:18:56.699283  

 1466 12:18:56.702246  CA PerBit enable=1, Macro0, CA PI delay=34

 1467 12:18:56.702329  

 1468 12:18:56.705711  [CBTSetCACLKResult] CA Dly = 34

 1469 12:18:56.708812  CS Dly: 6 (0~38)

 1470 12:18:56.708894  

 1471 12:18:56.712103  ----->DramcWriteLeveling(PI) begin...

 1472 12:18:56.712184  ==

 1473 12:18:56.715398  Dram Type= 6, Freq= 0, CH_1, rank 0

 1474 12:18:56.718869  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1475 12:18:56.718953  ==

 1476 12:18:56.722581  Write leveling (Byte 0): 26 => 26

 1477 12:18:56.725283  Write leveling (Byte 1): 26 => 26

 1478 12:18:56.729102  DramcWriteLeveling(PI) end<-----

 1479 12:18:56.729185  

 1480 12:18:56.729249  ==

 1481 12:18:56.732302  Dram Type= 6, Freq= 0, CH_1, rank 0

 1482 12:18:56.735293  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1483 12:18:56.735375  ==

 1484 12:18:56.738708  [Gating] SW mode calibration

 1485 12:18:56.745240  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1486 12:18:56.752348  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1487 12:18:56.755394   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1488 12:18:56.758549   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1489 12:18:56.765763   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1490 12:18:56.768696   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1491 12:18:56.772383   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1492 12:18:56.778711   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1493 12:18:56.782584   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1494 12:18:56.785632   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1495 12:18:56.792349   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1496 12:18:56.795754   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1497 12:18:56.798791   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1498 12:18:56.805838   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1499 12:18:56.808910   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1500 12:18:56.812167   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1501 12:18:56.818894   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1502 12:18:56.822445   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1503 12:18:56.826023   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1504 12:18:56.829525   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1505 12:18:56.835532   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1506 12:18:56.839291   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1507 12:18:56.842275   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1508 12:18:56.848804   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1509 12:18:56.852541   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1510 12:18:56.855880   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1511 12:18:56.862860   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1512 12:18:56.866150   0  9  4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)

 1513 12:18:56.869367   0  9  8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 1514 12:18:56.876525   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1515 12:18:56.879565   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1516 12:18:56.882816   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1517 12:18:56.889564   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1518 12:18:56.892948   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1519 12:18:56.896115   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 1520 12:18:56.899169   0 10  4 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 1)

 1521 12:18:56.905759   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1522 12:18:56.909586   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1523 12:18:56.912721   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1524 12:18:56.919623   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1525 12:18:56.922880   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1526 12:18:56.926078   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1527 12:18:56.932735   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1528 12:18:56.935904   0 11  4 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)

 1529 12:18:56.939586   0 11  8 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)

 1530 12:18:56.946390   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1531 12:18:56.949532   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1532 12:18:56.952972   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1533 12:18:56.959302   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1534 12:18:56.962689   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1535 12:18:56.966058   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1536 12:18:56.972724   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 1537 12:18:56.976064   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 1538 12:18:56.979423   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1539 12:18:56.983187   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1540 12:18:56.989879   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1541 12:18:56.993047   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1542 12:18:56.996321   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1543 12:18:57.003205   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1544 12:18:57.006290   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1545 12:18:57.009350   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1546 12:18:57.016271   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1547 12:18:57.019527   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1548 12:18:57.022852   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1549 12:18:57.029905   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1550 12:18:57.032880   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1551 12:18:57.036811   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1552 12:18:57.043146   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1553 12:18:57.043231  Total UI for P1: 0, mck2ui 16

 1554 12:18:57.046727  best dqsien dly found for B0: ( 0, 14,  2)

 1555 12:18:57.053058   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1556 12:18:57.056349  Total UI for P1: 0, mck2ui 16

 1557 12:18:57.060079  best dqsien dly found for B1: ( 0, 14,  4)

 1558 12:18:57.063129  best DQS0 dly(MCK, UI, PI) = (0, 14, 2)

 1559 12:18:57.066505  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1560 12:18:57.066588  

 1561 12:18:57.070196  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1562 12:18:57.073131  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1563 12:18:57.076714  [Gating] SW calibration Done

 1564 12:18:57.076796  ==

 1565 12:18:57.079795  Dram Type= 6, Freq= 0, CH_1, rank 0

 1566 12:18:57.083411  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1567 12:18:57.083494  ==

 1568 12:18:57.086425  RX Vref Scan: 0

 1569 12:18:57.086507  

 1570 12:18:57.086572  RX Vref 0 -> 0, step: 1

 1571 12:18:57.086632  

 1572 12:18:57.090042  RX Delay -130 -> 252, step: 16

 1573 12:18:57.093468  iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208

 1574 12:18:57.100063  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1575 12:18:57.103260  iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208

 1576 12:18:57.106541  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

 1577 12:18:57.110294  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1578 12:18:57.113431  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1579 12:18:57.120051  iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224

 1580 12:18:57.123474  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1581 12:18:57.126592  iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208

 1582 12:18:57.129802  iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208

 1583 12:18:57.133571  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

 1584 12:18:57.140357  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1585 12:18:57.143432  iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208

 1586 12:18:57.146638  iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208

 1587 12:18:57.150340  iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208

 1588 12:18:57.153266  iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208

 1589 12:18:57.156505  ==

 1590 12:18:57.159760  Dram Type= 6, Freq= 0, CH_1, rank 0

 1591 12:18:57.163476  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1592 12:18:57.163584  ==

 1593 12:18:57.163708  DQS Delay:

 1594 12:18:57.166658  DQS0 = 0, DQS1 = 0

 1595 12:18:57.166739  DQM Delay:

 1596 12:18:57.169741  DQM0 = 96, DQM1 = 93

 1597 12:18:57.169823  DQ Delay:

 1598 12:18:57.173232  DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =93

 1599 12:18:57.176777  DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93

 1600 12:18:57.179858  DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85

 1601 12:18:57.183387  DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101

 1602 12:18:57.183495  

 1603 12:18:57.183587  

 1604 12:18:57.183719  ==

 1605 12:18:57.186588  Dram Type= 6, Freq= 0, CH_1, rank 0

 1606 12:18:57.190195  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1607 12:18:57.190279  ==

 1608 12:18:57.190344  

 1609 12:18:57.193399  

 1610 12:18:57.193481  	TX Vref Scan disable

 1611 12:18:57.196551   == TX Byte 0 ==

 1612 12:18:57.200298  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1613 12:18:57.203434  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1614 12:18:57.206590   == TX Byte 1 ==

 1615 12:18:57.210311  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1616 12:18:57.213611  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1617 12:18:57.213694  ==

 1618 12:18:57.217045  Dram Type= 6, Freq= 0, CH_1, rank 0

 1619 12:18:57.223075  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1620 12:18:57.223212  ==

 1621 12:18:57.235277  TX Vref=22, minBit 0, minWin=26, winSum=434

 1622 12:18:57.239136  TX Vref=24, minBit 1, minWin=26, winSum=440

 1623 12:18:57.242168  TX Vref=26, minBit 0, minWin=27, winSum=445

 1624 12:18:57.245591  TX Vref=28, minBit 1, minWin=27, winSum=442

 1625 12:18:57.248835  TX Vref=30, minBit 1, minWin=27, winSum=447

 1626 12:18:57.251905  TX Vref=32, minBit 0, minWin=27, winSum=443

 1627 12:18:57.258773  [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 30

 1628 12:18:57.258859  

 1629 12:18:57.261963  Final TX Range 1 Vref 30

 1630 12:18:57.262045  

 1631 12:18:57.262109  ==

 1632 12:18:57.265691  Dram Type= 6, Freq= 0, CH_1, rank 0

 1633 12:18:57.268863  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1634 12:18:57.268946  ==

 1635 12:18:57.269011  

 1636 12:18:57.269086  

 1637 12:18:57.272114  	TX Vref Scan disable

 1638 12:18:57.275202   == TX Byte 0 ==

 1639 12:18:57.278933  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1640 12:18:57.281978  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1641 12:18:57.285509   == TX Byte 1 ==

 1642 12:18:57.289074  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 1643 12:18:57.291971  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 1644 12:18:57.292055  

 1645 12:18:57.295696  [DATLAT]

 1646 12:18:57.295778  Freq=800, CH1 RK0

 1647 12:18:57.295844  

 1648 12:18:57.298932  DATLAT Default: 0xa

 1649 12:18:57.299013  0, 0xFFFF, sum = 0

 1650 12:18:57.302063  1, 0xFFFF, sum = 0

 1651 12:18:57.302146  2, 0xFFFF, sum = 0

 1652 12:18:57.305764  3, 0xFFFF, sum = 0

 1653 12:18:57.305848  4, 0xFFFF, sum = 0

 1654 12:18:57.308942  5, 0xFFFF, sum = 0

 1655 12:18:57.309025  6, 0xFFFF, sum = 0

 1656 12:18:57.311972  7, 0xFFFF, sum = 0

 1657 12:18:57.312056  8, 0xFFFF, sum = 0

 1658 12:18:57.315988  9, 0x0, sum = 1

 1659 12:18:57.316071  10, 0x0, sum = 2

 1660 12:18:57.319032  11, 0x0, sum = 3

 1661 12:18:57.319115  12, 0x0, sum = 4

 1662 12:18:57.322197  best_step = 10

 1663 12:18:57.322302  

 1664 12:18:57.322395  ==

 1665 12:18:57.325830  Dram Type= 6, Freq= 0, CH_1, rank 0

 1666 12:18:57.329048  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1667 12:18:57.329132  ==

 1668 12:18:57.329197  RX Vref Scan: 1

 1669 12:18:57.329257  

 1670 12:18:57.332772  Set Vref Range= 32 -> 127

 1671 12:18:57.332855  

 1672 12:18:57.335617  RX Vref 32 -> 127, step: 1

 1673 12:18:57.335745  

 1674 12:18:57.339164  RX Delay -63 -> 252, step: 8

 1675 12:18:57.339245  

 1676 12:18:57.342357  Set Vref, RX VrefLevel [Byte0]: 32

 1677 12:18:57.345952                           [Byte1]: 32

 1678 12:18:57.346037  

 1679 12:18:57.349321  Set Vref, RX VrefLevel [Byte0]: 33

 1680 12:18:57.352649                           [Byte1]: 33

 1681 12:18:57.352759  

 1682 12:18:57.356131  Set Vref, RX VrefLevel [Byte0]: 34

 1683 12:18:57.359035                           [Byte1]: 34

 1684 12:18:57.359120  

 1685 12:18:57.362694  Set Vref, RX VrefLevel [Byte0]: 35

 1686 12:18:57.366234                           [Byte1]: 35

 1687 12:18:57.370119  

 1688 12:18:57.370202  Set Vref, RX VrefLevel [Byte0]: 36

 1689 12:18:57.373341                           [Byte1]: 36

 1690 12:18:57.377095  

 1691 12:18:57.377203  Set Vref, RX VrefLevel [Byte0]: 37

 1692 12:18:57.380906                           [Byte1]: 37

 1693 12:18:57.384730  

 1694 12:18:57.384812  Set Vref, RX VrefLevel [Byte0]: 38

 1695 12:18:57.388336                           [Byte1]: 38

 1696 12:18:57.392162  

 1697 12:18:57.392244  Set Vref, RX VrefLevel [Byte0]: 39

 1698 12:18:57.395755                           [Byte1]: 39

 1699 12:18:57.399861  

 1700 12:18:57.399942  Set Vref, RX VrefLevel [Byte0]: 40

 1701 12:18:57.403384                           [Byte1]: 40

 1702 12:18:57.407555  

 1703 12:18:57.407695  Set Vref, RX VrefLevel [Byte0]: 41

 1704 12:18:57.410395                           [Byte1]: 41

 1705 12:18:57.414868  

 1706 12:18:57.414976  Set Vref, RX VrefLevel [Byte0]: 42

 1707 12:18:57.418010                           [Byte1]: 42

 1708 12:18:57.422498  

 1709 12:18:57.422581  Set Vref, RX VrefLevel [Byte0]: 43

 1710 12:18:57.425614                           [Byte1]: 43

 1711 12:18:57.430081  

 1712 12:18:57.430164  Set Vref, RX VrefLevel [Byte0]: 44

 1713 12:18:57.433328                           [Byte1]: 44

 1714 12:18:57.437264  

 1715 12:18:57.437378  Set Vref, RX VrefLevel [Byte0]: 45

 1716 12:18:57.440597                           [Byte1]: 45

 1717 12:18:57.444708  

 1718 12:18:57.444797  Set Vref, RX VrefLevel [Byte0]: 46

 1719 12:18:57.448496                           [Byte1]: 46

 1720 12:18:57.452276  

 1721 12:18:57.452375  Set Vref, RX VrefLevel [Byte0]: 47

 1722 12:18:57.455769                           [Byte1]: 47

 1723 12:18:57.460108  

 1724 12:18:57.460192  Set Vref, RX VrefLevel [Byte0]: 48

 1725 12:18:57.462803                           [Byte1]: 48

 1726 12:18:57.467274  

 1727 12:18:57.467362  Set Vref, RX VrefLevel [Byte0]: 49

 1728 12:18:57.470371                           [Byte1]: 49

 1729 12:18:57.474898  

 1730 12:18:57.474982  Set Vref, RX VrefLevel [Byte0]: 50

 1731 12:18:57.478214                           [Byte1]: 50

 1732 12:18:57.482395  

 1733 12:18:57.482479  Set Vref, RX VrefLevel [Byte0]: 51

 1734 12:18:57.485819                           [Byte1]: 51

 1735 12:18:57.489820  

 1736 12:18:57.489906  Set Vref, RX VrefLevel [Byte0]: 52

 1737 12:18:57.492867                           [Byte1]: 52

 1738 12:18:57.497280  

 1739 12:18:57.497380  Set Vref, RX VrefLevel [Byte0]: 53

 1740 12:18:57.500376                           [Byte1]: 53

 1741 12:18:57.504851  

 1742 12:18:57.504966  Set Vref, RX VrefLevel [Byte0]: 54

 1743 12:18:57.508049                           [Byte1]: 54

 1744 12:18:57.512384  

 1745 12:18:57.512485  Set Vref, RX VrefLevel [Byte0]: 55

 1746 12:18:57.515270                           [Byte1]: 55

 1747 12:18:57.519795  

 1748 12:18:57.519877  Set Vref, RX VrefLevel [Byte0]: 56

 1749 12:18:57.522801                           [Byte1]: 56

 1750 12:18:57.527158  

 1751 12:18:57.527246  Set Vref, RX VrefLevel [Byte0]: 57

 1752 12:18:57.530390                           [Byte1]: 57

 1753 12:18:57.534809  

 1754 12:18:57.534897  Set Vref, RX VrefLevel [Byte0]: 58

 1755 12:18:57.537967                           [Byte1]: 58

 1756 12:18:57.542633  

 1757 12:18:57.542718  Set Vref, RX VrefLevel [Byte0]: 59

 1758 12:18:57.545707                           [Byte1]: 59

 1759 12:18:57.549440  

 1760 12:18:57.549525  Set Vref, RX VrefLevel [Byte0]: 60

 1761 12:18:57.553325                           [Byte1]: 60

 1762 12:18:57.557045  

 1763 12:18:57.557129  Set Vref, RX VrefLevel [Byte0]: 61

 1764 12:18:57.560894                           [Byte1]: 61

 1765 12:18:57.564736  

 1766 12:18:57.564822  Set Vref, RX VrefLevel [Byte0]: 62

 1767 12:18:57.568451                           [Byte1]: 62

 1768 12:18:57.572140  

 1769 12:18:57.572231  Set Vref, RX VrefLevel [Byte0]: 63

 1770 12:18:57.575241                           [Byte1]: 63

 1771 12:18:57.579452  

 1772 12:18:57.579540  Set Vref, RX VrefLevel [Byte0]: 64

 1773 12:18:57.583363                           [Byte1]: 64

 1774 12:18:57.586969  

 1775 12:18:57.587082  Set Vref, RX VrefLevel [Byte0]: 65

 1776 12:18:57.590732                           [Byte1]: 65

 1777 12:18:57.594651  

 1778 12:18:57.594726  Set Vref, RX VrefLevel [Byte0]: 66

 1779 12:18:57.598044                           [Byte1]: 66

 1780 12:18:57.601952  

 1781 12:18:57.602054  Set Vref, RX VrefLevel [Byte0]: 67

 1782 12:18:57.605318                           [Byte1]: 67

 1783 12:18:57.609518  

 1784 12:18:57.609619  Set Vref, RX VrefLevel [Byte0]: 68

 1785 12:18:57.613170                           [Byte1]: 68

 1786 12:18:57.617170  

 1787 12:18:57.617276  Set Vref, RX VrefLevel [Byte0]: 69

 1788 12:18:57.620385                           [Byte1]: 69

 1789 12:18:57.624568  

 1790 12:18:57.624652  Set Vref, RX VrefLevel [Byte0]: 70

 1791 12:18:57.628170                           [Byte1]: 70

 1792 12:18:57.631984  

 1793 12:18:57.632088  Set Vref, RX VrefLevel [Byte0]: 71

 1794 12:18:57.635548                           [Byte1]: 71

 1795 12:18:57.639704  

 1796 12:18:57.639786  Set Vref, RX VrefLevel [Byte0]: 72

 1797 12:18:57.642879                           [Byte1]: 72

 1798 12:18:57.647275  

 1799 12:18:57.647381  Set Vref, RX VrefLevel [Byte0]: 73

 1800 12:18:57.650469                           [Byte1]: 73

 1801 12:18:57.654941  

 1802 12:18:57.655026  Set Vref, RX VrefLevel [Byte0]: 74

 1803 12:18:57.658070                           [Byte1]: 74

 1804 12:18:57.662413  

 1805 12:18:57.662497  Set Vref, RX VrefLevel [Byte0]: 75

 1806 12:18:57.665551                           [Byte1]: 75

 1807 12:18:57.669968  

 1808 12:18:57.670053  Final RX Vref Byte 0 = 55 to rank0

 1809 12:18:57.673045  Final RX Vref Byte 1 = 58 to rank0

 1810 12:18:57.676234  Final RX Vref Byte 0 = 55 to rank1

 1811 12:18:57.680007  Final RX Vref Byte 1 = 58 to rank1==

 1812 12:18:57.683006  Dram Type= 6, Freq= 0, CH_1, rank 0

 1813 12:18:57.690036  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1814 12:18:57.690128  ==

 1815 12:18:57.690198  DQS Delay:

 1816 12:18:57.690261  DQS0 = 0, DQS1 = 0

 1817 12:18:57.693100  DQM Delay:

 1818 12:18:57.693210  DQM0 = 95, DQM1 = 90

 1819 12:18:57.696309  DQ Delay:

 1820 12:18:57.696416  DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88

 1821 12:18:57.700237  DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92

 1822 12:18:57.703361  DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84

 1823 12:18:57.709651  DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96

 1824 12:18:57.709761  

 1825 12:18:57.709856  

 1826 12:18:57.716095  [DQSOSCAuto] RK0, (LSB)MR18= 0x2c47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps

 1827 12:18:57.719611  CH1 RK0: MR19=606, MR18=2C47

 1828 12:18:57.726523  CH1_RK0: MR19=0x606, MR18=0x2C47, DQSOSC=392, MR23=63, INC=96, DEC=64

 1829 12:18:57.726614  

 1830 12:18:57.729395  ----->DramcWriteLeveling(PI) begin...

 1831 12:18:57.729482  ==

 1832 12:18:57.732714  Dram Type= 6, Freq= 0, CH_1, rank 1

 1833 12:18:57.736244  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1834 12:18:57.736330  ==

 1835 12:18:57.739406  Write leveling (Byte 0): 27 => 27

 1836 12:18:57.742940  Write leveling (Byte 1): 26 => 26

 1837 12:18:57.746120  DramcWriteLeveling(PI) end<-----

 1838 12:18:57.746206  

 1839 12:18:57.746272  ==

 1840 12:18:57.749654  Dram Type= 6, Freq= 0, CH_1, rank 1

 1841 12:18:57.752852  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1842 12:18:57.752938  ==

 1843 12:18:57.756128  [Gating] SW mode calibration

 1844 12:18:57.763046  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1845 12:18:57.769469  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1846 12:18:57.773297   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1847 12:18:57.776302   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1848 12:18:57.783306   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1849 12:18:57.786379   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1850 12:18:57.789564   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1851 12:18:57.796510   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1852 12:18:57.799736   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1853 12:18:57.802847   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1854 12:18:57.809869   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1855 12:18:57.813083   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1856 12:18:57.816835   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1857 12:18:57.820022   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1858 12:18:57.826449   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1859 12:18:57.830140   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1860 12:18:57.833131   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1861 12:18:57.839938   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1862 12:18:57.843195   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1863 12:18:57.846947   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1864 12:18:57.853516   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1865 12:18:57.856814   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1866 12:18:57.859711   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1867 12:18:57.866981   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1868 12:18:57.870215   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1869 12:18:57.873080   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1870 12:18:57.880299   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1871 12:18:57.883518   0  9  4 | B1->B0 | 2c2c 2322 | 1 1 | (1 1) (0 0)

 1872 12:18:57.886693   0  9  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 1873 12:18:57.893232   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1874 12:18:57.896363   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1875 12:18:57.900118   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1876 12:18:57.903332   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1877 12:18:57.909735   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1878 12:18:57.913542   0 10  0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 1879 12:18:57.916681   0 10  4 | B1->B0 | 2727 3030 | 0 0 | (0 0) (1 1)

 1880 12:18:57.923655   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1881 12:18:57.926739   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1882 12:18:57.930141   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1883 12:18:57.936941   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1884 12:18:57.940561   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1885 12:18:57.943829   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1886 12:18:57.950042   0 11  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1887 12:18:57.953739   0 11  4 | B1->B0 | 3b3b 2a2a | 0 0 | (1 1) (0 0)

 1888 12:18:57.956884   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1889 12:18:57.963555   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1890 12:18:57.967236   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1891 12:18:57.970333   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1892 12:18:57.973346   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1893 12:18:57.980496   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1894 12:18:57.983535   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1895 12:18:57.986864   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 1896 12:18:57.993608   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1897 12:18:57.997162   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1898 12:18:58.000230   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1899 12:18:58.006765   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1900 12:18:58.010527   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1901 12:18:58.013831   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1902 12:18:58.020028   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1903 12:18:58.023732   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1904 12:18:58.026882   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1905 12:18:58.033643   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1906 12:18:58.037151   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1907 12:18:58.040387   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1908 12:18:58.046938   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1909 12:18:58.050664   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1910 12:18:58.053798   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 1911 12:18:58.060707   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1912 12:18:58.060794  Total UI for P1: 0, mck2ui 16

 1913 12:18:58.063888  best dqsien dly found for B1: ( 0, 14,  0)

 1914 12:18:58.070472   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1915 12:18:58.073483  Total UI for P1: 0, mck2ui 16

 1916 12:18:58.076791  best dqsien dly found for B0: ( 0, 14,  4)

 1917 12:18:58.080635  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1918 12:18:58.083842  best DQS1 dly(MCK, UI, PI) = (0, 14, 0)

 1919 12:18:58.083945  

 1920 12:18:58.086888  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1921 12:18:58.090543  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)

 1922 12:18:58.093658  [Gating] SW calibration Done

 1923 12:18:58.093737  ==

 1924 12:18:58.097107  Dram Type= 6, Freq= 0, CH_1, rank 1

 1925 12:18:58.100258  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1926 12:18:58.100338  ==

 1927 12:18:58.103945  RX Vref Scan: 0

 1928 12:18:58.104039  

 1929 12:18:58.104106  RX Vref 0 -> 0, step: 1

 1930 12:18:58.104168  

 1931 12:18:58.107330  RX Delay -130 -> 252, step: 16

 1932 12:18:58.113697  iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208

 1933 12:18:58.117141  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1934 12:18:58.120272  iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208

 1935 12:18:58.123872  iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208

 1936 12:18:58.127066  iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208

 1937 12:18:58.130838  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1938 12:18:58.137260  iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208

 1939 12:18:58.140287  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1940 12:18:58.143921  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1941 12:18:58.146901  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1942 12:18:58.150504  iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224

 1943 12:18:58.157089  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1944 12:18:58.160277  iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208

 1945 12:18:58.163524  iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208

 1946 12:18:58.167348  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1947 12:18:58.173591  iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208

 1948 12:18:58.173700  ==

 1949 12:18:58.177031  Dram Type= 6, Freq= 0, CH_1, rank 1

 1950 12:18:58.180430  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1951 12:18:58.180510  ==

 1952 12:18:58.180574  DQS Delay:

 1953 12:18:58.183606  DQS0 = 0, DQS1 = 0

 1954 12:18:58.183727  DQM Delay:

 1955 12:18:58.187457  DQM0 = 93, DQM1 = 91

 1956 12:18:58.187559  DQ Delay:

 1957 12:18:58.190561  DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85

 1958 12:18:58.193649  DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93

 1959 12:18:58.196848  DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85

 1960 12:18:58.200411  DQ12 =101, DQ13 =101, DQ14 =93, DQ15 =101

 1961 12:18:58.200514  

 1962 12:18:58.200618  

 1963 12:18:58.200725  ==

 1964 12:18:58.203892  Dram Type= 6, Freq= 0, CH_1, rank 1

 1965 12:18:58.207292  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1966 12:18:58.207397  ==

 1967 12:18:58.207498  

 1968 12:18:58.210429  

 1969 12:18:58.210533  	TX Vref Scan disable

 1970 12:18:58.213640   == TX Byte 0 ==

 1971 12:18:58.217436  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1972 12:18:58.220576  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1973 12:18:58.223674   == TX Byte 1 ==

 1974 12:18:58.227274  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1975 12:18:58.230220  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1976 12:18:58.230296  ==

 1977 12:18:58.233757  Dram Type= 6, Freq= 0, CH_1, rank 1

 1978 12:18:58.240260  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1979 12:18:58.240339  ==

 1980 12:18:58.252358  TX Vref=22, minBit 1, minWin=26, winSum=438

 1981 12:18:58.255423  TX Vref=24, minBit 1, minWin=26, winSum=441

 1982 12:18:58.258928  TX Vref=26, minBit 0, minWin=27, winSum=444

 1983 12:18:58.262169  TX Vref=28, minBit 2, minWin=27, winSum=449

 1984 12:18:58.265900  TX Vref=30, minBit 2, minWin=27, winSum=448

 1985 12:18:58.269056  TX Vref=32, minBit 0, minWin=27, winSum=448

 1986 12:18:58.275996  [TxChooseVref] Worse bit 2, Min win 27, Win sum 449, Final Vref 28

 1987 12:18:58.276123  

 1988 12:18:58.279153  Final TX Range 1 Vref 28

 1989 12:18:58.279263  

 1990 12:18:58.279359  ==

 1991 12:18:58.282275  Dram Type= 6, Freq= 0, CH_1, rank 1

 1992 12:18:58.285813  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1993 12:18:58.285917  ==

 1994 12:18:58.286009  

 1995 12:18:58.286101  

 1996 12:18:58.289346  	TX Vref Scan disable

 1997 12:18:58.292313   == TX Byte 0 ==

 1998 12:18:58.296043  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1999 12:18:58.299137  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 2000 12:18:58.302886   == TX Byte 1 ==

 2001 12:18:58.306033  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 2002 12:18:58.309046  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 2003 12:18:58.309151  

 2004 12:18:58.312598  [DATLAT]

 2005 12:18:58.312685  Freq=800, CH1 RK1

 2006 12:18:58.312776  

 2007 12:18:58.316206  DATLAT Default: 0xa

 2008 12:18:58.316282  0, 0xFFFF, sum = 0

 2009 12:18:58.319299  1, 0xFFFF, sum = 0

 2010 12:18:58.319402  2, 0xFFFF, sum = 0

 2011 12:18:58.322473  3, 0xFFFF, sum = 0

 2012 12:18:58.322575  4, 0xFFFF, sum = 0

 2013 12:18:58.325574  5, 0xFFFF, sum = 0

 2014 12:18:58.325684  6, 0xFFFF, sum = 0

 2015 12:18:58.329307  7, 0xFFFF, sum = 0

 2016 12:18:58.329387  8, 0xFFFF, sum = 0

 2017 12:18:58.332476  9, 0x0, sum = 1

 2018 12:18:58.332575  10, 0x0, sum = 2

 2019 12:18:58.335631  11, 0x0, sum = 3

 2020 12:18:58.335743  12, 0x0, sum = 4

 2021 12:18:58.339243  best_step = 10

 2022 12:18:58.339341  

 2023 12:18:58.339430  ==

 2024 12:18:58.342269  Dram Type= 6, Freq= 0, CH_1, rank 1

 2025 12:18:58.345911  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2026 12:18:58.346048  ==

 2027 12:18:58.348970  RX Vref Scan: 0

 2028 12:18:58.349070  

 2029 12:18:58.349160  RX Vref 0 -> 0, step: 1

 2030 12:18:58.349251  

 2031 12:18:58.352177  RX Delay -79 -> 252, step: 8

 2032 12:18:58.358721  iDelay=209, Bit 0, Center 104 (9 ~ 200) 192

 2033 12:18:58.362621  iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200

 2034 12:18:58.365634  iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200

 2035 12:18:58.368970  iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200

 2036 12:18:58.372283  iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200

 2037 12:18:58.375530  iDelay=209, Bit 5, Center 112 (17 ~ 208) 192

 2038 12:18:58.382576  iDelay=209, Bit 6, Center 108 (9 ~ 208) 200

 2039 12:18:58.385705  iDelay=209, Bit 7, Center 92 (-7 ~ 192) 200

 2040 12:18:58.388903  iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208

 2041 12:18:58.392519  iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208

 2042 12:18:58.395482  iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216

 2043 12:18:58.402192  iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208

 2044 12:18:58.405975  iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216

 2045 12:18:58.409059  iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208

 2046 12:18:58.412268  iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208

 2047 12:18:58.415925  iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208

 2048 12:18:58.416034  ==

 2049 12:18:58.418922  Dram Type= 6, Freq= 0, CH_1, rank 1

 2050 12:18:58.425481  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2051 12:18:58.425562  ==

 2052 12:18:58.425627  DQS Delay:

 2053 12:18:58.429056  DQS0 = 0, DQS1 = 0

 2054 12:18:58.429203  DQM Delay:

 2055 12:18:58.429293  DQM0 = 97, DQM1 = 91

 2056 12:18:58.432161  DQ Delay:

 2057 12:18:58.435999  DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92

 2058 12:18:58.439154  DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =92

 2059 12:18:58.442257  DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88

 2060 12:18:58.445952  DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96

 2061 12:18:58.446058  

 2062 12:18:58.446152  

 2063 12:18:58.452341  [DQSOSCAuto] RK1, (LSB)MR18= 0x4710, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps

 2064 12:18:58.455918  CH1 RK1: MR19=606, MR18=4710

 2065 12:18:58.462581  CH1_RK1: MR19=0x606, MR18=0x4710, DQSOSC=392, MR23=63, INC=96, DEC=64

 2066 12:18:58.465863  [RxdqsGatingPostProcess] freq 800

 2067 12:18:58.469102  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2068 12:18:58.472194  Pre-setting of DQS Precalculation

 2069 12:18:58.479134  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2070 12:18:58.485869  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2071 12:18:58.492277  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2072 12:18:58.492389  

 2073 12:18:58.492482  

 2074 12:18:58.495410  [Calibration Summary] 1600 Mbps

 2075 12:18:58.495519  CH 0, Rank 0

 2076 12:18:58.499013  SW Impedance     : PASS

 2077 12:18:58.502035  DUTY Scan        : NO K

 2078 12:18:58.502140  ZQ Calibration   : PASS

 2079 12:18:58.505701  Jitter Meter     : NO K

 2080 12:18:58.509246  CBT Training     : PASS

 2081 12:18:58.509363  Write leveling   : PASS

 2082 12:18:58.512183  RX DQS gating    : PASS

 2083 12:18:58.515945  RX DQ/DQS(RDDQC) : PASS

 2084 12:18:58.516047  TX DQ/DQS        : PASS

 2085 12:18:58.519288  RX DATLAT        : PASS

 2086 12:18:58.522368  RX DQ/DQS(Engine): PASS

 2087 12:18:58.522470  TX OE            : NO K

 2088 12:18:58.525928  All Pass.

 2089 12:18:58.526027  

 2090 12:18:58.526120  CH 0, Rank 1

 2091 12:18:58.529074  SW Impedance     : PASS

 2092 12:18:58.529174  DUTY Scan        : NO K

 2093 12:18:58.532262  ZQ Calibration   : PASS

 2094 12:18:58.532361  Jitter Meter     : NO K

 2095 12:18:58.536014  CBT Training     : PASS

 2096 12:18:58.538896  Write leveling   : PASS

 2097 12:18:58.538998  RX DQS gating    : PASS

 2098 12:18:58.542428  RX DQ/DQS(RDDQC) : PASS

 2099 12:18:58.545512  TX DQ/DQS        : PASS

 2100 12:18:58.545624  RX DATLAT        : PASS

 2101 12:18:58.549178  RX DQ/DQS(Engine): PASS

 2102 12:18:58.552460  TX OE            : NO K

 2103 12:18:58.552536  All Pass.

 2104 12:18:58.552611  

 2105 12:18:58.552702  CH 1, Rank 0

 2106 12:18:58.555549  SW Impedance     : PASS

 2107 12:18:58.559402  DUTY Scan        : NO K

 2108 12:18:58.559498  ZQ Calibration   : PASS

 2109 12:18:58.562387  Jitter Meter     : NO K

 2110 12:18:58.565467  CBT Training     : PASS

 2111 12:18:58.565605  Write leveling   : PASS

 2112 12:18:58.569191  RX DQS gating    : PASS

 2113 12:18:58.572305  RX DQ/DQS(RDDQC) : PASS

 2114 12:18:58.572403  TX DQ/DQS        : PASS

 2115 12:18:58.575476  RX DATLAT        : PASS

 2116 12:18:58.575574  RX DQ/DQS(Engine): PASS

 2117 12:18:58.579218  TX OE            : NO K

 2118 12:18:58.579289  All Pass.

 2119 12:18:58.579349  

 2120 12:18:58.582239  CH 1, Rank 1

 2121 12:18:58.582338  SW Impedance     : PASS

 2122 12:18:58.586068  DUTY Scan        : NO K

 2123 12:18:58.588990  ZQ Calibration   : PASS

 2124 12:18:58.589058  Jitter Meter     : NO K

 2125 12:18:58.592507  CBT Training     : PASS

 2126 12:18:58.596117  Write leveling   : PASS

 2127 12:18:58.596210  RX DQS gating    : PASS

 2128 12:18:58.599442  RX DQ/DQS(RDDQC) : PASS

 2129 12:18:58.602641  TX DQ/DQS        : PASS

 2130 12:18:58.602756  RX DATLAT        : PASS

 2131 12:18:58.606182  RX DQ/DQS(Engine): PASS

 2132 12:18:58.606302  TX OE            : NO K

 2133 12:18:58.609366  All Pass.

 2134 12:18:58.609451  

 2135 12:18:58.609517  DramC Write-DBI off

 2136 12:18:58.612541  	PER_BANK_REFRESH: Hybrid Mode

 2137 12:18:58.616045  TX_TRACKING: ON

 2138 12:18:58.619544  [GetDramInforAfterCalByMRR] Vendor 6.

 2139 12:18:58.622614  [GetDramInforAfterCalByMRR] Revision 606.

 2140 12:18:58.625775  [GetDramInforAfterCalByMRR] Revision 2 0.

 2141 12:18:58.625866  MR0 0x3b3b

 2142 12:18:58.625938  MR8 0x5151

 2143 12:18:58.632988  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2144 12:18:58.633069  

 2145 12:18:58.633133  MR0 0x3b3b

 2146 12:18:58.633195  MR8 0x5151

 2147 12:18:58.636218  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2148 12:18:58.636302  

 2149 12:18:58.646319  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2150 12:18:58.649268  [FAST_K] Save calibration result to emmc

 2151 12:18:58.652739  [FAST_K] Save calibration result to emmc

 2152 12:18:58.656419  dram_init: config_dvfs: 1

 2153 12:18:58.659564  dramc_set_vcore_voltage set vcore to 662500

 2154 12:18:58.662811  Read voltage for 1200, 2

 2155 12:18:58.662889  Vio18 = 0

 2156 12:18:58.662955  Vcore = 662500

 2157 12:18:58.666240  Vdram = 0

 2158 12:18:58.666323  Vddq = 0

 2159 12:18:58.666389  Vmddr = 0

 2160 12:18:58.673196  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2161 12:18:58.676174  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2162 12:18:58.679377  MEM_TYPE=3, freq_sel=15

 2163 12:18:58.683241  sv_algorithm_assistance_LP4_1600 

 2164 12:18:58.686275  ============ PULL DRAM RESETB DOWN ============

 2165 12:18:58.689420  ========== PULL DRAM RESETB DOWN end =========

 2166 12:18:58.696187  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2167 12:18:58.699419  =================================== 

 2168 12:18:58.699523  LPDDR4 DRAM CONFIGURATION

 2169 12:18:58.703139  =================================== 

 2170 12:18:58.706376  EX_ROW_EN[0]    = 0x0

 2171 12:18:58.709525  EX_ROW_EN[1]    = 0x0

 2172 12:18:58.709635  LP4Y_EN      = 0x0

 2173 12:18:58.713031  WORK_FSP     = 0x0

 2174 12:18:58.713117  WL           = 0x4

 2175 12:18:58.716429  RL           = 0x4

 2176 12:18:58.716514  BL           = 0x2

 2177 12:18:58.719609  RPST         = 0x0

 2178 12:18:58.719699  RD_PRE       = 0x0

 2179 12:18:58.722736  WR_PRE       = 0x1

 2180 12:18:58.722820  WR_PST       = 0x0

 2181 12:18:58.726587  DBI_WR       = 0x0

 2182 12:18:58.726676  DBI_RD       = 0x0

 2183 12:18:58.729642  OTF          = 0x1

 2184 12:18:58.732865  =================================== 

 2185 12:18:58.736751  =================================== 

 2186 12:18:58.736831  ANA top config

 2187 12:18:58.739512  =================================== 

 2188 12:18:58.742955  DLL_ASYNC_EN            =  0

 2189 12:18:58.746271  ALL_SLAVE_EN            =  0

 2190 12:18:58.749720  NEW_RANK_MODE           =  1

 2191 12:18:58.749796  DLL_IDLE_MODE           =  1

 2192 12:18:58.752871  LP45_APHY_COMB_EN       =  1

 2193 12:18:58.756534  TX_ODT_DIS              =  1

 2194 12:18:58.759428  NEW_8X_MODE             =  1

 2195 12:18:58.762896  =================================== 

 2196 12:18:58.766630  =================================== 

 2197 12:18:58.766706  data_rate                  = 2400

 2198 12:18:58.769748  CKR                        = 1

 2199 12:18:58.772845  DQ_P2S_RATIO               = 8

 2200 12:18:58.776599  =================================== 

 2201 12:18:58.779690  CA_P2S_RATIO               = 8

 2202 12:18:58.783523  DQ_CA_OPEN                 = 0

 2203 12:18:58.786606  DQ_SEMI_OPEN               = 0

 2204 12:18:58.786722  CA_SEMI_OPEN               = 0

 2205 12:18:58.789830  CA_FULL_RATE               = 0

 2206 12:18:58.792904  DQ_CKDIV4_EN               = 0

 2207 12:18:58.796583  CA_CKDIV4_EN               = 0

 2208 12:18:58.800168  CA_PREDIV_EN               = 0

 2209 12:18:58.803390  PH8_DLY                    = 17

 2210 12:18:58.803474  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2211 12:18:58.806542  DQ_AAMCK_DIV               = 4

 2212 12:18:58.809673  CA_AAMCK_DIV               = 4

 2213 12:18:58.813503  CA_ADMCK_DIV               = 4

 2214 12:18:58.816632  DQ_TRACK_CA_EN             = 0

 2215 12:18:58.819924  CA_PICK                    = 1200

 2216 12:18:58.820009  CA_MCKIO                   = 1200

 2217 12:18:58.823661  MCKIO_SEMI                 = 0

 2218 12:18:58.826725  PLL_FREQ                   = 2366

 2219 12:18:58.830446  DQ_UI_PI_RATIO             = 32

 2220 12:18:58.833548  CA_UI_PI_RATIO             = 0

 2221 12:18:58.836360  =================================== 

 2222 12:18:58.840116  =================================== 

 2223 12:18:58.843180  memory_type:LPDDR4         

 2224 12:18:58.843281  GP_NUM     : 10       

 2225 12:18:58.846924  SRAM_EN    : 1       

 2226 12:18:58.847032  MD32_EN    : 0       

 2227 12:18:58.850222  =================================== 

 2228 12:18:58.853459  [ANA_INIT] >>>>>>>>>>>>>> 

 2229 12:18:58.856901  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2230 12:18:58.859977  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2231 12:18:58.863420  =================================== 

 2232 12:18:58.866777  data_rate = 2400,PCW = 0X5b00

 2233 12:18:58.870279  =================================== 

 2234 12:18:58.873570  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2235 12:18:58.876866  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2236 12:18:58.883288  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2237 12:18:58.889965  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2238 12:18:58.893627  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2239 12:18:58.896870  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2240 12:18:58.896979  [ANA_INIT] flow start 

 2241 12:18:58.899964  [ANA_INIT] PLL >>>>>>>> 

 2242 12:18:58.903550  [ANA_INIT] PLL <<<<<<<< 

 2243 12:18:58.903675  [ANA_INIT] MIDPI >>>>>>>> 

 2244 12:18:58.906708  [ANA_INIT] MIDPI <<<<<<<< 

 2245 12:18:58.909871  [ANA_INIT] DLL >>>>>>>> 

 2246 12:18:58.909948  [ANA_INIT] DLL <<<<<<<< 

 2247 12:18:58.913664  [ANA_INIT] flow end 

 2248 12:18:58.916925  ============ LP4 DIFF to SE enter ============

 2249 12:18:58.920100  ============ LP4 DIFF to SE exit  ============

 2250 12:18:58.923190  [ANA_INIT] <<<<<<<<<<<<< 

 2251 12:18:58.926999  [Flow] Enable top DCM control >>>>> 

 2252 12:18:58.930109  [Flow] Enable top DCM control <<<<< 

 2253 12:18:58.933352  Enable DLL master slave shuffle 

 2254 12:18:58.940443  ============================================================== 

 2255 12:18:58.940526  Gating Mode config

 2256 12:18:58.946947  ============================================================== 

 2257 12:18:58.947070  Config description: 

 2258 12:18:58.956807  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2259 12:18:58.963660  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2260 12:18:58.970310  SELPH_MODE            0: By rank         1: By Phase 

 2261 12:18:58.973446  ============================================================== 

 2262 12:18:58.977134  GAT_TRACK_EN                 =  1

 2263 12:18:58.980166  RX_GATING_MODE               =  2

 2264 12:18:58.983501  RX_GATING_TRACK_MODE         =  2

 2265 12:18:58.987097  SELPH_MODE                   =  1

 2266 12:18:58.990421  PICG_EARLY_EN                =  1

 2267 12:18:58.993988  VALID_LAT_VALUE              =  1

 2268 12:18:58.997377  ============================================================== 

 2269 12:18:59.000083  Enter into Gating configuration >>>> 

 2270 12:18:59.003731  Exit from Gating configuration <<<< 

 2271 12:18:59.007090  Enter into  DVFS_PRE_config >>>>> 

 2272 12:18:59.020058  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2273 12:18:59.020152  Exit from  DVFS_PRE_config <<<<< 

 2274 12:18:59.023818  Enter into PICG configuration >>>> 

 2275 12:18:59.026936  Exit from PICG configuration <<<< 

 2276 12:18:59.030763  [RX_INPUT] configuration >>>>> 

 2277 12:18:59.034084  [RX_INPUT] configuration <<<<< 

 2278 12:18:59.040483  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2279 12:18:59.044040  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2280 12:18:59.050255  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2281 12:18:59.057366  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2282 12:18:59.064013  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2283 12:18:59.070742  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2284 12:18:59.073862  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2285 12:18:59.077660  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2286 12:18:59.080791  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2287 12:18:59.083860  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2288 12:18:59.090536  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2289 12:18:59.094174  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2290 12:18:59.097056  =================================== 

 2291 12:18:59.100875  LPDDR4 DRAM CONFIGURATION

 2292 12:18:59.104139  =================================== 

 2293 12:18:59.104223  EX_ROW_EN[0]    = 0x0

 2294 12:18:59.107100  EX_ROW_EN[1]    = 0x0

 2295 12:18:59.107226  LP4Y_EN      = 0x0

 2296 12:18:59.110817  WORK_FSP     = 0x0

 2297 12:18:59.110892  WL           = 0x4

 2298 12:18:59.114049  RL           = 0x4

 2299 12:18:59.114132  BL           = 0x2

 2300 12:18:59.117016  RPST         = 0x0

 2301 12:18:59.117099  RD_PRE       = 0x0

 2302 12:18:59.120606  WR_PRE       = 0x1

 2303 12:18:59.123954  WR_PST       = 0x0

 2304 12:18:59.124036  DBI_WR       = 0x0

 2305 12:18:59.127163  DBI_RD       = 0x0

 2306 12:18:59.127256  OTF          = 0x1

 2307 12:18:59.130860  =================================== 

 2308 12:18:59.134103  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2309 12:18:59.137185  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2310 12:18:59.144199  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2311 12:18:59.147295  =================================== 

 2312 12:18:59.147424  LPDDR4 DRAM CONFIGURATION

 2313 12:18:59.151070  =================================== 

 2314 12:18:59.154190  EX_ROW_EN[0]    = 0x10

 2315 12:18:59.158152  EX_ROW_EN[1]    = 0x0

 2316 12:18:59.158239  LP4Y_EN      = 0x0

 2317 12:18:59.160868  WORK_FSP     = 0x0

 2318 12:18:59.160968  WL           = 0x4

 2319 12:18:59.164343  RL           = 0x4

 2320 12:18:59.164447  BL           = 0x2

 2321 12:18:59.167309  RPST         = 0x0

 2322 12:18:59.167413  RD_PRE       = 0x0

 2323 12:18:59.170521  WR_PRE       = 0x1

 2324 12:18:59.170612  WR_PST       = 0x0

 2325 12:18:59.174087  DBI_WR       = 0x0

 2326 12:18:59.174197  DBI_RD       = 0x0

 2327 12:18:59.177343  OTF          = 0x1

 2328 12:18:59.180996  =================================== 

 2329 12:18:59.187266  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2330 12:18:59.187397  ==

 2331 12:18:59.190982  Dram Type= 6, Freq= 0, CH_0, rank 0

 2332 12:18:59.194158  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2333 12:18:59.194262  ==

 2334 12:18:59.197642  [Duty_Offset_Calibration]

 2335 12:18:59.197743  	B0:2	B1:1	CA:1

 2336 12:18:59.197835  

 2337 12:18:59.200577  [DutyScan_Calibration_Flow] k_type=0

 2338 12:18:59.211035  

 2339 12:18:59.211153  ==CLK 0==

 2340 12:18:59.214821  Final CLK duty delay cell = 0

 2341 12:18:59.217928  [0] MAX Duty = 5187%(X100), DQS PI = 24

 2342 12:18:59.221110  [0] MIN Duty = 4844%(X100), DQS PI = 48

 2343 12:18:59.221192  [0] AVG Duty = 5015%(X100)

 2344 12:18:59.221258  

 2345 12:18:59.224383  CH0 CLK Duty spec in!! Max-Min= 343%

 2346 12:18:59.231433  [DutyScan_Calibration_Flow] ====Done====

 2347 12:18:59.231519  

 2348 12:18:59.234576  [DutyScan_Calibration_Flow] k_type=1

 2349 12:18:59.249908  

 2350 12:18:59.250044  ==DQS 0 ==

 2351 12:18:59.253113  Final DQS duty delay cell = -4

 2352 12:18:59.256440  [-4] MAX Duty = 5124%(X100), DQS PI = 22

 2353 12:18:59.259545  [-4] MIN Duty = 4782%(X100), DQS PI = 0

 2354 12:18:59.263395  [-4] AVG Duty = 4953%(X100)

 2355 12:18:59.263507  

 2356 12:18:59.263599  ==DQS 1 ==

 2357 12:18:59.266314  Final DQS duty delay cell = 0

 2358 12:18:59.269669  [0] MAX Duty = 5156%(X100), DQS PI = 0

 2359 12:18:59.273033  [0] MIN Duty = 5000%(X100), DQS PI = 34

 2360 12:18:59.276522  [0] AVG Duty = 5078%(X100)

 2361 12:18:59.276605  

 2362 12:18:59.279902  CH0 DQS 0 Duty spec in!! Max-Min= 342%

 2363 12:18:59.279988  

 2364 12:18:59.282786  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 2365 12:18:59.286481  [DutyScan_Calibration_Flow] ====Done====

 2366 12:18:59.286565  

 2367 12:18:59.289557  [DutyScan_Calibration_Flow] k_type=3

 2368 12:18:59.306552  

 2369 12:18:59.306638  ==DQM 0 ==

 2370 12:18:59.309611  Final DQM duty delay cell = 0

 2371 12:18:59.313063  [0] MAX Duty = 5156%(X100), DQS PI = 28

 2372 12:18:59.316477  [0] MIN Duty = 4875%(X100), DQS PI = 58

 2373 12:18:59.316587  [0] AVG Duty = 5015%(X100)

 2374 12:18:59.319714  

 2375 12:18:59.319790  ==DQM 1 ==

 2376 12:18:59.322761  Final DQM duty delay cell = 0

 2377 12:18:59.326630  [0] MAX Duty = 5124%(X100), DQS PI = 8

 2378 12:18:59.329803  [0] MIN Duty = 5031%(X100), DQS PI = 18

 2379 12:18:59.329879  [0] AVG Duty = 5077%(X100)

 2380 12:18:59.332996  

 2381 12:18:59.336163  CH0 DQM 0 Duty spec in!! Max-Min= 281%

 2382 12:18:59.336265  

 2383 12:18:59.339915  CH0 DQM 1 Duty spec in!! Max-Min= 93%

 2384 12:18:59.343032  [DutyScan_Calibration_Flow] ====Done====

 2385 12:18:59.343154  

 2386 12:18:59.346226  [DutyScan_Calibration_Flow] k_type=2

 2387 12:18:59.362767  

 2388 12:18:59.362881  ==DQ 0 ==

 2389 12:18:59.366223  Final DQ duty delay cell = 0

 2390 12:18:59.369224  [0] MAX Duty = 5031%(X100), DQS PI = 24

 2391 12:18:59.372943  [0] MIN Duty = 4906%(X100), DQS PI = 0

 2392 12:18:59.373031  [0] AVG Duty = 4968%(X100)

 2393 12:18:59.373095  

 2394 12:18:59.375864  ==DQ 1 ==

 2395 12:18:59.379466  Final DQ duty delay cell = 0

 2396 12:18:59.383009  [0] MAX Duty = 5093%(X100), DQS PI = 24

 2397 12:18:59.385960  [0] MIN Duty = 4907%(X100), DQS PI = 36

 2398 12:18:59.386036  [0] AVG Duty = 5000%(X100)

 2399 12:18:59.386115  

 2400 12:18:59.389303  CH0 DQ 0 Duty spec in!! Max-Min= 125%

 2401 12:18:59.389415  

 2402 12:18:59.393029  CH0 DQ 1 Duty spec in!! Max-Min= 186%

 2403 12:18:59.399840  [DutyScan_Calibration_Flow] ====Done====

 2404 12:18:59.399950  ==

 2405 12:18:59.402933  Dram Type= 6, Freq= 0, CH_1, rank 0

 2406 12:18:59.406162  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2407 12:18:59.406241  ==

 2408 12:18:59.409746  [Duty_Offset_Calibration]

 2409 12:18:59.409822  	B0:1	B1:0	CA:0

 2410 12:18:59.409884  

 2411 12:18:59.412815  [DutyScan_Calibration_Flow] k_type=0

 2412 12:18:59.422249  

 2413 12:18:59.422335  ==CLK 0==

 2414 12:18:59.425501  Final CLK duty delay cell = -4

 2415 12:18:59.428380  [-4] MAX Duty = 5031%(X100), DQS PI = 22

 2416 12:18:59.432161  [-4] MIN Duty = 4907%(X100), DQS PI = 12

 2417 12:18:59.435200  [-4] AVG Duty = 4969%(X100)

 2418 12:18:59.435300  

 2419 12:18:59.438466  CH1 CLK Duty spec in!! Max-Min= 124%

 2420 12:18:59.442347  [DutyScan_Calibration_Flow] ====Done====

 2421 12:18:59.442423  

 2422 12:18:59.445466  [DutyScan_Calibration_Flow] k_type=1

 2423 12:18:59.461628  

 2424 12:18:59.461740  ==DQS 0 ==

 2425 12:18:59.465415  Final DQS duty delay cell = 0

 2426 12:18:59.468336  [0] MAX Duty = 5094%(X100), DQS PI = 26

 2427 12:18:59.471972  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2428 12:18:59.472056  [0] AVG Duty = 4984%(X100)

 2429 12:18:59.475431  

 2430 12:18:59.475540  ==DQS 1 ==

 2431 12:18:59.478794  Final DQS duty delay cell = 0

 2432 12:18:59.482117  [0] MAX Duty = 5218%(X100), DQS PI = 18

 2433 12:18:59.485450  [0] MIN Duty = 4969%(X100), DQS PI = 10

 2434 12:18:59.485536  [0] AVG Duty = 5093%(X100)

 2435 12:18:59.488956  

 2436 12:18:59.492044  CH1 DQS 0 Duty spec in!! Max-Min= 219%

 2437 12:18:59.492155  

 2438 12:18:59.495609  CH1 DQS 1 Duty spec in!! Max-Min= 249%

 2439 12:18:59.498564  [DutyScan_Calibration_Flow] ====Done====

 2440 12:18:59.498640  

 2441 12:18:59.501863  [DutyScan_Calibration_Flow] k_type=3

 2442 12:18:59.518219  

 2443 12:18:59.518323  ==DQM 0 ==

 2444 12:18:59.521913  Final DQM duty delay cell = 0

 2445 12:18:59.525366  [0] MAX Duty = 5156%(X100), DQS PI = 6

 2446 12:18:59.528382  [0] MIN Duty = 5031%(X100), DQS PI = 0

 2447 12:18:59.528457  [0] AVG Duty = 5093%(X100)

 2448 12:18:59.528524  

 2449 12:18:59.532155  ==DQM 1 ==

 2450 12:18:59.534955  Final DQM duty delay cell = 0

 2451 12:18:59.538321  [0] MAX Duty = 5031%(X100), DQS PI = 18

 2452 12:18:59.541646  [0] MIN Duty = 4907%(X100), DQS PI = 36

 2453 12:18:59.541743  [0] AVG Duty = 4969%(X100)

 2454 12:18:59.545352  

 2455 12:18:59.548596  CH1 DQM 0 Duty spec in!! Max-Min= 125%

 2456 12:18:59.548672  

 2457 12:18:59.551743  CH1 DQM 1 Duty spec in!! Max-Min= 124%

 2458 12:18:59.554816  [DutyScan_Calibration_Flow] ====Done====

 2459 12:18:59.554885  

 2460 12:18:59.558486  [DutyScan_Calibration_Flow] k_type=2

 2461 12:18:59.574033  

 2462 12:18:59.574131  ==DQ 0 ==

 2463 12:18:59.577338  Final DQ duty delay cell = -4

 2464 12:18:59.581133  [-4] MAX Duty = 5062%(X100), DQS PI = 8

 2465 12:18:59.584315  [-4] MIN Duty = 4938%(X100), DQS PI = 0

 2466 12:18:59.587412  [-4] AVG Duty = 5000%(X100)

 2467 12:18:59.587521  

 2468 12:18:59.587614  ==DQ 1 ==

 2469 12:18:59.590795  Final DQ duty delay cell = 0

 2470 12:18:59.594149  [0] MAX Duty = 5125%(X100), DQS PI = 20

 2471 12:18:59.597326  [0] MIN Duty = 4938%(X100), DQS PI = 34

 2472 12:18:59.597462  [0] AVG Duty = 5031%(X100)

 2473 12:18:59.600928  

 2474 12:18:59.603974  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 2475 12:18:59.604058  

 2476 12:18:59.607580  CH1 DQ 1 Duty spec in!! Max-Min= 187%

 2477 12:18:59.611026  [DutyScan_Calibration_Flow] ====Done====

 2478 12:18:59.614504  nWR fixed to 30

 2479 12:18:59.614582  [ModeRegInit_LP4] CH0 RK0

 2480 12:18:59.617789  [ModeRegInit_LP4] CH0 RK1

 2481 12:18:59.620596  [ModeRegInit_LP4] CH1 RK0

 2482 12:18:59.624262  [ModeRegInit_LP4] CH1 RK1

 2483 12:18:59.624342  match AC timing 7

 2484 12:18:59.627284  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2485 12:18:59.634246  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2486 12:18:59.637295  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2487 12:18:59.644215  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2488 12:18:59.647357  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2489 12:18:59.647442  ==

 2490 12:18:59.650770  Dram Type= 6, Freq= 0, CH_0, rank 0

 2491 12:18:59.654286  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2492 12:18:59.654374  ==

 2493 12:18:59.661022  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2494 12:18:59.664295  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2495 12:18:59.674234  [CA 0] Center 39 (8~70) winsize 63

 2496 12:18:59.677956  [CA 1] Center 39 (8~70) winsize 63

 2497 12:18:59.681519  [CA 2] Center 35 (5~66) winsize 62

 2498 12:18:59.684701  [CA 3] Center 34 (4~65) winsize 62

 2499 12:18:59.687958  [CA 4] Center 33 (3~64) winsize 62

 2500 12:18:59.691001  [CA 5] Center 32 (3~62) winsize 60

 2501 12:18:59.691085  

 2502 12:18:59.694164  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 2503 12:18:59.694247  

 2504 12:18:59.697937  [CATrainingPosCal] consider 1 rank data

 2505 12:18:59.701336  u2DelayCellTimex100 = 270/100 ps

 2506 12:18:59.704317  CA0 delay=39 (8~70),Diff = 7 PI (33 cell)

 2507 12:18:59.707642  CA1 delay=39 (8~70),Diff = 7 PI (33 cell)

 2508 12:18:59.714400  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2509 12:18:59.718030  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2510 12:18:59.720869  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2511 12:18:59.724692  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2512 12:18:59.724778  

 2513 12:18:59.727703  CA PerBit enable=1, Macro0, CA PI delay=32

 2514 12:18:59.727788  

 2515 12:18:59.730936  [CBTSetCACLKResult] CA Dly = 32

 2516 12:18:59.731020  CS Dly: 6 (0~37)

 2517 12:18:59.731085  ==

 2518 12:18:59.734368  Dram Type= 6, Freq= 0, CH_0, rank 1

 2519 12:18:59.741431  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2520 12:18:59.741557  ==

 2521 12:18:59.744715  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2522 12:18:59.751534  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2523 12:18:59.759976  [CA 0] Center 38 (8~69) winsize 62

 2524 12:18:59.763462  [CA 1] Center 38 (8~69) winsize 62

 2525 12:18:59.766828  [CA 2] Center 35 (4~66) winsize 63

 2526 12:18:59.769897  [CA 3] Center 34 (4~65) winsize 62

 2527 12:18:59.773839  [CA 4] Center 33 (3~64) winsize 62

 2528 12:18:59.776726  [CA 5] Center 32 (2~62) winsize 61

 2529 12:18:59.776821  

 2530 12:18:59.780129  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2531 12:18:59.780215  

 2532 12:18:59.783389  [CATrainingPosCal] consider 2 rank data

 2533 12:18:59.786876  u2DelayCellTimex100 = 270/100 ps

 2534 12:18:59.790008  CA0 delay=38 (8~69),Diff = 6 PI (28 cell)

 2535 12:18:59.793696  CA1 delay=38 (8~69),Diff = 6 PI (28 cell)

 2536 12:18:59.800223  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2537 12:18:59.803370  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2538 12:18:59.807085  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2539 12:18:59.810299  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2540 12:18:59.810381  

 2541 12:18:59.813427  CA PerBit enable=1, Macro0, CA PI delay=32

 2542 12:18:59.813534  

 2543 12:18:59.816677  [CBTSetCACLKResult] CA Dly = 32

 2544 12:18:59.816753  CS Dly: 6 (0~38)

 2545 12:18:59.816817  

 2546 12:18:59.820316  ----->DramcWriteLeveling(PI) begin...

 2547 12:18:59.823863  ==

 2548 12:18:59.823943  Dram Type= 6, Freq= 0, CH_0, rank 0

 2549 12:18:59.830234  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2550 12:18:59.830315  ==

 2551 12:18:59.833351  Write leveling (Byte 0): 33 => 33

 2552 12:18:59.836706  Write leveling (Byte 1): 29 => 29

 2553 12:18:59.836787  DramcWriteLeveling(PI) end<-----

 2554 12:18:59.840306  

 2555 12:18:59.840390  ==

 2556 12:18:59.843587  Dram Type= 6, Freq= 0, CH_0, rank 0

 2557 12:18:59.847036  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2558 12:18:59.847121  ==

 2559 12:18:59.850446  [Gating] SW mode calibration

 2560 12:18:59.856744  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2561 12:18:59.860423  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2562 12:18:59.867320   0 15  0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)

 2563 12:18:59.870236   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2564 12:18:59.873840   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2565 12:18:59.880360   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2566 12:18:59.883609   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2567 12:18:59.887410   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2568 12:18:59.893617   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 2569 12:18:59.897356   0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)

 2570 12:18:59.900497   1  0  0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)

 2571 12:18:59.907517   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2572 12:18:59.910761   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2573 12:18:59.913935   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2574 12:18:59.917129   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2575 12:18:59.923987   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2576 12:18:59.927070   1  0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)

 2577 12:18:59.930836   1  0 28 | B1->B0 | 2525 4444 | 0 0 | (1 1) (0 0)

 2578 12:18:59.937543   1  1  0 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)

 2579 12:18:59.940548   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2580 12:18:59.943954   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2581 12:18:59.950675   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2582 12:18:59.953649   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2583 12:18:59.957389   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2584 12:18:59.964132   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2585 12:18:59.967002   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2586 12:18:59.970425   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2587 12:18:59.977467   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2588 12:18:59.980873   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2589 12:18:59.983739   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2590 12:18:59.990350   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2591 12:18:59.993730   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2592 12:18:59.997357   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2593 12:19:00.000853   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2594 12:19:00.007210   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2595 12:19:00.010462   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2596 12:19:00.014335   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2597 12:19:00.020632   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2598 12:19:00.023891   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2599 12:19:00.027122   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2600 12:19:00.033999   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2601 12:19:00.037178   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2602 12:19:00.040727   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2603 12:19:00.044069  Total UI for P1: 0, mck2ui 16

 2604 12:19:00.047490  best dqsien dly found for B0: ( 1,  3, 28)

 2605 12:19:00.050628  Total UI for P1: 0, mck2ui 16

 2606 12:19:00.054165  best dqsien dly found for B1: ( 1,  3, 30)

 2607 12:19:00.057598  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 2608 12:19:00.060934  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2609 12:19:00.061023  

 2610 12:19:00.064349  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2611 12:19:00.070489  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2612 12:19:00.070579  [Gating] SW calibration Done

 2613 12:19:00.074378  ==

 2614 12:19:00.074463  Dram Type= 6, Freq= 0, CH_0, rank 0

 2615 12:19:00.081137  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2616 12:19:00.081246  ==

 2617 12:19:00.081338  RX Vref Scan: 0

 2618 12:19:00.081420  

 2619 12:19:00.084037  RX Vref 0 -> 0, step: 1

 2620 12:19:00.084121  

 2621 12:19:00.087672  RX Delay -40 -> 252, step: 8

 2622 12:19:00.090665  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2623 12:19:00.094185  iDelay=200, Bit 1, Center 123 (48 ~ 199) 152

 2624 12:19:00.097463  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2625 12:19:00.104176  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2626 12:19:00.107501  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2627 12:19:00.110929  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2628 12:19:00.114393  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2629 12:19:00.117294  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2630 12:19:00.121071  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2631 12:19:00.128039  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 2632 12:19:00.131307  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2633 12:19:00.134396  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2634 12:19:00.137606  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2635 12:19:00.140786  iDelay=200, Bit 13, Center 123 (56 ~ 191) 136

 2636 12:19:00.147591  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2637 12:19:00.151127  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 2638 12:19:00.151204  ==

 2639 12:19:00.154249  Dram Type= 6, Freq= 0, CH_0, rank 0

 2640 12:19:00.157866  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2641 12:19:00.157946  ==

 2642 12:19:00.161036  DQS Delay:

 2643 12:19:00.161173  DQS0 = 0, DQS1 = 0

 2644 12:19:00.161247  DQM Delay:

 2645 12:19:00.164466  DQM0 = 121, DQM1 = 113

 2646 12:19:00.164566  DQ Delay:

 2647 12:19:00.167601  DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119

 2648 12:19:00.171258  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 2649 12:19:00.174716  DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107

 2650 12:19:00.181733  DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119

 2651 12:19:00.181827  

 2652 12:19:00.181900  

 2653 12:19:00.181962  ==

 2654 12:19:00.184452  Dram Type= 6, Freq= 0, CH_0, rank 0

 2655 12:19:00.188036  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2656 12:19:00.188118  ==

 2657 12:19:00.188210  

 2658 12:19:00.188314  

 2659 12:19:00.191222  	TX Vref Scan disable

 2660 12:19:00.191302   == TX Byte 0 ==

 2661 12:19:00.198096  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2662 12:19:00.201151  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2663 12:19:00.201233   == TX Byte 1 ==

 2664 12:19:00.208205  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2665 12:19:00.211556  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2666 12:19:00.211632  ==

 2667 12:19:00.214908  Dram Type= 6, Freq= 0, CH_0, rank 0

 2668 12:19:00.217692  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2669 12:19:00.217777  ==

 2670 12:19:00.230568  TX Vref=22, minBit 0, minWin=25, winSum=408

 2671 12:19:00.233815  TX Vref=24, minBit 0, minWin=25, winSum=407

 2672 12:19:00.237404  TX Vref=26, minBit 0, minWin=25, winSum=413

 2673 12:19:00.240685  TX Vref=28, minBit 0, minWin=26, winSum=422

 2674 12:19:00.243815  TX Vref=30, minBit 13, minWin=25, winSum=422

 2675 12:19:00.247562  TX Vref=32, minBit 0, minWin=26, winSum=420

 2676 12:19:00.253861  [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28

 2677 12:19:00.253962  

 2678 12:19:00.257591  Final TX Range 1 Vref 28

 2679 12:19:00.257674  

 2680 12:19:00.257740  ==

 2681 12:19:00.260756  Dram Type= 6, Freq= 0, CH_0, rank 0

 2682 12:19:00.263984  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2683 12:19:00.264063  ==

 2684 12:19:00.264132  

 2685 12:19:00.267535  

 2686 12:19:00.267615  	TX Vref Scan disable

 2687 12:19:00.270752   == TX Byte 0 ==

 2688 12:19:00.273896  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2689 12:19:00.277803  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2690 12:19:00.280955   == TX Byte 1 ==

 2691 12:19:00.283976  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 2692 12:19:00.287532  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 2693 12:19:00.287654  

 2694 12:19:00.290901  [DATLAT]

 2695 12:19:00.291004  Freq=1200, CH0 RK0

 2696 12:19:00.291110  

 2697 12:19:00.294143  DATLAT Default: 0xd

 2698 12:19:00.294248  0, 0xFFFF, sum = 0

 2699 12:19:00.297535  1, 0xFFFF, sum = 0

 2700 12:19:00.297650  2, 0xFFFF, sum = 0

 2701 12:19:00.300887  3, 0xFFFF, sum = 0

 2702 12:19:00.300971  4, 0xFFFF, sum = 0

 2703 12:19:00.304697  5, 0xFFFF, sum = 0

 2704 12:19:00.304814  6, 0xFFFF, sum = 0

 2705 12:19:00.307530  7, 0xFFFF, sum = 0

 2706 12:19:00.307648  8, 0xFFFF, sum = 0

 2707 12:19:00.310736  9, 0xFFFF, sum = 0

 2708 12:19:00.313801  10, 0xFFFF, sum = 0

 2709 12:19:00.313888  11, 0xFFFF, sum = 0

 2710 12:19:00.317407  12, 0x0, sum = 1

 2711 12:19:00.317492  13, 0x0, sum = 2

 2712 12:19:00.317559  14, 0x0, sum = 3

 2713 12:19:00.320998  15, 0x0, sum = 4

 2714 12:19:00.321109  best_step = 13

 2715 12:19:00.321202  

 2716 12:19:00.324063  ==

 2717 12:19:00.324149  Dram Type= 6, Freq= 0, CH_0, rank 0

 2718 12:19:00.331062  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2719 12:19:00.331150  ==

 2720 12:19:00.331215  RX Vref Scan: 1

 2721 12:19:00.331276  

 2722 12:19:00.334214  Set Vref Range= 32 -> 127

 2723 12:19:00.334312  

 2724 12:19:00.337231  RX Vref 32 -> 127, step: 1

 2725 12:19:00.337313  

 2726 12:19:00.340734  RX Delay -13 -> 252, step: 4

 2727 12:19:00.340821  

 2728 12:19:00.344124  Set Vref, RX VrefLevel [Byte0]: 32

 2729 12:19:00.347312                           [Byte1]: 32

 2730 12:19:00.347396  

 2731 12:19:00.351006  Set Vref, RX VrefLevel [Byte0]: 33

 2732 12:19:00.354071                           [Byte1]: 33

 2733 12:19:00.354154  

 2734 12:19:00.357739  Set Vref, RX VrefLevel [Byte0]: 34

 2735 12:19:00.360756                           [Byte1]: 34

 2736 12:19:00.364657  

 2737 12:19:00.364740  Set Vref, RX VrefLevel [Byte0]: 35

 2738 12:19:00.368519                           [Byte1]: 35

 2739 12:19:00.372717  

 2740 12:19:00.372807  Set Vref, RX VrefLevel [Byte0]: 36

 2741 12:19:00.375767                           [Byte1]: 36

 2742 12:19:00.380300  

 2743 12:19:00.380379  Set Vref, RX VrefLevel [Byte0]: 37

 2744 12:19:00.384092                           [Byte1]: 37

 2745 12:19:00.388556  

 2746 12:19:00.388634  Set Vref, RX VrefLevel [Byte0]: 38

 2747 12:19:00.391664                           [Byte1]: 38

 2748 12:19:00.396699  

 2749 12:19:00.396784  Set Vref, RX VrefLevel [Byte0]: 39

 2750 12:19:00.399910                           [Byte1]: 39

 2751 12:19:00.404261  

 2752 12:19:00.404353  Set Vref, RX VrefLevel [Byte0]: 40

 2753 12:19:00.407356                           [Byte1]: 40

 2754 12:19:00.412097  

 2755 12:19:00.415349  Set Vref, RX VrefLevel [Byte0]: 41

 2756 12:19:00.415434                           [Byte1]: 41

 2757 12:19:00.420147  

 2758 12:19:00.420230  Set Vref, RX VrefLevel [Byte0]: 42

 2759 12:19:00.423050                           [Byte1]: 42

 2760 12:19:00.427819  

 2761 12:19:00.427901  Set Vref, RX VrefLevel [Byte0]: 43

 2762 12:19:00.430993                           [Byte1]: 43

 2763 12:19:00.435615  

 2764 12:19:00.435713  Set Vref, RX VrefLevel [Byte0]: 44

 2765 12:19:00.439121                           [Byte1]: 44

 2766 12:19:00.443485  

 2767 12:19:00.443594  Set Vref, RX VrefLevel [Byte0]: 45

 2768 12:19:00.446635                           [Byte1]: 45

 2769 12:19:00.451397  

 2770 12:19:00.451513  Set Vref, RX VrefLevel [Byte0]: 46

 2771 12:19:00.454730                           [Byte1]: 46

 2772 12:19:00.459507  

 2773 12:19:00.459626  Set Vref, RX VrefLevel [Byte0]: 47

 2774 12:19:00.462560                           [Byte1]: 47

 2775 12:19:00.466972  

 2776 12:19:00.467059  Set Vref, RX VrefLevel [Byte0]: 48

 2777 12:19:00.470682                           [Byte1]: 48

 2778 12:19:00.475061  

 2779 12:19:00.475145  Set Vref, RX VrefLevel [Byte0]: 49

 2780 12:19:00.478779                           [Byte1]: 49

 2781 12:19:00.483233  

 2782 12:19:00.483317  Set Vref, RX VrefLevel [Byte0]: 50

 2783 12:19:00.486420                           [Byte1]: 50

 2784 12:19:00.490814  

 2785 12:19:00.490897  Set Vref, RX VrefLevel [Byte0]: 51

 2786 12:19:00.494524                           [Byte1]: 51

 2787 12:19:00.498903  

 2788 12:19:00.498985  Set Vref, RX VrefLevel [Byte0]: 52

 2789 12:19:00.501985                           [Byte1]: 52

 2790 12:19:00.506986  

 2791 12:19:00.507069  Set Vref, RX VrefLevel [Byte0]: 53

 2792 12:19:00.510210                           [Byte1]: 53

 2793 12:19:00.514706  

 2794 12:19:00.514791  Set Vref, RX VrefLevel [Byte0]: 54

 2795 12:19:00.517840                           [Byte1]: 54

 2796 12:19:00.522870  

 2797 12:19:00.522953  Set Vref, RX VrefLevel [Byte0]: 55

 2798 12:19:00.525893                           [Byte1]: 55

 2799 12:19:00.530683  

 2800 12:19:00.530765  Set Vref, RX VrefLevel [Byte0]: 56

 2801 12:19:00.533936                           [Byte1]: 56

 2802 12:19:00.538657  

 2803 12:19:00.538749  Set Vref, RX VrefLevel [Byte0]: 57

 2804 12:19:00.541699                           [Byte1]: 57

 2805 12:19:00.546566  

 2806 12:19:00.546683  Set Vref, RX VrefLevel [Byte0]: 58

 2807 12:19:00.549899                           [Byte1]: 58

 2808 12:19:00.554229  

 2809 12:19:00.554323  Set Vref, RX VrefLevel [Byte0]: 59

 2810 12:19:00.557724                           [Byte1]: 59

 2811 12:19:00.561992  

 2812 12:19:00.562078  Set Vref, RX VrefLevel [Byte0]: 60

 2813 12:19:00.565550                           [Byte1]: 60

 2814 12:19:00.569633  

 2815 12:19:00.569718  Set Vref, RX VrefLevel [Byte0]: 61

 2816 12:19:00.573330                           [Byte1]: 61

 2817 12:19:00.577591  

 2818 12:19:00.577672  Set Vref, RX VrefLevel [Byte0]: 62

 2819 12:19:00.581142                           [Byte1]: 62

 2820 12:19:00.585449  

 2821 12:19:00.585532  Set Vref, RX VrefLevel [Byte0]: 63

 2822 12:19:00.589126                           [Byte1]: 63

 2823 12:19:00.593570  

 2824 12:19:00.593650  Set Vref, RX VrefLevel [Byte0]: 64

 2825 12:19:00.596640                           [Byte1]: 64

 2826 12:19:00.601231  

 2827 12:19:00.601317  Set Vref, RX VrefLevel [Byte0]: 65

 2828 12:19:00.604680                           [Byte1]: 65

 2829 12:19:00.609111  

 2830 12:19:00.612278  Set Vref, RX VrefLevel [Byte0]: 66

 2831 12:19:00.612362                           [Byte1]: 66

 2832 12:19:00.617186  

 2833 12:19:00.617269  Set Vref, RX VrefLevel [Byte0]: 67

 2834 12:19:00.620289                           [Byte1]: 67

 2835 12:19:00.624923  

 2836 12:19:00.625006  Set Vref, RX VrefLevel [Byte0]: 68

 2837 12:19:00.628630                           [Byte1]: 68

 2838 12:19:00.633026  

 2839 12:19:00.633110  Set Vref, RX VrefLevel [Byte0]: 69

 2840 12:19:00.636132                           [Byte1]: 69

 2841 12:19:00.640810  

 2842 12:19:00.640908  Final RX Vref Byte 0 = 55 to rank0

 2843 12:19:00.644317  Final RX Vref Byte 1 = 46 to rank0

 2844 12:19:00.647284  Final RX Vref Byte 0 = 55 to rank1

 2845 12:19:00.651022  Final RX Vref Byte 1 = 46 to rank1==

 2846 12:19:00.654225  Dram Type= 6, Freq= 0, CH_0, rank 0

 2847 12:19:00.660920  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2848 12:19:00.661007  ==

 2849 12:19:00.661074  DQS Delay:

 2850 12:19:00.661147  DQS0 = 0, DQS1 = 0

 2851 12:19:00.663976  DQM Delay:

 2852 12:19:00.664059  DQM0 = 120, DQM1 = 110

 2853 12:19:00.667650  DQ Delay:

 2854 12:19:00.671181  DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118

 2855 12:19:00.674021  DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126

 2856 12:19:00.677651  DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102

 2857 12:19:00.681061  DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118

 2858 12:19:00.681144  

 2859 12:19:00.681210  

 2860 12:19:00.687807  [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps

 2861 12:19:00.690602  CH0 RK0: MR19=404, MR18=130C

 2862 12:19:00.697699  CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27

 2863 12:19:00.697782  

 2864 12:19:00.701059  ----->DramcWriteLeveling(PI) begin...

 2865 12:19:00.701136  ==

 2866 12:19:00.704344  Dram Type= 6, Freq= 0, CH_0, rank 1

 2867 12:19:00.707915  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2868 12:19:00.708001  ==

 2869 12:19:00.711024  Write leveling (Byte 0): 33 => 33

 2870 12:19:00.714228  Write leveling (Byte 1): 28 => 28

 2871 12:19:00.717415  DramcWriteLeveling(PI) end<-----

 2872 12:19:00.717495  

 2873 12:19:00.717559  ==

 2874 12:19:00.721062  Dram Type= 6, Freq= 0, CH_0, rank 1

 2875 12:19:00.728087  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2876 12:19:00.728165  ==

 2877 12:19:00.728234  [Gating] SW mode calibration

 2878 12:19:00.737475  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2879 12:19:00.741289  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2880 12:19:00.744419   0 15  0 | B1->B0 | 3232 2e2e | 1 0 | (1 1) (0 0)

 2881 12:19:00.750834   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2882 12:19:00.754356   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2883 12:19:00.757966   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2884 12:19:00.764430   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2885 12:19:00.767539   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2886 12:19:00.771238   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2887 12:19:00.777918   0 15 28 | B1->B0 | 2e2e 2c2c | 0 0 | (1 0) (1 0)

 2888 12:19:00.781426   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 2889 12:19:00.784458   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2890 12:19:00.790913   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2891 12:19:00.794813   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2892 12:19:00.797890   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2893 12:19:00.801314   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2894 12:19:00.807861   1  0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 2895 12:19:00.811341   1  0 28 | B1->B0 | 3636 3939 | 0 1 | (0 0) (0 0)

 2896 12:19:00.814779   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2897 12:19:00.821420   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2898 12:19:00.824645   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2899 12:19:00.827790   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2900 12:19:00.834621   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2901 12:19:00.837787   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2902 12:19:00.841327   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 2903 12:19:00.847809   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2904 12:19:00.851530   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2905 12:19:00.854785   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2906 12:19:00.861238   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2907 12:19:00.864600   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2908 12:19:00.868201   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2909 12:19:00.874415   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2910 12:19:00.878261   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2911 12:19:00.881390   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2912 12:19:00.887933   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2913 12:19:00.891579   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2914 12:19:00.894513   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2915 12:19:00.898137   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2916 12:19:00.904799   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2917 12:19:00.907867   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2918 12:19:00.911484   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2919 12:19:00.918233   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 2920 12:19:00.921383   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2921 12:19:00.925065   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2922 12:19:00.928166  Total UI for P1: 0, mck2ui 16

 2923 12:19:00.931457  best dqsien dly found for B0: ( 1,  4,  0)

 2924 12:19:00.934840  Total UI for P1: 0, mck2ui 16

 2925 12:19:00.938255  best dqsien dly found for B1: ( 1,  3, 30)

 2926 12:19:00.941943  best DQS0 dly(MCK, UI, PI) = (1, 4, 0)

 2927 12:19:00.944985  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2928 12:19:00.945133  

 2929 12:19:00.948311  best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2930 12:19:00.955201  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2931 12:19:00.955349  [Gating] SW calibration Done

 2932 12:19:00.955460  ==

 2933 12:19:00.958338  Dram Type= 6, Freq= 0, CH_0, rank 1

 2934 12:19:00.965297  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2935 12:19:00.965379  ==

 2936 12:19:00.965441  RX Vref Scan: 0

 2937 12:19:00.965499  

 2938 12:19:00.968232  RX Vref 0 -> 0, step: 1

 2939 12:19:00.968333  

 2940 12:19:00.971737  RX Delay -40 -> 252, step: 8

 2941 12:19:00.975167  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2942 12:19:00.978644  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2943 12:19:00.981540  iDelay=200, Bit 2, Center 123 (56 ~ 191) 136

 2944 12:19:00.985057  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2945 12:19:00.992081  iDelay=200, Bit 4, Center 127 (56 ~ 199) 144

 2946 12:19:00.994933  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2947 12:19:00.998479  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2948 12:19:01.002059  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2949 12:19:01.005046  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2950 12:19:01.011943  iDelay=200, Bit 9, Center 103 (32 ~ 175) 144

 2951 12:19:01.015331  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2952 12:19:01.018305  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2953 12:19:01.022012  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2954 12:19:01.025137  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 2955 12:19:01.031991  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2956 12:19:01.035189  iDelay=200, Bit 15, Center 119 (56 ~ 183) 128

 2957 12:19:01.035272  ==

 2958 12:19:01.038317  Dram Type= 6, Freq= 0, CH_0, rank 1

 2959 12:19:01.042020  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2960 12:19:01.042103  ==

 2961 12:19:01.044854  DQS Delay:

 2962 12:19:01.044975  DQS0 = 0, DQS1 = 0

 2963 12:19:01.045068  DQM Delay:

 2964 12:19:01.048409  DQM0 = 122, DQM1 = 112

 2965 12:19:01.048506  DQ Delay:

 2966 12:19:01.051703  DQ0 =119, DQ1 =119, DQ2 =123, DQ3 =119

 2967 12:19:01.054895  DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127

 2968 12:19:01.058755  DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107

 2969 12:19:01.064996  DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119

 2970 12:19:01.065091  

 2971 12:19:01.065157  

 2972 12:19:01.065217  ==

 2973 12:19:01.068275  Dram Type= 6, Freq= 0, CH_0, rank 1

 2974 12:19:01.072207  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2975 12:19:01.072288  ==

 2976 12:19:01.072369  

 2977 12:19:01.072429  

 2978 12:19:01.075233  	TX Vref Scan disable

 2979 12:19:01.075341   == TX Byte 0 ==

 2980 12:19:01.081944  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2981 12:19:01.085138  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2982 12:19:01.085212   == TX Byte 1 ==

 2983 12:19:01.092066  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 2984 12:19:01.095076  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 2985 12:19:01.095151  ==

 2986 12:19:01.098738  Dram Type= 6, Freq= 0, CH_0, rank 1

 2987 12:19:01.101656  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2988 12:19:01.101770  ==

 2989 12:19:01.114844  TX Vref=22, minBit 1, minWin=25, winSum=416

 2990 12:19:01.118587  TX Vref=24, minBit 3, minWin=25, winSum=420

 2991 12:19:01.121554  TX Vref=26, minBit 1, minWin=26, winSum=424

 2992 12:19:01.124895  TX Vref=28, minBit 4, minWin=26, winSum=429

 2993 12:19:01.128458  TX Vref=30, minBit 0, minWin=27, winSum=434

 2994 12:19:01.131597  TX Vref=32, minBit 8, minWin=26, winSum=430

 2995 12:19:01.138597  [TxChooseVref] Worse bit 0, Min win 27, Win sum 434, Final Vref 30

 2996 12:19:01.138678  

 2997 12:19:01.141683  Final TX Range 1 Vref 30

 2998 12:19:01.141783  

 2999 12:19:01.141871  ==

 3000 12:19:01.145288  Dram Type= 6, Freq= 0, CH_0, rank 1

 3001 12:19:01.148456  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3002 12:19:01.148531  ==

 3003 12:19:01.148593  

 3004 12:19:01.148650  

 3005 12:19:01.151605  	TX Vref Scan disable

 3006 12:19:01.155340   == TX Byte 0 ==

 3007 12:19:01.158322  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 3008 12:19:01.161708  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 3009 12:19:01.165263   == TX Byte 1 ==

 3010 12:19:01.168293  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3011 12:19:01.171606  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3012 12:19:01.171736  

 3013 12:19:01.174719  [DATLAT]

 3014 12:19:01.174799  Freq=1200, CH0 RK1

 3015 12:19:01.174863  

 3016 12:19:01.178540  DATLAT Default: 0xd

 3017 12:19:01.178637  0, 0xFFFF, sum = 0

 3018 12:19:01.181618  1, 0xFFFF, sum = 0

 3019 12:19:01.181708  2, 0xFFFF, sum = 0

 3020 12:19:01.185068  3, 0xFFFF, sum = 0

 3021 12:19:01.185141  4, 0xFFFF, sum = 0

 3022 12:19:01.188655  5, 0xFFFF, sum = 0

 3023 12:19:01.188774  6, 0xFFFF, sum = 0

 3024 12:19:01.191821  7, 0xFFFF, sum = 0

 3025 12:19:01.191924  8, 0xFFFF, sum = 0

 3026 12:19:01.194932  9, 0xFFFF, sum = 0

 3027 12:19:01.198624  10, 0xFFFF, sum = 0

 3028 12:19:01.198724  11, 0xFFFF, sum = 0

 3029 12:19:01.202046  12, 0x0, sum = 1

 3030 12:19:01.202145  13, 0x0, sum = 2

 3031 12:19:01.202235  14, 0x0, sum = 3

 3032 12:19:01.205089  15, 0x0, sum = 4

 3033 12:19:01.205162  best_step = 13

 3034 12:19:01.205221  

 3035 12:19:01.205278  ==

 3036 12:19:01.208547  Dram Type= 6, Freq= 0, CH_0, rank 1

 3037 12:19:01.215322  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3038 12:19:01.215432  ==

 3039 12:19:01.215527  RX Vref Scan: 0

 3040 12:19:01.215626  

 3041 12:19:01.218704  RX Vref 0 -> 0, step: 1

 3042 12:19:01.218781  

 3043 12:19:01.222185  RX Delay -13 -> 252, step: 4

 3044 12:19:01.225279  iDelay=195, Bit 0, Center 118 (51 ~ 186) 136

 3045 12:19:01.228328  iDelay=195, Bit 1, Center 120 (55 ~ 186) 132

 3046 12:19:01.235094  iDelay=195, Bit 2, Center 118 (51 ~ 186) 136

 3047 12:19:01.238464  iDelay=195, Bit 3, Center 118 (51 ~ 186) 136

 3048 12:19:01.241582  iDelay=195, Bit 4, Center 122 (55 ~ 190) 136

 3049 12:19:01.245321  iDelay=195, Bit 5, Center 116 (51 ~ 182) 132

 3050 12:19:01.248429  iDelay=195, Bit 6, Center 126 (59 ~ 194) 136

 3051 12:19:01.255399  iDelay=195, Bit 7, Center 126 (59 ~ 194) 136

 3052 12:19:01.258429  iDelay=195, Bit 8, Center 100 (35 ~ 166) 132

 3053 12:19:01.261626  iDelay=195, Bit 9, Center 96 (31 ~ 162) 132

 3054 12:19:01.264847  iDelay=195, Bit 10, Center 110 (47 ~ 174) 128

 3055 12:19:01.268554  iDelay=195, Bit 11, Center 100 (35 ~ 166) 132

 3056 12:19:01.274839  iDelay=195, Bit 12, Center 114 (51 ~ 178) 128

 3057 12:19:01.278516  iDelay=195, Bit 13, Center 116 (55 ~ 178) 124

 3058 12:19:01.281770  iDelay=195, Bit 14, Center 120 (59 ~ 182) 124

 3059 12:19:01.284951  iDelay=195, Bit 15, Center 118 (55 ~ 182) 128

 3060 12:19:01.285060  ==

 3061 12:19:01.288589  Dram Type= 6, Freq= 0, CH_0, rank 1

 3062 12:19:01.295157  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3063 12:19:01.295262  ==

 3064 12:19:01.295364  DQS Delay:

 3065 12:19:01.295454  DQS0 = 0, DQS1 = 0

 3066 12:19:01.298367  DQM Delay:

 3067 12:19:01.298465  DQM0 = 120, DQM1 = 109

 3068 12:19:01.301568  DQ Delay:

 3069 12:19:01.304780  DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118

 3070 12:19:01.308445  DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126

 3071 12:19:01.311538  DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100

 3072 12:19:01.314622  DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118

 3073 12:19:01.314720  

 3074 12:19:01.314783  

 3075 12:19:01.321935  [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps

 3076 12:19:01.324771  CH0 RK1: MR19=403, MR18=10F1

 3077 12:19:01.331806  CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26

 3078 12:19:01.334684  [RxdqsGatingPostProcess] freq 1200

 3079 12:19:01.341762  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3080 12:19:01.344961  best DQS0 dly(2T, 0.5T) = (0, 11)

 3081 12:19:01.345036  best DQS1 dly(2T, 0.5T) = (0, 11)

 3082 12:19:01.348391  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3083 12:19:01.351847  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3084 12:19:01.354897  best DQS0 dly(2T, 0.5T) = (0, 12)

 3085 12:19:01.358226  best DQS1 dly(2T, 0.5T) = (0, 11)

 3086 12:19:01.361972  best DQS0 P1 dly(2T, 0.5T) = (1, 0)

 3087 12:19:01.365393  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3088 12:19:01.368701  Pre-setting of DQS Precalculation

 3089 12:19:01.375040  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3090 12:19:01.375151  ==

 3091 12:19:01.378208  Dram Type= 6, Freq= 0, CH_1, rank 0

 3092 12:19:01.381985  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3093 12:19:01.382078  ==

 3094 12:19:01.388217  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3095 12:19:01.391959  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3096 12:19:01.401039  [CA 0] Center 37 (7~68) winsize 62

 3097 12:19:01.404159  [CA 1] Center 37 (7~68) winsize 62

 3098 12:19:01.408029  [CA 2] Center 35 (5~65) winsize 61

 3099 12:19:01.411278  [CA 3] Center 34 (4~64) winsize 61

 3100 12:19:01.414848  [CA 4] Center 34 (5~64) winsize 60

 3101 12:19:01.418046  [CA 5] Center 33 (3~63) winsize 61

 3102 12:19:01.418130  

 3103 12:19:01.421021  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3104 12:19:01.421131  

 3105 12:19:01.424686  [CATrainingPosCal] consider 1 rank data

 3106 12:19:01.427920  u2DelayCellTimex100 = 270/100 ps

 3107 12:19:01.431023  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3108 12:19:01.434574  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3109 12:19:01.440966  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3110 12:19:01.444424  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3111 12:19:01.447940  CA4 delay=34 (5~64),Diff = 1 PI (4 cell)

 3112 12:19:01.451431  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3113 12:19:01.451539  

 3114 12:19:01.454763  CA PerBit enable=1, Macro0, CA PI delay=33

 3115 12:19:01.454843  

 3116 12:19:01.458156  [CBTSetCACLKResult] CA Dly = 33

 3117 12:19:01.458260  CS Dly: 8 (0~39)

 3118 12:19:01.458351  ==

 3119 12:19:01.461404  Dram Type= 6, Freq= 0, CH_1, rank 1

 3120 12:19:01.467905  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3121 12:19:01.467997  ==

 3122 12:19:01.471123  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3123 12:19:01.478112  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3124 12:19:01.486834  [CA 0] Center 37 (7~68) winsize 62

 3125 12:19:01.489912  [CA 1] Center 37 (7~68) winsize 62

 3126 12:19:01.493167  [CA 2] Center 35 (5~65) winsize 61

 3127 12:19:01.496682  [CA 3] Center 34 (4~65) winsize 62

 3128 12:19:01.499964  [CA 4] Center 34 (4~65) winsize 62

 3129 12:19:01.503410  [CA 5] Center 33 (4~63) winsize 60

 3130 12:19:01.503511  

 3131 12:19:01.506750  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3132 12:19:01.506854  

 3133 12:19:01.509832  [CATrainingPosCal] consider 2 rank data

 3134 12:19:01.513631  u2DelayCellTimex100 = 270/100 ps

 3135 12:19:01.516788  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3136 12:19:01.519961  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3137 12:19:01.526902  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3138 12:19:01.529857  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3139 12:19:01.533729  CA4 delay=34 (5~64),Diff = 1 PI (4 cell)

 3140 12:19:01.536937  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3141 12:19:01.537025  

 3142 12:19:01.540090  CA PerBit enable=1, Macro0, CA PI delay=33

 3143 12:19:01.540178  

 3144 12:19:01.543713  [CBTSetCACLKResult] CA Dly = 33

 3145 12:19:01.543822  CS Dly: 9 (0~41)

 3146 12:19:01.543917  

 3147 12:19:01.546881  ----->DramcWriteLeveling(PI) begin...

 3148 12:19:01.549889  ==

 3149 12:19:01.549967  Dram Type= 6, Freq= 0, CH_1, rank 0

 3150 12:19:01.556786  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3151 12:19:01.556872  ==

 3152 12:19:01.560416  Write leveling (Byte 0): 26 => 26

 3153 12:19:01.563847  Write leveling (Byte 1): 29 => 29

 3154 12:19:01.563963  DramcWriteLeveling(PI) end<-----

 3155 12:19:01.566758  

 3156 12:19:01.566841  ==

 3157 12:19:01.570117  Dram Type= 6, Freq= 0, CH_1, rank 0

 3158 12:19:01.573398  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3159 12:19:01.573501  ==

 3160 12:19:01.577209  [Gating] SW mode calibration

 3161 12:19:01.583549  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3162 12:19:01.587363  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3163 12:19:01.593555   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3164 12:19:01.596791   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3165 12:19:01.599993   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3166 12:19:01.606780   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3167 12:19:01.610495   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3168 12:19:01.613443   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3169 12:19:01.620413   0 15 24 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 1)

 3170 12:19:01.623939   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 3171 12:19:01.627047   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3172 12:19:01.633707   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3173 12:19:01.636875   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3174 12:19:01.640824   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3175 12:19:01.643865   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3176 12:19:01.650250   1  0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 3177 12:19:01.653859   1  0 24 | B1->B0 | 3232 4444 | 0 0 | (1 1) (0 0)

 3178 12:19:01.657332   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3179 12:19:01.663767   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3180 12:19:01.667605   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3181 12:19:01.670493   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3182 12:19:01.677268   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3183 12:19:01.680863   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3184 12:19:01.684285   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3185 12:19:01.690298   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3186 12:19:01.694208   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3187 12:19:01.697396   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3188 12:19:01.703770   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3189 12:19:01.707517   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3190 12:19:01.710689   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3191 12:19:01.717032   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3192 12:19:01.720814   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3193 12:19:01.723883   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3194 12:19:01.727584   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3195 12:19:01.733862   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3196 12:19:01.737209   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3197 12:19:01.740598   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3198 12:19:01.747485   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3199 12:19:01.750635   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3200 12:19:01.754257   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3201 12:19:01.760388   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3202 12:19:01.763991   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3203 12:19:01.767325   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3204 12:19:01.770545  Total UI for P1: 0, mck2ui 16

 3205 12:19:01.774275  best dqsien dly found for B0: ( 1,  3, 26)

 3206 12:19:01.777426  Total UI for P1: 0, mck2ui 16

 3207 12:19:01.780839  best dqsien dly found for B1: ( 1,  3, 26)

 3208 12:19:01.783989  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3209 12:19:01.787774  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3210 12:19:01.787858  

 3211 12:19:01.790771  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3212 12:19:01.797457  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3213 12:19:01.797542  [Gating] SW calibration Done

 3214 12:19:01.797611  ==

 3215 12:19:01.800600  Dram Type= 6, Freq= 0, CH_1, rank 0

 3216 12:19:01.807601  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3217 12:19:01.807705  ==

 3218 12:19:01.807773  RX Vref Scan: 0

 3219 12:19:01.807834  

 3220 12:19:01.810907  RX Vref 0 -> 0, step: 1

 3221 12:19:01.810989  

 3222 12:19:01.814051  RX Delay -40 -> 252, step: 8

 3223 12:19:01.817152  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3224 12:19:01.820920  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3225 12:19:01.824223  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3226 12:19:01.830603  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3227 12:19:01.833766  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 3228 12:19:01.837487  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3229 12:19:01.840506  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 3230 12:19:01.844175  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3231 12:19:01.850788  iDelay=200, Bit 8, Center 103 (40 ~ 167) 128

 3232 12:19:01.853682  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3233 12:19:01.857176  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3234 12:19:01.860709  iDelay=200, Bit 11, Center 111 (48 ~ 175) 128

 3235 12:19:01.864119  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3236 12:19:01.870756  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3237 12:19:01.873919  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3238 12:19:01.877359  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3239 12:19:01.877481  ==

 3240 12:19:01.880682  Dram Type= 6, Freq= 0, CH_1, rank 0

 3241 12:19:01.883703  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3242 12:19:01.883841  ==

 3243 12:19:01.887255  DQS Delay:

 3244 12:19:01.887377  DQS0 = 0, DQS1 = 0

 3245 12:19:01.890431  DQM Delay:

 3246 12:19:01.890530  DQM0 = 120, DQM1 = 116

 3247 12:19:01.890600  DQ Delay:

 3248 12:19:01.894186  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3249 12:19:01.900687  DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123

 3250 12:19:01.904335  DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111

 3251 12:19:01.907215  DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123

 3252 12:19:01.907300  

 3253 12:19:01.907367  

 3254 12:19:01.907429  ==

 3255 12:19:01.910508  Dram Type= 6, Freq= 0, CH_1, rank 0

 3256 12:19:01.913821  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3257 12:19:01.913919  ==

 3258 12:19:01.913990  

 3259 12:19:01.914053  

 3260 12:19:01.917082  	TX Vref Scan disable

 3261 12:19:01.920911   == TX Byte 0 ==

 3262 12:19:01.924135  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3263 12:19:01.927315  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3264 12:19:01.930525   == TX Byte 1 ==

 3265 12:19:01.934366  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3266 12:19:01.937547  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3267 12:19:01.937628  ==

 3268 12:19:01.940716  Dram Type= 6, Freq= 0, CH_1, rank 0

 3269 12:19:01.943830  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3270 12:19:01.943909  ==

 3271 12:19:01.957139  TX Vref=22, minBit 9, minWin=25, winSum=415

 3272 12:19:01.960787  TX Vref=24, minBit 11, minWin=24, winSum=417

 3273 12:19:01.963746  TX Vref=26, minBit 9, minWin=25, winSum=425

 3274 12:19:01.967020  TX Vref=28, minBit 1, minWin=26, winSum=426

 3275 12:19:01.970233  TX Vref=30, minBit 1, minWin=26, winSum=431

 3276 12:19:01.977384  TX Vref=32, minBit 2, minWin=26, winSum=435

 3277 12:19:01.980329  [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 32

 3278 12:19:01.980441  

 3279 12:19:01.983690  Final TX Range 1 Vref 32

 3280 12:19:01.983769  

 3281 12:19:01.983833  ==

 3282 12:19:01.986943  Dram Type= 6, Freq= 0, CH_1, rank 0

 3283 12:19:01.990618  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3284 12:19:01.990722  ==

 3285 12:19:01.993709  

 3286 12:19:01.993809  

 3287 12:19:01.993907  	TX Vref Scan disable

 3288 12:19:01.997061   == TX Byte 0 ==

 3289 12:19:02.000561  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3290 12:19:02.003941  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3291 12:19:02.007283   == TX Byte 1 ==

 3292 12:19:02.010370  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3293 12:19:02.013674  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3294 12:19:02.017251  

 3295 12:19:02.017353  [DATLAT]

 3296 12:19:02.017460  Freq=1200, CH1 RK0

 3297 12:19:02.017528  

 3298 12:19:02.020531  DATLAT Default: 0xd

 3299 12:19:02.020614  0, 0xFFFF, sum = 0

 3300 12:19:02.023776  1, 0xFFFF, sum = 0

 3301 12:19:02.023860  2, 0xFFFF, sum = 0

 3302 12:19:02.027349  3, 0xFFFF, sum = 0

 3303 12:19:02.027434  4, 0xFFFF, sum = 0

 3304 12:19:02.030392  5, 0xFFFF, sum = 0

 3305 12:19:02.033416  6, 0xFFFF, sum = 0

 3306 12:19:02.033500  7, 0xFFFF, sum = 0

 3307 12:19:02.037212  8, 0xFFFF, sum = 0

 3308 12:19:02.037297  9, 0xFFFF, sum = 0

 3309 12:19:02.040426  10, 0xFFFF, sum = 0

 3310 12:19:02.040513  11, 0xFFFF, sum = 0

 3311 12:19:02.043441  12, 0x0, sum = 1

 3312 12:19:02.043526  13, 0x0, sum = 2

 3313 12:19:02.047272  14, 0x0, sum = 3

 3314 12:19:02.047388  15, 0x0, sum = 4

 3315 12:19:02.047484  best_step = 13

 3316 12:19:02.047582  

 3317 12:19:02.050333  ==

 3318 12:19:02.053495  Dram Type= 6, Freq= 0, CH_1, rank 0

 3319 12:19:02.057016  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3320 12:19:02.057135  ==

 3321 12:19:02.057232  RX Vref Scan: 1

 3322 12:19:02.057322  

 3323 12:19:02.060638  Set Vref Range= 32 -> 127

 3324 12:19:02.060728  

 3325 12:19:02.063921  RX Vref 32 -> 127, step: 1

 3326 12:19:02.064006  

 3327 12:19:02.066914  RX Delay -5 -> 252, step: 4

 3328 12:19:02.066991  

 3329 12:19:02.070722  Set Vref, RX VrefLevel [Byte0]: 32

 3330 12:19:02.073950                           [Byte1]: 32

 3331 12:19:02.074057  

 3332 12:19:02.077162  Set Vref, RX VrefLevel [Byte0]: 33

 3333 12:19:02.080383                           [Byte1]: 33

 3334 12:19:02.080461  

 3335 12:19:02.083443  Set Vref, RX VrefLevel [Byte0]: 34

 3336 12:19:02.087263                           [Byte1]: 34

 3337 12:19:02.091152  

 3338 12:19:02.091229  Set Vref, RX VrefLevel [Byte0]: 35

 3339 12:19:02.094430                           [Byte1]: 35

 3340 12:19:02.098670  

 3341 12:19:02.098753  Set Vref, RX VrefLevel [Byte0]: 36

 3342 12:19:02.102184                           [Byte1]: 36

 3343 12:19:02.106696  

 3344 12:19:02.106781  Set Vref, RX VrefLevel [Byte0]: 37

 3345 12:19:02.109994                           [Byte1]: 37

 3346 12:19:02.114292  

 3347 12:19:02.114377  Set Vref, RX VrefLevel [Byte0]: 38

 3348 12:19:02.117900                           [Byte1]: 38

 3349 12:19:02.122125  

 3350 12:19:02.122239  Set Vref, RX VrefLevel [Byte0]: 39

 3351 12:19:02.125632                           [Byte1]: 39

 3352 12:19:02.130335  

 3353 12:19:02.130419  Set Vref, RX VrefLevel [Byte0]: 40

 3354 12:19:02.133792                           [Byte1]: 40

 3355 12:19:02.138590  

 3356 12:19:02.138681  Set Vref, RX VrefLevel [Byte0]: 41

 3357 12:19:02.141458                           [Byte1]: 41

 3358 12:19:02.145803  

 3359 12:19:02.145884  Set Vref, RX VrefLevel [Byte0]: 42

 3360 12:19:02.149547                           [Byte1]: 42

 3361 12:19:02.153986  

 3362 12:19:02.154079  Set Vref, RX VrefLevel [Byte0]: 43

 3363 12:19:02.157086                           [Byte1]: 43

 3364 12:19:02.161487  

 3365 12:19:02.161576  Set Vref, RX VrefLevel [Byte0]: 44

 3366 12:19:02.165099                           [Byte1]: 44

 3367 12:19:02.169240  

 3368 12:19:02.169343  Set Vref, RX VrefLevel [Byte0]: 45

 3369 12:19:02.172611                           [Byte1]: 45

 3370 12:19:02.177379  

 3371 12:19:02.177464  Set Vref, RX VrefLevel [Byte0]: 46

 3372 12:19:02.180512                           [Byte1]: 46

 3373 12:19:02.185532  

 3374 12:19:02.185615  Set Vref, RX VrefLevel [Byte0]: 47

 3375 12:19:02.188545                           [Byte1]: 47

 3376 12:19:02.193019  

 3377 12:19:02.193102  Set Vref, RX VrefLevel [Byte0]: 48

 3378 12:19:02.196772                           [Byte1]: 48

 3379 12:19:02.200676  

 3380 12:19:02.200755  Set Vref, RX VrefLevel [Byte0]: 49

 3381 12:19:02.204402                           [Byte1]: 49

 3382 12:19:02.209059  

 3383 12:19:02.209140  Set Vref, RX VrefLevel [Byte0]: 50

 3384 12:19:02.212112                           [Byte1]: 50

 3385 12:19:02.216896  

 3386 12:19:02.216987  Set Vref, RX VrefLevel [Byte0]: 51

 3387 12:19:02.219861                           [Byte1]: 51

 3388 12:19:02.224217  

 3389 12:19:02.224312  Set Vref, RX VrefLevel [Byte0]: 52

 3390 12:19:02.227839                           [Byte1]: 52

 3391 12:19:02.232301  

 3392 12:19:02.232401  Set Vref, RX VrefLevel [Byte0]: 53

 3393 12:19:02.235692                           [Byte1]: 53

 3394 12:19:02.240065  

 3395 12:19:02.240175  Set Vref, RX VrefLevel [Byte0]: 54

 3396 12:19:02.243794                           [Byte1]: 54

 3397 12:19:02.248294  

 3398 12:19:02.248408  Set Vref, RX VrefLevel [Byte0]: 55

 3399 12:19:02.251491                           [Byte1]: 55

 3400 12:19:02.255771  

 3401 12:19:02.255873  Set Vref, RX VrefLevel [Byte0]: 56

 3402 12:19:02.259381                           [Byte1]: 56

 3403 12:19:02.263959  

 3404 12:19:02.264043  Set Vref, RX VrefLevel [Byte0]: 57

 3405 12:19:02.267073                           [Byte1]: 57

 3406 12:19:02.271547  

 3407 12:19:02.271631  Set Vref, RX VrefLevel [Byte0]: 58

 3408 12:19:02.275421                           [Byte1]: 58

 3409 12:19:02.279572  

 3410 12:19:02.279683  Set Vref, RX VrefLevel [Byte0]: 59

 3411 12:19:02.283005                           [Byte1]: 59

 3412 12:19:02.287548  

 3413 12:19:02.287631  Set Vref, RX VrefLevel [Byte0]: 60

 3414 12:19:02.290750                           [Byte1]: 60

 3415 12:19:02.295034  

 3416 12:19:02.295118  Set Vref, RX VrefLevel [Byte0]: 61

 3417 12:19:02.298261                           [Byte1]: 61

 3418 12:19:02.303103  

 3419 12:19:02.303186  Set Vref, RX VrefLevel [Byte0]: 62

 3420 12:19:02.306250                           [Byte1]: 62

 3421 12:19:02.310793  

 3422 12:19:02.310877  Set Vref, RX VrefLevel [Byte0]: 63

 3423 12:19:02.313875                           [Byte1]: 63

 3424 12:19:02.319054  

 3425 12:19:02.319137  Set Vref, RX VrefLevel [Byte0]: 64

 3426 12:19:02.321792                           [Byte1]: 64

 3427 12:19:02.326683  

 3428 12:19:02.326766  Set Vref, RX VrefLevel [Byte0]: 65

 3429 12:19:02.329924                           [Byte1]: 65

 3430 12:19:02.334333  

 3431 12:19:02.334416  Set Vref, RX VrefLevel [Byte0]: 66

 3432 12:19:02.337924                           [Byte1]: 66

 3433 12:19:02.342440  

 3434 12:19:02.342523  Set Vref, RX VrefLevel [Byte0]: 67

 3435 12:19:02.345570                           [Byte1]: 67

 3436 12:19:02.349862  

 3437 12:19:02.349946  Final RX Vref Byte 0 = 53 to rank0

 3438 12:19:02.353620  Final RX Vref Byte 1 = 47 to rank0

 3439 12:19:02.356814  Final RX Vref Byte 0 = 53 to rank1

 3440 12:19:02.360077  Final RX Vref Byte 1 = 47 to rank1==

 3441 12:19:02.363572  Dram Type= 6, Freq= 0, CH_1, rank 0

 3442 12:19:02.370210  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3443 12:19:02.370297  ==

 3444 12:19:02.370363  DQS Delay:

 3445 12:19:02.370424  DQS0 = 0, DQS1 = 0

 3446 12:19:02.373249  DQM Delay:

 3447 12:19:02.373332  DQM0 = 120, DQM1 = 116

 3448 12:19:02.376681  DQ Delay:

 3449 12:19:02.379882  DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116

 3450 12:19:02.383733  DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120

 3451 12:19:02.386889  DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108

 3452 12:19:02.389900  DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126

 3453 12:19:02.389983  

 3454 12:19:02.390049  

 3455 12:19:02.396661  [DQSOSCAuto] RK0, (LSB)MR18= 0x113, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps

 3456 12:19:02.400095  CH1 RK0: MR19=404, MR18=113

 3457 12:19:02.407010  CH1_RK0: MR19=0x404, MR18=0x113, DQSOSC=402, MR23=63, INC=40, DEC=27

 3458 12:19:02.407099  

 3459 12:19:02.410218  ----->DramcWriteLeveling(PI) begin...

 3460 12:19:02.410304  ==

 3461 12:19:02.413338  Dram Type= 6, Freq= 0, CH_1, rank 1

 3462 12:19:02.417161  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3463 12:19:02.417247  ==

 3464 12:19:02.420186  Write leveling (Byte 0): 26 => 26

 3465 12:19:02.423289  Write leveling (Byte 1): 29 => 29

 3466 12:19:02.426920  DramcWriteLeveling(PI) end<-----

 3467 12:19:02.427006  

 3468 12:19:02.427071  ==

 3469 12:19:02.430546  Dram Type= 6, Freq= 0, CH_1, rank 1

 3470 12:19:02.433795  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3471 12:19:02.436953  ==

 3472 12:19:02.437039  [Gating] SW mode calibration

 3473 12:19:02.446947  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3474 12:19:02.450101  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3475 12:19:02.453853   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3476 12:19:02.459932   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3477 12:19:02.463857   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3478 12:19:02.467189   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3479 12:19:02.473905   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3480 12:19:02.477128   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 3481 12:19:02.480284   0 15 24 | B1->B0 | 2a2a 3232 | 0 1 | (1 0) (1 0)

 3482 12:19:02.487245   0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 3483 12:19:02.490310   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3484 12:19:02.493854   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3485 12:19:02.497175   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3486 12:19:02.504134   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3487 12:19:02.507255   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3488 12:19:02.510635   1  0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 3489 12:19:02.517721   1  0 24 | B1->B0 | 4545 2c2c | 0 0 | (0 0) (0 0)

 3490 12:19:02.520960   1  0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 3491 12:19:02.524038   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3492 12:19:02.530885   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3493 12:19:02.533966   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3494 12:19:02.537011   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3495 12:19:02.543906   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3496 12:19:02.546943   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3497 12:19:02.550212   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3498 12:19:02.557140   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 3499 12:19:02.560707   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3500 12:19:02.563940   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3501 12:19:02.570418   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3502 12:19:02.573573   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3503 12:19:02.576819   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3504 12:19:02.583493   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3505 12:19:02.586719   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3506 12:19:02.590510   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3507 12:19:02.596841   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3508 12:19:02.600127   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3509 12:19:02.603617   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3510 12:19:02.610335   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3511 12:19:02.613458   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3512 12:19:02.617044   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 3513 12:19:02.620054   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3514 12:19:02.627080   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 3515 12:19:02.629880  Total UI for P1: 0, mck2ui 16

 3516 12:19:02.633606  best dqsien dly found for B1: ( 1,  3, 22)

 3517 12:19:02.636958   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3518 12:19:02.640387  Total UI for P1: 0, mck2ui 16

 3519 12:19:02.643311  best dqsien dly found for B0: ( 1,  3, 26)

 3520 12:19:02.646694  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3521 12:19:02.650427  best DQS1 dly(MCK, UI, PI) = (1, 3, 22)

 3522 12:19:02.650541  

 3523 12:19:02.653603  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3524 12:19:02.656782  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3525 12:19:02.659919  [Gating] SW calibration Done

 3526 12:19:02.660006  ==

 3527 12:19:02.663633  Dram Type= 6, Freq= 0, CH_1, rank 1

 3528 12:19:02.669892  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3529 12:19:02.670006  ==

 3530 12:19:02.670100  RX Vref Scan: 0

 3531 12:19:02.670199  

 3532 12:19:02.673729  RX Vref 0 -> 0, step: 1

 3533 12:19:02.673804  

 3534 12:19:02.676915  RX Delay -40 -> 252, step: 8

 3535 12:19:02.680160  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3536 12:19:02.683300  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3537 12:19:02.686476  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3538 12:19:02.690379  iDelay=200, Bit 3, Center 119 (56 ~ 183) 128

 3539 12:19:02.696621  iDelay=200, Bit 4, Center 119 (56 ~ 183) 128

 3540 12:19:02.699811  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3541 12:19:02.703583  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3542 12:19:02.706718  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3543 12:19:02.709915  iDelay=200, Bit 8, Center 107 (40 ~ 175) 136

 3544 12:19:02.716515  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3545 12:19:02.720114  iDelay=200, Bit 10, Center 119 (56 ~ 183) 128

 3546 12:19:02.723221  iDelay=200, Bit 11, Center 115 (48 ~ 183) 136

 3547 12:19:02.726722  iDelay=200, Bit 12, Center 127 (56 ~ 199) 144

 3548 12:19:02.730083  iDelay=200, Bit 13, Center 123 (56 ~ 191) 136

 3549 12:19:02.736395  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3550 12:19:02.739746  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3551 12:19:02.739867  ==

 3552 12:19:02.742930  Dram Type= 6, Freq= 0, CH_1, rank 1

 3553 12:19:02.746529  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3554 12:19:02.746605  ==

 3555 12:19:02.749691  DQS Delay:

 3556 12:19:02.749780  DQS0 = 0, DQS1 = 0

 3557 12:19:02.749858  DQM Delay:

 3558 12:19:02.752920  DQM0 = 121, DQM1 = 118

 3559 12:19:02.753013  DQ Delay:

 3560 12:19:02.756597  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3561 12:19:02.759507  DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123

 3562 12:19:02.766774  DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115

 3563 12:19:02.769754  DQ12 =127, DQ13 =123, DQ14 =123, DQ15 =123

 3564 12:19:02.769861  

 3565 12:19:02.769989  

 3566 12:19:02.770132  ==

 3567 12:19:02.772768  Dram Type= 6, Freq= 0, CH_1, rank 1

 3568 12:19:02.776533  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3569 12:19:02.776633  ==

 3570 12:19:02.776730  

 3571 12:19:02.776817  

 3572 12:19:02.779768  	TX Vref Scan disable

 3573 12:19:02.782933   == TX Byte 0 ==

 3574 12:19:02.786751  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3575 12:19:02.789891  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3576 12:19:02.792896   == TX Byte 1 ==

 3577 12:19:02.796521  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3578 12:19:02.799826  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3579 12:19:02.799927  ==

 3580 12:19:02.802986  Dram Type= 6, Freq= 0, CH_1, rank 1

 3581 12:19:02.806155  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3582 12:19:02.806237  ==

 3583 12:19:02.819359  TX Vref=22, minBit 9, minWin=25, winSum=419

 3584 12:19:02.822482  TX Vref=24, minBit 1, minWin=26, winSum=425

 3585 12:19:02.825806  TX Vref=26, minBit 2, minWin=26, winSum=430

 3586 12:19:02.829014  TX Vref=28, minBit 2, minWin=26, winSum=433

 3587 12:19:02.832861  TX Vref=30, minBit 1, minWin=27, winSum=437

 3588 12:19:02.839470  TX Vref=32, minBit 9, minWin=26, winSum=434

 3589 12:19:02.842506  [TxChooseVref] Worse bit 1, Min win 27, Win sum 437, Final Vref 30

 3590 12:19:02.842619  

 3591 12:19:02.846067  Final TX Range 1 Vref 30

 3592 12:19:02.846149  

 3593 12:19:02.846213  ==

 3594 12:19:02.849258  Dram Type= 6, Freq= 0, CH_1, rank 1

 3595 12:19:02.852910  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3596 12:19:02.853029  ==

 3597 12:19:02.856071  

 3598 12:19:02.856168  

 3599 12:19:02.856236  	TX Vref Scan disable

 3600 12:19:02.859155   == TX Byte 0 ==

 3601 12:19:02.862191  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3602 12:19:02.865797  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3603 12:19:02.869295   == TX Byte 1 ==

 3604 12:19:02.872480  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3605 12:19:02.879310  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3606 12:19:02.879445  

 3607 12:19:02.879544  [DATLAT]

 3608 12:19:02.879647  Freq=1200, CH1 RK1

 3609 12:19:02.879744  

 3610 12:19:02.882262  DATLAT Default: 0xd

 3611 12:19:02.882366  0, 0xFFFF, sum = 0

 3612 12:19:02.885933  1, 0xFFFF, sum = 0

 3613 12:19:02.886047  2, 0xFFFF, sum = 0

 3614 12:19:02.888729  3, 0xFFFF, sum = 0

 3615 12:19:02.892221  4, 0xFFFF, sum = 0

 3616 12:19:02.892333  5, 0xFFFF, sum = 0

 3617 12:19:02.895357  6, 0xFFFF, sum = 0

 3618 12:19:02.895461  7, 0xFFFF, sum = 0

 3619 12:19:02.898906  8, 0xFFFF, sum = 0

 3620 12:19:02.899013  9, 0xFFFF, sum = 0

 3621 12:19:02.901843  10, 0xFFFF, sum = 0

 3622 12:19:02.901924  11, 0xFFFF, sum = 0

 3623 12:19:02.905645  12, 0x0, sum = 1

 3624 12:19:02.905734  13, 0x0, sum = 2

 3625 12:19:02.908900  14, 0x0, sum = 3

 3626 12:19:02.908985  15, 0x0, sum = 4

 3627 12:19:02.912161  best_step = 13

 3628 12:19:02.912245  

 3629 12:19:02.912339  ==

 3630 12:19:02.915315  Dram Type= 6, Freq= 0, CH_1, rank 1

 3631 12:19:02.919278  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3632 12:19:02.919385  ==

 3633 12:19:02.919488  RX Vref Scan: 0

 3634 12:19:02.919579  

 3635 12:19:02.922289  RX Vref 0 -> 0, step: 1

 3636 12:19:02.922396  

 3637 12:19:02.925399  RX Delay -5 -> 252, step: 4

 3638 12:19:02.929157  iDelay=195, Bit 0, Center 122 (59 ~ 186) 128

 3639 12:19:02.935428  iDelay=195, Bit 1, Center 116 (55 ~ 178) 124

 3640 12:19:02.939214  iDelay=195, Bit 2, Center 110 (51 ~ 170) 120

 3641 12:19:02.942225  iDelay=195, Bit 3, Center 118 (59 ~ 178) 120

 3642 12:19:02.945769  iDelay=195, Bit 4, Center 116 (55 ~ 178) 124

 3643 12:19:02.949006  iDelay=195, Bit 5, Center 132 (71 ~ 194) 124

 3644 12:19:02.955859  iDelay=195, Bit 6, Center 130 (67 ~ 194) 128

 3645 12:19:02.958801  iDelay=195, Bit 7, Center 120 (59 ~ 182) 124

 3646 12:19:02.962047  iDelay=195, Bit 8, Center 104 (43 ~ 166) 124

 3647 12:19:02.965756  iDelay=195, Bit 9, Center 106 (47 ~ 166) 120

 3648 12:19:02.968990  iDelay=195, Bit 10, Center 116 (55 ~ 178) 124

 3649 12:19:02.972208  iDelay=195, Bit 11, Center 110 (51 ~ 170) 120

 3650 12:19:02.978882  iDelay=195, Bit 12, Center 126 (63 ~ 190) 128

 3651 12:19:02.982013  iDelay=195, Bit 13, Center 124 (67 ~ 182) 116

 3652 12:19:02.985784  iDelay=195, Bit 14, Center 122 (63 ~ 182) 120

 3653 12:19:02.988761  iDelay=195, Bit 15, Center 124 (63 ~ 186) 124

 3654 12:19:02.992241  ==

 3655 12:19:02.992334  Dram Type= 6, Freq= 0, CH_1, rank 1

 3656 12:19:02.998874  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3657 12:19:02.998988  ==

 3658 12:19:02.999094  DQS Delay:

 3659 12:19:03.001843  DQS0 = 0, DQS1 = 0

 3660 12:19:03.001949  DQM Delay:

 3661 12:19:03.005478  DQM0 = 120, DQM1 = 116

 3662 12:19:03.005584  DQ Delay:

 3663 12:19:03.008463  DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118

 3664 12:19:03.011804  DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120

 3665 12:19:03.015148  DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110

 3666 12:19:03.018608  DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124

 3667 12:19:03.018699  

 3668 12:19:03.018765  

 3669 12:19:03.028192  [DQSOSCAuto] RK1, (LSB)MR18= 0x14f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps

 3670 12:19:03.031803  CH1 RK1: MR19=403, MR18=14F1

 3671 12:19:03.035057  CH1_RK1: MR19=0x403, MR18=0x14F1, DQSOSC=402, MR23=63, INC=40, DEC=27

 3672 12:19:03.038293  [RxdqsGatingPostProcess] freq 1200

 3673 12:19:03.045284  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3674 12:19:03.048172  best DQS0 dly(2T, 0.5T) = (0, 11)

 3675 12:19:03.051822  best DQS1 dly(2T, 0.5T) = (0, 11)

 3676 12:19:03.054919  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3677 12:19:03.058624  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3678 12:19:03.061740  best DQS0 dly(2T, 0.5T) = (0, 11)

 3679 12:19:03.064869  best DQS1 dly(2T, 0.5T) = (0, 11)

 3680 12:19:03.068156  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3681 12:19:03.071823  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3682 12:19:03.071913  Pre-setting of DQS Precalculation

 3683 12:19:03.078684  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3684 12:19:03.085238  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3685 12:19:03.091732  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3686 12:19:03.091827  

 3687 12:19:03.091895  

 3688 12:19:03.094980  [Calibration Summary] 2400 Mbps

 3689 12:19:03.098219  CH 0, Rank 0

 3690 12:19:03.098299  SW Impedance     : PASS

 3691 12:19:03.101293  DUTY Scan        : NO K

 3692 12:19:03.104951  ZQ Calibration   : PASS

 3693 12:19:03.105035  Jitter Meter     : NO K

 3694 12:19:03.108045  CBT Training     : PASS

 3695 12:19:03.111295  Write leveling   : PASS

 3696 12:19:03.111407  RX DQS gating    : PASS

 3697 12:19:03.115049  RX DQ/DQS(RDDQC) : PASS

 3698 12:19:03.115161  TX DQ/DQS        : PASS

 3699 12:19:03.118065  RX DATLAT        : PASS

 3700 12:19:03.121726  RX DQ/DQS(Engine): PASS

 3701 12:19:03.121811  TX OE            : NO K

 3702 12:19:03.124787  All Pass.

 3703 12:19:03.124866  

 3704 12:19:03.124934  CH 0, Rank 1

 3705 12:19:03.127991  SW Impedance     : PASS

 3706 12:19:03.128095  DUTY Scan        : NO K

 3707 12:19:03.131335  ZQ Calibration   : PASS

 3708 12:19:03.134643  Jitter Meter     : NO K

 3709 12:19:03.134754  CBT Training     : PASS

 3710 12:19:03.137997  Write leveling   : PASS

 3711 12:19:03.141670  RX DQS gating    : PASS

 3712 12:19:03.141779  RX DQ/DQS(RDDQC) : PASS

 3713 12:19:03.144859  TX DQ/DQS        : PASS

 3714 12:19:03.147916  RX DATLAT        : PASS

 3715 12:19:03.147998  RX DQ/DQS(Engine): PASS

 3716 12:19:03.151255  TX OE            : NO K

 3717 12:19:03.151360  All Pass.

 3718 12:19:03.151454  

 3719 12:19:03.154883  CH 1, Rank 0

 3720 12:19:03.154989  SW Impedance     : PASS

 3721 12:19:03.157841  DUTY Scan        : NO K

 3722 12:19:03.161550  ZQ Calibration   : PASS

 3723 12:19:03.161657  Jitter Meter     : NO K

 3724 12:19:03.164593  CBT Training     : PASS

 3725 12:19:03.167913  Write leveling   : PASS

 3726 12:19:03.167995  RX DQS gating    : PASS

 3727 12:19:03.171572  RX DQ/DQS(RDDQC) : PASS

 3728 12:19:03.171689  TX DQ/DQS        : PASS

 3729 12:19:03.174699  RX DATLAT        : PASS

 3730 12:19:03.177831  RX DQ/DQS(Engine): PASS

 3731 12:19:03.177934  TX OE            : NO K

 3732 12:19:03.181679  All Pass.

 3733 12:19:03.181780  

 3734 12:19:03.181873  CH 1, Rank 1

 3735 12:19:03.184784  SW Impedance     : PASS

 3736 12:19:03.184896  DUTY Scan        : NO K

 3737 12:19:03.187968  ZQ Calibration   : PASS

 3738 12:19:03.191557  Jitter Meter     : NO K

 3739 12:19:03.191670  CBT Training     : PASS

 3740 12:19:03.194671  Write leveling   : PASS

 3741 12:19:03.197907  RX DQS gating    : PASS

 3742 12:19:03.198016  RX DQ/DQS(RDDQC) : PASS

 3743 12:19:03.201176  TX DQ/DQS        : PASS

 3744 12:19:03.204324  RX DATLAT        : PASS

 3745 12:19:03.204403  RX DQ/DQS(Engine): PASS

 3746 12:19:03.208030  TX OE            : NO K

 3747 12:19:03.208111  All Pass.

 3748 12:19:03.208176  

 3749 12:19:03.211331  DramC Write-DBI off

 3750 12:19:03.214492  	PER_BANK_REFRESH: Hybrid Mode

 3751 12:19:03.214605  TX_TRACKING: ON

 3752 12:19:03.224237  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3753 12:19:03.227886  [FAST_K] Save calibration result to emmc

 3754 12:19:03.231183  dramc_set_vcore_voltage set vcore to 650000

 3755 12:19:03.234389  Read voltage for 600, 5

 3756 12:19:03.234501  Vio18 = 0

 3757 12:19:03.234596  Vcore = 650000

 3758 12:19:03.238037  Vdram = 0

 3759 12:19:03.238140  Vddq = 0

 3760 12:19:03.238230  Vmddr = 0

 3761 12:19:03.244182  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3762 12:19:03.247603  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3763 12:19:03.251012  MEM_TYPE=3, freq_sel=19

 3764 12:19:03.254214  sv_algorithm_assistance_LP4_1600 

 3765 12:19:03.257284  ============ PULL DRAM RESETB DOWN ============

 3766 12:19:03.260975  ========== PULL DRAM RESETB DOWN end =========

 3767 12:19:03.267699  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3768 12:19:03.270877  =================================== 

 3769 12:19:03.270953  LPDDR4 DRAM CONFIGURATION

 3770 12:19:03.273904  =================================== 

 3771 12:19:03.277514  EX_ROW_EN[0]    = 0x0

 3772 12:19:03.281020  EX_ROW_EN[1]    = 0x0

 3773 12:19:03.281105  LP4Y_EN      = 0x0

 3774 12:19:03.284114  WORK_FSP     = 0x0

 3775 12:19:03.284217  WL           = 0x2

 3776 12:19:03.287447  RL           = 0x2

 3777 12:19:03.287550  BL           = 0x2

 3778 12:19:03.291316  RPST         = 0x0

 3779 12:19:03.291424  RD_PRE       = 0x0

 3780 12:19:03.294129  WR_PRE       = 0x1

 3781 12:19:03.294230  WR_PST       = 0x0

 3782 12:19:03.297760  DBI_WR       = 0x0

 3783 12:19:03.297861  DBI_RD       = 0x0

 3784 12:19:03.300971  OTF          = 0x1

 3785 12:19:03.304062  =================================== 

 3786 12:19:03.307327  =================================== 

 3787 12:19:03.307431  ANA top config

 3788 12:19:03.310506  =================================== 

 3789 12:19:03.314300  DLL_ASYNC_EN            =  0

 3790 12:19:03.317466  ALL_SLAVE_EN            =  1

 3791 12:19:03.320549  NEW_RANK_MODE           =  1

 3792 12:19:03.320651  DLL_IDLE_MODE           =  1

 3793 12:19:03.324052  LP45_APHY_COMB_EN       =  1

 3794 12:19:03.327191  TX_ODT_DIS              =  1

 3795 12:19:03.330762  NEW_8X_MODE             =  1

 3796 12:19:03.333873  =================================== 

 3797 12:19:03.337758  =================================== 

 3798 12:19:03.337858  data_rate                  = 1200

 3799 12:19:03.340980  CKR                        = 1

 3800 12:19:03.344355  DQ_P2S_RATIO               = 8

 3801 12:19:03.347518  =================================== 

 3802 12:19:03.350618  CA_P2S_RATIO               = 8

 3803 12:19:03.354240  DQ_CA_OPEN                 = 0

 3804 12:19:03.357267  DQ_SEMI_OPEN               = 0

 3805 12:19:03.357366  CA_SEMI_OPEN               = 0

 3806 12:19:03.360795  CA_FULL_RATE               = 0

 3807 12:19:03.364237  DQ_CKDIV4_EN               = 1

 3808 12:19:03.367566  CA_CKDIV4_EN               = 1

 3809 12:19:03.370665  CA_PREDIV_EN               = 0

 3810 12:19:03.374319  PH8_DLY                    = 0

 3811 12:19:03.374403  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3812 12:19:03.377569  DQ_AAMCK_DIV               = 4

 3813 12:19:03.381138  CA_AAMCK_DIV               = 4

 3814 12:19:03.384010  CA_ADMCK_DIV               = 4

 3815 12:19:03.387656  DQ_TRACK_CA_EN             = 0

 3816 12:19:03.390489  CA_PICK                    = 600

 3817 12:19:03.390630  CA_MCKIO                   = 600

 3818 12:19:03.394383  MCKIO_SEMI                 = 0

 3819 12:19:03.397440  PLL_FREQ                   = 2288

 3820 12:19:03.400522  DQ_UI_PI_RATIO             = 32

 3821 12:19:03.404088  CA_UI_PI_RATIO             = 0

 3822 12:19:03.407196  =================================== 

 3823 12:19:03.410361  =================================== 

 3824 12:19:03.414284  memory_type:LPDDR4         

 3825 12:19:03.414439  GP_NUM     : 10       

 3826 12:19:03.417486  SRAM_EN    : 1       

 3827 12:19:03.417565  MD32_EN    : 0       

 3828 12:19:03.420531  =================================== 

 3829 12:19:03.423573  [ANA_INIT] >>>>>>>>>>>>>> 

 3830 12:19:03.427437  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3831 12:19:03.430593  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3832 12:19:03.433713  =================================== 

 3833 12:19:03.436957  data_rate = 1200,PCW = 0X5800

 3834 12:19:03.440115  =================================== 

 3835 12:19:03.443342  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3836 12:19:03.450292  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3837 12:19:03.453591  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3838 12:19:03.459983  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3839 12:19:03.463707  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3840 12:19:03.466558  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3841 12:19:03.466671  [ANA_INIT] flow start 

 3842 12:19:03.469774  [ANA_INIT] PLL >>>>>>>> 

 3843 12:19:03.473025  [ANA_INIT] PLL <<<<<<<< 

 3844 12:19:03.473129  [ANA_INIT] MIDPI >>>>>>>> 

 3845 12:19:03.476760  [ANA_INIT] MIDPI <<<<<<<< 

 3846 12:19:03.479685  [ANA_INIT] DLL >>>>>>>> 

 3847 12:19:03.479791  [ANA_INIT] flow end 

 3848 12:19:03.486367  ============ LP4 DIFF to SE enter ============

 3849 12:19:03.490081  ============ LP4 DIFF to SE exit  ============

 3850 12:19:03.493497  [ANA_INIT] <<<<<<<<<<<<< 

 3851 12:19:03.496656  [Flow] Enable top DCM control >>>>> 

 3852 12:19:03.499644  [Flow] Enable top DCM control <<<<< 

 3853 12:19:03.503033  Enable DLL master slave shuffle 

 3854 12:19:03.506381  ============================================================== 

 3855 12:19:03.509836  Gating Mode config

 3856 12:19:03.513199  ============================================================== 

 3857 12:19:03.516488  Config description: 

 3858 12:19:03.526763  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3859 12:19:03.533338  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3860 12:19:03.536501  SELPH_MODE            0: By rank         1: By Phase 

 3861 12:19:03.542899  ============================================================== 

 3862 12:19:03.546785  GAT_TRACK_EN                 =  1

 3863 12:19:03.549896  RX_GATING_MODE               =  2

 3864 12:19:03.553058  RX_GATING_TRACK_MODE         =  2

 3865 12:19:03.556200  SELPH_MODE                   =  1

 3866 12:19:03.556289  PICG_EARLY_EN                =  1

 3867 12:19:03.559409  VALID_LAT_VALUE              =  1

 3868 12:19:03.566437  ============================================================== 

 3869 12:19:03.569846  Enter into Gating configuration >>>> 

 3870 12:19:03.572775  Exit from Gating configuration <<<< 

 3871 12:19:03.576519  Enter into  DVFS_PRE_config >>>>> 

 3872 12:19:03.586273  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3873 12:19:03.589328  Exit from  DVFS_PRE_config <<<<< 

 3874 12:19:03.593056  Enter into PICG configuration >>>> 

 3875 12:19:03.596039  Exit from PICG configuration <<<< 

 3876 12:19:03.599758  [RX_INPUT] configuration >>>>> 

 3877 12:19:03.602865  [RX_INPUT] configuration <<<<< 

 3878 12:19:03.605833  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3879 12:19:03.612590  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3880 12:19:03.619484  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3881 12:19:03.625786  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3882 12:19:03.632856  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3883 12:19:03.636270  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3884 12:19:03.642645  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3885 12:19:03.645746  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3886 12:19:03.649485  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3887 12:19:03.652728  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3888 12:19:03.659317  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3889 12:19:03.662516  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3890 12:19:03.665637  =================================== 

 3891 12:19:03.669426  LPDDR4 DRAM CONFIGURATION

 3892 12:19:03.672598  =================================== 

 3893 12:19:03.672688  EX_ROW_EN[0]    = 0x0

 3894 12:19:03.675746  EX_ROW_EN[1]    = 0x0

 3895 12:19:03.675832  LP4Y_EN      = 0x0

 3896 12:19:03.679463  WORK_FSP     = 0x0

 3897 12:19:03.679573  WL           = 0x2

 3898 12:19:03.682204  RL           = 0x2

 3899 12:19:03.682302  BL           = 0x2

 3900 12:19:03.686027  RPST         = 0x0

 3901 12:19:03.689246  RD_PRE       = 0x0

 3902 12:19:03.689364  WR_PRE       = 0x1

 3903 12:19:03.692613  WR_PST       = 0x0

 3904 12:19:03.692728  DBI_WR       = 0x0

 3905 12:19:03.695456  DBI_RD       = 0x0

 3906 12:19:03.695562  OTF          = 0x1

 3907 12:19:03.699017  =================================== 

 3908 12:19:03.702734  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3909 12:19:03.709125  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3910 12:19:03.712286  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3911 12:19:03.715382  =================================== 

 3912 12:19:03.718970  LPDDR4 DRAM CONFIGURATION

 3913 12:19:03.722166  =================================== 

 3914 12:19:03.722277  EX_ROW_EN[0]    = 0x10

 3915 12:19:03.725786  EX_ROW_EN[1]    = 0x0

 3916 12:19:03.725864  LP4Y_EN      = 0x0

 3917 12:19:03.728908  WORK_FSP     = 0x0

 3918 12:19:03.728986  WL           = 0x2

 3919 12:19:03.732579  RL           = 0x2

 3920 12:19:03.732656  BL           = 0x2

 3921 12:19:03.735886  RPST         = 0x0

 3922 12:19:03.735963  RD_PRE       = 0x0

 3923 12:19:03.739358  WR_PRE       = 0x1

 3924 12:19:03.739462  WR_PST       = 0x0

 3925 12:19:03.742465  DBI_WR       = 0x0

 3926 12:19:03.742555  DBI_RD       = 0x0

 3927 12:19:03.745811  OTF          = 0x1

 3928 12:19:03.748743  =================================== 

 3929 12:19:03.755347  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3930 12:19:03.758756  nWR fixed to 30

 3931 12:19:03.762522  [ModeRegInit_LP4] CH0 RK0

 3932 12:19:03.762603  [ModeRegInit_LP4] CH0 RK1

 3933 12:19:03.765659  [ModeRegInit_LP4] CH1 RK0

 3934 12:19:03.768899  [ModeRegInit_LP4] CH1 RK1

 3935 12:19:03.768976  match AC timing 17

 3936 12:19:03.775314  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3937 12:19:03.779171  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3938 12:19:03.782300  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3939 12:19:03.788669  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3940 12:19:03.792348  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3941 12:19:03.792451  ==

 3942 12:19:03.795672  Dram Type= 6, Freq= 0, CH_0, rank 0

 3943 12:19:03.799033  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3944 12:19:03.799153  ==

 3945 12:19:03.805456  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3946 12:19:03.812211  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 3947 12:19:03.815202  [CA 0] Center 35 (5~66) winsize 62

 3948 12:19:03.819015  [CA 1] Center 35 (5~66) winsize 62

 3949 12:19:03.821995  [CA 2] Center 33 (3~64) winsize 62

 3950 12:19:03.824997  [CA 3] Center 33 (2~64) winsize 63

 3951 12:19:03.828623  [CA 4] Center 33 (2~64) winsize 63

 3952 12:19:03.832236  [CA 5] Center 32 (2~63) winsize 62

 3953 12:19:03.832310  

 3954 12:19:03.835395  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3955 12:19:03.835465  

 3956 12:19:03.838594  [CATrainingPosCal] consider 1 rank data

 3957 12:19:03.842373  u2DelayCellTimex100 = 270/100 ps

 3958 12:19:03.845404  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3959 12:19:03.848682  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3960 12:19:03.851834  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3961 12:19:03.855432  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3962 12:19:03.858527  CA4 delay=33 (2~64),Diff = 1 PI (9 cell)

 3963 12:19:03.862234  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3964 12:19:03.862324  

 3965 12:19:03.868667  CA PerBit enable=1, Macro0, CA PI delay=32

 3966 12:19:03.868767  

 3967 12:19:03.871879  [CBTSetCACLKResult] CA Dly = 32

 3968 12:19:03.871967  CS Dly: 4 (0~35)

 3969 12:19:03.872032  ==

 3970 12:19:03.875062  Dram Type= 6, Freq= 0, CH_0, rank 1

 3971 12:19:03.878463  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3972 12:19:03.878562  ==

 3973 12:19:03.885399  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3974 12:19:03.892504  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3975 12:19:03.895633  [CA 0] Center 35 (5~66) winsize 62

 3976 12:19:03.898893  [CA 1] Center 35 (5~66) winsize 62

 3977 12:19:03.901790  [CA 2] Center 34 (3~65) winsize 63

 3978 12:19:03.904880  [CA 3] Center 33 (3~64) winsize 62

 3979 12:19:03.908470  [CA 4] Center 32 (2~63) winsize 62

 3980 12:19:03.911305  [CA 5] Center 32 (2~63) winsize 62

 3981 12:19:03.911400  

 3982 12:19:03.914768  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3983 12:19:03.914886  

 3984 12:19:03.918602  [CATrainingPosCal] consider 2 rank data

 3985 12:19:03.921371  u2DelayCellTimex100 = 270/100 ps

 3986 12:19:03.924608  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3987 12:19:03.928003  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3988 12:19:03.931570  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3989 12:19:03.935221  CA3 delay=33 (3~64),Diff = 1 PI (9 cell)

 3990 12:19:03.941354  CA4 delay=32 (2~63),Diff = 0 PI (0 cell)

 3991 12:19:03.944570  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3992 12:19:03.944660  

 3993 12:19:03.948257  CA PerBit enable=1, Macro0, CA PI delay=32

 3994 12:19:03.948349  

 3995 12:19:03.951394  [CBTSetCACLKResult] CA Dly = 32

 3996 12:19:03.951484  CS Dly: 4 (0~36)

 3997 12:19:03.951552  

 3998 12:19:03.954628  ----->DramcWriteLeveling(PI) begin...

 3999 12:19:03.954709  ==

 4000 12:19:03.958162  Dram Type= 6, Freq= 0, CH_0, rank 0

 4001 12:19:03.964400  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4002 12:19:03.964491  ==

 4003 12:19:03.968315  Write leveling (Byte 0): 34 => 34

 4004 12:19:03.971368  Write leveling (Byte 1): 32 => 32

 4005 12:19:03.971453  DramcWriteLeveling(PI) end<-----

 4006 12:19:03.971521  

 4007 12:19:03.974391  ==

 4008 12:19:03.978043  Dram Type= 6, Freq= 0, CH_0, rank 0

 4009 12:19:03.981100  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4010 12:19:03.981190  ==

 4011 12:19:03.984455  [Gating] SW mode calibration

 4012 12:19:03.990900  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4013 12:19:03.994214  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4014 12:19:04.001217   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4015 12:19:04.004296   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4016 12:19:04.008088   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4017 12:19:04.014515   0  9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)

 4018 12:19:04.017429   0  9 16 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)

 4019 12:19:04.021212   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4020 12:19:04.027644   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4021 12:19:04.030684   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4022 12:19:04.034077   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4023 12:19:04.041208   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4024 12:19:04.043948   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4025 12:19:04.047431   0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)

 4026 12:19:04.054338   0 10 16 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)

 4027 12:19:04.057411   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4028 12:19:04.060547   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4029 12:19:04.067268   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4030 12:19:04.071084   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4031 12:19:04.074386   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4032 12:19:04.080609   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4033 12:19:04.083785   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4034 12:19:04.087164   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4035 12:19:04.093757   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4036 12:19:04.097378   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4037 12:19:04.100390   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4038 12:19:04.103877   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4039 12:19:04.110606   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4040 12:19:04.113753   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4041 12:19:04.116977   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4042 12:19:04.123820   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4043 12:19:04.126938   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4044 12:19:04.130710   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4045 12:19:04.137328   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4046 12:19:04.140780   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4047 12:19:04.143897   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4048 12:19:04.150478   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4049 12:19:04.154038   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 4050 12:19:04.157004  Total UI for P1: 0, mck2ui 16

 4051 12:19:04.160656  best dqsien dly found for B0: ( 0, 13, 10)

 4052 12:19:04.163856   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4053 12:19:04.170305   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4054 12:19:04.170417  Total UI for P1: 0, mck2ui 16

 4055 12:19:04.177463  best dqsien dly found for B1: ( 0, 13, 16)

 4056 12:19:04.180718  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4057 12:19:04.183923  best DQS1 dly(MCK, UI, PI) = (0, 13, 16)

 4058 12:19:04.184020  

 4059 12:19:04.186939  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4060 12:19:04.190646  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4061 12:19:04.193626  [Gating] SW calibration Done

 4062 12:19:04.193721  ==

 4063 12:19:04.197253  Dram Type= 6, Freq= 0, CH_0, rank 0

 4064 12:19:04.200559  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4065 12:19:04.200655  ==

 4066 12:19:04.203568  RX Vref Scan: 0

 4067 12:19:04.203679  

 4068 12:19:04.203747  RX Vref 0 -> 0, step: 1

 4069 12:19:04.203809  

 4070 12:19:04.206891  RX Delay -230 -> 252, step: 16

 4071 12:19:04.213563  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4072 12:19:04.217009  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4073 12:19:04.220187  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4074 12:19:04.223347  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4075 12:19:04.226774  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4076 12:19:04.233751  iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304

 4077 12:19:04.236739  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4078 12:19:04.240549  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4079 12:19:04.243521  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4080 12:19:04.247067  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4081 12:19:04.253286  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4082 12:19:04.256959  iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304

 4083 12:19:04.260478  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4084 12:19:04.263399  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4085 12:19:04.270391  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4086 12:19:04.273444  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4087 12:19:04.273540  ==

 4088 12:19:04.276626  Dram Type= 6, Freq= 0, CH_0, rank 0

 4089 12:19:04.280218  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4090 12:19:04.280311  ==

 4091 12:19:04.283303  DQS Delay:

 4092 12:19:04.283395  DQS0 = 0, DQS1 = 0

 4093 12:19:04.287118  DQM Delay:

 4094 12:19:04.287205  DQM0 = 53, DQM1 = 47

 4095 12:19:04.287276  DQ Delay:

 4096 12:19:04.290172  DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49

 4097 12:19:04.293326  DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57

 4098 12:19:04.296746  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =49

 4099 12:19:04.300075  DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57

 4100 12:19:04.300162  

 4101 12:19:04.300229  

 4102 12:19:04.300290  ==

 4103 12:19:04.303175  Dram Type= 6, Freq= 0, CH_0, rank 0

 4104 12:19:04.310119  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4105 12:19:04.310200  ==

 4106 12:19:04.310270  

 4107 12:19:04.310335  

 4108 12:19:04.310395  	TX Vref Scan disable

 4109 12:19:04.314142   == TX Byte 0 ==

 4110 12:19:04.317350  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4111 12:19:04.324105  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4112 12:19:04.324203   == TX Byte 1 ==

 4113 12:19:04.327191  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4114 12:19:04.333693  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4115 12:19:04.333799  ==

 4116 12:19:04.336904  Dram Type= 6, Freq= 0, CH_0, rank 0

 4117 12:19:04.339863  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4118 12:19:04.339955  ==

 4119 12:19:04.340023  

 4120 12:19:04.340086  

 4121 12:19:04.343345  	TX Vref Scan disable

 4122 12:19:04.346515   == TX Byte 0 ==

 4123 12:19:04.350039  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4124 12:19:04.353666  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4125 12:19:04.356684   == TX Byte 1 ==

 4126 12:19:04.359792  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4127 12:19:04.363386  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4128 12:19:04.363473  

 4129 12:19:04.363539  [DATLAT]

 4130 12:19:04.366415  Freq=600, CH0 RK0

 4131 12:19:04.366502  

 4132 12:19:04.370088  DATLAT Default: 0x9

 4133 12:19:04.370180  0, 0xFFFF, sum = 0

 4134 12:19:04.373075  1, 0xFFFF, sum = 0

 4135 12:19:04.373166  2, 0xFFFF, sum = 0

 4136 12:19:04.376258  3, 0xFFFF, sum = 0

 4137 12:19:04.376350  4, 0xFFFF, sum = 0

 4138 12:19:04.380065  5, 0xFFFF, sum = 0

 4139 12:19:04.380155  6, 0xFFFF, sum = 0

 4140 12:19:04.383307  7, 0xFFFF, sum = 0

 4141 12:19:04.383402  8, 0x0, sum = 1

 4142 12:19:04.386381  9, 0x0, sum = 2

 4143 12:19:04.386469  10, 0x0, sum = 3

 4144 12:19:04.389978  11, 0x0, sum = 4

 4145 12:19:04.390076  best_step = 9

 4146 12:19:04.390141  

 4147 12:19:04.390203  ==

 4148 12:19:04.393142  Dram Type= 6, Freq= 0, CH_0, rank 0

 4149 12:19:04.396329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4150 12:19:04.396409  ==

 4151 12:19:04.400019  RX Vref Scan: 1

 4152 12:19:04.400101  

 4153 12:19:04.403164  RX Vref 0 -> 0, step: 1

 4154 12:19:04.403257  

 4155 12:19:04.403322  RX Delay -163 -> 252, step: 8

 4156 12:19:04.403383  

 4157 12:19:04.406288  Set Vref, RX VrefLevel [Byte0]: 55

 4158 12:19:04.409457                           [Byte1]: 46

 4159 12:19:04.414000  

 4160 12:19:04.414113  Final RX Vref Byte 0 = 55 to rank0

 4161 12:19:04.417669  Final RX Vref Byte 1 = 46 to rank0

 4162 12:19:04.420761  Final RX Vref Byte 0 = 55 to rank1

 4163 12:19:04.424604  Final RX Vref Byte 1 = 46 to rank1==

 4164 12:19:04.427707  Dram Type= 6, Freq= 0, CH_0, rank 0

 4165 12:19:04.434123  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4166 12:19:04.434235  ==

 4167 12:19:04.434308  DQS Delay:

 4168 12:19:04.434373  DQS0 = 0, DQS1 = 0

 4169 12:19:04.437845  DQM Delay:

 4170 12:19:04.437924  DQM0 = 52, DQM1 = 46

 4171 12:19:04.440983  DQ Delay:

 4172 12:19:04.444086  DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48

 4173 12:19:04.444169  DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60

 4174 12:19:04.447721  DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40

 4175 12:19:04.454180  DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52

 4176 12:19:04.454283  

 4177 12:19:04.454349  

 4178 12:19:04.460603  [DQSOSCAuto] RK0, (LSB)MR18= 0x7568, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 387 ps

 4179 12:19:04.463926  CH0 RK0: MR19=808, MR18=7568

 4180 12:19:04.470758  CH0_RK0: MR19=0x808, MR18=0x7568, DQSOSC=387, MR23=63, INC=175, DEC=116

 4181 12:19:04.470856  

 4182 12:19:04.473850  ----->DramcWriteLeveling(PI) begin...

 4183 12:19:04.473933  ==

 4184 12:19:04.477446  Dram Type= 6, Freq= 0, CH_0, rank 1

 4185 12:19:04.480929  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4186 12:19:04.481035  ==

 4187 12:19:04.484250  Write leveling (Byte 0): 34 => 34

 4188 12:19:04.487492  Write leveling (Byte 1): 33 => 33

 4189 12:19:04.490938  DramcWriteLeveling(PI) end<-----

 4190 12:19:04.491025  

 4191 12:19:04.491091  ==

 4192 12:19:04.493935  Dram Type= 6, Freq= 0, CH_0, rank 1

 4193 12:19:04.497530  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4194 12:19:04.497614  ==

 4195 12:19:04.501046  [Gating] SW mode calibration

 4196 12:19:04.507709  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4197 12:19:04.513895  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4198 12:19:04.517626   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4199 12:19:04.520824   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4200 12:19:04.527202   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4201 12:19:04.531104   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 4202 12:19:04.534203   0  9 16 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)

 4203 12:19:04.540555   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4204 12:19:04.544151   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4205 12:19:04.547298   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4206 12:19:04.554082   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4207 12:19:04.557351   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4208 12:19:04.560429   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4209 12:19:04.567343   0 10 12 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)

 4210 12:19:04.570258   0 10 16 | B1->B0 | 4040 4444 | 0 0 | (0 0) (0 0)

 4211 12:19:04.573879   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4212 12:19:04.580527   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4213 12:19:04.583927   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4214 12:19:04.587225   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4215 12:19:04.594041   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4216 12:19:04.597098   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4217 12:19:04.600491   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4218 12:19:04.607181   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4219 12:19:04.610443   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4220 12:19:04.613933   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4221 12:19:04.617225   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4222 12:19:04.624104   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4223 12:19:04.627484   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4224 12:19:04.630714   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4225 12:19:04.637276   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4226 12:19:04.640481   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4227 12:19:04.643607   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4228 12:19:04.650683   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4229 12:19:04.653536   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4230 12:19:04.656815   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4231 12:19:04.663724   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4232 12:19:04.666786   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4233 12:19:04.669927   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4234 12:19:04.676787   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4235 12:19:04.679856  Total UI for P1: 0, mck2ui 16

 4236 12:19:04.683521  best dqsien dly found for B0: ( 0, 13, 14)

 4237 12:19:04.686766  Total UI for P1: 0, mck2ui 16

 4238 12:19:04.689979  best dqsien dly found for B1: ( 0, 13, 14)

 4239 12:19:04.693766  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4240 12:19:04.696900  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4241 12:19:04.696981  

 4242 12:19:04.700176  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4243 12:19:04.703111  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4244 12:19:04.706831  [Gating] SW calibration Done

 4245 12:19:04.706905  ==

 4246 12:19:04.710041  Dram Type= 6, Freq= 0, CH_0, rank 1

 4247 12:19:04.713668  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4248 12:19:04.713748  ==

 4249 12:19:04.716596  RX Vref Scan: 0

 4250 12:19:04.716667  

 4251 12:19:04.716733  RX Vref 0 -> 0, step: 1

 4252 12:19:04.719926  

 4253 12:19:04.720002  RX Delay -230 -> 252, step: 16

 4254 12:19:04.726889  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4255 12:19:04.729863  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4256 12:19:04.733392  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4257 12:19:04.736906  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4258 12:19:04.739872  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4259 12:19:04.747038  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4260 12:19:04.750061  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4261 12:19:04.753413  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4262 12:19:04.756812  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4263 12:19:04.763085  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4264 12:19:04.766964  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4265 12:19:04.769931  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4266 12:19:04.773576  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4267 12:19:04.780331  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4268 12:19:04.783311  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4269 12:19:04.786515  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4270 12:19:04.786600  ==

 4271 12:19:04.790320  Dram Type= 6, Freq= 0, CH_0, rank 1

 4272 12:19:04.793652  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4273 12:19:04.793729  ==

 4274 12:19:04.796639  DQS Delay:

 4275 12:19:04.796715  DQS0 = 0, DQS1 = 0

 4276 12:19:04.799783  DQM Delay:

 4277 12:19:04.799862  DQM0 = 48, DQM1 = 42

 4278 12:19:04.799964  DQ Delay:

 4279 12:19:04.803520  DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41

 4280 12:19:04.806751  DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57

 4281 12:19:04.809900  DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33

 4282 12:19:04.813008  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49

 4283 12:19:04.813085  

 4284 12:19:04.813183  

 4285 12:19:04.816241  ==

 4286 12:19:04.816312  Dram Type= 6, Freq= 0, CH_0, rank 1

 4287 12:19:04.823016  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4288 12:19:04.823090  ==

 4289 12:19:04.823194  

 4290 12:19:04.823255  

 4291 12:19:04.826685  	TX Vref Scan disable

 4292 12:19:04.826775   == TX Byte 0 ==

 4293 12:19:04.829470  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4294 12:19:04.836403  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4295 12:19:04.836480   == TX Byte 1 ==

 4296 12:19:04.839889  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4297 12:19:04.846296  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4298 12:19:04.846380  ==

 4299 12:19:04.849953  Dram Type= 6, Freq= 0, CH_0, rank 1

 4300 12:19:04.853040  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4301 12:19:04.853115  ==

 4302 12:19:04.853177  

 4303 12:19:04.853253  

 4304 12:19:04.856243  	TX Vref Scan disable

 4305 12:19:04.859811   == TX Byte 0 ==

 4306 12:19:04.863290  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4307 12:19:04.866501  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4308 12:19:04.869690   == TX Byte 1 ==

 4309 12:19:04.872916  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4310 12:19:04.876546  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4311 12:19:04.876626  

 4312 12:19:04.879807  [DATLAT]

 4313 12:19:04.879878  Freq=600, CH0 RK1

 4314 12:19:04.879940  

 4315 12:19:04.883312  DATLAT Default: 0x9

 4316 12:19:04.883420  0, 0xFFFF, sum = 0

 4317 12:19:04.886142  1, 0xFFFF, sum = 0

 4318 12:19:04.886212  2, 0xFFFF, sum = 0

 4319 12:19:04.889734  3, 0xFFFF, sum = 0

 4320 12:19:04.889821  4, 0xFFFF, sum = 0

 4321 12:19:04.892884  5, 0xFFFF, sum = 0

 4322 12:19:04.892968  6, 0xFFFF, sum = 0

 4323 12:19:04.896507  7, 0xFFFF, sum = 0

 4324 12:19:04.896591  8, 0x0, sum = 1

 4325 12:19:04.899601  9, 0x0, sum = 2

 4326 12:19:04.899710  10, 0x0, sum = 3

 4327 12:19:04.902654  11, 0x0, sum = 4

 4328 12:19:04.902737  best_step = 9

 4329 12:19:04.902802  

 4330 12:19:04.902861  ==

 4331 12:19:04.906503  Dram Type= 6, Freq= 0, CH_0, rank 1

 4332 12:19:04.909689  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4333 12:19:04.909773  ==

 4334 12:19:04.912756  RX Vref Scan: 0

 4335 12:19:04.912838  

 4336 12:19:04.916433  RX Vref 0 -> 0, step: 1

 4337 12:19:04.916517  

 4338 12:19:04.916582  RX Delay -163 -> 252, step: 8

 4339 12:19:04.923980  iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288

 4340 12:19:04.927657  iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280

 4341 12:19:04.930736  iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288

 4342 12:19:04.933845  iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288

 4343 12:19:04.937535  iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280

 4344 12:19:04.943853  iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288

 4345 12:19:04.947237  iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272

 4346 12:19:04.950958  iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272

 4347 12:19:04.954368  iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288

 4348 12:19:04.957296  iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280

 4349 12:19:04.964104  iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280

 4350 12:19:04.967368  iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280

 4351 12:19:04.970528  iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272

 4352 12:19:04.974283  iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280

 4353 12:19:04.980829  iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280

 4354 12:19:04.984205  iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288

 4355 12:19:04.984288  ==

 4356 12:19:04.987495  Dram Type= 6, Freq= 0, CH_0, rank 1

 4357 12:19:04.990461  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4358 12:19:04.990538  ==

 4359 12:19:04.993712  DQS Delay:

 4360 12:19:04.993787  DQS0 = 0, DQS1 = 0

 4361 12:19:04.993851  DQM Delay:

 4362 12:19:04.997486  DQM0 = 54, DQM1 = 45

 4363 12:19:04.997605  DQ Delay:

 4364 12:19:05.000785  DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52

 4365 12:19:05.003864  DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60

 4366 12:19:05.007417  DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40

 4367 12:19:05.010410  DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52

 4368 12:19:05.010494  

 4369 12:19:05.010559  

 4370 12:19:05.020285  [DQSOSCAuto] RK1, (LSB)MR18= 0x6728, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps

 4371 12:19:05.020367  CH0 RK1: MR19=808, MR18=6728

 4372 12:19:05.027336  CH0_RK1: MR19=0x808, MR18=0x6728, DQSOSC=390, MR23=63, INC=172, DEC=114

 4373 12:19:05.030518  [RxdqsGatingPostProcess] freq 600

 4374 12:19:05.036908  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4375 12:19:05.040772  Pre-setting of DQS Precalculation

 4376 12:19:05.043900  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4377 12:19:05.043975  ==

 4378 12:19:05.046876  Dram Type= 6, Freq= 0, CH_1, rank 0

 4379 12:19:05.050737  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4380 12:19:05.053870  ==

 4381 12:19:05.057312  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4382 12:19:05.063918  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4383 12:19:05.066786  [CA 0] Center 36 (5~67) winsize 63

 4384 12:19:05.070256  [CA 1] Center 36 (6~67) winsize 62

 4385 12:19:05.073363  [CA 2] Center 35 (4~66) winsize 63

 4386 12:19:05.077184  [CA 3] Center 34 (4~65) winsize 62

 4387 12:19:05.080334  [CA 4] Center 34 (4~65) winsize 62

 4388 12:19:05.083580  [CA 5] Center 34 (4~65) winsize 62

 4389 12:19:05.083714  

 4390 12:19:05.086699  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4391 12:19:05.086798  

 4392 12:19:05.090283  [CATrainingPosCal] consider 1 rank data

 4393 12:19:05.093752  u2DelayCellTimex100 = 270/100 ps

 4394 12:19:05.097254  CA0 delay=36 (5~67),Diff = 2 PI (19 cell)

 4395 12:19:05.100385  CA1 delay=36 (6~67),Diff = 2 PI (19 cell)

 4396 12:19:05.103469  CA2 delay=35 (4~66),Diff = 1 PI (9 cell)

 4397 12:19:05.110064  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4398 12:19:05.113645  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4399 12:19:05.116992  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 4400 12:19:05.117068  

 4401 12:19:05.120269  CA PerBit enable=1, Macro0, CA PI delay=34

 4402 12:19:05.120342  

 4403 12:19:05.123615  [CBTSetCACLKResult] CA Dly = 34

 4404 12:19:05.123731  CS Dly: 5 (0~36)

 4405 12:19:05.123798  ==

 4406 12:19:05.126600  Dram Type= 6, Freq= 0, CH_1, rank 1

 4407 12:19:05.133307  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4408 12:19:05.133412  ==

 4409 12:19:05.137133  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4410 12:19:05.143388  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4411 12:19:05.146512  [CA 0] Center 36 (6~67) winsize 62

 4412 12:19:05.150130  [CA 1] Center 36 (6~67) winsize 62

 4413 12:19:05.153336  [CA 2] Center 35 (5~66) winsize 62

 4414 12:19:05.156443  [CA 3] Center 35 (4~66) winsize 63

 4415 12:19:05.160202  [CA 4] Center 35 (4~66) winsize 63

 4416 12:19:05.163343  [CA 5] Center 34 (4~65) winsize 62

 4417 12:19:05.163437  

 4418 12:19:05.166400  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4419 12:19:05.166496  

 4420 12:19:05.169878  [CATrainingPosCal] consider 2 rank data

 4421 12:19:05.173311  u2DelayCellTimex100 = 270/100 ps

 4422 12:19:05.176940  CA0 delay=36 (6~67),Diff = 2 PI (19 cell)

 4423 12:19:05.180085  CA1 delay=36 (6~67),Diff = 2 PI (19 cell)

 4424 12:19:05.186742  CA2 delay=35 (5~66),Diff = 1 PI (9 cell)

 4425 12:19:05.189924  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4426 12:19:05.193158  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4427 12:19:05.196207  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 4428 12:19:05.196277  

 4429 12:19:05.199738  CA PerBit enable=1, Macro0, CA PI delay=34

 4430 12:19:05.199807  

 4431 12:19:05.203176  [CBTSetCACLKResult] CA Dly = 34

 4432 12:19:05.203243  CS Dly: 6 (0~38)

 4433 12:19:05.203308  

 4434 12:19:05.206655  ----->DramcWriteLeveling(PI) begin...

 4435 12:19:05.209882  ==

 4436 12:19:05.212910  Dram Type= 6, Freq= 0, CH_1, rank 0

 4437 12:19:05.216481  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4438 12:19:05.216556  ==

 4439 12:19:05.219539  Write leveling (Byte 0): 29 => 29

 4440 12:19:05.223236  Write leveling (Byte 1): 30 => 30

 4441 12:19:05.226315  DramcWriteLeveling(PI) end<-----

 4442 12:19:05.226387  

 4443 12:19:05.226454  ==

 4444 12:19:05.229886  Dram Type= 6, Freq= 0, CH_1, rank 0

 4445 12:19:05.233162  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4446 12:19:05.233237  ==

 4447 12:19:05.236585  [Gating] SW mode calibration

 4448 12:19:05.243068  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4449 12:19:05.249345  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4450 12:19:05.253209   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4451 12:19:05.256330   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4452 12:19:05.259544   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 4453 12:19:05.266489   0  9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)

 4454 12:19:05.269687   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4455 12:19:05.272936   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4456 12:19:05.279603   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4457 12:19:05.283335   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4458 12:19:05.286564   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4459 12:19:05.292852   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4460 12:19:05.296249   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4461 12:19:05.299848   0 10 12 | B1->B0 | 3535 3939 | 0 0 | (0 0) (0 0)

 4462 12:19:05.306683   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4463 12:19:05.309781   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4464 12:19:05.312903   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4465 12:19:05.319861   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4466 12:19:05.323074   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4467 12:19:05.326070   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4468 12:19:05.333222   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4469 12:19:05.336257   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4470 12:19:05.339426   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4471 12:19:05.346198   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4472 12:19:05.349729   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4473 12:19:05.352763   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4474 12:19:05.356275   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4475 12:19:05.363030   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4476 12:19:05.366608   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4477 12:19:05.369865   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4478 12:19:05.376243   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4479 12:19:05.379384   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4480 12:19:05.382533   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4481 12:19:05.389424   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4482 12:19:05.393176   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4483 12:19:05.396325   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4484 12:19:05.402965   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4485 12:19:05.405875   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4486 12:19:05.409287   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4487 12:19:05.412994  Total UI for P1: 0, mck2ui 16

 4488 12:19:05.416099  best dqsien dly found for B0: ( 0, 13, 10)

 4489 12:19:05.423047   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4490 12:19:05.423126  Total UI for P1: 0, mck2ui 16

 4491 12:19:05.429330  best dqsien dly found for B1: ( 0, 13, 12)

 4492 12:19:05.432912  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4493 12:19:05.436231  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4494 12:19:05.436309  

 4495 12:19:05.439561  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4496 12:19:05.442699  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4497 12:19:05.446127  [Gating] SW calibration Done

 4498 12:19:05.446205  ==

 4499 12:19:05.449217  Dram Type= 6, Freq= 0, CH_1, rank 0

 4500 12:19:05.452442  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4501 12:19:05.452542  ==

 4502 12:19:05.456141  RX Vref Scan: 0

 4503 12:19:05.456211  

 4504 12:19:05.456293  RX Vref 0 -> 0, step: 1

 4505 12:19:05.456366  

 4506 12:19:05.459073  RX Delay -230 -> 252, step: 16

 4507 12:19:05.465990  iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304

 4508 12:19:05.469001  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4509 12:19:05.472446  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4510 12:19:05.475750  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4511 12:19:05.479357  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4512 12:19:05.485762  iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304

 4513 12:19:05.489407  iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304

 4514 12:19:05.492692  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4515 12:19:05.495767  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4516 12:19:05.498938  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4517 12:19:05.505792  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4518 12:19:05.508862  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4519 12:19:05.512736  iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304

 4520 12:19:05.515673  iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288

 4521 12:19:05.522081  iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288

 4522 12:19:05.525986  iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304

 4523 12:19:05.526072  ==

 4524 12:19:05.528891  Dram Type= 6, Freq= 0, CH_1, rank 0

 4525 12:19:05.532444  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4526 12:19:05.532531  ==

 4527 12:19:05.535531  DQS Delay:

 4528 12:19:05.535624  DQS0 = 0, DQS1 = 0

 4529 12:19:05.535711  DQM Delay:

 4530 12:19:05.538711  DQM0 = 52, DQM1 = 50

 4531 12:19:05.538780  DQ Delay:

 4532 12:19:05.542379  DQ0 =65, DQ1 =41, DQ2 =41, DQ3 =49

 4533 12:19:05.545585  DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =41

 4534 12:19:05.549274  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4535 12:19:05.552054  DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65

 4536 12:19:05.552124  

 4537 12:19:05.552184  

 4538 12:19:05.552247  ==

 4539 12:19:05.555303  Dram Type= 6, Freq= 0, CH_1, rank 0

 4540 12:19:05.562061  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4541 12:19:05.562169  ==

 4542 12:19:05.562359  

 4543 12:19:05.562420  

 4544 12:19:05.562489  	TX Vref Scan disable

 4545 12:19:05.565542   == TX Byte 0 ==

 4546 12:19:05.569180  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4547 12:19:05.575540  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4548 12:19:05.575674   == TX Byte 1 ==

 4549 12:19:05.579228  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4550 12:19:05.585727  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4551 12:19:05.585834  ==

 4552 12:19:05.589066  Dram Type= 6, Freq= 0, CH_1, rank 0

 4553 12:19:05.592556  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4554 12:19:05.592668  ==

 4555 12:19:05.592762  

 4556 12:19:05.592850  

 4557 12:19:05.595530  	TX Vref Scan disable

 4558 12:19:05.595632   == TX Byte 0 ==

 4559 12:19:05.602387  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4560 12:19:05.605582  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4561 12:19:05.608818   == TX Byte 1 ==

 4562 12:19:05.611876  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4563 12:19:05.615155  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4564 12:19:05.615224  

 4565 12:19:05.615286  [DATLAT]

 4566 12:19:05.618832  Freq=600, CH1 RK0

 4567 12:19:05.618899  

 4568 12:19:05.618958  DATLAT Default: 0x9

 4569 12:19:05.622536  0, 0xFFFF, sum = 0

 4570 12:19:05.622607  1, 0xFFFF, sum = 0

 4571 12:19:05.625645  2, 0xFFFF, sum = 0

 4572 12:19:05.625741  3, 0xFFFF, sum = 0

 4573 12:19:05.628820  4, 0xFFFF, sum = 0

 4574 12:19:05.632554  5, 0xFFFF, sum = 0

 4575 12:19:05.632625  6, 0xFFFF, sum = 0

 4576 12:19:05.635547  7, 0xFFFF, sum = 0

 4577 12:19:05.635648  8, 0x0, sum = 1

 4578 12:19:05.635739  9, 0x0, sum = 2

 4579 12:19:05.639070  10, 0x0, sum = 3

 4580 12:19:05.639166  11, 0x0, sum = 4

 4581 12:19:05.641918  best_step = 9

 4582 12:19:05.642014  

 4583 12:19:05.642100  ==

 4584 12:19:05.645650  Dram Type= 6, Freq= 0, CH_1, rank 0

 4585 12:19:05.649049  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4586 12:19:05.649130  ==

 4587 12:19:05.652241  RX Vref Scan: 1

 4588 12:19:05.652335  

 4589 12:19:05.652425  RX Vref 0 -> 0, step: 1

 4590 12:19:05.652511  

 4591 12:19:05.655402  RX Delay -163 -> 252, step: 8

 4592 12:19:05.655493  

 4593 12:19:05.658634  Set Vref, RX VrefLevel [Byte0]: 53

 4594 12:19:05.661718                           [Byte1]: 47

 4595 12:19:05.666187  

 4596 12:19:05.666281  Final RX Vref Byte 0 = 53 to rank0

 4597 12:19:05.669630  Final RX Vref Byte 1 = 47 to rank0

 4598 12:19:05.672463  Final RX Vref Byte 0 = 53 to rank1

 4599 12:19:05.676140  Final RX Vref Byte 1 = 47 to rank1==

 4600 12:19:05.679391  Dram Type= 6, Freq= 0, CH_1, rank 0

 4601 12:19:05.685944  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4602 12:19:05.686046  ==

 4603 12:19:05.686139  DQS Delay:

 4604 12:19:05.686227  DQS0 = 0, DQS1 = 0

 4605 12:19:05.689057  DQM Delay:

 4606 12:19:05.689151  DQM0 = 49, DQM1 = 45

 4607 12:19:05.692592  DQ Delay:

 4608 12:19:05.695799  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4609 12:19:05.698939  DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48

 4610 12:19:05.702781  DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40

 4611 12:19:05.706059  DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52

 4612 12:19:05.706158  

 4613 12:19:05.706245  

 4614 12:19:05.713043  [DQSOSCAuto] RK0, (LSB)MR18= 0x4d72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps

 4615 12:19:05.716020  CH1 RK0: MR19=808, MR18=4D72

 4616 12:19:05.722429  CH1_RK0: MR19=0x808, MR18=0x4D72, DQSOSC=388, MR23=63, INC=174, DEC=116

 4617 12:19:05.722506  

 4618 12:19:05.726218  ----->DramcWriteLeveling(PI) begin...

 4619 12:19:05.726316  ==

 4620 12:19:05.729434  Dram Type= 6, Freq= 0, CH_1, rank 1

 4621 12:19:05.732421  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4622 12:19:05.732490  ==

 4623 12:19:05.736297  Write leveling (Byte 0): 30 => 30

 4624 12:19:05.739359  Write leveling (Byte 1): 30 => 30

 4625 12:19:05.742483  DramcWriteLeveling(PI) end<-----

 4626 12:19:05.742578  

 4627 12:19:05.742668  ==

 4628 12:19:05.745606  Dram Type= 6, Freq= 0, CH_1, rank 1

 4629 12:19:05.749350  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4630 12:19:05.749443  ==

 4631 12:19:05.752522  [Gating] SW mode calibration

 4632 12:19:05.759056  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4633 12:19:05.766091  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4634 12:19:05.769211   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4635 12:19:05.772312   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4636 12:19:05.779177   0  9  8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)

 4637 12:19:05.782265   0  9 12 | B1->B0 | 2e2e 2e2e | 1 0 | (0 1) (0 1)

 4638 12:19:05.785679   0  9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 4639 12:19:05.792307   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4640 12:19:05.795507   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4641 12:19:05.799082   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4642 12:19:05.805961   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4643 12:19:05.809206   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4644 12:19:05.812235   0 10  8 | B1->B0 | 2625 2525 | 1 0 | (1 1) (0 0)

 4645 12:19:05.819340   0 10 12 | B1->B0 | 3a3a 3939 | 0 0 | (0 0) (0 0)

 4646 12:19:05.822613   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4647 12:19:05.825932   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4648 12:19:05.832448   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4649 12:19:05.835726   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4650 12:19:05.838811   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4651 12:19:05.845590   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4652 12:19:05.848784   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4653 12:19:05.852642   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4654 12:19:05.858936   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4655 12:19:05.862564   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4656 12:19:05.865724   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4657 12:19:05.872228   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4658 12:19:05.875479   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4659 12:19:05.878930   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4660 12:19:05.882122   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4661 12:19:05.889061   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4662 12:19:05.892184   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4663 12:19:05.895679   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4664 12:19:05.902087   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4665 12:19:05.905388   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4666 12:19:05.908782   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4667 12:19:05.915458   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4668 12:19:05.919254   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4669 12:19:05.922479   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4670 12:19:05.928723   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4671 12:19:05.928803  Total UI for P1: 0, mck2ui 16

 4672 12:19:05.935475  best dqsien dly found for B0: ( 0, 13, 12)

 4673 12:19:05.935580  Total UI for P1: 0, mck2ui 16

 4674 12:19:05.942370  best dqsien dly found for B1: ( 0, 13, 12)

 4675 12:19:05.945840  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4676 12:19:05.948674  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4677 12:19:05.948761  

 4678 12:19:05.952270  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4679 12:19:05.955290  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4680 12:19:05.958498  [Gating] SW calibration Done

 4681 12:19:05.958607  ==

 4682 12:19:05.962281  Dram Type= 6, Freq= 0, CH_1, rank 1

 4683 12:19:05.965303  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4684 12:19:05.965409  ==

 4685 12:19:05.968463  RX Vref Scan: 0

 4686 12:19:05.968611  

 4687 12:19:05.968720  RX Vref 0 -> 0, step: 1

 4688 12:19:05.968815  

 4689 12:19:05.972366  RX Delay -230 -> 252, step: 16

 4690 12:19:05.978663  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4691 12:19:05.981830  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4692 12:19:05.985268  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4693 12:19:05.988637  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4694 12:19:05.991846  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4695 12:19:05.998536  iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304

 4696 12:19:06.001648  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4697 12:19:06.005351  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4698 12:19:06.008400  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4699 12:19:06.014980  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4700 12:19:06.018464  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4701 12:19:06.021916  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4702 12:19:06.025084  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4703 12:19:06.031871  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4704 12:19:06.035012  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4705 12:19:06.038458  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4706 12:19:06.038538  ==

 4707 12:19:06.041506  Dram Type= 6, Freq= 0, CH_1, rank 1

 4708 12:19:06.044642  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4709 12:19:06.044720  ==

 4710 12:19:06.048196  DQS Delay:

 4711 12:19:06.048274  DQS0 = 0, DQS1 = 0

 4712 12:19:06.051341  DQM Delay:

 4713 12:19:06.051440  DQM0 = 50, DQM1 = 46

 4714 12:19:06.054937  DQ Delay:

 4715 12:19:06.055039  DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49

 4716 12:19:06.057845  DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49

 4717 12:19:06.061469  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4718 12:19:06.064587  DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57

 4719 12:19:06.064672  

 4720 12:19:06.064738  

 4721 12:19:06.067779  ==

 4722 12:19:06.071376  Dram Type= 6, Freq= 0, CH_1, rank 1

 4723 12:19:06.074585  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4724 12:19:06.074663  ==

 4725 12:19:06.074727  

 4726 12:19:06.074793  

 4727 12:19:06.077740  	TX Vref Scan disable

 4728 12:19:06.077821   == TX Byte 0 ==

 4729 12:19:06.084704  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4730 12:19:06.087870  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4731 12:19:06.087943   == TX Byte 1 ==

 4732 12:19:06.094890  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4733 12:19:06.097876  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4734 12:19:06.097977  ==

 4735 12:19:06.101494  Dram Type= 6, Freq= 0, CH_1, rank 1

 4736 12:19:06.104183  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4737 12:19:06.104259  ==

 4738 12:19:06.104323  

 4739 12:19:06.104388  

 4740 12:19:06.107900  	TX Vref Scan disable

 4741 12:19:06.111055   == TX Byte 0 ==

 4742 12:19:06.114544  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4743 12:19:06.117609  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4744 12:19:06.121182   == TX Byte 1 ==

 4745 12:19:06.124159  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4746 12:19:06.127608  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4747 12:19:06.127702  

 4748 12:19:06.130996  [DATLAT]

 4749 12:19:06.131074  Freq=600, CH1 RK1

 4750 12:19:06.131138  

 4751 12:19:06.134444  DATLAT Default: 0x9

 4752 12:19:06.134516  0, 0xFFFF, sum = 0

 4753 12:19:06.137523  1, 0xFFFF, sum = 0

 4754 12:19:06.137599  2, 0xFFFF, sum = 0

 4755 12:19:06.140610  3, 0xFFFF, sum = 0

 4756 12:19:06.140683  4, 0xFFFF, sum = 0

 4757 12:19:06.144406  5, 0xFFFF, sum = 0

 4758 12:19:06.144477  6, 0xFFFF, sum = 0

 4759 12:19:06.147517  7, 0xFFFF, sum = 0

 4760 12:19:06.147623  8, 0x0, sum = 1

 4761 12:19:06.150793  9, 0x0, sum = 2

 4762 12:19:06.150893  10, 0x0, sum = 3

 4763 12:19:06.153882  11, 0x0, sum = 4

 4764 12:19:06.153956  best_step = 9

 4765 12:19:06.154023  

 4766 12:19:06.154083  ==

 4767 12:19:06.157640  Dram Type= 6, Freq= 0, CH_1, rank 1

 4768 12:19:06.164215  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4769 12:19:06.164293  ==

 4770 12:19:06.164359  RX Vref Scan: 0

 4771 12:19:06.164419  

 4772 12:19:06.167627  RX Vref 0 -> 0, step: 1

 4773 12:19:06.167750  

 4774 12:19:06.170656  RX Delay -163 -> 252, step: 8

 4775 12:19:06.173821  iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288

 4776 12:19:06.177646  iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288

 4777 12:19:06.184225  iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288

 4778 12:19:06.187336  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4779 12:19:06.190503  iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280

 4780 12:19:06.194261  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4781 12:19:06.197351  iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288

 4782 12:19:06.203828  iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296

 4783 12:19:06.207523  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4784 12:19:06.210584  iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296

 4785 12:19:06.213711  iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296

 4786 12:19:06.220520  iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288

 4787 12:19:06.223761  iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296

 4788 12:19:06.227160  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4789 12:19:06.230356  iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288

 4790 12:19:06.233640  iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288

 4791 12:19:06.233718  ==

 4792 12:19:06.237056  Dram Type= 6, Freq= 0, CH_1, rank 1

 4793 12:19:06.243582  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4794 12:19:06.243687  ==

 4795 12:19:06.243755  DQS Delay:

 4796 12:19:06.247320  DQS0 = 0, DQS1 = 0

 4797 12:19:06.247419  DQM Delay:

 4798 12:19:06.250406  DQM0 = 49, DQM1 = 45

 4799 12:19:06.250509  DQ Delay:

 4800 12:19:06.253647  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4801 12:19:06.257346  DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48

 4802 12:19:06.260314  DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36

 4803 12:19:06.263507  DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52

 4804 12:19:06.263608  

 4805 12:19:06.263692  

 4806 12:19:06.270390  [DQSOSCAuto] RK1, (LSB)MR18= 0x681e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps

 4807 12:19:06.273609  CH1 RK1: MR19=808, MR18=681E

 4808 12:19:06.280561  CH1_RK1: MR19=0x808, MR18=0x681E, DQSOSC=390, MR23=63, INC=172, DEC=114

 4809 12:19:06.283633  [RxdqsGatingPostProcess] freq 600

 4810 12:19:06.287234  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4811 12:19:06.290646  Pre-setting of DQS Precalculation

 4812 12:19:06.297575  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4813 12:19:06.303850  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4814 12:19:06.310212  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4815 12:19:06.310319  

 4816 12:19:06.310413  

 4817 12:19:06.313847  [Calibration Summary] 1200 Mbps

 4818 12:19:06.313948  CH 0, Rank 0

 4819 12:19:06.316940  SW Impedance     : PASS

 4820 12:19:06.320058  DUTY Scan        : NO K

 4821 12:19:06.320147  ZQ Calibration   : PASS

 4822 12:19:06.323841  Jitter Meter     : NO K

 4823 12:19:06.327100  CBT Training     : PASS

 4824 12:19:06.327186  Write leveling   : PASS

 4825 12:19:06.330212  RX DQS gating    : PASS

 4826 12:19:06.333765  RX DQ/DQS(RDDQC) : PASS

 4827 12:19:06.333847  TX DQ/DQS        : PASS

 4828 12:19:06.337177  RX DATLAT        : PASS

 4829 12:19:06.340532  RX DQ/DQS(Engine): PASS

 4830 12:19:06.340609  TX OE            : NO K

 4831 12:19:06.340710  All Pass.

 4832 12:19:06.343415  

 4833 12:19:06.343490  CH 0, Rank 1

 4834 12:19:06.346987  SW Impedance     : PASS

 4835 12:19:06.347063  DUTY Scan        : NO K

 4836 12:19:06.350243  ZQ Calibration   : PASS

 4837 12:19:06.350326  Jitter Meter     : NO K

 4838 12:19:06.353639  CBT Training     : PASS

 4839 12:19:06.356917  Write leveling   : PASS

 4840 12:19:06.356993  RX DQS gating    : PASS

 4841 12:19:06.360033  RX DQ/DQS(RDDQC) : PASS

 4842 12:19:06.363745  TX DQ/DQS        : PASS

 4843 12:19:06.363828  RX DATLAT        : PASS

 4844 12:19:06.366689  RX DQ/DQS(Engine): PASS

 4845 12:19:06.370501  TX OE            : NO K

 4846 12:19:06.370590  All Pass.

 4847 12:19:06.370677  

 4848 12:19:06.370758  CH 1, Rank 0

 4849 12:19:06.373647  SW Impedance     : PASS

 4850 12:19:06.376866  DUTY Scan        : NO K

 4851 12:19:06.376945  ZQ Calibration   : PASS

 4852 12:19:06.380082  Jitter Meter     : NO K

 4853 12:19:06.383352  CBT Training     : PASS

 4854 12:19:06.383454  Write leveling   : PASS

 4855 12:19:06.387188  RX DQS gating    : PASS

 4856 12:19:06.390259  RX DQ/DQS(RDDQC) : PASS

 4857 12:19:06.390341  TX DQ/DQS        : PASS

 4858 12:19:06.393342  RX DATLAT        : PASS

 4859 12:19:06.393419  RX DQ/DQS(Engine): PASS

 4860 12:19:06.396878  TX OE            : NO K

 4861 12:19:06.396957  All Pass.

 4862 12:19:06.397040  

 4863 12:19:06.400594  CH 1, Rank 1

 4864 12:19:06.400673  SW Impedance     : PASS

 4865 12:19:06.403441  DUTY Scan        : NO K

 4866 12:19:06.407060  ZQ Calibration   : PASS

 4867 12:19:06.407163  Jitter Meter     : NO K

 4868 12:19:06.410169  CBT Training     : PASS

 4869 12:19:06.413276  Write leveling   : PASS

 4870 12:19:06.413352  RX DQS gating    : PASS

 4871 12:19:06.416912  RX DQ/DQS(RDDQC) : PASS

 4872 12:19:06.420003  TX DQ/DQS        : PASS

 4873 12:19:06.420077  RX DATLAT        : PASS

 4874 12:19:06.423737  RX DQ/DQS(Engine): PASS

 4875 12:19:06.426908  TX OE            : NO K

 4876 12:19:06.427007  All Pass.

 4877 12:19:06.427098  

 4878 12:19:06.427185  DramC Write-DBI off

 4879 12:19:06.430115  	PER_BANK_REFRESH: Hybrid Mode

 4880 12:19:06.433159  TX_TRACKING: ON

 4881 12:19:06.440414  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4882 12:19:06.443566  [FAST_K] Save calibration result to emmc

 4883 12:19:06.449959  dramc_set_vcore_voltage set vcore to 662500

 4884 12:19:06.450060  Read voltage for 933, 3

 4885 12:19:06.453690  Vio18 = 0

 4886 12:19:06.453787  Vcore = 662500

 4887 12:19:06.453879  Vdram = 0

 4888 12:19:06.456544  Vddq = 0

 4889 12:19:06.456614  Vmddr = 0

 4890 12:19:06.459828  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4891 12:19:06.466928  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4892 12:19:06.470072  MEM_TYPE=3, freq_sel=17

 4893 12:19:06.470154  sv_algorithm_assistance_LP4_1600 

 4894 12:19:06.476544  ============ PULL DRAM RESETB DOWN ============

 4895 12:19:06.480279  ========== PULL DRAM RESETB DOWN end =========

 4896 12:19:06.483182  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4897 12:19:06.486782  =================================== 

 4898 12:19:06.489944  LPDDR4 DRAM CONFIGURATION

 4899 12:19:06.493393  =================================== 

 4900 12:19:06.496343  EX_ROW_EN[0]    = 0x0

 4901 12:19:06.496421  EX_ROW_EN[1]    = 0x0

 4902 12:19:06.500126  LP4Y_EN      = 0x0

 4903 12:19:06.500241  WORK_FSP     = 0x0

 4904 12:19:06.503223  WL           = 0x3

 4905 12:19:06.503340  RL           = 0x3

 4906 12:19:06.506375  BL           = 0x2

 4907 12:19:06.506485  RPST         = 0x0

 4908 12:19:06.510111  RD_PRE       = 0x0

 4909 12:19:06.510213  WR_PRE       = 0x1

 4910 12:19:06.513294  WR_PST       = 0x0

 4911 12:19:06.513402  DBI_WR       = 0x0

 4912 12:19:06.516756  DBI_RD       = 0x0

 4913 12:19:06.516857  OTF          = 0x1

 4914 12:19:06.519754  =================================== 

 4915 12:19:06.523164  =================================== 

 4916 12:19:06.526174  ANA top config

 4917 12:19:06.529967  =================================== 

 4918 12:19:06.533162  DLL_ASYNC_EN            =  0

 4919 12:19:06.533240  ALL_SLAVE_EN            =  1

 4920 12:19:06.536356  NEW_RANK_MODE           =  1

 4921 12:19:06.540056  DLL_IDLE_MODE           =  1

 4922 12:19:06.543172  LP45_APHY_COMB_EN       =  1

 4923 12:19:06.546184  TX_ODT_DIS              =  1

 4924 12:19:06.546292  NEW_8X_MODE             =  1

 4925 12:19:06.550056  =================================== 

 4926 12:19:06.553097  =================================== 

 4927 12:19:06.556629  data_rate                  = 1866

 4928 12:19:06.559876  CKR                        = 1

 4929 12:19:06.562987  DQ_P2S_RATIO               = 8

 4930 12:19:06.566721  =================================== 

 4931 12:19:06.569788  CA_P2S_RATIO               = 8

 4932 12:19:06.569893  DQ_CA_OPEN                 = 0

 4933 12:19:06.573100  DQ_SEMI_OPEN               = 0

 4934 12:19:06.576171  CA_SEMI_OPEN               = 0

 4935 12:19:06.579874  CA_FULL_RATE               = 0

 4936 12:19:06.582920  DQ_CKDIV4_EN               = 1

 4937 12:19:06.586645  CA_CKDIV4_EN               = 1

 4938 12:19:06.586750  CA_PREDIV_EN               = 0

 4939 12:19:06.589568  PH8_DLY                    = 0

 4940 12:19:06.593190  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4941 12:19:06.596537  DQ_AAMCK_DIV               = 4

 4942 12:19:06.599572  CA_AAMCK_DIV               = 4

 4943 12:19:06.603274  CA_ADMCK_DIV               = 4

 4944 12:19:06.603384  DQ_TRACK_CA_EN             = 0

 4945 12:19:06.606434  CA_PICK                    = 933

 4946 12:19:06.609830  CA_MCKIO                   = 933

 4947 12:19:06.613245  MCKIO_SEMI                 = 0

 4948 12:19:06.616517  PLL_FREQ                   = 3732

 4949 12:19:06.619719  DQ_UI_PI_RATIO             = 32

 4950 12:19:06.622926  CA_UI_PI_RATIO             = 0

 4951 12:19:06.626600  =================================== 

 4952 12:19:06.629552  =================================== 

 4953 12:19:06.629672  memory_type:LPDDR4         

 4954 12:19:06.633032  GP_NUM     : 10       

 4955 12:19:06.636344  SRAM_EN    : 1       

 4956 12:19:06.636466  MD32_EN    : 0       

 4957 12:19:06.639413  =================================== 

 4958 12:19:06.643316  [ANA_INIT] >>>>>>>>>>>>>> 

 4959 12:19:06.646393  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4960 12:19:06.649550  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4961 12:19:06.652550  =================================== 

 4962 12:19:06.656343  data_rate = 1866,PCW = 0X8f00

 4963 12:19:06.659263  =================================== 

 4964 12:19:06.662608  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4965 12:19:06.665859  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4966 12:19:06.672798  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4967 12:19:06.676031  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4968 12:19:06.679171  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4969 12:19:06.682919  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4970 12:19:06.685827  [ANA_INIT] flow start 

 4971 12:19:06.689643  [ANA_INIT] PLL >>>>>>>> 

 4972 12:19:06.689746  [ANA_INIT] PLL <<<<<<<< 

 4973 12:19:06.692935  [ANA_INIT] MIDPI >>>>>>>> 

 4974 12:19:06.696172  [ANA_INIT] MIDPI <<<<<<<< 

 4975 12:19:06.696248  [ANA_INIT] DLL >>>>>>>> 

 4976 12:19:06.699255  [ANA_INIT] flow end 

 4977 12:19:06.702531  ============ LP4 DIFF to SE enter ============

 4978 12:19:06.709274  ============ LP4 DIFF to SE exit  ============

 4979 12:19:06.709382  [ANA_INIT] <<<<<<<<<<<<< 

 4980 12:19:06.712346  [Flow] Enable top DCM control >>>>> 

 4981 12:19:06.716181  [Flow] Enable top DCM control <<<<< 

 4982 12:19:06.719496  Enable DLL master slave shuffle 

 4983 12:19:06.725982  ============================================================== 

 4984 12:19:06.726076  Gating Mode config

 4985 12:19:06.732502  ============================================================== 

 4986 12:19:06.736267  Config description: 

 4987 12:19:06.742654  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4988 12:19:06.748978  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4989 12:19:06.756198  SELPH_MODE            0: By rank         1: By Phase 

 4990 12:19:06.759607  ============================================================== 

 4991 12:19:06.762867  GAT_TRACK_EN                 =  1

 4992 12:19:06.765673  RX_GATING_MODE               =  2

 4993 12:19:06.768938  RX_GATING_TRACK_MODE         =  2

 4994 12:19:06.772648  SELPH_MODE                   =  1

 4995 12:19:06.775881  PICG_EARLY_EN                =  1

 4996 12:19:06.779035  VALID_LAT_VALUE              =  1

 4997 12:19:06.786046  ============================================================== 

 4998 12:19:06.789234  Enter into Gating configuration >>>> 

 4999 12:19:06.792738  Exit from Gating configuration <<<< 

 5000 12:19:06.792820  Enter into  DVFS_PRE_config >>>>> 

 5001 12:19:06.805849  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 5002 12:19:06.808986  Exit from  DVFS_PRE_config <<<<< 

 5003 12:19:06.812716  Enter into PICG configuration >>>> 

 5004 12:19:06.815736  Exit from PICG configuration <<<< 

 5005 12:19:06.815832  [RX_INPUT] configuration >>>>> 

 5006 12:19:06.818907  [RX_INPUT] configuration <<<<< 

 5007 12:19:06.825931  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 5008 12:19:06.832248  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 5009 12:19:06.835525  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 5010 12:19:06.842225  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 5011 12:19:06.848984  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5012 12:19:06.855207  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5013 12:19:06.858666  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5014 12:19:06.862104  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5015 12:19:06.868785  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5016 12:19:06.871812  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5017 12:19:06.875539  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5018 12:19:06.881951  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5019 12:19:06.885170  =================================== 

 5020 12:19:06.885253  LPDDR4 DRAM CONFIGURATION

 5021 12:19:06.889004  =================================== 

 5022 12:19:06.892008  EX_ROW_EN[0]    = 0x0

 5023 12:19:06.892091  EX_ROW_EN[1]    = 0x0

 5024 12:19:06.895086  LP4Y_EN      = 0x0

 5025 12:19:06.895166  WORK_FSP     = 0x0

 5026 12:19:06.898662  WL           = 0x3

 5027 12:19:06.898743  RL           = 0x3

 5028 12:19:06.901792  BL           = 0x2

 5029 12:19:06.905515  RPST         = 0x0

 5030 12:19:06.905595  RD_PRE       = 0x0

 5031 12:19:06.908544  WR_PRE       = 0x1

 5032 12:19:06.908624  WR_PST       = 0x0

 5033 12:19:06.912207  DBI_WR       = 0x0

 5034 12:19:06.912287  DBI_RD       = 0x0

 5035 12:19:06.915324  OTF          = 0x1

 5036 12:19:06.918450  =================================== 

 5037 12:19:06.921940  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5038 12:19:06.925010  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5039 12:19:06.928883  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5040 12:19:06.932037  =================================== 

 5041 12:19:06.935119  LPDDR4 DRAM CONFIGURATION

 5042 12:19:06.938315  =================================== 

 5043 12:19:06.941947  EX_ROW_EN[0]    = 0x10

 5044 12:19:06.942028  EX_ROW_EN[1]    = 0x0

 5045 12:19:06.945017  LP4Y_EN      = 0x0

 5046 12:19:06.945101  WORK_FSP     = 0x0

 5047 12:19:06.948798  WL           = 0x3

 5048 12:19:06.948879  RL           = 0x3

 5049 12:19:06.951873  BL           = 0x2

 5050 12:19:06.952054  RPST         = 0x0

 5051 12:19:06.954970  RD_PRE       = 0x0

 5052 12:19:06.955051  WR_PRE       = 0x1

 5053 12:19:06.958253  WR_PST       = 0x0

 5054 12:19:06.961945  DBI_WR       = 0x0

 5055 12:19:06.962026  DBI_RD       = 0x0

 5056 12:19:06.965148  OTF          = 0x1

 5057 12:19:06.968262  =================================== 

 5058 12:19:06.971937  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5059 12:19:06.976797  nWR fixed to 30

 5060 12:19:06.980399  [ModeRegInit_LP4] CH0 RK0

 5061 12:19:06.980566  [ModeRegInit_LP4] CH0 RK1

 5062 12:19:06.983301  [ModeRegInit_LP4] CH1 RK0

 5063 12:19:06.986973  [ModeRegInit_LP4] CH1 RK1

 5064 12:19:06.987108  match AC timing 9

 5065 12:19:06.993159  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5066 12:19:06.996508  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5067 12:19:06.999978  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5068 12:19:07.006374  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5069 12:19:07.009722  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5070 12:19:07.009840  ==

 5071 12:19:07.012881  Dram Type= 6, Freq= 0, CH_0, rank 0

 5072 12:19:07.016059  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5073 12:19:07.016167  ==

 5074 12:19:07.023308  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5075 12:19:07.029354  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5076 12:19:07.033288  [CA 0] Center 37 (6~68) winsize 63

 5077 12:19:07.036391  [CA 1] Center 37 (7~68) winsize 62

 5078 12:19:07.039606  [CA 2] Center 34 (4~65) winsize 62

 5079 12:19:07.042697  [CA 3] Center 33 (3~64) winsize 62

 5080 12:19:07.046028  [CA 4] Center 33 (3~64) winsize 62

 5081 12:19:07.049566  [CA 5] Center 32 (2~62) winsize 61

 5082 12:19:07.049648  

 5083 12:19:07.052659  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5084 12:19:07.052764  

 5085 12:19:07.056369  [CATrainingPosCal] consider 1 rank data

 5086 12:19:07.059395  u2DelayCellTimex100 = 270/100 ps

 5087 12:19:07.063153  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5088 12:19:07.066291  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5089 12:19:07.069461  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5090 12:19:07.073204  CA3 delay=33 (3~64),Diff = 1 PI (6 cell)

 5091 12:19:07.076237  CA4 delay=33 (3~64),Diff = 1 PI (6 cell)

 5092 12:19:07.083174  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5093 12:19:07.083282  

 5094 12:19:07.086180  CA PerBit enable=1, Macro0, CA PI delay=32

 5095 12:19:07.086281  

 5096 12:19:07.089484  [CBTSetCACLKResult] CA Dly = 32

 5097 12:19:07.089590  CS Dly: 5 (0~36)

 5098 12:19:07.089683  ==

 5099 12:19:07.092564  Dram Type= 6, Freq= 0, CH_0, rank 1

 5100 12:19:07.096042  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5101 12:19:07.099311  ==

 5102 12:19:07.102771  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5103 12:19:07.109753  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5104 12:19:07.112961  [CA 0] Center 37 (6~68) winsize 63

 5105 12:19:07.116217  [CA 1] Center 37 (7~68) winsize 62

 5106 12:19:07.119341  [CA 2] Center 34 (4~65) winsize 62

 5107 12:19:07.122966  [CA 3] Center 34 (4~64) winsize 61

 5108 12:19:07.126270  [CA 4] Center 32 (2~63) winsize 62

 5109 12:19:07.129670  [CA 5] Center 32 (2~62) winsize 61

 5110 12:19:07.129753  

 5111 12:19:07.132606  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5112 12:19:07.132694  

 5113 12:19:07.136031  [CATrainingPosCal] consider 2 rank data

 5114 12:19:07.139363  u2DelayCellTimex100 = 270/100 ps

 5115 12:19:07.142376  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5116 12:19:07.146136  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5117 12:19:07.149364  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5118 12:19:07.152590  CA3 delay=34 (4~64),Diff = 2 PI (12 cell)

 5119 12:19:07.159122  CA4 delay=33 (3~63),Diff = 1 PI (6 cell)

 5120 12:19:07.162309  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5121 12:19:07.162454  

 5122 12:19:07.166090  CA PerBit enable=1, Macro0, CA PI delay=32

 5123 12:19:07.166174  

 5124 12:19:07.169316  [CBTSetCACLKResult] CA Dly = 32

 5125 12:19:07.169425  CS Dly: 5 (0~37)

 5126 12:19:07.169512  

 5127 12:19:07.172435  ----->DramcWriteLeveling(PI) begin...

 5128 12:19:07.172519  ==

 5129 12:19:07.175633  Dram Type= 6, Freq= 0, CH_0, rank 0

 5130 12:19:07.182573  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5131 12:19:07.182685  ==

 5132 12:19:07.185752  Write leveling (Byte 0): 33 => 33

 5133 12:19:07.188871  Write leveling (Byte 1): 30 => 30

 5134 12:19:07.188948  DramcWriteLeveling(PI) end<-----

 5135 12:19:07.189012  

 5136 12:19:07.192583  ==

 5137 12:19:07.195971  Dram Type= 6, Freq= 0, CH_0, rank 0

 5138 12:19:07.198763  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5139 12:19:07.198868  ==

 5140 12:19:07.202150  [Gating] SW mode calibration

 5141 12:19:07.208993  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5142 12:19:07.211985  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5143 12:19:07.218978   0 14  0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)

 5144 12:19:07.222276   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5145 12:19:07.225512   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5146 12:19:07.232538   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5147 12:19:07.235757   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5148 12:19:07.238874   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5149 12:19:07.245244   0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 5150 12:19:07.248747   0 14 28 | B1->B0 | 3333 2626 | 0 0 | (0 1) (1 1)

 5151 12:19:07.252280   0 15  0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)

 5152 12:19:07.259023   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5153 12:19:07.262054   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5154 12:19:07.265234   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5155 12:19:07.272268   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5156 12:19:07.275630   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5157 12:19:07.278698   0 15 24 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)

 5158 12:19:07.285523   0 15 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)

 5159 12:19:07.288641   1  0  0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)

 5160 12:19:07.292319   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5161 12:19:07.295533   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5162 12:19:07.302258   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5163 12:19:07.305351   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5164 12:19:07.308999   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5165 12:19:07.315293   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5166 12:19:07.318997   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5167 12:19:07.321890   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5168 12:19:07.328896   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5169 12:19:07.332125   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5170 12:19:07.335306   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5171 12:19:07.341738   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5172 12:19:07.344982   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5173 12:19:07.348716   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5174 12:19:07.354919   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5175 12:19:07.358617   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5176 12:19:07.361685   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5177 12:19:07.368462   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5178 12:19:07.371508   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5179 12:19:07.374966   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5180 12:19:07.381807   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5181 12:19:07.384986   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5182 12:19:07.388236   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5183 12:19:07.391487  Total UI for P1: 0, mck2ui 16

 5184 12:19:07.394796  best dqsien dly found for B0: ( 1,  2, 24)

 5185 12:19:07.401430   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5186 12:19:07.405161   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5187 12:19:07.408136  Total UI for P1: 0, mck2ui 16

 5188 12:19:07.411891  best dqsien dly found for B1: ( 1,  2, 30)

 5189 12:19:07.415118  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5190 12:19:07.418320  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5191 12:19:07.418402  

 5192 12:19:07.421786  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5193 12:19:07.424769  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5194 12:19:07.428173  [Gating] SW calibration Done

 5195 12:19:07.428255  ==

 5196 12:19:07.431418  Dram Type= 6, Freq= 0, CH_0, rank 0

 5197 12:19:07.434652  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5198 12:19:07.437802  ==

 5199 12:19:07.437885  RX Vref Scan: 0

 5200 12:19:07.437949  

 5201 12:19:07.441722  RX Vref 0 -> 0, step: 1

 5202 12:19:07.441805  

 5203 12:19:07.444825  RX Delay -80 -> 252, step: 8

 5204 12:19:07.448008  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5205 12:19:07.451226  iDelay=208, Bit 1, Center 111 (24 ~ 199) 176

 5206 12:19:07.454452  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5207 12:19:07.457870  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5208 12:19:07.461288  iDelay=208, Bit 4, Center 111 (24 ~ 199) 176

 5209 12:19:07.468003  iDelay=208, Bit 5, Center 91 (0 ~ 183) 184

 5210 12:19:07.471137  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5211 12:19:07.474303  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5212 12:19:07.477534  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5213 12:19:07.480660  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5214 12:19:07.484347  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5215 12:19:07.491154  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5216 12:19:07.494259  iDelay=208, Bit 12, Center 99 (8 ~ 191) 184

 5217 12:19:07.497243  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5218 12:19:07.500734  iDelay=208, Bit 14, Center 103 (8 ~ 199) 192

 5219 12:19:07.504198  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5220 12:19:07.504280  ==

 5221 12:19:07.507661  Dram Type= 6, Freq= 0, CH_0, rank 0

 5222 12:19:07.513876  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5223 12:19:07.513959  ==

 5224 12:19:07.514024  DQS Delay:

 5225 12:19:07.517244  DQS0 = 0, DQS1 = 0

 5226 12:19:07.517325  DQM Delay:

 5227 12:19:07.520733  DQM0 = 105, DQM1 = 95

 5228 12:19:07.520842  DQ Delay:

 5229 12:19:07.523792  DQ0 =103, DQ1 =111, DQ2 =99, DQ3 =99

 5230 12:19:07.526977  DQ4 =111, DQ5 =91, DQ6 =115, DQ7 =115

 5231 12:19:07.530504  DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91

 5232 12:19:07.533540  DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99

 5233 12:19:07.533623  

 5234 12:19:07.533687  

 5235 12:19:07.533746  ==

 5236 12:19:07.537159  Dram Type= 6, Freq= 0, CH_0, rank 0

 5237 12:19:07.540724  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5238 12:19:07.540808  ==

 5239 12:19:07.543572  

 5240 12:19:07.543698  

 5241 12:19:07.543765  	TX Vref Scan disable

 5242 12:19:07.547272   == TX Byte 0 ==

 5243 12:19:07.550556  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5244 12:19:07.553776  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5245 12:19:07.556892   == TX Byte 1 ==

 5246 12:19:07.560769  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5247 12:19:07.563889  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5248 12:19:07.563971  ==

 5249 12:19:07.566918  Dram Type= 6, Freq= 0, CH_0, rank 0

 5250 12:19:07.573786  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5251 12:19:07.573869  ==

 5252 12:19:07.573934  

 5253 12:19:07.573994  

 5254 12:19:07.574051  	TX Vref Scan disable

 5255 12:19:07.578068   == TX Byte 0 ==

 5256 12:19:07.581114  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5257 12:19:07.588100  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5258 12:19:07.588188   == TX Byte 1 ==

 5259 12:19:07.591061  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5260 12:19:07.594772  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5261 12:19:07.598093  

 5262 12:19:07.598177  [DATLAT]

 5263 12:19:07.598241  Freq=933, CH0 RK0

 5264 12:19:07.598302  

 5265 12:19:07.601352  DATLAT Default: 0xd

 5266 12:19:07.601434  0, 0xFFFF, sum = 0

 5267 12:19:07.604535  1, 0xFFFF, sum = 0

 5268 12:19:07.604618  2, 0xFFFF, sum = 0

 5269 12:19:07.607770  3, 0xFFFF, sum = 0

 5270 12:19:07.607853  4, 0xFFFF, sum = 0

 5271 12:19:07.611317  5, 0xFFFF, sum = 0

 5272 12:19:07.614502  6, 0xFFFF, sum = 0

 5273 12:19:07.614585  7, 0xFFFF, sum = 0

 5274 12:19:07.617608  8, 0xFFFF, sum = 0

 5275 12:19:07.617692  9, 0xFFFF, sum = 0

 5276 12:19:07.620817  10, 0x0, sum = 1

 5277 12:19:07.620900  11, 0x0, sum = 2

 5278 12:19:07.624465  12, 0x0, sum = 3

 5279 12:19:07.624549  13, 0x0, sum = 4

 5280 12:19:07.624614  best_step = 11

 5281 12:19:07.624674  

 5282 12:19:07.627542  ==

 5283 12:19:07.631272  Dram Type= 6, Freq= 0, CH_0, rank 0

 5284 12:19:07.634514  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5285 12:19:07.634596  ==

 5286 12:19:07.634661  RX Vref Scan: 1

 5287 12:19:07.634720  

 5288 12:19:07.637801  RX Vref 0 -> 0, step: 1

 5289 12:19:07.637897  

 5290 12:19:07.640885  RX Delay -45 -> 252, step: 4

 5291 12:19:07.640983  

 5292 12:19:07.644410  Set Vref, RX VrefLevel [Byte0]: 55

 5293 12:19:07.647544                           [Byte1]: 46

 5294 12:19:07.647676  

 5295 12:19:07.651142  Final RX Vref Byte 0 = 55 to rank0

 5296 12:19:07.654182  Final RX Vref Byte 1 = 46 to rank0

 5297 12:19:07.657429  Final RX Vref Byte 0 = 55 to rank1

 5298 12:19:07.660978  Final RX Vref Byte 1 = 46 to rank1==

 5299 12:19:07.664068  Dram Type= 6, Freq= 0, CH_0, rank 0

 5300 12:19:07.667788  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5301 12:19:07.667874  ==

 5302 12:19:07.670823  DQS Delay:

 5303 12:19:07.670908  DQS0 = 0, DQS1 = 0

 5304 12:19:07.674491  DQM Delay:

 5305 12:19:07.674566  DQM0 = 104, DQM1 = 94

 5306 12:19:07.674630  DQ Delay:

 5307 12:19:07.677795  DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =104

 5308 12:19:07.684469  DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =110

 5309 12:19:07.684549  DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =90

 5310 12:19:07.690877  DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102

 5311 12:19:07.690986  

 5312 12:19:07.691054  

 5313 12:19:07.697612  [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps

 5314 12:19:07.700655  CH0 RK0: MR19=505, MR18=332B

 5315 12:19:07.707628  CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44

 5316 12:19:07.707738  

 5317 12:19:07.710830  ----->DramcWriteLeveling(PI) begin...

 5318 12:19:07.710907  ==

 5319 12:19:07.713960  Dram Type= 6, Freq= 0, CH_0, rank 1

 5320 12:19:07.717613  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5321 12:19:07.717698  ==

 5322 12:19:07.720732  Write leveling (Byte 0): 33 => 33

 5323 12:19:07.723784  Write leveling (Byte 1): 28 => 28

 5324 12:19:07.726964  DramcWriteLeveling(PI) end<-----

 5325 12:19:07.727037  

 5326 12:19:07.727099  ==

 5327 12:19:07.730768  Dram Type= 6, Freq= 0, CH_0, rank 1

 5328 12:19:07.733880  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5329 12:19:07.733989  ==

 5330 12:19:07.737142  [Gating] SW mode calibration

 5331 12:19:07.743989  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5332 12:19:07.750505  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5333 12:19:07.754316   0 14  0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 5334 12:19:07.760576   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5335 12:19:07.764279   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5336 12:19:07.767379   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5337 12:19:07.770918   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5338 12:19:07.777623   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5339 12:19:07.780676   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5340 12:19:07.784163   0 14 28 | B1->B0 | 2828 2c2c | 0 0 | (0 1) (0 0)

 5341 12:19:07.791046   0 15  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 5342 12:19:07.794169   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5343 12:19:07.797338   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5344 12:19:07.804051   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5345 12:19:07.807197   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5346 12:19:07.810422   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5347 12:19:07.817435   0 15 24 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)

 5348 12:19:07.820574   0 15 28 | B1->B0 | 3d3d 3433 | 0 1 | (0 0) (0 0)

 5349 12:19:07.823551   1  0  0 | B1->B0 | 4646 4544 | 0 1 | (0 0) (0 0)

 5350 12:19:07.830495   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5351 12:19:07.833658   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5352 12:19:07.836884   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5353 12:19:07.843850   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5354 12:19:07.846984   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5355 12:19:07.850280   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5356 12:19:07.857078   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5357 12:19:07.859979   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5358 12:19:07.863522   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5359 12:19:07.870009   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5360 12:19:07.873677   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5361 12:19:07.876971   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5362 12:19:07.883337   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5363 12:19:07.887019   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5364 12:19:07.890452   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5365 12:19:07.896890   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5366 12:19:07.899859   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5367 12:19:07.903123   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5368 12:19:07.909803   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5369 12:19:07.913292   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5370 12:19:07.916459   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5371 12:19:07.920330   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5372 12:19:07.926479   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5373 12:19:07.930193   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 5374 12:19:07.933266  Total UI for P1: 0, mck2ui 16

 5375 12:19:07.936385  best dqsien dly found for B1: ( 1,  2, 28)

 5376 12:19:07.940309   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5377 12:19:07.943423  Total UI for P1: 0, mck2ui 16

 5378 12:19:07.946558  best dqsien dly found for B0: ( 1,  2, 30)

 5379 12:19:07.949803  best DQS0 dly(MCK, UI, PI) = (1, 2, 30)

 5380 12:19:07.953543  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5381 12:19:07.953626  

 5382 12:19:07.960075  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5383 12:19:07.963268  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5384 12:19:07.966658  [Gating] SW calibration Done

 5385 12:19:07.966742  ==

 5386 12:19:07.970063  Dram Type= 6, Freq= 0, CH_0, rank 1

 5387 12:19:07.973045  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5388 12:19:07.973126  ==

 5389 12:19:07.973257  RX Vref Scan: 0

 5390 12:19:07.973321  

 5391 12:19:07.976445  RX Vref 0 -> 0, step: 1

 5392 12:19:07.976542  

 5393 12:19:07.979920  RX Delay -80 -> 252, step: 8

 5394 12:19:07.982985  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5395 12:19:07.986802  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5396 12:19:07.993121  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5397 12:19:07.996376  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5398 12:19:08.000030  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5399 12:19:08.003102  iDelay=208, Bit 5, Center 99 (8 ~ 191) 184

 5400 12:19:08.006614  iDelay=208, Bit 6, Center 107 (16 ~ 199) 184

 5401 12:19:08.010019  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5402 12:19:08.013431  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5403 12:19:08.019924  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5404 12:19:08.023363  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5405 12:19:08.026241  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5406 12:19:08.029631  iDelay=208, Bit 12, Center 95 (8 ~ 183) 176

 5407 12:19:08.033219  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5408 12:19:08.039807  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5409 12:19:08.042697  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5410 12:19:08.042777  ==

 5411 12:19:08.046515  Dram Type= 6, Freq= 0, CH_0, rank 1

 5412 12:19:08.049730  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5413 12:19:08.049809  ==

 5414 12:19:08.049874  DQS Delay:

 5415 12:19:08.052826  DQS0 = 0, DQS1 = 0

 5416 12:19:08.052910  DQM Delay:

 5417 12:19:08.056483  DQM0 = 104, DQM1 = 93

 5418 12:19:08.056558  DQ Delay:

 5419 12:19:08.059801  DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99

 5420 12:19:08.062880  DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115

 5421 12:19:08.065984  DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87

 5422 12:19:08.069315  DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99

 5423 12:19:08.069395  

 5424 12:19:08.069463  

 5425 12:19:08.069525  ==

 5426 12:19:08.073009  Dram Type= 6, Freq= 0, CH_0, rank 1

 5427 12:19:08.079500  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5428 12:19:08.079583  ==

 5429 12:19:08.079660  

 5430 12:19:08.079735  

 5431 12:19:08.079793  	TX Vref Scan disable

 5432 12:19:08.083171   == TX Byte 0 ==

 5433 12:19:08.086539  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5434 12:19:08.089814  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5435 12:19:08.093521   == TX Byte 1 ==

 5436 12:19:08.096696  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5437 12:19:08.099828  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5438 12:19:08.103017  ==

 5439 12:19:08.106164  Dram Type= 6, Freq= 0, CH_0, rank 1

 5440 12:19:08.109725  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5441 12:19:08.109803  ==

 5442 12:19:08.109866  

 5443 12:19:08.109926  

 5444 12:19:08.112915  	TX Vref Scan disable

 5445 12:19:08.112995   == TX Byte 0 ==

 5446 12:19:08.119964  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5447 12:19:08.122831  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5448 12:19:08.122909   == TX Byte 1 ==

 5449 12:19:08.130009  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5450 12:19:08.133187  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5451 12:19:08.133302  

 5452 12:19:08.133400  [DATLAT]

 5453 12:19:08.136285  Freq=933, CH0 RK1

 5454 12:19:08.136361  

 5455 12:19:08.136423  DATLAT Default: 0xb

 5456 12:19:08.139821  0, 0xFFFF, sum = 0

 5457 12:19:08.139903  1, 0xFFFF, sum = 0

 5458 12:19:08.143352  2, 0xFFFF, sum = 0

 5459 12:19:08.143432  3, 0xFFFF, sum = 0

 5460 12:19:08.146313  4, 0xFFFF, sum = 0

 5461 12:19:08.146393  5, 0xFFFF, sum = 0

 5462 12:19:08.149432  6, 0xFFFF, sum = 0

 5463 12:19:08.153097  7, 0xFFFF, sum = 0

 5464 12:19:08.153201  8, 0xFFFF, sum = 0

 5465 12:19:08.156356  9, 0xFFFF, sum = 0

 5466 12:19:08.156434  10, 0x0, sum = 1

 5467 12:19:08.156507  11, 0x0, sum = 2

 5468 12:19:08.159842  12, 0x0, sum = 3

 5469 12:19:08.159930  13, 0x0, sum = 4

 5470 12:19:08.163323  best_step = 11

 5471 12:19:08.163430  

 5472 12:19:08.163529  ==

 5473 12:19:08.166367  Dram Type= 6, Freq= 0, CH_0, rank 1

 5474 12:19:08.169500  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5475 12:19:08.169580  ==

 5476 12:19:08.172776  RX Vref Scan: 0

 5477 12:19:08.172858  

 5478 12:19:08.172924  RX Vref 0 -> 0, step: 1

 5479 12:19:08.172986  

 5480 12:19:08.176525  RX Delay -53 -> 252, step: 4

 5481 12:19:08.183345  iDelay=199, Bit 0, Center 104 (15 ~ 194) 180

 5482 12:19:08.186860  iDelay=199, Bit 1, Center 104 (19 ~ 190) 172

 5483 12:19:08.190583  iDelay=199, Bit 2, Center 102 (15 ~ 190) 176

 5484 12:19:08.193486  iDelay=199, Bit 3, Center 102 (15 ~ 190) 176

 5485 12:19:08.197012  iDelay=199, Bit 4, Center 106 (19 ~ 194) 176

 5486 12:19:08.203350  iDelay=199, Bit 5, Center 98 (11 ~ 186) 176

 5487 12:19:08.206504  iDelay=199, Bit 6, Center 110 (27 ~ 194) 168

 5488 12:19:08.210428  iDelay=199, Bit 7, Center 112 (27 ~ 198) 172

 5489 12:19:08.213287  iDelay=199, Bit 8, Center 86 (3 ~ 170) 168

 5490 12:19:08.216581  iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168

 5491 12:19:08.223523  iDelay=199, Bit 10, Center 94 (11 ~ 178) 168

 5492 12:19:08.227078  iDelay=199, Bit 11, Center 88 (7 ~ 170) 164

 5493 12:19:08.230086  iDelay=199, Bit 12, Center 98 (15 ~ 182) 168

 5494 12:19:08.233415  iDelay=199, Bit 13, Center 98 (15 ~ 182) 168

 5495 12:19:08.236476  iDelay=199, Bit 14, Center 102 (19 ~ 186) 168

 5496 12:19:08.243379  iDelay=199, Bit 15, Center 102 (19 ~ 186) 168

 5497 12:19:08.243466  ==

 5498 12:19:08.246388  Dram Type= 6, Freq= 0, CH_0, rank 1

 5499 12:19:08.250320  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5500 12:19:08.250410  ==

 5501 12:19:08.250498  DQS Delay:

 5502 12:19:08.253557  DQS0 = 0, DQS1 = 0

 5503 12:19:08.253643  DQM Delay:

 5504 12:19:08.256593  DQM0 = 104, DQM1 = 93

 5505 12:19:08.256680  DQ Delay:

 5506 12:19:08.260244  DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102

 5507 12:19:08.263211  DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112

 5508 12:19:08.266408  DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88

 5509 12:19:08.269966  DQ12 =98, DQ13 =98, DQ14 =102, DQ15 =102

 5510 12:19:08.270058  

 5511 12:19:08.270143  

 5512 12:19:08.279681  [DQSOSCAuto] RK1, (LSB)MR18= 0x2d06, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps

 5513 12:19:08.279771  CH0 RK1: MR19=505, MR18=2D06

 5514 12:19:08.286728  CH0_RK1: MR19=0x505, MR18=0x2D06, DQSOSC=407, MR23=63, INC=65, DEC=43

 5515 12:19:08.289761  [RxdqsGatingPostProcess] freq 933

 5516 12:19:08.296288  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5517 12:19:08.299964  best DQS0 dly(2T, 0.5T) = (0, 10)

 5518 12:19:08.303219  best DQS1 dly(2T, 0.5T) = (0, 10)

 5519 12:19:08.306705  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5520 12:19:08.309951  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5521 12:19:08.313043  best DQS0 dly(2T, 0.5T) = (0, 10)

 5522 12:19:08.313133  best DQS1 dly(2T, 0.5T) = (0, 10)

 5523 12:19:08.316348  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5524 12:19:08.319927  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5525 12:19:08.323037  Pre-setting of DQS Precalculation

 5526 12:19:08.329895  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5527 12:19:08.329981  ==

 5528 12:19:08.333034  Dram Type= 6, Freq= 0, CH_1, rank 0

 5529 12:19:08.336198  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5530 12:19:08.336286  ==

 5531 12:19:08.343190  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5532 12:19:08.349552  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5533 12:19:08.353241  [CA 0] Center 36 (6~67) winsize 62

 5534 12:19:08.356361  [CA 1] Center 36 (6~67) winsize 62

 5535 12:19:08.359550  [CA 2] Center 34 (4~65) winsize 62

 5536 12:19:08.362826  [CA 3] Center 34 (4~65) winsize 62

 5537 12:19:08.366638  [CA 4] Center 34 (4~64) winsize 61

 5538 12:19:08.366725  [CA 5] Center 33 (3~64) winsize 62

 5539 12:19:08.369904  

 5540 12:19:08.373305  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5541 12:19:08.373393  

 5542 12:19:08.376368  [CATrainingPosCal] consider 1 rank data

 5543 12:19:08.379687  u2DelayCellTimex100 = 270/100 ps

 5544 12:19:08.383204  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5545 12:19:08.386188  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5546 12:19:08.389666  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5547 12:19:08.393018  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5548 12:19:08.396354  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5549 12:19:08.399337  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5550 12:19:08.399424  

 5551 12:19:08.402928  CA PerBit enable=1, Macro0, CA PI delay=33

 5552 12:19:08.403015  

 5553 12:19:08.406618  [CBTSetCACLKResult] CA Dly = 33

 5554 12:19:08.409535  CS Dly: 7 (0~38)

 5555 12:19:08.409613  ==

 5556 12:19:08.413049  Dram Type= 6, Freq= 0, CH_1, rank 1

 5557 12:19:08.416512  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5558 12:19:08.416611  ==

 5559 12:19:08.422682  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5560 12:19:08.429205  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5561 12:19:08.432940  [CA 0] Center 36 (6~67) winsize 62

 5562 12:19:08.435913  [CA 1] Center 37 (6~68) winsize 63

 5563 12:19:08.439718  [CA 2] Center 35 (5~65) winsize 61

 5564 12:19:08.442827  [CA 3] Center 34 (4~65) winsize 62

 5565 12:19:08.446326  [CA 4] Center 34 (4~65) winsize 62

 5566 12:19:08.449657  [CA 5] Center 33 (3~64) winsize 62

 5567 12:19:08.449754  

 5568 12:19:08.452739  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5569 12:19:08.452820  

 5570 12:19:08.456364  [CATrainingPosCal] consider 2 rank data

 5571 12:19:08.459452  u2DelayCellTimex100 = 270/100 ps

 5572 12:19:08.462841  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5573 12:19:08.466065  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5574 12:19:08.469800  CA2 delay=35 (5~65),Diff = 2 PI (12 cell)

 5575 12:19:08.472966  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5576 12:19:08.476014  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5577 12:19:08.479164  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5578 12:19:08.479249  

 5579 12:19:08.482781  CA PerBit enable=1, Macro0, CA PI delay=33

 5580 12:19:08.485763  

 5581 12:19:08.485848  [CBTSetCACLKResult] CA Dly = 33

 5582 12:19:08.489546  CS Dly: 8 (0~40)

 5583 12:19:08.489630  

 5584 12:19:08.492644  ----->DramcWriteLeveling(PI) begin...

 5585 12:19:08.492730  ==

 5586 12:19:08.496381  Dram Type= 6, Freq= 0, CH_1, rank 0

 5587 12:19:08.499459  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5588 12:19:08.499563  ==

 5589 12:19:08.502869  Write leveling (Byte 0): 26 => 26

 5590 12:19:08.506237  Write leveling (Byte 1): 26 => 26

 5591 12:19:08.509444  DramcWriteLeveling(PI) end<-----

 5592 12:19:08.509543  

 5593 12:19:08.509641  ==

 5594 12:19:08.512920  Dram Type= 6, Freq= 0, CH_1, rank 0

 5595 12:19:08.516299  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5596 12:19:08.516380  ==

 5597 12:19:08.518968  [Gating] SW mode calibration

 5598 12:19:08.525600  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5599 12:19:08.532227  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5600 12:19:08.536099   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5601 12:19:08.542183   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5602 12:19:08.545902   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5603 12:19:08.549033   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5604 12:19:08.555503   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5605 12:19:08.559395   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5606 12:19:08.562520   0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 1)

 5607 12:19:08.568912   0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)

 5608 12:19:08.572755   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5609 12:19:08.575946   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5610 12:19:08.582257   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5611 12:19:08.586041   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5612 12:19:08.589137   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5613 12:19:08.592160   0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 5614 12:19:08.598993   0 15 24 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)

 5615 12:19:08.602166   0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)

 5616 12:19:08.605377   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5617 12:19:08.612398   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5618 12:19:08.615481   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5619 12:19:08.618699   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5620 12:19:08.625673   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5621 12:19:08.629055   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5622 12:19:08.632187   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5623 12:19:08.638566   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5624 12:19:08.641954   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5625 12:19:08.645388   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5626 12:19:08.652379   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5627 12:19:08.655689   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5628 12:19:08.658898   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5629 12:19:08.665332   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5630 12:19:08.668916   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5631 12:19:08.671900   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5632 12:19:08.678460   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5633 12:19:08.682173   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5634 12:19:08.685441   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5635 12:19:08.691656   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5636 12:19:08.695541   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5637 12:19:08.698702   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5638 12:19:08.705223   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5639 12:19:08.709008   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5640 12:19:08.712023  Total UI for P1: 0, mck2ui 16

 5641 12:19:08.715188  best dqsien dly found for B0: ( 1,  2, 24)

 5642 12:19:08.718359  Total UI for P1: 0, mck2ui 16

 5643 12:19:08.721677  best dqsien dly found for B1: ( 1,  2, 24)

 5644 12:19:08.725530  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5645 12:19:08.728645  best DQS1 dly(MCK, UI, PI) = (1, 2, 24)

 5646 12:19:08.728721  

 5647 12:19:08.731749  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5648 12:19:08.734853  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5649 12:19:08.738740  [Gating] SW calibration Done

 5650 12:19:08.738846  ==

 5651 12:19:08.741806  Dram Type= 6, Freq= 0, CH_1, rank 0

 5652 12:19:08.744867  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5653 12:19:08.744974  ==

 5654 12:19:08.748312  RX Vref Scan: 0

 5655 12:19:08.748385  

 5656 12:19:08.751933  RX Vref 0 -> 0, step: 1

 5657 12:19:08.752005  

 5658 12:19:08.752080  RX Delay -80 -> 252, step: 8

 5659 12:19:08.758532  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5660 12:19:08.761605  iDelay=208, Bit 1, Center 95 (0 ~ 191) 192

 5661 12:19:08.765147  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5662 12:19:08.768432  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5663 12:19:08.771586  iDelay=208, Bit 4, Center 99 (8 ~ 191) 184

 5664 12:19:08.775139  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5665 12:19:08.781778  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5666 12:19:08.784948  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5667 12:19:08.788209  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5668 12:19:08.791983  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5669 12:19:08.794876  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5670 12:19:08.798379  iDelay=208, Bit 11, Center 95 (8 ~ 183) 176

 5671 12:19:08.805400  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5672 12:19:08.808554  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5673 12:19:08.811509  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5674 12:19:08.815219  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5675 12:19:08.815304  ==

 5676 12:19:08.818368  Dram Type= 6, Freq= 0, CH_1, rank 0

 5677 12:19:08.824882  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5678 12:19:08.824967  ==

 5679 12:19:08.825034  DQS Delay:

 5680 12:19:08.828016  DQS0 = 0, DQS1 = 0

 5681 12:19:08.828106  DQM Delay:

 5682 12:19:08.828173  DQM0 = 103, DQM1 = 98

 5683 12:19:08.831864  DQ Delay:

 5684 12:19:08.835069  DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99

 5685 12:19:08.838294  DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103

 5686 12:19:08.841512  DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95

 5687 12:19:08.844685  DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107

 5688 12:19:08.844769  

 5689 12:19:08.844835  

 5690 12:19:08.844896  ==

 5691 12:19:08.848389  Dram Type= 6, Freq= 0, CH_1, rank 0

 5692 12:19:08.851948  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5693 12:19:08.852033  ==

 5694 12:19:08.852098  

 5695 12:19:08.852159  

 5696 12:19:08.855046  	TX Vref Scan disable

 5697 12:19:08.858189   == TX Byte 0 ==

 5698 12:19:08.861893  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5699 12:19:08.865140  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5700 12:19:08.868351   == TX Byte 1 ==

 5701 12:19:08.871681  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5702 12:19:08.875245  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5703 12:19:08.875329  ==

 5704 12:19:08.878262  Dram Type= 6, Freq= 0, CH_1, rank 0

 5705 12:19:08.881604  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5706 12:19:08.884794  ==

 5707 12:19:08.884879  

 5708 12:19:08.884944  

 5709 12:19:08.885006  	TX Vref Scan disable

 5710 12:19:08.888628   == TX Byte 0 ==

 5711 12:19:08.891556  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5712 12:19:08.894883  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5713 12:19:08.898161   == TX Byte 1 ==

 5714 12:19:08.901739  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5715 12:19:08.908484  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5716 12:19:08.908568  

 5717 12:19:08.908633  [DATLAT]

 5718 12:19:08.908695  Freq=933, CH1 RK0

 5719 12:19:08.908754  

 5720 12:19:08.911441  DATLAT Default: 0xd

 5721 12:19:08.911527  0, 0xFFFF, sum = 0

 5722 12:19:08.914944  1, 0xFFFF, sum = 0

 5723 12:19:08.915030  2, 0xFFFF, sum = 0

 5724 12:19:08.918497  3, 0xFFFF, sum = 0

 5725 12:19:08.921469  4, 0xFFFF, sum = 0

 5726 12:19:08.921554  5, 0xFFFF, sum = 0

 5727 12:19:08.925076  6, 0xFFFF, sum = 0

 5728 12:19:08.925161  7, 0xFFFF, sum = 0

 5729 12:19:08.928679  8, 0xFFFF, sum = 0

 5730 12:19:08.928778  9, 0xFFFF, sum = 0

 5731 12:19:08.931520  10, 0x0, sum = 1

 5732 12:19:08.931619  11, 0x0, sum = 2

 5733 12:19:08.934921  12, 0x0, sum = 3

 5734 12:19:08.935021  13, 0x0, sum = 4

 5735 12:19:08.935117  best_step = 11

 5736 12:19:08.935208  

 5737 12:19:08.938005  ==

 5738 12:19:08.941672  Dram Type= 6, Freq= 0, CH_1, rank 0

 5739 12:19:08.944817  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5740 12:19:08.944914  ==

 5741 12:19:08.944979  RX Vref Scan: 1

 5742 12:19:08.945039  

 5743 12:19:08.948587  RX Vref 0 -> 0, step: 1

 5744 12:19:08.948683  

 5745 12:19:08.951520  RX Delay -45 -> 252, step: 4

 5746 12:19:08.951601  

 5747 12:19:08.954728  Set Vref, RX VrefLevel [Byte0]: 53

 5748 12:19:08.958387                           [Byte1]: 47

 5749 12:19:08.958500  

 5750 12:19:08.961437  Final RX Vref Byte 0 = 53 to rank0

 5751 12:19:08.965189  Final RX Vref Byte 1 = 47 to rank0

 5752 12:19:08.968385  Final RX Vref Byte 0 = 53 to rank1

 5753 12:19:08.971515  Final RX Vref Byte 1 = 47 to rank1==

 5754 12:19:08.974642  Dram Type= 6, Freq= 0, CH_1, rank 0

 5755 12:19:08.978373  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5756 12:19:08.978512  ==

 5757 12:19:08.981479  DQS Delay:

 5758 12:19:08.981603  DQS0 = 0, DQS1 = 0

 5759 12:19:08.984552  DQM Delay:

 5760 12:19:08.984636  DQM0 = 103, DQM1 = 100

 5761 12:19:08.988329  DQ Delay:

 5762 12:19:08.988405  DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =102

 5763 12:19:08.994485  DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102

 5764 12:19:08.998364  DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =94

 5765 12:19:09.001415  DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =110

 5766 12:19:09.001519  

 5767 12:19:09.001612  

 5768 12:19:09.008442  [DQSOSCAuto] RK0, (LSB)MR18= 0x1930, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps

 5769 12:19:09.011610  CH1 RK0: MR19=505, MR18=1930

 5770 12:19:09.018443  CH1_RK0: MR19=0x505, MR18=0x1930, DQSOSC=406, MR23=63, INC=65, DEC=43

 5771 12:19:09.018529  

 5772 12:19:09.021344  ----->DramcWriteLeveling(PI) begin...

 5773 12:19:09.021429  ==

 5774 12:19:09.024806  Dram Type= 6, Freq= 0, CH_1, rank 1

 5775 12:19:09.028257  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5776 12:19:09.028342  ==

 5777 12:19:09.031348  Write leveling (Byte 0): 28 => 28

 5778 12:19:09.034920  Write leveling (Byte 1): 28 => 28

 5779 12:19:09.038013  DramcWriteLeveling(PI) end<-----

 5780 12:19:09.038094  

 5781 12:19:09.038183  ==

 5782 12:19:09.041308  Dram Type= 6, Freq= 0, CH_1, rank 1

 5783 12:19:09.044961  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5784 12:19:09.045045  ==

 5785 12:19:09.048027  [Gating] SW mode calibration

 5786 12:19:09.054466  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5787 12:19:09.061071  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5788 12:19:09.064788   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5789 12:19:09.071391   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5790 12:19:09.074429   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5791 12:19:09.078195   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5792 12:19:09.084548   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5793 12:19:09.087714   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5794 12:19:09.090907   0 14 24 | B1->B0 | 2c2c 3030 | 1 0 | (1 0) (0 1)

 5795 12:19:09.097807   0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 5796 12:19:09.100824   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5797 12:19:09.104548   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5798 12:19:09.110924   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5799 12:19:09.114194   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5800 12:19:09.117986   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5801 12:19:09.121134   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5802 12:19:09.128006   0 15 24 | B1->B0 | 3939 2c2c | 0 0 | (0 0) (1 1)

 5803 12:19:09.131177   0 15 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)

 5804 12:19:09.134325   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5805 12:19:09.140982   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5806 12:19:09.144515   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5807 12:19:09.147549   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5808 12:19:09.154393   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5809 12:19:09.157536   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5810 12:19:09.160545   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5811 12:19:09.167746   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5812 12:19:09.170597   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5813 12:19:09.173923   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5814 12:19:09.181021   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5815 12:19:09.184162   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5816 12:19:09.187449   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5817 12:19:09.193831   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5818 12:19:09.197534   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5819 12:19:09.200539   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5820 12:19:09.207442   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5821 12:19:09.210711   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5822 12:19:09.214001   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5823 12:19:09.220862   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5824 12:19:09.223943   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5825 12:19:09.227065   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5826 12:19:09.233779   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5827 12:19:09.236967   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5828 12:19:09.240211  Total UI for P1: 0, mck2ui 16

 5829 12:19:09.243936  best dqsien dly found for B0: ( 1,  2, 24)

 5830 12:19:09.246954  Total UI for P1: 0, mck2ui 16

 5831 12:19:09.250528  best dqsien dly found for B1: ( 1,  2, 24)

 5832 12:19:09.254088  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5833 12:19:09.257086  best DQS1 dly(MCK, UI, PI) = (1, 2, 24)

 5834 12:19:09.257170  

 5835 12:19:09.260111  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5836 12:19:09.263864  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5837 12:19:09.267059  [Gating] SW calibration Done

 5838 12:19:09.267162  ==

 5839 12:19:09.269973  Dram Type= 6, Freq= 0, CH_1, rank 1

 5840 12:19:09.273764  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5841 12:19:09.273847  ==

 5842 12:19:09.276977  RX Vref Scan: 0

 5843 12:19:09.277074  

 5844 12:19:09.280237  RX Vref 0 -> 0, step: 1

 5845 12:19:09.280319  

 5846 12:19:09.280384  RX Delay -80 -> 252, step: 8

 5847 12:19:09.287010  iDelay=208, Bit 0, Center 111 (24 ~ 199) 176

 5848 12:19:09.290655  iDelay=208, Bit 1, Center 99 (8 ~ 191) 184

 5849 12:19:09.293409  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5850 12:19:09.296701  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5851 12:19:09.300231  iDelay=208, Bit 4, Center 95 (8 ~ 183) 176

 5852 12:19:09.303364  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5853 12:19:09.310353  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5854 12:19:09.313821  iDelay=208, Bit 7, Center 99 (8 ~ 191) 184

 5855 12:19:09.316692  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5856 12:19:09.320227  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5857 12:19:09.323517  iDelay=208, Bit 10, Center 103 (16 ~ 191) 176

 5858 12:19:09.326611  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5859 12:19:09.333361  iDelay=208, Bit 12, Center 103 (8 ~ 199) 192

 5860 12:19:09.336476  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5861 12:19:09.340350  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5862 12:19:09.343386  iDelay=208, Bit 15, Center 107 (24 ~ 191) 168

 5863 12:19:09.343460  ==

 5864 12:19:09.346575  Dram Type= 6, Freq= 0, CH_1, rank 1

 5865 12:19:09.353336  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5866 12:19:09.353421  ==

 5867 12:19:09.353487  DQS Delay:

 5868 12:19:09.356861  DQS0 = 0, DQS1 = 0

 5869 12:19:09.356934  DQM Delay:

 5870 12:19:09.356996  DQM0 = 103, DQM1 = 97

 5871 12:19:09.359724  DQ Delay:

 5872 12:19:09.363260  DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =99

 5873 12:19:09.366326  DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99

 5874 12:19:09.370049  DQ8 =83, DQ9 =87, DQ10 =103, DQ11 =91

 5875 12:19:09.373264  DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107

 5876 12:19:09.373341  

 5877 12:19:09.373412  

 5878 12:19:09.373473  ==

 5879 12:19:09.376846  Dram Type= 6, Freq= 0, CH_1, rank 1

 5880 12:19:09.379800  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5881 12:19:09.379880  ==

 5882 12:19:09.379945  

 5883 12:19:09.380004  

 5884 12:19:09.382971  	TX Vref Scan disable

 5885 12:19:09.386782   == TX Byte 0 ==

 5886 12:19:09.390015  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5887 12:19:09.393302  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5888 12:19:09.396467   == TX Byte 1 ==

 5889 12:19:09.400218  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5890 12:19:09.403169  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5891 12:19:09.403242  ==

 5892 12:19:09.406791  Dram Type= 6, Freq= 0, CH_1, rank 1

 5893 12:19:09.413071  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5894 12:19:09.413150  ==

 5895 12:19:09.413214  

 5896 12:19:09.413280  

 5897 12:19:09.413339  	TX Vref Scan disable

 5898 12:19:09.416869   == TX Byte 0 ==

 5899 12:19:09.420630  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5900 12:19:09.427165  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5901 12:19:09.427308   == TX Byte 1 ==

 5902 12:19:09.430118  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5903 12:19:09.436834  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5904 12:19:09.436916  

 5905 12:19:09.436980  [DATLAT]

 5906 12:19:09.437040  Freq=933, CH1 RK1

 5907 12:19:09.437098  

 5908 12:19:09.440371  DATLAT Default: 0xb

 5909 12:19:09.440453  0, 0xFFFF, sum = 0

 5910 12:19:09.443532  1, 0xFFFF, sum = 0

 5911 12:19:09.443612  2, 0xFFFF, sum = 0

 5912 12:19:09.446981  3, 0xFFFF, sum = 0

 5913 12:19:09.447065  4, 0xFFFF, sum = 0

 5914 12:19:09.450444  5, 0xFFFF, sum = 0

 5915 12:19:09.453717  6, 0xFFFF, sum = 0

 5916 12:19:09.453801  7, 0xFFFF, sum = 0

 5917 12:19:09.456763  8, 0xFFFF, sum = 0

 5918 12:19:09.456836  9, 0xFFFF, sum = 0

 5919 12:19:09.460476  10, 0x0, sum = 1

 5920 12:19:09.460558  11, 0x0, sum = 2

 5921 12:19:09.460623  12, 0x0, sum = 3

 5922 12:19:09.463690  13, 0x0, sum = 4

 5923 12:19:09.463796  best_step = 11

 5924 12:19:09.463888  

 5925 12:19:09.467078  ==

 5926 12:19:09.467175  Dram Type= 6, Freq= 0, CH_1, rank 1

 5927 12:19:09.473909  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5928 12:19:09.474011  ==

 5929 12:19:09.474101  RX Vref Scan: 0

 5930 12:19:09.474191  

 5931 12:19:09.477008  RX Vref 0 -> 0, step: 1

 5932 12:19:09.477099  

 5933 12:19:09.480106  RX Delay -53 -> 252, step: 4

 5934 12:19:09.483765  iDelay=203, Bit 0, Center 108 (27 ~ 190) 164

 5935 12:19:09.490408  iDelay=203, Bit 1, Center 98 (15 ~ 182) 168

 5936 12:19:09.493504  iDelay=203, Bit 2, Center 94 (11 ~ 178) 168

 5937 12:19:09.496548  iDelay=203, Bit 3, Center 100 (19 ~ 182) 164

 5938 12:19:09.500329  iDelay=203, Bit 4, Center 100 (19 ~ 182) 164

 5939 12:19:09.503506  iDelay=203, Bit 5, Center 118 (35 ~ 202) 168

 5940 12:19:09.510365  iDelay=203, Bit 6, Center 114 (31 ~ 198) 168

 5941 12:19:09.513506  iDelay=203, Bit 7, Center 102 (19 ~ 186) 168

 5942 12:19:09.517309  iDelay=203, Bit 8, Center 92 (11 ~ 174) 164

 5943 12:19:09.520491  iDelay=203, Bit 9, Center 88 (3 ~ 174) 172

 5944 12:19:09.523490  iDelay=203, Bit 10, Center 100 (19 ~ 182) 164

 5945 12:19:09.526733  iDelay=203, Bit 11, Center 94 (11 ~ 178) 168

 5946 12:19:09.533536  iDelay=203, Bit 12, Center 108 (19 ~ 198) 180

 5947 12:19:09.536737  iDelay=203, Bit 13, Center 102 (19 ~ 186) 168

 5948 12:19:09.540527  iDelay=203, Bit 14, Center 102 (19 ~ 186) 168

 5949 12:19:09.543767  iDelay=203, Bit 15, Center 106 (23 ~ 190) 168

 5950 12:19:09.543841  ==

 5951 12:19:09.546912  Dram Type= 6, Freq= 0, CH_1, rank 1

 5952 12:19:09.553238  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5953 12:19:09.553332  ==

 5954 12:19:09.553396  DQS Delay:

 5955 12:19:09.553455  DQS0 = 0, DQS1 = 0

 5956 12:19:09.556733  DQM Delay:

 5957 12:19:09.556820  DQM0 = 104, DQM1 = 99

 5958 12:19:09.560044  DQ Delay:

 5959 12:19:09.563753  DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100

 5960 12:19:09.567060  DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102

 5961 12:19:09.569949  DQ8 =92, DQ9 =88, DQ10 =100, DQ11 =94

 5962 12:19:09.573240  DQ12 =108, DQ13 =102, DQ14 =102, DQ15 =106

 5963 12:19:09.573363  

 5964 12:19:09.573458  

 5965 12:19:09.580042  [DQSOSCAuto] RK1, (LSB)MR18= 0x2bff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps

 5966 12:19:09.583455  CH1 RK1: MR19=504, MR18=2BFF

 5967 12:19:09.590174  CH1_RK1: MR19=0x504, MR18=0x2BFF, DQSOSC=408, MR23=63, INC=65, DEC=43

 5968 12:19:09.593399  [RxdqsGatingPostProcess] freq 933

 5969 12:19:09.599973  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5970 12:19:09.603466  best DQS0 dly(2T, 0.5T) = (0, 10)

 5971 12:19:09.603609  best DQS1 dly(2T, 0.5T) = (0, 10)

 5972 12:19:09.606705  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5973 12:19:09.609950  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5974 12:19:09.613046  best DQS0 dly(2T, 0.5T) = (0, 10)

 5975 12:19:09.616796  best DQS1 dly(2T, 0.5T) = (0, 10)

 5976 12:19:09.619865  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5977 12:19:09.623534  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5978 12:19:09.626684  Pre-setting of DQS Precalculation

 5979 12:19:09.632949  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5980 12:19:09.639943  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5981 12:19:09.646262  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5982 12:19:09.646348  

 5983 12:19:09.646414  

 5984 12:19:09.650116  [Calibration Summary] 1866 Mbps

 5985 12:19:09.650203  CH 0, Rank 0

 5986 12:19:09.653757  SW Impedance     : PASS

 5987 12:19:09.656781  DUTY Scan        : NO K

 5988 12:19:09.656865  ZQ Calibration   : PASS

 5989 12:19:09.659801  Jitter Meter     : NO K

 5990 12:19:09.663051  CBT Training     : PASS

 5991 12:19:09.663135  Write leveling   : PASS

 5992 12:19:09.666762  RX DQS gating    : PASS

 5993 12:19:09.666840  RX DQ/DQS(RDDQC) : PASS

 5994 12:19:09.669909  TX DQ/DQS        : PASS

 5995 12:19:09.673070  RX DATLAT        : PASS

 5996 12:19:09.673172  RX DQ/DQS(Engine): PASS

 5997 12:19:09.676323  TX OE            : NO K

 5998 12:19:09.676425  All Pass.

 5999 12:19:09.676518  

 6000 12:19:09.679544  CH 0, Rank 1

 6001 12:19:09.679651  SW Impedance     : PASS

 6002 12:19:09.683283  DUTY Scan        : NO K

 6003 12:19:09.686410  ZQ Calibration   : PASS

 6004 12:19:09.686524  Jitter Meter     : NO K

 6005 12:19:09.689376  CBT Training     : PASS

 6006 12:19:09.693057  Write leveling   : PASS

 6007 12:19:09.693139  RX DQS gating    : PASS

 6008 12:19:09.696508  RX DQ/DQS(RDDQC) : PASS

 6009 12:19:09.699479  TX DQ/DQS        : PASS

 6010 12:19:09.699582  RX DATLAT        : PASS

 6011 12:19:09.703324  RX DQ/DQS(Engine): PASS

 6012 12:19:09.706247  TX OE            : NO K

 6013 12:19:09.706349  All Pass.

 6014 12:19:09.706445  

 6015 12:19:09.706538  CH 1, Rank 0

 6016 12:19:09.709601  SW Impedance     : PASS

 6017 12:19:09.712616  DUTY Scan        : NO K

 6018 12:19:09.712691  ZQ Calibration   : PASS

 6019 12:19:09.716320  Jitter Meter     : NO K

 6020 12:19:09.719292  CBT Training     : PASS

 6021 12:19:09.719399  Write leveling   : PASS

 6022 12:19:09.722983  RX DQS gating    : PASS

 6023 12:19:09.723078  RX DQ/DQS(RDDQC) : PASS

 6024 12:19:09.725872  TX DQ/DQS        : PASS

 6025 12:19:09.729274  RX DATLAT        : PASS

 6026 12:19:09.729376  RX DQ/DQS(Engine): PASS

 6027 12:19:09.732619  TX OE            : NO K

 6028 12:19:09.732748  All Pass.

 6029 12:19:09.732849  

 6030 12:19:09.735874  CH 1, Rank 1

 6031 12:19:09.735960  SW Impedance     : PASS

 6032 12:19:09.739486  DUTY Scan        : NO K

 6033 12:19:09.742671  ZQ Calibration   : PASS

 6034 12:19:09.742767  Jitter Meter     : NO K

 6035 12:19:09.745877  CBT Training     : PASS

 6036 12:19:09.749115  Write leveling   : PASS

 6037 12:19:09.749199  RX DQS gating    : PASS

 6038 12:19:09.752855  RX DQ/DQS(RDDQC) : PASS

 6039 12:19:09.755999  TX DQ/DQS        : PASS

 6040 12:19:09.756083  RX DATLAT        : PASS

 6041 12:19:09.759035  RX DQ/DQS(Engine): PASS

 6042 12:19:09.762875  TX OE            : NO K

 6043 12:19:09.762960  All Pass.

 6044 12:19:09.763026  

 6045 12:19:09.763086  DramC Write-DBI off

 6046 12:19:09.765828  	PER_BANK_REFRESH: Hybrid Mode

 6047 12:19:09.769038  TX_TRACKING: ON

 6048 12:19:09.775919  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6049 12:19:09.779077  [FAST_K] Save calibration result to emmc

 6050 12:19:09.785888  dramc_set_vcore_voltage set vcore to 650000

 6051 12:19:09.785973  Read voltage for 400, 6

 6052 12:19:09.788971  Vio18 = 0

 6053 12:19:09.789057  Vcore = 650000

 6054 12:19:09.789124  Vdram = 0

 6055 12:19:09.792541  Vddq = 0

 6056 12:19:09.792625  Vmddr = 0

 6057 12:19:09.795629  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6058 12:19:09.802003  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6059 12:19:09.805814  MEM_TYPE=3, freq_sel=20

 6060 12:19:09.808996  sv_algorithm_assistance_LP4_800 

 6061 12:19:09.812043  ============ PULL DRAM RESETB DOWN ============

 6062 12:19:09.815813  ========== PULL DRAM RESETB DOWN end =========

 6063 12:19:09.818972  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6064 12:19:09.822029  =================================== 

 6065 12:19:09.825685  LPDDR4 DRAM CONFIGURATION

 6066 12:19:09.828832  =================================== 

 6067 12:19:09.832002  EX_ROW_EN[0]    = 0x0

 6068 12:19:09.832101  EX_ROW_EN[1]    = 0x0

 6069 12:19:09.835657  LP4Y_EN      = 0x0

 6070 12:19:09.835755  WORK_FSP     = 0x0

 6071 12:19:09.838781  WL           = 0x2

 6072 12:19:09.838880  RL           = 0x2

 6073 12:19:09.841847  BL           = 0x2

 6074 12:19:09.841946  RPST         = 0x0

 6075 12:19:09.845424  RD_PRE       = 0x0

 6076 12:19:09.845498  WR_PRE       = 0x1

 6077 12:19:09.848559  WR_PST       = 0x0

 6078 12:19:09.852373  DBI_WR       = 0x0

 6079 12:19:09.852446  DBI_RD       = 0x0

 6080 12:19:09.855375  OTF          = 0x1

 6081 12:19:09.858874  =================================== 

 6082 12:19:09.861949  =================================== 

 6083 12:19:09.862046  ANA top config

 6084 12:19:09.865232  =================================== 

 6085 12:19:09.868719  DLL_ASYNC_EN            =  0

 6086 12:19:09.868816  ALL_SLAVE_EN            =  1

 6087 12:19:09.872039  NEW_RANK_MODE           =  1

 6088 12:19:09.875029  DLL_IDLE_MODE           =  1

 6089 12:19:09.878348  LP45_APHY_COMB_EN       =  1

 6090 12:19:09.881919  TX_ODT_DIS              =  1

 6091 12:19:09.882029  NEW_8X_MODE             =  1

 6092 12:19:09.885082  =================================== 

 6093 12:19:09.888248  =================================== 

 6094 12:19:09.892006  data_rate                  =  800

 6095 12:19:09.895019  CKR                        = 1

 6096 12:19:09.898556  DQ_P2S_RATIO               = 4

 6097 12:19:09.901600  =================================== 

 6098 12:19:09.905390  CA_P2S_RATIO               = 4

 6099 12:19:09.908614  DQ_CA_OPEN                 = 0

 6100 12:19:09.908701  DQ_SEMI_OPEN               = 1

 6101 12:19:09.911892  CA_SEMI_OPEN               = 1

 6102 12:19:09.915070  CA_FULL_RATE               = 0

 6103 12:19:09.918789  DQ_CKDIV4_EN               = 0

 6104 12:19:09.922096  CA_CKDIV4_EN               = 1

 6105 12:19:09.925072  CA_PREDIV_EN               = 0

 6106 12:19:09.925180  PH8_DLY                    = 0

 6107 12:19:09.928322  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6108 12:19:09.931891  DQ_AAMCK_DIV               = 0

 6109 12:19:09.935166  CA_AAMCK_DIV               = 0

 6110 12:19:09.938285  CA_ADMCK_DIV               = 4

 6111 12:19:09.942074  DQ_TRACK_CA_EN             = 0

 6112 12:19:09.942161  CA_PICK                    = 800

 6113 12:19:09.945173  CA_MCKIO                   = 400

 6114 12:19:09.948208  MCKIO_SEMI                 = 400

 6115 12:19:09.951373  PLL_FREQ                   = 3016

 6116 12:19:09.955244  DQ_UI_PI_RATIO             = 32

 6117 12:19:09.958377  CA_UI_PI_RATIO             = 32

 6118 12:19:09.961587  =================================== 

 6119 12:19:09.964856  =================================== 

 6120 12:19:09.964956  memory_type:LPDDR4         

 6121 12:19:09.968067  GP_NUM     : 10       

 6122 12:19:09.971570  SRAM_EN    : 1       

 6123 12:19:09.971685  MD32_EN    : 0       

 6124 12:19:09.974917  =================================== 

 6125 12:19:09.978196  [ANA_INIT] >>>>>>>>>>>>>> 

 6126 12:19:09.981686  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6127 12:19:09.984707  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6128 12:19:09.988043  =================================== 

 6129 12:19:09.991550  data_rate = 800,PCW = 0X7400

 6130 12:19:09.994836  =================================== 

 6131 12:19:09.998059  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6132 12:19:10.001222  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6133 12:19:10.014517  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6134 12:19:10.018183  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6135 12:19:10.021596  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6136 12:19:10.024394  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6137 12:19:10.028154  [ANA_INIT] flow start 

 6138 12:19:10.031303  [ANA_INIT] PLL >>>>>>>> 

 6139 12:19:10.031405  [ANA_INIT] PLL <<<<<<<< 

 6140 12:19:10.034497  [ANA_INIT] MIDPI >>>>>>>> 

 6141 12:19:10.038033  [ANA_INIT] MIDPI <<<<<<<< 

 6142 12:19:10.038138  [ANA_INIT] DLL >>>>>>>> 

 6143 12:19:10.041318  [ANA_INIT] flow end 

 6144 12:19:10.044476  ============ LP4 DIFF to SE enter ============

 6145 12:19:10.048197  ============ LP4 DIFF to SE exit  ============

 6146 12:19:10.051417  [ANA_INIT] <<<<<<<<<<<<< 

 6147 12:19:10.054502  [Flow] Enable top DCM control >>>>> 

 6148 12:19:10.057721  [Flow] Enable top DCM control <<<<< 

 6149 12:19:10.061724  Enable DLL master slave shuffle 

 6150 12:19:10.067943  ============================================================== 

 6151 12:19:10.068036  Gating Mode config

 6152 12:19:10.075027  ============================================================== 

 6153 12:19:10.075110  Config description: 

 6154 12:19:10.084780  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6155 12:19:10.091415  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6156 12:19:10.098090  SELPH_MODE            0: By rank         1: By Phase 

 6157 12:19:10.101079  ============================================================== 

 6158 12:19:10.104540  GAT_TRACK_EN                 =  0

 6159 12:19:10.108007  RX_GATING_MODE               =  2

 6160 12:19:10.110908  RX_GATING_TRACK_MODE         =  2

 6161 12:19:10.114665  SELPH_MODE                   =  1

 6162 12:19:10.117709  PICG_EARLY_EN                =  1

 6163 12:19:10.121323  VALID_LAT_VALUE              =  1

 6164 12:19:10.127576  ============================================================== 

 6165 12:19:10.131257  Enter into Gating configuration >>>> 

 6166 12:19:10.134498  Exit from Gating configuration <<<< 

 6167 12:19:10.137576  Enter into  DVFS_PRE_config >>>>> 

 6168 12:19:10.147837  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6169 12:19:10.151016  Exit from  DVFS_PRE_config <<<<< 

 6170 12:19:10.154236  Enter into PICG configuration >>>> 

 6171 12:19:10.157781  Exit from PICG configuration <<<< 

 6172 12:19:10.157862  [RX_INPUT] configuration >>>>> 

 6173 12:19:10.161255  [RX_INPUT] configuration <<<<< 

 6174 12:19:10.167690  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6175 12:19:10.170873  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6176 12:19:10.177849  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6177 12:19:10.184288  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6178 12:19:10.191174  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6179 12:19:10.198016  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6180 12:19:10.201142  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6181 12:19:10.204352  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6182 12:19:10.210959  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6183 12:19:10.213989  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6184 12:19:10.217542  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6185 12:19:10.220573  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6186 12:19:10.224439  =================================== 

 6187 12:19:10.227567  LPDDR4 DRAM CONFIGURATION

 6188 12:19:10.230853  =================================== 

 6189 12:19:10.234063  EX_ROW_EN[0]    = 0x0

 6190 12:19:10.234169  EX_ROW_EN[1]    = 0x0

 6191 12:19:10.237811  LP4Y_EN      = 0x0

 6192 12:19:10.237916  WORK_FSP     = 0x0

 6193 12:19:10.240877  WL           = 0x2

 6194 12:19:10.240952  RL           = 0x2

 6195 12:19:10.244409  BL           = 0x2

 6196 12:19:10.244507  RPST         = 0x0

 6197 12:19:10.247350  RD_PRE       = 0x0

 6198 12:19:10.247452  WR_PRE       = 0x1

 6199 12:19:10.250992  WR_PST       = 0x0

 6200 12:19:10.251087  DBI_WR       = 0x0

 6201 12:19:10.254036  DBI_RD       = 0x0

 6202 12:19:10.257596  OTF          = 0x1

 6203 12:19:10.260503  =================================== 

 6204 12:19:10.263852  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6205 12:19:10.267499  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6206 12:19:10.270590  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6207 12:19:10.274040  =================================== 

 6208 12:19:10.277452  LPDDR4 DRAM CONFIGURATION

 6209 12:19:10.280879  =================================== 

 6210 12:19:10.284363  EX_ROW_EN[0]    = 0x10

 6211 12:19:10.284471  EX_ROW_EN[1]    = 0x0

 6212 12:19:10.287541  LP4Y_EN      = 0x0

 6213 12:19:10.287679  WORK_FSP     = 0x0

 6214 12:19:10.290629  WL           = 0x2

 6215 12:19:10.290707  RL           = 0x2

 6216 12:19:10.294389  BL           = 0x2

 6217 12:19:10.294459  RPST         = 0x0

 6218 12:19:10.297539  RD_PRE       = 0x0

 6219 12:19:10.297621  WR_PRE       = 0x1

 6220 12:19:10.300686  WR_PST       = 0x0

 6221 12:19:10.300785  DBI_WR       = 0x0

 6222 12:19:10.303728  DBI_RD       = 0x0

 6223 12:19:10.303824  OTF          = 0x1

 6224 12:19:10.307524  =================================== 

 6225 12:19:10.313720  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6226 12:19:10.318652  nWR fixed to 30

 6227 12:19:10.322287  [ModeRegInit_LP4] CH0 RK0

 6228 12:19:10.322362  [ModeRegInit_LP4] CH0 RK1

 6229 12:19:10.325092  [ModeRegInit_LP4] CH1 RK0

 6230 12:19:10.328767  [ModeRegInit_LP4] CH1 RK1

 6231 12:19:10.328841  match AC timing 19

 6232 12:19:10.334990  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6233 12:19:10.338159  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6234 12:19:10.342018  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6235 12:19:10.348280  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6236 12:19:10.352020  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6237 12:19:10.352096  ==

 6238 12:19:10.354919  Dram Type= 6, Freq= 0, CH_0, rank 0

 6239 12:19:10.358408  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6240 12:19:10.358484  ==

 6241 12:19:10.365321  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6242 12:19:10.371750  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6243 12:19:10.374667  [CA 0] Center 36 (8~64) winsize 57

 6244 12:19:10.378327  [CA 1] Center 36 (8~64) winsize 57

 6245 12:19:10.381305  [CA 2] Center 36 (8~64) winsize 57

 6246 12:19:10.385036  [CA 3] Center 36 (8~64) winsize 57

 6247 12:19:10.385143  [CA 4] Center 36 (8~64) winsize 57

 6248 12:19:10.388277  [CA 5] Center 36 (8~64) winsize 57

 6249 12:19:10.388375  

 6250 12:19:10.395227  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6251 12:19:10.395327  

 6252 12:19:10.398315  [CATrainingPosCal] consider 1 rank data

 6253 12:19:10.401709  u2DelayCellTimex100 = 270/100 ps

 6254 12:19:10.404879  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6255 12:19:10.408423  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6256 12:19:10.411732  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6257 12:19:10.414978  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6258 12:19:10.418408  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6259 12:19:10.421301  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6260 12:19:10.421384  

 6261 12:19:10.424825  CA PerBit enable=1, Macro0, CA PI delay=36

 6262 12:19:10.424909  

 6263 12:19:10.428390  [CBTSetCACLKResult] CA Dly = 36

 6264 12:19:10.431355  CS Dly: 1 (0~32)

 6265 12:19:10.431435  ==

 6266 12:19:10.434831  Dram Type= 6, Freq= 0, CH_0, rank 1

 6267 12:19:10.437977  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6268 12:19:10.438052  ==

 6269 12:19:10.444906  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6270 12:19:10.448176  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6271 12:19:10.451418  [CA 0] Center 36 (8~64) winsize 57

 6272 12:19:10.454559  [CA 1] Center 36 (8~64) winsize 57

 6273 12:19:10.458257  [CA 2] Center 36 (8~64) winsize 57

 6274 12:19:10.461419  [CA 3] Center 36 (8~64) winsize 57

 6275 12:19:10.464924  [CA 4] Center 36 (8~64) winsize 57

 6276 12:19:10.467923  [CA 5] Center 36 (8~64) winsize 57

 6277 12:19:10.467996  

 6278 12:19:10.471669  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6279 12:19:10.471761  

 6280 12:19:10.474857  [CATrainingPosCal] consider 2 rank data

 6281 12:19:10.477976  u2DelayCellTimex100 = 270/100 ps

 6282 12:19:10.481658  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6283 12:19:10.484630  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6284 12:19:10.488250  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6285 12:19:10.494525  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6286 12:19:10.498307  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6287 12:19:10.501323  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6288 12:19:10.501403  

 6289 12:19:10.505018  CA PerBit enable=1, Macro0, CA PI delay=36

 6290 12:19:10.505092  

 6291 12:19:10.507803  [CBTSetCACLKResult] CA Dly = 36

 6292 12:19:10.507924  CS Dly: 1 (0~32)

 6293 12:19:10.508043  

 6294 12:19:10.511677  ----->DramcWriteLeveling(PI) begin...

 6295 12:19:10.511751  ==

 6296 12:19:10.514800  Dram Type= 6, Freq= 0, CH_0, rank 0

 6297 12:19:10.521703  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6298 12:19:10.521780  ==

 6299 12:19:10.524816  Write leveling (Byte 0): 40 => 8

 6300 12:19:10.527821  Write leveling (Byte 1): 40 => 8

 6301 12:19:10.527900  DramcWriteLeveling(PI) end<-----

 6302 12:19:10.527990  

 6303 12:19:10.531291  ==

 6304 12:19:10.534539  Dram Type= 6, Freq= 0, CH_0, rank 0

 6305 12:19:10.538163  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6306 12:19:10.538234  ==

 6307 12:19:10.541534  [Gating] SW mode calibration

 6308 12:19:10.548060  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6309 12:19:10.551236  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6310 12:19:10.558311   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6311 12:19:10.561316   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6312 12:19:10.564331   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6313 12:19:10.571218   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6314 12:19:10.574649   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6315 12:19:10.577702   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6316 12:19:10.584379   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6317 12:19:10.587572   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6318 12:19:10.591216   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6319 12:19:10.594460  Total UI for P1: 0, mck2ui 16

 6320 12:19:10.597560  best dqsien dly found for B0: ( 0, 14, 24)

 6321 12:19:10.601384  Total UI for P1: 0, mck2ui 16

 6322 12:19:10.604303  best dqsien dly found for B1: ( 0, 14, 24)

 6323 12:19:10.608144  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6324 12:19:10.611126  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6325 12:19:10.611198  

 6326 12:19:10.617971  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6327 12:19:10.620903  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6328 12:19:10.620976  [Gating] SW calibration Done

 6329 12:19:10.624209  ==

 6330 12:19:10.627915  Dram Type= 6, Freq= 0, CH_0, rank 0

 6331 12:19:10.631161  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6332 12:19:10.631234  ==

 6333 12:19:10.631302  RX Vref Scan: 0

 6334 12:19:10.631384  

 6335 12:19:10.634269  RX Vref 0 -> 0, step: 1

 6336 12:19:10.634347  

 6337 12:19:10.637991  RX Delay -410 -> 252, step: 16

 6338 12:19:10.641134  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6339 12:19:10.644145  iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480

 6340 12:19:10.650950  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6341 12:19:10.654499  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6342 12:19:10.657605  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6343 12:19:10.660775  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6344 12:19:10.667251  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6345 12:19:10.670951  iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480

 6346 12:19:10.674501  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6347 12:19:10.677388  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6348 12:19:10.684355  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6349 12:19:10.687556  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6350 12:19:10.690771  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6351 12:19:10.696988  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6352 12:19:10.700843  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6353 12:19:10.703927  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6354 12:19:10.704010  ==

 6355 12:19:10.707541  Dram Type= 6, Freq= 0, CH_0, rank 0

 6356 12:19:10.710740  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6357 12:19:10.710818  ==

 6358 12:19:10.713853  DQS Delay:

 6359 12:19:10.713955  DQS0 = 27, DQS1 = 35

 6360 12:19:10.717573  DQM Delay:

 6361 12:19:10.717676  DQM0 = 9, DQM1 = 11

 6362 12:19:10.720486  DQ Delay:

 6363 12:19:10.720584  DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8

 6364 12:19:10.724057  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6365 12:19:10.727300  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6366 12:19:10.730431  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6367 12:19:10.730528  

 6368 12:19:10.730617  

 6369 12:19:10.730713  ==

 6370 12:19:10.734231  Dram Type= 6, Freq= 0, CH_0, rank 0

 6371 12:19:10.740612  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6372 12:19:10.740721  ==

 6373 12:19:10.740812  

 6374 12:19:10.740908  

 6375 12:19:10.740996  	TX Vref Scan disable

 6376 12:19:10.743826   == TX Byte 0 ==

 6377 12:19:10.747051  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6378 12:19:10.750706  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6379 12:19:10.753826   == TX Byte 1 ==

 6380 12:19:10.757052  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6381 12:19:10.760877  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6382 12:19:10.760986  ==

 6383 12:19:10.763902  Dram Type= 6, Freq= 0, CH_0, rank 0

 6384 12:19:10.770629  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6385 12:19:10.770758  ==

 6386 12:19:10.770855  

 6387 12:19:10.770950  

 6388 12:19:10.771052  	TX Vref Scan disable

 6389 12:19:10.773903   == TX Byte 0 ==

 6390 12:19:10.776996  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6391 12:19:10.780637  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6392 12:19:10.784149   == TX Byte 1 ==

 6393 12:19:10.787039  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6394 12:19:10.790331  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6395 12:19:10.790410  

 6396 12:19:10.793642  [DATLAT]

 6397 12:19:10.793719  Freq=400, CH0 RK0

 6398 12:19:10.793789  

 6399 12:19:10.797201  DATLAT Default: 0xf

 6400 12:19:10.797281  0, 0xFFFF, sum = 0

 6401 12:19:10.800257  1, 0xFFFF, sum = 0

 6402 12:19:10.800326  2, 0xFFFF, sum = 0

 6403 12:19:10.803503  3, 0xFFFF, sum = 0

 6404 12:19:10.803570  4, 0xFFFF, sum = 0

 6405 12:19:10.806924  5, 0xFFFF, sum = 0

 6406 12:19:10.806998  6, 0xFFFF, sum = 0

 6407 12:19:10.810520  7, 0xFFFF, sum = 0

 6408 12:19:10.810591  8, 0xFFFF, sum = 0

 6409 12:19:10.813515  9, 0xFFFF, sum = 0

 6410 12:19:10.813596  10, 0xFFFF, sum = 0

 6411 12:19:10.817251  11, 0xFFFF, sum = 0

 6412 12:19:10.820138  12, 0xFFFF, sum = 0

 6413 12:19:10.820208  13, 0x0, sum = 1

 6414 12:19:10.823736  14, 0x0, sum = 2

 6415 12:19:10.823808  15, 0x0, sum = 3

 6416 12:19:10.823867  16, 0x0, sum = 4

 6417 12:19:10.826786  best_step = 14

 6418 12:19:10.826876  

 6419 12:19:10.826943  ==

 6420 12:19:10.830318  Dram Type= 6, Freq= 0, CH_0, rank 0

 6421 12:19:10.833630  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6422 12:19:10.833727  ==

 6423 12:19:10.837322  RX Vref Scan: 1

 6424 12:19:10.837410  

 6425 12:19:10.837474  RX Vref 0 -> 0, step: 1

 6426 12:19:10.840558  

 6427 12:19:10.840660  RX Delay -311 -> 252, step: 8

 6428 12:19:10.840748  

 6429 12:19:10.843572  Set Vref, RX VrefLevel [Byte0]: 55

 6430 12:19:10.846809                           [Byte1]: 46

 6431 12:19:10.851815  

 6432 12:19:10.851883  Final RX Vref Byte 0 = 55 to rank0

 6433 12:19:10.855467  Final RX Vref Byte 1 = 46 to rank0

 6434 12:19:10.858648  Final RX Vref Byte 0 = 55 to rank1

 6435 12:19:10.861802  Final RX Vref Byte 1 = 46 to rank1==

 6436 12:19:10.865554  Dram Type= 6, Freq= 0, CH_0, rank 0

 6437 12:19:10.871891  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6438 12:19:10.871972  ==

 6439 12:19:10.872044  DQS Delay:

 6440 12:19:10.872140  DQS0 = 28, DQS1 = 36

 6441 12:19:10.875518  DQM Delay:

 6442 12:19:10.875646  DQM0 = 11, DQM1 = 12

 6443 12:19:10.878690  DQ Delay:

 6444 12:19:10.881843  DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8

 6445 12:19:10.881924  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16

 6446 12:19:10.885693  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8

 6447 12:19:10.888861  DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20

 6448 12:19:10.888954  

 6449 12:19:10.889018  

 6450 12:19:10.898815  [DQSOSCAuto] RK0, (LSB)MR18= 0xd1bf, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps

 6451 12:19:10.901904  CH0 RK0: MR19=C0C, MR18=D1BF

 6452 12:19:10.908294  CH0_RK0: MR19=0xC0C, MR18=0xD1BF, DQSOSC=384, MR23=63, INC=400, DEC=267

 6453 12:19:10.908427  ==

 6454 12:19:10.912072  Dram Type= 6, Freq= 0, CH_0, rank 1

 6455 12:19:10.915037  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6456 12:19:10.915149  ==

 6457 12:19:10.918196  [Gating] SW mode calibration

 6458 12:19:10.924924  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6459 12:19:10.931768  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6460 12:19:10.934991   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6461 12:19:10.938380   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6462 12:19:10.941754   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6463 12:19:10.948355   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6464 12:19:10.951529   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6465 12:19:10.954734   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6466 12:19:10.962286   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6467 12:19:10.965037   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6468 12:19:10.968035   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6469 12:19:10.971716  Total UI for P1: 0, mck2ui 16

 6470 12:19:10.974892  best dqsien dly found for B0: ( 0, 14, 24)

 6471 12:19:10.978472  Total UI for P1: 0, mck2ui 16

 6472 12:19:10.981619  best dqsien dly found for B1: ( 0, 14, 24)

 6473 12:19:10.984693  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6474 12:19:10.988498  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6475 12:19:10.991696  

 6476 12:19:10.994657  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6477 12:19:10.998368  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6478 12:19:11.001443  [Gating] SW calibration Done

 6479 12:19:11.001522  ==

 6480 12:19:11.004623  Dram Type= 6, Freq= 0, CH_0, rank 1

 6481 12:19:11.008248  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6482 12:19:11.008324  ==

 6483 12:19:11.008394  RX Vref Scan: 0

 6484 12:19:11.011585  

 6485 12:19:11.011673  RX Vref 0 -> 0, step: 1

 6486 12:19:11.011738  

 6487 12:19:11.014691  RX Delay -410 -> 252, step: 16

 6488 12:19:11.017714  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6489 12:19:11.024454  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6490 12:19:11.028202  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6491 12:19:11.031286  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6492 12:19:11.034849  iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480

 6493 12:19:11.041072  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6494 12:19:11.044776  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6495 12:19:11.048020  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6496 12:19:11.051138  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6497 12:19:11.057696  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6498 12:19:11.061387  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6499 12:19:11.064522  iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464

 6500 12:19:11.067972  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6501 12:19:11.074358  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6502 12:19:11.077636  iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448

 6503 12:19:11.081126  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6504 12:19:11.081204  ==

 6505 12:19:11.084361  Dram Type= 6, Freq= 0, CH_0, rank 1

 6506 12:19:11.087460  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6507 12:19:11.091254  ==

 6508 12:19:11.091332  DQS Delay:

 6509 12:19:11.091404  DQS0 = 27, DQS1 = 35

 6510 12:19:11.094290  DQM Delay:

 6511 12:19:11.094405  DQM0 = 12, DQM1 = 11

 6512 12:19:11.097550  DQ Delay:

 6513 12:19:11.097635  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6514 12:19:11.101311  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24

 6515 12:19:11.104311  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6516 12:19:11.107503  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6517 12:19:11.107580  

 6518 12:19:11.107660  

 6519 12:19:11.111288  ==

 6520 12:19:11.111378  Dram Type= 6, Freq= 0, CH_0, rank 1

 6521 12:19:11.117677  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6522 12:19:11.117792  ==

 6523 12:19:11.117867  

 6524 12:19:11.117928  

 6525 12:19:11.121005  	TX Vref Scan disable

 6526 12:19:11.121079   == TX Byte 0 ==

 6527 12:19:11.124076  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6528 12:19:11.127570  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6529 12:19:11.131313   == TX Byte 1 ==

 6530 12:19:11.134426  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6531 12:19:11.137564  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6532 12:19:11.141005  ==

 6533 12:19:11.144179  Dram Type= 6, Freq= 0, CH_0, rank 1

 6534 12:19:11.147334  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6535 12:19:11.147408  ==

 6536 12:19:11.147478  

 6537 12:19:11.147538  

 6538 12:19:11.150981  	TX Vref Scan disable

 6539 12:19:11.151080   == TX Byte 0 ==

 6540 12:19:11.154329  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6541 12:19:11.157416  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6542 12:19:11.160965   == TX Byte 1 ==

 6543 12:19:11.164478  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6544 12:19:11.167586  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6545 12:19:11.167692  

 6546 12:19:11.170988  [DATLAT]

 6547 12:19:11.171072  Freq=400, CH0 RK1

 6548 12:19:11.171187  

 6549 12:19:11.174036  DATLAT Default: 0xe

 6550 12:19:11.174121  0, 0xFFFF, sum = 0

 6551 12:19:11.177869  1, 0xFFFF, sum = 0

 6552 12:19:11.177984  2, 0xFFFF, sum = 0

 6553 12:19:11.180978  3, 0xFFFF, sum = 0

 6554 12:19:11.181064  4, 0xFFFF, sum = 0

 6555 12:19:11.184212  5, 0xFFFF, sum = 0

 6556 12:19:11.184319  6, 0xFFFF, sum = 0

 6557 12:19:11.187400  7, 0xFFFF, sum = 0

 6558 12:19:11.191147  8, 0xFFFF, sum = 0

 6559 12:19:11.191252  9, 0xFFFF, sum = 0

 6560 12:19:11.194042  10, 0xFFFF, sum = 0

 6561 12:19:11.194120  11, 0xFFFF, sum = 0

 6562 12:19:11.197553  12, 0xFFFF, sum = 0

 6563 12:19:11.197633  13, 0x0, sum = 1

 6564 12:19:11.200722  14, 0x0, sum = 2

 6565 12:19:11.200796  15, 0x0, sum = 3

 6566 12:19:11.203957  16, 0x0, sum = 4

 6567 12:19:11.204044  best_step = 14

 6568 12:19:11.204129  

 6569 12:19:11.204209  ==

 6570 12:19:11.207670  Dram Type= 6, Freq= 0, CH_0, rank 1

 6571 12:19:11.210840  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6572 12:19:11.210922  ==

 6573 12:19:11.213830  RX Vref Scan: 0

 6574 12:19:11.213917  

 6575 12:19:11.217194  RX Vref 0 -> 0, step: 1

 6576 12:19:11.217275  

 6577 12:19:11.217337  RX Delay -311 -> 252, step: 8

 6578 12:19:11.225726  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6579 12:19:11.229292  iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440

 6580 12:19:11.232444  iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448

 6581 12:19:11.236166  iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448

 6582 12:19:11.242406  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6583 12:19:11.245969  iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448

 6584 12:19:11.249057  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 6585 12:19:11.252206  iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448

 6586 12:19:11.259223  iDelay=217, Bit 8, Center -36 (-255 ~ 184) 440

 6587 12:19:11.262382  iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440

 6588 12:19:11.265917  iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440

 6589 12:19:11.268750  iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440

 6590 12:19:11.275439  iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440

 6591 12:19:11.279271  iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440

 6592 12:19:11.282404  iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440

 6593 12:19:11.288647  iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448

 6594 12:19:11.288749  ==

 6595 12:19:11.292488  Dram Type= 6, Freq= 0, CH_0, rank 1

 6596 12:19:11.295766  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6597 12:19:11.295840  ==

 6598 12:19:11.295918  DQS Delay:

 6599 12:19:11.298856  DQS0 = 24, DQS1 = 36

 6600 12:19:11.298954  DQM Delay:

 6601 12:19:11.302121  DQM0 = 9, DQM1 = 12

 6602 12:19:11.302215  DQ Delay:

 6603 12:19:11.305712  DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8

 6604 12:19:11.308763  DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16

 6605 12:19:11.312359  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6606 12:19:11.315488  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20

 6607 12:19:11.315584  

 6608 12:19:11.315716  

 6609 12:19:11.321905  [DQSOSCAuto] RK1, (LSB)MR18= 0xbb5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps

 6610 12:19:11.325406  CH0 RK1: MR19=C0C, MR18=BB5C

 6611 12:19:11.332091  CH0_RK1: MR19=0xC0C, MR18=0xBB5C, DQSOSC=386, MR23=63, INC=396, DEC=264

 6612 12:19:11.335404  [RxdqsGatingPostProcess] freq 400

 6613 12:19:11.341672  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6614 12:19:11.341755  best DQS0 dly(2T, 0.5T) = (0, 10)

 6615 12:19:11.345163  best DQS1 dly(2T, 0.5T) = (0, 10)

 6616 12:19:11.348516  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6617 12:19:11.351978  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6618 12:19:11.355330  best DQS0 dly(2T, 0.5T) = (0, 10)

 6619 12:19:11.358612  best DQS1 dly(2T, 0.5T) = (0, 10)

 6620 12:19:11.361695  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6621 12:19:11.365344  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6622 12:19:11.368468  Pre-setting of DQS Precalculation

 6623 12:19:11.372275  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6624 12:19:11.375214  ==

 6625 12:19:11.378644  Dram Type= 6, Freq= 0, CH_1, rank 0

 6626 12:19:11.381868  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6627 12:19:11.381965  ==

 6628 12:19:11.384977  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6629 12:19:11.391730  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6630 12:19:11.394866  [CA 0] Center 36 (8~64) winsize 57

 6631 12:19:11.398686  [CA 1] Center 36 (8~64) winsize 57

 6632 12:19:11.401871  [CA 2] Center 36 (8~64) winsize 57

 6633 12:19:11.405024  [CA 3] Center 36 (8~64) winsize 57

 6634 12:19:11.408137  [CA 4] Center 36 (8~64) winsize 57

 6635 12:19:11.411947  [CA 5] Center 36 (8~64) winsize 57

 6636 12:19:11.412044  

 6637 12:19:11.415198  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6638 12:19:11.415304  

 6639 12:19:11.418216  [CATrainingPosCal] consider 1 rank data

 6640 12:19:11.421865  u2DelayCellTimex100 = 270/100 ps

 6641 12:19:11.425000  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6642 12:19:11.428099  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6643 12:19:11.431253  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6644 12:19:11.437915  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6645 12:19:11.441769  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6646 12:19:11.444851  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6647 12:19:11.444933  

 6648 12:19:11.448077  CA PerBit enable=1, Macro0, CA PI delay=36

 6649 12:19:11.448159  

 6650 12:19:11.451312  [CBTSetCACLKResult] CA Dly = 36

 6651 12:19:11.451409  CS Dly: 1 (0~32)

 6652 12:19:11.451473  ==

 6653 12:19:11.455120  Dram Type= 6, Freq= 0, CH_1, rank 1

 6654 12:19:11.461451  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6655 12:19:11.461535  ==

 6656 12:19:11.464985  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6657 12:19:11.471574  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6658 12:19:11.474794  [CA 0] Center 36 (8~64) winsize 57

 6659 12:19:11.478242  [CA 1] Center 36 (8~64) winsize 57

 6660 12:19:11.481328  [CA 2] Center 36 (8~64) winsize 57

 6661 12:19:11.484892  [CA 3] Center 36 (8~64) winsize 57

 6662 12:19:11.488323  [CA 4] Center 36 (8~64) winsize 57

 6663 12:19:11.491508  [CA 5] Center 36 (8~64) winsize 57

 6664 12:19:11.491618  

 6665 12:19:11.494619  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6666 12:19:11.494728  

 6667 12:19:11.498083  [CATrainingPosCal] consider 2 rank data

 6668 12:19:11.501683  u2DelayCellTimex100 = 270/100 ps

 6669 12:19:11.504820  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6670 12:19:11.507960  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6671 12:19:11.511684  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6672 12:19:11.514803  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6673 12:19:11.517953  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6674 12:19:11.521474  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6675 12:19:11.521556  

 6676 12:19:11.527691  CA PerBit enable=1, Macro0, CA PI delay=36

 6677 12:19:11.527774  

 6678 12:19:11.527869  [CBTSetCACLKResult] CA Dly = 36

 6679 12:19:11.531263  CS Dly: 1 (0~32)

 6680 12:19:11.531358  

 6681 12:19:11.534577  ----->DramcWriteLeveling(PI) begin...

 6682 12:19:11.534675  ==

 6683 12:19:11.537717  Dram Type= 6, Freq= 0, CH_1, rank 0

 6684 12:19:11.541438  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6685 12:19:11.541520  ==

 6686 12:19:11.544520  Write leveling (Byte 0): 40 => 8

 6687 12:19:11.548207  Write leveling (Byte 1): 40 => 8

 6688 12:19:11.551288  DramcWriteLeveling(PI) end<-----

 6689 12:19:11.551386  

 6690 12:19:11.551462  ==

 6691 12:19:11.554420  Dram Type= 6, Freq= 0, CH_1, rank 0

 6692 12:19:11.558223  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6693 12:19:11.558335  ==

 6694 12:19:11.561341  [Gating] SW mode calibration

 6695 12:19:11.567784  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6696 12:19:11.574758  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6697 12:19:11.577870   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6698 12:19:11.584224   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6699 12:19:11.587746   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6700 12:19:11.591347   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6701 12:19:11.598288   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6702 12:19:11.601014   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6703 12:19:11.604181   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6704 12:19:11.611139   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6705 12:19:11.614285   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6706 12:19:11.617677  Total UI for P1: 0, mck2ui 16

 6707 12:19:11.621057  best dqsien dly found for B0: ( 0, 14, 24)

 6708 12:19:11.624248  Total UI for P1: 0, mck2ui 16

 6709 12:19:11.627594  best dqsien dly found for B1: ( 0, 14, 24)

 6710 12:19:11.633869  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6711 12:19:11.634140  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6712 12:19:11.634231  

 6713 12:19:11.637440  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6714 12:19:11.640918  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6715 12:19:11.644196  [Gating] SW calibration Done

 6716 12:19:11.644278  ==

 6717 12:19:11.647380  Dram Type= 6, Freq= 0, CH_1, rank 0

 6718 12:19:11.651003  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6719 12:19:11.651086  ==

 6720 12:19:11.653888  RX Vref Scan: 0

 6721 12:19:11.654004  

 6722 12:19:11.657819  RX Vref 0 -> 0, step: 1

 6723 12:19:11.657932  

 6724 12:19:11.661031  RX Delay -410 -> 252, step: 16

 6725 12:19:11.664352  iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480

 6726 12:19:11.667472  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6727 12:19:11.670643  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6728 12:19:11.677112  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6729 12:19:11.681048  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6730 12:19:11.684108  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6731 12:19:11.687238  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6732 12:19:11.694177  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6733 12:19:11.697561  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6734 12:19:11.700762  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6735 12:19:11.703698  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6736 12:19:11.710462  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6737 12:19:11.713657  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6738 12:19:11.717420  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6739 12:19:11.720648  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6740 12:19:11.726975  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6741 12:19:11.727097  ==

 6742 12:19:11.730532  Dram Type= 6, Freq= 0, CH_1, rank 0

 6743 12:19:11.733494  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6744 12:19:11.733576  ==

 6745 12:19:11.733641  DQS Delay:

 6746 12:19:11.737350  DQS0 = 27, DQS1 = 35

 6747 12:19:11.737433  DQM Delay:

 6748 12:19:11.740459  DQM0 = 11, DQM1 = 13

 6749 12:19:11.740565  DQ Delay:

 6750 12:19:11.743799  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6751 12:19:11.747312  DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8

 6752 12:19:11.750535  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6753 12:19:11.753852  DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24

 6754 12:19:11.753939  

 6755 12:19:11.754003  

 6756 12:19:11.754062  ==

 6757 12:19:11.756878  Dram Type= 6, Freq= 0, CH_1, rank 0

 6758 12:19:11.760134  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6759 12:19:11.760247  ==

 6760 12:19:11.760311  

 6761 12:19:11.760369  

 6762 12:19:11.763634  	TX Vref Scan disable

 6763 12:19:11.766932   == TX Byte 0 ==

 6764 12:19:11.770229  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6765 12:19:11.773507  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6766 12:19:11.776893   == TX Byte 1 ==

 6767 12:19:11.779927  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6768 12:19:11.783824  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6769 12:19:11.783906  ==

 6770 12:19:11.787052  Dram Type= 6, Freq= 0, CH_1, rank 0

 6771 12:19:11.790204  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6772 12:19:11.790287  ==

 6773 12:19:11.790352  

 6774 12:19:11.793422  

 6775 12:19:11.793504  	TX Vref Scan disable

 6776 12:19:11.796528   == TX Byte 0 ==

 6777 12:19:11.800333  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6778 12:19:11.803349  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6779 12:19:11.806903   == TX Byte 1 ==

 6780 12:19:11.809889  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6781 12:19:11.813578  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6782 12:19:11.813678  

 6783 12:19:11.813775  [DATLAT]

 6784 12:19:11.816760  Freq=400, CH1 RK0

 6785 12:19:11.816859  

 6786 12:19:11.816955  DATLAT Default: 0xf

 6787 12:19:11.820467  0, 0xFFFF, sum = 0

 6788 12:19:11.820568  1, 0xFFFF, sum = 0

 6789 12:19:11.823592  2, 0xFFFF, sum = 0

 6790 12:19:11.823718  3, 0xFFFF, sum = 0

 6791 12:19:11.826770  4, 0xFFFF, sum = 0

 6792 12:19:11.829982  5, 0xFFFF, sum = 0

 6793 12:19:11.830083  6, 0xFFFF, sum = 0

 6794 12:19:11.833756  7, 0xFFFF, sum = 0

 6795 12:19:11.833856  8, 0xFFFF, sum = 0

 6796 12:19:11.836939  9, 0xFFFF, sum = 0

 6797 12:19:11.837040  10, 0xFFFF, sum = 0

 6798 12:19:11.840033  11, 0xFFFF, sum = 0

 6799 12:19:11.840133  12, 0xFFFF, sum = 0

 6800 12:19:11.843793  13, 0x0, sum = 1

 6801 12:19:11.843921  14, 0x0, sum = 2

 6802 12:19:11.846733  15, 0x0, sum = 3

 6803 12:19:11.846832  16, 0x0, sum = 4

 6804 12:19:11.850206  best_step = 14

 6805 12:19:11.850304  

 6806 12:19:11.850383  ==

 6807 12:19:11.853312  Dram Type= 6, Freq= 0, CH_1, rank 0

 6808 12:19:11.856511  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6809 12:19:11.856609  ==

 6810 12:19:11.856706  RX Vref Scan: 1

 6811 12:19:11.856799  

 6812 12:19:11.860118  RX Vref 0 -> 0, step: 1

 6813 12:19:11.860217  

 6814 12:19:11.863296  RX Delay -311 -> 252, step: 8

 6815 12:19:11.863393  

 6816 12:19:11.866822  Set Vref, RX VrefLevel [Byte0]: 53

 6817 12:19:11.870045                           [Byte1]: 47

 6818 12:19:11.873773  

 6819 12:19:11.873873  Final RX Vref Byte 0 = 53 to rank0

 6820 12:19:11.877135  Final RX Vref Byte 1 = 47 to rank0

 6821 12:19:11.880583  Final RX Vref Byte 0 = 53 to rank1

 6822 12:19:11.883851  Final RX Vref Byte 1 = 47 to rank1==

 6823 12:19:11.886952  Dram Type= 6, Freq= 0, CH_1, rank 0

 6824 12:19:11.893674  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6825 12:19:11.893767  ==

 6826 12:19:11.893833  DQS Delay:

 6827 12:19:11.897261  DQS0 = 32, DQS1 = 32

 6828 12:19:11.897360  DQM Delay:

 6829 12:19:11.897434  DQM0 = 13, DQM1 = 11

 6830 12:19:11.900011  DQ Delay:

 6831 12:19:11.903356  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12

 6832 12:19:11.907093  DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12

 6833 12:19:11.907187  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4

 6834 12:19:11.910081  DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20

 6835 12:19:11.913611  

 6836 12:19:11.913691  

 6837 12:19:11.920216  [DQSOSCAuto] RK0, (LSB)MR18= 0x93ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps

 6838 12:19:11.923897  CH1 RK0: MR19=C0C, MR18=93CA

 6839 12:19:11.930247  CH1_RK0: MR19=0xC0C, MR18=0x93CA, DQSOSC=384, MR23=63, INC=400, DEC=267

 6840 12:19:11.930332  ==

 6841 12:19:11.933418  Dram Type= 6, Freq= 0, CH_1, rank 1

 6842 12:19:11.936625  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6843 12:19:11.936752  ==

 6844 12:19:11.940338  [Gating] SW mode calibration

 6845 12:19:11.946727  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6846 12:19:11.953496  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6847 12:19:11.956930   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6848 12:19:11.960081   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6849 12:19:11.966744   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6850 12:19:11.970256   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6851 12:19:11.973390   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6852 12:19:11.979693   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6853 12:19:11.982887   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6854 12:19:11.986583   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6855 12:19:11.993032   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6856 12:19:11.993117  Total UI for P1: 0, mck2ui 16

 6857 12:19:11.996187  best dqsien dly found for B0: ( 0, 14, 24)

 6858 12:19:11.999716  Total UI for P1: 0, mck2ui 16

 6859 12:19:12.003010  best dqsien dly found for B1: ( 0, 14, 24)

 6860 12:19:12.009530  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6861 12:19:12.012896  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6862 12:19:12.012980  

 6863 12:19:12.016270  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6864 12:19:12.019606  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6865 12:19:12.023287  [Gating] SW calibration Done

 6866 12:19:12.023369  ==

 6867 12:19:12.026493  Dram Type= 6, Freq= 0, CH_1, rank 1

 6868 12:19:12.029582  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6869 12:19:12.029682  ==

 6870 12:19:12.033180  RX Vref Scan: 0

 6871 12:19:12.033264  

 6872 12:19:12.033328  RX Vref 0 -> 0, step: 1

 6873 12:19:12.033401  

 6874 12:19:12.036292  RX Delay -410 -> 252, step: 16

 6875 12:19:12.039704  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6876 12:19:12.046299  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6877 12:19:12.049401  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6878 12:19:12.052557  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6879 12:19:12.056303  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6880 12:19:12.062832  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6881 12:19:12.065830  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6882 12:19:12.069458  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6883 12:19:12.072526  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6884 12:19:12.079387  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6885 12:19:12.082377  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6886 12:19:12.085656  iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464

 6887 12:19:12.092600  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6888 12:19:12.095837  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6889 12:19:12.099533  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6890 12:19:12.102671  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6891 12:19:12.102753  ==

 6892 12:19:12.105829  Dram Type= 6, Freq= 0, CH_1, rank 1

 6893 12:19:12.112298  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6894 12:19:12.112381  ==

 6895 12:19:12.112446  DQS Delay:

 6896 12:19:12.115913  DQS0 = 35, DQS1 = 35

 6897 12:19:12.115996  DQM Delay:

 6898 12:19:12.118869  DQM0 = 18, DQM1 = 14

 6899 12:19:12.118953  DQ Delay:

 6900 12:19:12.122638  DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16

 6901 12:19:12.125768  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6902 12:19:12.128909  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16

 6903 12:19:12.132640  DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24

 6904 12:19:12.132723  

 6905 12:19:12.132788  

 6906 12:19:12.132848  ==

 6907 12:19:12.135746  Dram Type= 6, Freq= 0, CH_1, rank 1

 6908 12:19:12.138829  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6909 12:19:12.138916  ==

 6910 12:19:12.138980  

 6911 12:19:12.139040  

 6912 12:19:12.142549  	TX Vref Scan disable

 6913 12:19:12.142634   == TX Byte 0 ==

 6914 12:19:12.148873  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6915 12:19:12.152217  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6916 12:19:12.152300   == TX Byte 1 ==

 6917 12:19:12.158671  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6918 12:19:12.162387  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6919 12:19:12.162495  ==

 6920 12:19:12.165717  Dram Type= 6, Freq= 0, CH_1, rank 1

 6921 12:19:12.168762  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6922 12:19:12.168847  ==

 6923 12:19:12.168912  

 6924 12:19:12.168971  

 6925 12:19:12.171997  	TX Vref Scan disable

 6926 12:19:12.172079   == TX Byte 0 ==

 6927 12:19:12.178656  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6928 12:19:12.182263  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6929 12:19:12.182346   == TX Byte 1 ==

 6930 12:19:12.188919  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6931 12:19:12.192051  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6932 12:19:12.192134  

 6933 12:19:12.192200  [DATLAT]

 6934 12:19:12.195270  Freq=400, CH1 RK1

 6935 12:19:12.195353  

 6936 12:19:12.195417  DATLAT Default: 0xe

 6937 12:19:12.199325  0, 0xFFFF, sum = 0

 6938 12:19:12.199436  1, 0xFFFF, sum = 0

 6939 12:19:12.202234  2, 0xFFFF, sum = 0

 6940 12:19:12.202318  3, 0xFFFF, sum = 0

 6941 12:19:12.205442  4, 0xFFFF, sum = 0

 6942 12:19:12.205526  5, 0xFFFF, sum = 0

 6943 12:19:12.208734  6, 0xFFFF, sum = 0

 6944 12:19:12.208817  7, 0xFFFF, sum = 0

 6945 12:19:12.212382  8, 0xFFFF, sum = 0

 6946 12:19:12.212467  9, 0xFFFF, sum = 0

 6947 12:19:12.215365  10, 0xFFFF, sum = 0

 6948 12:19:12.215453  11, 0xFFFF, sum = 0

 6949 12:19:12.218897  12, 0xFFFF, sum = 0

 6950 12:19:12.218981  13, 0x0, sum = 1

 6951 12:19:12.221987  14, 0x0, sum = 2

 6952 12:19:12.222070  15, 0x0, sum = 3

 6953 12:19:12.225505  16, 0x0, sum = 4

 6954 12:19:12.225588  best_step = 14

 6955 12:19:12.225653  

 6956 12:19:12.225714  ==

 6957 12:19:12.228522  Dram Type= 6, Freq= 0, CH_1, rank 1

 6958 12:19:12.235321  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6959 12:19:12.235404  ==

 6960 12:19:12.235471  RX Vref Scan: 0

 6961 12:19:12.235532  

 6962 12:19:12.238682  RX Vref 0 -> 0, step: 1

 6963 12:19:12.238752  

 6964 12:19:12.241628  RX Delay -311 -> 252, step: 8

 6965 12:19:12.248680  iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440

 6966 12:19:12.251891  iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448

 6967 12:19:12.255714  iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440

 6968 12:19:12.258779  iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448

 6969 12:19:12.265239  iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440

 6970 12:19:12.268878  iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448

 6971 12:19:12.271941  iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448

 6972 12:19:12.275390  iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440

 6973 12:19:12.278557  iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448

 6974 12:19:12.285399  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 6975 12:19:12.289063  iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456

 6976 12:19:12.292006  iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448

 6977 12:19:12.298637  iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456

 6978 12:19:12.301784  iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448

 6979 12:19:12.305311  iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448

 6980 12:19:12.308403  iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448

 6981 12:19:12.308487  ==

 6982 12:19:12.311607  Dram Type= 6, Freq= 0, CH_1, rank 1

 6983 12:19:12.318625  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6984 12:19:12.318714  ==

 6985 12:19:12.318780  DQS Delay:

 6986 12:19:12.321692  DQS0 = 28, DQS1 = 32

 6987 12:19:12.321761  DQM Delay:

 6988 12:19:12.325233  DQM0 = 10, DQM1 = 11

 6989 12:19:12.325303  DQ Delay:

 6990 12:19:12.328362  DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4

 6991 12:19:12.331440  DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8

 6992 12:19:12.334938  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8

 6993 12:19:12.338647  DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16

 6994 12:19:12.338730  

 6995 12:19:12.338795  

 6996 12:19:12.345018  [DQSOSCAuto] RK1, (LSB)MR18= 0xc253, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps

 6997 12:19:12.348072  CH1 RK1: MR19=C0C, MR18=C253

 6998 12:19:12.354937  CH1_RK1: MR19=0xC0C, MR18=0xC253, DQSOSC=385, MR23=63, INC=398, DEC=265

 6999 12:19:12.358056  [RxdqsGatingPostProcess] freq 400

 7000 12:19:12.361935  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 7001 12:19:12.365150  best DQS0 dly(2T, 0.5T) = (0, 10)

 7002 12:19:12.368278  best DQS1 dly(2T, 0.5T) = (0, 10)

 7003 12:19:12.371510  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7004 12:19:12.375280  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7005 12:19:12.378464  best DQS0 dly(2T, 0.5T) = (0, 10)

 7006 12:19:12.381580  best DQS1 dly(2T, 0.5T) = (0, 10)

 7007 12:19:12.384774  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7008 12:19:12.388581  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7009 12:19:12.391802  Pre-setting of DQS Precalculation

 7010 12:19:12.395052  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 7011 12:19:12.401765  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 7012 12:19:12.411368  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 7013 12:19:12.411454  

 7014 12:19:12.411520  

 7015 12:19:12.414639  [Calibration Summary] 800 Mbps

 7016 12:19:12.414719  CH 0, Rank 0

 7017 12:19:12.418050  SW Impedance     : PASS

 7018 12:19:12.418123  DUTY Scan        : NO K

 7019 12:19:12.421353  ZQ Calibration   : PASS

 7020 12:19:12.424348  Jitter Meter     : NO K

 7021 12:19:12.424417  CBT Training     : PASS

 7022 12:19:12.427932  Write leveling   : PASS

 7023 12:19:12.431005  RX DQS gating    : PASS

 7024 12:19:12.431081  RX DQ/DQS(RDDQC) : PASS

 7025 12:19:12.434771  TX DQ/DQS        : PASS

 7026 12:19:12.434850  RX DATLAT        : PASS

 7027 12:19:12.437990  RX DQ/DQS(Engine): PASS

 7028 12:19:12.440846  TX OE            : NO K

 7029 12:19:12.440920  All Pass.

 7030 12:19:12.440988  

 7031 12:19:12.444288  CH 0, Rank 1

 7032 12:19:12.444359  SW Impedance     : PASS

 7033 12:19:12.447554  DUTY Scan        : NO K

 7034 12:19:12.447690  ZQ Calibration   : PASS

 7035 12:19:12.451050  Jitter Meter     : NO K

 7036 12:19:12.454233  CBT Training     : PASS

 7037 12:19:12.454304  Write leveling   : NO K

 7038 12:19:12.457733  RX DQS gating    : PASS

 7039 12:19:12.461023  RX DQ/DQS(RDDQC) : PASS

 7040 12:19:12.461104  TX DQ/DQS        : PASS

 7041 12:19:12.464320  RX DATLAT        : PASS

 7042 12:19:12.468041  RX DQ/DQS(Engine): PASS

 7043 12:19:12.468118  TX OE            : NO K

 7044 12:19:12.471136  All Pass.

 7045 12:19:12.471217  

 7046 12:19:12.471279  CH 1, Rank 0

 7047 12:19:12.474287  SW Impedance     : PASS

 7048 12:19:12.474363  DUTY Scan        : NO K

 7049 12:19:12.477497  ZQ Calibration   : PASS

 7050 12:19:12.480767  Jitter Meter     : NO K

 7051 12:19:12.480843  CBT Training     : PASS

 7052 12:19:12.484571  Write leveling   : PASS

 7053 12:19:12.487682  RX DQS gating    : PASS

 7054 12:19:12.487795  RX DQ/DQS(RDDQC) : PASS

 7055 12:19:12.491327  TX DQ/DQS        : PASS

 7056 12:19:12.491404  RX DATLAT        : PASS

 7057 12:19:12.494540  RX DQ/DQS(Engine): PASS

 7058 12:19:12.497822  TX OE            : NO K

 7059 12:19:12.497898  All Pass.

 7060 12:19:12.497968  

 7061 12:19:12.498028  CH 1, Rank 1

 7062 12:19:12.500973  SW Impedance     : PASS

 7063 12:19:12.504194  DUTY Scan        : NO K

 7064 12:19:12.504269  ZQ Calibration   : PASS

 7065 12:19:12.507295  Jitter Meter     : NO K

 7066 12:19:12.510964  CBT Training     : PASS

 7067 12:19:12.511036  Write leveling   : NO K

 7068 12:19:12.513968  RX DQS gating    : PASS

 7069 12:19:12.517607  RX DQ/DQS(RDDQC) : PASS

 7070 12:19:12.517684  TX DQ/DQS        : PASS

 7071 12:19:12.520767  RX DATLAT        : PASS

 7072 12:19:12.523907  RX DQ/DQS(Engine): PASS

 7073 12:19:12.523983  TX OE            : NO K

 7074 12:19:12.527105  All Pass.

 7075 12:19:12.527190  

 7076 12:19:12.527256  DramC Write-DBI off

 7077 12:19:12.530874  	PER_BANK_REFRESH: Hybrid Mode

 7078 12:19:12.530950  TX_TRACKING: ON

 7079 12:19:12.540846  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7080 12:19:12.543872  [FAST_K] Save calibration result to emmc

 7081 12:19:12.547479  dramc_set_vcore_voltage set vcore to 725000

 7082 12:19:12.550501  Read voltage for 1600, 0

 7083 12:19:12.550583  Vio18 = 0

 7084 12:19:12.554248  Vcore = 725000

 7085 12:19:12.554330  Vdram = 0

 7086 12:19:12.554394  Vddq = 0

 7087 12:19:12.557340  Vmddr = 0

 7088 12:19:12.560697  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7089 12:19:12.567263  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7090 12:19:12.567346  MEM_TYPE=3, freq_sel=13

 7091 12:19:12.570844  sv_algorithm_assistance_LP4_3733 

 7092 12:19:12.573982  ============ PULL DRAM RESETB DOWN ============

 7093 12:19:12.580698  ========== PULL DRAM RESETB DOWN end =========

 7094 12:19:12.584210  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7095 12:19:12.587348  =================================== 

 7096 12:19:12.590380  LPDDR4 DRAM CONFIGURATION

 7097 12:19:12.594082  =================================== 

 7098 12:19:12.594160  EX_ROW_EN[0]    = 0x0

 7099 12:19:12.597221  EX_ROW_EN[1]    = 0x0

 7100 12:19:12.600426  LP4Y_EN      = 0x0

 7101 12:19:12.600499  WORK_FSP     = 0x1

 7102 12:19:12.603712  WL           = 0x5

 7103 12:19:12.603784  RL           = 0x5

 7104 12:19:12.607416  BL           = 0x2

 7105 12:19:12.607513  RPST         = 0x0

 7106 12:19:12.610551  RD_PRE       = 0x0

 7107 12:19:12.610659  WR_PRE       = 0x1

 7108 12:19:12.613800  WR_PST       = 0x1

 7109 12:19:12.613882  DBI_WR       = 0x0

 7110 12:19:12.616739  DBI_RD       = 0x0

 7111 12:19:12.616845  OTF          = 0x1

 7112 12:19:12.620641  =================================== 

 7113 12:19:12.623428  =================================== 

 7114 12:19:12.627189  ANA top config

 7115 12:19:12.630388  =================================== 

 7116 12:19:12.630483  DLL_ASYNC_EN            =  0

 7117 12:19:12.633558  ALL_SLAVE_EN            =  0

 7118 12:19:12.637158  NEW_RANK_MODE           =  1

 7119 12:19:12.640444  DLL_IDLE_MODE           =  1

 7120 12:19:12.640525  LP45_APHY_COMB_EN       =  1

 7121 12:19:12.643549  TX_ODT_DIS              =  0

 7122 12:19:12.646675  NEW_8X_MODE             =  1

 7123 12:19:12.650330  =================================== 

 7124 12:19:12.653989  =================================== 

 7125 12:19:12.657142  data_rate                  = 3200

 7126 12:19:12.660259  CKR                        = 1

 7127 12:19:12.663547  DQ_P2S_RATIO               = 8

 7128 12:19:12.666687  =================================== 

 7129 12:19:12.666779  CA_P2S_RATIO               = 8

 7130 12:19:12.670536  DQ_CA_OPEN                 = 0

 7131 12:19:12.673696  DQ_SEMI_OPEN               = 0

 7132 12:19:12.676738  CA_SEMI_OPEN               = 0

 7133 12:19:12.680559  CA_FULL_RATE               = 0

 7134 12:19:12.683713  DQ_CKDIV4_EN               = 0

 7135 12:19:12.683844  CA_CKDIV4_EN               = 0

 7136 12:19:12.686757  CA_PREDIV_EN               = 0

 7137 12:19:12.690419  PH8_DLY                    = 12

 7138 12:19:12.693406  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7139 12:19:12.696836  DQ_AAMCK_DIV               = 4

 7140 12:19:12.699779  CA_AAMCK_DIV               = 4

 7141 12:19:12.699855  CA_ADMCK_DIV               = 4

 7142 12:19:12.703557  DQ_TRACK_CA_EN             = 0

 7143 12:19:12.706352  CA_PICK                    = 1600

 7144 12:19:12.709864  CA_MCKIO                   = 1600

 7145 12:19:12.713381  MCKIO_SEMI                 = 0

 7146 12:19:12.716294  PLL_FREQ                   = 3068

 7147 12:19:12.719938  DQ_UI_PI_RATIO             = 32

 7148 12:19:12.723193  CA_UI_PI_RATIO             = 0

 7149 12:19:12.726910  =================================== 

 7150 12:19:12.726990  =================================== 

 7151 12:19:12.729694  memory_type:LPDDR4         

 7152 12:19:12.733404  GP_NUM     : 10       

 7153 12:19:12.733507  SRAM_EN    : 1       

 7154 12:19:12.736615  MD32_EN    : 0       

 7155 12:19:12.739634  =================================== 

 7156 12:19:12.743498  [ANA_INIT] >>>>>>>>>>>>>> 

 7157 12:19:12.746827  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7158 12:19:12.749956  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7159 12:19:12.753022  =================================== 

 7160 12:19:12.753117  data_rate = 3200,PCW = 0X7600

 7161 12:19:12.756694  =================================== 

 7162 12:19:12.759635  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7163 12:19:12.766399  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7164 12:19:12.773440  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7165 12:19:12.776606  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7166 12:19:12.779620  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7167 12:19:12.783387  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7168 12:19:12.786535  [ANA_INIT] flow start 

 7169 12:19:12.786619  [ANA_INIT] PLL >>>>>>>> 

 7170 12:19:12.789643  [ANA_INIT] PLL <<<<<<<< 

 7171 12:19:12.793341  [ANA_INIT] MIDPI >>>>>>>> 

 7172 12:19:12.796638  [ANA_INIT] MIDPI <<<<<<<< 

 7173 12:19:12.796714  [ANA_INIT] DLL >>>>>>>> 

 7174 12:19:12.799917  [ANA_INIT] DLL <<<<<<<< 

 7175 12:19:12.803057  [ANA_INIT] flow end 

 7176 12:19:12.806130  ============ LP4 DIFF to SE enter ============

 7177 12:19:12.809827  ============ LP4 DIFF to SE exit  ============

 7178 12:19:12.812719  [ANA_INIT] <<<<<<<<<<<<< 

 7179 12:19:12.816461  [Flow] Enable top DCM control >>>>> 

 7180 12:19:12.819520  [Flow] Enable top DCM control <<<<< 

 7181 12:19:12.822715  Enable DLL master slave shuffle 

 7182 12:19:12.826356  ============================================================== 

 7183 12:19:12.829487  Gating Mode config

 7184 12:19:12.836141  ============================================================== 

 7185 12:19:12.836225  Config description: 

 7186 12:19:12.846269  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7187 12:19:12.852667  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7188 12:19:12.856177  SELPH_MODE            0: By rank         1: By Phase 

 7189 12:19:12.862835  ============================================================== 

 7190 12:19:12.866245  GAT_TRACK_EN                 =  1

 7191 12:19:12.869248  RX_GATING_MODE               =  2

 7192 12:19:12.872442  RX_GATING_TRACK_MODE         =  2

 7193 12:19:12.876214  SELPH_MODE                   =  1

 7194 12:19:12.879367  PICG_EARLY_EN                =  1

 7195 12:19:12.882357  VALID_LAT_VALUE              =  1

 7196 12:19:12.885989  ============================================================== 

 7197 12:19:12.889031  Enter into Gating configuration >>>> 

 7198 12:19:12.892299  Exit from Gating configuration <<<< 

 7199 12:19:12.896074  Enter into  DVFS_PRE_config >>>>> 

 7200 12:19:12.906128  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7201 12:19:12.909300  Exit from  DVFS_PRE_config <<<<< 

 7202 12:19:12.912911  Enter into PICG configuration >>>> 

 7203 12:19:12.915940  Exit from PICG configuration <<<< 

 7204 12:19:12.919483  [RX_INPUT] configuration >>>>> 

 7205 12:19:12.922446  [RX_INPUT] configuration <<<<< 

 7206 12:19:12.929487  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7207 12:19:12.932627  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7208 12:19:12.938880  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7209 12:19:12.945628  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7210 12:19:12.952106  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7211 12:19:12.959261  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7212 12:19:12.962112  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7213 12:19:12.965716  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7214 12:19:12.969012  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7215 12:19:12.975594  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7216 12:19:12.978557  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7217 12:19:12.982057  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7218 12:19:12.985423  =================================== 

 7219 12:19:12.988609  LPDDR4 DRAM CONFIGURATION

 7220 12:19:12.992078  =================================== 

 7221 12:19:12.992154  EX_ROW_EN[0]    = 0x0

 7222 12:19:12.995419  EX_ROW_EN[1]    = 0x0

 7223 12:19:12.998636  LP4Y_EN      = 0x0

 7224 12:19:12.998712  WORK_FSP     = 0x1

 7225 12:19:13.002186  WL           = 0x5

 7226 12:19:13.002262  RL           = 0x5

 7227 12:19:13.005435  BL           = 0x2

 7228 12:19:13.005503  RPST         = 0x0

 7229 12:19:13.008576  RD_PRE       = 0x0

 7230 12:19:13.008682  WR_PRE       = 0x1

 7231 12:19:13.011907  WR_PST       = 0x1

 7232 12:19:13.011988  DBI_WR       = 0x0

 7233 12:19:13.015532  DBI_RD       = 0x0

 7234 12:19:13.015647  OTF          = 0x1

 7235 12:19:13.018761  =================================== 

 7236 12:19:13.021753  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7237 12:19:13.028818  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7238 12:19:13.032415  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7239 12:19:13.035549  =================================== 

 7240 12:19:13.038702  LPDDR4 DRAM CONFIGURATION

 7241 12:19:13.041928  =================================== 

 7242 12:19:13.042014  EX_ROW_EN[0]    = 0x10

 7243 12:19:13.045601  EX_ROW_EN[1]    = 0x0

 7244 12:19:13.045683  LP4Y_EN      = 0x0

 7245 12:19:13.048754  WORK_FSP     = 0x1

 7246 12:19:13.052370  WL           = 0x5

 7247 12:19:13.052452  RL           = 0x5

 7248 12:19:13.055384  BL           = 0x2

 7249 12:19:13.055466  RPST         = 0x0

 7250 12:19:13.058474  RD_PRE       = 0x0

 7251 12:19:13.058556  WR_PRE       = 0x1

 7252 12:19:13.062165  WR_PST       = 0x1

 7253 12:19:13.062248  DBI_WR       = 0x0

 7254 12:19:13.065338  DBI_RD       = 0x0

 7255 12:19:13.065420  OTF          = 0x1

 7256 12:19:13.068414  =================================== 

 7257 12:19:13.075471  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7258 12:19:13.075553  ==

 7259 12:19:13.078728  Dram Type= 6, Freq= 0, CH_0, rank 0

 7260 12:19:13.081819  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7261 12:19:13.081928  ==

 7262 12:19:13.085496  [Duty_Offset_Calibration]

 7263 12:19:13.088598  	B0:2	B1:1	CA:1

 7264 12:19:13.088680  

 7265 12:19:13.091603  [DutyScan_Calibration_Flow] k_type=0

 7266 12:19:13.100074  

 7267 12:19:13.100156  ==CLK 0==

 7268 12:19:13.103624  Final CLK duty delay cell = 0

 7269 12:19:13.107328  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7270 12:19:13.110525  [0] MIN Duty = 4876%(X100), DQS PI = 48

 7271 12:19:13.110634  [0] AVG Duty = 5016%(X100)

 7272 12:19:13.110727  

 7273 12:19:13.113624  CH0 CLK Duty spec in!! Max-Min= 280%

 7274 12:19:13.120219  [DutyScan_Calibration_Flow] ====Done====

 7275 12:19:13.120301  

 7276 12:19:13.123505  [DutyScan_Calibration_Flow] k_type=1

 7277 12:19:13.139598  

 7278 12:19:13.139732  ==DQS 0 ==

 7279 12:19:13.142471  Final DQS duty delay cell = -4

 7280 12:19:13.146100  [-4] MAX Duty = 5125%(X100), DQS PI = 24

 7281 12:19:13.149253  [-4] MIN Duty = 4657%(X100), DQS PI = 0

 7282 12:19:13.152965  [-4] AVG Duty = 4891%(X100)

 7283 12:19:13.153060  

 7284 12:19:13.153123  ==DQS 1 ==

 7285 12:19:13.155987  Final DQS duty delay cell = 0

 7286 12:19:13.159085  [0] MAX Duty = 5187%(X100), DQS PI = 4

 7287 12:19:13.162863  [0] MIN Duty = 5031%(X100), DQS PI = 52

 7288 12:19:13.166010  [0] AVG Duty = 5109%(X100)

 7289 12:19:13.166092  

 7290 12:19:13.169243  CH0 DQS 0 Duty spec in!! Max-Min= 468%

 7291 12:19:13.169324  

 7292 12:19:13.173151  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 7293 12:19:13.176246  [DutyScan_Calibration_Flow] ====Done====

 7294 12:19:13.176341  

 7295 12:19:13.179332  [DutyScan_Calibration_Flow] k_type=3

 7296 12:19:13.196219  

 7297 12:19:13.196302  ==DQM 0 ==

 7298 12:19:13.199323  Final DQM duty delay cell = 0

 7299 12:19:13.202561  [0] MAX Duty = 5187%(X100), DQS PI = 28

 7300 12:19:13.205579  [0] MIN Duty = 4907%(X100), DQS PI = 56

 7301 12:19:13.209381  [0] AVG Duty = 5047%(X100)

 7302 12:19:13.209502  

 7303 12:19:13.209594  ==DQM 1 ==

 7304 12:19:13.212419  Final DQM duty delay cell = -4

 7305 12:19:13.215725  [-4] MAX Duty = 4969%(X100), DQS PI = 20

 7306 12:19:13.218765  [-4] MIN Duty = 4844%(X100), DQS PI = 14

 7307 12:19:13.222256  [-4] AVG Duty = 4906%(X100)

 7308 12:19:13.222351  

 7309 12:19:13.225802  CH0 DQM 0 Duty spec in!! Max-Min= 280%

 7310 12:19:13.225908  

 7311 12:19:13.228873  CH0 DQM 1 Duty spec in!! Max-Min= 125%

 7312 12:19:13.232356  [DutyScan_Calibration_Flow] ====Done====

 7313 12:19:13.232437  

 7314 12:19:13.235586  [DutyScan_Calibration_Flow] k_type=2

 7315 12:19:13.253382  

 7316 12:19:13.253463  ==DQ 0 ==

 7317 12:19:13.256954  Final DQ duty delay cell = 0

 7318 12:19:13.260430  [0] MAX Duty = 5062%(X100), DQS PI = 24

 7319 12:19:13.263577  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7320 12:19:13.263721  [0] AVG Duty = 4984%(X100)

 7321 12:19:13.263820  

 7322 12:19:13.267075  ==DQ 1 ==

 7323 12:19:13.270046  Final DQ duty delay cell = 0

 7324 12:19:13.273652  [0] MAX Duty = 5125%(X100), DQS PI = 6

 7325 12:19:13.277220  [0] MIN Duty = 4938%(X100), DQS PI = 34

 7326 12:19:13.277309  [0] AVG Duty = 5031%(X100)

 7327 12:19:13.277375  

 7328 12:19:13.280431  CH0 DQ 0 Duty spec in!! Max-Min= 155%

 7329 12:19:13.280508  

 7330 12:19:13.283443  CH0 DQ 1 Duty spec in!! Max-Min= 187%

 7331 12:19:13.290636  [DutyScan_Calibration_Flow] ====Done====

 7332 12:19:13.290743  ==

 7333 12:19:13.293836  Dram Type= 6, Freq= 0, CH_1, rank 0

 7334 12:19:13.296962  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7335 12:19:13.297038  ==

 7336 12:19:13.300066  [Duty_Offset_Calibration]

 7337 12:19:13.300138  	B0:1	B1:0	CA:0

 7338 12:19:13.300198  

 7339 12:19:13.303911  [DutyScan_Calibration_Flow] k_type=0

 7340 12:19:13.312660  

 7341 12:19:13.312740  ==CLK 0==

 7342 12:19:13.316415  Final CLK duty delay cell = -4

 7343 12:19:13.319489  [-4] MAX Duty = 4969%(X100), DQS PI = 26

 7344 12:19:13.322680  [-4] MIN Duty = 4844%(X100), DQS PI = 0

 7345 12:19:13.326256  [-4] AVG Duty = 4906%(X100)

 7346 12:19:13.326347  

 7347 12:19:13.329251  CH1 CLK Duty spec in!! Max-Min= 125%

 7348 12:19:13.332934  [DutyScan_Calibration_Flow] ====Done====

 7349 12:19:13.333015  

 7350 12:19:13.336055  [DutyScan_Calibration_Flow] k_type=1

 7351 12:19:13.352851  

 7352 12:19:13.352933  ==DQS 0 ==

 7353 12:19:13.356317  Final DQS duty delay cell = 0

 7354 12:19:13.359314  [0] MAX Duty = 5094%(X100), DQS PI = 26

 7355 12:19:13.363071  [0] MIN Duty = 4844%(X100), DQS PI = 12

 7356 12:19:13.366232  [0] AVG Duty = 4969%(X100)

 7357 12:19:13.366314  

 7358 12:19:13.366377  ==DQS 1 ==

 7359 12:19:13.369306  Final DQS duty delay cell = 0

 7360 12:19:13.373049  [0] MAX Duty = 5249%(X100), DQS PI = 48

 7361 12:19:13.376031  [0] MIN Duty = 4938%(X100), DQS PI = 40

 7362 12:19:13.379525  [0] AVG Duty = 5093%(X100)

 7363 12:19:13.379632  

 7364 12:19:13.382680  CH1 DQS 0 Duty spec in!! Max-Min= 250%

 7365 12:19:13.382765  

 7366 12:19:13.385985  CH1 DQS 1 Duty spec in!! Max-Min= 311%

 7367 12:19:13.389288  [DutyScan_Calibration_Flow] ====Done====

 7368 12:19:13.389370  

 7369 12:19:13.392683  [DutyScan_Calibration_Flow] k_type=3

 7370 12:19:13.410067  

 7371 12:19:13.410153  ==DQM 0 ==

 7372 12:19:13.413271  Final DQM duty delay cell = 0

 7373 12:19:13.416250  [0] MAX Duty = 5187%(X100), DQS PI = 36

 7374 12:19:13.419458  [0] MIN Duty = 5031%(X100), DQS PI = 14

 7375 12:19:13.423210  [0] AVG Duty = 5109%(X100)

 7376 12:19:13.423291  

 7377 12:19:13.423357  ==DQM 1 ==

 7378 12:19:13.426562  Final DQM duty delay cell = 0

 7379 12:19:13.429729  [0] MAX Duty = 5093%(X100), DQS PI = 8

 7380 12:19:13.433348  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7381 12:19:13.433455  [0] AVG Duty = 5000%(X100)

 7382 12:19:13.436354  

 7383 12:19:13.439612  CH1 DQM 0 Duty spec in!! Max-Min= 156%

 7384 12:19:13.439717  

 7385 12:19:13.443340  CH1 DQM 1 Duty spec in!! Max-Min= 186%

 7386 12:19:13.446488  [DutyScan_Calibration_Flow] ====Done====

 7387 12:19:13.446569  

 7388 12:19:13.449490  [DutyScan_Calibration_Flow] k_type=2

 7389 12:19:13.465568  

 7390 12:19:13.465666  ==DQ 0 ==

 7391 12:19:13.469237  Final DQ duty delay cell = -4

 7392 12:19:13.472394  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 7393 12:19:13.475506  [-4] MIN Duty = 4875%(X100), DQS PI = 12

 7394 12:19:13.479386  [-4] AVG Duty = 4953%(X100)

 7395 12:19:13.479485  

 7396 12:19:13.479576  ==DQ 1 ==

 7397 12:19:13.482481  Final DQ duty delay cell = 0

 7398 12:19:13.485717  [0] MAX Duty = 5125%(X100), DQS PI = 10

 7399 12:19:13.488823  [0] MIN Duty = 4907%(X100), DQS PI = 42

 7400 12:19:13.492618  [0] AVG Duty = 5016%(X100)

 7401 12:19:13.492714  

 7402 12:19:13.495468  CH1 DQ 0 Duty spec in!! Max-Min= 156%

 7403 12:19:13.495566  

 7404 12:19:13.499154  CH1 DQ 1 Duty spec in!! Max-Min= 218%

 7405 12:19:13.502252  [DutyScan_Calibration_Flow] ====Done====

 7406 12:19:13.505833  nWR fixed to 30

 7407 12:19:13.505930  [ModeRegInit_LP4] CH0 RK0

 7408 12:19:13.509324  [ModeRegInit_LP4] CH0 RK1

 7409 12:19:13.512586  [ModeRegInit_LP4] CH1 RK0

 7410 12:19:13.515825  [ModeRegInit_LP4] CH1 RK1

 7411 12:19:13.515905  match AC timing 5

 7412 12:19:13.522299  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7413 12:19:13.525574  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7414 12:19:13.528718  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7415 12:19:13.535736  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7416 12:19:13.538916  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7417 12:19:13.539026  [MiockJmeterHQA]

 7418 12:19:13.539090  

 7419 12:19:13.542427  [DramcMiockJmeter] u1RxGatingPI = 0

 7420 12:19:13.545255  0 : 4255, 4029

 7421 12:19:13.545330  4 : 4363, 4138

 7422 12:19:13.548861  8 : 4252, 4027

 7423 12:19:13.548943  12 : 4253, 4026

 7424 12:19:13.549008  16 : 4363, 4137

 7425 12:19:13.551817  20 : 4363, 4137

 7426 12:19:13.551898  24 : 4252, 4027

 7427 12:19:13.555557  28 : 4252, 4026

 7428 12:19:13.555672  32 : 4252, 4027

 7429 12:19:13.558426  36 : 4252, 4027

 7430 12:19:13.558510  40 : 4255, 4029

 7431 12:19:13.562232  44 : 4363, 4138

 7432 12:19:13.562315  48 : 4253, 4026

 7433 12:19:13.562380  52 : 4252, 4027

 7434 12:19:13.565250  56 : 4252, 4027

 7435 12:19:13.565333  60 : 4255, 4029

 7436 12:19:13.568490  64 : 4249, 4027

 7437 12:19:13.568589  68 : 4363, 4140

 7438 12:19:13.571502  72 : 4361, 4137

 7439 12:19:13.571614  76 : 4252, 4030

 7440 12:19:13.575224  80 : 4250, 4026

 7441 12:19:13.575335  84 : 4250, 4027

 7442 12:19:13.575430  88 : 4252, 109

 7443 12:19:13.578390  92 : 4361, 0

 7444 12:19:13.578473  96 : 4250, 0

 7445 12:19:13.581636  100 : 4252, 0

 7446 12:19:13.581720  104 : 4249, 0

 7447 12:19:13.581786  108 : 4250, 0

 7448 12:19:13.585427  112 : 4253, 0

 7449 12:19:13.585510  116 : 4249, 0

 7450 12:19:13.585575  120 : 4250, 0

 7451 12:19:13.588519  124 : 4253, 0

 7452 12:19:13.588603  128 : 4360, 0

 7453 12:19:13.591746  132 : 4250, 0

 7454 12:19:13.591844  136 : 4361, 0

 7455 12:19:13.591910  140 : 4249, 0

 7456 12:19:13.594955  144 : 4250, 0

 7457 12:19:13.595067  148 : 4250, 0

 7458 12:19:13.598646  152 : 4252, 0

 7459 12:19:13.598760  156 : 4250, 0

 7460 12:19:13.598827  160 : 4250, 0

 7461 12:19:13.601614  164 : 4253, 0

 7462 12:19:13.601700  168 : 4249, 0

 7463 12:19:13.605429  172 : 4250, 0

 7464 12:19:13.605515  176 : 4250, 0

 7465 12:19:13.605581  180 : 4360, 0

 7466 12:19:13.608645  184 : 4361, 0

 7467 12:19:13.608730  188 : 4250, 0

 7468 12:19:13.608798  192 : 4250, 0

 7469 12:19:13.611840  196 : 4360, 0

 7470 12:19:13.611926  200 : 4250, 1

 7471 12:19:13.614868  204 : 4250, 1495

 7472 12:19:13.614953  208 : 4363, 4129

 7473 12:19:13.618636  212 : 4250, 4027

 7474 12:19:13.618722  216 : 4249, 4027

 7475 12:19:13.621739  220 : 4250, 4026

 7476 12:19:13.621824  224 : 4253, 4029

 7477 12:19:13.624752  228 : 4250, 4027

 7478 12:19:13.624852  232 : 4249, 4027

 7479 12:19:13.624919  236 : 4360, 4137

 7480 12:19:13.628417  240 : 4250, 4027

 7481 12:19:13.628506  244 : 4250, 4027

 7482 12:19:13.631474  248 : 4361, 4138

 7483 12:19:13.631593  252 : 4250, 4027

 7484 12:19:13.634714  256 : 4253, 4026

 7485 12:19:13.634795  260 : 4363, 4140

 7486 12:19:13.638351  264 : 4250, 4027

 7487 12:19:13.638450  268 : 4250, 4027

 7488 12:19:13.641489  272 : 4250, 4026

 7489 12:19:13.641585  276 : 4253, 4029

 7490 12:19:13.645083  280 : 4250, 4027

 7491 12:19:13.645167  284 : 4250, 4027

 7492 12:19:13.648738  288 : 4360, 4137

 7493 12:19:13.648834  292 : 4250, 4027

 7494 12:19:13.648922  296 : 4250, 4027

 7495 12:19:13.651431  300 : 4360, 4138

 7496 12:19:13.651514  304 : 4250, 4027

 7497 12:19:13.654877  308 : 4250, 3962

 7498 12:19:13.654983  312 : 4363, 1850

 7499 12:19:13.655083  

 7500 12:19:13.658485  	MIOCK jitter meter	ch=0

 7501 12:19:13.658576  

 7502 12:19:13.661714  1T = (312-88) = 224 dly cells

 7503 12:19:13.668419  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps

 7504 12:19:13.668514  ==

 7505 12:19:13.671471  Dram Type= 6, Freq= 0, CH_0, rank 0

 7506 12:19:13.674653  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7507 12:19:13.674800  ==

 7508 12:19:13.681520  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7509 12:19:13.684760  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7510 12:19:13.688468  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7511 12:19:13.694645  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7512 12:19:13.703595  [CA 0] Center 42 (12~73) winsize 62

 7513 12:19:13.706654  [CA 1] Center 42 (12~73) winsize 62

 7514 12:19:13.710358  [CA 2] Center 38 (8~68) winsize 61

 7515 12:19:13.713571  [CA 3] Center 37 (8~67) winsize 60

 7516 12:19:13.716670  [CA 4] Center 36 (6~66) winsize 61

 7517 12:19:13.719817  [CA 5] Center 35 (6~64) winsize 59

 7518 12:19:13.719889  

 7519 12:19:13.723525  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7520 12:19:13.723622  

 7521 12:19:13.726715  [CATrainingPosCal] consider 1 rank data

 7522 12:19:13.729703  u2DelayCellTimex100 = 290/100 ps

 7523 12:19:13.733259  CA0 delay=42 (12~73),Diff = 7 PI (23 cell)

 7524 12:19:13.740306  CA1 delay=42 (12~73),Diff = 7 PI (23 cell)

 7525 12:19:13.743376  CA2 delay=38 (8~68),Diff = 3 PI (10 cell)

 7526 12:19:13.746571  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7527 12:19:13.749849  CA4 delay=36 (6~66),Diff = 1 PI (3 cell)

 7528 12:19:13.753108  CA5 delay=35 (6~64),Diff = 0 PI (0 cell)

 7529 12:19:13.753190  

 7530 12:19:13.756865  CA PerBit enable=1, Macro0, CA PI delay=35

 7531 12:19:13.756948  

 7532 12:19:13.759902  [CBTSetCACLKResult] CA Dly = 35

 7533 12:19:13.763588  CS Dly: 9 (0~40)

 7534 12:19:13.766775  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7535 12:19:13.769912  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7536 12:19:13.769995  ==

 7537 12:19:13.773014  Dram Type= 6, Freq= 0, CH_0, rank 1

 7538 12:19:13.776292  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7539 12:19:13.779903  ==

 7540 12:19:13.783396  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7541 12:19:13.786792  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7542 12:19:13.793276  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7543 12:19:13.796688  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7544 12:19:13.806932  [CA 0] Center 42 (12~73) winsize 62

 7545 12:19:13.809897  [CA 1] Center 42 (12~73) winsize 62

 7546 12:19:13.813501  [CA 2] Center 37 (8~67) winsize 60

 7547 12:19:13.816772  [CA 3] Center 37 (7~68) winsize 62

 7548 12:19:13.819936  [CA 4] Center 35 (5~65) winsize 61

 7549 12:19:13.823358  [CA 5] Center 35 (5~65) winsize 61

 7550 12:19:13.823464  

 7551 12:19:13.826625  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7552 12:19:13.826732  

 7553 12:19:13.829701  [CATrainingPosCal] consider 2 rank data

 7554 12:19:13.833443  u2DelayCellTimex100 = 290/100 ps

 7555 12:19:13.836450  CA0 delay=42 (12~73),Diff = 7 PI (23 cell)

 7556 12:19:13.843572  CA1 delay=42 (12~73),Diff = 7 PI (23 cell)

 7557 12:19:13.846720  CA2 delay=37 (8~67),Diff = 2 PI (6 cell)

 7558 12:19:13.849593  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7559 12:19:13.853361  CA4 delay=35 (6~65),Diff = 0 PI (0 cell)

 7560 12:19:13.856623  CA5 delay=35 (6~64),Diff = 0 PI (0 cell)

 7561 12:19:13.856704  

 7562 12:19:13.859886  CA PerBit enable=1, Macro0, CA PI delay=35

 7563 12:19:13.859967  

 7564 12:19:13.862954  [CBTSetCACLKResult] CA Dly = 35

 7565 12:19:13.866599  CS Dly: 10 (0~42)

 7566 12:19:13.869796  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7567 12:19:13.873100  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7568 12:19:13.873180  

 7569 12:19:13.876344  ----->DramcWriteLeveling(PI) begin...

 7570 12:19:13.876426  ==

 7571 12:19:13.880106  Dram Type= 6, Freq= 0, CH_0, rank 0

 7572 12:19:13.883256  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7573 12:19:13.886436  ==

 7574 12:19:13.886517  Write leveling (Byte 0): 35 => 35

 7575 12:19:13.889614  Write leveling (Byte 1): 28 => 28

 7576 12:19:13.893425  DramcWriteLeveling(PI) end<-----

 7577 12:19:13.893506  

 7578 12:19:13.893571  ==

 7579 12:19:13.896486  Dram Type= 6, Freq= 0, CH_0, rank 0

 7580 12:19:13.903126  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7581 12:19:13.903209  ==

 7582 12:19:13.906340  [Gating] SW mode calibration

 7583 12:19:13.912994  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7584 12:19:13.916592  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7585 12:19:13.922791   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7586 12:19:13.926281   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7587 12:19:13.929773   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7588 12:19:13.936463   1  4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)

 7589 12:19:13.939856   1  4 16 | B1->B0 | 2323 3636 | 1 1 | (1 1) (0 0)

 7590 12:19:13.942926   1  4 20 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)

 7591 12:19:13.946237   1  4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)

 7592 12:19:13.952849   1  4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)

 7593 12:19:13.956881   1  5  0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)

 7594 12:19:13.959414   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7595 12:19:13.966050   1  5  8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)

 7596 12:19:13.969684   1  5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)

 7597 12:19:13.972962   1  5 16 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 0)

 7598 12:19:13.979397   1  5 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)

 7599 12:19:13.982686   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7600 12:19:13.986393   1  5 28 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)

 7601 12:19:13.992794   1  6  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7602 12:19:13.996009   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7603 12:19:13.999135   1  6  8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)

 7604 12:19:14.006366   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 7605 12:19:14.009519   1  6 16 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)

 7606 12:19:14.012737   1  6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 7607 12:19:14.019585   1  6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 7608 12:19:14.022857   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7609 12:19:14.026295   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7610 12:19:14.032442   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7611 12:19:14.036136   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7612 12:19:14.039345   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7613 12:19:14.045670   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7614 12:19:14.049444   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7615 12:19:14.052612   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7616 12:19:14.059352   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7617 12:19:14.062802   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7618 12:19:14.066090   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7619 12:19:14.069107   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7620 12:19:14.075746   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7621 12:19:14.079108   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7622 12:19:14.082457   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7623 12:19:14.088822   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7624 12:19:14.092286   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7625 12:19:14.095992   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7626 12:19:14.102892   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7627 12:19:14.105933   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7628 12:19:14.108830   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7629 12:19:14.115664   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7630 12:19:14.118855   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7631 12:19:14.122001  Total UI for P1: 0, mck2ui 16

 7632 12:19:14.125876  best dqsien dly found for B0: ( 1,  9, 14)

 7633 12:19:14.128952   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7634 12:19:14.131988  Total UI for P1: 0, mck2ui 16

 7635 12:19:14.135463  best dqsien dly found for B1: ( 1,  9, 20)

 7636 12:19:14.138969  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 7637 12:19:14.142273  best DQS1 dly(MCK, UI, PI) = (1, 9, 20)

 7638 12:19:14.142354  

 7639 12:19:14.148678  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 7640 12:19:14.152172  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)

 7641 12:19:14.155218  [Gating] SW calibration Done

 7642 12:19:14.155313  ==

 7643 12:19:14.159005  Dram Type= 6, Freq= 0, CH_0, rank 0

 7644 12:19:14.162091  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7645 12:19:14.162172  ==

 7646 12:19:14.162236  RX Vref Scan: 0

 7647 12:19:14.165137  

 7648 12:19:14.165222  RX Vref 0 -> 0, step: 1

 7649 12:19:14.165289  

 7650 12:19:14.168929  RX Delay 0 -> 252, step: 8

 7651 12:19:14.172223  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 7652 12:19:14.175410  iDelay=200, Bit 1, Center 143 (88 ~ 199) 112

 7653 12:19:14.181763  iDelay=200, Bit 2, Center 131 (80 ~ 183) 104

 7654 12:19:14.185466  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 7655 12:19:14.188540  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7656 12:19:14.191777  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7657 12:19:14.195601  iDelay=200, Bit 6, Center 139 (88 ~ 191) 104

 7658 12:19:14.198616  iDelay=200, Bit 7, Center 143 (96 ~ 191) 96

 7659 12:19:14.205280  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 7660 12:19:14.208773  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 7661 12:19:14.211950  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 7662 12:19:14.215163  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7663 12:19:14.218624  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 7664 12:19:14.225312  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 7665 12:19:14.228593  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7666 12:19:14.232039  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7667 12:19:14.232125  ==

 7668 12:19:14.235348  Dram Type= 6, Freq= 0, CH_0, rank 0

 7669 12:19:14.238554  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7670 12:19:14.242246  ==

 7671 12:19:14.242330  DQS Delay:

 7672 12:19:14.242397  DQS0 = 0, DQS1 = 0

 7673 12:19:14.245132  DQM Delay:

 7674 12:19:14.245216  DQM0 = 136, DQM1 = 130

 7675 12:19:14.248899  DQ Delay:

 7676 12:19:14.251990  DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135

 7677 12:19:14.255143  DQ4 =139, DQ5 =123, DQ6 =139, DQ7 =143

 7678 12:19:14.258584  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123

 7679 12:19:14.261760  DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135

 7680 12:19:14.261844  

 7681 12:19:14.261911  

 7682 12:19:14.261973  ==

 7683 12:19:14.264928  Dram Type= 6, Freq= 0, CH_0, rank 0

 7684 12:19:14.268691  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7685 12:19:14.268781  ==

 7686 12:19:14.268848  

 7687 12:19:14.272018  

 7688 12:19:14.272102  	TX Vref Scan disable

 7689 12:19:14.275112   == TX Byte 0 ==

 7690 12:19:14.278884  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 7691 12:19:14.282149  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7692 12:19:14.285344   == TX Byte 1 ==

 7693 12:19:14.288509  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 7694 12:19:14.291582  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 7695 12:19:14.291691  ==

 7696 12:19:14.295111  Dram Type= 6, Freq= 0, CH_0, rank 0

 7697 12:19:14.301908  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7698 12:19:14.301994  ==

 7699 12:19:14.313986  

 7700 12:19:14.317253  TX Vref early break, caculate TX vref

 7701 12:19:14.320356  TX Vref=16, minBit 0, minWin=23, winSum=380

 7702 12:19:14.323461  TX Vref=18, minBit 3, minWin=23, winSum=385

 7703 12:19:14.326745  TX Vref=20, minBit 1, minWin=24, winSum=399

 7704 12:19:14.330332  TX Vref=22, minBit 0, minWin=24, winSum=407

 7705 12:19:14.333867  TX Vref=24, minBit 6, minWin=25, winSum=416

 7706 12:19:14.340450  TX Vref=26, minBit 2, minWin=25, winSum=423

 7707 12:19:14.343707  TX Vref=28, minBit 1, minWin=25, winSum=426

 7708 12:19:14.346839  TX Vref=30, minBit 1, minWin=24, winSum=409

 7709 12:19:14.350215  TX Vref=32, minBit 6, minWin=23, winSum=406

 7710 12:19:14.353533  TX Vref=34, minBit 6, minWin=23, winSum=395

 7711 12:19:14.360376  [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28

 7712 12:19:14.360456  

 7713 12:19:14.363475  Final TX Range 0 Vref 28

 7714 12:19:14.363584  

 7715 12:19:14.363711  ==

 7716 12:19:14.366886  Dram Type= 6, Freq= 0, CH_0, rank 0

 7717 12:19:14.370206  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7718 12:19:14.370286  ==

 7719 12:19:14.370351  

 7720 12:19:14.370411  

 7721 12:19:14.373645  	TX Vref Scan disable

 7722 12:19:14.380241  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 7723 12:19:14.380324   == TX Byte 0 ==

 7724 12:19:14.383257  u2DelayCellOfst[0]=10 cells (3 PI)

 7725 12:19:14.387062  u2DelayCellOfst[1]=13 cells (4 PI)

 7726 12:19:14.390296  u2DelayCellOfst[2]=10 cells (3 PI)

 7727 12:19:14.393421  u2DelayCellOfst[3]=10 cells (3 PI)

 7728 12:19:14.396513  u2DelayCellOfst[4]=6 cells (2 PI)

 7729 12:19:14.400147  u2DelayCellOfst[5]=0 cells (0 PI)

 7730 12:19:14.403232  u2DelayCellOfst[6]=16 cells (5 PI)

 7731 12:19:14.407092  u2DelayCellOfst[7]=16 cells (5 PI)

 7732 12:19:14.410122  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 7733 12:19:14.413268  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7734 12:19:14.416522   == TX Byte 1 ==

 7735 12:19:14.416597  u2DelayCellOfst[8]=0 cells (0 PI)

 7736 12:19:14.420380  u2DelayCellOfst[9]=3 cells (1 PI)

 7737 12:19:14.423577  u2DelayCellOfst[10]=6 cells (2 PI)

 7738 12:19:14.426709  u2DelayCellOfst[11]=3 cells (1 PI)

 7739 12:19:14.429913  u2DelayCellOfst[12]=10 cells (3 PI)

 7740 12:19:14.433010  u2DelayCellOfst[13]=10 cells (3 PI)

 7741 12:19:14.436805  u2DelayCellOfst[14]=13 cells (4 PI)

 7742 12:19:14.439936  u2DelayCellOfst[15]=10 cells (3 PI)

 7743 12:19:14.443176  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 7744 12:19:14.449948  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 7745 12:19:14.450025  DramC Write-DBI on

 7746 12:19:14.450091  ==

 7747 12:19:14.453525  Dram Type= 6, Freq= 0, CH_0, rank 0

 7748 12:19:14.456641  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7749 12:19:14.459861  ==

 7750 12:19:14.459939  

 7751 12:19:14.460002  

 7752 12:19:14.460063  	TX Vref Scan disable

 7753 12:19:14.462986   == TX Byte 0 ==

 7754 12:19:14.466621  Update DQM dly =734 (2 ,6, 30)  DQM OEN =(3 ,3)

 7755 12:19:14.470176   == TX Byte 1 ==

 7756 12:19:14.473157  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 7757 12:19:14.476821  DramC Write-DBI off

 7758 12:19:14.476899  

 7759 12:19:14.476963  [DATLAT]

 7760 12:19:14.477028  Freq=1600, CH0 RK0

 7761 12:19:14.477090  

 7762 12:19:14.480298  DATLAT Default: 0xf

 7763 12:19:14.480369  0, 0xFFFF, sum = 0

 7764 12:19:14.483265  1, 0xFFFF, sum = 0

 7765 12:19:14.483345  2, 0xFFFF, sum = 0

 7766 12:19:14.486750  3, 0xFFFF, sum = 0

 7767 12:19:14.490261  4, 0xFFFF, sum = 0

 7768 12:19:14.490339  5, 0xFFFF, sum = 0

 7769 12:19:14.493112  6, 0xFFFF, sum = 0

 7770 12:19:14.493185  7, 0xFFFF, sum = 0

 7771 12:19:14.496231  8, 0xFFFF, sum = 0

 7772 12:19:14.496305  9, 0xFFFF, sum = 0

 7773 12:19:14.499780  10, 0xFFFF, sum = 0

 7774 12:19:14.499856  11, 0xFFFF, sum = 0

 7775 12:19:14.503165  12, 0xFFFF, sum = 0

 7776 12:19:14.503237  13, 0xFFFF, sum = 0

 7777 12:19:14.506316  14, 0x0, sum = 1

 7778 12:19:14.506387  15, 0x0, sum = 2

 7779 12:19:14.510109  16, 0x0, sum = 3

 7780 12:19:14.510186  17, 0x0, sum = 4

 7781 12:19:14.512985  best_step = 15

 7782 12:19:14.513059  

 7783 12:19:14.513120  ==

 7784 12:19:14.516401  Dram Type= 6, Freq= 0, CH_0, rank 0

 7785 12:19:14.520024  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7786 12:19:14.520102  ==

 7787 12:19:14.520167  RX Vref Scan: 1

 7788 12:19:14.523127  

 7789 12:19:14.523196  Set Vref Range= 24 -> 127

 7790 12:19:14.523260  

 7791 12:19:14.526298  RX Vref 24 -> 127, step: 1

 7792 12:19:14.526367  

 7793 12:19:14.530188  RX Delay 27 -> 252, step: 4

 7794 12:19:14.530261  

 7795 12:19:14.533407  Set Vref, RX VrefLevel [Byte0]: 24

 7796 12:19:14.536474                           [Byte1]: 24

 7797 12:19:14.536541  

 7798 12:19:14.539676  Set Vref, RX VrefLevel [Byte0]: 25

 7799 12:19:14.543408                           [Byte1]: 25

 7800 12:19:14.543473  

 7801 12:19:14.546530  Set Vref, RX VrefLevel [Byte0]: 26

 7802 12:19:14.550229                           [Byte1]: 26

 7803 12:19:14.553236  

 7804 12:19:14.553304  Set Vref, RX VrefLevel [Byte0]: 27

 7805 12:19:14.556974                           [Byte1]: 27

 7806 12:19:14.561273  

 7807 12:19:14.561364  Set Vref, RX VrefLevel [Byte0]: 28

 7808 12:19:14.564345                           [Byte1]: 28

 7809 12:19:14.568340  

 7810 12:19:14.568411  Set Vref, RX VrefLevel [Byte0]: 29

 7811 12:19:14.571949                           [Byte1]: 29

 7812 12:19:14.575851  

 7813 12:19:14.575922  Set Vref, RX VrefLevel [Byte0]: 30

 7814 12:19:14.579456                           [Byte1]: 30

 7815 12:19:14.583239  

 7816 12:19:14.586846  Set Vref, RX VrefLevel [Byte0]: 31

 7817 12:19:14.590255                           [Byte1]: 31

 7818 12:19:14.590331  

 7819 12:19:14.593416  Set Vref, RX VrefLevel [Byte0]: 32

 7820 12:19:14.596639                           [Byte1]: 32

 7821 12:19:14.596711  

 7822 12:19:14.599853  Set Vref, RX VrefLevel [Byte0]: 33

 7823 12:19:14.603519                           [Byte1]: 33

 7824 12:19:14.603592  

 7825 12:19:14.606601  Set Vref, RX VrefLevel [Byte0]: 34

 7826 12:19:14.610295                           [Byte1]: 34

 7827 12:19:14.613477  

 7828 12:19:14.613561  Set Vref, RX VrefLevel [Byte0]: 35

 7829 12:19:14.617055                           [Byte1]: 35

 7830 12:19:14.621273  

 7831 12:19:14.621345  Set Vref, RX VrefLevel [Byte0]: 36

 7832 12:19:14.624489                           [Byte1]: 36

 7833 12:19:14.628975  

 7834 12:19:14.629046  Set Vref, RX VrefLevel [Byte0]: 37

 7835 12:19:14.632007                           [Byte1]: 37

 7836 12:19:14.636503  

 7837 12:19:14.636575  Set Vref, RX VrefLevel [Byte0]: 38

 7838 12:19:14.639847                           [Byte1]: 38

 7839 12:19:14.644171  

 7840 12:19:14.644249  Set Vref, RX VrefLevel [Byte0]: 39

 7841 12:19:14.647404                           [Byte1]: 39

 7842 12:19:14.651735  

 7843 12:19:14.651816  Set Vref, RX VrefLevel [Byte0]: 40

 7844 12:19:14.654706                           [Byte1]: 40

 7845 12:19:14.659098  

 7846 12:19:14.659170  Set Vref, RX VrefLevel [Byte0]: 41

 7847 12:19:14.662178                           [Byte1]: 41

 7848 12:19:14.666551  

 7849 12:19:14.666621  Set Vref, RX VrefLevel [Byte0]: 42

 7850 12:19:14.669786                           [Byte1]: 42

 7851 12:19:14.674182  

 7852 12:19:14.674255  Set Vref, RX VrefLevel [Byte0]: 43

 7853 12:19:14.677309                           [Byte1]: 43

 7854 12:19:14.681573  

 7855 12:19:14.681644  Set Vref, RX VrefLevel [Byte0]: 44

 7856 12:19:14.684901                           [Byte1]: 44

 7857 12:19:14.689162  

 7858 12:19:14.689237  Set Vref, RX VrefLevel [Byte0]: 45

 7859 12:19:14.692300                           [Byte1]: 45

 7860 12:19:14.696290  

 7861 12:19:14.696369  Set Vref, RX VrefLevel [Byte0]: 46

 7862 12:19:14.699695                           [Byte1]: 46

 7863 12:19:14.704145  

 7864 12:19:14.704216  Set Vref, RX VrefLevel [Byte0]: 47

 7865 12:19:14.707422                           [Byte1]: 47

 7866 12:19:14.711702  

 7867 12:19:14.711795  Set Vref, RX VrefLevel [Byte0]: 48

 7868 12:19:14.714850                           [Byte1]: 48

 7869 12:19:14.719281  

 7870 12:19:14.719363  Set Vref, RX VrefLevel [Byte0]: 49

 7871 12:19:14.722275                           [Byte1]: 49

 7872 12:19:14.726662  

 7873 12:19:14.726737  Set Vref, RX VrefLevel [Byte0]: 50

 7874 12:19:14.729923                           [Byte1]: 50

 7875 12:19:14.734372  

 7876 12:19:14.734449  Set Vref, RX VrefLevel [Byte0]: 51

 7877 12:19:14.737499                           [Byte1]: 51

 7878 12:19:14.741860  

 7879 12:19:14.741968  Set Vref, RX VrefLevel [Byte0]: 52

 7880 12:19:14.745326                           [Byte1]: 52

 7881 12:19:14.749226  

 7882 12:19:14.749300  Set Vref, RX VrefLevel [Byte0]: 53

 7883 12:19:14.752449                           [Byte1]: 53

 7884 12:19:14.756670  

 7885 12:19:14.756742  Set Vref, RX VrefLevel [Byte0]: 54

 7886 12:19:14.760314                           [Byte1]: 54

 7887 12:19:14.764279  

 7888 12:19:14.764356  Set Vref, RX VrefLevel [Byte0]: 55

 7889 12:19:14.767981                           [Byte1]: 55

 7890 12:19:14.772115  

 7891 12:19:14.772190  Set Vref, RX VrefLevel [Byte0]: 56

 7892 12:19:14.775191                           [Byte1]: 56

 7893 12:19:14.779270  

 7894 12:19:14.779349  Set Vref, RX VrefLevel [Byte0]: 57

 7895 12:19:14.783137                           [Byte1]: 57

 7896 12:19:14.786924  

 7897 12:19:14.786999  Set Vref, RX VrefLevel [Byte0]: 58

 7898 12:19:14.790513                           [Byte1]: 58

 7899 12:19:14.794465  

 7900 12:19:14.794540  Set Vref, RX VrefLevel [Byte0]: 59

 7901 12:19:14.797572                           [Byte1]: 59

 7902 12:19:14.801854  

 7903 12:19:14.801925  Set Vref, RX VrefLevel [Byte0]: 60

 7904 12:19:14.805311                           [Byte1]: 60

 7905 12:19:14.809485  

 7906 12:19:14.809558  Set Vref, RX VrefLevel [Byte0]: 61

 7907 12:19:14.812584                           [Byte1]: 61

 7908 12:19:14.817025  

 7909 12:19:14.817095  Set Vref, RX VrefLevel [Byte0]: 62

 7910 12:19:14.820309                           [Byte1]: 62

 7911 12:19:14.824644  

 7912 12:19:14.824725  Set Vref, RX VrefLevel [Byte0]: 63

 7913 12:19:14.827855                           [Byte1]: 63

 7914 12:19:14.832280  

 7915 12:19:14.832361  Set Vref, RX VrefLevel [Byte0]: 64

 7916 12:19:14.835378                           [Byte1]: 64

 7917 12:19:14.839784  

 7918 12:19:14.839860  Set Vref, RX VrefLevel [Byte0]: 65

 7919 12:19:14.843042                           [Byte1]: 65

 7920 12:19:14.847392  

 7921 12:19:14.847462  Set Vref, RX VrefLevel [Byte0]: 66

 7922 12:19:14.850556                           [Byte1]: 66

 7923 12:19:14.855070  

 7924 12:19:14.855141  Set Vref, RX VrefLevel [Byte0]: 67

 7925 12:19:14.858181                           [Byte1]: 67

 7926 12:19:14.862329  

 7927 12:19:14.862402  Set Vref, RX VrefLevel [Byte0]: 68

 7928 12:19:14.865534                           [Byte1]: 68

 7929 12:19:14.869754  

 7930 12:19:14.869861  Set Vref, RX VrefLevel [Byte0]: 69

 7931 12:19:14.872997                           [Byte1]: 69

 7932 12:19:14.877279  

 7933 12:19:14.877353  Set Vref, RX VrefLevel [Byte0]: 70

 7934 12:19:14.880884                           [Byte1]: 70

 7935 12:19:14.884654  

 7936 12:19:14.884728  Set Vref, RX VrefLevel [Byte0]: 71

 7937 12:19:14.887909                           [Byte1]: 71

 7938 12:19:14.892519  

 7939 12:19:14.892599  Set Vref, RX VrefLevel [Byte0]: 72

 7940 12:19:14.895512                           [Byte1]: 72

 7941 12:19:14.900025  

 7942 12:19:14.900101  Set Vref, RX VrefLevel [Byte0]: 73

 7943 12:19:14.903319                           [Byte1]: 73

 7944 12:19:14.907688  

 7945 12:19:14.907765  Set Vref, RX VrefLevel [Byte0]: 74

 7946 12:19:14.910891                           [Byte1]: 74

 7947 12:19:14.915163  

 7948 12:19:14.915244  Final RX Vref Byte 0 = 57 to rank0

 7949 12:19:14.918545  Final RX Vref Byte 1 = 65 to rank0

 7950 12:19:14.921307  Final RX Vref Byte 0 = 57 to rank1

 7951 12:19:14.924746  Final RX Vref Byte 1 = 65 to rank1==

 7952 12:19:14.927959  Dram Type= 6, Freq= 0, CH_0, rank 0

 7953 12:19:14.934846  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7954 12:19:14.934923  ==

 7955 12:19:14.934991  DQS Delay:

 7956 12:19:14.937945  DQS0 = 0, DQS1 = 0

 7957 12:19:14.938023  DQM Delay:

 7958 12:19:14.938085  DQM0 = 133, DQM1 = 128

 7959 12:19:14.941151  DQ Delay:

 7960 12:19:14.944985  DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132

 7961 12:19:14.948174  DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138

 7962 12:19:14.951432  DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120

 7963 12:19:14.954670  DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136

 7964 12:19:14.954744  

 7965 12:19:14.954806  

 7966 12:19:14.954865  

 7967 12:19:14.957893  [DramC_TX_OE_Calibration] TA2

 7968 12:19:14.961024  Original DQ_B0 (3 6) =30, OEN = 27

 7969 12:19:14.964842  Original DQ_B1 (3 6) =30, OEN = 27

 7970 12:19:14.968037  24, 0x0, End_B0=24 End_B1=24

 7971 12:19:14.968114  25, 0x0, End_B0=25 End_B1=25

 7972 12:19:14.971074  26, 0x0, End_B0=26 End_B1=26

 7973 12:19:14.974426  27, 0x0, End_B0=27 End_B1=27

 7974 12:19:14.977988  28, 0x0, End_B0=28 End_B1=28

 7975 12:19:14.981160  29, 0x0, End_B0=29 End_B1=29

 7976 12:19:14.981235  30, 0x0, End_B0=30 End_B1=30

 7977 12:19:14.984326  31, 0x4141, End_B0=30 End_B1=30

 7978 12:19:14.988285  Byte0 end_step=30  best_step=27

 7979 12:19:14.991409  Byte1 end_step=30  best_step=27

 7980 12:19:14.994408  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7981 12:19:14.997827  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7982 12:19:14.997901  

 7983 12:19:14.997964  

 7984 12:19:15.004414  [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps

 7985 12:19:15.007433  CH0 RK0: MR19=303, MR18=2722

 7986 12:19:15.014786  CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16

 7987 12:19:15.014897  

 7988 12:19:15.017848  ----->DramcWriteLeveling(PI) begin...

 7989 12:19:15.017951  ==

 7990 12:19:15.021251  Dram Type= 6, Freq= 0, CH_0, rank 1

 7991 12:19:15.024031  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7992 12:19:15.024129  ==

 7993 12:19:15.027487  Write leveling (Byte 0): 35 => 35

 7994 12:19:15.030991  Write leveling (Byte 1): 27 => 27

 7995 12:19:15.034239  DramcWriteLeveling(PI) end<-----

 7996 12:19:15.034317  

 7997 12:19:15.034385  ==

 7998 12:19:15.037747  Dram Type= 6, Freq= 0, CH_0, rank 1

 7999 12:19:15.040753  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8000 12:19:15.040830  ==

 8001 12:19:15.044330  [Gating] SW mode calibration

 8002 12:19:15.050962  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8003 12:19:15.057312  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8004 12:19:15.060989   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8005 12:19:15.067258   1  4  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8006 12:19:15.070902   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8007 12:19:15.074091   1  4 12 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)

 8008 12:19:15.080432   1  4 16 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)

 8009 12:19:15.084070   1  4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)

 8010 12:19:15.087121   1  4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)

 8011 12:19:15.094047   1  4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)

 8012 12:19:15.097124   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8013 12:19:15.100161   1  5  4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)

 8014 12:19:15.103929   1  5  8 | B1->B0 | 3434 3535 | 1 1 | (1 0) (1 0)

 8015 12:19:15.110240   1  5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (0 1)

 8016 12:19:15.113652   1  5 16 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (1 0)

 8017 12:19:15.117443   1  5 20 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)

 8018 12:19:15.123956   1  5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8019 12:19:15.127142   1  5 28 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)

 8020 12:19:15.130349   1  6  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)

 8021 12:19:15.137168   1  6  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8022 12:19:15.140782   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8023 12:19:15.143505   1  6 12 | B1->B0 | 2525 3838 | 0 0 | (1 1) (0 0)

 8024 12:19:15.150209   1  6 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)

 8025 12:19:15.153909   1  6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 8026 12:19:15.157084   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8027 12:19:15.163402   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8028 12:19:15.166967   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8029 12:19:15.170260   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8030 12:19:15.177291   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8031 12:19:15.180634   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8032 12:19:15.183718   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8033 12:19:15.190639   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8034 12:19:15.193845   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8035 12:19:15.197029   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8036 12:19:15.203603   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8037 12:19:15.206744   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8038 12:19:15.210371   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8039 12:19:15.216854   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8040 12:19:15.220263   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8041 12:19:15.223607   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8042 12:19:15.226770   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8043 12:19:15.233559   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8044 12:19:15.236750   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8045 12:19:15.240443   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8046 12:19:15.247240   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8047 12:19:15.250367   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8048 12:19:15.253451   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8049 12:19:15.256724  Total UI for P1: 0, mck2ui 16

 8050 12:19:15.260339  best dqsien dly found for B0: ( 1,  9, 12)

 8051 12:19:15.266960   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8052 12:19:15.267084  Total UI for P1: 0, mck2ui 16

 8053 12:19:15.273857  best dqsien dly found for B1: ( 1,  9, 16)

 8054 12:19:15.276825  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8055 12:19:15.280299  best DQS1 dly(MCK, UI, PI) = (1, 9, 16)

 8056 12:19:15.280385  

 8057 12:19:15.283558  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8058 12:19:15.286725  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)

 8059 12:19:15.290233  [Gating] SW calibration Done

 8060 12:19:15.290317  ==

 8061 12:19:15.293155  Dram Type= 6, Freq= 0, CH_0, rank 1

 8062 12:19:15.297181  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8063 12:19:15.297258  ==

 8064 12:19:15.300359  RX Vref Scan: 0

 8065 12:19:15.300438  

 8066 12:19:15.300502  RX Vref 0 -> 0, step: 1

 8067 12:19:15.300564  

 8068 12:19:15.303369  RX Delay 0 -> 252, step: 8

 8069 12:19:15.307224  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8070 12:19:15.313623  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 8071 12:19:15.316689  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8072 12:19:15.319952  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8073 12:19:15.323613  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8074 12:19:15.326601  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8075 12:19:15.333549  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8076 12:19:15.336678  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8077 12:19:15.339891  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8078 12:19:15.343098  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8079 12:19:15.346309  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8080 12:19:15.353357  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 8081 12:19:15.356466  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8082 12:19:15.359614  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 8083 12:19:15.363247  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8084 12:19:15.369784  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8085 12:19:15.369896  ==

 8086 12:19:15.372718  Dram Type= 6, Freq= 0, CH_0, rank 1

 8087 12:19:15.376094  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8088 12:19:15.376178  ==

 8089 12:19:15.376244  DQS Delay:

 8090 12:19:15.379304  DQS0 = 0, DQS1 = 0

 8091 12:19:15.379386  DQM Delay:

 8092 12:19:15.382978  DQM0 = 137, DQM1 = 130

 8093 12:19:15.383061  DQ Delay:

 8094 12:19:15.386098  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135

 8095 12:19:15.389278  DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143

 8096 12:19:15.393039  DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123

 8097 12:19:15.396082  DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139

 8098 12:19:15.396165  

 8099 12:19:15.396231  

 8100 12:19:15.399453  ==

 8101 12:19:15.403097  Dram Type= 6, Freq= 0, CH_0, rank 1

 8102 12:19:15.405882  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8103 12:19:15.405966  ==

 8104 12:19:15.406032  

 8105 12:19:15.406093  

 8106 12:19:15.409367  	TX Vref Scan disable

 8107 12:19:15.409449   == TX Byte 0 ==

 8108 12:19:15.412380  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 8109 12:19:15.419345  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8110 12:19:15.419426   == TX Byte 1 ==

 8111 12:19:15.422906  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8112 12:19:15.429266  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8113 12:19:15.429347  ==

 8114 12:19:15.432865  Dram Type= 6, Freq= 0, CH_0, rank 1

 8115 12:19:15.435921  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8116 12:19:15.436019  ==

 8117 12:19:15.449996  

 8118 12:19:15.453212  TX Vref early break, caculate TX vref

 8119 12:19:15.456388  TX Vref=16, minBit 1, minWin=22, winSum=386

 8120 12:19:15.459543  TX Vref=18, minBit 0, minWin=23, winSum=395

 8121 12:19:15.463247  TX Vref=20, minBit 1, minWin=24, winSum=409

 8122 12:19:15.466445  TX Vref=22, minBit 3, minWin=24, winSum=409

 8123 12:19:15.470176  TX Vref=24, minBit 7, minWin=24, winSum=417

 8124 12:19:15.476348  TX Vref=26, minBit 3, minWin=25, winSum=426

 8125 12:19:15.479770  TX Vref=28, minBit 0, minWin=25, winSum=425

 8126 12:19:15.483240  TX Vref=30, minBit 0, minWin=25, winSum=417

 8127 12:19:15.486566  TX Vref=32, minBit 7, minWin=24, winSum=409

 8128 12:19:15.489782  TX Vref=34, minBit 4, minWin=23, winSum=398

 8129 12:19:15.496795  [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 26

 8130 12:19:15.496880  

 8131 12:19:15.499892  Final TX Range 0 Vref 26

 8132 12:19:15.499974  

 8133 12:19:15.500039  ==

 8134 12:19:15.503000  Dram Type= 6, Freq= 0, CH_0, rank 1

 8135 12:19:15.506674  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8136 12:19:15.506758  ==

 8137 12:19:15.506823  

 8138 12:19:15.506884  

 8139 12:19:15.509760  	TX Vref Scan disable

 8140 12:19:15.516873  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8141 12:19:15.516957   == TX Byte 0 ==

 8142 12:19:15.519967  u2DelayCellOfst[0]=13 cells (4 PI)

 8143 12:19:15.522885  u2DelayCellOfst[1]=13 cells (4 PI)

 8144 12:19:15.526325  u2DelayCellOfst[2]=10 cells (3 PI)

 8145 12:19:15.529640  u2DelayCellOfst[3]=10 cells (3 PI)

 8146 12:19:15.532903  u2DelayCellOfst[4]=6 cells (2 PI)

 8147 12:19:15.536088  u2DelayCellOfst[5]=0 cells (0 PI)

 8148 12:19:15.539540  u2DelayCellOfst[6]=13 cells (4 PI)

 8149 12:19:15.542866  u2DelayCellOfst[7]=13 cells (4 PI)

 8150 12:19:15.545944  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 8151 12:19:15.549333  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8152 12:19:15.552328   == TX Byte 1 ==

 8153 12:19:15.555831  u2DelayCellOfst[8]=3 cells (1 PI)

 8154 12:19:15.555914  u2DelayCellOfst[9]=0 cells (0 PI)

 8155 12:19:15.559407  u2DelayCellOfst[10]=10 cells (3 PI)

 8156 12:19:15.562520  u2DelayCellOfst[11]=3 cells (1 PI)

 8157 12:19:15.565665  u2DelayCellOfst[12]=10 cells (3 PI)

 8158 12:19:15.568865  u2DelayCellOfst[13]=13 cells (4 PI)

 8159 12:19:15.572698  u2DelayCellOfst[14]=13 cells (4 PI)

 8160 12:19:15.575829  u2DelayCellOfst[15]=10 cells (3 PI)

 8161 12:19:15.579001  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8162 12:19:15.585868  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8163 12:19:15.585950  DramC Write-DBI on

 8164 12:19:15.586016  ==

 8165 12:19:15.588970  Dram Type= 6, Freq= 0, CH_0, rank 1

 8166 12:19:15.595876  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8167 12:19:15.595960  ==

 8168 12:19:15.596025  

 8169 12:19:15.596086  

 8170 12:19:15.596144  	TX Vref Scan disable

 8171 12:19:15.599620   == TX Byte 0 ==

 8172 12:19:15.602801  Update DQM dly =736 (2 ,6, 32)  DQM OEN =(3 ,3)

 8173 12:19:15.605877   == TX Byte 1 ==

 8174 12:19:15.609691  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8175 12:19:15.612521  DramC Write-DBI off

 8176 12:19:15.612603  

 8177 12:19:15.612669  [DATLAT]

 8178 12:19:15.612740  Freq=1600, CH0 RK1

 8179 12:19:15.612801  

 8180 12:19:15.616149  DATLAT Default: 0xf

 8181 12:19:15.619386  0, 0xFFFF, sum = 0

 8182 12:19:15.619470  1, 0xFFFF, sum = 0

 8183 12:19:15.622436  2, 0xFFFF, sum = 0

 8184 12:19:15.622519  3, 0xFFFF, sum = 0

 8185 12:19:15.626163  4, 0xFFFF, sum = 0

 8186 12:19:15.626251  5, 0xFFFF, sum = 0

 8187 12:19:15.629334  6, 0xFFFF, sum = 0

 8188 12:19:15.629417  7, 0xFFFF, sum = 0

 8189 12:19:15.632446  8, 0xFFFF, sum = 0

 8190 12:19:15.632540  9, 0xFFFF, sum = 0

 8191 12:19:15.635828  10, 0xFFFF, sum = 0

 8192 12:19:15.635912  11, 0xFFFF, sum = 0

 8193 12:19:15.639231  12, 0xFFFF, sum = 0

 8194 12:19:15.639348  13, 0xFFFF, sum = 0

 8195 12:19:15.642368  14, 0x0, sum = 1

 8196 12:19:15.642452  15, 0x0, sum = 2

 8197 12:19:15.645937  16, 0x0, sum = 3

 8198 12:19:15.646021  17, 0x0, sum = 4

 8199 12:19:15.649472  best_step = 15

 8200 12:19:15.649553  

 8201 12:19:15.649618  ==

 8202 12:19:15.652875  Dram Type= 6, Freq= 0, CH_0, rank 1

 8203 12:19:15.655727  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8204 12:19:15.655810  ==

 8205 12:19:15.659012  RX Vref Scan: 0

 8206 12:19:15.659094  

 8207 12:19:15.659159  RX Vref 0 -> 0, step: 1

 8208 12:19:15.659220  

 8209 12:19:15.662420  RX Delay 19 -> 252, step: 4

 8210 12:19:15.665712  iDelay=191, Bit 0, Center 134 (83 ~ 186) 104

 8211 12:19:15.672476  iDelay=191, Bit 1, Center 138 (91 ~ 186) 96

 8212 12:19:15.675594  iDelay=191, Bit 2, Center 130 (79 ~ 182) 104

 8213 12:19:15.678865  iDelay=191, Bit 3, Center 134 (83 ~ 186) 104

 8214 12:19:15.682613  iDelay=191, Bit 4, Center 136 (87 ~ 186) 100

 8215 12:19:15.685758  iDelay=191, Bit 5, Center 124 (71 ~ 178) 108

 8216 12:19:15.692618  iDelay=191, Bit 6, Center 140 (91 ~ 190) 100

 8217 12:19:15.695723  iDelay=191, Bit 7, Center 140 (91 ~ 190) 100

 8218 12:19:15.698789  iDelay=191, Bit 8, Center 120 (71 ~ 170) 100

 8219 12:19:15.702512  iDelay=191, Bit 9, Center 116 (67 ~ 166) 100

 8220 12:19:15.705900  iDelay=191, Bit 10, Center 130 (79 ~ 182) 104

 8221 12:19:15.712740  iDelay=191, Bit 11, Center 118 (67 ~ 170) 104

 8222 12:19:15.715449  iDelay=191, Bit 12, Center 134 (83 ~ 186) 104

 8223 12:19:15.719131  iDelay=191, Bit 13, Center 132 (83 ~ 182) 100

 8224 12:19:15.722001  iDelay=191, Bit 14, Center 136 (87 ~ 186) 100

 8225 12:19:15.725729  iDelay=191, Bit 15, Center 134 (87 ~ 182) 96

 8226 12:19:15.728834  ==

 8227 12:19:15.732608  Dram Type= 6, Freq= 0, CH_0, rank 1

 8228 12:19:15.735215  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8229 12:19:15.735299  ==

 8230 12:19:15.735365  DQS Delay:

 8231 12:19:15.739006  DQS0 = 0, DQS1 = 0

 8232 12:19:15.739088  DQM Delay:

 8233 12:19:15.742055  DQM0 = 134, DQM1 = 127

 8234 12:19:15.742138  DQ Delay:

 8235 12:19:15.745744  DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134

 8236 12:19:15.748965  DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140

 8237 12:19:15.752191  DQ8 =120, DQ9 =116, DQ10 =130, DQ11 =118

 8238 12:19:15.755703  DQ12 =134, DQ13 =132, DQ14 =136, DQ15 =134

 8239 12:19:15.755787  

 8240 12:19:15.755853  

 8241 12:19:15.755914  

 8242 12:19:15.758739  [DramC_TX_OE_Calibration] TA2

 8243 12:19:15.762394  Original DQ_B0 (3 6) =30, OEN = 27

 8244 12:19:15.765403  Original DQ_B1 (3 6) =30, OEN = 27

 8245 12:19:15.769183  24, 0x0, End_B0=24 End_B1=24

 8246 12:19:15.772175  25, 0x0, End_B0=25 End_B1=25

 8247 12:19:15.772261  26, 0x0, End_B0=26 End_B1=26

 8248 12:19:15.775803  27, 0x0, End_B0=27 End_B1=27

 8249 12:19:15.778947  28, 0x0, End_B0=28 End_B1=28

 8250 12:19:15.782183  29, 0x0, End_B0=29 End_B1=29

 8251 12:19:15.782269  30, 0x0, End_B0=30 End_B1=30

 8252 12:19:15.785289  31, 0x4141, End_B0=30 End_B1=30

 8253 12:19:15.788650  Byte0 end_step=30  best_step=27

 8254 12:19:15.792380  Byte1 end_step=30  best_step=27

 8255 12:19:15.795504  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8256 12:19:15.798714  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8257 12:19:15.798830  

 8258 12:19:15.798924  

 8259 12:19:15.805678  [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps

 8260 12:19:15.808895  CH0 RK1: MR19=303, MR18=2109

 8261 12:19:15.815120  CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15

 8262 12:19:15.818715  [RxdqsGatingPostProcess] freq 1600

 8263 12:19:15.821807  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8264 12:19:15.825438  best DQS0 dly(2T, 0.5T) = (1, 1)

 8265 12:19:15.828986  best DQS1 dly(2T, 0.5T) = (1, 1)

 8266 12:19:15.831723  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8267 12:19:15.835098  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8268 12:19:15.838243  best DQS0 dly(2T, 0.5T) = (1, 1)

 8269 12:19:15.841684  best DQS1 dly(2T, 0.5T) = (1, 1)

 8270 12:19:15.845339  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8271 12:19:15.848225  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8272 12:19:15.851687  Pre-setting of DQS Precalculation

 8273 12:19:15.854895  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8274 12:19:15.855002  ==

 8275 12:19:15.858647  Dram Type= 6, Freq= 0, CH_1, rank 0

 8276 12:19:15.865321  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8277 12:19:15.865407  ==

 8278 12:19:15.868437  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8279 12:19:15.875266  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8280 12:19:15.878444  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8281 12:19:15.884768  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8282 12:19:15.892665  [CA 0] Center 42 (13~72) winsize 60

 8283 12:19:15.895674  [CA 1] Center 42 (13~72) winsize 60

 8284 12:19:15.899405  [CA 2] Center 38 (9~68) winsize 60

 8285 12:19:15.902569  [CA 3] Center 38 (9~68) winsize 60

 8286 12:19:15.905775  [CA 4] Center 39 (10~68) winsize 59

 8287 12:19:15.908985  [CA 5] Center 37 (8~67) winsize 60

 8288 12:19:15.909090  

 8289 12:19:15.912668  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8290 12:19:15.912752  

 8291 12:19:15.915735  [CATrainingPosCal] consider 1 rank data

 8292 12:19:15.918875  u2DelayCellTimex100 = 290/100 ps

 8293 12:19:15.925706  CA0 delay=42 (13~72),Diff = 5 PI (16 cell)

 8294 12:19:15.928836  CA1 delay=42 (13~72),Diff = 5 PI (16 cell)

 8295 12:19:15.932626  CA2 delay=38 (9~68),Diff = 1 PI (3 cell)

 8296 12:19:15.935789  CA3 delay=38 (9~68),Diff = 1 PI (3 cell)

 8297 12:19:15.939006  CA4 delay=39 (10~68),Diff = 2 PI (6 cell)

 8298 12:19:15.942560  CA5 delay=37 (8~67),Diff = 0 PI (0 cell)

 8299 12:19:15.942645  

 8300 12:19:15.945470  CA PerBit enable=1, Macro0, CA PI delay=37

 8301 12:19:15.945554  

 8302 12:19:15.948824  [CBTSetCACLKResult] CA Dly = 37

 8303 12:19:15.952314  CS Dly: 10 (0~41)

 8304 12:19:15.955373  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8305 12:19:15.958614  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8306 12:19:15.958698  ==

 8307 12:19:15.962233  Dram Type= 6, Freq= 0, CH_1, rank 1

 8308 12:19:15.965246  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8309 12:19:15.968842  ==

 8310 12:19:15.971980  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8311 12:19:15.975542  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8312 12:19:15.982217  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8313 12:19:15.988526  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8314 12:19:15.996127  [CA 0] Center 42 (12~72) winsize 61

 8315 12:19:15.999327  [CA 1] Center 42 (12~72) winsize 61

 8316 12:19:16.002479  [CA 2] Center 38 (9~68) winsize 60

 8317 12:19:16.006089  [CA 3] Center 37 (8~67) winsize 60

 8318 12:19:16.009343  [CA 4] Center 38 (8~68) winsize 61

 8319 12:19:16.012843  [CA 5] Center 37 (8~67) winsize 60

 8320 12:19:16.012927  

 8321 12:19:16.015752  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8322 12:19:16.015853  

 8323 12:19:16.019146  [CATrainingPosCal] consider 2 rank data

 8324 12:19:16.022637  u2DelayCellTimex100 = 290/100 ps

 8325 12:19:16.025563  CA0 delay=42 (13~72),Diff = 5 PI (16 cell)

 8326 12:19:16.032598  CA1 delay=42 (13~72),Diff = 5 PI (16 cell)

 8327 12:19:16.035729  CA2 delay=38 (9~68),Diff = 1 PI (3 cell)

 8328 12:19:16.038858  CA3 delay=38 (9~67),Diff = 1 PI (3 cell)

 8329 12:19:16.042594  CA4 delay=39 (10~68),Diff = 2 PI (6 cell)

 8330 12:19:16.045690  CA5 delay=37 (8~67),Diff = 0 PI (0 cell)

 8331 12:19:16.045773  

 8332 12:19:16.049427  CA PerBit enable=1, Macro0, CA PI delay=37

 8333 12:19:16.049508  

 8334 12:19:16.052458  [CBTSetCACLKResult] CA Dly = 37

 8335 12:19:16.055921  CS Dly: 11 (0~44)

 8336 12:19:16.058898  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8337 12:19:16.062710  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8338 12:19:16.062791  

 8339 12:19:16.065757  ----->DramcWriteLeveling(PI) begin...

 8340 12:19:16.065883  ==

 8341 12:19:16.069484  Dram Type= 6, Freq= 0, CH_1, rank 0

 8342 12:19:16.072262  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8343 12:19:16.075516  ==

 8344 12:19:16.075597  Write leveling (Byte 0): 25 => 25

 8345 12:19:16.079174  Write leveling (Byte 1): 28 => 28

 8346 12:19:16.082453  DramcWriteLeveling(PI) end<-----

 8347 12:19:16.082534  

 8348 12:19:16.082598  ==

 8349 12:19:16.085517  Dram Type= 6, Freq= 0, CH_1, rank 0

 8350 12:19:16.092328  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8351 12:19:16.092427  ==

 8352 12:19:16.095978  [Gating] SW mode calibration

 8353 12:19:16.102000  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8354 12:19:16.105625  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8355 12:19:16.112366   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8356 12:19:16.115548   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8357 12:19:16.118861   1  4  8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)

 8358 12:19:16.125591   1  4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 8359 12:19:16.128503   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8360 12:19:16.131642   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8361 12:19:16.138381   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8362 12:19:16.141727   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8363 12:19:16.145484   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8364 12:19:16.151587   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8365 12:19:16.154923   1  5  8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)

 8366 12:19:16.158596   1  5 12 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)

 8367 12:19:16.165064   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8368 12:19:16.168160   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8369 12:19:16.171939   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8370 12:19:16.178270   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8371 12:19:16.181395   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8372 12:19:16.185117   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8373 12:19:16.188100   1  6  8 | B1->B0 | 2525 4040 | 0 0 | (0 0) (0 0)

 8374 12:19:16.194967   1  6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8375 12:19:16.198527   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8376 12:19:16.201536   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8377 12:19:16.208107   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8378 12:19:16.211347   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8379 12:19:16.214639   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8380 12:19:16.221300   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8381 12:19:16.225170   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8382 12:19:16.228256   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8383 12:19:16.235215   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8384 12:19:16.238266   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8385 12:19:16.241949   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8386 12:19:16.248262   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8387 12:19:16.251494   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8388 12:19:16.255339   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8389 12:19:16.261644   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8390 12:19:16.264784   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8391 12:19:16.267853   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8392 12:19:16.274844   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8393 12:19:16.278058   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8394 12:19:16.281340   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8395 12:19:16.288114   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8396 12:19:16.291922   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8397 12:19:16.295061   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8398 12:19:16.298227   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8399 12:19:16.305081   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8400 12:19:16.308164  Total UI for P1: 0, mck2ui 16

 8401 12:19:16.311220  best dqsien dly found for B0: ( 1,  9, 10)

 8402 12:19:16.315186  Total UI for P1: 0, mck2ui 16

 8403 12:19:16.318243  best dqsien dly found for B1: ( 1,  9, 10)

 8404 12:19:16.321498  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8405 12:19:16.324564  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8406 12:19:16.324645  

 8407 12:19:16.328057  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8408 12:19:16.331311  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8409 12:19:16.334603  [Gating] SW calibration Done

 8410 12:19:16.334683  ==

 8411 12:19:16.337934  Dram Type= 6, Freq= 0, CH_1, rank 0

 8412 12:19:16.341330  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8413 12:19:16.341412  ==

 8414 12:19:16.344619  RX Vref Scan: 0

 8415 12:19:16.344699  

 8416 12:19:16.344763  RX Vref 0 -> 0, step: 1

 8417 12:19:16.348011  

 8418 12:19:16.348092  RX Delay 0 -> 252, step: 8

 8419 12:19:16.354809  iDelay=200, Bit 0, Center 139 (88 ~ 191) 104

 8420 12:19:16.357859  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8421 12:19:16.361319  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8422 12:19:16.364822  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8423 12:19:16.367962  iDelay=200, Bit 4, Center 131 (80 ~ 183) 104

 8424 12:19:16.371096  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8425 12:19:16.377908  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8426 12:19:16.381233  iDelay=200, Bit 7, Center 135 (80 ~ 191) 112

 8427 12:19:16.384241  iDelay=200, Bit 8, Center 123 (72 ~ 175) 104

 8428 12:19:16.388096  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 8429 12:19:16.391232  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8430 12:19:16.397841  iDelay=200, Bit 11, Center 127 (80 ~ 175) 96

 8431 12:19:16.400951  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8432 12:19:16.404546  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 8433 12:19:16.407747  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8434 12:19:16.414686  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8435 12:19:16.414767  ==

 8436 12:19:16.417684  Dram Type= 6, Freq= 0, CH_1, rank 0

 8437 12:19:16.420733  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8438 12:19:16.420844  ==

 8439 12:19:16.420909  DQS Delay:

 8440 12:19:16.424545  DQS0 = 0, DQS1 = 0

 8441 12:19:16.424640  DQM Delay:

 8442 12:19:16.427729  DQM0 = 136, DQM1 = 132

 8443 12:19:16.427838  DQ Delay:

 8444 12:19:16.430825  DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135

 8445 12:19:16.434012  DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135

 8446 12:19:16.437239  DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =127

 8447 12:19:16.440773  DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139

 8448 12:19:16.440869  

 8449 12:19:16.440932  

 8450 12:19:16.444532  ==

 8451 12:19:16.447658  Dram Type= 6, Freq= 0, CH_1, rank 0

 8452 12:19:16.450748  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8453 12:19:16.450829  ==

 8454 12:19:16.450908  

 8455 12:19:16.450983  

 8456 12:19:16.454120  	TX Vref Scan disable

 8457 12:19:16.454227   == TX Byte 0 ==

 8458 12:19:16.457182  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8459 12:19:16.463903  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8460 12:19:16.464010   == TX Byte 1 ==

 8461 12:19:16.467046  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8462 12:19:16.474229  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8463 12:19:16.474339  ==

 8464 12:19:16.477093  Dram Type= 6, Freq= 0, CH_1, rank 0

 8465 12:19:16.480392  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8466 12:19:16.480475  ==

 8467 12:19:16.494823  

 8468 12:19:16.498031  TX Vref early break, caculate TX vref

 8469 12:19:16.501175  TX Vref=16, minBit 1, minWin=22, winSum=376

 8470 12:19:16.504720  TX Vref=18, minBit 9, minWin=22, winSum=383

 8471 12:19:16.508223  TX Vref=20, minBit 1, minWin=23, winSum=395

 8472 12:19:16.511411  TX Vref=22, minBit 0, minWin=24, winSum=407

 8473 12:19:16.514690  TX Vref=24, minBit 1, minWin=25, winSum=415

 8474 12:19:16.521007  TX Vref=26, minBit 0, minWin=25, winSum=423

 8475 12:19:16.524699  TX Vref=28, minBit 0, minWin=25, winSum=424

 8476 12:19:16.527904  TX Vref=30, minBit 0, minWin=25, winSum=421

 8477 12:19:16.531064  TX Vref=32, minBit 6, minWin=24, winSum=414

 8478 12:19:16.534162  TX Vref=34, minBit 0, minWin=24, winSum=403

 8479 12:19:16.541149  TX Vref=36, minBit 2, minWin=23, winSum=389

 8480 12:19:16.544254  [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28

 8481 12:19:16.544338  

 8482 12:19:16.547846  Final TX Range 0 Vref 28

 8483 12:19:16.547929  

 8484 12:19:16.547993  ==

 8485 12:19:16.550913  Dram Type= 6, Freq= 0, CH_1, rank 0

 8486 12:19:16.554036  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8487 12:19:16.554120  ==

 8488 12:19:16.554185  

 8489 12:19:16.557821  

 8490 12:19:16.557903  	TX Vref Scan disable

 8491 12:19:16.564211  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8492 12:19:16.564293   == TX Byte 0 ==

 8493 12:19:16.567282  u2DelayCellOfst[0]=16 cells (5 PI)

 8494 12:19:16.570775  u2DelayCellOfst[1]=10 cells (3 PI)

 8495 12:19:16.574378  u2DelayCellOfst[2]=0 cells (0 PI)

 8496 12:19:16.577400  u2DelayCellOfst[3]=6 cells (2 PI)

 8497 12:19:16.580780  u2DelayCellOfst[4]=10 cells (3 PI)

 8498 12:19:16.584433  u2DelayCellOfst[5]=16 cells (5 PI)

 8499 12:19:16.587174  u2DelayCellOfst[6]=16 cells (5 PI)

 8500 12:19:16.591038  u2DelayCellOfst[7]=6 cells (2 PI)

 8501 12:19:16.594528  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8502 12:19:16.597527  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8503 12:19:16.600543   == TX Byte 1 ==

 8504 12:19:16.604225  u2DelayCellOfst[8]=0 cells (0 PI)

 8505 12:19:16.607537  u2DelayCellOfst[9]=3 cells (1 PI)

 8506 12:19:16.610400  u2DelayCellOfst[10]=10 cells (3 PI)

 8507 12:19:16.610483  u2DelayCellOfst[11]=0 cells (0 PI)

 8508 12:19:16.613923  u2DelayCellOfst[12]=13 cells (4 PI)

 8509 12:19:16.617321  u2DelayCellOfst[13]=13 cells (4 PI)

 8510 12:19:16.620338  u2DelayCellOfst[14]=13 cells (4 PI)

 8511 12:19:16.624211  u2DelayCellOfst[15]=13 cells (4 PI)

 8512 12:19:16.631203  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8513 12:19:16.633684  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8514 12:19:16.633794  DramC Write-DBI on

 8515 12:19:16.633888  ==

 8516 12:19:16.636865  Dram Type= 6, Freq= 0, CH_1, rank 0

 8517 12:19:16.643856  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8518 12:19:16.643939  ==

 8519 12:19:16.644004  

 8520 12:19:16.644064  

 8521 12:19:16.647065  	TX Vref Scan disable

 8522 12:19:16.647147   == TX Byte 0 ==

 8523 12:19:16.653800  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8524 12:19:16.653883   == TX Byte 1 ==

 8525 12:19:16.656845  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8526 12:19:16.660557  DramC Write-DBI off

 8527 12:19:16.660639  

 8528 12:19:16.660704  [DATLAT]

 8529 12:19:16.663773  Freq=1600, CH1 RK0

 8530 12:19:16.663855  

 8531 12:19:16.663932  DATLAT Default: 0xf

 8532 12:19:16.666947  0, 0xFFFF, sum = 0

 8533 12:19:16.667031  1, 0xFFFF, sum = 0

 8534 12:19:16.670114  2, 0xFFFF, sum = 0

 8535 12:19:16.670197  3, 0xFFFF, sum = 0

 8536 12:19:16.673829  4, 0xFFFF, sum = 0

 8537 12:19:16.673944  5, 0xFFFF, sum = 0

 8538 12:19:16.676920  6, 0xFFFF, sum = 0

 8539 12:19:16.677036  7, 0xFFFF, sum = 0

 8540 12:19:16.679834  8, 0xFFFF, sum = 0

 8541 12:19:16.679955  9, 0xFFFF, sum = 0

 8542 12:19:16.683527  10, 0xFFFF, sum = 0

 8543 12:19:16.686562  11, 0xFFFF, sum = 0

 8544 12:19:16.686674  12, 0xFFFF, sum = 0

 8545 12:19:16.690483  13, 0xFFFF, sum = 0

 8546 12:19:16.690567  14, 0x0, sum = 1

 8547 12:19:16.693674  15, 0x0, sum = 2

 8548 12:19:16.693757  16, 0x0, sum = 3

 8549 12:19:16.693823  17, 0x0, sum = 4

 8550 12:19:16.696702  best_step = 15

 8551 12:19:16.696783  

 8552 12:19:16.696848  ==

 8553 12:19:16.700334  Dram Type= 6, Freq= 0, CH_1, rank 0

 8554 12:19:16.703446  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8555 12:19:16.703555  ==

 8556 12:19:16.707249  RX Vref Scan: 1

 8557 12:19:16.707332  

 8558 12:19:16.710431  Set Vref Range= 24 -> 127

 8559 12:19:16.710514  

 8560 12:19:16.710578  RX Vref 24 -> 127, step: 1

 8561 12:19:16.710640  

 8562 12:19:16.713511  RX Delay 27 -> 252, step: 4

 8563 12:19:16.713593  

 8564 12:19:16.716457  Set Vref, RX VrefLevel [Byte0]: 24

 8565 12:19:16.719940                           [Byte1]: 24

 8566 12:19:16.720023  

 8567 12:19:16.723126  Set Vref, RX VrefLevel [Byte0]: 25

 8568 12:19:16.726341                           [Byte1]: 25

 8569 12:19:16.730609  

 8570 12:19:16.730722  Set Vref, RX VrefLevel [Byte0]: 26

 8571 12:19:16.733594                           [Byte1]: 26

 8572 12:19:16.738059  

 8573 12:19:16.738142  Set Vref, RX VrefLevel [Byte0]: 27

 8574 12:19:16.741371                           [Byte1]: 27

 8575 12:19:16.745710  

 8576 12:19:16.745797  Set Vref, RX VrefLevel [Byte0]: 28

 8577 12:19:16.748788                           [Byte1]: 28

 8578 12:19:16.753230  

 8579 12:19:16.753306  Set Vref, RX VrefLevel [Byte0]: 29

 8580 12:19:16.756385                           [Byte1]: 29

 8581 12:19:16.760621  

 8582 12:19:16.760695  Set Vref, RX VrefLevel [Byte0]: 30

 8583 12:19:16.764211                           [Byte1]: 30

 8584 12:19:16.768642  

 8585 12:19:16.768725  Set Vref, RX VrefLevel [Byte0]: 31

 8586 12:19:16.771720                           [Byte1]: 31

 8587 12:19:16.775543  

 8588 12:19:16.775650  Set Vref, RX VrefLevel [Byte0]: 32

 8589 12:19:16.778816                           [Byte1]: 32

 8590 12:19:16.783325  

 8591 12:19:16.783407  Set Vref, RX VrefLevel [Byte0]: 33

 8592 12:19:16.786848                           [Byte1]: 33

 8593 12:19:16.790726  

 8594 12:19:16.790813  Set Vref, RX VrefLevel [Byte0]: 34

 8595 12:19:16.794393                           [Byte1]: 34

 8596 12:19:16.798244  

 8597 12:19:16.798327  Set Vref, RX VrefLevel [Byte0]: 35

 8598 12:19:16.801436                           [Byte1]: 35

 8599 12:19:16.805758  

 8600 12:19:16.805840  Set Vref, RX VrefLevel [Byte0]: 36

 8601 12:19:16.809169                           [Byte1]: 36

 8602 12:19:16.813450  

 8603 12:19:16.813533  Set Vref, RX VrefLevel [Byte0]: 37

 8604 12:19:16.816742                           [Byte1]: 37

 8605 12:19:16.821201  

 8606 12:19:16.821285  Set Vref, RX VrefLevel [Byte0]: 38

 8607 12:19:16.824417                           [Byte1]: 38

 8608 12:19:16.828207  

 8609 12:19:16.828289  Set Vref, RX VrefLevel [Byte0]: 39

 8610 12:19:16.832011                           [Byte1]: 39

 8611 12:19:16.836250  

 8612 12:19:16.836332  Set Vref, RX VrefLevel [Byte0]: 40

 8613 12:19:16.839364                           [Byte1]: 40

 8614 12:19:16.843575  

 8615 12:19:16.843670  Set Vref, RX VrefLevel [Byte0]: 41

 8616 12:19:16.847012                           [Byte1]: 41

 8617 12:19:16.850965  

 8618 12:19:16.851047  Set Vref, RX VrefLevel [Byte0]: 42

 8619 12:19:16.854276                           [Byte1]: 42

 8620 12:19:16.858672  

 8621 12:19:16.858754  Set Vref, RX VrefLevel [Byte0]: 43

 8622 12:19:16.861720                           [Byte1]: 43

 8623 12:19:16.866104  

 8624 12:19:16.866186  Set Vref, RX VrefLevel [Byte0]: 44

 8625 12:19:16.869376                           [Byte1]: 44

 8626 12:19:16.873948  

 8627 12:19:16.874031  Set Vref, RX VrefLevel [Byte0]: 45

 8628 12:19:16.876941                           [Byte1]: 45

 8629 12:19:16.881061  

 8630 12:19:16.881171  Set Vref, RX VrefLevel [Byte0]: 46

 8631 12:19:16.884255                           [Byte1]: 46

 8632 12:19:16.888603  

 8633 12:19:16.888685  Set Vref, RX VrefLevel [Byte0]: 47

 8634 12:19:16.892350                           [Byte1]: 47

 8635 12:19:16.896531  

 8636 12:19:16.896613  Set Vref, RX VrefLevel [Byte0]: 48

 8637 12:19:16.899749                           [Byte1]: 48

 8638 12:19:16.903756  

 8639 12:19:16.903868  Set Vref, RX VrefLevel [Byte0]: 49

 8640 12:19:16.907053                           [Byte1]: 49

 8641 12:19:16.911392  

 8642 12:19:16.911501  Set Vref, RX VrefLevel [Byte0]: 50

 8643 12:19:16.914293                           [Byte1]: 50

 8644 12:19:16.919109  

 8645 12:19:16.919191  Set Vref, RX VrefLevel [Byte0]: 51

 8646 12:19:16.922203                           [Byte1]: 51

 8647 12:19:16.926732  

 8648 12:19:16.926844  Set Vref, RX VrefLevel [Byte0]: 52

 8649 12:19:16.929941                           [Byte1]: 52

 8650 12:19:16.934220  

 8651 12:19:16.934328  Set Vref, RX VrefLevel [Byte0]: 53

 8652 12:19:16.937426                           [Byte1]: 53

 8653 12:19:16.941586  

 8654 12:19:16.941668  Set Vref, RX VrefLevel [Byte0]: 54

 8655 12:19:16.944757                           [Byte1]: 54

 8656 12:19:16.949073  

 8657 12:19:16.949159  Set Vref, RX VrefLevel [Byte0]: 55

 8658 12:19:16.952326                           [Byte1]: 55

 8659 12:19:16.956530  

 8660 12:19:16.956612  Set Vref, RX VrefLevel [Byte0]: 56

 8661 12:19:16.959711                           [Byte1]: 56

 8662 12:19:16.964087  

 8663 12:19:16.964168  Set Vref, RX VrefLevel [Byte0]: 57

 8664 12:19:16.967277                           [Byte1]: 57

 8665 12:19:16.971624  

 8666 12:19:16.971715  Set Vref, RX VrefLevel [Byte0]: 58

 8667 12:19:16.975199                           [Byte1]: 58

 8668 12:19:16.979075  

 8669 12:19:16.979157  Set Vref, RX VrefLevel [Byte0]: 59

 8670 12:19:16.982325                           [Byte1]: 59

 8671 12:19:16.986490  

 8672 12:19:16.986573  Set Vref, RX VrefLevel [Byte0]: 60

 8673 12:19:16.989918                           [Byte1]: 60

 8674 12:19:16.994081  

 8675 12:19:16.994163  Set Vref, RX VrefLevel [Byte0]: 61

 8676 12:19:16.997443                           [Byte1]: 61

 8677 12:19:17.001634  

 8678 12:19:17.001750  Set Vref, RX VrefLevel [Byte0]: 62

 8679 12:19:17.004829                           [Byte1]: 62

 8680 12:19:17.009141  

 8681 12:19:17.009220  Set Vref, RX VrefLevel [Byte0]: 63

 8682 12:19:17.012543                           [Byte1]: 63

 8683 12:19:17.016763  

 8684 12:19:17.016839  Set Vref, RX VrefLevel [Byte0]: 64

 8685 12:19:17.020318                           [Byte1]: 64

 8686 12:19:17.024156  

 8687 12:19:17.024295  Set Vref, RX VrefLevel [Byte0]: 65

 8688 12:19:17.027763                           [Byte1]: 65

 8689 12:19:17.031532  

 8690 12:19:17.031664  Set Vref, RX VrefLevel [Byte0]: 66

 8691 12:19:17.035423                           [Byte1]: 66

 8692 12:19:17.039222  

 8693 12:19:17.039319  Set Vref, RX VrefLevel [Byte0]: 67

 8694 12:19:17.042913                           [Byte1]: 67

 8695 12:19:17.046618  

 8696 12:19:17.046742  Set Vref, RX VrefLevel [Byte0]: 68

 8697 12:19:17.050438                           [Byte1]: 68

 8698 12:19:17.054343  

 8699 12:19:17.054440  Set Vref, RX VrefLevel [Byte0]: 69

 8700 12:19:17.057519                           [Byte1]: 69

 8701 12:19:17.061784  

 8702 12:19:17.061881  Set Vref, RX VrefLevel [Byte0]: 70

 8703 12:19:17.065573                           [Byte1]: 70

 8704 12:19:17.069328  

 8705 12:19:17.069425  Set Vref, RX VrefLevel [Byte0]: 71

 8706 12:19:17.072538                           [Byte1]: 71

 8707 12:19:17.077001  

 8708 12:19:17.077097  Set Vref, RX VrefLevel [Byte0]: 72

 8709 12:19:17.080203                           [Byte1]: 72

 8710 12:19:17.084486  

 8711 12:19:17.084602  Set Vref, RX VrefLevel [Byte0]: 73

 8712 12:19:17.087611                           [Byte1]: 73

 8713 12:19:17.092029  

 8714 12:19:17.092140  Set Vref, RX VrefLevel [Byte0]: 74

 8715 12:19:17.095509                           [Byte1]: 74

 8716 12:19:17.099868  

 8717 12:19:17.099963  Set Vref, RX VrefLevel [Byte0]: 75

 8718 12:19:17.102699                           [Byte1]: 75

 8719 12:19:17.107409  

 8720 12:19:17.107532  Set Vref, RX VrefLevel [Byte0]: 76

 8721 12:19:17.110435                           [Byte1]: 76

 8722 12:19:17.114952  

 8723 12:19:17.115049  Set Vref, RX VrefLevel [Byte0]: 77

 8724 12:19:17.118033                           [Byte1]: 77

 8725 12:19:17.122168  

 8726 12:19:17.122249  Set Vref, RX VrefLevel [Byte0]: 78

 8727 12:19:17.125385                           [Byte1]: 78

 8728 12:19:17.129521  

 8729 12:19:17.129617  Final RX Vref Byte 0 = 58 to rank0

 8730 12:19:17.133188  Final RX Vref Byte 1 = 57 to rank0

 8731 12:19:17.136175  Final RX Vref Byte 0 = 58 to rank1

 8732 12:19:17.139632  Final RX Vref Byte 1 = 57 to rank1==

 8733 12:19:17.143169  Dram Type= 6, Freq= 0, CH_1, rank 0

 8734 12:19:17.149590  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8735 12:19:17.149688  ==

 8736 12:19:17.149784  DQS Delay:

 8737 12:19:17.149858  DQS0 = 0, DQS1 = 0

 8738 12:19:17.152752  DQM Delay:

 8739 12:19:17.152867  DQM0 = 134, DQM1 = 131

 8740 12:19:17.156481  DQ Delay:

 8741 12:19:17.159585  DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130

 8742 12:19:17.162632  DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =134

 8743 12:19:17.166402  DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124

 8744 12:19:17.169696  DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140

 8745 12:19:17.169793  

 8746 12:19:17.169871  

 8747 12:19:17.169960  

 8748 12:19:17.172780  [DramC_TX_OE_Calibration] TA2

 8749 12:19:17.176001  Original DQ_B0 (3 6) =30, OEN = 27

 8750 12:19:17.179130  Original DQ_B1 (3 6) =30, OEN = 27

 8751 12:19:17.183158  24, 0x0, End_B0=24 End_B1=24

 8752 12:19:17.183234  25, 0x0, End_B0=25 End_B1=25

 8753 12:19:17.186351  26, 0x0, End_B0=26 End_B1=26

 8754 12:19:17.189509  27, 0x0, End_B0=27 End_B1=27

 8755 12:19:17.192563  28, 0x0, End_B0=28 End_B1=28

 8756 12:19:17.196439  29, 0x0, End_B0=29 End_B1=29

 8757 12:19:17.196538  30, 0x0, End_B0=30 End_B1=30

 8758 12:19:17.199614  31, 0x5151, End_B0=30 End_B1=30

 8759 12:19:17.202687  Byte0 end_step=30  best_step=27

 8760 12:19:17.206391  Byte1 end_step=30  best_step=27

 8761 12:19:17.209419  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8762 12:19:17.212560  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8763 12:19:17.212669  

 8764 12:19:17.212763  

 8765 12:19:17.219368  [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps

 8766 12:19:17.223116  CH1 RK0: MR19=303, MR18=1523

 8767 12:19:17.229388  CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16

 8768 12:19:17.229498  

 8769 12:19:17.233013  ----->DramcWriteLeveling(PI) begin...

 8770 12:19:17.233117  ==

 8771 12:19:17.236077  Dram Type= 6, Freq= 0, CH_1, rank 1

 8772 12:19:17.239352  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8773 12:19:17.239454  ==

 8774 12:19:17.242974  Write leveling (Byte 0): 25 => 25

 8775 12:19:17.245852  Write leveling (Byte 1): 28 => 28

 8776 12:19:17.249353  DramcWriteLeveling(PI) end<-----

 8777 12:19:17.249450  

 8778 12:19:17.249551  ==

 8779 12:19:17.252499  Dram Type= 6, Freq= 0, CH_1, rank 1

 8780 12:19:17.255713  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8781 12:19:17.255820  ==

 8782 12:19:17.259227  [Gating] SW mode calibration

 8783 12:19:17.266041  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8784 12:19:17.272565  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8785 12:19:17.276097   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8786 12:19:17.279189   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8787 12:19:17.285643   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8788 12:19:17.289353   1  4 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)

 8789 12:19:17.292556   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8790 12:19:17.299345   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8791 12:19:17.302415   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8792 12:19:17.305560   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8793 12:19:17.312410   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8794 12:19:17.315437   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 8795 12:19:17.318551   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (0 1) (1 0)

 8796 12:19:17.325226   1  5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)

 8797 12:19:17.328434   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8798 12:19:17.332284   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8799 12:19:17.338434   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8800 12:19:17.342138   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8801 12:19:17.345349   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8802 12:19:17.352340   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8803 12:19:17.355259   1  6  8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)

 8804 12:19:17.359004   1  6 12 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)

 8805 12:19:17.364993   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8806 12:19:17.368707   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8807 12:19:17.371915   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8808 12:19:17.378457   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8809 12:19:17.381888   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8810 12:19:17.385238   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8811 12:19:17.391720   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8812 12:19:17.395070   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8813 12:19:17.398881   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8814 12:19:17.405177   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8815 12:19:17.408421   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8816 12:19:17.412016   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8817 12:19:17.414925   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8818 12:19:17.422115   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8819 12:19:17.425508   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8820 12:19:17.428885   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8821 12:19:17.435146   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8822 12:19:17.438370   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8823 12:19:17.442001   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8824 12:19:17.448848   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8825 12:19:17.451992   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8826 12:19:17.455063   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8827 12:19:17.462114   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8828 12:19:17.465206   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8829 12:19:17.468222  Total UI for P1: 0, mck2ui 16

 8830 12:19:17.471765  best dqsien dly found for B1: ( 1,  9,  6)

 8831 12:19:17.475343   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8832 12:19:17.478552  Total UI for P1: 0, mck2ui 16

 8833 12:19:17.481703  best dqsien dly found for B0: ( 1,  9, 12)

 8834 12:19:17.484855  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8835 12:19:17.488652  best DQS1 dly(MCK, UI, PI) = (1, 9, 6)

 8836 12:19:17.488730  

 8837 12:19:17.494772  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8838 12:19:17.498161  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8839 12:19:17.498238  [Gating] SW calibration Done

 8840 12:19:17.501977  ==

 8841 12:19:17.505163  Dram Type= 6, Freq= 0, CH_1, rank 1

 8842 12:19:17.508366  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8843 12:19:17.508444  ==

 8844 12:19:17.508508  RX Vref Scan: 0

 8845 12:19:17.508568  

 8846 12:19:17.511511  RX Vref 0 -> 0, step: 1

 8847 12:19:17.511610  

 8848 12:19:17.514719  RX Delay 0 -> 252, step: 8

 8849 12:19:17.518465  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8850 12:19:17.521470  iDelay=208, Bit 1, Center 135 (80 ~ 191) 112

 8851 12:19:17.525056  iDelay=208, Bit 2, Center 123 (72 ~ 175) 104

 8852 12:19:17.531467  iDelay=208, Bit 3, Center 131 (80 ~ 183) 104

 8853 12:19:17.534991  iDelay=208, Bit 4, Center 131 (80 ~ 183) 104

 8854 12:19:17.537904  iDelay=208, Bit 5, Center 151 (96 ~ 207) 112

 8855 12:19:17.541612  iDelay=208, Bit 6, Center 147 (96 ~ 199) 104

 8856 12:19:17.544717  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8857 12:19:17.551484  iDelay=208, Bit 8, Center 119 (64 ~ 175) 112

 8858 12:19:17.554559  iDelay=208, Bit 9, Center 119 (64 ~ 175) 112

 8859 12:19:17.557711  iDelay=208, Bit 10, Center 135 (80 ~ 191) 112

 8860 12:19:17.561594  iDelay=208, Bit 11, Center 127 (72 ~ 183) 112

 8861 12:19:17.564747  iDelay=208, Bit 12, Center 143 (88 ~ 199) 112

 8862 12:19:17.571485  iDelay=208, Bit 13, Center 143 (88 ~ 199) 112

 8863 12:19:17.574585  iDelay=208, Bit 14, Center 139 (88 ~ 191) 104

 8864 12:19:17.577633  iDelay=208, Bit 15, Center 143 (88 ~ 199) 112

 8865 12:19:17.577711  ==

 8866 12:19:17.581033  Dram Type= 6, Freq= 0, CH_1, rank 1

 8867 12:19:17.584251  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8868 12:19:17.588058  ==

 8869 12:19:17.588131  DQS Delay:

 8870 12:19:17.588193  DQS0 = 0, DQS1 = 0

 8871 12:19:17.591178  DQM Delay:

 8872 12:19:17.591252  DQM0 = 136, DQM1 = 133

 8873 12:19:17.594290  DQ Delay:

 8874 12:19:17.598019  DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131

 8875 12:19:17.601217  DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135

 8876 12:19:17.604312  DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127

 8877 12:19:17.608056  DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143

 8878 12:19:17.608166  

 8879 12:19:17.608234  

 8880 12:19:17.608295  ==

 8881 12:19:17.611053  Dram Type= 6, Freq= 0, CH_1, rank 1

 8882 12:19:17.614608  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8883 12:19:17.614696  ==

 8884 12:19:17.614762  

 8885 12:19:17.618132  

 8886 12:19:17.618214  	TX Vref Scan disable

 8887 12:19:17.621223   == TX Byte 0 ==

 8888 12:19:17.624239  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8889 12:19:17.627888  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8890 12:19:17.630886   == TX Byte 1 ==

 8891 12:19:17.634503  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8892 12:19:17.637890  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8893 12:19:17.637972  ==

 8894 12:19:17.641455  Dram Type= 6, Freq= 0, CH_1, rank 1

 8895 12:19:17.647945  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8896 12:19:17.648032  ==

 8897 12:19:17.660472  

 8898 12:19:17.663524  TX Vref early break, caculate TX vref

 8899 12:19:17.666649  TX Vref=16, minBit 0, minWin=23, winSum=382

 8900 12:19:17.669856  TX Vref=18, minBit 2, minWin=23, winSum=395

 8901 12:19:17.673457  TX Vref=20, minBit 0, minWin=24, winSum=401

 8902 12:19:17.676697  TX Vref=22, minBit 5, minWin=24, winSum=412

 8903 12:19:17.680440  TX Vref=24, minBit 0, minWin=24, winSum=416

 8904 12:19:17.686498  TX Vref=26, minBit 0, minWin=25, winSum=425

 8905 12:19:17.689966  TX Vref=28, minBit 0, minWin=25, winSum=425

 8906 12:19:17.693159  TX Vref=30, minBit 1, minWin=25, winSum=421

 8907 12:19:17.696911  TX Vref=32, minBit 1, minWin=25, winSum=413

 8908 12:19:17.700087  TX Vref=34, minBit 1, minWin=24, winSum=405

 8909 12:19:17.703246  TX Vref=36, minBit 0, minWin=23, winSum=396

 8910 12:19:17.710288  [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26

 8911 12:19:17.710368  

 8912 12:19:17.713405  Final TX Range 0 Vref 26

 8913 12:19:17.713483  

 8914 12:19:17.713547  ==

 8915 12:19:17.716453  Dram Type= 6, Freq= 0, CH_1, rank 1

 8916 12:19:17.720048  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8917 12:19:17.720125  ==

 8918 12:19:17.720196  

 8919 12:19:17.720259  

 8920 12:19:17.723411  	TX Vref Scan disable

 8921 12:19:17.730308  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8922 12:19:17.730397   == TX Byte 0 ==

 8923 12:19:17.733361  u2DelayCellOfst[0]=16 cells (5 PI)

 8924 12:19:17.736540  u2DelayCellOfst[1]=10 cells (3 PI)

 8925 12:19:17.740330  u2DelayCellOfst[2]=0 cells (0 PI)

 8926 12:19:17.743505  u2DelayCellOfst[3]=6 cells (2 PI)

 8927 12:19:17.746620  u2DelayCellOfst[4]=10 cells (3 PI)

 8928 12:19:17.749917  u2DelayCellOfst[5]=16 cells (5 PI)

 8929 12:19:17.753489  u2DelayCellOfst[6]=16 cells (5 PI)

 8930 12:19:17.756455  u2DelayCellOfst[7]=6 cells (2 PI)

 8931 12:19:17.759945  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8932 12:19:17.763270  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8933 12:19:17.766706   == TX Byte 1 ==

 8934 12:19:17.769651  u2DelayCellOfst[8]=0 cells (0 PI)

 8935 12:19:17.769732  u2DelayCellOfst[9]=3 cells (1 PI)

 8936 12:19:17.773475  u2DelayCellOfst[10]=10 cells (3 PI)

 8937 12:19:17.776389  u2DelayCellOfst[11]=6 cells (2 PI)

 8938 12:19:17.779603  u2DelayCellOfst[12]=13 cells (4 PI)

 8939 12:19:17.783145  u2DelayCellOfst[13]=13 cells (4 PI)

 8940 12:19:17.786222  u2DelayCellOfst[14]=16 cells (5 PI)

 8941 12:19:17.789750  u2DelayCellOfst[15]=16 cells (5 PI)

 8942 12:19:17.792884  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8943 12:19:17.799878  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8944 12:19:17.799969  DramC Write-DBI on

 8945 12:19:17.800036  ==

 8946 12:19:17.803100  Dram Type= 6, Freq= 0, CH_1, rank 1

 8947 12:19:17.809553  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8948 12:19:17.809637  ==

 8949 12:19:17.809702  

 8950 12:19:17.809763  

 8951 12:19:17.809831  	TX Vref Scan disable

 8952 12:19:17.813262   == TX Byte 0 ==

 8953 12:19:17.816437  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8954 12:19:17.820320   == TX Byte 1 ==

 8955 12:19:17.823449  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8956 12:19:17.826581  DramC Write-DBI off

 8957 12:19:17.826664  

 8958 12:19:17.826729  [DATLAT]

 8959 12:19:17.826788  Freq=1600, CH1 RK1

 8960 12:19:17.826846  

 8961 12:19:17.830235  DATLAT Default: 0xf

 8962 12:19:17.830308  0, 0xFFFF, sum = 0

 8963 12:19:17.833254  1, 0xFFFF, sum = 0

 8964 12:19:17.833325  2, 0xFFFF, sum = 0

 8965 12:19:17.836533  3, 0xFFFF, sum = 0

 8966 12:19:17.840284  4, 0xFFFF, sum = 0

 8967 12:19:17.840358  5, 0xFFFF, sum = 0

 8968 12:19:17.843658  6, 0xFFFF, sum = 0

 8969 12:19:17.843741  7, 0xFFFF, sum = 0

 8970 12:19:17.846852  8, 0xFFFF, sum = 0

 8971 12:19:17.846934  9, 0xFFFF, sum = 0

 8972 12:19:17.849983  10, 0xFFFF, sum = 0

 8973 12:19:17.850054  11, 0xFFFF, sum = 0

 8974 12:19:17.853621  12, 0xFFFF, sum = 0

 8975 12:19:17.853703  13, 0xFFFF, sum = 0

 8976 12:19:17.856822  14, 0x0, sum = 1

 8977 12:19:17.856895  15, 0x0, sum = 2

 8978 12:19:17.859987  16, 0x0, sum = 3

 8979 12:19:17.860059  17, 0x0, sum = 4

 8980 12:19:17.863039  best_step = 15

 8981 12:19:17.863113  

 8982 12:19:17.863175  ==

 8983 12:19:17.866331  Dram Type= 6, Freq= 0, CH_1, rank 1

 8984 12:19:17.870079  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8985 12:19:17.870161  ==

 8986 12:19:17.870224  RX Vref Scan: 0

 8987 12:19:17.873222  

 8988 12:19:17.873295  RX Vref 0 -> 0, step: 1

 8989 12:19:17.873356  

 8990 12:19:17.876419  RX Delay 19 -> 252, step: 4

 8991 12:19:17.880121  iDelay=195, Bit 0, Center 138 (91 ~ 186) 96

 8992 12:19:17.886338  iDelay=195, Bit 1, Center 130 (83 ~ 178) 96

 8993 12:19:17.889547  iDelay=195, Bit 2, Center 122 (71 ~ 174) 104

 8994 12:19:17.893055  iDelay=195, Bit 3, Center 130 (83 ~ 178) 96

 8995 12:19:17.896415  iDelay=195, Bit 4, Center 130 (83 ~ 178) 96

 8996 12:19:17.899711  iDelay=195, Bit 5, Center 146 (99 ~ 194) 96

 8997 12:19:17.903443  iDelay=195, Bit 6, Center 144 (95 ~ 194) 100

 8998 12:19:17.909543  iDelay=195, Bit 7, Center 134 (83 ~ 186) 104

 8999 12:19:17.913332  iDelay=195, Bit 8, Center 118 (67 ~ 170) 104

 9000 12:19:17.916203  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 9001 12:19:17.919476  iDelay=195, Bit 10, Center 132 (83 ~ 182) 100

 9002 12:19:17.923036  iDelay=195, Bit 11, Center 124 (71 ~ 178) 108

 9003 12:19:17.929441  iDelay=195, Bit 12, Center 140 (87 ~ 194) 108

 9004 12:19:17.933218  iDelay=195, Bit 13, Center 138 (87 ~ 190) 104

 9005 12:19:17.936356  iDelay=195, Bit 14, Center 136 (87 ~ 186) 100

 9006 12:19:17.939547  iDelay=195, Bit 15, Center 140 (91 ~ 190) 100

 9007 12:19:17.939672  ==

 9008 12:19:17.942988  Dram Type= 6, Freq= 0, CH_1, rank 1

 9009 12:19:17.949428  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9010 12:19:17.949528  ==

 9011 12:19:17.949610  DQS Delay:

 9012 12:19:17.952718  DQS0 = 0, DQS1 = 0

 9013 12:19:17.952789  DQM Delay:

 9014 12:19:17.956202  DQM0 = 134, DQM1 = 130

 9015 12:19:17.956280  DQ Delay:

 9016 12:19:17.959467  DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130

 9017 12:19:17.963170  DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134

 9018 12:19:17.966338  DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124

 9019 12:19:17.969365  DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140

 9020 12:19:17.969439  

 9021 12:19:17.969501  

 9022 12:19:17.969567  

 9023 12:19:17.972592  [DramC_TX_OE_Calibration] TA2

 9024 12:19:17.976452  Original DQ_B0 (3 6) =30, OEN = 27

 9025 12:19:17.979682  Original DQ_B1 (3 6) =30, OEN = 27

 9026 12:19:17.982843  24, 0x0, End_B0=24 End_B1=24

 9027 12:19:17.982917  25, 0x0, End_B0=25 End_B1=25

 9028 12:19:17.985986  26, 0x0, End_B0=26 End_B1=26

 9029 12:19:17.989850  27, 0x0, End_B0=27 End_B1=27

 9030 12:19:17.992925  28, 0x0, End_B0=28 End_B1=28

 9031 12:19:17.996155  29, 0x0, End_B0=29 End_B1=29

 9032 12:19:17.996234  30, 0x0, End_B0=30 End_B1=30

 9033 12:19:17.999361  31, 0x4141, End_B0=30 End_B1=30

 9034 12:19:18.003010  Byte0 end_step=30  best_step=27

 9035 12:19:18.006242  Byte1 end_step=30  best_step=27

 9036 12:19:18.009344  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9037 12:19:18.012637  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9038 12:19:18.012707  

 9039 12:19:18.012768  

 9040 12:19:18.019628  [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps

 9041 12:19:18.022615  CH1 RK1: MR19=303, MR18=2308

 9042 12:19:18.029205  CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16

 9043 12:19:18.032762  [RxdqsGatingPostProcess] freq 1600

 9044 12:19:18.035736  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9045 12:19:18.039469  best DQS0 dly(2T, 0.5T) = (1, 1)

 9046 12:19:18.042473  best DQS1 dly(2T, 0.5T) = (1, 1)

 9047 12:19:18.046000  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9048 12:19:18.049480  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9049 12:19:18.052522  best DQS0 dly(2T, 0.5T) = (1, 1)

 9050 12:19:18.056024  best DQS1 dly(2T, 0.5T) = (1, 1)

 9051 12:19:18.059461  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9052 12:19:18.062357  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9053 12:19:18.065949  Pre-setting of DQS Precalculation

 9054 12:19:18.069442  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9055 12:19:18.076158  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9056 12:19:18.082898  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9057 12:19:18.086170  

 9058 12:19:18.086247  

 9059 12:19:18.086309  [Calibration Summary] 3200 Mbps

 9060 12:19:18.089212  CH 0, Rank 0

 9061 12:19:18.089283  SW Impedance     : PASS

 9062 12:19:18.092918  DUTY Scan        : NO K

 9063 12:19:18.096149  ZQ Calibration   : PASS

 9064 12:19:18.096220  Jitter Meter     : NO K

 9065 12:19:18.099433  CBT Training     : PASS

 9066 12:19:18.102673  Write leveling   : PASS

 9067 12:19:18.102749  RX DQS gating    : PASS

 9068 12:19:18.106275  RX DQ/DQS(RDDQC) : PASS

 9069 12:19:18.109445  TX DQ/DQS        : PASS

 9070 12:19:18.109518  RX DATLAT        : PASS

 9071 12:19:18.112738  RX DQ/DQS(Engine): PASS

 9072 12:19:18.115996  TX OE            : PASS

 9073 12:19:18.116072  All Pass.

 9074 12:19:18.116134  

 9075 12:19:18.116193  CH 0, Rank 1

 9076 12:19:18.119247  SW Impedance     : PASS

 9077 12:19:18.122449  DUTY Scan        : NO K

 9078 12:19:18.122521  ZQ Calibration   : PASS

 9079 12:19:18.125664  Jitter Meter     : NO K

 9080 12:19:18.128806  CBT Training     : PASS

 9081 12:19:18.128883  Write leveling   : PASS

 9082 12:19:18.132261  RX DQS gating    : PASS

 9083 12:19:18.135335  RX DQ/DQS(RDDQC) : PASS

 9084 12:19:18.135410  TX DQ/DQS        : PASS

 9085 12:19:18.139051  RX DATLAT        : PASS

 9086 12:19:18.139128  RX DQ/DQS(Engine): PASS

 9087 12:19:18.142282  TX OE            : PASS

 9088 12:19:18.142352  All Pass.

 9089 12:19:18.142419  

 9090 12:19:18.145375  CH 1, Rank 0

 9091 12:19:18.145446  SW Impedance     : PASS

 9092 12:19:18.148995  DUTY Scan        : NO K

 9093 12:19:18.151941  ZQ Calibration   : PASS

 9094 12:19:18.152021  Jitter Meter     : NO K

 9095 12:19:18.155437  CBT Training     : PASS

 9096 12:19:18.159122  Write leveling   : PASS

 9097 12:19:18.159201  RX DQS gating    : PASS

 9098 12:19:18.162128  RX DQ/DQS(RDDQC) : PASS

 9099 12:19:18.165180  TX DQ/DQS        : PASS

 9100 12:19:18.165254  RX DATLAT        : PASS

 9101 12:19:18.168602  RX DQ/DQS(Engine): PASS

 9102 12:19:18.171956  TX OE            : PASS

 9103 12:19:18.172028  All Pass.

 9104 12:19:18.172099  

 9105 12:19:18.172160  CH 1, Rank 1

 9106 12:19:18.175157  SW Impedance     : PASS

 9107 12:19:18.178429  DUTY Scan        : NO K

 9108 12:19:18.178508  ZQ Calibration   : PASS

 9109 12:19:18.182190  Jitter Meter     : NO K

 9110 12:19:18.185226  CBT Training     : PASS

 9111 12:19:18.185305  Write leveling   : PASS

 9112 12:19:18.188585  RX DQS gating    : PASS

 9113 12:19:18.191959  RX DQ/DQS(RDDQC) : PASS

 9114 12:19:18.192037  TX DQ/DQS        : PASS

 9115 12:19:18.195534  RX DATLAT        : PASS

 9116 12:19:18.195652  RX DQ/DQS(Engine): PASS

 9117 12:19:18.198643  TX OE            : PASS

 9118 12:19:18.198726  All Pass.

 9119 12:19:18.198794  

 9120 12:19:18.201979  DramC Write-DBI on

 9121 12:19:18.205098  	PER_BANK_REFRESH: Hybrid Mode

 9122 12:19:18.205174  TX_TRACKING: ON

 9123 12:19:18.215020  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9124 12:19:18.221990  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9125 12:19:18.231615  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9126 12:19:18.235448  [FAST_K] Save calibration result to emmc

 9127 12:19:18.235524  sync common calibartion params.

 9128 12:19:18.238481  sync cbt_mode0:1, 1:1

 9129 12:19:18.241898  dram_init: ddr_geometry: 2

 9130 12:19:18.245086  dram_init: ddr_geometry: 2

 9131 12:19:18.245163  dram_init: ddr_geometry: 2

 9132 12:19:18.248126  0:dram_rank_size:100000000

 9133 12:19:18.251960  1:dram_rank_size:100000000

 9134 12:19:18.254980  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9135 12:19:18.258452  DFS_SHUFFLE_HW_MODE: ON

 9136 12:19:18.261814  dramc_set_vcore_voltage set vcore to 725000

 9137 12:19:18.265184  Read voltage for 1600, 0

 9138 12:19:18.265261  Vio18 = 0

 9139 12:19:18.268404  Vcore = 725000

 9140 12:19:18.268488  Vdram = 0

 9141 12:19:18.268556  Vddq = 0

 9142 12:19:18.268618  Vmddr = 0

 9143 12:19:18.271673  switch to 3200 Mbps bootup

 9144 12:19:18.274663  [DramcRunTimeConfig]

 9145 12:19:18.274732  PHYPLL

 9146 12:19:18.278259  DPM_CONTROL_AFTERK: ON

 9147 12:19:18.278335  PER_BANK_REFRESH: ON

 9148 12:19:18.281376  REFRESH_OVERHEAD_REDUCTION: ON

 9149 12:19:18.284978  CMD_PICG_NEW_MODE: OFF

 9150 12:19:18.285057  XRTWTW_NEW_MODE: ON

 9151 12:19:18.288204  XRTRTR_NEW_MODE: ON

 9152 12:19:18.288278  TX_TRACKING: ON

 9153 12:19:18.291223  RDSEL_TRACKING: OFF

 9154 12:19:18.291301  DQS Precalculation for DVFS: ON

 9155 12:19:18.294583  RX_TRACKING: OFF

 9156 12:19:18.294662  HW_GATING DBG: ON

 9157 12:19:18.298005  ZQCS_ENABLE_LP4: ON

 9158 12:19:18.301414  RX_PICG_NEW_MODE: ON

 9159 12:19:18.301500  TX_PICG_NEW_MODE: ON

 9160 12:19:18.304575  ENABLE_RX_DCM_DPHY: ON

 9161 12:19:18.308246  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9162 12:19:18.308331  DUMMY_READ_FOR_TRACKING: OFF

 9163 12:19:18.311267  !!! SPM_CONTROL_AFTERK: OFF

 9164 12:19:18.314880  !!! SPM could not control APHY

 9165 12:19:18.317868  IMPEDANCE_TRACKING: ON

 9166 12:19:18.317951  TEMP_SENSOR: ON

 9167 12:19:18.321588  HW_SAVE_FOR_SR: OFF

 9168 12:19:18.324420  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9169 12:19:18.328085  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9170 12:19:18.328170  Read ODT Tracking: ON

 9171 12:19:18.331045  Refresh Rate DeBounce: ON

 9172 12:19:18.334907  DFS_NO_QUEUE_FLUSH: ON

 9173 12:19:18.338045  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9174 12:19:18.338128  ENABLE_DFS_RUNTIME_MRW: OFF

 9175 12:19:18.341199  DDR_RESERVE_NEW_MODE: ON

 9176 12:19:18.344369  MR_CBT_SWITCH_FREQ: ON

 9177 12:19:18.344451  =========================

 9178 12:19:18.364678  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9179 12:19:18.367570  dram_init: ddr_geometry: 2

 9180 12:19:18.385795  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9181 12:19:18.389511  dram_init: dram init end (result: 0)

 9182 12:19:18.395844  DRAM-K: Full calibration passed in 24477 msecs

 9183 12:19:18.399065  MRC: failed to locate region type 0.

 9184 12:19:18.399177  DRAM rank0 size:0x100000000,

 9185 12:19:18.402970  DRAM rank1 size=0x100000000

 9186 12:19:18.412845  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9187 12:19:18.418998  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9188 12:19:18.425673  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9189 12:19:18.432567  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9190 12:19:18.435917  DRAM rank0 size:0x100000000,

 9191 12:19:18.439098  DRAM rank1 size=0x100000000

 9192 12:19:18.439205  CBMEM:

 9193 12:19:18.442556  IMD: root @ 0xfffff000 254 entries.

 9194 12:19:18.445929  IMD: root @ 0xffffec00 62 entries.

 9195 12:19:18.449362  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9196 12:19:18.452389  WARNING: RO_VPD is uninitialized or empty.

 9197 12:19:18.458965  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9198 12:19:18.465962  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9199 12:19:18.478901  read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps

 9200 12:19:18.490500  BS: romstage times (exec / console): total (unknown) / 24008 ms

 9201 12:19:18.490587  

 9202 12:19:18.490652  

 9203 12:19:18.500497  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9204 12:19:18.503481  ARM64: Exception handlers installed.

 9205 12:19:18.507224  ARM64: Testing exception

 9206 12:19:18.510331  ARM64: Done test exception

 9207 12:19:18.510414  Enumerating buses...

 9208 12:19:18.513356  Show all devs... Before device enumeration.

 9209 12:19:18.517081  Root Device: enabled 1

 9210 12:19:18.520164  CPU_CLUSTER: 0: enabled 1

 9211 12:19:18.520246  CPU: 00: enabled 1

 9212 12:19:18.523357  Compare with tree...

 9213 12:19:18.523439  Root Device: enabled 1

 9214 12:19:18.526574   CPU_CLUSTER: 0: enabled 1

 9215 12:19:18.530374    CPU: 00: enabled 1

 9216 12:19:18.530456  Root Device scanning...

 9217 12:19:18.533619  scan_static_bus for Root Device

 9218 12:19:18.536766  CPU_CLUSTER: 0 enabled

 9219 12:19:18.539946  scan_static_bus for Root Device done

 9220 12:19:18.543410  scan_bus: bus Root Device finished in 8 msecs

 9221 12:19:18.543495  done

 9222 12:19:18.549979  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9223 12:19:18.553465  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9224 12:19:18.559602  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9225 12:19:18.563204  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9226 12:19:18.566461  Allocating resources...

 9227 12:19:18.569604  Reading resources...

 9228 12:19:18.573165  Root Device read_resources bus 0 link: 0

 9229 12:19:18.573248  DRAM rank0 size:0x100000000,

 9230 12:19:18.576218  DRAM rank1 size=0x100000000

 9231 12:19:18.579976  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9232 12:19:18.583172  CPU: 00 missing read_resources

 9233 12:19:18.589959  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9234 12:19:18.592979  Root Device read_resources bus 0 link: 0 done

 9235 12:19:18.593062  Done reading resources.

 9236 12:19:18.599696  Show resources in subtree (Root Device)...After reading.

 9237 12:19:18.602802   Root Device child on link 0 CPU_CLUSTER: 0

 9238 12:19:18.606378    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9239 12:19:18.616310    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9240 12:19:18.616410     CPU: 00

 9241 12:19:18.619463  Root Device assign_resources, bus 0 link: 0

 9242 12:19:18.623203  CPU_CLUSTER: 0 missing set_resources

 9243 12:19:18.629425  Root Device assign_resources, bus 0 link: 0 done

 9244 12:19:18.629523  Done setting resources.

 9245 12:19:18.636166  Show resources in subtree (Root Device)...After assigning values.

 9246 12:19:18.639883   Root Device child on link 0 CPU_CLUSTER: 0

 9247 12:19:18.643068    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9248 12:19:18.652882    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9249 12:19:18.652966     CPU: 00

 9250 12:19:18.656014  Done allocating resources.

 9251 12:19:18.659365  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9252 12:19:18.663007  Enabling resources...

 9253 12:19:18.663089  done.

 9254 12:19:18.669663  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9255 12:19:18.669747  Initializing devices...

 9256 12:19:18.672788  Root Device init

 9257 12:19:18.672886  init hardware done!

 9258 12:19:18.675849  0x00000018: ctrlr->caps

 9259 12:19:18.679659  52.000 MHz: ctrlr->f_max

 9260 12:19:18.679758  0.400 MHz: ctrlr->f_min

 9261 12:19:18.682466  0x40ff8080: ctrlr->voltages

 9262 12:19:18.682549  sclk: 390625

 9263 12:19:18.685723  Bus Width = 1

 9264 12:19:18.685805  sclk: 390625

 9265 12:19:18.689406  Bus Width = 1

 9266 12:19:18.689487  Early init status = 3

 9267 12:19:18.696020  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9268 12:19:18.699085  in-header: 03 fc 00 00 01 00 00 00 

 9269 12:19:18.702454  in-data: 00 

 9270 12:19:18.705773  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9271 12:19:18.710641  in-header: 03 fd 00 00 00 00 00 00 

 9272 12:19:18.714091  in-data: 

 9273 12:19:18.717572  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9274 12:19:18.721828  in-header: 03 fc 00 00 01 00 00 00 

 9275 12:19:18.724901  in-data: 00 

 9276 12:19:18.727978  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9277 12:19:18.733625  in-header: 03 fd 00 00 00 00 00 00 

 9278 12:19:18.737447  in-data: 

 9279 12:19:18.740488  [SSUSB] Setting up USB HOST controller...

 9280 12:19:18.743486  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9281 12:19:18.747291  [SSUSB] phy power-on done.

 9282 12:19:18.750421  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9283 12:19:18.757374  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9284 12:19:18.760319  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9285 12:19:18.766673  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9286 12:19:18.773971  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9287 12:19:18.780066  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9288 12:19:18.787024  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9289 12:19:18.793371  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9290 12:19:18.796896  SPM: binary array size = 0x9dc

 9291 12:19:18.800362  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9292 12:19:18.807047  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9293 12:19:18.813547  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9294 12:19:18.816886  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9295 12:19:18.823027  configure_display: Starting display init

 9296 12:19:18.856942  anx7625_power_on_init: Init interface.

 9297 12:19:18.860120  anx7625_disable_pd_protocol: Disabled PD feature.

 9298 12:19:18.863853  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9299 12:19:18.891747  anx7625_start_dp_work: Secure OCM version=00

 9300 12:19:18.894889  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9301 12:19:18.909352  sp_tx_get_edid_block: EDID Block = 1

 9302 12:19:19.012380  Extracted contents:

 9303 12:19:19.015166  header:          00 ff ff ff ff ff ff 00

 9304 12:19:19.019133  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9305 12:19:19.022301  version:         01 04

 9306 12:19:19.025374  basic params:    95 1f 11 78 0a

 9307 12:19:19.028967  chroma info:     76 90 94 55 54 90 27 21 50 54

 9308 12:19:19.032112  established:     00 00 00

 9309 12:19:19.038438  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9310 12:19:19.041878  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9311 12:19:19.048655  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9312 12:19:19.054982  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9313 12:19:19.061805  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9314 12:19:19.065251  extensions:      00

 9315 12:19:19.065335  checksum:        fb

 9316 12:19:19.065402  

 9317 12:19:19.068449  Manufacturer: IVO Model 57d Serial Number 0

 9318 12:19:19.071907  Made week 0 of 2020

 9319 12:19:19.071989  EDID version: 1.4

 9320 12:19:19.075157  Digital display

 9321 12:19:19.078544  6 bits per primary color channel

 9322 12:19:19.078628  DisplayPort interface

 9323 12:19:19.081576  Maximum image size: 31 cm x 17 cm

 9324 12:19:19.084707  Gamma: 220%

 9325 12:19:19.084791  Check DPMS levels

 9326 12:19:19.088617  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9327 12:19:19.094686  First detailed timing is preferred timing

 9328 12:19:19.094770  Established timings supported:

 9329 12:19:19.098405  Standard timings supported:

 9330 12:19:19.101624  Detailed timings

 9331 12:19:19.104857  Hex of detail: 383680a07038204018303c0035ae10000019

 9332 12:19:19.108029  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9333 12:19:19.114887                 0780 0798 07c8 0820 hborder 0

 9334 12:19:19.118152                 0438 043b 0447 0458 vborder 0

 9335 12:19:19.121650                 -hsync -vsync

 9336 12:19:19.121733  Did detailed timing

 9337 12:19:19.128434  Hex of detail: 000000000000000000000000000000000000

 9338 12:19:19.128519  Manufacturer-specified data, tag 0

 9339 12:19:19.135017  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9340 12:19:19.138047  ASCII string: InfoVision

 9341 12:19:19.141295  Hex of detail: 000000fe00523134304e574635205248200a

 9342 12:19:19.144469  ASCII string: R140NWF5 RH 

 9343 12:19:19.144553  Checksum

 9344 12:19:19.148082  Checksum: 0xfb (valid)

 9345 12:19:19.151433  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9346 12:19:19.154767  DSI data_rate: 832800000 bps

 9347 12:19:19.161021  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9348 12:19:19.164391  anx7625_parse_edid: pixelclock(138800).

 9349 12:19:19.167923   hactive(1920), hsync(48), hfp(24), hbp(88)

 9350 12:19:19.171049   vactive(1080), vsync(12), vfp(3), vbp(17)

 9351 12:19:19.174588  anx7625_dsi_config: config dsi.

 9352 12:19:19.181062  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9353 12:19:19.193993  anx7625_dsi_config: success to config DSI

 9354 12:19:19.197581  anx7625_dp_start: MIPI phy setup OK.

 9355 12:19:19.201085  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9356 12:19:19.204218  mtk_ddp_mode_set invalid vrefresh 60

 9357 12:19:19.207333  main_disp_path_setup

 9358 12:19:19.207416  ovl_layer_smi_id_en

 9359 12:19:19.211000  ovl_layer_smi_id_en

 9360 12:19:19.211115  ccorr_config

 9361 12:19:19.211209  aal_config

 9362 12:19:19.214221  gamma_config

 9363 12:19:19.214305  postmask_config

 9364 12:19:19.217302  dither_config

 9365 12:19:19.220490  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9366 12:19:19.227458                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9367 12:19:19.230436  Root Device init finished in 555 msecs

 9368 12:19:19.233874  CPU_CLUSTER: 0 init

 9369 12:19:19.240427  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9370 12:19:19.244036  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9371 12:19:19.247179  APU_MBOX 0x190000b0 = 0x10001

 9372 12:19:19.250372  APU_MBOX 0x190001b0 = 0x10001

 9373 12:19:19.253668  APU_MBOX 0x190005b0 = 0x10001

 9374 12:19:19.257318  APU_MBOX 0x190006b0 = 0x10001

 9375 12:19:19.260132  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9376 12:19:19.272890  read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps

 9377 12:19:19.285569  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9378 12:19:19.292408  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9379 12:19:19.303898  read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps

 9380 12:19:19.312632  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9381 12:19:19.316085  CPU_CLUSTER: 0 init finished in 81 msecs

 9382 12:19:19.319537  Devices initialized

 9383 12:19:19.322842  Show all devs... After init.

 9384 12:19:19.322926  Root Device: enabled 1

 9385 12:19:19.326067  CPU_CLUSTER: 0: enabled 1

 9386 12:19:19.329505  CPU: 00: enabled 1

 9387 12:19:19.332741  BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms

 9388 12:19:19.335969  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9389 12:19:19.339597  ELOG: NV offset 0x57f000 size 0x1000

 9390 12:19:19.346379  read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps

 9391 12:19:19.353035  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9392 12:19:19.356164  ELOG: Event(17) added with size 13 at 2023-10-27 12:17:44 UTC

 9393 12:19:19.359213  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9394 12:19:19.363487  in-header: 03 c9 00 00 2c 00 00 00 

 9395 12:19:19.376919  in-data: 96 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9396 12:19:19.383271  ELOG: Event(A1) added with size 10 at 2023-10-27 12:17:44 UTC

 9397 12:19:19.390286  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9398 12:19:19.393346  ELOG: Event(A0) added with size 9 at 2023-10-27 12:17:44 UTC

 9399 12:19:19.399801  elog_add_boot_reason: Logged dev mode boot

 9400 12:19:19.403398  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9401 12:19:19.406926  Finalize devices...

 9402 12:19:19.407009  Devices finalized

 9403 12:19:19.413192  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9404 12:19:19.416361  Writing coreboot table at 0xffe64000

 9405 12:19:19.420143   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9406 12:19:19.423304   1. 0000000040000000-00000000400fffff: RAM

 9407 12:19:19.426484   2. 0000000040100000-000000004032afff: RAMSTAGE

 9408 12:19:19.433212   3. 000000004032b000-00000000545fffff: RAM

 9409 12:19:19.436660   4. 0000000054600000-000000005465ffff: BL31

 9410 12:19:19.439848   5. 0000000054660000-00000000ffe63fff: RAM

 9411 12:19:19.443305   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9412 12:19:19.449648   7. 0000000100000000-000000023fffffff: RAM

 9413 12:19:19.449732  Passing 5 GPIOs to payload:

 9414 12:19:19.456350              NAME |       PORT | POLARITY |     VALUE

 9415 12:19:19.459635          EC in RW | 0x000000aa |      low | undefined

 9416 12:19:19.466119      EC interrupt | 0x00000005 |      low | undefined

 9417 12:19:19.469836     TPM interrupt | 0x000000ab |     high | undefined

 9418 12:19:19.473005    SD card detect | 0x00000011 |     high | undefined

 9419 12:19:19.479569    speaker enable | 0x00000093 |     high | undefined

 9420 12:19:19.482801  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9421 12:19:19.486203  in-header: 03 f9 00 00 02 00 00 00 

 9422 12:19:19.489467  in-data: 02 00 

 9423 12:19:19.489549  ADC[4]: Raw value=905834 ID=7

 9424 12:19:19.492996  ADC[3]: Raw value=213072 ID=1

 9425 12:19:19.496038  RAM Code: 0x71

 9426 12:19:19.496121  ADC[6]: Raw value=75332 ID=0

 9427 12:19:19.499220  ADC[5]: Raw value=212703 ID=1

 9428 12:19:19.502954  SKU Code: 0x1

 9429 12:19:19.506187  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2fd8

 9430 12:19:19.509304  coreboot table: 964 bytes.

 9431 12:19:19.512860  IMD ROOT    0. 0xfffff000 0x00001000

 9432 12:19:19.516063  IMD SMALL   1. 0xffffe000 0x00001000

 9433 12:19:19.519276  RO MCACHE   2. 0xffffc000 0x00001104

 9434 12:19:19.522983  CONSOLE     3. 0xfff7c000 0x00080000

 9435 12:19:19.526142  FMAP        4. 0xfff7b000 0x00000452

 9436 12:19:19.529257  TIME STAMP  5. 0xfff7a000 0x00000910

 9437 12:19:19.533095  VBOOT WORK  6. 0xfff66000 0x00014000

 9438 12:19:19.536141  RAMOOPS     7. 0xffe66000 0x00100000

 9439 12:19:19.539293  COREBOOT    8. 0xffe64000 0x00002000

 9440 12:19:19.539375  IMD small region:

 9441 12:19:19.542537    IMD ROOT    0. 0xffffec00 0x00000400

 9442 12:19:19.546359    VPD         1. 0xffffeb80 0x0000006c

 9443 12:19:19.549381    MMC STATUS  2. 0xffffeb60 0x00000004

 9444 12:19:19.555972  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9445 12:19:19.559126  Probing TPM:  done!

 9446 12:19:19.562355  Connected to device vid:did:rid of 1ae0:0028:00

 9447 12:19:19.572978  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9448 12:19:19.576170  Initialized TPM device CR50 revision 0

 9449 12:19:19.579800  Checking cr50 for pending updates

 9450 12:19:19.583085  Reading cr50 TPM mode

 9451 12:19:19.591966  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9452 12:19:19.598237  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9453 12:19:19.638715  read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps

 9454 12:19:19.641983  Checking segment from ROM address 0x40100000

 9455 12:19:19.645135  Checking segment from ROM address 0x4010001c

 9456 12:19:19.652034  Loading segment from ROM address 0x40100000

 9457 12:19:19.652117    code (compression=0)

 9458 12:19:19.662144    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9459 12:19:19.668506  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9460 12:19:19.668589  it's not compressed!

 9461 12:19:19.675290  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9462 12:19:19.678305  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9463 12:19:19.698895  Loading segment from ROM address 0x4010001c

 9464 12:19:19.698985    Entry Point 0x80000000

 9465 12:19:19.702331  Loaded segments

 9466 12:19:19.705743  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9467 12:19:19.712404  Jumping to boot code at 0x80000000(0xffe64000)

 9468 12:19:19.719278  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9469 12:19:19.725668  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9470 12:19:19.733842  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9471 12:19:19.737010  Checking segment from ROM address 0x40100000

 9472 12:19:19.740262  Checking segment from ROM address 0x4010001c

 9473 12:19:19.747147  Loading segment from ROM address 0x40100000

 9474 12:19:19.747230    code (compression=1)

 9475 12:19:19.753506    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9476 12:19:19.763588  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9477 12:19:19.763694  using LZMA

 9478 12:19:19.771763  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9479 12:19:19.778217  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9480 12:19:19.782011  Loading segment from ROM address 0x4010001c

 9481 12:19:19.782128    Entry Point 0x54601000

 9482 12:19:19.785066  Loaded segments

 9483 12:19:19.788496  NOTICE:  MT8192 bl31_setup

 9484 12:19:19.795295  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9485 12:19:19.798427  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9486 12:19:19.802315  WARNING: region 0:

 9487 12:19:19.805568  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9488 12:19:19.805652  WARNING: region 1:

 9489 12:19:19.811973  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9490 12:19:19.815246  WARNING: region 2:

 9491 12:19:19.818580  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9492 12:19:19.822296  WARNING: region 3:

 9493 12:19:19.825344  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9494 12:19:19.828743  WARNING: region 4:

 9495 12:19:19.832203  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9496 12:19:19.835612  WARNING: region 5:

 9497 12:19:19.838576  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9498 12:19:19.842096  WARNING: region 6:

 9499 12:19:19.845946  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9500 12:19:19.846029  WARNING: region 7:

 9501 12:19:19.852372  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9502 12:19:19.858815  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9503 12:19:19.862602  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9504 12:19:19.865790  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9505 12:19:19.868924  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9506 12:19:19.875940  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9507 12:19:19.879170  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9508 12:19:19.885834  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9509 12:19:19.889037  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9510 12:19:19.892961  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9511 12:19:19.898954  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9512 12:19:19.902792  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9513 12:19:19.905804  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9514 12:19:19.912561  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9515 12:19:19.915619  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9516 12:19:19.922438  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9517 12:19:19.926071  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9518 12:19:19.929285  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9519 12:19:19.935986  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9520 12:19:19.939482  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9521 12:19:19.942832  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9522 12:19:19.949483  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9523 12:19:19.952632  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9524 12:19:19.959341  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9525 12:19:19.962885  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9526 12:19:19.965903  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9527 12:19:19.972763  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9528 12:19:19.975870  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9529 12:19:19.979622  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9530 12:19:19.985950  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9531 12:19:19.989471  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9532 12:19:19.996344  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9533 12:19:19.999480  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9534 12:19:20.003173  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9535 12:19:20.009826  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9536 12:19:20.012926  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9537 12:19:20.016467  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9538 12:19:20.019438  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9539 12:19:20.023128  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9540 12:19:20.029280  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9541 12:19:20.032716  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9542 12:19:20.036379  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9543 12:19:20.039740  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9544 12:19:20.046489  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9545 12:19:20.049552  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9546 12:19:20.052788  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9547 12:19:20.059820  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9548 12:19:20.062806  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9549 12:19:20.066361  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9550 12:19:20.069659  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9551 12:19:20.076240  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9552 12:19:20.079287  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9553 12:19:20.086280  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9554 12:19:20.089524  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9555 12:19:20.096384  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9556 12:19:20.099442  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9557 12:19:20.103151  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9558 12:19:20.109456  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9559 12:19:20.113057  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9560 12:19:20.119517  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9561 12:19:20.123233  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9562 12:19:20.129533  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9563 12:19:20.132748  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9564 12:19:20.136392  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9565 12:19:20.142682  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9566 12:19:20.146496  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9567 12:19:20.152728  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9568 12:19:20.156460  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9569 12:19:20.162696  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9570 12:19:20.165920  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9571 12:19:20.169803  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9572 12:19:20.176054  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9573 12:19:20.179336  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9574 12:19:20.186391  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9575 12:19:20.189435  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9576 12:19:20.195775  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9577 12:19:20.199404  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9578 12:19:20.206066  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9579 12:19:20.209618  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9580 12:19:20.212873  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9581 12:19:20.219437  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9582 12:19:20.222747  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9583 12:19:20.229502  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9584 12:19:20.233007  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9585 12:19:20.239380  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9586 12:19:20.243163  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9587 12:19:20.246354  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9588 12:19:20.253296  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9589 12:19:20.256366  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9590 12:19:20.263200  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9591 12:19:20.266281  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9592 12:19:20.272789  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9593 12:19:20.276007  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9594 12:19:20.279658  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9595 12:19:20.286759  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9596 12:19:20.289860  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9597 12:19:20.296105  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9598 12:19:20.299764  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9599 12:19:20.302774  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9600 12:19:20.306352  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9601 12:19:20.312994  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9602 12:19:20.316035  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9603 12:19:20.319476  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9604 12:19:20.326124  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9605 12:19:20.329436  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9606 12:19:20.336231  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9607 12:19:20.339495  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9608 12:19:20.343060  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9609 12:19:20.349573  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9610 12:19:20.352968  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9611 12:19:20.359658  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9612 12:19:20.362838  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9613 12:19:20.366464  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9614 12:19:20.373342  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9615 12:19:20.376676  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9616 12:19:20.382829  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9617 12:19:20.386481  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9618 12:19:20.389676  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9619 12:19:20.392806  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9620 12:19:20.399823  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9621 12:19:20.402803  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9622 12:19:20.406627  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9623 12:19:20.409737  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9624 12:19:20.416180  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9625 12:19:20.419746  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9626 12:19:20.422853  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9627 12:19:20.429930  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9628 12:19:20.433294  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9629 12:19:20.439668  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9630 12:19:20.442776  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9631 12:19:20.446699  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9632 12:19:20.452781  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9633 12:19:20.456079  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9634 12:19:20.459560  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9635 12:19:20.466461  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9636 12:19:20.469632  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9637 12:19:20.476097  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9638 12:19:20.479770  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9639 12:19:20.483003  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9640 12:19:20.489931  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9641 12:19:20.493212  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9642 12:19:20.499376  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9643 12:19:20.503139  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9644 12:19:20.506239  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9645 12:19:20.513261  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9646 12:19:20.516462  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9647 12:19:20.519480  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9648 12:19:20.526568  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9649 12:19:20.529696  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9650 12:19:20.536483  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9651 12:19:20.539513  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9652 12:19:20.542989  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9653 12:19:20.549988  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9654 12:19:20.553103  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9655 12:19:20.556645  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9656 12:19:20.562898  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9657 12:19:20.566575  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9658 12:19:20.573055  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9659 12:19:20.576551  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9660 12:19:20.579958  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9661 12:19:20.586451  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9662 12:19:20.589987  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9663 12:19:20.596249  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9664 12:19:20.599823  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9665 12:19:20.603012  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9666 12:19:20.609933  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9667 12:19:20.613089  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9668 12:19:20.616221  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9669 12:19:20.623334  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9670 12:19:20.626389  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9671 12:19:20.632806  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9672 12:19:20.636506  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9673 12:19:20.639568  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9674 12:19:20.646616  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9675 12:19:20.649614  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9676 12:19:20.656242  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9677 12:19:20.659560  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9678 12:19:20.663319  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9679 12:19:20.670089  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9680 12:19:20.673150  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9681 12:19:20.676328  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9682 12:19:20.683059  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9683 12:19:20.686527  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9684 12:19:20.692756  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9685 12:19:20.696698  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9686 12:19:20.699786  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9687 12:19:20.706633  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9688 12:19:20.709660  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9689 12:19:20.716465  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9690 12:19:20.719341  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9691 12:19:20.722902  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9692 12:19:20.729258  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9693 12:19:20.733009  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9694 12:19:20.739551  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9695 12:19:20.743212  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9696 12:19:20.749734  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9697 12:19:20.752841  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9698 12:19:20.756128  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9699 12:19:20.762760  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9700 12:19:20.766203  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9701 12:19:20.772944  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9702 12:19:20.776001  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9703 12:19:20.779153  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9704 12:19:20.786077  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9705 12:19:20.789197  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9706 12:19:20.796281  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9707 12:19:20.799373  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9708 12:19:20.805683  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9709 12:19:20.809501  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9710 12:19:20.812664  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9711 12:19:20.819566  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9712 12:19:20.822740  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9713 12:19:20.829395  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9714 12:19:20.832519  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9715 12:19:20.836021  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9716 12:19:20.842528  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9717 12:19:20.845791  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9718 12:19:20.852524  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9719 12:19:20.855715  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9720 12:19:20.862397  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9721 12:19:20.865633  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9722 12:19:20.869336  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9723 12:19:20.875983  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9724 12:19:20.878957  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9725 12:19:20.885952  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9726 12:19:20.889165  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9727 12:19:20.892288  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9728 12:19:20.899008  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9729 12:19:20.902435  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9730 12:19:20.908733  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9731 12:19:20.912503  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9732 12:19:20.915537  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9733 12:19:20.918715  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9734 12:19:20.925748  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9735 12:19:20.928935  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9736 12:19:20.932135  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9737 12:19:20.939000  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9738 12:19:20.941914  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9739 12:19:20.945378  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9740 12:19:20.952356  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9741 12:19:20.955577  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9742 12:19:20.958572  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9743 12:19:20.965400  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9744 12:19:20.968323  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9745 12:19:20.971830  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9746 12:19:20.978448  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9747 12:19:20.982038  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9748 12:19:20.988576  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9749 12:19:20.991927  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9750 12:19:20.994986  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9751 12:19:21.001711  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9752 12:19:21.004749  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9753 12:19:21.008339  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9754 12:19:21.014998  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9755 12:19:21.018252  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9756 12:19:21.021977  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9757 12:19:21.028468  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9758 12:19:21.032121  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9759 12:19:21.038297  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9760 12:19:21.041564  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9761 12:19:21.045422  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9762 12:19:21.052169  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9763 12:19:21.055309  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9764 12:19:21.058354  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9765 12:19:21.065195  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9766 12:19:21.068299  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9767 12:19:21.072029  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9768 12:19:21.078089  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9769 12:19:21.081744  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9770 12:19:21.087912  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9771 12:19:21.091596  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9772 12:19:21.094518  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9773 12:19:21.097903  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9774 12:19:21.101127  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9775 12:19:21.107594  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9776 12:19:21.111061  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9777 12:19:21.114255  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9778 12:19:21.117918  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9779 12:19:21.124475  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9780 12:19:21.127478  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9781 12:19:21.131278  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9782 12:19:21.137523  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9783 12:19:21.141403  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9784 12:19:21.144610  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9785 12:19:21.150916  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9786 12:19:21.154639  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9787 12:19:21.160780  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9788 12:19:21.164560  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9789 12:19:21.167565  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9790 12:19:21.174622  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9791 12:19:21.177665  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9792 12:19:21.184453  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9793 12:19:21.187839  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9794 12:19:21.190874  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9795 12:19:21.197747  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9796 12:19:21.200959  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9797 12:19:21.207608  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9798 12:19:21.210769  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9799 12:19:21.214417  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9800 12:19:21.220792  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9801 12:19:21.223932  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9802 12:19:21.230967  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9803 12:19:21.234365  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9804 12:19:21.237368  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9805 12:19:21.243983  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9806 12:19:21.247440  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9807 12:19:21.253831  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9808 12:19:21.257549  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9809 12:19:21.260616  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9810 12:19:21.267562  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9811 12:19:21.270963  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9812 12:19:21.277224  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9813 12:19:21.280291  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9814 12:19:21.286923  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9815 12:19:21.290692  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9816 12:19:21.293797  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9817 12:19:21.300653  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9818 12:19:21.303791  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9819 12:19:21.310741  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9820 12:19:21.313917  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9821 12:19:21.317065  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9822 12:19:21.324001  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9823 12:19:21.327102  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9824 12:19:21.330727  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9825 12:19:21.337512  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9826 12:19:21.340730  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9827 12:19:21.347470  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9828 12:19:21.350512  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9829 12:19:21.357273  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9830 12:19:21.360552  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9831 12:19:21.363933  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9832 12:19:21.370467  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9833 12:19:21.373698  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9834 12:19:21.380448  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9835 12:19:21.384115  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9836 12:19:21.387181  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9837 12:19:21.393877  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9838 12:19:21.397257  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9839 12:19:21.403299  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9840 12:19:21.407210  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9841 12:19:21.410325  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9842 12:19:21.416595  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9843 12:19:21.420527  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9844 12:19:21.426984  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9845 12:19:21.430020  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9846 12:19:21.436761  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9847 12:19:21.439697  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9848 12:19:21.443273  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9849 12:19:21.450154  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9850 12:19:21.453136  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9851 12:19:21.459898  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9852 12:19:21.463029  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9853 12:19:21.466827  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9854 12:19:21.473082  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9855 12:19:21.476161  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9856 12:19:21.482919  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9857 12:19:21.486307  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9858 12:19:21.492950  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9859 12:19:21.496417  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9860 12:19:21.499631  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9861 12:19:21.506264  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9862 12:19:21.510131  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9863 12:19:21.516532  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9864 12:19:21.519653  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9865 12:19:21.526720  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9866 12:19:21.529912  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9867 12:19:21.533083  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9868 12:19:21.539739  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9869 12:19:21.542872  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9870 12:19:21.549689  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9871 12:19:21.553202  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9872 12:19:21.559395  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9873 12:19:21.562970  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9874 12:19:21.566028  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9875 12:19:21.573049  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9876 12:19:21.576132  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9877 12:19:21.583058  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9878 12:19:21.586276  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9879 12:19:21.593010  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9880 12:19:21.596148  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9881 12:19:21.599647  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9882 12:19:21.606467  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9883 12:19:21.609864  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9884 12:19:21.616350  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9885 12:19:21.619162  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9886 12:19:21.625954  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9887 12:19:21.629608  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9888 12:19:21.633198  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9889 12:19:21.639540  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9890 12:19:21.642661  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9891 12:19:21.649347  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9892 12:19:21.652521  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9893 12:19:21.659038  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9894 12:19:21.662755  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9895 12:19:21.665900  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9896 12:19:21.672449  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9897 12:19:21.675751  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9898 12:19:21.682574  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9899 12:19:21.685844  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9900 12:19:21.692779  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9901 12:19:21.695819  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9902 12:19:21.702667  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9903 12:19:21.705719  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9904 12:19:21.708861  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9905 12:19:21.715869  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9906 12:19:21.719077  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9907 12:19:21.725977  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9908 12:19:21.729095  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9909 12:19:21.735658  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9910 12:19:21.738575  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9911 12:19:21.745727  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9912 12:19:21.748903  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9913 12:19:21.755238  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9914 12:19:21.758625  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9915 12:19:21.762513  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9916 12:19:21.768728  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9917 12:19:21.772329  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9918 12:19:21.778958  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9919 12:19:21.782062  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9920 12:19:21.788481  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9921 12:19:21.792307  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9922 12:19:21.798360  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9923 12:19:21.802286  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9924 12:19:21.808487  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9925 12:19:21.812348  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9926 12:19:21.818520  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9927 12:19:21.822097  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9928 12:19:21.828670  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9929 12:19:21.832213  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9930 12:19:21.838473  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9931 12:19:21.841660  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9932 12:19:21.848584  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9933 12:19:21.851731  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9934 12:19:21.858464  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9935 12:19:21.861795  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9936 12:19:21.868350  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9937 12:19:21.868433  INFO:    [APUAPC] vio 0

 9938 12:19:21.875224  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9939 12:19:21.878169  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9940 12:19:21.882079  INFO:    [APUAPC] D0_APC_0: 0x400510

 9941 12:19:21.885049  INFO:    [APUAPC] D0_APC_1: 0x0

 9942 12:19:21.888162  INFO:    [APUAPC] D0_APC_2: 0x1540

 9943 12:19:21.891824  INFO:    [APUAPC] D0_APC_3: 0x0

 9944 12:19:21.894829  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9945 12:19:21.898602  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9946 12:19:21.901758  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9947 12:19:21.904913  INFO:    [APUAPC] D1_APC_3: 0x0

 9948 12:19:21.908181  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9949 12:19:21.911829  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9950 12:19:21.915017  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9951 12:19:21.918677  INFO:    [APUAPC] D2_APC_3: 0x0

 9952 12:19:21.921784  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9953 12:19:21.924895  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9954 12:19:21.928094  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9955 12:19:21.928177  INFO:    [APUAPC] D3_APC_3: 0x0

 9956 12:19:21.934959  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9957 12:19:21.938419  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9958 12:19:21.941546  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9959 12:19:21.941630  INFO:    [APUAPC] D4_APC_3: 0x0

 9960 12:19:21.944833  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9961 12:19:21.951765  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9962 12:19:21.954855  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9963 12:19:21.954938  INFO:    [APUAPC] D5_APC_3: 0x0

 9964 12:19:21.958006  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9965 12:19:21.961289  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9966 12:19:21.965079  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9967 12:19:21.968193  INFO:    [APUAPC] D6_APC_3: 0x0

 9968 12:19:21.971276  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9969 12:19:21.975093  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9970 12:19:21.978261  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9971 12:19:21.981342  INFO:    [APUAPC] D7_APC_3: 0x0

 9972 12:19:21.984474  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9973 12:19:21.988162  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9974 12:19:21.991062  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9975 12:19:21.994678  INFO:    [APUAPC] D8_APC_3: 0x0

 9976 12:19:21.997884  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9977 12:19:22.001558  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9978 12:19:22.004561  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9979 12:19:22.007901  INFO:    [APUAPC] D9_APC_3: 0x0

 9980 12:19:22.011185  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9981 12:19:22.014874  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9982 12:19:22.017670  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9983 12:19:22.021359  INFO:    [APUAPC] D10_APC_3: 0x0

 9984 12:19:22.024506  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9985 12:19:22.028295  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9986 12:19:22.031413  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9987 12:19:22.034737  INFO:    [APUAPC] D11_APC_3: 0x0

 9988 12:19:22.037780  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9989 12:19:22.041494  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9990 12:19:22.045017  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9991 12:19:22.048129  INFO:    [APUAPC] D12_APC_3: 0x0

 9992 12:19:22.051267  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9993 12:19:22.054698  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9994 12:19:22.057842  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9995 12:19:22.061713  INFO:    [APUAPC] D13_APC_3: 0x0

 9996 12:19:22.064951  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9997 12:19:22.068168  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9998 12:19:22.071380  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9999 12:19:22.074485  INFO:    [APUAPC] D14_APC_3: 0x0

10000 12:19:22.078366  INFO:    [APUAPC] D15_APC_0: 0xffffffff

10001 12:19:22.081484  INFO:    [APUAPC] D15_APC_1: 0xffffffff

10002 12:19:22.084754  INFO:    [APUAPC] D15_APC_2: 0x3fffff

10003 12:19:22.087907  INFO:    [APUAPC] D15_APC_3: 0x0

10004 12:19:22.091055  INFO:    [APUAPC] APC_CON: 0x4

10005 12:19:22.094986  INFO:    [NOCDAPC] D0_APC_0: 0x0

10006 12:19:22.098096  INFO:    [NOCDAPC] D0_APC_1: 0x0

10007 12:19:22.101248  INFO:    [NOCDAPC] D1_APC_0: 0x0

10008 12:19:22.101381  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10009 12:19:22.104640  INFO:    [NOCDAPC] D2_APC_0: 0x0

10010 12:19:22.107873  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10011 12:19:22.110901  INFO:    [NOCDAPC] D3_APC_0: 0x0

10012 12:19:22.114626  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10013 12:19:22.117729  INFO:    [NOCDAPC] D4_APC_0: 0x0

10014 12:19:22.121294  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10015 12:19:22.124494  INFO:    [NOCDAPC] D5_APC_0: 0x0

10016 12:19:22.127602  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10017 12:19:22.131234  INFO:    [NOCDAPC] D6_APC_0: 0x0

10018 12:19:22.134765  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10019 12:19:22.134848  INFO:    [NOCDAPC] D7_APC_0: 0x0

10020 12:19:22.137863  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10021 12:19:22.141330  INFO:    [NOCDAPC] D8_APC_0: 0x0

10022 12:19:22.144597  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10023 12:19:22.147542  INFO:    [NOCDAPC] D9_APC_0: 0x0

10024 12:19:22.151037  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10025 12:19:22.154238  INFO:    [NOCDAPC] D10_APC_0: 0x0

10026 12:19:22.157494  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10027 12:19:22.161006  INFO:    [NOCDAPC] D11_APC_0: 0x0

10028 12:19:22.164095  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10029 12:19:22.167834  INFO:    [NOCDAPC] D12_APC_0: 0x0

10030 12:19:22.170920  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10031 12:19:22.174139  INFO:    [NOCDAPC] D13_APC_0: 0x0

10032 12:19:22.177918  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10033 12:19:22.178003  INFO:    [NOCDAPC] D14_APC_0: 0x0

10034 12:19:22.180997  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10035 12:19:22.184023  INFO:    [NOCDAPC] D15_APC_0: 0x0

10036 12:19:22.187780  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10037 12:19:22.190944  INFO:    [NOCDAPC] APC_CON: 0x4

10038 12:19:22.194053  INFO:    [APUAPC] set_apusys_apc done

10039 12:19:22.197703  INFO:    [DEVAPC] devapc_init done

10040 12:19:22.200775  INFO:    GICv3 without legacy support detected.

10041 12:19:22.207673  INFO:    ARM GICv3 driver initialized in EL3

10042 12:19:22.211019  INFO:    Maximum SPI INTID supported: 639

10043 12:19:22.214207  INFO:    BL31: Initializing runtime services

10044 12:19:22.220845  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10045 12:19:22.220931  INFO:    SPM: enable CPC mode

10046 12:19:22.227435  INFO:    mcdi ready for mcusys-off-idle and system suspend

10047 12:19:22.230663  INFO:    BL31: Preparing for EL3 exit to normal world

10048 12:19:22.233918  INFO:    Entry point address = 0x80000000

10049 12:19:22.236995  INFO:    SPSR = 0x8

10050 12:19:22.243183  

10051 12:19:22.243267  

10052 12:19:22.243357  

10053 12:19:22.244048  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10054 12:19:22.244186  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10055 12:19:22.244309  Setting prompt string to ['asurada:']
10056 12:19:22.244425  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10057 12:19:22.246630  Starting depthcharge on Spherion...

10058 12:19:22.246712  

10059 12:19:22.246776  Wipe memory regions:

10060 12:19:22.246837  

10061 12:19:22.250084  	[0x00000040000000, 0x00000054600000)

10062 12:19:22.372506  

10063 12:19:22.372653  	[0x00000054660000, 0x00000080000000)

10064 12:19:22.632664  

10065 12:19:22.632796  	[0x000000821a7280, 0x000000ffe64000)

10066 12:19:23.377446  

10067 12:19:23.377600  	[0x00000100000000, 0x00000240000000)

10068 12:19:25.267449  

10069 12:19:25.270458  Initializing XHCI USB controller at 0x11200000.

10070 12:19:26.308736  

10071 12:19:26.312001  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10072 12:19:26.312116  

10073 12:19:26.312185  

10074 12:19:26.312247  

10075 12:19:26.312534  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 12:19:26.412891  asurada: tftpboot 192.168.201.1 11893116/tftp-deploy-xlfix1x7/kernel/image.itb 11893116/tftp-deploy-xlfix1x7/kernel/cmdline 

10078 12:19:26.413104  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10079 12:19:26.413225  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10080 12:19:26.416926  tftpboot 192.168.201.1 11893116/tftp-deploy-xlfix1x7/kernel/image.itbtp-deploy-xlfix1x7/kernel/cmdline 

10081 12:19:26.417092  

10082 12:19:26.417160  Waiting for link

10083 12:19:26.577533  

10084 12:19:26.577670  R8152: Initializing

10085 12:19:26.577738  

10086 12:19:26.580798  Version 9 (ocp_data = 6010)

10087 12:19:26.580880  

10088 12:19:26.584057  R8152: Done initializing

10089 12:19:26.584139  

10090 12:19:26.584205  Adding net device

10091 12:19:28.457144  

10092 12:19:28.457282  done.

10093 12:19:28.457356  

10094 12:19:28.457430  MAC: 00:e0:4c:78:7a:aa

10095 12:19:28.457498  

10096 12:19:28.460398  Sending DHCP discover... done.

10097 12:19:28.460478  

10098 12:19:28.463486  Waiting for reply... done.

10099 12:19:28.463560  

10100 12:19:28.466513  Sending DHCP request... done.

10101 12:19:28.466594  

10102 12:19:28.470283  Waiting for reply... done.

10103 12:19:28.470364  

10104 12:19:28.470428  My ip is 192.168.201.12

10105 12:19:28.470494  

10106 12:19:28.473260  The DHCP server ip is 192.168.201.1

10107 12:19:28.473334  

10108 12:19:28.476412  TFTP server IP predefined by user: 192.168.201.1

10109 12:19:28.480230  

10110 12:19:28.486566  Bootfile predefined by user: 11893116/tftp-deploy-xlfix1x7/kernel/image.itb

10111 12:19:28.486652  

10112 12:19:28.486719  Sending tftp read request... done.

10113 12:19:28.486786  

10114 12:19:28.493118  Waiting for the transfer... 

10115 12:19:28.493203  

10116 12:19:28.757578  00000000 ################################################################

10117 12:19:28.757784  

10118 12:19:29.028843  00080000 ################################################################

10119 12:19:29.029011  

10120 12:19:29.292668  00100000 ################################################################

10121 12:19:29.292822  

10122 12:19:29.572615  00180000 ################################################################

10123 12:19:29.572771  

10124 12:19:29.829854  00200000 ################################################################

10125 12:19:29.830000  

10126 12:19:30.103436  00280000 ################################################################

10127 12:19:30.103578  

10128 12:19:30.393813  00300000 ################################################################

10129 12:19:30.393956  

10130 12:19:30.648686  00380000 ################################################################

10131 12:19:30.648825  

10132 12:19:30.903574  00400000 ################################################################

10133 12:19:30.903766  

10134 12:19:31.181000  00480000 ################################################################

10135 12:19:31.181144  

10136 12:19:31.442738  00500000 ################################################################

10137 12:19:31.442891  

10138 12:19:31.697993  00580000 ################################################################

10139 12:19:31.698129  

10140 12:19:31.962402  00600000 ################################################################

10141 12:19:31.962540  

10142 12:19:32.242070  00680000 ################################################################

10143 12:19:32.242229  

10144 12:19:32.505348  00700000 ################################################################

10145 12:19:32.505484  

10146 12:19:32.764008  00780000 ################################################################

10147 12:19:32.764147  

10148 12:19:33.038555  00800000 ################################################################

10149 12:19:33.038708  

10150 12:19:33.293488  00880000 ################################################################

10151 12:19:33.293629  

10152 12:19:33.562978  00900000 ################################################################

10153 12:19:33.563113  

10154 12:19:33.835320  00980000 ################################################################

10155 12:19:33.835481  

10156 12:19:34.078132  00a00000 ################################################################

10157 12:19:34.078299  

10158 12:19:34.321480  00a80000 ################################################################

10159 12:19:34.321634  

10160 12:19:34.576379  00b00000 ################################################################

10161 12:19:34.576533  

10162 12:19:34.829523  00b80000 ################################################################

10163 12:19:34.829686  

10164 12:19:35.100914  00c00000 ################################################################

10165 12:19:35.101069  

10166 12:19:35.376319  00c80000 ################################################################

10167 12:19:35.376492  

10168 12:19:35.651345  00d00000 ################################################################

10169 12:19:35.651499  

10170 12:19:35.911248  00d80000 ################################################################

10171 12:19:35.911426  

10172 12:19:36.179835  00e00000 ################################################################

10173 12:19:36.179989  

10174 12:19:36.451898  00e80000 ################################################################

10175 12:19:36.452046  

10176 12:19:36.738207  00f00000 ################################################################

10177 12:19:36.738360  

10178 12:19:37.000820  00f80000 ################################################################

10179 12:19:37.000972  

10180 12:19:37.267425  01000000 ################################################################

10181 12:19:37.267589  

10182 12:19:37.546884  01080000 ################################################################

10183 12:19:37.547040  

10184 12:19:37.815396  01100000 ################################################################

10185 12:19:37.815548  

10186 12:19:38.096220  01180000 ################################################################

10187 12:19:38.096360  

10188 12:19:38.374384  01200000 ################################################################

10189 12:19:38.374524  

10190 12:19:38.649851  01280000 ################################################################

10191 12:19:38.650005  

10192 12:19:38.919126  01300000 ################################################################

10193 12:19:38.919270  

10194 12:19:39.191778  01380000 ################################################################

10195 12:19:39.191941  

10196 12:19:39.472722  01400000 ################################################################

10197 12:19:39.472888  

10198 12:19:39.736856  01480000 ################################################################

10199 12:19:39.736992  

10200 12:19:39.991619  01500000 ################################################################

10201 12:19:39.991783  

10202 12:19:40.240955  01580000 ################################################################

10203 12:19:40.241343  

10204 12:19:40.518394  01600000 ################################################################

10205 12:19:40.518535  

10206 12:19:40.789942  01680000 ################################################################

10207 12:19:40.790080  

10208 12:19:41.065054  01700000 ################################################################

10209 12:19:41.065203  

10210 12:19:41.347669  01780000 ################################################################

10211 12:19:41.347824  

10212 12:19:41.630528  01800000 ################################################################

10213 12:19:41.630668  

10214 12:19:41.922735  01880000 ################################################################

10215 12:19:41.922910  

10216 12:19:42.210776  01900000 ################################################################

10217 12:19:42.210954  

10218 12:19:42.499277  01980000 ################################################################

10219 12:19:42.499429  

10220 12:19:42.774949  01a00000 ################################################################

10221 12:19:42.775100  

10222 12:19:43.049188  01a80000 ################################################################

10223 12:19:43.049361  

10224 12:19:43.328017  01b00000 ################################################################

10225 12:19:43.328194  

10226 12:19:43.355824  01b80000 ####### done.

10227 12:19:43.355961  

10228 12:19:43.358937  The bootfile was 28886350 bytes long.

10229 12:19:43.359021  

10230 12:19:43.362413  Sending tftp read request... done.

10231 12:19:43.362498  

10232 12:19:43.365842  Waiting for the transfer... 

10233 12:19:43.365925  

10234 12:19:43.365991  00000000 # done.

10235 12:19:43.366053  

10236 12:19:43.372608  Command line loaded dynamically from TFTP file: 11893116/tftp-deploy-xlfix1x7/kernel/cmdline

10237 12:19:43.375853  

10238 12:19:43.395450  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893116/extract-nfsrootfs-fmw_h8hb,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10239 12:19:43.395570  

10240 12:19:43.395643  Loading FIT.

10241 12:19:43.398509  

10242 12:19:43.398592  Image ramdisk-1 has 17789041 bytes.

10243 12:19:43.398658  

10244 12:19:43.402311  Image fdt-1 has 47278 bytes.

10245 12:19:43.402393  

10246 12:19:43.405504  Image kernel-1 has 11047994 bytes.

10247 12:19:43.405586  

10248 12:19:43.414937  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10249 12:19:43.415022  

10250 12:19:43.431589  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10251 12:19:43.431748  

10252 12:19:43.438337  Choosing best match conf-1 for compat google,spherion-rev2.

10253 12:19:43.441987  

10254 12:19:43.446833  Connected to device vid:did:rid of 1ae0:0028:00

10255 12:19:43.454394  

10256 12:19:43.458096  tpm_get_response: command 0x17b, return code 0x0

10257 12:19:43.458180  

10258 12:19:43.464907  ec_init: CrosEC protocol v3 supported (256, 248)

10259 12:19:43.464992  

10260 12:19:43.468078  tpm_cleanup: add release locality here.

10261 12:19:43.468160  

10262 12:19:43.471231  Shutting down all USB controllers.

10263 12:19:43.471313  

10264 12:19:43.474404  Removing current net device

10265 12:19:43.474505  

10266 12:19:43.477861  Exiting depthcharge with code 4 at timestamp: 50534971

10267 12:19:43.481292  

10268 12:19:43.484370  LZMA decompressing kernel-1 to 0x821a6718

10269 12:19:43.484455  

10270 12:19:43.488063  LZMA decompressing kernel-1 to 0x40000000

10271 12:19:44.875629  

10272 12:19:44.875823  jumping to kernel

10273 12:19:44.876274  end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10274 12:19:44.876373  start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10275 12:19:44.876450  Setting prompt string to ['Linux version [0-9]']
10276 12:19:44.876519  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10277 12:19:44.876589  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10278 12:19:44.958343  

10279 12:19:44.962056  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10280 12:19:44.965512  start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10281 12:19:44.965604  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10282 12:19:44.965677  Setting prompt string to []
10283 12:19:44.965754  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10284 12:19:44.965827  Using line separator: #'\n'#
10285 12:19:44.965887  No login prompt set.
10286 12:19:44.965947  Parsing kernel messages
10287 12:19:44.966003  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10288 12:19:44.966104  [login-action] Waiting for messages, (timeout 00:04:03)
10289 12:19:44.985109  [    0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023

10290 12:19:44.987892  [    0.000000] random: crng init done

10291 12:19:44.994756  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10292 12:19:44.997856  [    0.000000] efi: UEFI not found.

10293 12:19:45.004342  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10294 12:19:45.011313  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10295 12:19:45.021265  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10296 12:19:45.030892  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10297 12:19:45.037430  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10298 12:19:45.043861  [    0.000000] printk: bootconsole [mtk8250] enabled

10299 12:19:45.050697  [    0.000000] NUMA: No NUMA configuration found

10300 12:19:45.057275  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10301 12:19:45.060859  [    0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]

10302 12:19:45.064041  [    0.000000] Zone ranges:

10303 12:19:45.070822  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10304 12:19:45.074038  [    0.000000]   DMA32    empty

10305 12:19:45.080487  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10306 12:19:45.083547  [    0.000000] Movable zone start for each node

10307 12:19:45.087412  [    0.000000] Early memory node ranges

10308 12:19:45.093599  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10309 12:19:45.100429  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10310 12:19:45.107037  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10311 12:19:45.113766  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10312 12:19:45.120292  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10313 12:19:45.126992  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10314 12:19:45.183103  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10315 12:19:45.189723  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10316 12:19:45.195946  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10317 12:19:45.199528  [    0.000000] psci: probing for conduit method from DT.

10318 12:19:45.206241  [    0.000000] psci: PSCIv1.1 detected in firmware.

10319 12:19:45.209551  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10320 12:19:45.215982  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10321 12:19:45.219435  [    0.000000] psci: SMC Calling Convention v1.2

10322 12:19:45.225588  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10323 12:19:45.228901  [    0.000000] Detected VIPT I-cache on CPU0

10324 12:19:45.235563  [    0.000000] CPU features: detected: GIC system register CPU interface

10325 12:19:45.242845  [    0.000000] CPU features: detected: Virtualization Host Extensions

10326 12:19:45.249082  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10327 12:19:45.255889  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10328 12:19:45.266026  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10329 12:19:45.272146  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10330 12:19:45.275195  [    0.000000] alternatives: applying boot alternatives

10331 12:19:45.281922  [    0.000000] Fallback order for Node 0: 0 

10332 12:19:45.288889  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10333 12:19:45.291908  [    0.000000] Policy zone: Normal

10334 12:19:45.314857  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11893116/extract-nfsrootfs-fmw_h8hb,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10335 12:19:45.324909  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10336 12:19:45.335529  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10337 12:19:45.345997  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10338 12:19:45.352228  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10339 12:19:45.355289  <6>[    0.000000] software IO TLB: area num 8.

10340 12:19:45.412324  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10341 12:19:45.561318  <6>[    0.000000] Memory: 7952116K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 400652K reserved, 32768K cma-reserved)

10342 12:19:45.568202  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10343 12:19:45.574508  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10344 12:19:45.578137  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10345 12:19:45.584754  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10346 12:19:45.591224  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10347 12:19:45.594397  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10348 12:19:45.604634  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10349 12:19:45.611272  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10350 12:19:45.617562  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10351 12:19:45.624464  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10352 12:19:45.627526  <6>[    0.000000] GICv3: 608 SPIs implemented

10353 12:19:45.631117  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10354 12:19:45.637450  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10355 12:19:45.640637  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10356 12:19:45.647606  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10357 12:19:45.660579  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10358 12:19:45.670613  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10359 12:19:45.680532  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10360 12:19:45.688376  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10361 12:19:45.701377  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10362 12:19:45.707811  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10363 12:19:45.714604  <6>[    0.009230] Console: colour dummy device 80x25

10364 12:19:45.725081  <6>[    0.013956] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10365 12:19:45.731400  <6>[    0.024397] pid_max: default: 32768 minimum: 301

10366 12:19:45.734541  <6>[    0.029270] LSM: Security Framework initializing

10367 12:19:45.741786  <6>[    0.034208] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10368 12:19:45.751401  <6>[    0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10369 12:19:45.758162  <6>[    0.051494] cblist_init_generic: Setting adjustable number of callback queues.

10370 12:19:45.764866  <6>[    0.058938] cblist_init_generic: Setting shift to 3 and lim to 1.

10371 12:19:45.774482  <6>[    0.065276] cblist_init_generic: Setting adjustable number of callback queues.

10372 12:19:45.781397  <6>[    0.072748] cblist_init_generic: Setting shift to 3 and lim to 1.

10373 12:19:45.784074  <6>[    0.079148] rcu: Hierarchical SRCU implementation.

10374 12:19:45.790693  <6>[    0.084194] rcu: 	Max phase no-delay instances is 1000.

10375 12:19:45.797393  <6>[    0.091217] EFI services will not be available.

10376 12:19:45.800997  <6>[    0.096174] smp: Bringing up secondary CPUs ...

10377 12:19:45.809520  <6>[    0.101225] Detected VIPT I-cache on CPU1

10378 12:19:45.815998  <6>[    0.101293] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10379 12:19:45.822333  <6>[    0.101322] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10380 12:19:45.825365  <6>[    0.101663] Detected VIPT I-cache on CPU2

10381 12:19:45.835759  <6>[    0.101715] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10382 12:19:45.842630  <6>[    0.101731] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10383 12:19:45.845895  <6>[    0.101992] Detected VIPT I-cache on CPU3

10384 12:19:45.852279  <6>[    0.102040] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10385 12:19:45.858774  <6>[    0.102054] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10386 12:19:45.862208  <6>[    0.102360] CPU features: detected: Spectre-v4

10387 12:19:45.868881  <6>[    0.102366] CPU features: detected: Spectre-BHB

10388 12:19:45.871934  <6>[    0.102370] Detected PIPT I-cache on CPU4

10389 12:19:45.878537  <6>[    0.102427] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10390 12:19:45.885031  <6>[    0.102443] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10391 12:19:45.891979  <6>[    0.102743] Detected PIPT I-cache on CPU5

10392 12:19:45.898492  <6>[    0.102805] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10393 12:19:45.905575  <6>[    0.102822] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10394 12:19:45.908429  <6>[    0.103104] Detected PIPT I-cache on CPU6

10395 12:19:45.915432  <6>[    0.103170] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10396 12:19:45.921611  <6>[    0.103187] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10397 12:19:45.928621  <6>[    0.103484] Detected PIPT I-cache on CPU7

10398 12:19:45.935127  <6>[    0.103550] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10399 12:19:45.941734  <6>[    0.103566] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10400 12:19:45.945212  <6>[    0.103613] smp: Brought up 1 node, 8 CPUs

10401 12:19:45.951791  <6>[    0.245037] SMP: Total of 8 processors activated.

10402 12:19:45.955122  <6>[    0.249958] CPU features: detected: 32-bit EL0 Support

10403 12:19:45.964629  <6>[    0.255355] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10404 12:19:45.971284  <6>[    0.264155] CPU features: detected: Common not Private translations

10405 12:19:45.977861  <6>[    0.270671] CPU features: detected: CRC32 instructions

10406 12:19:45.980946  <6>[    0.276023] CPU features: detected: RCpc load-acquire (LDAPR)

10407 12:19:45.987953  <6>[    0.282020] CPU features: detected: LSE atomic instructions

10408 12:19:45.994541  <6>[    0.287838] CPU features: detected: Privileged Access Never

10409 12:19:46.001280  <6>[    0.293618] CPU features: detected: RAS Extension Support

10410 12:19:46.007899  <6>[    0.299226] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10411 12:19:46.011444  <6>[    0.306446] CPU: All CPU(s) started at EL2

10412 12:19:46.017647  <6>[    0.310789] alternatives: applying system-wide alternatives

10413 12:19:46.026998  <6>[    0.321538] devtmpfs: initialized

10414 12:19:46.042754  <6>[    0.330368] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10415 12:19:46.049161  <6>[    0.340332] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10416 12:19:46.055836  <6>[    0.348355] pinctrl core: initialized pinctrl subsystem

10417 12:19:46.059089  <6>[    0.355031] DMI not present or invalid.

10418 12:19:46.066103  <6>[    0.359435] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10419 12:19:46.075920  <6>[    0.366246] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10420 12:19:46.082854  <6>[    0.373832] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10421 12:19:46.092506  <6>[    0.382045] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10422 12:19:46.095613  <6>[    0.390290] audit: initializing netlink subsys (disabled)

10423 12:19:46.106040  <5>[    0.395987] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1

10424 12:19:46.111837  <6>[    0.396694] thermal_sys: Registered thermal governor 'step_wise'

10425 12:19:46.118237  <6>[    0.403955] thermal_sys: Registered thermal governor 'power_allocator'

10426 12:19:46.121740  <6>[    0.410212] cpuidle: using governor menu

10427 12:19:46.128128  <6>[    0.421175] NET: Registered PF_QIPCRTR protocol family

10428 12:19:46.135393  <6>[    0.426673] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10429 12:19:46.138555  <6>[    0.433777] ASID allocator initialised with 32768 entries

10430 12:19:46.145603  <6>[    0.440352] Serial: AMBA PL011 UART driver

10431 12:19:46.154526  <4>[    0.449158] Trying to register duplicate clock ID: 134

10432 12:19:46.209213  <6>[    0.506468] KASLR enabled

10433 12:19:46.223179  <6>[    0.514184] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10434 12:19:46.229685  <6>[    0.521200] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10435 12:19:46.236327  <6>[    0.527689] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10436 12:19:46.242601  <6>[    0.534695] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10437 12:19:46.249522  <6>[    0.541185] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10438 12:19:46.256386  <6>[    0.548191] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10439 12:19:46.262644  <6>[    0.554679] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10440 12:19:46.269515  <6>[    0.561686] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10441 12:19:46.272986  <6>[    0.569186] ACPI: Interpreter disabled.

10442 12:19:46.281500  <6>[    0.575587] iommu: Default domain type: Translated 

10443 12:19:46.288065  <6>[    0.580698] iommu: DMA domain TLB invalidation policy: strict mode 

10444 12:19:46.291774  <5>[    0.587356] SCSI subsystem initialized

10445 12:19:46.298006  <6>[    0.591533] usbcore: registered new interface driver usbfs

10446 12:19:46.304511  <6>[    0.597264] usbcore: registered new interface driver hub

10447 12:19:46.307878  <6>[    0.602816] usbcore: registered new device driver usb

10448 12:19:46.315032  <6>[    0.608914] pps_core: LinuxPPS API ver. 1 registered

10449 12:19:46.324591  <6>[    0.614107] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10450 12:19:46.328102  <6>[    0.623453] PTP clock support registered

10451 12:19:46.331267  <6>[    0.627698] EDAC MC: Ver: 3.0.0

10452 12:19:46.338648  <6>[    0.632852] FPGA manager framework

10453 12:19:46.345269  <6>[    0.636533] Advanced Linux Sound Architecture Driver Initialized.

10454 12:19:46.348070  <6>[    0.643312] vgaarb: loaded

10455 12:19:46.355290  <6>[    0.646515] clocksource: Switched to clocksource arch_sys_counter

10456 12:19:46.358438  <5>[    0.652955] VFS: Disk quotas dquot_6.6.0

10457 12:19:46.365321  <6>[    0.657141] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10458 12:19:46.368116  <6>[    0.664335] pnp: PnP ACPI: disabled

10459 12:19:46.376626  <6>[    0.671021] NET: Registered PF_INET protocol family

10460 12:19:46.386795  <6>[    0.676616] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10461 12:19:46.397683  <6>[    0.688951] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10462 12:19:46.408260  <6>[    0.697770] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10463 12:19:46.414426  <6>[    0.705745] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10464 12:19:46.421294  <6>[    0.714448] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10465 12:19:46.433230  <6>[    0.724208] TCP: Hash tables configured (established 65536 bind 65536)

10466 12:19:46.439952  <6>[    0.731072] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10467 12:19:46.446741  <6>[    0.738271] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10468 12:19:46.453768  <6>[    0.745970] NET: Registered PF_UNIX/PF_LOCAL protocol family

10469 12:19:46.460070  <6>[    0.752120] RPC: Registered named UNIX socket transport module.

10470 12:19:46.463061  <6>[    0.758275] RPC: Registered udp transport module.

10471 12:19:46.470346  <6>[    0.763209] RPC: Registered tcp transport module.

10472 12:19:46.476132  <6>[    0.768141] RPC: Registered tcp NFSv4.1 backchannel transport module.

10473 12:19:46.480047  <6>[    0.774808] PCI: CLS 0 bytes, default 64

10474 12:19:46.483259  <6>[    0.779165] Unpacking initramfs...

10475 12:19:46.507247  <6>[    0.798629] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10476 12:19:46.517841  <6>[    0.807269] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10477 12:19:46.520726  <6>[    0.816115] kvm [1]: IPA Size Limit: 40 bits

10478 12:19:46.527631  <6>[    0.820645] kvm [1]: GICv3: no GICV resource entry

10479 12:19:46.530835  <6>[    0.825667] kvm [1]: disabling GICv2 emulation

10480 12:19:46.537622  <6>[    0.830355] kvm [1]: GIC system register CPU interface enabled

10481 12:19:46.540708  <6>[    0.836515] kvm [1]: vgic interrupt IRQ18

10482 12:19:46.547809  <6>[    0.840867] kvm [1]: VHE mode initialized successfully

10483 12:19:46.554232  <5>[    0.847251] Initialise system trusted keyrings

10484 12:19:46.560787  <6>[    0.852051] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10485 12:19:46.567980  <6>[    0.862127] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10486 12:19:46.574465  <5>[    0.868542] NFS: Registering the id_resolver key type

10487 12:19:46.577946  <5>[    0.873839] Key type id_resolver registered

10488 12:19:46.584281  <5>[    0.878256] Key type id_legacy registered

10489 12:19:46.591533  <6>[    0.882544] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10490 12:19:46.597884  <6>[    0.889468] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10491 12:19:46.604266  <6>[    0.897185] 9p: Installing v9fs 9p2000 file system support

10492 12:19:46.640351  <5>[    0.934807] Key type asymmetric registered

10493 12:19:46.643559  <5>[    0.939135] Asymmetric key parser 'x509' registered

10494 12:19:46.653387  <6>[    0.944271] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10495 12:19:46.657242  <6>[    0.951887] io scheduler mq-deadline registered

10496 12:19:46.660188  <6>[    0.956663] io scheduler kyber registered

10497 12:19:46.679801  <6>[    0.973704] EINJ: ACPI disabled.

10498 12:19:46.712179  <4>[    0.999364] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10499 12:19:46.722161  <4>[    1.009974] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10500 12:19:46.736915  <6>[    1.030697] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10501 12:19:46.744668  <6>[    1.038693] printk: console [ttyS0] disabled

10502 12:19:46.772224  <6>[    1.063339] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10503 12:19:46.778589  <6>[    1.072819] printk: console [ttyS0] enabled

10504 12:19:46.782328  <6>[    1.072819] printk: console [ttyS0] enabled

10505 12:19:46.788390  <6>[    1.081712] printk: bootconsole [mtk8250] disabled

10506 12:19:46.791632  <6>[    1.081712] printk: bootconsole [mtk8250] disabled

10507 12:19:46.798649  <6>[    1.092753] SuperH (H)SCI(F) driver initialized

10508 12:19:46.802032  <6>[    1.098033] msm_serial: driver initialized

10509 12:19:46.815477  <6>[    1.106983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10510 12:19:46.825713  <6>[    1.115526] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10511 12:19:46.832105  <6>[    1.124067] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10512 12:19:46.842550  <6>[    1.132696] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10513 12:19:46.852360  <6>[    1.141404] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10514 12:19:46.858853  <6>[    1.150117] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10515 12:19:46.869605  <6>[    1.158656] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10516 12:19:46.875811  <6>[    1.167449] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10517 12:19:46.885500  <6>[    1.175995] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10518 12:19:46.897173  <6>[    1.191484] loop: module loaded

10519 12:19:46.903488  <6>[    1.197607] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10520 12:19:46.926436  <4>[    1.220852] mtk-pmic-keys: Failed to locate of_node [id: -1]

10521 12:19:46.932922  <6>[    1.227705] megasas: 07.719.03.00-rc1

10522 12:19:46.943142  <6>[    1.237268] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10523 12:19:46.951995  <6>[    1.245933] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10524 12:19:46.968995  <6>[    1.262694] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10525 12:19:47.025266  <6>[    1.312911] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10526 12:19:47.221738  <6>[    1.515883] Freeing initrd memory: 17372K

10527 12:19:47.231766  <6>[    1.526216] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10528 12:19:47.243110  <6>[    1.537402] tun: Universal TUN/TAP device driver, 1.6

10529 12:19:47.246339  <6>[    1.543486] thunder_xcv, ver 1.0

10530 12:19:47.249850  <6>[    1.546994] thunder_bgx, ver 1.0

10531 12:19:47.252770  <6>[    1.550485] nicpf, ver 1.0

10532 12:19:47.263434  <6>[    1.554511] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10533 12:19:47.267051  <6>[    1.561986] hns3: Copyright (c) 2017 Huawei Corporation.

10534 12:19:47.270839  <6>[    1.567574] hclge is initializing

10535 12:19:47.276775  <6>[    1.571156] e1000: Intel(R) PRO/1000 Network Driver

10536 12:19:47.284093  <6>[    1.576285] e1000: Copyright (c) 1999-2006 Intel Corporation.

10537 12:19:47.286956  <6>[    1.582301] e1000e: Intel(R) PRO/1000 Network Driver

10538 12:19:47.293709  <6>[    1.587517] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10539 12:19:47.300117  <6>[    1.593702] igb: Intel(R) Gigabit Ethernet Network Driver

10540 12:19:47.306955  <6>[    1.599352] igb: Copyright (c) 2007-2014 Intel Corporation.

10541 12:19:47.313788  <6>[    1.605188] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10542 12:19:47.316621  <6>[    1.611706] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10543 12:19:47.323946  <6>[    1.618174] sky2: driver version 1.30

10544 12:19:47.330398  <6>[    1.623174] VFIO - User Level meta-driver version: 0.3

10545 12:19:47.336614  <6>[    1.631427] usbcore: registered new interface driver usb-storage

10546 12:19:47.343869  <6>[    1.637872] usbcore: registered new device driver onboard-usb-hub

10547 12:19:47.352449  <6>[    1.647022] mt6397-rtc mt6359-rtc: registered as rtc0

10548 12:19:47.363039  <6>[    1.652482] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:18:12 UTC (1698409092)

10549 12:19:47.366378  <6>[    1.662078] i2c_dev: i2c /dev entries driver

10550 12:19:47.382617  <6>[    1.673839] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10551 12:19:47.402664  <6>[    1.696837] cpu cpu0: EM: created perf domain

10552 12:19:47.405833  <6>[    1.701768] cpu cpu4: EM: created perf domain

10553 12:19:47.413290  <6>[    1.707054] sdhci: Secure Digital Host Controller Interface driver

10554 12:19:47.419370  <6>[    1.713484] sdhci: Copyright(c) Pierre Ossman

10555 12:19:47.425956  <6>[    1.718446] Synopsys Designware Multimedia Card Interface Driver

10556 12:19:47.432517  <6>[    1.725089] sdhci-pltfm: SDHCI platform and OF driver helper

10557 12:19:47.436127  <6>[    1.725145] mmc0: CQHCI version 5.10

10558 12:19:47.442705  <6>[    1.734956] ledtrig-cpu: registered to indicate activity on CPUs

10559 12:19:47.449166  <6>[    1.742077] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10560 12:19:47.455958  <6>[    1.749129] usbcore: registered new interface driver usbhid

10561 12:19:47.459090  <6>[    1.754956] usbhid: USB HID core driver

10562 12:19:47.466013  <6>[    1.759221] spi_master spi0: will run message pump with realtime priority

10563 12:19:47.509545  <6>[    1.797566] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10564 12:19:47.529129  <6>[    1.812864] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10565 12:19:47.536101  <6>[    1.828645] cros-ec-spi spi0.0: Chrome EC device registered

10566 12:19:47.539110  <6>[    1.834729] mmc0: Command Queue Engine enabled

10567 12:19:47.545659  <6>[    1.839460] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10568 12:19:47.552450  <6>[    1.846832] mmcblk0: mmc0:0001 DA4128 116 GiB 

10569 12:19:47.562783  <6>[    1.847936] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10570 12:19:47.565696  <6>[    1.855908]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10571 12:19:47.572421  <6>[    1.861821] NET: Registered PF_PACKET protocol family

10572 12:19:47.579136  <6>[    1.869043] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10573 12:19:47.582304  <6>[    1.872163] 9pnet: Installing 9P2000 support

10574 12:19:47.589137  <6>[    1.878174] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10575 12:19:47.592249  <5>[    1.881843] Key type dns_resolver registered

10576 12:19:47.598789  <6>[    1.887727] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10577 12:19:47.602746  <6>[    1.892012] registered taskstats version 1

10578 12:19:47.608524  <5>[    1.902435] Loading compiled-in X.509 certificates

10579 12:19:47.637321  <4>[    1.924857] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10580 12:19:47.647309  <4>[    1.935507] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10581 12:19:47.654073  <3>[    1.946024] debugfs: File 'uA_load' in directory '/' already present!

10582 12:19:47.660285  <3>[    1.952726] debugfs: File 'min_uV' in directory '/' already present!

10583 12:19:47.667193  <3>[    1.959369] debugfs: File 'max_uV' in directory '/' already present!

10584 12:19:47.673425  <3>[    1.965979] debugfs: File 'constraint_flags' in directory '/' already present!

10585 12:19:47.684423  <3>[    1.975043] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10586 12:19:47.692741  <6>[    1.987146] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10587 12:19:47.699710  <6>[    1.994014] xhci-mtk 11200000.usb: xHCI Host Controller

10588 12:19:47.706007  <6>[    1.999515] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10589 12:19:47.728285  <6>[    2.007359] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10590 12:19:47.728763  <6>[    2.016772] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10591 12:19:47.729976  <6>[    2.022849] xhci-mtk 11200000.usb: xHCI Host Controller

10592 12:19:47.737415  <6>[    2.028330] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10593 12:19:47.742786  <6>[    2.035978] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10594 12:19:47.750091  <6>[    2.043699] hub 1-0:1.0: USB hub found

10595 12:19:47.753277  <6>[    2.047709] hub 1-0:1.0: 1 port detected

10596 12:19:47.760179  <6>[    2.051977] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10597 12:19:47.767106  <6>[    2.060539] hub 2-0:1.0: USB hub found

10598 12:19:47.769914  <6>[    2.064542] hub 2-0:1.0: 1 port detected

10599 12:19:47.777820  <6>[    2.072169] mtk-msdc 11f70000.mmc: Got CD GPIO

10600 12:19:47.788337  <6>[    2.079190] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10601 12:19:47.794911  <6>[    2.087217] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10602 12:19:47.804854  <4>[    2.095121] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10603 12:19:47.815007  <6>[    2.104643] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10604 12:19:47.821291  <6>[    2.112724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10605 12:19:47.827780  <6>[    2.120851] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10606 12:19:47.837692  <6>[    2.128839] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10607 12:19:47.844298  <6>[    2.136661] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10608 12:19:47.854337  <6>[    2.144495] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10609 12:19:47.865241  <6>[    2.155024] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10610 12:19:47.871633  <6>[    2.163413] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10611 12:19:47.881892  <6>[    2.171754] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10612 12:19:47.888437  <6>[    2.180105] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10613 12:19:47.898283  <6>[    2.188444] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10614 12:19:47.904695  <6>[    2.196795] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10615 12:19:47.915074  <6>[    2.205136] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10616 12:19:47.921409  <6>[    2.213485] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10617 12:19:47.931535  <6>[    2.221824] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10618 12:19:47.937942  <6>[    2.230172] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10619 12:19:47.947772  <6>[    2.238511] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10620 12:19:47.954566  <6>[    2.246849] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10621 12:19:47.964604  <6>[    2.255191] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10622 12:19:47.970991  <6>[    2.263529] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10623 12:19:47.981490  <6>[    2.271867] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10624 12:19:47.988010  <6>[    2.280662] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10625 12:19:47.994747  <6>[    2.287854] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10626 12:19:48.001203  <6>[    2.294623] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10627 12:19:48.007997  <6>[    2.301391] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10628 12:19:48.014235  <6>[    2.308331] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10629 12:19:48.024324  <6>[    2.315175] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10630 12:19:48.034426  <6>[    2.324306] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10631 12:19:48.044144  <6>[    2.333427] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10632 12:19:48.054166  <6>[    2.342755] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10633 12:19:48.060864  <6>[    2.352230] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10634 12:19:48.070973  <6>[    2.361698] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10635 12:19:48.080564  <6>[    2.370822] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10636 12:19:48.090749  <6>[    2.380289] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10637 12:19:48.100233  <6>[    2.389410] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10638 12:19:48.110401  <6>[    2.398705] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10639 12:19:48.120015  <6>[    2.408865] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10640 12:19:48.130457  <6>[    2.420368] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10641 12:19:48.136958  <6>[    2.430252] Trying to probe devices needed for running init ...

10642 12:19:48.160098  <6>[    2.451100] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10643 12:19:48.188436  <6>[    2.482717] hub 2-1:1.0: USB hub found

10644 12:19:48.191260  <6>[    2.487218] hub 2-1:1.0: 3 ports detected

10645 12:19:48.311628  <6>[    2.602715] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10646 12:19:48.467096  <6>[    2.761280] hub 1-1:1.0: USB hub found

10647 12:19:48.470582  <6>[    2.765811] hub 1-1:1.0: 4 ports detected

10648 12:19:48.544250  <6>[    2.835055] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10649 12:19:48.791316  <6>[    3.082838] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10650 12:19:48.924102  <6>[    3.218579] hub 1-1.4:1.0: USB hub found

10651 12:19:48.927285  <6>[    3.223217] hub 1-1.4:1.0: 2 ports detected

10652 12:19:49.223415  <6>[    3.514811] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10653 12:19:49.415254  <6>[    3.706826] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10654 12:20:00.436799  <6>[   14.735890] ALSA device list:

10655 12:20:00.443459  <6>[   14.739191]   No soundcards found.

10656 12:20:00.451539  <6>[   14.747289] Freeing unused kernel memory: 8384K

10657 12:20:00.454738  <6>[   14.752323] Run /init as init process

10658 12:20:00.466276  Loading, please wait...

10659 12:20:00.487094  Starting version 247.3-7+deb11u2

10660 12:20:00.728370  <6>[   15.021286] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10661 12:20:00.737322  <6>[   15.033608] remoteproc remoteproc0: scp is available

10662 12:20:00.747992  <6>[   15.044192] remoteproc remoteproc0: powering up scp

10663 12:20:00.758063  <6>[   15.049376] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10664 12:20:00.761373  <6>[   15.057838] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10665 12:20:00.770756  <3>[   15.060869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10666 12:20:00.777402  <3>[   15.071636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10667 12:20:00.787312  <3>[   15.079840] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10668 12:20:00.794443  <6>[   15.083622] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10669 12:20:00.797491  <6>[   15.091416] mc: Linux media interface: v0.10

10670 12:20:00.807524  <6>[   15.095693] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10671 12:20:00.814090  <3>[   15.098592] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10672 12:20:00.823956  <3>[   15.098614] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10673 12:20:00.830669  <3>[   15.098619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10674 12:20:00.840740  <3>[   15.098631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10675 12:20:00.847196  <3>[   15.098635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10676 12:20:00.857167  <3>[   15.098717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10677 12:20:00.863806  <3>[   15.098771] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10678 12:20:00.870870  <3>[   15.098774] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10679 12:20:00.881018  <3>[   15.098777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10680 12:20:00.887217  <3>[   15.098800] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10681 12:20:00.897364  <3>[   15.098802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10682 12:20:00.904333  <3>[   15.098806] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10683 12:20:00.913763  <3>[   15.098809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10684 12:20:00.920523  <3>[   15.098811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10685 12:20:00.930771  <3>[   15.098841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10686 12:20:00.937604  <4>[   15.108528] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10687 12:20:00.944152  <6>[   15.108801] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10688 12:20:00.953848  <4>[   15.135069] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10689 12:20:00.956974  <6>[   15.157886] videodev: Linux video capture interface: v2.00

10690 12:20:00.963770  <6>[   15.169573] usbcore: registered new interface driver r8152

10691 12:20:00.970247  <6>[   15.174912] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10692 12:20:00.980553  <6>[   15.188952] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10693 12:20:00.986887  <6>[   15.190017] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10694 12:20:00.993850  <6>[   15.190025] remoteproc remoteproc0: remote processor scp is now up

10695 12:20:01.000380  <6>[   15.267604] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10696 12:20:01.010214  <6>[   15.275517] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10697 12:20:01.016800  <6>[   15.280493] pci_bus 0000:00: root bus resource [bus 00-ff]

10698 12:20:01.026811  <6>[   15.282779] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10699 12:20:01.036519  <6>[   15.289672] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10700 12:20:01.043282  <6>[   15.295427] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10701 12:20:01.050052  <6>[   15.305446] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10702 12:20:01.060280  <6>[   15.313277] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10703 12:20:01.066869  <6>[   15.314945] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10704 12:20:01.076583  <4>[   15.318791] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10705 12:20:01.079704  <4>[   15.318791] Fallback method does not support PEC.

10706 12:20:01.086235  <6>[   15.328012] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10707 12:20:01.090187  <6>[   15.328595] Bluetooth: Core ver 2.22

10708 12:20:01.097737  <6>[   15.328661] NET: Registered PF_BLUETOOTH protocol family

10709 12:20:01.104215  <6>[   15.328664] Bluetooth: HCI device and connection manager initialized

10710 12:20:01.107397  <6>[   15.328679] Bluetooth: HCI socket layer initialized

10711 12:20:01.114216  <6>[   15.328683] Bluetooth: L2CAP socket layer initialized

10712 12:20:01.120459  <6>[   15.328690] Bluetooth: SCO socket layer initialized

10713 12:20:01.126992  <6>[   15.329870] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10714 12:20:01.134024  <6>[   15.337560] usbcore: registered new interface driver cdc_ether

10715 12:20:01.143465  <4>[   15.341769] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

10716 12:20:01.150814  <4>[   15.341776] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

10717 12:20:01.157198  <6>[   15.343905] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10718 12:20:01.164218  <6>[   15.343997] pci 0000:00:00.0: supports D1 D2

10719 12:20:01.171197  <6>[   15.362921] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10720 12:20:01.177246  <6>[   15.369206] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10721 12:20:01.183946  <6>[   15.369806] usbcore: registered new interface driver r8153_ecm

10722 12:20:01.191183  <6>[   15.370672] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10723 12:20:01.197547  <6>[   15.370843] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10724 12:20:01.203972  <6>[   15.370869] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10725 12:20:01.210939  <6>[   15.370887] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10726 12:20:01.220832  <6>[   15.370902] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10727 12:20:01.224144  <6>[   15.371028] pci 0000:01:00.0: supports D1 D2

10728 12:20:01.230556  <6>[   15.371030] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10729 12:20:01.237303  <6>[   15.383106] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10730 12:20:01.250562  <6>[   15.384458] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10731 12:20:01.256996  <6>[   15.384633] usbcore: registered new interface driver uvcvideo

10732 12:20:01.263709  <6>[   15.390661] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10733 12:20:01.270405  <6>[   15.393030] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10734 12:20:01.276742  <6>[   15.399196] usbcore: registered new interface driver btusb

10735 12:20:01.287067  <4>[   15.399906] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10736 12:20:01.293269  <3>[   15.399923] Bluetooth: hci0: Failed to load firmware file (-2)

10737 12:20:01.299968  <3>[   15.399927] Bluetooth: hci0: Failed to set up firmware (-2)

10738 12:20:01.310294  <4>[   15.399932] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10739 12:20:01.316596  <6>[   15.405170] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10740 12:20:01.326700  <3>[   15.412379] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10741 12:20:01.333218  <6>[   15.415606] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10742 12:20:01.339583  <6>[   15.420784] r8152 2-1.3:1.0 eth0: v1.12.13

10743 12:20:01.346538  <6>[   15.428987] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10744 12:20:01.353229  <6>[   15.449536] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0

10745 12:20:01.359893  <6>[   15.452174] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10746 12:20:01.369675  <3>[   15.464495] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10747 12:20:01.376168  <6>[   15.471202] pci 0000:00:00.0: PCI bridge to [bus 01]

10748 12:20:01.382460  <6>[   15.675962] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10749 12:20:01.389141  <6>[   15.684096] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10750 12:20:01.396319  <6>[   15.691007] pcieport 0000:00:00.0: PME: Signaling with IRQ 283

10751 12:20:01.402594  <6>[   15.697621] pcieport 0000:00:00.0: AER: enabled with IRQ 283

10752 12:20:01.419516  <5>[   15.712521] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10753 12:20:01.441390  <5>[   15.734283] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10754 12:20:01.447753  <4>[   15.741201] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10755 12:20:01.454536  <6>[   15.750098] cfg80211: failed to load regulatory.db

10756 12:20:01.503350  <6>[   15.796166] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10757 12:20:01.509748  <6>[   15.803685] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10758 12:20:01.533975  <6>[   15.830374] mt7921e 0000:01:00.0: ASIC revision: 79610010

10759 12:20:01.640218  <4>[   15.930137] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10760 12:20:01.653677  Begin: Loading essential drivers ... done.

10761 12:20:01.657130  Begin: Running /scripts/init-premount ... done.

10762 12:20:01.663837  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.

10763 12:20:01.673901  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available

10764 12:20:01.677043  Device /sys/class/net/enx00e04c787aaa found

10765 12:20:01.677133  done.

10766 12:20:01.741812  IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP

10767 12:20:01.760340  <4>[   16.049815] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10768 12:20:01.876624  <4>[   16.165862] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10769 12:20:01.996980  <4>[   16.286751] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10770 12:20:02.117630  <4>[   16.406850] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10771 12:20:02.237247  <4>[   16.526704] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10772 12:20:02.357327  <4>[   16.646856] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10773 12:20:02.477088  <4>[   16.766674] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10774 12:20:02.597079  <4>[   16.886705] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10775 12:20:02.716929  <4>[   17.006619] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10776 12:20:02.728615  <6>[   17.025030] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on

10777 12:20:02.828765  <3>[   17.124596] mt7921e 0000:01:00.0: hardware init failed

10778 12:20:02.856707  IP-Config: no response after 2 secs - giving up

10779 12:20:02.897745  IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP

10780 12:20:02.901579  IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):

10781 12:20:02.908150   address: 192.168.201.12   broadcast: 192.168.201.255  netmask: 255.255.255.0   

10782 12:20:02.914480   gateway: 192.168.201.1    dns0     : 192.168.201.1    dns1   : 0.0.0.0         

10783 12:20:02.921059   host   : mt8192-asurada-spherion-r0-cbg-0                                

10784 12:20:02.927903   domain : lava-rack                                                       

10785 12:20:02.931024   rootserver: 192.168.201.1 rootpath: 

10786 12:20:02.934092   filename  : 

10787 12:20:03.045185  done.

10788 12:20:03.048198  Begin: Running /scripts/nfs-bottom ... done.

10789 12:20:03.070062  Begin: Running /scripts/init-bottom ... done.

10790 12:20:04.234863  <6>[   18.531966] NET: Registered PF_INET6 protocol family

10791 12:20:04.242373  <6>[   18.539288] Segment Routing with IPv6

10792 12:20:04.245497  <6>[   18.543282] In-situ OAM (IOAM) with IPv6

10793 12:20:04.362304  <30>[   18.639013] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10794 12:20:04.368352  <30>[   18.663536] systemd[1]: Detected architecture arm64.

10795 12:20:04.386090  

10796 12:20:04.389512  Welcome to Debian GNU/Linux 11 (bullseye)!

10797 12:20:04.389597  

10798 12:20:04.404005  <30>[   18.700714] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10799 12:20:05.196463  <30>[   19.490092] systemd[1]: Queued start job for default target Graphical Interface.

10800 12:20:05.224525  <30>[   19.521474] systemd[1]: Created slice system-getty.slice.

10801 12:20:05.231526  [  OK  ] Created slice system-getty.slice.

10802 12:20:05.247823  <30>[   19.544414] systemd[1]: Created slice system-modprobe.slice.

10803 12:20:05.254029  [  OK  ] Created slice system-modprobe.slice.

10804 12:20:05.271444  <30>[   19.568223] systemd[1]: Created slice system-serial\x2dgetty.slice.

10805 12:20:05.281647  [  OK  ] Created slice system-serial\x2dgetty.slice.

10806 12:20:05.295455  <30>[   19.592023] systemd[1]: Created slice User and Session Slice.

10807 12:20:05.301880  [  OK  ] Created slice User and Session Slice.

10808 12:20:05.322370  <30>[   19.615602] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10809 12:20:05.331952  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10810 12:20:05.349763  <30>[   19.643048] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10811 12:20:05.356115  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10812 12:20:05.376745  <30>[   19.666950] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10813 12:20:05.382954  <30>[   19.679112] systemd[1]: Reached target Local Encrypted Volumes.

10814 12:20:05.389992  [  OK  ] Reached target Local Encrypted Volumes.

10815 12:20:05.406783  <30>[   19.703403] systemd[1]: Reached target Paths.

10816 12:20:05.409668  [  OK  ] Reached target Paths.

10817 12:20:05.425876  <30>[   19.722815] systemd[1]: Reached target Remote File Systems.

10818 12:20:05.432751  [  OK  ] Reached target Remote File Systems.

10819 12:20:05.450646  <30>[   19.747193] systemd[1]: Reached target Slices.

10820 12:20:05.457107  [  OK  ] Reached target Slices.

10821 12:20:05.469859  <30>[   19.766836] systemd[1]: Reached target Swap.

10822 12:20:05.473063  [  OK  ] Reached target Swap.

10823 12:20:05.493804  <30>[   19.787387] systemd[1]: Listening on initctl Compatibility Named Pipe.

10824 12:20:05.500415  [  OK  ] Listening on initctl Compatibility Named Pipe.

10825 12:20:05.507344  <30>[   19.803523] systemd[1]: Listening on Journal Audit Socket.

10826 12:20:05.513613  [  OK  ] Listening on Journal Audit Socket.

10827 12:20:05.531293  <30>[   19.828012] systemd[1]: Listening on Journal Socket (/dev/log).

10828 12:20:05.537613  [  OK  ] Listening on Journal Socket (/dev/log).

10829 12:20:05.554598  <30>[   19.851484] systemd[1]: Listening on Journal Socket.

10830 12:20:05.561243  [  OK  ] Listening on Journal Socket.

10831 12:20:05.579080  <30>[   19.872252] systemd[1]: Listening on Network Service Netlink Socket.

10832 12:20:05.585381  [  OK  ] Listening on Network Service Netlink Socket.

10833 12:20:05.600620  <30>[   19.897135] systemd[1]: Listening on udev Control Socket.

10834 12:20:05.607050  [  OK  ] Listening on udev Control Socket.

10835 12:20:05.622367  <30>[   19.919359] systemd[1]: Listening on udev Kernel Socket.

10836 12:20:05.628858  [  OK  ] Listening on udev Kernel Socket.

10837 12:20:05.669952  <30>[   19.966864] systemd[1]: Mounting Huge Pages File System...

10838 12:20:05.676475           Mounting Huge Pages File System...

10839 12:20:05.693594  <30>[   19.990400] systemd[1]: Mounting POSIX Message Queue File System...

10840 12:20:05.700496           Mounting POSIX Message Queue File System...

10841 12:20:05.725071  <30>[   20.022012] systemd[1]: Mounting Kernel Debug File System...

10842 12:20:05.732080           Mounting Kernel Debug File System...

10843 12:20:05.749680  <30>[   20.043444] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10844 12:20:05.810203  <30>[   20.103772] systemd[1]: Starting Create list of static device nodes for the current kernel...

10845 12:20:05.816694           Starting Create list of st…odes for the current kernel...

10846 12:20:05.839272  <30>[   20.136262] systemd[1]: Starting Load Kernel Module configfs...

10847 12:20:05.846264           Starting Load Kernel Module configfs...

10848 12:20:05.867231  <30>[   20.164299] systemd[1]: Starting Load Kernel Module drm...

10849 12:20:05.874217           Starting Load Kernel Module drm...

10850 12:20:05.894758  <30>[   20.191919] systemd[1]: Starting Load Kernel Module fuse...

10851 12:20:05.901784           Starting Load Kernel Module fuse...

10852 12:20:05.930943  <6>[   20.227860] fuse: init (API version 7.37)

10853 12:20:05.940986  <30>[   20.228769] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10854 12:20:05.987018  <30>[   20.283844] systemd[1]: Starting Journal Service...

10855 12:20:05.993719           Starting Journal Service...

10856 12:20:06.015549  <30>[   20.312601] systemd[1]: Starting Load Kernel Modules...

10857 12:20:06.022228           Starting Load Kernel Modules...

10858 12:20:06.045121  <30>[   20.338637] systemd[1]: Starting Remount Root and Kernel File Systems...

10859 12:20:06.051510           Starting Remount Root and Kernel File Systems...

10860 12:20:06.069132  <30>[   20.366264] systemd[1]: Starting Coldplug All udev Devices...

10861 12:20:06.075571           Starting Coldplug All udev Devices...

10862 12:20:06.097651  <30>[   20.394717] systemd[1]: Mounted Huge Pages File System.

10863 12:20:06.104555  [  OK  ] Mounted Huge Pages File System.

10864 12:20:06.119084  <30>[   20.415154] systemd[1]: Mounted POSIX Message Queue File System.

10865 12:20:06.128648  <3>[   20.421147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10866 12:20:06.135563  [  OK  ] Mounted POSIX Message Queue File System.

10867 12:20:06.150894  <30>[   20.447063] systemd[1]: Mounted Kernel Debug File System.

10868 12:20:06.160863  <3>[   20.452269] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10869 12:20:06.167375  [  OK  ] Mounted Kernel Debug File System.

10870 12:20:06.186114  <30>[   20.480078] systemd[1]: Finished Create list of static device nodes for the current kernel.

10871 12:20:06.196185  [  OK  ] Finished Create list of st… nodes for the current kernel.

10872 12:20:06.208767  <3>[   20.502604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10873 12:20:06.216425  <30>[   20.513021] systemd[1]: modprobe@configfs.service: Succeeded.

10874 12:20:06.223937  <30>[   20.520667] systemd[1]: Finished Load Kernel Module configfs.

10875 12:20:06.230365  [  OK  ] Finished Load Kernel Module configfs.

10876 12:20:06.251490  <3>[   20.545045] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10877 12:20:06.258462  <30>[   20.555281] systemd[1]: modprobe@drm.service: Succeeded.

10878 12:20:06.265255  <30>[   20.562330] systemd[1]: Finished Load Kernel Module drm.

10879 12:20:06.271875  [  OK  ] Finished Load Kernel Module drm.

10880 12:20:06.287389  <30>[   20.583584] systemd[1]: modprobe@fuse.service: Succeeded.

10881 12:20:06.297078  <3>[   20.586989] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10882 12:20:06.300207  <30>[   20.590034] systemd[1]: Finished Load Kernel Module fuse.

10883 12:20:06.307942  [  OK  ] Finished Load Kernel Module fuse.

10884 12:20:06.327898  <3>[   20.621770] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10885 12:20:06.336095  <30>[   20.633031] systemd[1]: Finished Load Kernel Modules.

10886 12:20:06.342687  [  OK  ] Finished Load Kernel Modules.

10887 12:20:06.361434  <3>[   20.655261] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10888 12:20:06.367987  <30>[   20.655897] systemd[1]: Finished Remount Root and Kernel File Systems.

10889 12:20:06.375189  [  OK  ] Finished Remount Root and Kernel File Systems.

10890 12:20:06.392862  <3>[   20.686299] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10891 12:20:06.424836  <3>[   20.718575] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10892 12:20:06.437541  <30>[   20.734775] systemd[1]: Mounting FUSE Control File System...

10893 12:20:06.444501           Mounting FUSE Control File System...

10894 12:20:06.457737  <3>[   20.750854] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10895 12:20:06.471880  <30>[   20.765446] systemd[1]: Mounting Kernel Configuration File System...

10896 12:20:06.475136           Mounting Kernel Configuration File System...

10897 12:20:06.496188  <30>[   20.789791] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.

10898 12:20:06.506773  <30>[   20.799001] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.

10899 12:20:06.535557  <30>[   20.831724] systemd[1]: Starting Load/Save Random Seed...

10900 12:20:06.542265           Starting Load/Save Random Seed...

10901 12:20:06.560485  <30>[   20.857206] systemd[1]: Starting Apply Kernel Variables...

10902 12:20:06.567206           Starting Apply Kernel Variables...

10903 12:20:06.593420  <4>[   20.880121] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent

10904 12:20:06.600350  <30>[   20.882199] systemd[1]: Starting Create System Users...

10905 12:20:06.606284  <3>[   20.895866] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5

10906 12:20:06.613291           Starting Create System Users...

10907 12:20:06.628592  <30>[   20.925448] systemd[1]: Started Journal Service.

10908 12:20:06.634934  [  OK  ] Started Journal Service.

10909 12:20:06.658998  [FAILED] Failed to start Coldplug All udev Devices.

10910 12:20:06.673986  See 'systemctl status systemd-udev-trigger.service' for details.

10911 12:20:06.691056  [  OK  ] Mounted FUSE Control File System.

10912 12:20:06.706897  [  OK  ] Mounted Kernel Configuration File System.

10913 12:20:06.727864  [  OK  ] Finished Load/Save Random Seed.

10914 12:20:06.735613  [  OK  ] Finished Apply Kernel Variables.

10915 12:20:06.751963  [  OK  ] Finished Create System Users.

10916 12:20:06.799151           Starting Flush Journal to Persistent Storage...

10917 12:20:06.818863           Starting Create Static Device Nodes in /dev...

10918 12:20:06.851038  <46>[   21.145019] systemd-journald[300]: Received client request to flush runtime journal.

10919 12:20:06.882844  [  OK  ] Finished Create Static Device Nodes in /dev.

10920 12:20:06.898853  [  OK  ] Reached target Local File Systems (Pre).

10921 12:20:06.914200  [  OK  ] Reached target Local File Systems.

10922 12:20:06.966592           Starting Rule-based Manage…for Device Events and Files...

10923 12:20:08.247906  [  OK  ] Finished Flush Journal to Persistent Storage.

10924 12:20:08.283095           Starting Create Volatile Files and Directories...

10925 12:20:08.311718  [  OK  ] Started Rule-based Manager for Device Events and Files.

10926 12:20:08.391588           Starting Network Service...

10927 12:20:08.500297  [  OK  ] Finished Create Volatile Files and Directories.

10928 12:20:08.555809           Starting Network Time Synchronization...

10929 12:20:08.576226           Starting Update UTMP about System Boot/Shutdown...

10930 12:20:08.729628  [  OK  ] Found device /dev/ttyS0.

10931 12:20:08.758859  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10932 12:20:08.807668           Starting Load/Save Screen …of leds:white:kbd_backlight...

10933 12:20:09.063220  [  OK  ] Reached target Bluetooth.

10934 12:20:09.081117  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10935 12:20:09.130260           Starting Load/Save RF Kill Switch Status...

10936 12:20:09.146372  [  OK  ] Started Network Service.

10937 12:20:09.162472  [  OK  ] Started Load/Save RF Kill Switch Status.

10938 12:20:09.183674  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10939 12:20:09.216996  [  OK  ] Started Network Time Synchronization.

10940 12:20:09.235818  [  OK  ] Reached target System Time Set.

10941 12:20:09.250164  [  OK  ] Reached target System Time Synchronized.

10942 12:20:09.331240           Starting Network Name Resolution...

10943 12:20:09.357955  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10944 12:20:09.384561  [  OK  ] Reached target System Initialization.

10945 12:20:10.052093  [  OK  ] Started Daily apt download activities.

10946 12:20:10.388194  [  OK  ] Started Daily apt upgrade and clean activities.

10947 12:20:10.407937  [  OK  ] Started Periodic ext4 Onli…ata Check for All Filesystems.

10948 12:20:10.427337  [  OK  ] Started Discard unused blocks once a week.

10949 12:20:10.445011  [  OK  ] Started Daily Cleanup of Temporary Directories.

10950 12:20:10.457552  [  OK  ] Reached target Timers.

10951 12:20:10.487987  [  OK  ] Listening on D-Bus System Message Bus Socket.

10952 12:20:10.501611  [  OK  ] Reached target Sockets.

10953 12:20:10.517268  [  OK  ] Reached target Basic System.

10954 12:20:10.578949  [  OK  ] Started D-Bus System Message Bus.

10955 12:20:10.619759           Starting Remove Stale Onli…t4 Metadata Check Snapshots...

10956 12:20:10.732767           Starting User Login Management...

10957 12:20:11.192415  [  OK  ] Finished Remove Stale Onli…ext4 Metadata Check Snapshots.

10958 12:20:11.252782  [  OK  ] Started Network Name Resolution.

10959 12:20:11.261732  [  OK  ] Reached target Network.

10960 12:20:11.280859  [  OK  ] Reached target Host and Network Name Lookups.

10961 12:20:11.326467           Starting Permit User Sessions...

10962 12:20:11.344761  [  OK  ] Started User Login Management.

10963 12:20:11.364124  [  OK  ] Finished Permit User Sessions.

10964 12:20:11.379592  [  OK  ] Started Getty on tty1.

10965 12:20:11.406762  [  OK  ] Started Serial Getty on ttyS0.

10966 12:20:11.427764  [  OK  ] Reached target Login Prompts.

10967 12:20:11.443805  [  OK  ] Reached target Multi-User System.

10968 12:20:11.461644  [  OK  ] Reached target Graphical Interface.

10969 12:20:11.501790           Starting Update UTMP about System Runlevel Changes...

10970 12:20:11.559980  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10971 12:20:11.629613  

10972 12:20:11.630131  

10973 12:20:11.633027  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10974 12:20:11.633473  

10975 12:20:11.636369  debian-bullseye-arm64 login: root (automatic login)

10976 12:20:11.636815  

10977 12:20:11.637248  

10978 12:20:11.980151  Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64

10979 12:20:11.980696  

10980 12:20:11.987440  The programs included with the Debian GNU/Linux system are free software;

10981 12:20:11.993925  the exact distribution terms for each program are described in the

10982 12:20:11.997196  individual files in /usr/share/doc/*/copyright.

10983 12:20:11.997730  

10984 12:20:12.003886  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

10985 12:20:12.006652  permitted by applicable law.

10986 12:20:12.106184  Matched prompt #10: / #
10988 12:20:12.107472  Setting prompt string to ['/ #']
10989 12:20:12.108168  end: 2.2.5.1 login-action (duration 00:00:27) [common]
10991 12:20:12.109411  end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10992 12:20:12.109923  start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10993 12:20:12.110331  Setting prompt string to ['/ #']
10994 12:20:12.110718  Forcing a shell prompt, looking for ['/ #']
10996 12:20:12.161820  / # 

10997 12:20:12.162458  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 12:20:12.162913  Waiting using forced prompt support (timeout 00:02:30)
10999 12:20:12.168135  

11000 12:20:12.169108  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11001 12:20:12.169724  start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11003 12:20:12.271205  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893116/extract-nfsrootfs-fmw_h8hb'

11004 12:20:12.277465  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/11893116/extract-nfsrootfs-fmw_h8hb'

11006 12:20:12.379026  / # export NFS_SERVER_IP='192.168.201.1'

11007 12:20:12.386107  export NFS_SERVER_IP='192.168.201.1'

11008 12:20:12.387082  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11009 12:20:12.387619  end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11010 12:20:12.388148  end: 2 depthcharge-action (duration 00:01:25) [common]
11011 12:20:12.388656  start: 3 lava-test-retry (timeout 00:30:00) [common]
11012 12:20:12.389099  start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11013 12:20:12.389518  Using namespace: common
11015 12:20:12.490636  / # #

11016 12:20:12.491245  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11017 12:20:12.497128  #

11018 12:20:12.497845  Using /lava-11893116
11020 12:20:12.599014  / # export SHELL=/bin/sh

11021 12:20:12.605440  export SHELL=/bin/sh

11023 12:20:12.707042  / # . /lava-11893116/environment

11024 12:20:12.714087  . /lava-11893116/environment

11026 12:20:12.821704  / # /lava-11893116/bin/lava-test-runner /lava-11893116/0

11027 12:20:12.822337  Test shell timeout: 10s (minimum of the action and connection timeout)
11028 12:20:12.828469  /lava-11893116/bin/lava-test-runner /lava-11893116/0

11029 12:20:13.083428  + export TESTRUN_ID=0_lc-compliance

11030 12:20:13.089928  + cd /lava-11893116/0/tests/0_lc-compliance

11031 12:20:13.090568  + cat uuid

11032 12:20:13.096298  + UUID=11893116_1.6.2.3.1

11033 12:20:13.096788  + set +x

11034 12:20:13.102649  <LAVA_SIGNAL_STARTRUN 0_lc-compliance 11893116_1.6.2.3.1>

11035 12:20:13.103551  Received signal: <STARTRUN> 0_lc-compliance 11893116_1.6.2.3.1
11036 12:20:13.104160  Starting test lava.0_lc-compliance (11893116_1.6.2.3.1)
11037 12:20:13.104701  Skipping test definition patterns.
11038 12:20:13.106188  + /usr/bin/lc-compliance-parser.sh

11039 12:20:14.305155  [0:00:28.481567154] [406]  INFO Camera camera_manager.cpp:297 libcamera v0.0.0+1-1f607da9

11040 12:20:14.308380  Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741

11041 12:20:14.322134  [0:00:28.498795692] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11042 12:20:14.383151  [0:00:28.559573077] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11043 12:20:14.385943  [==========] Running 120 tests from 1 test suite.

11044 12:20:14.435203  [0:00:28.611827539] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11045 12:20:14.441955  [----------] Global test environment set-up.

11046 12:20:14.489686  [0:00:28.666241462] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11047 12:20:14.506567  [----------] 120 tests from CaptureTests/SingleStream

11048 12:20:14.566446  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_1

11049 12:20:14.616891  <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>

11050 12:20:14.617184  Received signal: <TESTSET> START CaptureTests/SingleStream
11051 12:20:14.617286  Starting test_set CaptureTests/SingleStream
11052 12:20:14.620107  Camera needs 4 requests, can't test only 1

11053 12:20:14.679905  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11054 12:20:14.753016  

11055 12:20:14.842267  [  SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)

11056 12:20:14.855669  [0:00:29.031583923] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11057 12:20:14.924042  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>

11058 12:20:14.924357  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11060 12:20:14.937432  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_2

11061 12:20:14.978791  Camera needs 4 requests, can't test only 2

11062 12:20:15.033899  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11063 12:20:15.092749  

11064 12:20:15.152189  [  SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (53 ms)

11065 12:20:15.221259  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>

11066 12:20:15.221583  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11068 12:20:15.234978  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_3

11069 12:20:15.277653  Camera needs 4 requests, can't test only 3

11070 12:20:15.322166  [0:00:29.498502231] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11071 12:20:15.344947  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11072 12:20:15.413478  

11073 12:20:15.474862  [  SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (54 ms)

11074 12:20:15.568042  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>

11075 12:20:15.568844  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11077 12:20:15.583742  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_5

11078 12:20:15.632305  [       OK ] CaptureTests/SingleStream.Capture/Raw_5 (365 ms)

11079 12:20:15.716731  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>

11080 12:20:15.717462  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11082 12:20:15.733626  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_8

11083 12:20:15.783742  [       OK ] CaptureTests/SingleStream.Capture/Raw_8 (468 ms)

11084 12:20:15.857007  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>

11085 12:20:15.857299  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11087 12:20:15.867103  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_13

11088 12:20:16.075802  [       OK ] CaptureTests/SingleStream.Capture/Raw_13 (762 ms)

11089 12:20:16.086097  [0:00:30.261124693] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11090 12:20:16.148432  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>

11091 12:20:16.149188  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11093 12:20:16.164231  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_21

11094 12:20:16.977612  [       OK ] CaptureTests/SingleStream.Capture/Raw_21 (901 ms)

11095 12:20:16.987226  [0:00:31.162675231] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11096 12:20:17.076221  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>

11097 12:20:17.076941  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11099 12:20:17.092151  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_34

11100 12:20:18.372435  [       OK ] CaptureTests/SingleStream.Capture/Raw_34 (1395 ms)

11101 12:20:18.382353  [0:00:32.557400231] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11102 12:20:18.465901  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>

11103 12:20:18.466804  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11105 12:20:18.480410  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_55

11106 12:20:20.467455  [       OK ] CaptureTests/SingleStream.Capture/Raw_55 (2095 ms)

11107 12:20:20.477043  [0:00:34.652533693] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11108 12:20:20.558616  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>

11109 12:20:20.559318  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11111 12:20:20.575034  [ RUN      ] CaptureTests/SingleStream.Capture/Raw_89

11112 12:20:23.760483  [       OK ] CaptureTests/SingleStream.Capture/Raw_89 (3293 ms)

11113 12:20:23.770557  [0:00:37.946290462] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11114 12:20:23.822680  [0:00:38.000157232] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11115 12:20:23.856473  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>

11116 12:20:23.857185  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11118 12:20:23.877089  [0:00:38.054636693] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11119 12:20:23.880977  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_1

11120 12:20:23.924199  Camera needs 4 requests, can't test only 1

11121 12:20:23.933558  [0:00:38.109459924] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11122 12:20:24.001045  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11123 12:20:24.070022  

11124 12:20:24.145998  [  SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (54 ms)

11125 12:20:24.229530  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>

11126 12:20:24.230446  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11128 12:20:24.242684  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_2

11129 12:20:24.295288  [0:00:38.472672693] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11130 12:20:24.298526  Camera needs 4 requests, can't test only 2

11131 12:20:24.374942  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11132 12:20:24.443934  

11133 12:20:24.520289  [  SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (54 ms)

11134 12:20:24.604287  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>

11135 12:20:24.604705  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11137 12:20:24.619088  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_3

11138 12:20:24.670929  Camera needs 4 requests, can't test only 3

11139 12:20:24.753397  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11140 12:20:24.763141  [0:00:38.941149462] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11141 12:20:24.830472  

11142 12:20:24.916783  [  SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (55 ms)

11143 12:20:25.003154  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>

11144 12:20:25.003927  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11146 12:20:25.019731  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_5

11147 12:20:25.081903  [       OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (364 ms)

11148 12:20:25.171024  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>

11149 12:20:25.171761  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11151 12:20:25.185877  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_8

11152 12:20:25.240875  [       OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (468 ms)

11153 12:20:25.334011  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>

11154 12:20:25.334746  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11156 12:20:25.348785  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_13

11157 12:20:25.516221  [       OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (761 ms)

11158 12:20:25.529408  [0:00:39.702423693] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11159 12:20:25.613536  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>

11160 12:20:25.614299  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11162 12:20:25.630314  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_21

11163 12:20:26.417560  [       OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (901 ms)

11164 12:20:26.430707  [0:00:40.603506924] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11165 12:20:26.511221  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>

11166 12:20:26.512081  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11168 12:20:26.528896  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_34

11169 12:20:27.813213  [       OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1396 ms)

11170 12:20:27.826175  [0:00:41.999534232] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11171 12:20:27.907171  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>

11172 12:20:27.907928  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11174 12:20:27.923328  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_55

11175 12:20:29.940009  [       OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2127 ms)

11176 12:20:29.952788  [0:00:44.126318001] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11177 12:20:30.027812  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>

11178 12:20:30.028528  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11180 12:20:30.042713  [ RUN      ] CaptureTests/SingleStream.Capture/StillCapture_89

11181 12:20:31.855722  <6>[   46.158767] vpu: disabling

11182 12:20:31.859175  <6>[   46.161877] vproc2: disabling

11183 12:20:31.862519  <6>[   46.165660] vproc1: disabling

11184 12:20:31.866587  <6>[   46.169810] vaud18: disabling

11185 12:20:31.874070  <6>[   46.173632] vsram_others: disabling

11186 12:20:31.877151  <6>[   46.177863] va09: disabling

11187 12:20:31.880681  <6>[   46.181298] vsram_md: disabling

11188 12:20:31.883658  <6>[   46.185128] Vgpu: disabling

11189 12:20:33.232614  [       OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3293 ms)

11190 12:20:33.245678  [0:00:47.420075617] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11191 12:20:33.295933  [0:00:47.474562386] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11192 12:20:33.306840  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>

11193 12:20:33.307126  Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11195 12:20:33.318223  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_1

11196 12:20:33.351199  [0:00:47.530272463] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11197 12:20:33.360562  Camera needs 4 requests, can't test only 1

11198 12:20:33.405863  [0:00:47.584662155] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11199 12:20:33.412424  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11200 12:20:33.457511  

11201 12:20:33.508127  [  SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (55 ms)

11202 12:20:33.565600  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>

11203 12:20:33.565924  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11205 12:20:33.576604  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_2

11206 12:20:33.609512  Camera needs 4 requests, can't test only 2

11207 12:20:33.661602  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11208 12:20:33.709520  

11209 12:20:33.770536  [0:00:47.949490001] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11210 12:20:33.777388  [  SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (56 ms)

11211 12:20:33.835861  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>

11212 12:20:33.836189  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11214 12:20:33.846592  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_3

11215 12:20:33.879584  Camera needs 4 requests, can't test only 3

11216 12:20:33.928105  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11217 12:20:33.971556  

11218 12:20:34.023537  [  SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)

11219 12:20:34.082733  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>

11220 12:20:34.083055  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11222 12:20:34.092689  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_5

11223 12:20:34.131379  [       OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (364 ms)

11224 12:20:34.193743  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>

11225 12:20:34.194045  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11227 12:20:34.205173  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_8

11228 12:20:34.233602  [0:00:48.412689771] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11229 12:20:34.242008  [       OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (464 ms)

11230 12:20:34.300592  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>

11231 12:20:34.300959  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11233 12:20:34.315556  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_13

11234 12:20:34.953575  [       OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (728 ms)

11235 12:20:34.966878  [0:00:49.140888078] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11236 12:20:35.017522  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>

11237 12:20:35.017891  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11239 12:20:35.028294  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_21

11240 12:20:35.851629  [       OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (898 ms)

11241 12:20:35.864582  [0:00:50.039131771] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11242 12:20:35.918078  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>

11243 12:20:35.918410  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11245 12:20:35.928295  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_34

11246 12:20:37.247393  [       OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1396 ms)

11247 12:20:37.260876  [0:00:51.435132078] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11248 12:20:37.310230  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>

11249 12:20:37.310553  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11251 12:20:37.319835  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_55

11252 12:20:39.343449  [       OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2096 ms)

11253 12:20:39.356054  [0:00:53.531244771] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11254 12:20:39.415551  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>

11255 12:20:39.415929  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11257 12:20:39.427065  [ RUN      ] CaptureTests/SingleStream.Capture/VideoRecording_89

11258 12:20:42.572426  [       OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3228 ms)

11259 12:20:42.585470  [0:00:56.760080251] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11260 12:20:42.634212  [0:00:56.813661042] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11261 12:20:42.642143  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>

11262 12:20:42.642426  Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11264 12:20:42.654277  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_1

11265 12:20:42.687738  [0:00:56.867402453] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11266 12:20:42.696380  Camera needs 4 requests, can't test only 1

11267 12:20:42.743197  [0:00:56.922626049] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11268 12:20:42.756903  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11269 12:20:42.811239  

11270 12:20:42.872370  [  SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (53 ms)

11271 12:20:42.940532  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>

11272 12:20:42.940854  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11274 12:20:42.953464  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_2

11275 12:20:42.991479  Camera needs 4 requests, can't test only 2

11276 12:20:43.045617  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11277 12:20:43.109315  [0:00:57.288704884] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11278 12:20:43.109450  

11279 12:20:43.166683  [  SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (53 ms)

11280 12:20:43.229176  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>

11281 12:20:43.229521  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11283 12:20:43.240645  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_3

11284 12:20:43.277859  Camera needs 4 requests, can't test only 3

11285 12:20:43.332238  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11286 12:20:43.382053  

11287 12:20:43.442831  [  SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (55 ms)

11288 12:20:43.509627  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>

11289 12:20:43.509956  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11291 12:20:43.521782  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_5

11292 12:20:43.573919  [0:00:57.752808300] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11293 12:20:43.577121  [       OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (366 ms)

11294 12:20:43.632776  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>

11295 12:20:43.633096  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11297 12:20:43.643172  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_8

11298 12:20:43.682169  [       OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (465 ms)

11299 12:20:43.749827  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>

11300 12:20:43.750158  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11302 12:20:43.760834  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_13

11303 12:20:44.261702  [       OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (696 ms)

11304 12:20:44.272235  [0:00:58.449165930] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11305 12:20:44.327336  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>

11306 12:20:44.327672  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11308 12:20:44.339733  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_21

11309 12:20:45.257790  [       OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (995 ms)

11310 12:20:45.270618  [0:00:59.444468195] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11311 12:20:45.325172  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>

11312 12:20:45.325495  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11314 12:20:45.335312  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_34

11315 12:20:46.687168  [       OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1429 ms)

11316 12:20:46.700128  [0:01:00.874014867] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11317 12:20:46.751899  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>

11318 12:20:46.752228  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11320 12:20:46.762035  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_55

11321 12:20:48.816058  [       OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2129 ms)

11322 12:20:48.828893  [0:01:03.002498233] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11323 12:20:48.879544  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>

11324 12:20:48.879872  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11326 12:20:48.890991  [ RUN      ] CaptureTests/SingleStream.Capture/Viewfinder_89

11327 12:20:52.108516  [       OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3292 ms)

11328 12:20:52.121971  [0:01:06.294559838] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11329 12:20:52.173949  [0:01:06.351277358] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11330 12:20:52.177476  Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11332 12:20:52.180418  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>

11333 12:20:52.187581  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_1

11334 12:20:52.229683  [0:01:06.406878529] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11335 12:20:52.232604  Camera needs 4 requests, can't test only 1

11336 12:20:52.284181  [0:01:06.461127944] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11337 12:20:52.287270  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11338 12:20:52.328612  

11339 12:20:52.389560  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (57 ms)

11340 12:20:52.447946  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>

11341 12:20:52.448250  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11343 12:20:52.461818  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_2

11344 12:20:52.501554  Camera needs 4 requests, can't test only 2

11345 12:20:52.565035  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11346 12:20:52.617315  

11347 12:20:52.680743  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (56 ms)

11348 12:20:52.745860  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>

11349 12:20:52.746157  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11351 12:20:52.754562  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_3

11352 12:20:52.793167  Camera needs 4 requests, can't test only 3

11353 12:20:52.849212  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11354 12:20:52.901543  

11355 12:20:52.963924  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (54 ms)

11356 12:20:53.026571  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>

11357 12:20:53.026860  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11359 12:20:53.036578  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_5

11360 12:20:53.459236  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1183 ms)

11361 12:20:53.471839  [0:01:07.644466805] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11362 12:20:53.524480  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>

11363 12:20:53.524757  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11365 12:20:53.535279  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_8

11366 12:20:54.847479  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1389 ms)

11367 12:20:54.860828  [0:01:09.033019814] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11368 12:20:54.915523  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>

11369 12:20:54.915886  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11371 12:20:54.925421  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_13

11372 12:20:56.931407  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2083 ms)

11373 12:20:56.944496  [0:01:11.116564798] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11374 12:20:56.996799  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>

11375 12:20:56.997091  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11377 12:20:57.007390  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_21

11378 12:20:59.619120  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2687 ms)

11379 12:20:59.632309  [0:01:13.803833120] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11380 12:20:59.687831  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>

11381 12:20:59.688159  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11383 12:20:59.698805  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_34

11384 12:21:03.867477  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4248 ms)

11385 12:21:03.880612  [0:01:18.052475319] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11386 12:21:03.925847  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>

11387 12:21:03.926173  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11389 12:21:03.936231  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_55

11390 12:21:10.246770  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6380 ms)

11391 12:21:10.259929  [0:01:24.432244496] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11392 12:21:10.312971  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>

11393 12:21:10.313386  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11395 12:21:10.322875  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Raw_89

11396 12:21:19.992511  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9745 ms)

11397 12:21:20.005479  [0:01:34.177257144] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11398 12:21:20.053499  [0:01:34.230725212] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11399 12:21:20.082983  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>

11400 12:21:20.083760  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11402 12:21:20.098431  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1

11403 12:21:20.111504  [0:01:34.285694453] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11404 12:21:20.148688  Camera needs 4 requests, can't test only 1

11405 12:21:20.164571  [0:01:34.341474201] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11406 12:21:20.228081  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11407 12:21:20.303611  

11408 12:21:20.392650  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (54 ms)

11409 12:21:20.488771  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>

11410 12:21:20.489580  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11412 12:21:20.502162  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2

11413 12:21:20.562007  Camera needs 4 requests, can't test only 2

11414 12:21:20.642242  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11415 12:21:20.718254  

11416 12:21:20.801518  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (54 ms)

11417 12:21:20.873695  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>

11418 12:21:20.873985  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11420 12:21:20.882862  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3

11421 12:21:20.926085  Camera needs 4 requests, can't test only 3

11422 12:21:20.980842  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11423 12:21:21.046950  

11424 12:21:21.126944  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (56 ms)

11425 12:21:21.201757  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>

11426 12:21:21.202084  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11428 12:21:21.209317  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5

11429 12:21:21.280842  [       OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1122 ms)

11430 12:21:21.290815  [0:01:35.463537652] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11431 12:21:21.356145  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>

11432 12:21:21.356470  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11434 12:21:21.364475  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8

11435 12:21:22.671114  [       OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1390 ms)

11436 12:21:22.680885  [0:01:36.854153283] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11437 12:21:22.742182  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>

11438 12:21:22.742507  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11440 12:21:22.750166  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13

11441 12:21:24.818030  [       OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2147 ms)

11442 12:21:24.827909  [0:01:39.000885924] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11443 12:21:24.884080  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>

11444 12:21:24.884352  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11446 12:21:24.893527  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21

11447 12:21:27.639342  [       OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2821 ms)

11448 12:21:27.648912  [0:01:41.822390944] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11449 12:21:27.717995  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>

11450 12:21:27.718274  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11452 12:21:27.725536  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34

11453 12:21:31.919684  [       OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4281 ms)

11454 12:21:31.929418  [0:01:46.103272145] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11455 12:21:31.982515  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>

11456 12:21:31.982829  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11458 12:21:31.992056  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55

11459 12:21:38.201391  [       OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6282 ms)

11460 12:21:38.210828  [0:01:52.384867312] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11461 12:21:38.277551  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>

11462 12:21:38.277845  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11464 12:21:38.285419  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89

11465 12:21:47.913214  [       OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9712 ms)

11466 12:21:47.923049  [0:02:02.097528213] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11467 12:21:47.971729  [0:02:02.151470245] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11468 12:21:47.978486  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>

11469 12:21:47.978777  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11471 12:21:47.988999  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1

11472 12:21:48.027722  [0:02:02.207481631] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11473 12:21:48.030986  Camera needs 4 requests, can't test only 1

11474 12:21:48.083935  [0:02:02.263449946] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11475 12:21:48.090223  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11476 12:21:48.146504  

11477 12:21:48.215058  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (54 ms)

11478 12:21:48.288670  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>

11479 12:21:48.288995  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11481 12:21:48.296401  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2

11482 12:21:48.340514  Camera needs 4 requests, can't test only 2

11483 12:21:48.406526  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11484 12:21:48.471036  

11485 12:21:48.531201  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (55 ms)

11486 12:21:48.593379  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>

11487 12:21:48.593806  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11489 12:21:48.600477  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3

11490 12:21:48.640905  Camera needs 4 requests, can't test only 3

11491 12:21:48.699701  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11492 12:21:48.758638  

11493 12:21:48.820776  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (56 ms)

11494 12:21:48.879810  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>

11495 12:21:48.880161  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11497 12:21:48.889079  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5

11498 12:21:49.233760  [       OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1155 ms)

11499 12:21:49.243205  [0:02:03.418396884] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11500 12:21:49.304820  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>

11501 12:21:49.305147  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11503 12:21:49.316056  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8

11504 12:21:50.655632  [       OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1422 ms)

11505 12:21:50.665931  [0:02:04.840557706] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11506 12:21:50.730714  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>

11507 12:21:50.731062  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11509 12:21:50.739489  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13

11510 12:21:52.833506  [       OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2177 ms)

11511 12:21:52.843423  [0:02:07.018100380] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11512 12:21:52.905233  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>

11513 12:21:52.905587  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11515 12:21:52.915980  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21

11516 12:21:55.520130  [       OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2686 ms)

11517 12:21:55.529981  [0:02:09.704580625] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11518 12:21:55.589418  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>

11519 12:21:55.589726  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11521 12:21:55.599514  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34

11522 12:21:59.769153  [       OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4250 ms)

11523 12:21:59.779087  [0:02:13.954231397] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11524 12:21:59.839076  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>

11525 12:21:59.839388  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11527 12:21:59.850835  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55

11528 12:22:06.385969  [       OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6616 ms)

11529 12:22:06.396130  [0:02:20.571056950] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11530 12:22:06.486640  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>

11531 12:22:06.486786  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89

11532 12:22:06.487045  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11534 12:22:16.099055  [       OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9714 ms)

11535 12:22:16.109111  [0:02:30.284426571] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11536 12:22:16.160100  [0:02:30.339978893] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11537 12:22:16.166389  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>

11538 12:22:16.166653  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11540 12:22:16.172746  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1

11541 12:22:16.214033  [0:02:30.394226909] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11542 12:22:16.217154  Camera needs 4 requests, can't test only 1

11543 12:22:16.267378  [0:02:30.447852271] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11544 12:22:16.273793  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11545 12:22:16.322598  

11546 12:22:16.383530  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (55 ms)

11547 12:22:16.450690  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>

11548 12:22:16.450995  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11550 12:22:16.458181  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2

11551 12:22:16.494470  Camera needs 4 requests, can't test only 2

11552 12:22:16.547212  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11553 12:22:16.595921  

11554 12:22:16.663372  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (56 ms)

11555 12:22:16.723059  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11557 12:22:16.726724  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>

11558 12:22:16.733759  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3

11559 12:22:16.771753  Camera needs 4 requests, can't test only 3

11560 12:22:16.825824  ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped

11561 12:22:16.871480  

11562 12:22:16.936978  [  SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (53 ms)

11563 12:22:16.998125  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>

11564 12:22:16.998421  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11566 12:22:17.006512  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5

11567 12:22:17.354921  [0:02:31.535109569] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11568 12:22:17.361162  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1087 ms)

11569 12:22:17.416373  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>

11570 12:22:17.416655  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11572 12:22:17.425186  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8

11573 12:22:18.747161  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1397 ms)

11574 12:22:18.756682  [0:02:32.934225094] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11575 12:22:18.816260  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>

11576 12:22:18.816552  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11578 12:22:18.825536  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13

11579 12:22:20.929044  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2182 ms)

11580 12:22:20.938930  [0:02:35.116083510] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11581 12:22:20.999052  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>

11582 12:22:20.999349  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11584 12:22:21.008645  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21

11585 12:22:23.616170  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2688 ms)

11586 12:22:23.626221  [0:02:37.803789686] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11587 12:22:23.682392  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>

11588 12:22:23.682679  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11590 12:22:23.689933  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34

11591 12:22:27.835761  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4218 ms)

11592 12:22:27.845869  [0:02:42.023969520] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11593 12:22:27.906747  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>

11594 12:22:27.907059  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11596 12:22:27.915998  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55

11597 12:22:34.117769  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6280 ms)

11598 12:22:34.127132  [0:02:48.306024118] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11599 12:22:34.185244  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>

11600 12:22:34.185538  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11602 12:22:34.192921  [ RUN      ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89

11603 12:22:43.834124  [       OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9715 ms)

11604 12:22:43.844001  [0:02:58.023250630] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11605 12:22:43.901143  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>

11606 12:22:43.901457  Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11608 12:22:43.908102  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_1

11609 12:22:44.193398  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (361 ms)

11610 12:22:44.203775  [0:02:58.386218635] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11611 12:22:44.257822  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>

11612 12:22:44.258142  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11614 12:22:44.270408  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_2

11615 12:22:44.590289  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (394 ms)

11616 12:22:44.602911  [0:02:58.782219144] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11617 12:22:44.659161  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>

11618 12:22:44.659502  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11620 12:22:44.670857  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_3

11621 12:22:44.892360  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (302 ms)

11622 12:22:44.902378  [0:02:59.083904569] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11623 12:22:44.963348  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>

11624 12:22:44.963694  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11626 12:22:44.973999  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_5

11627 12:22:45.265847  [0:02:59.447824680] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11628 12:22:45.271986  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (366 ms)

11629 12:22:45.329023  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>

11630 12:22:45.329382  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11632 12:22:45.340221  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_8

11633 12:22:45.795201  [0:02:59.977276988] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11634 12:22:45.798342  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (529 ms)

11635 12:22:45.860518  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>

11636 12:22:45.860815  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11638 12:22:45.871757  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_13

11639 12:22:46.492077  [0:03:00.674115172] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11640 12:22:46.498203  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (697 ms)

11641 12:22:46.554686  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>

11642 12:22:46.555009  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11644 12:22:46.566306  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_21

11645 12:22:47.487900  [0:03:01.670205835] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11646 12:22:47.494263  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (996 ms)

11647 12:22:47.542585  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>

11648 12:22:47.542930  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11650 12:22:47.551081  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_34

11651 12:22:48.947877  [0:03:03.130447806] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11652 12:22:48.954505  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1460 ms)

11653 12:22:49.017739  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>

11654 12:22:49.018038  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11656 12:22:49.029894  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_55

11657 12:22:51.043426  [0:03:05.226255098] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11658 12:22:51.050306  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2096 ms)

11659 12:22:51.104736  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>

11660 12:22:51.105026  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11662 12:22:51.115258  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Raw_89

11663 12:22:54.243460  [0:03:08.426313488] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11664 12:22:54.250128  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3200 ms)

11665 12:22:54.304534  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>

11666 12:22:54.304911  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11668 12:22:54.315973  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1

11669 12:22:54.605224  [0:03:08.788310997] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11670 12:22:54.612132  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (362 ms)

11671 12:22:54.675741  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>

11672 12:22:54.676060  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11674 12:22:54.685021  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2

11675 12:22:54.963354  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (362 ms)

11676 12:22:54.973252  [0:03:09.149650797] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11677 12:22:55.031515  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>

11678 12:22:55.031882  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11680 12:22:55.039015  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3

11681 12:22:55.263483  [0:03:09.446583367] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11682 12:22:55.270274  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (296 ms)

11683 12:22:55.324864  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>

11684 12:22:55.325182  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11686 12:22:55.332041  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5

11687 12:22:55.628246  [0:03:09.811291186] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11688 12:22:55.634925  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (365 ms)

11689 12:22:55.691732  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11691 12:22:55.694756  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>

11692 12:22:55.701524  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8

11693 12:22:56.096151  [0:03:10.279150502] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11694 12:22:56.102619  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (468 ms)

11695 12:22:56.164253  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>

11696 12:22:56.164577  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11698 12:22:56.171101  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13

11699 12:22:56.858268  [0:03:11.041003610] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11700 12:22:56.864437  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (762 ms)

11701 12:22:56.924659  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>

11702 12:22:56.925017  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11704 12:22:56.932136  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21

11705 12:22:57.758698  [0:03:11.941946725] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11706 12:22:57.765642  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (901 ms)

11707 12:22:57.826956  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>

11708 12:22:57.827358  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11710 12:22:57.834747  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34

11711 12:22:59.154701  [0:03:13.337872013] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11712 12:22:59.161509  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1396 ms)

11713 12:22:59.218143  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>

11714 12:22:59.218448  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11716 12:22:59.226207  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55

11717 12:23:01.250624  [0:03:15.434059374] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11718 12:23:01.257209  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2096 ms)

11719 12:23:01.316795  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>

11720 12:23:01.317103  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11722 12:23:01.323362  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89

11723 12:23:04.543885  [0:03:18.727801727] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11724 12:23:04.550731  [       OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3294 ms)

11725 12:23:04.612815  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>

11726 12:23:04.613209  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11728 12:23:04.619506  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1

11729 12:23:04.841197  [0:03:19.024758863] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11730 12:23:04.847610  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (296 ms)

11731 12:23:04.911517  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>

11732 12:23:04.911866  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11734 12:23:04.921433  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2

11735 12:23:05.139465  [0:03:19.323362466] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11736 12:23:05.145818  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (298 ms)

11737 12:23:05.200812  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>

11738 12:23:05.201113  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11740 12:23:05.207627  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3

11741 12:23:05.437636  [0:03:19.621709844] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11742 12:23:05.444371  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (298 ms)

11743 12:23:05.504479  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>

11744 12:23:05.504812  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11746 12:23:05.512613  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5

11747 12:23:05.802599  [0:03:19.986795930] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11748 12:23:05.809575  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (365 ms)

11749 12:23:05.868409  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>

11750 12:23:05.868730  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11752 12:23:05.874931  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8

11753 12:23:06.270947  [0:03:20.454852366] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11754 12:23:06.277247  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (468 ms)

11755 12:23:06.333515  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>

11756 12:23:06.333859  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11758 12:23:06.341341  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13

11759 12:23:07.032059  [0:03:21.216146573] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11760 12:23:07.039102  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (761 ms)

11761 12:23:07.097660  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>

11762 12:23:07.097983  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11764 12:23:07.106704  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21

11765 12:23:07.933051  [0:03:22.117243241] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11766 12:23:07.939882  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (901 ms)

11767 12:23:07.995598  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>

11768 12:23:07.995988  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11770 12:23:08.005406  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34

11771 12:23:09.329099  [0:03:23.513489954] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11772 12:23:09.336283  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1396 ms)

11773 12:23:09.393696  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>

11774 12:23:09.394007  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11776 12:23:09.401011  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55

11777 12:23:11.424765  [0:03:25.609014653] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11778 12:23:11.431214  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2096 ms)

11779 12:23:11.486807  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>

11780 12:23:11.487116  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11782 12:23:11.494960  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89

11783 12:23:14.686101  [0:03:28.870817553] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11784 12:23:14.692451  [       OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3261 ms)

11785 12:23:14.745904  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>

11786 12:23:14.746241  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11788 12:23:14.752380  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1

11789 12:23:15.014365  [0:03:29.198757222] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11790 12:23:15.020647  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (327 ms)

11791 12:23:15.068639  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>

11792 12:23:15.068984  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11794 12:23:15.078238  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2

11795 12:23:15.278944  [0:03:29.463749731] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11796 12:23:15.285331  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (265 ms)

11797 12:23:15.339840  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11799 12:23:15.343250  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>

11800 12:23:15.349861  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3

11801 12:23:15.577321  [0:03:29.762205507] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11802 12:23:15.583847  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (298 ms)

11803 12:23:15.636119  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11805 12:23:15.639264  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>

11806 12:23:15.646670  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5

11807 12:23:15.941887  [0:03:30.126916043] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11808 12:23:15.948993  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (365 ms)

11809 12:23:15.995250  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11811 12:23:15.998484  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>

11812 12:23:16.004865  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8

11813 12:23:16.410171  [0:03:30.594800214] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11814 12:23:16.416569  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (468 ms)

11815 12:23:16.466515  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11817 12:23:16.469624  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>

11818 12:23:16.476223  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13

11819 12:23:17.172193  [0:03:31.356705504] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11820 12:23:17.178342  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (761 ms)

11821 12:23:17.231774  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11823 12:23:17.235034  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>

11824 12:23:17.241906  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21

11825 12:23:18.072803  [0:03:32.257950328] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11826 12:23:18.079398  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (901 ms)

11827 12:23:18.127419  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11829 12:23:18.130555  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>

11830 12:23:18.138547  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34

11831 12:23:19.468776  [0:03:33.653910058] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11832 12:23:19.475191  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1396 ms)

11833 12:23:19.529743  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11835 12:23:19.532403  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>

11836 12:23:19.539512  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55

11837 12:23:21.597898  [0:03:35.783195482] [406]  INFO Camera camera.cpp:1027 configuring streams: (0) 1280x720-MJPEG

11838 12:23:21.604545  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2129 ms)

11839 12:23:21.656887  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11841 12:23:21.659873  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>

11842 12:23:21.668139  [ RUN      ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89

11843 12:23:24.793389  [       OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3200 ms)

11844 12:23:24.859721  Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11846 12:23:24.862640  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>

11847 12:23:24.870776  [----------] 120 tests from CaptureTests/SingleStream (190485 ms total)

11848 12:23:24.914395  

11849 12:23:24.968305  [----------] Global test environment tear-down

11850 12:23:25.022226  [==========] 120 tests from 1 test suite ran. (190485 ms total)

11851 12:23:25.075317  <LAVA_SIGNAL_TESTSET STOP>

11852 12:23:25.075672  Received signal: <TESTSET> STOP
11853 12:23:25.075786  Closing test_set CaptureTests/SingleStream
11854 12:23:25.082159  + set +x

11855 12:23:25.085687  <LAVA_SIGNAL_ENDRUN 0_lc-compliance 11893116_1.6.2.3.1>

11856 12:23:25.085971  Received signal: <ENDRUN> 0_lc-compliance 11893116_1.6.2.3.1
11857 12:23:25.086065  Ending use of test pattern.
11858 12:23:25.086134  Ending test lava.0_lc-compliance (11893116_1.6.2.3.1), duration 191.98
11860 12:23:25.088881  <LAVA_TEST_RUNNER EXIT>

11861 12:23:25.089130  ok: lava_test_shell seems to have completed
11862 12:23:25.091430  Capture/Raw_1:
  result: skip
  set: CaptureTests/SingleStream
Capture/Raw_13:
  result: pass
  set: CaptureTests/SingleStream
Capture/Raw_2:
  result: skip
  set: CaptureTests/SingleStream
Capture/Raw_21:
  result: pass
  set: CaptureTests/SingleStream
Capture/Raw_3:
  result: skip
  set: CaptureTests/SingleStream
Capture/Raw_34:
  result: pass
  set: CaptureTests/SingleStream
Capture/Raw_5:
  result: pass
  set: CaptureTests/SingleStream
Capture/Raw_55:
  result: pass
  set: CaptureTests/SingleStream
Capture/Raw_8:
  result: pass
  set: CaptureTests/SingleStream
Capture/Raw_89:
  result: pass
  set: CaptureTests/SingleStream
Capture/StillCapture_1:
  result: skip
  set: CaptureTests/SingleStream
Capture/StillCapture_13:
  result: pass
  set: CaptureTests/SingleStream
Capture/StillCapture_2:
  result: skip
  set: CaptureTests/SingleStream
Capture/StillCapture_21:
  result: pass
  set: CaptureTests/SingleStream
Capture/StillCapture_3:
  result: skip
  set: CaptureTests/SingleStream
Capture/StillCapture_34:
  result: pass
  set: CaptureTests/SingleStream
Capture/StillCapture_5:
  result: pass
  set: CaptureTests/SingleStream
Capture/StillCapture_55:
  result: pass
  set: CaptureTests/SingleStream
Capture/StillCapture_8:
  result: pass
  set: CaptureTests/SingleStream
Capture/StillCapture_89:
  result: pass
  set: CaptureTests/SingleStream
Capture/VideoRecording_1:
  result: skip
  set: CaptureTests/SingleStream
Capture/VideoRecording_13:
  result: pass
  set: CaptureTests/SingleStream
Capture/VideoRecording_2:
  result: skip
  set: CaptureTests/SingleStream
Capture/VideoRecording_21:
  result: pass
  set: CaptureTests/SingleStream
Capture/VideoRecording_3:
  result: skip
  set: CaptureTests/SingleStream
Capture/VideoRecording_34:
  result: pass
  set: CaptureTests/SingleStream
Capture/VideoRecording_5:
  result: pass
  set: CaptureTests/SingleStream
Capture/VideoRecording_55:
  result: pass
  set: CaptureTests/SingleStream
Capture/VideoRecording_8:
  result: pass
  set: CaptureTests/SingleStream
Capture/VideoRecording_89:
  result: pass
  set: CaptureTests/SingleStream
Capture/Viewfinder_1:
  result: skip
  set: CaptureTests/SingleStream
Capture/Viewfinder_13:
  result: pass
  set: CaptureTests/SingleStream
Capture/Viewfinder_2:
  result: skip
  set: CaptureTests/SingleStream
Capture/Viewfinder_21:
  result: pass
  set: CaptureTests/SingleStream
Capture/Viewfinder_3:
  result: skip
  set: CaptureTests/SingleStream
Capture/Viewfinder_34:
  result: pass
  set: CaptureTests/SingleStream
Capture/Viewfinder_5:
  result: pass
  set: CaptureTests/SingleStream
Capture/Viewfinder_55:
  result: pass
  set: CaptureTests/SingleStream
Capture/Viewfinder_8:
  result: pass
  set: CaptureTests/SingleStream
Capture/Viewfinder_89:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
  result: skip
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
  result: pass
  set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
  result: pass
  set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
  result: pass
  set: CaptureTests/SingleStream

11863 12:23:25.091617  end: 3.1 lava-test-shell (duration 00:03:13) [common]
11864 12:23:25.091733  end: 3 lava-test-retry (duration 00:03:13) [common]
11865 12:23:25.091829  start: 4 finalize (timeout 00:10:00) [common]
11866 12:23:25.091925  start: 4.1 power-off (timeout 00:00:30) [common]
11867 12:23:25.092074  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11868 12:23:25.169729  >> Command sent successfully.

11869 12:23:25.172552  Returned 0 in 0 seconds
11870 12:23:25.272998  end: 4.1 power-off (duration 00:00:00) [common]
11872 12:23:25.273412  start: 4.2 read-feedback (timeout 00:10:00) [common]
11873 12:23:25.273680  Listened to connection for namespace 'common' for up to 1s
11874 12:23:26.274676  Finalising connection for namespace 'common'
11875 12:23:26.274888  Disconnecting from shell: Finalise
11876 12:23:26.274971  / # 
11877 12:23:26.375271  end: 4.2 read-feedback (duration 00:00:01) [common]
11878 12:23:26.375459  end: 4 finalize (duration 00:00:01) [common]
11879 12:23:26.375576  Cleaning after the job
11880 12:23:26.375730  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/ramdisk
11881 12:23:26.378402  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/kernel
11882 12:23:26.391532  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/dtb
11883 12:23:26.391811  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/nfsrootfs
11884 12:23:26.452511  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893116/tftp-deploy-xlfix1x7/modules
11885 12:23:26.460282  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893116
11886 12:23:26.794386  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893116
11887 12:23:26.794569  Job finished correctly