Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 103
- Kernel Errors: 274
- Errors: 0
- Boot result: PASS
1 12:16:19.747084 lava-dispatcher, installed at version: 2023.08
2 12:16:19.747355 start: 0 validate
3 12:16:19.747505 Start time: 2023-10-27 12:16:19.747497+00:00 (UTC)
4 12:16:19.747634 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:16:19.747777 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:16:20.016607 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:16:20.017029 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:16:20.285276 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:16:20.286073 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:17:12.727440 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:17:12.727672 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:17:13.251969 validate duration: 53.50
14 12:17:13.252249 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:17:13.252346 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:17:13.252432 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:17:13.252558 Not decompressing ramdisk as can be used compressed.
18 12:17:13.252645 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 12:17:13.252708 saving as /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/ramdisk/rootfs.cpio.gz
20 12:17:13.252771 total size: 84918747 (80 MB)
21 12:17:16.127214 progress 0 % (0 MB)
22 12:17:16.149866 progress 5 % (4 MB)
23 12:17:16.172512 progress 10 % (8 MB)
24 12:17:16.194785 progress 15 % (12 MB)
25 12:17:16.217001 progress 20 % (16 MB)
26 12:17:16.239371 progress 25 % (20 MB)
27 12:17:16.261711 progress 30 % (24 MB)
28 12:17:16.284089 progress 35 % (28 MB)
29 12:17:16.306124 progress 40 % (32 MB)
30 12:17:16.328223 progress 45 % (36 MB)
31 12:17:16.350314 progress 50 % (40 MB)
32 12:17:16.373431 progress 55 % (44 MB)
33 12:17:16.396564 progress 60 % (48 MB)
34 12:17:16.418474 progress 65 % (52 MB)
35 12:17:16.440366 progress 70 % (56 MB)
36 12:17:16.462254 progress 75 % (60 MB)
37 12:17:16.485298 progress 80 % (64 MB)
38 12:17:16.507714 progress 85 % (68 MB)
39 12:17:16.530296 progress 90 % (72 MB)
40 12:17:16.552459 progress 95 % (76 MB)
41 12:17:16.574397 progress 100 % (80 MB)
42 12:17:16.574699 80 MB downloaded in 3.32 s (24.38 MB/s)
43 12:17:16.574876 end: 1.1.1 http-download (duration 00:00:03) [common]
45 12:17:16.575119 end: 1.1 download-retry (duration 00:00:03) [common]
46 12:17:16.575205 start: 1.2 download-retry (timeout 00:09:57) [common]
47 12:17:16.575332 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 12:17:16.575498 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:17:16.575572 saving as /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/kernel/Image
50 12:17:16.575633 total size: 49236480 (46 MB)
51 12:17:16.575711 No compression specified
52 12:17:16.576982 progress 0 % (0 MB)
53 12:17:16.590514 progress 5 % (2 MB)
54 12:17:16.603770 progress 10 % (4 MB)
55 12:17:16.617393 progress 15 % (7 MB)
56 12:17:16.630694 progress 20 % (9 MB)
57 12:17:16.644001 progress 25 % (11 MB)
58 12:17:16.657070 progress 30 % (14 MB)
59 12:17:16.670253 progress 35 % (16 MB)
60 12:17:16.683858 progress 40 % (18 MB)
61 12:17:16.697121 progress 45 % (21 MB)
62 12:17:16.710332 progress 50 % (23 MB)
63 12:17:16.723354 progress 55 % (25 MB)
64 12:17:16.736922 progress 60 % (28 MB)
65 12:17:16.751078 progress 65 % (30 MB)
66 12:17:16.765199 progress 70 % (32 MB)
67 12:17:16.779311 progress 75 % (35 MB)
68 12:17:16.792602 progress 80 % (37 MB)
69 12:17:16.805615 progress 85 % (39 MB)
70 12:17:16.818765 progress 90 % (42 MB)
71 12:17:16.831498 progress 95 % (44 MB)
72 12:17:16.844156 progress 100 % (46 MB)
73 12:17:16.844461 46 MB downloaded in 0.27 s (174.67 MB/s)
74 12:17:16.844625 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:17:16.844855 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:17:16.844942 start: 1.3 download-retry (timeout 00:09:56) [common]
78 12:17:16.845026 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 12:17:16.845182 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:17:16.845251 saving as /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/dtb/mt8192-asurada-spherion-r0.dtb
81 12:17:16.845317 total size: 47278 (0 MB)
82 12:17:16.845378 No compression specified
83 12:17:16.846491 progress 69 % (0 MB)
84 12:17:16.846764 progress 100 % (0 MB)
85 12:17:16.846919 0 MB downloaded in 0.00 s (28.18 MB/s)
86 12:17:16.847042 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:17:16.847294 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:17:16.847458 start: 1.4 download-retry (timeout 00:09:56) [common]
90 12:17:16.847573 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 12:17:16.847759 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:17:16.847891 saving as /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/modules/modules.tar
93 12:17:16.847980 total size: 8625084 (8 MB)
94 12:17:16.848071 Using unxz to decompress xz
95 12:17:16.852988 progress 0 % (0 MB)
96 12:17:16.874696 progress 5 % (0 MB)
97 12:17:16.897078 progress 10 % (0 MB)
98 12:17:16.923609 progress 15 % (1 MB)
99 12:17:16.949839 progress 20 % (1 MB)
100 12:17:16.976713 progress 25 % (2 MB)
101 12:17:17.003627 progress 30 % (2 MB)
102 12:17:17.031761 progress 35 % (2 MB)
103 12:17:17.057359 progress 40 % (3 MB)
104 12:17:17.082531 progress 45 % (3 MB)
105 12:17:17.109567 progress 50 % (4 MB)
106 12:17:17.135372 progress 55 % (4 MB)
107 12:17:17.160579 progress 60 % (4 MB)
108 12:17:17.185942 progress 65 % (5 MB)
109 12:17:17.211317 progress 70 % (5 MB)
110 12:17:17.235822 progress 75 % (6 MB)
111 12:17:17.262393 progress 80 % (6 MB)
112 12:17:17.292146 progress 85 % (7 MB)
113 12:17:17.319760 progress 90 % (7 MB)
114 12:17:17.346406 progress 95 % (7 MB)
115 12:17:17.370144 progress 100 % (8 MB)
116 12:17:17.375107 8 MB downloaded in 0.53 s (15.60 MB/s)
117 12:17:17.375479 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:17:17.376014 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:17:17.376184 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 12:17:17.376353 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 12:17:17.376503 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:17:17.376657 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 12:17:17.376993 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj
125 12:17:17.377228 makedir: /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin
126 12:17:17.377414 makedir: /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/tests
127 12:17:17.377584 makedir: /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/results
128 12:17:17.377777 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-add-keys
129 12:17:17.378012 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-add-sources
130 12:17:17.378226 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-background-process-start
131 12:17:17.378437 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-background-process-stop
132 12:17:17.378645 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-common-functions
133 12:17:17.378856 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-echo-ipv4
134 12:17:17.379065 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-install-packages
135 12:17:17.379274 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-installed-packages
136 12:17:17.379486 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-os-build
137 12:17:17.379701 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-probe-channel
138 12:17:17.379950 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-probe-ip
139 12:17:17.380157 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-target-ip
140 12:17:17.380364 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-target-mac
141 12:17:17.380574 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-target-storage
142 12:17:17.380788 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-test-case
143 12:17:17.381003 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-test-event
144 12:17:17.381218 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-test-feedback
145 12:17:17.381430 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-test-raise
146 12:17:17.381649 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-test-reference
147 12:17:17.381874 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-test-runner
148 12:17:17.382091 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-test-set
149 12:17:17.382305 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-test-shell
150 12:17:17.382521 Updating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-install-packages (oe)
151 12:17:17.382779 Updating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/bin/lava-installed-packages (oe)
152 12:17:17.382992 Creating /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/environment
153 12:17:17.383172 LAVA metadata
154 12:17:17.383309 - LAVA_JOB_ID=11893112
155 12:17:17.383436 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:17:17.383621 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 12:17:17.383787 skipped lava-vland-overlay
158 12:17:17.383933 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:17:17.384094 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 12:17:17.384229 skipped lava-multinode-overlay
161 12:17:17.384377 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:17:17.384537 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 12:17:17.384683 Loading test definitions
164 12:17:17.384853 start: 1.5.2.3.1 git-repo-action (timeout 00:09:56) [common]
165 12:17:17.385003 Using /lava-11893112 at stage 0
166 12:17:17.385190 Fetching tests from https://github.com/kernelci/kernelci-core
167 12:17:17.385344 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/0/tests/0_sleep'
168 12:17:18.053087 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/0/tests/0_sleep
169 12:17:18.054558 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 12:17:18.055076 uuid=11893112_1.5.2.3.1 testdef=None
171 12:17:18.055217 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 12:17:18.055526 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
174 12:17:18.056147 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 12:17:18.056408 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
177 12:17:18.057355 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 12:17:18.057581 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
180 12:17:18.058256 runner path: /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/0/tests/0_sleep test_uuid 11893112_1.5.2.3.1
181 12:17:18.058338 sleep_params='mem freeze'
182 12:17:18.058478 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 12:17:18.058686 Creating lava-test-runner.conf files
185 12:17:18.058767 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893112/lava-overlay-6s40sdaj/lava-11893112/0 for stage 0
186 12:17:18.058917 - 0_sleep
187 12:17:18.059046 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 12:17:18.059147 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
189 12:17:18.190929 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 12:17:18.191088 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
191 12:17:18.191180 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 12:17:18.191279 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 12:17:18.191364 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
194 12:17:20.650158 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 12:17:20.650559 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
196 12:17:20.650669 extracting modules file /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893112/extract-overlay-ramdisk-nmo7uxw2/ramdisk
197 12:17:20.880003 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 12:17:20.880174 start: 1.5.5 apply-overlay-tftp (timeout 00:09:52) [common]
199 12:17:20.880273 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893112/compress-overlay-iatrhc6c/overlay-1.5.2.4.tar.gz to ramdisk
200 12:17:20.880346 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893112/compress-overlay-iatrhc6c/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893112/extract-overlay-ramdisk-nmo7uxw2/ramdisk
201 12:17:20.976179 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 12:17:20.976337 start: 1.5.6 configure-preseed-file (timeout 00:09:52) [common]
203 12:17:20.976441 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 12:17:20.976533 start: 1.5.7 compress-ramdisk (timeout 00:09:52) [common]
205 12:17:20.976619 Building ramdisk /var/lib/lava/dispatcher/tmp/11893112/extract-overlay-ramdisk-nmo7uxw2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893112/extract-overlay-ramdisk-nmo7uxw2/ramdisk
206 12:17:22.518053 >> 563484 blocks
207 12:17:32.183797 rename /var/lib/lava/dispatcher/tmp/11893112/extract-overlay-ramdisk-nmo7uxw2/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/ramdisk/ramdisk.cpio.gz
208 12:17:32.184248 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 12:17:32.184372 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
210 12:17:32.184471 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
211 12:17:32.184583 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/kernel/Image'
212 12:17:44.792196 Returned 0 in 12 seconds
213 12:17:44.893122 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/kernel/image.itb
214 12:17:46.264784 output: FIT description: Kernel Image image with one or more FDT blobs
215 12:17:46.265215 output: Created: Fri Oct 27 13:17:46 2023
216 12:17:46.265360 output: Image 0 (kernel-1)
217 12:17:46.265469 output: Description:
218 12:17:46.265539 output: Created: Fri Oct 27 13:17:46 2023
219 12:17:46.265605 output: Type: Kernel Image
220 12:17:46.265667 output: Compression: lzma compressed
221 12:17:46.265728 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
222 12:17:46.265827 output: Architecture: AArch64
223 12:17:46.265902 output: OS: Linux
224 12:17:46.265960 output: Load Address: 0x00000000
225 12:17:46.266020 output: Entry Point: 0x00000000
226 12:17:46.266079 output: Hash algo: crc32
227 12:17:46.266138 output: Hash value: d33b93ae
228 12:17:46.266194 output: Image 1 (fdt-1)
229 12:17:46.266252 output: Description: mt8192-asurada-spherion-r0
230 12:17:46.266306 output: Created: Fri Oct 27 13:17:46 2023
231 12:17:46.266360 output: Type: Flat Device Tree
232 12:17:46.266414 output: Compression: uncompressed
233 12:17:46.266468 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 12:17:46.266522 output: Architecture: AArch64
235 12:17:46.266575 output: Hash algo: crc32
236 12:17:46.266628 output: Hash value: cc4352de
237 12:17:46.266682 output: Image 2 (ramdisk-1)
238 12:17:46.266735 output: Description: unavailable
239 12:17:46.266788 output: Created: Fri Oct 27 13:17:46 2023
240 12:17:46.266842 output: Type: RAMDisk Image
241 12:17:46.266895 output: Compression: Unknown Compression
242 12:17:46.266948 output: Data Size: 98325783 Bytes = 96021.27 KiB = 93.77 MiB
243 12:17:46.267002 output: Architecture: AArch64
244 12:17:46.267056 output: OS: Linux
245 12:17:46.267109 output: Load Address: unavailable
246 12:17:46.267162 output: Entry Point: unavailable
247 12:17:46.267215 output: Hash algo: crc32
248 12:17:46.267268 output: Hash value: 6fc764fe
249 12:17:46.267322 output: Default Configuration: 'conf-1'
250 12:17:46.267375 output: Configuration 0 (conf-1)
251 12:17:46.267428 output: Description: mt8192-asurada-spherion-r0
252 12:17:46.267481 output: Kernel: kernel-1
253 12:17:46.267534 output: Init Ramdisk: ramdisk-1
254 12:17:46.267587 output: FDT: fdt-1
255 12:17:46.267640 output: Loadables: kernel-1
256 12:17:46.267692 output:
257 12:17:46.267935 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 12:17:46.268034 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 12:17:46.268142 end: 1.5 prepare-tftp-overlay (duration 00:00:29) [common]
260 12:17:46.268239 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:27) [common]
261 12:17:46.268321 No LXC device requested
262 12:17:46.268401 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 12:17:46.268489 start: 1.7 deploy-device-env (timeout 00:09:27) [common]
264 12:17:46.268566 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 12:17:46.268636 Checking files for TFTP limit of 4294967296 bytes.
266 12:17:46.269140 end: 1 tftp-deploy (duration 00:00:33) [common]
267 12:17:46.269250 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 12:17:46.269342 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 12:17:46.269463 substitutions:
270 12:17:46.269532 - {DTB}: 11893112/tftp-deploy-13d80pt7/dtb/mt8192-asurada-spherion-r0.dtb
271 12:17:46.269597 - {INITRD}: 11893112/tftp-deploy-13d80pt7/ramdisk/ramdisk.cpio.gz
272 12:17:46.269656 - {KERNEL}: 11893112/tftp-deploy-13d80pt7/kernel/Image
273 12:17:46.269722 - {LAVA_MAC}: None
274 12:17:46.269790 - {PRESEED_CONFIG}: None
275 12:17:46.269861 - {PRESEED_LOCAL}: None
276 12:17:46.269938 - {RAMDISK}: 11893112/tftp-deploy-13d80pt7/ramdisk/ramdisk.cpio.gz
277 12:17:46.269997 - {ROOT_PART}: None
278 12:17:46.270053 - {ROOT}: None
279 12:17:46.270123 - {SERVER_IP}: 192.168.201.1
280 12:17:46.270203 - {TEE}: None
281 12:17:46.270281 Parsed boot commands:
282 12:17:46.270338 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 12:17:46.270523 Parsed boot commands: tftpboot 192.168.201.1 11893112/tftp-deploy-13d80pt7/kernel/image.itb 11893112/tftp-deploy-13d80pt7/kernel/cmdline
284 12:17:46.270622 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 12:17:46.270753 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 12:17:46.270892 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 12:17:46.271049 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 12:17:46.271177 Not connected, no need to disconnect.
289 12:17:46.271301 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 12:17:46.271435 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 12:17:46.271541 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
292 12:17:46.276020 Setting prompt string to ['lava-test: # ']
293 12:17:46.276512 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 12:17:46.276693 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 12:17:46.276867 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 12:17:46.277081 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 12:17:46.277567 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
298 12:17:51.414486 >> Command sent successfully.
299 12:17:51.417545 Returned 0 in 5 seconds
300 12:17:51.517915 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 12:17:51.518233 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 12:17:51.518339 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 12:17:51.518432 Setting prompt string to 'Starting depthcharge on Spherion...'
305 12:17:51.518535 Changing prompt to 'Starting depthcharge on Spherion...'
306 12:17:51.518614 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 12:17:51.518880 [Enter `^Ec?' for help]
308 12:17:51.693371
309 12:17:51.693517
310 12:17:51.693622 F0: 102B 0000
311 12:17:51.693718
312 12:17:51.693811 F3: 1001 0000 [0200]
313 12:17:51.693900
314 12:17:51.697011 F3: 1001 0000
315 12:17:51.697113
316 12:17:51.697210 F7: 102D 0000
317 12:17:51.697304
318 12:17:51.697378 F1: 0000 0000
319 12:17:51.697437
320 12:17:51.700796 V0: 0000 0000 [0001]
321 12:17:51.700887
322 12:17:51.700954 00: 0007 8000
323 12:17:51.701025
324 12:17:51.703688 01: 0000 0000
325 12:17:51.703805
326 12:17:51.703872 BP: 0C00 0209 [0000]
327 12:17:51.703934
328 12:17:51.707161 G0: 1182 0000
329 12:17:51.707245
330 12:17:51.707311 EC: 0000 0021 [4000]
331 12:17:51.707374
332 12:17:51.710556 S7: 0000 0000 [0000]
333 12:17:51.710695
334 12:17:51.710790 CC: 0000 0000 [0001]
335 12:17:51.710881
336 12:17:51.714300 T0: 0000 0040 [010F]
337 12:17:51.714401
338 12:17:51.714490 Jump to BL
339 12:17:51.714577
340 12:17:51.740177
341 12:17:51.740271
342 12:17:51.740339
343 12:17:51.747836 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 12:17:51.751617 ARM64: Exception handlers installed.
345 12:17:51.754776 ARM64: Testing exception
346 12:17:51.758541 ARM64: Done test exception
347 12:17:51.765948 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 12:17:51.775563 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 12:17:51.782256 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 12:17:51.792168 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 12:17:51.798707 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 12:17:51.805074 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 12:17:51.816428 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 12:17:51.823167 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 12:17:51.842825 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 12:17:51.846264 WDT: Last reset was cold boot
357 12:17:51.849640 SPI1(PAD0) initialized at 2873684 Hz
358 12:17:51.852791 SPI5(PAD0) initialized at 992727 Hz
359 12:17:51.856196 VBOOT: Loading verstage.
360 12:17:51.862903 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 12:17:51.865980 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 12:17:51.869528 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 12:17:51.872706 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 12:17:51.880496 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 12:17:51.887151 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 12:17:51.897870 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 12:17:51.897960
368 12:17:51.898027
369 12:17:51.907544 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 12:17:51.911033 ARM64: Exception handlers installed.
371 12:17:51.914311 ARM64: Testing exception
372 12:17:51.914423 ARM64: Done test exception
373 12:17:51.920908 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 12:17:51.924327 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 12:17:51.938548 Probing TPM: . done!
376 12:17:51.938637 TPM ready after 0 ms
377 12:17:51.945723 Connected to device vid:did:rid of 1ae0:0028:00
378 12:17:51.955525 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
379 12:17:51.993343 Initialized TPM device CR50 revision 0
380 12:17:52.005620 tlcl_send_startup: Startup return code is 0
381 12:17:52.005713 TPM: setup succeeded
382 12:17:52.017128 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 12:17:52.025976 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 12:17:52.036166 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 12:17:52.045102 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 12:17:52.048020 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 12:17:52.051212 in-header: 03 07 00 00 08 00 00 00
388 12:17:52.054415 in-data: aa e4 47 04 13 02 00 00
389 12:17:52.057733 Chrome EC: UHEPI supported
390 12:17:52.064397 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 12:17:52.067785 in-header: 03 ad 00 00 08 00 00 00
392 12:17:52.071196 in-data: 00 20 20 08 00 00 00 00
393 12:17:52.071281 Phase 1
394 12:17:52.074426 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 12:17:52.081076 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 12:17:52.088049 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 12:17:52.091129 Recovery requested (1009000e)
398 12:17:52.094965 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 12:17:52.103539 tlcl_extend: response is 0
400 12:17:52.111643 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 12:17:52.117172 tlcl_extend: response is 0
402 12:17:52.123700 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 12:17:52.144133 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 12:17:52.150594 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 12:17:52.150683
406 12:17:52.150753
407 12:17:52.161457 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 12:17:52.165291 ARM64: Exception handlers installed.
409 12:17:52.165403 ARM64: Testing exception
410 12:17:52.167921 ARM64: Done test exception
411 12:17:52.189928 pmic_efuse_setting: Set efuses in 11 msecs
412 12:17:52.193685 pmwrap_interface_init: Select PMIF_VLD_RDY
413 12:17:52.197106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 12:17:52.203700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 12:17:52.207114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 12:17:52.213606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 12:17:52.216988 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 12:17:52.223875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 12:17:52.227364 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 12:17:52.234264 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 12:17:52.237658 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 12:17:52.240614 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 12:17:52.247025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 12:17:52.250471 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 12:17:52.253852 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 12:17:52.261215 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 12:17:52.267787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 12:17:52.274360 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 12:17:52.278019 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 12:17:52.284455 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 12:17:52.291066 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 12:17:52.294423 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 12:17:52.301390 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 12:17:52.308231 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 12:17:52.311892 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 12:17:52.319422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 12:17:52.322695 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 12:17:52.329417 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 12:17:52.332934 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 12:17:52.340357 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 12:17:52.343176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 12:17:52.346864 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 12:17:52.353809 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 12:17:52.357626 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 12:17:52.363906 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 12:17:52.367233 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 12:17:52.374516 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 12:17:52.377515 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 12:17:52.384455 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 12:17:52.388186 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 12:17:52.392146 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 12:17:52.399233 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 12:17:52.402071 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 12:17:52.405708 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 12:17:52.408666 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 12:17:52.415356 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 12:17:52.418695 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 12:17:52.422072 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 12:17:52.428509 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 12:17:52.432289 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 12:17:52.435100 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 12:17:52.442244 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 12:17:52.445516 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 12:17:52.451646 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 12:17:52.461750 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 12:17:52.465301 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 12:17:52.475355 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 12:17:52.481327 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 12:17:52.488460 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 12:17:52.491673 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 12:17:52.494559 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 12:17:52.502279 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x10
473 12:17:52.508774 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 12:17:52.512195 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
475 12:17:52.518745 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 12:17:52.526846 [RTC]rtc_get_frequency_meter,154: input=15, output=835
477 12:17:52.536323 [RTC]rtc_get_frequency_meter,154: input=7, output=708
478 12:17:52.545732 [RTC]rtc_get_frequency_meter,154: input=11, output=773
479 12:17:52.555665 [RTC]rtc_get_frequency_meter,154: input=13, output=804
480 12:17:52.564679 [RTC]rtc_get_frequency_meter,154: input=12, output=788
481 12:17:52.574429 [RTC]rtc_get_frequency_meter,154: input=12, output=788
482 12:17:52.584025 [RTC]rtc_get_frequency_meter,154: input=13, output=804
483 12:17:52.587370 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
484 12:17:52.594101 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
485 12:17:52.597565 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
486 12:17:52.600833 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
487 12:17:52.607332 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
488 12:17:52.610519 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
489 12:17:52.613831 ADC[4]: Raw value=904509 ID=7
490 12:17:52.613916 ADC[3]: Raw value=213652 ID=1
491 12:17:52.617519 RAM Code: 0x71
492 12:17:52.620371 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
493 12:17:52.627490 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
494 12:17:52.634092 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
495 12:17:52.640765 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
496 12:17:52.644034 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
497 12:17:52.647124 in-header: 03 07 00 00 08 00 00 00
498 12:17:52.650988 in-data: aa e4 47 04 13 02 00 00
499 12:17:52.654449 Chrome EC: UHEPI supported
500 12:17:52.660243 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
501 12:17:52.664054 in-header: 03 dd 00 00 08 00 00 00
502 12:17:52.667080 in-data: 90 20 60 08 00 00 00 00
503 12:17:52.670663 MRC: failed to locate region type 0.
504 12:17:52.677146 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
505 12:17:52.680292 DRAM-K: Running full calibration
506 12:17:52.687208 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
507 12:17:52.687293 header.status = 0x0
508 12:17:52.690798 header.version = 0x6 (expected: 0x6)
509 12:17:52.693571 header.size = 0xd00 (expected: 0xd00)
510 12:17:52.697148 header.flags = 0x0
511 12:17:52.703371 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
512 12:17:52.720954 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
513 12:17:52.727182 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
514 12:17:52.730521 dram_init: ddr_geometry: 2
515 12:17:52.734098 [EMI] MDL number = 2
516 12:17:52.734184 [EMI] Get MDL freq = 0
517 12:17:52.737424 dram_init: ddr_type: 0
518 12:17:52.737508 is_discrete_lpddr4: 1
519 12:17:52.740795 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
520 12:17:52.740879
521 12:17:52.740944
522 12:17:52.743973 [Bian_co] ETT version 0.0.0.1
523 12:17:52.750349 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
524 12:17:52.750434
525 12:17:52.753791 dramc_set_vcore_voltage set vcore to 650000
526 12:17:52.756984 Read voltage for 800, 4
527 12:17:52.757067 Vio18 = 0
528 12:17:52.757133 Vcore = 650000
529 12:17:52.757194 Vdram = 0
530 12:17:52.760372 Vddq = 0
531 12:17:52.760456 Vmddr = 0
532 12:17:52.763553 dram_init: config_dvfs: 1
533 12:17:52.767207 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
534 12:17:52.773828 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
535 12:17:52.777318 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
536 12:17:52.780491 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
537 12:17:52.783523 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
538 12:17:52.786759 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
539 12:17:52.790194 MEM_TYPE=3, freq_sel=18
540 12:17:52.793736 sv_algorithm_assistance_LP4_1600
541 12:17:52.796836 ============ PULL DRAM RESETB DOWN ============
542 12:17:52.803246 ========== PULL DRAM RESETB DOWN end =========
543 12:17:52.806789 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
544 12:17:52.809960 ===================================
545 12:17:52.813637 LPDDR4 DRAM CONFIGURATION
546 12:17:52.816587 ===================================
547 12:17:52.816672 EX_ROW_EN[0] = 0x0
548 12:17:52.819756 EX_ROW_EN[1] = 0x0
549 12:17:52.819853 LP4Y_EN = 0x0
550 12:17:52.823472 WORK_FSP = 0x0
551 12:17:52.823555 WL = 0x2
552 12:17:52.826539 RL = 0x2
553 12:17:52.826622 BL = 0x2
554 12:17:52.829933 RPST = 0x0
555 12:17:52.833488 RD_PRE = 0x0
556 12:17:52.833572 WR_PRE = 0x1
557 12:17:52.837150 WR_PST = 0x0
558 12:17:52.837234 DBI_WR = 0x0
559 12:17:52.840272 DBI_RD = 0x0
560 12:17:52.840355 OTF = 0x1
561 12:17:52.843055 ===================================
562 12:17:52.846662 ===================================
563 12:17:52.846746 ANA top config
564 12:17:52.849810 ===================================
565 12:17:52.853059 DLL_ASYNC_EN = 0
566 12:17:52.856497 ALL_SLAVE_EN = 1
567 12:17:52.859649 NEW_RANK_MODE = 1
568 12:17:52.863418 DLL_IDLE_MODE = 1
569 12:17:52.863501 LP45_APHY_COMB_EN = 1
570 12:17:52.866315 TX_ODT_DIS = 1
571 12:17:52.869674 NEW_8X_MODE = 1
572 12:17:52.873254 ===================================
573 12:17:52.876594 ===================================
574 12:17:52.879696 data_rate = 1600
575 12:17:52.882805 CKR = 1
576 12:17:52.882888 DQ_P2S_RATIO = 8
577 12:17:52.886053 ===================================
578 12:17:52.889921 CA_P2S_RATIO = 8
579 12:17:52.893470 DQ_CA_OPEN = 0
580 12:17:52.896290 DQ_SEMI_OPEN = 0
581 12:17:52.899392 CA_SEMI_OPEN = 0
582 12:17:52.903053 CA_FULL_RATE = 0
583 12:17:52.903172 DQ_CKDIV4_EN = 1
584 12:17:52.905974 CA_CKDIV4_EN = 1
585 12:17:52.909317 CA_PREDIV_EN = 0
586 12:17:52.912931 PH8_DLY = 0
587 12:17:52.915995 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
588 12:17:52.919347 DQ_AAMCK_DIV = 4
589 12:17:52.919519 CA_AAMCK_DIV = 4
590 12:17:52.922641 CA_ADMCK_DIV = 4
591 12:17:52.926007 DQ_TRACK_CA_EN = 0
592 12:17:52.929170 CA_PICK = 800
593 12:17:52.932606 CA_MCKIO = 800
594 12:17:52.935874 MCKIO_SEMI = 0
595 12:17:52.939264 PLL_FREQ = 3068
596 12:17:52.939348 DQ_UI_PI_RATIO = 32
597 12:17:52.942565 CA_UI_PI_RATIO = 0
598 12:17:52.945922 ===================================
599 12:17:52.949303 ===================================
600 12:17:52.952643 memory_type:LPDDR4
601 12:17:52.955664 GP_NUM : 10
602 12:17:52.955785 SRAM_EN : 1
603 12:17:52.959056 MD32_EN : 0
604 12:17:52.962307 ===================================
605 12:17:52.965699 [ANA_INIT] >>>>>>>>>>>>>>
606 12:17:52.965782 <<<<<< [CONFIGURE PHASE]: ANA_TX
607 12:17:52.972221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
608 12:17:52.975762 ===================================
609 12:17:52.975845 data_rate = 1600,PCW = 0X7600
610 12:17:52.979304 ===================================
611 12:17:52.982779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
612 12:17:52.988895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
613 12:17:52.995441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
614 12:17:52.998829 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
615 12:17:53.002331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
616 12:17:53.005791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
617 12:17:53.009120 [ANA_INIT] flow start
618 12:17:53.009204 [ANA_INIT] PLL >>>>>>>>
619 12:17:53.012453 [ANA_INIT] PLL <<<<<<<<
620 12:17:53.015773 [ANA_INIT] MIDPI >>>>>>>>
621 12:17:53.018721 [ANA_INIT] MIDPI <<<<<<<<
622 12:17:53.018805 [ANA_INIT] DLL >>>>>>>>
623 12:17:53.022077 [ANA_INIT] flow end
624 12:17:53.025234 ============ LP4 DIFF to SE enter ============
625 12:17:53.028755 ============ LP4 DIFF to SE exit ============
626 12:17:53.032152 [ANA_INIT] <<<<<<<<<<<<<
627 12:17:53.035532 [Flow] Enable top DCM control >>>>>
628 12:17:53.038715 [Flow] Enable top DCM control <<<<<
629 12:17:53.042293 Enable DLL master slave shuffle
630 12:17:53.048527 ==============================================================
631 12:17:53.048616 Gating Mode config
632 12:17:53.055712 ==============================================================
633 12:17:53.055835 Config description:
634 12:17:53.065495 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
635 12:17:53.071889 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
636 12:17:53.078730 SELPH_MODE 0: By rank 1: By Phase
637 12:17:53.081948 ==============================================================
638 12:17:53.085199 GAT_TRACK_EN = 1
639 12:17:53.089007 RX_GATING_MODE = 2
640 12:17:53.092220 RX_GATING_TRACK_MODE = 2
641 12:17:53.095432 SELPH_MODE = 1
642 12:17:53.098713 PICG_EARLY_EN = 1
643 12:17:53.102213 VALID_LAT_VALUE = 1
644 12:17:53.105555 ==============================================================
645 12:17:53.108903 Enter into Gating configuration >>>>
646 12:17:53.111949 Exit from Gating configuration <<<<
647 12:17:53.115427 Enter into DVFS_PRE_config >>>>>
648 12:17:53.128582 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
649 12:17:53.131745 Exit from DVFS_PRE_config <<<<<
650 12:17:53.135256 Enter into PICG configuration >>>>
651 12:17:53.138540 Exit from PICG configuration <<<<
652 12:17:53.138624 [RX_INPUT] configuration >>>>>
653 12:17:53.141497 [RX_INPUT] configuration <<<<<
654 12:17:53.148274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
655 12:17:53.152085 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
656 12:17:53.159255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
657 12:17:53.166586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
658 12:17:53.170323 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
659 12:17:53.177628 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
660 12:17:53.181270 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
661 12:17:53.184914 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
662 12:17:53.189015 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
663 12:17:53.195527 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
664 12:17:53.199312 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
665 12:17:53.203242 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
666 12:17:53.207213 ===================================
667 12:17:53.207298 LPDDR4 DRAM CONFIGURATION
668 12:17:53.210003 ===================================
669 12:17:53.214006 EX_ROW_EN[0] = 0x0
670 12:17:53.214091 EX_ROW_EN[1] = 0x0
671 12:17:53.217664 LP4Y_EN = 0x0
672 12:17:53.217747 WORK_FSP = 0x0
673 12:17:53.221313 WL = 0x2
674 12:17:53.221396 RL = 0x2
675 12:17:53.224971 BL = 0x2
676 12:17:53.225055 RPST = 0x0
677 12:17:53.228786 RD_PRE = 0x0
678 12:17:53.228869 WR_PRE = 0x1
679 12:17:53.232536 WR_PST = 0x0
680 12:17:53.232623 DBI_WR = 0x0
681 12:17:53.236173 DBI_RD = 0x0
682 12:17:53.236257 OTF = 0x1
683 12:17:53.239582 ===================================
684 12:17:53.243133 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
685 12:17:53.247197 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
686 12:17:53.250789 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
687 12:17:53.254016 ===================================
688 12:17:53.258066 LPDDR4 DRAM CONFIGURATION
689 12:17:53.262251 ===================================
690 12:17:53.262335 EX_ROW_EN[0] = 0x10
691 12:17:53.265898 EX_ROW_EN[1] = 0x0
692 12:17:53.265982 LP4Y_EN = 0x0
693 12:17:53.269086 WORK_FSP = 0x0
694 12:17:53.269170 WL = 0x2
695 12:17:53.272927 RL = 0x2
696 12:17:53.273013 BL = 0x2
697 12:17:53.276718 RPST = 0x0
698 12:17:53.276815 RD_PRE = 0x0
699 12:17:53.280543 WR_PRE = 0x1
700 12:17:53.280630 WR_PST = 0x0
701 12:17:53.284219 DBI_WR = 0x0
702 12:17:53.284305 DBI_RD = 0x0
703 12:17:53.284371 OTF = 0x1
704 12:17:53.287470 ===================================
705 12:17:53.294748 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
706 12:17:53.298774 nWR fixed to 40
707 12:17:53.302950 [ModeRegInit_LP4] CH0 RK0
708 12:17:53.303040 [ModeRegInit_LP4] CH0 RK1
709 12:17:53.306530 [ModeRegInit_LP4] CH1 RK0
710 12:17:53.310170 [ModeRegInit_LP4] CH1 RK1
711 12:17:53.310257 match AC timing 13
712 12:17:53.313784 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
713 12:17:53.317114 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
714 12:17:53.324126 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
715 12:17:53.327487 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
716 12:17:53.331102 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
717 12:17:53.334016 [EMI DOE] emi_dcm 0
718 12:17:53.337281 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
719 12:17:53.337365 ==
720 12:17:53.340695 Dram Type= 6, Freq= 0, CH_0, rank 0
721 12:17:53.344128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
722 12:17:53.347999 ==
723 12:17:53.350626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
724 12:17:53.357339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
725 12:17:53.366391 [CA 0] Center 37 (6~68) winsize 63
726 12:17:53.370160 [CA 1] Center 37 (6~68) winsize 63
727 12:17:53.372906 [CA 2] Center 34 (4~65) winsize 62
728 12:17:53.376558 [CA 3] Center 34 (4~65) winsize 62
729 12:17:53.380284 [CA 4] Center 33 (3~64) winsize 62
730 12:17:53.383687 [CA 5] Center 33 (3~64) winsize 62
731 12:17:53.383820
732 12:17:53.387399 [CmdBusTrainingLP45] Vref(ca) range 1: 34
733 12:17:53.387483
734 12:17:53.390595 [CATrainingPosCal] consider 1 rank data
735 12:17:53.394443 u2DelayCellTimex100 = 270/100 ps
736 12:17:53.397267 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
737 12:17:53.400336 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
738 12:17:53.403674 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
739 12:17:53.407099 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
740 12:17:53.410367 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
741 12:17:53.417194 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
742 12:17:53.417277
743 12:17:53.420443 CA PerBit enable=1, Macro0, CA PI delay=33
744 12:17:53.420527
745 12:17:53.423884 [CBTSetCACLKResult] CA Dly = 33
746 12:17:53.423968 CS Dly: 7 (0~38)
747 12:17:53.424035 ==
748 12:17:53.426917 Dram Type= 6, Freq= 0, CH_0, rank 1
749 12:17:53.430434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 12:17:53.434027 ==
751 12:17:53.437387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 12:17:53.443544 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 12:17:53.452485 [CA 0] Center 37 (6~68) winsize 63
754 12:17:53.455678 [CA 1] Center 37 (7~68) winsize 62
755 12:17:53.459235 [CA 2] Center 34 (4~65) winsize 62
756 12:17:53.462670 [CA 3] Center 34 (4~65) winsize 62
757 12:17:53.465924 [CA 4] Center 33 (3~64) winsize 62
758 12:17:53.469227 [CA 5] Center 33 (3~64) winsize 62
759 12:17:53.469312
760 12:17:53.472772 [CmdBusTrainingLP45] Vref(ca) range 1: 34
761 12:17:53.472857
762 12:17:53.475995 [CATrainingPosCal] consider 2 rank data
763 12:17:53.479414 u2DelayCellTimex100 = 270/100 ps
764 12:17:53.482834 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
765 12:17:53.485778 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
766 12:17:53.493173 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
767 12:17:53.496474 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
768 12:17:53.496557 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
769 12:17:53.500291 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 12:17:53.504228
771 12:17:53.507730 CA PerBit enable=1, Macro0, CA PI delay=33
772 12:17:53.507847
773 12:17:53.507941 [CBTSetCACLKResult] CA Dly = 33
774 12:17:53.511248 CS Dly: 7 (0~39)
775 12:17:53.511351
776 12:17:53.514801 ----->DramcWriteLeveling(PI) begin...
777 12:17:53.514903 ==
778 12:17:53.518670 Dram Type= 6, Freq= 0, CH_0, rank 0
779 12:17:53.521890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 12:17:53.522037 ==
781 12:17:53.525408 Write leveling (Byte 0): 30 => 30
782 12:17:53.528809 Write leveling (Byte 1): 29 => 29
783 12:17:53.532186 DramcWriteLeveling(PI) end<-----
784 12:17:53.532286
785 12:17:53.532390 ==
786 12:17:53.535407 Dram Type= 6, Freq= 0, CH_0, rank 0
787 12:17:53.538583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 12:17:53.538670 ==
789 12:17:53.541965 [Gating] SW mode calibration
790 12:17:53.548928 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
791 12:17:53.555651 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
792 12:17:53.558750 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
793 12:17:53.562014 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
794 12:17:53.568851 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
795 12:17:53.572600 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:17:53.575226 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:17:53.578620 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:17:53.585274 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:17:53.588816 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:17:53.592085 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:17:53.598535 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:17:53.602024 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:17:53.605156 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:17:53.611973 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:17:53.615550 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:17:53.618872 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:17:53.625264 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:17:53.629131 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
809 12:17:53.631991 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
810 12:17:53.638580 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
811 12:17:53.641896 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:17:53.645146 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:17:53.651986 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:17:53.655162 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:17:53.658503 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:17:53.665268 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:17:53.668789 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:17:53.672016 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
819 12:17:53.679037 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
820 12:17:53.681860 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 12:17:53.685496 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 12:17:53.689034 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
823 12:17:53.695441 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
824 12:17:53.698890 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
825 12:17:53.701938 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
826 12:17:53.708479 0 10 8 | B1->B0 | 3232 2929 | 0 1 | (0 0) (1 0)
827 12:17:53.711931 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
828 12:17:53.715104 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:17:53.721549 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:17:53.725471 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 12:17:53.728252 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 12:17:53.735121 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 12:17:53.738485 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 12:17:53.741688 0 11 8 | B1->B0 | 2727 3737 | 0 1 | (0 0) (0 0)
835 12:17:53.748349 0 11 12 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
836 12:17:53.751409 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:17:53.755416 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:17:53.761516 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
839 12:17:53.764788 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
840 12:17:53.768027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
841 12:17:53.775231 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
842 12:17:53.778493 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
843 12:17:53.781404 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
844 12:17:53.788107 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:17:53.791516 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:17:53.794959 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:17:53.801462 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:17:53.804791 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:17:53.808477 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:17:53.811603 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:17:53.818184 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:17:53.821644 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:17:53.824622 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 12:17:53.831448 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:17:53.834662 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:17:53.838194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:17:53.844742 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:17:53.848659 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
859 12:17:53.851468 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
860 12:17:53.854915 Total UI for P1: 0, mck2ui 16
861 12:17:53.858289 best dqsien dly found for B0: ( 0, 14, 8)
862 12:17:53.861454 Total UI for P1: 0, mck2ui 16
863 12:17:53.864911 best dqsien dly found for B1: ( 0, 14, 8)
864 12:17:53.868157 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
865 12:17:53.871277 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
866 12:17:53.871390
867 12:17:53.878323 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
868 12:17:53.881554 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
869 12:17:53.881725 [Gating] SW calibration Done
870 12:17:53.884748 ==
871 12:17:53.884859 Dram Type= 6, Freq= 0, CH_0, rank 0
872 12:17:53.892309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
873 12:17:53.892416 ==
874 12:17:53.892488 RX Vref Scan: 0
875 12:17:53.892551
876 12:17:53.895660 RX Vref 0 -> 0, step: 1
877 12:17:53.895769
878 12:17:53.898785 RX Delay -130 -> 252, step: 16
879 12:17:53.901738 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
880 12:17:53.905129 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
881 12:17:53.908823 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
882 12:17:53.912239 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
883 12:17:53.919348 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
884 12:17:53.922164 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
885 12:17:53.925865 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
886 12:17:53.929799 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
887 12:17:53.933408 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
888 12:17:53.937326 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
889 12:17:53.940940 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
890 12:17:53.944734 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
891 12:17:53.948379 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
892 12:17:53.955369 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
893 12:17:53.959072 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
894 12:17:53.962756 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
895 12:17:53.962851 ==
896 12:17:53.966219 Dram Type= 6, Freq= 0, CH_0, rank 0
897 12:17:53.970541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
898 12:17:53.970666 ==
899 12:17:53.970786 DQS Delay:
900 12:17:53.974075 DQS0 = 0, DQS1 = 0
901 12:17:53.974215 DQM Delay:
902 12:17:53.974329 DQM0 = 87, DQM1 = 76
903 12:17:53.977447 DQ Delay:
904 12:17:53.981182 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
905 12:17:53.984475 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
906 12:17:53.984560 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
907 12:17:53.988393 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
908 12:17:53.988477
909 12:17:53.988543
910 12:17:53.992226 ==
911 12:17:53.992310 Dram Type= 6, Freq= 0, CH_0, rank 0
912 12:17:53.999290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 12:17:53.999375 ==
914 12:17:53.999477
915 12:17:53.999539
916 12:17:53.999598 TX Vref Scan disable
917 12:17:54.002640 == TX Byte 0 ==
918 12:17:54.005990 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
919 12:17:54.009399 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
920 12:17:54.012905 == TX Byte 1 ==
921 12:17:54.016069 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
922 12:17:54.019794 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
923 12:17:54.019875 ==
924 12:17:54.023074 Dram Type= 6, Freq= 0, CH_0, rank 0
925 12:17:54.029973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 12:17:54.030101 ==
927 12:17:54.042052 TX Vref=22, minBit 1, minWin=27, winSum=438
928 12:17:54.045673 TX Vref=24, minBit 5, minWin=27, winSum=443
929 12:17:54.049508 TX Vref=26, minBit 8, minWin=27, winSum=444
930 12:17:54.053186 TX Vref=28, minBit 10, minWin=27, winSum=446
931 12:17:54.057157 TX Vref=30, minBit 4, minWin=27, winSum=442
932 12:17:54.060024 TX Vref=32, minBit 4, minWin=27, winSum=445
933 12:17:54.066967 [TxChooseVref] Worse bit 10, Min win 27, Win sum 446, Final Vref 28
934 12:17:54.067077
935 12:17:54.067173 Final TX Range 1 Vref 28
936 12:17:54.067267
937 12:17:54.069856 ==
938 12:17:54.074104 Dram Type= 6, Freq= 0, CH_0, rank 0
939 12:17:54.076525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
940 12:17:54.076692 ==
941 12:17:54.076794
942 12:17:54.076887
943 12:17:54.079979 TX Vref Scan disable
944 12:17:54.080096 == TX Byte 0 ==
945 12:17:54.086757 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
946 12:17:54.090168 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
947 12:17:54.090283 == TX Byte 1 ==
948 12:17:54.096586 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
949 12:17:54.099946 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
950 12:17:54.100030
951 12:17:54.100096 [DATLAT]
952 12:17:54.103226 Freq=800, CH0 RK0
953 12:17:54.103326
954 12:17:54.103417 DATLAT Default: 0xa
955 12:17:54.107128 0, 0xFFFF, sum = 0
956 12:17:54.107241 1, 0xFFFF, sum = 0
957 12:17:54.109971 2, 0xFFFF, sum = 0
958 12:17:54.110077 3, 0xFFFF, sum = 0
959 12:17:54.113427 4, 0xFFFF, sum = 0
960 12:17:54.113541 5, 0xFFFF, sum = 0
961 12:17:54.116893 6, 0xFFFF, sum = 0
962 12:17:54.117004 7, 0xFFFF, sum = 0
963 12:17:54.120167 8, 0xFFFF, sum = 0
964 12:17:54.120253 9, 0x0, sum = 1
965 12:17:54.123351 10, 0x0, sum = 2
966 12:17:54.123462 11, 0x0, sum = 3
967 12:17:54.126685 12, 0x0, sum = 4
968 12:17:54.126799 best_step = 10
969 12:17:54.126894
970 12:17:54.126998 ==
971 12:17:54.130090 Dram Type= 6, Freq= 0, CH_0, rank 0
972 12:17:54.136793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 12:17:54.136901 ==
974 12:17:54.136997 RX Vref Scan: 1
975 12:17:54.137099
976 12:17:54.139675 Set Vref Range= 32 -> 127
977 12:17:54.139802
978 12:17:54.143505 RX Vref 32 -> 127, step: 1
979 12:17:54.143603
980 12:17:54.143693 RX Delay -95 -> 252, step: 8
981 12:17:54.146514
982 12:17:54.146630 Set Vref, RX VrefLevel [Byte0]: 32
983 12:17:54.149793 [Byte1]: 32
984 12:17:54.154394
985 12:17:54.154476 Set Vref, RX VrefLevel [Byte0]: 33
986 12:17:54.157258 [Byte1]: 33
987 12:17:54.161794
988 12:17:54.161879 Set Vref, RX VrefLevel [Byte0]: 34
989 12:17:54.165090 [Byte1]: 34
990 12:17:54.168972
991 12:17:54.169056 Set Vref, RX VrefLevel [Byte0]: 35
992 12:17:54.172769 [Byte1]: 35
993 12:17:54.176953
994 12:17:54.177061 Set Vref, RX VrefLevel [Byte0]: 36
995 12:17:54.180105 [Byte1]: 36
996 12:17:54.184708
997 12:17:54.184792 Set Vref, RX VrefLevel [Byte0]: 37
998 12:17:54.188351 [Byte1]: 37
999 12:17:54.192357
1000 12:17:54.192441 Set Vref, RX VrefLevel [Byte0]: 38
1001 12:17:54.195393 [Byte1]: 38
1002 12:17:54.199658
1003 12:17:54.199797 Set Vref, RX VrefLevel [Byte0]: 39
1004 12:17:54.202894 [Byte1]: 39
1005 12:17:54.207655
1006 12:17:54.207800 Set Vref, RX VrefLevel [Byte0]: 40
1007 12:17:54.210795 [Byte1]: 40
1008 12:17:54.215402
1009 12:17:54.215513 Set Vref, RX VrefLevel [Byte0]: 41
1010 12:17:54.218068 [Byte1]: 41
1011 12:17:54.222805
1012 12:17:54.222889 Set Vref, RX VrefLevel [Byte0]: 42
1013 12:17:54.226004 [Byte1]: 42
1014 12:17:54.230016
1015 12:17:54.230123 Set Vref, RX VrefLevel [Byte0]: 43
1016 12:17:54.233617 [Byte1]: 43
1017 12:17:54.237470
1018 12:17:54.237553 Set Vref, RX VrefLevel [Byte0]: 44
1019 12:17:54.241394 [Byte1]: 44
1020 12:17:54.245244
1021 12:17:54.245329 Set Vref, RX VrefLevel [Byte0]: 45
1022 12:17:54.248599 [Byte1]: 45
1023 12:17:54.253129
1024 12:17:54.253214 Set Vref, RX VrefLevel [Byte0]: 46
1025 12:17:54.256109 [Byte1]: 46
1026 12:17:54.260949
1027 12:17:54.261033 Set Vref, RX VrefLevel [Byte0]: 47
1028 12:17:54.263637 [Byte1]: 47
1029 12:17:54.267852
1030 12:17:54.267936 Set Vref, RX VrefLevel [Byte0]: 48
1031 12:17:54.271309 [Byte1]: 48
1032 12:17:54.275877
1033 12:17:54.275960 Set Vref, RX VrefLevel [Byte0]: 49
1034 12:17:54.279362 [Byte1]: 49
1035 12:17:54.283174
1036 12:17:54.283256 Set Vref, RX VrefLevel [Byte0]: 50
1037 12:17:54.286506 [Byte1]: 50
1038 12:17:54.290668
1039 12:17:54.290777 Set Vref, RX VrefLevel [Byte0]: 51
1040 12:17:54.293884 [Byte1]: 51
1041 12:17:54.298553
1042 12:17:54.298636 Set Vref, RX VrefLevel [Byte0]: 52
1043 12:17:54.301807 [Byte1]: 52
1044 12:17:54.305706
1045 12:17:54.305789 Set Vref, RX VrefLevel [Byte0]: 53
1046 12:17:54.308976 [Byte1]: 53
1047 12:17:54.313483
1048 12:17:54.316918 Set Vref, RX VrefLevel [Byte0]: 54
1049 12:17:54.320107 [Byte1]: 54
1050 12:17:54.320190
1051 12:17:54.323198 Set Vref, RX VrefLevel [Byte0]: 55
1052 12:17:54.327071 [Byte1]: 55
1053 12:17:54.327155
1054 12:17:54.330152 Set Vref, RX VrefLevel [Byte0]: 56
1055 12:17:54.333318 [Byte1]: 56
1056 12:17:54.333401
1057 12:17:54.336352 Set Vref, RX VrefLevel [Byte0]: 57
1058 12:17:54.339791 [Byte1]: 57
1059 12:17:54.344017
1060 12:17:54.344100 Set Vref, RX VrefLevel [Byte0]: 58
1061 12:17:54.347230 [Byte1]: 58
1062 12:17:54.351640
1063 12:17:54.351770 Set Vref, RX VrefLevel [Byte0]: 59
1064 12:17:54.354834 [Byte1]: 59
1065 12:17:54.359216
1066 12:17:54.359299 Set Vref, RX VrefLevel [Byte0]: 60
1067 12:17:54.362555 [Byte1]: 60
1068 12:17:54.366719
1069 12:17:54.366827 Set Vref, RX VrefLevel [Byte0]: 61
1070 12:17:54.370243 [Byte1]: 61
1071 12:17:54.374536
1072 12:17:54.374618 Set Vref, RX VrefLevel [Byte0]: 62
1073 12:17:54.377425 [Byte1]: 62
1074 12:17:54.381829
1075 12:17:54.381912 Set Vref, RX VrefLevel [Byte0]: 63
1076 12:17:54.385063 [Byte1]: 63
1077 12:17:54.389323
1078 12:17:54.389406 Set Vref, RX VrefLevel [Byte0]: 64
1079 12:17:54.392792 [Byte1]: 64
1080 12:17:54.397109
1081 12:17:54.397192 Set Vref, RX VrefLevel [Byte0]: 65
1082 12:17:54.400423 [Byte1]: 65
1083 12:17:54.404432
1084 12:17:54.404514 Set Vref, RX VrefLevel [Byte0]: 66
1085 12:17:54.408203 [Byte1]: 66
1086 12:17:54.412028
1087 12:17:54.415623 Set Vref, RX VrefLevel [Byte0]: 67
1088 12:17:54.415758 [Byte1]: 67
1089 12:17:54.419899
1090 12:17:54.419982 Set Vref, RX VrefLevel [Byte0]: 68
1091 12:17:54.423442 [Byte1]: 68
1092 12:17:54.427666
1093 12:17:54.427804 Set Vref, RX VrefLevel [Byte0]: 69
1094 12:17:54.431877 [Byte1]: 69
1095 12:17:54.434997
1096 12:17:54.435079 Set Vref, RX VrefLevel [Byte0]: 70
1097 12:17:54.438524 [Byte1]: 70
1098 12:17:54.443174
1099 12:17:54.443257 Set Vref, RX VrefLevel [Byte0]: 71
1100 12:17:54.445877 [Byte1]: 71
1101 12:17:54.450910
1102 12:17:54.450994 Set Vref, RX VrefLevel [Byte0]: 72
1103 12:17:54.453947 [Byte1]: 72
1104 12:17:54.457815
1105 12:17:54.457897 Set Vref, RX VrefLevel [Byte0]: 73
1106 12:17:54.461311 [Byte1]: 73
1107 12:17:54.465812
1108 12:17:54.465894 Set Vref, RX VrefLevel [Byte0]: 74
1109 12:17:54.469185 [Byte1]: 74
1110 12:17:54.473175
1111 12:17:54.473258 Set Vref, RX VrefLevel [Byte0]: 75
1112 12:17:54.476403 [Byte1]: 75
1113 12:17:54.480908
1114 12:17:54.484245 Set Vref, RX VrefLevel [Byte0]: 76
1115 12:17:54.484349 [Byte1]: 76
1116 12:17:54.488602
1117 12:17:54.488704 Set Vref, RX VrefLevel [Byte0]: 77
1118 12:17:54.492029 [Byte1]: 77
1119 12:17:54.495653
1120 12:17:54.495767 Set Vref, RX VrefLevel [Byte0]: 78
1121 12:17:54.498988 [Byte1]: 78
1122 12:17:54.503530
1123 12:17:54.503630 Set Vref, RX VrefLevel [Byte0]: 79
1124 12:17:54.506896 [Byte1]: 79
1125 12:17:54.510841
1126 12:17:54.510939 Set Vref, RX VrefLevel [Byte0]: 80
1127 12:17:54.514061 [Byte1]: 80
1128 12:17:54.518535
1129 12:17:54.518632 Set Vref, RX VrefLevel [Byte0]: 81
1130 12:17:54.522231 [Byte1]: 81
1131 12:17:54.526559
1132 12:17:54.526666 Set Vref, RX VrefLevel [Byte0]: 82
1133 12:17:54.529524 [Byte1]: 82
1134 12:17:54.534333
1135 12:17:54.534415 Set Vref, RX VrefLevel [Byte0]: 83
1136 12:17:54.537612 [Byte1]: 83
1137 12:17:54.542039
1138 12:17:54.542146 Final RX Vref Byte 0 = 67 to rank0
1139 12:17:54.545278 Final RX Vref Byte 1 = 52 to rank0
1140 12:17:54.549075 Final RX Vref Byte 0 = 67 to rank1
1141 12:17:54.552803 Final RX Vref Byte 1 = 52 to rank1==
1142 12:17:54.556316 Dram Type= 6, Freq= 0, CH_0, rank 0
1143 12:17:54.559934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 12:17:54.560043 ==
1145 12:17:54.562855 DQS Delay:
1146 12:17:54.562954 DQS0 = 0, DQS1 = 0
1147 12:17:54.563045 DQM Delay:
1148 12:17:54.566400 DQM0 = 88, DQM1 = 76
1149 12:17:54.566507 DQ Delay:
1150 12:17:54.569604 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1151 12:17:54.572669 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1152 12:17:54.576380 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1153 12:17:54.578996 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1154 12:17:54.579102
1155 12:17:54.579212
1156 12:17:54.589224 [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1157 12:17:54.589332 CH0 RK0: MR19=606, MR18=4729
1158 12:17:54.595672 CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64
1159 12:17:54.595789
1160 12:17:54.599184 ----->DramcWriteLeveling(PI) begin...
1161 12:17:54.602636 ==
1162 12:17:54.602737 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 12:17:54.609281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 12:17:54.609381 ==
1165 12:17:54.612635 Write leveling (Byte 0): 34 => 34
1166 12:17:54.656722 Write leveling (Byte 1): 28 => 28
1167 12:17:54.656814 DramcWriteLeveling(PI) end<-----
1168 12:17:54.656905
1169 12:17:54.657000 ==
1170 12:17:54.657284 Dram Type= 6, Freq= 0, CH_0, rank 1
1171 12:17:54.657379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1172 12:17:54.657467 ==
1173 12:17:54.657557 [Gating] SW mode calibration
1174 12:17:54.657685 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1175 12:17:54.657792 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1176 12:17:54.658068 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1177 12:17:54.658349 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1178 12:17:54.658634 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1179 12:17:54.658726 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1180 12:17:54.661519 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:17:54.668179 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:17:54.671504 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:17:54.674768 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:17:54.681051 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:17:54.684612 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:17:54.688472 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:17:54.694311 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:17:54.697781 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:17:54.701443 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:17:54.707926 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:17:54.711159 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:17:54.714279 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:17:54.720988 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1194 12:17:54.724295 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1195 12:17:54.727954 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:17:54.734478 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:17:54.737742 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 12:17:54.741644 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 12:17:54.745013 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 12:17:54.751839 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 12:17:54.755693 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 12:17:54.759260 0 9 8 | B1->B0 | 2424 2c2c | 1 1 | (1 1) (1 1)
1203 12:17:54.762825 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1204 12:17:54.766072 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 12:17:54.773504 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1206 12:17:54.777009 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1207 12:17:54.780800 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1208 12:17:54.784627 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 12:17:54.791652 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1210 12:17:54.795212 0 10 8 | B1->B0 | 3232 2b2b | 1 0 | (0 1) (1 0)
1211 12:17:54.799388 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1212 12:17:54.802498 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:17:54.805950 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:17:54.813472 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:17:54.817477 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:17:54.820989 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:17:54.824792 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:17:54.828421 0 11 8 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
1219 12:17:54.835437 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
1220 12:17:54.839278 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 12:17:54.843004 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 12:17:54.846644 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 12:17:54.850533 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1224 12:17:54.857673 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 12:17:54.860962 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 12:17:54.864875 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1227 12:17:54.868116 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:17:54.872510 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 12:17:54.879311 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 12:17:54.883032 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 12:17:54.886345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 12:17:54.890079 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 12:17:54.893987 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 12:17:54.901173 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 12:17:54.905127 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 12:17:54.908954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 12:17:54.912368 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 12:17:54.916212 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 12:17:54.923328 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 12:17:54.927034 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 12:17:54.930580 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 12:17:54.933984 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1243 12:17:54.937721 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 12:17:54.941847 Total UI for P1: 0, mck2ui 16
1245 12:17:54.945530 best dqsien dly found for B0: ( 0, 14, 8)
1246 12:17:54.948830 Total UI for P1: 0, mck2ui 16
1247 12:17:54.953090 best dqsien dly found for B1: ( 0, 14, 8)
1248 12:17:54.956400 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1249 12:17:54.959630 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1250 12:17:54.959754
1251 12:17:54.963662 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1252 12:17:54.967567 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1253 12:17:54.970853 [Gating] SW calibration Done
1254 12:17:54.970953 ==
1255 12:17:54.974143 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 12:17:54.978634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 12:17:54.978742 ==
1258 12:17:54.978835 RX Vref Scan: 0
1259 12:17:54.978923
1260 12:17:54.981776 RX Vref 0 -> 0, step: 1
1261 12:17:54.981878
1262 12:17:54.986071 RX Delay -130 -> 252, step: 16
1263 12:17:54.989212 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1264 12:17:54.992454 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1265 12:17:54.996603 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1266 12:17:54.999817 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1267 12:17:55.003908 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1268 12:17:55.007473 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1269 12:17:55.011111 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1270 12:17:55.014800 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1271 12:17:55.018811 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1272 12:17:55.022118 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1273 12:17:55.029882 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1274 12:17:55.033366 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1275 12:17:55.037598 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1276 12:17:55.040659 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1277 12:17:55.043905 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1278 12:17:55.047760 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1279 12:17:55.047877 ==
1280 12:17:55.051392 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 12:17:55.055122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 12:17:55.055254 ==
1283 12:17:55.059252 DQS Delay:
1284 12:17:55.059364 DQS0 = 0, DQS1 = 0
1285 12:17:55.059467 DQM Delay:
1286 12:17:55.062507 DQM0 = 84, DQM1 = 78
1287 12:17:55.062608 DQ Delay:
1288 12:17:55.066041 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1289 12:17:55.069553 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1290 12:17:55.072728 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1291 12:17:55.076342 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1292 12:17:55.076441
1293 12:17:55.076540
1294 12:17:55.076640 ==
1295 12:17:55.079169 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 12:17:55.082598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 12:17:55.082695 ==
1298 12:17:55.082783
1299 12:17:55.086271
1300 12:17:55.086366 TX Vref Scan disable
1301 12:17:55.089263 == TX Byte 0 ==
1302 12:17:55.092379 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1303 12:17:55.095746 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1304 12:17:55.099522 == TX Byte 1 ==
1305 12:17:55.102523 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1306 12:17:55.106047 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1307 12:17:55.106145 ==
1308 12:17:55.109150 Dram Type= 6, Freq= 0, CH_0, rank 1
1309 12:17:55.116037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1310 12:17:55.116165 ==
1311 12:17:55.128674 TX Vref=22, minBit 4, minWin=27, winSum=441
1312 12:17:55.131440 TX Vref=24, minBit 4, minWin=27, winSum=445
1313 12:17:55.135037 TX Vref=26, minBit 9, minWin=27, winSum=446
1314 12:17:55.138278 TX Vref=28, minBit 9, minWin=27, winSum=446
1315 12:17:55.141420 TX Vref=30, minBit 9, minWin=27, winSum=446
1316 12:17:55.148301 TX Vref=32, minBit 2, minWin=27, winSum=443
1317 12:17:55.151637 [TxChooseVref] Worse bit 9, Min win 27, Win sum 446, Final Vref 26
1318 12:17:55.151749
1319 12:17:55.154834 Final TX Range 1 Vref 26
1320 12:17:55.154941
1321 12:17:55.155032 ==
1322 12:17:55.158385 Dram Type= 6, Freq= 0, CH_0, rank 1
1323 12:17:55.161882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1324 12:17:55.161979 ==
1325 12:17:55.164775
1326 12:17:55.164873
1327 12:17:55.164962 TX Vref Scan disable
1328 12:17:55.168131 == TX Byte 0 ==
1329 12:17:55.171652 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1330 12:17:55.178445 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1331 12:17:55.178544 == TX Byte 1 ==
1332 12:17:55.181541 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1333 12:17:55.188209 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1334 12:17:55.188313
1335 12:17:55.188403 [DATLAT]
1336 12:17:55.188491 Freq=800, CH0 RK1
1337 12:17:55.188577
1338 12:17:55.191542 DATLAT Default: 0xa
1339 12:17:55.191637 0, 0xFFFF, sum = 0
1340 12:17:55.194810 1, 0xFFFF, sum = 0
1341 12:17:55.194913 2, 0xFFFF, sum = 0
1342 12:17:55.198137 3, 0xFFFF, sum = 0
1343 12:17:55.201321 4, 0xFFFF, sum = 0
1344 12:17:55.201425 5, 0xFFFF, sum = 0
1345 12:17:55.204726 6, 0xFFFF, sum = 0
1346 12:17:55.204825 7, 0xFFFF, sum = 0
1347 12:17:55.208198 8, 0xFFFF, sum = 0
1348 12:17:55.208297 9, 0x0, sum = 1
1349 12:17:55.211492 10, 0x0, sum = 2
1350 12:17:55.211587 11, 0x0, sum = 3
1351 12:17:55.211676 12, 0x0, sum = 4
1352 12:17:55.214640 best_step = 10
1353 12:17:55.214734
1354 12:17:55.214820 ==
1355 12:17:55.218219 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 12:17:55.221634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 12:17:55.221740 ==
1358 12:17:55.224855 RX Vref Scan: 0
1359 12:17:55.224960
1360 12:17:55.225052 RX Vref 0 -> 0, step: 1
1361 12:17:55.228120
1362 12:17:55.228228 RX Delay -95 -> 252, step: 8
1363 12:17:55.234948 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1364 12:17:55.238314 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1365 12:17:55.241852 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1366 12:17:55.244786 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1367 12:17:55.248500 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1368 12:17:55.254875 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1369 12:17:55.258354 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1370 12:17:55.261545 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1371 12:17:55.264975 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1372 12:17:55.268251 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1373 12:17:55.274677 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1374 12:17:55.278385 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1375 12:17:55.281761 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1376 12:17:55.285138 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1377 12:17:55.291494 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1378 12:17:55.294573 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1379 12:17:55.294676 ==
1380 12:17:55.298078 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 12:17:55.301450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 12:17:55.301560 ==
1383 12:17:55.304361 DQS Delay:
1384 12:17:55.304462 DQS0 = 0, DQS1 = 0
1385 12:17:55.304551 DQM Delay:
1386 12:17:55.307704 DQM0 = 85, DQM1 = 77
1387 12:17:55.307830 DQ Delay:
1388 12:17:55.311053 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1389 12:17:55.314461 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1390 12:17:55.318129 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1391 12:17:55.321172 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1392 12:17:55.321270
1393 12:17:55.321359
1394 12:17:55.331112 [DQSOSCAuto] RK1, (LSB)MR18= 0x4007, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1395 12:17:55.331194 CH0 RK1: MR19=606, MR18=4007
1396 12:17:55.337460 CH0_RK1: MR19=0x606, MR18=0x4007, DQSOSC=393, MR23=63, INC=95, DEC=63
1397 12:17:55.341085 [RxdqsGatingPostProcess] freq 800
1398 12:17:55.347693 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1399 12:17:55.351166 Pre-setting of DQS Precalculation
1400 12:17:55.354175 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1401 12:17:55.354273 ==
1402 12:17:55.357842 Dram Type= 6, Freq= 0, CH_1, rank 0
1403 12:17:56.562880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 12:17:56.563140 ==
1405 12:17:56.563502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 12:17:56.563626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 12:17:56.563734 [CA 0] Center 36 (6~67) winsize 62
1408 12:17:56.563805 [CA 1] Center 37 (7~67) winsize 61
1409 12:17:56.563904 [CA 2] Center 34 (4~65) winsize 62
1410 12:17:56.564010 [CA 3] Center 34 (3~65) winsize 63
1411 12:17:56.564129 [CA 4] Center 34 (4~65) winsize 62
1412 12:17:56.564234 [CA 5] Center 34 (3~65) winsize 63
1413 12:17:56.564368
1414 12:17:56.564475 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 12:17:56.564571
1416 12:17:56.564665 [CATrainingPosCal] consider 1 rank data
1417 12:17:56.564761 u2DelayCellTimex100 = 270/100 ps
1418 12:17:56.564865 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1419 12:17:56.564962 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1420 12:17:56.565056 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1421 12:17:56.565146 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1422 12:17:56.565241 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1423 12:17:56.565350 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1424 12:17:56.565438
1425 12:17:56.565533 CA PerBit enable=1, Macro0, CA PI delay=34
1426 12:17:56.565633
1427 12:17:56.565722 [CBTSetCACLKResult] CA Dly = 34
1428 12:17:56.565827 CS Dly: 4 (0~35)
1429 12:17:56.565916 ==
1430 12:17:56.566008 Dram Type= 6, Freq= 0, CH_1, rank 1
1431 12:17:56.566110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1432 12:17:56.566254 ==
1433 12:17:56.566353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1434 12:17:56.566444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1435 12:17:56.566530 [CA 0] Center 36 (6~67) winsize 62
1436 12:17:56.566651 [CA 1] Center 36 (6~67) winsize 62
1437 12:17:56.566743 [CA 2] Center 34 (4~65) winsize 62
1438 12:17:56.566837 [CA 3] Center 34 (3~65) winsize 63
1439 12:17:56.566946 [CA 4] Center 34 (4~65) winsize 62
1440 12:17:56.567039 [CA 5] Center 33 (3~64) winsize 62
1441 12:17:56.567147
1442 12:17:56.567237 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1443 12:17:56.567336
1444 12:17:56.567437 [CATrainingPosCal] consider 2 rank data
1445 12:17:56.567527 u2DelayCellTimex100 = 270/100 ps
1446 12:17:56.567650 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1447 12:17:56.567747 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
1448 12:17:56.567857 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1449 12:17:56.567976 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1450 12:17:56.568067 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1451 12:17:56.568175 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1452 12:17:56.568289
1453 12:17:56.568390 CA PerBit enable=1, Macro0, CA PI delay=33
1454 12:17:56.568478
1455 12:17:56.568575 [CBTSetCACLKResult] CA Dly = 33
1456 12:17:56.568666 CS Dly: 5 (0~38)
1457 12:17:56.568749
1458 12:17:56.568847 ----->DramcWriteLeveling(PI) begin...
1459 12:17:56.568939 ==
1460 12:17:56.569024 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 12:17:56.569126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 12:17:56.569215 ==
1463 12:17:56.569307 Write leveling (Byte 0): 24 => 24
1464 12:17:56.569404 Write leveling (Byte 1): 28 => 28
1465 12:17:56.569489 DramcWriteLeveling(PI) end<-----
1466 12:17:56.569585
1467 12:17:56.569675 ==
1468 12:17:56.569759 Dram Type= 6, Freq= 0, CH_1, rank 0
1469 12:17:56.569860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 12:17:56.569944 ==
1471 12:17:56.570031 [Gating] SW mode calibration
1472 12:17:56.570133 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1473 12:17:56.570219 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1474 12:17:56.570316 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1475 12:17:56.570408 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1476 12:17:56.570493 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1477 12:17:56.570595 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:17:56.570682 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:17:56.570773 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:17:56.570868 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:17:56.570955 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:17:56.571056 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:17:56.571142 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:17:56.571442 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:17:56.571558 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:17:56.571662 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:17:56.571789 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:17:56.571928 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:17:56.572031 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:17:56.572185 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:17:56.572303 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1492 12:17:56.572423 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:17:56.572549 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:17:56.572634 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:17:56.572750 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 12:17:56.572868 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 12:17:56.573010 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 12:17:56.573147 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:17:56.573296 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 12:17:56.573406 0 9 8 | B1->B0 | 2b2b 3232 | 1 0 | (1 1) (1 0)
1501 12:17:56.573510 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 12:17:56.573623 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 12:17:56.573787 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1504 12:17:56.573913 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1505 12:17:56.574011 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 12:17:56.574115 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 12:17:56.574213 0 10 4 | B1->B0 | 3333 3232 | 0 0 | (0 0) (0 1)
1508 12:17:56.574314 0 10 8 | B1->B0 | 2727 2323 | 0 1 | (1 0) (1 0)
1509 12:17:56.574414 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:17:56.574785 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:17:56.574940 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:17:56.575038 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:17:56.575159 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:17:56.575283 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:17:56.575401 0 11 4 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
1516 12:17:56.575499 0 11 8 | B1->B0 | 3e3e 4444 | 0 0 | (1 1) (0 0)
1517 12:17:56.575601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 12:17:56.575767 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 12:17:56.575883 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 12:17:56.575964 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1521 12:17:56.576060 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 12:17:56.576166 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 12:17:56.576243 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1524 12:17:56.576347 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1525 12:17:56.576445 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 12:17:56.576539 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 12:17:56.576642 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 12:17:56.576740 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 12:17:56.576840 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 12:17:56.576937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 12:17:56.577030 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 12:17:56.577135 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 12:17:56.577228 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 12:17:56.577327 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 12:17:56.577427 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 12:17:56.577520 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 12:17:56.577623 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 12:17:56.577720 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 12:17:56.577819 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1540 12:17:56.577915 Total UI for P1: 0, mck2ui 16
1541 12:17:56.578012 best dqsien dly found for B0: ( 0, 14, 2)
1542 12:17:56.578115 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 12:17:56.578209 Total UI for P1: 0, mck2ui 16
1544 12:17:56.578309 best dqsien dly found for B1: ( 0, 14, 6)
1545 12:17:56.578406 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1546 12:17:56.578502 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1547 12:17:56.578606
1548 12:17:56.578702 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1549 12:17:56.578805 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1550 12:17:56.578901 [Gating] SW calibration Done
1551 12:17:56.579001 ==
1552 12:17:56.579098 Dram Type= 6, Freq= 0, CH_1, rank 0
1553 12:17:56.579194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1554 12:17:56.579298 ==
1555 12:17:56.579392 RX Vref Scan: 0
1556 12:17:56.579497
1557 12:17:56.579594 RX Vref 0 -> 0, step: 1
1558 12:17:56.579693
1559 12:17:56.579801 RX Delay -130 -> 252, step: 16
1560 12:17:56.579896 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1561 12:17:56.579999 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1562 12:17:56.580093 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1563 12:17:56.580190 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1564 12:17:56.580289 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1565 12:17:56.580386 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1566 12:17:56.580479 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1567 12:17:56.580581 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1568 12:17:56.580691 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1569 12:17:56.580788 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1570 12:17:56.580881 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1571 12:17:56.581029 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1572 12:17:56.581122 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1573 12:17:56.581223 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1574 12:17:56.581317 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1575 12:17:56.581417 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1576 12:17:56.581511 ==
1577 12:17:56.581606 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 12:17:56.581706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 12:17:56.581804 ==
1580 12:17:56.581903 DQS Delay:
1581 12:17:56.581998 DQS0 = 0, DQS1 = 0
1582 12:17:56.582096 DQM Delay:
1583 12:17:56.582192 DQM0 = 89, DQM1 = 79
1584 12:17:56.582283 DQ Delay:
1585 12:17:56.582382 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1586 12:17:56.582478 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1587 12:17:56.582619 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1588 12:17:56.582717 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1589 12:17:56.582810
1590 12:17:56.582909
1591 12:17:56.583000 ==
1592 12:17:56.583097 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 12:17:56.583193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 12:17:56.583288 ==
1595 12:17:56.583388
1596 12:17:56.583482
1597 12:17:56.583571 TX Vref Scan disable
1598 12:17:56.583671 == TX Byte 0 ==
1599 12:17:56.583797 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1600 12:17:56.583898 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1601 12:17:56.583992 == TX Byte 1 ==
1602 12:17:56.584088 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 12:17:56.584183 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 12:17:56.584276 ==
1605 12:17:56.584376 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 12:17:56.584470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 12:17:56.584566 ==
1608 12:17:56.584661 TX Vref=22, minBit 0, minWin=27, winSum=438
1609 12:17:56.584753 TX Vref=24, minBit 13, minWin=26, winSum=439
1610 12:17:56.584859 TX Vref=26, minBit 1, minWin=27, winSum=443
1611 12:17:56.584955 TX Vref=28, minBit 1, minWin=27, winSum=446
1612 12:17:56.585055 TX Vref=30, minBit 0, minWin=27, winSum=446
1613 12:17:56.585147 TX Vref=32, minBit 0, minWin=27, winSum=439
1614 12:17:56.585246 [TxChooseVref] Worse bit 1, Min win 27, Win sum 446, Final Vref 28
1615 12:17:56.585341
1616 12:17:56.585436 Final TX Range 1 Vref 28
1617 12:17:56.585537
1618 12:17:56.585629 ==
1619 12:17:56.585724 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 12:17:56.585824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 12:17:56.585919 ==
1622 12:17:56.586016
1623 12:17:56.586113
1624 12:17:56.586205 TX Vref Scan disable
1625 12:17:56.586305 == TX Byte 0 ==
1626 12:17:56.586603 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1627 12:17:56.586696 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1628 12:17:56.586790 == TX Byte 1 ==
1629 12:17:56.586889 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1630 12:17:56.586984 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1631 12:17:56.587075
1632 12:17:56.587169 [DATLAT]
1633 12:17:56.587261 Freq=800, CH1 RK0
1634 12:17:56.587363
1635 12:17:56.587459 DATLAT Default: 0xa
1636 12:17:56.587556 0, 0xFFFF, sum = 0
1637 12:17:56.587677 1, 0xFFFF, sum = 0
1638 12:17:56.587798 2, 0xFFFF, sum = 0
1639 12:17:56.587903 3, 0xFFFF, sum = 0
1640 12:17:56.588002 4, 0xFFFF, sum = 0
1641 12:17:56.588106 5, 0xFFFF, sum = 0
1642 12:17:56.588200 6, 0xFFFF, sum = 0
1643 12:17:56.588320 7, 0xFFFF, sum = 0
1644 12:17:56.588475 8, 0xFFFF, sum = 0
1645 12:17:56.588570 9, 0x0, sum = 1
1646 12:17:56.588673 10, 0x0, sum = 2
1647 12:17:56.588766 11, 0x0, sum = 3
1648 12:17:56.588871 12, 0x0, sum = 4
1649 12:17:56.588968 best_step = 10
1650 12:17:56.589064
1651 12:17:56.589158 ==
1652 12:17:56.589252 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 12:17:56.589354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 12:17:56.589451 ==
1655 12:17:56.589542 RX Vref Scan: 1
1656 12:17:56.589644
1657 12:17:56.589735 Set Vref Range= 32 -> 127
1658 12:17:56.589829
1659 12:17:56.589931 RX Vref 32 -> 127, step: 1
1660 12:17:56.590027
1661 12:17:56.590125 RX Delay -95 -> 252, step: 8
1662 12:17:56.590221
1663 12:17:56.590311 Set Vref, RX VrefLevel [Byte0]: 32
1664 12:17:56.590411 [Byte1]: 32
1665 12:17:56.590507
1666 12:17:56.590606 Set Vref, RX VrefLevel [Byte0]: 33
1667 12:17:56.590697 [Byte1]: 33
1668 12:17:56.590794
1669 12:17:56.590894 Set Vref, RX VrefLevel [Byte0]: 34
1670 12:17:56.590985 [Byte1]: 34
1671 12:17:56.591078
1672 12:17:56.591178 Set Vref, RX VrefLevel [Byte0]: 35
1673 12:17:56.591274 [Byte1]: 35
1674 12:17:56.591373
1675 12:17:56.591550 Set Vref, RX VrefLevel [Byte0]: 36
1676 12:17:56.591652 [Byte1]: 36
1677 12:17:56.591779
1678 12:17:56.591881 Set Vref, RX VrefLevel [Byte0]: 37
1679 12:17:56.591976 [Byte1]: 37
1680 12:17:56.592072
1681 12:17:56.592171 Set Vref, RX VrefLevel [Byte0]: 38
1682 12:17:56.592320 [Byte1]: 38
1683 12:17:56.592424
1684 12:17:56.592516 Set Vref, RX VrefLevel [Byte0]: 39
1685 12:17:56.592613 [Byte1]: 39
1686 12:17:56.592710
1687 12:17:56.592809 Set Vref, RX VrefLevel [Byte0]: 40
1688 12:17:56.592905 [Byte1]: 40
1689 12:17:56.593001
1690 12:17:56.593099 Set Vref, RX VrefLevel [Byte0]: 41
1691 12:17:56.593190 [Byte1]: 41
1692 12:17:56.593286
1693 12:17:56.593384 Set Vref, RX VrefLevel [Byte0]: 42
1694 12:17:56.593477 [Byte1]: 42
1695 12:17:56.593576
1696 12:17:56.593666 Set Vref, RX VrefLevel [Byte0]: 43
1697 12:17:56.593765 [Byte1]: 43
1698 12:17:56.593861
1699 12:17:56.593957 Set Vref, RX VrefLevel [Byte0]: 44
1700 12:17:56.594055 [Byte1]: 44
1701 12:17:56.594146
1702 12:17:56.594242 Set Vref, RX VrefLevel [Byte0]: 45
1703 12:17:56.594340 [Byte1]: 45
1704 12:17:56.594432
1705 12:17:56.594531 Set Vref, RX VrefLevel [Byte0]: 46
1706 12:17:56.594621 [Byte1]: 46
1707 12:17:56.594761
1708 12:17:56.594853 Set Vref, RX VrefLevel [Byte0]: 47
1709 12:17:56.594951 [Byte1]: 47
1710 12:17:56.595048
1711 12:17:56.595142 Set Vref, RX VrefLevel [Byte0]: 48
1712 12:17:56.595240 [Byte1]: 48
1713 12:17:56.595337
1714 12:17:56.595427 Set Vref, RX VrefLevel [Byte0]: 49
1715 12:17:56.595551 [Byte1]: 49
1716 12:17:56.595649
1717 12:17:56.595759 Set Vref, RX VrefLevel [Byte0]: 50
1718 12:17:56.595870 [Byte1]: 50
1719 12:17:56.595971
1720 12:17:56.596065 Set Vref, RX VrefLevel [Byte0]: 51
1721 12:17:56.596156 [Byte1]: 51
1722 12:17:56.596256
1723 12:17:56.596351 Set Vref, RX VrefLevel [Byte0]: 52
1724 12:17:56.596443 [Byte1]: 52
1725 12:17:56.596543
1726 12:17:56.596637 Set Vref, RX VrefLevel [Byte0]: 53
1727 12:17:56.596729 [Byte1]: 53
1728 12:17:56.596828
1729 12:17:56.596920 Set Vref, RX VrefLevel [Byte0]: 54
1730 12:17:56.597014 [Byte1]: 54
1731 12:17:56.597115
1732 12:17:56.597204 Set Vref, RX VrefLevel [Byte0]: 55
1733 12:17:56.597293 [Byte1]: 55
1734 12:17:56.597393
1735 12:17:56.597489 Set Vref, RX VrefLevel [Byte0]: 56
1736 12:17:56.597585 [Byte1]: 56
1737 12:17:56.597679
1738 12:17:56.597810 Set Vref, RX VrefLevel [Byte0]: 57
1739 12:17:56.597969 [Byte1]: 57
1740 12:17:56.598063
1741 12:17:56.598159 Set Vref, RX VrefLevel [Byte0]: 58
1742 12:17:56.598257 [Byte1]: 58
1743 12:17:56.598352
1744 12:17:56.598451 Set Vref, RX VrefLevel [Byte0]: 59
1745 12:17:56.598544 [Byte1]: 59
1746 12:17:56.598639
1747 12:17:56.598735 Set Vref, RX VrefLevel [Byte0]: 60
1748 12:17:56.598828 [Byte1]: 60
1749 12:17:56.598926
1750 12:17:56.599020 Set Vref, RX VrefLevel [Byte0]: 61
1751 12:17:56.599119 [Byte1]: 61
1752 12:17:56.599213
1753 12:17:56.599303 Set Vref, RX VrefLevel [Byte0]: 62
1754 12:17:56.599399 [Byte1]: 62
1755 12:17:56.599495
1756 12:17:56.599587 Set Vref, RX VrefLevel [Byte0]: 63
1757 12:17:56.599682 [Byte1]: 63
1758 12:17:56.599819
1759 12:17:56.599911 Set Vref, RX VrefLevel [Byte0]: 64
1760 12:17:56.600011 [Byte1]: 64
1761 12:17:56.600107
1762 12:17:56.600203 Set Vref, RX VrefLevel [Byte0]: 65
1763 12:17:56.600303 [Byte1]: 65
1764 12:17:56.600396
1765 12:17:56.600486 Set Vref, RX VrefLevel [Byte0]: 66
1766 12:17:56.600585 [Byte1]: 66
1767 12:17:56.600681
1768 12:17:56.600779 Set Vref, RX VrefLevel [Byte0]: 67
1769 12:17:56.600873 [Byte1]: 67
1770 12:17:56.600963
1771 12:17:56.601063 Set Vref, RX VrefLevel [Byte0]: 68
1772 12:17:56.601158 [Byte1]: 68
1773 12:17:56.601251
1774 12:17:56.601347 Set Vref, RX VrefLevel [Byte0]: 69
1775 12:17:56.601442 [Byte1]: 69
1776 12:17:56.601539
1777 12:17:56.601635 Set Vref, RX VrefLevel [Byte0]: 70
1778 12:17:56.601728 [Byte1]: 70
1779 12:17:56.601821
1780 12:17:56.601920 Set Vref, RX VrefLevel [Byte0]: 71
1781 12:17:56.602014 [Byte1]: 71
1782 12:17:56.602104
1783 12:17:56.602200 Set Vref, RX VrefLevel [Byte0]: 72
1784 12:17:56.602300 [Byte1]: 72
1785 12:17:56.602397
1786 12:17:56.602495 Set Vref, RX VrefLevel [Byte0]: 73
1787 12:17:56.602589 [Byte1]: 73
1788 12:17:56.602714
1789 12:17:56.602846 Set Vref, RX VrefLevel [Byte0]: 74
1790 12:17:56.602939 [Byte1]: 74
1791 12:17:56.603034
1792 12:17:56.603130 Set Vref, RX VrefLevel [Byte0]: 75
1793 12:17:56.603226 [Byte1]: 75
1794 12:17:56.603325
1795 12:17:56.603632 Set Vref, RX VrefLevel [Byte0]: 76
1796 12:17:56.603737 [Byte1]: 76
1797 12:17:56.603844
1798 12:17:56.603942 Set Vref, RX VrefLevel [Byte0]: 77
1799 12:17:56.604038 [Byte1]: 77
1800 12:17:56.604139
1801 12:17:56.604236 Final RX Vref Byte 0 = 55 to rank0
1802 12:17:56.604336 Final RX Vref Byte 1 = 65 to rank0
1803 12:17:56.604434 Final RX Vref Byte 0 = 55 to rank1
1804 12:17:56.604526 Final RX Vref Byte 1 = 65 to rank1==
1805 12:17:56.604629 Dram Type= 6, Freq= 0, CH_1, rank 0
1806 12:17:56.604723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 12:17:56.604823 ==
1808 12:17:56.604919 DQS Delay:
1809 12:17:56.605013 DQS0 = 0, DQS1 = 0
1810 12:17:56.605112 DQM Delay:
1811 12:17:56.605209 DQM0 = 86, DQM1 = 78
1812 12:17:56.605305 DQ Delay:
1813 12:17:56.605404 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1814 12:17:56.605495 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1815 12:17:56.605593 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1816 12:17:56.605692 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1817 12:17:56.605785
1818 12:17:56.605875
1819 12:17:56.605976 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1820 12:17:56.606072 CH1 RK0: MR19=606, MR18=2E1B
1821 12:17:56.606169 CH1_RK0: MR19=0x606, MR18=0x2E1B, DQSOSC=398, MR23=63, INC=93, DEC=62
1822 12:17:56.606263
1823 12:17:56.606357 ----->DramcWriteLeveling(PI) begin...
1824 12:17:56.606459 ==
1825 12:17:56.606556 Dram Type= 6, Freq= 0, CH_1, rank 1
1826 12:17:56.606653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1827 12:17:56.606751 ==
1828 12:17:56.606842 Write leveling (Byte 0): 29 => 29
1829 12:17:56.606943 Write leveling (Byte 1): 29 => 29
1830 12:17:56.607034 DramcWriteLeveling(PI) end<-----
1831 12:17:56.607132
1832 12:17:56.607229 ==
1833 12:17:56.607324 Dram Type= 6, Freq= 0, CH_1, rank 1
1834 12:17:56.607421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1835 12:17:56.607520 ==
1836 12:17:56.607613 [Gating] SW mode calibration
1837 12:17:56.607708 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1838 12:17:56.608114 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1839 12:17:56.611339 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1840 12:17:56.617997 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1841 12:17:56.621438 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1842 12:17:56.625245 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:17:56.631203 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:17:56.634958 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:17:56.638121 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:17:56.641313 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:17:56.648406 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:17:56.651560 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:17:56.655165 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:17:56.661267 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:17:56.664917 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:17:56.668088 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:17:56.674708 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:17:56.677784 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:17:56.681348 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:17:56.687699 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1857 12:17:56.691032 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:17:56.694560 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:17:56.701267 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:17:56.704768 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:17:56.708024 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:17:56.714755 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:17:56.718299 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:17:56.721429 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:17:56.728029 0 9 8 | B1->B0 | 302f 2525 | 1 1 | (1 1) (0 0)
1866 12:17:56.731203 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 12:17:56.734795 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 12:17:56.741206 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 12:17:56.744618 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1870 12:17:56.748217 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1871 12:17:56.754375 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1872 12:17:56.757821 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1873 12:17:56.761041 0 10 8 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (1 0)
1874 12:17:56.767662 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:17:56.770835 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:17:56.774039 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:17:56.781219 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:17:56.784427 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:17:56.788021 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:17:56.790803 0 11 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1881 12:17:56.797605 0 11 8 | B1->B0 | 4040 3535 | 0 1 | (0 0) (0 0)
1882 12:17:56.800829 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 12:17:56.804176 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 12:17:56.810739 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 12:17:56.814266 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 12:17:56.817534 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1887 12:17:56.823873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 12:17:56.827322 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1889 12:17:56.830853 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 12:17:56.837657 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 12:17:56.840607 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 12:17:56.843990 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 12:17:56.850557 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 12:17:56.853850 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 12:17:56.857274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 12:17:56.864000 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 12:17:56.867164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 12:17:56.870450 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 12:17:56.877077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 12:17:56.880598 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 12:17:56.884262 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 12:17:56.890754 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 12:17:56.894115 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 12:17:56.897117 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1905 12:17:56.904028 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 12:17:56.904111 Total UI for P1: 0, mck2ui 16
1907 12:17:56.907099 best dqsien dly found for B0: ( 0, 14, 6)
1908 12:17:56.910895 Total UI for P1: 0, mck2ui 16
1909 12:17:56.913605 best dqsien dly found for B1: ( 0, 14, 4)
1910 12:17:56.920279 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1911 12:17:56.924094 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1912 12:17:56.924176
1913 12:17:56.926869 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1914 12:17:56.930536 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1915 12:17:56.933704 [Gating] SW calibration Done
1916 12:17:56.933785 ==
1917 12:17:56.937035 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 12:17:56.940246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 12:17:56.940329 ==
1920 12:17:56.940395 RX Vref Scan: 0
1921 12:17:56.943428
1922 12:17:56.943514 RX Vref 0 -> 0, step: 1
1923 12:17:56.943617
1924 12:17:56.946759 RX Delay -130 -> 252, step: 16
1925 12:17:56.950317 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1926 12:17:56.954064 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1927 12:17:56.960371 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1928 12:17:56.963694 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1929 12:17:56.966564 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1930 12:17:56.970357 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1931 12:17:56.976695 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1932 12:17:56.980028 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1933 12:17:56.983171 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1934 12:17:56.986606 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1935 12:17:56.989794 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1936 12:17:56.997005 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1937 12:17:57.000204 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1938 12:17:57.003520 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1939 12:17:57.006976 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1940 12:17:57.010322 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1941 12:17:57.013126 ==
1942 12:17:57.016714 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 12:17:57.019737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 12:17:57.019835 ==
1945 12:17:57.019901 DQS Delay:
1946 12:17:57.022988 DQS0 = 0, DQS1 = 0
1947 12:17:57.023069 DQM Delay:
1948 12:17:57.026609 DQM0 = 87, DQM1 = 78
1949 12:17:57.026691 DQ Delay:
1950 12:17:57.029562 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1951 12:17:57.032891 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1952 12:17:57.036619 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1953 12:17:57.039885 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1954 12:17:57.039968
1955 12:17:57.040033
1956 12:17:57.040094 ==
1957 12:17:57.043151 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 12:17:57.046445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 12:17:57.046529 ==
1960 12:17:57.046593
1961 12:17:57.046661
1962 12:17:57.049888 TX Vref Scan disable
1963 12:17:57.053339 == TX Byte 0 ==
1964 12:17:57.056639 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1965 12:17:57.059956 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1966 12:17:57.062840 == TX Byte 1 ==
1967 12:17:57.066114 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1968 12:17:57.069851 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1969 12:17:57.069933 ==
1970 12:17:57.072741 Dram Type= 6, Freq= 0, CH_1, rank 1
1971 12:17:57.079619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1972 12:17:57.079702 ==
1973 12:17:57.091098 TX Vref=22, minBit 8, minWin=27, winSum=448
1974 12:17:57.094256 TX Vref=24, minBit 8, minWin=27, winSum=450
1975 12:17:57.097942 TX Vref=26, minBit 15, minWin=27, winSum=453
1976 12:17:57.100936 TX Vref=28, minBit 13, minWin=27, winSum=453
1977 12:17:57.104304 TX Vref=30, minBit 13, minWin=27, winSum=449
1978 12:17:57.111306 TX Vref=32, minBit 8, minWin=27, winSum=447
1979 12:17:57.114498 [TxChooseVref] Worse bit 15, Min win 27, Win sum 453, Final Vref 26
1980 12:17:57.114590
1981 12:17:57.117982 Final TX Range 1 Vref 26
1982 12:17:57.118097
1983 12:17:57.118189 ==
1984 12:17:57.121186 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 12:17:57.124452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 12:17:57.127880 ==
1987 12:17:57.127964
1988 12:17:57.128029
1989 12:17:57.128089 TX Vref Scan disable
1990 12:17:57.131071 == TX Byte 0 ==
1991 12:17:57.134527 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1992 12:17:57.141031 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1993 12:17:57.141117 == TX Byte 1 ==
1994 12:17:57.144472 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1995 12:17:57.151268 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1996 12:17:57.151351
1997 12:17:57.151416 [DATLAT]
1998 12:17:57.151478 Freq=800, CH1 RK1
1999 12:17:57.151537
2000 12:17:57.154726 DATLAT Default: 0xa
2001 12:17:57.154810 0, 0xFFFF, sum = 0
2002 12:17:57.158065 1, 0xFFFF, sum = 0
2003 12:17:57.161458 2, 0xFFFF, sum = 0
2004 12:17:57.161541 3, 0xFFFF, sum = 0
2005 12:17:57.164692 4, 0xFFFF, sum = 0
2006 12:17:57.164776 5, 0xFFFF, sum = 0
2007 12:17:57.167881 6, 0xFFFF, sum = 0
2008 12:17:57.167966 7, 0xFFFF, sum = 0
2009 12:17:57.171096 8, 0xFFFF, sum = 0
2010 12:17:57.171179 9, 0x0, sum = 1
2011 12:17:57.174494 10, 0x0, sum = 2
2012 12:17:57.174578 11, 0x0, sum = 3
2013 12:17:57.174645 12, 0x0, sum = 4
2014 12:17:57.177935 best_step = 10
2015 12:17:57.178018
2016 12:17:57.178083 ==
2017 12:17:57.180894 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 12:17:57.184235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 12:17:57.184320 ==
2020 12:17:57.187561 RX Vref Scan: 0
2021 12:17:57.187650
2022 12:17:57.191007 RX Vref 0 -> 0, step: 1
2023 12:17:57.191096
2024 12:17:57.191165 RX Delay -95 -> 252, step: 8
2025 12:17:57.197983 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2026 12:17:57.201541 iDelay=217, Bit 1, Center 84 (-23 ~ 192) 216
2027 12:17:57.205191 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2028 12:17:57.207743 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2029 12:17:57.211212 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2030 12:17:57.217810 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2031 12:17:57.221116 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2032 12:17:57.224596 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2033 12:17:57.228024 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2034 12:17:57.231066 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2035 12:17:57.237962 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2036 12:17:57.241250 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2037 12:17:57.244514 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2038 12:17:57.247749 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2039 12:17:57.254519 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
2040 12:17:57.258107 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2041 12:17:57.258243 ==
2042 12:17:57.261223 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 12:17:57.264644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 12:17:57.264799 ==
2045 12:17:57.267687 DQS Delay:
2046 12:17:57.267874 DQS0 = 0, DQS1 = 0
2047 12:17:57.268013 DQM Delay:
2048 12:17:57.271015 DQM0 = 87, DQM1 = 79
2049 12:17:57.271188 DQ Delay:
2050 12:17:57.274262 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2051 12:17:57.278134 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2052 12:17:57.281116 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2053 12:17:57.284550 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
2054 12:17:57.284849
2055 12:17:57.285085
2056 12:17:57.294716 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e17, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2057 12:17:57.295157 CH1 RK1: MR19=606, MR18=1E17
2058 12:17:57.301583 CH1_RK1: MR19=0x606, MR18=0x1E17, DQSOSC=402, MR23=63, INC=91, DEC=60
2059 12:17:57.304274 [RxdqsGatingPostProcess] freq 800
2060 12:17:57.311118 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2061 12:17:57.314452 Pre-setting of DQS Precalculation
2062 12:17:57.317793 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2063 12:17:57.327641 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2064 12:17:57.333962 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2065 12:17:57.334413
2066 12:17:57.334764
2067 12:17:57.337178 [Calibration Summary] 1600 Mbps
2068 12:17:57.337649 CH 0, Rank 0
2069 12:17:57.340773 SW Impedance : PASS
2070 12:17:57.341229 DUTY Scan : NO K
2071 12:17:57.344015 ZQ Calibration : PASS
2072 12:17:57.347303 Jitter Meter : NO K
2073 12:17:57.347755 CBT Training : PASS
2074 12:17:57.350569 Write leveling : PASS
2075 12:17:57.354131 RX DQS gating : PASS
2076 12:17:57.354558 RX DQ/DQS(RDDQC) : PASS
2077 12:17:57.357405 TX DQ/DQS : PASS
2078 12:17:57.360428 RX DATLAT : PASS
2079 12:17:57.360855 RX DQ/DQS(Engine): PASS
2080 12:17:57.364292 TX OE : NO K
2081 12:17:57.364718 All Pass.
2082 12:17:57.365058
2083 12:17:57.366880 CH 0, Rank 1
2084 12:17:57.367305 SW Impedance : PASS
2085 12:17:57.370205 DUTY Scan : NO K
2086 12:17:57.370628 ZQ Calibration : PASS
2087 12:17:57.373873 Jitter Meter : NO K
2088 12:17:57.377244 CBT Training : PASS
2089 12:17:57.377672 Write leveling : PASS
2090 12:17:57.380436 RX DQS gating : PASS
2091 12:17:57.383831 RX DQ/DQS(RDDQC) : PASS
2092 12:17:57.384259 TX DQ/DQS : PASS
2093 12:17:57.387055 RX DATLAT : PASS
2094 12:17:57.390422 RX DQ/DQS(Engine): PASS
2095 12:17:57.390847 TX OE : NO K
2096 12:17:57.393338 All Pass.
2097 12:17:57.393775
2098 12:17:57.394113 CH 1, Rank 0
2099 12:17:57.396994 SW Impedance : PASS
2100 12:17:57.397423 DUTY Scan : NO K
2101 12:17:57.400316 ZQ Calibration : PASS
2102 12:17:57.403520 Jitter Meter : NO K
2103 12:17:57.404016 CBT Training : PASS
2104 12:17:57.407041 Write leveling : PASS
2105 12:17:57.410191 RX DQS gating : PASS
2106 12:17:57.410618 RX DQ/DQS(RDDQC) : PASS
2107 12:17:57.413390 TX DQ/DQS : PASS
2108 12:17:57.416906 RX DATLAT : PASS
2109 12:17:57.417330 RX DQ/DQS(Engine): PASS
2110 12:17:57.420156 TX OE : NO K
2111 12:17:57.420584 All Pass.
2112 12:17:57.420920
2113 12:17:57.423362 CH 1, Rank 1
2114 12:17:57.423834 SW Impedance : PASS
2115 12:17:57.426834 DUTY Scan : NO K
2116 12:17:57.430043 ZQ Calibration : PASS
2117 12:17:57.430467 Jitter Meter : NO K
2118 12:17:57.433277 CBT Training : PASS
2119 12:17:57.437007 Write leveling : PASS
2120 12:17:57.437434 RX DQS gating : PASS
2121 12:17:57.439642 RX DQ/DQS(RDDQC) : PASS
2122 12:17:57.440322 TX DQ/DQS : PASS
2123 12:17:57.443161 RX DATLAT : PASS
2124 12:17:57.446710 RX DQ/DQS(Engine): PASS
2125 12:17:57.447129 TX OE : NO K
2126 12:17:57.449876 All Pass.
2127 12:17:57.450299
2128 12:17:57.450825 DramC Write-DBI off
2129 12:17:57.453619 PER_BANK_REFRESH: Hybrid Mode
2130 12:17:57.456450 TX_TRACKING: ON
2131 12:17:57.459859 [GetDramInforAfterCalByMRR] Vendor 6.
2132 12:17:57.463361 [GetDramInforAfterCalByMRR] Revision 606.
2133 12:17:57.466944 [GetDramInforAfterCalByMRR] Revision 2 0.
2134 12:17:57.467379 MR0 0x3b3b
2135 12:17:57.467914 MR8 0x5151
2136 12:17:57.472674 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2137 12:17:57.473065
2138 12:17:57.473317 MR0 0x3b3b
2139 12:17:57.473551 MR8 0x5151
2140 12:17:57.476198 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2141 12:17:57.476501
2142 12:17:57.485950 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2143 12:17:57.489306 [FAST_K] Save calibration result to emmc
2144 12:17:57.492590 [FAST_K] Save calibration result to emmc
2145 12:17:57.495699 dram_init: config_dvfs: 1
2146 12:17:57.499651 dramc_set_vcore_voltage set vcore to 662500
2147 12:17:57.502400 Read voltage for 1200, 2
2148 12:17:57.502505 Vio18 = 0
2149 12:17:57.502586 Vcore = 662500
2150 12:17:57.505725 Vdram = 0
2151 12:17:57.505865 Vddq = 0
2152 12:17:57.505980 Vmddr = 0
2153 12:17:57.512219 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2154 12:17:57.515873 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2155 12:17:57.519118 MEM_TYPE=3, freq_sel=15
2156 12:17:57.522343 sv_algorithm_assistance_LP4_1600
2157 12:17:57.525688 ============ PULL DRAM RESETB DOWN ============
2158 12:17:57.532364 ========== PULL DRAM RESETB DOWN end =========
2159 12:17:57.535903 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2160 12:17:57.538805 ===================================
2161 12:17:57.542351 LPDDR4 DRAM CONFIGURATION
2162 12:17:57.545874 ===================================
2163 12:17:57.545957 EX_ROW_EN[0] = 0x0
2164 12:17:57.549172 EX_ROW_EN[1] = 0x0
2165 12:17:57.549255 LP4Y_EN = 0x0
2166 12:17:57.551911 WORK_FSP = 0x0
2167 12:17:57.551998 WL = 0x4
2168 12:17:57.555289 RL = 0x4
2169 12:17:57.555373 BL = 0x2
2170 12:17:57.558748 RPST = 0x0
2171 12:17:57.562001 RD_PRE = 0x0
2172 12:17:57.562083 WR_PRE = 0x1
2173 12:17:57.565058 WR_PST = 0x0
2174 12:17:57.565140 DBI_WR = 0x0
2175 12:17:57.568638 DBI_RD = 0x0
2176 12:17:57.568721 OTF = 0x1
2177 12:17:57.571878 ===================================
2178 12:17:57.575106 ===================================
2179 12:17:57.578777 ANA top config
2180 12:17:57.581878 ===================================
2181 12:17:57.581989 DLL_ASYNC_EN = 0
2182 12:17:57.584839 ALL_SLAVE_EN = 0
2183 12:17:57.588461 NEW_RANK_MODE = 1
2184 12:17:57.592038 DLL_IDLE_MODE = 1
2185 12:17:57.592127 LP45_APHY_COMB_EN = 1
2186 12:17:57.595232 TX_ODT_DIS = 1
2187 12:17:57.598762 NEW_8X_MODE = 1
2188 12:17:57.601659 ===================================
2189 12:17:57.605434 ===================================
2190 12:17:57.608186 data_rate = 2400
2191 12:17:57.611563 CKR = 1
2192 12:17:57.615154 DQ_P2S_RATIO = 8
2193 12:17:57.618304 ===================================
2194 12:17:57.618442 CA_P2S_RATIO = 8
2195 12:17:57.621530 DQ_CA_OPEN = 0
2196 12:17:57.624758 DQ_SEMI_OPEN = 0
2197 12:17:57.628290 CA_SEMI_OPEN = 0
2198 12:17:57.631563 CA_FULL_RATE = 0
2199 12:17:57.634802 DQ_CKDIV4_EN = 0
2200 12:17:57.635004 CA_CKDIV4_EN = 0
2201 12:17:57.638044 CA_PREDIV_EN = 0
2202 12:17:57.641576 PH8_DLY = 17
2203 12:17:57.644972 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2204 12:17:57.648204 DQ_AAMCK_DIV = 4
2205 12:17:57.651826 CA_AAMCK_DIV = 4
2206 12:17:57.652252 CA_ADMCK_DIV = 4
2207 12:17:57.655037 DQ_TRACK_CA_EN = 0
2208 12:17:57.658394 CA_PICK = 1200
2209 12:17:57.661944 CA_MCKIO = 1200
2210 12:17:57.664697 MCKIO_SEMI = 0
2211 12:17:57.668163 PLL_FREQ = 2366
2212 12:17:57.671960 DQ_UI_PI_RATIO = 32
2213 12:17:57.672389 CA_UI_PI_RATIO = 0
2214 12:17:57.674558 ===================================
2215 12:17:57.678050 ===================================
2216 12:17:57.681440 memory_type:LPDDR4
2217 12:17:57.684819 GP_NUM : 10
2218 12:17:57.685262 SRAM_EN : 1
2219 12:17:57.687985 MD32_EN : 0
2220 12:17:57.691092 ===================================
2221 12:17:57.694345 [ANA_INIT] >>>>>>>>>>>>>>
2222 12:17:57.697912 <<<<<< [CONFIGURE PHASE]: ANA_TX
2223 12:17:57.700927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2224 12:17:57.704373 ===================================
2225 12:17:57.707536 data_rate = 2400,PCW = 0X5b00
2226 12:17:57.710858 ===================================
2227 12:17:57.714068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2228 12:17:57.717933 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2229 12:17:57.724252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2230 12:17:57.727875 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2231 12:17:57.730780 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2232 12:17:57.734305 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2233 12:17:57.737679 [ANA_INIT] flow start
2234 12:17:57.741208 [ANA_INIT] PLL >>>>>>>>
2235 12:17:57.741737 [ANA_INIT] PLL <<<<<<<<
2236 12:17:57.744113 [ANA_INIT] MIDPI >>>>>>>>
2237 12:17:57.747625 [ANA_INIT] MIDPI <<<<<<<<
2238 12:17:57.748107 [ANA_INIT] DLL >>>>>>>>
2239 12:17:57.750684 [ANA_INIT] DLL <<<<<<<<
2240 12:17:57.754129 [ANA_INIT] flow end
2241 12:17:57.757314 ============ LP4 DIFF to SE enter ============
2242 12:17:57.760358 ============ LP4 DIFF to SE exit ============
2243 12:17:57.763773 [ANA_INIT] <<<<<<<<<<<<<
2244 12:17:57.767073 [Flow] Enable top DCM control >>>>>
2245 12:17:57.770550 [Flow] Enable top DCM control <<<<<
2246 12:17:57.773640 Enable DLL master slave shuffle
2247 12:17:57.777006 ==============================================================
2248 12:17:57.780408 Gating Mode config
2249 12:17:57.787122 ==============================================================
2250 12:17:57.787262 Config description:
2251 12:17:57.796902 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2252 12:17:57.803350 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2253 12:17:57.809885 SELPH_MODE 0: By rank 1: By Phase
2254 12:17:57.813438 ==============================================================
2255 12:17:57.816835 GAT_TRACK_EN = 1
2256 12:17:57.820045 RX_GATING_MODE = 2
2257 12:17:57.823165 RX_GATING_TRACK_MODE = 2
2258 12:17:57.826749 SELPH_MODE = 1
2259 12:17:57.829969 PICG_EARLY_EN = 1
2260 12:17:57.833243 VALID_LAT_VALUE = 1
2261 12:17:57.836755 ==============================================================
2262 12:17:57.840118 Enter into Gating configuration >>>>
2263 12:17:57.843120 Exit from Gating configuration <<<<
2264 12:17:57.846280 Enter into DVFS_PRE_config >>>>>
2265 12:17:57.860228 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2266 12:17:57.863392 Exit from DVFS_PRE_config <<<<<
2267 12:17:57.866476 Enter into PICG configuration >>>>
2268 12:17:57.866580 Exit from PICG configuration <<<<
2269 12:17:57.869782 [RX_INPUT] configuration >>>>>
2270 12:17:57.873386 [RX_INPUT] configuration <<<<<
2271 12:17:57.879772 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2272 12:17:57.883130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2273 12:17:57.889556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2274 12:17:57.896172 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2275 12:17:57.902734 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2276 12:17:57.909567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2277 12:17:57.913033 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2278 12:17:57.916177 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2279 12:17:57.923018 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2280 12:17:57.925990 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2281 12:17:57.929403 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2282 12:17:57.932748 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2283 12:17:57.936157 ===================================
2284 12:17:57.939464 LPDDR4 DRAM CONFIGURATION
2285 12:17:57.942696 ===================================
2286 12:17:57.946040 EX_ROW_EN[0] = 0x0
2287 12:17:57.946123 EX_ROW_EN[1] = 0x0
2288 12:17:57.949140 LP4Y_EN = 0x0
2289 12:17:57.949223 WORK_FSP = 0x0
2290 12:17:57.953148 WL = 0x4
2291 12:17:57.953232 RL = 0x4
2292 12:17:57.955730 BL = 0x2
2293 12:17:57.955845 RPST = 0x0
2294 12:17:57.959259 RD_PRE = 0x0
2295 12:17:57.959342 WR_PRE = 0x1
2296 12:17:57.962575 WR_PST = 0x0
2297 12:17:57.962658 DBI_WR = 0x0
2298 12:17:57.966220 DBI_RD = 0x0
2299 12:17:57.966302 OTF = 0x1
2300 12:17:57.969081 ===================================
2301 12:17:57.975744 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2302 12:17:57.979061 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2303 12:17:57.982479 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 12:17:57.985600 ===================================
2305 12:17:57.988903 LPDDR4 DRAM CONFIGURATION
2306 12:17:57.992384 ===================================
2307 12:17:57.995944 EX_ROW_EN[0] = 0x10
2308 12:17:57.996040 EX_ROW_EN[1] = 0x0
2309 12:17:57.998685 LP4Y_EN = 0x0
2310 12:17:57.998762 WORK_FSP = 0x0
2311 12:17:58.002372 WL = 0x4
2312 12:17:58.002459 RL = 0x4
2313 12:17:58.005347 BL = 0x2
2314 12:17:58.005428 RPST = 0x0
2315 12:17:58.008932 RD_PRE = 0x0
2316 12:17:58.009013 WR_PRE = 0x1
2317 12:17:58.012271 WR_PST = 0x0
2318 12:17:58.012353 DBI_WR = 0x0
2319 12:17:58.015253 DBI_RD = 0x0
2320 12:17:58.015335 OTF = 0x1
2321 12:17:58.018713 ===================================
2322 12:17:58.025075 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2323 12:17:58.025184 ==
2324 12:17:58.028488 Dram Type= 6, Freq= 0, CH_0, rank 0
2325 12:17:58.035031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2326 12:17:58.035113 ==
2327 12:17:58.035177 [Duty_Offset_Calibration]
2328 12:17:58.038655 B0:1 B1:-1 CA:0
2329 12:17:58.038736
2330 12:17:58.041849 [DutyScan_Calibration_Flow] k_type=0
2331 12:17:58.051176
2332 12:17:58.051259 ==CLK 0==
2333 12:17:58.054477 Final CLK duty delay cell = 0
2334 12:17:58.057477 [0] MAX Duty = 5125%(X100), DQS PI = 24
2335 12:17:58.061042 [0] MIN Duty = 4907%(X100), DQS PI = 6
2336 12:17:58.064437 [0] AVG Duty = 5016%(X100)
2337 12:17:58.064522
2338 12:17:58.067226 CH0 CLK Duty spec in!! Max-Min= 218%
2339 12:17:58.070820 [DutyScan_Calibration_Flow] ====Done====
2340 12:17:58.070903
2341 12:17:58.073913 [DutyScan_Calibration_Flow] k_type=1
2342 12:17:58.089618
2343 12:17:58.089749 ==DQS 0 ==
2344 12:17:58.092916 Final DQS duty delay cell = -4
2345 12:17:58.095651 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2346 12:17:58.099299 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2347 12:17:58.102419 [-4] AVG Duty = 4968%(X100)
2348 12:17:58.102502
2349 12:17:58.102565 ==DQS 1 ==
2350 12:17:58.105713 Final DQS duty delay cell = 0
2351 12:17:58.109195 [0] MAX Duty = 5124%(X100), DQS PI = 2
2352 12:17:58.112249 [0] MIN Duty = 5000%(X100), DQS PI = 24
2353 12:17:58.115539 [0] AVG Duty = 5062%(X100)
2354 12:17:58.115624
2355 12:17:58.119005 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2356 12:17:58.119081
2357 12:17:58.122206 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2358 12:17:58.125758 [DutyScan_Calibration_Flow] ====Done====
2359 12:17:58.125834
2360 12:17:58.128806 [DutyScan_Calibration_Flow] k_type=3
2361 12:17:58.147286
2362 12:17:58.147443 ==DQM 0 ==
2363 12:17:58.150726 Final DQM duty delay cell = 0
2364 12:17:58.153434 [0] MAX Duty = 5062%(X100), DQS PI = 20
2365 12:17:58.157001 [0] MIN Duty = 4875%(X100), DQS PI = 8
2366 12:17:58.160027 [0] AVG Duty = 4968%(X100)
2367 12:17:58.160110
2368 12:17:58.160198 ==DQM 1 ==
2369 12:17:58.163885 Final DQM duty delay cell = 4
2370 12:17:58.166988 [4] MAX Duty = 5187%(X100), DQS PI = 32
2371 12:17:58.170114 [4] MIN Duty = 5000%(X100), DQS PI = 24
2372 12:17:58.173799 [4] AVG Duty = 5093%(X100)
2373 12:17:58.173919
2374 12:17:58.176945 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2375 12:17:58.177031
2376 12:17:58.180022 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2377 12:17:58.183448 [DutyScan_Calibration_Flow] ====Done====
2378 12:17:58.183532
2379 12:17:58.186659 [DutyScan_Calibration_Flow] k_type=2
2380 12:17:58.202160
2381 12:17:58.202265 ==DQ 0 ==
2382 12:17:58.204953 Final DQ duty delay cell = -4
2383 12:17:58.208605 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2384 12:17:58.211705 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2385 12:17:58.215114 [-4] AVG Duty = 4969%(X100)
2386 12:17:58.215275
2387 12:17:58.215406 ==DQ 1 ==
2388 12:17:58.218377 Final DQ duty delay cell = -4
2389 12:17:58.221495 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2390 12:17:58.224837 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2391 12:17:58.228388 [-4] AVG Duty = 4938%(X100)
2392 12:17:58.228495
2393 12:17:58.231494 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2394 12:17:58.231598
2395 12:17:58.234937 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2396 12:17:58.238531 [DutyScan_Calibration_Flow] ====Done====
2397 12:17:58.238646 ==
2398 12:17:58.241840 Dram Type= 6, Freq= 0, CH_1, rank 0
2399 12:17:58.244826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2400 12:17:58.244923 ==
2401 12:17:58.248364 [Duty_Offset_Calibration]
2402 12:17:58.251601 B0:-1 B1:1 CA:1
2403 12:17:58.251750
2404 12:17:58.254667 [DutyScan_Calibration_Flow] k_type=0
2405 12:17:58.262772
2406 12:17:58.262958 ==CLK 0==
2407 12:17:58.266243 Final CLK duty delay cell = 0
2408 12:17:58.269674 [0] MAX Duty = 5156%(X100), DQS PI = 20
2409 12:17:58.273033 [0] MIN Duty = 4969%(X100), DQS PI = 62
2410 12:17:58.273209 [0] AVG Duty = 5062%(X100)
2411 12:17:58.276318
2412 12:17:58.279610 CH1 CLK Duty spec in!! Max-Min= 187%
2413 12:17:58.282506 [DutyScan_Calibration_Flow] ====Done====
2414 12:17:58.282838
2415 12:17:58.285990 [DutyScan_Calibration_Flow] k_type=1
2416 12:17:58.302433
2417 12:17:58.303209 ==DQS 0 ==
2418 12:17:58.306033 Final DQS duty delay cell = 0
2419 12:17:58.308974 [0] MAX Duty = 5125%(X100), DQS PI = 48
2420 12:17:58.312466 [0] MIN Duty = 4907%(X100), DQS PI = 6
2421 12:17:58.315592 [0] AVG Duty = 5016%(X100)
2422 12:17:58.316129
2423 12:17:58.316509 ==DQS 1 ==
2424 12:17:58.318645 Final DQS duty delay cell = 0
2425 12:17:58.322608 [0] MAX Duty = 5094%(X100), DQS PI = 12
2426 12:17:58.325391 [0] MIN Duty = 4969%(X100), DQS PI = 58
2427 12:17:58.328952 [0] AVG Duty = 5031%(X100)
2428 12:17:58.329264
2429 12:17:58.332168 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2430 12:17:58.332394
2431 12:17:58.335306 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2432 12:17:58.338612 [DutyScan_Calibration_Flow] ====Done====
2433 12:17:58.338806
2434 12:17:58.341575 [DutyScan_Calibration_Flow] k_type=3
2435 12:17:58.358079
2436 12:17:58.358236 ==DQM 0 ==
2437 12:17:58.361060 Final DQM duty delay cell = -4
2438 12:17:58.364318 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2439 12:17:58.367494 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2440 12:17:58.370708 [-4] AVG Duty = 4969%(X100)
2441 12:17:58.370786
2442 12:17:58.370876 ==DQM 1 ==
2443 12:17:58.373906 Final DQM duty delay cell = 0
2444 12:17:58.377692 [0] MAX Duty = 5156%(X100), DQS PI = 4
2445 12:17:58.380560 [0] MIN Duty = 4969%(X100), DQS PI = 28
2446 12:17:58.384084 [0] AVG Duty = 5062%(X100)
2447 12:17:58.384173
2448 12:17:58.387505 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2449 12:17:58.387618
2450 12:17:58.390480 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2451 12:17:58.393886 [DutyScan_Calibration_Flow] ====Done====
2452 12:17:58.393967
2453 12:17:58.396943 [DutyScan_Calibration_Flow] k_type=2
2454 12:17:58.414315
2455 12:17:58.414404 ==DQ 0 ==
2456 12:17:58.417777 Final DQ duty delay cell = 0
2457 12:17:58.421344 [0] MAX Duty = 5187%(X100), DQS PI = 32
2458 12:17:58.424257 [0] MIN Duty = 4876%(X100), DQS PI = 8
2459 12:17:58.424341 [0] AVG Duty = 5031%(X100)
2460 12:17:58.424425
2461 12:17:58.427469 ==DQ 1 ==
2462 12:17:58.430772 Final DQ duty delay cell = 0
2463 12:17:58.434461 [0] MAX Duty = 5124%(X100), DQS PI = 10
2464 12:17:58.437859 [0] MIN Duty = 4969%(X100), DQS PI = 60
2465 12:17:58.437949 [0] AVG Duty = 5046%(X100)
2466 12:17:58.438031
2467 12:17:58.441132 CH1 DQ 0 Duty spec in!! Max-Min= 311%
2468 12:17:58.441210
2469 12:17:58.444532 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2470 12:17:58.450821 [DutyScan_Calibration_Flow] ====Done====
2471 12:17:58.454299 nWR fixed to 30
2472 12:17:58.454378 [ModeRegInit_LP4] CH0 RK0
2473 12:17:58.457435 [ModeRegInit_LP4] CH0 RK1
2474 12:17:58.461017 [ModeRegInit_LP4] CH1 RK0
2475 12:17:58.461107 [ModeRegInit_LP4] CH1 RK1
2476 12:17:58.464505 match AC timing 7
2477 12:17:58.467156 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2478 12:17:58.473896 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2479 12:17:58.477467 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2480 12:17:58.480527 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2481 12:17:58.487150 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2482 12:17:58.487231 ==
2483 12:17:58.490605 Dram Type= 6, Freq= 0, CH_0, rank 0
2484 12:17:58.493798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2485 12:17:58.493879 ==
2486 12:17:58.500348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2487 12:17:58.507311 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2488 12:17:58.514235 [CA 0] Center 39 (9~70) winsize 62
2489 12:17:58.517319 [CA 1] Center 39 (9~70) winsize 62
2490 12:17:58.521252 [CA 2] Center 35 (5~66) winsize 62
2491 12:17:58.523950 [CA 3] Center 35 (5~65) winsize 61
2492 12:17:58.527342 [CA 4] Center 33 (3~64) winsize 62
2493 12:17:58.530634 [CA 5] Center 33 (4~63) winsize 60
2494 12:17:58.530732
2495 12:17:58.533844 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2496 12:17:58.533949
2497 12:17:58.537407 [CATrainingPosCal] consider 1 rank data
2498 12:17:58.540472 u2DelayCellTimex100 = 270/100 ps
2499 12:17:58.544030 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2500 12:17:58.550473 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2501 12:17:58.553959 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2502 12:17:58.556994 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2503 12:17:58.560547 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2504 12:17:58.563940 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2505 12:17:58.564048
2506 12:17:58.566876 CA PerBit enable=1, Macro0, CA PI delay=33
2507 12:17:58.566975
2508 12:17:58.570320 [CBTSetCACLKResult] CA Dly = 33
2509 12:17:58.573945 CS Dly: 8 (0~39)
2510 12:17:58.574048 ==
2511 12:17:58.576931 Dram Type= 6, Freq= 0, CH_0, rank 1
2512 12:17:58.580250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 12:17:58.580357 ==
2514 12:17:58.586732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2515 12:17:58.590000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2516 12:17:58.600124 [CA 0] Center 39 (9~70) winsize 62
2517 12:17:58.603549 [CA 1] Center 39 (9~70) winsize 62
2518 12:17:58.606830 [CA 2] Center 35 (5~66) winsize 62
2519 12:17:58.610231 [CA 3] Center 34 (4~65) winsize 62
2520 12:17:58.613215 [CA 4] Center 33 (3~64) winsize 62
2521 12:17:58.617032 [CA 5] Center 33 (3~63) winsize 61
2522 12:17:58.617136
2523 12:17:58.619914 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2524 12:17:58.620053
2525 12:17:58.623226 [CATrainingPosCal] consider 2 rank data
2526 12:17:58.626571 u2DelayCellTimex100 = 270/100 ps
2527 12:17:58.629878 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2528 12:17:58.633516 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 12:17:58.640078 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2530 12:17:58.643194 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2531 12:17:58.646414 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2532 12:17:58.650074 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2533 12:17:58.650155
2534 12:17:58.653277 CA PerBit enable=1, Macro0, CA PI delay=33
2535 12:17:58.653384
2536 12:17:58.656895 [CBTSetCACLKResult] CA Dly = 33
2537 12:17:58.656977 CS Dly: 9 (0~41)
2538 12:17:58.657041
2539 12:17:58.660345 ----->DramcWriteLeveling(PI) begin...
2540 12:17:58.662803 ==
2541 12:17:58.666543 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 12:17:58.669574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 12:17:58.669682 ==
2544 12:17:58.673053 Write leveling (Byte 0): 33 => 33
2545 12:17:58.676495 Write leveling (Byte 1): 28 => 28
2546 12:17:58.679636 DramcWriteLeveling(PI) end<-----
2547 12:17:58.679780
2548 12:17:58.679847 ==
2549 12:17:58.682877 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 12:17:58.686465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 12:17:58.686554 ==
2552 12:17:58.689732 [Gating] SW mode calibration
2553 12:17:58.696206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2554 12:17:58.702639 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2555 12:17:58.705665 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2556 12:17:58.709426 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
2557 12:17:58.715605 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2558 12:17:58.718934 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2559 12:17:58.722455 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2560 12:17:58.729186 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2561 12:17:58.732358 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2562 12:17:58.736010 0 15 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
2563 12:17:58.742589 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
2564 12:17:58.745944 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2565 12:17:58.749176 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2566 12:17:58.755463 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2567 12:17:58.758760 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2568 12:17:58.762074 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2569 12:17:58.768818 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2570 12:17:58.772246 1 0 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
2571 12:17:58.775573 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2572 12:17:58.778876 1 1 4 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
2573 12:17:58.785362 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 12:17:58.789308 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 12:17:58.792301 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2576 12:17:58.798696 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 12:17:58.802072 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 12:17:58.805575 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2579 12:17:58.812235 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2580 12:17:58.815289 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 12:17:58.818901 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 12:17:58.825111 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2583 12:17:58.828405 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2584 12:17:58.832069 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2585 12:17:58.838540 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2586 12:17:58.842033 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2587 12:17:58.845183 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 12:17:58.852008 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 12:17:58.855035 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 12:17:58.858231 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 12:17:58.865081 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 12:17:58.868178 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 12:17:58.871652 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 12:17:58.878269 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2595 12:17:58.881646 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2596 12:17:58.885093 Total UI for P1: 0, mck2ui 16
2597 12:17:58.888044 best dqsien dly found for B0: ( 1, 3, 28)
2598 12:17:58.891357 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 12:17:58.894875 Total UI for P1: 0, mck2ui 16
2600 12:17:58.897984 best dqsien dly found for B1: ( 1, 4, 0)
2601 12:17:58.901686 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2602 12:17:58.904830 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2603 12:17:58.904909
2604 12:17:58.911547 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2605 12:17:58.914525 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2606 12:17:58.914603 [Gating] SW calibration Done
2607 12:17:58.918118 ==
2608 12:17:58.918198 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 12:17:58.924684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 12:17:58.924763 ==
2611 12:17:58.924851 RX Vref Scan: 0
2612 12:17:58.924933
2613 12:17:58.928087 RX Vref 0 -> 0, step: 1
2614 12:17:58.928168
2615 12:17:58.931601 RX Delay -40 -> 252, step: 8
2616 12:17:58.934494 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2617 12:17:58.937767 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2618 12:17:58.941071 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2619 12:17:58.948512 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2620 12:17:58.951263 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2621 12:17:58.954662 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2622 12:17:58.957681 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2623 12:17:58.960987 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2624 12:17:58.968204 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2625 12:17:58.971466 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2626 12:17:58.974448 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2627 12:17:58.977932 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2628 12:17:58.981216 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2629 12:17:58.988104 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2630 12:17:58.991011 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2631 12:17:58.994651 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2632 12:17:58.994734 ==
2633 12:17:58.997500 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 12:17:59.001544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 12:17:59.004480 ==
2636 12:17:59.004565 DQS Delay:
2637 12:17:59.004651 DQS0 = 0, DQS1 = 0
2638 12:17:59.007820 DQM Delay:
2639 12:17:59.007906 DQM0 = 119, DQM1 = 107
2640 12:17:59.011119 DQ Delay:
2641 12:17:59.014162 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2642 12:17:59.017665 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2643 12:17:59.020724 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =103
2644 12:17:59.023914 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2645 12:17:59.024007
2646 12:17:59.024073
2647 12:17:59.024134 ==
2648 12:17:59.027191 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 12:17:59.030426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 12:17:59.030519 ==
2651 12:17:59.030585
2652 12:17:59.033944
2653 12:17:59.034020 TX Vref Scan disable
2654 12:17:59.037312 == TX Byte 0 ==
2655 12:17:59.040856 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2656 12:17:59.043998 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2657 12:17:59.047061 == TX Byte 1 ==
2658 12:17:59.050442 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2659 12:17:59.054259 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2660 12:17:59.054345 ==
2661 12:17:59.057164 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 12:17:59.064144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 12:17:59.064232 ==
2664 12:17:59.074791 TX Vref=22, minBit 13, minWin=25, winSum=417
2665 12:17:59.078092 TX Vref=24, minBit 13, minWin=25, winSum=421
2666 12:17:59.081552 TX Vref=26, minBit 8, minWin=26, winSum=431
2667 12:17:59.084544 TX Vref=28, minBit 5, minWin=26, winSum=434
2668 12:17:59.088024 TX Vref=30, minBit 10, minWin=26, winSum=434
2669 12:17:59.094455 TX Vref=32, minBit 5, minWin=26, winSum=432
2670 12:17:59.097700 [TxChooseVref] Worse bit 5, Min win 26, Win sum 434, Final Vref 28
2671 12:17:59.097786
2672 12:17:59.100896 Final TX Range 1 Vref 28
2673 12:17:59.100983
2674 12:17:59.101069 ==
2675 12:17:59.104442 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 12:17:59.107828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 12:17:59.111061 ==
2678 12:17:59.111147
2679 12:17:59.111233
2680 12:17:59.111315 TX Vref Scan disable
2681 12:17:59.114433 == TX Byte 0 ==
2682 12:17:59.117977 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2683 12:17:59.124317 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2684 12:17:59.124404 == TX Byte 1 ==
2685 12:17:59.128075 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2686 12:17:59.134760 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2687 12:17:59.134846
2688 12:17:59.134933 [DATLAT]
2689 12:17:59.135033 Freq=1200, CH0 RK0
2690 12:17:59.135098
2691 12:17:59.137688 DATLAT Default: 0xd
2692 12:17:59.141130 0, 0xFFFF, sum = 0
2693 12:17:59.141218 1, 0xFFFF, sum = 0
2694 12:17:59.144166 2, 0xFFFF, sum = 0
2695 12:17:59.144254 3, 0xFFFF, sum = 0
2696 12:17:59.147969 4, 0xFFFF, sum = 0
2697 12:17:59.148057 5, 0xFFFF, sum = 0
2698 12:17:59.150627 6, 0xFFFF, sum = 0
2699 12:17:59.150730 7, 0xFFFF, sum = 0
2700 12:17:59.154241 8, 0xFFFF, sum = 0
2701 12:17:59.154328 9, 0xFFFF, sum = 0
2702 12:17:59.157573 10, 0xFFFF, sum = 0
2703 12:17:59.157660 11, 0xFFFF, sum = 0
2704 12:17:59.161097 12, 0x0, sum = 1
2705 12:17:59.161185 13, 0x0, sum = 2
2706 12:17:59.164910 14, 0x0, sum = 3
2707 12:17:59.164997 15, 0x0, sum = 4
2708 12:17:59.167297 best_step = 13
2709 12:17:59.167382
2710 12:17:59.167468 ==
2711 12:17:59.170991 Dram Type= 6, Freq= 0, CH_0, rank 0
2712 12:17:59.174352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2713 12:17:59.174438 ==
2714 12:17:59.174524 RX Vref Scan: 1
2715 12:17:59.177765
2716 12:17:59.177851 Set Vref Range= 32 -> 127
2717 12:17:59.177938
2718 12:17:59.180699 RX Vref 32 -> 127, step: 1
2719 12:17:59.180784
2720 12:17:59.184553 RX Delay -21 -> 252, step: 4
2721 12:17:59.184638
2722 12:17:59.187603 Set Vref, RX VrefLevel [Byte0]: 32
2723 12:17:59.191229 [Byte1]: 32
2724 12:17:59.191314
2725 12:17:59.193864 Set Vref, RX VrefLevel [Byte0]: 33
2726 12:17:59.197073 [Byte1]: 33
2727 12:17:59.201537
2728 12:17:59.201622 Set Vref, RX VrefLevel [Byte0]: 34
2729 12:17:59.204623 [Byte1]: 34
2730 12:17:59.209175
2731 12:17:59.209262 Set Vref, RX VrefLevel [Byte0]: 35
2732 12:17:59.212492 [Byte1]: 35
2733 12:17:59.217225
2734 12:17:59.217310 Set Vref, RX VrefLevel [Byte0]: 36
2735 12:17:59.220301 [Byte1]: 36
2736 12:17:59.224954
2737 12:17:59.225039 Set Vref, RX VrefLevel [Byte0]: 37
2738 12:17:59.228453 [Byte1]: 37
2739 12:17:59.232818
2740 12:17:59.232904 Set Vref, RX VrefLevel [Byte0]: 38
2741 12:17:59.236046 [Byte1]: 38
2742 12:17:59.240612
2743 12:17:59.240698 Set Vref, RX VrefLevel [Byte0]: 39
2744 12:17:59.244301 [Byte1]: 39
2745 12:17:59.248612
2746 12:17:59.248698 Set Vref, RX VrefLevel [Byte0]: 40
2747 12:17:59.252305 [Byte1]: 40
2748 12:17:59.256461
2749 12:17:59.256547 Set Vref, RX VrefLevel [Byte0]: 41
2750 12:17:59.260221 [Byte1]: 41
2751 12:17:59.264792
2752 12:17:59.264883 Set Vref, RX VrefLevel [Byte0]: 42
2753 12:17:59.267892 [Byte1]: 42
2754 12:17:59.272746
2755 12:17:59.272828 Set Vref, RX VrefLevel [Byte0]: 43
2756 12:17:59.276214 [Byte1]: 43
2757 12:17:59.280398
2758 12:17:59.280481 Set Vref, RX VrefLevel [Byte0]: 44
2759 12:17:59.283594 [Byte1]: 44
2760 12:17:59.288581
2761 12:17:59.288668 Set Vref, RX VrefLevel [Byte0]: 45
2762 12:17:59.291944 [Byte1]: 45
2763 12:17:59.296443
2764 12:17:59.296526 Set Vref, RX VrefLevel [Byte0]: 46
2765 12:17:59.299924 [Byte1]: 46
2766 12:17:59.304756
2767 12:17:59.304839 Set Vref, RX VrefLevel [Byte0]: 47
2768 12:17:59.307536 [Byte1]: 47
2769 12:17:59.312340
2770 12:17:59.312422 Set Vref, RX VrefLevel [Byte0]: 48
2771 12:17:59.315407 [Byte1]: 48
2772 12:17:59.319937
2773 12:17:59.320019 Set Vref, RX VrefLevel [Byte0]: 49
2774 12:17:59.323396 [Byte1]: 49
2775 12:17:59.328786
2776 12:17:59.328868 Set Vref, RX VrefLevel [Byte0]: 50
2777 12:17:59.331270 [Byte1]: 50
2778 12:17:59.335701
2779 12:17:59.335827 Set Vref, RX VrefLevel [Byte0]: 51
2780 12:17:59.339487 [Byte1]: 51
2781 12:17:59.343980
2782 12:17:59.344063 Set Vref, RX VrefLevel [Byte0]: 52
2783 12:17:59.347035 [Byte1]: 52
2784 12:17:59.351552
2785 12:17:59.351660 Set Vref, RX VrefLevel [Byte0]: 53
2786 12:17:59.354972 [Byte1]: 53
2787 12:17:59.359974
2788 12:17:59.360056 Set Vref, RX VrefLevel [Byte0]: 54
2789 12:17:59.363127 [Byte1]: 54
2790 12:17:59.367512
2791 12:17:59.367594 Set Vref, RX VrefLevel [Byte0]: 55
2792 12:17:59.370935 [Byte1]: 55
2793 12:17:59.375380
2794 12:17:59.375462 Set Vref, RX VrefLevel [Byte0]: 56
2795 12:17:59.378888 [Byte1]: 56
2796 12:17:59.383605
2797 12:17:59.383714 Set Vref, RX VrefLevel [Byte0]: 57
2798 12:17:59.386789 [Byte1]: 57
2799 12:17:59.391350
2800 12:17:59.391432 Set Vref, RX VrefLevel [Byte0]: 58
2801 12:17:59.394611 [Byte1]: 58
2802 12:17:59.399654
2803 12:17:59.399782 Set Vref, RX VrefLevel [Byte0]: 59
2804 12:17:59.402548 [Byte1]: 59
2805 12:17:59.407534
2806 12:17:59.407616 Set Vref, RX VrefLevel [Byte0]: 60
2807 12:17:59.410373 [Byte1]: 60
2808 12:17:59.415256
2809 12:17:59.415365 Set Vref, RX VrefLevel [Byte0]: 61
2810 12:17:59.418530 [Byte1]: 61
2811 12:17:59.423212
2812 12:17:59.423294 Set Vref, RX VrefLevel [Byte0]: 62
2813 12:17:59.426374 [Byte1]: 62
2814 12:17:59.430999
2815 12:17:59.431079 Set Vref, RX VrefLevel [Byte0]: 63
2816 12:17:59.434065 [Byte1]: 63
2817 12:17:59.438820
2818 12:17:59.438898 Set Vref, RX VrefLevel [Byte0]: 64
2819 12:17:59.442389 [Byte1]: 64
2820 12:17:59.446735
2821 12:17:59.446815 Set Vref, RX VrefLevel [Byte0]: 65
2822 12:17:59.450043 [Byte1]: 65
2823 12:17:59.454874
2824 12:17:59.458028 Set Vref, RX VrefLevel [Byte0]: 66
2825 12:17:59.461556 [Byte1]: 66
2826 12:17:59.461645
2827 12:17:59.464693 Set Vref, RX VrefLevel [Byte0]: 67
2828 12:17:59.467802 [Byte1]: 67
2829 12:17:59.467884
2830 12:17:59.471049 Set Vref, RX VrefLevel [Byte0]: 68
2831 12:17:59.474162 [Byte1]: 68
2832 12:17:59.478774
2833 12:17:59.478884 Set Vref, RX VrefLevel [Byte0]: 69
2834 12:17:59.481827 [Byte1]: 69
2835 12:17:59.486550
2836 12:17:59.486628 Set Vref, RX VrefLevel [Byte0]: 70
2837 12:17:59.489532 [Byte1]: 70
2838 12:17:59.494472
2839 12:17:59.494552 Set Vref, RX VrefLevel [Byte0]: 71
2840 12:17:59.497601 [Byte1]: 71
2841 12:17:59.502432
2842 12:17:59.502513 Set Vref, RX VrefLevel [Byte0]: 72
2843 12:17:59.505601 [Byte1]: 72
2844 12:17:59.510523
2845 12:17:59.510605 Set Vref, RX VrefLevel [Byte0]: 73
2846 12:17:59.513942 [Byte1]: 73
2847 12:17:59.518046
2848 12:17:59.518122 Set Vref, RX VrefLevel [Byte0]: 74
2849 12:17:59.521843 [Byte1]: 74
2850 12:17:59.525977
2851 12:17:59.526116 Set Vref, RX VrefLevel [Byte0]: 75
2852 12:17:59.529103 [Byte1]: 75
2853 12:17:59.534128
2854 12:17:59.534238 Set Vref, RX VrefLevel [Byte0]: 76
2855 12:17:59.537321 [Byte1]: 76
2856 12:17:59.541897
2857 12:17:59.541977 Set Vref, RX VrefLevel [Byte0]: 77
2858 12:17:59.545162 [Byte1]: 77
2859 12:17:59.549786
2860 12:17:59.549871 Set Vref, RX VrefLevel [Byte0]: 78
2861 12:17:59.553031 [Byte1]: 78
2862 12:17:59.557895
2863 12:17:59.557972 Final RX Vref Byte 0 = 60 to rank0
2864 12:17:59.561000 Final RX Vref Byte 1 = 48 to rank0
2865 12:17:59.564464 Final RX Vref Byte 0 = 60 to rank1
2866 12:17:59.567891 Final RX Vref Byte 1 = 48 to rank1==
2867 12:17:59.571321 Dram Type= 6, Freq= 0, CH_0, rank 0
2868 12:17:59.577751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 12:17:59.577836 ==
2870 12:17:59.577900 DQS Delay:
2871 12:17:59.580741 DQS0 = 0, DQS1 = 0
2872 12:17:59.580849 DQM Delay:
2873 12:17:59.580934 DQM0 = 119, DQM1 = 106
2874 12:17:59.584101 DQ Delay:
2875 12:17:59.587312 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2876 12:17:59.590800 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
2877 12:17:59.594014 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =100
2878 12:17:59.597390 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2879 12:17:59.597463
2880 12:17:59.597531
2881 12:17:59.607444 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps
2882 12:17:59.607523 CH0 RK0: MR19=403, MR18=12FE
2883 12:17:59.613796 CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26
2884 12:17:59.613902
2885 12:17:59.617283 ----->DramcWriteLeveling(PI) begin...
2886 12:17:59.617364 ==
2887 12:17:59.620608 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 12:17:59.627180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 12:17:59.627263 ==
2890 12:17:59.630488 Write leveling (Byte 0): 32 => 32
2891 12:17:59.630566 Write leveling (Byte 1): 30 => 30
2892 12:17:59.633762 DramcWriteLeveling(PI) end<-----
2893 12:17:59.633863
2894 12:17:59.637265 ==
2895 12:17:59.637346 Dram Type= 6, Freq= 0, CH_0, rank 1
2896 12:17:59.643655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2897 12:17:59.643778 ==
2898 12:17:59.646994 [Gating] SW mode calibration
2899 12:17:59.653775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2900 12:17:59.657345 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2901 12:17:59.663981 0 15 0 | B1->B0 | 2322 3131 | 1 0 | (0 0) (0 0)
2902 12:17:59.667259 0 15 4 | B1->B0 | 3130 3434 | 1 1 | (1 1) (1 1)
2903 12:17:59.671180 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 12:17:59.677340 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 12:17:59.680396 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 12:17:59.683576 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 12:17:59.690266 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 12:17:59.693441 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2909 12:17:59.696707 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2910 12:17:59.703681 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 12:17:59.706998 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 12:17:59.710677 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 12:17:59.716810 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 12:17:59.720588 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 12:17:59.723640 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 12:17:59.727172 1 0 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
2917 12:17:59.733368 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2918 12:17:59.736717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 12:17:59.740122 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 12:17:59.746855 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 12:17:59.750438 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 12:17:59.753891 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 12:17:59.760459 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2924 12:17:59.763873 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2925 12:17:59.766512 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2926 12:17:59.773739 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 12:17:59.777232 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 12:17:59.780018 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 12:17:59.786557 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:17:59.789831 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:17:59.793724 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:17:59.800522 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 12:17:59.803236 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 12:17:59.806690 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 12:17:59.813103 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 12:17:59.816345 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 12:17:59.819736 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 12:17:59.826459 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 12:17:59.829933 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 12:17:59.832972 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2941 12:17:59.839562 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2942 12:17:59.839646 Total UI for P1: 0, mck2ui 16
2943 12:17:59.846403 best dqsien dly found for B0: ( 1, 3, 28)
2944 12:17:59.849716 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 12:17:59.852772 Total UI for P1: 0, mck2ui 16
2946 12:17:59.856210 best dqsien dly found for B1: ( 1, 4, 0)
2947 12:17:59.859982 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2948 12:17:59.863191 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2949 12:17:59.863270
2950 12:17:59.866775 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2951 12:17:59.869826 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2952 12:17:59.873182 [Gating] SW calibration Done
2953 12:17:59.873264 ==
2954 12:17:59.876652 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 12:17:59.879870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 12:17:59.879975 ==
2957 12:17:59.882792 RX Vref Scan: 0
2958 12:17:59.882893
2959 12:17:59.886208 RX Vref 0 -> 0, step: 1
2960 12:17:59.886306
2961 12:17:59.886404 RX Delay -40 -> 252, step: 8
2962 12:17:59.892543 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2963 12:17:59.895851 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2964 12:17:59.899403 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2965 12:17:59.902465 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2966 12:17:59.906065 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2967 12:17:59.912713 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2968 12:17:59.916078 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2969 12:17:59.919559 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2970 12:17:59.922511 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2971 12:17:59.926177 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2972 12:17:59.932681 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2973 12:17:59.936099 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2974 12:17:59.939598 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2975 12:17:59.942699 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2976 12:17:59.945825 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2977 12:17:59.952499 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2978 12:17:59.952581 ==
2979 12:17:59.955950 Dram Type= 6, Freq= 0, CH_0, rank 1
2980 12:17:59.959082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2981 12:17:59.959160 ==
2982 12:17:59.959272 DQS Delay:
2983 12:17:59.962687 DQS0 = 0, DQS1 = 0
2984 12:17:59.962771 DQM Delay:
2985 12:17:59.965612 DQM0 = 116, DQM1 = 108
2986 12:17:59.965687 DQ Delay:
2987 12:17:59.969584 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2988 12:17:59.972333 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2989 12:17:59.976018 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2990 12:17:59.979154 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2991 12:17:59.979234
2992 12:17:59.979333
2993 12:17:59.982428 ==
2994 12:17:59.985545 Dram Type= 6, Freq= 0, CH_0, rank 1
2995 12:17:59.989505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2996 12:17:59.989592 ==
2997 12:17:59.989673
2998 12:17:59.989751
2999 12:17:59.992008 TX Vref Scan disable
3000 12:17:59.992092 == TX Byte 0 ==
3001 12:17:59.999016 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3002 12:18:00.002488 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3003 12:18:00.002566 == TX Byte 1 ==
3004 12:18:00.008962 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3005 12:18:00.012251 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3006 12:18:00.012333 ==
3007 12:18:00.015328 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 12:18:00.019157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 12:18:00.019237 ==
3010 12:18:00.031782 TX Vref=22, minBit 5, minWin=25, winSum=420
3011 12:18:00.034267 TX Vref=24, minBit 1, minWin=26, winSum=428
3012 12:18:00.037674 TX Vref=26, minBit 1, minWin=26, winSum=429
3013 12:18:00.041260 TX Vref=28, minBit 1, minWin=26, winSum=436
3014 12:18:00.044312 TX Vref=30, minBit 2, minWin=27, winSum=440
3015 12:18:00.050957 TX Vref=32, minBit 10, minWin=26, winSum=433
3016 12:18:00.054018 [TxChooseVref] Worse bit 2, Min win 27, Win sum 440, Final Vref 30
3017 12:18:00.054099
3018 12:18:00.057317 Final TX Range 1 Vref 30
3019 12:18:00.057397
3020 12:18:00.057480 ==
3021 12:18:00.060811 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 12:18:00.064101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 12:18:00.067436 ==
3024 12:18:00.067546
3025 12:18:00.067639
3026 12:18:00.067753 TX Vref Scan disable
3027 12:18:00.070829 == TX Byte 0 ==
3028 12:18:00.074047 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3029 12:18:00.080607 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3030 12:18:00.080717 == TX Byte 1 ==
3031 12:18:00.084236 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3032 12:18:00.090837 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3033 12:18:00.090921
3034 12:18:00.090987 [DATLAT]
3035 12:18:00.091048 Freq=1200, CH0 RK1
3036 12:18:00.091107
3037 12:18:00.094151 DATLAT Default: 0xd
3038 12:18:00.094234 0, 0xFFFF, sum = 0
3039 12:18:00.097481 1, 0xFFFF, sum = 0
3040 12:18:00.100671 2, 0xFFFF, sum = 0
3041 12:18:00.100755 3, 0xFFFF, sum = 0
3042 12:18:00.104274 4, 0xFFFF, sum = 0
3043 12:18:00.104359 5, 0xFFFF, sum = 0
3044 12:18:00.107071 6, 0xFFFF, sum = 0
3045 12:18:00.107156 7, 0xFFFF, sum = 0
3046 12:18:00.110716 8, 0xFFFF, sum = 0
3047 12:18:00.110801 9, 0xFFFF, sum = 0
3048 12:18:00.113969 10, 0xFFFF, sum = 0
3049 12:18:00.114057 11, 0xFFFF, sum = 0
3050 12:18:00.117308 12, 0x0, sum = 1
3051 12:18:00.117393 13, 0x0, sum = 2
3052 12:18:00.120897 14, 0x0, sum = 3
3053 12:18:00.120981 15, 0x0, sum = 4
3054 12:18:00.124107 best_step = 13
3055 12:18:00.124189
3056 12:18:00.124261 ==
3057 12:18:00.127249 Dram Type= 6, Freq= 0, CH_0, rank 1
3058 12:18:00.130599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 12:18:00.130686 ==
3060 12:18:00.130772 RX Vref Scan: 0
3061 12:18:00.130854
3062 12:18:00.133867 RX Vref 0 -> 0, step: 1
3063 12:18:00.133953
3064 12:18:00.136904 RX Delay -21 -> 252, step: 4
3065 12:18:00.140397 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3066 12:18:00.147222 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3067 12:18:00.150374 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3068 12:18:00.153802 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3069 12:18:00.157654 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3070 12:18:00.160784 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3071 12:18:00.166931 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3072 12:18:00.170371 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3073 12:18:00.173629 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3074 12:18:00.177049 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3075 12:18:00.180258 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3076 12:18:00.187210 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3077 12:18:00.190314 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3078 12:18:00.193662 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3079 12:18:00.197004 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3080 12:18:00.200581 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3081 12:18:00.203968 ==
3082 12:18:00.207278 Dram Type= 6, Freq= 0, CH_0, rank 1
3083 12:18:00.210489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 12:18:00.210573 ==
3085 12:18:00.210637 DQS Delay:
3086 12:18:00.213746 DQS0 = 0, DQS1 = 0
3087 12:18:00.213819 DQM Delay:
3088 12:18:00.216942 DQM0 = 116, DQM1 = 107
3089 12:18:00.217049 DQ Delay:
3090 12:18:00.220185 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3091 12:18:00.223412 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3092 12:18:00.227410 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3093 12:18:00.230629 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3094 12:18:00.230711
3095 12:18:00.230779
3096 12:18:00.240498 [DQSOSCAuto] RK1, (LSB)MR18= 0x10eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3097 12:18:00.243343 CH0 RK1: MR19=403, MR18=10EB
3098 12:18:00.246970 CH0_RK1: MR19=0x403, MR18=0x10EB, DQSOSC=403, MR23=63, INC=40, DEC=26
3099 12:18:00.250306 [RxdqsGatingPostProcess] freq 1200
3100 12:18:00.257274 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3101 12:18:00.260327 best DQS0 dly(2T, 0.5T) = (0, 11)
3102 12:18:00.263410 best DQS1 dly(2T, 0.5T) = (0, 12)
3103 12:18:00.267039 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3104 12:18:00.270151 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3105 12:18:00.273901 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 12:18:00.273981 best DQS1 dly(2T, 0.5T) = (0, 12)
3107 12:18:00.277290 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 12:18:00.280175 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3109 12:18:00.284184 Pre-setting of DQS Precalculation
3110 12:18:00.290466 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3111 12:18:00.290551 ==
3112 12:18:00.293555 Dram Type= 6, Freq= 0, CH_1, rank 0
3113 12:18:00.296901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3114 12:18:00.296985 ==
3115 12:18:00.303622 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3116 12:18:00.310231 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3117 12:18:00.317375 [CA 0] Center 37 (7~67) winsize 61
3118 12:18:00.320597 [CA 1] Center 38 (8~68) winsize 61
3119 12:18:00.324143 [CA 2] Center 34 (4~64) winsize 61
3120 12:18:00.327384 [CA 3] Center 33 (3~64) winsize 62
3121 12:18:00.330803 [CA 4] Center 34 (4~64) winsize 61
3122 12:18:00.333999 [CA 5] Center 33 (3~64) winsize 62
3123 12:18:00.334081
3124 12:18:00.337134 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3125 12:18:00.337217
3126 12:18:00.340559 [CATrainingPosCal] consider 1 rank data
3127 12:18:00.343608 u2DelayCellTimex100 = 270/100 ps
3128 12:18:00.347215 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3129 12:18:00.353787 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3130 12:18:00.357561 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3131 12:18:00.360753 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3132 12:18:00.364164 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3133 12:18:00.366860 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3134 12:18:00.366942
3135 12:18:00.370475 CA PerBit enable=1, Macro0, CA PI delay=33
3136 12:18:00.370585
3137 12:18:00.373527 [CBTSetCACLKResult] CA Dly = 33
3138 12:18:00.373609 CS Dly: 5 (0~36)
3139 12:18:00.377233 ==
3140 12:18:00.380671 Dram Type= 6, Freq= 0, CH_1, rank 1
3141 12:18:00.383363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3142 12:18:00.383495 ==
3143 12:18:00.387019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3144 12:18:00.393555 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3145 12:18:00.402796 [CA 0] Center 37 (7~67) winsize 61
3146 12:18:00.406072 [CA 1] Center 37 (7~68) winsize 62
3147 12:18:00.409507 [CA 2] Center 34 (4~65) winsize 62
3148 12:18:00.413028 [CA 3] Center 33 (3~64) winsize 62
3149 12:18:00.415997 [CA 4] Center 34 (4~64) winsize 61
3150 12:18:00.419274 [CA 5] Center 33 (3~64) winsize 62
3151 12:18:00.419351
3152 12:18:00.422652 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3153 12:18:00.422736
3154 12:18:00.425838 [CATrainingPosCal] consider 2 rank data
3155 12:18:00.429305 u2DelayCellTimex100 = 270/100 ps
3156 12:18:00.432610 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3157 12:18:00.440051 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3158 12:18:00.442718 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 12:18:00.446114 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3160 12:18:00.449029 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3161 12:18:00.452353 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3162 12:18:00.452436
3163 12:18:00.456203 CA PerBit enable=1, Macro0, CA PI delay=33
3164 12:18:00.456285
3165 12:18:00.459073 [CBTSetCACLKResult] CA Dly = 33
3166 12:18:00.462471 CS Dly: 7 (0~40)
3167 12:18:00.462570
3168 12:18:00.466357 ----->DramcWriteLeveling(PI) begin...
3169 12:18:00.466440 ==
3170 12:18:00.469031 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 12:18:00.472577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 12:18:00.472659 ==
3173 12:18:00.475853 Write leveling (Byte 0): 26 => 26
3174 12:18:00.478894 Write leveling (Byte 1): 28 => 28
3175 12:18:00.482183 DramcWriteLeveling(PI) end<-----
3176 12:18:00.482264
3177 12:18:00.482330 ==
3178 12:18:00.485667 Dram Type= 6, Freq= 0, CH_1, rank 0
3179 12:18:00.488880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3180 12:18:00.488963 ==
3181 12:18:00.492047 [Gating] SW mode calibration
3182 12:18:00.498707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3183 12:18:00.505195 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3184 12:18:00.508763 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3185 12:18:00.511769 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 12:18:00.518657 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 12:18:00.521729 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 12:18:00.524937 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 12:18:00.531861 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 12:18:00.535037 0 15 24 | B1->B0 | 3232 3131 | 1 1 | (1 1) (1 0)
3191 12:18:00.538420 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (0 0) (1 0)
3192 12:18:00.545257 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 12:18:00.548058 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 12:18:00.551523 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 12:18:00.558097 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 12:18:00.561360 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 12:18:00.564646 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 12:18:00.571308 1 0 24 | B1->B0 | 2929 3c3c | 0 0 | (0 0) (0 0)
3199 12:18:00.574576 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 12:18:00.577908 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 12:18:00.584657 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 12:18:00.588142 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 12:18:00.591134 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 12:18:00.598596 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 12:18:00.601551 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 12:18:00.604405 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 12:18:00.611165 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3208 12:18:00.615032 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 12:18:00.617949 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 12:18:00.624500 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:18:00.627577 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:18:00.631042 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:18:00.637844 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:18:00.640765 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 12:18:00.643979 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 12:18:00.650621 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 12:18:00.654223 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 12:18:00.657725 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 12:18:00.664292 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 12:18:00.667179 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 12:18:00.670394 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 12:18:00.677050 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3223 12:18:00.680155 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3224 12:18:00.683506 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 12:18:00.686728 Total UI for P1: 0, mck2ui 16
3226 12:18:00.690345 best dqsien dly found for B0: ( 1, 3, 26)
3227 12:18:00.693865 Total UI for P1: 0, mck2ui 16
3228 12:18:00.697132 best dqsien dly found for B1: ( 1, 3, 26)
3229 12:18:00.700679 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3230 12:18:00.703611 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3231 12:18:00.703731
3232 12:18:00.707234 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3233 12:18:00.713573 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3234 12:18:00.713679 [Gating] SW calibration Done
3235 12:18:00.713780 ==
3236 12:18:00.716925 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 12:18:00.723789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 12:18:00.723878 ==
3239 12:18:00.723948 RX Vref Scan: 0
3240 12:18:00.724009
3241 12:18:00.727397 RX Vref 0 -> 0, step: 1
3242 12:18:00.727477
3243 12:18:00.730530 RX Delay -40 -> 252, step: 8
3244 12:18:00.733961 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3245 12:18:00.736697 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3246 12:18:00.740124 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3247 12:18:00.746697 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3248 12:18:00.750264 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3249 12:18:00.753460 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3250 12:18:00.756741 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3251 12:18:00.760045 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3252 12:18:00.766711 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3253 12:18:00.770233 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3254 12:18:00.773311 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3255 12:18:00.776610 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3256 12:18:00.779957 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3257 12:18:00.786413 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3258 12:18:00.789950 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3259 12:18:00.793432 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3260 12:18:00.793516 ==
3261 12:18:00.796160 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 12:18:00.799403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 12:18:00.802653 ==
3264 12:18:00.802727 DQS Delay:
3265 12:18:00.802793 DQS0 = 0, DQS1 = 0
3266 12:18:00.806210 DQM Delay:
3267 12:18:00.806285 DQM0 = 117, DQM1 = 109
3268 12:18:00.809309 DQ Delay:
3269 12:18:00.812684 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3270 12:18:00.816203 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3271 12:18:00.819716 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3272 12:18:00.822901 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3273 12:18:00.822975
3274 12:18:00.823045
3275 12:18:00.823108 ==
3276 12:18:00.826363 Dram Type= 6, Freq= 0, CH_1, rank 0
3277 12:18:00.829751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3278 12:18:00.829856 ==
3279 12:18:00.829960
3280 12:18:00.830046
3281 12:18:00.832821 TX Vref Scan disable
3282 12:18:00.836141 == TX Byte 0 ==
3283 12:18:00.839382 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3284 12:18:00.843045 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3285 12:18:00.846159 == TX Byte 1 ==
3286 12:18:00.849308 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3287 12:18:00.852993 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3288 12:18:00.853070 ==
3289 12:18:00.856404 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 12:18:00.859321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 12:18:00.862621 ==
3292 12:18:00.872700 TX Vref=22, minBit 8, minWin=25, winSum=419
3293 12:18:00.875939 TX Vref=24, minBit 11, minWin=25, winSum=425
3294 12:18:00.879285 TX Vref=26, minBit 9, minWin=25, winSum=429
3295 12:18:00.882536 TX Vref=28, minBit 9, minWin=25, winSum=433
3296 12:18:00.886334 TX Vref=30, minBit 9, minWin=25, winSum=429
3297 12:18:00.892649 TX Vref=32, minBit 9, minWin=25, winSum=424
3298 12:18:00.896587 [TxChooseVref] Worse bit 9, Min win 25, Win sum 433, Final Vref 28
3299 12:18:00.896702
3300 12:18:00.899378 Final TX Range 1 Vref 28
3301 12:18:00.899494
3302 12:18:00.899588 ==
3303 12:18:00.902829 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 12:18:00.905819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 12:18:00.905908 ==
3306 12:18:00.909186
3307 12:18:00.909273
3308 12:18:00.909342 TX Vref Scan disable
3309 12:18:00.912501 == TX Byte 0 ==
3310 12:18:00.915920 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3311 12:18:00.922411 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3312 12:18:00.922490 == TX Byte 1 ==
3313 12:18:00.925460 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3314 12:18:00.932362 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3315 12:18:00.932469
3316 12:18:00.932532 [DATLAT]
3317 12:18:00.932591 Freq=1200, CH1 RK0
3318 12:18:00.932658
3319 12:18:00.935655 DATLAT Default: 0xd
3320 12:18:00.935793 0, 0xFFFF, sum = 0
3321 12:18:00.939126 1, 0xFFFF, sum = 0
3322 12:18:00.939207 2, 0xFFFF, sum = 0
3323 12:18:00.942334 3, 0xFFFF, sum = 0
3324 12:18:00.945614 4, 0xFFFF, sum = 0
3325 12:18:00.945694 5, 0xFFFF, sum = 0
3326 12:18:00.949311 6, 0xFFFF, sum = 0
3327 12:18:00.949387 7, 0xFFFF, sum = 0
3328 12:18:00.952462 8, 0xFFFF, sum = 0
3329 12:18:00.952546 9, 0xFFFF, sum = 0
3330 12:18:00.955437 10, 0xFFFF, sum = 0
3331 12:18:00.955519 11, 0xFFFF, sum = 0
3332 12:18:00.958964 12, 0x0, sum = 1
3333 12:18:00.959043 13, 0x0, sum = 2
3334 12:18:00.962274 14, 0x0, sum = 3
3335 12:18:00.962356 15, 0x0, sum = 4
3336 12:18:00.965448 best_step = 13
3337 12:18:00.965531
3338 12:18:00.965594 ==
3339 12:18:00.968834 Dram Type= 6, Freq= 0, CH_1, rank 0
3340 12:18:00.972307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3341 12:18:00.972386 ==
3342 12:18:00.972451 RX Vref Scan: 1
3343 12:18:00.972511
3344 12:18:00.975297 Set Vref Range= 32 -> 127
3345 12:18:00.975370
3346 12:18:00.979155 RX Vref 32 -> 127, step: 1
3347 12:18:00.979235
3348 12:18:00.981930 RX Delay -21 -> 252, step: 4
3349 12:18:00.982014
3350 12:18:00.985216 Set Vref, RX VrefLevel [Byte0]: 32
3351 12:18:00.988855 [Byte1]: 32
3352 12:18:00.988929
3353 12:18:00.992064 Set Vref, RX VrefLevel [Byte0]: 33
3354 12:18:00.995450 [Byte1]: 33
3355 12:18:00.998841
3356 12:18:00.998916 Set Vref, RX VrefLevel [Byte0]: 34
3357 12:18:01.002444 [Byte1]: 34
3358 12:18:01.006963
3359 12:18:01.007038 Set Vref, RX VrefLevel [Byte0]: 35
3360 12:18:01.010119 [Byte1]: 35
3361 12:18:01.015175
3362 12:18:01.015254 Set Vref, RX VrefLevel [Byte0]: 36
3363 12:18:01.018412 [Byte1]: 36
3364 12:18:01.022723
3365 12:18:01.022827 Set Vref, RX VrefLevel [Byte0]: 37
3366 12:18:01.026000 [Byte1]: 37
3367 12:18:01.030854
3368 12:18:01.030942 Set Vref, RX VrefLevel [Byte0]: 38
3369 12:18:01.034247 [Byte1]: 38
3370 12:18:01.038394
3371 12:18:01.038469 Set Vref, RX VrefLevel [Byte0]: 39
3372 12:18:01.041752 [Byte1]: 39
3373 12:18:01.047003
3374 12:18:01.047077 Set Vref, RX VrefLevel [Byte0]: 40
3375 12:18:01.049740 [Byte1]: 40
3376 12:18:01.054382
3377 12:18:01.054456 Set Vref, RX VrefLevel [Byte0]: 41
3378 12:18:01.057737 [Byte1]: 41
3379 12:18:01.062444
3380 12:18:01.062519 Set Vref, RX VrefLevel [Byte0]: 42
3381 12:18:01.065487 [Byte1]: 42
3382 12:18:01.070359
3383 12:18:01.070434 Set Vref, RX VrefLevel [Byte0]: 43
3384 12:18:01.076370 [Byte1]: 43
3385 12:18:01.076448
3386 12:18:01.079813 Set Vref, RX VrefLevel [Byte0]: 44
3387 12:18:01.083038 [Byte1]: 44
3388 12:18:01.083112
3389 12:18:01.086439 Set Vref, RX VrefLevel [Byte0]: 45
3390 12:18:01.089791 [Byte1]: 45
3391 12:18:01.094447
3392 12:18:01.094525 Set Vref, RX VrefLevel [Byte0]: 46
3393 12:18:01.097149 [Byte1]: 46
3394 12:18:01.102082
3395 12:18:01.102158 Set Vref, RX VrefLevel [Byte0]: 47
3396 12:18:01.105247 [Byte1]: 47
3397 12:18:01.109798
3398 12:18:01.109921 Set Vref, RX VrefLevel [Byte0]: 48
3399 12:18:01.113066 [Byte1]: 48
3400 12:18:01.117577
3401 12:18:01.117748 Set Vref, RX VrefLevel [Byte0]: 49
3402 12:18:01.121326 [Byte1]: 49
3403 12:18:01.125624
3404 12:18:01.125797 Set Vref, RX VrefLevel [Byte0]: 50
3405 12:18:01.128907 [Byte1]: 50
3406 12:18:01.133438
3407 12:18:01.133520 Set Vref, RX VrefLevel [Byte0]: 51
3408 12:18:01.136784 [Byte1]: 51
3409 12:18:01.141758
3410 12:18:01.141833 Set Vref, RX VrefLevel [Byte0]: 52
3411 12:18:01.144572 [Byte1]: 52
3412 12:18:01.149832
3413 12:18:01.149908 Set Vref, RX VrefLevel [Byte0]: 53
3414 12:18:01.153002 [Byte1]: 53
3415 12:18:01.157241
3416 12:18:01.157329 Set Vref, RX VrefLevel [Byte0]: 54
3417 12:18:01.160496 [Byte1]: 54
3418 12:18:01.165563
3419 12:18:01.165639 Set Vref, RX VrefLevel [Byte0]: 55
3420 12:18:01.168354 [Byte1]: 55
3421 12:18:01.172911
3422 12:18:01.172988 Set Vref, RX VrefLevel [Byte0]: 56
3423 12:18:01.176182 [Byte1]: 56
3424 12:18:01.181461
3425 12:18:01.181544 Set Vref, RX VrefLevel [Byte0]: 57
3426 12:18:01.184456 [Byte1]: 57
3427 12:18:01.189277
3428 12:18:01.189379 Set Vref, RX VrefLevel [Byte0]: 58
3429 12:18:01.192139 [Byte1]: 58
3430 12:18:01.196728
3431 12:18:01.196833 Set Vref, RX VrefLevel [Byte0]: 59
3432 12:18:01.200172 [Byte1]: 59
3433 12:18:01.204745
3434 12:18:01.204828 Set Vref, RX VrefLevel [Byte0]: 60
3435 12:18:01.208200 [Byte1]: 60
3436 12:18:01.212601
3437 12:18:01.212675 Set Vref, RX VrefLevel [Byte0]: 61
3438 12:18:01.215840 [Byte1]: 61
3439 12:18:01.220741
3440 12:18:01.220855 Set Vref, RX VrefLevel [Byte0]: 62
3441 12:18:01.224197 [Byte1]: 62
3442 12:18:01.228680
3443 12:18:01.228762 Set Vref, RX VrefLevel [Byte0]: 63
3444 12:18:01.231839 [Byte1]: 63
3445 12:18:01.236507
3446 12:18:01.236596 Set Vref, RX VrefLevel [Byte0]: 64
3447 12:18:01.240150 [Byte1]: 64
3448 12:18:01.244301
3449 12:18:01.244380 Set Vref, RX VrefLevel [Byte0]: 65
3450 12:18:01.247638 [Byte1]: 65
3451 12:18:01.252203
3452 12:18:01.252288 Set Vref, RX VrefLevel [Byte0]: 66
3453 12:18:01.255640 [Byte1]: 66
3454 12:18:01.260497
3455 12:18:01.260581 Set Vref, RX VrefLevel [Byte0]: 67
3456 12:18:01.263289 [Byte1]: 67
3457 12:18:01.268267
3458 12:18:01.268346 Set Vref, RX VrefLevel [Byte0]: 68
3459 12:18:01.271429 [Byte1]: 68
3460 12:18:01.275962
3461 12:18:01.276040 Set Vref, RX VrefLevel [Byte0]: 69
3462 12:18:01.279550 [Byte1]: 69
3463 12:18:01.283783
3464 12:18:01.283864 Final RX Vref Byte 0 = 47 to rank0
3465 12:18:01.287194 Final RX Vref Byte 1 = 59 to rank0
3466 12:18:01.291097 Final RX Vref Byte 0 = 47 to rank1
3467 12:18:01.293998 Final RX Vref Byte 1 = 59 to rank1==
3468 12:18:01.297475 Dram Type= 6, Freq= 0, CH_1, rank 0
3469 12:18:01.303561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 12:18:01.303646 ==
3471 12:18:01.303717 DQS Delay:
3472 12:18:01.306994 DQS0 = 0, DQS1 = 0
3473 12:18:01.307075 DQM Delay:
3474 12:18:01.307140 DQM0 = 116, DQM1 = 112
3475 12:18:01.310283 DQ Delay:
3476 12:18:01.313563 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =112
3477 12:18:01.316886 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3478 12:18:01.320373 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =102
3479 12:18:01.323459 DQ12 =120, DQ13 =118, DQ14 =122, DQ15 =120
3480 12:18:01.323538
3481 12:18:01.323611
3482 12:18:01.333617 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f5, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 409 ps
3483 12:18:01.333710 CH1 RK0: MR19=403, MR18=1F5
3484 12:18:01.340064 CH1_RK0: MR19=0x403, MR18=0x1F5, DQSOSC=409, MR23=63, INC=39, DEC=26
3485 12:18:01.340149
3486 12:18:01.343289 ----->DramcWriteLeveling(PI) begin...
3487 12:18:01.343375 ==
3488 12:18:01.346592 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 12:18:01.353135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 12:18:01.353224 ==
3491 12:18:01.356204 Write leveling (Byte 0): 27 => 27
3492 12:18:01.359463 Write leveling (Byte 1): 27 => 27
3493 12:18:01.359549 DramcWriteLeveling(PI) end<-----
3494 12:18:01.359655
3495 12:18:01.363189 ==
3496 12:18:01.366497 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 12:18:01.369821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 12:18:01.369956 ==
3499 12:18:01.372763 [Gating] SW mode calibration
3500 12:18:01.379828 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3501 12:18:01.382849 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3502 12:18:01.389348 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 12:18:01.393023 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 12:18:01.395945 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 12:18:01.402734 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 12:18:01.405845 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 12:18:01.409584 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 12:18:01.416195 0 15 24 | B1->B0 | 2c2c 3333 | 0 1 | (0 1) (1 0)
3509 12:18:01.419022 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 12:18:01.422378 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 12:18:01.429048 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 12:18:01.432422 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 12:18:01.435670 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 12:18:01.442037 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 12:18:01.445816 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 12:18:01.448977 1 0 24 | B1->B0 | 3434 2525 | 0 0 | (0 0) (0 0)
3517 12:18:01.455965 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 12:18:01.458548 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 12:18:01.461881 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 12:18:01.468605 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 12:18:01.472312 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 12:18:01.475154 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 12:18:01.481790 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 12:18:01.485169 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3525 12:18:01.488167 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3526 12:18:01.495274 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:18:01.498537 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:18:01.501770 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:18:01.508039 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:18:01.511606 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:18:01.514936 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:18:01.521376 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:18:01.524654 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:18:01.528001 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:18:01.534538 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:18:01.537874 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:18:01.541233 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 12:18:01.548031 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 12:18:01.551278 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3540 12:18:01.554436 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3541 12:18:01.560745 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3542 12:18:01.564696 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 12:18:01.567557 Total UI for P1: 0, mck2ui 16
3544 12:18:01.570692 best dqsien dly found for B0: ( 1, 3, 26)
3545 12:18:01.574424 Total UI for P1: 0, mck2ui 16
3546 12:18:01.577854 best dqsien dly found for B1: ( 1, 3, 24)
3547 12:18:01.580775 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3548 12:18:01.584116 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3549 12:18:01.584196
3550 12:18:01.587200 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3551 12:18:01.590819 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3552 12:18:01.594106 [Gating] SW calibration Done
3553 12:18:01.594182 ==
3554 12:18:01.597026 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 12:18:01.603655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 12:18:01.603745 ==
3557 12:18:01.603812 RX Vref Scan: 0
3558 12:18:01.603872
3559 12:18:01.606963 RX Vref 0 -> 0, step: 1
3560 12:18:01.607066
3561 12:18:01.610198 RX Delay -40 -> 252, step: 8
3562 12:18:01.613757 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3563 12:18:01.617021 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3564 12:18:01.620311 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3565 12:18:01.626569 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3566 12:18:01.629872 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3567 12:18:01.633159 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3568 12:18:01.636564 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3569 12:18:01.640004 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3570 12:18:01.646934 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3571 12:18:01.649817 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3572 12:18:01.653302 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3573 12:18:01.656615 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3574 12:18:01.660078 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3575 12:18:01.666215 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3576 12:18:01.669449 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3577 12:18:01.673270 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3578 12:18:01.673345 ==
3579 12:18:01.676731 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 12:18:01.679436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 12:18:01.679525 ==
3582 12:18:01.683051 DQS Delay:
3583 12:18:01.683137 DQS0 = 0, DQS1 = 0
3584 12:18:01.686346 DQM Delay:
3585 12:18:01.686431 DQM0 = 116, DQM1 = 110
3586 12:18:01.689408 DQ Delay:
3587 12:18:01.693057 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3588 12:18:01.695996 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3589 12:18:01.699418 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3590 12:18:01.703052 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3591 12:18:01.703137
3592 12:18:01.703238
3593 12:18:01.703337 ==
3594 12:18:01.706184 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 12:18:01.709193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 12:18:01.709278 ==
3597 12:18:01.709363
3598 12:18:01.709443
3599 12:18:01.712722 TX Vref Scan disable
3600 12:18:01.715972 == TX Byte 0 ==
3601 12:18:01.719180 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3602 12:18:01.722475 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3603 12:18:01.725897 == TX Byte 1 ==
3604 12:18:01.729243 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3605 12:18:01.732517 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3606 12:18:01.732602 ==
3607 12:18:01.736203 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 12:18:01.742551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 12:18:01.742637 ==
3610 12:18:01.752884 TX Vref=22, minBit 1, minWin=26, winSum=422
3611 12:18:01.756248 TX Vref=24, minBit 3, minWin=26, winSum=425
3612 12:18:01.759325 TX Vref=26, minBit 8, minWin=26, winSum=428
3613 12:18:01.762537 TX Vref=28, minBit 9, minWin=26, winSum=430
3614 12:18:01.766217 TX Vref=30, minBit 9, minWin=26, winSum=430
3615 12:18:01.772339 TX Vref=32, minBit 8, minWin=26, winSum=429
3616 12:18:01.776100 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 28
3617 12:18:01.776185
3618 12:18:01.779515 Final TX Range 1 Vref 28
3619 12:18:01.779599
3620 12:18:01.779700 ==
3621 12:18:01.782605 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 12:18:01.785812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 12:18:01.789371 ==
3624 12:18:01.789453
3625 12:18:01.789518
3626 12:18:01.789578 TX Vref Scan disable
3627 12:18:01.792522 == TX Byte 0 ==
3628 12:18:01.795966 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3629 12:18:01.802045 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3630 12:18:01.802127 == TX Byte 1 ==
3631 12:18:01.805598 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3632 12:18:01.811952 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3633 12:18:01.812034
3634 12:18:01.812099 [DATLAT]
3635 12:18:01.812160 Freq=1200, CH1 RK1
3636 12:18:01.812235
3637 12:18:01.815599 DATLAT Default: 0xd
3638 12:18:01.818630 0, 0xFFFF, sum = 0
3639 12:18:01.818716 1, 0xFFFF, sum = 0
3640 12:18:01.822127 2, 0xFFFF, sum = 0
3641 12:18:01.822213 3, 0xFFFF, sum = 0
3642 12:18:01.825308 4, 0xFFFF, sum = 0
3643 12:18:01.825394 5, 0xFFFF, sum = 0
3644 12:18:01.828983 6, 0xFFFF, sum = 0
3645 12:18:01.829069 7, 0xFFFF, sum = 0
3646 12:18:01.831937 8, 0xFFFF, sum = 0
3647 12:18:01.832049 9, 0xFFFF, sum = 0
3648 12:18:01.835163 10, 0xFFFF, sum = 0
3649 12:18:01.835277 11, 0xFFFF, sum = 0
3650 12:18:01.838675 12, 0x0, sum = 1
3651 12:18:01.838760 13, 0x0, sum = 2
3652 12:18:01.842060 14, 0x0, sum = 3
3653 12:18:01.842141 15, 0x0, sum = 4
3654 12:18:01.845317 best_step = 13
3655 12:18:01.845395
3656 12:18:01.845457 ==
3657 12:18:01.848545 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 12:18:01.851972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 12:18:01.852050 ==
3660 12:18:01.855384 RX Vref Scan: 0
3661 12:18:01.855463
3662 12:18:01.855524 RX Vref 0 -> 0, step: 1
3663 12:18:01.855583
3664 12:18:01.858527 RX Delay -21 -> 252, step: 4
3665 12:18:01.865105 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3666 12:18:01.868010 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3667 12:18:01.871618 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3668 12:18:01.874990 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3669 12:18:01.877780 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3670 12:18:01.884778 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3671 12:18:01.888158 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3672 12:18:01.891288 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3673 12:18:01.894466 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3674 12:18:01.897746 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3675 12:18:01.904316 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3676 12:18:01.907648 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3677 12:18:01.911300 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3678 12:18:01.914325 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3679 12:18:01.921147 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3680 12:18:01.924178 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3681 12:18:01.924290 ==
3682 12:18:01.927611 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 12:18:01.931061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 12:18:01.931145 ==
3685 12:18:01.934071 DQS Delay:
3686 12:18:01.934154 DQS0 = 0, DQS1 = 0
3687 12:18:01.934220 DQM Delay:
3688 12:18:01.937244 DQM0 = 116, DQM1 = 110
3689 12:18:01.937321 DQ Delay:
3690 12:18:01.940949 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3691 12:18:01.944078 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =114
3692 12:18:01.950602 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =102
3693 12:18:01.954028 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3694 12:18:01.954117
3695 12:18:01.954187
3696 12:18:01.960731 [DQSOSCAuto] RK1, (LSB)MR18= 0xf4f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
3697 12:18:01.964083 CH1 RK1: MR19=303, MR18=F4F0
3698 12:18:01.970799 CH1_RK1: MR19=0x303, MR18=0xF4F0, DQSOSC=415, MR23=63, INC=38, DEC=25
3699 12:18:01.973826 [RxdqsGatingPostProcess] freq 1200
3700 12:18:01.977472 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3701 12:18:01.980579 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 12:18:01.983679 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 12:18:01.987281 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 12:18:01.990622 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 12:18:01.993792 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 12:18:01.996962 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 12:18:02.000639 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 12:18:02.003518 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 12:18:02.006499 Pre-setting of DQS Precalculation
3710 12:18:02.013131 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3711 12:18:02.020206 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3712 12:18:02.026424 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3713 12:18:02.026510
3714 12:18:02.026579
3715 12:18:02.030612 [Calibration Summary] 2400 Mbps
3716 12:18:02.030688 CH 0, Rank 0
3717 12:18:02.033207 SW Impedance : PASS
3718 12:18:02.036704 DUTY Scan : NO K
3719 12:18:02.036791 ZQ Calibration : PASS
3720 12:18:02.040070 Jitter Meter : NO K
3721 12:18:02.043057 CBT Training : PASS
3722 12:18:02.043187 Write leveling : PASS
3723 12:18:02.046297 RX DQS gating : PASS
3724 12:18:02.046384 RX DQ/DQS(RDDQC) : PASS
3725 12:18:02.049890 TX DQ/DQS : PASS
3726 12:18:02.052838 RX DATLAT : PASS
3727 12:18:02.052932 RX DQ/DQS(Engine): PASS
3728 12:18:02.056148 TX OE : NO K
3729 12:18:02.056246 All Pass.
3730 12:18:02.056350
3731 12:18:02.059663 CH 0, Rank 1
3732 12:18:02.059820 SW Impedance : PASS
3733 12:18:02.062889 DUTY Scan : NO K
3734 12:18:02.066056 ZQ Calibration : PASS
3735 12:18:02.066160 Jitter Meter : NO K
3736 12:18:02.069815 CBT Training : PASS
3737 12:18:02.072977 Write leveling : PASS
3738 12:18:02.073084 RX DQS gating : PASS
3739 12:18:02.076066 RX DQ/DQS(RDDQC) : PASS
3740 12:18:02.079514 TX DQ/DQS : PASS
3741 12:18:02.079638 RX DATLAT : PASS
3742 12:18:02.082781 RX DQ/DQS(Engine): PASS
3743 12:18:02.086442 TX OE : NO K
3744 12:18:02.086529 All Pass.
3745 12:18:02.086595
3746 12:18:02.086656 CH 1, Rank 0
3747 12:18:02.089406 SW Impedance : PASS
3748 12:18:02.092816 DUTY Scan : NO K
3749 12:18:02.092902 ZQ Calibration : PASS
3750 12:18:02.095714 Jitter Meter : NO K
3751 12:18:02.099323 CBT Training : PASS
3752 12:18:02.099413 Write leveling : PASS
3753 12:18:02.102363 RX DQS gating : PASS
3754 12:18:02.105621 RX DQ/DQS(RDDQC) : PASS
3755 12:18:02.105734 TX DQ/DQS : PASS
3756 12:18:02.109042 RX DATLAT : PASS
3757 12:18:02.112462 RX DQ/DQS(Engine): PASS
3758 12:18:02.112548 TX OE : NO K
3759 12:18:02.112614 All Pass.
3760 12:18:02.112675
3761 12:18:02.116084 CH 1, Rank 1
3762 12:18:02.119207 SW Impedance : PASS
3763 12:18:02.119289 DUTY Scan : NO K
3764 12:18:02.122515 ZQ Calibration : PASS
3765 12:18:02.122597 Jitter Meter : NO K
3766 12:18:02.125441 CBT Training : PASS
3767 12:18:02.129540 Write leveling : PASS
3768 12:18:02.129622 RX DQS gating : PASS
3769 12:18:02.132311 RX DQ/DQS(RDDQC) : PASS
3770 12:18:02.135709 TX DQ/DQS : PASS
3771 12:18:02.135833 RX DATLAT : PASS
3772 12:18:02.139269 RX DQ/DQS(Engine): PASS
3773 12:18:02.142003 TX OE : NO K
3774 12:18:02.142085 All Pass.
3775 12:18:02.142151
3776 12:18:02.145510 DramC Write-DBI off
3777 12:18:02.145591 PER_BANK_REFRESH: Hybrid Mode
3778 12:18:02.148713 TX_TRACKING: ON
3779 12:18:02.158720 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3780 12:18:02.162050 [FAST_K] Save calibration result to emmc
3781 12:18:02.165319 dramc_set_vcore_voltage set vcore to 650000
3782 12:18:02.165401 Read voltage for 600, 5
3783 12:18:02.168535 Vio18 = 0
3784 12:18:02.168622 Vcore = 650000
3785 12:18:02.168691 Vdram = 0
3786 12:18:02.172232 Vddq = 0
3787 12:18:02.172309 Vmddr = 0
3788 12:18:02.175775 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3789 12:18:02.181655 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3790 12:18:02.184918 MEM_TYPE=3, freq_sel=19
3791 12:18:02.188267 sv_algorithm_assistance_LP4_1600
3792 12:18:02.191268 ============ PULL DRAM RESETB DOWN ============
3793 12:18:02.195008 ========== PULL DRAM RESETB DOWN end =========
3794 12:18:02.201387 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3795 12:18:02.204528 ===================================
3796 12:18:02.204609 LPDDR4 DRAM CONFIGURATION
3797 12:18:02.208247 ===================================
3798 12:18:02.211281 EX_ROW_EN[0] = 0x0
3799 12:18:02.214493 EX_ROW_EN[1] = 0x0
3800 12:18:02.214574 LP4Y_EN = 0x0
3801 12:18:02.217910 WORK_FSP = 0x0
3802 12:18:02.217984 WL = 0x2
3803 12:18:02.221217 RL = 0x2
3804 12:18:02.221288 BL = 0x2
3805 12:18:02.224758 RPST = 0x0
3806 12:18:02.224827 RD_PRE = 0x0
3807 12:18:02.228384 WR_PRE = 0x1
3808 12:18:02.228456 WR_PST = 0x0
3809 12:18:02.230939 DBI_WR = 0x0
3810 12:18:02.231006 DBI_RD = 0x0
3811 12:18:02.234344 OTF = 0x1
3812 12:18:02.237893 ===================================
3813 12:18:02.241152 ===================================
3814 12:18:02.241224 ANA top config
3815 12:18:02.244571 ===================================
3816 12:18:02.247733 DLL_ASYNC_EN = 0
3817 12:18:02.251418 ALL_SLAVE_EN = 1
3818 12:18:02.254262 NEW_RANK_MODE = 1
3819 12:18:02.254341 DLL_IDLE_MODE = 1
3820 12:18:02.257593 LP45_APHY_COMB_EN = 1
3821 12:18:02.260903 TX_ODT_DIS = 1
3822 12:18:02.264170 NEW_8X_MODE = 1
3823 12:18:02.267463 ===================================
3824 12:18:02.270937 ===================================
3825 12:18:02.274262 data_rate = 1200
3826 12:18:02.274332 CKR = 1
3827 12:18:02.277617 DQ_P2S_RATIO = 8
3828 12:18:02.280529 ===================================
3829 12:18:02.284250 CA_P2S_RATIO = 8
3830 12:18:02.287197 DQ_CA_OPEN = 0
3831 12:18:02.290503 DQ_SEMI_OPEN = 0
3832 12:18:02.293699 CA_SEMI_OPEN = 0
3833 12:18:02.293775 CA_FULL_RATE = 0
3834 12:18:02.297317 DQ_CKDIV4_EN = 1
3835 12:18:02.300626 CA_CKDIV4_EN = 1
3836 12:18:02.303905 CA_PREDIV_EN = 0
3837 12:18:02.306989 PH8_DLY = 0
3838 12:18:02.310486 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3839 12:18:02.310561 DQ_AAMCK_DIV = 4
3840 12:18:02.313791 CA_AAMCK_DIV = 4
3841 12:18:02.316690 CA_ADMCK_DIV = 4
3842 12:18:02.320235 DQ_TRACK_CA_EN = 0
3843 12:18:02.323393 CA_PICK = 600
3844 12:18:02.326628 CA_MCKIO = 600
3845 12:18:02.329970 MCKIO_SEMI = 0
3846 12:18:02.333167 PLL_FREQ = 2288
3847 12:18:02.333244 DQ_UI_PI_RATIO = 32
3848 12:18:02.336683 CA_UI_PI_RATIO = 0
3849 12:18:02.339712 ===================================
3850 12:18:02.343609 ===================================
3851 12:18:02.346339 memory_type:LPDDR4
3852 12:18:02.349731 GP_NUM : 10
3853 12:18:02.349808 SRAM_EN : 1
3854 12:18:02.353023 MD32_EN : 0
3855 12:18:02.356234 ===================================
3856 12:18:02.359817 [ANA_INIT] >>>>>>>>>>>>>>
3857 12:18:02.359898 <<<<<< [CONFIGURE PHASE]: ANA_TX
3858 12:18:02.363162 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3859 12:18:02.366558 ===================================
3860 12:18:02.369531 data_rate = 1200,PCW = 0X5800
3861 12:18:02.373022 ===================================
3862 12:18:02.376318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3863 12:18:02.383158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 12:18:02.389647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3865 12:18:02.392806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3866 12:18:02.396337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3867 12:18:02.399621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3868 12:18:02.402767 [ANA_INIT] flow start
3869 12:18:02.402850 [ANA_INIT] PLL >>>>>>>>
3870 12:18:02.406748 [ANA_INIT] PLL <<<<<<<<
3871 12:18:02.409426 [ANA_INIT] MIDPI >>>>>>>>
3872 12:18:02.409501 [ANA_INIT] MIDPI <<<<<<<<
3873 12:18:02.412635 [ANA_INIT] DLL >>>>>>>>
3874 12:18:02.416208 [ANA_INIT] flow end
3875 12:18:02.419712 ============ LP4 DIFF to SE enter ============
3876 12:18:02.423055 ============ LP4 DIFF to SE exit ============
3877 12:18:02.425911 [ANA_INIT] <<<<<<<<<<<<<
3878 12:18:02.429337 [Flow] Enable top DCM control >>>>>
3879 12:18:02.432530 [Flow] Enable top DCM control <<<<<
3880 12:18:02.435935 Enable DLL master slave shuffle
3881 12:18:02.442354 ==============================================================
3882 12:18:02.442433 Gating Mode config
3883 12:18:02.449343 ==============================================================
3884 12:18:02.449422 Config description:
3885 12:18:02.459498 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3886 12:18:02.465603 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3887 12:18:02.472011 SELPH_MODE 0: By rank 1: By Phase
3888 12:18:02.475509 ==============================================================
3889 12:18:02.478928 GAT_TRACK_EN = 1
3890 12:18:02.482417 RX_GATING_MODE = 2
3891 12:18:02.485707 RX_GATING_TRACK_MODE = 2
3892 12:18:02.488541 SELPH_MODE = 1
3893 12:18:02.492084 PICG_EARLY_EN = 1
3894 12:18:02.495578 VALID_LAT_VALUE = 1
3895 12:18:02.501835 ==============================================================
3896 12:18:02.505086 Enter into Gating configuration >>>>
3897 12:18:02.508212 Exit from Gating configuration <<<<
3898 12:18:02.511832 Enter into DVFS_PRE_config >>>>>
3899 12:18:02.522357 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3900 12:18:02.525500 Exit from DVFS_PRE_config <<<<<
3901 12:18:02.528068 Enter into PICG configuration >>>>
3902 12:18:02.531710 Exit from PICG configuration <<<<
3903 12:18:02.534525 [RX_INPUT] configuration >>>>>
3904 12:18:02.534607 [RX_INPUT] configuration <<<<<
3905 12:18:02.541428 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3906 12:18:02.548003 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3907 12:18:02.551515 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 12:18:02.558257 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 12:18:02.564738 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 12:18:02.571353 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 12:18:02.574387 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3912 12:18:02.578175 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3913 12:18:02.584594 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3914 12:18:02.588049 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3915 12:18:02.590826 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3916 12:18:02.597463 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 12:18:02.600940 ===================================
3918 12:18:02.601022 LPDDR4 DRAM CONFIGURATION
3919 12:18:02.604102 ===================================
3920 12:18:02.607438 EX_ROW_EN[0] = 0x0
3921 12:18:02.610831 EX_ROW_EN[1] = 0x0
3922 12:18:02.610913 LP4Y_EN = 0x0
3923 12:18:02.614365 WORK_FSP = 0x0
3924 12:18:02.614447 WL = 0x2
3925 12:18:02.617560 RL = 0x2
3926 12:18:02.617642 BL = 0x2
3927 12:18:02.620841 RPST = 0x0
3928 12:18:02.620922 RD_PRE = 0x0
3929 12:18:02.624144 WR_PRE = 0x1
3930 12:18:02.624226 WR_PST = 0x0
3931 12:18:02.627804 DBI_WR = 0x0
3932 12:18:02.627886 DBI_RD = 0x0
3933 12:18:02.630603 OTF = 0x1
3934 12:18:02.633919 ===================================
3935 12:18:02.637131 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3936 12:18:02.640330 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3937 12:18:02.647296 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3938 12:18:02.650203 ===================================
3939 12:18:02.650286 LPDDR4 DRAM CONFIGURATION
3940 12:18:02.654222 ===================================
3941 12:18:02.657204 EX_ROW_EN[0] = 0x10
3942 12:18:02.660177 EX_ROW_EN[1] = 0x0
3943 12:18:02.660264 LP4Y_EN = 0x0
3944 12:18:02.663521 WORK_FSP = 0x0
3945 12:18:02.663603 WL = 0x2
3946 12:18:02.666740 RL = 0x2
3947 12:18:02.666822 BL = 0x2
3948 12:18:02.670192 RPST = 0x0
3949 12:18:02.670274 RD_PRE = 0x0
3950 12:18:02.673676 WR_PRE = 0x1
3951 12:18:02.673758 WR_PST = 0x0
3952 12:18:02.676645 DBI_WR = 0x0
3953 12:18:02.676727 DBI_RD = 0x0
3954 12:18:02.680091 OTF = 0x1
3955 12:18:02.683305 ===================================
3956 12:18:02.689906 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3957 12:18:02.693105 nWR fixed to 30
3958 12:18:02.696425 [ModeRegInit_LP4] CH0 RK0
3959 12:18:02.696507 [ModeRegInit_LP4] CH0 RK1
3960 12:18:02.699743 [ModeRegInit_LP4] CH1 RK0
3961 12:18:02.702777 [ModeRegInit_LP4] CH1 RK1
3962 12:18:02.702859 match AC timing 17
3963 12:18:02.709664 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3964 12:18:02.712787 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3965 12:18:02.715810 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3966 12:18:02.722878 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3967 12:18:02.726013 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3968 12:18:02.726095 ==
3969 12:18:02.729663 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 12:18:02.732724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 12:18:02.732807 ==
3972 12:18:02.739348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 12:18:02.745887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 12:18:02.748994 [CA 0] Center 36 (6~66) winsize 61
3975 12:18:02.752208 [CA 1] Center 36 (6~66) winsize 61
3976 12:18:02.756184 [CA 2] Center 33 (3~64) winsize 62
3977 12:18:02.759350 [CA 3] Center 34 (4~65) winsize 62
3978 12:18:02.762612 [CA 4] Center 33 (3~64) winsize 62
3979 12:18:02.765531 [CA 5] Center 33 (3~64) winsize 62
3980 12:18:02.765613
3981 12:18:02.768831 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 12:18:02.768914
3983 12:18:02.772469 [CATrainingPosCal] consider 1 rank data
3984 12:18:02.776076 u2DelayCellTimex100 = 270/100 ps
3985 12:18:02.779008 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3986 12:18:02.782289 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3987 12:18:02.785640 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
3988 12:18:02.789060 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3989 12:18:02.791992 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 12:18:02.799010 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 12:18:02.799094
3992 12:18:02.801869 CA PerBit enable=1, Macro0, CA PI delay=33
3993 12:18:02.801955
3994 12:18:02.804978 [CBTSetCACLKResult] CA Dly = 33
3995 12:18:02.805064 CS Dly: 5 (0~36)
3996 12:18:02.805130 ==
3997 12:18:02.808420 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 12:18:02.811980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 12:18:02.815082 ==
4000 12:18:02.818431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4001 12:18:02.824953 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4002 12:18:02.828143 [CA 0] Center 36 (6~66) winsize 61
4003 12:18:02.831838 [CA 1] Center 36 (6~66) winsize 61
4004 12:18:02.834750 [CA 2] Center 33 (3~64) winsize 62
4005 12:18:02.838375 [CA 3] Center 33 (3~64) winsize 62
4006 12:18:02.841447 [CA 4] Center 33 (3~64) winsize 62
4007 12:18:02.845023 [CA 5] Center 33 (2~64) winsize 63
4008 12:18:02.845106
4009 12:18:02.848204 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4010 12:18:02.848286
4011 12:18:02.851665 [CATrainingPosCal] consider 2 rank data
4012 12:18:02.854928 u2DelayCellTimex100 = 270/100 ps
4013 12:18:02.858085 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4014 12:18:02.861162 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4015 12:18:02.867619 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4016 12:18:02.871800 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4017 12:18:02.874475 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4018 12:18:02.877704 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4019 12:18:02.877787
4020 12:18:02.880802 CA PerBit enable=1, Macro0, CA PI delay=33
4021 12:18:02.880884
4022 12:18:02.884450 [CBTSetCACLKResult] CA Dly = 33
4023 12:18:02.884531 CS Dly: 5 (0~36)
4024 12:18:02.887807
4025 12:18:02.890809 ----->DramcWriteLeveling(PI) begin...
4026 12:18:02.890892 ==
4027 12:18:02.894505 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 12:18:02.897594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 12:18:02.897676 ==
4030 12:18:02.901038 Write leveling (Byte 0): 32 => 32
4031 12:18:02.903949 Write leveling (Byte 1): 27 => 27
4032 12:18:02.907460 DramcWriteLeveling(PI) end<-----
4033 12:18:02.907542
4034 12:18:02.907606 ==
4035 12:18:02.910807 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 12:18:02.914148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 12:18:02.914230 ==
4038 12:18:02.917470 [Gating] SW mode calibration
4039 12:18:02.924167 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4040 12:18:02.930792 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4041 12:18:02.933656 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 12:18:02.937168 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 12:18:02.943415 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 12:18:02.946651 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4045 12:18:02.950211 0 9 16 | B1->B0 | 3131 2525 | 0 0 | (1 1) (0 0)
4046 12:18:02.957488 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 12:18:02.959950 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 12:18:02.963386 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 12:18:02.970136 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 12:18:02.973040 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 12:18:02.976425 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 12:18:02.982953 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4053 12:18:02.986327 0 10 16 | B1->B0 | 3535 4444 | 0 0 | (0 0) (0 0)
4054 12:18:02.989703 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 12:18:02.995975 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 12:18:02.999851 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 12:18:03.002930 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 12:18:03.009448 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 12:18:03.012822 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 12:18:03.015922 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4061 12:18:03.023016 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:18:03.025695 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:18:03.029182 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:18:03.035673 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:18:03.039086 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:18:03.042803 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:18:03.049148 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:18:03.052021 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:18:03.055473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:18:03.062298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:18:03.065684 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:18:03.069052 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:18:03.075251 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:18:03.078350 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:18:03.082229 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:18:03.088544 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4077 12:18:03.091921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4078 12:18:03.095232 Total UI for P1: 0, mck2ui 16
4079 12:18:03.098434 best dqsien dly found for B0: ( 0, 13, 12)
4080 12:18:03.102204 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 12:18:03.105122 Total UI for P1: 0, mck2ui 16
4082 12:18:03.108736 best dqsien dly found for B1: ( 0, 13, 16)
4083 12:18:03.111517 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4084 12:18:03.118049 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4085 12:18:03.118364
4086 12:18:03.121730 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4087 12:18:03.125359 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4088 12:18:03.128604 [Gating] SW calibration Done
4089 12:18:03.129040 ==
4090 12:18:03.131496 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 12:18:03.135347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 12:18:03.135827 ==
4093 12:18:03.138318 RX Vref Scan: 0
4094 12:18:03.138756
4095 12:18:03.139150 RX Vref 0 -> 0, step: 1
4096 12:18:03.139496
4097 12:18:03.141397 RX Delay -230 -> 252, step: 16
4098 12:18:03.144931 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4099 12:18:03.151638 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4100 12:18:03.154656 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4101 12:18:03.157843 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4102 12:18:03.161639 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4103 12:18:03.167850 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4104 12:18:03.170946 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4105 12:18:03.174191 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4106 12:18:03.177329 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4107 12:18:03.180560 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4108 12:18:03.187075 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4109 12:18:03.190572 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4110 12:18:03.193777 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4111 12:18:03.197320 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4112 12:18:03.203693 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4113 12:18:03.207357 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4114 12:18:03.207536 ==
4115 12:18:03.210183 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 12:18:03.213797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 12:18:03.214023 ==
4118 12:18:03.216873 DQS Delay:
4119 12:18:03.217009 DQS0 = 0, DQS1 = 0
4120 12:18:03.220053 DQM Delay:
4121 12:18:03.220286 DQM0 = 42, DQM1 = 31
4122 12:18:03.220415 DQ Delay:
4123 12:18:03.223270 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4124 12:18:03.227018 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =49
4125 12:18:03.229951 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4126 12:18:03.233363 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4127 12:18:03.233489
4128 12:18:03.233574
4129 12:18:03.236824 ==
4130 12:18:03.240103 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 12:18:04.072108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 12:18:04.072301 ==
4133 12:18:04.072434
4134 12:18:04.072540
4135 12:18:04.072602 TX Vref Scan disable
4136 12:18:04.072665 == TX Byte 0 ==
4137 12:18:04.072784 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4138 12:18:04.072877 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4139 12:18:04.072981 == TX Byte 1 ==
4140 12:18:04.073102 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4141 12:18:04.073192 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4142 12:18:04.073281 ==
4143 12:18:04.073369 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 12:18:04.073461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 12:18:04.073549 ==
4146 12:18:04.073638
4147 12:18:04.073726
4148 12:18:04.073814 TX Vref Scan disable
4149 12:18:04.073905 == TX Byte 0 ==
4150 12:18:04.073993 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4151 12:18:04.074083 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4152 12:18:04.074169 == TX Byte 1 ==
4153 12:18:04.074258 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4154 12:18:04.074345 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4155 12:18:04.074432
4156 12:18:04.074516 [DATLAT]
4157 12:18:04.074576 Freq=600, CH0 RK0
4158 12:18:04.074636
4159 12:18:04.074697 DATLAT Default: 0x9
4160 12:18:04.074757 0, 0xFFFF, sum = 0
4161 12:18:04.074848 1, 0xFFFF, sum = 0
4162 12:18:04.074937 2, 0xFFFF, sum = 0
4163 12:18:04.075035 3, 0xFFFF, sum = 0
4164 12:18:04.075123 4, 0xFFFF, sum = 0
4165 12:18:04.075216 5, 0xFFFF, sum = 0
4166 12:18:04.075322 6, 0xFFFF, sum = 0
4167 12:18:04.075406 7, 0xFFFF, sum = 0
4168 12:18:04.075513 8, 0x0, sum = 1
4169 12:18:04.075603 9, 0x0, sum = 2
4170 12:18:04.075693 10, 0x0, sum = 3
4171 12:18:04.075824 11, 0x0, sum = 4
4172 12:18:04.075912 best_step = 9
4173 12:18:04.076000
4174 12:18:04.076088 ==
4175 12:18:04.076177 Dram Type= 6, Freq= 0, CH_0, rank 0
4176 12:18:04.076265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4177 12:18:04.076349 ==
4178 12:18:04.076426 RX Vref Scan: 1
4179 12:18:04.076499
4180 12:18:04.076641 RX Vref 0 -> 0, step: 1
4181 12:18:04.076756
4182 12:18:04.076853 RX Delay -195 -> 252, step: 8
4183 12:18:04.076968
4184 12:18:04.077082 Set Vref, RX VrefLevel [Byte0]: 60
4185 12:18:04.077183 [Byte1]: 48
4186 12:18:04.077271
4187 12:18:04.077356 Final RX Vref Byte 0 = 60 to rank0
4188 12:18:04.077441 Final RX Vref Byte 1 = 48 to rank0
4189 12:18:04.077530 Final RX Vref Byte 0 = 60 to rank1
4190 12:18:04.077618 Final RX Vref Byte 1 = 48 to rank1==
4191 12:18:04.077707 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 12:18:04.077795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 12:18:04.077881 ==
4194 12:18:04.077969 DQS Delay:
4195 12:18:04.078056 DQS0 = 0, DQS1 = 0
4196 12:18:04.078144 DQM Delay:
4197 12:18:04.078233 DQM0 = 43, DQM1 = 32
4198 12:18:04.078321 DQ Delay:
4199 12:18:04.078406 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4200 12:18:04.078495 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4201 12:18:04.078579 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4202 12:18:04.078666 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4203 12:18:04.078759
4204 12:18:04.078845
4205 12:18:04.078932 [DQSOSCAuto] RK0, (LSB)MR18= 0x6c43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4206 12:18:04.079060 CH0 RK0: MR19=808, MR18=6C43
4207 12:18:04.079159 CH0_RK0: MR19=0x808, MR18=0x6C43, DQSOSC=389, MR23=63, INC=173, DEC=115
4208 12:18:04.079292
4209 12:18:04.079407 ----->DramcWriteLeveling(PI) begin...
4210 12:18:04.079520 ==
4211 12:18:04.079610 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 12:18:04.079695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 12:18:04.079790 ==
4214 12:18:04.079880 Write leveling (Byte 0): 32 => 32
4215 12:18:04.079967 Write leveling (Byte 1): 31 => 31
4216 12:18:04.080055 DramcWriteLeveling(PI) end<-----
4217 12:18:04.080145
4218 12:18:04.080265 ==
4219 12:18:04.080419 Dram Type= 6, Freq= 0, CH_0, rank 1
4220 12:18:04.080507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4221 12:18:04.080596 ==
4222 12:18:04.080684 [Gating] SW mode calibration
4223 12:18:04.080777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4224 12:18:04.080891 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4225 12:18:04.080989 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 12:18:04.081072 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 12:18:04.081155 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 12:18:04.081238 0 9 12 | B1->B0 | 3333 3030 | 1 0 | (1 0) (0 1)
4229 12:18:04.081321 0 9 16 | B1->B0 | 2d2d 2626 | 1 0 | (1 0) (0 0)
4230 12:18:04.081403 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 12:18:04.081486 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 12:18:04.081582 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 12:18:04.081706 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 12:18:04.081788 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 12:18:04.081871 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 12:18:04.081953 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4237 12:18:04.082056 0 10 16 | B1->B0 | 3939 3e3e | 0 0 | (1 1) (0 0)
4238 12:18:04.082156 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 12:18:04.082239 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 12:18:04.082321 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 12:18:04.082404 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 12:18:04.082486 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 12:18:04.082569 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 12:18:04.082651 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4245 12:18:04.082739 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4246 12:18:04.082794 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:18:04.082848 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:18:04.082901 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:18:04.082954 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:18:04.083006 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:18:04.083073 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:18:04.083141 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:18:04.083212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:18:04.083296 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:18:04.083408 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:18:04.083522 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:18:04.083604 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:18:04.083687 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:18:04.084016 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:18:04.084106 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4261 12:18:04.084190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4262 12:18:04.084273 Total UI for P1: 0, mck2ui 16
4263 12:18:04.084357 best dqsien dly found for B0: ( 0, 13, 12)
4264 12:18:04.084441 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 12:18:04.084523 Total UI for P1: 0, mck2ui 16
4266 12:18:04.084606 best dqsien dly found for B1: ( 0, 13, 16)
4267 12:18:04.084689 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4268 12:18:04.084771 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4269 12:18:04.084853
4270 12:18:04.084935 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4271 12:18:04.085017 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4272 12:18:04.085098 [Gating] SW calibration Done
4273 12:18:04.085197 ==
4274 12:18:04.085281 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 12:18:04.085360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 12:18:04.085416 ==
4277 12:18:04.085469 RX Vref Scan: 0
4278 12:18:04.085522
4279 12:18:04.085575 RX Vref 0 -> 0, step: 1
4280 12:18:04.085630
4281 12:18:04.085683 RX Delay -230 -> 252, step: 16
4282 12:18:04.085735 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4283 12:18:04.085789 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4284 12:18:04.085841 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4285 12:18:04.085894 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4286 12:18:04.085946 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4287 12:18:04.086008 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4288 12:18:04.086092 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4289 12:18:04.086146 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4290 12:18:04.086198 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4291 12:18:04.086252 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4292 12:18:04.086304 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4293 12:18:04.086357 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4294 12:18:04.086409 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4295 12:18:04.086462 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4296 12:18:04.086514 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4297 12:18:04.086567 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4298 12:18:04.086619 ==
4299 12:18:04.086672 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 12:18:04.086724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 12:18:04.086776 ==
4302 12:18:04.086828 DQS Delay:
4303 12:18:04.086881 DQS0 = 0, DQS1 = 0
4304 12:18:04.086933 DQM Delay:
4305 12:18:04.086985 DQM0 = 41, DQM1 = 34
4306 12:18:04.087037 DQ Delay:
4307 12:18:04.087090 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4308 12:18:04.087142 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4309 12:18:04.087193 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4310 12:18:04.087280 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4311 12:18:04.087361
4312 12:18:04.087441
4313 12:18:04.087521 ==
4314 12:18:04.087620 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 12:18:04.087704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 12:18:04.087790 ==
4317 12:18:04.087844
4318 12:18:04.087897
4319 12:18:04.087949 TX Vref Scan disable
4320 12:18:04.088002 == TX Byte 0 ==
4321 12:18:04.088054 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4322 12:18:04.088107 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4323 12:18:04.088162 == TX Byte 1 ==
4324 12:18:04.088252 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4325 12:18:04.088305 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4326 12:18:04.088357 ==
4327 12:18:04.088409 Dram Type= 6, Freq= 0, CH_0, rank 1
4328 12:18:04.088461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4329 12:18:04.088514 ==
4330 12:18:04.088566
4331 12:18:04.088617
4332 12:18:04.088669 TX Vref Scan disable
4333 12:18:04.088720 == TX Byte 0 ==
4334 12:18:04.088772 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4335 12:18:04.088824 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4336 12:18:04.088877 == TX Byte 1 ==
4337 12:18:04.088929 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4338 12:18:04.088981 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4339 12:18:04.089033
4340 12:18:04.089084 [DATLAT]
4341 12:18:04.089137 Freq=600, CH0 RK1
4342 12:18:04.089191
4343 12:18:04.089243 DATLAT Default: 0x9
4344 12:18:04.089295 0, 0xFFFF, sum = 0
4345 12:18:04.089348 1, 0xFFFF, sum = 0
4346 12:18:04.089401 2, 0xFFFF, sum = 0
4347 12:18:04.089454 3, 0xFFFF, sum = 0
4348 12:18:04.089507 4, 0xFFFF, sum = 0
4349 12:18:04.089560 5, 0xFFFF, sum = 0
4350 12:18:04.089612 6, 0xFFFF, sum = 0
4351 12:18:04.089665 7, 0xFFFF, sum = 0
4352 12:18:04.089721 8, 0x0, sum = 1
4353 12:18:04.089779 9, 0x0, sum = 2
4354 12:18:04.089862 10, 0x0, sum = 3
4355 12:18:04.089915 11, 0x0, sum = 4
4356 12:18:04.089968 best_step = 9
4357 12:18:04.090020
4358 12:18:04.090071 ==
4359 12:18:04.090123 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 12:18:04.090175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 12:18:04.090228 ==
4362 12:18:04.090280 RX Vref Scan: 0
4363 12:18:04.090332
4364 12:18:04.090384 RX Vref 0 -> 0, step: 1
4365 12:18:04.090436
4366 12:18:04.090488 RX Delay -179 -> 252, step: 8
4367 12:18:04.090540 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4368 12:18:04.090593 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4369 12:18:04.090644 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4370 12:18:04.090696 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4371 12:18:04.090748 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4372 12:18:04.090799 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4373 12:18:04.090851 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4374 12:18:04.090903 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4375 12:18:04.090955 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4376 12:18:04.091006 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4377 12:18:04.091058 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4378 12:18:04.091110 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4379 12:18:04.091162 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4380 12:18:04.091214 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4381 12:18:04.091265 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4382 12:18:04.091317 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4383 12:18:04.091370 ==
4384 12:18:04.091422 Dram Type= 6, Freq= 0, CH_0, rank 1
4385 12:18:04.091500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 12:18:04.091567 ==
4387 12:18:04.091619 DQS Delay:
4388 12:18:04.091671 DQS0 = 0, DQS1 = 0
4389 12:18:04.091748 DQM Delay:
4390 12:18:04.091823 DQM0 = 41, DQM1 = 36
4391 12:18:04.091876 DQ Delay:
4392 12:18:04.091928 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4393 12:18:04.091980 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4394 12:18:04.092032 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4395 12:18:04.092084 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4396 12:18:04.092136
4397 12:18:04.092187
4398 12:18:04.092430 [DQSOSCAuto] RK1, (LSB)MR18= 0x6114, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4399 12:18:04.092490 CH0 RK1: MR19=808, MR18=6114
4400 12:18:04.092545 CH0_RK1: MR19=0x808, MR18=0x6114, DQSOSC=391, MR23=63, INC=171, DEC=114
4401 12:18:04.092598 [RxdqsGatingPostProcess] freq 600
4402 12:18:04.092651 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4403 12:18:04.092704 Pre-setting of DQS Precalculation
4404 12:18:04.092757 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4405 12:18:04.092819 ==
4406 12:18:04.092873 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 12:18:04.092925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 12:18:04.092978 ==
4409 12:18:04.093030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4410 12:18:04.093083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4411 12:18:04.093134 [CA 0] Center 35 (5~66) winsize 62
4412 12:18:04.093187 [CA 1] Center 35 (5~66) winsize 62
4413 12:18:04.093238 [CA 2] Center 34 (3~65) winsize 63
4414 12:18:04.093290 [CA 3] Center 33 (3~64) winsize 62
4415 12:18:04.093341 [CA 4] Center 34 (4~65) winsize 62
4416 12:18:04.093393 [CA 5] Center 33 (3~64) winsize 62
4417 12:18:04.093444
4418 12:18:04.093496 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4419 12:18:04.093548
4420 12:18:04.093599 [CATrainingPosCal] consider 1 rank data
4421 12:18:04.093651 u2DelayCellTimex100 = 270/100 ps
4422 12:18:04.093704 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4423 12:18:04.093757 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4424 12:18:04.093809 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4425 12:18:04.093861 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 12:18:04.093913 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4427 12:18:04.093965 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4428 12:18:04.094016
4429 12:18:04.094068 CA PerBit enable=1, Macro0, CA PI delay=33
4430 12:18:04.094119
4431 12:18:04.094171 [CBTSetCACLKResult] CA Dly = 33
4432 12:18:04.094223 CS Dly: 5 (0~36)
4433 12:18:04.094275 ==
4434 12:18:04.094327 Dram Type= 6, Freq= 0, CH_1, rank 1
4435 12:18:04.094380 fsp= 0, odt_onoff= 0, Byte mode=nk 1
4436 12:18:04.094432 fsp= 0, odt_onoff= 0, Byte mode=nd=95, pi_step=1, new_cbt_mode=1, autok=0
4437 12:18:04.094485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4438 12:18:04.094538 [CA 0] Center 35 (5~66) winsize 62
4439 12:18:04.094590 [CA 1] Center 36 (6~66) winsize 61
4440 12:18:04.094654 [CA 2] Center 34 (4~65) winsize 62
4441 12:18:04.096612 [CA 3] Center 34 (3~65) winsize 63
4442 12:18:04.099481 [CA 4] Center 34 (3~65) winsize 63
4443 12:18:04.102672 [CA 5] Center 34 (3~65) winsize 63
4444 12:18:04.102753
4445 12:18:04.105860 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4446 12:18:04.105956
4447 12:18:04.109657 [CATrainingPosCal] consider 2 rank data
4448 12:18:04.112755 u2DelayCellTimex100 = 270/100 ps
4449 12:18:04.116187 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4450 12:18:04.122519 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4451 12:18:04.126181 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4452 12:18:04.129126 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4453 12:18:04.132887 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4454 12:18:04.136478 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4455 12:18:04.136559
4456 12:18:04.139354 CA PerBit enable=1, Macro0, CA PI delay=33
4457 12:18:04.139435
4458 12:18:04.142848 [CBTSetCACLKResult] CA Dly = 33
4459 12:18:04.146275 CS Dly: 4 (0~35)
4460 12:18:04.146381
4461 12:18:04.149383 ----->DramcWriteLeveling(PI) begin...
4462 12:18:04.149467 ==
4463 12:18:04.152829 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 12:18:04.156020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 12:18:04.156101 ==
4466 12:18:04.159068 Write leveling (Byte 0): 30 => 30
4467 12:18:04.162281 Write leveling (Byte 1): 30 => 30
4468 12:18:04.166196 DramcWriteLeveling(PI) end<-----
4469 12:18:04.166280
4470 12:18:04.166352 ==
4471 12:18:04.168996 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 12:18:04.172390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 12:18:04.172472 ==
4474 12:18:04.175637 [Gating] SW mode calibration
4475 12:18:04.181956 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4476 12:18:04.188908 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4477 12:18:04.192403 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 12:18:04.195672 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 12:18:04.202644 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4480 12:18:04.205811 0 9 12 | B1->B0 | 3030 2929 | 0 0 | (0 1) (0 0)
4481 12:18:04.208789 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4482 12:18:04.215423 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 12:18:04.218698 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 12:18:04.221671 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 12:18:04.228590 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 12:18:04.231893 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 12:18:04.235554 0 10 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4488 12:18:04.241750 0 10 12 | B1->B0 | 2c2c 4040 | 1 0 | (0 0) (0 0)
4489 12:18:04.245205 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 12:18:04.248476 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 12:18:04.255011 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 12:18:04.258555 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 12:18:04.261331 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 12:18:04.268222 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 12:18:04.271276 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 12:18:04.274603 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4497 12:18:04.281296 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:18:04.284648 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:18:04.288230 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:18:04.294208 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:18:04.297599 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:18:04.301027 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:18:04.307539 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:18:04.310774 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:18:04.314232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:18:04.321184 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:18:04.324579 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:18:04.327787 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:18:04.333997 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:18:04.337186 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:18:04.340648 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:18:04.347462 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4513 12:18:04.347638 Total UI for P1: 0, mck2ui 16
4514 12:18:04.354124 best dqsien dly found for B0: ( 0, 13, 10)
4515 12:18:04.357398 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 12:18:04.360539 Total UI for P1: 0, mck2ui 16
4517 12:18:04.363636 best dqsien dly found for B1: ( 0, 13, 12)
4518 12:18:04.367282 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4519 12:18:04.370472 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4520 12:18:04.370641
4521 12:18:04.373503 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4522 12:18:04.377164 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4523 12:18:04.379997 [Gating] SW calibration Done
4524 12:18:04.380111 ==
4525 12:18:04.383455 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 12:18:04.390223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 12:18:04.390366 ==
4528 12:18:04.390437 RX Vref Scan: 0
4529 12:18:04.390502
4530 12:18:04.394028 RX Vref 0 -> 0, step: 1
4531 12:18:04.394130
4532 12:18:04.396524 RX Delay -230 -> 252, step: 16
4533 12:18:04.399888 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4534 12:18:04.403137 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4535 12:18:04.406653 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4536 12:18:04.413065 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4537 12:18:04.416728 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4538 12:18:04.419610 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4539 12:18:04.423079 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4540 12:18:04.430620 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4541 12:18:04.433407 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4542 12:18:04.436760 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4543 12:18:04.439761 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4544 12:18:04.442777 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4545 12:18:04.449457 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4546 12:18:04.453158 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4547 12:18:04.456673 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4548 12:18:04.459622 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4549 12:18:04.462919 ==
4550 12:18:04.466019 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 12:18:04.469556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 12:18:04.469654 ==
4553 12:18:04.469732 DQS Delay:
4554 12:18:04.473234 DQS0 = 0, DQS1 = 0
4555 12:18:04.473339 DQM Delay:
4556 12:18:04.476292 DQM0 = 43, DQM1 = 32
4557 12:18:04.476403 DQ Delay:
4558 12:18:04.479694 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4559 12:18:04.482475 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4560 12:18:04.485861 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4561 12:18:04.489768 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4562 12:18:04.489911
4563 12:18:04.490025
4564 12:18:04.490130 ==
4565 12:18:04.492494 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 12:18:04.495957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 12:18:04.496121 ==
4568 12:18:04.496251
4569 12:18:04.496370
4570 12:18:04.499370 TX Vref Scan disable
4571 12:18:04.502868 == TX Byte 0 ==
4572 12:18:04.506023 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4573 12:18:04.509438 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4574 12:18:04.512839 == TX Byte 1 ==
4575 12:18:04.516123 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4576 12:18:04.519582 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4577 12:18:04.520122 ==
4578 12:18:04.522289 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 12:18:04.529227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 12:18:04.529659 ==
4581 12:18:04.529999
4582 12:18:04.530314
4583 12:18:04.530619 TX Vref Scan disable
4584 12:18:04.533364 == TX Byte 0 ==
4585 12:18:04.537113 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4586 12:18:04.543868 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4587 12:18:04.544208 == TX Byte 1 ==
4588 12:18:04.546872 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4589 12:18:04.553135 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4590 12:18:04.553385
4591 12:18:04.553615 [DATLAT]
4592 12:18:04.553837 Freq=600, CH1 RK0
4593 12:18:04.554059
4594 12:18:04.556536 DATLAT Default: 0x9
4595 12:18:04.556724 0, 0xFFFF, sum = 0
4596 12:18:04.559822 1, 0xFFFF, sum = 0
4597 12:18:04.563390 2, 0xFFFF, sum = 0
4598 12:18:04.563605 3, 0xFFFF, sum = 0
4599 12:18:04.566139 4, 0xFFFF, sum = 0
4600 12:18:04.566308 5, 0xFFFF, sum = 0
4601 12:18:04.569669 6, 0xFFFF, sum = 0
4602 12:18:04.569819 7, 0xFFFF, sum = 0
4603 12:18:04.572600 8, 0x0, sum = 1
4604 12:18:04.572721 9, 0x0, sum = 2
4605 12:18:04.575994 10, 0x0, sum = 3
4606 12:18:04.576142 11, 0x0, sum = 4
4607 12:18:04.576240 best_step = 9
4608 12:18:04.576327
4609 12:18:04.579426 ==
4610 12:18:04.582808 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 12:18:04.585820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 12:18:04.585939 ==
4613 12:18:04.586034 RX Vref Scan: 1
4614 12:18:04.586121
4615 12:18:04.589255 RX Vref 0 -> 0, step: 1
4616 12:18:04.589371
4617 12:18:04.592685 RX Delay -195 -> 252, step: 8
4618 12:18:04.592802
4619 12:18:04.595924 Set Vref, RX VrefLevel [Byte0]: 47
4620 12:18:04.599099 [Byte1]: 59
4621 12:18:04.599214
4622 12:18:04.602650 Final RX Vref Byte 0 = 47 to rank0
4623 12:18:04.605681 Final RX Vref Byte 1 = 59 to rank0
4624 12:18:04.609009 Final RX Vref Byte 0 = 47 to rank1
4625 12:18:04.612514 Final RX Vref Byte 1 = 59 to rank1==
4626 12:18:04.615341 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 12:18:04.618712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 12:18:04.622158 ==
4629 12:18:04.622345 DQS Delay:
4630 12:18:04.622493 DQS0 = 0, DQS1 = 0
4631 12:18:04.625740 DQM Delay:
4632 12:18:04.625930 DQM0 = 44, DQM1 = 34
4633 12:18:04.629595 DQ Delay:
4634 12:18:04.632218 DQ0 =48, DQ1 =40, DQ2 =36, DQ3 =40
4635 12:18:04.632483 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =36
4636 12:18:04.635450 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4637 12:18:04.642536 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4638 12:18:04.642968
4639 12:18:04.643358
4640 12:18:04.648645 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4641 12:18:04.652490 CH1 RK0: MR19=808, MR18=4C31
4642 12:18:04.658747 CH1_RK0: MR19=0x808, MR18=0x4C31, DQSOSC=395, MR23=63, INC=168, DEC=112
4643 12:18:04.659181
4644 12:18:04.662202 ----->DramcWriteLeveling(PI) begin...
4645 12:18:04.662637 ==
4646 12:18:04.665187 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 12:18:04.668592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 12:18:04.669024 ==
4649 12:18:04.671777 Write leveling (Byte 0): 29 => 29
4650 12:18:04.675114 Write leveling (Byte 1): 32 => 32
4651 12:18:04.678779 DramcWriteLeveling(PI) end<-----
4652 12:18:04.679206
4653 12:18:04.679544 ==
4654 12:18:04.681648 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 12:18:04.685414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 12:18:04.688289 ==
4657 12:18:04.688733 [Gating] SW mode calibration
4658 12:18:04.694862 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4659 12:18:04.701462 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4660 12:18:04.704686 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 12:18:04.711259 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 12:18:04.714499 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4663 12:18:04.717892 0 9 12 | B1->B0 | 2f2f 3333 | 1 0 | (1 1) (0 0)
4664 12:18:04.724726 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 12:18:04.727918 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 12:18:04.731409 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 12:18:04.737663 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 12:18:04.740699 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 12:18:04.744020 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 12:18:04.750777 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 12:18:04.753927 0 10 12 | B1->B0 | 3939 2f2f | 0 0 | (0 0) (0 0)
4672 12:18:04.757319 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
4673 12:18:04.763282 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 12:18:04.766664 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 12:18:04.770074 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 12:18:04.776776 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 12:18:04.780069 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 12:18:04.783000 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 12:18:04.789691 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 12:18:04.793423 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:18:04.796584 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:18:04.802969 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:18:04.806637 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:18:04.809700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:18:04.816145 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:18:04.819414 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:18:04.822778 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:18:04.829354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:18:04.832694 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:18:04.836088 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:18:04.842786 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:18:04.846346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:18:04.849605 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:18:04.855886 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:18:04.859036 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4696 12:18:04.862237 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 12:18:04.866183 Total UI for P1: 0, mck2ui 16
4698 12:18:04.868803 best dqsien dly found for B0: ( 0, 13, 12)
4699 12:18:04.872105 Total UI for P1: 0, mck2ui 16
4700 12:18:04.875756 best dqsien dly found for B1: ( 0, 13, 12)
4701 12:18:04.879299 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4702 12:18:04.885240 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4703 12:18:04.885324
4704 12:18:04.888669 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4705 12:18:04.892290 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4706 12:18:04.895423 [Gating] SW calibration Done
4707 12:18:04.895506 ==
4708 12:18:04.898701 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 12:18:04.901986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 12:18:04.902071 ==
4711 12:18:04.905196 RX Vref Scan: 0
4712 12:18:04.905279
4713 12:18:04.905344 RX Vref 0 -> 0, step: 1
4714 12:18:04.905405
4715 12:18:04.908532 RX Delay -230 -> 252, step: 16
4716 12:18:04.911865 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4717 12:18:04.918920 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4718 12:18:04.922250 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4719 12:18:04.925352 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4720 12:18:04.928728 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4721 12:18:04.931676 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4722 12:18:04.938467 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4723 12:18:04.941660 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4724 12:18:04.944888 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4725 12:18:04.948213 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4726 12:18:04.954927 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4727 12:18:04.958277 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4728 12:18:04.961535 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4729 12:18:04.964704 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4730 12:18:04.971650 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4731 12:18:04.974961 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4732 12:18:04.975062 ==
4733 12:18:04.978188 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 12:18:04.981442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 12:18:04.981526 ==
4736 12:18:04.984690 DQS Delay:
4737 12:18:04.984773 DQS0 = 0, DQS1 = 0
4738 12:18:04.984839 DQM Delay:
4739 12:18:04.987907 DQM0 = 41, DQM1 = 35
4740 12:18:04.987991 DQ Delay:
4741 12:18:04.991211 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4742 12:18:04.994567 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4743 12:18:04.997760 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4744 12:18:05.001114 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4745 12:18:05.001198
4746 12:18:05.001264
4747 12:18:05.001325 ==
4748 12:18:05.004508 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 12:18:05.011310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 12:18:05.011391 ==
4751 12:18:05.011456
4752 12:18:05.011517
4753 12:18:05.014404 TX Vref Scan disable
4754 12:18:05.014485 == TX Byte 0 ==
4755 12:18:05.017808 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4756 12:18:05.024394 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4757 12:18:05.024476 == TX Byte 1 ==
4758 12:18:05.030596 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4759 12:18:05.034087 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4760 12:18:05.034169 ==
4761 12:18:05.037585 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 12:18:05.040362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 12:18:05.040447 ==
4764 12:18:05.040512
4765 12:18:05.040571
4766 12:18:05.043921 TX Vref Scan disable
4767 12:18:05.047460 == TX Byte 0 ==
4768 12:18:05.050214 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4769 12:18:05.053596 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4770 12:18:05.056965 == TX Byte 1 ==
4771 12:18:05.060410 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4772 12:18:05.063584 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4773 12:18:05.063666
4774 12:18:05.067497 [DATLAT]
4775 12:18:05.067577 Freq=600, CH1 RK1
4776 12:18:05.067642
4777 12:18:05.070391 DATLAT Default: 0x9
4778 12:18:05.070473 0, 0xFFFF, sum = 0
4779 12:18:05.073903 1, 0xFFFF, sum = 0
4780 12:18:05.073986 2, 0xFFFF, sum = 0
4781 12:18:05.077141 3, 0xFFFF, sum = 0
4782 12:18:05.077223 4, 0xFFFF, sum = 0
4783 12:18:05.080694 5, 0xFFFF, sum = 0
4784 12:18:05.083327 6, 0xFFFF, sum = 0
4785 12:18:05.083409 7, 0xFFFF, sum = 0
4786 12:18:05.083474 8, 0x0, sum = 1
4787 12:18:05.086613 9, 0x0, sum = 2
4788 12:18:05.086697 10, 0x0, sum = 3
4789 12:18:05.090019 11, 0x0, sum = 4
4790 12:18:05.090101 best_step = 9
4791 12:18:05.090166
4792 12:18:05.090225 ==
4793 12:18:05.093378 Dram Type= 6, Freq= 0, CH_1, rank 1
4794 12:18:05.100042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4795 12:18:05.100124 ==
4796 12:18:05.100188 RX Vref Scan: 0
4797 12:18:05.100249
4798 12:18:05.103145 RX Vref 0 -> 0, step: 1
4799 12:18:05.103226
4800 12:18:05.106479 RX Delay -195 -> 252, step: 8
4801 12:18:05.109739 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4802 12:18:05.116589 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4803 12:18:05.119496 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4804 12:18:05.123237 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4805 12:18:05.126483 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4806 12:18:05.133184 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4807 12:18:05.136090 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4808 12:18:05.139578 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4809 12:18:05.142810 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4810 12:18:05.146362 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4811 12:18:05.152909 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4812 12:18:05.155957 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4813 12:18:05.159301 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4814 12:18:05.162948 iDelay=213, Bit 13, Center 44 (-115 ~ 204) 320
4815 12:18:05.169623 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4816 12:18:05.172847 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4817 12:18:05.172930 ==
4818 12:18:05.175929 Dram Type= 6, Freq= 0, CH_1, rank 1
4819 12:18:05.179121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4820 12:18:05.179204 ==
4821 12:18:05.182642 DQS Delay:
4822 12:18:05.182725 DQS0 = 0, DQS1 = 0
4823 12:18:05.182790 DQM Delay:
4824 12:18:05.185745 DQM0 = 42, DQM1 = 34
4825 12:18:05.185826 DQ Delay:
4826 12:18:05.189289 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4827 12:18:05.192489 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4828 12:18:05.195646 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4829 12:18:05.198869 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4830 12:18:05.198951
4831 12:18:05.199016
4832 12:18:05.208776 [DQSOSCAuto] RK1, (LSB)MR18= 0x332a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
4833 12:18:05.212242 CH1 RK1: MR19=808, MR18=332A
4834 12:18:05.215522 CH1_RK1: MR19=0x808, MR18=0x332A, DQSOSC=400, MR23=63, INC=163, DEC=109
4835 12:18:05.218668 [RxdqsGatingPostProcess] freq 600
4836 12:18:05.225793 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4837 12:18:05.228639 Pre-setting of DQS Precalculation
4838 12:18:05.232178 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4839 12:18:05.241965 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4840 12:18:05.248523 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4841 12:18:05.248605
4842 12:18:05.248669
4843 12:18:05.251609 [Calibration Summary] 1200 Mbps
4844 12:18:05.251691 CH 0, Rank 0
4845 12:18:05.255446 SW Impedance : PASS
4846 12:18:05.255527 DUTY Scan : NO K
4847 12:18:05.258799 ZQ Calibration : PASS
4848 12:18:05.261527 Jitter Meter : NO K
4849 12:18:05.261609 CBT Training : PASS
4850 12:18:05.264837 Write leveling : PASS
4851 12:18:05.268167 RX DQS gating : PASS
4852 12:18:05.268249 RX DQ/DQS(RDDQC) : PASS
4853 12:18:05.271902 TX DQ/DQS : PASS
4854 12:18:05.275042 RX DATLAT : PASS
4855 12:18:05.275124 RX DQ/DQS(Engine): PASS
4856 12:18:05.277977 TX OE : NO K
4857 12:18:05.278060 All Pass.
4858 12:18:05.278124
4859 12:18:05.281366 CH 0, Rank 1
4860 12:18:05.281448 SW Impedance : PASS
4861 12:18:05.284611 DUTY Scan : NO K
4862 12:18:05.287922 ZQ Calibration : PASS
4863 12:18:05.288004 Jitter Meter : NO K
4864 12:18:05.291021 CBT Training : PASS
4865 12:18:05.294510 Write leveling : PASS
4866 12:18:05.294600 RX DQS gating : PASS
4867 12:18:05.297738 RX DQ/DQS(RDDQC) : PASS
4868 12:18:05.301569 TX DQ/DQS : PASS
4869 12:18:05.301651 RX DATLAT : PASS
4870 12:18:05.304726 RX DQ/DQS(Engine): PASS
4871 12:18:05.307630 TX OE : NO K
4872 12:18:05.307712 All Pass.
4873 12:18:05.307815
4874 12:18:05.307875 CH 1, Rank 0
4875 12:18:05.311402 SW Impedance : PASS
4876 12:18:05.314543 DUTY Scan : NO K
4877 12:18:05.314625 ZQ Calibration : PASS
4878 12:18:05.317732 Jitter Meter : NO K
4879 12:18:05.320529 CBT Training : PASS
4880 12:18:05.320610 Write leveling : PASS
4881 12:18:05.324198 RX DQS gating : PASS
4882 12:18:05.327499 RX DQ/DQS(RDDQC) : PASS
4883 12:18:05.327580 TX DQ/DQS : PASS
4884 12:18:05.330574 RX DATLAT : PASS
4885 12:18:05.333968 RX DQ/DQS(Engine): PASS
4886 12:18:05.334050 TX OE : NO K
4887 12:18:05.334115 All Pass.
4888 12:18:05.334174
4889 12:18:05.337288 CH 1, Rank 1
4890 12:18:05.337370 SW Impedance : PASS
4891 12:18:05.340503 DUTY Scan : NO K
4892 12:18:05.343589 ZQ Calibration : PASS
4893 12:18:05.343670 Jitter Meter : NO K
4894 12:18:05.347235 CBT Training : PASS
4895 12:18:05.350580 Write leveling : PASS
4896 12:18:05.350662 RX DQS gating : PASS
4897 12:18:05.354009 RX DQ/DQS(RDDQC) : PASS
4898 12:18:05.356786 TX DQ/DQS : PASS
4899 12:18:05.356869 RX DATLAT : PASS
4900 12:18:05.360457 RX DQ/DQS(Engine): PASS
4901 12:18:05.363762 TX OE : NO K
4902 12:18:05.363857 All Pass.
4903 12:18:05.363922
4904 12:18:05.367059 DramC Write-DBI off
4905 12:18:05.367140 PER_BANK_REFRESH: Hybrid Mode
4906 12:18:05.369971 TX_TRACKING: ON
4907 12:18:05.380201 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4908 12:18:05.383599 [FAST_K] Save calibration result to emmc
4909 12:18:05.386445 dramc_set_vcore_voltage set vcore to 662500
4910 12:18:05.386528 Read voltage for 933, 3
4911 12:18:05.389617 Vio18 = 0
4912 12:18:05.389699 Vcore = 662500
4913 12:18:05.389764 Vdram = 0
4914 12:18:05.393465 Vddq = 0
4915 12:18:05.393547 Vmddr = 0
4916 12:18:05.399695 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4917 12:18:05.402752 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4918 12:18:05.406316 MEM_TYPE=3, freq_sel=17
4919 12:18:05.409764 sv_algorithm_assistance_LP4_1600
4920 12:18:05.413315 ============ PULL DRAM RESETB DOWN ============
4921 12:18:05.416717 ========== PULL DRAM RESETB DOWN end =========
4922 12:18:05.423075 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4923 12:18:05.426433 ===================================
4924 12:18:05.426515 LPDDR4 DRAM CONFIGURATION
4925 12:18:05.429610 ===================================
4926 12:18:05.432995 EX_ROW_EN[0] = 0x0
4927 12:18:05.436112 EX_ROW_EN[1] = 0x0
4928 12:18:05.436194 LP4Y_EN = 0x0
4929 12:18:05.439557 WORK_FSP = 0x0
4930 12:18:05.439639 WL = 0x3
4931 12:18:05.442838 RL = 0x3
4932 12:18:05.442919 BL = 0x2
4933 12:18:05.446217 RPST = 0x0
4934 12:18:05.446299 RD_PRE = 0x0
4935 12:18:05.449531 WR_PRE = 0x1
4936 12:18:05.449612 WR_PST = 0x0
4937 12:18:05.452787 DBI_WR = 0x0
4938 12:18:05.452869 DBI_RD = 0x0
4939 12:18:05.456287 OTF = 0x1
4940 12:18:05.459240 ===================================
4941 12:18:05.462389 ===================================
4942 12:18:05.462491 ANA top config
4943 12:18:05.465957 ===================================
4944 12:18:05.469208 DLL_ASYNC_EN = 0
4945 12:18:05.472573 ALL_SLAVE_EN = 1
4946 12:18:05.476021 NEW_RANK_MODE = 1
4947 12:18:05.476128 DLL_IDLE_MODE = 1
4948 12:18:05.479277 LP45_APHY_COMB_EN = 1
4949 12:18:05.482887 TX_ODT_DIS = 1
4950 12:18:05.485984 NEW_8X_MODE = 1
4951 12:18:05.489074 ===================================
4952 12:18:05.492476 ===================================
4953 12:18:05.495629 data_rate = 1866
4954 12:18:05.495774 CKR = 1
4955 12:18:05.498790 DQ_P2S_RATIO = 8
4956 12:18:05.502399 ===================================
4957 12:18:05.505310 CA_P2S_RATIO = 8
4958 12:18:05.508946 DQ_CA_OPEN = 0
4959 12:18:05.511848 DQ_SEMI_OPEN = 0
4960 12:18:05.515528 CA_SEMI_OPEN = 0
4961 12:18:05.515610 CA_FULL_RATE = 0
4962 12:18:05.518700 DQ_CKDIV4_EN = 1
4963 12:18:05.522029 CA_CKDIV4_EN = 1
4964 12:18:05.525246 CA_PREDIV_EN = 0
4965 12:18:05.528546 PH8_DLY = 0
4966 12:18:05.531646 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4967 12:18:05.531766 DQ_AAMCK_DIV = 4
4968 12:18:05.535068 CA_AAMCK_DIV = 4
4969 12:18:05.538355 CA_ADMCK_DIV = 4
4970 12:18:05.541834 DQ_TRACK_CA_EN = 0
4971 12:18:05.544933 CA_PICK = 933
4972 12:18:05.548650 CA_MCKIO = 933
4973 12:18:05.552094 MCKIO_SEMI = 0
4974 12:18:05.552176 PLL_FREQ = 3732
4975 12:18:05.555150 DQ_UI_PI_RATIO = 32
4976 12:18:05.558527 CA_UI_PI_RATIO = 0
4977 12:18:05.561631 ===================================
4978 12:18:05.565458 ===================================
4979 12:18:05.568655 memory_type:LPDDR4
4980 12:18:05.571495 GP_NUM : 10
4981 12:18:05.571676 SRAM_EN : 1
4982 12:18:05.575104 MD32_EN : 0
4983 12:18:05.578137 ===================================
4984 12:18:05.578318 [ANA_INIT] >>>>>>>>>>>>>>
4985 12:18:05.581866 <<<<<< [CONFIGURE PHASE]: ANA_TX
4986 12:18:05.584708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4987 12:18:05.587966 ===================================
4988 12:18:05.591656 data_rate = 1866,PCW = 0X8f00
4989 12:18:05.594892 ===================================
4990 12:18:05.598075 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4991 12:18:05.604603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 12:18:05.611529 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4993 12:18:05.615245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4994 12:18:05.618353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4995 12:18:05.621822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4996 12:18:05.624712 [ANA_INIT] flow start
4997 12:18:05.625182 [ANA_INIT] PLL >>>>>>>>
4998 12:18:05.628119 [ANA_INIT] PLL <<<<<<<<
4999 12:18:05.631481 [ANA_INIT] MIDPI >>>>>>>>
5000 12:18:05.631984 [ANA_INIT] MIDPI <<<<<<<<
5001 12:18:05.634712 [ANA_INIT] DLL >>>>>>>>
5002 12:18:05.638436 [ANA_INIT] flow end
5003 12:18:05.641208 ============ LP4 DIFF to SE enter ============
5004 12:18:05.644541 ============ LP4 DIFF to SE exit ============
5005 12:18:05.647853 [ANA_INIT] <<<<<<<<<<<<<
5006 12:18:05.651390 [Flow] Enable top DCM control >>>>>
5007 12:18:05.654717 [Flow] Enable top DCM control <<<<<
5008 12:18:05.657754 Enable DLL master slave shuffle
5009 12:18:05.664203 ==============================================================
5010 12:18:05.664753 Gating Mode config
5011 12:18:05.671052 ==============================================================
5012 12:18:05.671544 Config description:
5013 12:18:05.680613 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5014 12:18:05.686950 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5015 12:18:05.693351 SELPH_MODE 0: By rank 1: By Phase
5016 12:18:05.697506 ==============================================================
5017 12:18:05.700381 GAT_TRACK_EN = 1
5018 12:18:05.703613 RX_GATING_MODE = 2
5019 12:18:05.706925 RX_GATING_TRACK_MODE = 2
5020 12:18:05.710408 SELPH_MODE = 1
5021 12:18:05.714122 PICG_EARLY_EN = 1
5022 12:18:05.717238 VALID_LAT_VALUE = 1
5023 12:18:05.723302 ==============================================================
5024 12:18:05.726560 Enter into Gating configuration >>>>
5025 12:18:05.730552 Exit from Gating configuration <<<<
5026 12:18:05.733600 Enter into DVFS_PRE_config >>>>>
5027 12:18:05.743377 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5028 12:18:05.746582 Exit from DVFS_PRE_config <<<<<
5029 12:18:05.749664 Enter into PICG configuration >>>>
5030 12:18:05.752817 Exit from PICG configuration <<<<
5031 12:18:05.756142 [RX_INPUT] configuration >>>>>
5032 12:18:05.756611 [RX_INPUT] configuration <<<<<
5033 12:18:05.763143 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5034 12:18:05.769612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5035 12:18:05.776613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5036 12:18:05.779428 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5037 12:18:05.786386 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 12:18:05.792770 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 12:18:05.796069 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5040 12:18:05.799558 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5041 12:18:05.805918 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5042 12:18:05.809200 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5043 12:18:05.812248 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5044 12:18:05.819325 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 12:18:05.822243 ===================================
5046 12:18:05.822733 LPDDR4 DRAM CONFIGURATION
5047 12:18:05.825680 ===================================
5048 12:18:05.829107 EX_ROW_EN[0] = 0x0
5049 12:18:05.832435 EX_ROW_EN[1] = 0x0
5050 12:18:05.832924 LP4Y_EN = 0x0
5051 12:18:05.835373 WORK_FSP = 0x0
5052 12:18:05.835974 WL = 0x3
5053 12:18:05.838884 RL = 0x3
5054 12:18:05.839369 BL = 0x2
5055 12:18:05.841920 RPST = 0x0
5056 12:18:05.842381 RD_PRE = 0x0
5057 12:18:05.845815 WR_PRE = 0x1
5058 12:18:05.846382 WR_PST = 0x0
5059 12:18:05.848582 DBI_WR = 0x0
5060 12:18:05.849251 DBI_RD = 0x0
5061 12:18:05.851667 OTF = 0x1
5062 12:18:05.855453 ===================================
5063 12:18:05.858359 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5064 12:18:05.861526 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5065 12:18:05.868465 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5066 12:18:05.871618 ===================================
5067 12:18:05.872137 LPDDR4 DRAM CONFIGURATION
5068 12:18:05.874896 ===================================
5069 12:18:05.877973 EX_ROW_EN[0] = 0x10
5070 12:18:05.881480 EX_ROW_EN[1] = 0x0
5071 12:18:05.882044 LP4Y_EN = 0x0
5072 12:18:05.884648 WORK_FSP = 0x0
5073 12:18:05.885115 WL = 0x3
5074 12:18:05.888148 RL = 0x3
5075 12:18:05.888614 BL = 0x2
5076 12:18:05.891299 RPST = 0x0
5077 12:18:05.891800 RD_PRE = 0x0
5078 12:18:05.894405 WR_PRE = 0x1
5079 12:18:05.894870 WR_PST = 0x0
5080 12:18:05.897745 DBI_WR = 0x0
5081 12:18:05.898211 DBI_RD = 0x0
5082 12:18:05.901022 OTF = 0x1
5083 12:18:05.904232 ===================================
5084 12:18:05.911008 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5085 12:18:05.914344 nWR fixed to 30
5086 12:18:05.918096 [ModeRegInit_LP4] CH0 RK0
5087 12:18:05.918657 [ModeRegInit_LP4] CH0 RK1
5088 12:18:05.921100 [ModeRegInit_LP4] CH1 RK0
5089 12:18:05.924298 [ModeRegInit_LP4] CH1 RK1
5090 12:18:05.924764 match AC timing 9
5091 12:18:05.931276 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5092 12:18:05.934560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5093 12:18:05.937783 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5094 12:18:05.944053 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5095 12:18:05.948090 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5096 12:18:05.948654 ==
5097 12:18:05.950810 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 12:18:05.954167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 12:18:05.954740 ==
5100 12:18:05.960754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5101 12:18:05.967340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5102 12:18:05.970768 [CA 0] Center 37 (7~68) winsize 62
5103 12:18:05.973677 [CA 1] Center 37 (7~68) winsize 62
5104 12:18:05.977143 [CA 2] Center 34 (4~65) winsize 62
5105 12:18:05.980202 [CA 3] Center 35 (5~65) winsize 61
5106 12:18:05.983813 [CA 4] Center 34 (4~64) winsize 61
5107 12:18:05.987148 [CA 5] Center 33 (3~63) winsize 61
5108 12:18:05.987719
5109 12:18:05.990689 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5110 12:18:05.991261
5111 12:18:05.993876 [CATrainingPosCal] consider 1 rank data
5112 12:18:05.997292 u2DelayCellTimex100 = 270/100 ps
5113 12:18:06.000335 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5114 12:18:06.003412 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5115 12:18:06.006899 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5116 12:18:06.010793 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5117 12:18:06.017065 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5118 12:18:06.020208 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5119 12:18:06.020682
5120 12:18:06.023271 CA PerBit enable=1, Macro0, CA PI delay=33
5121 12:18:06.023779
5122 12:18:06.026564 [CBTSetCACLKResult] CA Dly = 33
5123 12:18:06.027044 CS Dly: 7 (0~38)
5124 12:18:06.027416 ==
5125 12:18:06.030315 Dram Type= 6, Freq= 0, CH_0, rank 1
5126 12:18:06.037104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 12:18:06.037673 ==
5128 12:18:06.039889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5129 12:18:06.046743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5130 12:18:06.049866 [CA 0] Center 37 (7~68) winsize 62
5131 12:18:06.053492 [CA 1] Center 37 (7~68) winsize 62
5132 12:18:06.056413 [CA 2] Center 34 (4~65) winsize 62
5133 12:18:06.059976 [CA 3] Center 35 (5~65) winsize 61
5134 12:18:06.063221 [CA 4] Center 33 (3~64) winsize 62
5135 12:18:06.066223 [CA 5] Center 33 (3~63) winsize 61
5136 12:18:06.066794
5137 12:18:06.069744 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5138 12:18:06.070317
5139 12:18:06.073267 [CATrainingPosCal] consider 2 rank data
5140 12:18:06.075931 u2DelayCellTimex100 = 270/100 ps
5141 12:18:06.079295 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5142 12:18:06.087090 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5143 12:18:06.089054 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5144 12:18:06.092985 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5145 12:18:06.095610 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5146 12:18:06.099899 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5147 12:18:06.100472
5148 12:18:06.102786 CA PerBit enable=1, Macro0, CA PI delay=33
5149 12:18:06.103251
5150 12:18:06.106121 [CBTSetCACLKResult] CA Dly = 33
5151 12:18:06.106591 CS Dly: 7 (0~39)
5152 12:18:06.109357
5153 12:18:06.112515 ----->DramcWriteLeveling(PI) begin...
5154 12:18:06.113094 ==
5155 12:18:06.115898 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 12:18:06.119687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 12:18:06.120319 ==
5158 12:18:06.122718 Write leveling (Byte 0): 34 => 34
5159 12:18:06.125706 Write leveling (Byte 1): 30 => 30
5160 12:18:06.129691 DramcWriteLeveling(PI) end<-----
5161 12:18:06.130279
5162 12:18:06.130657 ==
5163 12:18:06.132562 Dram Type= 6, Freq= 0, CH_0, rank 0
5164 12:18:06.136203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5165 12:18:06.136789 ==
5166 12:18:06.139038 [Gating] SW mode calibration
5167 12:18:06.145881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5168 12:18:06.152243 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5169 12:18:06.155776 0 14 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
5170 12:18:06.159089 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5171 12:18:06.165497 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 12:18:06.169195 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 12:18:06.172061 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 12:18:06.178645 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 12:18:06.182369 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 12:18:06.185564 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)
5177 12:18:06.192325 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
5178 12:18:06.195464 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 12:18:06.199048 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 12:18:06.205191 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 12:18:06.208516 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 12:18:06.211807 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 12:18:06.218480 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 12:18:06.221550 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5185 12:18:06.224677 1 0 0 | B1->B0 | 2f2f 4141 | 0 0 | (0 0) (0 0)
5186 12:18:06.231390 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 12:18:06.234934 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 12:18:06.238231 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 12:18:06.244940 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 12:18:06.248528 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 12:18:06.251811 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 12:18:06.258132 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 12:18:06.261617 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:18:06.264441 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:18:06.271234 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:18:06.274605 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:18:06.278320 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:18:06.285079 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:18:06.287923 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:18:06.291561 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:18:06.298297 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:18:06.301417 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:18:06.304217 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:18:06.310773 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:18:06.314192 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:18:06.318019 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:18:06.322112 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 12:18:06.327531 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5209 12:18:06.330930 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5210 12:18:06.334198 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 12:18:06.337436 Total UI for P1: 0, mck2ui 16
5212 12:18:06.341159 best dqsien dly found for B0: ( 1, 2, 30)
5213 12:18:06.344242 Total UI for P1: 0, mck2ui 16
5214 12:18:06.348144 best dqsien dly found for B1: ( 1, 3, 0)
5215 12:18:06.350483 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5216 12:18:06.354154 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5217 12:18:06.357577
5218 12:18:06.360925 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5219 12:18:06.364630 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5220 12:18:06.367679 [Gating] SW calibration Done
5221 12:18:06.368322 ==
5222 12:18:06.370718 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 12:18:06.373787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 12:18:06.374277 ==
5225 12:18:06.374778 RX Vref Scan: 0
5226 12:18:06.375247
5227 12:18:06.377300 RX Vref 0 -> 0, step: 1
5228 12:18:06.377786
5229 12:18:06.380283 RX Delay -80 -> 252, step: 8
5230 12:18:06.383935 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5231 12:18:06.387439 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5232 12:18:06.393878 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5233 12:18:06.396873 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5234 12:18:06.400017 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5235 12:18:06.403775 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5236 12:18:06.407143 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5237 12:18:06.410173 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5238 12:18:06.416717 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5239 12:18:06.420428 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5240 12:18:06.423425 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5241 12:18:06.426781 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5242 12:18:06.430828 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5243 12:18:06.436563 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5244 12:18:06.440005 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5245 12:18:06.443683 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5246 12:18:06.444329 ==
5247 12:18:06.446879 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 12:18:06.450101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 12:18:06.450656 ==
5250 12:18:06.453404 DQS Delay:
5251 12:18:06.453997 DQS0 = 0, DQS1 = 0
5252 12:18:06.456676 DQM Delay:
5253 12:18:06.457162 DQM0 = 96, DQM1 = 85
5254 12:18:06.457657 DQ Delay:
5255 12:18:06.459896 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5256 12:18:06.463251 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5257 12:18:06.466678 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5258 12:18:06.470417 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5259 12:18:06.471004
5260 12:18:06.471504
5261 12:18:06.473055 ==
5262 12:18:06.476557 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 12:18:06.480251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 12:18:06.480722 ==
5265 12:18:06.481091
5266 12:18:06.481434
5267 12:18:06.483256 TX Vref Scan disable
5268 12:18:06.483780 == TX Byte 0 ==
5269 12:18:06.489473 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5270 12:18:06.492836 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5271 12:18:06.493301 == TX Byte 1 ==
5272 12:18:06.499916 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5273 12:18:06.503148 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5274 12:18:06.503717 ==
5275 12:18:06.506259 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 12:18:06.509822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 12:18:06.510292 ==
5278 12:18:06.510662
5279 12:18:06.511003
5280 12:18:06.512850 TX Vref Scan disable
5281 12:18:06.515989 == TX Byte 0 ==
5282 12:18:06.519887 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5283 12:18:06.522707 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5284 12:18:06.526030 == TX Byte 1 ==
5285 12:18:06.529598 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5286 12:18:06.532518 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5287 12:18:06.533158
5288 12:18:06.535970 [DATLAT]
5289 12:18:06.536433 Freq=933, CH0 RK0
5290 12:18:06.536804
5291 12:18:06.539119 DATLAT Default: 0xd
5292 12:18:06.539597 0, 0xFFFF, sum = 0
5293 12:18:06.542893 1, 0xFFFF, sum = 0
5294 12:18:06.543367 2, 0xFFFF, sum = 0
5295 12:18:06.545924 3, 0xFFFF, sum = 0
5296 12:18:06.546508 4, 0xFFFF, sum = 0
5297 12:18:06.549749 5, 0xFFFF, sum = 0
5298 12:18:06.550329 6, 0xFFFF, sum = 0
5299 12:18:06.552485 7, 0xFFFF, sum = 0
5300 12:18:06.552960 8, 0xFFFF, sum = 0
5301 12:18:06.555633 9, 0xFFFF, sum = 0
5302 12:18:06.556159 10, 0x0, sum = 1
5303 12:18:06.558820 11, 0x0, sum = 2
5304 12:18:06.559328 12, 0x0, sum = 3
5305 12:18:06.562382 13, 0x0, sum = 4
5306 12:18:06.562851 best_step = 11
5307 12:18:06.563217
5308 12:18:06.563554 ==
5309 12:18:06.565542 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 12:18:06.572273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 12:18:06.572693 ==
5312 12:18:06.573106 RX Vref Scan: 1
5313 12:18:06.573424
5314 12:18:06.575610 RX Vref 0 -> 0, step: 1
5315 12:18:06.576225
5316 12:18:06.579094 RX Delay -61 -> 252, step: 4
5317 12:18:06.579510
5318 12:18:06.582276 Set Vref, RX VrefLevel [Byte0]: 60
5319 12:18:06.585452 [Byte1]: 48
5320 12:18:06.585874
5321 12:18:06.588432 Final RX Vref Byte 0 = 60 to rank0
5322 12:18:06.591797 Final RX Vref Byte 1 = 48 to rank0
5323 12:18:06.595316 Final RX Vref Byte 0 = 60 to rank1
5324 12:18:06.598535 Final RX Vref Byte 1 = 48 to rank1==
5325 12:18:06.602165 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 12:18:06.605267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 12:18:06.605775 ==
5328 12:18:06.609027 DQS Delay:
5329 12:18:06.609547 DQS0 = 0, DQS1 = 0
5330 12:18:06.611601 DQM Delay:
5331 12:18:06.612055 DQM0 = 97, DQM1 = 85
5332 12:18:06.612387 DQ Delay:
5333 12:18:06.614902 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =94
5334 12:18:06.618456 DQ4 =96, DQ5 =88, DQ6 =106, DQ7 =106
5335 12:18:06.621908 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
5336 12:18:06.624907 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =94
5337 12:18:06.628202
5338 12:18:06.628617
5339 12:18:06.634907 [DQSOSCAuto] RK0, (LSB)MR18= 0x3016, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 406 ps
5340 12:18:06.638063 CH0 RK0: MR19=505, MR18=3016
5341 12:18:06.644843 CH0_RK0: MR19=0x505, MR18=0x3016, DQSOSC=406, MR23=63, INC=65, DEC=43
5342 12:18:06.645419
5343 12:18:06.647958 ----->DramcWriteLeveling(PI) begin...
5344 12:18:06.648385 ==
5345 12:18:06.651160 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 12:18:06.654412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 12:18:06.654838 ==
5348 12:18:06.658269 Write leveling (Byte 0): 32 => 32
5349 12:18:06.661265 Write leveling (Byte 1): 30 => 30
5350 12:18:06.664406 DramcWriteLeveling(PI) end<-----
5351 12:18:06.664829
5352 12:18:06.665180 ==
5353 12:18:06.667999 Dram Type= 6, Freq= 0, CH_0, rank 1
5354 12:18:06.671305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5355 12:18:06.671762 ==
5356 12:18:06.674230 [Gating] SW mode calibration
5357 12:18:06.680681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5358 12:18:06.687608 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5359 12:18:06.690624 0 14 0 | B1->B0 | 2626 3232 | 1 1 | (1 1) (1 1)
5360 12:18:06.697512 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 12:18:06.701488 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 12:18:06.704183 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 12:18:06.710339 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 12:18:06.714009 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 12:18:06.716918 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5366 12:18:06.723697 0 14 28 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 0)
5367 12:18:06.726754 0 15 0 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
5368 12:18:06.730479 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5369 12:18:06.737114 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 12:18:06.740332 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 12:18:06.743632 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 12:18:06.750260 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 12:18:06.753432 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 12:18:06.756528 0 15 28 | B1->B0 | 2727 3636 | 0 0 | (0 0) (0 0)
5375 12:18:06.759990 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5376 12:18:06.766867 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 12:18:06.770093 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 12:18:06.773568 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 12:18:06.780275 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 12:18:06.783580 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 12:18:06.790044 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 12:18:06.792891 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5383 12:18:06.796507 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5384 12:18:06.799479 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:18:06.806250 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:18:06.809680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:18:06.813394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:18:06.819860 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:18:06.823446 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:18:06.826357 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:18:06.833331 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:18:06.835675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:18:06.839346 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:18:06.846411 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:18:06.849731 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:18:06.855854 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:18:06.859379 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:18:06.862647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5399 12:18:06.869122 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5400 12:18:06.869664 Total UI for P1: 0, mck2ui 16
5401 12:18:06.872236 best dqsien dly found for B0: ( 1, 2, 28)
5402 12:18:06.878764 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 12:18:06.881925 Total UI for P1: 0, mck2ui 16
5404 12:18:06.885281 best dqsien dly found for B1: ( 1, 2, 30)
5405 12:18:06.888586 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5406 12:18:06.891852 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5407 12:18:06.892334
5408 12:18:06.895375 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5409 12:18:06.898356 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5410 12:18:06.902073 [Gating] SW calibration Done
5411 12:18:06.902650 ==
5412 12:18:06.904989 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 12:18:06.908752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 12:18:06.909236 ==
5415 12:18:06.911472 RX Vref Scan: 0
5416 12:18:06.912006
5417 12:18:06.914841 RX Vref 0 -> 0, step: 1
5418 12:18:06.915319
5419 12:18:06.915922 RX Delay -80 -> 252, step: 8
5420 12:18:06.922177 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5421 12:18:06.925329 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5422 12:18:06.928317 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5423 12:18:06.931771 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5424 12:18:06.935204 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5425 12:18:06.938546 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5426 12:18:06.945640 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5427 12:18:06.948573 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5428 12:18:06.951815 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5429 12:18:06.955477 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5430 12:18:06.958458 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5431 12:18:06.964828 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5432 12:18:06.968146 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5433 12:18:06.971541 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5434 12:18:06.974655 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5435 12:18:06.977936 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5436 12:18:06.981147 ==
5437 12:18:06.981615 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 12:18:06.988063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 12:18:06.988548 ==
5440 12:18:06.988921 DQS Delay:
5441 12:18:06.991487 DQS0 = 0, DQS1 = 0
5442 12:18:06.992003 DQM Delay:
5443 12:18:06.994533 DQM0 = 98, DQM1 = 87
5444 12:18:06.994998 DQ Delay:
5445 12:18:06.998217 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5446 12:18:07.000824 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5447 12:18:07.004353 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5448 12:18:07.007496 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5449 12:18:07.008005
5450 12:18:07.008373
5451 12:18:07.008725 ==
5452 12:18:07.011429 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 12:18:07.014527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 12:18:07.015085 ==
5455 12:18:07.015459
5456 12:18:07.015844
5457 12:18:07.017680 TX Vref Scan disable
5458 12:18:07.021176 == TX Byte 0 ==
5459 12:18:07.024279 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5460 12:18:07.027228 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5461 12:18:07.030459 == TX Byte 1 ==
5462 12:18:07.033751 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5463 12:18:07.037317 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5464 12:18:07.037785 ==
5465 12:18:07.040703 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 12:18:07.047255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 12:18:07.047852 ==
5468 12:18:07.048258
5469 12:18:07.048610
5470 12:18:07.048937 TX Vref Scan disable
5471 12:18:07.051292 == TX Byte 0 ==
5472 12:18:07.055434 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5473 12:18:07.061406 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5474 12:18:07.061964 == TX Byte 1 ==
5475 12:18:07.064647 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5476 12:18:07.071081 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5477 12:18:07.071660
5478 12:18:07.072191 [DATLAT]
5479 12:18:07.072650 Freq=933, CH0 RK1
5480 12:18:07.073097
5481 12:18:07.074516 DATLAT Default: 0xb
5482 12:18:07.078002 0, 0xFFFF, sum = 0
5483 12:18:07.078495 1, 0xFFFF, sum = 0
5484 12:18:07.080654 2, 0xFFFF, sum = 0
5485 12:18:07.081144 3, 0xFFFF, sum = 0
5486 12:18:07.084050 4, 0xFFFF, sum = 0
5487 12:18:07.084541 5, 0xFFFF, sum = 0
5488 12:18:07.087876 6, 0xFFFF, sum = 0
5489 12:18:07.088377 7, 0xFFFF, sum = 0
5490 12:18:07.090838 8, 0xFFFF, sum = 0
5491 12:18:07.091330 9, 0xFFFF, sum = 0
5492 12:18:07.093984 10, 0x0, sum = 1
5493 12:18:07.094472 11, 0x0, sum = 2
5494 12:18:07.097461 12, 0x0, sum = 3
5495 12:18:07.098055 13, 0x0, sum = 4
5496 12:18:07.100933 best_step = 11
5497 12:18:07.101413
5498 12:18:07.101900 ==
5499 12:18:07.104128 Dram Type= 6, Freq= 0, CH_0, rank 1
5500 12:18:07.107465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 12:18:07.108196 ==
5502 12:18:07.108617 RX Vref Scan: 0
5503 12:18:07.110498
5504 12:18:07.110961 RX Vref 0 -> 0, step: 1
5505 12:18:07.111332
5506 12:18:07.113784 RX Delay -61 -> 252, step: 4
5507 12:18:07.120552 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5508 12:18:07.123773 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5509 12:18:07.127131 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5510 12:18:07.130506 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5511 12:18:07.133974 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5512 12:18:07.136840 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5513 12:18:07.143538 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5514 12:18:07.146764 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5515 12:18:07.150064 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5516 12:18:07.152971 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5517 12:18:07.159690 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5518 12:18:07.163399 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5519 12:18:07.166183 iDelay=203, Bit 12, Center 94 (3 ~ 186) 184
5520 12:18:07.169567 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5521 12:18:07.173318 iDelay=203, Bit 14, Center 100 (11 ~ 190) 180
5522 12:18:07.179497 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5523 12:18:07.180017 ==
5524 12:18:07.182865 Dram Type= 6, Freq= 0, CH_0, rank 1
5525 12:18:07.186233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 12:18:07.186706 ==
5527 12:18:07.187079 DQS Delay:
5528 12:18:07.189551 DQS0 = 0, DQS1 = 0
5529 12:18:07.190035 DQM Delay:
5530 12:18:07.192622 DQM0 = 95, DQM1 = 87
5531 12:18:07.193087 DQ Delay:
5532 12:18:07.195775 DQ0 =92, DQ1 =98, DQ2 =90, DQ3 =94
5533 12:18:07.199311 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5534 12:18:07.202697 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5535 12:18:07.205716 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =92
5536 12:18:07.206218
5537 12:18:07.206615
5538 12:18:07.215445 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5539 12:18:07.216053 CH0 RK1: MR19=504, MR18=26F6
5540 12:18:07.222499 CH0_RK1: MR19=0x504, MR18=0x26F6, DQSOSC=409, MR23=63, INC=64, DEC=43
5541 12:18:07.226042 [RxdqsGatingPostProcess] freq 933
5542 12:18:07.232575 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5543 12:18:07.235663 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 12:18:07.238256 best DQS1 dly(2T, 0.5T) = (0, 11)
5545 12:18:07.242475 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 12:18:07.245093 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5547 12:18:07.248227 best DQS0 dly(2T, 0.5T) = (0, 10)
5548 12:18:07.252132 best DQS1 dly(2T, 0.5T) = (0, 10)
5549 12:18:07.254667 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5550 12:18:07.257900 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5551 12:18:07.261618 Pre-setting of DQS Precalculation
5552 12:18:07.264675 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5553 12:18:07.265145 ==
5554 12:18:07.268109 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 12:18:07.271176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 12:18:07.271645 ==
5557 12:18:07.278164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5558 12:18:07.284475 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5559 12:18:07.287709 [CA 0] Center 36 (6~67) winsize 62
5560 12:18:07.291321 [CA 1] Center 36 (6~67) winsize 62
5561 12:18:07.294605 [CA 2] Center 34 (4~64) winsize 61
5562 12:18:07.297739 [CA 3] Center 33 (3~64) winsize 62
5563 12:18:07.301107 [CA 4] Center 34 (4~64) winsize 61
5564 12:18:07.304010 [CA 5] Center 33 (3~64) winsize 62
5565 12:18:07.304433
5566 12:18:07.307370 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5567 12:18:07.307822
5568 12:18:07.311002 [CATrainingPosCal] consider 1 rank data
5569 12:18:07.314556 u2DelayCellTimex100 = 270/100 ps
5570 12:18:07.317761 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5571 12:18:07.321187 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5572 12:18:07.324160 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5573 12:18:07.327442 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5574 12:18:07.334239 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5575 12:18:07.337195 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5576 12:18:07.337619
5577 12:18:07.340755 CA PerBit enable=1, Macro0, CA PI delay=33
5578 12:18:07.341277
5579 12:18:07.344058 [CBTSetCACLKResult] CA Dly = 33
5580 12:18:07.344579 CS Dly: 6 (0~37)
5581 12:18:07.344917 ==
5582 12:18:07.347109 Dram Type= 6, Freq= 0, CH_1, rank 1
5583 12:18:07.353837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 12:18:07.354356 ==
5585 12:18:07.357612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5586 12:18:07.363507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5587 12:18:07.366896 [CA 0] Center 36 (6~67) winsize 62
5588 12:18:07.370315 [CA 1] Center 37 (7~67) winsize 61
5589 12:18:07.373827 [CA 2] Center 34 (4~65) winsize 62
5590 12:18:07.376586 [CA 3] Center 34 (3~65) winsize 63
5591 12:18:07.380458 [CA 4] Center 34 (4~65) winsize 62
5592 12:18:07.383271 [CA 5] Center 33 (3~64) winsize 62
5593 12:18:07.383690
5594 12:18:07.386862 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5595 12:18:07.387378
5596 12:18:07.390033 [CATrainingPosCal] consider 2 rank data
5597 12:18:07.393237 u2DelayCellTimex100 = 270/100 ps
5598 12:18:07.396961 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5599 12:18:07.403318 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5600 12:18:07.406416 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5601 12:18:07.409780 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5602 12:18:07.412985 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5603 12:18:07.416835 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5604 12:18:07.417373
5605 12:18:07.420413 CA PerBit enable=1, Macro0, CA PI delay=33
5606 12:18:07.420841
5607 12:18:07.423450 [CBTSetCACLKResult] CA Dly = 33
5608 12:18:07.423900 CS Dly: 7 (0~39)
5609 12:18:07.424243
5610 12:18:07.429672 ----->DramcWriteLeveling(PI) begin...
5611 12:18:07.430184 ==
5612 12:18:07.433267 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 12:18:07.436437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 12:18:07.436860 ==
5615 12:18:07.440485 Write leveling (Byte 0): 27 => 27
5616 12:18:07.443305 Write leveling (Byte 1): 27 => 27
5617 12:18:07.446887 DramcWriteLeveling(PI) end<-----
5618 12:18:07.447503
5619 12:18:07.447910 ==
5620 12:18:07.449920 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 12:18:07.453031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 12:18:07.453500 ==
5623 12:18:07.456542 [Gating] SW mode calibration
5624 12:18:07.462641 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5625 12:18:07.469791 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5626 12:18:07.472645 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5627 12:18:07.475768 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 12:18:07.482396 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 12:18:07.485672 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 12:18:07.489072 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 12:18:07.496573 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 12:18:07.499288 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
5633 12:18:07.502659 0 14 28 | B1->B0 | 2f2f 2b2b | 0 1 | (1 1) (1 1)
5634 12:18:07.508725 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5635 12:18:07.512384 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 12:18:07.515656 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 12:18:07.522716 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 12:18:07.525857 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 12:18:07.528719 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 12:18:07.535564 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5641 12:18:07.538682 0 15 28 | B1->B0 | 3737 3939 | 0 1 | (0 0) (0 0)
5642 12:18:07.541634 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5643 12:18:07.548228 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 12:18:07.551975 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 12:18:07.555169 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 12:18:07.561474 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 12:18:07.565062 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 12:18:07.568201 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5649 12:18:07.574793 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 12:18:07.578074 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5651 12:18:07.581418 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:18:07.588053 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:18:07.591462 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:18:07.594677 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:18:07.601049 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:18:07.604684 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:18:07.607795 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:18:07.614676 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:18:07.617886 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 12:18:07.620968 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 12:18:07.628100 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 12:18:07.630652 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:18:07.633920 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 12:18:07.640724 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5665 12:18:07.643876 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5666 12:18:07.647417 Total UI for P1: 0, mck2ui 16
5667 12:18:07.650766 best dqsien dly found for B0: ( 1, 2, 24)
5668 12:18:07.653843 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 12:18:07.657219 Total UI for P1: 0, mck2ui 16
5670 12:18:07.660495 best dqsien dly found for B1: ( 1, 2, 28)
5671 12:18:07.663866 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5672 12:18:07.666949 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5673 12:18:07.667534
5674 12:18:07.674367 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5675 12:18:07.677345 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5676 12:18:07.677882 [Gating] SW calibration Done
5677 12:18:07.680853 ==
5678 12:18:07.683832 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 12:18:07.687092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 12:18:07.687672 ==
5681 12:18:07.688266 RX Vref Scan: 0
5682 12:18:07.688808
5683 12:18:07.690071 RX Vref 0 -> 0, step: 1
5684 12:18:07.690629
5685 12:18:07.693595 RX Delay -80 -> 252, step: 8
5686 12:18:07.696767 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5687 12:18:07.699990 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5688 12:18:07.703595 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5689 12:18:07.710224 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5690 12:18:07.713256 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5691 12:18:07.716778 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5692 12:18:07.719821 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5693 12:18:07.723361 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5694 12:18:07.729842 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5695 12:18:07.733440 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5696 12:18:07.736392 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5697 12:18:07.739837 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5698 12:18:07.742927 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5699 12:18:07.749305 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5700 12:18:07.752917 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5701 12:18:07.756154 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5702 12:18:07.756716 ==
5703 12:18:07.759595 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 12:18:07.762773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 12:18:07.763288 ==
5706 12:18:07.765886 DQS Delay:
5707 12:18:07.766523 DQS0 = 0, DQS1 = 0
5708 12:18:07.768965 DQM Delay:
5709 12:18:07.769580 DQM0 = 102, DQM1 = 91
5710 12:18:07.770101 DQ Delay:
5711 12:18:07.772614 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5712 12:18:07.775963 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5713 12:18:07.778912 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5714 12:18:07.782342 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5715 12:18:07.785682
5716 12:18:07.785992
5717 12:18:07.786280 ==
5718 12:18:07.789029 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 12:18:07.792256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 12:18:07.792491 ==
5721 12:18:07.792672
5722 12:18:07.792837
5723 12:18:07.795324 TX Vref Scan disable
5724 12:18:07.795547 == TX Byte 0 ==
5725 12:18:07.802052 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5726 12:18:07.805196 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5727 12:18:07.805496 == TX Byte 1 ==
5728 12:18:07.811956 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5729 12:18:07.815309 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5730 12:18:07.815565 ==
5731 12:18:07.818669 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 12:18:07.821896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 12:18:07.822078 ==
5734 12:18:07.822246
5735 12:18:07.822478
5736 12:18:07.825150 TX Vref Scan disable
5737 12:18:07.827943 == TX Byte 0 ==
5738 12:18:07.831706 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5739 12:18:07.834832 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5740 12:18:07.838330 == TX Byte 1 ==
5741 12:18:07.842009 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5742 12:18:07.845235 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5743 12:18:07.848855
5744 12:18:07.849273 [DATLAT]
5745 12:18:07.849603 Freq=933, CH1 RK0
5746 12:18:07.849920
5747 12:18:07.851568 DATLAT Default: 0xd
5748 12:18:07.852032 0, 0xFFFF, sum = 0
5749 12:18:07.855113 1, 0xFFFF, sum = 0
5750 12:18:07.855554 2, 0xFFFF, sum = 0
5751 12:18:07.858231 3, 0xFFFF, sum = 0
5752 12:18:07.858727 4, 0xFFFF, sum = 0
5753 12:18:07.861316 5, 0xFFFF, sum = 0
5754 12:18:07.865007 6, 0xFFFF, sum = 0
5755 12:18:07.865431 7, 0xFFFF, sum = 0
5756 12:18:07.868203 8, 0xFFFF, sum = 0
5757 12:18:07.868627 9, 0xFFFF, sum = 0
5758 12:18:07.871570 10, 0x0, sum = 1
5759 12:18:07.872039 11, 0x0, sum = 2
5760 12:18:07.872382 12, 0x0, sum = 3
5761 12:18:07.874636 13, 0x0, sum = 4
5762 12:18:07.875059 best_step = 11
5763 12:18:07.875388
5764 12:18:07.878272 ==
5765 12:18:07.878788 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 12:18:07.884710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 12:18:07.885132 ==
5768 12:18:07.885468 RX Vref Scan: 1
5769 12:18:07.885780
5770 12:18:07.888317 RX Vref 0 -> 0, step: 1
5771 12:18:07.888736
5772 12:18:07.891584 RX Delay -69 -> 252, step: 4
5773 12:18:07.892074
5774 12:18:07.894836 Set Vref, RX VrefLevel [Byte0]: 47
5775 12:18:07.897941 [Byte1]: 59
5776 12:18:07.898357
5777 12:18:07.901263 Final RX Vref Byte 0 = 47 to rank0
5778 12:18:07.904532 Final RX Vref Byte 1 = 59 to rank0
5779 12:18:07.907986 Final RX Vref Byte 0 = 47 to rank1
5780 12:18:07.911321 Final RX Vref Byte 1 = 59 to rank1==
5781 12:18:07.914552 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 12:18:07.918430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 12:18:07.921236 ==
5784 12:18:07.921718 DQS Delay:
5785 12:18:07.922119 DQS0 = 0, DQS1 = 0
5786 12:18:07.924502 DQM Delay:
5787 12:18:07.925059 DQM0 = 100, DQM1 = 93
5788 12:18:07.927368 DQ Delay:
5789 12:18:07.930999 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5790 12:18:07.934149 DQ4 =98, DQ5 =110, DQ6 =108, DQ7 =98
5791 12:18:07.937319 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =82
5792 12:18:07.940497 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
5793 12:18:07.940984
5794 12:18:07.941443
5795 12:18:07.947601 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5796 12:18:07.951160 CH1 RK0: MR19=505, MR18=1E0E
5797 12:18:07.957110 CH1_RK0: MR19=0x505, MR18=0x1E0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5798 12:18:07.957643
5799 12:18:07.960943 ----->DramcWriteLeveling(PI) begin...
5800 12:18:07.961549 ==
5801 12:18:07.964418 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 12:18:07.967119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 12:18:07.967542 ==
5804 12:18:07.970624 Write leveling (Byte 0): 24 => 24
5805 12:18:07.973582 Write leveling (Byte 1): 27 => 27
5806 12:18:07.977239 DramcWriteLeveling(PI) end<-----
5807 12:18:07.977759
5808 12:18:07.978203 ==
5809 12:18:07.980355 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 12:18:07.986920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 12:18:07.987381 ==
5812 12:18:07.987717 [Gating] SW mode calibration
5813 12:18:07.997077 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5814 12:18:08.000323 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5815 12:18:08.003801 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5816 12:18:08.010121 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 12:18:08.013415 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 12:18:08.017052 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 12:18:08.023394 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 12:18:08.026693 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 12:18:08.030198 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
5822 12:18:08.036461 0 14 28 | B1->B0 | 2a2a 2e2e | 0 1 | (1 0) (1 0)
5823 12:18:08.039764 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5824 12:18:08.042984 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 12:18:08.050259 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 12:18:08.053071 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 12:18:08.056568 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 12:18:08.062712 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 12:18:08.066367 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5830 12:18:08.069792 0 15 28 | B1->B0 | 3a3a 3434 | 1 0 | (0 0) (0 0)
5831 12:18:08.076459 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 12:18:08.079444 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 12:18:08.082666 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 12:18:08.089421 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 12:18:08.092850 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 12:18:08.095694 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 12:18:08.102968 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5838 12:18:08.105616 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5839 12:18:08.109026 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:18:08.115933 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:18:08.118758 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:18:08.122246 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:18:08.128779 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:18:08.132158 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:18:08.135675 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:18:08.141696 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:18:08.145650 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 12:18:08.148616 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 12:18:08.155096 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 12:18:08.158314 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 12:18:08.161651 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:18:08.168573 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 12:18:08.171858 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5854 12:18:08.175343 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5855 12:18:08.181604 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 12:18:08.181984 Total UI for P1: 0, mck2ui 16
5857 12:18:08.188168 best dqsien dly found for B0: ( 1, 2, 26)
5858 12:18:08.188469 Total UI for P1: 0, mck2ui 16
5859 12:18:08.194952 best dqsien dly found for B1: ( 1, 2, 28)
5860 12:18:08.198135 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5861 12:18:08.201598 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5862 12:18:08.201894
5863 12:18:08.204710 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5864 12:18:08.208190 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5865 12:18:08.211036 [Gating] SW calibration Done
5866 12:18:08.211417 ==
5867 12:18:08.214583 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 12:18:08.218027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 12:18:08.218277 ==
5870 12:18:08.221183 RX Vref Scan: 0
5871 12:18:08.221409
5872 12:18:08.221610 RX Vref 0 -> 0, step: 1
5873 12:18:08.224315
5874 12:18:08.224626 RX Delay -80 -> 252, step: 8
5875 12:18:08.231139 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5876 12:18:08.234425 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5877 12:18:08.237792 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5878 12:18:08.241306 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5879 12:18:08.244202 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5880 12:18:08.247740 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5881 12:18:08.254129 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5882 12:18:08.257346 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5883 12:18:08.260767 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5884 12:18:08.264015 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5885 12:18:08.267374 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5886 12:18:08.274312 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5887 12:18:08.276957 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5888 12:18:08.280824 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5889 12:18:08.284144 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5890 12:18:08.287804 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5891 12:18:08.288047 ==
5892 12:18:08.290603 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 12:18:08.297190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 12:18:08.297389 ==
5895 12:18:08.297560 DQS Delay:
5896 12:18:08.300333 DQS0 = 0, DQS1 = 0
5897 12:18:08.300485 DQM Delay:
5898 12:18:08.300606 DQM0 = 99, DQM1 = 91
5899 12:18:08.303353 DQ Delay:
5900 12:18:08.306640 DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =99
5901 12:18:08.309944 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5902 12:18:08.313330 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5903 12:18:08.316726 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5904 12:18:08.316938
5905 12:18:08.317110
5906 12:18:08.317226 ==
5907 12:18:08.319659 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 12:18:08.323199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 12:18:08.323404 ==
5910 12:18:08.323577
5911 12:18:08.323757
5912 12:18:08.326641 TX Vref Scan disable
5913 12:18:08.330090 == TX Byte 0 ==
5914 12:18:08.333348 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5915 12:18:08.336645 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5916 12:18:08.339896 == TX Byte 1 ==
5917 12:18:08.343301 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5918 12:18:08.346326 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5919 12:18:08.346506 ==
5920 12:18:08.350182 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 12:18:08.353164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 12:18:08.356387 ==
5923 12:18:08.356562
5924 12:18:08.356699
5925 12:18:08.356826 TX Vref Scan disable
5926 12:18:08.359757 == TX Byte 0 ==
5927 12:18:08.362985 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5928 12:18:08.369623 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5929 12:18:08.369798 == TX Byte 1 ==
5930 12:18:08.373637 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5931 12:18:08.380098 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5932 12:18:08.380273
5933 12:18:08.380433 [DATLAT]
5934 12:18:08.380576 Freq=933, CH1 RK1
5935 12:18:08.380714
5936 12:18:08.383017 DATLAT Default: 0xb
5937 12:18:08.386173 0, 0xFFFF, sum = 0
5938 12:18:08.386363 1, 0xFFFF, sum = 0
5939 12:18:08.389487 2, 0xFFFF, sum = 0
5940 12:18:08.389719 3, 0xFFFF, sum = 0
5941 12:18:08.392797 4, 0xFFFF, sum = 0
5942 12:18:08.392973 5, 0xFFFF, sum = 0
5943 12:18:08.396003 6, 0xFFFF, sum = 0
5944 12:18:08.396240 7, 0xFFFF, sum = 0
5945 12:18:08.399247 8, 0xFFFF, sum = 0
5946 12:18:08.399430 9, 0xFFFF, sum = 0
5947 12:18:08.402583 10, 0x0, sum = 1
5948 12:18:08.402760 11, 0x0, sum = 2
5949 12:18:08.406053 12, 0x0, sum = 3
5950 12:18:08.406230 13, 0x0, sum = 4
5951 12:18:08.409064 best_step = 11
5952 12:18:08.409250
5953 12:18:08.409389 ==
5954 12:18:08.412319 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 12:18:08.415662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 12:18:08.415869 ==
5957 12:18:08.416009 RX Vref Scan: 0
5958 12:18:08.418991
5959 12:18:08.419164 RX Vref 0 -> 0, step: 1
5960 12:18:08.419302
5961 12:18:08.422378 RX Delay -61 -> 252, step: 4
5962 12:18:08.429075 iDelay=203, Bit 0, Center 104 (15 ~ 194) 180
5963 12:18:08.432351 iDelay=203, Bit 1, Center 96 (11 ~ 182) 172
5964 12:18:08.435556 iDelay=203, Bit 2, Center 90 (3 ~ 178) 176
5965 12:18:08.439232 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5966 12:18:08.442316 iDelay=203, Bit 4, Center 100 (11 ~ 190) 180
5967 12:18:08.448830 iDelay=203, Bit 5, Center 110 (23 ~ 198) 176
5968 12:18:08.452031 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5969 12:18:08.455466 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5970 12:18:08.459096 iDelay=203, Bit 8, Center 84 (-5 ~ 174) 180
5971 12:18:08.461927 iDelay=203, Bit 9, Center 84 (-5 ~ 174) 180
5972 12:18:08.465580 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5973 12:18:08.472118 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5974 12:18:08.475586 iDelay=203, Bit 12, Center 102 (11 ~ 194) 184
5975 12:18:08.478788 iDelay=203, Bit 13, Center 102 (11 ~ 194) 184
5976 12:18:08.481924 iDelay=203, Bit 14, Center 102 (11 ~ 194) 184
5977 12:18:08.488881 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5978 12:18:08.489281 ==
5979 12:18:08.491861 Dram Type= 6, Freq= 0, CH_1, rank 1
5980 12:18:08.495521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5981 12:18:08.496046 ==
5982 12:18:08.496442 DQS Delay:
5983 12:18:08.498689 DQS0 = 0, DQS1 = 0
5984 12:18:08.499121 DQM Delay:
5985 12:18:08.501802 DQM0 = 101, DQM1 = 94
5986 12:18:08.502304 DQ Delay:
5987 12:18:08.505553 DQ0 =104, DQ1 =96, DQ2 =90, DQ3 =98
5988 12:18:08.508608 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =96
5989 12:18:08.511654 DQ8 =84, DQ9 =84, DQ10 =92, DQ11 =84
5990 12:18:08.515015 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
5991 12:18:08.515400
5992 12:18:08.515704
5993 12:18:08.524595 [DQSOSCAuto] RK1, (LSB)MR18= 0x600, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
5994 12:18:08.524985 CH1 RK1: MR19=505, MR18=600
5995 12:18:08.531319 CH1_RK1: MR19=0x505, MR18=0x600, DQSOSC=420, MR23=63, INC=61, DEC=40
5996 12:18:08.534650 [RxdqsGatingPostProcess] freq 933
5997 12:18:08.541455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5998 12:18:08.544495 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 12:18:08.547802 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 12:18:08.551020 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 12:18:08.554507 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 12:18:08.557577 best DQS0 dly(2T, 0.5T) = (0, 10)
6003 12:18:08.561143 best DQS1 dly(2T, 0.5T) = (0, 10)
6004 12:18:08.564468 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6005 12:18:08.567639 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6006 12:18:08.567958 Pre-setting of DQS Precalculation
6007 12:18:08.574161 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6008 12:18:08.580603 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6009 12:18:08.587590 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6010 12:18:08.587842
6011 12:18:08.588082
6012 12:18:08.590621 [Calibration Summary] 1866 Mbps
6013 12:18:08.594044 CH 0, Rank 0
6014 12:18:08.594259 SW Impedance : PASS
6015 12:18:08.597263 DUTY Scan : NO K
6016 12:18:08.600607 ZQ Calibration : PASS
6017 12:18:08.600832 Jitter Meter : NO K
6018 12:18:08.603526 CBT Training : PASS
6019 12:18:08.607154 Write leveling : PASS
6020 12:18:08.607369 RX DQS gating : PASS
6021 12:18:08.610564 RX DQ/DQS(RDDQC) : PASS
6022 12:18:08.613775 TX DQ/DQS : PASS
6023 12:18:08.613990 RX DATLAT : PASS
6024 12:18:08.617299 RX DQ/DQS(Engine): PASS
6025 12:18:08.617513 TX OE : NO K
6026 12:18:08.620805 All Pass.
6027 12:18:08.621018
6028 12:18:08.621188 CH 0, Rank 1
6029 12:18:08.623755 SW Impedance : PASS
6030 12:18:08.623971 DUTY Scan : NO K
6031 12:18:08.626804 ZQ Calibration : PASS
6032 12:18:08.630852 Jitter Meter : NO K
6033 12:18:08.631070 CBT Training : PASS
6034 12:18:08.633448 Write leveling : PASS
6035 12:18:08.637297 RX DQS gating : PASS
6036 12:18:08.637509 RX DQ/DQS(RDDQC) : PASS
6037 12:18:08.640344 TX DQ/DQS : PASS
6038 12:18:08.643438 RX DATLAT : PASS
6039 12:18:08.643719 RX DQ/DQS(Engine): PASS
6040 12:18:08.646932 TX OE : NO K
6041 12:18:08.647148 All Pass.
6042 12:18:08.647317
6043 12:18:08.650078 CH 1, Rank 0
6044 12:18:08.650291 SW Impedance : PASS
6045 12:18:08.653259 DUTY Scan : NO K
6046 12:18:08.656784 ZQ Calibration : PASS
6047 12:18:08.656999 Jitter Meter : NO K
6048 12:18:08.659798 CBT Training : PASS
6049 12:18:08.663058 Write leveling : PASS
6050 12:18:08.663329 RX DQS gating : PASS
6051 12:18:08.666532 RX DQ/DQS(RDDQC) : PASS
6052 12:18:08.669666 TX DQ/DQS : PASS
6053 12:18:08.669964 RX DATLAT : PASS
6054 12:18:08.673071 RX DQ/DQS(Engine): PASS
6055 12:18:08.676448 TX OE : NO K
6056 12:18:08.676667 All Pass.
6057 12:18:08.676854
6058 12:18:08.677059 CH 1, Rank 1
6059 12:18:08.679959 SW Impedance : PASS
6060 12:18:08.682844 DUTY Scan : NO K
6061 12:18:08.683110 ZQ Calibration : PASS
6062 12:18:08.686134 Jitter Meter : NO K
6063 12:18:08.689753 CBT Training : PASS
6064 12:18:08.690009 Write leveling : PASS
6065 12:18:08.692742 RX DQS gating : PASS
6066 12:18:08.693037 RX DQ/DQS(RDDQC) : PASS
6067 12:18:08.696117 TX DQ/DQS : PASS
6068 12:18:08.699787 RX DATLAT : PASS
6069 12:18:08.700004 RX DQ/DQS(Engine): PASS
6070 12:18:08.702706 TX OE : NO K
6071 12:18:08.702923 All Pass.
6072 12:18:08.703097
6073 12:18:08.706243 DramC Write-DBI off
6074 12:18:08.709206 PER_BANK_REFRESH: Hybrid Mode
6075 12:18:08.709519 TX_TRACKING: ON
6076 12:18:08.719136 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6077 12:18:08.722580 [FAST_K] Save calibration result to emmc
6078 12:18:08.725813 dramc_set_vcore_voltage set vcore to 650000
6079 12:18:08.728929 Read voltage for 400, 6
6080 12:18:08.729151 Vio18 = 0
6081 12:18:08.732167 Vcore = 650000
6082 12:18:08.732407 Vdram = 0
6083 12:18:08.732581 Vddq = 0
6084 12:18:08.732736 Vmddr = 0
6085 12:18:08.738988 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6086 12:18:08.745799 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6087 12:18:08.746034 MEM_TYPE=3, freq_sel=20
6088 12:18:08.749271 sv_algorithm_assistance_LP4_800
6089 12:18:08.752635 ============ PULL DRAM RESETB DOWN ============
6090 12:18:08.758840 ========== PULL DRAM RESETB DOWN end =========
6091 12:18:08.762071 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6092 12:18:08.765515 ===================================
6093 12:18:08.768871 LPDDR4 DRAM CONFIGURATION
6094 12:18:08.771739 ===================================
6095 12:18:08.772000 EX_ROW_EN[0] = 0x0
6096 12:18:08.775516 EX_ROW_EN[1] = 0x0
6097 12:18:08.778491 LP4Y_EN = 0x0
6098 12:18:08.778775 WORK_FSP = 0x0
6099 12:18:08.781763 WL = 0x2
6100 12:18:08.782037 RL = 0x2
6101 12:18:08.785055 BL = 0x2
6102 12:18:08.785357 RPST = 0x0
6103 12:18:08.788322 RD_PRE = 0x0
6104 12:18:08.788639 WR_PRE = 0x1
6105 12:18:08.792093 WR_PST = 0x0
6106 12:18:08.792371 DBI_WR = 0x0
6107 12:18:08.795042 DBI_RD = 0x0
6108 12:18:08.795253 OTF = 0x1
6109 12:18:08.798108 ===================================
6110 12:18:08.801665 ===================================
6111 12:18:08.805268 ANA top config
6112 12:18:08.808182 ===================================
6113 12:18:08.808512 DLL_ASYNC_EN = 0
6114 12:18:08.811285 ALL_SLAVE_EN = 1
6115 12:18:08.814488 NEW_RANK_MODE = 1
6116 12:18:08.817849 DLL_IDLE_MODE = 1
6117 12:18:08.821508 LP45_APHY_COMB_EN = 1
6118 12:18:08.821777 TX_ODT_DIS = 1
6119 12:18:08.824694 NEW_8X_MODE = 1
6120 12:18:08.827815 ===================================
6121 12:18:08.830878 ===================================
6122 12:18:08.834259 data_rate = 800
6123 12:18:08.837573 CKR = 1
6124 12:18:08.841075 DQ_P2S_RATIO = 4
6125 12:18:08.844542 ===================================
6126 12:18:08.847731 CA_P2S_RATIO = 4
6127 12:18:08.847835 DQ_CA_OPEN = 0
6128 12:18:08.851267 DQ_SEMI_OPEN = 1
6129 12:18:08.854588 CA_SEMI_OPEN = 1
6130 12:18:08.857859 CA_FULL_RATE = 0
6131 12:18:08.860826 DQ_CKDIV4_EN = 0
6132 12:18:08.864129 CA_CKDIV4_EN = 1
6133 12:18:08.864280 CA_PREDIV_EN = 0
6134 12:18:08.867567 PH8_DLY = 0
6135 12:18:08.870711 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6136 12:18:08.874357 DQ_AAMCK_DIV = 0
6137 12:18:08.877459 CA_AAMCK_DIV = 0
6138 12:18:08.881420 CA_ADMCK_DIV = 4
6139 12:18:08.881567 DQ_TRACK_CA_EN = 0
6140 12:18:08.884415 CA_PICK = 800
6141 12:18:08.887313 CA_MCKIO = 400
6142 12:18:08.890891 MCKIO_SEMI = 400
6143 12:18:08.894258 PLL_FREQ = 3016
6144 12:18:08.897236 DQ_UI_PI_RATIO = 32
6145 12:18:08.900616 CA_UI_PI_RATIO = 32
6146 12:18:08.904088 ===================================
6147 12:18:08.907268 ===================================
6148 12:18:08.907419 memory_type:LPDDR4
6149 12:18:08.910683 GP_NUM : 10
6150 12:18:08.913586 SRAM_EN : 1
6151 12:18:08.913734 MD32_EN : 0
6152 12:18:08.917112 ===================================
6153 12:18:08.920589 [ANA_INIT] >>>>>>>>>>>>>>
6154 12:18:08.923483 <<<<<< [CONFIGURE PHASE]: ANA_TX
6155 12:18:08.926789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6156 12:18:08.930266 ===================================
6157 12:18:08.933554 data_rate = 800,PCW = 0X7400
6158 12:18:08.937022 ===================================
6159 12:18:08.940422 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6160 12:18:08.943767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 12:18:08.956804 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6162 12:18:08.960689 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6163 12:18:08.963518 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6164 12:18:08.966802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6165 12:18:08.970166 [ANA_INIT] flow start
6166 12:18:08.973381 [ANA_INIT] PLL >>>>>>>>
6167 12:18:08.974046 [ANA_INIT] PLL <<<<<<<<
6168 12:18:08.976818 [ANA_INIT] MIDPI >>>>>>>>
6169 12:18:08.980080 [ANA_INIT] MIDPI <<<<<<<<
6170 12:18:08.980497 [ANA_INIT] DLL >>>>>>>>
6171 12:18:08.983263 [ANA_INIT] flow end
6172 12:18:08.986670 ============ LP4 DIFF to SE enter ============
6173 12:18:08.993317 ============ LP4 DIFF to SE exit ============
6174 12:18:08.993745 [ANA_INIT] <<<<<<<<<<<<<
6175 12:18:08.996867 [Flow] Enable top DCM control >>>>>
6176 12:18:08.999705 [Flow] Enable top DCM control <<<<<
6177 12:18:09.003416 Enable DLL master slave shuffle
6178 12:18:09.009536 ==============================================================
6179 12:18:09.009958 Gating Mode config
6180 12:18:09.016545 ==============================================================
6181 12:18:09.019571 Config description:
6182 12:18:09.026425 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6183 12:18:09.033039 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6184 12:18:09.039849 SELPH_MODE 0: By rank 1: By Phase
6185 12:18:09.046165 ==============================================================
6186 12:18:09.046705 GAT_TRACK_EN = 0
6187 12:18:09.049942 RX_GATING_MODE = 2
6188 12:18:09.053094 RX_GATING_TRACK_MODE = 2
6189 12:18:09.056683 SELPH_MODE = 1
6190 12:18:09.059524 PICG_EARLY_EN = 1
6191 12:18:09.062880 VALID_LAT_VALUE = 1
6192 12:18:09.069278 ==============================================================
6193 12:18:09.072122 Enter into Gating configuration >>>>
6194 12:18:09.076071 Exit from Gating configuration <<<<
6195 12:18:09.079375 Enter into DVFS_PRE_config >>>>>
6196 12:18:09.088829 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6197 12:18:09.092116 Exit from DVFS_PRE_config <<<<<
6198 12:18:09.095686 Enter into PICG configuration >>>>
6199 12:18:09.098517 Exit from PICG configuration <<<<
6200 12:18:09.101966 [RX_INPUT] configuration >>>>>
6201 12:18:09.105341 [RX_INPUT] configuration <<<<<
6202 12:18:09.108540 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6203 12:18:09.114899 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6204 12:18:09.121738 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 12:18:09.128506 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 12:18:09.131601 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 12:18:09.138095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 12:18:09.145072 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6209 12:18:09.148331 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6210 12:18:09.151815 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6211 12:18:09.155125 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6212 12:18:09.158053 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6213 12:18:09.164951 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6214 12:18:09.168039 ===================================
6215 12:18:09.171687 LPDDR4 DRAM CONFIGURATION
6216 12:18:09.175066 ===================================
6217 12:18:09.175490 EX_ROW_EN[0] = 0x0
6218 12:18:09.178153 EX_ROW_EN[1] = 0x0
6219 12:18:09.178576 LP4Y_EN = 0x0
6220 12:18:09.181187 WORK_FSP = 0x0
6221 12:18:09.181608 WL = 0x2
6222 12:18:09.184556 RL = 0x2
6223 12:18:09.185098 BL = 0x2
6224 12:18:09.187858 RPST = 0x0
6225 12:18:09.188503 RD_PRE = 0x0
6226 12:18:09.191201 WR_PRE = 0x1
6227 12:18:09.194740 WR_PST = 0x0
6228 12:18:09.195161 DBI_WR = 0x0
6229 12:18:09.198030 DBI_RD = 0x0
6230 12:18:09.198448 OTF = 0x1
6231 12:18:09.201275 ===================================
6232 12:18:09.204489 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6233 12:18:09.207661 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6234 12:18:09.214533 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6235 12:18:09.217859 ===================================
6236 12:18:09.221529 LPDDR4 DRAM CONFIGURATION
6237 12:18:09.224096 ===================================
6238 12:18:09.224364 EX_ROW_EN[0] = 0x10
6239 12:18:09.227196 EX_ROW_EN[1] = 0x0
6240 12:18:09.227422 LP4Y_EN = 0x0
6241 12:18:09.230545 WORK_FSP = 0x0
6242 12:18:09.230772 WL = 0x2
6243 12:18:09.233817 RL = 0x2
6244 12:18:09.234000 BL = 0x2
6245 12:18:09.237229 RPST = 0x0
6246 12:18:09.237462 RD_PRE = 0x0
6247 12:18:09.240514 WR_PRE = 0x1
6248 12:18:09.244229 WR_PST = 0x0
6249 12:18:09.244464 DBI_WR = 0x0
6250 12:18:09.247101 DBI_RD = 0x0
6251 12:18:09.247336 OTF = 0x1
6252 12:18:09.250312 ===================================
6253 12:18:09.257070 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6254 12:18:09.260852 nWR fixed to 30
6255 12:18:09.264120 [ModeRegInit_LP4] CH0 RK0
6256 12:18:09.264354 [ModeRegInit_LP4] CH0 RK1
6257 12:18:09.267775 [ModeRegInit_LP4] CH1 RK0
6258 12:18:09.270893 [ModeRegInit_LP4] CH1 RK1
6259 12:18:09.271146 match AC timing 19
6260 12:18:09.277603 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6261 12:18:09.280699 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6262 12:18:09.283862 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6263 12:18:09.290466 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6264 12:18:09.293828 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6265 12:18:09.294345 ==
6266 12:18:09.296989 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 12:18:09.300182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 12:18:09.303521 ==
6269 12:18:09.307118 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6270 12:18:09.313518 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6271 12:18:09.316826 [CA 0] Center 36 (8~64) winsize 57
6272 12:18:09.319789 [CA 1] Center 36 (8~64) winsize 57
6273 12:18:09.323236 [CA 2] Center 36 (8~64) winsize 57
6274 12:18:09.326498 [CA 3] Center 36 (8~64) winsize 57
6275 12:18:09.330072 [CA 4] Center 36 (8~64) winsize 57
6276 12:18:09.333031 [CA 5] Center 36 (8~64) winsize 57
6277 12:18:09.333516
6278 12:18:09.336328 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6279 12:18:09.336758
6280 12:18:09.339402 [CATrainingPosCal] consider 1 rank data
6281 12:18:09.343266 u2DelayCellTimex100 = 270/100 ps
6282 12:18:09.346197 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 12:18:09.349332 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 12:18:09.352954 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 12:18:09.356252 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 12:18:09.359161 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 12:18:09.362795 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 12:18:09.363328
6289 12:18:09.369472 CA PerBit enable=1, Macro0, CA PI delay=36
6290 12:18:09.370365
6291 12:18:09.372728 [CBTSetCACLKResult] CA Dly = 36
6292 12:18:09.373474 CS Dly: 1 (0~32)
6293 12:18:09.374133 ==
6294 12:18:09.375696 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 12:18:09.379240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 12:18:09.379681 ==
6297 12:18:09.385713 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6298 12:18:09.392292 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6299 12:18:09.395432 [CA 0] Center 36 (8~64) winsize 57
6300 12:18:09.398893 [CA 1] Center 36 (8~64) winsize 57
6301 12:18:09.402285 [CA 2] Center 36 (8~64) winsize 57
6302 12:18:09.405652 [CA 3] Center 36 (8~64) winsize 57
6303 12:18:09.408947 [CA 4] Center 36 (8~64) winsize 57
6304 12:18:09.411602 [CA 5] Center 36 (8~64) winsize 57
6305 12:18:09.411808
6306 12:18:09.415352 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6307 12:18:09.415580
6308 12:18:09.418599 [CATrainingPosCal] consider 2 rank data
6309 12:18:09.421740 u2DelayCellTimex100 = 270/100 ps
6310 12:18:09.424908 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 12:18:09.428063 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 12:18:09.431479 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 12:18:09.435169 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 12:18:09.437784 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 12:18:09.441082 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 12:18:09.441184
6317 12:18:09.447888 CA PerBit enable=1, Macro0, CA PI delay=36
6318 12:18:09.447970
6319 12:18:09.448035 [CBTSetCACLKResult] CA Dly = 36
6320 12:18:09.451384 CS Dly: 1 (0~32)
6321 12:18:09.451491
6322 12:18:09.454394 ----->DramcWriteLeveling(PI) begin...
6323 12:18:09.454504 ==
6324 12:18:09.458009 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 12:18:09.460934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 12:18:09.461016 ==
6327 12:18:09.464131 Write leveling (Byte 0): 40 => 8
6328 12:18:09.467538 Write leveling (Byte 1): 32 => 0
6329 12:18:09.470992 DramcWriteLeveling(PI) end<-----
6330 12:18:09.471073
6331 12:18:09.471138 ==
6332 12:18:09.474008 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 12:18:09.480445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 12:18:09.480534 ==
6335 12:18:09.480602 [Gating] SW mode calibration
6336 12:18:09.490349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6337 12:18:09.494313 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6338 12:18:09.497221 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 12:18:09.503422 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6340 12:18:09.507088 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 12:18:09.513474 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 12:18:09.516986 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 12:18:09.520401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 12:18:09.523571 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 12:18:09.530211 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 12:18:09.533653 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 12:18:09.536496 Total UI for P1: 0, mck2ui 16
6348 12:18:09.540287 best dqsien dly found for B0: ( 0, 14, 24)
6349 12:18:09.543483 Total UI for P1: 0, mck2ui 16
6350 12:18:09.546691 best dqsien dly found for B1: ( 0, 14, 24)
6351 12:18:09.549900 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6352 12:18:09.553686 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6353 12:18:09.553770
6354 12:18:09.556735 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 12:18:09.562918 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6356 12:18:09.563002 [Gating] SW calibration Done
6357 12:18:09.566249 ==
6358 12:18:09.566332 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 12:18:09.573162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 12:18:09.573246 ==
6361 12:18:09.573312 RX Vref Scan: 0
6362 12:18:09.573374
6363 12:18:09.576461 RX Vref 0 -> 0, step: 1
6364 12:18:09.576543
6365 12:18:09.579306 RX Delay -410 -> 252, step: 16
6366 12:18:09.582623 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6367 12:18:09.585844 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6368 12:18:09.592447 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6369 12:18:09.596267 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6370 12:18:09.599306 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6371 12:18:09.606324 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6372 12:18:09.609169 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6373 12:18:09.612367 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6374 12:18:09.615462 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6375 12:18:09.622164 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6376 12:18:09.625736 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6377 12:18:09.629231 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6378 12:18:09.632226 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6379 12:18:09.638606 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6380 12:18:09.642317 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6381 12:18:09.645409 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6382 12:18:09.645485 ==
6383 12:18:09.648676 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 12:18:09.652143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 12:18:09.655762 ==
6386 12:18:09.655857 DQS Delay:
6387 12:18:09.655922 DQS0 = 43, DQS1 = 59
6388 12:18:09.659163 DQM Delay:
6389 12:18:09.659253 DQM0 = 11, DQM1 = 12
6390 12:18:09.662405 DQ Delay:
6391 12:18:09.662513 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6392 12:18:09.665760 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6393 12:18:09.668790 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6394 12:18:09.672292 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6395 12:18:09.672388
6396 12:18:09.672481
6397 12:18:09.675434 ==
6398 12:18:09.675516 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 12:18:09.682226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 12:18:09.682335 ==
6401 12:18:09.682429
6402 12:18:09.682524
6403 12:18:09.685424 TX Vref Scan disable
6404 12:18:09.685506 == TX Byte 0 ==
6405 12:18:09.688806 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 12:18:09.695601 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 12:18:09.695712 == TX Byte 1 ==
6408 12:18:09.698501 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6409 12:18:09.704965 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6410 12:18:09.705059 ==
6411 12:18:09.708668 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 12:18:09.712101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 12:18:09.712178 ==
6414 12:18:09.712241
6415 12:18:09.712313
6416 12:18:09.714843 TX Vref Scan disable
6417 12:18:09.714941 == TX Byte 0 ==
6418 12:18:09.718423 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 12:18:09.725185 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 12:18:09.725267 == TX Byte 1 ==
6421 12:18:09.728428 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6422 12:18:09.734666 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6423 12:18:09.734772
6424 12:18:09.734862 [DATLAT]
6425 12:18:09.738150 Freq=400, CH0 RK0
6426 12:18:09.738257
6427 12:18:09.738349 DATLAT Default: 0xf
6428 12:18:09.741189 0, 0xFFFF, sum = 0
6429 12:18:09.741290 1, 0xFFFF, sum = 0
6430 12:18:09.744860 2, 0xFFFF, sum = 0
6431 12:18:09.744934 3, 0xFFFF, sum = 0
6432 12:18:09.748544 4, 0xFFFF, sum = 0
6433 12:18:09.748624 5, 0xFFFF, sum = 0
6434 12:18:09.751403 6, 0xFFFF, sum = 0
6435 12:18:09.751476 7, 0xFFFF, sum = 0
6436 12:18:09.754791 8, 0xFFFF, sum = 0
6437 12:18:09.754898 9, 0xFFFF, sum = 0
6438 12:18:09.757835 10, 0xFFFF, sum = 0
6439 12:18:09.757941 11, 0xFFFF, sum = 0
6440 12:18:09.761354 12, 0xFFFF, sum = 0
6441 12:18:09.761460 13, 0x0, sum = 1
6442 12:18:09.764397 14, 0x0, sum = 2
6443 12:18:09.764508 15, 0x0, sum = 3
6444 12:18:09.767659 16, 0x0, sum = 4
6445 12:18:09.767800 best_step = 14
6446 12:18:09.767866
6447 12:18:09.767926 ==
6448 12:18:09.771327 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 12:18:09.778361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 12:18:09.778444 ==
6451 12:18:09.778510 RX Vref Scan: 1
6452 12:18:09.778571
6453 12:18:09.781003 RX Vref 0 -> 0, step: 1
6454 12:18:09.781086
6455 12:18:09.784209 RX Delay -359 -> 252, step: 8
6456 12:18:09.784318
6457 12:18:09.787476 Set Vref, RX VrefLevel [Byte0]: 60
6458 12:18:09.790919 [Byte1]: 48
6459 12:18:09.794576
6460 12:18:09.794666 Final RX Vref Byte 0 = 60 to rank0
6461 12:18:09.797739 Final RX Vref Byte 1 = 48 to rank0
6462 12:18:09.801142 Final RX Vref Byte 0 = 60 to rank1
6463 12:18:09.804343 Final RX Vref Byte 1 = 48 to rank1==
6464 12:18:09.807680 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 12:18:09.814363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 12:18:09.814449 ==
6467 12:18:09.814516 DQS Delay:
6468 12:18:09.817330 DQS0 = 48, DQS1 = 60
6469 12:18:09.817413 DQM Delay:
6470 12:18:09.821114 DQM0 = 11, DQM1 = 13
6471 12:18:09.821197 DQ Delay:
6472 12:18:09.823836 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6473 12:18:09.827006 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6474 12:18:09.830924 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6475 12:18:09.833844 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6476 12:18:09.833928
6477 12:18:09.833994
6478 12:18:09.840753 [DQSOSCAuto] RK0, (LSB)MR18= 0xc588, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 385 ps
6479 12:18:09.843692 CH0 RK0: MR19=C0C, MR18=C588
6480 12:18:09.850251 CH0_RK0: MR19=0xC0C, MR18=0xC588, DQSOSC=385, MR23=63, INC=398, DEC=265
6481 12:18:09.850336 ==
6482 12:18:09.853465 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 12:18:09.856854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 12:18:09.856937 ==
6485 12:18:09.860071 [Gating] SW mode calibration
6486 12:18:09.866737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6487 12:18:09.873800 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6488 12:18:09.876730 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 12:18:09.879974 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 12:18:09.886726 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 12:18:09.890120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 12:18:09.893192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 12:18:09.900062 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 12:18:09.902792 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 12:18:09.906709 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 12:18:09.913267 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 12:18:09.916160 Total UI for P1: 0, mck2ui 16
6498 12:18:09.919417 best dqsien dly found for B0: ( 0, 14, 24)
6499 12:18:09.922832 Total UI for P1: 0, mck2ui 16
6500 12:18:09.926070 best dqsien dly found for B1: ( 0, 14, 24)
6501 12:18:09.929403 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6502 12:18:09.932917 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6503 12:18:09.933002
6504 12:18:09.936226 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 12:18:09.939495 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6506 12:18:09.942833 [Gating] SW calibration Done
6507 12:18:09.942918 ==
6508 12:18:09.945855 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 12:18:09.949006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 12:18:09.949116 ==
6511 12:18:09.952705 RX Vref Scan: 0
6512 12:18:09.952789
6513 12:18:09.956044 RX Vref 0 -> 0, step: 1
6514 12:18:09.956145
6515 12:18:09.959941 RX Delay -410 -> 252, step: 16
6516 12:18:09.962531 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6517 12:18:09.965552 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6518 12:18:09.968945 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6519 12:18:09.975489 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6520 12:18:09.978759 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6521 12:18:09.982213 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6522 12:18:09.985155 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6523 12:18:09.992205 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6524 12:18:09.995168 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6525 12:18:09.998820 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6526 12:18:10.002493 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6527 12:18:10.008380 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6528 12:18:10.011902 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6529 12:18:10.015547 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6530 12:18:10.021651 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6531 12:18:10.025107 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6532 12:18:10.025215 ==
6533 12:18:10.028391 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 12:18:10.031668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 12:18:10.031775 ==
6536 12:18:10.035203 DQS Delay:
6537 12:18:10.035285 DQS0 = 43, DQS1 = 59
6538 12:18:10.035350 DQM Delay:
6539 12:18:10.038005 DQM0 = 11, DQM1 = 16
6540 12:18:10.038087 DQ Delay:
6541 12:18:10.041896 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6542 12:18:10.045129 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6543 12:18:10.048573 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6544 12:18:10.051542 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6545 12:18:10.051652
6546 12:18:10.051790
6547 12:18:10.051874 ==
6548 12:18:10.055068 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 12:18:10.058038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 12:18:10.061164 ==
6551 12:18:10.061249
6552 12:18:10.061334
6553 12:18:10.061415 TX Vref Scan disable
6554 12:18:10.064905 == TX Byte 0 ==
6555 12:18:10.068282 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6556 12:18:10.071281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6557 12:18:10.074716 == TX Byte 1 ==
6558 12:18:10.078055 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6559 12:18:10.081170 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6560 12:18:10.081252 ==
6561 12:18:10.084858 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 12:18:10.088268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 12:18:10.091479 ==
6564 12:18:10.091561
6565 12:18:10.091626
6566 12:18:10.091686 TX Vref Scan disable
6567 12:18:10.094633 == TX Byte 0 ==
6568 12:18:10.097873 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6569 12:18:10.101268 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6570 12:18:10.104832 == TX Byte 1 ==
6571 12:18:10.107699 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6572 12:18:10.111159 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6573 12:18:10.111240
6574 12:18:10.114225 [DATLAT]
6575 12:18:10.114306 Freq=400, CH0 RK1
6576 12:18:10.114371
6577 12:18:10.117797 DATLAT Default: 0xe
6578 12:18:10.117877 0, 0xFFFF, sum = 0
6579 12:18:10.121156 1, 0xFFFF, sum = 0
6580 12:18:10.121238 2, 0xFFFF, sum = 0
6581 12:18:10.124660 3, 0xFFFF, sum = 0
6582 12:18:10.124742 4, 0xFFFF, sum = 0
6583 12:18:10.127669 5, 0xFFFF, sum = 0
6584 12:18:10.127796 6, 0xFFFF, sum = 0
6585 12:18:10.130791 7, 0xFFFF, sum = 0
6586 12:18:10.130885 8, 0xFFFF, sum = 0
6587 12:18:10.134202 9, 0xFFFF, sum = 0
6588 12:18:10.134312 10, 0xFFFF, sum = 0
6589 12:18:10.137524 11, 0xFFFF, sum = 0
6590 12:18:10.137623 12, 0xFFFF, sum = 0
6591 12:18:10.140778 13, 0x0, sum = 1
6592 12:18:10.140864 14, 0x0, sum = 2
6593 12:18:10.144011 15, 0x0, sum = 3
6594 12:18:10.144097 16, 0x0, sum = 4
6595 12:18:10.147484 best_step = 14
6596 12:18:10.147631
6597 12:18:10.147745 ==
6598 12:18:10.151113 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 12:18:10.154322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 12:18:10.154408 ==
6601 12:18:10.157325 RX Vref Scan: 0
6602 12:18:10.157409
6603 12:18:10.157495 RX Vref 0 -> 0, step: 1
6604 12:18:10.157576
6605 12:18:10.160724 RX Delay -359 -> 252, step: 8
6606 12:18:10.169107 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6607 12:18:10.172395 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6608 12:18:10.175492 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6609 12:18:10.182256 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6610 12:18:10.184938 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6611 12:18:10.188718 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6612 12:18:10.191886 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6613 12:18:10.198278 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6614 12:18:10.201725 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6615 12:18:10.205056 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6616 12:18:10.208387 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6617 12:18:10.215204 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6618 12:18:10.218373 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6619 12:18:10.221844 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6620 12:18:10.228623 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6621 12:18:10.231409 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6622 12:18:10.231613 ==
6623 12:18:10.234683 Dram Type= 6, Freq= 0, CH_0, rank 1
6624 12:18:10.238252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 12:18:10.238479 ==
6626 12:18:10.241599 DQS Delay:
6627 12:18:10.241836 DQS0 = 44, DQS1 = 60
6628 12:18:10.242013 DQM Delay:
6629 12:18:10.244864 DQM0 = 7, DQM1 = 15
6630 12:18:10.245101 DQ Delay:
6631 12:18:10.247765 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6632 12:18:10.250715 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6633 12:18:10.254278 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6634 12:18:10.257562 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6635 12:18:10.257816
6636 12:18:10.258008
6637 12:18:10.267655 [DQSOSCAuto] RK1, (LSB)MR18= 0xb440, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 387 ps
6638 12:18:10.268091 CH0 RK1: MR19=C0C, MR18=B440
6639 12:18:10.274344 CH0_RK1: MR19=0xC0C, MR18=0xB440, DQSOSC=387, MR23=63, INC=394, DEC=262
6640 12:18:10.277942 [RxdqsGatingPostProcess] freq 400
6641 12:18:10.284134 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6642 12:18:10.288013 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 12:18:10.291172 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 12:18:10.294239 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 12:18:10.298030 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 12:18:10.300357 best DQS0 dly(2T, 0.5T) = (0, 10)
6647 12:18:10.304175 best DQS1 dly(2T, 0.5T) = (0, 10)
6648 12:18:10.307534 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6649 12:18:10.310669 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6650 12:18:10.311250 Pre-setting of DQS Precalculation
6651 12:18:10.317126 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6652 12:18:10.317680 ==
6653 12:18:10.320392 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 12:18:10.324045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 12:18:10.324509 ==
6656 12:18:10.330424 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6657 12:18:10.337230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6658 12:18:10.339932 [CA 0] Center 36 (8~64) winsize 57
6659 12:18:10.343206 [CA 1] Center 36 (8~64) winsize 57
6660 12:18:10.346950 [CA 2] Center 36 (8~64) winsize 57
6661 12:18:10.350405 [CA 3] Center 36 (8~64) winsize 57
6662 12:18:10.353317 [CA 4] Center 36 (8~64) winsize 57
6663 12:18:10.353873 [CA 5] Center 36 (8~64) winsize 57
6664 12:18:10.354422
6665 12:18:10.359864 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6666 12:18:10.360289
6667 12:18:10.363178 [CATrainingPosCal] consider 1 rank data
6668 12:18:10.366622 u2DelayCellTimex100 = 270/100 ps
6669 12:18:10.369686 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 12:18:10.372920 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 12:18:10.376148 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 12:18:10.379229 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 12:18:10.382578 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 12:18:10.386370 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 12:18:10.386558
6676 12:18:10.389369 CA PerBit enable=1, Macro0, CA PI delay=36
6677 12:18:10.392311
6678 12:18:10.392492 [CBTSetCACLKResult] CA Dly = 36
6679 12:18:10.395632 CS Dly: 1 (0~32)
6680 12:18:10.395856 ==
6681 12:18:10.399460 Dram Type= 6, Freq= 0, CH_1, rank 1
6682 12:18:10.402855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 12:18:10.403037 ==
6684 12:18:10.409172 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6685 12:18:10.415411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6686 12:18:10.418763 [CA 0] Center 36 (8~64) winsize 57
6687 12:18:10.422195 [CA 1] Center 36 (8~64) winsize 57
6688 12:18:10.425199 [CA 2] Center 36 (8~64) winsize 57
6689 12:18:10.428873 [CA 3] Center 36 (8~64) winsize 57
6690 12:18:10.429055 [CA 4] Center 36 (8~64) winsize 57
6691 12:18:10.432042 [CA 5] Center 36 (8~64) winsize 57
6692 12:18:10.432253
6693 12:18:10.438372 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6694 12:18:10.438586
6695 12:18:10.441554 [CATrainingPosCal] consider 2 rank data
6696 12:18:10.445692 u2DelayCellTimex100 = 270/100 ps
6697 12:18:10.448580 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 12:18:10.451938 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 12:18:10.454907 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 12:18:10.458262 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 12:18:10.461425 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 12:18:10.465116 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 12:18:10.465327
6704 12:18:10.468649 CA PerBit enable=1, Macro0, CA PI delay=36
6705 12:18:10.468874
6706 12:18:10.471300 [CBTSetCACLKResult] CA Dly = 36
6707 12:18:10.475243 CS Dly: 1 (0~32)
6708 12:18:10.475462
6709 12:18:10.478084 ----->DramcWriteLeveling(PI) begin...
6710 12:18:10.478380 ==
6711 12:18:10.481165 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 12:18:10.484787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 12:18:10.485016 ==
6714 12:18:10.488012 Write leveling (Byte 0): 40 => 8
6715 12:18:10.491213 Write leveling (Byte 1): 40 => 8
6716 12:18:10.494243 DramcWriteLeveling(PI) end<-----
6717 12:18:10.494388
6718 12:18:10.494543 ==
6719 12:18:10.497630 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 12:18:10.500928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 12:18:10.501080 ==
6722 12:18:10.504291 [Gating] SW mode calibration
6723 12:18:10.511384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6724 12:18:10.518091 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6725 12:18:10.520675 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 12:18:10.527375 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6727 12:18:10.530750 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 12:18:10.533992 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 12:18:10.540692 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 12:18:10.544182 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 12:18:10.547040 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 12:18:10.553509 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 12:18:10.557140 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 12:18:10.560343 Total UI for P1: 0, mck2ui 16
6735 12:18:10.563665 best dqsien dly found for B0: ( 0, 14, 24)
6736 12:18:10.566750 Total UI for P1: 0, mck2ui 16
6737 12:18:10.570082 best dqsien dly found for B1: ( 0, 14, 24)
6738 12:18:10.573551 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6739 12:18:10.577134 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6740 12:18:10.577216
6741 12:18:10.580378 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 12:18:10.583573 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6743 12:18:10.586593 [Gating] SW calibration Done
6744 12:18:10.586690 ==
6745 12:18:10.590159 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 12:18:10.593709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 12:18:10.596904 ==
6748 12:18:10.597005 RX Vref Scan: 0
6749 12:18:10.597095
6750 12:18:10.600298 RX Vref 0 -> 0, step: 1
6751 12:18:10.600366
6752 12:18:10.603555 RX Delay -410 -> 252, step: 16
6753 12:18:10.606920 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6754 12:18:10.610122 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6755 12:18:10.613391 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6756 12:18:10.619651 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6757 12:18:10.623051 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6758 12:18:10.626371 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6759 12:18:10.629670 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6760 12:18:10.636300 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6761 12:18:10.639555 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6762 12:18:10.643097 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6763 12:18:10.649710 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6764 12:18:10.652622 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6765 12:18:10.656192 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6766 12:18:10.659464 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6767 12:18:10.666217 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6768 12:18:10.669212 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6769 12:18:10.669318 ==
6770 12:18:10.672953 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 12:18:10.676060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 12:18:10.676150 ==
6773 12:18:10.679622 DQS Delay:
6774 12:18:10.679741 DQS0 = 43, DQS1 = 51
6775 12:18:10.682789 DQM Delay:
6776 12:18:10.682900 DQM0 = 12, DQM1 = 14
6777 12:18:10.682995 DQ Delay:
6778 12:18:10.685811 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6779 12:18:10.689358 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6780 12:18:10.692606 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6781 12:18:10.695925 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6782 12:18:10.696033
6783 12:18:10.696127
6784 12:18:10.696216 ==
6785 12:18:10.699429 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 12:18:10.705490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 12:18:10.705601 ==
6788 12:18:10.705695
6789 12:18:10.705789
6790 12:18:10.705881 TX Vref Scan disable
6791 12:18:10.709105 == TX Byte 0 ==
6792 12:18:10.712292 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 12:18:10.715728 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 12:18:10.718709 == TX Byte 1 ==
6795 12:18:10.722449 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 12:18:10.725436 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 12:18:10.725518 ==
6798 12:18:10.728745 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 12:18:10.734974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 12:18:10.735056 ==
6801 12:18:10.735121
6802 12:18:10.735180
6803 12:18:10.735238 TX Vref Scan disable
6804 12:18:10.738725 == TX Byte 0 ==
6805 12:18:10.741983 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 12:18:10.745246 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 12:18:10.748624 == TX Byte 1 ==
6808 12:18:10.751578 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 12:18:10.755178 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 12:18:10.758451
6811 12:18:10.758544 [DATLAT]
6812 12:18:10.758617 Freq=400, CH1 RK0
6813 12:18:10.758686
6814 12:18:10.761885 DATLAT Default: 0xf
6815 12:18:10.761978 0, 0xFFFF, sum = 0
6816 12:18:10.765209 1, 0xFFFF, sum = 0
6817 12:18:10.765304 2, 0xFFFF, sum = 0
6818 12:18:10.769022 3, 0xFFFF, sum = 0
6819 12:18:10.769117 4, 0xFFFF, sum = 0
6820 12:18:10.771824 5, 0xFFFF, sum = 0
6821 12:18:10.774740 6, 0xFFFF, sum = 0
6822 12:18:10.774834 7, 0xFFFF, sum = 0
6823 12:18:10.778037 8, 0xFFFF, sum = 0
6824 12:18:10.778167 9, 0xFFFF, sum = 0
6825 12:18:10.781509 10, 0xFFFF, sum = 0
6826 12:18:10.781633 11, 0xFFFF, sum = 0
6827 12:18:10.784876 12, 0xFFFF, sum = 0
6828 12:18:10.785002 13, 0x0, sum = 1
6829 12:18:10.788133 14, 0x0, sum = 2
6830 12:18:10.788263 15, 0x0, sum = 3
6831 12:18:10.790898 16, 0x0, sum = 4
6832 12:18:10.791021 best_step = 14
6833 12:18:10.791126
6834 12:18:10.791227 ==
6835 12:18:10.794520 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 12:18:10.797662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 12:18:10.801419 ==
6838 12:18:10.801518 RX Vref Scan: 1
6839 12:18:10.801648
6840 12:18:10.804579 RX Vref 0 -> 0, step: 1
6841 12:18:10.804718
6842 12:18:10.807846 RX Delay -343 -> 252, step: 8
6843 12:18:10.807994
6844 12:18:10.810763 Set Vref, RX VrefLevel [Byte0]: 47
6845 12:18:10.813989 [Byte1]: 59
6846 12:18:10.814147
6847 12:18:10.818046 Final RX Vref Byte 0 = 47 to rank0
6848 12:18:10.820864 Final RX Vref Byte 1 = 59 to rank0
6849 12:18:10.824225 Final RX Vref Byte 0 = 47 to rank1
6850 12:18:10.827482 Final RX Vref Byte 1 = 59 to rank1==
6851 12:18:10.831147 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 12:18:10.833863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 12:18:10.837596 ==
6854 12:18:10.837746 DQS Delay:
6855 12:18:10.837870 DQS0 = 44, DQS1 = 56
6856 12:18:10.840994 DQM Delay:
6857 12:18:10.841128 DQM0 = 8, DQM1 = 12
6858 12:18:10.844069 DQ Delay:
6859 12:18:10.844244 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6860 12:18:10.847560 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6861 12:18:10.851113 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6862 12:18:10.854339 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6863 12:18:10.854761
6864 12:18:10.855094
6865 12:18:10.864618 [DQSOSCAuto] RK0, (LSB)MR18= 0x9c73, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6866 12:18:10.867356 CH1 RK0: MR19=C0C, MR18=9C73
6867 12:18:10.870823 CH1_RK0: MR19=0xC0C, MR18=0x9C73, DQSOSC=390, MR23=63, INC=388, DEC=258
6868 12:18:10.874269 ==
6869 12:18:10.877272 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 12:18:10.880464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 12:18:10.880947 ==
6872 12:18:10.884115 [Gating] SW mode calibration
6873 12:18:10.891007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6874 12:18:10.894490 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6875 12:18:10.900754 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 12:18:10.903763 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6877 12:18:10.907120 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 12:18:10.913627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 12:18:10.916767 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 12:18:10.920410 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 12:18:10.926648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 12:18:10.930694 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 12:18:10.933162 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 12:18:10.937267 Total UI for P1: 0, mck2ui 16
6885 12:18:10.939972 best dqsien dly found for B0: ( 0, 14, 24)
6886 12:18:10.943475 Total UI for P1: 0, mck2ui 16
6887 12:18:10.946714 best dqsien dly found for B1: ( 0, 14, 24)
6888 12:18:10.949799 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6889 12:18:10.956705 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6890 12:18:10.957168
6891 12:18:10.960209 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 12:18:10.963587 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6893 12:18:10.966320 [Gating] SW calibration Done
6894 12:18:10.966738 ==
6895 12:18:10.969885 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 12:18:10.973221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 12:18:10.973738 ==
6898 12:18:10.976442 RX Vref Scan: 0
6899 12:18:10.976860
6900 12:18:10.977191 RX Vref 0 -> 0, step: 1
6901 12:18:10.977505
6902 12:18:10.979554 RX Delay -410 -> 252, step: 16
6903 12:18:10.986286 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6904 12:18:10.990042 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6905 12:18:10.992464 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6906 12:18:10.995823 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6907 12:18:11.002903 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6908 12:18:11.005782 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6909 12:18:11.009086 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6910 12:18:11.012712 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6911 12:18:11.019265 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6912 12:18:11.022438 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6913 12:18:11.025827 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6914 12:18:11.029086 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6915 12:18:11.035455 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6916 12:18:11.039085 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6917 12:18:11.041846 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6918 12:18:11.048797 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6919 12:18:11.049230 ==
6920 12:18:11.051837 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 12:18:11.055158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 12:18:11.055589 ==
6923 12:18:11.056008 DQS Delay:
6924 12:18:11.058445 DQS0 = 51, DQS1 = 59
6925 12:18:11.058873 DQM Delay:
6926 12:18:11.061738 DQM0 = 19, DQM1 = 22
6927 12:18:11.062163 DQ Delay:
6928 12:18:11.064985 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6929 12:18:11.068274 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6930 12:18:11.071693 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6931 12:18:11.075285 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6932 12:18:11.075708
6933 12:18:11.076098
6934 12:18:11.076416 ==
6935 12:18:11.078199 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 12:18:11.081169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 12:18:11.081475 ==
6938 12:18:11.081723
6939 12:18:11.084812
6940 12:18:11.085115 TX Vref Scan disable
6941 12:18:11.087828 == TX Byte 0 ==
6942 12:18:11.091143 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6943 12:18:11.094828 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6944 12:18:11.097702 == TX Byte 1 ==
6945 12:18:11.100941 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6946 12:18:11.104414 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6947 12:18:11.104720 ==
6948 12:18:11.107718 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 12:18:11.111131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 12:18:11.114280 ==
6951 12:18:11.114666
6952 12:18:11.114999
6953 12:18:11.115318 TX Vref Scan disable
6954 12:18:11.118030 == TX Byte 0 ==
6955 12:18:11.120898 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6956 12:18:11.124315 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6957 12:18:11.127769 == TX Byte 1 ==
6958 12:18:11.130814 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6959 12:18:11.134065 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6960 12:18:11.134368
6961 12:18:11.137151 [DATLAT]
6962 12:18:11.137453 Freq=400, CH1 RK1
6963 12:18:11.137694
6964 12:18:11.140490 DATLAT Default: 0xe
6965 12:18:11.140910 0, 0xFFFF, sum = 0
6966 12:18:11.144258 1, 0xFFFF, sum = 0
6967 12:18:11.144729 2, 0xFFFF, sum = 0
6968 12:18:11.147353 3, 0xFFFF, sum = 0
6969 12:18:11.147811 4, 0xFFFF, sum = 0
6970 12:18:11.150598 5, 0xFFFF, sum = 0
6971 12:18:11.150905 6, 0xFFFF, sum = 0
6972 12:18:11.153806 7, 0xFFFF, sum = 0
6973 12:18:11.154113 8, 0xFFFF, sum = 0
6974 12:18:11.157146 9, 0xFFFF, sum = 0
6975 12:18:11.157579 10, 0xFFFF, sum = 0
6976 12:18:11.160596 11, 0xFFFF, sum = 0
6977 12:18:11.161026 12, 0xFFFF, sum = 0
6978 12:18:11.163783 13, 0x0, sum = 1
6979 12:18:11.164373 14, 0x0, sum = 2
6980 12:18:11.167177 15, 0x0, sum = 3
6981 12:18:11.167606 16, 0x0, sum = 4
6982 12:18:11.170693 best_step = 14
6983 12:18:11.171221
6984 12:18:11.171561 ==
6985 12:18:11.174034 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 12:18:11.177208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 12:18:11.177639 ==
6988 12:18:11.180638 RX Vref Scan: 0
6989 12:18:11.181066
6990 12:18:11.181403 RX Vref 0 -> 0, step: 1
6991 12:18:11.183384
6992 12:18:11.183866 RX Delay -359 -> 252, step: 8
6993 12:18:11.192064 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6994 12:18:11.195515 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6995 12:18:11.198804 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6996 12:18:11.204824 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6997 12:18:11.208106 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6998 12:18:11.211886 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6999 12:18:11.214776 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7000 12:18:11.221468 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7001 12:18:11.224676 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7002 12:18:11.227804 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7003 12:18:11.232458 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7004 12:18:11.238253 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
7005 12:18:11.241407 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7006 12:18:11.244962 iDelay=225, Bit 13, Center -36 (-287 ~ 216) 504
7007 12:18:11.250946 iDelay=225, Bit 14, Center -36 (-287 ~ 216) 504
7008 12:18:11.254440 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7009 12:18:11.255047 ==
7010 12:18:11.257288 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 12:18:11.261379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 12:18:11.261967 ==
7013 12:18:11.264258 DQS Delay:
7014 12:18:11.264727 DQS0 = 48, DQS1 = 56
7015 12:18:11.265102 DQM Delay:
7016 12:18:11.267803 DQM0 = 13, DQM1 = 12
7017 12:18:11.268578 DQ Delay:
7018 12:18:11.270741 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7019 12:18:11.273666 DQ4 =12, DQ5 =20, DQ6 =28, DQ7 =12
7020 12:18:11.276986 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7021 12:18:11.280144 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
7022 12:18:11.280230
7023 12:18:11.280316
7024 12:18:11.289867 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7025 12:18:11.289954 CH1 RK1: MR19=C0C, MR18=6D5D
7026 12:18:11.296508 CH1_RK1: MR19=0xC0C, MR18=0x6D5D, DQSOSC=396, MR23=63, INC=376, DEC=251
7027 12:18:11.300167 [RxdqsGatingPostProcess] freq 400
7028 12:18:11.306743 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7029 12:18:11.310129 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 12:18:11.313262 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 12:18:11.316762 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 12:18:11.319618 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 12:18:11.322868 best DQS0 dly(2T, 0.5T) = (0, 10)
7034 12:18:11.326059 best DQS1 dly(2T, 0.5T) = (0, 10)
7035 12:18:11.329770 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7036 12:18:11.332719 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7037 12:18:11.335964 Pre-setting of DQS Precalculation
7038 12:18:11.339661 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7039 12:18:11.346221 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7040 12:18:11.352668 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7041 12:18:11.352756
7042 12:18:11.352822
7043 12:18:11.356064 [Calibration Summary] 800 Mbps
7044 12:18:11.359395 CH 0, Rank 0
7045 12:18:11.359478 SW Impedance : PASS
7046 12:18:11.362653 DUTY Scan : NO K
7047 12:18:11.366107 ZQ Calibration : PASS
7048 12:18:11.366198 Jitter Meter : NO K
7049 12:18:11.369716 CBT Training : PASS
7050 12:18:11.373092 Write leveling : PASS
7051 12:18:11.373179 RX DQS gating : PASS
7052 12:18:11.375870 RX DQ/DQS(RDDQC) : PASS
7053 12:18:11.379512 TX DQ/DQS : PASS
7054 12:18:11.379606 RX DATLAT : PASS
7055 12:18:11.382527 RX DQ/DQS(Engine): PASS
7056 12:18:11.382626 TX OE : NO K
7057 12:18:11.386163 All Pass.
7058 12:18:11.386272
7059 12:18:11.386359 CH 0, Rank 1
7060 12:18:11.389418 SW Impedance : PASS
7061 12:18:11.389541 DUTY Scan : NO K
7062 12:18:11.392777 ZQ Calibration : PASS
7063 12:18:11.395717 Jitter Meter : NO K
7064 12:18:11.395930 CBT Training : PASS
7065 12:18:11.399268 Write leveling : NO K
7066 12:18:11.402534 RX DQS gating : PASS
7067 12:18:11.402723 RX DQ/DQS(RDDQC) : PASS
7068 12:18:11.406005 TX DQ/DQS : PASS
7069 12:18:11.409429 RX DATLAT : PASS
7070 12:18:11.409657 RX DQ/DQS(Engine): PASS
7071 12:18:11.412668 TX OE : NO K
7072 12:18:11.412960 All Pass.
7073 12:18:11.413207
7074 12:18:11.415535 CH 1, Rank 0
7075 12:18:11.415819 SW Impedance : PASS
7076 12:18:11.419317 DUTY Scan : NO K
7077 12:18:11.422373 ZQ Calibration : PASS
7078 12:18:11.422736 Jitter Meter : NO K
7079 12:18:11.425917 CBT Training : PASS
7080 12:18:11.429322 Write leveling : PASS
7081 12:18:11.429731 RX DQS gating : PASS
7082 12:18:11.432373 RX DQ/DQS(RDDQC) : PASS
7083 12:18:11.435945 TX DQ/DQS : PASS
7084 12:18:11.436340 RX DATLAT : PASS
7085 12:18:11.439048 RX DQ/DQS(Engine): PASS
7086 12:18:11.442465 TX OE : NO K
7087 12:18:11.442859 All Pass.
7088 12:18:11.443174
7089 12:18:11.443507 CH 1, Rank 1
7090 12:18:11.445561 SW Impedance : PASS
7091 12:18:11.448818 DUTY Scan : NO K
7092 12:18:11.449200 ZQ Calibration : PASS
7093 12:18:11.452653 Jitter Meter : NO K
7094 12:18:11.455552 CBT Training : PASS
7095 12:18:11.456003 Write leveling : NO K
7096 12:18:11.458924 RX DQS gating : PASS
7097 12:18:11.459309 RX DQ/DQS(RDDQC) : PASS
7098 12:18:11.462346 TX DQ/DQS : PASS
7099 12:18:11.465616 RX DATLAT : PASS
7100 12:18:11.466020 RX DQ/DQS(Engine): PASS
7101 12:18:11.469228 TX OE : NO K
7102 12:18:11.469634 All Pass.
7103 12:18:11.469994
7104 12:18:11.471957 DramC Write-DBI off
7105 12:18:11.475088 PER_BANK_REFRESH: Hybrid Mode
7106 12:18:11.475486 TX_TRACKING: ON
7107 12:18:11.485298 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7108 12:18:11.488539 [FAST_K] Save calibration result to emmc
7109 12:18:11.491800 dramc_set_vcore_voltage set vcore to 725000
7110 12:18:11.495327 Read voltage for 1600, 0
7111 12:18:11.495790 Vio18 = 0
7112 12:18:11.498304 Vcore = 725000
7113 12:18:11.498751 Vdram = 0
7114 12:18:11.499111 Vddq = 0
7115 12:18:11.499421 Vmddr = 0
7116 12:18:11.505015 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7117 12:18:11.511317 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7118 12:18:11.511793 MEM_TYPE=3, freq_sel=13
7119 12:18:11.514609 sv_algorithm_assistance_LP4_3733
7120 12:18:11.518082 ============ PULL DRAM RESETB DOWN ============
7121 12:18:11.524635 ========== PULL DRAM RESETB DOWN end =========
7122 12:18:11.527666 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7123 12:18:11.531234 ===================================
7124 12:18:11.534472 LPDDR4 DRAM CONFIGURATION
7125 12:18:11.537585 ===================================
7126 12:18:11.537992 EX_ROW_EN[0] = 0x0
7127 12:18:11.541038 EX_ROW_EN[1] = 0x0
7128 12:18:11.544554 LP4Y_EN = 0x0
7129 12:18:11.544955 WORK_FSP = 0x1
7130 12:18:11.547562 WL = 0x5
7131 12:18:11.548009 RL = 0x5
7132 12:18:11.551015 BL = 0x2
7133 12:18:11.551413 RPST = 0x0
7134 12:18:11.554004 RD_PRE = 0x0
7135 12:18:11.554385 WR_PRE = 0x1
7136 12:18:11.557323 WR_PST = 0x1
7137 12:18:11.557782 DBI_WR = 0x0
7138 12:18:11.560840 DBI_RD = 0x0
7139 12:18:11.561313 OTF = 0x1
7140 12:18:11.564051 ===================================
7141 12:18:11.567298 ===================================
7142 12:18:11.570994 ANA top config
7143 12:18:11.574505 ===================================
7144 12:18:11.574979 DLL_ASYNC_EN = 0
7145 12:18:11.577908 ALL_SLAVE_EN = 0
7146 12:18:11.580488 NEW_RANK_MODE = 1
7147 12:18:11.584041 DLL_IDLE_MODE = 1
7148 12:18:11.587694 LP45_APHY_COMB_EN = 1
7149 12:18:11.588163 TX_ODT_DIS = 0
7150 12:18:11.590620 NEW_8X_MODE = 1
7151 12:18:11.594131 ===================================
7152 12:18:11.597321 ===================================
7153 12:18:11.600569 data_rate = 3200
7154 12:18:11.603837 CKR = 1
7155 12:18:11.607179 DQ_P2S_RATIO = 8
7156 12:18:11.610535 ===================================
7157 12:18:11.613863 CA_P2S_RATIO = 8
7158 12:18:11.614319 DQ_CA_OPEN = 0
7159 12:18:11.616940 DQ_SEMI_OPEN = 0
7160 12:18:11.620799 CA_SEMI_OPEN = 0
7161 12:18:11.623359 CA_FULL_RATE = 0
7162 12:18:11.626789 DQ_CKDIV4_EN = 0
7163 12:18:11.630012 CA_CKDIV4_EN = 0
7164 12:18:11.630438 CA_PREDIV_EN = 0
7165 12:18:11.633784 PH8_DLY = 12
7166 12:18:11.636795 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7167 12:18:11.640281 DQ_AAMCK_DIV = 4
7168 12:18:11.643625 CA_AAMCK_DIV = 4
7169 12:18:11.647026 CA_ADMCK_DIV = 4
7170 12:18:11.647570 DQ_TRACK_CA_EN = 0
7171 12:18:11.650195 CA_PICK = 1600
7172 12:18:11.653574 CA_MCKIO = 1600
7173 12:18:11.656552 MCKIO_SEMI = 0
7174 12:18:11.659892 PLL_FREQ = 3068
7175 12:18:11.662974 DQ_UI_PI_RATIO = 32
7176 12:18:11.666455 CA_UI_PI_RATIO = 0
7177 12:18:11.669622 ===================================
7178 12:18:11.673178 ===================================
7179 12:18:11.676488 memory_type:LPDDR4
7180 12:18:11.676915 GP_NUM : 10
7181 12:18:11.679718 SRAM_EN : 1
7182 12:18:11.680283 MD32_EN : 0
7183 12:18:11.682988 ===================================
7184 12:18:11.686144 [ANA_INIT] >>>>>>>>>>>>>>
7185 12:18:11.689611 <<<<<< [CONFIGURE PHASE]: ANA_TX
7186 12:18:11.692541 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7187 12:18:11.695815 ===================================
7188 12:18:11.699179 data_rate = 3200,PCW = 0X7600
7189 12:18:11.702904 ===================================
7190 12:18:11.706240 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7191 12:18:11.709545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 12:18:11.715674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7193 12:18:11.722607 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7194 12:18:11.725865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7195 12:18:11.729269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7196 12:18:11.729719 [ANA_INIT] flow start
7197 12:18:11.732549 [ANA_INIT] PLL >>>>>>>>
7198 12:18:11.735794 [ANA_INIT] PLL <<<<<<<<
7199 12:18:11.736188 [ANA_INIT] MIDPI >>>>>>>>
7200 12:18:11.739281 [ANA_INIT] MIDPI <<<<<<<<
7201 12:18:11.742205 [ANA_INIT] DLL >>>>>>>>
7202 12:18:11.742546 [ANA_INIT] DLL <<<<<<<<
7203 12:18:11.746099 [ANA_INIT] flow end
7204 12:18:11.748748 ============ LP4 DIFF to SE enter ============
7205 12:18:11.752755 ============ LP4 DIFF to SE exit ============
7206 12:18:11.755553 [ANA_INIT] <<<<<<<<<<<<<
7207 12:18:11.758785 [Flow] Enable top DCM control >>>>>
7208 12:18:11.762199 [Flow] Enable top DCM control <<<<<
7209 12:18:11.765683 Enable DLL master slave shuffle
7210 12:18:11.772517 ==============================================================
7211 12:18:11.772938 Gating Mode config
7212 12:18:11.778856 ==============================================================
7213 12:18:11.782094 Config description:
7214 12:18:11.788879 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7215 12:18:11.795151 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7216 12:18:11.801313 SELPH_MODE 0: By rank 1: By Phase
7217 12:18:11.808232 ==============================================================
7218 12:18:11.811342 GAT_TRACK_EN = 1
7219 12:18:11.811426 RX_GATING_MODE = 2
7220 12:18:11.814756 RX_GATING_TRACK_MODE = 2
7221 12:18:11.818142 SELPH_MODE = 1
7222 12:18:11.821270 PICG_EARLY_EN = 1
7223 12:18:11.824945 VALID_LAT_VALUE = 1
7224 12:18:11.831345 ==============================================================
7225 12:18:11.834767 Enter into Gating configuration >>>>
7226 12:18:11.837924 Exit from Gating configuration <<<<
7227 12:18:11.841620 Enter into DVFS_PRE_config >>>>>
7228 12:18:11.851324 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7229 12:18:11.854580 Exit from DVFS_PRE_config <<<<<
7230 12:18:11.857930 Enter into PICG configuration >>>>
7231 12:18:11.861076 Exit from PICG configuration <<<<
7232 12:18:11.864456 [RX_INPUT] configuration >>>>>
7233 12:18:11.867905 [RX_INPUT] configuration <<<<<
7234 12:18:11.871452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7235 12:18:11.878107 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7236 12:18:11.884347 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 12:18:11.890654 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 12:18:11.896980 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 12:18:11.900554 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 12:18:11.907231 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7241 12:18:11.910733 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7242 12:18:11.914292 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7243 12:18:11.916946 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7244 12:18:11.923692 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7245 12:18:11.927057 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7246 12:18:11.930468 ===================================
7247 12:18:11.933655 LPDDR4 DRAM CONFIGURATION
7248 12:18:11.936885 ===================================
7249 12:18:11.937447 EX_ROW_EN[0] = 0x0
7250 12:18:11.940518 EX_ROW_EN[1] = 0x0
7251 12:18:11.940931 LP4Y_EN = 0x0
7252 12:18:11.943650 WORK_FSP = 0x1
7253 12:18:11.944107 WL = 0x5
7254 12:18:11.947356 RL = 0x5
7255 12:18:11.947715 BL = 0x2
7256 12:18:11.950463 RPST = 0x0
7257 12:18:11.950885 RD_PRE = 0x0
7258 12:18:11.953738 WR_PRE = 0x1
7259 12:18:11.954163 WR_PST = 0x1
7260 12:18:11.956882 DBI_WR = 0x0
7261 12:18:11.960184 DBI_RD = 0x0
7262 12:18:11.960628 OTF = 0x1
7263 12:18:11.963428 ===================================
7264 12:18:11.966842 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7265 12:18:11.969997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7266 12:18:11.976509 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7267 12:18:11.979547 ===================================
7268 12:18:11.982650 LPDDR4 DRAM CONFIGURATION
7269 12:18:11.986337 ===================================
7270 12:18:11.986421 EX_ROW_EN[0] = 0x10
7271 12:18:11.989326 EX_ROW_EN[1] = 0x0
7272 12:18:11.989409 LP4Y_EN = 0x0
7273 12:18:11.992606 WORK_FSP = 0x1
7274 12:18:11.992727 WL = 0x5
7275 12:18:11.995685 RL = 0x5
7276 12:18:11.995822 BL = 0x2
7277 12:18:11.999660 RPST = 0x0
7278 12:18:11.999784 RD_PRE = 0x0
7279 12:18:12.002419 WR_PRE = 0x1
7280 12:18:12.005846 WR_PST = 0x1
7281 12:18:12.005939 DBI_WR = 0x0
7282 12:18:12.009043 DBI_RD = 0x0
7283 12:18:12.009155 OTF = 0x1
7284 12:18:12.012134 ===================================
7285 12:18:12.018713 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7286 12:18:12.018818 ==
7287 12:18:12.022145 Dram Type= 6, Freq= 0, CH_0, rank 0
7288 12:18:12.025558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7289 12:18:12.025630 ==
7290 12:18:12.028900 [Duty_Offset_Calibration]
7291 12:18:12.032000 B0:1 B1:-1 CA:0
7292 12:18:12.032076
7293 12:18:12.035653 [DutyScan_Calibration_Flow] k_type=0
7294 12:18:12.043856
7295 12:18:12.043933 ==CLK 0==
7296 12:18:12.047078 Final CLK duty delay cell = 0
7297 12:18:12.050466 [0] MAX Duty = 5125%(X100), DQS PI = 22
7298 12:18:12.053720 [0] MIN Duty = 4875%(X100), DQS PI = 10
7299 12:18:12.057374 [0] AVG Duty = 5000%(X100)
7300 12:18:12.057451
7301 12:18:12.060303 CH0 CLK Duty spec in!! Max-Min= 250%
7302 12:18:12.063555 [DutyScan_Calibration_Flow] ====Done====
7303 12:18:12.063625
7304 12:18:12.067301 [DutyScan_Calibration_Flow] k_type=1
7305 12:18:12.082842
7306 12:18:12.082948 ==DQS 0 ==
7307 12:18:12.086521 Final DQS duty delay cell = -4
7308 12:18:12.090179 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7309 12:18:12.093049 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7310 12:18:12.096602 [-4] AVG Duty = 4922%(X100)
7311 12:18:12.096685
7312 12:18:12.096749 ==DQS 1 ==
7313 12:18:12.099251 Final DQS duty delay cell = 0
7314 12:18:12.102719 [0] MAX Duty = 5187%(X100), DQS PI = 4
7315 12:18:12.106243 [0] MIN Duty = 5031%(X100), DQS PI = 18
7316 12:18:12.109281 [0] AVG Duty = 5109%(X100)
7317 12:18:12.109363
7318 12:18:12.112951 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7319 12:18:12.113023
7320 12:18:12.116283 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7321 12:18:12.119490 [DutyScan_Calibration_Flow] ====Done====
7322 12:18:12.119597
7323 12:18:12.122765 [DutyScan_Calibration_Flow] k_type=3
7324 12:18:12.140901
7325 12:18:12.140987 ==DQM 0 ==
7326 12:18:12.144013 Final DQM duty delay cell = 0
7327 12:18:12.147101 [0] MAX Duty = 5124%(X100), DQS PI = 22
7328 12:18:12.150170 [0] MIN Duty = 4907%(X100), DQS PI = 8
7329 12:18:12.153887 [0] AVG Duty = 5015%(X100)
7330 12:18:12.153960
7331 12:18:12.154022 ==DQM 1 ==
7332 12:18:12.156876 Final DQM duty delay cell = 0
7333 12:18:12.160504 [0] MAX Duty = 5031%(X100), DQS PI = 54
7334 12:18:12.163576 [0] MIN Duty = 4782%(X100), DQS PI = 22
7335 12:18:12.167068 [0] AVG Duty = 4906%(X100)
7336 12:18:12.167158
7337 12:18:12.170220 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7338 12:18:12.170303
7339 12:18:12.173514 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7340 12:18:12.176900 [DutyScan_Calibration_Flow] ====Done====
7341 12:18:12.176993
7342 12:18:12.180319 [DutyScan_Calibration_Flow] k_type=2
7343 12:18:12.197040
7344 12:18:12.197136 ==DQ 0 ==
7345 12:18:12.200556 Final DQ duty delay cell = -4
7346 12:18:12.204136 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7347 12:18:12.206993 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7348 12:18:12.210035 [-4] AVG Duty = 4953%(X100)
7349 12:18:12.210117
7350 12:18:12.210182 ==DQ 1 ==
7351 12:18:12.213684 Final DQ duty delay cell = 0
7352 12:18:12.217341 [0] MAX Duty = 5125%(X100), DQS PI = 4
7353 12:18:12.220313 [0] MIN Duty = 5000%(X100), DQS PI = 36
7354 12:18:12.223132 [0] AVG Duty = 5062%(X100)
7355 12:18:12.223213
7356 12:18:12.226730 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7357 12:18:12.226818
7358 12:18:12.229858 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7359 12:18:12.233353 [DutyScan_Calibration_Flow] ====Done====
7360 12:18:12.233480 ==
7361 12:18:12.236347 Dram Type= 6, Freq= 0, CH_1, rank 0
7362 12:18:12.239756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7363 12:18:12.239853 ==
7364 12:18:12.243334 [Duty_Offset_Calibration]
7365 12:18:12.243435 B0:-1 B1:1 CA:2
7366 12:18:12.246729
7367 12:18:12.249339 [DutyScan_Calibration_Flow] k_type=0
7368 12:18:12.257460
7369 12:18:12.257595 ==CLK 0==
7370 12:18:12.260987 Final CLK duty delay cell = 0
7371 12:18:12.263806 [0] MAX Duty = 5187%(X100), DQS PI = 24
7372 12:18:12.267510 [0] MIN Duty = 4969%(X100), DQS PI = 0
7373 12:18:12.271244 [0] AVG Duty = 5078%(X100)
7374 12:18:12.271823
7375 12:18:12.274925 CH1 CLK Duty spec in!! Max-Min= 218%
7376 12:18:12.277345 [DutyScan_Calibration_Flow] ====Done====
7377 12:18:12.277788
7378 12:18:12.280927 [DutyScan_Calibration_Flow] k_type=1
7379 12:18:12.297655
7380 12:18:12.298266 ==DQS 0 ==
7381 12:18:12.300668 Final DQS duty delay cell = 0
7382 12:18:12.304252 [0] MAX Duty = 5156%(X100), DQS PI = 18
7383 12:18:12.307618 [0] MIN Duty = 4907%(X100), DQS PI = 10
7384 12:18:12.311071 [0] AVG Duty = 5031%(X100)
7385 12:18:12.311470
7386 12:18:12.311850 ==DQS 1 ==
7387 12:18:12.313834 Final DQS duty delay cell = 0
7388 12:18:12.317181 [0] MAX Duty = 5093%(X100), DQS PI = 24
7389 12:18:12.320816 [0] MIN Duty = 4969%(X100), DQS PI = 56
7390 12:18:12.323827 [0] AVG Duty = 5031%(X100)
7391 12:18:12.324277
7392 12:18:12.327044 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7393 12:18:12.327490
7394 12:18:12.330513 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7395 12:18:12.334073 [DutyScan_Calibration_Flow] ====Done====
7396 12:18:12.334505
7397 12:18:12.337082 [DutyScan_Calibration_Flow] k_type=3
7398 12:18:12.353783
7399 12:18:12.354202 ==DQM 0 ==
7400 12:18:12.357173 Final DQM duty delay cell = -4
7401 12:18:12.360321 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7402 12:18:12.363836 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7403 12:18:12.366895 [-4] AVG Duty = 4922%(X100)
7404 12:18:12.367434
7405 12:18:12.367997 ==DQM 1 ==
7406 12:18:12.370032 Final DQM duty delay cell = 0
7407 12:18:12.373558 [0] MAX Duty = 5156%(X100), DQS PI = 6
7408 12:18:12.376804 [0] MIN Duty = 4969%(X100), DQS PI = 28
7409 12:18:12.380147 [0] AVG Duty = 5062%(X100)
7410 12:18:12.380562
7411 12:18:12.383538 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7412 12:18:12.384010
7413 12:18:12.386505 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7414 12:18:12.390267 [DutyScan_Calibration_Flow] ====Done====
7415 12:18:12.390742
7416 12:18:12.393228 [DutyScan_Calibration_Flow] k_type=2
7417 12:18:12.410546
7418 12:18:12.410988 ==DQ 0 ==
7419 12:18:12.414178 Final DQ duty delay cell = 0
7420 12:18:12.417283 [0] MAX Duty = 5187%(X100), DQS PI = 34
7421 12:18:12.420759 [0] MIN Duty = 4906%(X100), DQS PI = 10
7422 12:18:12.423999 [0] AVG Duty = 5046%(X100)
7423 12:18:12.424467
7424 12:18:12.424808 ==DQ 1 ==
7425 12:18:12.427057 Final DQ duty delay cell = 0
7426 12:18:12.430758 [0] MAX Duty = 5156%(X100), DQS PI = 8
7427 12:18:12.433884 [0] MIN Duty = 4969%(X100), DQS PI = 56
7428 12:18:12.434317 [0] AVG Duty = 5062%(X100)
7429 12:18:12.437502
7430 12:18:12.440275 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7431 12:18:12.440745
7432 12:18:12.443648 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7433 12:18:12.446644 [DutyScan_Calibration_Flow] ====Done====
7434 12:18:12.450140 nWR fixed to 30
7435 12:18:12.453649 [ModeRegInit_LP4] CH0 RK0
7436 12:18:12.454067 [ModeRegInit_LP4] CH0 RK1
7437 12:18:12.456882 [ModeRegInit_LP4] CH1 RK0
7438 12:18:12.460238 [ModeRegInit_LP4] CH1 RK1
7439 12:18:12.460706 match AC timing 5
7440 12:18:12.466945 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7441 12:18:12.470475 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7442 12:18:12.473622 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7443 12:18:12.480551 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7444 12:18:12.483673 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7445 12:18:12.484184 [MiockJmeterHQA]
7446 12:18:12.484566
7447 12:18:12.487001 [DramcMiockJmeter] u1RxGatingPI = 0
7448 12:18:12.489970 0 : 4366, 4140
7449 12:18:12.490524 4 : 4252, 4027
7450 12:18:12.493131 8 : 4365, 4140
7451 12:18:12.493606 12 : 4253, 4026
7452 12:18:12.496876 16 : 4252, 4027
7453 12:18:12.497343 20 : 4363, 4137
7454 12:18:12.497737 24 : 4253, 4027
7455 12:18:12.499787 28 : 4253, 4026
7456 12:18:12.500345 32 : 4252, 4027
7457 12:18:12.502950 36 : 4255, 4029
7458 12:18:12.503378 40 : 4363, 4138
7459 12:18:12.506162 44 : 4252, 4026
7460 12:18:12.506571 48 : 4363, 4137
7461 12:18:12.510041 52 : 4250, 4027
7462 12:18:12.510496 56 : 4253, 4027
7463 12:18:12.510860 60 : 4250, 4027
7464 12:18:12.513390 64 : 4363, 4138
7465 12:18:12.513847 68 : 4250, 4027
7466 12:18:12.516338 72 : 4360, 4137
7467 12:18:12.516750 76 : 4249, 4027
7468 12:18:12.520029 80 : 4250, 4027
7469 12:18:12.520485 84 : 4250, 4027
7470 12:18:12.520828 88 : 4252, 4029
7471 12:18:12.523126 92 : 4360, 558
7472 12:18:12.523577 96 : 4253, 0
7473 12:18:12.526562 100 : 4360, 0
7474 12:18:12.527014 104 : 4363, 0
7475 12:18:12.527375 108 : 4363, 0
7476 12:18:12.529910 112 : 4251, 0
7477 12:18:12.530365 116 : 4250, 0
7478 12:18:12.533337 120 : 4250, 0
7479 12:18:12.533789 124 : 4250, 0
7480 12:18:12.534154 128 : 4250, 0
7481 12:18:12.536885 132 : 4250, 0
7482 12:18:12.537315 136 : 4253, 0
7483 12:18:12.539953 140 : 4360, 0
7484 12:18:12.540401 144 : 4250, 0
7485 12:18:12.540766 148 : 4250, 0
7486 12:18:12.543018 152 : 4249, 0
7487 12:18:12.543469 156 : 4361, 0
7488 12:18:12.543853 160 : 4360, 0
7489 12:18:12.546360 164 : 4249, 0
7490 12:18:12.546790 168 : 4360, 0
7491 12:18:12.549863 172 : 4250, 0
7492 12:18:12.550343 176 : 4250, 0
7493 12:18:12.550751 180 : 4250, 0
7494 12:18:12.552989 184 : 4250, 0
7495 12:18:12.553445 188 : 4253, 0
7496 12:18:12.556143 192 : 4250, 0
7497 12:18:12.556611 196 : 4250, 0
7498 12:18:12.556963 200 : 4253, 0
7499 12:18:12.560042 204 : 4250, 0
7500 12:18:12.560476 208 : 4360, 0
7501 12:18:12.563085 212 : 4250, 0
7502 12:18:12.563512 216 : 4250, 0
7503 12:18:12.563960 220 : 4360, 0
7504 12:18:12.566483 224 : 4250, 99
7505 12:18:12.566933 228 : 4249, 3299
7506 12:18:12.569478 232 : 4250, 4027
7507 12:18:12.569929 236 : 4252, 4029
7508 12:18:12.573224 240 : 4363, 4140
7509 12:18:12.573709 244 : 4360, 4138
7510 12:18:12.576348 248 : 4250, 4027
7511 12:18:12.576840 252 : 4363, 4140
7512 12:18:12.577220 256 : 4360, 4138
7513 12:18:12.579379 260 : 4250, 4027
7514 12:18:12.579794 264 : 4250, 4027
7515 12:18:12.582830 268 : 4252, 4029
7516 12:18:12.583232 272 : 4250, 4027
7517 12:18:12.586281 276 : 4250, 4027
7518 12:18:12.586902 280 : 4250, 4027
7519 12:18:12.589510 284 : 4252, 4029
7520 12:18:12.590016 288 : 4250, 4027
7521 12:18:12.593248 292 : 4360, 4138
7522 12:18:12.593726 296 : 4360, 4138
7523 12:18:12.596357 300 : 4250, 4027
7524 12:18:12.596816 304 : 4363, 4139
7525 12:18:12.599148 308 : 4360, 4138
7526 12:18:12.599549 312 : 4250, 4027
7527 12:18:12.602656 316 : 4250, 4027
7528 12:18:12.603111 320 : 4252, 4029
7529 12:18:12.603452 324 : 4250, 4027
7530 12:18:12.606014 328 : 4250, 4027
7531 12:18:12.606425 332 : 4249, 4027
7532 12:18:12.609446 336 : 4252, 3924
7533 12:18:12.609902 340 : 4250, 2578
7534 12:18:12.612263 344 : 4360, 41
7535 12:18:12.612729
7536 12:18:12.615981 MIOCK jitter meter ch=0
7537 12:18:12.616397
7538 12:18:12.616730 1T = (344-92) = 252 dly cells
7539 12:18:12.622659 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7540 12:18:12.623082 ==
7541 12:18:12.625775 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 12:18:12.629140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 12:18:12.629561 ==
7544 12:18:12.635969 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7545 12:18:12.638875 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7546 12:18:12.645845 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7547 12:18:12.648958 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7548 12:18:12.659143 [CA 0] Center 43 (12~74) winsize 63
7549 12:18:12.662460 [CA 1] Center 43 (13~73) winsize 61
7550 12:18:12.666143 [CA 2] Center 38 (9~68) winsize 60
7551 12:18:12.669087 [CA 3] Center 38 (9~68) winsize 60
7552 12:18:12.672721 [CA 4] Center 36 (7~66) winsize 60
7553 12:18:12.675683 [CA 5] Center 36 (7~66) winsize 60
7554 12:18:12.676184
7555 12:18:12.679288 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7556 12:18:12.679761
7557 12:18:12.682544 [CATrainingPosCal] consider 1 rank data
7558 12:18:12.685717 u2DelayCellTimex100 = 258/100 ps
7559 12:18:12.692481 CA0 delay=43 (12~74),Diff = 7 PI (26 cell)
7560 12:18:12.695106 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7561 12:18:12.698658 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7562 12:18:12.701799 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7563 12:18:12.705368 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7564 12:18:12.708650 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7565 12:18:12.709073
7566 12:18:12.712046 CA PerBit enable=1, Macro0, CA PI delay=36
7567 12:18:12.712466
7568 12:18:12.715687 [CBTSetCACLKResult] CA Dly = 36
7569 12:18:12.718485 CS Dly: 12 (0~43)
7570 12:18:12.721694 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7571 12:18:12.724973 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7572 12:18:12.725418 ==
7573 12:18:12.728584 Dram Type= 6, Freq= 0, CH_0, rank 1
7574 12:18:12.734721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 12:18:12.735173 ==
7576 12:18:12.738441 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7577 12:18:12.745088 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7578 12:18:12.748002 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7579 12:18:12.755234 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7580 12:18:12.762547 [CA 0] Center 43 (13~73) winsize 61
7581 12:18:12.765667 [CA 1] Center 43 (14~73) winsize 60
7582 12:18:12.768776 [CA 2] Center 38 (9~68) winsize 60
7583 12:18:12.772048 [CA 3] Center 38 (9~67) winsize 59
7584 12:18:12.775704 [CA 4] Center 36 (7~65) winsize 59
7585 12:18:12.778633 [CA 5] Center 36 (7~65) winsize 59
7586 12:18:12.778715
7587 12:18:12.782224 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7588 12:18:12.782307
7589 12:18:12.785242 [CATrainingPosCal] consider 2 rank data
7590 12:18:12.788567 u2DelayCellTimex100 = 258/100 ps
7591 12:18:12.795096 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7592 12:18:12.798586 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7593 12:18:12.801706 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7594 12:18:12.805183 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7595 12:18:12.808237 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7596 12:18:12.811762 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7597 12:18:12.811845
7598 12:18:12.814730 CA PerBit enable=1, Macro0, CA PI delay=36
7599 12:18:12.814811
7600 12:18:12.818069 [CBTSetCACLKResult] CA Dly = 36
7601 12:18:12.821402 CS Dly: 12 (0~43)
7602 12:18:12.824816 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7603 12:18:12.827969 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7604 12:18:12.828076
7605 12:18:12.831512 ----->DramcWriteLeveling(PI) begin...
7606 12:18:12.831621 ==
7607 12:18:12.834443 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 12:18:12.841377 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 12:18:12.841460 ==
7610 12:18:12.844814 Write leveling (Byte 0): 35 => 35
7611 12:18:12.848032 Write leveling (Byte 1): 25 => 25
7612 12:18:12.848115 DramcWriteLeveling(PI) end<-----
7613 12:18:12.850985
7614 12:18:12.851066 ==
7615 12:18:12.854473 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 12:18:12.857797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 12:18:12.857880 ==
7618 12:18:12.860609 [Gating] SW mode calibration
7619 12:18:12.867468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7620 12:18:12.873896 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7621 12:18:12.877270 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 12:18:12.880648 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 12:18:12.887163 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 12:18:12.890807 1 4 12 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7625 12:18:12.893918 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7626 12:18:12.900404 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7627 12:18:12.904181 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 12:18:12.907683 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 12:18:12.910716 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 12:18:12.917473 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 12:18:12.920227 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7632 12:18:12.923663 1 5 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
7633 12:18:12.930193 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7634 12:18:12.933560 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7635 12:18:12.936861 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7636 12:18:12.943805 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 12:18:12.946808 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 12:18:12.950130 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 12:18:12.956822 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7640 12:18:12.960177 1 6 12 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
7641 12:18:12.963206 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7642 12:18:12.970105 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7643 12:18:12.972870 1 6 24 | B1->B0 | 4140 4646 | 1 0 | (0 0) (0 0)
7644 12:18:12.976480 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 12:18:12.982860 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 12:18:12.986084 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 12:18:12.989620 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7648 12:18:12.996253 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7649 12:18:12.999550 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7650 12:18:13.002697 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7651 12:18:13.009388 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 12:18:13.012689 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 12:18:13.015881 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 12:18:13.022608 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 12:18:13.026243 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 12:18:13.029339 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 12:18:13.035708 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 12:18:13.039088 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 12:18:13.042555 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 12:18:13.049121 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 12:18:13.052361 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 12:18:13.055555 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 12:18:13.062154 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 12:18:13.065559 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7665 12:18:13.068872 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7666 12:18:13.072360 Total UI for P1: 0, mck2ui 16
7667 12:18:13.075380 best dqsien dly found for B0: ( 1, 9, 12)
7668 12:18:13.082067 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7669 12:18:13.085328 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 12:18:13.088767 Total UI for P1: 0, mck2ui 16
7671 12:18:13.092219 best dqsien dly found for B1: ( 1, 9, 20)
7672 12:18:13.095455 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7673 12:18:13.098715 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7674 12:18:13.098824
7675 12:18:13.101807 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7676 12:18:13.108607 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7677 12:18:13.108690 [Gating] SW calibration Done
7678 12:18:13.108756 ==
7679 12:18:13.112237 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 12:18:13.118622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 12:18:13.118706 ==
7682 12:18:13.118803 RX Vref Scan: 0
7683 12:18:13.118864
7684 12:18:13.121978 RX Vref 0 -> 0, step: 1
7685 12:18:13.122060
7686 12:18:13.125273 RX Delay 0 -> 252, step: 8
7687 12:18:13.128771 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7688 12:18:13.132089 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7689 12:18:13.135224 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7690 12:18:13.138344 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7691 12:18:13.144947 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7692 12:18:13.148278 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7693 12:18:13.151431 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7694 12:18:13.154867 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7695 12:18:13.158146 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7696 12:18:13.164791 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7697 12:18:13.167940 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7698 12:18:13.171619 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7699 12:18:13.174406 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7700 12:18:13.181316 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7701 12:18:13.184410 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7702 12:18:13.187678 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7703 12:18:13.187806 ==
7704 12:18:13.190977 Dram Type= 6, Freq= 0, CH_0, rank 0
7705 12:18:13.194339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7706 12:18:13.197806 ==
7707 12:18:13.197889 DQS Delay:
7708 12:18:13.197954 DQS0 = 0, DQS1 = 0
7709 12:18:13.200912 DQM Delay:
7710 12:18:13.200994 DQM0 = 136, DQM1 = 126
7711 12:18:13.203994 DQ Delay:
7712 12:18:13.207240 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7713 12:18:13.210799 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7714 12:18:13.214247 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7715 12:18:13.217042 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7716 12:18:13.217141
7717 12:18:13.217231
7718 12:18:13.217320 ==
7719 12:18:13.220464 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 12:18:13.223901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 12:18:13.224004 ==
7722 12:18:13.226994
7723 12:18:13.227090
7724 12:18:13.227178 TX Vref Scan disable
7725 12:18:13.230326 == TX Byte 0 ==
7726 12:18:13.233610 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7727 12:18:13.237014 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7728 12:18:13.240048 == TX Byte 1 ==
7729 12:18:13.243418 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7730 12:18:13.246942 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7731 12:18:13.249990 ==
7732 12:18:13.253184 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 12:18:13.256574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 12:18:13.256681 ==
7735 12:18:13.269753
7736 12:18:13.273074 TX Vref early break, caculate TX vref
7737 12:18:13.276528 TX Vref=16, minBit 4, minWin=22, winSum=367
7738 12:18:13.279636 TX Vref=18, minBit 4, minWin=22, winSum=378
7739 12:18:13.282591 TX Vref=20, minBit 1, minWin=23, winSum=385
7740 12:18:13.286023 TX Vref=22, minBit 1, minWin=24, winSum=399
7741 12:18:13.289607 TX Vref=24, minBit 7, minWin=24, winSum=406
7742 12:18:13.295914 TX Vref=26, minBit 0, minWin=25, winSum=415
7743 12:18:13.299230 TX Vref=28, minBit 0, minWin=24, winSum=415
7744 12:18:13.302652 TX Vref=30, minBit 0, minWin=24, winSum=406
7745 12:18:13.306088 TX Vref=32, minBit 0, minWin=24, winSum=401
7746 12:18:13.309590 TX Vref=34, minBit 7, minWin=22, winSum=383
7747 12:18:13.316040 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 26
7748 12:18:13.316145
7749 12:18:13.319830 Final TX Range 0 Vref 26
7750 12:18:13.319934
7751 12:18:13.320027 ==
7752 12:18:13.322398 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 12:18:13.325869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 12:18:13.325975 ==
7755 12:18:13.326069
7756 12:18:13.326156
7757 12:18:13.329144 TX Vref Scan disable
7758 12:18:13.335953 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7759 12:18:13.336057 == TX Byte 0 ==
7760 12:18:13.338821 u2DelayCellOfst[0]=15 cells (4 PI)
7761 12:18:13.342226 u2DelayCellOfst[1]=18 cells (5 PI)
7762 12:18:13.345314 u2DelayCellOfst[2]=15 cells (4 PI)
7763 12:18:13.348721 u2DelayCellOfst[3]=15 cells (4 PI)
7764 12:18:13.352152 u2DelayCellOfst[4]=11 cells (3 PI)
7765 12:18:13.355185 u2DelayCellOfst[5]=0 cells (0 PI)
7766 12:18:13.358939 u2DelayCellOfst[6]=18 cells (5 PI)
7767 12:18:13.361925 u2DelayCellOfst[7]=22 cells (6 PI)
7768 12:18:13.365457 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7769 12:18:13.368611 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7770 12:18:13.372303 == TX Byte 1 ==
7771 12:18:13.375410 u2DelayCellOfst[8]=0 cells (0 PI)
7772 12:18:13.378733 u2DelayCellOfst[9]=3 cells (1 PI)
7773 12:18:13.378817 u2DelayCellOfst[10]=7 cells (2 PI)
7774 12:18:13.381727 u2DelayCellOfst[11]=3 cells (1 PI)
7775 12:18:13.385055 u2DelayCellOfst[12]=11 cells (3 PI)
7776 12:18:13.388439 u2DelayCellOfst[13]=15 cells (4 PI)
7777 12:18:13.391911 u2DelayCellOfst[14]=15 cells (4 PI)
7778 12:18:13.394897 u2DelayCellOfst[15]=11 cells (3 PI)
7779 12:18:13.401768 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7780 12:18:13.405217 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7781 12:18:13.405318 DramC Write-DBI on
7782 12:18:13.405412 ==
7783 12:18:13.408136 Dram Type= 6, Freq= 0, CH_0, rank 0
7784 12:18:13.414657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7785 12:18:13.414759 ==
7786 12:18:13.414856
7787 12:18:13.414946
7788 12:18:13.418244 TX Vref Scan disable
7789 12:18:13.418347 == TX Byte 0 ==
7790 12:18:13.424422 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7791 12:18:13.424526 == TX Byte 1 ==
7792 12:18:13.427766 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7793 12:18:13.431275 DramC Write-DBI off
7794 12:18:13.431374
7795 12:18:13.431469 [DATLAT]
7796 12:18:13.434732 Freq=1600, CH0 RK0
7797 12:18:13.434835
7798 12:18:13.434927 DATLAT Default: 0xf
7799 12:18:13.437749 0, 0xFFFF, sum = 0
7800 12:18:13.437848 1, 0xFFFF, sum = 0
7801 12:18:13.441202 2, 0xFFFF, sum = 0
7802 12:18:13.441307 3, 0xFFFF, sum = 0
7803 12:18:13.444494 4, 0xFFFF, sum = 0
7804 12:18:13.444600 5, 0xFFFF, sum = 0
7805 12:18:13.448200 6, 0xFFFF, sum = 0
7806 12:18:13.450953 7, 0xFFFF, sum = 0
7807 12:18:13.451057 8, 0xFFFF, sum = 0
7808 12:18:13.453987 9, 0xFFFF, sum = 0
7809 12:18:13.454091 10, 0xFFFF, sum = 0
7810 12:18:13.457299 11, 0xFFFF, sum = 0
7811 12:18:13.457403 12, 0xFFFF, sum = 0
7812 12:18:13.460675 13, 0xFFFF, sum = 0
7813 12:18:13.460779 14, 0x0, sum = 1
7814 12:18:13.464229 15, 0x0, sum = 2
7815 12:18:13.464319 16, 0x0, sum = 3
7816 12:18:13.467616 17, 0x0, sum = 4
7817 12:18:13.467744 best_step = 15
7818 12:18:13.467836
7819 12:18:13.467924 ==
7820 12:18:13.470543 Dram Type= 6, Freq= 0, CH_0, rank 0
7821 12:18:13.473870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7822 12:18:13.477391 ==
7823 12:18:13.477466 RX Vref Scan: 1
7824 12:18:13.477530
7825 12:18:13.480849 Set Vref Range= 24 -> 127
7826 12:18:13.480922
7827 12:18:13.484232 RX Vref 24 -> 127, step: 1
7828 12:18:13.484340
7829 12:18:13.484437 RX Delay 19 -> 252, step: 4
7830 12:18:13.484526
7831 12:18:13.487477 Set Vref, RX VrefLevel [Byte0]: 24
7832 12:18:13.490698 [Byte1]: 24
7833 12:18:13.494195
7834 12:18:13.494296 Set Vref, RX VrefLevel [Byte0]: 25
7835 12:18:13.497468 [Byte1]: 25
7836 12:18:13.502446
7837 12:18:13.502862 Set Vref, RX VrefLevel [Byte0]: 26
7838 12:18:13.505502 [Byte1]: 26
7839 12:18:13.509878
7840 12:18:13.510294 Set Vref, RX VrefLevel [Byte0]: 27
7841 12:18:13.513387 [Byte1]: 27
7842 12:18:13.517341
7843 12:18:13.520472 Set Vref, RX VrefLevel [Byte0]: 28
7844 12:18:13.523688 [Byte1]: 28
7845 12:18:13.524185
7846 12:18:13.526984 Set Vref, RX VrefLevel [Byte0]: 29
7847 12:18:13.530624 [Byte1]: 29
7848 12:18:13.530734
7849 12:18:13.533628 Set Vref, RX VrefLevel [Byte0]: 30
7850 12:18:13.536923 [Byte1]: 30
7851 12:18:13.537018
7852 12:18:13.540251 Set Vref, RX VrefLevel [Byte0]: 31
7853 12:18:13.543022 [Byte1]: 31
7854 12:18:13.547393
7855 12:18:13.550668 Set Vref, RX VrefLevel [Byte0]: 32
7856 12:18:13.550779 [Byte1]: 32
7857 12:18:13.554841
7858 12:18:13.554981 Set Vref, RX VrefLevel [Byte0]: 33
7859 12:18:13.558346 [Byte1]: 33
7860 12:18:13.562372
7861 12:18:13.562482 Set Vref, RX VrefLevel [Byte0]: 34
7862 12:18:13.565986 [Byte1]: 34
7863 12:18:13.569744
7864 12:18:13.569851 Set Vref, RX VrefLevel [Byte0]: 35
7865 12:18:13.573444 [Byte1]: 35
7866 12:18:13.578048
7867 12:18:13.578128 Set Vref, RX VrefLevel [Byte0]: 36
7868 12:18:13.583989 [Byte1]: 36
7869 12:18:13.584093
7870 12:18:13.587559 Set Vref, RX VrefLevel [Byte0]: 37
7871 12:18:13.590457 [Byte1]: 37
7872 12:18:13.590562
7873 12:18:13.593653 Set Vref, RX VrefLevel [Byte0]: 38
7874 12:18:13.597434 [Byte1]: 38
7875 12:18:13.597536
7876 12:18:13.600200 Set Vref, RX VrefLevel [Byte0]: 39
7877 12:18:13.603657 [Byte1]: 39
7878 12:18:13.607916
7879 12:18:13.608016 Set Vref, RX VrefLevel [Byte0]: 40
7880 12:18:13.610991 [Byte1]: 40
7881 12:18:13.615682
7882 12:18:13.615854 Set Vref, RX VrefLevel [Byte0]: 41
7883 12:18:13.619159 [Byte1]: 41
7884 12:18:13.622915
7885 12:18:13.623013 Set Vref, RX VrefLevel [Byte0]: 42
7886 12:18:13.626237 [Byte1]: 42
7887 12:18:13.630728
7888 12:18:13.630812 Set Vref, RX VrefLevel [Byte0]: 43
7889 12:18:13.633764 [Byte1]: 43
7890 12:18:13.638375
7891 12:18:13.638481 Set Vref, RX VrefLevel [Byte0]: 44
7892 12:18:13.641374 [Byte1]: 44
7893 12:18:13.645850
7894 12:18:13.645954 Set Vref, RX VrefLevel [Byte0]: 45
7895 12:18:13.648788 [Byte1]: 45
7896 12:18:13.653141
7897 12:18:13.653245 Set Vref, RX VrefLevel [Byte0]: 46
7898 12:18:13.656431 [Byte1]: 46
7899 12:18:13.660744
7900 12:18:13.660846 Set Vref, RX VrefLevel [Byte0]: 47
7901 12:18:13.663981 [Byte1]: 47
7902 12:18:13.668328
7903 12:18:13.668431 Set Vref, RX VrefLevel [Byte0]: 48
7904 12:18:13.671854 [Byte1]: 48
7905 12:18:13.675836
7906 12:18:13.675913 Set Vref, RX VrefLevel [Byte0]: 49
7907 12:18:13.682878 [Byte1]: 49
7908 12:18:13.682979
7909 12:18:13.686041 Set Vref, RX VrefLevel [Byte0]: 50
7910 12:18:13.689645 [Byte1]: 50
7911 12:18:13.689754
7912 12:18:13.692474 Set Vref, RX VrefLevel [Byte0]: 51
7913 12:18:13.695698 [Byte1]: 51
7914 12:18:13.698673
7915 12:18:13.698773 Set Vref, RX VrefLevel [Byte0]: 52
7916 12:18:13.702153 [Byte1]: 52
7917 12:18:13.706388
7918 12:18:13.706488 Set Vref, RX VrefLevel [Byte0]: 53
7919 12:18:13.709792 [Byte1]: 53
7920 12:18:13.713975
7921 12:18:13.714074 Set Vref, RX VrefLevel [Byte0]: 54
7922 12:18:13.717156 [Byte1]: 54
7923 12:18:13.721516
7924 12:18:13.721619 Set Vref, RX VrefLevel [Byte0]: 55
7925 12:18:13.724665 [Byte1]: 55
7926 12:18:13.729073
7927 12:18:13.729178 Set Vref, RX VrefLevel [Byte0]: 56
7928 12:18:13.732450 [Byte1]: 56
7929 12:18:13.736422
7930 12:18:13.736494 Set Vref, RX VrefLevel [Byte0]: 57
7931 12:18:13.739713 [Byte1]: 57
7932 12:18:13.744260
7933 12:18:13.744335 Set Vref, RX VrefLevel [Byte0]: 58
7934 12:18:13.747305 [Byte1]: 58
7935 12:18:13.751742
7936 12:18:13.751847 Set Vref, RX VrefLevel [Byte0]: 59
7937 12:18:13.755096 [Byte1]: 59
7938 12:18:13.759532
7939 12:18:13.759635 Set Vref, RX VrefLevel [Byte0]: 60
7940 12:18:13.762518 [Byte1]: 60
7941 12:18:13.766761
7942 12:18:13.766854 Set Vref, RX VrefLevel [Byte0]: 61
7943 12:18:13.770143 [Byte1]: 61
7944 12:18:13.774725
7945 12:18:13.774830 Set Vref, RX VrefLevel [Byte0]: 62
7946 12:18:13.777970 [Byte1]: 62
7947 12:18:13.781924
7948 12:18:13.782028 Set Vref, RX VrefLevel [Byte0]: 63
7949 12:18:13.785334 [Byte1]: 63
7950 12:18:13.790033
7951 12:18:13.790147 Set Vref, RX VrefLevel [Byte0]: 64
7952 12:18:13.792987 [Byte1]: 64
7953 12:18:13.797373
7954 12:18:13.797477 Set Vref, RX VrefLevel [Byte0]: 65
7955 12:18:13.800530 [Byte1]: 65
7956 12:18:13.804792
7957 12:18:13.804900 Set Vref, RX VrefLevel [Byte0]: 66
7958 12:18:13.808248 [Byte1]: 66
7959 12:18:13.812396
7960 12:18:13.812498 Set Vref, RX VrefLevel [Byte0]: 67
7961 12:18:13.815836 [Byte1]: 67
7962 12:18:13.820194
7963 12:18:13.820276 Set Vref, RX VrefLevel [Byte0]: 68
7964 12:18:13.823172 [Byte1]: 68
7965 12:18:13.827518
7966 12:18:13.827623 Set Vref, RX VrefLevel [Byte0]: 69
7967 12:18:13.830596 [Byte1]: 69
7968 12:18:13.834813
7969 12:18:13.834921 Set Vref, RX VrefLevel [Byte0]: 70
7970 12:18:13.838234 [Byte1]: 70
7971 12:18:13.842532
7972 12:18:13.842635 Set Vref, RX VrefLevel [Byte0]: 71
7973 12:18:13.845810 [Byte1]: 71
7974 12:18:13.850688
7975 12:18:13.850769 Set Vref, RX VrefLevel [Byte0]: 72
7976 12:18:13.853542 [Byte1]: 72
7977 12:18:13.857637
7978 12:18:13.857735 Set Vref, RX VrefLevel [Byte0]: 73
7979 12:18:13.860987 [Byte1]: 73
7980 12:18:13.865416
7981 12:18:13.865516 Set Vref, RX VrefLevel [Byte0]: 74
7982 12:18:13.868455 [Byte1]: 74
7983 12:18:13.873241
7984 12:18:13.873320 Set Vref, RX VrefLevel [Byte0]: 75
7985 12:18:13.876464 [Byte1]: 75
7986 12:18:13.880335
7987 12:18:13.880412 Set Vref, RX VrefLevel [Byte0]: 76
7988 12:18:13.883887 [Byte1]: 76
7989 12:18:13.888152
7990 12:18:13.888232 Set Vref, RX VrefLevel [Byte0]: 77
7991 12:18:13.891172 [Byte1]: 77
7992 12:18:13.895446
7993 12:18:13.895549 Set Vref, RX VrefLevel [Byte0]: 78
7994 12:18:13.898678 [Byte1]: 78
7995 12:18:13.903297
7996 12:18:13.903403 Final RX Vref Byte 0 = 63 to rank0
7997 12:18:13.906459 Final RX Vref Byte 1 = 58 to rank0
7998 12:18:13.909695 Final RX Vref Byte 0 = 63 to rank1
7999 12:18:13.913047 Final RX Vref Byte 1 = 58 to rank1==
8000 12:18:13.916296 Dram Type= 6, Freq= 0, CH_0, rank 0
8001 12:18:13.923094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 12:18:13.923200 ==
8003 12:18:13.923294 DQS Delay:
8004 12:18:13.926310 DQS0 = 0, DQS1 = 0
8005 12:18:13.926408 DQM Delay:
8006 12:18:13.926496 DQM0 = 133, DQM1 = 123
8007 12:18:13.929548 DQ Delay:
8008 12:18:13.932718 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8009 12:18:13.935987 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8010 12:18:13.939105 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =118
8011 12:18:13.942581 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8012 12:18:13.942686
8013 12:18:13.942777
8014 12:18:13.942864
8015 12:18:13.946106 [DramC_TX_OE_Calibration] TA2
8016 12:18:13.948972 Original DQ_B0 (3 6) =30, OEN = 27
8017 12:18:13.952351 Original DQ_B1 (3 6) =30, OEN = 27
8018 12:18:13.956060 24, 0x0, End_B0=24 End_B1=24
8019 12:18:13.958808 25, 0x0, End_B0=25 End_B1=25
8020 12:18:13.958909 26, 0x0, End_B0=26 End_B1=26
8021 12:18:13.962006 27, 0x0, End_B0=27 End_B1=27
8022 12:18:13.965431 28, 0x0, End_B0=28 End_B1=28
8023 12:18:13.968875 29, 0x0, End_B0=29 End_B1=29
8024 12:18:13.968978 30, 0x0, End_B0=30 End_B1=30
8025 12:18:13.972533 31, 0x4141, End_B0=30 End_B1=30
8026 12:18:13.975630 Byte0 end_step=30 best_step=27
8027 12:18:13.978566 Byte1 end_step=30 best_step=27
8028 12:18:13.982305 Byte0 TX OE(2T, 0.5T) = (3, 3)
8029 12:18:13.985733 Byte1 TX OE(2T, 0.5T) = (3, 3)
8030 12:18:13.985834
8031 12:18:13.985923
8032 12:18:13.991928 [DQSOSCAuto] RK0, (LSB)MR18= 0x2113, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
8033 12:18:13.995137 CH0 RK0: MR19=303, MR18=2113
8034 12:18:14.002059 CH0_RK0: MR19=0x303, MR18=0x2113, DQSOSC=393, MR23=63, INC=23, DEC=15
8035 12:18:14.002165
8036 12:18:14.005180 ----->DramcWriteLeveling(PI) begin...
8037 12:18:14.005283 ==
8038 12:18:14.008810 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 12:18:14.012106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 12:18:14.012209 ==
8041 12:18:14.015039 Write leveling (Byte 0): 35 => 35
8042 12:18:14.018617 Write leveling (Byte 1): 30 => 30
8043 12:18:14.021592 DramcWriteLeveling(PI) end<-----
8044 12:18:14.021694
8045 12:18:14.021784 ==
8046 12:18:14.024801 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 12:18:14.031828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 12:18:14.031923 ==
8049 12:18:14.032017 [Gating] SW mode calibration
8050 12:18:14.041638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8051 12:18:14.044766 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8052 12:18:14.051229 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 12:18:14.054562 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 12:18:14.057925 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 12:18:14.064420 1 4 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8056 12:18:14.067914 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8057 12:18:14.071358 1 4 20 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
8058 12:18:14.077516 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 12:18:14.080886 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 12:18:14.084223 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 12:18:14.090580 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 12:18:14.093937 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8063 12:18:14.097159 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8064 12:18:14.104026 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8065 12:18:14.107197 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8066 12:18:14.110471 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 12:18:14.116926 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 12:18:14.120391 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 12:18:14.123573 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 12:18:14.130285 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 12:18:14.133717 1 6 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8072 12:18:14.136847 1 6 16 | B1->B0 | 2d2c 4545 | 1 0 | (0 0) (0 0)
8073 12:18:14.143592 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 12:18:14.146753 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 12:18:14.150338 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 12:18:14.156799 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 12:18:14.160248 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 12:18:14.163203 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 12:18:14.169876 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 12:18:14.173247 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8081 12:18:14.176870 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8082 12:18:14.179923 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8083 12:18:14.186489 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 12:18:14.189729 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 12:18:14.193453 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 12:18:14.199553 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 12:18:14.203058 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 12:18:14.206070 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 12:18:14.212958 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 12:18:14.216104 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 12:18:14.223044 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 12:18:14.226122 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 12:18:14.229315 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8094 12:18:14.235889 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8095 12:18:14.238843 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8096 12:18:14.242757 Total UI for P1: 0, mck2ui 16
8097 12:18:14.245774 best dqsien dly found for B0: ( 1, 9, 6)
8098 12:18:14.249235 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8099 12:18:14.255321 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 12:18:14.255428 Total UI for P1: 0, mck2ui 16
8101 12:18:14.259244 best dqsien dly found for B1: ( 1, 9, 16)
8102 12:18:14.262401 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8103 12:18:14.268572 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8104 12:18:14.268683
8105 12:18:14.271892 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8106 12:18:14.275284 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8107 12:18:14.278585 [Gating] SW calibration Done
8108 12:18:14.278684 ==
8109 12:18:14.282034 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 12:18:14.285006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 12:18:14.285104 ==
8112 12:18:14.288511 RX Vref Scan: 0
8113 12:18:14.288607
8114 12:18:14.288696 RX Vref 0 -> 0, step: 1
8115 12:18:14.288785
8116 12:18:14.291662 RX Delay 0 -> 252, step: 8
8117 12:18:14.295088 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8118 12:18:14.301618 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8119 12:18:14.305077 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8120 12:18:14.308323 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8121 12:18:14.311799 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8122 12:18:14.315011 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8123 12:18:14.321717 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8124 12:18:14.324934 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8125 12:18:14.328262 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8126 12:18:14.331508 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8127 12:18:14.334731 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8128 12:18:14.341421 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8129 12:18:14.344652 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8130 12:18:14.348272 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8131 12:18:14.351655 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8132 12:18:14.355067 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8133 12:18:14.358316 ==
8134 12:18:14.361637 Dram Type= 6, Freq= 0, CH_0, rank 1
8135 12:18:14.365461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8136 12:18:14.365956 ==
8137 12:18:14.366272 DQS Delay:
8138 12:18:14.368505 DQS0 = 0, DQS1 = 0
8139 12:18:14.368933 DQM Delay:
8140 12:18:14.371781 DQM0 = 133, DQM1 = 129
8141 12:18:14.372213 DQ Delay:
8142 12:18:14.375255 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8143 12:18:14.378833 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8144 12:18:14.381610 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8145 12:18:14.384917 DQ12 =131, DQ13 =135, DQ14 =143, DQ15 =135
8146 12:18:14.385408
8147 12:18:14.385785
8148 12:18:14.388384 ==
8149 12:18:14.388854 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 12:18:14.394488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 12:18:14.395052 ==
8152 12:18:14.395436
8153 12:18:14.395828
8154 12:18:14.397843 TX Vref Scan disable
8155 12:18:14.398304 == TX Byte 0 ==
8156 12:18:14.401262 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8157 12:18:14.408109 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8158 12:18:14.408587 == TX Byte 1 ==
8159 12:18:14.414651 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8160 12:18:14.417698 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
8161 12:18:14.418225 ==
8162 12:18:14.421103 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 12:18:14.424209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 12:18:14.424630 ==
8165 12:18:14.436855
8166 12:18:14.439788 TX Vref early break, caculate TX vref
8167 12:18:14.443410 TX Vref=16, minBit 0, minWin=23, winSum=383
8168 12:18:14.447015 TX Vref=18, minBit 1, minWin=23, winSum=388
8169 12:18:14.450373 TX Vref=20, minBit 3, minWin=23, winSum=396
8170 12:18:14.453791 TX Vref=22, minBit 1, minWin=24, winSum=408
8171 12:18:14.456384 TX Vref=24, minBit 3, minWin=24, winSum=412
8172 12:18:14.462798 TX Vref=26, minBit 0, minWin=25, winSum=416
8173 12:18:14.466656 TX Vref=28, minBit 1, minWin=24, winSum=414
8174 12:18:14.469873 TX Vref=30, minBit 1, minWin=23, winSum=403
8175 12:18:14.473066 TX Vref=32, minBit 0, minWin=23, winSum=394
8176 12:18:14.479530 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 26
8177 12:18:14.480333
8178 12:18:14.482993 Final TX Range 0 Vref 26
8179 12:18:14.483681
8180 12:18:14.484185 ==
8181 12:18:14.485990 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 12:18:14.489213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 12:18:14.489779 ==
8184 12:18:14.490323
8185 12:18:14.490773
8186 12:18:14.492533 TX Vref Scan disable
8187 12:18:14.499551 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8188 12:18:14.500079 == TX Byte 0 ==
8189 12:18:14.502693 u2DelayCellOfst[0]=15 cells (4 PI)
8190 12:18:14.505862 u2DelayCellOfst[1]=18 cells (5 PI)
8191 12:18:14.509751 u2DelayCellOfst[2]=15 cells (4 PI)
8192 12:18:14.512366 u2DelayCellOfst[3]=15 cells (4 PI)
8193 12:18:14.516111 u2DelayCellOfst[4]=11 cells (3 PI)
8194 12:18:14.519223 u2DelayCellOfst[5]=0 cells (0 PI)
8195 12:18:14.522782 u2DelayCellOfst[6]=22 cells (6 PI)
8196 12:18:14.525978 u2DelayCellOfst[7]=22 cells (6 PI)
8197 12:18:14.529296 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8198 12:18:14.532406 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8199 12:18:14.536120 == TX Byte 1 ==
8200 12:18:14.538792 u2DelayCellOfst[8]=0 cells (0 PI)
8201 12:18:14.539259 u2DelayCellOfst[9]=3 cells (1 PI)
8202 12:18:14.542474 u2DelayCellOfst[10]=7 cells (2 PI)
8203 12:18:14.545914 u2DelayCellOfst[11]=3 cells (1 PI)
8204 12:18:14.548775 u2DelayCellOfst[12]=15 cells (4 PI)
8205 12:18:14.551960 u2DelayCellOfst[13]=15 cells (4 PI)
8206 12:18:14.555444 u2DelayCellOfst[14]=18 cells (5 PI)
8207 12:18:14.559199 u2DelayCellOfst[15]=15 cells (4 PI)
8208 12:18:14.562000 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8209 12:18:14.568603 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8210 12:18:14.569031 DramC Write-DBI on
8211 12:18:14.569366 ==
8212 12:18:14.571841 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 12:18:14.578838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 12:18:14.579397 ==
8215 12:18:14.580060
8216 12:18:14.580399
8217 12:18:14.580709 TX Vref Scan disable
8218 12:18:14.582423 == TX Byte 0 ==
8219 12:18:14.585860 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8220 12:18:14.588909 == TX Byte 1 ==
8221 12:18:14.592279 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8222 12:18:14.595591 DramC Write-DBI off
8223 12:18:14.596040
8224 12:18:14.596382 [DATLAT]
8225 12:18:14.596696 Freq=1600, CH0 RK1
8226 12:18:14.597019
8227 12:18:14.598804 DATLAT Default: 0xf
8228 12:18:14.599232 0, 0xFFFF, sum = 0
8229 12:18:14.602878 1, 0xFFFF, sum = 0
8230 12:18:14.605663 2, 0xFFFF, sum = 0
8231 12:18:14.606103 3, 0xFFFF, sum = 0
8232 12:18:14.608524 4, 0xFFFF, sum = 0
8233 12:18:14.608958 5, 0xFFFF, sum = 0
8234 12:18:14.611940 6, 0xFFFF, sum = 0
8235 12:18:14.612374 7, 0xFFFF, sum = 0
8236 12:18:14.615243 8, 0xFFFF, sum = 0
8237 12:18:14.615675 9, 0xFFFF, sum = 0
8238 12:18:14.618343 10, 0xFFFF, sum = 0
8239 12:18:14.618777 11, 0xFFFF, sum = 0
8240 12:18:14.622421 12, 0xFFFF, sum = 0
8241 12:18:14.623001 13, 0xFFFF, sum = 0
8242 12:18:14.625271 14, 0x0, sum = 1
8243 12:18:14.625752 15, 0x0, sum = 2
8244 12:18:14.628452 16, 0x0, sum = 3
8245 12:18:14.628932 17, 0x0, sum = 4
8246 12:18:14.631851 best_step = 15
8247 12:18:14.632276
8248 12:18:14.632637 ==
8249 12:18:14.635429 Dram Type= 6, Freq= 0, CH_0, rank 1
8250 12:18:14.638610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 12:18:14.639037 ==
8252 12:18:14.641847 RX Vref Scan: 0
8253 12:18:14.642274
8254 12:18:14.642610 RX Vref 0 -> 0, step: 1
8255 12:18:14.642929
8256 12:18:14.644756 RX Delay 11 -> 252, step: 4
8257 12:18:14.651521 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8258 12:18:14.654508 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8259 12:18:14.657993 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8260 12:18:14.661779 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8261 12:18:14.664449 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8262 12:18:14.671050 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8263 12:18:14.674394 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8264 12:18:14.678355 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8265 12:18:14.680952 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8266 12:18:14.687808 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8267 12:18:14.690774 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8268 12:18:14.694013 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8269 12:18:14.697559 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8270 12:18:14.700721 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8271 12:18:14.707469 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8272 12:18:14.710791 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8273 12:18:14.711372 ==
8274 12:18:14.713481 Dram Type= 6, Freq= 0, CH_0, rank 1
8275 12:18:14.717483 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 12:18:14.717912 ==
8277 12:18:14.720706 DQS Delay:
8278 12:18:14.721131 DQS0 = 0, DQS1 = 0
8279 12:18:14.721469 DQM Delay:
8280 12:18:14.723454 DQM0 = 130, DQM1 = 125
8281 12:18:14.723928 DQ Delay:
8282 12:18:14.726745 DQ0 =128, DQ1 =132, DQ2 =126, DQ3 =128
8283 12:18:14.733620 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8284 12:18:14.737088 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8285 12:18:14.740275 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8286 12:18:14.740703
8287 12:18:14.741042
8288 12:18:14.741356
8289 12:18:14.743432 [DramC_TX_OE_Calibration] TA2
8290 12:18:14.747074 Original DQ_B0 (3 6) =30, OEN = 27
8291 12:18:14.750382 Original DQ_B1 (3 6) =30, OEN = 27
8292 12:18:14.750912 24, 0x0, End_B0=24 End_B1=24
8293 12:18:14.753618 25, 0x0, End_B0=25 End_B1=25
8294 12:18:14.757314 26, 0x0, End_B0=26 End_B1=26
8295 12:18:14.760138 27, 0x0, End_B0=27 End_B1=27
8296 12:18:14.760661 28, 0x0, End_B0=28 End_B1=28
8297 12:18:14.763303 29, 0x0, End_B0=29 End_B1=29
8298 12:18:14.766563 30, 0x0, End_B0=30 End_B1=30
8299 12:18:14.769828 31, 0x4141, End_B0=30 End_B1=30
8300 12:18:14.773093 Byte0 end_step=30 best_step=27
8301 12:18:14.776504 Byte1 end_step=30 best_step=27
8302 12:18:14.779779 Byte0 TX OE(2T, 0.5T) = (3, 3)
8303 12:18:14.780206 Byte1 TX OE(2T, 0.5T) = (3, 3)
8304 12:18:14.780561
8305 12:18:14.780880
8306 12:18:14.789445 [DQSOSCAuto] RK1, (LSB)MR18= 0x2104, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
8307 12:18:14.793237 CH0 RK1: MR19=303, MR18=2104
8308 12:18:14.799214 CH0_RK1: MR19=0x303, MR18=0x2104, DQSOSC=393, MR23=63, INC=23, DEC=15
8309 12:18:14.799521 [RxdqsGatingPostProcess] freq 1600
8310 12:18:14.805996 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8311 12:18:14.809317 best DQS0 dly(2T, 0.5T) = (1, 1)
8312 12:18:14.812508 best DQS1 dly(2T, 0.5T) = (1, 1)
8313 12:18:14.815680 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8314 12:18:14.819400 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8315 12:18:14.822792 best DQS0 dly(2T, 0.5T) = (1, 1)
8316 12:18:14.825714 best DQS1 dly(2T, 0.5T) = (1, 1)
8317 12:18:14.829278 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8318 12:18:14.832541 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8319 12:18:14.835457 Pre-setting of DQS Precalculation
8320 12:18:14.839161 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8321 12:18:14.839580 ==
8322 12:18:14.842476 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 12:18:14.845823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 12:18:14.846426 ==
8325 12:18:14.852542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 12:18:14.855287 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 12:18:14.861813 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 12:18:14.865345 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 12:18:14.875969 [CA 0] Center 41 (12~71) winsize 60
8330 12:18:14.879483 [CA 1] Center 41 (12~71) winsize 60
8331 12:18:14.882196 [CA 2] Center 37 (8~66) winsize 59
8332 12:18:14.885779 [CA 3] Center 36 (7~65) winsize 59
8333 12:18:14.888866 [CA 4] Center 37 (7~67) winsize 61
8334 12:18:14.892196 [CA 5] Center 36 (7~65) winsize 59
8335 12:18:14.892660
8336 12:18:14.895482 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8337 12:18:14.896013
8338 12:18:14.899090 [CATrainingPosCal] consider 1 rank data
8339 12:18:14.902156 u2DelayCellTimex100 = 258/100 ps
8340 12:18:14.905547 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8341 12:18:14.912293 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8342 12:18:14.914930 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8343 12:18:14.918521 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8344 12:18:14.922053 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8345 12:18:14.925353 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8346 12:18:14.925888
8347 12:18:14.928319 CA PerBit enable=1, Macro0, CA PI delay=36
8348 12:18:14.928896
8349 12:18:14.931673 [CBTSetCACLKResult] CA Dly = 36
8350 12:18:14.934778 CS Dly: 9 (0~40)
8351 12:18:14.938312 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 12:18:14.941409 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 12:18:14.941835 ==
8354 12:18:14.945047 Dram Type= 6, Freq= 0, CH_1, rank 1
8355 12:18:14.952278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 12:18:14.952864 ==
8357 12:18:14.954535 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8358 12:18:14.958406 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8359 12:18:14.965102 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8360 12:18:14.971346 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8361 12:18:14.978639 [CA 0] Center 42 (12~72) winsize 61
8362 12:18:14.982111 [CA 1] Center 42 (13~72) winsize 60
8363 12:18:14.985241 [CA 2] Center 37 (8~67) winsize 60
8364 12:18:14.988422 [CA 3] Center 37 (8~66) winsize 59
8365 12:18:14.992312 [CA 4] Center 37 (8~67) winsize 60
8366 12:18:14.995285 [CA 5] Center 36 (7~66) winsize 60
8367 12:18:14.995705
8368 12:18:14.998427 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8369 12:18:14.998869
8370 12:18:15.001568 [CATrainingPosCal] consider 2 rank data
8371 12:18:15.004931 u2DelayCellTimex100 = 258/100 ps
8372 12:18:15.011918 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8373 12:18:15.014770 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8374 12:18:15.018705 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8375 12:18:15.021352 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8376 12:18:15.024798 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8377 12:18:15.027923 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8378 12:18:15.028364
8379 12:18:15.031321 CA PerBit enable=1, Macro0, CA PI delay=36
8380 12:18:15.031893
8381 12:18:15.034671 [CBTSetCACLKResult] CA Dly = 36
8382 12:18:15.038672 CS Dly: 10 (0~43)
8383 12:18:15.040975 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8384 12:18:15.044614 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8385 12:18:15.045053
8386 12:18:15.047973 ----->DramcWriteLeveling(PI) begin...
8387 12:18:15.048497 ==
8388 12:18:15.051426 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 12:18:15.058098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 12:18:15.058780 ==
8391 12:18:15.060975 Write leveling (Byte 0): 25 => 25
8392 12:18:15.064356 Write leveling (Byte 1): 28 => 28
8393 12:18:15.067832 DramcWriteLeveling(PI) end<-----
8394 12:18:15.068346
8395 12:18:15.068681 ==
8396 12:18:15.070812 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 12:18:15.074117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 12:18:15.074550 ==
8399 12:18:15.078109 [Gating] SW mode calibration
8400 12:18:15.084117 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8401 12:18:15.087403 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8402 12:18:15.094134 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 12:18:15.097079 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 12:18:15.103819 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 12:18:15.107459 1 4 12 | B1->B0 | 3131 3434 | 0 0 | (1 1) (0 0)
8406 12:18:15.110305 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 12:18:15.113944 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 12:18:15.120455 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 12:18:15.123289 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 12:18:15.129905 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 12:18:15.133293 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 12:18:15.136581 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8413 12:18:15.143682 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (0 1) (1 0)
8414 12:18:15.146547 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 12:18:15.149815 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 12:18:15.156577 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 12:18:15.159831 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 12:18:15.163666 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 12:18:15.170147 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 12:18:15.173420 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 12:18:15.176037 1 6 12 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
8422 12:18:15.183139 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 12:18:15.186336 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 12:18:15.189454 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 12:18:15.196293 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 12:18:15.199604 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 12:18:15.202422 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 12:18:15.209161 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 12:18:15.212410 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8430 12:18:15.215677 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 12:18:15.222710 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 12:18:15.225472 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 12:18:15.228881 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 12:18:15.235385 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 12:18:15.238773 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 12:18:15.242624 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 12:18:15.245412 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 12:18:15.252744 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 12:18:15.255541 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 12:18:15.258612 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 12:18:15.265548 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 12:18:15.268908 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 12:18:15.271921 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 12:18:15.278776 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8445 12:18:15.282341 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8446 12:18:15.285631 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 12:18:15.288410 Total UI for P1: 0, mck2ui 16
8448 12:18:15.292069 best dqsien dly found for B0: ( 1, 9, 10)
8449 12:18:15.295097 Total UI for P1: 0, mck2ui 16
8450 12:18:15.298541 best dqsien dly found for B1: ( 1, 9, 10)
8451 12:18:15.302008 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8452 12:18:15.308201 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8453 12:18:15.308673
8454 12:18:15.311693 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8455 12:18:15.315491 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8456 12:18:15.318454 [Gating] SW calibration Done
8457 12:18:15.319026 ==
8458 12:18:15.321391 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 12:18:15.324859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 12:18:15.325332 ==
8461 12:18:15.328415 RX Vref Scan: 0
8462 12:18:15.328885
8463 12:18:15.329258 RX Vref 0 -> 0, step: 1
8464 12:18:15.329606
8465 12:18:15.331262 RX Delay 0 -> 252, step: 8
8466 12:18:15.335073 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8467 12:18:15.341654 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8468 12:18:15.344730 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8469 12:18:15.348275 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8470 12:18:15.351083 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8471 12:18:15.354655 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8472 12:18:15.361009 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8473 12:18:15.364433 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8474 12:18:15.367611 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8475 12:18:15.370938 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8476 12:18:15.374178 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8477 12:18:15.380667 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8478 12:18:15.384289 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8479 12:18:15.387385 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8480 12:18:15.390718 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8481 12:18:15.397116 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8482 12:18:15.397596 ==
8483 12:18:15.400663 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 12:18:15.403861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 12:18:15.404418 ==
8486 12:18:15.404898 DQS Delay:
8487 12:18:15.407047 DQS0 = 0, DQS1 = 0
8488 12:18:15.407618 DQM Delay:
8489 12:18:15.410343 DQM0 = 138, DQM1 = 131
8490 12:18:15.410768 DQ Delay:
8491 12:18:15.413672 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8492 12:18:15.416882 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8493 12:18:15.420737 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8494 12:18:15.423493 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =143
8495 12:18:15.423988
8496 12:18:15.424336
8497 12:18:15.426714 ==
8498 12:18:15.430363 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 12:18:15.433467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 12:18:15.434072 ==
8501 12:18:15.434650
8502 12:18:15.435135
8503 12:18:15.436819 TX Vref Scan disable
8504 12:18:15.437298 == TX Byte 0 ==
8505 12:18:15.440357 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8506 12:18:15.446861 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8507 12:18:15.447310 == TX Byte 1 ==
8508 12:18:15.453233 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8509 12:18:15.456679 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8510 12:18:15.457108 ==
8511 12:18:15.459933 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 12:18:15.463084 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 12:18:15.463571 ==
8514 12:18:15.476599
8515 12:18:15.479532 TX Vref early break, caculate TX vref
8516 12:18:15.483334 TX Vref=16, minBit 6, minWin=22, winSum=377
8517 12:18:15.486341 TX Vref=18, minBit 6, minWin=22, winSum=383
8518 12:18:15.489848 TX Vref=20, minBit 0, minWin=23, winSum=395
8519 12:18:15.492975 TX Vref=22, minBit 5, minWin=24, winSum=408
8520 12:18:15.496143 TX Vref=24, minBit 0, minWin=25, winSum=415
8521 12:18:15.503616 TX Vref=26, minBit 0, minWin=25, winSum=423
8522 12:18:15.505982 TX Vref=28, minBit 5, minWin=25, winSum=423
8523 12:18:15.509406 TX Vref=30, minBit 0, minWin=25, winSum=413
8524 12:18:15.512831 TX Vref=32, minBit 13, minWin=24, winSum=408
8525 12:18:15.516253 TX Vref=34, minBit 1, minWin=23, winSum=397
8526 12:18:15.522600 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 26
8527 12:18:15.523023
8528 12:18:15.525927 Final TX Range 0 Vref 26
8529 12:18:15.526349
8530 12:18:15.526682 ==
8531 12:18:15.529222 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 12:18:15.532495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 12:18:15.532940 ==
8534 12:18:15.533291
8535 12:18:15.533608
8536 12:18:15.535690 TX Vref Scan disable
8537 12:18:15.542114 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8538 12:18:15.542735 == TX Byte 0 ==
8539 12:18:15.545651 u2DelayCellOfst[0]=18 cells (5 PI)
8540 12:18:15.548839 u2DelayCellOfst[1]=15 cells (4 PI)
8541 12:18:15.552408 u2DelayCellOfst[2]=0 cells (0 PI)
8542 12:18:15.555775 u2DelayCellOfst[3]=7 cells (2 PI)
8543 12:18:15.559510 u2DelayCellOfst[4]=7 cells (2 PI)
8544 12:18:15.562512 u2DelayCellOfst[5]=22 cells (6 PI)
8545 12:18:15.565285 u2DelayCellOfst[6]=22 cells (6 PI)
8546 12:18:15.568831 u2DelayCellOfst[7]=3 cells (1 PI)
8547 12:18:15.572332 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8548 12:18:15.576001 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8549 12:18:15.578884 == TX Byte 1 ==
8550 12:18:15.582029 u2DelayCellOfst[8]=0 cells (0 PI)
8551 12:18:15.582464 u2DelayCellOfst[9]=7 cells (2 PI)
8552 12:18:15.585627 u2DelayCellOfst[10]=15 cells (4 PI)
8553 12:18:15.588505 u2DelayCellOfst[11]=3 cells (1 PI)
8554 12:18:15.591954 u2DelayCellOfst[12]=15 cells (4 PI)
8555 12:18:15.595477 u2DelayCellOfst[13]=18 cells (5 PI)
8556 12:18:15.599075 u2DelayCellOfst[14]=18 cells (5 PI)
8557 12:18:15.602074 u2DelayCellOfst[15]=18 cells (5 PI)
8558 12:18:15.608586 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8559 12:18:15.611450 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8560 12:18:15.612008 DramC Write-DBI on
8561 12:18:15.612369 ==
8562 12:18:15.615256 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 12:18:15.621956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 12:18:15.622464 ==
8565 12:18:15.622851
8566 12:18:15.623245
8567 12:18:15.623623 TX Vref Scan disable
8568 12:18:15.626140 == TX Byte 0 ==
8569 12:18:15.629106 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8570 12:18:15.632436 == TX Byte 1 ==
8571 12:18:15.635775 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8572 12:18:15.639608 DramC Write-DBI off
8573 12:18:15.640349
8574 12:18:15.640747 [DATLAT]
8575 12:18:15.641113 Freq=1600, CH1 RK0
8576 12:18:15.641448
8577 12:18:15.642413 DATLAT Default: 0xf
8578 12:18:15.645556 0, 0xFFFF, sum = 0
8579 12:18:15.646050 1, 0xFFFF, sum = 0
8580 12:18:15.648643 2, 0xFFFF, sum = 0
8581 12:18:15.649135 3, 0xFFFF, sum = 0
8582 12:18:15.652413 4, 0xFFFF, sum = 0
8583 12:18:15.652953 5, 0xFFFF, sum = 0
8584 12:18:15.656018 6, 0xFFFF, sum = 0
8585 12:18:15.656497 7, 0xFFFF, sum = 0
8586 12:18:15.658545 8, 0xFFFF, sum = 0
8587 12:18:15.659081 9, 0xFFFF, sum = 0
8588 12:18:15.662342 10, 0xFFFF, sum = 0
8589 12:18:15.662856 11, 0xFFFF, sum = 0
8590 12:18:15.665178 12, 0xFFFF, sum = 0
8591 12:18:15.665606 13, 0xFFFF, sum = 0
8592 12:18:15.668875 14, 0x0, sum = 1
8593 12:18:15.669469 15, 0x0, sum = 2
8594 12:18:15.671675 16, 0x0, sum = 3
8595 12:18:15.672169 17, 0x0, sum = 4
8596 12:18:15.675312 best_step = 15
8597 12:18:15.675690
8598 12:18:15.676055 ==
8599 12:18:15.678240 Dram Type= 6, Freq= 0, CH_1, rank 0
8600 12:18:15.682061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8601 12:18:15.682585 ==
8602 12:18:15.685271 RX Vref Scan: 1
8603 12:18:15.685694
8604 12:18:15.686029 Set Vref Range= 24 -> 127
8605 12:18:15.686342
8606 12:18:15.688209 RX Vref 24 -> 127, step: 1
8607 12:18:15.688631
8608 12:18:15.691509 RX Delay 19 -> 252, step: 4
8609 12:18:15.691967
8610 12:18:15.694908 Set Vref, RX VrefLevel [Byte0]: 24
8611 12:18:15.698173 [Byte1]: 24
8612 12:18:15.698598
8613 12:18:15.701216 Set Vref, RX VrefLevel [Byte0]: 25
8614 12:18:15.704284 [Byte1]: 25
8615 12:18:15.708446
8616 12:18:15.708961 Set Vref, RX VrefLevel [Byte0]: 26
8617 12:18:15.711624 [Byte1]: 26
8618 12:18:15.716112
8619 12:18:15.716538 Set Vref, RX VrefLevel [Byte0]: 27
8620 12:18:15.719712 [Byte1]: 27
8621 12:18:15.724058
8622 12:18:15.724599 Set Vref, RX VrefLevel [Byte0]: 28
8623 12:18:15.726630 [Byte1]: 28
8624 12:18:15.731275
8625 12:18:15.731761 Set Vref, RX VrefLevel [Byte0]: 29
8626 12:18:15.734618 [Byte1]: 29
8627 12:18:15.738858
8628 12:18:15.738941 Set Vref, RX VrefLevel [Byte0]: 30
8629 12:18:15.741671 [Byte1]: 30
8630 12:18:15.746086
8631 12:18:15.746169 Set Vref, RX VrefLevel [Byte0]: 31
8632 12:18:15.749392 [Byte1]: 31
8633 12:18:15.753648
8634 12:18:15.753814 Set Vref, RX VrefLevel [Byte0]: 32
8635 12:18:15.757183 [Byte1]: 32
8636 12:18:15.761423
8637 12:18:15.761606 Set Vref, RX VrefLevel [Byte0]: 33
8638 12:18:15.764686 [Byte1]: 33
8639 12:18:15.769402
8640 12:18:15.769974 Set Vref, RX VrefLevel [Byte0]: 34
8641 12:18:15.772532 [Byte1]: 34
8642 12:18:15.776392
8643 12:18:15.776859 Set Vref, RX VrefLevel [Byte0]: 35
8644 12:18:15.780178 [Byte1]: 35
8645 12:18:15.784513
8646 12:18:15.785082 Set Vref, RX VrefLevel [Byte0]: 36
8647 12:18:15.787659 [Byte1]: 36
8648 12:18:15.791899
8649 12:18:15.795430 Set Vref, RX VrefLevel [Byte0]: 37
8650 12:18:15.796068 [Byte1]: 37
8651 12:18:15.799143
8652 12:18:15.799706 Set Vref, RX VrefLevel [Byte0]: 38
8653 12:18:15.802436 [Byte1]: 38
8654 12:18:15.807239
8655 12:18:15.807707 Set Vref, RX VrefLevel [Byte0]: 39
8656 12:18:15.809858 [Byte1]: 39
8657 12:18:15.814488
8658 12:18:15.814958 Set Vref, RX VrefLevel [Byte0]: 40
8659 12:18:15.817456 [Byte1]: 40
8660 12:18:15.821947
8661 12:18:15.822414 Set Vref, RX VrefLevel [Byte0]: 41
8662 12:18:15.828571 [Byte1]: 41
8663 12:18:15.829042
8664 12:18:15.831513 Set Vref, RX VrefLevel [Byte0]: 42
8665 12:18:15.835105 [Byte1]: 42
8666 12:18:15.835639
8667 12:18:15.838516 Set Vref, RX VrefLevel [Byte0]: 43
8668 12:18:15.841569 [Byte1]: 43
8669 12:18:15.842102
8670 12:18:15.844862 Set Vref, RX VrefLevel [Byte0]: 44
8671 12:18:15.848261 [Byte1]: 44
8672 12:18:15.852672
8673 12:18:15.853243 Set Vref, RX VrefLevel [Byte0]: 45
8674 12:18:15.855833 [Byte1]: 45
8675 12:18:15.859859
8676 12:18:15.860341 Set Vref, RX VrefLevel [Byte0]: 46
8677 12:18:15.863628 [Byte1]: 46
8678 12:18:15.867295
8679 12:18:15.867774 Set Vref, RX VrefLevel [Byte0]: 47
8680 12:18:15.871146 [Byte1]: 47
8681 12:18:15.875132
8682 12:18:15.875675 Set Vref, RX VrefLevel [Byte0]: 48
8683 12:18:15.878294 [Byte1]: 48
8684 12:18:15.882412
8685 12:18:15.882837 Set Vref, RX VrefLevel [Byte0]: 49
8686 12:18:15.885710 [Byte1]: 49
8687 12:18:15.890159
8688 12:18:15.890583 Set Vref, RX VrefLevel [Byte0]: 50
8689 12:18:15.893511 [Byte1]: 50
8690 12:18:15.897552
8691 12:18:15.897974 Set Vref, RX VrefLevel [Byte0]: 51
8692 12:18:15.900921 [Byte1]: 51
8693 12:18:15.905769
8694 12:18:15.906303 Set Vref, RX VrefLevel [Byte0]: 52
8695 12:18:15.908772 [Byte1]: 52
8696 12:18:15.913269
8697 12:18:15.913994 Set Vref, RX VrefLevel [Byte0]: 53
8698 12:18:15.916082 [Byte1]: 53
8699 12:18:15.920623
8700 12:18:15.921146 Set Vref, RX VrefLevel [Byte0]: 54
8701 12:18:15.923581 [Byte1]: 54
8702 12:18:15.928419
8703 12:18:15.928954 Set Vref, RX VrefLevel [Byte0]: 55
8704 12:18:15.931449 [Byte1]: 55
8705 12:18:15.935785
8706 12:18:15.936214 Set Vref, RX VrefLevel [Byte0]: 56
8707 12:18:15.938937 [Byte1]: 56
8708 12:18:15.943512
8709 12:18:15.944110 Set Vref, RX VrefLevel [Byte0]: 57
8710 12:18:15.946505 [Byte1]: 57
8711 12:18:15.951183
8712 12:18:15.951713 Set Vref, RX VrefLevel [Byte0]: 58
8713 12:18:15.953663 [Byte1]: 58
8714 12:18:15.958170
8715 12:18:15.958713 Set Vref, RX VrefLevel [Byte0]: 59
8716 12:18:15.961710 [Byte1]: 59
8717 12:18:15.965785
8718 12:18:15.966210 Set Vref, RX VrefLevel [Byte0]: 60
8719 12:18:15.969299 [Byte1]: 60
8720 12:18:15.973818
8721 12:18:15.974346 Set Vref, RX VrefLevel [Byte0]: 61
8722 12:18:15.976845 [Byte1]: 61
8723 12:18:15.981056
8724 12:18:15.981616 Set Vref, RX VrefLevel [Byte0]: 62
8725 12:18:15.984317 [Byte1]: 62
8726 12:18:15.988771
8727 12:18:15.989193 Set Vref, RX VrefLevel [Byte0]: 63
8728 12:18:15.992097 [Byte1]: 63
8729 12:18:15.996096
8730 12:18:15.996631 Set Vref, RX VrefLevel [Byte0]: 64
8731 12:18:15.999389 [Byte1]: 64
8732 12:18:16.003586
8733 12:18:16.004060 Set Vref, RX VrefLevel [Byte0]: 65
8734 12:18:16.006879 [Byte1]: 65
8735 12:18:16.011608
8736 12:18:16.012203 Set Vref, RX VrefLevel [Byte0]: 66
8737 12:18:16.014896 [Byte1]: 66
8738 12:18:16.019246
8739 12:18:16.019848 Set Vref, RX VrefLevel [Byte0]: 67
8740 12:18:16.022118 [Byte1]: 67
8741 12:18:16.026270
8742 12:18:16.026696 Set Vref, RX VrefLevel [Byte0]: 68
8743 12:18:16.029638 [Byte1]: 68
8744 12:18:16.033697
8745 12:18:16.034125 Set Vref, RX VrefLevel [Byte0]: 69
8746 12:18:16.037161 [Byte1]: 69
8747 12:18:16.041708
8748 12:18:16.042437 Set Vref, RX VrefLevel [Byte0]: 70
8749 12:18:16.045092 [Byte1]: 70
8750 12:18:16.049244
8751 12:18:16.049670 Set Vref, RX VrefLevel [Byte0]: 71
8752 12:18:16.052734 [Byte1]: 71
8753 12:18:16.057267
8754 12:18:16.057799 Set Vref, RX VrefLevel [Byte0]: 72
8755 12:18:16.060311 [Byte1]: 72
8756 12:18:16.064446
8757 12:18:16.064872 Final RX Vref Byte 0 = 53 to rank0
8758 12:18:16.067768 Final RX Vref Byte 1 = 59 to rank0
8759 12:18:16.070847 Final RX Vref Byte 0 = 53 to rank1
8760 12:18:16.074209 Final RX Vref Byte 1 = 59 to rank1==
8761 12:18:16.077772 Dram Type= 6, Freq= 0, CH_1, rank 0
8762 12:18:16.084313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8763 12:18:16.084834 ==
8764 12:18:16.085176 DQS Delay:
8765 12:18:16.087395 DQS0 = 0, DQS1 = 0
8766 12:18:16.087987 DQM Delay:
8767 12:18:16.088346 DQM0 = 135, DQM1 = 129
8768 12:18:16.090554 DQ Delay:
8769 12:18:16.094207 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8770 12:18:16.096988 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8771 12:18:16.100721 DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =120
8772 12:18:16.103763 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =138
8773 12:18:16.104370
8774 12:18:16.104726
8775 12:18:16.105044
8776 12:18:16.107635 [DramC_TX_OE_Calibration] TA2
8777 12:18:16.111326 Original DQ_B0 (3 6) =30, OEN = 27
8778 12:18:16.113834 Original DQ_B1 (3 6) =30, OEN = 27
8779 12:18:16.116877 24, 0x0, End_B0=24 End_B1=24
8780 12:18:16.117430 25, 0x0, End_B0=25 End_B1=25
8781 12:18:16.120121 26, 0x0, End_B0=26 End_B1=26
8782 12:18:16.123670 27, 0x0, End_B0=27 End_B1=27
8783 12:18:16.126984 28, 0x0, End_B0=28 End_B1=28
8784 12:18:16.130210 29, 0x0, End_B0=29 End_B1=29
8785 12:18:16.130642 30, 0x0, End_B0=30 End_B1=30
8786 12:18:16.133711 31, 0x4141, End_B0=30 End_B1=30
8787 12:18:16.136963 Byte0 end_step=30 best_step=27
8788 12:18:16.140673 Byte1 end_step=30 best_step=27
8789 12:18:16.143832 Byte0 TX OE(2T, 0.5T) = (3, 3)
8790 12:18:16.146941 Byte1 TX OE(2T, 0.5T) = (3, 3)
8791 12:18:16.147635
8792 12:18:16.148053
8793 12:18:16.153650 [DQSOSCAuto] RK0, (LSB)MR18= 0x170d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8794 12:18:16.156642 CH1 RK0: MR19=303, MR18=170D
8795 12:18:16.163649 CH1_RK0: MR19=0x303, MR18=0x170D, DQSOSC=398, MR23=63, INC=23, DEC=15
8796 12:18:16.164220
8797 12:18:16.166523 ----->DramcWriteLeveling(PI) begin...
8798 12:18:16.167151 ==
8799 12:18:16.169820 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 12:18:16.172933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 12:18:16.173386 ==
8802 12:18:16.176219 Write leveling (Byte 0): 25 => 25
8803 12:18:16.179624 Write leveling (Byte 1): 27 => 27
8804 12:18:16.183077 DramcWriteLeveling(PI) end<-----
8805 12:18:16.183505
8806 12:18:16.183891 ==
8807 12:18:16.186217 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 12:18:16.192735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 12:18:16.193167 ==
8810 12:18:16.193509 [Gating] SW mode calibration
8811 12:18:16.202849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8812 12:18:16.205795 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8813 12:18:16.212709 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 12:18:16.215500 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 12:18:16.219357 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 12:18:16.225552 1 4 12 | B1->B0 | 3232 2424 | 0 0 | (0 0) (0 0)
8817 12:18:16.229260 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 12:18:16.231980 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 12:18:16.239173 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 12:18:16.242204 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 12:18:16.245989 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8822 12:18:16.251790 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8823 12:18:16.255193 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8824 12:18:16.258535 1 5 12 | B1->B0 | 2323 3333 | 0 0 | (1 0) (0 1)
8825 12:18:16.265357 1 5 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8826 12:18:16.268392 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 12:18:16.271953 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 12:18:16.278394 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 12:18:16.281941 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 12:18:16.285058 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8831 12:18:16.288621 1 6 8 | B1->B0 | 3535 2323 | 1 0 | (0 0) (0 0)
8832 12:18:16.295535 1 6 12 | B1->B0 | 4646 2525 | 0 0 | (0 0) (0 0)
8833 12:18:16.298546 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 12:18:16.301420 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 12:18:16.308333 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 12:18:16.311233 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 12:18:16.318184 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8838 12:18:16.321385 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 12:18:16.324605 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8840 12:18:16.330664 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8841 12:18:16.334533 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8842 12:18:16.337472 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 12:18:16.344591 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 12:18:16.347691 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 12:18:16.351114 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 12:18:16.357263 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 12:18:16.360769 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 12:18:16.364460 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 12:18:16.370710 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 12:18:16.374027 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 12:18:16.377253 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 12:18:16.383561 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 12:18:16.386799 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 12:18:16.390918 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 12:18:16.396744 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8856 12:18:16.399986 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8857 12:18:16.403462 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 12:18:16.406722 Total UI for P1: 0, mck2ui 16
8859 12:18:16.409924 best dqsien dly found for B0: ( 1, 9, 12)
8860 12:18:16.413020 Total UI for P1: 0, mck2ui 16
8861 12:18:16.417067 best dqsien dly found for B1: ( 1, 9, 10)
8862 12:18:16.420064 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8863 12:18:16.423286 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8864 12:18:16.423710
8865 12:18:16.426821 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8866 12:18:16.433526 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8867 12:18:16.434099 [Gating] SW calibration Done
8868 12:18:16.436594 ==
8869 12:18:16.439686 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 12:18:16.443024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 12:18:16.443563 ==
8872 12:18:16.444003 RX Vref Scan: 0
8873 12:18:16.444352
8874 12:18:16.446576 RX Vref 0 -> 0, step: 1
8875 12:18:16.447184
8876 12:18:16.450095 RX Delay 0 -> 252, step: 8
8877 12:18:16.452930 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8878 12:18:16.456169 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8879 12:18:16.459402 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8880 12:18:16.466167 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8881 12:18:16.469345 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8882 12:18:16.472613 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8883 12:18:16.475888 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8884 12:18:16.479502 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8885 12:18:16.485765 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8886 12:18:16.489157 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8887 12:18:16.492236 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8888 12:18:16.495549 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8889 12:18:16.502191 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8890 12:18:16.505444 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8891 12:18:16.508630 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
8892 12:18:16.511683 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8893 12:18:16.512322 ==
8894 12:18:16.515300 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 12:18:16.521969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 12:18:16.522537 ==
8897 12:18:16.523024 DQS Delay:
8898 12:18:16.525128 DQS0 = 0, DQS1 = 0
8899 12:18:16.525761 DQM Delay:
8900 12:18:16.529025 DQM0 = 136, DQM1 = 130
8901 12:18:16.529450 DQ Delay:
8902 12:18:16.531831 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8903 12:18:16.535144 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8904 12:18:16.538382 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8905 12:18:16.541430 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8906 12:18:16.541857
8907 12:18:16.542196
8908 12:18:16.542510 ==
8909 12:18:16.545147 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 12:18:16.551640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 12:18:16.552223 ==
8912 12:18:16.552571
8913 12:18:16.552887
8914 12:18:16.553190 TX Vref Scan disable
8915 12:18:16.555375 == TX Byte 0 ==
8916 12:18:16.558234 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8917 12:18:16.564860 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8918 12:18:16.565294 == TX Byte 1 ==
8919 12:18:16.568036 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8920 12:18:16.574951 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8921 12:18:16.575490 ==
8922 12:18:16.578279 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 12:18:16.581361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 12:18:16.581972 ==
8925 12:18:16.593964
8926 12:18:16.597522 TX Vref early break, caculate TX vref
8927 12:18:16.600998 TX Vref=16, minBit 1, minWin=23, winSum=391
8928 12:18:16.603833 TX Vref=18, minBit 5, minWin=23, winSum=397
8929 12:18:16.606967 TX Vref=20, minBit 1, minWin=24, winSum=410
8930 12:18:16.610407 TX Vref=22, minBit 1, minWin=25, winSum=416
8931 12:18:16.613588 TX Vref=24, minBit 1, minWin=25, winSum=424
8932 12:18:16.620337 TX Vref=26, minBit 0, minWin=25, winSum=426
8933 12:18:16.623286 TX Vref=28, minBit 0, minWin=25, winSum=429
8934 12:18:16.626942 TX Vref=30, minBit 0, minWin=25, winSum=420
8935 12:18:16.630108 TX Vref=32, minBit 0, minWin=24, winSum=409
8936 12:18:16.633356 TX Vref=34, minBit 0, minWin=23, winSum=401
8937 12:18:16.640490 [TxChooseVref] Worse bit 0, Min win 25, Win sum 429, Final Vref 28
8938 12:18:16.641005
8939 12:18:16.643373 Final TX Range 0 Vref 28
8940 12:18:16.643839
8941 12:18:16.644185 ==
8942 12:18:16.646642 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 12:18:16.649808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 12:18:16.650283 ==
8945 12:18:16.650630
8946 12:18:16.650947
8947 12:18:16.653485 TX Vref Scan disable
8948 12:18:16.660216 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8949 12:18:16.660739 == TX Byte 0 ==
8950 12:18:16.663346 u2DelayCellOfst[0]=22 cells (6 PI)
8951 12:18:16.666199 u2DelayCellOfst[1]=15 cells (4 PI)
8952 12:18:16.669816 u2DelayCellOfst[2]=0 cells (0 PI)
8953 12:18:16.672792 u2DelayCellOfst[3]=7 cells (2 PI)
8954 12:18:16.676705 u2DelayCellOfst[4]=7 cells (2 PI)
8955 12:18:16.679794 u2DelayCellOfst[5]=22 cells (6 PI)
8956 12:18:16.682633 u2DelayCellOfst[6]=22 cells (6 PI)
8957 12:18:16.686412 u2DelayCellOfst[7]=7 cells (2 PI)
8958 12:18:16.689845 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8959 12:18:16.692724 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8960 12:18:16.695856 == TX Byte 1 ==
8961 12:18:16.699187 u2DelayCellOfst[8]=0 cells (0 PI)
8962 12:18:16.702586 u2DelayCellOfst[9]=7 cells (2 PI)
8963 12:18:16.705929 u2DelayCellOfst[10]=15 cells (4 PI)
8964 12:18:16.706357 u2DelayCellOfst[11]=7 cells (2 PI)
8965 12:18:16.709726 u2DelayCellOfst[12]=18 cells (5 PI)
8966 12:18:16.712454 u2DelayCellOfst[13]=18 cells (5 PI)
8967 12:18:16.715894 u2DelayCellOfst[14]=18 cells (5 PI)
8968 12:18:16.718827 u2DelayCellOfst[15]=18 cells (5 PI)
8969 12:18:16.725696 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8970 12:18:16.728973 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8971 12:18:16.729404 DramC Write-DBI on
8972 12:18:16.729742 ==
8973 12:18:16.732204 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 12:18:16.739349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 12:18:16.739911 ==
8976 12:18:16.740256
8977 12:18:16.740570
8978 12:18:16.742416 TX Vref Scan disable
8979 12:18:16.742937 == TX Byte 0 ==
8980 12:18:16.749011 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8981 12:18:16.749441 == TX Byte 1 ==
8982 12:18:16.751871 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8983 12:18:16.755562 DramC Write-DBI off
8984 12:18:16.756034
8985 12:18:16.756394 [DATLAT]
8986 12:18:16.758881 Freq=1600, CH1 RK1
8987 12:18:16.759310
8988 12:18:16.759649 DATLAT Default: 0xf
8989 12:18:16.761922 0, 0xFFFF, sum = 0
8990 12:18:16.762357 1, 0xFFFF, sum = 0
8991 12:18:16.765419 2, 0xFFFF, sum = 0
8992 12:18:16.765943 3, 0xFFFF, sum = 0
8993 12:18:16.768294 4, 0xFFFF, sum = 0
8994 12:18:16.768730 5, 0xFFFF, sum = 0
8995 12:18:16.771887 6, 0xFFFF, sum = 0
8996 12:18:16.772383 7, 0xFFFF, sum = 0
8997 12:18:16.775308 8, 0xFFFF, sum = 0
8998 12:18:16.775783 9, 0xFFFF, sum = 0
8999 12:18:16.778961 10, 0xFFFF, sum = 0
9000 12:18:16.782118 11, 0xFFFF, sum = 0
9001 12:18:16.782643 12, 0xFFFF, sum = 0
9002 12:18:16.785264 13, 0xFFFF, sum = 0
9003 12:18:16.785790 14, 0x0, sum = 1
9004 12:18:16.788596 15, 0x0, sum = 2
9005 12:18:16.789034 16, 0x0, sum = 3
9006 12:18:16.791809 17, 0x0, sum = 4
9007 12:18:16.792261 best_step = 15
9008 12:18:16.792604
9009 12:18:16.792924 ==
9010 12:18:16.795511 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 12:18:16.798576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 12:18:16.799130 ==
9013 12:18:16.801571 RX Vref Scan: 0
9014 12:18:16.802172
9015 12:18:16.804937 RX Vref 0 -> 0, step: 1
9016 12:18:16.805372
9017 12:18:16.805712 RX Delay 11 -> 252, step: 4
9018 12:18:16.811776 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9019 12:18:16.815588 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9020 12:18:16.818353 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9021 12:18:16.821680 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9022 12:18:16.828360 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9023 12:18:16.831717 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9024 12:18:16.835264 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9025 12:18:16.839034 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9026 12:18:16.841444 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9027 12:18:16.847973 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9028 12:18:16.851204 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9029 12:18:16.854899 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9030 12:18:16.858235 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9031 12:18:16.864526 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9032 12:18:16.867558 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9033 12:18:16.871295 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9034 12:18:16.871868 ==
9035 12:18:16.874435 Dram Type= 6, Freq= 0, CH_1, rank 1
9036 12:18:16.877561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9037 12:18:16.878076 ==
9038 12:18:16.881071 DQS Delay:
9039 12:18:16.881488 DQS0 = 0, DQS1 = 0
9040 12:18:16.884221 DQM Delay:
9041 12:18:16.884640 DQM0 = 133, DQM1 = 126
9042 12:18:16.884973 DQ Delay:
9043 12:18:16.890894 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9044 12:18:16.894161 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9045 12:18:16.897590 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9046 12:18:16.900766 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9047 12:18:16.901184
9048 12:18:16.901516
9049 12:18:16.901826
9050 12:18:16.904040 [DramC_TX_OE_Calibration] TA2
9051 12:18:16.907432 Original DQ_B0 (3 6) =30, OEN = 27
9052 12:18:16.910841 Original DQ_B1 (3 6) =30, OEN = 27
9053 12:18:16.911376 24, 0x0, End_B0=24 End_B1=24
9054 12:18:16.914266 25, 0x0, End_B0=25 End_B1=25
9055 12:18:16.917744 26, 0x0, End_B0=26 End_B1=26
9056 12:18:16.920503 27, 0x0, End_B0=27 End_B1=27
9057 12:18:16.924180 28, 0x0, End_B0=28 End_B1=28
9058 12:18:16.924635 29, 0x0, End_B0=29 End_B1=29
9059 12:18:16.927199 30, 0x0, End_B0=30 End_B1=30
9060 12:18:16.930897 31, 0x5151, End_B0=30 End_B1=30
9061 12:18:16.933936 Byte0 end_step=30 best_step=27
9062 12:18:16.937799 Byte1 end_step=30 best_step=27
9063 12:18:16.938318 Byte0 TX OE(2T, 0.5T) = (3, 3)
9064 12:18:16.940674 Byte1 TX OE(2T, 0.5T) = (3, 3)
9065 12:18:16.941105
9066 12:18:16.941443
9067 12:18:16.950988 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
9068 12:18:16.954310 CH1 RK1: MR19=303, MR18=E0A
9069 12:18:16.957350 CH1_RK1: MR19=0x303, MR18=0xE0A, DQSOSC=402, MR23=63, INC=22, DEC=15
9070 12:18:16.960278 [RxdqsGatingPostProcess] freq 1600
9071 12:18:16.966766 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9072 12:18:16.970205 best DQS0 dly(2T, 0.5T) = (1, 1)
9073 12:18:16.973738 best DQS1 dly(2T, 0.5T) = (1, 1)
9074 12:18:16.976856 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9075 12:18:16.980283 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9076 12:18:16.983473 best DQS0 dly(2T, 0.5T) = (1, 1)
9077 12:18:16.987117 best DQS1 dly(2T, 0.5T) = (1, 1)
9078 12:18:16.990183 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9079 12:18:16.993479 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9080 12:18:16.994021 Pre-setting of DQS Precalculation
9081 12:18:16.999868 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9082 12:18:17.006332 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9083 12:18:17.013146 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9084 12:18:17.013711
9085 12:18:17.014062
9086 12:18:17.016478 [Calibration Summary] 3200 Mbps
9087 12:18:17.019977 CH 0, Rank 0
9088 12:18:17.020403 SW Impedance : PASS
9089 12:18:17.022820 DUTY Scan : NO K
9090 12:18:17.026266 ZQ Calibration : PASS
9091 12:18:17.026695 Jitter Meter : NO K
9092 12:18:17.029777 CBT Training : PASS
9093 12:18:17.033532 Write leveling : PASS
9094 12:18:17.034054 RX DQS gating : PASS
9095 12:18:17.036440 RX DQ/DQS(RDDQC) : PASS
9096 12:18:17.039314 TX DQ/DQS : PASS
9097 12:18:17.039904 RX DATLAT : PASS
9098 12:18:17.042902 RX DQ/DQS(Engine): PASS
9099 12:18:17.045937 TX OE : PASS
9100 12:18:17.046368 All Pass.
9101 12:18:17.046707
9102 12:18:17.047021 CH 0, Rank 1
9103 12:18:17.049375 SW Impedance : PASS
9104 12:18:17.052350 DUTY Scan : NO K
9105 12:18:17.052777 ZQ Calibration : PASS
9106 12:18:17.055971 Jitter Meter : NO K
9107 12:18:17.059213 CBT Training : PASS
9108 12:18:17.059640 Write leveling : PASS
9109 12:18:17.062494 RX DQS gating : PASS
9110 12:18:17.062970 RX DQ/DQS(RDDQC) : PASS
9111 12:18:17.065798 TX DQ/DQS : PASS
9112 12:18:17.069283 RX DATLAT : PASS
9113 12:18:17.069712 RX DQ/DQS(Engine): PASS
9114 12:18:17.072705 TX OE : PASS
9115 12:18:17.073229 All Pass.
9116 12:18:17.073570
9117 12:18:17.075880 CH 1, Rank 0
9118 12:18:17.076344 SW Impedance : PASS
9119 12:18:17.078636 DUTY Scan : NO K
9120 12:18:17.082243 ZQ Calibration : PASS
9121 12:18:17.082762 Jitter Meter : NO K
9122 12:18:17.085410 CBT Training : PASS
9123 12:18:17.088832 Write leveling : PASS
9124 12:18:17.089261 RX DQS gating : PASS
9125 12:18:17.092516 RX DQ/DQS(RDDQC) : PASS
9126 12:18:17.095614 TX DQ/DQS : PASS
9127 12:18:17.096220 RX DATLAT : PASS
9128 12:18:17.098879 RX DQ/DQS(Engine): PASS
9129 12:18:17.102313 TX OE : PASS
9130 12:18:17.102838 All Pass.
9131 12:18:17.103238
9132 12:18:17.103789 CH 1, Rank 1
9133 12:18:17.105388 SW Impedance : PASS
9134 12:18:17.108386 DUTY Scan : NO K
9135 12:18:17.109036 ZQ Calibration : PASS
9136 12:18:17.111888 Jitter Meter : NO K
9137 12:18:17.115056 CBT Training : PASS
9138 12:18:17.115484 Write leveling : PASS
9139 12:18:17.118356 RX DQS gating : PASS
9140 12:18:17.121616 RX DQ/DQS(RDDQC) : PASS
9141 12:18:17.122043 TX DQ/DQS : PASS
9142 12:18:17.124932 RX DATLAT : PASS
9143 12:18:17.128199 RX DQ/DQS(Engine): PASS
9144 12:18:17.128623 TX OE : PASS
9145 12:18:17.128965 All Pass.
9146 12:18:17.131604
9147 12:18:17.132185 DramC Write-DBI on
9148 12:18:17.134862 PER_BANK_REFRESH: Hybrid Mode
9149 12:18:17.135382 TX_TRACKING: ON
9150 12:18:17.145255 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9151 12:18:17.151559 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9152 12:18:17.161644 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9153 12:18:17.164427 [FAST_K] Save calibration result to emmc
9154 12:18:17.168270 sync common calibartion params.
9155 12:18:17.168699 sync cbt_mode0:1, 1:1
9156 12:18:17.171240 dram_init: ddr_geometry: 2
9157 12:18:17.174396 dram_init: ddr_geometry: 2
9158 12:18:17.174921 dram_init: ddr_geometry: 2
9159 12:18:17.177972 0:dram_rank_size:100000000
9160 12:18:17.181062 1:dram_rank_size:100000000
9161 12:18:17.187301 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9162 12:18:17.187773 DFS_SHUFFLE_HW_MODE: ON
9163 12:18:17.190855 dramc_set_vcore_voltage set vcore to 725000
9164 12:18:17.194202 Read voltage for 1600, 0
9165 12:18:17.194778 Vio18 = 0
9166 12:18:17.197365 Vcore = 725000
9167 12:18:17.197795 Vdram = 0
9168 12:18:17.198136 Vddq = 0
9169 12:18:17.200561 Vmddr = 0
9170 12:18:17.200989 switch to 3200 Mbps bootup
9171 12:18:17.204264 [DramcRunTimeConfig]
9172 12:18:17.204718 PHYPLL
9173 12:18:17.207382 DPM_CONTROL_AFTERK: ON
9174 12:18:17.207969 PER_BANK_REFRESH: ON
9175 12:18:17.210378 REFRESH_OVERHEAD_REDUCTION: ON
9176 12:18:17.214038 CMD_PICG_NEW_MODE: OFF
9177 12:18:17.214558 XRTWTW_NEW_MODE: ON
9178 12:18:17.217667 XRTRTR_NEW_MODE: ON
9179 12:18:17.218194 TX_TRACKING: ON
9180 12:18:17.220572 RDSEL_TRACKING: OFF
9181 12:18:17.223883 DQS Precalculation for DVFS: ON
9182 12:18:17.224371 RX_TRACKING: OFF
9183 12:18:17.227224 HW_GATING DBG: ON
9184 12:18:17.227649 ZQCS_ENABLE_LP4: ON
9185 12:18:17.230513 RX_PICG_NEW_MODE: ON
9186 12:18:17.230938 TX_PICG_NEW_MODE: ON
9187 12:18:17.233686 ENABLE_RX_DCM_DPHY: ON
9188 12:18:17.237067 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9189 12:18:17.240666 DUMMY_READ_FOR_TRACKING: OFF
9190 12:18:17.243493 !!! SPM_CONTROL_AFTERK: OFF
9191 12:18:17.243979 !!! SPM could not control APHY
9192 12:18:17.246709 IMPEDANCE_TRACKING: ON
9193 12:18:17.247134 TEMP_SENSOR: ON
9194 12:18:17.250536 HW_SAVE_FOR_SR: OFF
9195 12:18:17.253838 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9196 12:18:17.256778 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9197 12:18:17.260287 Read ODT Tracking: ON
9198 12:18:17.260852 Refresh Rate DeBounce: ON
9199 12:18:17.263799 DFS_NO_QUEUE_FLUSH: ON
9200 12:18:17.267062 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9201 12:18:17.269946 ENABLE_DFS_RUNTIME_MRW: OFF
9202 12:18:17.270482 DDR_RESERVE_NEW_MODE: ON
9203 12:18:17.273436 MR_CBT_SWITCH_FREQ: ON
9204 12:18:17.276935 =========================
9205 12:18:17.294973 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9206 12:18:17.298406 dram_init: ddr_geometry: 2
9207 12:18:17.316250 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9208 12:18:17.319545 dram_init: dram init end (result: 0)
9209 12:18:17.326042 DRAM-K: Full calibration passed in 24633 msecs
9210 12:18:17.329444 MRC: failed to locate region type 0.
9211 12:18:17.330099 DRAM rank0 size:0x100000000,
9212 12:18:17.332757 DRAM rank1 size=0x100000000
9213 12:18:17.342284 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9214 12:18:17.349003 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9215 12:18:17.355958 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9216 12:18:17.365816 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9217 12:18:17.366240 DRAM rank0 size:0x100000000,
9218 12:18:17.369014 DRAM rank1 size=0x100000000
9219 12:18:17.369463 CBMEM:
9220 12:18:17.372350 IMD: root @ 0xfffff000 254 entries.
9221 12:18:17.375812 IMD: root @ 0xffffec00 62 entries.
9222 12:18:17.378766 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9223 12:18:17.385339 WARNING: RO_VPD is uninitialized or empty.
9224 12:18:17.388935 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9225 12:18:17.396346 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9226 12:18:17.408990 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9227 12:18:17.419893 BS: romstage times (exec / console): total (unknown) / 24127 ms
9228 12:18:17.420539
9229 12:18:17.421069
9230 12:18:17.429802 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9231 12:18:17.433680 ARM64: Exception handlers installed.
9232 12:18:17.436940 ARM64: Testing exception
9233 12:18:17.439834 ARM64: Done test exception
9234 12:18:17.440273 Enumerating buses...
9235 12:18:17.442916 Show all devs... Before device enumeration.
9236 12:18:17.446608 Root Device: enabled 1
9237 12:18:17.450064 CPU_CLUSTER: 0: enabled 1
9238 12:18:17.450593 CPU: 00: enabled 1
9239 12:18:17.453225 Compare with tree...
9240 12:18:17.453743 Root Device: enabled 1
9241 12:18:17.456216 CPU_CLUSTER: 0: enabled 1
9242 12:18:17.459854 CPU: 00: enabled 1
9243 12:18:17.460437 Root Device scanning...
9244 12:18:17.462959 scan_static_bus for Root Device
9245 12:18:17.466318 CPU_CLUSTER: 0 enabled
9246 12:18:17.469401 scan_static_bus for Root Device done
9247 12:18:17.473277 scan_bus: bus Root Device finished in 8 msecs
9248 12:18:17.473793 done
9249 12:18:17.479916 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9250 12:18:17.482373 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9251 12:18:17.489600 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9252 12:18:17.495670 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9253 12:18:17.496136 Allocating resources...
9254 12:18:17.499129 Reading resources...
9255 12:18:17.502305 Root Device read_resources bus 0 link: 0
9256 12:18:17.505781 DRAM rank0 size:0x100000000,
9257 12:18:17.506235 DRAM rank1 size=0x100000000
9258 12:18:17.512343 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9259 12:18:17.512857 CPU: 00 missing read_resources
9260 12:18:17.519196 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9261 12:18:17.522442 Root Device read_resources bus 0 link: 0 done
9262 12:18:17.525458 Done reading resources.
9263 12:18:17.528754 Show resources in subtree (Root Device)...After reading.
9264 12:18:17.532245 Root Device child on link 0 CPU_CLUSTER: 0
9265 12:18:17.535754 CPU_CLUSTER: 0 child on link 0 CPU: 00
9266 12:18:17.545294 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9267 12:18:17.546087 CPU: 00
9268 12:18:17.551646 Root Device assign_resources, bus 0 link: 0
9269 12:18:17.555616 CPU_CLUSTER: 0 missing set_resources
9270 12:18:17.558717 Root Device assign_resources, bus 0 link: 0 done
9271 12:18:17.559253 Done setting resources.
9272 12:18:17.565271 Show resources in subtree (Root Device)...After assigning values.
9273 12:18:17.568706 Root Device child on link 0 CPU_CLUSTER: 0
9274 12:18:17.575174 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 12:18:17.582043 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 12:18:17.582601 CPU: 00
9277 12:18:17.585111 Done allocating resources.
9278 12:18:17.591853 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9279 12:18:17.592380 Enabling resources...
9280 12:18:17.594815 done.
9281 12:18:17.598067 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9282 12:18:17.601896 Initializing devices...
9283 12:18:17.602413 Root Device init
9284 12:18:17.604879 init hardware done!
9285 12:18:17.605294 0x00000018: ctrlr->caps
9286 12:18:17.608096 52.000 MHz: ctrlr->f_max
9287 12:18:17.611715 0.400 MHz: ctrlr->f_min
9288 12:18:17.614798 0x40ff8080: ctrlr->voltages
9289 12:18:17.615328 sclk: 390625
9290 12:18:17.615665 Bus Width = 1
9291 12:18:17.618033 sclk: 390625
9292 12:18:17.618551 Bus Width = 1
9293 12:18:17.620924 Early init status = 3
9294 12:18:17.624430 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9295 12:18:17.627607 in-header: 03 fc 00 00 01 00 00 00
9296 12:18:17.631047 in-data: 00
9297 12:18:17.634584 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9298 12:18:17.638860 in-header: 03 fd 00 00 00 00 00 00
9299 12:18:17.642236 in-data:
9300 12:18:17.645361 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9301 12:18:17.649050 in-header: 03 fc 00 00 01 00 00 00
9302 12:18:17.652291 in-data: 00
9303 12:18:17.655758 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9304 12:18:17.660442 in-header: 03 fd 00 00 00 00 00 00
9305 12:18:17.663513 in-data:
9306 12:18:17.666844 [SSUSB] Setting up USB HOST controller...
9307 12:18:17.670269 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9308 12:18:17.673303 [SSUSB] phy power-on done.
9309 12:18:17.676802 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9310 12:18:17.683336 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9311 12:18:17.686989 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9312 12:18:17.693513 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9313 12:18:17.700135 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9314 12:18:17.706181 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9315 12:18:17.713232 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9316 12:18:17.720149 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9317 12:18:17.722965 SPM: binary array size = 0x9dc
9318 12:18:17.726688 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9319 12:18:17.733347 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9320 12:18:17.740692 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9321 12:18:17.746595 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9322 12:18:17.749297 configure_display: Starting display init
9323 12:18:17.784040 anx7625_power_on_init: Init interface.
9324 12:18:17.787111 anx7625_disable_pd_protocol: Disabled PD feature.
9325 12:18:17.790221 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9326 12:18:17.818136 anx7625_start_dp_work: Secure OCM version=00
9327 12:18:17.821418 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9328 12:18:17.836291 sp_tx_get_edid_block: EDID Block = 1
9329 12:18:17.938725 Extracted contents:
9330 12:18:17.941866 header: 00 ff ff ff ff ff ff 00
9331 12:18:17.945204 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9332 12:18:17.948494 version: 01 04
9333 12:18:17.951908 basic params: 95 1f 11 78 0a
9334 12:18:17.954887 chroma info: 76 90 94 55 54 90 27 21 50 54
9335 12:18:17.958414 established: 00 00 00
9336 12:18:17.964970 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9337 12:18:17.971312 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9338 12:18:17.975035 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9339 12:18:17.981941 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9340 12:18:17.988327 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9341 12:18:17.991372 extensions: 00
9342 12:18:17.992030 checksum: fb
9343 12:18:17.992582
9344 12:18:17.998287 Manufacturer: IVO Model 57d Serial Number 0
9345 12:18:17.998753 Made week 0 of 2020
9346 12:18:18.001238 EDID version: 1.4
9347 12:18:18.001777 Digital display
9348 12:18:18.004595 6 bits per primary color channel
9349 12:18:18.005106 DisplayPort interface
9350 12:18:18.008047 Maximum image size: 31 cm x 17 cm
9351 12:18:18.011247 Gamma: 220%
9352 12:18:18.011671 Check DPMS levels
9353 12:18:18.017993 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9354 12:18:18.020935 First detailed timing is preferred timing
9355 12:18:18.021414 Established timings supported:
9356 12:18:18.024623 Standard timings supported:
9357 12:18:18.027494 Detailed timings
9358 12:18:18.031126 Hex of detail: 383680a07038204018303c0035ae10000019
9359 12:18:18.037162 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9360 12:18:18.040631 0780 0798 07c8 0820 hborder 0
9361 12:18:18.044298 0438 043b 0447 0458 vborder 0
9362 12:18:18.047772 -hsync -vsync
9363 12:18:18.048200 Did detailed timing
9364 12:18:18.054184 Hex of detail: 000000000000000000000000000000000000
9365 12:18:18.057493 Manufacturer-specified data, tag 0
9366 12:18:18.060608 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9367 12:18:18.063671 ASCII string: InfoVision
9368 12:18:18.067000 Hex of detail: 000000fe00523134304e574635205248200a
9369 12:18:18.070441 ASCII string: R140NWF5 RH
9370 12:18:18.070863 Checksum
9371 12:18:18.073721 Checksum: 0xfb (valid)
9372 12:18:18.077395 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9373 12:18:18.080316 DSI data_rate: 832800000 bps
9374 12:18:18.086825 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9375 12:18:18.090682 anx7625_parse_edid: pixelclock(138800).
9376 12:18:18.093462 hactive(1920), hsync(48), hfp(24), hbp(88)
9377 12:18:18.096574 vactive(1080), vsync(12), vfp(3), vbp(17)
9378 12:18:18.100235 anx7625_dsi_config: config dsi.
9379 12:18:18.106362 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9380 12:18:18.121028 anx7625_dsi_config: success to config DSI
9381 12:18:18.124334 anx7625_dp_start: MIPI phy setup OK.
9382 12:18:18.127141 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9383 12:18:18.130755 mtk_ddp_mode_set invalid vrefresh 60
9384 12:18:18.134016 main_disp_path_setup
9385 12:18:18.134484 ovl_layer_smi_id_en
9386 12:18:18.137000 ovl_layer_smi_id_en
9387 12:18:18.137469 ccorr_config
9388 12:18:18.137900 aal_config
9389 12:18:18.140316 gamma_config
9390 12:18:18.140741 postmask_config
9391 12:18:18.143610 dither_config
9392 12:18:18.147361 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9393 12:18:18.154155 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9394 12:18:18.157280 Root Device init finished in 551 msecs
9395 12:18:18.160598 CPU_CLUSTER: 0 init
9396 12:18:18.166772 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9397 12:18:18.173795 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9398 12:18:18.174366 APU_MBOX 0x190000b0 = 0x10001
9399 12:18:18.176457 APU_MBOX 0x190001b0 = 0x10001
9400 12:18:18.180213 APU_MBOX 0x190005b0 = 0x10001
9401 12:18:18.183159 APU_MBOX 0x190006b0 = 0x10001
9402 12:18:18.189851 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9403 12:18:18.199472 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9404 12:18:18.212335 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9405 12:18:18.218987 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9406 12:18:18.230572 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9407 12:18:18.239834 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9408 12:18:18.243381 CPU_CLUSTER: 0 init finished in 81 msecs
9409 12:18:18.246450 Devices initialized
9410 12:18:18.249690 Show all devs... After init.
9411 12:18:18.250164 Root Device: enabled 1
9412 12:18:18.252648 CPU_CLUSTER: 0: enabled 1
9413 12:18:18.255973 CPU: 00: enabled 1
9414 12:18:18.259506 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9415 12:18:18.262931 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9416 12:18:18.265837 ELOG: NV offset 0x57f000 size 0x1000
9417 12:18:18.272491 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9418 12:18:18.280141 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9419 12:18:18.282829 ELOG: Event(17) added with size 13 at 2023-10-27 12:18:18 UTC
9420 12:18:18.288806 out: cmd=0x121: 03 db 21 01 00 00 00 00
9421 12:18:18.292539 in-header: 03 bd 00 00 2c 00 00 00
9422 12:18:18.302428 in-data: a2 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9423 12:18:18.308982 ELOG: Event(A1) added with size 10 at 2023-10-27 12:18:18 UTC
9424 12:18:18.315325 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9425 12:18:18.322260 ELOG: Event(A0) added with size 9 at 2023-10-27 12:18:18 UTC
9426 12:18:18.325507 elog_add_boot_reason: Logged dev mode boot
9427 12:18:18.332102 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9428 12:18:18.332627 Finalize devices...
9429 12:18:18.335371 Devices finalized
9430 12:18:18.338467 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9431 12:18:18.341864 Writing coreboot table at 0xffe64000
9432 12:18:18.345219 0. 000000000010a000-0000000000113fff: RAMSTAGE
9433 12:18:18.351897 1. 0000000040000000-00000000400fffff: RAM
9434 12:18:18.355385 2. 0000000040100000-000000004032afff: RAMSTAGE
9435 12:18:18.358063 3. 000000004032b000-00000000545fffff: RAM
9436 12:18:18.361479 4. 0000000054600000-000000005465ffff: BL31
9437 12:18:18.365108 5. 0000000054660000-00000000ffe63fff: RAM
9438 12:18:18.371865 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9439 12:18:18.374624 7. 0000000100000000-000000023fffffff: RAM
9440 12:18:18.378037 Passing 5 GPIOs to payload:
9441 12:18:18.381708 NAME | PORT | POLARITY | VALUE
9442 12:18:18.388264 EC in RW | 0x000000aa | low | undefined
9443 12:18:18.391509 EC interrupt | 0x00000005 | low | undefined
9444 12:18:18.394565 TPM interrupt | 0x000000ab | high | undefined
9445 12:18:18.401109 SD card detect | 0x00000011 | high | undefined
9446 12:18:18.404430 speaker enable | 0x00000093 | high | undefined
9447 12:18:18.407797 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9448 12:18:18.411073 in-header: 03 f9 00 00 02 00 00 00
9449 12:18:18.414593 in-data: 02 00
9450 12:18:18.418262 ADC[4]: Raw value=903770 ID=7
9451 12:18:18.420802 ADC[3]: Raw value=213652 ID=1
9452 12:18:18.421221 RAM Code: 0x71
9453 12:18:18.424644 ADC[6]: Raw value=75036 ID=0
9454 12:18:18.427850 ADC[5]: Raw value=213282 ID=1
9455 12:18:18.428491 SKU Code: 0x1
9456 12:18:18.433928 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a169
9457 12:18:18.434386 coreboot table: 964 bytes.
9458 12:18:18.437388 IMD ROOT 0. 0xfffff000 0x00001000
9459 12:18:18.440990 IMD SMALL 1. 0xffffe000 0x00001000
9460 12:18:18.444190 RO MCACHE 2. 0xffffc000 0x00001104
9461 12:18:18.447217 CONSOLE 3. 0xfff7c000 0x00080000
9462 12:18:18.450625 FMAP 4. 0xfff7b000 0x00000452
9463 12:18:18.454187 TIME STAMP 5. 0xfff7a000 0x00000910
9464 12:18:18.457183 VBOOT WORK 6. 0xfff66000 0x00014000
9465 12:18:18.460299 RAMOOPS 7. 0xffe66000 0x00100000
9466 12:18:18.463931 COREBOOT 8. 0xffe64000 0x00002000
9467 12:18:18.467380 IMD small region:
9468 12:18:18.470446 IMD ROOT 0. 0xffffec00 0x00000400
9469 12:18:18.473507 VPD 1. 0xffffeb80 0x0000006c
9470 12:18:18.477196 MMC STATUS 2. 0xffffeb60 0x00000004
9471 12:18:18.483548 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9472 12:18:18.484043 Probing TPM: done!
9473 12:18:18.490946 Connected to device vid:did:rid of 1ae0:0028:00
9474 12:18:18.496825 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9475 12:18:18.499995 Initialized TPM device CR50 revision 0
9476 12:18:18.503816 Checking cr50 for pending updates
9477 12:18:18.509409 Reading cr50 TPM mode
9478 12:18:18.517838 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9479 12:18:18.524774 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9480 12:18:18.564565 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9481 12:18:18.567783 Checking segment from ROM address 0x40100000
9482 12:18:18.574302 Checking segment from ROM address 0x4010001c
9483 12:18:18.577566 Loading segment from ROM address 0x40100000
9484 12:18:18.578061 code (compression=0)
9485 12:18:18.588078 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9486 12:18:18.594187 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9487 12:18:18.597568 it's not compressed!
9488 12:18:18.601101 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9489 12:18:18.607253 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9490 12:18:18.624754 Loading segment from ROM address 0x4010001c
9491 12:18:18.625328 Entry Point 0x80000000
9492 12:18:18.628517 Loaded segments
9493 12:18:18.631543 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9494 12:18:18.638247 Jumping to boot code at 0x80000000(0xffe64000)
9495 12:18:18.644769 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9496 12:18:18.651313 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9497 12:18:18.659673 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9498 12:18:18.662815 Checking segment from ROM address 0x40100000
9499 12:18:18.665820 Checking segment from ROM address 0x4010001c
9500 12:18:18.672507 Loading segment from ROM address 0x40100000
9501 12:18:18.672950 code (compression=1)
9502 12:18:18.679507 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9503 12:18:18.689454 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9504 12:18:18.689963 using LZMA
9505 12:18:18.698024 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9506 12:18:18.704342 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9507 12:18:18.707836 Loading segment from ROM address 0x4010001c
9508 12:18:18.708256 Entry Point 0x54601000
9509 12:18:18.711154 Loaded segments
9510 12:18:18.714497 NOTICE: MT8192 bl31_setup
9511 12:18:18.721487 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9512 12:18:18.725012 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9513 12:18:18.727898 WARNING: region 0:
9514 12:18:18.731602 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 12:18:18.732072 WARNING: region 1:
9516 12:18:18.737844 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9517 12:18:18.741233 WARNING: region 2:
9518 12:18:18.744665 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9519 12:18:18.748853 WARNING: region 3:
9520 12:18:18.751466 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 12:18:18.754923 WARNING: region 4:
9522 12:18:18.761662 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9523 12:18:18.762271 WARNING: region 5:
9524 12:18:18.764428 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 12:18:18.768017 WARNING: region 6:
9526 12:18:18.771126 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 12:18:18.775304 WARNING: region 7:
9528 12:18:18.778022 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 12:18:18.784291 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9530 12:18:18.787597 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9531 12:18:18.791144 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9532 12:18:18.797459 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9533 12:18:18.800890 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9534 12:18:18.807332 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9535 12:18:18.811289 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9536 12:18:18.814575 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9537 12:18:18.820921 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9538 12:18:18.824287 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9539 12:18:18.830950 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9540 12:18:18.834167 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9541 12:18:18.837571 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9542 12:18:18.843955 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9543 12:18:18.847052 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9544 12:18:18.850518 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9545 12:18:18.857176 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9546 12:18:18.860511 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9547 12:18:18.867131 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9548 12:18:18.870585 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9549 12:18:18.874177 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9550 12:18:18.880841 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9551 12:18:18.883675 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9552 12:18:18.887021 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9553 12:18:18.893985 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9554 12:18:18.897035 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9555 12:18:18.903671 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9556 12:18:18.906990 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9557 12:18:18.913430 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9558 12:18:18.917066 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9559 12:18:18.920293 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9560 12:18:18.926979 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9561 12:18:18.930138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9562 12:18:18.933755 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9563 12:18:18.937237 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9564 12:18:18.943168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9565 12:18:18.946521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9566 12:18:18.949835 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9567 12:18:18.953216 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9568 12:18:18.960049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9569 12:18:18.963391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9570 12:18:18.966852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9571 12:18:18.970040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9572 12:18:18.976513 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9573 12:18:18.980026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9574 12:18:18.983100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9575 12:18:18.990007 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9576 12:18:18.993437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9577 12:18:18.996513 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9578 12:18:19.003585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9579 12:18:19.006840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9580 12:18:19.009702 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9581 12:18:19.016443 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9582 12:18:19.019769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9583 12:18:19.026549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9584 12:18:19.029851 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9585 12:18:19.036391 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9586 12:18:19.039990 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9587 12:18:19.043252 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9588 12:18:19.049707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9589 12:18:19.053014 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9590 12:18:19.060128 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9591 12:18:19.063779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9592 12:18:19.070375 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9593 12:18:19.073182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9594 12:18:19.079927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9595 12:18:19.083476 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9596 12:18:19.086507 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9597 12:18:19.093192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9598 12:18:19.096482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9599 12:18:19.103177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9600 12:18:19.106553 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9601 12:18:19.113075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9602 12:18:19.116426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9603 12:18:19.119908 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9604 12:18:19.126388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9605 12:18:19.129764 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9606 12:18:19.136242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9607 12:18:19.140288 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9608 12:18:19.146009 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9609 12:18:19.149406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9610 12:18:19.155947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9611 12:18:19.159103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9612 12:18:19.162976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9613 12:18:19.169156 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9614 12:18:19.172287 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9615 12:18:19.179443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9616 12:18:19.182594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9617 12:18:19.189539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9618 12:18:19.192256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9619 12:18:19.195834 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9620 12:18:19.202552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9621 12:18:19.205782 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9622 12:18:19.212372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9623 12:18:19.215544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9624 12:18:19.222106 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9625 12:18:19.225462 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9626 12:18:19.228956 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9627 12:18:19.232286 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9628 12:18:19.238889 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9629 12:18:19.242271 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9630 12:18:19.245632 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9631 12:18:19.252406 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9632 12:18:19.255384 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9633 12:18:19.262398 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9634 12:18:19.265662 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9635 12:18:19.269061 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9636 12:18:19.275923 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9637 12:18:19.279063 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9638 12:18:19.285883 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9639 12:18:19.289080 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9640 12:18:19.292136 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9641 12:18:19.298953 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9642 12:18:19.302224 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9643 12:18:19.308499 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9644 12:18:19.311812 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9645 12:18:19.315616 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9646 12:18:19.322319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9647 12:18:19.325922 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9648 12:18:19.328349 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9649 12:18:19.332093 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9650 12:18:19.338269 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9651 12:18:19.341837 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9652 12:18:19.345673 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9653 12:18:19.351988 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9654 12:18:19.355510 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9655 12:18:19.358295 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9656 12:18:19.365743 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9657 12:18:19.368656 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9658 12:18:19.375214 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9659 12:18:19.378137 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9660 12:18:19.381839 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9661 12:18:19.388684 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9662 12:18:19.391308 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9663 12:18:19.398503 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9664 12:18:19.401703 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9665 12:18:19.404809 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9666 12:18:19.411314 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9667 12:18:19.414825 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9668 12:18:19.418506 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9669 12:18:19.424577 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9670 12:18:19.427846 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9671 12:18:19.434791 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9672 12:18:19.438143 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9673 12:18:19.441194 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9674 12:18:19.448225 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9675 12:18:19.451114 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9676 12:18:19.457760 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9677 12:18:19.461243 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9678 12:18:19.464280 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9679 12:18:19.471082 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9680 12:18:19.474114 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9681 12:18:19.481089 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9682 12:18:19.484254 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9683 12:18:19.487391 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9684 12:18:19.494689 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9685 12:18:19.497430 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9686 12:18:19.503869 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9687 12:18:19.507362 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9688 12:18:19.510727 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9689 12:18:19.517126 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9690 12:18:19.520558 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9691 12:18:19.527086 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9692 12:18:19.530521 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9693 12:18:19.533979 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9694 12:18:19.540238 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9695 12:18:19.543674 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9696 12:18:19.550176 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9697 12:18:19.553683 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9698 12:18:19.556934 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9699 12:18:19.563358 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9700 12:18:19.566436 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9701 12:18:19.573000 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9702 12:18:19.576790 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9703 12:18:19.579580 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9704 12:18:19.586133 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9705 12:18:19.589850 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9706 12:18:19.596056 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9707 12:18:19.599297 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9708 12:18:19.602608 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9709 12:18:19.609221 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9710 12:18:19.612699 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9711 12:18:19.619833 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9712 12:18:19.622816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9713 12:18:19.626295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9714 12:18:19.633272 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9715 12:18:19.635918 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9716 12:18:19.642662 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9717 12:18:19.646078 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9718 12:18:19.652479 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9719 12:18:19.656099 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9720 12:18:19.659254 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9721 12:18:19.665459 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9722 12:18:19.668709 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9723 12:18:19.675292 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9724 12:18:19.678720 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9725 12:18:19.685268 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9726 12:18:19.688709 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9727 12:18:19.691570 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9728 12:18:19.698155 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9729 12:18:19.702019 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9730 12:18:19.708146 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9731 12:18:19.711384 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9732 12:18:19.715386 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9733 12:18:19.721258 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9734 12:18:19.724608 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9735 12:18:19.731557 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9736 12:18:19.734855 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9737 12:18:19.741653 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9738 12:18:19.745046 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9739 12:18:19.748215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9740 12:18:19.754690 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9741 12:18:19.757904 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9742 12:18:19.764680 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9743 12:18:19.767943 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9744 12:18:19.775103 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9745 12:18:19.777738 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9746 12:18:19.781449 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9747 12:18:19.787584 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9748 12:18:19.790813 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9749 12:18:19.797328 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9750 12:18:19.800958 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9751 12:18:19.807260 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9752 12:18:19.810383 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9753 12:18:19.813665 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9754 12:18:19.820619 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9755 12:18:19.823830 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9756 12:18:19.830251 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9757 12:18:19.833411 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9758 12:18:19.836883 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9759 12:18:19.843957 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9760 12:18:19.846897 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9761 12:18:19.851098 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9762 12:18:19.853772 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9763 12:18:19.860591 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9764 12:18:19.863720 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9765 12:18:19.867419 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9766 12:18:19.873380 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9767 12:18:19.876677 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9768 12:18:19.880318 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9769 12:18:19.886539 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9770 12:18:19.890140 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9771 12:18:19.896236 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9772 12:18:19.899852 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9773 12:18:19.902919 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9774 12:18:19.909635 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9775 12:18:19.912867 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9776 12:18:19.919359 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9777 12:18:19.922972 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9778 12:18:19.926121 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9779 12:18:19.932738 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9780 12:18:19.936474 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9781 12:18:19.939521 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9782 12:18:19.946638 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9783 12:18:19.950011 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9784 12:18:19.952931 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9785 12:18:19.959467 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9786 12:18:19.962862 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9787 12:18:19.969195 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9788 12:18:19.972501 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9789 12:18:19.976005 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9790 12:18:19.982476 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9791 12:18:19.985776 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9792 12:18:19.989341 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9793 12:18:19.995412 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9794 12:18:19.999074 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9795 12:18:20.005242 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9796 12:18:20.008556 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9797 12:18:20.011775 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9798 12:18:20.015616 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9799 12:18:20.021819 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9800 12:18:20.025833 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9801 12:18:20.028893 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9802 12:18:20.032278 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9803 12:18:20.038223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9804 12:18:20.041656 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9805 12:18:20.044953 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9806 12:18:20.048068 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9807 12:18:20.054757 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9808 12:18:20.058404 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9809 12:18:20.061548 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9810 12:18:20.068550 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9811 12:18:20.071370 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9812 12:18:20.074637 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9813 12:18:20.081117 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9814 12:18:20.084698 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9815 12:18:20.091317 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9816 12:18:20.094078 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9817 12:18:20.101069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9818 12:18:20.104087 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9819 12:18:20.107469 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9820 12:18:20.113924 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9821 12:18:20.117272 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9822 12:18:20.124036 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9823 12:18:20.127071 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9824 12:18:20.133465 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9825 12:18:20.136946 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9826 12:18:20.140303 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9827 12:18:20.147203 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9828 12:18:20.150405 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9829 12:18:20.157482 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9830 12:18:20.160430 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9831 12:18:20.163715 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9832 12:18:20.170993 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9833 12:18:20.173562 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9834 12:18:20.180364 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9835 12:18:20.183343 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9836 12:18:20.190245 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9837 12:18:20.193552 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9838 12:18:20.196729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9839 12:18:20.202834 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9840 12:18:20.206538 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9841 12:18:20.212991 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9842 12:18:20.216594 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9843 12:18:20.219979 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9844 12:18:20.226219 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9845 12:18:20.229266 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9846 12:18:20.235715 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9847 12:18:20.239265 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9848 12:18:20.245893 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9849 12:18:20.249429 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9850 12:18:20.252583 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9851 12:18:20.259395 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9852 12:18:20.262850 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9853 12:18:20.269502 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9854 12:18:20.272262 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9855 12:18:20.279044 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9856 12:18:20.281986 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9857 12:18:20.285487 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9858 12:18:20.292213 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9859 12:18:20.295217 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9860 12:18:20.301638 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9861 12:18:20.304994 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9862 12:18:20.308254 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9863 12:18:20.315105 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9864 12:18:20.318421 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9865 12:18:20.324833 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9866 12:18:20.328393 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9867 12:18:20.334809 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9868 12:18:20.337671 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9869 12:18:20.340586 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9870 12:18:20.347150 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9871 12:18:20.351070 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9872 12:18:20.357526 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9873 12:18:20.360848 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9874 12:18:20.364201 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9875 12:18:20.370724 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9876 12:18:20.373844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9877 12:18:20.380590 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9878 12:18:20.384510 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9879 12:18:20.390896 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9880 12:18:20.394091 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9881 12:18:20.400531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9882 12:18:20.403641 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9883 12:18:20.407105 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9884 12:18:20.413797 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9885 12:18:20.417259 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9886 12:18:20.423362 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9887 12:18:20.427022 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9888 12:18:20.433498 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9889 12:18:20.436818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9890 12:18:20.440146 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9891 12:18:20.446950 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9892 12:18:20.450565 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9893 12:18:20.456719 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9894 12:18:20.459817 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9895 12:18:20.466285 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9896 12:18:20.469997 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9897 12:18:20.476732 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9898 12:18:20.479690 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9899 12:18:20.482929 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9900 12:18:20.490061 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9901 12:18:20.493085 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9902 12:18:20.499929 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9903 12:18:20.502603 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9904 12:18:20.509311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9905 12:18:20.512798 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9906 12:18:20.516172 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9907 12:18:20.522624 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9908 12:18:20.526142 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9909 12:18:20.532877 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9910 12:18:20.535782 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9911 12:18:20.542399 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9912 12:18:20.546127 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9913 12:18:20.552389 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9914 12:18:20.555345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9915 12:18:20.558896 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9916 12:18:20.565400 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9917 12:18:20.568922 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9918 12:18:20.575292 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9919 12:18:20.578790 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9920 12:18:20.585805 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9921 12:18:20.588452 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9922 12:18:20.591845 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9923 12:18:20.599054 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9924 12:18:20.601657 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9925 12:18:20.608336 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9926 12:18:20.611674 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9927 12:18:20.618737 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9928 12:18:20.621442 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9929 12:18:20.628148 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9930 12:18:20.631570 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9931 12:18:20.634694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9932 12:18:20.641310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9933 12:18:20.644843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9934 12:18:20.651622 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9935 12:18:20.655168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9936 12:18:20.662174 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9937 12:18:20.664468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9938 12:18:20.671570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9939 12:18:20.674648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9940 12:18:20.681183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9941 12:18:20.684764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9942 12:18:20.690959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9943 12:18:20.694359 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9944 12:18:20.700811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9945 12:18:20.704276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9946 12:18:20.710901 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9947 12:18:20.713714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9948 12:18:20.721362 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9949 12:18:20.723673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9950 12:18:20.730526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9951 12:18:20.733659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9952 12:18:20.740467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9953 12:18:20.743581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9954 12:18:20.750213 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9955 12:18:20.753951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9956 12:18:20.759998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9957 12:18:20.763410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9958 12:18:20.769931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9959 12:18:20.773299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9960 12:18:20.780038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9961 12:18:20.783483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9962 12:18:20.789865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9963 12:18:20.793605 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9964 12:18:20.796730 INFO: [APUAPC] vio 0
9965 12:18:20.800110 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9966 12:18:20.806603 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9967 12:18:20.810098 INFO: [APUAPC] D0_APC_0: 0x400510
9968 12:18:20.810534 INFO: [APUAPC] D0_APC_1: 0x0
9969 12:18:20.812963 INFO: [APUAPC] D0_APC_2: 0x1540
9970 12:18:20.816625 INFO: [APUAPC] D0_APC_3: 0x0
9971 12:18:20.819711 INFO: [APUAPC] D1_APC_0: 0xffffffff
9972 12:18:20.823163 INFO: [APUAPC] D1_APC_1: 0xffffffff
9973 12:18:20.826328 INFO: [APUAPC] D1_APC_2: 0x3fffff
9974 12:18:20.829477 INFO: [APUAPC] D1_APC_3: 0x0
9975 12:18:20.833124 INFO: [APUAPC] D2_APC_0: 0xffffffff
9976 12:18:20.836418 INFO: [APUAPC] D2_APC_1: 0xffffffff
9977 12:18:20.839676 INFO: [APUAPC] D2_APC_2: 0x3fffff
9978 12:18:20.842877 INFO: [APUAPC] D2_APC_3: 0x0
9979 12:18:20.845976 INFO: [APUAPC] D3_APC_0: 0xffffffff
9980 12:18:20.849364 INFO: [APUAPC] D3_APC_1: 0xffffffff
9981 12:18:20.852893 INFO: [APUAPC] D3_APC_2: 0x3fffff
9982 12:18:20.856068 INFO: [APUAPC] D3_APC_3: 0x0
9983 12:18:20.859224 INFO: [APUAPC] D4_APC_0: 0xffffffff
9984 12:18:20.862698 INFO: [APUAPC] D4_APC_1: 0xffffffff
9985 12:18:20.866193 INFO: [APUAPC] D4_APC_2: 0x3fffff
9986 12:18:20.869186 INFO: [APUAPC] D4_APC_3: 0x0
9987 12:18:20.873283 INFO: [APUAPC] D5_APC_0: 0xffffffff
9988 12:18:20.875837 INFO: [APUAPC] D5_APC_1: 0xffffffff
9989 12:18:20.879838 INFO: [APUAPC] D5_APC_2: 0x3fffff
9990 12:18:20.882703 INFO: [APUAPC] D5_APC_3: 0x0
9991 12:18:20.885876 INFO: [APUAPC] D6_APC_0: 0xffffffff
9992 12:18:20.889036 INFO: [APUAPC] D6_APC_1: 0xffffffff
9993 12:18:20.892425 INFO: [APUAPC] D6_APC_2: 0x3fffff
9994 12:18:20.895568 INFO: [APUAPC] D6_APC_3: 0x0
9995 12:18:20.898873 INFO: [APUAPC] D7_APC_0: 0xffffffff
9996 12:18:20.902066 INFO: [APUAPC] D7_APC_1: 0xffffffff
9997 12:18:20.905428 INFO: [APUAPC] D7_APC_2: 0x3fffff
9998 12:18:20.908745 INFO: [APUAPC] D7_APC_3: 0x0
9999 12:18:20.911779 INFO: [APUAPC] D8_APC_0: 0xffffffff
10000 12:18:20.915543 INFO: [APUAPC] D8_APC_1: 0xffffffff
10001 12:18:20.919051 INFO: [APUAPC] D8_APC_2: 0x3fffff
10002 12:18:20.921823 INFO: [APUAPC] D8_APC_3: 0x0
10003 12:18:20.925648 INFO: [APUAPC] D9_APC_0: 0xffffffff
10004 12:18:20.928957 INFO: [APUAPC] D9_APC_1: 0xffffffff
10005 12:18:20.931820 INFO: [APUAPC] D9_APC_2: 0x3fffff
10006 12:18:20.934932 INFO: [APUAPC] D9_APC_3: 0x0
10007 12:18:20.938391 INFO: [APUAPC] D10_APC_0: 0xffffffff
10008 12:18:20.941606 INFO: [APUAPC] D10_APC_1: 0xffffffff
10009 12:18:20.945377 INFO: [APUAPC] D10_APC_2: 0x3fffff
10010 12:18:20.948170 INFO: [APUAPC] D10_APC_3: 0x0
10011 12:18:20.951598 INFO: [APUAPC] D11_APC_0: 0xffffffff
10012 12:18:20.955497 INFO: [APUAPC] D11_APC_1: 0xffffffff
10013 12:18:20.958567 INFO: [APUAPC] D11_APC_2: 0x3fffff
10014 12:18:20.962189 INFO: [APUAPC] D11_APC_3: 0x0
10015 12:18:20.964881 INFO: [APUAPC] D12_APC_0: 0xffffffff
10016 12:18:20.968555 INFO: [APUAPC] D12_APC_1: 0xffffffff
10017 12:18:20.972284 INFO: [APUAPC] D12_APC_2: 0x3fffff
10018 12:18:20.974597 INFO: [APUAPC] D12_APC_3: 0x0
10019 12:18:20.978161 INFO: [APUAPC] D13_APC_0: 0xffffffff
10020 12:18:20.981024 INFO: [APUAPC] D13_APC_1: 0xffffffff
10021 12:18:20.984403 INFO: [APUAPC] D13_APC_2: 0x3fffff
10022 12:18:20.987810 INFO: [APUAPC] D13_APC_3: 0x0
10023 12:18:20.991059 INFO: [APUAPC] D14_APC_0: 0xffffffff
10024 12:18:20.994259 INFO: [APUAPC] D14_APC_1: 0xffffffff
10025 12:18:20.997667 INFO: [APUAPC] D14_APC_2: 0x3fffff
10026 12:18:21.001049 INFO: [APUAPC] D14_APC_3: 0x0
10027 12:18:21.004358 INFO: [APUAPC] D15_APC_0: 0xffffffff
10028 12:18:21.007770 INFO: [APUAPC] D15_APC_1: 0xffffffff
10029 12:18:21.010805 INFO: [APUAPC] D15_APC_2: 0x3fffff
10030 12:18:21.013964 INFO: [APUAPC] D15_APC_3: 0x0
10031 12:18:21.017283 INFO: [APUAPC] APC_CON: 0x4
10032 12:18:21.021124 INFO: [NOCDAPC] D0_APC_0: 0x0
10033 12:18:21.024182 INFO: [NOCDAPC] D0_APC_1: 0x0
10034 12:18:21.027714 INFO: [NOCDAPC] D1_APC_0: 0x0
10035 12:18:21.031180 INFO: [NOCDAPC] D1_APC_1: 0xfff
10036 12:18:21.031821 INFO: [NOCDAPC] D2_APC_0: 0x0
10037 12:18:21.034083 INFO: [NOCDAPC] D2_APC_1: 0xfff
10038 12:18:21.037037 INFO: [NOCDAPC] D3_APC_0: 0x0
10039 12:18:21.040332 INFO: [NOCDAPC] D3_APC_1: 0xfff
10040 12:18:21.043719 INFO: [NOCDAPC] D4_APC_0: 0x0
10041 12:18:21.046822 INFO: [NOCDAPC] D4_APC_1: 0xfff
10042 12:18:21.050382 INFO: [NOCDAPC] D5_APC_0: 0x0
10043 12:18:21.053611 INFO: [NOCDAPC] D5_APC_1: 0xfff
10044 12:18:21.056828 INFO: [NOCDAPC] D6_APC_0: 0x0
10045 12:18:21.060168 INFO: [NOCDAPC] D6_APC_1: 0xfff
10046 12:18:21.063795 INFO: [NOCDAPC] D7_APC_0: 0x0
10047 12:18:21.064230 INFO: [NOCDAPC] D7_APC_1: 0xfff
10048 12:18:21.066957 INFO: [NOCDAPC] D8_APC_0: 0x0
10049 12:18:21.069880 INFO: [NOCDAPC] D8_APC_1: 0xfff
10050 12:18:21.073296 INFO: [NOCDAPC] D9_APC_0: 0x0
10051 12:18:21.076633 INFO: [NOCDAPC] D9_APC_1: 0xfff
10052 12:18:21.079978 INFO: [NOCDAPC] D10_APC_0: 0x0
10053 12:18:21.083011 INFO: [NOCDAPC] D10_APC_1: 0xfff
10054 12:18:21.086361 INFO: [NOCDAPC] D11_APC_0: 0x0
10055 12:18:21.089614 INFO: [NOCDAPC] D11_APC_1: 0xfff
10056 12:18:21.093369 INFO: [NOCDAPC] D12_APC_0: 0x0
10057 12:18:21.096189 INFO: [NOCDAPC] D12_APC_1: 0xfff
10058 12:18:21.099583 INFO: [NOCDAPC] D13_APC_0: 0x0
10059 12:18:21.103159 INFO: [NOCDAPC] D13_APC_1: 0xfff
10060 12:18:21.106332 INFO: [NOCDAPC] D14_APC_0: 0x0
10061 12:18:21.109292 INFO: [NOCDAPC] D14_APC_1: 0xfff
10062 12:18:21.109448 INFO: [NOCDAPC] D15_APC_0: 0x0
10063 12:18:21.112825 INFO: [NOCDAPC] D15_APC_1: 0xfff
10064 12:18:21.116009 INFO: [NOCDAPC] APC_CON: 0x4
10065 12:18:21.119463 INFO: [APUAPC] set_apusys_apc done
10066 12:18:21.122476 INFO: [DEVAPC] devapc_init done
10067 12:18:21.129569 INFO: GICv3 without legacy support detected.
10068 12:18:21.132561 INFO: ARM GICv3 driver initialized in EL3
10069 12:18:21.136120 INFO: Maximum SPI INTID supported: 639
10070 12:18:21.139184 INFO: BL31: Initializing runtime services
10071 12:18:21.146079 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10072 12:18:21.149252 INFO: SPM: enable CPC mode
10073 12:18:21.152764 INFO: mcdi ready for mcusys-off-idle and system suspend
10074 12:18:21.159286 INFO: BL31: Preparing for EL3 exit to normal world
10075 12:18:21.162523 INFO: Entry point address = 0x80000000
10076 12:18:21.162953 INFO: SPSR = 0x8
10077 12:18:21.169814
10078 12:18:21.170340
10079 12:18:21.170680
10080 12:18:21.172468 Starting depthcharge on Spherion...
10081 12:18:21.172897
10082 12:18:21.173237 Wipe memory regions:
10083 12:18:21.173554
10084 12:18:21.175991 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10085 12:18:21.176504 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10086 12:18:21.176927 Setting prompt string to ['asurada:']
10087 12:18:21.177320 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10088 12:18:21.177973 [0x00000040000000, 0x00000054600000)
10089 12:18:21.298301
10090 12:18:21.298865 [0x00000054660000, 0x00000080000000)
10091 12:18:21.558736
10092 12:18:21.559278 [0x000000821a7280, 0x000000ffe64000)
10093 12:18:22.302642
10094 12:18:22.302830 [0x00000100000000, 0x00000240000000)
10095 12:18:24.190994
10096 12:18:24.194323 Initializing XHCI USB controller at 0x11200000.
10097 12:18:25.175743
10098 12:18:25.175893 R8152: Initializing
10099 12:18:25.175962
10100 12:18:25.179388 Version 9 (ocp_data = 6010)
10101 12:18:25.179526
10102 12:18:25.183378 R8152: Done initializing
10103 12:18:25.183461
10104 12:18:25.183527 Adding net device
10105 12:18:25.705029
10106 12:18:25.708058 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10107 12:18:25.708151
10108 12:18:25.708218
10109 12:18:25.708280
10110 12:18:25.708548 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10112 12:18:25.808902 asurada: tftpboot 192.168.201.1 11893112/tftp-deploy-13d80pt7/kernel/image.itb 11893112/tftp-deploy-13d80pt7/kernel/cmdline
10113 12:18:25.809097 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10114 12:18:25.809229 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10115 12:18:25.813241 tftpboot 192.168.201.1 11893112/tftp-deploy-13d80pt7/kernel/image.itp-deploy-13d80pt7/kernel/cmdline
10116 12:18:25.813350
10117 12:18:25.813430 Waiting for link
10118 12:18:26.016262
10119 12:18:26.016415 done.
10120 12:18:26.016483
10121 12:18:26.016546 MAC: f4:f5:e8:50:de:0a
10122 12:18:26.016606
10123 12:18:26.019175 Sending DHCP discover... done.
10124 12:18:26.019259
10125 12:18:26.022252 Waiting for reply... done.
10126 12:18:26.022336
10127 12:18:26.025638 Sending DHCP request... done.
10128 12:18:26.025723
10129 12:18:26.025798 Waiting for reply... done.
10130 12:18:26.025863
10131 12:18:26.028774 My ip is 192.168.201.14
10132 12:18:26.028876
10133 12:18:26.032140 The DHCP server ip is 192.168.201.1
10134 12:18:26.032217
10135 12:18:26.035277 TFTP server IP predefined by user: 192.168.201.1
10136 12:18:26.035388
10137 12:18:26.042223 Bootfile predefined by user: 11893112/tftp-deploy-13d80pt7/kernel/image.itb
10138 12:18:26.042349
10139 12:18:26.045410 Sending tftp read request... done.
10140 12:18:26.045515
10141 12:18:26.048576 Waiting for the transfer...
10142 12:18:26.048677
10143 12:18:26.373055 00000000 ################################################################
10144 12:18:26.373208
10145 12:18:26.686424 00080000 ################################################################
10146 12:18:26.686617
10147 12:18:26.998520 00100000 ################################################################
10148 12:18:26.998678
10149 12:18:27.326347 00180000 ################################################################
10150 12:18:27.326501
10151 12:18:27.642305 00200000 ################################################################
10152 12:18:27.642458
10153 12:18:27.968316 00280000 ################################################################
10154 12:18:27.968472
10155 12:18:28.278826 00300000 ################################################################
10156 12:18:28.279006
10157 12:18:28.606991 00380000 ################################################################
10158 12:18:28.607133
10159 12:18:28.917857 00400000 ################################################################
10160 12:18:28.918043
10161 12:18:29.230102 00480000 ################################################################
10162 12:18:29.230250
10163 12:18:29.552009 00500000 ################################################################
10164 12:18:29.552161
10165 12:18:29.876735 00580000 ################################################################
10166 12:18:29.876897
10167 12:18:30.191062 00600000 ################################################################
10168 12:18:30.191200
10169 12:18:30.443011 00680000 ################################################################
10170 12:18:30.443209
10171 12:18:30.688075 00700000 ################################################################
10172 12:18:30.688238
10173 12:18:30.994345 00780000 ################################################################
10174 12:18:30.994510
10175 12:18:31.319045 00800000 ################################################################
10176 12:18:31.319243
10177 12:18:31.640913 00880000 ################################################################
10178 12:18:31.641100
10179 12:18:31.961499 00900000 ################################################################
10180 12:18:31.961690
10181 12:18:32.279534 00980000 ################################################################
10182 12:18:32.279686
10183 12:18:32.593758 00a00000 ################################################################
10184 12:18:32.593952
10185 12:18:32.903331 00a80000 ################################################################
10186 12:18:32.903475
10187 12:18:33.217483 00b00000 ################################################################
10188 12:18:33.217640
10189 12:18:33.538907 00b80000 ################################################################
10190 12:18:33.539083
10191 12:18:33.815414 00c00000 ################################################################
10192 12:18:33.815569
10193 12:18:34.048269 00c80000 ################################################################
10194 12:18:34.048404
10195 12:18:34.288098 00d00000 ################################################################
10196 12:18:34.288242
10197 12:18:34.615289 00d80000 ################################################################
10198 12:18:34.615466
10199 12:18:34.930472 00e00000 ################################################################
10200 12:18:34.930626
10201 12:18:35.244597 00e80000 ################################################################
10202 12:18:35.244746
10203 12:18:35.558671 00f00000 ################################################################
10204 12:18:35.558818
10205 12:18:35.886634 00f80000 ################################################################
10206 12:18:35.886773
10207 12:18:36.206908 01000000 ################################################################
10208 12:18:36.207051
10209 12:18:36.532088 01080000 ################################################################
10210 12:18:36.532239
10211 12:18:36.855578 01100000 ################################################################
10212 12:18:36.855840
10213 12:18:37.180204 01180000 ################################################################
10214 12:18:37.180358
10215 12:18:37.507292 01200000 ################################################################
10216 12:18:37.507441
10217 12:18:37.818411 01280000 ################################################################
10218 12:18:37.818568
10219 12:18:38.127277 01300000 ################################################################
10220 12:18:38.127412
10221 12:18:38.441352 01380000 ################################################################
10222 12:18:38.441499
10223 12:18:38.757834 01400000 ################################################################
10224 12:18:38.757990
10225 12:18:39.072373 01480000 ################################################################
10226 12:18:39.072563
10227 12:18:39.381025 01500000 ################################################################
10228 12:18:39.381168
10229 12:18:39.694668 01580000 ################################################################
10230 12:18:39.694805
10231 12:18:40.008157 01600000 ################################################################
10232 12:18:40.008315
10233 12:18:40.324435 01680000 ################################################################
10234 12:18:40.324594
10235 12:18:40.636550 01700000 ################################################################
10236 12:18:40.636734
10237 12:18:40.949355 01780000 ################################################################
10238 12:18:40.949538
10239 12:18:41.285876 01800000 ################################################################
10240 12:18:41.286031
10241 12:18:41.601205 01880000 ################################################################
10242 12:18:41.601374
10243 12:18:41.906612 01900000 ################################################################
10244 12:18:41.906769
10245 12:18:42.223470 01980000 ################################################################
10246 12:18:42.223620
10247 12:18:42.542215 01a00000 ################################################################
10248 12:18:42.542385
10249 12:18:42.862734 01a80000 ################################################################
10250 12:18:42.862923
10251 12:18:43.197079 01b00000 ################################################################
10252 12:18:43.197245
10253 12:18:43.513811 01b80000 ################################################################
10254 12:18:43.513970
10255 12:18:43.854356 01c00000 ################################################################
10256 12:18:43.854502
10257 12:18:44.180237 01c80000 ################################################################
10258 12:18:44.180397
10259 12:18:44.513827 01d00000 ################################################################
10260 12:18:44.513978
10261 12:18:44.846761 01d80000 ################################################################
10262 12:18:44.846909
10263 12:18:45.180440 01e00000 ################################################################
10264 12:18:45.180591
10265 12:18:45.485191 01e80000 ################################################################
10266 12:18:45.485343
10267 12:18:45.817331 01f00000 ################################################################
10268 12:18:45.817480
10269 12:18:46.133073 01f80000 ################################################################
10270 12:18:46.133228
10271 12:18:46.449301 02000000 ################################################################
10272 12:18:46.449481
10273 12:18:46.761038 02080000 ################################################################
10274 12:18:46.761184
10275 12:18:47.082160 02100000 ################################################################
10276 12:18:47.082340
10277 12:18:47.406005 02180000 ################################################################
10278 12:18:47.406184
10279 12:18:47.710570 02200000 ################################################################
10280 12:18:47.710806
10281 12:18:48.014348 02280000 ################################################################
10282 12:18:48.014526
10283 12:18:48.328662 02300000 ################################################################
10284 12:18:48.328838
10285 12:18:48.649107 02380000 ################################################################
10286 12:18:48.649276
10287 12:18:48.973932 02400000 ################################################################
10288 12:18:48.974108
10289 12:18:49.282326 02480000 ################################################################
10290 12:18:49.282506
10291 12:18:49.523614 02500000 ################################################################
10292 12:18:49.523785
10293 12:18:49.769789 02580000 ################################################################
10294 12:18:49.769945
10295 12:18:50.028108 02600000 ################################################################
10296 12:18:50.028280
10297 12:18:50.294330 02680000 ################################################################
10298 12:18:50.294509
10299 12:18:50.552678 02700000 ################################################################
10300 12:18:50.552836
10301 12:18:50.798535 02780000 ################################################################
10302 12:18:50.798686
10303 12:18:51.042001 02800000 ################################################################
10304 12:18:51.042155
10305 12:18:51.279195 02880000 ################################################################
10306 12:18:51.279337
10307 12:18:51.525959 02900000 ################################################################
10308 12:18:51.526108
10309 12:18:51.764136 02980000 ################################################################
10310 12:18:51.764287
10311 12:18:51.997206 02a00000 ################################################################
10312 12:18:51.997369
10313 12:18:52.236161 02a80000 ################################################################
10314 12:18:52.236298
10315 12:18:52.478543 02b00000 ################################################################
10316 12:18:52.478686
10317 12:18:52.725424 02b80000 ################################################################
10318 12:18:52.725575
10319 12:18:52.980115 02c00000 ################################################################
10320 12:18:52.980265
10321 12:18:53.233944 02c80000 ################################################################
10322 12:18:53.234090
10323 12:18:53.489007 02d00000 ################################################################
10324 12:18:53.489163
10325 12:18:53.743963 02d80000 ################################################################
10326 12:18:53.744112
10327 12:18:53.989046 02e00000 ################################################################
10328 12:18:53.989188
10329 12:18:54.244487 02e80000 ################################################################
10330 12:18:54.244638
10331 12:18:54.487318 02f00000 ################################################################
10332 12:18:54.487472
10333 12:18:54.735364 02f80000 ################################################################
10334 12:18:54.735539
10335 12:18:54.984226 03000000 ################################################################
10336 12:18:54.984378
10337 12:18:55.227995 03080000 ################################################################
10338 12:18:55.228144
10339 12:18:55.474601 03100000 ################################################################
10340 12:18:55.474752
10341 12:18:55.724595 03180000 ################################################################
10342 12:18:55.724745
10343 12:18:55.967263 03200000 ################################################################
10344 12:18:55.967414
10345 12:18:56.219617 03280000 ################################################################
10346 12:18:56.219809
10347 12:18:56.466308 03300000 ################################################################
10348 12:18:56.466503
10349 12:18:56.707676 03380000 ################################################################
10350 12:18:56.707864
10351 12:18:56.950605 03400000 ################################################################
10352 12:18:56.950757
10353 12:18:57.198733 03480000 ################################################################
10354 12:18:57.198885
10355 12:18:57.449243 03500000 ################################################################
10356 12:18:57.449382
10357 12:18:57.699523 03580000 ################################################################
10358 12:18:57.699673
10359 12:18:57.953952 03600000 ################################################################
10360 12:18:57.954104
10361 12:18:58.192679 03680000 ################################################################
10362 12:18:58.192827
10363 12:18:58.441477 03700000 ################################################################
10364 12:18:58.441631
10365 12:18:58.697332 03780000 ################################################################
10366 12:18:58.697481
10367 12:18:58.955403 03800000 ################################################################
10368 12:18:58.955549
10369 12:18:59.201462 03880000 ################################################################
10370 12:18:59.201621
10371 12:18:59.450149 03900000 ################################################################
10372 12:18:59.450288
10373 12:18:59.703680 03980000 ################################################################
10374 12:18:59.703861
10375 12:18:59.960960 03a00000 ################################################################
10376 12:18:59.961116
10377 12:19:00.216339 03a80000 ################################################################
10378 12:19:00.216488
10379 12:19:00.471425 03b00000 ################################################################
10380 12:19:00.471605
10381 12:19:00.712590 03b80000 ################################################################
10382 12:19:00.712738
10383 12:19:00.958585 03c00000 ################################################################
10384 12:19:00.958735
10385 12:19:01.206396 03c80000 ################################################################
10386 12:19:01.206545
10387 12:19:01.459559 03d00000 ################################################################
10388 12:19:01.459712
10389 12:19:01.705383 03d80000 ################################################################
10390 12:19:01.705533
10391 12:19:01.964003 03e00000 ################################################################
10392 12:19:01.964156
10393 12:19:02.208187 03e80000 ################################################################
10394 12:19:02.208338
10395 12:19:02.454413 03f00000 ################################################################
10396 12:19:02.454573
10397 12:19:02.699637 03f80000 ################################################################
10398 12:19:02.699821
10399 12:19:02.944102 04000000 ################################################################
10400 12:19:02.944261
10401 12:19:03.185129 04080000 ################################################################
10402 12:19:03.185314
10403 12:19:03.427652 04100000 ################################################################
10404 12:19:03.427822
10405 12:19:03.669652 04180000 ################################################################
10406 12:19:03.669825
10407 12:19:03.927552 04200000 ################################################################
10408 12:19:03.927735
10409 12:19:04.180851 04280000 ################################################################
10410 12:19:04.181067
10411 12:19:04.423997 04300000 ################################################################
10412 12:19:04.424146
10413 12:19:04.667427 04380000 ################################################################
10414 12:19:04.667578
10415 12:19:04.924011 04400000 ################################################################
10416 12:19:04.924160
10417 12:19:05.165311 04480000 ################################################################
10418 12:19:05.165459
10419 12:19:05.407067 04500000 ################################################################
10420 12:19:05.407259
10421 12:19:05.646472 04580000 ################################################################
10422 12:19:05.646623
10423 12:19:05.899019 04600000 ################################################################
10424 12:19:05.899220
10425 12:19:06.144550 04680000 ################################################################
10426 12:19:06.144701
10427 12:19:06.384777 04700000 ################################################################
10428 12:19:06.384927
10429 12:19:06.623100 04780000 ################################################################
10430 12:19:06.623250
10431 12:19:06.871025 04800000 ################################################################
10432 12:19:06.871175
10433 12:19:07.110424 04880000 ################################################################
10434 12:19:07.110567
10435 12:19:07.362742 04900000 ################################################################
10436 12:19:07.362881
10437 12:19:07.615166 04980000 ################################################################
10438 12:19:07.615321
10439 12:19:07.856770 04a00000 ################################################################
10440 12:19:07.856921
10441 12:19:08.092077 04a80000 ################################################################
10442 12:19:08.092229
10443 12:19:08.332373 04b00000 ################################################################
10444 12:19:08.332514
10445 12:19:08.568075 04b80000 ################################################################
10446 12:19:08.568219
10447 12:19:08.816628 04c00000 ################################################################
10448 12:19:08.816777
10449 12:19:09.061825 04c80000 ################################################################
10450 12:19:09.062001
10451 12:19:09.302772 04d00000 ################################################################
10452 12:19:09.302926
10453 12:19:09.552855 04d80000 ################################################################
10454 12:19:09.553006
10455 12:19:09.797641 04e00000 ################################################################
10456 12:19:09.797790
10457 12:19:10.036855 04e80000 ################################################################
10458 12:19:10.036993
10459 12:19:10.280864 04f00000 ################################################################
10460 12:19:10.281029
10461 12:19:10.531273 04f80000 ################################################################
10462 12:19:10.531471
10463 12:19:10.770144 05000000 ################################################################
10464 12:19:10.770297
10465 12:19:11.013710 05080000 ################################################################
10466 12:19:11.013865
10467 12:19:11.252987 05100000 ################################################################
10468 12:19:11.253143
10469 12:19:11.495157 05180000 ################################################################
10470 12:19:11.495330
10471 12:19:11.738532 05200000 ################################################################
10472 12:19:11.738681
10473 12:19:11.976705 05280000 ################################################################
10474 12:19:11.976858
10475 12:19:12.220383 05300000 ################################################################
10476 12:19:12.220538
10477 12:19:12.468776 05380000 ################################################################
10478 12:19:12.469001
10479 12:19:12.719512 05400000 ################################################################
10480 12:19:12.719664
10481 12:19:12.967504 05480000 ################################################################
10482 12:19:12.967681
10483 12:19:13.203011 05500000 ################################################################
10484 12:19:13.203158
10485 12:19:13.452747 05580000 ################################################################
10486 12:19:13.452908
10487 12:19:13.702994 05600000 ################################################################
10488 12:19:13.703138
10489 12:19:13.947966 05680000 ################################################################
10490 12:19:13.948113
10491 12:19:14.188473 05700000 ################################################################
10492 12:19:14.188627
10493 12:19:14.444046 05780000 ################################################################
10494 12:19:14.444252
10495 12:19:14.700528 05800000 ################################################################
10496 12:19:14.700679
10497 12:19:14.954507 05880000 ################################################################
10498 12:19:14.954658
10499 12:19:15.192460 05900000 ################################################################
10500 12:19:15.192633
10501 12:19:15.437097 05980000 ################################################################
10502 12:19:15.437236
10503 12:19:15.678346 05a00000 ################################################################
10504 12:19:15.678510
10505 12:19:15.924672 05a80000 ################################################################
10506 12:19:15.924825
10507 12:19:16.166813 05b00000 ################################################################
10508 12:19:16.166963
10509 12:19:16.409042 05b80000 ################################################################
10510 12:19:16.409202
10511 12:19:16.663431 05c00000 ################################################################
10512 12:19:16.663581
10513 12:19:16.914734 05c80000 ################################################################
10514 12:19:16.914888
10515 12:19:17.158466 05d00000 ################################################################
10516 12:19:17.158602
10517 12:19:17.409448 05d80000 ################################################################
10518 12:19:17.409601
10519 12:19:17.659422 05e00000 ################################################################
10520 12:19:17.659575
10521 12:19:17.900433 05e80000 ################################################################
10522 12:19:17.900583
10523 12:19:18.138421 05f00000 ################################################################
10524 12:19:18.138573
10525 12:19:18.377845 05f80000 ################################################################
10526 12:19:18.377995
10527 12:19:18.620174 06000000 ################################################################
10528 12:19:18.620317
10529 12:19:18.856541 06080000 ################################################################
10530 12:19:18.856692
10531 12:19:19.090699 06100000 ################################################################
10532 12:19:19.090882
10533 12:19:19.337447 06180000 ################################################################
10534 12:19:19.337588
10535 12:19:19.594797 06200000 ################################################################
10536 12:19:19.594946
10537 12:19:19.838913 06280000 ################################################################
10538 12:19:19.839063
10539 12:19:20.089922 06300000 ################################################################
10540 12:19:20.090101
10541 12:19:20.330091 06380000 ################################################################
10542 12:19:20.330247
10543 12:19:20.582074 06400000 ################################################################
10544 12:19:20.582221
10545 12:19:20.823952 06480000 ################################################################
10546 12:19:20.824098
10547 12:19:21.076581 06500000 ################################################################
10548 12:19:21.076726
10549 12:19:21.325728 06580000 ################################################################
10550 12:19:21.325902
10551 12:19:21.579389 06600000 ################################################################
10552 12:19:21.579533
10553 12:19:21.821277 06680000 ################################################################
10554 12:19:21.821427
10555 12:19:22.064823 06700000 ################################################################
10556 12:19:22.065118
10557 12:19:22.311903 06780000 ################################################################
10558 12:19:22.312049
10559 12:19:22.482638 06800000 ############################################## done.
10560 12:19:22.482798
10561 12:19:22.486001 The bootfile was 109423090 bytes long.
10562 12:19:22.486087
10563 12:19:22.489707 Sending tftp read request... done.
10564 12:19:22.489793
10565 12:19:22.492982 Waiting for the transfer...
10566 12:19:22.493067
10567 12:19:22.493133 00000000 # done.
10568 12:19:22.493198
10569 12:19:22.502477 Command line loaded dynamically from TFTP file: 11893112/tftp-deploy-13d80pt7/kernel/cmdline
10570 12:19:22.502562
10571 12:19:22.515563 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10572 12:19:22.515650
10573 12:19:22.515765 Loading FIT.
10574 12:19:22.515829
10575 12:19:22.518817 Image ramdisk-1 has 98325783 bytes.
10576 12:19:22.518900
10577 12:19:22.522374 Image fdt-1 has 47278 bytes.
10578 12:19:22.522458
10579 12:19:22.525727 Image kernel-1 has 11047994 bytes.
10580 12:19:22.525811
10581 12:19:22.535217 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10582 12:19:22.535302
10583 12:19:22.551649 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10584 12:19:22.551767
10585 12:19:22.558085 Choosing best match conf-1 for compat google,spherion-rev2.
10586 12:19:22.558170
10587 12:19:22.565100 Connected to device vid:did:rid of 1ae0:0028:00
10588 12:19:22.572451
10589 12:19:22.575999 tpm_get_response: command 0x17b, return code 0x0
10590 12:19:22.576084
10591 12:19:22.578924 ec_init: CrosEC protocol v3 supported (256, 248)
10592 12:19:22.583694
10593 12:19:22.587122 tpm_cleanup: add release locality here.
10594 12:19:22.587206
10595 12:19:22.587284 Shutting down all USB controllers.
10596 12:19:22.590759
10597 12:19:22.590842 Removing current net device
10598 12:19:22.590910
10599 12:19:22.597083 Exiting depthcharge with code 4 at timestamp: 90853290
10600 12:19:22.597167
10601 12:19:22.600275 LZMA decompressing kernel-1 to 0x821a6718
10602 12:19:22.600358
10603 12:19:22.604038 LZMA decompressing kernel-1 to 0x40000000
10604 12:19:23.992549
10605 12:19:23.992707 jumping to kernel
10606 12:19:23.993270 end: 2.2.4 bootloader-commands (duration 00:01:03) [common]
10607 12:19:23.993366 start: 2.2.5 auto-login-action (timeout 00:03:22) [common]
10608 12:19:23.993445 Setting prompt string to ['Linux version [0-9]']
10609 12:19:23.993517 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10610 12:19:23.993587 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10611 12:19:24.074162
10612 12:19:24.077376 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10613 12:19:24.080788 start: 2.2.5.1 login-action (timeout 00:03:22) [common]
10614 12:19:24.080903 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10615 12:19:24.081004 Setting prompt string to []
10616 12:19:24.081113 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10617 12:19:24.081214 Using line separator: #'\n'#
10618 12:19:24.081301 No login prompt set.
10619 12:19:24.081393 Parsing kernel messages
10620 12:19:24.081476 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10621 12:19:24.081646 [login-action] Waiting for messages, (timeout 00:03:22)
10622 12:19:24.100643 [ 0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023
10623 12:19:24.103490 [ 0.000000] random: crng init done
10624 12:19:24.110501 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10625 12:19:24.113679 [ 0.000000] efi: UEFI not found.
10626 12:19:24.120088 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10627 12:19:24.126959 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10628 12:19:24.136924 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10629 12:19:24.146775 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10630 12:19:24.153594 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10631 12:19:24.159888 [ 0.000000] printk: bootconsole [mtk8250] enabled
10632 12:19:24.166715 [ 0.000000] NUMA: No NUMA configuration found
10633 12:19:24.172762 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10634 12:19:24.176576 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10635 12:19:24.179498 [ 0.000000] Zone ranges:
10636 12:19:24.185947 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10637 12:19:24.189398 [ 0.000000] DMA32 empty
10638 12:19:24.196214 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10639 12:19:24.199694 [ 0.000000] Movable zone start for each node
10640 12:19:24.203382 [ 0.000000] Early memory node ranges
10641 12:19:24.209297 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10642 12:19:24.216038 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10643 12:19:24.222910 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10644 12:19:24.229312 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10645 12:19:24.235542 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10646 12:19:24.241934 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10647 12:19:24.298204 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10648 12:19:24.304519 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10649 12:19:24.311561 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10650 12:19:24.314665 [ 0.000000] psci: probing for conduit method from DT.
10651 12:19:24.321739 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10652 12:19:24.324388 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10653 12:19:24.331010 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10654 12:19:24.334347 [ 0.000000] psci: SMC Calling Convention v1.2
10655 12:19:24.340509 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10656 12:19:24.344046 [ 0.000000] Detected VIPT I-cache on CPU0
10657 12:19:24.350730 [ 0.000000] CPU features: detected: GIC system register CPU interface
10658 12:19:24.357357 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10659 12:19:24.363900 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10660 12:19:24.370325 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10661 12:19:24.380429 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10662 12:19:24.387364 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10663 12:19:24.390480 [ 0.000000] alternatives: applying boot alternatives
10664 12:19:24.397003 [ 0.000000] Fallback order for Node 0: 0
10665 12:19:24.403727 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10666 12:19:24.406740 [ 0.000000] Policy zone: Normal
10667 12:19:24.419644 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10668 12:19:24.429937 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10669 12:19:24.442492 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10670 12:19:24.452352 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10671 12:19:24.459054 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10672 12:19:24.462027 <6>[ 0.000000] software IO TLB: area num 8.
10673 12:19:24.518785 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10674 12:19:24.667866 <6>[ 0.000000] Memory: 7873468K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 479300K reserved, 32768K cma-reserved)
10675 12:19:24.674630 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10676 12:19:24.681271 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10677 12:19:24.684326 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10678 12:19:24.690878 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10679 12:19:24.697582 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10680 12:19:24.704196 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10681 12:19:24.710714 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10682 12:19:24.717496 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10683 12:19:24.724006 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10684 12:19:24.730579 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10685 12:19:24.733400 <6>[ 0.000000] GICv3: 608 SPIs implemented
10686 12:19:24.736757 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10687 12:19:24.743219 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10688 12:19:24.746911 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10689 12:19:24.753592 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10690 12:19:24.766276 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10691 12:19:24.779648 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10692 12:19:24.786305 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10693 12:19:24.795079 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10694 12:19:24.808038 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10695 12:19:24.814538 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10696 12:19:24.821118 <6>[ 0.009178] Console: colour dummy device 80x25
10697 12:19:24.830851 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10698 12:19:24.837822 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10699 12:19:24.841338 <6>[ 0.029217] LSM: Security Framework initializing
10700 12:19:24.847630 <6>[ 0.034157] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10701 12:19:24.857489 <6>[ 0.042019] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10702 12:19:24.864796 <6>[ 0.051327] cblist_init_generic: Setting adjustable number of callback queues.
10703 12:19:24.870996 <6>[ 0.058772] cblist_init_generic: Setting shift to 3 and lim to 1.
10704 12:19:24.880763 <6>[ 0.065110] cblist_init_generic: Setting adjustable number of callback queues.
10705 12:19:24.887490 <6>[ 0.072584] cblist_init_generic: Setting shift to 3 and lim to 1.
10706 12:19:24.890316 <6>[ 0.078985] rcu: Hierarchical SRCU implementation.
10707 12:19:24.897336 <6>[ 0.084000] rcu: Max phase no-delay instances is 1000.
10708 12:19:24.903811 <6>[ 0.091027] EFI services will not be available.
10709 12:19:24.907178 <6>[ 0.096013] smp: Bringing up secondary CPUs ...
10710 12:19:24.915544 <6>[ 0.101063] Detected VIPT I-cache on CPU1
10711 12:19:24.922023 <6>[ 0.101133] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10712 12:19:24.928748 <6>[ 0.101162] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10713 12:19:24.932013 <6>[ 0.101502] Detected VIPT I-cache on CPU2
10714 12:19:24.941713 <6>[ 0.101556] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10715 12:19:24.948409 <6>[ 0.101574] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10716 12:19:24.951605 <6>[ 0.101831] Detected VIPT I-cache on CPU3
10717 12:19:24.958119 <6>[ 0.101878] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10718 12:19:24.964632 <6>[ 0.101892] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10719 12:19:24.971489 <6>[ 0.102198] CPU features: detected: Spectre-v4
10720 12:19:24.974502 <6>[ 0.102204] CPU features: detected: Spectre-BHB
10721 12:19:24.977617 <6>[ 0.102209] Detected PIPT I-cache on CPU4
10722 12:19:24.987658 <6>[ 0.102267] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10723 12:19:24.994080 <6>[ 0.102283] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10724 12:19:24.997600 <6>[ 0.102574] Detected PIPT I-cache on CPU5
10725 12:19:25.004304 <6>[ 0.102636] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10726 12:19:25.010575 <6>[ 0.102652] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10727 12:19:25.013762 <6>[ 0.102934] Detected PIPT I-cache on CPU6
10728 12:19:25.024066 <6>[ 0.102999] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10729 12:19:25.030408 <6>[ 0.103015] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10730 12:19:25.033689 <6>[ 0.103312] Detected PIPT I-cache on CPU7
10731 12:19:25.040182 <6>[ 0.103377] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10732 12:19:25.047089 <6>[ 0.103394] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10733 12:19:25.050130 <6>[ 0.103440] smp: Brought up 1 node, 8 CPUs
10734 12:19:25.056486 <6>[ 0.244711] SMP: Total of 8 processors activated.
10735 12:19:25.063438 <6>[ 0.249632] CPU features: detected: 32-bit EL0 Support
10736 12:19:25.069781 <6>[ 0.255029] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10737 12:19:25.076641 <6>[ 0.263830] CPU features: detected: Common not Private translations
10738 12:19:25.082836 <6>[ 0.270306] CPU features: detected: CRC32 instructions
10739 12:19:25.089560 <6>[ 0.275658] CPU features: detected: RCpc load-acquire (LDAPR)
10740 12:19:25.093119 <6>[ 0.281618] CPU features: detected: LSE atomic instructions
10741 12:19:25.099709 <6>[ 0.287436] CPU features: detected: Privileged Access Never
10742 12:19:25.106128 <6>[ 0.293216] CPU features: detected: RAS Extension Support
10743 12:19:25.112709 <6>[ 0.298825] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10744 12:19:25.115668 <6>[ 0.306090] CPU: All CPU(s) started at EL2
10745 12:19:25.122704 <6>[ 0.310407] alternatives: applying system-wide alternatives
10746 12:19:25.132753 <6>[ 0.321056] devtmpfs: initialized
10747 12:19:25.148173 <6>[ 0.329851] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10748 12:19:25.155070 <6>[ 0.339815] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10749 12:19:25.161521 <6>[ 0.347828] pinctrl core: initialized pinctrl subsystem
10750 12:19:25.164522 <6>[ 0.354509] DMI not present or invalid.
10751 12:19:25.171406 <6>[ 0.358915] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10752 12:19:25.181024 <6>[ 0.365760] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10753 12:19:25.187684 <6>[ 0.373346] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10754 12:19:25.197658 <6>[ 0.381560] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10755 12:19:25.201185 <6>[ 0.389803] audit: initializing netlink subsys (disabled)
10756 12:19:25.211108 <5>[ 0.395498] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10757 12:19:25.217557 <6>[ 0.396211] thermal_sys: Registered thermal governor 'step_wise'
10758 12:19:25.224196 <6>[ 0.403468] thermal_sys: Registered thermal governor 'power_allocator'
10759 12:19:25.227842 <6>[ 0.409725] cpuidle: using governor menu
10760 12:19:25.234433 <6>[ 0.420688] NET: Registered PF_QIPCRTR protocol family
10761 12:19:25.240995 <6>[ 0.426178] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10762 12:19:25.247558 <6>[ 0.433285] ASID allocator initialised with 32768 entries
10763 12:19:25.250571 <6>[ 0.439865] Serial: AMBA PL011 UART driver
10764 12:19:25.260484 <4>[ 0.448657] Trying to register duplicate clock ID: 134
10765 12:19:25.314387 <6>[ 0.505880] KASLR enabled
10766 12:19:25.328980 <6>[ 0.513575] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10767 12:19:25.335062 <6>[ 0.520590] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10768 12:19:25.342176 <6>[ 0.527082] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10769 12:19:25.348645 <6>[ 0.534088] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10770 12:19:25.355006 <6>[ 0.540576] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10771 12:19:25.361569 <6>[ 0.547584] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10772 12:19:25.368271 <6>[ 0.554072] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10773 12:19:25.374664 <6>[ 0.561078] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10774 12:19:25.378008 <6>[ 0.568585] ACPI: Interpreter disabled.
10775 12:19:25.386935 <6>[ 0.575002] iommu: Default domain type: Translated
10776 12:19:25.393448 <6>[ 0.580114] iommu: DMA domain TLB invalidation policy: strict mode
10777 12:19:25.397186 <5>[ 0.586740] SCSI subsystem initialized
10778 12:19:25.403531 <6>[ 0.590910] usbcore: registered new interface driver usbfs
10779 12:19:25.410691 <6>[ 0.596643] usbcore: registered new interface driver hub
10780 12:19:25.413205 <6>[ 0.602195] usbcore: registered new device driver usb
10781 12:19:25.420554 <6>[ 0.608289] pps_core: LinuxPPS API ver. 1 registered
10782 12:19:25.430198 <6>[ 0.613482] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10783 12:19:25.433418 <6>[ 0.622832] PTP clock support registered
10784 12:19:25.436697 <6>[ 0.627075] EDAC MC: Ver: 3.0.0
10785 12:19:25.444055 <6>[ 0.632242] FPGA manager framework
10786 12:19:25.450654 <6>[ 0.635924] Advanced Linux Sound Architecture Driver Initialized.
10787 12:19:25.453885 <6>[ 0.642696] vgaarb: loaded
10788 12:19:25.460430 <6>[ 0.645862] clocksource: Switched to clocksource arch_sys_counter
10789 12:19:25.463855 <5>[ 0.652305] VFS: Disk quotas dquot_6.6.0
10790 12:19:25.470514 <6>[ 0.656493] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10791 12:19:25.473763 <6>[ 0.663682] pnp: PnP ACPI: disabled
10792 12:19:25.482250 <6>[ 0.670319] NET: Registered PF_INET protocol family
10793 12:19:25.491912 <6>[ 0.675913] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10794 12:19:25.503839 <6>[ 0.688241] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10795 12:19:25.513288 <6>[ 0.697061] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10796 12:19:25.519519 <6>[ 0.705036] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10797 12:19:25.529709 <6>[ 0.713736] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10798 12:19:25.536329 <6>[ 0.723493] TCP: Hash tables configured (established 65536 bind 65536)
10799 12:19:25.543008 <6>[ 0.730357] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10800 12:19:25.553075 <6>[ 0.737556] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10801 12:19:25.559701 <6>[ 0.745257] NET: Registered PF_UNIX/PF_LOCAL protocol family
10802 12:19:25.566185 <6>[ 0.751410] RPC: Registered named UNIX socket transport module.
10803 12:19:25.569452 <6>[ 0.757563] RPC: Registered udp transport module.
10804 12:19:25.575920 <6>[ 0.762496] RPC: Registered tcp transport module.
10805 12:19:25.582418 <6>[ 0.767429] RPC: Registered tcp NFSv4.1 backchannel transport module.
10806 12:19:25.585667 <6>[ 0.774095] PCI: CLS 0 bytes, default 64
10807 12:19:25.588687 <6>[ 0.778447] Unpacking initramfs...
10808 12:19:25.613288 <6>[ 0.797950] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10809 12:19:25.622830 <6>[ 0.806612] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10810 12:19:25.626146 <6>[ 0.815474] kvm [1]: IPA Size Limit: 40 bits
10811 12:19:25.632731 <6>[ 0.820002] kvm [1]: GICv3: no GICV resource entry
10812 12:19:25.636010 <6>[ 0.825026] kvm [1]: disabling GICv2 emulation
10813 12:19:25.642906 <6>[ 0.829713] kvm [1]: GIC system register CPU interface enabled
10814 12:19:25.646243 <6>[ 0.835875] kvm [1]: vgic interrupt IRQ18
10815 12:19:25.652777 <6>[ 0.840232] kvm [1]: VHE mode initialized successfully
10816 12:19:25.659227 <5>[ 0.846649] Initialise system trusted keyrings
10817 12:19:25.665654 <6>[ 0.851433] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10818 12:19:25.673392 <6>[ 0.861338] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10819 12:19:25.679986 <5>[ 0.867728] NFS: Registering the id_resolver key type
10820 12:19:25.682782 <5>[ 0.873028] Key type id_resolver registered
10821 12:19:25.689724 <5>[ 0.877447] Key type id_legacy registered
10822 12:19:25.696095 <6>[ 0.881729] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10823 12:19:25.702686 <6>[ 0.888653] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10824 12:19:25.709802 <6>[ 0.896355] 9p: Installing v9fs 9p2000 file system support
10825 12:19:25.746032 <5>[ 0.934421] Key type asymmetric registered
10826 12:19:25.749675 <5>[ 0.938752] Asymmetric key parser 'x509' registered
10827 12:19:25.759757 <6>[ 0.943893] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10828 12:19:25.762921 <6>[ 0.951512] io scheduler mq-deadline registered
10829 12:19:25.765960 <6>[ 0.956304] io scheduler kyber registered
10830 12:19:25.785270 <6>[ 0.973402] EINJ: ACPI disabled.
10831 12:19:25.817663 <4>[ 0.998762] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10832 12:19:25.827045 <4>[ 1.009377] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10833 12:19:25.841983 <6>[ 1.029959] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10834 12:19:25.850193 <6>[ 1.037977] printk: console [ttyS0] disabled
10835 12:19:25.877746 <6>[ 1.062619] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10836 12:19:25.884413 <6>[ 1.072090] printk: console [ttyS0] enabled
10837 12:19:25.887493 <6>[ 1.072090] printk: console [ttyS0] enabled
10838 12:19:25.894165 <6>[ 1.080984] printk: bootconsole [mtk8250] disabled
10839 12:19:25.897609 <6>[ 1.080984] printk: bootconsole [mtk8250] disabled
10840 12:19:25.904051 <6>[ 1.092263] SuperH (H)SCI(F) driver initialized
10841 12:19:25.907491 <6>[ 1.097552] msm_serial: driver initialized
10842 12:19:25.921794 <6>[ 1.106530] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10843 12:19:25.931580 <6>[ 1.115075] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10844 12:19:25.938240 <6>[ 1.123618] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10845 12:19:25.948024 <6>[ 1.132247] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10846 12:19:25.958193 <6>[ 1.140953] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10847 12:19:25.964794 <6>[ 1.149667] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10848 12:19:25.974798 <6>[ 1.158214] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10849 12:19:25.981092 <6>[ 1.167014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10850 12:19:25.990849 <6>[ 1.175557] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10851 12:19:26.002793 <6>[ 1.190897] loop: module loaded
10852 12:19:26.009046 <6>[ 1.196864] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10853 12:19:26.032049 <4>[ 1.220282] mtk-pmic-keys: Failed to locate of_node [id: -1]
10854 12:19:26.038874 <6>[ 1.227352] megasas: 07.719.03.00-rc1
10855 12:19:26.048705 <6>[ 1.237163] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10856 12:19:26.056993 <6>[ 1.245251] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10857 12:19:26.073941 <6>[ 1.261832] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10858 12:19:26.134169 <6>[ 1.315729] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10859 12:19:29.570005 <6>[ 4.759246] Freeing initrd memory: 96020K
10860 12:19:29.580415 <6>[ 4.769496] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10861 12:19:29.591280 <6>[ 4.780500] tun: Universal TUN/TAP device driver, 1.6
10862 12:19:29.594556 <6>[ 4.786597] thunder_xcv, ver 1.0
10863 12:19:29.597945 <6>[ 4.790102] thunder_bgx, ver 1.0
10864 12:19:29.601745 <6>[ 4.793590] nicpf, ver 1.0
10865 12:19:29.612015 <6>[ 4.797625] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10866 12:19:29.615313 <6>[ 4.805100] hns3: Copyright (c) 2017 Huawei Corporation.
10867 12:19:29.621767 <6>[ 4.810691] hclge is initializing
10868 12:19:29.625732 <6>[ 4.814272] e1000: Intel(R) PRO/1000 Network Driver
10869 12:19:29.631822 <6>[ 4.819401] e1000: Copyright (c) 1999-2006 Intel Corporation.
10870 12:19:29.635136 <6>[ 4.825419] e1000e: Intel(R) PRO/1000 Network Driver
10871 12:19:29.641673 <6>[ 4.830635] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10872 12:19:29.648213 <6>[ 4.836821] igb: Intel(R) Gigabit Ethernet Network Driver
10873 12:19:29.654615 <6>[ 4.842471] igb: Copyright (c) 2007-2014 Intel Corporation.
10874 12:19:29.661415 <6>[ 4.848308] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10875 12:19:29.668074 <6>[ 4.854826] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10876 12:19:29.671455 <6>[ 4.861301] sky2: driver version 1.30
10877 12:19:29.678290 <6>[ 4.866316] VFIO - User Level meta-driver version: 0.3
10878 12:19:29.685611 <6>[ 4.874601] usbcore: registered new interface driver usb-storage
10879 12:19:29.692041 <6>[ 4.881045] usbcore: registered new device driver onboard-usb-hub
10880 12:19:29.701111 <6>[ 4.890191] mt6397-rtc mt6359-rtc: registered as rtc0
10881 12:19:29.711028 <6>[ 4.895656] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:19:30 UTC (1698409170)
10882 12:19:29.714421 <6>[ 4.905227] i2c_dev: i2c /dev entries driver
10883 12:19:29.731126 <6>[ 4.916983] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10884 12:19:29.751432 <6>[ 4.939985] cpu cpu0: EM: created perf domain
10885 12:19:29.754785 <6>[ 4.944925] cpu cpu4: EM: created perf domain
10886 12:19:29.761738 <6>[ 4.950526] sdhci: Secure Digital Host Controller Interface driver
10887 12:19:29.768776 <6>[ 4.956958] sdhci: Copyright(c) Pierre Ossman
10888 12:19:29.774766 <6>[ 4.961920] Synopsys Designware Multimedia Card Interface Driver
10889 12:19:29.781724 <6>[ 4.968552] sdhci-pltfm: SDHCI platform and OF driver helper
10890 12:19:29.784502 <6>[ 4.968699] mmc0: CQHCI version 5.10
10891 12:19:29.791341 <6>[ 4.978911] ledtrig-cpu: registered to indicate activity on CPUs
10892 12:19:29.798276 <6>[ 4.985967] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10893 12:19:29.804630 <6>[ 4.993017] usbcore: registered new interface driver usbhid
10894 12:19:29.808031 <6>[ 4.998842] usbhid: USB HID core driver
10895 12:19:29.818008 <6>[ 5.003054] spi_master spi0: will run message pump with realtime priority
10896 12:19:29.861236 <6>[ 5.043582] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10897 12:19:29.880213 <6>[ 5.059282] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10898 12:19:29.883553 <6>[ 5.072918] mmc0: Command Queue Engine enabled
10899 12:19:29.890166 <6>[ 5.077739] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10900 12:19:29.896784 <6>[ 5.085041] mmcblk0: mmc0:0001 DA4128 116 GiB
10901 12:19:29.903678 <6>[ 5.089993] cros-ec-spi spi0.0: Chrome EC device registered
10902 12:19:29.907098 <6>[ 5.093894] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10903 12:19:29.914511 <6>[ 5.103662] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10904 12:19:29.921369 <6>[ 5.109554] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10905 12:19:29.927845 <6>[ 5.115875] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10906 12:19:29.945755 <6>[ 5.131085] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10907 12:19:29.953025 <6>[ 5.141700] NET: Registered PF_PACKET protocol family
10908 12:19:29.959262 <6>[ 5.147138] 9pnet: Installing 9P2000 support
10909 12:19:29.962769 <5>[ 5.151716] Key type dns_resolver registered
10910 12:19:29.965795 <6>[ 5.156761] registered taskstats version 1
10911 12:19:29.972314 <5>[ 5.161151] Loading compiled-in X.509 certificates
10912 12:19:30.002834 <4>[ 5.185304] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10913 12:19:30.012777 <4>[ 5.196016] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10914 12:19:30.019516 <3>[ 5.206561] debugfs: File 'uA_load' in directory '/' already present!
10915 12:19:30.025890 <3>[ 5.213265] debugfs: File 'min_uV' in directory '/' already present!
10916 12:19:30.032609 <3>[ 5.219873] debugfs: File 'max_uV' in directory '/' already present!
10917 12:19:30.039165 <3>[ 5.226479] debugfs: File 'constraint_flags' in directory '/' already present!
10918 12:19:30.050412 <3>[ 5.236064] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10919 12:19:30.059376 <6>[ 5.248731] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10920 12:19:30.066349 <6>[ 5.255584] xhci-mtk 11200000.usb: xHCI Host Controller
10921 12:19:30.073643 <6>[ 5.261110] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10922 12:19:30.083370 <6>[ 5.268970] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10923 12:19:30.089795 <6>[ 5.278388] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10924 12:19:30.096373 <6>[ 5.284456] xhci-mtk 11200000.usb: xHCI Host Controller
10925 12:19:30.103084 <6>[ 5.289932] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10926 12:19:30.109527 <6>[ 5.297577] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10927 12:19:30.116234 <6>[ 5.305281] hub 1-0:1.0: USB hub found
10928 12:19:30.119473 <6>[ 5.309289] hub 1-0:1.0: 1 port detected
10929 12:19:30.129734 <6>[ 5.313556] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10930 12:19:30.133069 <6>[ 5.322196] hub 2-0:1.0: USB hub found
10931 12:19:30.136156 <6>[ 5.326217] hub 2-0:1.0: 1 port detected
10932 12:19:30.145418 <6>[ 5.334530] mtk-msdc 11f70000.mmc: Got CD GPIO
10933 12:19:30.157217 <6>[ 5.342694] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10934 12:19:30.164042 <6>[ 5.350720] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10935 12:19:30.173436 <4>[ 5.358629] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10936 12:19:30.183271 <6>[ 5.368158] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10937 12:19:30.189973 <6>[ 5.376234] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10938 12:19:30.196469 <6>[ 5.384370] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10939 12:19:30.206756 <6>[ 5.392293] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10940 12:19:30.213067 <6>[ 5.400110] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10941 12:19:30.223438 <6>[ 5.407927] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10942 12:19:30.232840 <6>[ 5.418452] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10943 12:19:30.242680 <6>[ 5.426830] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10944 12:19:30.249701 <6>[ 5.435169] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10945 12:19:30.259039 <6>[ 5.443507] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10946 12:19:30.265435 <6>[ 5.451848] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10947 12:19:30.275418 <6>[ 5.460186] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10948 12:19:30.282109 <6>[ 5.468525] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10949 12:19:30.292209 <6>[ 5.476872] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10950 12:19:30.298725 <6>[ 5.485211] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10951 12:19:30.308250 <6>[ 5.493549] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10952 12:19:30.314816 <6>[ 5.501888] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10953 12:19:30.325019 <6>[ 5.510226] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10954 12:19:30.331286 <6>[ 5.518565] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10955 12:19:30.341085 <6>[ 5.526904] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10956 12:19:30.351342 <6>[ 5.535244] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10957 12:19:30.357591 <6>[ 5.543990] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10958 12:19:30.364086 <6>[ 5.551131] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10959 12:19:30.370727 <6>[ 5.557902] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10960 12:19:30.377250 <6>[ 5.564662] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10961 12:19:30.384688 <6>[ 5.571603] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10962 12:19:30.393846 <6>[ 5.578454] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10963 12:19:30.404051 <6>[ 5.587592] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10964 12:19:30.413817 <6>[ 5.596712] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10965 12:19:30.420515 <6>[ 5.606007] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10966 12:19:30.430164 <6>[ 5.615475] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10967 12:19:30.440100 <6>[ 5.624943] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10968 12:19:30.449793 <6>[ 5.634064] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10969 12:19:30.459680 <6>[ 5.643534] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10970 12:19:30.466716 <6>[ 5.652653] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10971 12:19:30.479573 <6>[ 5.661949] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10972 12:19:30.489500 <6>[ 5.672110] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10973 12:19:30.499500 <6>[ 5.683698] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10974 12:19:30.544231 <6>[ 5.730125] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10975 12:19:30.699001 <6>[ 5.888082] hub 1-1:1.0: USB hub found
10976 12:19:30.702697 <6>[ 5.892601] hub 1-1:1.0: 4 ports detected
10977 12:19:30.824656 <6>[ 6.010241] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10978 12:19:30.851251 <6>[ 6.040036] hub 2-1:1.0: USB hub found
10979 12:19:30.854598 <6>[ 6.044547] hub 2-1:1.0: 3 ports detected
10980 12:19:31.024725 <6>[ 6.210187] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10981 12:19:31.155520 <6>[ 6.344544] hub 1-1.1:1.0: USB hub found
10982 12:19:31.159291 <6>[ 6.348895] hub 1-1.1:1.0: 4 ports detected
10983 12:19:31.272797 <6>[ 6.458226] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10984 12:19:31.405350 <6>[ 6.593959] hub 1-1.4:1.0: USB hub found
10985 12:19:31.408828 <6>[ 6.598632] hub 1-1.4:1.0: 2 ports detected
10986 12:19:31.488154 <6>[ 6.674023] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10987 12:19:31.676079 <6>[ 6.862125] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10988 12:19:31.761521 <3>[ 6.950431] usb 1-1.1.4: device descriptor read/64, error -32
10989 12:19:31.953467 <3>[ 7.142342] usb 1-1.1.4: device descriptor read/64, error -32
10990 12:19:32.148207 <6>[ 7.334150] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10991 12:19:32.336127 <6>[ 7.522159] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10992 12:19:32.421108 <3>[ 7.610337] usb 1-1.1.4: device descriptor read/64, error -32
10993 12:19:32.612972 <3>[ 7.802384] usb 1-1.1.4: device descriptor read/64, error -32
10994 12:19:32.725226 <6>[ 7.914747] usb 1-1.1-port4: attempt power cycle
10995 12:19:32.811926 <6>[ 7.998188] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10996 12:19:33.335969 <6>[ 8.522201] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10997 12:19:33.343189 <4>[ 8.529698] usb 1-1.1.4: Device not responding to setup address.
10998 12:19:33.553220 <4>[ 8.742494] usb 1-1.1.4: Device not responding to setup address.
10999 12:19:33.764940 <3>[ 8.954225] usb 1-1.1.4: device not accepting address 10, error -71
11000 12:19:33.852080 <6>[ 9.038196] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
11001 12:19:33.858697 <4>[ 9.045693] usb 1-1.1.4: Device not responding to setup address.
11002 12:19:34.068980 <4>[ 9.258428] usb 1-1.1.4: Device not responding to setup address.
11003 12:19:34.280827 <3>[ 9.470181] usb 1-1.1.4: device not accepting address 11, error -71
11004 12:19:34.288179 <3>[ 9.477248] usb 1-1.1-port4: unable to enumerate USB device
11005 12:19:42.773592 <6>[ 17.967263] ALSA device list:
11006 12:19:42.780306 <6>[ 17.970563] No soundcards found.
11007 12:19:42.788074 <6>[ 17.978696] Freeing unused kernel memory: 8384K
11008 12:19:42.791871 <6>[ 17.983695] Run /init as init process
11009 12:19:42.841719 <6>[ 18.032476] NET: Registered PF_INET6 protocol family
11010 12:19:42.848406 <6>[ 18.039034] Segment Routing with IPv6
11011 12:19:42.851570 <6>[ 18.043001] In-situ OAM (IOAM) with IPv6
11012 12:19:42.886901 <30>[ 18.056954] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
11013 12:19:42.889703 <30>[ 18.080820] systemd[1]: Detected architecture arm64.
11014 12:19:42.889793
11015 12:19:42.896627 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
11016 12:19:42.896710
11017 12:19:42.911854 <30>[ 18.102220] systemd[1]: Set hostname to <debian-bullseye-arm64>.
11018 12:19:43.073619 <30>[ 18.260872] systemd[1]: Queued start job for default target Graphical Interface.
11019 12:19:43.116770 <30>[ 18.307027] systemd[1]: Created slice system-getty.slice.
11020 12:19:43.123011 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
11021 12:19:43.140424 <30>[ 18.330656] systemd[1]: Created slice system-modprobe.slice.
11022 12:19:43.146722 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
11023 12:19:43.164857 <30>[ 18.355449] systemd[1]: Created slice system-serial\x2dgetty.slice.
11024 12:19:43.175205 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
11025 12:19:43.188654 <30>[ 18.378724] systemd[1]: Created slice User and Session Slice.
11026 12:19:43.194850 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
11027 12:19:43.215772 <30>[ 18.402889] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
11028 12:19:43.225739 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
11029 12:19:43.243593 <30>[ 18.430880] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
11030 12:19:43.250416 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
11031 12:19:43.274177 <30>[ 18.458275] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
11032 12:19:43.280806 <30>[ 18.470453] systemd[1]: Reached target Local Encrypted Volumes.
11033 12:19:43.287552 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
11034 12:19:43.304718 <30>[ 18.494697] systemd[1]: Reached target Paths.
11035 12:19:43.307793 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
11036 12:19:43.324058 <30>[ 18.514193] systemd[1]: Reached target Remote File Systems.
11037 12:19:43.330902 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
11038 12:19:43.344142 <30>[ 18.534138] systemd[1]: Reached target Slices.
11039 12:19:43.347214 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
11040 12:19:43.364395 <30>[ 18.554175] systemd[1]: Reached target Swap.
11041 12:19:43.367259 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
11042 12:19:43.387964 <30>[ 18.574674] systemd[1]: Listening on initctl Compatibility Named Pipe.
11043 12:19:43.394545 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
11044 12:19:43.410126 <30>[ 18.599708] systemd[1]: Listening on Journal Audit Socket.
11045 12:19:43.416287 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
11046 12:19:43.433155 <30>[ 18.623368] systemd[1]: Listening on Journal Socket (/dev/log).
11047 12:19:43.440233 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
11048 12:19:43.457322 <30>[ 18.647433] systemd[1]: Listening on Journal Socket.
11049 12:19:43.464248 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
11050 12:19:43.476980 <30>[ 18.666801] systemd[1]: Listening on udev Control Socket.
11051 12:19:43.483327 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
11052 12:19:43.501348 <30>[ 18.691279] systemd[1]: Listening on udev Kernel Socket.
11053 12:19:43.508240 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11054 12:19:43.548791 <30>[ 18.738322] systemd[1]: Mounting Huge Pages File System...
11055 12:19:43.555289 Mounting [0;1;39mHuge Pages File System[0m...
11056 12:19:43.572534 <30>[ 18.762420] systemd[1]: Mounting POSIX Message Queue File System...
11057 12:19:43.579111 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11058 12:19:43.600723 <30>[ 18.790553] systemd[1]: Mounting Kernel Debug File System...
11059 12:19:43.607195 Mounting [0;1;39mKernel Debug File System[0m...
11060 12:19:43.623541 <30>[ 18.810485] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11061 12:19:43.672243 <30>[ 18.858627] systemd[1]: Starting Create list of static device nodes for the current kernel...
11062 12:19:43.678917 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11063 12:19:43.700814 <30>[ 18.890895] systemd[1]: Starting Load Kernel Module configfs...
11064 12:19:43.707543 Starting [0;1;39mLoad Kernel Module configfs[0m...
11065 12:19:43.722301 <30>[ 18.912508] systemd[1]: Starting Load Kernel Module drm...
11066 12:19:43.728874 Starting [0;1;39mLoad Kernel Module drm[0m...
11067 12:19:43.747765 <30>[ 18.934549] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11068 12:19:43.788883 <30>[ 18.978666] systemd[1]: Starting Journal Service...
11069 12:19:43.791885 Starting [0;1;39mJournal Service[0m...
11070 12:19:43.810984 <30>[ 19.001180] systemd[1]: Starting Load Kernel Modules...
11071 12:19:43.817594 Starting [0;1;39mLoad Kernel Modules[0m...
11072 12:19:43.837569 <30>[ 19.024383] systemd[1]: Starting Remount Root and Kernel File Systems...
11073 12:19:43.844395 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11074 12:19:43.859573 <30>[ 19.049567] systemd[1]: Starting Coldplug All udev Devices...
11075 12:19:43.865842 Starting [0;1;39mColdplug All udev Devices[0m...
11076 12:19:43.882759 <30>[ 19.072938] systemd[1]: Started Journal Service.
11077 12:19:43.889320 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11078 12:19:43.906190 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11079 12:19:43.924872 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11080 12:19:43.941595 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11081 12:19:43.962181 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11082 12:19:43.978764 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11083 12:19:43.999675 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11084 12:19:44.019063 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11085 12:19:44.038612 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11086 12:19:44.052309 See 'systemctl status systemd-remount-fs.service' for details.
11087 12:19:44.101705 Mounting [0;1;39mKernel Configuration File System[0m...
11088 12:19:44.119488 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11089 12:19:44.132757 <46>[ 19.319713] systemd-journald[180]: Received client request to flush runtime journal.
11090 12:19:44.142307 Starting [0;1;39mLoad/Save Random Seed[0m...
11091 12:19:44.160100 Starting [0;1;39mApply Kernel Variables[0m...
11092 12:19:44.184781 Starting [0;1;39mCreate System Users[0m...
11093 12:19:44.204194 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11094 12:19:44.220619 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11095 12:19:44.241803 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11096 12:19:44.262419 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11097 12:19:44.282120 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11098 12:19:44.302241 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11099 12:19:44.349458 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11100 12:19:44.368167 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11101 12:19:44.380868 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11102 12:19:44.395729 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11103 12:19:44.440572 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11104 12:19:44.468579 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11105 12:19:44.489052 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11106 12:19:44.509215 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11107 12:19:44.522268 Starting [0;1;39mNetwork Time Synchronization[0m...
11108 12:19:44.542148 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11109 12:19:44.570569 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11110 12:19:44.598324 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11111 12:19:44.617597 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11112 12:19:44.636551 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11113 12:19:44.646777 <6>[ 19.833157] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11114 12:19:44.653350 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11115 12:19:44.666735 <6>[ 19.856882] remoteproc remoteproc0: scp is available
11116 12:19:44.676394 [[0;32m OK [0m] Reached targ<6>[ 19.865692] remoteproc remoteproc0: powering up scp
11117 12:19:44.686483 et [0;1;39mSyst<6>[ 19.871486] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11118 12:19:44.693050 em Time Synchron<6>[ 19.880959] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11119 12:19:44.693640 ized[0m.
11120 12:19:44.699552 <6>[ 19.883901] mc: Linux media interface: v0.10
11121 12:19:44.712959 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once <6>[ 19.898996] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11122 12:19:44.713390 a week[0m.
11123 12:19:44.722996 <6>[ 19.907772] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11124 12:19:44.729685 <6>[ 19.917506] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11125 12:19:44.737069 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11126 12:19:44.743715 <4>[ 19.931827] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11127 12:19:44.755862 <3>[ 19.942593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11128 12:19:44.762466 <4>[ 19.947018] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11129 12:19:44.772271 <6>[ 19.948446] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11130 12:19:44.778622 <3>[ 19.951406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11131 12:19:44.788921 <4>[ 19.971677] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11132 12:19:44.792399 <4>[ 19.971677] Fallback method does not support PEC.
11133 12:19:44.802201 <3>[ 19.974062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11134 12:19:44.805487 <6>[ 19.979500] usbcore: registered new interface driver r8152
11135 12:19:44.815594 <6>[ 19.997142] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11136 12:19:44.821609 <6>[ 20.002501] videodev: Linux video capture interface: v2.00
11137 12:19:44.831784 <3>[ 20.009177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11138 12:19:44.838283 <3>[ 20.009241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11139 12:19:44.848088 <3>[ 20.009257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11140 12:19:44.854529 <3>[ 20.009270] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11141 12:19:44.861305 <3>[ 20.009279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11142 12:19:44.871379 <3>[ 20.015531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11143 12:19:44.881223 <6>[ 20.017824] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11144 12:19:44.887696 <6>[ 20.017832] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11145 12:19:44.894345 <6>[ 20.018634] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11146 12:19:44.904122 <3>[ 20.029241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11147 12:19:44.910989 <6>[ 20.033927] remoteproc remoteproc0: remote processor scp is now up
11148 12:19:44.917302 <6>[ 20.047228] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11149 12:19:44.924397 <3>[ 20.050499] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11150 12:19:44.930418 <6>[ 20.058746] pci_bus 0000:00: root bus resource [bus 00-ff]
11151 12:19:44.940473 <3>[ 20.066302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11152 12:19:44.946704 <3>[ 20.066399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11153 12:19:44.953490 <6>[ 20.066612] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
11154 12:19:44.960066 <6>[ 20.074926] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11155 12:19:44.970030 <3>[ 20.081919] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11156 12:19:44.976413 <3>[ 20.081924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11157 12:19:44.986394 <3>[ 20.081932] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11158 12:19:44.993348 <3>[ 20.081939] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11159 12:19:45.002988 <3>[ 20.081998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11160 12:19:45.013008 <6>[ 20.090996] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11161 12:19:45.019375 <6>[ 20.134528] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11162 12:19:45.025862 <6>[ 20.142581] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11163 12:19:45.029105 <6>[ 20.190487] Bluetooth: Core ver 2.22
11164 12:19:45.039157 <6>[ 20.197287] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11165 12:19:45.045921 <6>[ 20.198095] usbcore: registered new interface driver cdc_ether
11166 12:19:45.052819 <4>[ 20.205993] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11167 12:19:45.062405 <4>[ 20.205999] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11168 12:19:45.068924 <6>[ 20.207287] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11169 12:19:45.076114 <6>[ 20.207292] NET: Registered PF_BLUETOOTH protocol family
11170 12:19:45.082242 <6>[ 20.207298] Bluetooth: HCI device and connection manager initialized
11171 12:19:45.088983 <6>[ 20.207323] Bluetooth: HCI socket layer initialized
11172 12:19:45.092264 <6>[ 20.207329] Bluetooth: L2CAP socket layer initialized
11173 12:19:45.099106 <6>[ 20.207346] Bluetooth: SCO socket layer initialized
11174 12:19:45.102374 <6>[ 20.216597] pci 0000:00:00.0: supports D1 D2
11175 12:19:45.108853 <6>[ 20.217014] usbcore: registered new interface driver r8153_ecm
11176 12:19:45.115379 <6>[ 20.236070] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11177 12:19:45.125841 <6>[ 20.240147] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11178 12:19:45.132261 <6>[ 20.241569] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11179 12:19:45.138710 <6>[ 20.242797] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11180 12:19:45.152225 <6>[ 20.243975] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11181 12:19:45.158453 <6>[ 20.244081] usbcore: registered new interface driver uvcvideo
11182 12:19:45.161789 <6>[ 20.258239] r8152 1-1.1.1:1.0 eth0: v1.12.13
11183 12:19:45.168281 <6>[ 20.259026] usbcore: registered new interface driver btusb
11184 12:19:45.175486 <6>[ 20.259191] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11185 12:19:45.184980 <4>[ 20.259899] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11186 12:19:45.191501 <3>[ 20.259919] Bluetooth: hci0: Failed to load firmware file (-2)
11187 12:19:45.198189 <3>[ 20.259923] Bluetooth: hci0: Failed to set up firmware (-2)
11188 12:19:45.207893 <4>[ 20.259930] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11189 12:19:45.214828 <6>[ 20.266086] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11190 12:19:45.221812 <6>[ 20.281270] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
11191 12:19:45.228354 <6>[ 20.283281] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11192 12:19:45.234856 [[0;32m OK [<6>[ 20.422987] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11193 12:19:45.244925 0m] Listening on<6>[ 20.431970] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11194 12:19:45.251704 [0;1;39mD-Bus <6>[ 20.440860] pci 0000:01:00.0: supports D1 D2
11195 12:19:45.258003 <6>[ 20.446700] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11196 12:19:45.261505 System Message Bus Socket[0m.
11197 12:19:45.271866 <3>[ 20.458872] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11198 12:19:45.282360 <3>[ 20.459734] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11199 12:19:45.288308 <6>[ 20.467827] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11200 12:19:45.295003 <6>[ 20.483123] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11201 12:19:45.304898 <6>[ 20.483127] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11202 12:19:45.311505 <6>[ 20.483135] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11203 12:19:45.318828 <6>[ 20.483147] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11204 12:19:45.329218 <6>[ 20.483160] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11205 12:19:45.335560 [[0;32m OK [<6>[ 20.483172] pci 0000:00:00.0: PCI bridge to [bus 01]
11206 12:19:45.345233 0m] Reached targ<6>[ 20.483176] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11207 12:19:45.355462 et [0;1;39mSock<3>[ 20.515625] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11208 12:19:45.356018 ets[0m.
11209 12:19:45.362470 <3>[ 20.516789] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
11210 12:19:45.368254 <6>[ 20.523457] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11211 12:19:45.378123 <3>[ 20.528213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11212 12:19:45.384744 <3>[ 20.558586] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11213 12:19:45.391512 <6>[ 20.565470] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11214 12:19:45.399046 [[0;32m OK [<6>[ 20.589227] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11215 12:19:45.409079 <3>[ 20.595462] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11216 12:19:45.411782 0m] Reached target [0;1;39mBasic System[0m.
11217 12:19:45.421876 <5>[ 20.609364] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11218 12:19:45.439061 <5>[ 20.629315] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11219 12:19:45.449054 <4>[ 20.636325] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11220 12:19:45.455778 <6>[ 20.645224] cfg80211: failed to load regulatory.db
11221 12:19:45.465285 <3>[ 20.652234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11222 12:19:45.472052 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11223 12:19:45.499381 <3>[ 20.686270] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11224 12:19:45.512418 Startin<6>[ 20.700229] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11225 12:19:45.519705 g [0;1;39mUser <6>[ 20.708484] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11226 12:19:45.529011 Login Management<3>[ 20.715452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11227 12:19:45.532136 [0m...
11228 12:19:45.545366 <6>[ 20.736345] mt7921e 0000:01:00.0: ASIC revision: 79610010
11229 12:19:45.555105 Starting [0;1;39mPermit User Sessions[0m...
11230 12:19:45.576054 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11231 12:19:45.610616 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11232 12:19:45.631530 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11233 12:19:45.655362 <4>[ 20.839449] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11234 12:19:45.762735 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11235 12:19:45.778616 <4>[ 20.962934] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11236 12:19:45.785751 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11237 12:19:45.803529 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11238 12:19:45.860275 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11239 12:19:45.883374 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11240 12:19:45.898954 <4>[ 21.083264] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11241 12:19:45.907461 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11242 12:19:45.928919 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11243 12:19:45.944314 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11244 12:19:45.996669 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11245 12:19:46.027636 Startin<4>[ 21.212724] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11246 12:19:46.034024 g [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11247 12:19:46.060097 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11248 12:19:46.129941 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11249 12:19:46.155111 <4>[ 21.339074] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11250 12:19:46.161773 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11251 12:19:46.190242 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11252 12:19:46.206057
11253 12:19:46.206145
11254 12:19:46.209412 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11255 12:19:46.209494
11256 12:19:46.212950 debian-bullseye-arm64 login: root (automatic login)
11257 12:19:46.213032
11258 12:19:46.213098
11259 12:19:46.228416 Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64
11260 12:19:46.228506
11261 12:19:46.235414 The programs included with the Debian GNU/Linux system are free software;
11262 12:19:46.241753 the exact distribution terms for each program are described in the
11263 12:19:46.244867 individual files in /usr/share/doc/*/copyright.
11264 12:19:46.244949
11265 12:19:46.251193 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11266 12:19:46.254796 permitted by applicable law.
11267 12:19:46.255188 Matched prompt #10: / #
11269 12:19:46.255397 Setting prompt string to ['/ #']
11270 12:19:46.255488 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11272 12:19:46.255676 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11273 12:19:46.255808 start: 2.2.6 expect-shell-connection (timeout 00:03:00) [common]
11274 12:19:46.255878 Setting prompt string to ['/ #']
11275 12:19:46.255938 Forcing a shell prompt, looking for ['/ #']
11277 12:19:46.306121 / #
11278 12:19:46.306229 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11279 12:19:46.306304 Waiting using forced prompt support (timeout 00:02:30)
11280 12:19:46.306399 <4>[ 21.462232] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11281 12:19:46.311349
11282 12:19:46.311648 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11283 12:19:46.311807 start: 2.2.7 export-device-env (timeout 00:03:00) [common]
11284 12:19:46.311907 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11285 12:19:46.312002 end: 2.2 depthcharge-retry (duration 00:02:00) [common]
11286 12:19:46.312088 end: 2 depthcharge-action (duration 00:02:00) [common]
11287 12:19:46.312176 start: 3 lava-test-retry (timeout 00:05:00) [common]
11288 12:19:46.312264 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11289 12:19:46.312338 Using namespace: common
11291 12:19:46.412681 / # #
11292 12:19:46.412829 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11293 12:19:46.412940 #<4>[ 21.587347] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11294 12:19:46.419108
11295 12:19:46.419372 Using /lava-11893112
11297 12:19:46.519709 / # export SHELL=/bin/sh
11298 12:19:46.563821 export SHELL=/bin/sh<4>[ 21.711208] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11299 12:19:46.563957
11301 12:19:46.664502 / # . /lava-11893112/environment
11302 12:19:46.664692 . /lava-11893112/environment<4>[ 21.831208] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11303 12:19:46.669611
11305 12:19:46.770147 / # /lava-11893112/bin/lava-test-runner /lava-11893112/0
11306 12:19:46.770290 Test shell timeout: 10s (minimum of the action and connection timeout)
11307 12:19:46.771213 /lava-11893112/bin/lava-test-runner /lava-11893112/0<4>[ 21.955190] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11308 12:19:46.811808
11309 12:19:46.811902 + export TESTRUN_ID=0_sleep
11310 12:19:46.811969 + cd /lava-11893112/0/tests/0_sleep
11311 12:19:46.812030 + cat uuid
11312 12:19:46.812088 + UUID=11893112_1.5.2.3.1
11313 12:19:46.812145 + set +x
11314 12:19:46.818462 <LAVA_SIGNAL_STARTRUN 0_sleep 11893112_1.5.2.3.1>
11315 12:19:46.818720 Received signal: <STARTRUN> 0_sleep 11893112_1.5.2.3.1
11316 12:19:46.818795 Starting test lava.0_sleep (11893112_1.5.2.3.1)
11317 12:19:46.818881 Skipping test definition patterns.
11318 12:19:46.821872 + ./config/lava/sleep/sleep.sh mem freeze
11319 12:19:46.825350 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11321 12:19:46.828418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11322 12:19:46.831828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11323 12:19:46.832077 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11325 12:19:46.834992 rtcwake: assuming RTC uses UTC ...
11326 12:19:46.844852 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:19:53<6>[ 22.036708] PM: suspend entry (deep)
11327 12:19:46.844934 2023
11328 12:19:46.852086 <6>[ 22.040825] Filesystems sync: 0.000 seconds
11329 12:19:46.857814 <6>[ 22.048578] Freezing user space processes
11330 12:19:46.864397 <6>[ 22.054838] Freezing user space processes completed (elapsed 0.001 seconds)
11331 12:19:46.871506 <6>[ 22.062080] OOM killer disabled.
11332 12:19:46.874613 <6>[ 22.065565] Freezing remaining freezable tasks
11333 12:19:46.884780 <6>[ 22.072221] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11334 12:19:46.888112 <3>[ 22.075503] mt7921e 0000:01:00.0: hardware init failed
11335 12:19:46.897607 <6>[ 22.079945] printk: Suspending console(s) (use no_console_suspend to debug)
11336 12:19:50.236780 <3>[ 25.166172] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11337 12:19:50.246108 <3>[ 25.166200] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11338 12:19:50.256250 <3>[ 25.166237] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11339 12:19:50.263042 <3>[ 25.166274] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11340 12:19:50.273066 <3>[ 25.166551] PM: Some devices failed to suspend, or early wake event detected
11341 12:19:50.279626 <4>[ 25.180526] typec port0-partner: PM: parent port0 should not be sleeping
11342 12:19:50.286302 <4>[ 25.197241] typec port0-cable: PM: parent port0 should not be sleeping
11343 12:19:50.289724 <6>[ 25.481396] OOM killer enabled.
11344 12:19:50.296383 <6>[ 25.484809] Restarting tasks ... done.
11345 12:19:50.299547 <5>[ 25.491589] random: crng reseeded on system resumption
11346 12:19:50.303344 <6>[ 25.497823] PM: suspend exit
11347 12:19:50.306618 rtcwake: write error
11348 12:19:50.314610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=fail>
11349 12:19:50.314870 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=fail
11351 12:19:50.317995 rtcwake: assuming RTC uses UTC ...
11352 12:19:50.324665 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:19:56 2023
11353 12:19:50.337749 <6>[ 25.528911] PM: suspend entry (deep)
11354 12:19:50.340762 <6>[ 25.532805] Filesystems sync: 0.000 seconds
11355 12:19:50.344230 <6>[ 25.537857] Freezing user space processes
11356 12:19:50.355919 <6>[ 25.543797] Freezing user space processes completed (elapsed 0.001 seconds)
11357 12:19:50.359167 <6>[ 25.551021] OOM killer disabled.
11358 12:19:50.362477 <6>[ 25.554503] Freezing remaining freezable tasks
11359 12:19:50.373951 <6>[ 25.562121] usb 1-1.1.4: new full-speed USB device number 12 using xhci-mtk
11360 12:19:50.458890 <3>[ 25.650165] usb 1-1.1.4: device descriptor read/64, error -32
11361 12:19:50.650998 <3>[ 25.842089] usb 1-1.1.4: device descriptor read/64, error -32
11362 12:19:50.846537 <6>[ 26.034182] usb 1-1.1.4: new full-speed USB device number 13 using xhci-mtk
11363 12:19:50.930699 <3>[ 26.122097] usb 1-1.1.4: device descriptor read/64, error -32
11364 12:19:51.122517 <3>[ 26.314078] usb 1-1.1.4: device descriptor read/64, error -32
11365 12:19:51.234896 <6>[ 26.426305] usb 1-1.1-port4: attempt power cycle
11366 12:19:51.846070 <6>[ 27.034037] usb 1-1.1.4: new full-speed USB device number 14 using xhci-mtk
11367 12:19:51.852834 <4>[ 27.041423] usb 1-1.1.4: Device not responding to setup address.
11368 12:19:52.063019 <4>[ 27.254383] usb 1-1.1.4: Device not responding to setup address.
11369 12:19:52.274556 <3>[ 27.466207] usb 1-1.1.4: device not accepting address 14, error -71
11370 12:19:52.361665 <6>[ 27.550045] usb 1-1.1.4: new full-speed USB device number 15 using xhci-mtk
11371 12:19:52.368408 <4>[ 27.557430] usb 1-1.1.4: Device not responding to setup address.
11372 12:19:52.578576 <4>[ 27.770230] usb 1-1.1.4: Device not responding to setup address.
11373 12:19:52.790700 <3>[ 27.982109] usb 1-1.1.4: device not accepting address 15, error -71
11374 12:19:52.797350 <3>[ 27.988972] usb 1-1.1-port4: unable to enumerate USB device
11375 12:19:52.810614 <6>[ 27.998589] Freezing remaining freezable tasks completed (elapsed 2.439 seconds)
11376 12:19:52.816917 <6>[ 28.006292] printk: Suspending console(s) (use no_console_suspend to debug)
11377 12:19:56.129000 <3>[ 31.054201] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11378 12:19:56.138773 <3>[ 31.054236] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11379 12:19:56.148737 <3>[ 31.054286] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11380 12:19:56.155317 <3>[ 31.054332] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11381 12:19:56.165349 <3>[ 31.054694] PM: Some devices failed to suspend, or early wake event detected
11382 12:19:56.168562 <6>[ 31.360272] OOM killer enabled.
11383 12:19:56.174852 <6>[ 31.363691] Restarting tasks ... done.
11384 12:19:56.178831 <5>[ 31.370192] random: crng reseeded on system resumption
11385 12:19:56.181923 <6>[ 31.376535] PM: suspend exit
11386 12:19:56.185271 rtcwake: write error
11387 12:19:56.193804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=fail>
11388 12:19:56.194586 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=fail
11390 12:19:56.196716 rtcwake: assuming RTC uses UTC ...
11391 12:19:56.203430 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:20:02 2023
11392 12:19:56.216971 <6>[ 31.408015] PM: suspend entry (deep)
11393 12:19:56.220014 <6>[ 31.411907] Filesystems sync: 0.000 seconds
11394 12:19:56.223560 <6>[ 31.416911] Freezing user space processes
11395 12:19:56.234684 <6>[ 31.422801] Freezing user space processes completed (elapsed 0.001 seconds)
11396 12:19:56.237883 <6>[ 31.430062] OOM killer disabled.
11397 12:19:56.240960 <6>[ 31.433540] Freezing remaining freezable tasks
11398 12:19:56.261738 <6>[ 31.450012] usb 1-1.1.4: new full-speed USB device number 16 using xhci-mtk
11399 12:19:56.342471 <3>[ 31.534019] usb 1-1.1.4: device descriptor read/64, error -32
11400 12:19:56.534490 <3>[ 31.726248] usb 1-1.1.4: device descriptor read/64, error -32
11401 12:19:56.729835 <6>[ 31.918056] usb 1-1.1.4: new full-speed USB device number 17 using xhci-mtk
11402 12:19:56.815030 <3>[ 32.006515] usb 1-1.1.4: device descriptor read/64, error -32
11403 12:19:57.006878 <3>[ 32.198091] usb 1-1.1.4: device descriptor read/64, error -32
11404 12:19:57.118565 <6>[ 32.310307] usb 1-1.1-port4: attempt power cycle
11405 12:19:57.729782 <6>[ 32.918055] usb 1-1.1.4: new full-speed USB device number 18 using xhci-mtk
11406 12:19:57.736359 <4>[ 32.925440] usb 1-1.1.4: Device not responding to setup address.
11407 12:19:57.946688 <4>[ 33.138261] usb 1-1.1.4: Device not responding to setup address.
11408 12:19:58.158627 <3>[ 33.350178] usb 1-1.1.4: device not accepting address 18, error -71
11409 12:19:58.246221 <6>[ 33.434188] usb 1-1.1.4: new full-speed USB device number 19 using xhci-mtk
11410 12:19:58.252209 <4>[ 33.441573] usb 1-1.1.4: Device not responding to setup address.
11411 12:19:58.462943 <4>[ 33.654230] usb 1-1.1.4: Device not responding to setup address.
11412 12:19:58.677315 <3>[ 33.866043] usb 1-1.1.4: device not accepting address 19, error -71
11413 12:19:58.680551 <3>[ 33.872939] usb 1-1.1-port4: unable to enumerate USB device
11414 12:19:58.692238 <6>[ 33.880650] Freezing remaining freezable tasks completed (elapsed 2.442 seconds)
11415 12:19:58.698798 <6>[ 33.888354] printk: Suspending console(s) (use no_console_suspend to debug)
11416 12:20:02.016227 <3>[ 36.942241] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
11417 12:20:02.026199 <3>[ 36.942279] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11418 12:20:02.035860 <3>[ 36.942338] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11419 12:20:02.042766 <3>[ 36.942400] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11420 12:20:02.052993 <3>[ 36.942614] PM: Some devices failed to suspend, or early wake event detected
11421 12:20:02.055834 <6>[ 37.248415] OOM killer enabled.
11422 12:20:02.062693 <6>[ 37.251836] Restarting tasks ... done.
11423 12:20:02.065762 <5>[ 37.258801] random: crng reseeded on system resumption
11424 12:20:02.069805 <6>[ 37.265232] PM: suspend exit
11425 12:20:02.073221 rtcwake: write error
11426 12:20:02.081311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=fail>
11427 12:20:02.082161 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=fail
11429 12:20:02.084577 rtcwake: assuming RTC uses UTC ...
11430 12:20:02.090590 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:20:08 2023
11431 12:20:02.103691 <6>[ 37.295993] PM: suspend entry (deep)
11432 12:20:02.107443 <6>[ 37.299959] Filesystems sync: 0.000 seconds
11433 12:20:02.113891 <6>[ 37.305095] Freezing user space processes
11434 12:20:02.120496 <6>[ 37.311337] Freezing user space processes completed (elapsed 0.001 seconds)
11435 12:20:02.123946 <6>[ 37.318572] OOM killer disabled.
11436 12:20:02.130240 <6>[ 37.322058] Freezing remaining freezable tasks
11437 12:20:02.145220 <6>[ 37.334005] usb 1-1.1.4: new full-speed USB device number 20 using xhci-mtk
11438 12:20:02.226038 <3>[ 37.418231] usb 1-1.1.4: device descriptor read/64, error -32
11439 12:20:02.418097 <3>[ 37.610104] usb 1-1.1.4: device descriptor read/64, error -32
11440 12:20:02.613469 <6>[ 37.802061] usb 1-1.1.4: new full-speed USB device number 21 using xhci-mtk
11441 12:20:02.698390 <3>[ 37.890231] usb 1-1.1.4: device descriptor read/64, error -32
11442 12:20:02.889917 <3>[ 38.082112] usb 1-1.1.4: device descriptor read/64, error -32
11443 12:20:03.002437 <6>[ 38.194297] usb 1-1.1-port4: attempt power cycle
11444 12:20:03.612996 <6>[ 38.802070] usb 1-1.1.4: new full-speed USB device number 22 using xhci-mtk
11445 12:20:03.619566 <4>[ 38.809452] usb 1-1.1.4: Device not responding to setup address.
11446 12:20:03.829742 <4>[ 39.022340] usb 1-1.1.4: Device not responding to setup address.
11447 12:20:04.041809 <3>[ 39.234047] usb 1-1.1.4: device not accepting address 22, error -71
11448 12:20:04.128940 <6>[ 39.318044] usb 1-1.1.4: new full-speed USB device number 23 using xhci-mtk
11449 12:20:04.135795 <4>[ 39.325428] usb 1-1.1.4: Device not responding to setup address.
11450 12:20:04.346049 <4>[ 39.538240] usb 1-1.1.4: Device not responding to setup address.
11451 12:20:04.557785 <3>[ 39.750180] usb 1-1.1.4: device not accepting address 23, error -71
11452 12:20:04.564603 <3>[ 39.757065] usb 1-1.1-port4: unable to enumerate USB device
11453 12:20:04.579145 <6>[ 39.768052] Freezing remaining freezable tasks completed (elapsed 2.441 seconds)
11454 12:20:04.585906 <6>[ 39.775747] printk: Suspending console(s) (use no_console_suspend to debug)
11455 12:20:07.899461 <3>[ 42.830239] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
11456 12:20:07.909506 <3>[ 42.830280] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11457 12:20:07.919562 <3>[ 42.830339] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11458 12:20:07.926358 <3>[ 42.830386] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11459 12:20:07.935788 <3>[ 42.830726] PM: Some devices failed to suspend, or early wake event detected
11460 12:20:07.939527 <6>[ 43.132314] OOM killer enabled.
11461 12:20:07.946228 <6>[ 43.135730] Restarting tasks ... done.
11462 12:20:07.952811 <5>[ 43.143728] random: crng reseeded on system resumption
11463 12:20:07.955762 <6>[ 43.150367] PM: suspend exit
11464 12:20:07.959094 rtcwake: write error
11465 12:20:07.965887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=fail>
11466 12:20:07.966662 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=fail
11468 12:20:07.968873 rtcwake: assuming RTC uses UTC ...
11469 12:20:07.975537 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:20:14 2023
11470 12:20:07.988541 <6>[ 43.181259] PM: suspend entry (deep)
11471 12:20:07.991599 <6>[ 43.185145] Filesystems sync: 0.000 seconds
11472 12:20:07.998491 <6>[ 43.190290] Freezing user space processes
11473 12:20:08.005222 <6>[ 43.196223] Freezing user space processes completed (elapsed 0.001 seconds)
11474 12:20:08.008764 <6>[ 43.203445] OOM killer disabled.
11475 12:20:08.014503 <6>[ 43.206926] Freezing remaining freezable tasks
11476 12:20:08.029221 <6>[ 43.218079] usb 1-1.1.4: new full-speed USB device number 24 using xhci-mtk
11477 12:20:08.113768 <3>[ 43.306036] usb 1-1.1.4: device descriptor read/64, error -32
11478 12:20:08.305315 <3>[ 43.498246] usb 1-1.1.4: device descriptor read/64, error -32
11479 12:20:08.500357 <6>[ 43.690060] usb 1-1.1.4: new full-speed USB device number 25 using xhci-mtk
11480 12:20:08.584737 <3>[ 43.778082] usb 1-1.1.4: device descriptor read/64, error -32
11481 12:20:08.777500 <3>[ 43.970206] usb 1-1.1.4: device descriptor read/64, error -32
11482 12:20:08.889326 <6>[ 44.082450] usb 1-1.1-port4: attempt power cycle
11483 12:20:09.500160 <6>[ 44.690028] usb 1-1.1.4: new full-speed USB device number 26 using xhci-mtk
11484 12:20:09.506683 <4>[ 44.697402] usb 1-1.1.4: Device not responding to setup address.
11485 12:20:09.717785 <4>[ 44.910606] usb 1-1.1.4: Device not responding to setup address.
11486 12:20:09.928848 <3>[ 45.122087] usb 1-1.1.4: device not accepting address 26, error -71
11487 12:20:10.016174 <6>[ 45.206199] usb 1-1.1.4: new full-speed USB device number 27 using xhci-mtk
11488 12:20:10.022956 <4>[ 45.213585] usb 1-1.1.4: Device not responding to setup address.
11489 12:20:10.233533 <4>[ 45.426292] usb 1-1.1.4: Device not responding to setup address.
11490 12:20:10.448621 <3>[ 45.638177] usb 1-1.1.4: device not accepting address 27, error -71
11491 12:20:10.451366 <3>[ 45.645035] usb 1-1.1-port4: unable to enumerate USB device
11492 12:20:10.468503 <6>[ 45.658508] Freezing remaining freezable tasks completed (elapsed 2.446 seconds)
11493 12:20:10.475363 <6>[ 45.666203] printk: Suspending console(s) (use no_console_suspend to debug)
11494 12:20:13.787788 <6>[ 48.206447] vpu: disabling
11495 12:20:13.790983 <6>[ 48.206583] vproc2: disabling
11496 12:20:13.794643 <6>[ 48.206644] vproc1: disabling
11497 12:20:13.798055 <6>[ 48.206704] vaud18: disabling
11498 12:20:13.801242 <6>[ 48.206975] vsram_others: disabling
11499 12:20:13.804781 <6>[ 48.207193] va09: disabling
11500 12:20:13.807667 <6>[ 48.207278] vsram_md: disabling
11501 12:20:13.811114 <6>[ 48.207420] Vgpu: disabling
11502 12:20:13.817506 <3>[ 48.718199] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
11503 12:20:13.827559 <3>[ 48.718235] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11504 12:20:13.837221 <3>[ 48.718285] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11505 12:20:13.844025 <3>[ 48.718331] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11506 12:20:13.850970 <3>[ 48.718686] PM: Some devices failed to suspend, or early wake event detected
11507 12:20:13.853950 <6>[ 49.050435] OOM killer enabled.
11508 12:20:13.862604 <6>[ 49.053836] Restarting tasks ... done.
11509 12:20:13.866518 <5>[ 49.059851] random: crng reseeded on system resumption
11510 12:20:13.870178 <6>[ 49.066197] PM: suspend exit
11511 12:20:13.872992 rtcwake: write error
11512 12:20:13.880750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=fail>
11513 12:20:13.881630 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=fail
11515 12:20:13.884053 rtcwake: assuming RTC uses UTC ...
11516 12:20:13.890940 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:20:20 2023
11517 12:20:13.903062 <6>[ 49.096610] PM: suspend entry (deep)
11518 12:20:13.906763 <6>[ 49.100611] Filesystems sync: 0.000 seconds
11519 12:20:13.912931 <6>[ 49.105649] Freezing user space processes
11520 12:20:13.919949 <6>[ 49.111736] Freezing user space processes completed (elapsed 0.001 seconds)
11521 12:20:13.922992 <6>[ 49.118973] OOM killer disabled.
11522 12:20:13.929580 <6>[ 49.122457] Freezing remaining freezable tasks
11523 12:20:13.947751 <6>[ 49.138001] usb 1-1.1.4: new full-speed USB device number 28 using xhci-mtk
11524 12:20:14.028497 <3>[ 49.222073] usb 1-1.1.4: device descriptor read/64, error -32
11525 12:20:14.220832 <3>[ 49.414067] usb 1-1.1.4: device descriptor read/64, error -32
11526 12:20:14.415611 <6>[ 49.606058] usb 1-1.1.4: new full-speed USB device number 29 using xhci-mtk
11527 12:20:14.500220 <3>[ 49.694097] usb 1-1.1.4: device descriptor read/64, error -32
11528 12:20:14.692708 <3>[ 49.886230] usb 1-1.1.4: device descriptor read/64, error -32
11529 12:20:14.804862 <6>[ 49.998509] usb 1-1.1-port4: attempt power cycle
11530 12:20:15.415713 <6>[ 50.606045] usb 1-1.1.4: new full-speed USB device number 30 using xhci-mtk
11531 12:20:15.422402 <4>[ 50.613490] usb 1-1.1.4: Device not responding to setup address.
11532 12:20:15.632546 <4>[ 50.826311] usb 1-1.1.4: Device not responding to setup address.
11533 12:20:15.845311 <3>[ 51.038226] usb 1-1.1.4: device not accepting address 30, error -71
11534 12:20:15.931554 <6>[ 51.122034] usb 1-1.1.4: new full-speed USB device number 31 using xhci-mtk
11535 12:20:15.938117 <4>[ 51.129466] usb 1-1.1.4: Device not responding to setup address.
11536 12:20:16.148567 <4>[ 51.342294] usb 1-1.1.4: Device not responding to setup address.
11537 12:20:16.360359 <3>[ 51.554034] usb 1-1.1.4: device not accepting address 31, error -71
11538 12:20:16.366729 <3>[ 51.560861] usb 1-1.1-port4: unable to enumerate USB device
11539 12:20:16.383399 <6>[ 51.574078] Freezing remaining freezable tasks completed (elapsed 2.446 seconds)
11540 12:20:16.390114 <6>[ 51.581899] printk: Suspending console(s) (use no_console_suspend to debug)
11541 12:20:19.674184 <3>[ 54.606207] mt7921e 0000:01:00.0: Message 00020007 (seq 11) timeout
11542 12:20:19.687421 <3>[ 54.606242] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11543 12:20:19.694066 <3>[ 54.606292] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11544 12:20:19.700710 <3>[ 54.606338] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11545 12:20:19.710783 <3>[ 54.606627] PM: Some devices failed to suspend, or early wake event detected
11546 12:20:19.713801 <6>[ 54.908414] OOM killer enabled.
11547 12:20:19.730574 <6>[ 54.911832] Restarting tasks ... done.
11548 12:20:19.736410 <5>[ 54.928692] random: crng reseeded on system resumption
11549 12:20:19.740126 <6>[ 54.935550] PM: suspend exit
11550 12:20:19.743479 rtcwake: write error
11551 12:20:19.749717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=fail>
11552 12:20:19.750566 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=fail
11554 12:20:19.753093 rtcwake: assuming RTC uses UTC ...
11555 12:20:19.759969 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:20:26 2023
11556 12:20:19.772351 <6>[ 54.966106] PM: suspend entry (deep)
11557 12:20:19.775302 <6>[ 54.970024] Filesystems sync: 0.000 seconds
11558 12:20:19.778746 <6>[ 54.975086] Freezing user space processes
11559 12:20:19.790058 <6>[ 54.981132] Freezing user space processes completed (elapsed 0.001 seconds)
11560 12:20:19.793823 <6>[ 54.988366] OOM killer disabled.
11561 12:20:19.796831 <6>[ 54.991852] Freezing remaining freezable tasks
11562 12:20:19.806990 <6>[ 54.997923] usb 1-1.1.4: new full-speed USB device number 32 using xhci-mtk
11563 12:20:19.888048 <3>[ 55.081958] usb 1-1.1.4: device descriptor read/64, error -32
11564 12:20:20.080695 <3>[ 55.274238] usb 1-1.1.4: device descriptor read/64, error -32
11565 12:20:20.275244 <6>[ 55.466050] usb 1-1.1.4: new full-speed USB device number 33 using xhci-mtk
11566 12:20:20.356153 <3>[ 55.550084] usb 1-1.1.4: device descriptor read/64, error -32
11567 12:20:20.548119 <3>[ 55.742228] usb 1-1.1.4: device descriptor read/64, error -32
11568 12:20:20.660000 <6>[ 55.854363] usb 1-1.1-port4: attempt power cycle
11569 12:20:21.272026 <6>[ 56.462051] usb 1-1.1.4: new full-speed USB device number 34 using xhci-mtk
11570 12:20:21.277727 <4>[ 56.469506] usb 1-1.1.4: Device not responding to setup address.
11571 12:20:21.487779 <4>[ 56.682250] usb 1-1.1.4: Device not responding to setup address.
11572 12:20:21.699893 <3>[ 56.894178] usb 1-1.1.4: device not accepting address 34, error -71
11573 12:20:21.787578 <6>[ 56.978318] usb 1-1.1.4: new full-speed USB device number 35 using xhci-mtk
11574 12:20:21.793730 <4>[ 56.985696] usb 1-1.1.4: Device not responding to setup address.
11575 12:20:22.003493 <4>[ 57.198292] usb 1-1.1.4: Device not responding to setup address.
11576 12:20:22.216012 <3>[ 57.410247] usb 1-1.1.4: device not accepting address 35, error -71
11577 12:20:22.223041 <3>[ 57.417079] usb 1-1.1-port4: unable to enumerate USB device
11578 12:20:22.238930 <6>[ 57.430233] Freezing remaining freezable tasks completed (elapsed 2.433 seconds)
11579 12:20:22.246011 <6>[ 57.437940] printk: Suspending console(s) (use no_console_suspend to debug)
11580 12:20:25.566210 <3>[ 60.494240] mt7921e 0000:01:00.0: Message 00020007 (seq 12) timeout
11581 12:20:25.575379 <3>[ 60.494277] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11582 12:20:25.585375 <3>[ 60.494326] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11583 12:20:25.591709 <3>[ 60.494372] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11584 12:20:25.601582 <3>[ 60.494652] PM: Some devices failed to suspend, or early wake event detected
11585 12:20:25.605201 <6>[ 60.800348] OOM killer enabled.
11586 12:20:25.611843 <6>[ 60.803773] Restarting tasks ... done.
11587 12:20:25.615114 <5>[ 60.809977] random: crng reseeded on system resumption
11588 12:20:25.618234 <6>[ 60.816356] PM: suspend exit
11589 12:20:25.621718 rtcwake: write error
11590 12:20:25.629852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=fail>
11591 12:20:25.630748 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=fail
11593 12:20:25.633114 rtcwake: assuming RTC uses UTC ...
11594 12:20:25.639704 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:20:32 2023
11595 12:20:25.652249 <6>[ 60.846999] PM: suspend entry (deep)
11596 12:20:25.655528 <6>[ 60.850884] Filesystems sync: 0.000 seconds
11597 12:20:25.659284 <6>[ 60.855918] Freezing user space processes
11598 12:20:25.670380 <6>[ 60.861984] Freezing user space processes completed (elapsed 0.001 seconds)
11599 12:20:25.673631 <6>[ 60.869218] OOM killer disabled.
11600 12:20:25.676916 <6>[ 60.872701] Freezing remaining freezable tasks
11601 12:20:25.694676 <6>[ 60.886043] usb 1-1.1.4: new full-speed USB device number 36 using xhci-mtk
11602 12:20:25.775105 <3>[ 60.970040] usb 1-1.1.4: device descriptor read/64, error -32
11603 12:20:25.966954 <3>[ 61.162240] usb 1-1.1.4: device descriptor read/64, error -32
11604 12:20:26.161826 <6>[ 61.354035] usb 1-1.1.4: new full-speed USB device number 37 using xhci-mtk
11605 12:20:26.242949 <3>[ 61.438093] usb 1-1.1.4: device descriptor read/64, error -32
11606 12:20:26.435146 <3>[ 61.630230] usb 1-1.1.4: device descriptor read/64, error -32
11607 12:20:26.547061 <6>[ 61.742447] usb 1-1.1-port4: attempt power cycle
11608 12:20:27.157900 <6>[ 62.350197] usb 1-1.1.4: new full-speed USB device number 38 using xhci-mtk
11609 12:20:27.164630 <4>[ 62.357646] usb 1-1.1.4: Device not responding to setup address.
11610 12:20:27.375149 <4>[ 62.570291] usb 1-1.1.4: Device not responding to setup address.
11611 12:20:27.586374 <3>[ 62.782179] usb 1-1.1.4: device not accepting address 38, error -71
11612 12:20:27.673679 <6>[ 62.866188] usb 1-1.1.4: new full-speed USB device number 39 using xhci-mtk
11613 12:20:27.680372 <4>[ 62.873634] usb 1-1.1.4: Device not responding to setup address.
11614 12:20:27.890451 <4>[ 63.086226] usb 1-1.1.4: Device not responding to setup address.
11615 12:20:28.102708 <3>[ 63.298038] usb 1-1.1.4: device not accepting address 39, error -71
11616 12:20:28.109785 <3>[ 63.304926] usb 1-1.1-port4: unable to enumerate USB device
11617 12:20:28.120026 <6>[ 63.311913] Freezing remaining freezable tasks completed (elapsed 2.434 seconds)
11618 12:20:28.127068 <6>[ 63.319609] printk: Suspending console(s) (use no_console_suspend to debug)
11619 12:20:31.453247 <3>[ 66.382241] mt7921e 0000:01:00.0: Message 00020007 (seq 13) timeout
11620 12:20:31.463355 <3>[ 66.382283] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11621 12:20:31.473202 <3>[ 66.382343] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11622 12:20:31.480369 <3>[ 66.382391] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11623 12:20:31.489787 <3>[ 66.382711] PM: Some devices failed to suspend, or early wake event detected
11624 12:20:31.493343 <6>[ 66.688618] OOM killer enabled.
11625 12:20:31.500172 <6>[ 66.692035] Restarting tasks ... done.
11626 12:20:31.503426 <5>[ 66.698416] random: crng reseeded on system resumption
11627 12:20:31.506425 <6>[ 66.704809] PM: suspend exit
11628 12:20:31.509132 rtcwake: write error
11629 12:20:31.519064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=fail>
11630 12:20:31.519951 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=fail
11632 12:20:31.521793 rtcwake: assuming RTC uses UTC ...
11633 12:20:31.528335 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:20:37 2023
11634 12:20:31.540839 <6>[ 66.736548] PM: suspend entry (deep)
11635 12:20:31.544389 <6>[ 66.740429] Filesystems sync: 0.000 seconds
11636 12:20:31.547672 <6>[ 66.745420] Freezing user space processes
11637 12:20:31.559290 <6>[ 66.751480] Freezing user space processes completed (elapsed 0.001 seconds)
11638 12:20:31.562586 <6>[ 66.758729] OOM killer disabled.
11639 12:20:31.566225 <6>[ 66.762212] Freezing remaining freezable tasks
11640 12:20:31.582262 <6>[ 66.774154] usb 1-1.1.4: new full-speed USB device number 40 using xhci-mtk
11641 12:20:31.666324 <3>[ 66.862046] usb 1-1.1.4: device descriptor read/64, error -32
11642 12:20:31.859039 <3>[ 67.054242] usb 1-1.1.4: device descriptor read/64, error -32
11643 12:20:32.054433 <6>[ 67.246197] usb 1-1.1.4: new full-speed USB device number 41 using xhci-mtk
11644 12:20:32.139176 <3>[ 67.334192] usb 1-1.1.4: device descriptor read/64, error -32
11645 12:20:32.330459 <3>[ 67.526092] usb 1-1.1.4: device descriptor read/64, error -32
11646 12:20:32.443027 <6>[ 67.638309] usb 1-1.1-port4: attempt power cycle
11647 12:20:33.053669 <6>[ 68.246055] usb 1-1.1.4: new full-speed USB device number 42 using xhci-mtk
11648 12:20:33.060343 <4>[ 68.253441] usb 1-1.1.4: Device not responding to setup address.
11649 12:20:33.270482 <4>[ 68.466260] usb 1-1.1.4: Device not responding to setup address.
11650 12:20:33.482548 <3>[ 68.678179] usb 1-1.1.4: device not accepting address 42, error -71
11651 12:20:33.569992 <6>[ 68.762188] usb 1-1.1.4: new full-speed USB device number 43 using xhci-mtk
11652 12:20:33.576324 <4>[ 68.769574] usb 1-1.1.4: Device not responding to setup address.
11653 12:20:33.786800 <4>[ 68.982487] usb 1-1.1.4: Device not responding to setup address.
11654 12:20:33.998902 <3>[ 69.194040] usb 1-1.1.4: device not accepting address 43, error -71
11655 12:20:34.005180 <3>[ 69.200896] usb 1-1.1-port4: unable to enumerate USB device
11656 12:20:34.015349 <6>[ 69.207653] Freezing remaining freezable tasks completed (elapsed 2.440 seconds)
11657 12:20:34.021864 <6>[ 69.215359] printk: Suspending console(s) (use no_console_suspend to debug)
11658 12:20:37.336458 <3>[ 72.270201] mt7921e 0000:01:00.0: Message 00020007 (seq 14) timeout
11659 12:20:37.349577 <3>[ 72.270237] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11660 12:20:37.356174 <3>[ 72.270286] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11661 12:20:37.362992 <3>[ 72.270334] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11662 12:20:37.372980 <3>[ 72.270618] PM: Some devices failed to suspend, or early wake event detected
11663 12:20:37.375932 <6>[ 72.572653] OOM killer enabled.
11664 12:20:37.379538 <6>[ 72.576070] Restarting tasks ... done.
11665 12:20:37.386261 <5>[ 72.582248] random: crng reseeded on system resumption
11666 12:20:37.389522 <6>[ 72.588726] PM: suspend exit
11667 12:20:37.392901 rtcwake: write error
11668 12:20:37.400918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=fail>
11669 12:20:37.401852 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=fail
11671 12:20:37.403949 rtcwake: assuming RTC uses UTC ...
11672 12:20:37.410411 rtcwake: wakeup from "mem" using rtc0 at Fri Oct 27 12:20:43 2023
11673 12:20:37.423454 <6>[ 72.619524] PM: suspend entry (deep)
11674 12:20:37.426998 <6>[ 72.623421] Filesystems sync: 0.000 seconds
11675 12:20:37.430047 <6>[ 72.628443] Freezing user space processes
11676 12:20:37.441198 <6>[ 72.633942] Freezing user space processes completed (elapsed 0.001 seconds)
11677 12:20:37.444816 <6>[ 72.641158] OOM killer disabled.
11678 12:20:37.447709 <6>[ 72.644640] Freezing remaining freezable tasks
11679 12:20:37.465249 <6>[ 72.658073] usb 1-1.1.4: new full-speed USB device number 44 using xhci-mtk
11680 12:20:37.546288 <3>[ 72.741960] usb 1-1.1.4: device descriptor read/64, error -32
11681 12:20:37.737674 <3>[ 72.934040] usb 1-1.1.4: device descriptor read/64, error -32
11682 12:20:37.933028 <6>[ 73.126044] usb 1-1.1.4: new full-speed USB device number 45 using xhci-mtk
11683 12:20:38.017956 <3>[ 73.214228] usb 1-1.1.4: device descriptor read/64, error -32
11684 12:20:38.210003 <3>[ 73.406091] usb 1-1.1.4: device descriptor read/64, error -32
11685 12:20:38.321919 <6>[ 73.518271] usb 1-1.1-port4: attempt power cycle
11686 12:20:38.933024 <6>[ 74.126040] usb 1-1.1.4: new full-speed USB device number 46 using xhci-mtk
11687 12:20:38.940390 <4>[ 74.133420] usb 1-1.1.4: Device not responding to setup address.
11688 12:20:39.150358 <4>[ 74.346224] usb 1-1.1.4: Device not responding to setup address.
11689 12:20:39.361847 <3>[ 74.558179] usb 1-1.1.4: device not accepting address 46, error -71
11690 12:20:39.448804 <6>[ 74.642188] usb 1-1.1.4: new full-speed USB device number 47 using xhci-mtk
11691 12:20:39.455463 <4>[ 74.649640] usb 1-1.1.4: Device not responding to setup address.
11692 12:20:39.665977 <4>[ 74.862325] usb 1-1.1.4: Device not responding to setup address.
11693 12:20:39.877864 <3>[ 75.074238] usb 1-1.1.4: device not accepting address 47, error -71
11694 12:20:39.884606 <3>[ 75.081138] usb 1-1.1-port4: unable to enumerate USB device
11695 12:20:39.900745 <6>[ 75.093979] Freezing remaining freezable tasks completed (elapsed 2.444 seconds)
11696 12:20:39.907618 <6>[ 75.101662] printk: Suspending console(s) (use no_console_suspend to debug)
11697 12:20:43.223629 <3>[ 78.158209] mt7921e 0000:01:00.0: Message 00020007 (seq 15) timeout
11698 12:20:43.233420 <3>[ 78.158245] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11699 12:20:43.243756 <3>[ 78.158294] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11700 12:20:43.250387 <3>[ 78.158343] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11701 12:20:43.260206 <3>[ 78.158649] PM: Some devices failed to suspend, or early wake event detected
11702 12:20:43.263620 <6>[ 78.460540] OOM killer enabled.
11703 12:20:43.266825 <6>[ 78.463958] Restarting tasks ... done.
11704 12:20:43.273807 <5>[ 78.470151] random: crng reseeded on system resumption
11705 12:20:43.277071 <6>[ 78.476680] PM: suspend exit
11706 12:20:43.280355 rtcwake: write error
11707 12:20:43.289340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=fail>
11708 12:20:43.290202 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=fail
11710 12:20:43.292748 rtcwake: assuming RTC uses UTC ...
11711 12:20:43.299138 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:20:49 2023
11712 12:20:43.313247 <6>[ 78.510082] PM: suspend entry (s2idle)
11713 12:20:43.316611 <6>[ 78.514139] Filesystems sync: 0.000 seconds
11714 12:20:43.323261 <6>[ 78.519220] Freezing user space processes
11715 12:20:43.330240 <6>[ 78.525250] Freezing user space processes completed (elapsed 0.001 seconds)
11716 12:20:43.333414 <6>[ 78.532486] OOM killer disabled.
11717 12:20:43.339913 <6>[ 78.535968] Freezing remaining freezable tasks
11718 12:20:43.356908 <6>[ 78.550134] usb 1-1.1.4: new full-speed USB device number 48 using xhci-mtk
11719 12:20:43.440924 <3>[ 78.638028] usb 1-1.1.4: device descriptor read/64, error -32
11720 12:20:43.633300 <3>[ 78.830109] usb 1-1.1.4: device descriptor read/64, error -32
11721 12:20:43.828457 <6>[ 79.022212] usb 1-1.1.4: new full-speed USB device number 49 using xhci-mtk
11722 12:20:43.913065 <3>[ 79.110085] usb 1-1.1.4: device descriptor read/64, error -32
11723 12:20:44.105458 <3>[ 79.302230] usb 1-1.1.4: device descriptor read/64, error -32
11724 12:20:44.217336 <6>[ 79.414448] usb 1-1.1-port4: attempt power cycle
11725 12:20:44.828599 <6>[ 80.022189] usb 1-1.1.4: new full-speed USB device number 50 using xhci-mtk
11726 12:20:44.834895 <4>[ 80.029643] usb 1-1.1.4: Device not responding to setup address.
11727 12:20:45.045123 <4>[ 80.242155] usb 1-1.1.4: Device not responding to setup address.
11728 12:20:45.256813 <3>[ 80.454037] usb 1-1.1.4: device not accepting address 50, error -71
11729 12:20:45.344120 <6>[ 80.538054] usb 1-1.1.4: new full-speed USB device number 51 using xhci-mtk
11730 12:20:45.351118 <4>[ 80.545436] usb 1-1.1.4: Device not responding to setup address.
11731 12:20:45.561255 <4>[ 80.758348] usb 1-1.1.4: Device not responding to setup address.
11732 12:20:45.773335 <3>[ 80.970227] usb 1-1.1.4: device not accepting address 51, error -71
11733 12:20:45.779832 <3>[ 80.977089] usb 1-1.1-port4: unable to enumerate USB device
11734 12:20:45.794735 <6>[ 80.988445] Freezing remaining freezable tasks completed (elapsed 2.447 seconds)
11735 12:20:45.801276 <6>[ 80.996140] printk: Suspending console(s) (use no_console_suspend to debug)
11736 12:20:49.115368 <3>[ 84.046199] mt7921e 0000:01:00.0: Message 00020007 (seq 1) timeout
11737 12:20:49.125751 <3>[ 84.046234] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11738 12:20:49.135411 <3>[ 84.046284] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11739 12:20:49.141840 <3>[ 84.046331] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11740 12:20:49.148647 <3>[ 84.046690] PM: Some devices failed to suspend, or early wake event detected
11741 12:20:49.155162 <6>[ 84.352471] OOM killer enabled.
11742 12:20:49.158642 <6>[ 84.355887] Restarting tasks ... done.
11743 12:20:49.164820 <5>[ 84.362193] random: crng reseeded on system resumption
11744 12:20:49.168270 <6>[ 84.368514] PM: suspend exit
11745 12:20:49.171679 rtcwake: write error
11746 12:20:49.179028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail>
11747 12:20:49.179794 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-1 RESULT=fail
11749 12:20:49.182035 rtcwake: assuming RTC uses UTC ...
11750 12:20:49.189013 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:20:55 2023
11751 12:20:49.201217 <6>[ 84.398681] PM: suspend entry (s2idle)
11752 12:20:49.204686 <6>[ 84.402769] Filesystems sync: 0.000 seconds
11753 12:20:49.211108 <6>[ 84.407819] Freezing user space processes
11754 12:20:49.217546 <6>[ 84.413834] Freezing user space processes completed (elapsed 0.001 seconds)
11755 12:20:49.221292 <6>[ 84.421067] OOM killer disabled.
11756 12:20:49.227950 <6>[ 84.424551] Freezing remaining freezable tasks
11757 12:20:49.243951 <6>[ 84.438079] usb 1-1.1.4: new full-speed USB device number 52 using xhci-mtk
11758 12:20:49.324575 <3>[ 84.521977] usb 1-1.1.4: device descriptor read/64, error -32
11759 12:20:49.517269 <3>[ 84.714245] usb 1-1.1.4: device descriptor read/64, error -32
11760 12:20:49.711807 <6>[ 84.906025] usb 1-1.1.4: new full-speed USB device number 53 using xhci-mtk
11761 12:20:49.796098 <3>[ 84.994199] usb 1-1.1.4: device descriptor read/64, error -32
11762 12:20:49.988758 <3>[ 85.186072] usb 1-1.1.4: device descriptor read/64, error -32
11763 12:20:50.100482 <6>[ 85.298267] usb 1-1.1-port4: attempt power cycle
11764 12:20:50.711342 <6>[ 85.906041] usb 1-1.1.4: new full-speed USB device number 54 using xhci-mtk
11765 12:20:50.717899 <4>[ 85.913420] usb 1-1.1.4: Device not responding to setup address.
11766 12:20:50.928404 <4>[ 86.126207] usb 1-1.1.4: Device not responding to setup address.
11767 12:20:51.140281 <3>[ 86.338035] usb 1-1.1.4: device not accepting address 54, error -71
11768 12:20:51.227670 <6>[ 86.422045] usb 1-1.1.4: new full-speed USB device number 55 using xhci-mtk
11769 12:20:51.234477 <4>[ 86.429430] usb 1-1.1.4: Device not responding to setup address.
11770 12:20:51.444383 <4>[ 86.642214] usb 1-1.1.4: Device not responding to setup address.
11771 12:20:51.656247 <3>[ 86.854197] usb 1-1.1.4: device not accepting address 55, error -71
11772 12:20:51.663587 <3>[ 86.861055] usb 1-1.1-port4: unable to enumerate USB device
11773 12:20:51.676519 <6>[ 86.870903] Freezing remaining freezable tasks completed (elapsed 2.441 seconds)
11774 12:20:51.683438 <6>[ 86.878598] printk: Suspending console(s) (use no_console_suspend to debug)
11775 12:20:54.998561 <3>[ 89.934204] mt7921e 0000:01:00.0: Message 00020007 (seq 2) timeout
11776 12:20:55.008843 <3>[ 89.934239] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11777 12:20:55.018125 <3>[ 89.934289] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11778 12:20:55.024897 <3>[ 89.934336] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11779 12:20:55.031701 <3>[ 89.934690] PM: Some devices failed to suspend, or early wake event detected
11780 12:20:55.038397 <6>[ 90.236334] OOM killer enabled.
11781 12:20:55.041907 <6>[ 90.239752] Restarting tasks ... done.
11782 12:20:55.047979 <5>[ 90.245920] random: crng reseeded on system resumption
11783 12:20:55.052028 <6>[ 90.252310] PM: suspend exit
11784 12:20:55.055022 rtcwake: write error
11785 12:20:55.065610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail>
11786 12:20:55.066315 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-2 RESULT=fail
11788 12:20:55.068790 rtcwake: assuming RTC uses UTC ...
11789 12:20:55.074959 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:21:01 2023
11790 12:20:55.088057 <6>[ 90.286197] PM: suspend entry (s2idle)
11791 12:20:55.091523 <6>[ 90.290251] Filesystems sync: 0.000 seconds
11792 12:20:55.098222 <6>[ 90.295331] Freezing user space processes
11793 12:20:55.104619 <6>[ 90.301301] Freezing user space processes completed (elapsed 0.001 seconds)
11794 12:20:55.108387 <6>[ 90.308533] OOM killer disabled.
11795 12:20:55.115173 <6>[ 90.312015] Freezing remaining freezable tasks
11796 12:20:55.135193 <6>[ 90.330133] usb 1-1.1.4: new full-speed USB device number 56 using xhci-mtk
11797 12:20:55.220480 <3>[ 90.418080] usb 1-1.1.4: device descriptor read/64, error -32
11798 12:20:55.411871 <3>[ 90.610069] usb 1-1.1.4: device descriptor read/64, error -32
11799 12:20:55.607485 <6>[ 90.801970] usb 1-1.1.4: new full-speed USB device number 57 using xhci-mtk
11800 12:20:55.687484 <3>[ 90.886081] usb 1-1.1.4: device descriptor read/64, error -32
11801 12:20:55.879965 <3>[ 91.078234] usb 1-1.1.4: device descriptor read/64, error -32
11802 12:20:55.991892 <6>[ 91.190311] usb 1-1.1-port4: attempt power cycle
11803 12:20:56.602894 <6>[ 91.797999] usb 1-1.1.4: new full-speed USB device number 58 using xhci-mtk
11804 12:20:56.609172 <4>[ 91.805374] usb 1-1.1.4: Device not responding to setup address.
11805 12:20:56.819719 <4>[ 92.018275] usb 1-1.1.4: Device not responding to setup address.
11806 12:20:57.031659 <3>[ 92.230179] usb 1-1.1.4: device not accepting address 58, error -71
11807 12:20:57.119184 <6>[ 92.314187] usb 1-1.1.4: new full-speed USB device number 59 using xhci-mtk
11808 12:20:57.125694 <4>[ 92.321632] usb 1-1.1.4: Device not responding to setup address.
11809 12:20:57.335913 <4>[ 92.534237] usb 1-1.1.4: Device not responding to setup address.
11810 12:20:57.547680 <3>[ 92.746036] usb 1-1.1.4: device not accepting address 59, error -71
11811 12:20:57.554353 <3>[ 92.752891] usb 1-1.1-port4: unable to enumerate USB device
11812 12:20:57.564695 <6>[ 92.759917] Freezing remaining freezable tasks completed (elapsed 2.443 seconds)
11813 12:20:57.571066 <6>[ 92.767621] printk: Suspending console(s) (use no_console_suspend to debug)
11814 12:21:00.886072 <3>[ 95.822199] mt7921e 0000:01:00.0: Message 00020007 (seq 3) timeout
11815 12:21:00.895826 <3>[ 95.822234] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11816 12:21:00.905771 <3>[ 95.822284] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11817 12:21:00.912211 <3>[ 95.822333] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11818 12:21:00.922355 <3>[ 95.822546] PM: Some devices failed to suspend, or early wake event detected
11819 12:21:00.925543 <6>[ 96.124558] OOM killer enabled.
11820 12:21:00.929206 <6>[ 96.127975] Restarting tasks ... done.
11821 12:21:00.936112 <5>[ 96.134029] random: crng reseeded on system resumption
11822 12:21:00.938949 <6>[ 96.140383] PM: suspend exit
11823 12:21:00.942182 rtcwake: write error
11824 12:21:00.949367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail>
11825 12:21:00.950158 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-3 RESULT=fail
11827 12:21:00.952897 rtcwake: assuming RTC uses UTC ...
11828 12:21:00.959506 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:21:07 2023
11829 12:21:00.974685 <6>[ 96.173554] PM: suspend entry (s2idle)
11830 12:21:00.978028 <6>[ 96.177649] Filesystems sync: 0.000 seconds
11831 12:21:00.984350 <6>[ 96.182863] Freezing user space processes
11832 12:21:00.991335 <6>[ 96.189089] Freezing user space processes completed (elapsed 0.001 seconds)
11833 12:21:00.994537 <6>[ 96.196423] OOM killer disabled.
11834 12:21:01.001154 <6>[ 96.199913] Freezing remaining freezable tasks
11835 12:21:01.026227 <6>[ 96.221956] usb 1-1.1.4: new full-speed USB device number 60 using xhci-mtk
11836 12:21:01.111609 <3>[ 96.310235] usb 1-1.1.4: device descriptor read/64, error -32
11837 12:21:01.303138 <3>[ 96.502042] usb 1-1.1.4: device descriptor read/64, error -32
11838 12:21:01.499030 <6>[ 96.694096] usb 1-1.1.4: new full-speed USB device number 61 using xhci-mtk
11839 12:21:01.583153 <3>[ 96.782083] usb 1-1.1.4: device descriptor read/64, error -32
11840 12:21:01.775051 <3>[ 96.974361] usb 1-1.1.4: device descriptor read/64, error -32
11841 12:21:01.887212 <6>[ 97.086453] usb 1-1.1-port4: attempt power cycle
11842 12:21:02.498138 <6>[ 97.694188] usb 1-1.1.4: new full-speed USB device number 62 using xhci-mtk
11843 12:21:02.504665 <4>[ 97.701634] usb 1-1.1.4: Device not responding to setup address.
11844 12:21:02.715000 <4>[ 97.914295] usb 1-1.1.4: Device not responding to setup address.
11845 12:21:02.926497 <3>[ 98.126021] usb 1-1.1.4: device not accepting address 62, error -71
11846 12:21:03.013730 <6>[ 98.210055] usb 1-1.1.4: new full-speed USB device number 63 using xhci-mtk
11847 12:21:03.020364 <4>[ 98.217498] usb 1-1.1.4: Device not responding to setup address.
11848 12:21:03.230686 <4>[ 98.430229] usb 1-1.1.4: Device not responding to setup address.
11849 12:21:03.442547 <3>[ 98.642044] usb 1-1.1.4: device not accepting address 63, error -71
11850 12:21:03.449180 <3>[ 98.648944] usb 1-1.1-port4: unable to enumerate USB device
11851 12:21:03.461782 <6>[ 98.658216] Freezing remaining freezable tasks completed (elapsed 2.453 seconds)
11852 12:21:03.468304 <6>[ 98.665910] printk: Suspending console(s) (use no_console_suspend to debug)
11853 12:21:06.776977 <3>[ 101.710230] mt7921e 0000:01:00.0: Message 00020007 (seq 4) timeout
11854 12:21:06.786764 <3>[ 101.710264] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11855 12:21:06.797284 <3>[ 101.710314] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11856 12:21:06.803424 <3>[ 101.710360] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11857 12:21:06.810440 <3>[ 101.710671] PM: Some devices failed to suspend, or early wake event detected
11858 12:21:06.817010 <6>[ 102.016300] OOM killer enabled.
11859 12:21:06.820554 <6>[ 102.019716] Restarting tasks ... done.
11860 12:21:06.826705 <5>[ 102.025773] random: crng reseeded on system resumption
11861 12:21:06.830043 <6>[ 102.032223] PM: suspend exit
11862 12:21:06.833300 rtcwake: write error
11863 12:21:06.840605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail>
11864 12:21:06.841447 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-4 RESULT=fail
11866 12:21:06.844006 rtcwake: assuming RTC uses UTC ...
11867 12:21:06.851115 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:21:13 2023
11868 12:21:06.863552 <6>[ 102.062869] PM: suspend entry (s2idle)
11869 12:21:06.866843 <6>[ 102.066955] Filesystems sync: 0.000 seconds
11870 12:21:06.873523 <6>[ 102.072005] Freezing user space processes
11871 12:21:06.879702 <6>[ 102.078066] Freezing user space processes completed (elapsed 0.001 seconds)
11872 12:21:06.883507 <6>[ 102.085294] OOM killer disabled.
11873 12:21:06.889577 <6>[ 102.088778] Freezing remaining freezable tasks
11874 12:21:06.905985 <6>[ 102.102092] usb 1-1.1.4: new full-speed USB device number 64 using xhci-mtk
11875 12:21:06.990483 <3>[ 102.190187] usb 1-1.1.4: device descriptor read/64, error -32
11876 12:21:07.182992 <3>[ 102.382191] usb 1-1.1.4: device descriptor read/64, error -32
11877 12:21:07.377660 <6>[ 102.574047] usb 1-1.1.4: new full-speed USB device number 65 using xhci-mtk
11878 12:21:07.462938 <3>[ 102.662233] usb 1-1.1.4: device descriptor read/64, error -32
11879 12:21:07.654733 <3>[ 102.854229] usb 1-1.1.4: device descriptor read/64, error -32
11880 12:21:07.766888 <6>[ 102.966607] usb 1-1.1-port4: attempt power cycle
11881 12:21:08.377715 <6>[ 103.574185] usb 1-1.1.4: new full-speed USB device number 66 using xhci-mtk
11882 12:21:08.384626 <4>[ 103.581564] usb 1-1.1.4: Device not responding to setup address.
11883 12:21:08.593955 <4>[ 103.794255] usb 1-1.1.4: Device not responding to setup address.
11884 12:21:08.805848 <3>[ 104.006222] usb 1-1.1.4: device not accepting address 66, error -71
11885 12:21:08.893294 <6>[ 104.090194] usb 1-1.1.4: new full-speed USB device number 67 using xhci-mtk
11886 12:21:08.899998 <4>[ 104.097582] usb 1-1.1.4: Device not responding to setup address.
11887 12:21:09.110274 <4>[ 104.310316] usb 1-1.1.4: Device not responding to setup address.
11888 12:21:09.322066 <3>[ 104.522020] usb 1-1.1.4: device not accepting address 67, error -71
11889 12:21:09.328689 <3>[ 104.528867] usb 1-1.1-port4: unable to enumerate USB device
11890 12:21:09.346011 <6>[ 104.542876] Freezing remaining freezable tasks completed (elapsed 2.449 seconds)
11891 12:21:09.352311 <6>[ 104.550571] printk: Suspending console(s) (use no_console_suspend to debug)
11892 12:21:12.663949 <3>[ 107.598211] mt7921e 0000:01:00.0: Message 00020007 (seq 5) timeout
11893 12:21:12.673658 <3>[ 107.598247] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11894 12:21:12.683452 <3>[ 107.598296] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11895 12:21:12.690291 <3>[ 107.598343] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11896 12:21:12.699993 <3>[ 107.598575] PM: Some devices failed to suspend, or early wake event detected
11897 12:21:12.703043 <6>[ 107.904230] OOM killer enabled.
11898 12:21:12.713958 <6>[ 107.907644] Restarting tasks ... done.
11899 12:21:12.717215 <5>[ 107.918579] random: crng reseeded on system resumption
11900 12:21:12.720982 <6>[ 107.924961] PM: suspend exit
11901 12:21:12.724487 rtcwake: write error
11902 12:21:12.732595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail>
11903 12:21:12.732863 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-5 RESULT=fail
11905 12:21:12.735573 rtcwake: assuming RTC uses UTC ...
11906 12:21:12.742175 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:21:19 2023
11907 12:21:12.755330 <6>[ 107.955677] PM: suspend entry (s2idle)
11908 12:21:12.758494 <6>[ 107.959765] Filesystems sync: 0.000 seconds
11909 12:21:12.764986 <6>[ 107.964791] Freezing user space processes
11910 12:21:12.771706 <6>[ 107.970674] Freezing user space processes completed (elapsed 0.001 seconds)
11911 12:21:12.774757 <6>[ 107.977891] OOM killer disabled.
11912 12:21:12.781903 <6>[ 107.981368] Freezing remaining freezable tasks
11913 12:21:12.793216 <6>[ 107.990090] usb 1-1.1.4: new full-speed USB device number 68 using xhci-mtk
11914 12:21:12.873197 <3>[ 108.074005] usb 1-1.1.4: device descriptor read/64, error -32
11915 12:21:13.065433 <3>[ 108.266248] usb 1-1.1.4: device descriptor read/64, error -32
11916 12:21:13.260713 <6>[ 108.458062] usb 1-1.1.4: new full-speed USB device number 69 using xhci-mtk
11917 12:21:13.345588 <3>[ 108.546238] usb 1-1.1.4: device descriptor read/64, error -32
11918 12:21:13.537810 <3>[ 108.738092] usb 1-1.1.4: device descriptor read/64, error -32
11919 12:21:13.649926 <6>[ 108.850309] usb 1-1.1-port4: attempt power cycle
11920 12:21:14.260400 <6>[ 109.458052] usb 1-1.1.4: new full-speed USB device number 70 using xhci-mtk
11921 12:21:14.267022 <4>[ 109.465438] usb 1-1.1.4: Device not responding to setup address.
11922 12:21:14.477663 <4>[ 109.678317] usb 1-1.1.4: Device not responding to setup address.
11923 12:21:14.689547 <3>[ 109.890177] usb 1-1.1.4: device not accepting address 70, error -71
11924 12:21:14.776743 <6>[ 109.974237] usb 1-1.1.4: new full-speed USB device number 71 using xhci-mtk
11925 12:21:14.783459 <4>[ 109.981623] usb 1-1.1.4: Device not responding to setup address.
11926 12:21:14.993075 <4>[ 110.194226] usb 1-1.1.4: Device not responding to setup address.
11927 12:21:15.205126 <3>[ 110.406043] usb 1-1.1.4: device not accepting address 71, error -71
11928 12:21:15.211995 <3>[ 110.412896] usb 1-1.1-port4: unable to enumerate USB device
11929 12:21:15.223431 <6>[ 110.421017] Freezing remaining freezable tasks completed (elapsed 2.434 seconds)
11930 12:21:15.230002 <6>[ 110.428714] printk: Suspending console(s) (use no_console_suspend to debug)
11931 12:21:18.551318 <3>[ 113.486230] mt7921e 0000:01:00.0: Message 00020007 (seq 6) timeout
11932 12:21:18.561188 <3>[ 113.486265] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11933 12:21:18.571241 <3>[ 113.486315] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11934 12:21:18.578398 <3>[ 113.486365] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11935 12:21:18.584582 <3>[ 113.486674] PM: Some devices failed to suspend, or early wake event detected
11936 12:21:18.591137 <6>[ 113.792484] OOM killer enabled.
11937 12:21:18.594612 <6>[ 113.795888] Restarting tasks ... done.
11938 12:21:18.601227 <5>[ 113.801643] random: crng reseeded on system resumption
11939 12:21:18.604828 <6>[ 113.807894] PM: suspend exit
11940 12:21:18.607640 rtcwake: write error
11941 12:21:18.614484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail>
11942 12:21:18.614746 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-6 RESULT=fail
11944 12:21:18.617766 rtcwake: assuming RTC uses UTC ...
11945 12:21:18.624823 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:21:25 2023
11946 12:21:18.637180 <6>[ 113.838375] PM: suspend entry (s2idle)
11947 12:21:18.640415 <6>[ 113.842440] Filesystems sync: 0.000 seconds
11948 12:21:18.644010 <6>[ 113.847473] Freezing user space processes
11949 12:21:18.655313 <6>[ 113.853388] Freezing user space processes completed (elapsed 0.001 seconds)
11950 12:21:18.658598 <6>[ 113.860616] OOM killer disabled.
11951 12:21:18.662223 <6>[ 113.864099] Freezing remaining freezable tasks
11952 12:21:18.683900 <6>[ 113.882021] usb 1-1.1.4: new full-speed USB device number 72 using xhci-mtk
11953 12:21:18.765256 <3>[ 113.966184] usb 1-1.1.4: device descriptor read/64, error -32
11954 12:21:18.957383 <3>[ 114.158103] usb 1-1.1.4: device descriptor read/64, error -32
11955 12:21:19.152518 <6>[ 114.350196] usb 1-1.1.4: new full-speed USB device number 73 using xhci-mtk
11956 12:21:19.237844 <3>[ 114.438099] usb 1-1.1.4: device descriptor read/64, error -32
11957 12:21:19.429339 <3>[ 114.630228] usb 1-1.1.4: device descriptor read/64, error -32
11958 12:21:19.541555 <6>[ 114.742447] usb 1-1.1-port4: attempt power cycle
11959 12:21:20.152651 <6>[ 115.350046] usb 1-1.1.4: new full-speed USB device number 74 using xhci-mtk
11960 12:21:20.158776 <4>[ 115.357430] usb 1-1.1.4: Device not responding to setup address.
11961 12:21:20.369684 <4>[ 115.570234] usb 1-1.1.4: Device not responding to setup address.
11962 12:21:20.580829 <3>[ 115.782043] usb 1-1.1.4: device not accepting address 74, error -71
11963 12:21:20.667842 <6>[ 115.866071] usb 1-1.1.4: new full-speed USB device number 75 using xhci-mtk
11964 12:21:20.674467 <4>[ 115.873454] usb 1-1.1.4: Device not responding to setup address.
11965 12:21:20.885293 <4>[ 116.086339] usb 1-1.1.4: Device not responding to setup address.
11966 12:21:21.096913 <3>[ 116.298180] usb 1-1.1.4: device not accepting address 75, error -71
11967 12:21:21.103901 <3>[ 116.305042] usb 1-1.1-port4: unable to enumerate USB device
11968 12:21:21.119676 <6>[ 116.318207] Freezing remaining freezable tasks completed (elapsed 2.449 seconds)
11969 12:21:21.126493 <6>[ 116.325901] printk: Suspending console(s) (use no_console_suspend to debug)
11970 12:21:24.439344 <3>[ 119.374214] mt7921e 0000:01:00.0: Message 00020007 (seq 7) timeout
11971 12:21:24.448620 <3>[ 119.374250] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
11972 12:21:24.458631 <3>[ 119.374299] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
11973 12:21:24.465495 <3>[ 119.374345] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
11974 12:21:24.475010 <3>[ 119.374630] PM: Some devices failed to suspend, or early wake event detected
11975 12:21:24.478487 <6>[ 119.680316] OOM killer enabled.
11976 12:21:24.481979 <6>[ 119.683733] Restarting tasks ... done.
11977 12:21:24.488382 <5>[ 119.689824] random: crng reseeded on system resumption
11978 12:21:24.492026 <6>[ 119.696514] PM: suspend exit
11979 12:21:24.495388 rtcwake: write error
11980 12:21:24.503461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail>
11981 12:21:24.504197 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-7 RESULT=fail
11983 12:21:24.506509 rtcwake: assuming RTC uses UTC ...
11984 12:21:24.513224 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:21:30 2023
11985 12:21:24.525815 <6>[ 119.727167] PM: suspend entry (s2idle)
11986 12:21:24.528884 <6>[ 119.731246] Filesystems sync: 0.000 seconds
11987 12:21:24.535717 <6>[ 119.736316] Freezing user space processes
11988 12:21:24.542404 <6>[ 119.741994] Freezing user space processes completed (elapsed 0.001 seconds)
11989 12:21:24.545298 <6>[ 119.749215] OOM killer disabled.
11990 12:21:24.551911 <6>[ 119.752695] Freezing remaining freezable tasks
11991 12:21:24.568090 <6>[ 119.766045] usb 1-1.1.4: new full-speed USB device number 76 using xhci-mtk
11992 12:21:24.652904 <3>[ 119.854176] usb 1-1.1.4: device descriptor read/64, error -32
11993 12:21:24.844377 <3>[ 120.046104] usb 1-1.1.4: device descriptor read/64, error -32
11994 12:21:25.039802 <6>[ 120.238195] usb 1-1.1.4: new full-speed USB device number 77 using xhci-mtk
11995 12:21:25.124396 <3>[ 120.326254] usb 1-1.1.4: device descriptor read/64, error -32
11996 12:21:25.316454 <3>[ 120.518229] usb 1-1.1.4: device descriptor read/64, error -32
11997 12:21:25.429094 <6>[ 120.630452] usb 1-1.1-port4: attempt power cycle
11998 12:21:26.039900 <6>[ 121.238188] usb 1-1.1.4: new full-speed USB device number 78 using xhci-mtk
11999 12:21:26.046402 <4>[ 121.245575] usb 1-1.1.4: Device not responding to setup address.
12000 12:21:26.256442 <4>[ 121.458140] usb 1-1.1.4: Device not responding to setup address.
12001 12:21:26.468379 <3>[ 121.670177] usb 1-1.1.4: device not accepting address 78, error -71
12002 12:21:26.556099 <6>[ 121.754187] usb 1-1.1.4: new full-speed USB device number 79 using xhci-mtk
12003 12:21:26.562740 <4>[ 121.761616] usb 1-1.1.4: Device not responding to setup address.
12004 12:21:26.772757 <4>[ 121.974264] usb 1-1.1.4: Device not responding to setup address.
12005 12:21:26.984015 <3>[ 122.186045] usb 1-1.1.4: device not accepting address 79, error -71
12006 12:21:26.991025 <3>[ 122.192937] usb 1-1.1-port4: unable to enumerate USB device
12007 12:21:27.001677 <6>[ 122.200287] Freezing remaining freezable tasks completed (elapsed 2.442 seconds)
12008 12:21:27.008418 <6>[ 122.207984] printk: Suspending console(s) (use no_console_suspend to debug)
12009 12:21:30.333890 <3>[ 125.262212] mt7921e 0000:01:00.0: Message 00020007 (seq 8) timeout
12010 12:21:30.343805 <3>[ 125.262247] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12011 12:21:30.353581 <3>[ 125.262297] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12012 12:21:30.360606 <3>[ 125.262343] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12013 12:21:30.370534 <3>[ 125.262703] PM: Some devices failed to suspend, or early wake event detected
12014 12:21:30.373622 <6>[ 125.576150] OOM killer enabled.
12015 12:21:30.380336 <6>[ 125.579565] Restarting tasks ... done.
12016 12:21:30.383636 <5>[ 125.586926] random: crng reseeded on system resumption
12017 12:21:30.388045 <6>[ 125.593624] PM: suspend exit
12018 12:21:30.391258 rtcwake: write error
12019 12:21:30.399194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail>
12020 12:21:30.399965 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-8 RESULT=fail
12022 12:21:30.402408 rtcwake: assuming RTC uses UTC ...
12023 12:21:30.408928 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:21:36 2023
12024 12:21:30.421727 <6>[ 125.624151] PM: suspend entry (s2idle)
12025 12:21:30.425231 <6>[ 125.628228] Filesystems sync: 0.000 seconds
12026 12:21:30.431612 <6>[ 125.633324] Freezing user space processes
12027 12:21:30.438484 <6>[ 125.639339] Freezing user space processes completed (elapsed 0.001 seconds)
12028 12:21:30.441464 <6>[ 125.646568] OOM killer disabled.
12029 12:21:30.448066 <6>[ 125.650046] Freezing remaining freezable tasks
12030 12:21:30.463374 <6>[ 125.662046] usb 1-1.1.4: new full-speed USB device number 80 using xhci-mtk
12031 12:21:30.543859 <3>[ 125.746103] usb 1-1.1.4: device descriptor read/64, error -32
12032 12:21:30.736194 <3>[ 125.938099] usb 1-1.1.4: device descriptor read/64, error -32
12033 12:21:30.930852 <6>[ 126.130079] usb 1-1.1.4: new full-speed USB device number 81 using xhci-mtk
12034 12:21:31.016105 <3>[ 126.218099] usb 1-1.1.4: device descriptor read/64, error -32
12035 12:21:31.207783 <3>[ 126.410229] usb 1-1.1.4: device descriptor read/64, error -32
12036 12:21:31.319665 <6>[ 126.522451] usb 1-1.1-port4: attempt power cycle
12037 12:21:31.930891 <6>[ 127.130189] usb 1-1.1.4: new full-speed USB device number 82 using xhci-mtk
12038 12:21:31.937640 <4>[ 127.137589] usb 1-1.1.4: Device not responding to setup address.
12039 12:21:32.147678 <4>[ 127.350399] usb 1-1.1.4: Device not responding to setup address.
12040 12:21:32.359180 <3>[ 127.562046] usb 1-1.1.4: device not accepting address 82, error -71
12041 12:21:32.446393 <6>[ 127.646053] usb 1-1.1.4: new full-speed USB device number 83 using xhci-mtk
12042 12:21:32.452854 <4>[ 127.653441] usb 1-1.1.4: Device not responding to setup address.
12043 12:21:32.663341 <4>[ 127.866182] usb 1-1.1.4: Device not responding to setup address.
12044 12:21:32.876057 <3>[ 128.078240] usb 1-1.1.4: device not accepting address 83, error -71
12045 12:21:32.882351 <3>[ 128.085102] usb 1-1.1-port4: unable to enumerate USB device
12046 12:21:32.896774 <6>[ 128.096337] Freezing remaining freezable tasks completed (elapsed 2.441 seconds)
12047 12:21:32.903720 <6>[ 128.104033] printk: Suspending console(s) (use no_console_suspend to debug)
12048 12:21:36.213999 <3>[ 131.150199] mt7921e 0000:01:00.0: Message 00020007 (seq 9) timeout
12049 12:21:36.223613 <3>[ 131.150234] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12050 12:21:36.233792 <3>[ 131.150284] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12051 12:21:36.240180 <3>[ 131.150330] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12052 12:21:36.250198 <3>[ 131.150682] PM: Some devices failed to suspend, or early wake event detected
12053 12:21:36.253477 <6>[ 131.456470] OOM killer enabled.
12054 12:21:36.257084 <6>[ 131.459885] Restarting tasks ... done.
12055 12:21:36.263503 <5>[ 131.466020] random: crng reseeded on system resumption
12056 12:21:36.266788 <6>[ 131.472277] PM: suspend exit
12057 12:21:36.270130 rtcwake: write error
12058 12:21:36.277699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail>
12059 12:21:36.278623 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-9 RESULT=fail
12061 12:21:36.280531 rtcwake: assuming RTC uses UTC ...
12062 12:21:36.287145 rtcwake: wakeup from "freeze" using rtc0 at Fri Oct 27 12:21:42 2023
12063 12:21:36.300414 <6>[ 131.503139] PM: suspend entry (s2idle)
12064 12:21:36.303670 <6>[ 131.507212] Filesystems sync: 0.000 seconds
12065 12:21:36.309803 <6>[ 131.512203] Freezing user space processes
12066 12:21:36.316893 <6>[ 131.518148] Freezing user space processes completed (elapsed 0.001 seconds)
12067 12:21:36.319991 <6>[ 131.525374] OOM killer disabled.
12068 12:21:36.326938 <6>[ 131.528857] Freezing remaining freezable tasks
12069 12:21:36.346376 <6>[ 131.545997] usb 1-1.1.4: new full-speed USB device number 84 using xhci-mtk
12070 12:21:36.426954 <3>[ 131.630182] usb 1-1.1.4: device descriptor read/64, error -32
12071 12:21:36.618807 <3>[ 131.822103] usb 1-1.1.4: device descriptor read/64, error -32
12072 12:21:36.814323 <6>[ 132.014197] usb 1-1.1.4: new full-speed USB device number 85 using xhci-mtk
12073 12:21:36.899218 <3>[ 132.102096] usb 1-1.1.4: device descriptor read/64, error -32
12074 12:21:37.090919 <3>[ 132.294227] usb 1-1.1.4: device descriptor read/64, error -32
12075 12:21:37.203029 <6>[ 132.406445] usb 1-1.1-port4: attempt power cycle
12076 12:21:37.813656 <6>[ 133.014030] usb 1-1.1.4: new full-speed USB device number 86 using xhci-mtk
12077 12:21:37.820447 <4>[ 133.021407] usb 1-1.1.4: Device not responding to setup address.
12078 12:21:38.030758 <4>[ 133.234232] usb 1-1.1.4: Device not responding to setup address.
12079 12:21:38.242461 <3>[ 133.446045] usb 1-1.1.4: device not accepting address 86, error -71
12080 12:21:38.330001 <6>[ 133.530188] usb 1-1.1.4: new full-speed USB device number 87 using xhci-mtk
12081 12:21:38.336593 <4>[ 133.537580] usb 1-1.1.4: Device not responding to setup address.
12082 12:21:38.546484 <4>[ 133.750317] usb 1-1.1.4: Device not responding to setup address.
12083 12:21:38.758471 <3>[ 133.962080] usb 1-1.1.4: device not accepting address 87, error -71
12084 12:21:38.765150 <3>[ 133.968936] usb 1-1.1-port4: unable to enumerate USB device
12085 12:21:38.782123 <6>[ 133.982460] Freezing remaining freezable tasks completed (elapsed 2.448 seconds)
12086 12:21:38.788485 <6>[ 133.990160] printk: Suspending console(s) (use no_console_suspend to debug)
12087 12:21:42.100411 <3>[ 137.038241] mt7921e 0000:01:00.0: Message 00020007 (seq 10) timeout
12088 12:21:42.113895 <3>[ 137.038278] mt7921e 0000:01:00.0: PM: pci_pm_suspend(): mt7921_pci_suspend+0x0/0x280 [mt7921e] returns -110
12089 12:21:42.120891 <3>[ 137.038334] mt7921e 0000:01:00.0: PM: dpm_run_callback(): pci_pm_suspend+0x0/0x1c0 returns -110
12090 12:21:42.127417 <3>[ 137.038385] mt7921e 0000:01:00.0: PM: failed to suspend async: error -110
12091 12:21:42.137041 <3>[ 137.038648] PM: Some devices failed to suspend, or early wake event detected
12092 12:21:42.140537 <6>[ 137.344673] OOM killer enabled.
12093 12:21:42.143992 <6>[ 137.348089] Restarting tasks ... done.
12094 12:21:42.150344 <5>[ 137.354192] random: crng reseeded on system resumption
12095 12:21:42.153720 <6>[ 137.360678] PM: suspend exit
12096 12:21:42.157009 rtcwake: write error
12097 12:21:42.164837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail>
12098 12:21:42.165137 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-freeze-10 RESULT=fail
12100 12:21:42.167955 + set +x
12101 12:21:42.171386 <LAVA_SIGNAL_ENDRUN 0_sleep 11893112_1.5.2.3.1>
12102 12:21:42.171469 <LAVA_TEST_RUNNER EXIT>
12103 12:21:42.171709 Received signal: <ENDRUN> 0_sleep 11893112_1.5.2.3.1
12104 12:21:42.171840 Ending use of test pattern.
12105 12:21:42.171903 Ending test lava.0_sleep (11893112_1.5.2.3.1), duration 115.35
12107 12:21:42.172160 ok: lava_test_shell seems to have completed
12108 12:21:42.172381 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-freeze-1: fail
rtcwake-freeze-10: fail
rtcwake-freeze-2: fail
rtcwake-freeze-3: fail
rtcwake-freeze-4: fail
rtcwake-freeze-5: fail
rtcwake-freeze-6: fail
rtcwake-freeze-7: fail
rtcwake-freeze-8: fail
rtcwake-freeze-9: fail
rtcwake-mem-1: fail
rtcwake-mem-10: fail
rtcwake-mem-2: fail
rtcwake-mem-3: fail
rtcwake-mem-4: fail
rtcwake-mem-5: fail
rtcwake-mem-6: fail
rtcwake-mem-7: fail
rtcwake-mem-8: fail
rtcwake-mem-9: fail
12109 12:21:42.172485 end: 3.1 lava-test-shell (duration 00:01:56) [common]
12110 12:21:42.172577 end: 3 lava-test-retry (duration 00:01:56) [common]
12111 12:21:42.172662 start: 4 finalize (timeout 00:05:31) [common]
12112 12:21:42.172761 start: 4.1 power-off (timeout 00:00:30) [common]
12113 12:21:42.172913 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
12114 12:21:42.250522 >> Command sent successfully.
12115 12:21:42.253225 Returned 0 in 0 seconds
12116 12:21:42.353615 end: 4.1 power-off (duration 00:00:00) [common]
12118 12:21:42.353944 start: 4.2 read-feedback (timeout 00:05:31) [common]
12119 12:21:42.354216 Listened to connection for namespace 'common' for up to 1s
12121 12:21:42.354591 Listened to connection for namespace 'common' for up to 1s
12122 12:21:43.355156 Finalising connection for namespace 'common'
12123 12:21:43.355331 Disconnecting from shell: Finalise
12124 12:21:43.455727 end: 4.2 read-feedback (duration 00:00:01) [common]
12125 12:21:43.455928 end: 4 finalize (duration 00:00:01) [common]
12126 12:21:43.456054 Cleaning after the job
12127 12:21:43.456177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/ramdisk
12128 12:21:43.469177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/kernel
12129 12:21:43.491680 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/dtb
12130 12:21:43.491942 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893112/tftp-deploy-13d80pt7/modules
12131 12:21:43.498800 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893112
12132 12:21:43.673257 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893112
12133 12:21:43.673436 Job finished correctly