Boot log: mt8192-asurada-spherion-r0
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: UNKNOWN
1 12:20:21.243106 lava-dispatcher, installed at version: 2023.08
2 12:20:21.243304 start: 0 validate
3 12:20:21.243433 Start time: 2023-10-27 12:20:21.243425+00:00 (UTC)
4 12:20:21.243562 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:20:21.243691 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:20:21.516169 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:20:21.516351 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:20:21.781185 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:20:21.781369 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:20:22.039556 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:20:22.040230 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:20:22.314950 validate duration: 1.07
14 12:20:22.316438 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:20:22.317051 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:20:22.317562 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:20:22.318208 Not decompressing ramdisk as can be used compressed.
18 12:20:22.318707 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 12:20:22.319082 saving as /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/ramdisk/rootfs.cpio.gz
20 12:20:22.319441 total size: 26246609 (25 MB)
21 12:20:22.326537 progress 0 % (0 MB)
22 12:20:22.353038 progress 5 % (1 MB)
23 12:20:22.365222 progress 10 % (2 MB)
24 12:20:22.374366 progress 15 % (3 MB)
25 12:20:22.382010 progress 20 % (5 MB)
26 12:20:22.388813 progress 25 % (6 MB)
27 12:20:22.395453 progress 30 % (7 MB)
28 12:20:22.402057 progress 35 % (8 MB)
29 12:20:22.408627 progress 40 % (10 MB)
30 12:20:22.415173 progress 45 % (11 MB)
31 12:20:22.424601 progress 50 % (12 MB)
32 12:20:22.434036 progress 55 % (13 MB)
33 12:20:22.444490 progress 60 % (15 MB)
34 12:20:22.453972 progress 65 % (16 MB)
35 12:20:22.463450 progress 70 % (17 MB)
36 12:20:22.473791 progress 75 % (18 MB)
37 12:20:22.482669 progress 80 % (20 MB)
38 12:20:22.491343 progress 85 % (21 MB)
39 12:20:22.502081 progress 90 % (22 MB)
40 12:20:22.511212 progress 95 % (23 MB)
41 12:20:22.520665 progress 100 % (25 MB)
42 12:20:22.520917 25 MB downloaded in 0.20 s (124.23 MB/s)
43 12:20:22.521125 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:20:22.521369 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:20:22.521457 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:20:22.521540 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:20:22.521672 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:20:22.521750 saving as /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/kernel/Image
50 12:20:22.521812 total size: 49236480 (46 MB)
51 12:20:22.521874 No compression specified
52 12:20:22.522967 progress 0 % (0 MB)
53 12:20:22.535430 progress 5 % (2 MB)
54 12:20:22.547819 progress 10 % (4 MB)
55 12:20:22.560057 progress 15 % (7 MB)
56 12:20:22.572298 progress 20 % (9 MB)
57 12:20:22.584795 progress 25 % (11 MB)
58 12:20:22.597604 progress 30 % (14 MB)
59 12:20:22.610059 progress 35 % (16 MB)
60 12:20:22.623090 progress 40 % (18 MB)
61 12:20:22.635552 progress 45 % (21 MB)
62 12:20:22.648660 progress 50 % (23 MB)
63 12:20:22.661087 progress 55 % (25 MB)
64 12:20:22.673660 progress 60 % (28 MB)
65 12:20:22.686338 progress 65 % (30 MB)
66 12:20:22.698753 progress 70 % (32 MB)
67 12:20:22.711141 progress 75 % (35 MB)
68 12:20:22.724487 progress 80 % (37 MB)
69 12:20:22.737001 progress 85 % (39 MB)
70 12:20:22.749550 progress 90 % (42 MB)
71 12:20:22.762342 progress 95 % (44 MB)
72 12:20:22.774510 progress 100 % (46 MB)
73 12:20:22.774712 46 MB downloaded in 0.25 s (185.67 MB/s)
74 12:20:22.774863 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:20:22.775094 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:20:22.775181 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:20:22.775272 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:20:22.775401 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:20:22.775471 saving as /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/dtb/mt8192-asurada-spherion-r0.dtb
81 12:20:22.775537 total size: 47278 (0 MB)
82 12:20:22.775601 No compression specified
83 12:20:22.776834 progress 69 % (0 MB)
84 12:20:22.777147 progress 100 % (0 MB)
85 12:20:22.777333 0 MB downloaded in 0.00 s (25.13 MB/s)
86 12:20:22.777458 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:20:22.777678 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:20:22.777762 start: 1.4 download-retry (timeout 00:10:00) [common]
90 12:20:22.777844 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 12:20:22.777955 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:20:22.778053 saving as /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/modules/modules.tar
93 12:20:22.778114 total size: 8625084 (8 MB)
94 12:20:22.778176 Using unxz to decompress xz
95 12:20:22.781819 progress 0 % (0 MB)
96 12:20:22.803586 progress 5 % (0 MB)
97 12:20:22.826102 progress 10 % (0 MB)
98 12:20:22.851896 progress 15 % (1 MB)
99 12:20:22.876650 progress 20 % (1 MB)
100 12:20:22.902481 progress 25 % (2 MB)
101 12:20:22.927858 progress 30 % (2 MB)
102 12:20:22.955004 progress 35 % (2 MB)
103 12:20:22.979548 progress 40 % (3 MB)
104 12:20:23.003694 progress 45 % (3 MB)
105 12:20:23.030844 progress 50 % (4 MB)
106 12:20:23.055681 progress 55 % (4 MB)
107 12:20:23.079940 progress 60 % (4 MB)
108 12:20:23.104117 progress 65 % (5 MB)
109 12:20:23.128953 progress 70 % (5 MB)
110 12:20:23.152580 progress 75 % (6 MB)
111 12:20:23.178473 progress 80 % (6 MB)
112 12:20:23.207339 progress 85 % (7 MB)
113 12:20:23.234561 progress 90 % (7 MB)
114 12:20:23.260351 progress 95 % (7 MB)
115 12:20:23.283345 progress 100 % (8 MB)
116 12:20:23.288198 8 MB downloaded in 0.51 s (16.13 MB/s)
117 12:20:23.288425 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:20:23.288678 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:20:23.288769 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:20:23.288864 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:20:23.288988 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:20:23.289073 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:20:23.289280 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y
125 12:20:23.289407 makedir: /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin
126 12:20:23.289507 makedir: /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/tests
127 12:20:23.289602 makedir: /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/results
128 12:20:23.289717 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-add-keys
129 12:20:23.289859 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-add-sources
130 12:20:23.289986 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-background-process-start
131 12:20:23.290111 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-background-process-stop
132 12:20:23.290232 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-common-functions
133 12:20:23.290352 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-echo-ipv4
134 12:20:23.290472 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-install-packages
135 12:20:23.290592 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-installed-packages
136 12:20:23.290709 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-os-build
137 12:20:23.290828 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-probe-channel
138 12:20:23.290947 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-probe-ip
139 12:20:23.291065 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-target-ip
140 12:20:23.291181 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-target-mac
141 12:20:23.291298 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-target-storage
142 12:20:23.291420 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-test-case
143 12:20:23.291540 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-test-event
144 12:20:23.291659 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-test-feedback
145 12:20:23.291777 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-test-raise
146 12:20:23.291898 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-test-reference
147 12:20:23.292017 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-test-runner
148 12:20:23.292135 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-test-set
149 12:20:23.292256 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-test-shell
150 12:20:23.292377 Updating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-install-packages (oe)
151 12:20:23.292520 Updating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/bin/lava-installed-packages (oe)
152 12:20:23.292642 Creating /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/environment
153 12:20:23.292743 LAVA metadata
154 12:20:23.292818 - LAVA_JOB_ID=11893133
155 12:20:23.292915 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:20:23.293062 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:20:23.293130 skipped lava-vland-overlay
158 12:20:23.293203 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:20:23.293286 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:20:23.293349 skipped lava-multinode-overlay
161 12:20:23.293423 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:20:23.293507 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:20:23.293581 Loading test definitions
164 12:20:23.293669 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:20:23.293740 Using /lava-11893133 at stage 0
166 12:20:23.294031 uuid=11893133_1.5.2.3.1 testdef=None
167 12:20:23.294119 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:20:23.294205 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:20:23.294700 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:20:23.294920 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:20:23.295566 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:20:23.295912 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:20:23.296748 runner path: /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 11893133_1.5.2.3.1
176 12:20:23.296937 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:20:23.297280 Creating lava-test-runner.conf files
179 12:20:23.297372 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893133/lava-overlay-tuz5pj1y/lava-11893133/0 for stage 0
180 12:20:23.297490 - 0_v4l2-compliance-mtk-vcodec-enc
181 12:20:23.297619 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:20:23.297736 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:20:23.304393 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:20:23.304496 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:20:23.304580 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:20:23.304662 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:20:23.304745 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:20:23.975948 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:20:23.976326 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:20:23.976477 extracting modules file /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893133/extract-overlay-ramdisk-wi_4yan8/ramdisk
191 12:20:24.222508 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:20:24.222682 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:20:24.222779 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893133/compress-overlay-ugpef3xk/overlay-1.5.2.4.tar.gz to ramdisk
194 12:20:24.222849 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893133/compress-overlay-ugpef3xk/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893133/extract-overlay-ramdisk-wi_4yan8/ramdisk
195 12:20:24.229322 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:20:24.229438 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:20:24.229525 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:20:24.229624 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:20:24.229704 Building ramdisk /var/lib/lava/dispatcher/tmp/11893133/extract-overlay-ramdisk-wi_4yan8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893133/extract-overlay-ramdisk-wi_4yan8/ramdisk
200 12:20:24.924756 >> 228399 blocks
201 12:20:28.728390 rename /var/lib/lava/dispatcher/tmp/11893133/extract-overlay-ramdisk-wi_4yan8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/ramdisk/ramdisk.cpio.gz
202 12:20:28.728817 end: 1.5.7 compress-ramdisk (duration 00:00:04) [common]
203 12:20:28.728959 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 12:20:28.729082 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 12:20:28.729189 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/kernel/Image'
206 12:20:40.845097 Returned 0 in 12 seconds
207 12:20:40.945968 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/kernel/image.itb
208 12:20:41.495579 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:20:41.495931 output: Created: Fri Oct 27 13:20:41 2023
210 12:20:41.496010 output: Image 0 (kernel-1)
211 12:20:41.496075 output: Description:
212 12:20:41.496138 output: Created: Fri Oct 27 13:20:41 2023
213 12:20:41.496199 output: Type: Kernel Image
214 12:20:41.496259 output: Compression: lzma compressed
215 12:20:41.496317 output: Data Size: 11047994 Bytes = 10789.06 KiB = 10.54 MiB
216 12:20:41.496375 output: Architecture: AArch64
217 12:20:41.496434 output: OS: Linux
218 12:20:41.496491 output: Load Address: 0x00000000
219 12:20:41.496548 output: Entry Point: 0x00000000
220 12:20:41.496604 output: Hash algo: crc32
221 12:20:41.496665 output: Hash value: d33b93ae
222 12:20:41.496752 output: Image 1 (fdt-1)
223 12:20:41.496837 output: Description: mt8192-asurada-spherion-r0
224 12:20:41.496920 output: Created: Fri Oct 27 13:20:41 2023
225 12:20:41.496988 output: Type: Flat Device Tree
226 12:20:41.497042 output: Compression: uncompressed
227 12:20:41.497096 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:20:41.497149 output: Architecture: AArch64
229 12:20:41.497202 output: Hash algo: crc32
230 12:20:41.497256 output: Hash value: cc4352de
231 12:20:41.497312 output: Image 2 (ramdisk-1)
232 12:20:41.497366 output: Description: unavailable
233 12:20:41.497419 output: Created: Fri Oct 27 13:20:41 2023
234 12:20:41.497473 output: Type: RAMDisk Image
235 12:20:41.497525 output: Compression: Unknown Compression
236 12:20:41.497578 output: Data Size: 39363440 Bytes = 38440.86 KiB = 37.54 MiB
237 12:20:41.497632 output: Architecture: AArch64
238 12:20:41.497684 output: OS: Linux
239 12:20:41.497737 output: Load Address: unavailable
240 12:20:41.497790 output: Entry Point: unavailable
241 12:20:41.497843 output: Hash algo: crc32
242 12:20:41.497895 output: Hash value: be996fea
243 12:20:41.497947 output: Default Configuration: 'conf-1'
244 12:20:41.497999 output: Configuration 0 (conf-1)
245 12:20:41.498051 output: Description: mt8192-asurada-spherion-r0
246 12:20:41.498104 output: Kernel: kernel-1
247 12:20:41.498156 output: Init Ramdisk: ramdisk-1
248 12:20:41.498209 output: FDT: fdt-1
249 12:20:41.498261 output: Loadables: kernel-1
250 12:20:41.498313 output:
251 12:20:41.498496 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:20:41.498597 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:20:41.498697 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 12:20:41.498793 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 12:20:41.498870 No LXC device requested
256 12:20:41.498948 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:20:41.499033 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 12:20:41.499109 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:20:41.499178 Checking files for TFTP limit of 4294967296 bytes.
260 12:20:41.499651 end: 1 tftp-deploy (duration 00:00:19) [common]
261 12:20:41.499750 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:20:41.499839 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:20:41.499956 substitutions:
264 12:20:41.500022 - {DTB}: 11893133/tftp-deploy-znijld6f/dtb/mt8192-asurada-spherion-r0.dtb
265 12:20:41.500084 - {INITRD}: 11893133/tftp-deploy-znijld6f/ramdisk/ramdisk.cpio.gz
266 12:20:41.500143 - {KERNEL}: 11893133/tftp-deploy-znijld6f/kernel/Image
267 12:20:41.500204 - {LAVA_MAC}: None
268 12:20:41.500261 - {PRESEED_CONFIG}: None
269 12:20:41.500316 - {PRESEED_LOCAL}: None
270 12:20:41.500370 - {RAMDISK}: 11893133/tftp-deploy-znijld6f/ramdisk/ramdisk.cpio.gz
271 12:20:41.500425 - {ROOT_PART}: None
272 12:20:41.500479 - {ROOT}: None
273 12:20:41.500532 - {SERVER_IP}: 192.168.201.1
274 12:20:41.500586 - {TEE}: None
275 12:20:41.500639 Parsed boot commands:
276 12:20:41.500693 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:20:41.500883 Parsed boot commands: tftpboot 192.168.201.1 11893133/tftp-deploy-znijld6f/kernel/image.itb 11893133/tftp-deploy-znijld6f/kernel/cmdline
278 12:20:41.500996 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:20:41.501083 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:20:41.501176 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:20:41.501265 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:20:41.501332 Not connected, no need to disconnect.
283 12:20:41.501405 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:20:41.501485 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:20:41.501549 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
286 12:20:41.504795 Setting prompt string to ['lava-test: # ']
287 12:20:41.505167 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:20:41.505276 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:20:41.505372 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:20:41.505461 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:20:41.505654 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 12:20:46.654189 >> Command sent successfully.
293 12:20:46.665721 Returned 0 in 5 seconds
294 12:20:46.766949 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:20:46.769136 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:20:46.769996 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:20:46.770644 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:20:46.771217 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:20:46.771764 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:20:46.773447 [Enter `^Ec?' for help]
302 12:20:46.931843
303 12:20:46.932437
304 12:20:46.932823 F0: 102B 0000
305 12:20:46.933262
306 12:20:46.933614 F3: 1001 0000 [0200]
307 12:20:46.935375
308 12:20:46.935945 F3: 1001 0000
309 12:20:46.936382
310 12:20:46.936735 F7: 102D 0000
311 12:20:46.937152
312 12:20:46.938445 F1: 0000 0000
313 12:20:46.938916
314 12:20:46.939290 V0: 0000 0000 [0001]
315 12:20:46.939639
316 12:20:46.941910 00: 0007 8000
317 12:20:46.942406
318 12:20:46.942780 01: 0000 0000
319 12:20:46.943135
320 12:20:46.945199 BP: 0C00 0209 [0000]
321 12:20:46.945669
322 12:20:46.946040 G0: 1182 0000
323 12:20:46.946387
324 12:20:46.948570 EC: 0000 0021 [4000]
325 12:20:46.949080
326 12:20:46.949549 S7: 0000 0000 [0000]
327 12:20:46.949909
328 12:20:46.952307 CC: 0000 0000 [0001]
329 12:20:46.952792
330 12:20:46.953266 T0: 0000 0040 [010F]
331 12:20:46.953643
332 12:20:46.955434 Jump to BL
333 12:20:46.955957
334 12:20:46.979282
335 12:20:46.979845
336 12:20:46.980217
337 12:20:46.986808 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:20:46.990257 ARM64: Exception handlers installed.
339 12:20:46.994056 ARM64: Testing exception
340 12:20:46.994596 ARM64: Done test exception
341 12:20:47.004923 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:20:47.014361 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:20:47.021618 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:20:47.031452 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:20:47.037781 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:20:47.045165 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:20:47.055720 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:20:47.062355 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:20:47.081656 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:20:47.085240 WDT: Last reset was cold boot
351 12:20:47.088325 SPI1(PAD0) initialized at 2873684 Hz
352 12:20:47.091839 SPI5(PAD0) initialized at 992727 Hz
353 12:20:47.095538 VBOOT: Loading verstage.
354 12:20:47.101829 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:20:47.105157 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:20:47.108594 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:20:47.111994 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:20:47.118966 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:20:47.126263 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:20:47.136769 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 12:20:47.137410
362 12:20:47.137797
363 12:20:47.147064 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:20:47.150548 ARM64: Exception handlers installed.
365 12:20:47.153574 ARM64: Testing exception
366 12:20:47.154059 ARM64: Done test exception
367 12:20:47.160152 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:20:47.163261 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:20:47.178081 Probing TPM: . done!
370 12:20:47.178679 TPM ready after 0 ms
371 12:20:47.184595 Connected to device vid:did:rid of 1ae0:0028:00
372 12:20:47.191500 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:20:47.194851 Initialized TPM device CR50 revision 0
374 12:20:47.260173 tlcl_send_startup: Startup return code is 0
375 12:20:47.260737 TPM: setup succeeded
376 12:20:47.271501 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:20:47.280189 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:20:47.290409 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:20:47.299555 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:20:47.302839 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:20:47.312227 in-header: 03 07 00 00 08 00 00 00
382 12:20:47.315572 in-data: aa e4 47 04 13 02 00 00
383 12:20:47.319125 Chrome EC: UHEPI supported
384 12:20:47.326445 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:20:47.330497 in-header: 03 ad 00 00 08 00 00 00
386 12:20:47.334083 in-data: 00 20 20 08 00 00 00 00
387 12:20:47.334587 Phase 1
388 12:20:47.337614 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:20:47.345041 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:20:47.348718 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:20:47.352340 Recovery requested (1009000e)
392 12:20:47.361365 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:20:47.366988 tlcl_extend: response is 0
394 12:20:47.376149 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:20:47.382318 tlcl_extend: response is 0
396 12:20:47.389176 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:20:47.409012 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:20:47.416251 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:20:47.416815
400 12:20:47.417259
401 12:20:47.426461 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:20:47.429634 ARM64: Exception handlers installed.
403 12:20:47.430111 ARM64: Testing exception
404 12:20:47.432925 ARM64: Done test exception
405 12:20:47.454358 pmic_efuse_setting: Set efuses in 11 msecs
406 12:20:47.457768 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:20:47.465103 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:20:47.468435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:20:47.471894 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:20:47.478608 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:20:47.482048 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:20:47.489185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:20:47.492655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:20:47.496715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:20:47.500034 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:20:47.507352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:20:47.511382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:20:47.514981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:20:47.518453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:20:47.525830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:20:47.532224 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:20:47.539704 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:20:47.543060 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:20:47.550863 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:20:47.554271 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:20:47.560683 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:20:47.564758 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:20:47.571869 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:20:47.578728 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:20:47.581574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:20:47.588518 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:20:47.595222 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:20:47.598776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:20:47.605100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:20:47.608416 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:20:47.611570 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:20:47.618319 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:20:47.621470 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:20:47.628196 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:20:47.631735 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:20:47.638605 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:20:47.641556 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:20:47.649171 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:20:47.651997 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:20:47.658281 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:20:47.661694 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:20:47.665903 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:20:47.669839 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:20:47.676211 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:20:47.679687 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:20:47.683227 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:20:47.690214 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:20:47.693028 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:20:47.696567 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:20:47.699955 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:20:47.706423 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:20:47.709854 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:20:47.717822 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:20:47.724569 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:20:47.728129 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:20:47.739784 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:20:47.746953 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:20:47.751086 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:20:47.754624 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:20:47.758468 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:20:47.767232 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xa
467 12:20:47.771013 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:20:47.778943 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:20:47.781578 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:20:47.791890 [RTC]rtc_get_frequency_meter,154: input=15, output=774
471 12:20:47.800859 [RTC]rtc_get_frequency_meter,154: input=23, output=957
472 12:20:47.810201 [RTC]rtc_get_frequency_meter,154: input=19, output=863
473 12:20:47.820058 [RTC]rtc_get_frequency_meter,154: input=17, output=820
474 12:20:47.830041 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 12:20:47.833268 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 12:20:47.836604 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 12:20:47.843650 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
478 12:20:47.847519 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 12:20:47.851186 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 12:20:47.855051 ADC[4]: Raw value=903614 ID=7
481 12:20:47.855619 ADC[3]: Raw value=213179 ID=1
482 12:20:47.858150 RAM Code: 0x71
483 12:20:47.861477 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 12:20:47.868500 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 12:20:47.874618 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 12:20:47.881659 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 12:20:47.884815 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 12:20:47.888041 in-header: 03 07 00 00 08 00 00 00
489 12:20:47.891694 in-data: aa e4 47 04 13 02 00 00
490 12:20:47.895076 Chrome EC: UHEPI supported
491 12:20:47.901638 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 12:20:47.905239 in-header: 03 ed 00 00 08 00 00 00
493 12:20:47.908208 in-data: 80 20 60 08 00 00 00 00
494 12:20:47.911706 MRC: failed to locate region type 0.
495 12:20:47.918236 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 12:20:47.921863 DRAM-K: Running full calibration
497 12:20:47.928130 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 12:20:47.928700 header.status = 0x0
499 12:20:47.931385 header.version = 0x6 (expected: 0x6)
500 12:20:47.934523 header.size = 0xd00 (expected: 0xd00)
501 12:20:47.938007 header.flags = 0x0
502 12:20:47.944779 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 12:20:47.961392 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
504 12:20:47.967970 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 12:20:47.971169 dram_init: ddr_geometry: 2
506 12:20:47.975223 [EMI] MDL number = 2
507 12:20:47.975839 [EMI] Get MDL freq = 0
508 12:20:47.977878 dram_init: ddr_type: 0
509 12:20:47.978414 is_discrete_lpddr4: 1
510 12:20:47.981313 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 12:20:47.981784
512 12:20:47.982158
513 12:20:47.984557 [Bian_co] ETT version 0.0.0.1
514 12:20:47.991602 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 12:20:47.992201
516 12:20:47.995088 dramc_set_vcore_voltage set vcore to 650000
517 12:20:47.995678 Read voltage for 800, 4
518 12:20:47.998405 Vio18 = 0
519 12:20:47.998977 Vcore = 650000
520 12:20:47.999357 Vdram = 0
521 12:20:48.001468 Vddq = 0
522 12:20:48.002064 Vmddr = 0
523 12:20:48.005234 dram_init: config_dvfs: 1
524 12:20:48.008469 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 12:20:48.014644 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 12:20:48.017746 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
527 12:20:48.021213 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
528 12:20:48.024697 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 12:20:48.027946 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 12:20:48.031500 MEM_TYPE=3, freq_sel=18
531 12:20:48.034638 sv_algorithm_assistance_LP4_1600
532 12:20:48.038227 ============ PULL DRAM RESETB DOWN ============
533 12:20:48.041147 ========== PULL DRAM RESETB DOWN end =========
534 12:20:48.047836 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 12:20:48.051362 ===================================
536 12:20:48.054798 LPDDR4 DRAM CONFIGURATION
537 12:20:48.058043 ===================================
538 12:20:48.058594 EX_ROW_EN[0] = 0x0
539 12:20:48.061316 EX_ROW_EN[1] = 0x0
540 12:20:48.061796 LP4Y_EN = 0x0
541 12:20:48.064953 WORK_FSP = 0x0
542 12:20:48.065436 WL = 0x2
543 12:20:48.067944 RL = 0x2
544 12:20:48.068427 BL = 0x2
545 12:20:48.071232 RPST = 0x0
546 12:20:48.071718 RD_PRE = 0x0
547 12:20:48.074572 WR_PRE = 0x1
548 12:20:48.075051 WR_PST = 0x0
549 12:20:48.077880 DBI_WR = 0x0
550 12:20:48.078363 DBI_RD = 0x0
551 12:20:48.081207 OTF = 0x1
552 12:20:48.084666 ===================================
553 12:20:48.088380 ===================================
554 12:20:48.089007 ANA top config
555 12:20:48.091754 ===================================
556 12:20:48.094895 DLL_ASYNC_EN = 0
557 12:20:48.098351 ALL_SLAVE_EN = 1
558 12:20:48.101360 NEW_RANK_MODE = 1
559 12:20:48.101860 DLL_IDLE_MODE = 1
560 12:20:48.104948 LP45_APHY_COMB_EN = 1
561 12:20:48.108206 TX_ODT_DIS = 1
562 12:20:48.111411 NEW_8X_MODE = 1
563 12:20:48.114946 ===================================
564 12:20:48.118375 ===================================
565 12:20:48.121465 data_rate = 1600
566 12:20:48.121950 CKR = 1
567 12:20:48.124615 DQ_P2S_RATIO = 8
568 12:20:48.127918 ===================================
569 12:20:48.131805 CA_P2S_RATIO = 8
570 12:20:48.135420 DQ_CA_OPEN = 0
571 12:20:48.138039 DQ_SEMI_OPEN = 0
572 12:20:48.138603 CA_SEMI_OPEN = 0
573 12:20:48.141368 CA_FULL_RATE = 0
574 12:20:48.145620 DQ_CKDIV4_EN = 1
575 12:20:48.149057 CA_CKDIV4_EN = 1
576 12:20:48.149572 CA_PREDIV_EN = 0
577 12:20:48.152921 PH8_DLY = 0
578 12:20:48.156379 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 12:20:48.159715 DQ_AAMCK_DIV = 4
580 12:20:48.163425 CA_AAMCK_DIV = 4
581 12:20:48.163991 CA_ADMCK_DIV = 4
582 12:20:48.166794 DQ_TRACK_CA_EN = 0
583 12:20:48.171000 CA_PICK = 800
584 12:20:48.174482 CA_MCKIO = 800
585 12:20:48.175122 MCKIO_SEMI = 0
586 12:20:48.177935 PLL_FREQ = 3068
587 12:20:48.181589 DQ_UI_PI_RATIO = 32
588 12:20:48.185373 CA_UI_PI_RATIO = 0
589 12:20:48.189297 ===================================
590 12:20:48.192596 ===================================
591 12:20:48.193210 memory_type:LPDDR4
592 12:20:48.196335 GP_NUM : 10
593 12:20:48.196808 SRAM_EN : 1
594 12:20:48.199622 MD32_EN : 0
595 12:20:48.203646 ===================================
596 12:20:48.204328 [ANA_INIT] >>>>>>>>>>>>>>
597 12:20:48.207132 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 12:20:48.210677 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 12:20:48.214436 ===================================
600 12:20:48.218039 data_rate = 1600,PCW = 0X7600
601 12:20:48.221426 ===================================
602 12:20:48.225522 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 12:20:48.228598 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 12:20:48.236154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 12:20:48.239808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 12:20:48.244105 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 12:20:48.247312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 12:20:48.247762 [ANA_INIT] flow start
609 12:20:48.250942 [ANA_INIT] PLL >>>>>>>>
610 12:20:48.254598 [ANA_INIT] PLL <<<<<<<<
611 12:20:48.255027 [ANA_INIT] MIDPI >>>>>>>>
612 12:20:48.258197 [ANA_INIT] MIDPI <<<<<<<<
613 12:20:48.262295 [ANA_INIT] DLL >>>>>>>>
614 12:20:48.262725 [ANA_INIT] flow end
615 12:20:48.266012 ============ LP4 DIFF to SE enter ============
616 12:20:48.269802 ============ LP4 DIFF to SE exit ============
617 12:20:48.273379 [ANA_INIT] <<<<<<<<<<<<<
618 12:20:48.277268 [Flow] Enable top DCM control >>>>>
619 12:20:48.280759 [Flow] Enable top DCM control <<<<<
620 12:20:48.284384 Enable DLL master slave shuffle
621 12:20:48.287702 ==============================================================
622 12:20:48.291919 Gating Mode config
623 12:20:48.295240 ==============================================================
624 12:20:48.298903 Config description:
625 12:20:48.306633 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 12:20:48.313834 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 12:20:48.317835 SELPH_MODE 0: By rank 1: By Phase
628 12:20:48.325060 ==============================================================
629 12:20:48.328640 GAT_TRACK_EN = 1
630 12:20:48.329108 RX_GATING_MODE = 2
631 12:20:48.332579 RX_GATING_TRACK_MODE = 2
632 12:20:48.336271 SELPH_MODE = 1
633 12:20:48.339772 PICG_EARLY_EN = 1
634 12:20:48.343410 VALID_LAT_VALUE = 1
635 12:20:48.347040 ==============================================================
636 12:20:48.350386 Enter into Gating configuration >>>>
637 12:20:48.354458 Exit from Gating configuration <<<<
638 12:20:48.358504 Enter into DVFS_PRE_config >>>>>
639 12:20:48.369217 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 12:20:48.372421 Exit from DVFS_PRE_config <<<<<
641 12:20:48.372852 Enter into PICG configuration >>>>
642 12:20:48.376316 Exit from PICG configuration <<<<
643 12:20:48.379820 [RX_INPUT] configuration >>>>>
644 12:20:48.383619 [RX_INPUT] configuration <<<<<
645 12:20:48.387406 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 12:20:48.394517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 12:20:48.398348 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 12:20:48.405819 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 12:20:48.412850 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 12:20:48.420299 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 12:20:48.424299 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 12:20:48.427858 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 12:20:48.431397 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 12:20:48.434927 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 12:20:48.438913 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 12:20:48.442778 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 12:20:48.446142 ===================================
658 12:20:48.450106 LPDDR4 DRAM CONFIGURATION
659 12:20:48.453778 ===================================
660 12:20:48.454251 EX_ROW_EN[0] = 0x0
661 12:20:48.457462 EX_ROW_EN[1] = 0x0
662 12:20:48.457889 LP4Y_EN = 0x0
663 12:20:48.460878 WORK_FSP = 0x0
664 12:20:48.461489 WL = 0x2
665 12:20:48.464735 RL = 0x2
666 12:20:48.465248 BL = 0x2
667 12:20:48.468723 RPST = 0x0
668 12:20:48.469238 RD_PRE = 0x0
669 12:20:48.469584 WR_PRE = 0x1
670 12:20:48.472452 WR_PST = 0x0
671 12:20:48.472920 DBI_WR = 0x0
672 12:20:48.476418 DBI_RD = 0x0
673 12:20:48.476844 OTF = 0x1
674 12:20:48.480426 ===================================
675 12:20:48.483664 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 12:20:48.487851 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 12:20:48.491134 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 12:20:48.495086 ===================================
679 12:20:48.498226 LPDDR4 DRAM CONFIGURATION
680 12:20:48.501281 ===================================
681 12:20:48.504646 EX_ROW_EN[0] = 0x10
682 12:20:48.505123 EX_ROW_EN[1] = 0x0
683 12:20:48.507867 LP4Y_EN = 0x0
684 12:20:48.508306 WORK_FSP = 0x0
685 12:20:48.511509 WL = 0x2
686 12:20:48.512040 RL = 0x2
687 12:20:48.514991 BL = 0x2
688 12:20:48.515426 RPST = 0x0
689 12:20:48.517971 RD_PRE = 0x0
690 12:20:48.518406 WR_PRE = 0x1
691 12:20:48.521474 WR_PST = 0x0
692 12:20:48.521910 DBI_WR = 0x0
693 12:20:48.525081 DBI_RD = 0x0
694 12:20:48.525604 OTF = 0x1
695 12:20:48.528179 ===================================
696 12:20:48.534822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 12:20:48.539981 nWR fixed to 40
698 12:20:48.542879 [ModeRegInit_LP4] CH0 RK0
699 12:20:48.543346 [ModeRegInit_LP4] CH0 RK1
700 12:20:48.545857 [ModeRegInit_LP4] CH1 RK0
701 12:20:48.549820 [ModeRegInit_LP4] CH1 RK1
702 12:20:48.550457 match AC timing 13
703 12:20:48.556299 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 12:20:48.559371 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 12:20:48.562948 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 12:20:48.569352 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 12:20:48.572629 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 12:20:48.576043 [EMI DOE] emi_dcm 0
709 12:20:48.579550 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 12:20:48.580124 ==
711 12:20:48.582810 Dram Type= 6, Freq= 0, CH_0, rank 0
712 12:20:48.585938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 12:20:48.586400 ==
714 12:20:48.592988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 12:20:48.599417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 12:20:48.607477 [CA 0] Center 38 (7~69) winsize 63
717 12:20:48.610617 [CA 1] Center 38 (7~69) winsize 63
718 12:20:48.613778 [CA 2] Center 35 (5~66) winsize 62
719 12:20:48.617526 [CA 3] Center 35 (5~66) winsize 62
720 12:20:48.620575 [CA 4] Center 34 (4~65) winsize 62
721 12:20:48.623901 [CA 5] Center 34 (4~64) winsize 61
722 12:20:48.624468
723 12:20:48.627247 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 12:20:48.627811
725 12:20:48.630785 [CATrainingPosCal] consider 1 rank data
726 12:20:48.634006 u2DelayCellTimex100 = 270/100 ps
727 12:20:48.637133 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
728 12:20:48.640463 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
729 12:20:48.647419 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
730 12:20:48.650428 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
731 12:20:48.653637 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
732 12:20:48.657245 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
733 12:20:48.657726
734 12:20:48.660404 CA PerBit enable=1, Macro0, CA PI delay=34
735 12:20:48.660915
736 12:20:48.664062 [CBTSetCACLKResult] CA Dly = 34
737 12:20:48.664663 CS Dly: 6 (0~37)
738 12:20:48.665097 ==
739 12:20:48.667428 Dram Type= 6, Freq= 0, CH_0, rank 1
740 12:20:48.673859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 12:20:48.674431 ==
742 12:20:48.677210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 12:20:48.684525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 12:20:48.693350 [CA 0] Center 38 (7~69) winsize 63
745 12:20:48.696839 [CA 1] Center 38 (8~69) winsize 62
746 12:20:48.700531 [CA 2] Center 36 (6~67) winsize 62
747 12:20:48.703212 [CA 3] Center 36 (5~67) winsize 63
748 12:20:48.707233 [CA 4] Center 35 (4~66) winsize 63
749 12:20:48.709955 [CA 5] Center 34 (4~65) winsize 62
750 12:20:48.710437
751 12:20:48.713437 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 12:20:48.713963
753 12:20:48.716832 [CATrainingPosCal] consider 2 rank data
754 12:20:48.720432 u2DelayCellTimex100 = 270/100 ps
755 12:20:48.723754 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
756 12:20:48.726988 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
757 12:20:48.733773 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
758 12:20:48.736776 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 12:20:48.740402 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 12:20:48.743671 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 12:20:48.744151
762 12:20:48.747362 CA PerBit enable=1, Macro0, CA PI delay=34
763 12:20:48.747965
764 12:20:48.750159 [CBTSetCACLKResult] CA Dly = 34
765 12:20:48.750578 CS Dly: 6 (0~38)
766 12:20:48.750987
767 12:20:48.753578 ----->DramcWriteLeveling(PI) begin...
768 12:20:48.757434 ==
769 12:20:48.758012 Dram Type= 6, Freq= 0, CH_0, rank 0
770 12:20:48.763543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 12:20:48.764155 ==
772 12:20:48.767001 Write leveling (Byte 0): 32 => 32
773 12:20:48.770609 Write leveling (Byte 1): 28 => 28
774 12:20:48.773595 DramcWriteLeveling(PI) end<-----
775 12:20:48.774077
776 12:20:48.774458 ==
777 12:20:48.777056 Dram Type= 6, Freq= 0, CH_0, rank 0
778 12:20:48.780439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 12:20:48.781156 ==
780 12:20:48.783518 [Gating] SW mode calibration
781 12:20:48.790351 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 12:20:48.794213 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 12:20:48.801040 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 12:20:48.804427 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
785 12:20:48.808230 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 12:20:48.811659 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 12:20:48.815115 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 12:20:48.821973 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:20:48.825907 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:20:48.829368 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:20:48.835778 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:20:48.839273 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:20:48.842764 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:20:48.845914 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:20:48.852557 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:20:48.856032 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:20:48.859412 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:20:48.866061 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:20:48.869317 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 12:20:48.872658 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
801 12:20:48.879420 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
802 12:20:48.882463 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:20:48.885924 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:20:48.892636 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:20:48.896267 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:20:48.899392 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:20:48.905952 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:20:48.909471 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:20:48.912582 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
810 12:20:48.919727 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
811 12:20:48.922964 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 12:20:48.925989 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 12:20:48.929366 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 12:20:48.936178 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:20:48.939537 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:20:48.943217 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
817 12:20:48.949585 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
818 12:20:48.953617 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
819 12:20:48.956591 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 12:20:48.962845 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 12:20:48.966303 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:20:48.970014 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:20:48.976394 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:20:48.979620 0 11 4 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
825 12:20:48.982828 0 11 8 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
826 12:20:48.989651 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
827 12:20:48.992652 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 12:20:48.995887 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 12:20:49.002825 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 12:20:49.006247 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:20:49.009392 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:20:49.016139 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 12:20:49.019602 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 12:20:49.022663 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 12:20:49.029828 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 12:20:49.033034 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 12:20:49.036262 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:20:49.039705 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:20:49.046096 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:20:49.049465 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:20:49.053106 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:20:49.059806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:20:49.063016 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:20:49.066386 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:20:49.073086 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:20:49.076311 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:20:49.079956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:20:49.086315 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 12:20:49.089707 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 12:20:49.093131 Total UI for P1: 0, mck2ui 16
851 12:20:49.096368 best dqsien dly found for B0: ( 0, 14, 4)
852 12:20:49.099715 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 12:20:49.103273 Total UI for P1: 0, mck2ui 16
854 12:20:49.106513 best dqsien dly found for B1: ( 0, 14, 6)
855 12:20:49.109608 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
856 12:20:49.113109 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
857 12:20:49.113682
858 12:20:49.116486 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
859 12:20:49.119816 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
860 12:20:49.123283 [Gating] SW calibration Done
861 12:20:49.123762 ==
862 12:20:49.126166 Dram Type= 6, Freq= 0, CH_0, rank 0
863 12:20:49.132870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 12:20:49.133439 ==
865 12:20:49.133877 RX Vref Scan: 0
866 12:20:49.134445
867 12:20:49.136764 RX Vref 0 -> 0, step: 1
868 12:20:49.137325
869 12:20:49.139838 RX Delay -130 -> 252, step: 16
870 12:20:49.143122 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
871 12:20:49.146442 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 12:20:49.149723 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
873 12:20:49.153044 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
874 12:20:49.160161 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
875 12:20:49.163205 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 12:20:49.166267 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 12:20:49.169449 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 12:20:49.172800 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 12:20:49.179827 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
880 12:20:49.183101 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
881 12:20:49.186249 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 12:20:49.189555 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
883 12:20:49.196250 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
884 12:20:49.199992 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 12:20:49.203176 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
886 12:20:49.203713 ==
887 12:20:49.206248 Dram Type= 6, Freq= 0, CH_0, rank 0
888 12:20:49.209624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 12:20:49.210106 ==
890 12:20:49.213040 DQS Delay:
891 12:20:49.213546 DQS0 = 0, DQS1 = 0
892 12:20:49.213926 DQM Delay:
893 12:20:49.216260 DQM0 = 93, DQM1 = 82
894 12:20:49.216735 DQ Delay:
895 12:20:49.219657 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
896 12:20:49.223057 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
897 12:20:49.226418 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
898 12:20:49.229647 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
899 12:20:49.230078
900 12:20:49.230416
901 12:20:49.230761 ==
902 12:20:49.233235 Dram Type= 6, Freq= 0, CH_0, rank 0
903 12:20:49.239759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 12:20:49.240238 ==
905 12:20:49.240612
906 12:20:49.241102
907 12:20:49.241457 TX Vref Scan disable
908 12:20:49.243600 == TX Byte 0 ==
909 12:20:49.247043 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
910 12:20:49.253230 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
911 12:20:49.253795 == TX Byte 1 ==
912 12:20:49.257309 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
913 12:20:49.263696 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
914 12:20:49.264263 ==
915 12:20:49.266610 Dram Type= 6, Freq= 0, CH_0, rank 0
916 12:20:49.269983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 12:20:49.270482 ==
918 12:20:49.283204 TX Vref=22, minBit 6, minWin=27, winSum=442
919 12:20:49.286726 TX Vref=24, minBit 8, minWin=27, winSum=443
920 12:20:49.289652 TX Vref=26, minBit 11, minWin=27, winSum=448
921 12:20:49.293057 TX Vref=28, minBit 11, minWin=27, winSum=454
922 12:20:49.296620 TX Vref=30, minBit 6, minWin=28, winSum=457
923 12:20:49.302951 TX Vref=32, minBit 11, minWin=27, winSum=456
924 12:20:49.306471 [TxChooseVref] Worse bit 6, Min win 28, Win sum 457, Final Vref 30
925 12:20:49.307048
926 12:20:49.309651 Final TX Range 1 Vref 30
927 12:20:49.310127
928 12:20:49.310502 ==
929 12:20:49.313245 Dram Type= 6, Freq= 0, CH_0, rank 0
930 12:20:49.316348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 12:20:49.316824 ==
932 12:20:49.319500
933 12:20:49.319977
934 12:20:49.320394 TX Vref Scan disable
935 12:20:49.323329 == TX Byte 0 ==
936 12:20:49.326735 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
937 12:20:49.330168 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
938 12:20:49.333180 == TX Byte 1 ==
939 12:20:49.336560 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
940 12:20:49.339568 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
941 12:20:49.343228
942 12:20:49.343702 [DATLAT]
943 12:20:49.344097 Freq=800, CH0 RK0
944 12:20:49.344498
945 12:20:49.346571 DATLAT Default: 0xa
946 12:20:49.347050 0, 0xFFFF, sum = 0
947 12:20:49.349821 1, 0xFFFF, sum = 0
948 12:20:49.350307 2, 0xFFFF, sum = 0
949 12:20:49.353047 3, 0xFFFF, sum = 0
950 12:20:49.353532 4, 0xFFFF, sum = 0
951 12:20:49.356571 5, 0xFFFF, sum = 0
952 12:20:49.357090 6, 0xFFFF, sum = 0
953 12:20:49.359935 7, 0xFFFF, sum = 0
954 12:20:49.363397 8, 0xFFFF, sum = 0
955 12:20:49.363886 9, 0x0, sum = 1
956 12:20:49.364291 10, 0x0, sum = 2
957 12:20:49.366324 11, 0x0, sum = 3
958 12:20:49.366809 12, 0x0, sum = 4
959 12:20:49.369951 best_step = 10
960 12:20:49.370427
961 12:20:49.370804 ==
962 12:20:49.373311 Dram Type= 6, Freq= 0, CH_0, rank 0
963 12:20:49.376505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 12:20:49.377019 ==
965 12:20:49.379849 RX Vref Scan: 1
966 12:20:49.380354
967 12:20:49.380729 Set Vref Range= 32 -> 127
968 12:20:49.381113
969 12:20:49.383206 RX Vref 32 -> 127, step: 1
970 12:20:49.383685
971 12:20:49.387145 RX Delay -79 -> 252, step: 8
972 12:20:49.387724
973 12:20:49.390144 Set Vref, RX VrefLevel [Byte0]: 32
974 12:20:49.393149 [Byte1]: 32
975 12:20:49.393761
976 12:20:49.396348 Set Vref, RX VrefLevel [Byte0]: 33
977 12:20:49.399758 [Byte1]: 33
978 12:20:49.403282
979 12:20:49.403755 Set Vref, RX VrefLevel [Byte0]: 34
980 12:20:49.406895 [Byte1]: 34
981 12:20:49.410888
982 12:20:49.411360 Set Vref, RX VrefLevel [Byte0]: 35
983 12:20:49.414022 [Byte1]: 35
984 12:20:49.418225
985 12:20:49.418699 Set Vref, RX VrefLevel [Byte0]: 36
986 12:20:49.421830 [Byte1]: 36
987 12:20:49.426373
988 12:20:49.426848 Set Vref, RX VrefLevel [Byte0]: 37
989 12:20:49.429000 [Byte1]: 37
990 12:20:49.434488
991 12:20:49.434971 Set Vref, RX VrefLevel [Byte0]: 38
992 12:20:49.437494 [Byte1]: 38
993 12:20:49.440907
994 12:20:49.441387 Set Vref, RX VrefLevel [Byte0]: 39
995 12:20:49.444167 [Byte1]: 39
996 12:20:49.448281
997 12:20:49.448748 Set Vref, RX VrefLevel [Byte0]: 40
998 12:20:49.451581 [Byte1]: 40
999 12:20:49.456001
1000 12:20:49.456430 Set Vref, RX VrefLevel [Byte0]: 41
1001 12:20:49.459348 [Byte1]: 41
1002 12:20:49.464376
1003 12:20:49.464805 Set Vref, RX VrefLevel [Byte0]: 42
1004 12:20:49.467424 [Byte1]: 42
1005 12:20:49.471265
1006 12:20:49.471350 Set Vref, RX VrefLevel [Byte0]: 43
1007 12:20:49.474369 [Byte1]: 43
1008 12:20:49.479234
1009 12:20:49.479319 Set Vref, RX VrefLevel [Byte0]: 44
1010 12:20:49.482595 [Byte1]: 44
1011 12:20:49.486458
1012 12:20:49.486543 Set Vref, RX VrefLevel [Byte0]: 45
1013 12:20:49.489752 [Byte1]: 45
1014 12:20:49.493876
1015 12:20:49.493960 Set Vref, RX VrefLevel [Byte0]: 46
1016 12:20:49.497201 [Byte1]: 46
1017 12:20:49.501437
1018 12:20:49.501522 Set Vref, RX VrefLevel [Byte0]: 47
1019 12:20:49.504386 [Byte1]: 47
1020 12:20:49.508405
1021 12:20:49.508489 Set Vref, RX VrefLevel [Byte0]: 48
1022 12:20:49.511939 [Byte1]: 48
1023 12:20:49.516065
1024 12:20:49.516149 Set Vref, RX VrefLevel [Byte0]: 49
1025 12:20:49.519372 [Byte1]: 49
1026 12:20:49.523560
1027 12:20:49.523643 Set Vref, RX VrefLevel [Byte0]: 50
1028 12:20:49.527180 [Byte1]: 50
1029 12:20:49.531094
1030 12:20:49.531213 Set Vref, RX VrefLevel [Byte0]: 51
1031 12:20:49.534334 [Byte1]: 51
1032 12:20:49.538539
1033 12:20:49.538639 Set Vref, RX VrefLevel [Byte0]: 52
1034 12:20:49.542003 [Byte1]: 52
1035 12:20:49.546261
1036 12:20:49.546346 Set Vref, RX VrefLevel [Byte0]: 53
1037 12:20:49.549567 [Byte1]: 53
1038 12:20:49.554256
1039 12:20:49.554347 Set Vref, RX VrefLevel [Byte0]: 54
1040 12:20:49.556996 [Byte1]: 54
1041 12:20:49.561457
1042 12:20:49.561543 Set Vref, RX VrefLevel [Byte0]: 55
1043 12:20:49.564656 [Byte1]: 55
1044 12:20:49.569132
1045 12:20:49.569219 Set Vref, RX VrefLevel [Byte0]: 56
1046 12:20:49.572183 [Byte1]: 56
1047 12:20:49.576771
1048 12:20:49.576851 Set Vref, RX VrefLevel [Byte0]: 57
1049 12:20:49.579709 [Byte1]: 57
1050 12:20:49.583854
1051 12:20:49.583938 Set Vref, RX VrefLevel [Byte0]: 58
1052 12:20:49.587271 [Byte1]: 58
1053 12:20:49.591259
1054 12:20:49.591351 Set Vref, RX VrefLevel [Byte0]: 59
1055 12:20:49.594847 [Byte1]: 59
1056 12:20:49.599191
1057 12:20:49.599273 Set Vref, RX VrefLevel [Byte0]: 60
1058 12:20:49.602498 [Byte1]: 60
1059 12:20:49.606711
1060 12:20:49.606801 Set Vref, RX VrefLevel [Byte0]: 61
1061 12:20:49.609727 [Byte1]: 61
1062 12:20:49.614184
1063 12:20:49.614268 Set Vref, RX VrefLevel [Byte0]: 62
1064 12:20:49.617768 [Byte1]: 62
1065 12:20:49.621718
1066 12:20:49.621795 Set Vref, RX VrefLevel [Byte0]: 63
1067 12:20:49.624945 [Byte1]: 63
1068 12:20:49.629689
1069 12:20:49.629765 Set Vref, RX VrefLevel [Byte0]: 64
1070 12:20:49.635733 [Byte1]: 64
1071 12:20:49.635813
1072 12:20:49.638943 Set Vref, RX VrefLevel [Byte0]: 65
1073 12:20:49.642480 [Byte1]: 65
1074 12:20:49.642564
1075 12:20:49.645790 Set Vref, RX VrefLevel [Byte0]: 66
1076 12:20:49.649121 [Byte1]: 66
1077 12:20:49.649204
1078 12:20:49.652456 Set Vref, RX VrefLevel [Byte0]: 67
1079 12:20:49.655487 [Byte1]: 67
1080 12:20:49.659678
1081 12:20:49.659761 Set Vref, RX VrefLevel [Byte0]: 68
1082 12:20:49.662833 [Byte1]: 68
1083 12:20:49.667427
1084 12:20:49.667536 Set Vref, RX VrefLevel [Byte0]: 69
1085 12:20:49.670585 [Byte1]: 69
1086 12:20:49.674572
1087 12:20:49.674655 Set Vref, RX VrefLevel [Byte0]: 70
1088 12:20:49.677686 [Byte1]: 70
1089 12:20:49.682155
1090 12:20:49.682238 Set Vref, RX VrefLevel [Byte0]: 71
1091 12:20:49.685545 [Byte1]: 71
1092 12:20:49.689682
1093 12:20:49.689771 Set Vref, RX VrefLevel [Byte0]: 72
1094 12:20:49.693137 [Byte1]: 72
1095 12:20:49.697476
1096 12:20:49.697564 Set Vref, RX VrefLevel [Byte0]: 73
1097 12:20:49.700660 [Byte1]: 73
1098 12:20:49.705323
1099 12:20:49.705399 Set Vref, RX VrefLevel [Byte0]: 74
1100 12:20:49.707990 [Byte1]: 74
1101 12:20:49.712583
1102 12:20:49.712652 Set Vref, RX VrefLevel [Byte0]: 75
1103 12:20:49.715756 [Byte1]: 75
1104 12:20:49.719887
1105 12:20:49.719986 Final RX Vref Byte 0 = 61 to rank0
1106 12:20:49.723047 Final RX Vref Byte 1 = 58 to rank0
1107 12:20:49.726561 Final RX Vref Byte 0 = 61 to rank1
1108 12:20:49.729694 Final RX Vref Byte 1 = 58 to rank1==
1109 12:20:49.733085 Dram Type= 6, Freq= 0, CH_0, rank 0
1110 12:20:49.739746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1111 12:20:49.739829 ==
1112 12:20:49.739895 DQS Delay:
1113 12:20:49.739956 DQS0 = 0, DQS1 = 0
1114 12:20:49.743127 DQM Delay:
1115 12:20:49.743210 DQM0 = 93, DQM1 = 82
1116 12:20:49.746567 DQ Delay:
1117 12:20:49.749871 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1118 12:20:49.749955 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1119 12:20:49.753326 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1120 12:20:49.756569 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1121 12:20:49.760239
1122 12:20:49.760321
1123 12:20:49.766571 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
1124 12:20:49.769897 CH0 RK0: MR19=606, MR18=3B36
1125 12:20:49.776741 CH0_RK0: MR19=0x606, MR18=0x3B36, DQSOSC=394, MR23=63, INC=95, DEC=63
1126 12:20:49.776825
1127 12:20:49.780157 ----->DramcWriteLeveling(PI) begin...
1128 12:20:49.780242 ==
1129 12:20:49.783297 Dram Type= 6, Freq= 0, CH_0, rank 1
1130 12:20:49.786605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1131 12:20:49.786689 ==
1132 12:20:49.790052 Write leveling (Byte 0): 30 => 30
1133 12:20:49.793461 Write leveling (Byte 1): 29 => 29
1134 12:20:49.796636 DramcWriteLeveling(PI) end<-----
1135 12:20:49.796719
1136 12:20:49.796785 ==
1137 12:20:49.800261 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 12:20:49.803447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 12:20:49.803531 ==
1140 12:20:49.806877 [Gating] SW mode calibration
1141 12:20:49.813578 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1142 12:20:49.820311 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1143 12:20:49.823937 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1144 12:20:49.827345 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1145 12:20:49.830376 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 12:20:49.836981 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 12:20:49.840562 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 12:20:49.844052 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 12:20:49.850720 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 12:20:49.853878 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 12:20:49.898219 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 12:20:49.898534 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 12:20:49.898791 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 12:20:49.898863 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:20:49.898954 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:20:49.899384 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:20:49.899785 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:20:49.900242 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:20:49.900326 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1160 12:20:49.900583 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1161 12:20:49.906095 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1162 12:20:49.909242 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:20:49.912736 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:20:49.916127 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:20:49.919781 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:20:49.922879 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:20:49.929792 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:20:49.932977 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:20:49.936503 0 9 8 | B1->B0 | 2a2a 3232 | 0 1 | (1 1) (1 1)
1170 12:20:49.942777 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 12:20:49.946280 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 12:20:49.949522 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 12:20:49.956293 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 12:20:49.959658 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 12:20:49.962707 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 12:20:49.969367 0 10 4 | B1->B0 | 3434 3131 | 0 0 | (0 1) (0 1)
1177 12:20:49.972835 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (1 0)
1178 12:20:49.976298 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:20:49.983211 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:20:49.986391 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:20:49.989372 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:20:49.996438 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:20:49.999757 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:20:50.003175 0 11 4 | B1->B0 | 2626 2f2f | 0 1 | (0 0) (0 0)
1185 12:20:50.006211 0 11 8 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
1186 12:20:50.013193 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 12:20:50.016145 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 12:20:50.019742 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 12:20:50.026506 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 12:20:50.030059 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 12:20:50.032778 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 12:20:50.039454 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1193 12:20:50.043143 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1194 12:20:50.046969 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 12:20:50.050594 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 12:20:50.057923 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 12:20:50.061909 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 12:20:50.065311 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 12:20:50.068631 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 12:20:50.072085 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 12:20:50.079252 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 12:20:50.082416 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:20:50.086170 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:20:50.092232 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:20:50.095716 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:20:50.099342 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:20:50.105887 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:20:50.109427 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1209 12:20:50.112398 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 12:20:50.115990 Total UI for P1: 0, mck2ui 16
1211 12:20:50.118918 best dqsien dly found for B0: ( 0, 14, 4)
1212 12:20:50.122565 Total UI for P1: 0, mck2ui 16
1213 12:20:50.126223 best dqsien dly found for B1: ( 0, 14, 6)
1214 12:20:50.129048 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1215 12:20:50.132559 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1216 12:20:50.132678
1217 12:20:50.135975 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1218 12:20:50.142513 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1219 12:20:50.142633 [Gating] SW calibration Done
1220 12:20:50.142727 ==
1221 12:20:50.145718 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 12:20:50.152453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1223 12:20:50.152561 ==
1224 12:20:50.152671 RX Vref Scan: 0
1225 12:20:50.152767
1226 12:20:50.155871 RX Vref 0 -> 0, step: 1
1227 12:20:50.155974
1228 12:20:50.159372 RX Delay -130 -> 252, step: 16
1229 12:20:50.162849 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1230 12:20:50.166265 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1231 12:20:50.169253 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1232 12:20:50.175803 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1233 12:20:50.179089 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1234 12:20:50.182532 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1235 12:20:50.185666 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1236 12:20:50.189497 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1237 12:20:50.192380 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1238 12:20:50.199026 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1239 12:20:50.202308 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1240 12:20:50.205674 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1241 12:20:50.209216 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1242 12:20:50.212514 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1243 12:20:50.219519 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1244 12:20:50.222363 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1245 12:20:50.222437 ==
1246 12:20:50.225929 Dram Type= 6, Freq= 0, CH_0, rank 1
1247 12:20:50.229003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1248 12:20:50.229108 ==
1249 12:20:50.232702 DQS Delay:
1250 12:20:50.232805 DQS0 = 0, DQS1 = 0
1251 12:20:50.232902 DQM Delay:
1252 12:20:50.236119 DQM0 = 91, DQM1 = 81
1253 12:20:50.236221 DQ Delay:
1254 12:20:50.239362 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1255 12:20:50.242531 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =101
1256 12:20:50.245619 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1257 12:20:50.249320 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1258 12:20:50.249432
1259 12:20:50.249533
1260 12:20:50.249628 ==
1261 12:20:50.252388 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 12:20:50.259684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 12:20:50.259795 ==
1264 12:20:50.259890
1265 12:20:50.259991
1266 12:20:50.260076 TX Vref Scan disable
1267 12:20:50.263265 == TX Byte 0 ==
1268 12:20:50.266424 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1269 12:20:50.272869 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1270 12:20:50.273020 == TX Byte 1 ==
1271 12:20:50.276314 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1272 12:20:50.279827 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1273 12:20:50.282933 ==
1274 12:20:50.286404 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 12:20:50.289687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 12:20:50.289804 ==
1277 12:20:50.301901 TX Vref=22, minBit 3, minWin=27, winSum=445
1278 12:20:50.305807 TX Vref=24, minBit 3, minWin=27, winSum=446
1279 12:20:50.308781 TX Vref=26, minBit 8, minWin=27, winSum=448
1280 12:20:50.312301 TX Vref=28, minBit 8, minWin=27, winSum=452
1281 12:20:50.315621 TX Vref=30, minBit 10, minWin=27, winSum=455
1282 12:20:50.318780 TX Vref=32, minBit 6, minWin=28, winSum=456
1283 12:20:50.325598 [TxChooseVref] Worse bit 6, Min win 28, Win sum 456, Final Vref 32
1284 12:20:50.325703
1285 12:20:50.328817 Final TX Range 1 Vref 32
1286 12:20:50.328936
1287 12:20:50.329036 ==
1288 12:20:50.332266 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 12:20:50.336082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 12:20:50.336188 ==
1291 12:20:50.336282
1292 12:20:50.336374
1293 12:20:50.338822 TX Vref Scan disable
1294 12:20:50.342228 == TX Byte 0 ==
1295 12:20:50.345681 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1296 12:20:50.349307 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1297 12:20:50.352531 == TX Byte 1 ==
1298 12:20:50.356130 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1299 12:20:50.359016 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1300 12:20:50.359088
1301 12:20:50.362384 [DATLAT]
1302 12:20:50.362479 Freq=800, CH0 RK1
1303 12:20:50.362570
1304 12:20:50.365736 DATLAT Default: 0xa
1305 12:20:50.365817 0, 0xFFFF, sum = 0
1306 12:20:50.368865 1, 0xFFFF, sum = 0
1307 12:20:50.368994 2, 0xFFFF, sum = 0
1308 12:20:50.372250 3, 0xFFFF, sum = 0
1309 12:20:50.372353 4, 0xFFFF, sum = 0
1310 12:20:50.375830 5, 0xFFFF, sum = 0
1311 12:20:50.375932 6, 0xFFFF, sum = 0
1312 12:20:50.379370 7, 0xFFFF, sum = 0
1313 12:20:50.379454 8, 0xFFFF, sum = 0
1314 12:20:50.382188 9, 0x0, sum = 1
1315 12:20:50.382262 10, 0x0, sum = 2
1316 12:20:50.386260 11, 0x0, sum = 3
1317 12:20:50.386338 12, 0x0, sum = 4
1318 12:20:50.389257 best_step = 10
1319 12:20:50.389333
1320 12:20:50.389393 ==
1321 12:20:50.393069 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 12:20:50.395658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 12:20:50.395757 ==
1324 12:20:50.399185 RX Vref Scan: 0
1325 12:20:50.399267
1326 12:20:50.399327 RX Vref 0 -> 0, step: 1
1327 12:20:50.399415
1328 12:20:50.402298 RX Delay -95 -> 252, step: 8
1329 12:20:50.408798 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1330 12:20:50.412230 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1331 12:20:50.415570 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1332 12:20:50.419130 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1333 12:20:50.422319 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1334 12:20:50.429025 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1335 12:20:50.432531 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1336 12:20:50.436074 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1337 12:20:50.438974 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1338 12:20:50.442437 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1339 12:20:50.446038 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1340 12:20:50.452381 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1341 12:20:50.455643 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1342 12:20:50.458957 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1343 12:20:50.462511 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1344 12:20:50.468759 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1345 12:20:50.468874 ==
1346 12:20:50.472318 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 12:20:50.476532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 12:20:50.476632 ==
1349 12:20:50.476720 DQS Delay:
1350 12:20:50.478983 DQS0 = 0, DQS1 = 0
1351 12:20:50.479056 DQM Delay:
1352 12:20:50.482603 DQM0 = 90, DQM1 = 81
1353 12:20:50.482675 DQ Delay:
1354 12:20:50.485786 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1355 12:20:50.489122 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1356 12:20:50.492464 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =80
1357 12:20:50.495956 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1358 12:20:50.496053
1359 12:20:50.496142
1360 12:20:50.502577 [DQSOSCAuto] RK1, (LSB)MR18= 0x401b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1361 12:20:50.506040 CH0 RK1: MR19=606, MR18=401B
1362 12:20:50.512409 CH0_RK1: MR19=0x606, MR18=0x401B, DQSOSC=393, MR23=63, INC=95, DEC=63
1363 12:20:50.515772 [RxdqsGatingPostProcess] freq 800
1364 12:20:50.522326 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1365 12:20:50.522429 Pre-setting of DQS Precalculation
1366 12:20:50.529428 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1367 12:20:50.529504 ==
1368 12:20:50.532324 Dram Type= 6, Freq= 0, CH_1, rank 0
1369 12:20:50.536189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 12:20:50.536285 ==
1371 12:20:50.542538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1372 12:20:50.549446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1373 12:20:50.557069 [CA 0] Center 36 (6~67) winsize 62
1374 12:20:50.560880 [CA 1] Center 36 (6~67) winsize 62
1375 12:20:50.563916 [CA 2] Center 35 (5~65) winsize 61
1376 12:20:50.567509 [CA 3] Center 34 (3~65) winsize 63
1377 12:20:50.570818 [CA 4] Center 34 (4~65) winsize 62
1378 12:20:50.573895 [CA 5] Center 34 (3~65) winsize 63
1379 12:20:50.573992
1380 12:20:50.577318 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1381 12:20:50.577418
1382 12:20:50.580491 [CATrainingPosCal] consider 1 rank data
1383 12:20:50.583858 u2DelayCellTimex100 = 270/100 ps
1384 12:20:50.587237 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1385 12:20:50.590478 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1386 12:20:50.593830 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1387 12:20:50.600837 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1388 12:20:50.604130 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1389 12:20:50.607268 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1390 12:20:50.607346
1391 12:20:50.610844 CA PerBit enable=1, Macro0, CA PI delay=34
1392 12:20:50.610941
1393 12:20:50.613888 [CBTSetCACLKResult] CA Dly = 34
1394 12:20:50.613986 CS Dly: 5 (0~36)
1395 12:20:50.614077 ==
1396 12:20:50.617273 Dram Type= 6, Freq= 0, CH_1, rank 1
1397 12:20:50.623815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 12:20:50.623912 ==
1399 12:20:50.627505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1400 12:20:50.633858 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1401 12:20:50.643701 [CA 0] Center 37 (7~67) winsize 61
1402 12:20:50.647034 [CA 1] Center 37 (6~68) winsize 63
1403 12:20:50.649718 [CA 2] Center 35 (4~66) winsize 63
1404 12:20:50.653725 [CA 3] Center 34 (4~65) winsize 62
1405 12:20:50.656520 [CA 4] Center 34 (4~65) winsize 62
1406 12:20:50.660177 [CA 5] Center 33 (3~64) winsize 62
1407 12:20:50.660273
1408 12:20:50.663274 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1409 12:20:50.663372
1410 12:20:50.666930 [CATrainingPosCal] consider 2 rank data
1411 12:20:50.670022 u2DelayCellTimex100 = 270/100 ps
1412 12:20:50.673269 CA0 delay=37 (7~67),Diff = 4 PI (28 cell)
1413 12:20:50.676712 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 12:20:50.683388 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1415 12:20:50.687108 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1416 12:20:50.689936 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 12:20:50.693361 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1418 12:20:50.693456
1419 12:20:50.696704 CA PerBit enable=1, Macro0, CA PI delay=33
1420 12:20:50.696797
1421 12:20:50.699966 [CBTSetCACLKResult] CA Dly = 33
1422 12:20:50.700060 CS Dly: 6 (0~38)
1423 12:20:50.700148
1424 12:20:50.703231 ----->DramcWriteLeveling(PI) begin...
1425 12:20:50.707037 ==
1426 12:20:50.707129 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 12:20:50.713999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 12:20:50.714098 ==
1429 12:20:50.717683 Write leveling (Byte 0): 26 => 26
1430 12:20:50.717778 Write leveling (Byte 1): 29 => 29
1431 12:20:50.721201 DramcWriteLeveling(PI) end<-----
1432 12:20:50.721293
1433 12:20:50.721379 ==
1434 12:20:50.725137 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 12:20:50.729107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 12:20:50.729184 ==
1437 12:20:50.732916 [Gating] SW mode calibration
1438 12:20:50.740573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1439 12:20:50.743890 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1440 12:20:50.748059 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1441 12:20:50.754653 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1442 12:20:50.758332 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 12:20:50.761710 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 12:20:50.768433 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 12:20:50.771451 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 12:20:50.774780 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 12:20:50.781672 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 12:20:50.784863 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 12:20:50.788346 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 12:20:50.791479 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 12:20:50.798490 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 12:20:50.801664 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:20:50.805024 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:20:50.811711 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:20:50.814984 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:20:50.818373 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1457 12:20:50.825099 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1458 12:20:50.828630 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:20:50.831448 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:20:50.838129 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:20:50.841382 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:20:50.845063 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:20:50.851707 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:20:50.855040 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:20:50.858276 0 9 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1466 12:20:50.865275 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 12:20:50.868336 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 12:20:50.871973 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 12:20:50.874759 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 12:20:50.881555 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 12:20:50.884720 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 12:20:50.888131 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1473 12:20:50.895490 0 10 4 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (1 0)
1474 12:20:50.898105 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:20:50.901954 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:20:50.908049 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:20:50.911397 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:20:50.915020 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:20:50.921672 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:20:50.924668 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1481 12:20:50.928071 0 11 4 | B1->B0 | 2e2e 3c3c | 0 1 | (0 0) (0 0)
1482 12:20:50.934986 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1483 12:20:50.938232 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 12:20:50.941462 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 12:20:50.948055 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 12:20:50.951652 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 12:20:50.954825 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 12:20:50.961733 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 12:20:50.964818 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1490 12:20:50.968297 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 12:20:50.971462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 12:20:50.978279 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 12:20:50.981407 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 12:20:50.984867 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 12:20:50.992018 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 12:20:50.995460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 12:20:50.998419 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 12:20:51.005206 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 12:20:51.008414 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 12:20:51.011920 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:20:51.018297 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:20:51.022000 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:20:51.025130 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:20:51.031474 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:20:51.034881 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1506 12:20:51.038352 Total UI for P1: 0, mck2ui 16
1507 12:20:51.041584 best dqsien dly found for B0: ( 0, 14, 2)
1508 12:20:51.044843 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 12:20:51.048192 Total UI for P1: 0, mck2ui 16
1510 12:20:51.051755 best dqsien dly found for B1: ( 0, 14, 4)
1511 12:20:51.054977 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1512 12:20:51.058357 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1513 12:20:51.058441
1514 12:20:51.061453 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1515 12:20:51.068250 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1516 12:20:51.068333 [Gating] SW calibration Done
1517 12:20:51.068400 ==
1518 12:20:51.071513 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 12:20:51.078365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 12:20:51.078449 ==
1521 12:20:51.078516 RX Vref Scan: 0
1522 12:20:51.078577
1523 12:20:51.081540 RX Vref 0 -> 0, step: 1
1524 12:20:51.081623
1525 12:20:51.084826 RX Delay -130 -> 252, step: 16
1526 12:20:51.088331 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1527 12:20:51.092035 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1528 12:20:51.095033 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1529 12:20:51.098511 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1530 12:20:51.105327 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1531 12:20:51.108509 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1532 12:20:51.112130 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1533 12:20:51.115045 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1534 12:20:51.118493 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1535 12:20:51.125396 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1536 12:20:51.128328 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1537 12:20:51.131681 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1538 12:20:51.134933 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1539 12:20:51.141688 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1540 12:20:51.145053 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1541 12:20:51.148321 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1542 12:20:51.148424 ==
1543 12:20:51.151776 Dram Type= 6, Freq= 0, CH_1, rank 0
1544 12:20:51.155044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1545 12:20:51.155163 ==
1546 12:20:51.158464 DQS Delay:
1547 12:20:51.158584 DQS0 = 0, DQS1 = 0
1548 12:20:51.158692 DQM Delay:
1549 12:20:51.161998 DQM0 = 91, DQM1 = 80
1550 12:20:51.162100 DQ Delay:
1551 12:20:51.165379 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1552 12:20:51.168439 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1553 12:20:51.172021 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1554 12:20:51.175608 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1555 12:20:51.175740
1556 12:20:51.175852
1557 12:20:51.175951 ==
1558 12:20:51.178667 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 12:20:51.185097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 12:20:51.185178 ==
1561 12:20:51.185286
1562 12:20:51.185378
1563 12:20:51.185477 TX Vref Scan disable
1564 12:20:51.188669 == TX Byte 0 ==
1565 12:20:51.192117 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1566 12:20:51.199007 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1567 12:20:51.199092 == TX Byte 1 ==
1568 12:20:51.202286 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1569 12:20:51.208778 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1570 12:20:51.208886 ==
1571 12:20:51.212326 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 12:20:51.215775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 12:20:51.215858 ==
1574 12:20:51.227939 TX Vref=22, minBit 10, minWin=27, winSum=448
1575 12:20:51.231527 TX Vref=24, minBit 13, minWin=27, winSum=453
1576 12:20:51.234856 TX Vref=26, minBit 15, minWin=27, winSum=455
1577 12:20:51.238140 TX Vref=28, minBit 15, minWin=27, winSum=458
1578 12:20:51.241454 TX Vref=30, minBit 15, minWin=27, winSum=458
1579 12:20:51.247903 TX Vref=32, minBit 9, minWin=27, winSum=456
1580 12:20:51.251482 [TxChooseVref] Worse bit 15, Min win 27, Win sum 458, Final Vref 28
1581 12:20:51.251706
1582 12:20:51.254999 Final TX Range 1 Vref 28
1583 12:20:51.255184
1584 12:20:51.255376 ==
1585 12:20:51.258213 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 12:20:51.264434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 12:20:51.264690 ==
1588 12:20:51.264882
1589 12:20:51.265092
1590 12:20:51.265265 TX Vref Scan disable
1591 12:20:51.268490 == TX Byte 0 ==
1592 12:20:51.271912 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1593 12:20:51.275279 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1594 12:20:51.278611 == TX Byte 1 ==
1595 12:20:51.282021 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1596 12:20:51.285252 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1597 12:20:51.288821
1598 12:20:51.289391 [DATLAT]
1599 12:20:51.289843 Freq=800, CH1 RK0
1600 12:20:51.290335
1601 12:20:51.292070 DATLAT Default: 0xa
1602 12:20:51.292631 0, 0xFFFF, sum = 0
1603 12:20:51.295735 1, 0xFFFF, sum = 0
1604 12:20:51.296296 2, 0xFFFF, sum = 0
1605 12:20:51.300037 3, 0xFFFF, sum = 0
1606 12:20:51.300704 4, 0xFFFF, sum = 0
1607 12:20:51.302754 5, 0xFFFF, sum = 0
1608 12:20:51.303377 6, 0xFFFF, sum = 0
1609 12:20:51.306290 7, 0xFFFF, sum = 0
1610 12:20:51.306908 8, 0xFFFF, sum = 0
1611 12:20:51.309419 9, 0x0, sum = 1
1612 12:20:51.309964 10, 0x0, sum = 2
1613 12:20:51.312916 11, 0x0, sum = 3
1614 12:20:51.313433 12, 0x0, sum = 4
1615 12:20:51.316371 best_step = 10
1616 12:20:51.317043
1617 12:20:51.317490 ==
1618 12:20:51.319596 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 12:20:51.323175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 12:20:51.323778 ==
1621 12:20:51.324300 RX Vref Scan: 1
1622 12:20:51.324840
1623 12:20:51.326546 Set Vref Range= 32 -> 127
1624 12:20:51.327204
1625 12:20:51.329391 RX Vref 32 -> 127, step: 1
1626 12:20:51.329910
1627 12:20:51.332863 RX Delay -95 -> 252, step: 8
1628 12:20:51.333383
1629 12:20:51.336391 Set Vref, RX VrefLevel [Byte0]: 32
1630 12:20:51.339627 [Byte1]: 32
1631 12:20:51.340175
1632 12:20:51.342965 Set Vref, RX VrefLevel [Byte0]: 33
1633 12:20:51.346291 [Byte1]: 33
1634 12:20:51.346858
1635 12:20:51.349515 Set Vref, RX VrefLevel [Byte0]: 34
1636 12:20:51.353234 [Byte1]: 34
1637 12:20:51.356646
1638 12:20:51.357286 Set Vref, RX VrefLevel [Byte0]: 35
1639 12:20:51.359740 [Byte1]: 35
1640 12:20:51.364257
1641 12:20:51.364869 Set Vref, RX VrefLevel [Byte0]: 36
1642 12:20:51.367816 [Byte1]: 36
1643 12:20:51.372250
1644 12:20:51.372788 Set Vref, RX VrefLevel [Byte0]: 37
1645 12:20:51.375093 [Byte1]: 37
1646 12:20:51.379543
1647 12:20:51.380116 Set Vref, RX VrefLevel [Byte0]: 38
1648 12:20:51.382707 [Byte1]: 38
1649 12:20:51.387122
1650 12:20:51.387670 Set Vref, RX VrefLevel [Byte0]: 39
1651 12:20:51.390661 [Byte1]: 39
1652 12:20:51.395215
1653 12:20:51.395802 Set Vref, RX VrefLevel [Byte0]: 40
1654 12:20:51.397982 [Byte1]: 40
1655 12:20:51.402207
1656 12:20:51.402623 Set Vref, RX VrefLevel [Byte0]: 41
1657 12:20:51.405668 [Byte1]: 41
1658 12:20:51.410012
1659 12:20:51.410532 Set Vref, RX VrefLevel [Byte0]: 42
1660 12:20:51.413291 [Byte1]: 42
1661 12:20:51.417576
1662 12:20:51.418039 Set Vref, RX VrefLevel [Byte0]: 43
1663 12:20:51.420788 [Byte1]: 43
1664 12:20:51.425115
1665 12:20:51.425670 Set Vref, RX VrefLevel [Byte0]: 44
1666 12:20:51.428340 [Byte1]: 44
1667 12:20:51.432770
1668 12:20:51.433232 Set Vref, RX VrefLevel [Byte0]: 45
1669 12:20:51.436145 [Byte1]: 45
1670 12:20:51.440343
1671 12:20:51.440800 Set Vref, RX VrefLevel [Byte0]: 46
1672 12:20:51.444168 [Byte1]: 46
1673 12:20:51.448019
1674 12:20:51.448720 Set Vref, RX VrefLevel [Byte0]: 47
1675 12:20:51.451021 [Byte1]: 47
1676 12:20:51.455348
1677 12:20:51.455850 Set Vref, RX VrefLevel [Byte0]: 48
1678 12:20:51.459029 [Byte1]: 48
1679 12:20:51.462996
1680 12:20:51.463694 Set Vref, RX VrefLevel [Byte0]: 49
1681 12:20:51.466187 [Byte1]: 49
1682 12:20:51.471020
1683 12:20:51.471644 Set Vref, RX VrefLevel [Byte0]: 50
1684 12:20:51.474243 [Byte1]: 50
1685 12:20:51.478501
1686 12:20:51.478980 Set Vref, RX VrefLevel [Byte0]: 51
1687 12:20:51.481791 [Byte1]: 51
1688 12:20:51.485855
1689 12:20:51.486314 Set Vref, RX VrefLevel [Byte0]: 52
1690 12:20:51.489102 [Byte1]: 52
1691 12:20:51.493350
1692 12:20:51.496463 Set Vref, RX VrefLevel [Byte0]: 53
1693 12:20:51.499910 [Byte1]: 53
1694 12:20:51.500382
1695 12:20:51.503138 Set Vref, RX VrefLevel [Byte0]: 54
1696 12:20:51.506485 [Byte1]: 54
1697 12:20:51.507101
1698 12:20:51.509884 Set Vref, RX VrefLevel [Byte0]: 55
1699 12:20:51.513177 [Byte1]: 55
1700 12:20:51.513640
1701 12:20:51.516915 Set Vref, RX VrefLevel [Byte0]: 56
1702 12:20:51.520486 [Byte1]: 56
1703 12:20:51.524012
1704 12:20:51.524476 Set Vref, RX VrefLevel [Byte0]: 57
1705 12:20:51.527554 [Byte1]: 57
1706 12:20:51.532125
1707 12:20:51.532689 Set Vref, RX VrefLevel [Byte0]: 58
1708 12:20:51.534724 [Byte1]: 58
1709 12:20:51.538905
1710 12:20:51.539369 Set Vref, RX VrefLevel [Byte0]: 59
1711 12:20:51.542970 [Byte1]: 59
1712 12:20:51.546777
1713 12:20:51.547243 Set Vref, RX VrefLevel [Byte0]: 60
1714 12:20:51.550163 [Byte1]: 60
1715 12:20:51.554582
1716 12:20:51.555046 Set Vref, RX VrefLevel [Byte0]: 61
1717 12:20:51.557594 [Byte1]: 61
1718 12:20:51.561951
1719 12:20:51.562450 Set Vref, RX VrefLevel [Byte0]: 62
1720 12:20:51.565098 [Byte1]: 62
1721 12:20:51.569426
1722 12:20:51.569888 Set Vref, RX VrefLevel [Byte0]: 63
1723 12:20:51.572563 [Byte1]: 63
1724 12:20:51.577116
1725 12:20:51.577578 Set Vref, RX VrefLevel [Byte0]: 64
1726 12:20:51.580253 [Byte1]: 64
1727 12:20:51.584499
1728 12:20:51.584995 Set Vref, RX VrefLevel [Byte0]: 65
1729 12:20:51.587902 [Byte1]: 65
1730 12:20:51.592358
1731 12:20:51.592821 Set Vref, RX VrefLevel [Byte0]: 66
1732 12:20:51.595761 [Byte1]: 66
1733 12:20:51.600144
1734 12:20:51.600611 Set Vref, RX VrefLevel [Byte0]: 67
1735 12:20:51.602964 [Byte1]: 67
1736 12:20:51.607455
1737 12:20:51.607935 Set Vref, RX VrefLevel [Byte0]: 68
1738 12:20:51.610593 [Byte1]: 68
1739 12:20:51.615553
1740 12:20:51.616140 Set Vref, RX VrefLevel [Byte0]: 69
1741 12:20:51.618581 [Byte1]: 69
1742 12:20:51.622930
1743 12:20:51.623410 Set Vref, RX VrefLevel [Byte0]: 70
1744 12:20:51.629088 [Byte1]: 70
1745 12:20:51.629554
1746 12:20:51.632457 Set Vref, RX VrefLevel [Byte0]: 71
1747 12:20:51.636036 [Byte1]: 71
1748 12:20:51.636605
1749 12:20:51.639183 Set Vref, RX VrefLevel [Byte0]: 72
1750 12:20:51.642809 [Byte1]: 72
1751 12:20:51.643384
1752 12:20:51.645931 Set Vref, RX VrefLevel [Byte0]: 73
1753 12:20:51.649072 [Byte1]: 73
1754 12:20:51.653371
1755 12:20:51.653943 Set Vref, RX VrefLevel [Byte0]: 74
1756 12:20:51.656241 [Byte1]: 74
1757 12:20:51.661105
1758 12:20:51.661688 Set Vref, RX VrefLevel [Byte0]: 75
1759 12:20:51.664278 [Byte1]: 75
1760 12:20:51.668014
1761 12:20:51.668479 Set Vref, RX VrefLevel [Byte0]: 76
1762 12:20:51.671416 [Byte1]: 76
1763 12:20:51.675975
1764 12:20:51.676437 Set Vref, RX VrefLevel [Byte0]: 77
1765 12:20:51.679256 [Byte1]: 77
1766 12:20:51.683401
1767 12:20:51.683860 Final RX Vref Byte 0 = 53 to rank0
1768 12:20:51.686850 Final RX Vref Byte 1 = 63 to rank0
1769 12:20:51.690048 Final RX Vref Byte 0 = 53 to rank1
1770 12:20:51.693533 Final RX Vref Byte 1 = 63 to rank1==
1771 12:20:51.696792 Dram Type= 6, Freq= 0, CH_1, rank 0
1772 12:20:51.703302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 12:20:51.703790 ==
1774 12:20:51.704155 DQS Delay:
1775 12:20:51.704492 DQS0 = 0, DQS1 = 0
1776 12:20:51.706856 DQM Delay:
1777 12:20:51.707318 DQM0 = 92, DQM1 = 83
1778 12:20:51.709950 DQ Delay:
1779 12:20:51.713458 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1780 12:20:51.716855 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1781 12:20:51.720025 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1782 12:20:51.723365 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1783 12:20:51.723826
1784 12:20:51.724187
1785 12:20:51.730260 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 398 ps
1786 12:20:51.733865 CH1 RK0: MR19=606, MR18=2E4C
1787 12:20:51.740006 CH1_RK0: MR19=0x606, MR18=0x2E4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1788 12:20:51.740562
1789 12:20:51.743808 ----->DramcWriteLeveling(PI) begin...
1790 12:20:51.744375 ==
1791 12:20:51.747060 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 12:20:51.750261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 12:20:51.750754 ==
1794 12:20:51.753408 Write leveling (Byte 0): 27 => 27
1795 12:20:51.756773 Write leveling (Byte 1): 28 => 28
1796 12:20:51.760035 DramcWriteLeveling(PI) end<-----
1797 12:20:51.760553
1798 12:20:51.760921 ==
1799 12:20:51.763474 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 12:20:51.766712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 12:20:51.767176 ==
1802 12:20:51.770715 [Gating] SW mode calibration
1803 12:20:51.776976 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1804 12:20:51.783438 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1805 12:20:51.787008 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1806 12:20:51.790978 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1807 12:20:51.797215 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:20:51.800487 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:20:51.803957 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:20:51.810567 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:20:51.813697 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:20:51.816980 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:20:51.823543 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 12:20:51.826928 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 12:20:51.830409 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:20:51.833652 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:20:51.840336 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:20:51.843677 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:20:51.847005 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:20:51.853912 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:20:51.856681 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:20:51.860561 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1823 12:20:51.866679 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1824 12:20:51.870400 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:20:51.873317 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:20:51.880057 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:20:51.883491 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:20:51.887177 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:20:51.893439 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:20:51.896877 0 9 4 | B1->B0 | 2727 2424 | 1 1 | (0 0) (0 0)
1831 12:20:51.900110 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (0 0) (0 0)
1832 12:20:51.906801 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 12:20:51.910555 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 12:20:51.913584 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 12:20:51.920631 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 12:20:51.923578 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 12:20:51.926827 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1838 12:20:51.933829 0 10 4 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
1839 12:20:51.936628 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1840 12:20:51.940131 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:20:51.946916 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:20:51.950506 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:20:51.953888 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 12:20:51.956779 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:20:51.963563 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:20:51.966709 0 11 4 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (1 1)
1847 12:20:51.970583 0 11 8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
1848 12:20:51.976855 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 12:20:51.980420 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 12:20:51.983525 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 12:20:51.990456 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 12:20:51.993488 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 12:20:51.996992 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1854 12:20:52.003454 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 12:20:52.006933 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:20:52.010159 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:20:52.017185 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:20:52.020157 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:20:52.023709 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:20:52.029913 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:20:52.033743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:20:52.036656 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 12:20:52.040163 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 12:20:52.046828 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 12:20:52.050570 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 12:20:52.053602 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 12:20:52.060892 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:20:52.064089 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:20:52.066875 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:20:52.073784 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1871 12:20:52.076987 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1872 12:20:52.080989 Total UI for P1: 0, mck2ui 16
1873 12:20:52.083844 best dqsien dly found for B1: ( 0, 14, 4)
1874 12:20:52.087171 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 12:20:52.090718 Total UI for P1: 0, mck2ui 16
1876 12:20:52.093653 best dqsien dly found for B0: ( 0, 14, 6)
1877 12:20:52.096801 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1878 12:20:52.100491 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1879 12:20:52.101035
1880 12:20:52.104293 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1881 12:20:52.110542 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 12:20:52.111112 [Gating] SW calibration Done
1883 12:20:52.111503 ==
1884 12:20:52.113734 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 12:20:52.120403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 12:20:52.120870 ==
1887 12:20:52.121287 RX Vref Scan: 0
1888 12:20:52.121639
1889 12:20:52.123910 RX Vref 0 -> 0, step: 1
1890 12:20:52.124426
1891 12:20:52.126852 RX Delay -130 -> 252, step: 16
1892 12:20:52.130550 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1893 12:20:52.133707 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1894 12:20:52.136973 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1895 12:20:52.144023 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1896 12:20:52.147106 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1897 12:20:52.150244 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1898 12:20:52.153839 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1899 12:20:52.157082 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1900 12:20:52.160349 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1901 12:20:52.167272 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1902 12:20:52.170707 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1903 12:20:52.173812 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1904 12:20:52.177039 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1905 12:20:52.180710 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1906 12:20:52.187530 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1907 12:20:52.190352 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1908 12:20:52.190823 ==
1909 12:20:52.193816 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 12:20:52.197225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 12:20:52.197693 ==
1912 12:20:52.201039 DQS Delay:
1913 12:20:52.201602 DQS0 = 0, DQS1 = 0
1914 12:20:52.201971 DQM Delay:
1915 12:20:52.204174 DQM0 = 86, DQM1 = 80
1916 12:20:52.204631 DQ Delay:
1917 12:20:52.207343 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1918 12:20:52.210779 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =77
1919 12:20:52.213781 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1920 12:20:52.217568 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1921 12:20:52.218132
1922 12:20:52.218496
1923 12:20:52.218830 ==
1924 12:20:52.220771 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 12:20:52.227222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 12:20:52.227794 ==
1927 12:20:52.228167
1928 12:20:52.228507
1929 12:20:52.228825 TX Vref Scan disable
1930 12:20:52.230957 == TX Byte 0 ==
1931 12:20:52.233986 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1932 12:20:52.237534 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1933 12:20:52.240726 == TX Byte 1 ==
1934 12:20:52.244252 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1935 12:20:52.247755 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1936 12:20:52.250654 ==
1937 12:20:52.254234 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 12:20:52.257429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 12:20:52.257938 ==
1940 12:20:52.269955 TX Vref=22, minBit 13, minWin=27, winSum=453
1941 12:20:52.273034 TX Vref=24, minBit 3, minWin=28, winSum=459
1942 12:20:52.276293 TX Vref=26, minBit 9, minWin=28, winSum=459
1943 12:20:52.279876 TX Vref=28, minBit 8, minWin=28, winSum=458
1944 12:20:52.283050 TX Vref=30, minBit 8, minWin=28, winSum=459
1945 12:20:52.289761 TX Vref=32, minBit 8, minWin=28, winSum=459
1946 12:20:52.293250 [TxChooseVref] Worse bit 3, Min win 28, Win sum 459, Final Vref 24
1947 12:20:52.293747
1948 12:20:52.296386 Final TX Range 1 Vref 24
1949 12:20:52.297010
1950 12:20:52.297393 ==
1951 12:20:52.299918 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 12:20:52.303233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 12:20:52.303809 ==
1954 12:20:52.304186
1955 12:20:52.306319
1956 12:20:52.306785 TX Vref Scan disable
1957 12:20:52.309790 == TX Byte 0 ==
1958 12:20:52.313394 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1959 12:20:52.316332 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1960 12:20:52.320331 == TX Byte 1 ==
1961 12:20:52.323082 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1962 12:20:52.326686 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1963 12:20:52.329648
1964 12:20:52.330117 [DATLAT]
1965 12:20:52.330491 Freq=800, CH1 RK1
1966 12:20:52.330836
1967 12:20:52.333090 DATLAT Default: 0xa
1968 12:20:52.333560 0, 0xFFFF, sum = 0
1969 12:20:52.336782 1, 0xFFFF, sum = 0
1970 12:20:52.337406 2, 0xFFFF, sum = 0
1971 12:20:52.339791 3, 0xFFFF, sum = 0
1972 12:20:52.340269 4, 0xFFFF, sum = 0
1973 12:20:52.342928 5, 0xFFFF, sum = 0
1974 12:20:52.347676 6, 0xFFFF, sum = 0
1975 12:20:52.348255 7, 0xFFFF, sum = 0
1976 12:20:52.349361 8, 0xFFFF, sum = 0
1977 12:20:52.349839 9, 0x0, sum = 1
1978 12:20:52.350217 10, 0x0, sum = 2
1979 12:20:52.352677 11, 0x0, sum = 3
1980 12:20:52.353225 12, 0x0, sum = 4
1981 12:20:52.356327 best_step = 10
1982 12:20:52.356872
1983 12:20:52.357301 ==
1984 12:20:52.359143 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 12:20:52.362591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 12:20:52.363194 ==
1987 12:20:52.366185 RX Vref Scan: 0
1988 12:20:52.366656
1989 12:20:52.367023 RX Vref 0 -> 0, step: 1
1990 12:20:52.367361
1991 12:20:52.369038 RX Delay -95 -> 252, step: 8
1992 12:20:52.376073 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1993 12:20:52.379670 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
1994 12:20:52.383107 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1995 12:20:52.386294 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1996 12:20:52.389949 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1997 12:20:52.396440 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
1998 12:20:52.399975 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1999 12:20:52.402932 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2000 12:20:52.406585 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2001 12:20:52.410084 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2002 12:20:52.413323 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2003 12:20:52.420470 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2004 12:20:52.423117 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2005 12:20:52.426692 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2006 12:20:52.430299 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2007 12:20:52.436564 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2008 12:20:52.437175 ==
2009 12:20:52.439928 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 12:20:52.443188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 12:20:52.443665 ==
2012 12:20:52.444039 DQS Delay:
2013 12:20:52.446437 DQS0 = 0, DQS1 = 0
2014 12:20:52.447015 DQM Delay:
2015 12:20:52.449466 DQM0 = 91, DQM1 = 84
2016 12:20:52.449937 DQ Delay:
2017 12:20:52.452896 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2018 12:20:52.456199 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2019 12:20:52.459514 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2020 12:20:52.462976 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2021 12:20:52.463461
2022 12:20:52.463830
2023 12:20:52.469810 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 395 ps
2024 12:20:52.472915 CH1 RK1: MR19=606, MR18=3A10
2025 12:20:52.479680 CH1_RK1: MR19=0x606, MR18=0x3A10, DQSOSC=395, MR23=63, INC=94, DEC=63
2026 12:20:52.483000 [RxdqsGatingPostProcess] freq 800
2027 12:20:52.489928 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 12:20:52.490401 Pre-setting of DQS Precalculation
2029 12:20:52.496674 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 12:20:52.503517 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 12:20:52.509814 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 12:20:52.510286
2033 12:20:52.510650
2034 12:20:52.513295 [Calibration Summary] 1600 Mbps
2035 12:20:52.516329 CH 0, Rank 0
2036 12:20:52.516788 SW Impedance : PASS
2037 12:20:52.519940 DUTY Scan : NO K
2038 12:20:52.523176 ZQ Calibration : PASS
2039 12:20:52.523734 Jitter Meter : NO K
2040 12:20:52.526710 CBT Training : PASS
2041 12:20:52.527298 Write leveling : PASS
2042 12:20:52.530107 RX DQS gating : PASS
2043 12:20:52.533471 RX DQ/DQS(RDDQC) : PASS
2044 12:20:52.533933 TX DQ/DQS : PASS
2045 12:20:52.536789 RX DATLAT : PASS
2046 12:20:52.539896 RX DQ/DQS(Engine): PASS
2047 12:20:52.540458 TX OE : NO K
2048 12:20:52.543166 All Pass.
2049 12:20:52.543727
2050 12:20:52.544091 CH 0, Rank 1
2051 12:20:52.546773 SW Impedance : PASS
2052 12:20:52.547237 DUTY Scan : NO K
2053 12:20:52.549827 ZQ Calibration : PASS
2054 12:20:52.553183 Jitter Meter : NO K
2055 12:20:52.553692 CBT Training : PASS
2056 12:20:52.556563 Write leveling : PASS
2057 12:20:52.559901 RX DQS gating : PASS
2058 12:20:52.560389 RX DQ/DQS(RDDQC) : PASS
2059 12:20:52.563132 TX DQ/DQS : PASS
2060 12:20:52.563697 RX DATLAT : PASS
2061 12:20:52.566229 RX DQ/DQS(Engine): PASS
2062 12:20:52.569798 TX OE : NO K
2063 12:20:52.570258 All Pass.
2064 12:20:52.570616
2065 12:20:52.570950 CH 1, Rank 0
2066 12:20:52.573093 SW Impedance : PASS
2067 12:20:52.576613 DUTY Scan : NO K
2068 12:20:52.577179 ZQ Calibration : PASS
2069 12:20:52.580245 Jitter Meter : NO K
2070 12:20:52.583098 CBT Training : PASS
2071 12:20:52.583563 Write leveling : PASS
2072 12:20:52.586251 RX DQS gating : PASS
2073 12:20:52.590041 RX DQ/DQS(RDDQC) : PASS
2074 12:20:52.590504 TX DQ/DQS : PASS
2075 12:20:52.593139 RX DATLAT : PASS
2076 12:20:52.596805 RX DQ/DQS(Engine): PASS
2077 12:20:52.597417 TX OE : NO K
2078 12:20:52.597787 All Pass.
2079 12:20:52.600000
2080 12:20:52.600612 CH 1, Rank 1
2081 12:20:52.603505 SW Impedance : PASS
2082 12:20:52.604068 DUTY Scan : NO K
2083 12:20:52.607060 ZQ Calibration : PASS
2084 12:20:52.607623 Jitter Meter : NO K
2085 12:20:52.609757 CBT Training : PASS
2086 12:20:52.613310 Write leveling : PASS
2087 12:20:52.613874 RX DQS gating : PASS
2088 12:20:52.616660 RX DQ/DQS(RDDQC) : PASS
2089 12:20:52.619821 TX DQ/DQS : PASS
2090 12:20:52.620369 RX DATLAT : PASS
2091 12:20:52.623317 RX DQ/DQS(Engine): PASS
2092 12:20:52.626844 TX OE : NO K
2093 12:20:52.627413 All Pass.
2094 12:20:52.627782
2095 12:20:52.630091 DramC Write-DBI off
2096 12:20:52.630553 PER_BANK_REFRESH: Hybrid Mode
2097 12:20:52.633432 TX_TRACKING: ON
2098 12:20:52.637325 [GetDramInforAfterCalByMRR] Vendor 6.
2099 12:20:52.640257 [GetDramInforAfterCalByMRR] Revision 606.
2100 12:20:52.643466 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 12:20:52.643930 MR0 0x3b3b
2102 12:20:52.647242 MR8 0x5151
2103 12:20:52.649972 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 12:20:52.650439
2105 12:20:52.650801 MR0 0x3b3b
2106 12:20:52.651138 MR8 0x5151
2107 12:20:52.656862 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 12:20:52.657591
2109 12:20:52.663055 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 12:20:52.666694 [FAST_K] Save calibration result to emmc
2111 12:20:52.669979 [FAST_K] Save calibration result to emmc
2112 12:20:52.673224 dram_init: config_dvfs: 1
2113 12:20:52.676603 dramc_set_vcore_voltage set vcore to 662500
2114 12:20:52.679972 Read voltage for 1200, 2
2115 12:20:52.680543 Vio18 = 0
2116 12:20:52.683565 Vcore = 662500
2117 12:20:52.684027 Vdram = 0
2118 12:20:52.684389 Vddq = 0
2119 12:20:52.684726 Vmddr = 0
2120 12:20:52.690379 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 12:20:52.696805 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 12:20:52.697572 MEM_TYPE=3, freq_sel=15
2123 12:20:52.700029 sv_algorithm_assistance_LP4_1600
2124 12:20:52.703433 ============ PULL DRAM RESETB DOWN ============
2125 12:20:52.710092 ========== PULL DRAM RESETB DOWN end =========
2126 12:20:52.713529 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 12:20:52.716690 ===================================
2128 12:20:52.720265 LPDDR4 DRAM CONFIGURATION
2129 12:20:52.723266 ===================================
2130 12:20:52.723731 EX_ROW_EN[0] = 0x0
2131 12:20:52.727091 EX_ROW_EN[1] = 0x0
2132 12:20:52.727764 LP4Y_EN = 0x0
2133 12:20:52.730795 WORK_FSP = 0x0
2134 12:20:52.731352 WL = 0x4
2135 12:20:52.733719 RL = 0x4
2136 12:20:52.734181 BL = 0x2
2137 12:20:52.736994 RPST = 0x0
2138 12:20:52.737560 RD_PRE = 0x0
2139 12:20:52.740290 WR_PRE = 0x1
2140 12:20:52.740751 WR_PST = 0x0
2141 12:20:52.743484 DBI_WR = 0x0
2142 12:20:52.746921 DBI_RD = 0x0
2143 12:20:52.747548 OTF = 0x1
2144 12:20:52.750156 ===================================
2145 12:20:52.753624 ===================================
2146 12:20:52.754088 ANA top config
2147 12:20:52.757038 ===================================
2148 12:20:52.760546 DLL_ASYNC_EN = 0
2149 12:20:52.763629 ALL_SLAVE_EN = 0
2150 12:20:52.766879 NEW_RANK_MODE = 1
2151 12:20:52.767350 DLL_IDLE_MODE = 1
2152 12:20:52.770028 LP45_APHY_COMB_EN = 1
2153 12:20:52.773487 TX_ODT_DIS = 1
2154 12:20:52.776813 NEW_8X_MODE = 1
2155 12:20:52.780337 ===================================
2156 12:20:52.784063 ===================================
2157 12:20:52.786958 data_rate = 2400
2158 12:20:52.787420 CKR = 1
2159 12:20:52.790277 DQ_P2S_RATIO = 8
2160 12:20:52.793404 ===================================
2161 12:20:52.796691 CA_P2S_RATIO = 8
2162 12:20:52.800495 DQ_CA_OPEN = 0
2163 12:20:52.803810 DQ_SEMI_OPEN = 0
2164 12:20:52.807033 CA_SEMI_OPEN = 0
2165 12:20:52.807500 CA_FULL_RATE = 0
2166 12:20:52.810818 DQ_CKDIV4_EN = 0
2167 12:20:52.813939 CA_CKDIV4_EN = 0
2168 12:20:52.817021 CA_PREDIV_EN = 0
2169 12:20:52.820207 PH8_DLY = 17
2170 12:20:52.823654 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 12:20:52.824218 DQ_AAMCK_DIV = 4
2172 12:20:52.826781 CA_AAMCK_DIV = 4
2173 12:20:52.830495 CA_ADMCK_DIV = 4
2174 12:20:52.833853 DQ_TRACK_CA_EN = 0
2175 12:20:52.837189 CA_PICK = 1200
2176 12:20:52.840641 CA_MCKIO = 1200
2177 12:20:52.843720 MCKIO_SEMI = 0
2178 12:20:52.844190 PLL_FREQ = 2366
2179 12:20:52.847427 DQ_UI_PI_RATIO = 32
2180 12:20:52.850785 CA_UI_PI_RATIO = 0
2181 12:20:52.854061 ===================================
2182 12:20:52.857670 ===================================
2183 12:20:52.860161 memory_type:LPDDR4
2184 12:20:52.860635 GP_NUM : 10
2185 12:20:52.864092 SRAM_EN : 1
2186 12:20:52.867079 MD32_EN : 0
2187 12:20:52.870278 ===================================
2188 12:20:52.870751 [ANA_INIT] >>>>>>>>>>>>>>
2189 12:20:52.873838 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 12:20:52.877251 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 12:20:52.880373 ===================================
2192 12:20:52.883656 data_rate = 2400,PCW = 0X5b00
2193 12:20:52.887272 ===================================
2194 12:20:52.890555 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 12:20:52.897488 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 12:20:52.900661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 12:20:52.907055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 12:20:52.910708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 12:20:52.913905 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 12:20:52.914379 [ANA_INIT] flow start
2201 12:20:52.917015 [ANA_INIT] PLL >>>>>>>>
2202 12:20:52.920435 [ANA_INIT] PLL <<<<<<<<
2203 12:20:52.920904 [ANA_INIT] MIDPI >>>>>>>>
2204 12:20:52.923550 [ANA_INIT] MIDPI <<<<<<<<
2205 12:20:52.927372 [ANA_INIT] DLL >>>>>>>>
2206 12:20:52.927841 [ANA_INIT] DLL <<<<<<<<
2207 12:20:52.930496 [ANA_INIT] flow end
2208 12:20:52.934195 ============ LP4 DIFF to SE enter ============
2209 12:20:52.940484 ============ LP4 DIFF to SE exit ============
2210 12:20:52.941074 [ANA_INIT] <<<<<<<<<<<<<
2211 12:20:52.943697 [Flow] Enable top DCM control >>>>>
2212 12:20:52.947592 [Flow] Enable top DCM control <<<<<
2213 12:20:52.950941 Enable DLL master slave shuffle
2214 12:20:52.957377 ==============================================================
2215 12:20:52.957880 Gating Mode config
2216 12:20:52.964131 ==============================================================
2217 12:20:52.964701 Config description:
2218 12:20:52.974200 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 12:20:52.980692 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 12:20:52.987592 SELPH_MODE 0: By rank 1: By Phase
2221 12:20:52.990738 ==============================================================
2222 12:20:52.994387 GAT_TRACK_EN = 1
2223 12:20:52.997411 RX_GATING_MODE = 2
2224 12:20:53.000989 RX_GATING_TRACK_MODE = 2
2225 12:20:53.004228 SELPH_MODE = 1
2226 12:20:53.007657 PICG_EARLY_EN = 1
2227 12:20:53.010899 VALID_LAT_VALUE = 1
2228 12:20:53.014283 ==============================================================
2229 12:20:53.020801 Enter into Gating configuration >>>>
2230 12:20:53.021328 Exit from Gating configuration <<<<
2231 12:20:53.024411 Enter into DVFS_PRE_config >>>>>
2232 12:20:53.037493 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 12:20:53.040705 Exit from DVFS_PRE_config <<<<<
2234 12:20:53.044063 Enter into PICG configuration >>>>
2235 12:20:53.047752 Exit from PICG configuration <<<<
2236 12:20:53.048315 [RX_INPUT] configuration >>>>>
2237 12:20:53.051175 [RX_INPUT] configuration <<<<<
2238 12:20:53.057712 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 12:20:53.061282 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 12:20:53.068076 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 12:20:53.074465 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 12:20:53.081158 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 12:20:53.088207 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 12:20:53.090855 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 12:20:53.094336 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 12:20:53.097719 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 12:20:53.104424 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 12:20:53.108054 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 12:20:53.110877 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 12:20:53.114339 ===================================
2251 12:20:53.117281 LPDDR4 DRAM CONFIGURATION
2252 12:20:53.120659 ===================================
2253 12:20:53.124281 EX_ROW_EN[0] = 0x0
2254 12:20:53.124848 EX_ROW_EN[1] = 0x0
2255 12:20:53.127391 LP4Y_EN = 0x0
2256 12:20:53.127908 WORK_FSP = 0x0
2257 12:20:53.130951 WL = 0x4
2258 12:20:53.131512 RL = 0x4
2259 12:20:53.134184 BL = 0x2
2260 12:20:53.134645 RPST = 0x0
2261 12:20:53.137266 RD_PRE = 0x0
2262 12:20:53.137792 WR_PRE = 0x1
2263 12:20:53.140890 WR_PST = 0x0
2264 12:20:53.141395 DBI_WR = 0x0
2265 12:20:53.144770 DBI_RD = 0x0
2266 12:20:53.145291 OTF = 0x1
2267 12:20:53.147328 ===================================
2268 12:20:53.150633 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 12:20:53.157436 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 12:20:53.160569 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 12:20:53.164126 ===================================
2272 12:20:53.167412 LPDDR4 DRAM CONFIGURATION
2273 12:20:53.170614 ===================================
2274 12:20:53.171077 EX_ROW_EN[0] = 0x10
2275 12:20:53.174034 EX_ROW_EN[1] = 0x0
2276 12:20:53.177429 LP4Y_EN = 0x0
2277 12:20:53.177894 WORK_FSP = 0x0
2278 12:20:53.180677 WL = 0x4
2279 12:20:53.181170 RL = 0x4
2280 12:20:53.184195 BL = 0x2
2281 12:20:53.184672 RPST = 0x0
2282 12:20:53.187993 RD_PRE = 0x0
2283 12:20:53.188553 WR_PRE = 0x1
2284 12:20:53.191308 WR_PST = 0x0
2285 12:20:53.191915 DBI_WR = 0x0
2286 12:20:53.194209 DBI_RD = 0x0
2287 12:20:53.194671 OTF = 0x1
2288 12:20:53.197589 ===================================
2289 12:20:53.204366 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 12:20:53.204927 ==
2291 12:20:53.207674 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 12:20:53.211327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 12:20:53.211783 ==
2294 12:20:53.214364 [Duty_Offset_Calibration]
2295 12:20:53.214813 B0:2 B1:0 CA:1
2296 12:20:53.218023
2297 12:20:53.220900 [DutyScan_Calibration_Flow] k_type=0
2298 12:20:53.227914
2299 12:20:53.228399 ==CLK 0==
2300 12:20:53.231234 Final CLK duty delay cell = -4
2301 12:20:53.235224 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2302 12:20:53.238105 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2303 12:20:53.241540 [-4] AVG Duty = 4953%(X100)
2304 12:20:53.241995
2305 12:20:53.244821 CH0 CLK Duty spec in!! Max-Min= 156%
2306 12:20:53.248572 [DutyScan_Calibration_Flow] ====Done====
2307 12:20:53.249169
2308 12:20:53.251540 [DutyScan_Calibration_Flow] k_type=1
2309 12:20:53.267312
2310 12:20:53.267863 ==DQS 0 ==
2311 12:20:53.270055 Final DQS duty delay cell = 0
2312 12:20:53.273710 [0] MAX Duty = 5187%(X100), DQS PI = 30
2313 12:20:53.277267 [0] MIN Duty = 4938%(X100), DQS PI = 0
2314 12:20:53.277722 [0] AVG Duty = 5062%(X100)
2315 12:20:53.278077
2316 12:20:53.280266 ==DQS 1 ==
2317 12:20:53.283830 Final DQS duty delay cell = -4
2318 12:20:53.287414 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2319 12:20:53.290617 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2320 12:20:53.293845 [-4] AVG Duty = 5031%(X100)
2321 12:20:53.294257
2322 12:20:53.297442 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2323 12:20:53.297955
2324 12:20:53.300579 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2325 12:20:53.303994 [DutyScan_Calibration_Flow] ====Done====
2326 12:20:53.304521
2327 12:20:53.307498 [DutyScan_Calibration_Flow] k_type=3
2328 12:20:53.324091
2329 12:20:53.324640 ==DQM 0 ==
2330 12:20:53.327510 Final DQM duty delay cell = 0
2331 12:20:53.330560 [0] MAX Duty = 5062%(X100), DQS PI = 24
2332 12:20:53.333854 [0] MIN Duty = 4813%(X100), DQS PI = 2
2333 12:20:53.334414 [0] AVG Duty = 4937%(X100)
2334 12:20:53.336858
2335 12:20:53.337374 ==DQM 1 ==
2336 12:20:53.340244 Final DQM duty delay cell = 0
2337 12:20:53.343883 [0] MAX Duty = 5187%(X100), DQS PI = 48
2338 12:20:53.347263 [0] MIN Duty = 5000%(X100), DQS PI = 14
2339 12:20:53.347835 [0] AVG Duty = 5093%(X100)
2340 12:20:53.350448
2341 12:20:53.353748 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2342 12:20:53.354202
2343 12:20:53.357025 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2344 12:20:53.360680 [DutyScan_Calibration_Flow] ====Done====
2345 12:20:53.361349
2346 12:20:53.363940 [DutyScan_Calibration_Flow] k_type=2
2347 12:20:53.380378
2348 12:20:53.380925 ==DQ 0 ==
2349 12:20:53.383539 Final DQ duty delay cell = -4
2350 12:20:53.387081 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2351 12:20:53.390509 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2352 12:20:53.393800 [-4] AVG Duty = 4968%(X100)
2353 12:20:53.394344
2354 12:20:53.394697 ==DQ 1 ==
2355 12:20:53.396725 Final DQ duty delay cell = 4
2356 12:20:53.400245 [4] MAX Duty = 5093%(X100), DQS PI = 6
2357 12:20:53.403605 [4] MIN Duty = 5031%(X100), DQS PI = 0
2358 12:20:53.404172 [4] AVG Duty = 5062%(X100)
2359 12:20:53.406999
2360 12:20:53.410299 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2361 12:20:53.410757
2362 12:20:53.413586 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2363 12:20:53.417328 [DutyScan_Calibration_Flow] ====Done====
2364 12:20:53.417885 ==
2365 12:20:53.420876 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 12:20:53.423602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 12:20:53.424150 ==
2368 12:20:53.426904 [Duty_Offset_Calibration]
2369 12:20:53.427450 B0:0 B1:-1 CA:2
2370 12:20:53.427805
2371 12:20:53.430531 [DutyScan_Calibration_Flow] k_type=0
2372 12:20:53.440747
2373 12:20:53.441345 ==CLK 0==
2374 12:20:53.443839 Final CLK duty delay cell = 0
2375 12:20:53.447121 [0] MAX Duty = 5156%(X100), DQS PI = 16
2376 12:20:53.450150 [0] MIN Duty = 4938%(X100), DQS PI = 44
2377 12:20:53.450602 [0] AVG Duty = 5047%(X100)
2378 12:20:53.453727
2379 12:20:53.454180 CH1 CLK Duty spec in!! Max-Min= 218%
2380 12:20:53.460483 [DutyScan_Calibration_Flow] ====Done====
2381 12:20:53.460969
2382 12:20:53.463909 [DutyScan_Calibration_Flow] k_type=1
2383 12:20:53.479983
2384 12:20:53.480538 ==DQS 0 ==
2385 12:20:53.483533 Final DQS duty delay cell = 0
2386 12:20:53.486717 [0] MAX Duty = 5093%(X100), DQS PI = 24
2387 12:20:53.489813 [0] MIN Duty = 4969%(X100), DQS PI = 0
2388 12:20:53.490312 [0] AVG Duty = 5031%(X100)
2389 12:20:53.493486
2390 12:20:53.494028 ==DQS 1 ==
2391 12:20:53.496688 Final DQS duty delay cell = 0
2392 12:20:53.500044 [0] MAX Duty = 5156%(X100), DQS PI = 0
2393 12:20:53.503477 [0] MIN Duty = 4844%(X100), DQS PI = 36
2394 12:20:53.504036 [0] AVG Duty = 5000%(X100)
2395 12:20:53.504398
2396 12:20:53.509781 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2397 12:20:53.510332
2398 12:20:53.513424 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2399 12:20:53.516954 [DutyScan_Calibration_Flow] ====Done====
2400 12:20:53.517509
2401 12:20:53.519895 [DutyScan_Calibration_Flow] k_type=3
2402 12:20:53.536528
2403 12:20:53.537112 ==DQM 0 ==
2404 12:20:53.539744 Final DQM duty delay cell = 4
2405 12:20:53.542826 [4] MAX Duty = 5093%(X100), DQS PI = 20
2406 12:20:53.546395 [4] MIN Duty = 4969%(X100), DQS PI = 28
2407 12:20:53.549841 [4] AVG Duty = 5031%(X100)
2408 12:20:53.550424
2409 12:20:53.550778 ==DQM 1 ==
2410 12:20:53.553156 Final DQM duty delay cell = -4
2411 12:20:53.556306 [-4] MAX Duty = 5000%(X100), DQS PI = 60
2412 12:20:53.559354 [-4] MIN Duty = 4751%(X100), DQS PI = 34
2413 12:20:53.563214 [-4] AVG Duty = 4875%(X100)
2414 12:20:53.563893
2415 12:20:53.566310 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2416 12:20:53.566852
2417 12:20:53.569588 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2418 12:20:53.573026 [DutyScan_Calibration_Flow] ====Done====
2419 12:20:53.573478
2420 12:20:53.576573 [DutyScan_Calibration_Flow] k_type=2
2421 12:20:53.593387
2422 12:20:53.593943 ==DQ 0 ==
2423 12:20:53.596602 Final DQ duty delay cell = 0
2424 12:20:53.600350 [0] MAX Duty = 5062%(X100), DQS PI = 20
2425 12:20:53.603555 [0] MIN Duty = 4938%(X100), DQS PI = 46
2426 12:20:53.604108 [0] AVG Duty = 5000%(X100)
2427 12:20:53.606601
2428 12:20:53.607145 ==DQ 1 ==
2429 12:20:53.610099 Final DQ duty delay cell = 0
2430 12:20:53.613039 [0] MAX Duty = 5031%(X100), DQS PI = 2
2431 12:20:53.616532 [0] MIN Duty = 4813%(X100), DQS PI = 34
2432 12:20:53.617117 [0] AVG Duty = 4922%(X100)
2433 12:20:53.617481
2434 12:20:53.619694 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2435 12:20:53.623184
2436 12:20:53.626586 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2437 12:20:53.629597 [DutyScan_Calibration_Flow] ====Done====
2438 12:20:53.633154 nWR fixed to 30
2439 12:20:53.633710 [ModeRegInit_LP4] CH0 RK0
2440 12:20:53.636456 [ModeRegInit_LP4] CH0 RK1
2441 12:20:53.640082 [ModeRegInit_LP4] CH1 RK0
2442 12:20:53.640706 [ModeRegInit_LP4] CH1 RK1
2443 12:20:53.643199 match AC timing 7
2444 12:20:53.646949 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 12:20:53.649935 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 12:20:53.656536 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 12:20:53.659664 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 12:20:53.666791 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 12:20:53.667243 ==
2450 12:20:53.669700 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 12:20:53.673155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 12:20:53.673624 ==
2453 12:20:53.680104 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 12:20:53.683330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2455 12:20:53.693467 [CA 0] Center 38 (8~69) winsize 62
2456 12:20:53.696791 [CA 1] Center 38 (7~69) winsize 63
2457 12:20:53.699576 [CA 2] Center 35 (5~66) winsize 62
2458 12:20:53.703529 [CA 3] Center 35 (5~66) winsize 62
2459 12:20:53.706254 [CA 4] Center 34 (4~65) winsize 62
2460 12:20:53.709683 [CA 5] Center 33 (3~63) winsize 61
2461 12:20:53.710245
2462 12:20:53.713055 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2463 12:20:53.713642
2464 12:20:53.716394 [CATrainingPosCal] consider 1 rank data
2465 12:20:53.719727 u2DelayCellTimex100 = 270/100 ps
2466 12:20:53.723426 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2467 12:20:53.726801 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2468 12:20:53.733366 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2469 12:20:53.736642 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2470 12:20:53.740271 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2471 12:20:53.743184 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2472 12:20:53.743662
2473 12:20:53.746548 CA PerBit enable=1, Macro0, CA PI delay=33
2474 12:20:53.747106
2475 12:20:53.749791 [CBTSetCACLKResult] CA Dly = 33
2476 12:20:53.750259 CS Dly: 6 (0~37)
2477 12:20:53.750628 ==
2478 12:20:53.753398 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 12:20:53.759966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 12:20:53.760560 ==
2481 12:20:53.763501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 12:20:53.769675 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 12:20:53.778890 [CA 0] Center 39 (8~70) winsize 63
2484 12:20:53.782236 [CA 1] Center 38 (8~69) winsize 62
2485 12:20:53.785690 [CA 2] Center 35 (5~66) winsize 62
2486 12:20:53.788884 [CA 3] Center 35 (5~66) winsize 62
2487 12:20:53.791874 [CA 4] Center 34 (4~65) winsize 62
2488 12:20:53.795408 [CA 5] Center 34 (4~64) winsize 61
2489 12:20:53.795876
2490 12:20:53.798655 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2491 12:20:53.799165
2492 12:20:53.802317 [CATrainingPosCal] consider 2 rank data
2493 12:20:53.805444 u2DelayCellTimex100 = 270/100 ps
2494 12:20:53.809072 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2495 12:20:53.811928 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2496 12:20:53.819332 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 12:20:53.822347 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2498 12:20:53.825610 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2499 12:20:53.828749 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2500 12:20:53.829360
2501 12:20:53.832229 CA PerBit enable=1, Macro0, CA PI delay=33
2502 12:20:53.832802
2503 12:20:53.835370 [CBTSetCACLKResult] CA Dly = 33
2504 12:20:53.835925 CS Dly: 7 (0~39)
2505 12:20:53.836298
2506 12:20:53.838518 ----->DramcWriteLeveling(PI) begin...
2507 12:20:53.842096 ==
2508 12:20:53.842566 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 12:20:53.848906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 12:20:53.849549 ==
2511 12:20:53.852249 Write leveling (Byte 0): 33 => 33
2512 12:20:53.855851 Write leveling (Byte 1): 31 => 31
2513 12:20:53.858636 DramcWriteLeveling(PI) end<-----
2514 12:20:53.859069
2515 12:20:53.859429 ==
2516 12:20:53.862178 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 12:20:53.865520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 12:20:53.865994 ==
2519 12:20:53.868759 [Gating] SW mode calibration
2520 12:20:53.875861 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 12:20:53.879162 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 12:20:53.885303 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2523 12:20:53.888980 0 15 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
2524 12:20:53.892454 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 12:20:53.899412 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 12:20:53.902391 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 12:20:53.905560 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 12:20:53.912269 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2529 12:20:53.915822 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2530 12:20:53.918975 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2531 12:20:53.925806 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 12:20:53.928829 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 12:20:53.932467 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 12:20:53.939209 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 12:20:53.942637 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 12:20:53.945794 1 0 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
2537 12:20:53.949318 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2538 12:20:53.956181 1 1 0 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
2539 12:20:53.959528 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 12:20:53.962456 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 12:20:53.969773 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 12:20:53.972311 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 12:20:53.975849 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 12:20:53.982754 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 12:20:53.985910 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 12:20:53.989531 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 12:20:53.995925 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:20:53.999095 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:20:54.002731 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:20:54.009175 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:20:54.012788 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:20:54.016166 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 12:20:54.019742 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 12:20:54.026062 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 12:20:54.029659 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 12:20:54.033093 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 12:20:54.039818 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 12:20:54.043004 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:20:54.046078 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:20:54.053258 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2561 12:20:54.057463 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2562 12:20:54.059973 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2563 12:20:54.063008 Total UI for P1: 0, mck2ui 16
2564 12:20:54.066335 best dqsien dly found for B0: ( 1, 3, 26)
2565 12:20:54.070161 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 12:20:54.072862 Total UI for P1: 0, mck2ui 16
2567 12:20:54.076379 best dqsien dly found for B1: ( 1, 4, 0)
2568 12:20:54.079953 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2569 12:20:54.086205 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2570 12:20:54.086678
2571 12:20:54.089714 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2572 12:20:54.093055 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2573 12:20:54.096632 [Gating] SW calibration Done
2574 12:20:54.097310 ==
2575 12:20:54.099700 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 12:20:54.102928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 12:20:54.103519 ==
2578 12:20:54.103901 RX Vref Scan: 0
2579 12:20:54.107075
2580 12:20:54.107539 RX Vref 0 -> 0, step: 1
2581 12:20:54.107913
2582 12:20:54.109450 RX Delay -40 -> 252, step: 8
2583 12:20:54.112985 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
2584 12:20:54.116262 iDelay=208, Bit 1, Center 123 (48 ~ 199) 152
2585 12:20:54.122758 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2586 12:20:54.126229 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2587 12:20:54.129444 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2588 12:20:54.133010 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2589 12:20:54.136256 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2590 12:20:54.142774 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2591 12:20:54.146272 iDelay=208, Bit 8, Center 103 (40 ~ 167) 128
2592 12:20:54.149280 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2593 12:20:54.152898 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2594 12:20:54.156154 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2595 12:20:54.162974 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2596 12:20:54.166140 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2597 12:20:54.169422 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2598 12:20:54.172828 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2599 12:20:54.173351 ==
2600 12:20:54.176360 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 12:20:54.179474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 12:20:54.183188 ==
2603 12:20:54.183653 DQS Delay:
2604 12:20:54.184016 DQS0 = 0, DQS1 = 0
2605 12:20:54.186376 DQM Delay:
2606 12:20:54.186927 DQM0 = 122, DQM1 = 110
2607 12:20:54.189469 DQ Delay:
2608 12:20:54.192903 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2609 12:20:54.196245 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2610 12:20:54.199794 DQ8 =103, DQ9 =99, DQ10 =107, DQ11 =107
2611 12:20:54.203159 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2612 12:20:54.203875
2613 12:20:54.204510
2614 12:20:54.205096 ==
2615 12:20:54.206194 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 12:20:54.209545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 12:20:54.210064 ==
2618 12:20:54.210432
2619 12:20:54.212811
2620 12:20:54.213254 TX Vref Scan disable
2621 12:20:54.216143 == TX Byte 0 ==
2622 12:20:54.219902 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2623 12:20:54.222895 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2624 12:20:54.226504 == TX Byte 1 ==
2625 12:20:54.229440 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2626 12:20:54.233112 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2627 12:20:54.233531 ==
2628 12:20:54.236155 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 12:20:54.243116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 12:20:54.243626 ==
2631 12:20:54.253460 TX Vref=22, minBit 1, minWin=24, winSum=407
2632 12:20:54.256763 TX Vref=24, minBit 0, minWin=25, winSum=415
2633 12:20:54.260157 TX Vref=26, minBit 0, minWin=25, winSum=417
2634 12:20:54.263260 TX Vref=28, minBit 3, minWin=25, winSum=423
2635 12:20:54.266980 TX Vref=30, minBit 2, minWin=25, winSum=418
2636 12:20:54.270288 TX Vref=32, minBit 5, minWin=25, winSum=422
2637 12:20:54.276762 [TxChooseVref] Worse bit 3, Min win 25, Win sum 423, Final Vref 28
2638 12:20:54.277302
2639 12:20:54.280184 Final TX Range 1 Vref 28
2640 12:20:54.280644
2641 12:20:54.281074 ==
2642 12:20:54.283508 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 12:20:54.286581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 12:20:54.287083 ==
2645 12:20:54.287448
2646 12:20:54.287783
2647 12:20:54.289973 TX Vref Scan disable
2648 12:20:54.293531 == TX Byte 0 ==
2649 12:20:54.297026 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2650 12:20:54.300153 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2651 12:20:54.303726 == TX Byte 1 ==
2652 12:20:54.307486 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2653 12:20:54.310420 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2654 12:20:54.311025
2655 12:20:54.313492 [DATLAT]
2656 12:20:54.313953 Freq=1200, CH0 RK0
2657 12:20:54.314326
2658 12:20:54.316744 DATLAT Default: 0xd
2659 12:20:54.317222 0, 0xFFFF, sum = 0
2660 12:20:54.320585 1, 0xFFFF, sum = 0
2661 12:20:54.321191 2, 0xFFFF, sum = 0
2662 12:20:54.323523 3, 0xFFFF, sum = 0
2663 12:20:54.324091 4, 0xFFFF, sum = 0
2664 12:20:54.326650 5, 0xFFFF, sum = 0
2665 12:20:54.327117 6, 0xFFFF, sum = 0
2666 12:20:54.330247 7, 0xFFFF, sum = 0
2667 12:20:54.330877 8, 0xFFFF, sum = 0
2668 12:20:54.333323 9, 0xFFFF, sum = 0
2669 12:20:54.333793 10, 0xFFFF, sum = 0
2670 12:20:54.337013 11, 0xFFFF, sum = 0
2671 12:20:54.337483 12, 0x0, sum = 1
2672 12:20:54.340112 13, 0x0, sum = 2
2673 12:20:54.340586 14, 0x0, sum = 3
2674 12:20:54.343875 15, 0x0, sum = 4
2675 12:20:54.344343 best_step = 13
2676 12:20:54.344705
2677 12:20:54.345076 ==
2678 12:20:54.346925 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 12:20:54.353236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 12:20:54.353701 ==
2681 12:20:54.354064 RX Vref Scan: 1
2682 12:20:54.354405
2683 12:20:54.356888 Set Vref Range= 32 -> 127
2684 12:20:54.357498
2685 12:20:54.360797 RX Vref 32 -> 127, step: 1
2686 12:20:54.361412
2687 12:20:54.363641 RX Delay -13 -> 252, step: 4
2688 12:20:54.364203
2689 12:20:54.367052 Set Vref, RX VrefLevel [Byte0]: 32
2690 12:20:54.367614 [Byte1]: 32
2691 12:20:54.371830
2692 12:20:54.372396 Set Vref, RX VrefLevel [Byte0]: 33
2693 12:20:54.374835 [Byte1]: 33
2694 12:20:54.379614
2695 12:20:54.380210 Set Vref, RX VrefLevel [Byte0]: 34
2696 12:20:54.382922 [Byte1]: 34
2697 12:20:54.387223
2698 12:20:54.387685 Set Vref, RX VrefLevel [Byte0]: 35
2699 12:20:54.390807 [Byte1]: 35
2700 12:20:54.395375
2701 12:20:54.395946 Set Vref, RX VrefLevel [Byte0]: 36
2702 12:20:54.398533 [Byte1]: 36
2703 12:20:54.403381
2704 12:20:54.403943 Set Vref, RX VrefLevel [Byte0]: 37
2705 12:20:54.406424 [Byte1]: 37
2706 12:20:54.411025
2707 12:20:54.411628 Set Vref, RX VrefLevel [Byte0]: 38
2708 12:20:54.414906 [Byte1]: 38
2709 12:20:54.419257
2710 12:20:54.419816 Set Vref, RX VrefLevel [Byte0]: 39
2711 12:20:54.422345 [Byte1]: 39
2712 12:20:54.427047
2713 12:20:54.427614 Set Vref, RX VrefLevel [Byte0]: 40
2714 12:20:54.429928 [Byte1]: 40
2715 12:20:54.434928
2716 12:20:54.435507 Set Vref, RX VrefLevel [Byte0]: 41
2717 12:20:54.437840 [Byte1]: 41
2718 12:20:54.442566
2719 12:20:54.443125 Set Vref, RX VrefLevel [Byte0]: 42
2720 12:20:54.445699 [Byte1]: 42
2721 12:20:54.450120
2722 12:20:54.450624 Set Vref, RX VrefLevel [Byte0]: 43
2723 12:20:54.453459 [Byte1]: 43
2724 12:20:54.458435
2725 12:20:54.458994 Set Vref, RX VrefLevel [Byte0]: 44
2726 12:20:54.461522 [Byte1]: 44
2727 12:20:54.465857
2728 12:20:54.466318 Set Vref, RX VrefLevel [Byte0]: 45
2729 12:20:54.469535 [Byte1]: 45
2730 12:20:54.473788
2731 12:20:54.474284 Set Vref, RX VrefLevel [Byte0]: 46
2732 12:20:54.477318 [Byte1]: 46
2733 12:20:54.482386
2734 12:20:54.482946 Set Vref, RX VrefLevel [Byte0]: 47
2735 12:20:54.485236 [Byte1]: 47
2736 12:20:54.489568
2737 12:20:54.490026 Set Vref, RX VrefLevel [Byte0]: 48
2738 12:20:54.493056 [Byte1]: 48
2739 12:20:54.498084
2740 12:20:54.498644 Set Vref, RX VrefLevel [Byte0]: 49
2741 12:20:54.500997 [Byte1]: 49
2742 12:20:54.505638
2743 12:20:54.506216 Set Vref, RX VrefLevel [Byte0]: 50
2744 12:20:54.508741 [Byte1]: 50
2745 12:20:54.513551
2746 12:20:54.514258 Set Vref, RX VrefLevel [Byte0]: 51
2747 12:20:54.517153 [Byte1]: 51
2748 12:20:54.521191
2749 12:20:54.521930 Set Vref, RX VrefLevel [Byte0]: 52
2750 12:20:54.524656 [Byte1]: 52
2751 12:20:54.529306
2752 12:20:54.529974 Set Vref, RX VrefLevel [Byte0]: 53
2753 12:20:54.535512 [Byte1]: 53
2754 12:20:54.536129
2755 12:20:54.538858 Set Vref, RX VrefLevel [Byte0]: 54
2756 12:20:54.542487 [Byte1]: 54
2757 12:20:54.543125
2758 12:20:54.545778 Set Vref, RX VrefLevel [Byte0]: 55
2759 12:20:54.549655 [Byte1]: 55
2760 12:20:54.552615
2761 12:20:54.553184 Set Vref, RX VrefLevel [Byte0]: 56
2762 12:20:54.555968 [Byte1]: 56
2763 12:20:54.560421
2764 12:20:54.561010 Set Vref, RX VrefLevel [Byte0]: 57
2765 12:20:54.563947 [Byte1]: 57
2766 12:20:54.568916
2767 12:20:54.569368 Set Vref, RX VrefLevel [Byte0]: 58
2768 12:20:54.571786 [Byte1]: 58
2769 12:20:54.576200
2770 12:20:54.576714 Set Vref, RX VrefLevel [Byte0]: 59
2771 12:20:54.579934 [Byte1]: 59
2772 12:20:54.584267
2773 12:20:54.584784 Set Vref, RX VrefLevel [Byte0]: 60
2774 12:20:54.587787 [Byte1]: 60
2775 12:20:54.592014
2776 12:20:54.592081 Set Vref, RX VrefLevel [Byte0]: 61
2777 12:20:54.595082 [Byte1]: 61
2778 12:20:54.599952
2779 12:20:54.600024 Set Vref, RX VrefLevel [Byte0]: 62
2780 12:20:54.603110 [Byte1]: 62
2781 12:20:54.607771
2782 12:20:54.607838 Set Vref, RX VrefLevel [Byte0]: 63
2783 12:20:54.611029 [Byte1]: 63
2784 12:20:54.615523
2785 12:20:54.615624 Set Vref, RX VrefLevel [Byte0]: 64
2786 12:20:54.618707 [Byte1]: 64
2787 12:20:54.623207
2788 12:20:54.623304 Set Vref, RX VrefLevel [Byte0]: 65
2789 12:20:54.626457 [Byte1]: 65
2790 12:20:54.631398
2791 12:20:54.631497 Set Vref, RX VrefLevel [Byte0]: 66
2792 12:20:54.634608 [Byte1]: 66
2793 12:20:54.639009
2794 12:20:54.639103 Set Vref, RX VrefLevel [Byte0]: 67
2795 12:20:54.642413 [Byte1]: 67
2796 12:20:54.647102
2797 12:20:54.647201 Set Vref, RX VrefLevel [Byte0]: 68
2798 12:20:54.650183 [Byte1]: 68
2799 12:20:54.654902
2800 12:20:54.654997 Set Vref, RX VrefLevel [Byte0]: 69
2801 12:20:54.658563 [Byte1]: 69
2802 12:20:54.663032
2803 12:20:54.663138 Final RX Vref Byte 0 = 58 to rank0
2804 12:20:54.666287 Final RX Vref Byte 1 = 50 to rank0
2805 12:20:54.669622 Final RX Vref Byte 0 = 58 to rank1
2806 12:20:54.673092 Final RX Vref Byte 1 = 50 to rank1==
2807 12:20:54.676271 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 12:20:54.679461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 12:20:54.683017 ==
2810 12:20:54.683118 DQS Delay:
2811 12:20:54.683209 DQS0 = 0, DQS1 = 0
2812 12:20:54.686455 DQM Delay:
2813 12:20:54.686553 DQM0 = 122, DQM1 = 109
2814 12:20:54.689714 DQ Delay:
2815 12:20:54.693054 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2816 12:20:54.696741 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2817 12:20:54.699851 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =108
2818 12:20:54.703324 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2819 12:20:54.703421
2820 12:20:54.703510
2821 12:20:54.709772 [DQSOSCAuto] RK0, (LSB)MR18= 0x906, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 406 ps
2822 12:20:54.713091 CH0 RK0: MR19=404, MR18=906
2823 12:20:54.720578 CH0_RK0: MR19=0x404, MR18=0x906, DQSOSC=406, MR23=63, INC=39, DEC=26
2824 12:20:54.720682
2825 12:20:54.723227 ----->DramcWriteLeveling(PI) begin...
2826 12:20:54.723326 ==
2827 12:20:54.726921 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 12:20:54.730623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 12:20:54.730722 ==
2830 12:20:54.733358 Write leveling (Byte 0): 33 => 33
2831 12:20:54.736721 Write leveling (Byte 1): 29 => 29
2832 12:20:54.740308 DramcWriteLeveling(PI) end<-----
2833 12:20:54.740402
2834 12:20:54.740490 ==
2835 12:20:54.743709 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 12:20:54.746895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 12:20:54.746993 ==
2838 12:20:54.750429 [Gating] SW mode calibration
2839 12:20:54.756920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 12:20:54.763564 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 12:20:54.766731 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2842 12:20:54.770161 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 12:20:54.777021 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 12:20:54.780529 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 12:20:54.783699 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 12:20:54.790780 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 12:20:54.793816 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 12:20:54.797280 0 15 28 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (1 0)
2849 12:20:54.803782 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2850 12:20:54.807243 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 12:20:54.810275 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 12:20:54.816885 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 12:20:54.820489 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 12:20:54.823772 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 12:20:54.830394 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2856 12:20:54.834189 1 0 28 | B1->B0 | 3a3a 4140 | 0 1 | (0 0) (0 0)
2857 12:20:54.836973 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 12:20:54.843574 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 12:20:54.846874 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 12:20:54.850490 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 12:20:54.857039 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 12:20:54.860532 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 12:20:54.863654 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 12:20:54.867159 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2865 12:20:54.873524 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2866 12:20:54.877146 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:20:54.880315 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:20:54.887303 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:20:54.890763 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:20:54.894043 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 12:20:54.900758 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 12:20:54.903826 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 12:20:54.907470 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 12:20:54.913788 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 12:20:54.917139 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 12:20:54.920901 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 12:20:54.927296 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 12:20:54.930956 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 12:20:54.934084 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 12:20:54.937647 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2881 12:20:54.944320 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 12:20:54.947141 Total UI for P1: 0, mck2ui 16
2883 12:20:54.951091 best dqsien dly found for B0: ( 1, 3, 28)
2884 12:20:54.954136 Total UI for P1: 0, mck2ui 16
2885 12:20:54.957271 best dqsien dly found for B1: ( 1, 3, 28)
2886 12:20:54.960835 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2887 12:20:54.964154 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2888 12:20:54.964237
2889 12:20:54.967504 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2890 12:20:54.970806 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2891 12:20:54.974312 [Gating] SW calibration Done
2892 12:20:54.974396 ==
2893 12:20:54.978009 Dram Type= 6, Freq= 0, CH_0, rank 1
2894 12:20:54.981021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2895 12:20:54.981104 ==
2896 12:20:54.984269 RX Vref Scan: 0
2897 12:20:54.984372
2898 12:20:54.984438 RX Vref 0 -> 0, step: 1
2899 12:20:54.984505
2900 12:20:54.988381 RX Delay -40 -> 252, step: 8
2901 12:20:54.990955 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2902 12:20:54.997561 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2903 12:20:55.000953 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2904 12:20:55.004580 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2905 12:20:55.007984 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2906 12:20:55.011525 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2907 12:20:55.017834 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2908 12:20:55.021131 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2909 12:20:55.024811 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2910 12:20:55.027991 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2911 12:20:55.031510 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2912 12:20:55.034891 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2913 12:20:55.041634 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2914 12:20:55.044776 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2915 12:20:55.049081 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2916 12:20:55.051806 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2917 12:20:55.052236 ==
2918 12:20:55.054744 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 12:20:55.061483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 12:20:55.061924 ==
2921 12:20:55.062264 DQS Delay:
2922 12:20:55.064891 DQS0 = 0, DQS1 = 0
2923 12:20:55.065381 DQM Delay:
2924 12:20:55.065721 DQM0 = 120, DQM1 = 108
2925 12:20:55.068677 DQ Delay:
2926 12:20:55.071901 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2927 12:20:55.074955 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2928 12:20:55.078591 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2929 12:20:55.081405 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2930 12:20:55.081895
2931 12:20:55.082307
2932 12:20:55.082628 ==
2933 12:20:55.084889 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 12:20:55.088258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 12:20:55.088786 ==
2936 12:20:55.091764
2937 12:20:55.092189
2938 12:20:55.092524 TX Vref Scan disable
2939 12:20:55.095289 == TX Byte 0 ==
2940 12:20:55.098228 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2941 12:20:55.101584 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2942 12:20:55.105381 == TX Byte 1 ==
2943 12:20:55.108351 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2944 12:20:55.111985 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2945 12:20:55.112518 ==
2946 12:20:55.115292 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 12:20:55.121649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 12:20:55.122127 ==
2949 12:20:55.132354 TX Vref=22, minBit 1, minWin=24, winSum=416
2950 12:20:55.135454 TX Vref=24, minBit 0, minWin=25, winSum=423
2951 12:20:55.138957 TX Vref=26, minBit 0, minWin=25, winSum=424
2952 12:20:55.142318 TX Vref=28, minBit 1, minWin=25, winSum=426
2953 12:20:55.145580 TX Vref=30, minBit 5, minWin=25, winSum=428
2954 12:20:55.148773 TX Vref=32, minBit 7, minWin=25, winSum=428
2955 12:20:55.155891 [TxChooseVref] Worse bit 5, Min win 25, Win sum 428, Final Vref 30
2956 12:20:55.155969
2957 12:20:55.158904 Final TX Range 1 Vref 30
2958 12:20:55.158978
2959 12:20:55.159043 ==
2960 12:20:55.162082 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 12:20:55.165458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 12:20:55.165531 ==
2963 12:20:55.165597
2964 12:20:55.165655
2965 12:20:55.168768 TX Vref Scan disable
2966 12:20:55.172146 == TX Byte 0 ==
2967 12:20:55.175335 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2968 12:20:55.178699 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2969 12:20:55.182079 == TX Byte 1 ==
2970 12:20:55.185342 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2971 12:20:55.188895 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2972 12:20:55.189014
2973 12:20:55.192333 [DATLAT]
2974 12:20:55.192424 Freq=1200, CH0 RK1
2975 12:20:55.192526
2976 12:20:55.195712 DATLAT Default: 0xd
2977 12:20:55.195812 0, 0xFFFF, sum = 0
2978 12:20:55.198878 1, 0xFFFF, sum = 0
2979 12:20:55.198953 2, 0xFFFF, sum = 0
2980 12:20:55.202054 3, 0xFFFF, sum = 0
2981 12:20:55.202142 4, 0xFFFF, sum = 0
2982 12:20:55.205342 5, 0xFFFF, sum = 0
2983 12:20:55.205425 6, 0xFFFF, sum = 0
2984 12:20:55.208694 7, 0xFFFF, sum = 0
2985 12:20:55.208769 8, 0xFFFF, sum = 0
2986 12:20:55.211896 9, 0xFFFF, sum = 0
2987 12:20:55.211975 10, 0xFFFF, sum = 0
2988 12:20:55.215281 11, 0xFFFF, sum = 0
2989 12:20:55.218772 12, 0x0, sum = 1
2990 12:20:55.218850 13, 0x0, sum = 2
2991 12:20:55.218922 14, 0x0, sum = 3
2992 12:20:55.222232 15, 0x0, sum = 4
2993 12:20:55.222317 best_step = 13
2994 12:20:55.222389
2995 12:20:55.222450 ==
2996 12:20:55.225508 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 12:20:55.231908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 12:20:55.231985 ==
2999 12:20:55.232048 RX Vref Scan: 0
3000 12:20:55.232107
3001 12:20:55.235373 RX Vref 0 -> 0, step: 1
3002 12:20:55.235456
3003 12:20:55.239039 RX Delay -21 -> 252, step: 4
3004 12:20:55.241996 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3005 12:20:55.245412 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3006 12:20:55.251901 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3007 12:20:55.255637 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3008 12:20:55.258523 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3009 12:20:55.261956 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3010 12:20:55.265450 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3011 12:20:55.272228 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3012 12:20:55.275957 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3013 12:20:55.278924 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3014 12:20:55.282540 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3015 12:20:55.285627 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3016 12:20:55.289577 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3017 12:20:55.295684 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3018 12:20:55.299436 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3019 12:20:55.302329 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3020 12:20:55.302411 ==
3021 12:20:55.305738 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 12:20:55.308893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 12:20:55.312260 ==
3024 12:20:55.312342 DQS Delay:
3025 12:20:55.312408 DQS0 = 0, DQS1 = 0
3026 12:20:55.315860 DQM Delay:
3027 12:20:55.315942 DQM0 = 119, DQM1 = 108
3028 12:20:55.318918 DQ Delay:
3029 12:20:55.322351 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =114
3030 12:20:55.325722 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3031 12:20:55.329354 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3032 12:20:55.332464 DQ12 =114, DQ13 =110, DQ14 =120, DQ15 =114
3033 12:20:55.332547
3034 12:20:55.332613
3035 12:20:55.339102 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3036 12:20:55.342767 CH0 RK1: MR19=403, MR18=BF2
3037 12:20:55.349310 CH0_RK1: MR19=0x403, MR18=0xBF2, DQSOSC=405, MR23=63, INC=39, DEC=26
3038 12:20:55.352354 [RxdqsGatingPostProcess] freq 1200
3039 12:20:55.355914 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3040 12:20:55.359370 best DQS0 dly(2T, 0.5T) = (0, 11)
3041 12:20:55.362980 best DQS1 dly(2T, 0.5T) = (0, 12)
3042 12:20:55.365873 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3043 12:20:55.369408 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3044 12:20:55.372720 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 12:20:55.375667 best DQS1 dly(2T, 0.5T) = (0, 11)
3046 12:20:55.379291 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 12:20:55.382464 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3048 12:20:55.385845 Pre-setting of DQS Precalculation
3049 12:20:55.389178 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3050 12:20:55.389260 ==
3051 12:20:55.392639 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 12:20:55.399556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 12:20:55.399639 ==
3054 12:20:55.402777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3055 12:20:55.409565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3056 12:20:55.417841 [CA 0] Center 38 (8~68) winsize 61
3057 12:20:55.421110 [CA 1] Center 37 (7~68) winsize 62
3058 12:20:55.424638 [CA 2] Center 35 (5~65) winsize 61
3059 12:20:55.428556 [CA 3] Center 34 (4~65) winsize 62
3060 12:20:55.431236 [CA 4] Center 34 (4~65) winsize 62
3061 12:20:55.434302 [CA 5] Center 33 (3~64) winsize 62
3062 12:20:55.434385
3063 12:20:55.437730 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3064 12:20:55.437817
3065 12:20:55.441232 [CATrainingPosCal] consider 1 rank data
3066 12:20:55.444367 u2DelayCellTimex100 = 270/100 ps
3067 12:20:55.447727 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3068 12:20:55.451418 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3069 12:20:55.457846 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3070 12:20:55.461232 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3071 12:20:55.464807 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3072 12:20:55.467979 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3073 12:20:55.468062
3074 12:20:55.471390 CA PerBit enable=1, Macro0, CA PI delay=33
3075 12:20:55.471473
3076 12:20:55.474546 [CBTSetCACLKResult] CA Dly = 33
3077 12:20:55.474636 CS Dly: 5 (0~36)
3078 12:20:55.474702 ==
3079 12:20:55.477810 Dram Type= 6, Freq= 0, CH_1, rank 1
3080 12:20:55.484565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 12:20:55.484649 ==
3082 12:20:55.488131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3083 12:20:55.494351 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3084 12:20:55.503393 [CA 0] Center 38 (8~69) winsize 62
3085 12:20:55.507022 [CA 1] Center 38 (7~69) winsize 63
3086 12:20:55.510366 [CA 2] Center 35 (5~66) winsize 62
3087 12:20:55.513529 [CA 3] Center 35 (5~65) winsize 61
3088 12:20:55.516729 [CA 4] Center 34 (4~64) winsize 61
3089 12:20:55.520361 [CA 5] Center 34 (4~64) winsize 61
3090 12:20:55.520443
3091 12:20:55.524222 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3092 12:20:55.524305
3093 12:20:55.527264 [CATrainingPosCal] consider 2 rank data
3094 12:20:55.530118 u2DelayCellTimex100 = 270/100 ps
3095 12:20:55.533407 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3096 12:20:55.536907 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3097 12:20:55.543638 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3098 12:20:55.546948 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3099 12:20:55.550331 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3100 12:20:55.553662 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3101 12:20:55.553745
3102 12:20:55.557135 CA PerBit enable=1, Macro0, CA PI delay=34
3103 12:20:55.557217
3104 12:20:55.560264 [CBTSetCACLKResult] CA Dly = 34
3105 12:20:55.560346 CS Dly: 6 (0~39)
3106 12:20:55.560411
3107 12:20:55.563817 ----->DramcWriteLeveling(PI) begin...
3108 12:20:55.563904 ==
3109 12:20:55.566882 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 12:20:55.573586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 12:20:55.573670 ==
3112 12:20:55.576851 Write leveling (Byte 0): 24 => 24
3113 12:20:55.580134 Write leveling (Byte 1): 28 => 28
3114 12:20:55.580243 DramcWriteLeveling(PI) end<-----
3115 12:20:55.583655
3116 12:20:55.583758 ==
3117 12:20:55.586982 Dram Type= 6, Freq= 0, CH_1, rank 0
3118 12:20:55.590218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3119 12:20:55.590319 ==
3120 12:20:55.593472 [Gating] SW mode calibration
3121 12:20:55.600473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3122 12:20:55.603692 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3123 12:20:55.610810 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 12:20:55.613662 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 12:20:55.617461 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 12:20:55.624132 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 12:20:55.627146 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 12:20:55.630342 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3129 12:20:55.637222 0 15 24 | B1->B0 | 2929 2424 | 0 0 | (0 0) (1 0)
3130 12:20:55.640449 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3131 12:20:55.643691 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 12:20:55.650519 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 12:20:55.654203 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 12:20:55.656971 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 12:20:55.660588 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 12:20:55.667235 1 0 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3137 12:20:55.670428 1 0 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3138 12:20:55.673936 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 12:20:55.680445 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 12:20:55.684311 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 12:20:55.687490 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 12:20:55.694075 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 12:20:55.697284 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 12:20:55.700513 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3145 12:20:55.707301 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3146 12:20:55.710419 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:20:55.714038 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:20:55.720765 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:20:55.724016 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:20:55.727408 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:20:55.734292 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:20:55.737278 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:20:55.740742 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 12:20:55.744193 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 12:20:55.750929 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 12:20:55.753969 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 12:20:55.757319 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 12:20:55.763917 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 12:20:55.767446 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 12:20:55.770564 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 12:20:55.777577 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3162 12:20:55.780760 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 12:20:55.783962 Total UI for P1: 0, mck2ui 16
3164 12:20:55.787041 best dqsien dly found for B0: ( 1, 3, 24)
3165 12:20:55.790551 Total UI for P1: 0, mck2ui 16
3166 12:20:55.793728 best dqsien dly found for B1: ( 1, 3, 26)
3167 12:20:55.796982 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3168 12:20:55.800290 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3169 12:20:55.800361
3170 12:20:55.803870 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3171 12:20:55.807023 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3172 12:20:55.810896 [Gating] SW calibration Done
3173 12:20:55.810997 ==
3174 12:20:55.813969 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 12:20:55.817455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 12:20:55.820359 ==
3177 12:20:55.820432 RX Vref Scan: 0
3178 12:20:55.820494
3179 12:20:55.824090 RX Vref 0 -> 0, step: 1
3180 12:20:55.824162
3181 12:20:55.827554 RX Delay -40 -> 252, step: 8
3182 12:20:55.830952 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3183 12:20:55.834059 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3184 12:20:55.837265 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3185 12:20:55.840565 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3186 12:20:55.847164 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3187 12:20:55.850397 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3188 12:20:55.854212 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3189 12:20:55.857048 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3190 12:20:55.860369 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3191 12:20:55.863604 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3192 12:20:55.870398 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3193 12:20:55.873895 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3194 12:20:55.877275 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3195 12:20:55.880281 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3196 12:20:55.887023 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3197 12:20:55.890420 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3198 12:20:55.890521 ==
3199 12:20:55.893661 Dram Type= 6, Freq= 0, CH_1, rank 0
3200 12:20:55.897320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3201 12:20:55.897392 ==
3202 12:20:55.897462 DQS Delay:
3203 12:20:55.900824 DQS0 = 0, DQS1 = 0
3204 12:20:55.900918 DQM Delay:
3205 12:20:55.904066 DQM0 = 119, DQM1 = 113
3206 12:20:55.904134 DQ Delay:
3207 12:20:55.907420 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3208 12:20:55.910860 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3209 12:20:55.914113 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3210 12:20:55.917168 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3211 12:20:55.917263
3212 12:20:55.917354
3213 12:20:55.920651 ==
3214 12:20:55.923829 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 12:20:55.927154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 12:20:55.927225 ==
3217 12:20:55.927293
3218 12:20:55.927352
3219 12:20:55.930504 TX Vref Scan disable
3220 12:20:55.930601 == TX Byte 0 ==
3221 12:20:55.933615 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3222 12:20:55.940577 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3223 12:20:55.940677 == TX Byte 1 ==
3224 12:20:55.943687 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3225 12:20:55.950405 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3226 12:20:55.950504 ==
3227 12:20:55.954901 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 12:20:55.956804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 12:20:55.956900 ==
3230 12:20:55.969632 TX Vref=22, minBit 1, minWin=25, winSum=410
3231 12:20:55.972453 TX Vref=24, minBit 3, minWin=25, winSum=410
3232 12:20:55.975945 TX Vref=26, minBit 8, minWin=25, winSum=412
3233 12:20:55.979137 TX Vref=28, minBit 10, minWin=25, winSum=419
3234 12:20:55.982770 TX Vref=30, minBit 10, minWin=25, winSum=422
3235 12:20:55.986319 TX Vref=32, minBit 9, minWin=25, winSum=420
3236 12:20:55.992699 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 30
3237 12:20:55.992822
3238 12:20:55.995859 Final TX Range 1 Vref 30
3239 12:20:55.995972
3240 12:20:55.996054 ==
3241 12:20:55.999124 Dram Type= 6, Freq= 0, CH_1, rank 0
3242 12:20:56.002297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3243 12:20:56.002383 ==
3244 12:20:56.005882
3245 12:20:56.006003
3246 12:20:56.006099 TX Vref Scan disable
3247 12:20:56.009590 == TX Byte 0 ==
3248 12:20:56.013043 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3249 12:20:56.015981 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3250 12:20:56.019269 == TX Byte 1 ==
3251 12:20:56.022847 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3252 12:20:56.025930 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3253 12:20:56.026040
3254 12:20:56.029276 [DATLAT]
3255 12:20:56.029358 Freq=1200, CH1 RK0
3256 12:20:56.029423
3257 12:20:56.032852 DATLAT Default: 0xd
3258 12:20:56.032958 0, 0xFFFF, sum = 0
3259 12:20:56.036167 1, 0xFFFF, sum = 0
3260 12:20:56.036251 2, 0xFFFF, sum = 0
3261 12:20:56.039357 3, 0xFFFF, sum = 0
3262 12:20:56.039441 4, 0xFFFF, sum = 0
3263 12:20:56.042604 5, 0xFFFF, sum = 0
3264 12:20:56.042689 6, 0xFFFF, sum = 0
3265 12:20:56.045812 7, 0xFFFF, sum = 0
3266 12:20:56.049291 8, 0xFFFF, sum = 0
3267 12:20:56.049403 9, 0xFFFF, sum = 0
3268 12:20:56.052800 10, 0xFFFF, sum = 0
3269 12:20:56.052884 11, 0xFFFF, sum = 0
3270 12:20:56.056320 12, 0x0, sum = 1
3271 12:20:56.056405 13, 0x0, sum = 2
3272 12:20:56.059204 14, 0x0, sum = 3
3273 12:20:56.059289 15, 0x0, sum = 4
3274 12:20:56.059356 best_step = 13
3275 12:20:56.059428
3276 12:20:56.062697 ==
3277 12:20:56.062781 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 12:20:56.069305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 12:20:56.069389 ==
3280 12:20:56.069455 RX Vref Scan: 1
3281 12:20:56.069518
3282 12:20:56.072437 Set Vref Range= 32 -> 127
3283 12:20:56.072561
3284 12:20:56.075930 RX Vref 32 -> 127, step: 1
3285 12:20:56.076013
3286 12:20:56.079078 RX Delay -13 -> 252, step: 4
3287 12:20:56.079162
3288 12:20:56.082741 Set Vref, RX VrefLevel [Byte0]: 32
3289 12:20:56.085800 [Byte1]: 32
3290 12:20:56.085888
3291 12:20:56.089409 Set Vref, RX VrefLevel [Byte0]: 33
3292 12:20:56.092543 [Byte1]: 33
3293 12:20:56.092643
3294 12:20:56.096189 Set Vref, RX VrefLevel [Byte0]: 34
3295 12:20:56.099354 [Byte1]: 34
3296 12:20:56.103354
3297 12:20:56.103452 Set Vref, RX VrefLevel [Byte0]: 35
3298 12:20:56.106919 [Byte1]: 35
3299 12:20:56.111117
3300 12:20:56.111186 Set Vref, RX VrefLevel [Byte0]: 36
3301 12:20:56.114464 [Byte1]: 36
3302 12:20:56.119108
3303 12:20:56.119177 Set Vref, RX VrefLevel [Byte0]: 37
3304 12:20:56.122546 [Byte1]: 37
3305 12:20:56.127547
3306 12:20:56.127654 Set Vref, RX VrefLevel [Byte0]: 38
3307 12:20:56.130250 [Byte1]: 38
3308 12:20:56.134779
3309 12:20:56.134860 Set Vref, RX VrefLevel [Byte0]: 39
3310 12:20:56.138262 [Byte1]: 39
3311 12:20:56.142951
3312 12:20:56.143033 Set Vref, RX VrefLevel [Byte0]: 40
3313 12:20:56.146085 [Byte1]: 40
3314 12:20:56.151026
3315 12:20:56.151114 Set Vref, RX VrefLevel [Byte0]: 41
3316 12:20:56.154226 [Byte1]: 41
3317 12:20:56.158724
3318 12:20:56.158805 Set Vref, RX VrefLevel [Byte0]: 42
3319 12:20:56.161903 [Byte1]: 42
3320 12:20:56.166611
3321 12:20:56.166690 Set Vref, RX VrefLevel [Byte0]: 43
3322 12:20:56.170015 [Byte1]: 43
3323 12:20:56.174463
3324 12:20:56.174571 Set Vref, RX VrefLevel [Byte0]: 44
3325 12:20:56.177829 [Byte1]: 44
3326 12:20:56.182535
3327 12:20:56.182616 Set Vref, RX VrefLevel [Byte0]: 45
3328 12:20:56.185713 [Byte1]: 45
3329 12:20:56.190319
3330 12:20:56.190404 Set Vref, RX VrefLevel [Byte0]: 46
3331 12:20:56.193494 [Byte1]: 46
3332 12:20:56.198291
3333 12:20:56.198398 Set Vref, RX VrefLevel [Byte0]: 47
3334 12:20:56.201213 [Byte1]: 47
3335 12:20:56.206028
3336 12:20:56.206128 Set Vref, RX VrefLevel [Byte0]: 48
3337 12:20:56.209529 [Byte1]: 48
3338 12:20:56.213730
3339 12:20:56.213800 Set Vref, RX VrefLevel [Byte0]: 49
3340 12:20:56.217340 [Byte1]: 49
3341 12:20:56.221757
3342 12:20:56.221826 Set Vref, RX VrefLevel [Byte0]: 50
3343 12:20:56.224842 [Byte1]: 50
3344 12:20:56.230175
3345 12:20:56.230249 Set Vref, RX VrefLevel [Byte0]: 51
3346 12:20:56.233206 [Byte1]: 51
3347 12:20:56.237528
3348 12:20:56.237597 Set Vref, RX VrefLevel [Byte0]: 52
3349 12:20:56.240693 [Byte1]: 52
3350 12:20:56.245277
3351 12:20:56.245348 Set Vref, RX VrefLevel [Byte0]: 53
3352 12:20:56.248427 [Byte1]: 53
3353 12:20:56.253293
3354 12:20:56.253390 Set Vref, RX VrefLevel [Byte0]: 54
3355 12:20:56.256401 [Byte1]: 54
3356 12:20:56.261050
3357 12:20:56.261118 Set Vref, RX VrefLevel [Byte0]: 55
3358 12:20:56.264574 [Byte1]: 55
3359 12:20:56.269300
3360 12:20:56.269373 Set Vref, RX VrefLevel [Byte0]: 56
3361 12:20:56.272708 [Byte1]: 56
3362 12:20:56.276787
3363 12:20:56.276886 Set Vref, RX VrefLevel [Byte0]: 57
3364 12:20:56.280109 [Byte1]: 57
3365 12:20:56.284909
3366 12:20:56.285022 Set Vref, RX VrefLevel [Byte0]: 58
3367 12:20:56.288216 [Byte1]: 58
3368 12:20:56.292787
3369 12:20:56.292886 Set Vref, RX VrefLevel [Byte0]: 59
3370 12:20:56.296147 [Byte1]: 59
3371 12:20:56.300338
3372 12:20:56.300412 Set Vref, RX VrefLevel [Byte0]: 60
3373 12:20:56.303904 [Byte1]: 60
3374 12:20:56.308361
3375 12:20:56.308442 Set Vref, RX VrefLevel [Byte0]: 61
3376 12:20:56.312045 [Byte1]: 61
3377 12:20:56.316539
3378 12:20:56.316620 Set Vref, RX VrefLevel [Byte0]: 62
3379 12:20:56.319637 [Byte1]: 62
3380 12:20:56.324298
3381 12:20:56.324379 Set Vref, RX VrefLevel [Byte0]: 63
3382 12:20:56.327808 [Byte1]: 63
3383 12:20:56.332374
3384 12:20:56.332455 Set Vref, RX VrefLevel [Byte0]: 64
3385 12:20:56.335472 [Byte1]: 64
3386 12:20:56.340105
3387 12:20:56.340186 Set Vref, RX VrefLevel [Byte0]: 65
3388 12:20:56.343377 [Byte1]: 65
3389 12:20:56.348335
3390 12:20:56.348416 Set Vref, RX VrefLevel [Byte0]: 66
3391 12:20:56.351353 [Byte1]: 66
3392 12:20:56.355773
3393 12:20:56.355857 Set Vref, RX VrefLevel [Byte0]: 67
3394 12:20:56.359252 [Byte1]: 67
3395 12:20:56.363708
3396 12:20:56.363788 Final RX Vref Byte 0 = 52 to rank0
3397 12:20:56.366889 Final RX Vref Byte 1 = 53 to rank0
3398 12:20:56.370296 Final RX Vref Byte 0 = 52 to rank1
3399 12:20:56.374114 Final RX Vref Byte 1 = 53 to rank1==
3400 12:20:56.377035 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 12:20:56.380587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 12:20:56.383982 ==
3403 12:20:56.384063 DQS Delay:
3404 12:20:56.384127 DQS0 = 0, DQS1 = 0
3405 12:20:56.387360 DQM Delay:
3406 12:20:56.387440 DQM0 = 119, DQM1 = 112
3407 12:20:56.390634 DQ Delay:
3408 12:20:56.394222 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3409 12:20:56.396913 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =116
3410 12:20:56.400680 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3411 12:20:56.403848 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3412 12:20:56.403955
3413 12:20:56.404053
3414 12:20:56.410555 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3415 12:20:56.413850 CH1 RK0: MR19=404, MR18=215
3416 12:20:56.420281 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3417 12:20:56.420364
3418 12:20:56.423772 ----->DramcWriteLeveling(PI) begin...
3419 12:20:56.423855 ==
3420 12:20:56.426871 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 12:20:56.430785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 12:20:56.430867 ==
3423 12:20:56.433794 Write leveling (Byte 0): 24 => 24
3424 12:20:56.436850 Write leveling (Byte 1): 29 => 29
3425 12:20:56.440392 DramcWriteLeveling(PI) end<-----
3426 12:20:56.440474
3427 12:20:56.440538 ==
3428 12:20:56.443899 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 12:20:56.450447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 12:20:56.450529 ==
3431 12:20:56.450594 [Gating] SW mode calibration
3432 12:20:56.460244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 12:20:56.463652 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 12:20:56.467389 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 12:20:56.473676 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 12:20:56.477134 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 12:20:56.480562 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 12:20:56.487425 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 12:20:56.490770 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 12:20:56.493932 0 15 24 | B1->B0 | 2929 3131 | 0 0 | (0 1) (1 0)
3441 12:20:56.500632 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (1 0) (0 1)
3442 12:20:56.503580 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 12:20:56.507312 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 12:20:56.513724 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 12:20:56.517389 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 12:20:56.520491 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 12:20:56.524121 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3448 12:20:56.530826 1 0 24 | B1->B0 | 3939 2525 | 0 0 | (1 1) (0 0)
3449 12:20:56.534181 1 0 28 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
3450 12:20:56.537477 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 12:20:56.544198 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 12:20:56.547296 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 12:20:56.550733 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 12:20:56.557782 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 12:20:56.560526 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 12:20:56.564232 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3457 12:20:56.570879 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3458 12:20:56.574427 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 12:20:56.577673 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 12:20:56.583947 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 12:20:56.587256 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:20:56.590593 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:20:56.597199 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:20:56.600709 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:20:56.603961 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:20:56.610528 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:20:56.613803 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:20:56.617109 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:20:56.620461 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:20:56.627219 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 12:20:56.631054 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 12:20:56.633979 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3473 12:20:56.640551 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 12:20:56.644077 Total UI for P1: 0, mck2ui 16
3475 12:20:56.646995 best dqsien dly found for B0: ( 1, 3, 24)
3476 12:20:56.650228 Total UI for P1: 0, mck2ui 16
3477 12:20:56.653747 best dqsien dly found for B1: ( 1, 3, 24)
3478 12:20:56.657064 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3479 12:20:56.660847 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3480 12:20:56.661000
3481 12:20:56.663482 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3482 12:20:56.667208 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3483 12:20:56.670347 [Gating] SW calibration Done
3484 12:20:56.670425 ==
3485 12:20:56.673560 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 12:20:56.676896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 12:20:56.676998 ==
3488 12:20:56.680450 RX Vref Scan: 0
3489 12:20:56.680565
3490 12:20:56.680633 RX Vref 0 -> 0, step: 1
3491 12:20:56.683654
3492 12:20:56.683737 RX Delay -40 -> 252, step: 8
3493 12:20:56.690303 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3494 12:20:56.693643 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3495 12:20:56.697167 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3496 12:20:56.700561 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3497 12:20:56.703569 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3498 12:20:56.710066 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3499 12:20:56.713798 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3500 12:20:56.716705 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3501 12:20:56.720422 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3502 12:20:56.723570 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3503 12:20:56.726881 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3504 12:20:56.733462 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3505 12:20:56.736842 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3506 12:20:56.740096 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3507 12:20:56.743262 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3508 12:20:56.750050 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3509 12:20:56.750140 ==
3510 12:20:56.753253 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 12:20:56.756810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 12:20:56.756894 ==
3513 12:20:56.757005 DQS Delay:
3514 12:20:56.760287 DQS0 = 0, DQS1 = 0
3515 12:20:56.760370 DQM Delay:
3516 12:20:56.763336 DQM0 = 120, DQM1 = 113
3517 12:20:56.763419 DQ Delay:
3518 12:20:56.766894 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =123
3519 12:20:56.770006 DQ4 =119, DQ5 =131, DQ6 =127, DQ7 =115
3520 12:20:56.773483 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3521 12:20:56.776603 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3522 12:20:56.776716
3523 12:20:56.776781
3524 12:20:56.776855 ==
3525 12:20:56.779938 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 12:20:56.786804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 12:20:56.786888 ==
3528 12:20:56.786953
3529 12:20:56.787013
3530 12:20:56.787070 TX Vref Scan disable
3531 12:20:56.790313 == TX Byte 0 ==
3532 12:20:56.793793 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3533 12:20:56.800406 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3534 12:20:56.800489 == TX Byte 1 ==
3535 12:20:56.803454 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3536 12:20:56.810130 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3537 12:20:56.810243 ==
3538 12:20:56.814039 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 12:20:56.816724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 12:20:56.816806 ==
3541 12:20:56.828240 TX Vref=22, minBit 1, minWin=25, winSum=419
3542 12:20:56.831334 TX Vref=24, minBit 3, minWin=25, winSum=423
3543 12:20:56.834998 TX Vref=26, minBit 1, minWin=26, winSum=429
3544 12:20:56.838262 TX Vref=28, minBit 1, minWin=26, winSum=427
3545 12:20:56.841629 TX Vref=30, minBit 1, minWin=26, winSum=430
3546 12:20:56.848181 TX Vref=32, minBit 9, minWin=25, winSum=429
3547 12:20:56.851570 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3548 12:20:56.851669
3549 12:20:56.855088 Final TX Range 1 Vref 30
3550 12:20:56.855187
3551 12:20:56.855289 ==
3552 12:20:56.858165 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 12:20:56.861198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 12:20:56.864657 ==
3555 12:20:56.864726
3556 12:20:56.864786
3557 12:20:56.864843 TX Vref Scan disable
3558 12:20:56.868099 == TX Byte 0 ==
3559 12:20:56.871578 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3560 12:20:56.878030 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3561 12:20:56.878116 == TX Byte 1 ==
3562 12:20:56.881435 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3563 12:20:56.884913 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3564 12:20:56.888025
3565 12:20:56.888107 [DATLAT]
3566 12:20:56.888172 Freq=1200, CH1 RK1
3567 12:20:56.888234
3568 12:20:56.891935 DATLAT Default: 0xd
3569 12:20:56.892016 0, 0xFFFF, sum = 0
3570 12:20:56.894586 1, 0xFFFF, sum = 0
3571 12:20:56.894671 2, 0xFFFF, sum = 0
3572 12:20:56.898254 3, 0xFFFF, sum = 0
3573 12:20:56.901165 4, 0xFFFF, sum = 0
3574 12:20:56.901249 5, 0xFFFF, sum = 0
3575 12:20:56.904458 6, 0xFFFF, sum = 0
3576 12:20:56.904557 7, 0xFFFF, sum = 0
3577 12:20:56.908265 8, 0xFFFF, sum = 0
3578 12:20:56.908350 9, 0xFFFF, sum = 0
3579 12:20:56.911465 10, 0xFFFF, sum = 0
3580 12:20:56.911548 11, 0xFFFF, sum = 0
3581 12:20:56.914459 12, 0x0, sum = 1
3582 12:20:56.914544 13, 0x0, sum = 2
3583 12:20:56.917810 14, 0x0, sum = 3
3584 12:20:56.917893 15, 0x0, sum = 4
3585 12:20:56.921151 best_step = 13
3586 12:20:56.921233
3587 12:20:56.921298 ==
3588 12:20:56.924505 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 12:20:56.927815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 12:20:56.927898 ==
3591 12:20:56.927965 RX Vref Scan: 0
3592 12:20:56.928026
3593 12:20:56.931378 RX Vref 0 -> 0, step: 1
3594 12:20:56.931461
3595 12:20:56.934445 RX Delay -13 -> 252, step: 4
3596 12:20:56.937935 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3597 12:20:56.944462 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3598 12:20:56.947801 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3599 12:20:56.951208 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3600 12:20:56.954387 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3601 12:20:56.957617 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3602 12:20:56.964302 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3603 12:20:56.967626 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3604 12:20:56.971365 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3605 12:20:56.974703 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3606 12:20:56.977880 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3607 12:20:56.984273 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3608 12:20:56.987468 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3609 12:20:56.991150 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3610 12:20:56.994254 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3611 12:20:56.997703 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3612 12:20:57.000767 ==
3613 12:20:57.004017 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 12:20:57.007571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 12:20:57.007654 ==
3616 12:20:57.007719 DQS Delay:
3617 12:20:57.011090 DQS0 = 0, DQS1 = 0
3618 12:20:57.011173 DQM Delay:
3619 12:20:57.014092 DQM0 = 119, DQM1 = 113
3620 12:20:57.014188 DQ Delay:
3621 12:20:57.017621 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3622 12:20:57.020862 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3623 12:20:57.024036 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3624 12:20:57.027234 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3625 12:20:57.027317
3626 12:20:57.027383
3627 12:20:57.037410 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
3628 12:20:57.041070 CH1 RK1: MR19=403, MR18=6EA
3629 12:20:57.043987 CH1_RK1: MR19=0x403, MR18=0x6EA, DQSOSC=407, MR23=63, INC=39, DEC=26
3630 12:20:57.047061 [RxdqsGatingPostProcess] freq 1200
3631 12:20:57.053743 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3632 12:20:57.057228 best DQS0 dly(2T, 0.5T) = (0, 11)
3633 12:20:57.060419 best DQS1 dly(2T, 0.5T) = (0, 11)
3634 12:20:57.064134 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3635 12:20:57.067620 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3636 12:20:57.070436 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 12:20:57.074044 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 12:20:57.077131 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 12:20:57.080723 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 12:20:57.080806 Pre-setting of DQS Precalculation
3641 12:20:57.087368 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3642 12:20:57.093599 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3643 12:20:57.100223 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3644 12:20:57.100307
3645 12:20:57.100372
3646 12:20:57.103727 [Calibration Summary] 2400 Mbps
3647 12:20:57.106813 CH 0, Rank 0
3648 12:20:57.106896 SW Impedance : PASS
3649 12:20:57.110254 DUTY Scan : NO K
3650 12:20:57.113699 ZQ Calibration : PASS
3651 12:20:57.113782 Jitter Meter : NO K
3652 12:20:57.117110 CBT Training : PASS
3653 12:20:57.120321 Write leveling : PASS
3654 12:20:57.120404 RX DQS gating : PASS
3655 12:20:57.123914 RX DQ/DQS(RDDQC) : PASS
3656 12:20:57.123997 TX DQ/DQS : PASS
3657 12:20:57.126916 RX DATLAT : PASS
3658 12:20:57.130567 RX DQ/DQS(Engine): PASS
3659 12:20:57.130649 TX OE : NO K
3660 12:20:57.133617 All Pass.
3661 12:20:57.133699
3662 12:20:57.133764 CH 0, Rank 1
3663 12:20:57.137091 SW Impedance : PASS
3664 12:20:57.137174 DUTY Scan : NO K
3665 12:20:57.140180 ZQ Calibration : PASS
3666 12:20:57.143387 Jitter Meter : NO K
3667 12:20:57.143470 CBT Training : PASS
3668 12:20:57.146921 Write leveling : PASS
3669 12:20:57.150681 RX DQS gating : PASS
3670 12:20:57.150764 RX DQ/DQS(RDDQC) : PASS
3671 12:20:57.153513 TX DQ/DQS : PASS
3672 12:20:57.156816 RX DATLAT : PASS
3673 12:20:57.156899 RX DQ/DQS(Engine): PASS
3674 12:20:57.160006 TX OE : NO K
3675 12:20:57.160089 All Pass.
3676 12:20:57.160154
3677 12:20:57.163718 CH 1, Rank 0
3678 12:20:57.163800 SW Impedance : PASS
3679 12:20:57.166901 DUTY Scan : NO K
3680 12:20:57.170171 ZQ Calibration : PASS
3681 12:20:57.170254 Jitter Meter : NO K
3682 12:20:57.173770 CBT Training : PASS
3683 12:20:57.173853 Write leveling : PASS
3684 12:20:57.176764 RX DQS gating : PASS
3685 12:20:57.179955 RX DQ/DQS(RDDQC) : PASS
3686 12:20:57.180038 TX DQ/DQS : PASS
3687 12:20:57.183471 RX DATLAT : PASS
3688 12:20:57.186624 RX DQ/DQS(Engine): PASS
3689 12:20:57.186706 TX OE : NO K
3690 12:20:57.190145 All Pass.
3691 12:20:57.190228
3692 12:20:57.190293 CH 1, Rank 1
3693 12:20:57.193405 SW Impedance : PASS
3694 12:20:57.193488 DUTY Scan : NO K
3695 12:20:57.196577 ZQ Calibration : PASS
3696 12:20:57.200029 Jitter Meter : NO K
3697 12:20:57.200112 CBT Training : PASS
3698 12:20:57.203416 Write leveling : PASS
3699 12:20:57.206391 RX DQS gating : PASS
3700 12:20:57.206473 RX DQ/DQS(RDDQC) : PASS
3701 12:20:57.210090 TX DQ/DQS : PASS
3702 12:20:57.213299 RX DATLAT : PASS
3703 12:20:57.213381 RX DQ/DQS(Engine): PASS
3704 12:20:57.216735 TX OE : NO K
3705 12:20:57.216818 All Pass.
3706 12:20:57.216883
3707 12:20:57.219936 DramC Write-DBI off
3708 12:20:57.223311 PER_BANK_REFRESH: Hybrid Mode
3709 12:20:57.223393 TX_TRACKING: ON
3710 12:20:57.233151 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3711 12:20:57.236283 [FAST_K] Save calibration result to emmc
3712 12:20:57.239818 dramc_set_vcore_voltage set vcore to 650000
3713 12:20:57.242981 Read voltage for 600, 5
3714 12:20:57.243063 Vio18 = 0
3715 12:20:57.243129 Vcore = 650000
3716 12:20:57.246354 Vdram = 0
3717 12:20:57.246436 Vddq = 0
3718 12:20:57.246502 Vmddr = 0
3719 12:20:57.253532 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3720 12:20:57.256321 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3721 12:20:57.259651 MEM_TYPE=3, freq_sel=19
3722 12:20:57.262966 sv_algorithm_assistance_LP4_1600
3723 12:20:57.266173 ============ PULL DRAM RESETB DOWN ============
3724 12:20:57.269976 ========== PULL DRAM RESETB DOWN end =========
3725 12:20:57.276197 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3726 12:20:57.279765 ===================================
3727 12:20:57.279888 LPDDR4 DRAM CONFIGURATION
3728 12:20:57.282961 ===================================
3729 12:20:57.286398 EX_ROW_EN[0] = 0x0
3730 12:20:57.290057 EX_ROW_EN[1] = 0x0
3731 12:20:57.290140 LP4Y_EN = 0x0
3732 12:20:57.292904 WORK_FSP = 0x0
3733 12:20:57.293027 WL = 0x2
3734 12:20:57.296178 RL = 0x2
3735 12:20:57.296282 BL = 0x2
3736 12:20:57.299358 RPST = 0x0
3737 12:20:57.299458 RD_PRE = 0x0
3738 12:20:57.302793 WR_PRE = 0x1
3739 12:20:57.302886 WR_PST = 0x0
3740 12:20:57.306145 DBI_WR = 0x0
3741 12:20:57.306229 DBI_RD = 0x0
3742 12:20:57.309977 OTF = 0x1
3743 12:20:57.312908 ===================================
3744 12:20:57.316320 ===================================
3745 12:20:57.316404 ANA top config
3746 12:20:57.319657 ===================================
3747 12:20:57.322919 DLL_ASYNC_EN = 0
3748 12:20:57.326409 ALL_SLAVE_EN = 1
3749 12:20:57.329952 NEW_RANK_MODE = 1
3750 12:20:57.330037 DLL_IDLE_MODE = 1
3751 12:20:57.333004 LP45_APHY_COMB_EN = 1
3752 12:20:57.336359 TX_ODT_DIS = 1
3753 12:20:57.339596 NEW_8X_MODE = 1
3754 12:20:57.343073 ===================================
3755 12:20:57.346183 ===================================
3756 12:20:57.349606 data_rate = 1200
3757 12:20:57.349690 CKR = 1
3758 12:20:57.352775 DQ_P2S_RATIO = 8
3759 12:20:57.356128 ===================================
3760 12:20:57.359421 CA_P2S_RATIO = 8
3761 12:20:57.363390 DQ_CA_OPEN = 0
3762 12:20:57.366394 DQ_SEMI_OPEN = 0
3763 12:20:57.366507 CA_SEMI_OPEN = 0
3764 12:20:57.369446 CA_FULL_RATE = 0
3765 12:20:57.372818 DQ_CKDIV4_EN = 1
3766 12:20:57.376464 CA_CKDIV4_EN = 1
3767 12:20:57.380105 CA_PREDIV_EN = 0
3768 12:20:57.383456 PH8_DLY = 0
3769 12:20:57.383944 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3770 12:20:57.386692 DQ_AAMCK_DIV = 4
3771 12:20:57.389626 CA_AAMCK_DIV = 4
3772 12:20:57.393507 CA_ADMCK_DIV = 4
3773 12:20:57.396048 DQ_TRACK_CA_EN = 0
3774 12:20:57.399745 CA_PICK = 600
3775 12:20:57.402962 CA_MCKIO = 600
3776 12:20:57.403431 MCKIO_SEMI = 0
3777 12:20:57.406174 PLL_FREQ = 2288
3778 12:20:57.409437 DQ_UI_PI_RATIO = 32
3779 12:20:57.412876 CA_UI_PI_RATIO = 0
3780 12:20:57.416290 ===================================
3781 12:20:57.419577 ===================================
3782 12:20:57.422585 memory_type:LPDDR4
3783 12:20:57.423205 GP_NUM : 10
3784 12:20:57.426433 SRAM_EN : 1
3785 12:20:57.429419 MD32_EN : 0
3786 12:20:57.432737 ===================================
3787 12:20:57.433249 [ANA_INIT] >>>>>>>>>>>>>>
3788 12:20:57.436170 <<<<<< [CONFIGURE PHASE]: ANA_TX
3789 12:20:57.439941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3790 12:20:57.442639 ===================================
3791 12:20:57.446002 data_rate = 1200,PCW = 0X5800
3792 12:20:57.449308 ===================================
3793 12:20:57.452843 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3794 12:20:57.459882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3795 12:20:57.463320 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 12:20:57.469339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3797 12:20:57.472581 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3798 12:20:57.475765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3799 12:20:57.476238 [ANA_INIT] flow start
3800 12:20:57.479088 [ANA_INIT] PLL >>>>>>>>
3801 12:20:57.482711 [ANA_INIT] PLL <<<<<<<<
3802 12:20:57.485752 [ANA_INIT] MIDPI >>>>>>>>
3803 12:20:57.486225 [ANA_INIT] MIDPI <<<<<<<<
3804 12:20:57.489039 [ANA_INIT] DLL >>>>>>>>
3805 12:20:57.489514 [ANA_INIT] flow end
3806 12:20:57.495971 ============ LP4 DIFF to SE enter ============
3807 12:20:57.498977 ============ LP4 DIFF to SE exit ============
3808 12:20:57.502538 [ANA_INIT] <<<<<<<<<<<<<
3809 12:20:57.505625 [Flow] Enable top DCM control >>>>>
3810 12:20:57.509302 [Flow] Enable top DCM control <<<<<
3811 12:20:57.512378 Enable DLL master slave shuffle
3812 12:20:57.515511 ==============================================================
3813 12:20:57.518786 Gating Mode config
3814 12:20:57.522250 ==============================================================
3815 12:20:57.525538 Config description:
3816 12:20:57.535559 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3817 12:20:57.542209 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3818 12:20:57.546037 SELPH_MODE 0: By rank 1: By Phase
3819 12:20:57.552324 ==============================================================
3820 12:20:57.555925 GAT_TRACK_EN = 1
3821 12:20:57.559064 RX_GATING_MODE = 2
3822 12:20:57.562579 RX_GATING_TRACK_MODE = 2
3823 12:20:57.566160 SELPH_MODE = 1
3824 12:20:57.566726 PICG_EARLY_EN = 1
3825 12:20:57.569174 VALID_LAT_VALUE = 1
3826 12:20:57.575618 ==============================================================
3827 12:20:57.579144 Enter into Gating configuration >>>>
3828 12:20:57.582524 Exit from Gating configuration <<<<
3829 12:20:57.585726 Enter into DVFS_PRE_config >>>>>
3830 12:20:57.595853 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3831 12:20:57.599457 Exit from DVFS_PRE_config <<<<<
3832 12:20:57.603317 Enter into PICG configuration >>>>
3833 12:20:57.605762 Exit from PICG configuration <<<<
3834 12:20:57.609194 [RX_INPUT] configuration >>>>>
3835 12:20:57.612510 [RX_INPUT] configuration <<<<<
3836 12:20:57.615612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3837 12:20:57.623173 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3838 12:20:57.628630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 12:20:57.635601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 12:20:57.642505 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 12:20:57.645214 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 12:20:57.652197 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3843 12:20:57.655510 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3844 12:20:57.658993 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3845 12:20:57.662011 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3846 12:20:57.669553 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3847 12:20:57.672359 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 12:20:57.675216 ===================================
3849 12:20:57.679044 LPDDR4 DRAM CONFIGURATION
3850 12:20:57.682051 ===================================
3851 12:20:57.682550 EX_ROW_EN[0] = 0x0
3852 12:20:57.685183 EX_ROW_EN[1] = 0x0
3853 12:20:57.685662 LP4Y_EN = 0x0
3854 12:20:57.688564 WORK_FSP = 0x0
3855 12:20:57.689188 WL = 0x2
3856 12:20:57.691951 RL = 0x2
3857 12:20:57.692429 BL = 0x2
3858 12:20:57.695145 RPST = 0x0
3859 12:20:57.695612 RD_PRE = 0x0
3860 12:20:57.698327 WR_PRE = 0x1
3861 12:20:57.698798 WR_PST = 0x0
3862 12:20:57.702061 DBI_WR = 0x0
3863 12:20:57.705197 DBI_RD = 0x0
3864 12:20:57.705666 OTF = 0x1
3865 12:20:57.708423 ===================================
3866 12:20:57.711680 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3867 12:20:57.715631 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3868 12:20:57.721654 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 12:20:57.725467 ===================================
3870 12:20:57.729113 LPDDR4 DRAM CONFIGURATION
3871 12:20:57.729683 ===================================
3872 12:20:57.732097 EX_ROW_EN[0] = 0x10
3873 12:20:57.735303 EX_ROW_EN[1] = 0x0
3874 12:20:57.735928 LP4Y_EN = 0x0
3875 12:20:57.738722 WORK_FSP = 0x0
3876 12:20:57.739192 WL = 0x2
3877 12:20:57.741830 RL = 0x2
3878 12:20:57.742302 BL = 0x2
3879 12:20:57.745525 RPST = 0x0
3880 12:20:57.746066 RD_PRE = 0x0
3881 12:20:57.748635 WR_PRE = 0x1
3882 12:20:57.749248 WR_PST = 0x0
3883 12:20:57.752408 DBI_WR = 0x0
3884 12:20:57.752879 DBI_RD = 0x0
3885 12:20:57.755182 OTF = 0x1
3886 12:20:57.758502 ===================================
3887 12:20:57.765294 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3888 12:20:57.768710 nWR fixed to 30
3889 12:20:57.771715 [ModeRegInit_LP4] CH0 RK0
3890 12:20:57.772145 [ModeRegInit_LP4] CH0 RK1
3891 12:20:57.775410 [ModeRegInit_LP4] CH1 RK0
3892 12:20:57.778213 [ModeRegInit_LP4] CH1 RK1
3893 12:20:57.778690 match AC timing 17
3894 12:20:57.785122 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3895 12:20:57.788479 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3896 12:20:57.791782 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3897 12:20:57.798426 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3898 12:20:57.801514 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3899 12:20:57.801982 ==
3900 12:20:57.804847 Dram Type= 6, Freq= 0, CH_0, rank 0
3901 12:20:57.808357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3902 12:20:57.808822 ==
3903 12:20:57.815297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3904 12:20:57.821588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3905 12:20:57.825228 [CA 0] Center 36 (5~67) winsize 63
3906 12:20:57.828344 [CA 1] Center 36 (6~67) winsize 62
3907 12:20:57.831638 [CA 2] Center 34 (4~65) winsize 62
3908 12:20:57.834759 [CA 3] Center 34 (3~65) winsize 63
3909 12:20:57.838220 [CA 4] Center 33 (3~64) winsize 62
3910 12:20:57.841261 [CA 5] Center 33 (2~64) winsize 63
3911 12:20:57.841737
3912 12:20:57.844966 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3913 12:20:57.845436
3914 12:20:57.848351 [CATrainingPosCal] consider 1 rank data
3915 12:20:57.851515 u2DelayCellTimex100 = 270/100 ps
3916 12:20:57.854800 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3917 12:20:57.857936 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3918 12:20:57.861265 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3919 12:20:57.864547 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3920 12:20:57.868125 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3921 12:20:57.871441 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3922 12:20:57.874803
3923 12:20:57.877862 CA PerBit enable=1, Macro0, CA PI delay=33
3924 12:20:57.878352
3925 12:20:57.881322 [CBTSetCACLKResult] CA Dly = 33
3926 12:20:57.881786 CS Dly: 5 (0~36)
3927 12:20:57.882156 ==
3928 12:20:57.884493 Dram Type= 6, Freq= 0, CH_0, rank 1
3929 12:20:57.888026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 12:20:57.888636 ==
3931 12:20:57.894576 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 12:20:57.901033 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3933 12:20:57.904535 [CA 0] Center 36 (6~67) winsize 62
3934 12:20:57.907842 [CA 1] Center 36 (6~67) winsize 62
3935 12:20:57.911257 [CA 2] Center 35 (5~66) winsize 62
3936 12:20:57.914496 [CA 3] Center 35 (4~66) winsize 63
3937 12:20:57.917499 [CA 4] Center 34 (4~65) winsize 62
3938 12:20:57.920905 [CA 5] Center 34 (3~65) winsize 63
3939 12:20:57.921582
3940 12:20:57.924552 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3941 12:20:57.925071
3942 12:20:57.927742 [CATrainingPosCal] consider 2 rank data
3943 12:20:57.931004 u2DelayCellTimex100 = 270/100 ps
3944 12:20:57.934107 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3945 12:20:57.937706 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3946 12:20:57.940858 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3947 12:20:57.944482 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 12:20:57.950770 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3949 12:20:57.954134 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 12:20:57.954697
3951 12:20:57.957314 CA PerBit enable=1, Macro0, CA PI delay=33
3952 12:20:57.957782
3953 12:20:57.961440 [CBTSetCACLKResult] CA Dly = 33
3954 12:20:57.962006 CS Dly: 5 (0~37)
3955 12:20:57.962377
3956 12:20:57.964326 ----->DramcWriteLeveling(PI) begin...
3957 12:20:57.964899 ==
3958 12:20:57.967313 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 12:20:57.974144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 12:20:57.974739 ==
3961 12:20:57.977598 Write leveling (Byte 0): 34 => 34
3962 12:20:57.980568 Write leveling (Byte 1): 30 => 30
3963 12:20:57.981059 DramcWriteLeveling(PI) end<-----
3964 12:20:57.981435
3965 12:20:57.983849 ==
3966 12:20:57.987259 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 12:20:57.990473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 12:20:57.991060 ==
3969 12:20:57.993946 [Gating] SW mode calibration
3970 12:20:58.000871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3971 12:20:58.003894 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3972 12:20:58.010819 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 12:20:58.014051 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 12:20:58.017299 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 12:20:58.024141 0 9 12 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)
3976 12:20:58.027585 0 9 16 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
3977 12:20:58.030425 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 12:20:58.036959 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 12:20:58.040596 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 12:20:58.043623 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 12:20:58.050318 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 12:20:58.053757 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
3983 12:20:58.057159 0 10 12 | B1->B0 | 2a29 3b3b | 1 0 | (0 0) (0 0)
3984 12:20:58.063907 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
3985 12:20:58.067065 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 12:20:58.070008 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 12:20:58.077095 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 12:20:58.079893 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 12:20:58.083441 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 12:20:58.090028 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 12:20:58.093581 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3992 12:20:58.096510 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3993 12:20:58.103038 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:20:58.106627 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 12:20:58.110083 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:20:58.113149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:20:58.120077 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:20:58.123551 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:20:58.126535 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:20:58.133025 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:20:58.136532 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:20:58.139971 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:20:58.146661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:20:58.149912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:20:58.153210 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:20:58.159782 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:20:58.163197 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4008 12:20:58.166416 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 12:20:58.169925 Total UI for P1: 0, mck2ui 16
4010 12:20:58.173484 best dqsien dly found for B0: ( 0, 13, 12)
4011 12:20:58.176335 Total UI for P1: 0, mck2ui 16
4012 12:20:58.179243 best dqsien dly found for B1: ( 0, 13, 14)
4013 12:20:58.182951 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4014 12:20:58.190031 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4015 12:20:58.190591
4016 12:20:58.192603 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4017 12:20:58.196301 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4018 12:20:58.199599 [Gating] SW calibration Done
4019 12:20:58.200301 ==
4020 12:20:58.202665 Dram Type= 6, Freq= 0, CH_0, rank 0
4021 12:20:58.205871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 12:20:58.206409 ==
4023 12:20:58.206778 RX Vref Scan: 0
4024 12:20:58.209245
4025 12:20:58.209705 RX Vref 0 -> 0, step: 1
4026 12:20:58.210070
4027 12:20:58.212704 RX Delay -230 -> 252, step: 16
4028 12:20:58.216348 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4029 12:20:58.222918 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4030 12:20:58.226130 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4031 12:20:58.229281 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4032 12:20:58.232516 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4033 12:20:58.235949 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4034 12:20:58.242701 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4035 12:20:58.246304 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4036 12:20:58.249357 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4037 12:20:58.252771 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4038 12:20:58.256466 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4039 12:20:58.262794 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4040 12:20:58.266140 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4041 12:20:58.269584 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4042 12:20:58.273008 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4043 12:20:58.279360 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4044 12:20:58.280021 ==
4045 12:20:58.282978 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 12:20:58.286229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 12:20:58.286858 ==
4048 12:20:58.287243 DQS Delay:
4049 12:20:58.289389 DQS0 = 0, DQS1 = 0
4050 12:20:58.289850 DQM Delay:
4051 12:20:58.293045 DQM0 = 50, DQM1 = 42
4052 12:20:58.293511 DQ Delay:
4053 12:20:58.296147 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4054 12:20:58.299499 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4055 12:20:58.302834 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4056 12:20:58.306280 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4057 12:20:58.306741
4058 12:20:58.307106
4059 12:20:58.307444 ==
4060 12:20:58.309595 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 12:20:58.312661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 12:20:58.313168 ==
4063 12:20:58.316011
4064 12:20:58.316713
4065 12:20:58.317385 TX Vref Scan disable
4066 12:20:58.319068 == TX Byte 0 ==
4067 12:20:58.322420 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4068 12:20:58.326057 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4069 12:20:58.329198 == TX Byte 1 ==
4070 12:20:58.332613 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4071 12:20:58.335656 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4072 12:20:58.339383 ==
4073 12:20:58.342687 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 12:20:58.346206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 12:20:58.346633 ==
4076 12:20:58.346962
4077 12:20:58.347265
4078 12:20:58.348815 TX Vref Scan disable
4079 12:20:58.349434 == TX Byte 0 ==
4080 12:20:58.355592 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4081 12:20:58.358950 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4082 12:20:58.359372 == TX Byte 1 ==
4083 12:20:58.366034 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4084 12:20:58.369043 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4085 12:20:58.369620
4086 12:20:58.370111 [DATLAT]
4087 12:20:58.372650 Freq=600, CH0 RK0
4088 12:20:58.373167
4089 12:20:58.373485 DATLAT Default: 0x9
4090 12:20:58.375812 0, 0xFFFF, sum = 0
4091 12:20:58.376248 1, 0xFFFF, sum = 0
4092 12:20:58.379054 2, 0xFFFF, sum = 0
4093 12:20:58.379622 3, 0xFFFF, sum = 0
4094 12:20:58.382354 4, 0xFFFF, sum = 0
4095 12:20:58.382871 5, 0xFFFF, sum = 0
4096 12:20:58.386201 6, 0xFFFF, sum = 0
4097 12:20:58.386755 7, 0xFFFF, sum = 0
4098 12:20:58.389434 8, 0x0, sum = 1
4099 12:20:58.389952 9, 0x0, sum = 2
4100 12:20:58.392416 10, 0x0, sum = 3
4101 12:20:58.392839 11, 0x0, sum = 4
4102 12:20:58.395678 best_step = 9
4103 12:20:58.396094
4104 12:20:58.396423 ==
4105 12:20:58.399194 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 12:20:58.402477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 12:20:58.402902 ==
4108 12:20:58.405853 RX Vref Scan: 1
4109 12:20:58.406297
4110 12:20:58.406626 RX Vref 0 -> 0, step: 1
4111 12:20:58.406942
4112 12:20:58.409106 RX Delay -179 -> 252, step: 8
4113 12:20:58.409534
4114 12:20:58.412567 Set Vref, RX VrefLevel [Byte0]: 58
4115 12:20:58.416401 [Byte1]: 50
4116 12:20:58.419537
4117 12:20:58.419957 Final RX Vref Byte 0 = 58 to rank0
4118 12:20:58.422841 Final RX Vref Byte 1 = 50 to rank0
4119 12:20:58.426068 Final RX Vref Byte 0 = 58 to rank1
4120 12:20:58.429240 Final RX Vref Byte 1 = 50 to rank1==
4121 12:20:58.432454 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 12:20:58.439216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 12:20:58.439662 ==
4124 12:20:58.440003 DQS Delay:
4125 12:20:58.440310 DQS0 = 0, DQS1 = 0
4126 12:20:58.442685 DQM Delay:
4127 12:20:58.443222 DQM0 = 48, DQM1 = 39
4128 12:20:58.445713 DQ Delay:
4129 12:20:58.449005 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4130 12:20:58.452389 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4131 12:20:58.455757 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =32
4132 12:20:58.459136 DQ12 =48, DQ13 =40, DQ14 =52, DQ15 =48
4133 12:20:58.459557
4134 12:20:58.459889
4135 12:20:58.465949 [DQSOSCAuto] RK0, (LSB)MR18= 0x5954, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4136 12:20:58.468986 CH0 RK0: MR19=808, MR18=5954
4137 12:20:58.476181 CH0_RK0: MR19=0x808, MR18=0x5954, DQSOSC=393, MR23=63, INC=169, DEC=113
4138 12:20:58.476695
4139 12:20:58.479144 ----->DramcWriteLeveling(PI) begin...
4140 12:20:58.479567 ==
4141 12:20:58.482534 Dram Type= 6, Freq= 0, CH_0, rank 1
4142 12:20:58.485758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 12:20:58.486194 ==
4144 12:20:58.489067 Write leveling (Byte 0): 36 => 36
4145 12:20:58.492504 Write leveling (Byte 1): 30 => 30
4146 12:20:58.495828 DramcWriteLeveling(PI) end<-----
4147 12:20:58.496288
4148 12:20:58.496653 ==
4149 12:20:58.499334 Dram Type= 6, Freq= 0, CH_0, rank 1
4150 12:20:58.502389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 12:20:58.502857 ==
4152 12:20:58.505852 [Gating] SW mode calibration
4153 12:20:58.512347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4154 12:20:58.518852 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4155 12:20:58.522859 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 12:20:58.529282 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 12:20:58.532816 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 12:20:58.535968 0 9 12 | B1->B0 | 3232 3333 | 1 1 | (1 1) (0 0)
4159 12:20:58.539454 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4160 12:20:58.545585 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 12:20:58.549035 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 12:20:58.552184 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 12:20:58.558886 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 12:20:58.562268 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 12:20:58.565323 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 12:20:58.571949 0 10 12 | B1->B0 | 2f2f 3131 | 0 0 | (1 1) (1 1)
4167 12:20:58.575325 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4168 12:20:58.578695 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 12:20:58.585294 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 12:20:58.589153 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 12:20:58.591903 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 12:20:58.598926 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 12:20:58.601959 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 12:20:58.605165 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 12:20:58.612020 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:20:58.615396 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:20:58.619281 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:20:58.625270 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 12:20:58.628530 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 12:20:58.632155 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:20:58.638865 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:20:58.642164 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:20:58.645237 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:20:58.651658 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:20:58.655259 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:20:58.658296 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:20:58.665179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:20:58.668825 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:20:58.672122 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:20:58.675269 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4191 12:20:58.681658 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 12:20:58.685579 Total UI for P1: 0, mck2ui 16
4193 12:20:58.688475 best dqsien dly found for B0: ( 0, 13, 12)
4194 12:20:58.692117 Total UI for P1: 0, mck2ui 16
4195 12:20:58.694973 best dqsien dly found for B1: ( 0, 13, 12)
4196 12:20:58.698953 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4197 12:20:58.701637 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4198 12:20:58.702127
4199 12:20:58.705148 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4200 12:20:58.708460 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4201 12:20:58.712274 [Gating] SW calibration Done
4202 12:20:58.712863 ==
4203 12:20:58.715157 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 12:20:58.718672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 12:20:58.719268 ==
4206 12:20:58.721683 RX Vref Scan: 0
4207 12:20:58.722166
4208 12:20:58.724757 RX Vref 0 -> 0, step: 1
4209 12:20:58.725270
4210 12:20:58.725754 RX Delay -230 -> 252, step: 16
4211 12:20:58.731679 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4212 12:20:58.735187 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4213 12:20:58.738180 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4214 12:20:58.741445 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4215 12:20:58.748516 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4216 12:20:58.751492 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4217 12:20:58.754850 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4218 12:20:58.758041 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4219 12:20:58.761415 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4220 12:20:58.768118 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4221 12:20:58.771310 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4222 12:20:58.774756 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4223 12:20:58.777993 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4224 12:20:58.784987 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4225 12:20:58.788038 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4226 12:20:58.791367 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4227 12:20:58.791851 ==
4228 12:20:58.794995 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 12:20:58.798706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 12:20:58.801164 ==
4231 12:20:58.801649 DQS Delay:
4232 12:20:58.802125 DQS0 = 0, DQS1 = 0
4233 12:20:58.804891 DQM Delay:
4234 12:20:58.805422 DQM0 = 47, DQM1 = 42
4235 12:20:58.808085 DQ Delay:
4236 12:20:58.808566 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4237 12:20:58.811096 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4238 12:20:58.814975 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4239 12:20:58.818234 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4240 12:20:58.818669
4241 12:20:58.821377
4242 12:20:58.821819 ==
4243 12:20:58.824598 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 12:20:58.827768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 12:20:58.828221 ==
4246 12:20:58.828657
4247 12:20:58.829162
4248 12:20:58.831177 TX Vref Scan disable
4249 12:20:58.831614 == TX Byte 0 ==
4250 12:20:58.838388 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4251 12:20:58.841421 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4252 12:20:58.841865 == TX Byte 1 ==
4253 12:20:58.848049 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4254 12:20:58.851175 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4255 12:20:58.851646 ==
4256 12:20:58.854576 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 12:20:58.857927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 12:20:58.858369 ==
4259 12:20:58.858805
4260 12:20:58.859215
4261 12:20:58.861140 TX Vref Scan disable
4262 12:20:58.864401 == TX Byte 0 ==
4263 12:20:58.868081 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4264 12:20:58.870923 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4265 12:20:58.874408 == TX Byte 1 ==
4266 12:20:58.877563 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4267 12:20:58.880891 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4268 12:20:58.884430
4269 12:20:58.884854 [DATLAT]
4270 12:20:58.885383 Freq=600, CH0 RK1
4271 12:20:58.885724
4272 12:20:58.887837 DATLAT Default: 0x9
4273 12:20:58.888264 0, 0xFFFF, sum = 0
4274 12:20:58.891303 1, 0xFFFF, sum = 0
4275 12:20:58.891762 2, 0xFFFF, sum = 0
4276 12:20:58.894383 3, 0xFFFF, sum = 0
4277 12:20:58.894817 4, 0xFFFF, sum = 0
4278 12:20:58.897659 5, 0xFFFF, sum = 0
4279 12:20:58.901193 6, 0xFFFF, sum = 0
4280 12:20:58.901629 7, 0xFFFF, sum = 0
4281 12:20:58.901971 8, 0x0, sum = 1
4282 12:20:58.904365 9, 0x0, sum = 2
4283 12:20:58.904798 10, 0x0, sum = 3
4284 12:20:58.907602 11, 0x0, sum = 4
4285 12:20:58.908033 best_step = 9
4286 12:20:58.908368
4287 12:20:58.908680 ==
4288 12:20:58.911160 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 12:20:58.917683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 12:20:58.918113 ==
4291 12:20:58.918458 RX Vref Scan: 0
4292 12:20:58.918882
4293 12:20:58.920993 RX Vref 0 -> 0, step: 1
4294 12:20:58.921407
4295 12:20:58.924292 RX Delay -179 -> 252, step: 8
4296 12:20:58.927502 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4297 12:20:58.934592 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4298 12:20:58.937639 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4299 12:20:58.940903 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4300 12:20:58.944106 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4301 12:20:58.947569 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4302 12:20:58.950788 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4303 12:20:58.957774 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4304 12:20:58.961141 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4305 12:20:58.964441 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4306 12:20:58.967559 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4307 12:20:58.974311 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4308 12:20:58.977709 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4309 12:20:58.980908 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4310 12:20:58.984087 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4311 12:20:58.987671 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4312 12:20:58.990685 ==
4313 12:20:58.994013 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 12:20:58.997335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 12:20:58.997758 ==
4316 12:20:58.998088 DQS Delay:
4317 12:20:59.000776 DQS0 = 0, DQS1 = 0
4318 12:20:59.001257 DQM Delay:
4319 12:20:59.004379 DQM0 = 48, DQM1 = 40
4320 12:20:59.004795 DQ Delay:
4321 12:20:59.007457 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4322 12:20:59.010636 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4323 12:20:59.014046 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4324 12:20:59.017432 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4325 12:20:59.018056
4326 12:20:59.018496
4327 12:20:59.024097 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e2c, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
4328 12:20:59.027195 CH0 RK1: MR19=808, MR18=5E2C
4329 12:20:59.034245 CH0_RK1: MR19=0x808, MR18=0x5E2C, DQSOSC=392, MR23=63, INC=170, DEC=113
4330 12:20:59.037366 [RxdqsGatingPostProcess] freq 600
4331 12:20:59.044061 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4332 12:20:59.044489 Pre-setting of DQS Precalculation
4333 12:20:59.050661 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4334 12:20:59.051138 ==
4335 12:20:59.053770 Dram Type= 6, Freq= 0, CH_1, rank 0
4336 12:20:59.057044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 12:20:59.057431 ==
4338 12:20:59.064005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4339 12:20:59.070723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4340 12:20:59.073931 [CA 0] Center 35 (5~66) winsize 62
4341 12:20:59.077478 [CA 1] Center 35 (5~66) winsize 62
4342 12:20:59.080339 [CA 2] Center 34 (3~65) winsize 63
4343 12:20:59.083760 [CA 3] Center 33 (3~64) winsize 62
4344 12:20:59.086892 [CA 4] Center 34 (3~65) winsize 63
4345 12:20:59.090214 [CA 5] Center 33 (3~64) winsize 62
4346 12:20:59.090629
4347 12:20:59.093749 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4348 12:20:59.094163
4349 12:20:59.097075 [CATrainingPosCal] consider 1 rank data
4350 12:20:59.100710 u2DelayCellTimex100 = 270/100 ps
4351 12:20:59.104357 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4352 12:20:59.107326 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4353 12:20:59.111028 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4354 12:20:59.113755 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4355 12:20:59.117181 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4356 12:20:59.120505 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4357 12:20:59.120983
4358 12:20:59.127241 CA PerBit enable=1, Macro0, CA PI delay=33
4359 12:20:59.127653
4360 12:20:59.127979 [CBTSetCACLKResult] CA Dly = 33
4361 12:20:59.131286 CS Dly: 4 (0~35)
4362 12:20:59.131798 ==
4363 12:20:59.134354 Dram Type= 6, Freq= 0, CH_1, rank 1
4364 12:20:59.137219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 12:20:59.137776 ==
4366 12:20:59.144312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 12:20:59.150739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4368 12:20:59.153735 [CA 0] Center 35 (5~66) winsize 62
4369 12:20:59.157101 [CA 1] Center 35 (5~66) winsize 62
4370 12:20:59.160578 [CA 2] Center 34 (4~65) winsize 62
4371 12:20:59.163734 [CA 3] Center 34 (4~65) winsize 62
4372 12:20:59.167206 [CA 4] Center 34 (3~65) winsize 63
4373 12:20:59.170315 [CA 5] Center 33 (3~64) winsize 62
4374 12:20:59.170880
4375 12:20:59.173735 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4376 12:20:59.174193
4377 12:20:59.176921 [CATrainingPosCal] consider 2 rank data
4378 12:20:59.180438 u2DelayCellTimex100 = 270/100 ps
4379 12:20:59.183615 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 12:20:59.186756 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4381 12:20:59.190123 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 12:20:59.193858 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4383 12:20:59.197139 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4384 12:20:59.200757 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 12:20:59.203427
4386 12:20:59.206717 CA PerBit enable=1, Macro0, CA PI delay=33
4387 12:20:59.207236
4388 12:20:59.210027 [CBTSetCACLKResult] CA Dly = 33
4389 12:20:59.210579 CS Dly: 5 (0~37)
4390 12:20:59.211171
4391 12:20:59.213462 ----->DramcWriteLeveling(PI) begin...
4392 12:20:59.213926 ==
4393 12:20:59.216795 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 12:20:59.220074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 12:20:59.223861 ==
4396 12:20:59.224454 Write leveling (Byte 0): 30 => 30
4397 12:20:59.227732 Write leveling (Byte 1): 30 => 30
4398 12:20:59.230387 DramcWriteLeveling(PI) end<-----
4399 12:20:59.230839
4400 12:20:59.231191 ==
4401 12:20:59.233727 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 12:20:59.240173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 12:20:59.240741 ==
4404 12:20:59.241230 [Gating] SW mode calibration
4405 12:20:59.249915 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4406 12:20:59.253699 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4407 12:20:59.256714 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 12:20:59.263310 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 12:20:59.266575 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 12:20:59.270088 0 9 12 | B1->B0 | 2b2b 2b2b | 1 0 | (1 0) (0 0)
4411 12:20:59.277159 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 12:20:59.279979 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 12:20:59.283316 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 12:20:59.289841 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 12:20:59.293677 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 12:20:59.296813 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 12:20:59.303422 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4418 12:20:59.306457 0 10 12 | B1->B0 | 3a3a 3b3b | 0 0 | (0 0) (0 0)
4419 12:20:59.309879 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 12:20:59.316628 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 12:20:59.319645 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 12:20:59.323032 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 12:20:59.329547 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 12:20:59.333261 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 12:20:59.336845 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4426 12:20:59.342854 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4427 12:20:59.346435 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:20:59.349490 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:20:59.356283 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:20:59.359335 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:20:59.363139 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:20:59.369320 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:20:59.372617 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:20:59.376135 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:20:59.382569 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:20:59.385838 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:20:59.389016 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:20:59.395984 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:20:59.399201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:20:59.402296 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:20:59.409038 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 12:20:59.412244 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4443 12:20:59.415484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 12:20:59.418931 Total UI for P1: 0, mck2ui 16
4445 12:20:59.422193 best dqsien dly found for B0: ( 0, 13, 12)
4446 12:20:59.425849 Total UI for P1: 0, mck2ui 16
4447 12:20:59.429335 best dqsien dly found for B1: ( 0, 13, 12)
4448 12:20:59.432342 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4449 12:20:59.435746 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4450 12:20:59.436302
4451 12:20:59.442208 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4452 12:20:59.445416 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4453 12:20:59.445862 [Gating] SW calibration Done
4454 12:20:59.449051 ==
4455 12:20:59.449490 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 12:20:59.455297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 12:20:59.455725 ==
4458 12:20:59.456062 RX Vref Scan: 0
4459 12:20:59.456377
4460 12:20:59.458862 RX Vref 0 -> 0, step: 1
4461 12:20:59.459286
4462 12:20:59.461967 RX Delay -230 -> 252, step: 16
4463 12:20:59.465667 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4464 12:20:59.468490 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4465 12:20:59.475663 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4466 12:20:59.478640 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4467 12:20:59.482418 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4468 12:20:59.485419 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4469 12:20:59.488688 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4470 12:20:59.495468 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4471 12:20:59.498827 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4472 12:20:59.501934 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4473 12:20:59.505183 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4474 12:20:59.511891 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4475 12:20:59.515546 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4476 12:20:59.518697 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4477 12:20:59.522422 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4478 12:20:59.528687 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4479 12:20:59.529156 ==
4480 12:20:59.531641 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 12:20:59.535092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 12:20:59.535520 ==
4483 12:20:59.535855 DQS Delay:
4484 12:20:59.538322 DQS0 = 0, DQS1 = 0
4485 12:20:59.538767 DQM Delay:
4486 12:20:59.542244 DQM0 = 53, DQM1 = 45
4487 12:20:59.542769 DQ Delay:
4488 12:20:59.545193 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4489 12:20:59.548291 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4490 12:20:59.551573 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4491 12:20:59.555018 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4492 12:20:59.555440
4493 12:20:59.555777
4494 12:20:59.556100 ==
4495 12:20:59.558476 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 12:20:59.561915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 12:20:59.562344 ==
4498 12:20:59.562678
4499 12:20:59.562987
4500 12:20:59.565031 TX Vref Scan disable
4501 12:20:59.568704 == TX Byte 0 ==
4502 12:20:59.571646 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4503 12:20:59.575175 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4504 12:20:59.578170 == TX Byte 1 ==
4505 12:20:59.581494 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 12:20:59.585059 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 12:20:59.585559 ==
4508 12:20:59.588447 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 12:20:59.594713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 12:20:59.595137 ==
4511 12:20:59.595471
4512 12:20:59.595780
4513 12:20:59.596076 TX Vref Scan disable
4514 12:20:59.599622 == TX Byte 0 ==
4515 12:20:59.602147 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4516 12:20:59.609152 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4517 12:20:59.609656 == TX Byte 1 ==
4518 12:20:59.612398 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 12:20:59.619398 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 12:20:59.619930
4521 12:20:59.620276 [DATLAT]
4522 12:20:59.620597 Freq=600, CH1 RK0
4523 12:20:59.620907
4524 12:20:59.622142 DATLAT Default: 0x9
4525 12:20:59.622581 0, 0xFFFF, sum = 0
4526 12:20:59.625629 1, 0xFFFF, sum = 0
4527 12:20:59.626158 2, 0xFFFF, sum = 0
4528 12:20:59.629219 3, 0xFFFF, sum = 0
4529 12:20:59.629651 4, 0xFFFF, sum = 0
4530 12:20:59.632031 5, 0xFFFF, sum = 0
4531 12:20:59.635534 6, 0xFFFF, sum = 0
4532 12:20:59.635968 7, 0xFFFF, sum = 0
4533 12:20:59.638827 8, 0x0, sum = 1
4534 12:20:59.639260 9, 0x0, sum = 2
4535 12:20:59.639605 10, 0x0, sum = 3
4536 12:20:59.642062 11, 0x0, sum = 4
4537 12:20:59.642491 best_step = 9
4538 12:20:59.642826
4539 12:20:59.643136 ==
4540 12:20:59.645565 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 12:20:59.652035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 12:20:59.652467 ==
4543 12:20:59.652806 RX Vref Scan: 1
4544 12:20:59.653188
4545 12:20:59.655475 RX Vref 0 -> 0, step: 1
4546 12:20:59.655894
4547 12:20:59.659206 RX Delay -163 -> 252, step: 8
4548 12:20:59.659747
4549 12:20:59.662173 Set Vref, RX VrefLevel [Byte0]: 52
4550 12:20:59.665555 [Byte1]: 53
4551 12:20:59.665982
4552 12:20:59.668907 Final RX Vref Byte 0 = 52 to rank0
4553 12:20:59.672116 Final RX Vref Byte 1 = 53 to rank0
4554 12:20:59.675334 Final RX Vref Byte 0 = 52 to rank1
4555 12:20:59.678542 Final RX Vref Byte 1 = 53 to rank1==
4556 12:20:59.682100 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 12:20:59.685132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 12:20:59.685561 ==
4559 12:20:59.688749 DQS Delay:
4560 12:20:59.689234 DQS0 = 0, DQS1 = 0
4561 12:20:59.691832 DQM Delay:
4562 12:20:59.692256 DQM0 = 49, DQM1 = 41
4563 12:20:59.692636 DQ Delay:
4564 12:20:59.694889 DQ0 =56, DQ1 =48, DQ2 =36, DQ3 =44
4565 12:20:59.698496 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4566 12:20:59.701870 DQ8 =28, DQ9 =28, DQ10 =48, DQ11 =32
4567 12:20:59.705701 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4568 12:20:59.706217
4569 12:20:59.706550
4570 12:20:59.715127 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a71, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4571 12:20:59.718377 CH1 RK0: MR19=808, MR18=4A71
4572 12:20:59.724888 CH1_RK0: MR19=0x808, MR18=0x4A71, DQSOSC=388, MR23=63, INC=174, DEC=116
4573 12:20:59.725421
4574 12:20:59.728312 ----->DramcWriteLeveling(PI) begin...
4575 12:20:59.728743 ==
4576 12:20:59.731412 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 12:20:59.734727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 12:20:59.735157 ==
4579 12:20:59.738115 Write leveling (Byte 0): 28 => 28
4580 12:20:59.741319 Write leveling (Byte 1): 29 => 29
4581 12:20:59.744877 DramcWriteLeveling(PI) end<-----
4582 12:20:59.745487
4583 12:20:59.745830 ==
4584 12:20:59.748457 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 12:20:59.751198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 12:20:59.751623 ==
4587 12:20:59.755068 [Gating] SW mode calibration
4588 12:20:59.761218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4589 12:20:59.767735 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4590 12:20:59.771446 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 12:20:59.774423 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 12:20:59.781268 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 12:20:59.784745 0 9 12 | B1->B0 | 2d2d 3030 | 0 0 | (1 1) (0 0)
4594 12:20:59.788039 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 12:20:59.794605 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 12:20:59.797942 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 12:20:59.801248 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 12:20:59.808063 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 12:20:59.811147 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 12:20:59.814331 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4601 12:20:59.820996 0 10 12 | B1->B0 | 3838 2525 | 0 1 | (0 0) (0 0)
4602 12:20:59.824218 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4603 12:20:59.827895 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 12:20:59.834306 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 12:20:59.837772 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 12:20:59.841015 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 12:20:59.844419 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 12:20:59.850972 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4609 12:20:59.854213 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4610 12:20:59.857623 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:20:59.864115 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:20:59.867421 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:20:59.870837 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:20:59.877526 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 12:20:59.881034 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:20:59.884587 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:20:59.890873 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:20:59.894329 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:20:59.897312 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:20:59.903913 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:20:59.907526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:20:59.911269 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:20:59.917440 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:20:59.920610 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4625 12:20:59.923942 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4626 12:20:59.927647 Total UI for P1: 0, mck2ui 16
4627 12:20:59.930886 best dqsien dly found for B0: ( 0, 13, 10)
4628 12:20:59.937098 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 12:20:59.937522 Total UI for P1: 0, mck2ui 16
4630 12:20:59.944166 best dqsien dly found for B1: ( 0, 13, 10)
4631 12:20:59.947370 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4632 12:20:59.950536 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4633 12:20:59.951005
4634 12:20:59.953962 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4635 12:20:59.957400 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4636 12:20:59.960725 [Gating] SW calibration Done
4637 12:20:59.961191 ==
4638 12:20:59.964188 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 12:20:59.967348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 12:20:59.967774 ==
4641 12:20:59.970544 RX Vref Scan: 0
4642 12:20:59.970968
4643 12:20:59.971304 RX Vref 0 -> 0, step: 1
4644 12:20:59.971619
4645 12:20:59.974192 RX Delay -230 -> 252, step: 16
4646 12:20:59.977427 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4647 12:20:59.984219 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4648 12:20:59.987638 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4649 12:20:59.990688 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4650 12:20:59.994127 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4651 12:20:59.997443 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4652 12:21:00.004325 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4653 12:21:00.007752 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4654 12:21:00.010895 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4655 12:21:00.014666 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4656 12:21:00.020567 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4657 12:21:00.024117 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4658 12:21:00.027656 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4659 12:21:00.031096 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4660 12:21:00.037172 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4661 12:21:00.040653 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4662 12:21:00.041114 ==
4663 12:21:00.043963 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 12:21:00.047085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 12:21:00.047517 ==
4666 12:21:00.050778 DQS Delay:
4667 12:21:00.051215 DQS0 = 0, DQS1 = 0
4668 12:21:00.051573 DQM Delay:
4669 12:21:00.053854 DQM0 = 51, DQM1 = 47
4670 12:21:00.054280 DQ Delay:
4671 12:21:00.057595 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4672 12:21:00.060534 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4673 12:21:00.064130 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4674 12:21:00.067277 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4675 12:21:00.067703
4676 12:21:00.068037
4677 12:21:00.068345 ==
4678 12:21:00.070304 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 12:21:00.074013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 12:21:00.077158 ==
4681 12:21:00.077582
4682 12:21:00.077917
4683 12:21:00.078228 TX Vref Scan disable
4684 12:21:00.080174 == TX Byte 0 ==
4685 12:21:00.083859 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4686 12:21:00.090864 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4687 12:21:00.091294 == TX Byte 1 ==
4688 12:21:00.093613 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4689 12:21:00.100369 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4690 12:21:00.100797 ==
4691 12:21:00.103975 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 12:21:00.107448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 12:21:00.107983 ==
4694 12:21:00.108326
4695 12:21:00.108641
4696 12:21:00.110311 TX Vref Scan disable
4697 12:21:00.110738 == TX Byte 0 ==
4698 12:21:00.117028 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4699 12:21:00.120805 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4700 12:21:00.121359 == TX Byte 1 ==
4701 12:21:00.127326 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4702 12:21:00.130687 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4703 12:21:00.131209
4704 12:21:00.131549 [DATLAT]
4705 12:21:00.134390 Freq=600, CH1 RK1
4706 12:21:00.134914
4707 12:21:00.135249 DATLAT Default: 0x9
4708 12:21:00.137177 0, 0xFFFF, sum = 0
4709 12:21:00.137736 1, 0xFFFF, sum = 0
4710 12:21:00.140501 2, 0xFFFF, sum = 0
4711 12:21:00.141059 3, 0xFFFF, sum = 0
4712 12:21:00.144034 4, 0xFFFF, sum = 0
4713 12:21:00.144564 5, 0xFFFF, sum = 0
4714 12:21:00.147559 6, 0xFFFF, sum = 0
4715 12:21:00.150404 7, 0xFFFF, sum = 0
4716 12:21:00.150839 8, 0x0, sum = 1
4717 12:21:00.151199 9, 0x0, sum = 2
4718 12:21:00.153847 10, 0x0, sum = 3
4719 12:21:00.154361 11, 0x0, sum = 4
4720 12:21:00.157384 best_step = 9
4721 12:21:00.157847
4722 12:21:00.158186 ==
4723 12:21:00.160594 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 12:21:00.163795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 12:21:00.164219 ==
4726 12:21:00.166963 RX Vref Scan: 0
4727 12:21:00.167384
4728 12:21:00.167715 RX Vref 0 -> 0, step: 1
4729 12:21:00.168023
4730 12:21:00.170408 RX Delay -163 -> 252, step: 8
4731 12:21:00.177509 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4732 12:21:00.180608 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4733 12:21:00.184019 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4734 12:21:00.187723 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4735 12:21:00.193671 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4736 12:21:00.197180 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4737 12:21:00.200216 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4738 12:21:00.203678 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4739 12:21:00.206968 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4740 12:21:00.213554 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4741 12:21:00.216779 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4742 12:21:00.220429 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4743 12:21:00.224005 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4744 12:21:00.227327 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4745 12:21:00.233745 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4746 12:21:00.237184 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4747 12:21:00.237742 ==
4748 12:21:00.240330 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 12:21:00.243906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 12:21:00.244332 ==
4751 12:21:00.246826 DQS Delay:
4752 12:21:00.247349 DQS0 = 0, DQS1 = 0
4753 12:21:00.247683 DQM Delay:
4754 12:21:00.250123 DQM0 = 50, DQM1 = 44
4755 12:21:00.250629 DQ Delay:
4756 12:21:00.253407 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =48
4757 12:21:00.256854 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4758 12:21:00.260190 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4759 12:21:00.263124 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4760 12:21:00.263571
4761 12:21:00.263963
4762 12:21:00.273306 [DQSOSCAuto] RK1, (LSB)MR18= 0x5319, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4763 12:21:00.276398 CH1 RK1: MR19=808, MR18=5319
4764 12:21:00.279822 CH1_RK1: MR19=0x808, MR18=0x5319, DQSOSC=394, MR23=63, INC=168, DEC=112
4765 12:21:00.283619 [RxdqsGatingPostProcess] freq 600
4766 12:21:00.290039 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4767 12:21:00.293161 Pre-setting of DQS Precalculation
4768 12:21:00.296490 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4769 12:21:00.306372 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4770 12:21:00.313418 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4771 12:21:00.313842
4772 12:21:00.314196
4773 12:21:00.316444 [Calibration Summary] 1200 Mbps
4774 12:21:00.316896 CH 0, Rank 0
4775 12:21:00.319740 SW Impedance : PASS
4776 12:21:00.320159 DUTY Scan : NO K
4777 12:21:00.323228 ZQ Calibration : PASS
4778 12:21:00.326342 Jitter Meter : NO K
4779 12:21:00.326758 CBT Training : PASS
4780 12:21:00.329715 Write leveling : PASS
4781 12:21:00.333309 RX DQS gating : PASS
4782 12:21:00.333752 RX DQ/DQS(RDDQC) : PASS
4783 12:21:00.336432 TX DQ/DQS : PASS
4784 12:21:00.339684 RX DATLAT : PASS
4785 12:21:00.340107 RX DQ/DQS(Engine): PASS
4786 12:21:00.343102 TX OE : NO K
4787 12:21:00.343631 All Pass.
4788 12:21:00.343964
4789 12:21:00.346272 CH 0, Rank 1
4790 12:21:00.346791 SW Impedance : PASS
4791 12:21:00.349871 DUTY Scan : NO K
4792 12:21:00.350395 ZQ Calibration : PASS
4793 12:21:00.353207 Jitter Meter : NO K
4794 12:21:00.356174 CBT Training : PASS
4795 12:21:00.356725 Write leveling : PASS
4796 12:21:00.359372 RX DQS gating : PASS
4797 12:21:00.362808 RX DQ/DQS(RDDQC) : PASS
4798 12:21:00.363256 TX DQ/DQS : PASS
4799 12:21:00.366309 RX DATLAT : PASS
4800 12:21:00.369844 RX DQ/DQS(Engine): PASS
4801 12:21:00.370272 TX OE : NO K
4802 12:21:00.372765 All Pass.
4803 12:21:00.373259
4804 12:21:00.373606 CH 1, Rank 0
4805 12:21:00.376183 SW Impedance : PASS
4806 12:21:00.376651 DUTY Scan : NO K
4807 12:21:00.379880 ZQ Calibration : PASS
4808 12:21:00.382653 Jitter Meter : NO K
4809 12:21:00.383082 CBT Training : PASS
4810 12:21:00.386608 Write leveling : PASS
4811 12:21:00.389691 RX DQS gating : PASS
4812 12:21:00.390117 RX DQ/DQS(RDDQC) : PASS
4813 12:21:00.392657 TX DQ/DQS : PASS
4814 12:21:00.393108 RX DATLAT : PASS
4815 12:21:00.396062 RX DQ/DQS(Engine): PASS
4816 12:21:00.399415 TX OE : NO K
4817 12:21:00.399835 All Pass.
4818 12:21:00.400164
4819 12:21:00.400465 CH 1, Rank 1
4820 12:21:00.402950 SW Impedance : PASS
4821 12:21:00.406155 DUTY Scan : NO K
4822 12:21:00.406686 ZQ Calibration : PASS
4823 12:21:00.409482 Jitter Meter : NO K
4824 12:21:00.412682 CBT Training : PASS
4825 12:21:00.413196 Write leveling : PASS
4826 12:21:00.415756 RX DQS gating : PASS
4827 12:21:00.419545 RX DQ/DQS(RDDQC) : PASS
4828 12:21:00.419987 TX DQ/DQS : PASS
4829 12:21:00.422756 RX DATLAT : PASS
4830 12:21:00.425842 RX DQ/DQS(Engine): PASS
4831 12:21:00.426261 TX OE : NO K
4832 12:21:00.429159 All Pass.
4833 12:21:00.429574
4834 12:21:00.429903 DramC Write-DBI off
4835 12:21:00.432772 PER_BANK_REFRESH: Hybrid Mode
4836 12:21:00.433228 TX_TRACKING: ON
4837 12:21:00.443064 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4838 12:21:00.446267 [FAST_K] Save calibration result to emmc
4839 12:21:00.449022 dramc_set_vcore_voltage set vcore to 662500
4840 12:21:00.452453 Read voltage for 933, 3
4841 12:21:00.452872 Vio18 = 0
4842 12:21:00.455791 Vcore = 662500
4843 12:21:00.456238 Vdram = 0
4844 12:21:00.456571 Vddq = 0
4845 12:21:00.458810 Vmddr = 0
4846 12:21:00.462409 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4847 12:21:00.468957 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4848 12:21:00.469436 MEM_TYPE=3, freq_sel=17
4849 12:21:00.472256 sv_algorithm_assistance_LP4_1600
4850 12:21:00.475778 ============ PULL DRAM RESETB DOWN ============
4851 12:21:00.482061 ========== PULL DRAM RESETB DOWN end =========
4852 12:21:00.485571 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 12:21:00.489417 ===================================
4854 12:21:00.492412 LPDDR4 DRAM CONFIGURATION
4855 12:21:00.495950 ===================================
4856 12:21:00.496380 EX_ROW_EN[0] = 0x0
4857 12:21:00.498702 EX_ROW_EN[1] = 0x0
4858 12:21:00.502462 LP4Y_EN = 0x0
4859 12:21:00.503138 WORK_FSP = 0x0
4860 12:21:00.505466 WL = 0x3
4861 12:21:00.505895 RL = 0x3
4862 12:21:00.508780 BL = 0x2
4863 12:21:00.509240 RPST = 0x0
4864 12:21:00.511895 RD_PRE = 0x0
4865 12:21:00.512323 WR_PRE = 0x1
4866 12:21:00.515225 WR_PST = 0x0
4867 12:21:00.515866 DBI_WR = 0x0
4868 12:21:00.518404 DBI_RD = 0x0
4869 12:21:00.518989 OTF = 0x1
4870 12:21:00.521891 ===================================
4871 12:21:00.525553 ===================================
4872 12:21:00.528690 ANA top config
4873 12:21:00.532050 ===================================
4874 12:21:00.532483 DLL_ASYNC_EN = 0
4875 12:21:00.535316 ALL_SLAVE_EN = 1
4876 12:21:00.538884 NEW_RANK_MODE = 1
4877 12:21:00.541911 DLL_IDLE_MODE = 1
4878 12:21:00.545338 LP45_APHY_COMB_EN = 1
4879 12:21:00.545823 TX_ODT_DIS = 1
4880 12:21:00.548620 NEW_8X_MODE = 1
4881 12:21:00.551607 ===================================
4882 12:21:00.555019 ===================================
4883 12:21:00.558519 data_rate = 1866
4884 12:21:00.561851 CKR = 1
4885 12:21:00.565685 DQ_P2S_RATIO = 8
4886 12:21:00.568558 ===================================
4887 12:21:00.571640 CA_P2S_RATIO = 8
4888 12:21:00.572165 DQ_CA_OPEN = 0
4889 12:21:00.574882 DQ_SEMI_OPEN = 0
4890 12:21:00.578278 CA_SEMI_OPEN = 0
4891 12:21:00.581958 CA_FULL_RATE = 0
4892 12:21:00.584706 DQ_CKDIV4_EN = 1
4893 12:21:00.585228 CA_CKDIV4_EN = 1
4894 12:21:00.588161 CA_PREDIV_EN = 0
4895 12:21:00.591322 PH8_DLY = 0
4896 12:21:00.595103 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4897 12:21:00.598065 DQ_AAMCK_DIV = 4
4898 12:21:00.601489 CA_AAMCK_DIV = 4
4899 12:21:00.601910 CA_ADMCK_DIV = 4
4900 12:21:00.604662 DQ_TRACK_CA_EN = 0
4901 12:21:00.607998 CA_PICK = 933
4902 12:21:00.611323 CA_MCKIO = 933
4903 12:21:00.614975 MCKIO_SEMI = 0
4904 12:21:00.618237 PLL_FREQ = 3732
4905 12:21:00.621500 DQ_UI_PI_RATIO = 32
4906 12:21:00.625017 CA_UI_PI_RATIO = 0
4907 12:21:00.625486 ===================================
4908 12:21:00.627991 ===================================
4909 12:21:00.631668 memory_type:LPDDR4
4910 12:21:00.635019 GP_NUM : 10
4911 12:21:00.635580 SRAM_EN : 1
4912 12:21:00.637927 MD32_EN : 0
4913 12:21:00.641418 ===================================
4914 12:21:00.645105 [ANA_INIT] >>>>>>>>>>>>>>
4915 12:21:00.648312 <<<<<< [CONFIGURE PHASE]: ANA_TX
4916 12:21:00.651480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4917 12:21:00.654444 ===================================
4918 12:21:00.654913 data_rate = 1866,PCW = 0X8f00
4919 12:21:00.658249 ===================================
4920 12:21:00.661470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4921 12:21:00.668144 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 12:21:00.675087 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 12:21:00.677795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4924 12:21:00.681499 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4925 12:21:00.684652 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4926 12:21:00.687855 [ANA_INIT] flow start
4927 12:21:00.691110 [ANA_INIT] PLL >>>>>>>>
4928 12:21:00.691680 [ANA_INIT] PLL <<<<<<<<
4929 12:21:00.694720 [ANA_INIT] MIDPI >>>>>>>>
4930 12:21:00.697823 [ANA_INIT] MIDPI <<<<<<<<
4931 12:21:00.698287 [ANA_INIT] DLL >>>>>>>>
4932 12:21:00.701303 [ANA_INIT] flow end
4933 12:21:00.704838 ============ LP4 DIFF to SE enter ============
4934 12:21:00.707732 ============ LP4 DIFF to SE exit ============
4935 12:21:00.711047 [ANA_INIT] <<<<<<<<<<<<<
4936 12:21:00.714435 [Flow] Enable top DCM control >>>>>
4937 12:21:00.717483 [Flow] Enable top DCM control <<<<<
4938 12:21:00.721136 Enable DLL master slave shuffle
4939 12:21:00.727826 ==============================================================
4940 12:21:00.728386 Gating Mode config
4941 12:21:00.734182 ==============================================================
4942 12:21:00.734651 Config description:
4943 12:21:00.743966 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4944 12:21:00.750828 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4945 12:21:00.757451 SELPH_MODE 0: By rank 1: By Phase
4946 12:21:00.760729 ==============================================================
4947 12:21:00.764340 GAT_TRACK_EN = 1
4948 12:21:00.767607 RX_GATING_MODE = 2
4949 12:21:00.770936 RX_GATING_TRACK_MODE = 2
4950 12:21:00.774152 SELPH_MODE = 1
4951 12:21:00.777842 PICG_EARLY_EN = 1
4952 12:21:00.781103 VALID_LAT_VALUE = 1
4953 12:21:00.787917 ==============================================================
4954 12:21:00.790721 Enter into Gating configuration >>>>
4955 12:21:00.794179 Exit from Gating configuration <<<<
4956 12:21:00.794645 Enter into DVFS_PRE_config >>>>>
4957 12:21:00.807687 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4958 12:21:00.810814 Exit from DVFS_PRE_config <<<<<
4959 12:21:00.814114 Enter into PICG configuration >>>>
4960 12:21:00.817229 Exit from PICG configuration <<<<
4961 12:21:00.817697 [RX_INPUT] configuration >>>>>
4962 12:21:00.820918 [RX_INPUT] configuration <<<<<
4963 12:21:00.827295 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4964 12:21:00.830859 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4965 12:21:00.837595 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 12:21:00.843753 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 12:21:00.850587 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 12:21:00.857641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 12:21:00.860544 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4970 12:21:00.863543 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4971 12:21:00.870592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4972 12:21:00.874186 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4973 12:21:00.877091 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4974 12:21:00.880685 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 12:21:00.883987 ===================================
4976 12:21:00.887347 LPDDR4 DRAM CONFIGURATION
4977 12:21:00.890392 ===================================
4978 12:21:00.893660 EX_ROW_EN[0] = 0x0
4979 12:21:00.894224 EX_ROW_EN[1] = 0x0
4980 12:21:00.897037 LP4Y_EN = 0x0
4981 12:21:00.897684 WORK_FSP = 0x0
4982 12:21:00.900064 WL = 0x3
4983 12:21:00.900792 RL = 0x3
4984 12:21:00.903555 BL = 0x2
4985 12:21:00.904173 RPST = 0x0
4986 12:21:00.906743 RD_PRE = 0x0
4987 12:21:00.907214 WR_PRE = 0x1
4988 12:21:00.910185 WR_PST = 0x0
4989 12:21:00.913723 DBI_WR = 0x0
4990 12:21:00.914194 DBI_RD = 0x0
4991 12:21:00.916807 OTF = 0x1
4992 12:21:00.920121 ===================================
4993 12:21:00.923843 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4994 12:21:00.927056 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4995 12:21:00.929986 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 12:21:00.933449 ===================================
4997 12:21:00.936809 LPDDR4 DRAM CONFIGURATION
4998 12:21:00.940047 ===================================
4999 12:21:00.943461 EX_ROW_EN[0] = 0x10
5000 12:21:00.943934 EX_ROW_EN[1] = 0x0
5001 12:21:00.947059 LP4Y_EN = 0x0
5002 12:21:00.947798 WORK_FSP = 0x0
5003 12:21:00.950105 WL = 0x3
5004 12:21:00.950665 RL = 0x3
5005 12:21:00.953795 BL = 0x2
5006 12:21:00.954265 RPST = 0x0
5007 12:21:00.956452 RD_PRE = 0x0
5008 12:21:00.956922 WR_PRE = 0x1
5009 12:21:00.959925 WR_PST = 0x0
5010 12:21:00.963783 DBI_WR = 0x0
5011 12:21:00.964404 DBI_RD = 0x0
5012 12:21:00.966471 OTF = 0x1
5013 12:21:00.969766 ===================================
5014 12:21:00.973248 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5015 12:21:00.978514 nWR fixed to 30
5016 12:21:00.981637 [ModeRegInit_LP4] CH0 RK0
5017 12:21:00.982110 [ModeRegInit_LP4] CH0 RK1
5018 12:21:00.984913 [ModeRegInit_LP4] CH1 RK0
5019 12:21:00.988432 [ModeRegInit_LP4] CH1 RK1
5020 12:21:00.989028 match AC timing 9
5021 12:21:00.995592 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5022 12:21:00.998668 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5023 12:21:01.001680 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5024 12:21:01.008243 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5025 12:21:01.011645 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5026 12:21:01.012137 ==
5027 12:21:01.015292 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 12:21:01.018266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5029 12:21:01.018739 ==
5030 12:21:01.024834 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5031 12:21:01.031869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5032 12:21:01.035014 [CA 0] Center 37 (7~68) winsize 62
5033 12:21:01.038210 [CA 1] Center 38 (7~69) winsize 63
5034 12:21:01.041720 [CA 2] Center 35 (5~66) winsize 62
5035 12:21:01.045082 [CA 3] Center 35 (5~66) winsize 62
5036 12:21:01.048218 [CA 4] Center 34 (4~65) winsize 62
5037 12:21:01.051529 [CA 5] Center 33 (3~64) winsize 62
5038 12:21:01.052001
5039 12:21:01.054763 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5040 12:21:01.055233
5041 12:21:01.058302 [CATrainingPosCal] consider 1 rank data
5042 12:21:01.061624 u2DelayCellTimex100 = 270/100 ps
5043 12:21:01.065053 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5044 12:21:01.068683 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5045 12:21:01.072069 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5046 12:21:01.075013 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5047 12:21:01.078725 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5048 12:21:01.081595 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5049 12:21:01.082065
5050 12:21:01.088577 CA PerBit enable=1, Macro0, CA PI delay=33
5051 12:21:01.089177
5052 12:21:01.089561 [CBTSetCACLKResult] CA Dly = 33
5053 12:21:01.091464 CS Dly: 7 (0~38)
5054 12:21:01.091936 ==
5055 12:21:01.095112 Dram Type= 6, Freq= 0, CH_0, rank 1
5056 12:21:01.098204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 12:21:01.098683 ==
5058 12:21:01.104907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 12:21:01.111966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5060 12:21:01.115382 [CA 0] Center 38 (8~69) winsize 62
5061 12:21:01.118736 [CA 1] Center 38 (8~69) winsize 62
5062 12:21:01.121551 [CA 2] Center 36 (6~66) winsize 61
5063 12:21:01.125110 [CA 3] Center 35 (5~66) winsize 62
5064 12:21:01.128552 [CA 4] Center 34 (4~65) winsize 62
5065 12:21:01.131250 [CA 5] Center 34 (4~64) winsize 61
5066 12:21:01.131831
5067 12:21:01.135290 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5068 12:21:01.135869
5069 12:21:01.138164 [CATrainingPosCal] consider 2 rank data
5070 12:21:01.141507 u2DelayCellTimex100 = 270/100 ps
5071 12:21:01.145101 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5072 12:21:01.148246 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5073 12:21:01.151409 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5074 12:21:01.155020 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5075 12:21:01.157532 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5076 12:21:01.161231 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5077 12:21:01.164359
5078 12:21:01.167886 CA PerBit enable=1, Macro0, CA PI delay=34
5079 12:21:01.167975
5080 12:21:01.170808 [CBTSetCACLKResult] CA Dly = 34
5081 12:21:01.170985 CS Dly: 7 (0~39)
5082 12:21:01.171068
5083 12:21:01.174212 ----->DramcWriteLeveling(PI) begin...
5084 12:21:01.174351 ==
5085 12:21:01.177910 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 12:21:01.180873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 12:21:01.184448 ==
5088 12:21:01.184999 Write leveling (Byte 0): 35 => 35
5089 12:21:01.187687 Write leveling (Byte 1): 27 => 27
5090 12:21:01.191302 DramcWriteLeveling(PI) end<-----
5091 12:21:01.191883
5092 12:21:01.192260 ==
5093 12:21:01.194263 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 12:21:01.201472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 12:21:01.202039 ==
5096 12:21:01.204232 [Gating] SW mode calibration
5097 12:21:01.210798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 12:21:01.214224 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5099 12:21:01.221031 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5100 12:21:01.224315 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 12:21:01.227783 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 12:21:01.234571 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 12:21:01.237613 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 12:21:01.241321 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 12:21:01.244812 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5106 12:21:01.251243 0 14 28 | B1->B0 | 3131 2424 | 0 0 | (0 0) (0 0)
5107 12:21:01.254343 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 12:21:01.257717 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 12:21:01.264730 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 12:21:01.267808 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 12:21:01.271308 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 12:21:01.277342 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 12:21:01.280651 0 15 24 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
5114 12:21:01.284363 0 15 28 | B1->B0 | 2b2b 4545 | 1 0 | (0 0) (0 0)
5115 12:21:01.290519 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5116 12:21:01.293824 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 12:21:01.297152 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 12:21:01.303979 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 12:21:01.307258 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 12:21:01.310188 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 12:21:01.316871 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5122 12:21:01.320302 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5123 12:21:01.323564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 12:21:01.330419 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 12:21:01.333640 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:21:01.336996 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:21:01.343043 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:21:01.347009 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:21:01.349697 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:21:01.356365 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:21:01.359724 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:21:01.363095 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:21:01.370272 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:21:01.372985 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:21:01.376636 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:21:01.383286 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:21:01.386389 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5138 12:21:01.389883 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5139 12:21:01.396637 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5140 12:21:01.396981 Total UI for P1: 0, mck2ui 16
5141 12:21:01.403536 best dqsien dly found for B0: ( 1, 2, 26)
5142 12:21:01.406932 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 12:21:01.410136 Total UI for P1: 0, mck2ui 16
5144 12:21:01.413300 best dqsien dly found for B1: ( 1, 2, 30)
5145 12:21:01.417046 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5146 12:21:01.420348 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5147 12:21:01.421024
5148 12:21:01.423228 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5149 12:21:01.426462 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5150 12:21:01.430161 [Gating] SW calibration Done
5151 12:21:01.430755 ==
5152 12:21:01.433323 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 12:21:01.436622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 12:21:01.437237 ==
5155 12:21:01.439922 RX Vref Scan: 0
5156 12:21:01.440422
5157 12:21:01.443288 RX Vref 0 -> 0, step: 1
5158 12:21:01.443771
5159 12:21:01.444143 RX Delay -80 -> 252, step: 8
5160 12:21:01.449949 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5161 12:21:01.453139 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5162 12:21:01.456270 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5163 12:21:01.459795 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5164 12:21:01.462889 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5165 12:21:01.469686 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5166 12:21:01.473034 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5167 12:21:01.476480 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5168 12:21:01.479487 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5169 12:21:01.482844 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5170 12:21:01.486087 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5171 12:21:01.492875 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5172 12:21:01.496186 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5173 12:21:01.499736 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5174 12:21:01.503147 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5175 12:21:01.506386 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5176 12:21:01.506858 ==
5177 12:21:01.509354 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 12:21:01.516142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 12:21:01.516571 ==
5180 12:21:01.517094 DQS Delay:
5181 12:21:01.517419 DQS0 = 0, DQS1 = 0
5182 12:21:01.519498 DQM Delay:
5183 12:21:01.519914 DQM0 = 105, DQM1 = 91
5184 12:21:01.522909 DQ Delay:
5185 12:21:01.526708 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5186 12:21:01.529383 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5187 12:21:01.533110 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5188 12:21:01.536359 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5189 12:21:01.536873
5190 12:21:01.537267
5191 12:21:01.537578 ==
5192 12:21:01.539550 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 12:21:01.542764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 12:21:01.543286 ==
5195 12:21:01.543621
5196 12:21:01.543929
5197 12:21:01.546175 TX Vref Scan disable
5198 12:21:01.549558 == TX Byte 0 ==
5199 12:21:01.552832 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5200 12:21:01.556142 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5201 12:21:01.559595 == TX Byte 1 ==
5202 12:21:01.562850 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5203 12:21:01.566145 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5204 12:21:01.566721 ==
5205 12:21:01.569455 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 12:21:01.572463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 12:21:01.575815 ==
5208 12:21:01.576354
5209 12:21:01.576703
5210 12:21:01.577057 TX Vref Scan disable
5211 12:21:01.579335 == TX Byte 0 ==
5212 12:21:01.582559 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5213 12:21:01.589496 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5214 12:21:01.589919 == TX Byte 1 ==
5215 12:21:01.592501 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5216 12:21:01.599401 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5217 12:21:01.599934
5218 12:21:01.600275 [DATLAT]
5219 12:21:01.600584 Freq=933, CH0 RK0
5220 12:21:01.600884
5221 12:21:01.602687 DATLAT Default: 0xd
5222 12:21:01.603212 0, 0xFFFF, sum = 0
5223 12:21:01.605792 1, 0xFFFF, sum = 0
5224 12:21:01.606225 2, 0xFFFF, sum = 0
5225 12:21:01.609402 3, 0xFFFF, sum = 0
5226 12:21:01.612888 4, 0xFFFF, sum = 0
5227 12:21:01.613476 5, 0xFFFF, sum = 0
5228 12:21:01.616087 6, 0xFFFF, sum = 0
5229 12:21:01.616661 7, 0xFFFF, sum = 0
5230 12:21:01.619458 8, 0xFFFF, sum = 0
5231 12:21:01.620081 9, 0xFFFF, sum = 0
5232 12:21:01.622754 10, 0x0, sum = 1
5233 12:21:01.623230 11, 0x0, sum = 2
5234 12:21:01.626169 12, 0x0, sum = 3
5235 12:21:01.626752 13, 0x0, sum = 4
5236 12:21:01.627137 best_step = 11
5237 12:21:01.627481
5238 12:21:01.629467 ==
5239 12:21:01.629938 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 12:21:01.635953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 12:21:01.636431 ==
5242 12:21:01.636811 RX Vref Scan: 1
5243 12:21:01.637214
5244 12:21:01.639294 RX Vref 0 -> 0, step: 1
5245 12:21:01.639760
5246 12:21:01.642660 RX Delay -53 -> 252, step: 4
5247 12:21:01.643132
5248 12:21:01.645966 Set Vref, RX VrefLevel [Byte0]: 58
5249 12:21:01.648969 [Byte1]: 50
5250 12:21:01.649448
5251 12:21:01.653164 Final RX Vref Byte 0 = 58 to rank0
5252 12:21:01.656314 Final RX Vref Byte 1 = 50 to rank0
5253 12:21:01.659396 Final RX Vref Byte 0 = 58 to rank1
5254 12:21:01.662616 Final RX Vref Byte 1 = 50 to rank1==
5255 12:21:01.665931 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 12:21:01.669082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 12:21:01.669559 ==
5258 12:21:01.672991 DQS Delay:
5259 12:21:01.673590 DQS0 = 0, DQS1 = 0
5260 12:21:01.675906 DQM Delay:
5261 12:21:01.676374 DQM0 = 107, DQM1 = 92
5262 12:21:01.676749 DQ Delay:
5263 12:21:01.682394 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5264 12:21:01.685890 DQ4 =106, DQ5 =98, DQ6 =118, DQ7 =114
5265 12:21:01.686365 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =92
5266 12:21:01.692371 DQ12 =96, DQ13 =96, DQ14 =104, DQ15 =100
5267 12:21:01.692878
5268 12:21:01.693377
5269 12:21:01.699545 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5270 12:21:01.702950 CH0 RK0: MR19=505, MR18=2622
5271 12:21:01.709648 CH0_RK0: MR19=0x505, MR18=0x2622, DQSOSC=409, MR23=63, INC=64, DEC=43
5272 12:21:01.710219
5273 12:21:01.712460 ----->DramcWriteLeveling(PI) begin...
5274 12:21:01.712964 ==
5275 12:21:01.716067 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 12:21:01.719076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 12:21:01.719550 ==
5278 12:21:01.722630 Write leveling (Byte 0): 35 => 35
5279 12:21:01.725948 Write leveling (Byte 1): 29 => 29
5280 12:21:01.729021 DramcWriteLeveling(PI) end<-----
5281 12:21:01.729489
5282 12:21:01.729860 ==
5283 12:21:01.732751 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 12:21:01.735793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 12:21:01.736268 ==
5286 12:21:01.739169 [Gating] SW mode calibration
5287 12:21:01.745758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5288 12:21:01.752648 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5289 12:21:01.755856 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5290 12:21:01.759178 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 12:21:01.765599 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 12:21:01.769007 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 12:21:01.772192 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 12:21:01.778834 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 12:21:01.782230 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5296 12:21:01.785479 0 14 28 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5297 12:21:01.791986 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5298 12:21:01.795793 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 12:21:01.799114 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 12:21:01.805481 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 12:21:01.809117 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 12:21:01.812530 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 12:21:01.819099 0 15 24 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
5304 12:21:01.822091 0 15 28 | B1->B0 | 3939 4141 | 0 1 | (1 1) (0 0)
5305 12:21:01.825299 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5306 12:21:01.832022 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 12:21:01.835575 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 12:21:01.839266 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 12:21:01.845329 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 12:21:01.848969 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 12:21:01.852503 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 12:21:01.858721 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5313 12:21:01.862561 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5314 12:21:01.865260 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:21:01.872051 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 12:21:01.875096 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 12:21:01.878675 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:21:01.885330 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:21:01.888761 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:21:01.891944 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:21:01.898482 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:21:01.902035 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:21:01.905234 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:21:01.908813 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:21:01.915257 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:21:01.918883 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:21:01.921828 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5328 12:21:01.929172 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5329 12:21:01.931735 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 12:21:01.935048 Total UI for P1: 0, mck2ui 16
5331 12:21:01.938555 best dqsien dly found for B0: ( 1, 2, 26)
5332 12:21:01.941827 Total UI for P1: 0, mck2ui 16
5333 12:21:01.945323 best dqsien dly found for B1: ( 1, 2, 26)
5334 12:21:01.948302 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5335 12:21:01.952411 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5336 12:21:01.953019
5337 12:21:01.955113 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5338 12:21:01.958391 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5339 12:21:01.961809 [Gating] SW calibration Done
5340 12:21:01.962260 ==
5341 12:21:01.964969 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 12:21:01.968513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 12:21:01.971787 ==
5344 12:21:01.972344 RX Vref Scan: 0
5345 12:21:01.972845
5346 12:21:01.975294 RX Vref 0 -> 0, step: 1
5347 12:21:01.975844
5348 12:21:01.978519 RX Delay -80 -> 252, step: 8
5349 12:21:01.982161 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5350 12:21:01.984969 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5351 12:21:01.988351 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5352 12:21:01.991599 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5353 12:21:01.998107 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5354 12:21:02.001378 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5355 12:21:02.005416 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5356 12:21:02.008075 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5357 12:21:02.011670 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5358 12:21:02.014679 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5359 12:21:02.021411 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5360 12:21:02.024825 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5361 12:21:02.027995 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5362 12:21:02.031387 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5363 12:21:02.035071 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5364 12:21:02.038218 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5365 12:21:02.038772 ==
5366 12:21:02.041785 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 12:21:02.048195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 12:21:02.048751 ==
5369 12:21:02.049172 DQS Delay:
5370 12:21:02.051668 DQS0 = 0, DQS1 = 0
5371 12:21:02.052219 DQM Delay:
5372 12:21:02.054997 DQM0 = 104, DQM1 = 90
5373 12:21:02.055558 DQ Delay:
5374 12:21:02.058075 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5375 12:21:02.061662 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5376 12:21:02.064391 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5377 12:21:02.068051 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5378 12:21:02.068505
5379 12:21:02.068860
5380 12:21:02.069239 ==
5381 12:21:02.071951 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 12:21:02.074725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 12:21:02.075181 ==
5384 12:21:02.075537
5385 12:21:02.075865
5386 12:21:02.078338 TX Vref Scan disable
5387 12:21:02.081613 == TX Byte 0 ==
5388 12:21:02.085011 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5389 12:21:02.088024 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5390 12:21:02.091604 == TX Byte 1 ==
5391 12:21:02.094677 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5392 12:21:02.097652 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5393 12:21:02.098134 ==
5394 12:21:02.101391 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 12:21:02.107636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 12:21:02.108175 ==
5397 12:21:02.108534
5398 12:21:02.108864
5399 12:21:02.109236 TX Vref Scan disable
5400 12:21:02.111756 == TX Byte 0 ==
5401 12:21:02.115226 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5402 12:21:02.121554 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5403 12:21:02.122138 == TX Byte 1 ==
5404 12:21:02.125090 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5405 12:21:02.131652 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5406 12:21:02.132113
5407 12:21:02.132466 [DATLAT]
5408 12:21:02.132797 Freq=933, CH0 RK1
5409 12:21:02.133178
5410 12:21:02.134797 DATLAT Default: 0xb
5411 12:21:02.135281 0, 0xFFFF, sum = 0
5412 12:21:02.138184 1, 0xFFFF, sum = 0
5413 12:21:02.138641 2, 0xFFFF, sum = 0
5414 12:21:02.141552 3, 0xFFFF, sum = 0
5415 12:21:02.144994 4, 0xFFFF, sum = 0
5416 12:21:02.145612 5, 0xFFFF, sum = 0
5417 12:21:02.148028 6, 0xFFFF, sum = 0
5418 12:21:02.148489 7, 0xFFFF, sum = 0
5419 12:21:02.151858 8, 0xFFFF, sum = 0
5420 12:21:02.152413 9, 0xFFFF, sum = 0
5421 12:21:02.154993 10, 0x0, sum = 1
5422 12:21:02.155454 11, 0x0, sum = 2
5423 12:21:02.155818 12, 0x0, sum = 3
5424 12:21:02.158105 13, 0x0, sum = 4
5425 12:21:02.158566 best_step = 11
5426 12:21:02.158949
5427 12:21:02.161652 ==
5428 12:21:02.162279 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 12:21:02.168306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 12:21:02.168760 ==
5431 12:21:02.169172 RX Vref Scan: 0
5432 12:21:02.169515
5433 12:21:02.171729 RX Vref 0 -> 0, step: 1
5434 12:21:02.172279
5435 12:21:02.175380 RX Delay -53 -> 252, step: 4
5436 12:21:02.178297 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5437 12:21:02.184961 iDelay=199, Bit 1, Center 104 (15 ~ 194) 180
5438 12:21:02.188372 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5439 12:21:02.192117 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5440 12:21:02.194853 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5441 12:21:02.198212 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5442 12:21:02.201666 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5443 12:21:02.208305 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5444 12:21:02.211502 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5445 12:21:02.214872 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5446 12:21:02.218267 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5447 12:21:02.221498 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5448 12:21:02.228501 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5449 12:21:02.231615 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5450 12:21:02.234849 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5451 12:21:02.238154 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5452 12:21:02.238631 ==
5453 12:21:02.241258 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 12:21:02.248218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 12:21:02.248881 ==
5456 12:21:02.249428 DQS Delay:
5457 12:21:02.249932 DQS0 = 0, DQS1 = 0
5458 12:21:02.251467 DQM Delay:
5459 12:21:02.252016 DQM0 = 104, DQM1 = 92
5460 12:21:02.254740 DQ Delay:
5461 12:21:02.257934 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =98
5462 12:21:02.261301 DQ4 =106, DQ5 =98, DQ6 =114, DQ7 =110
5463 12:21:02.264613 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5464 12:21:02.267784 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =98
5465 12:21:02.268252
5466 12:21:02.268618
5467 12:21:02.274580 [DQSOSCAuto] RK1, (LSB)MR18= 0x2606, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
5468 12:21:02.277951 CH0 RK1: MR19=505, MR18=2606
5469 12:21:02.284316 CH0_RK1: MR19=0x505, MR18=0x2606, DQSOSC=409, MR23=63, INC=64, DEC=43
5470 12:21:02.287963 [RxdqsGatingPostProcess] freq 933
5471 12:21:02.294179 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5472 12:21:02.294652 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 12:21:02.298003 best DQS1 dly(2T, 0.5T) = (0, 10)
5474 12:21:02.300898 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 12:21:02.304062 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5476 12:21:02.307867 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 12:21:02.310775 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 12:21:02.314310 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 12:21:02.317583 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 12:21:02.321066 Pre-setting of DQS Precalculation
5481 12:21:02.327785 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5482 12:21:02.328258 ==
5483 12:21:02.331121 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 12:21:02.334219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 12:21:02.334690 ==
5486 12:21:02.337525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5487 12:21:02.344250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5488 12:21:02.347895 [CA 0] Center 37 (7~68) winsize 62
5489 12:21:02.351329 [CA 1] Center 37 (7~68) winsize 62
5490 12:21:02.354511 [CA 2] Center 36 (6~66) winsize 61
5491 12:21:02.357931 [CA 3] Center 34 (4~65) winsize 62
5492 12:21:02.361338 [CA 4] Center 35 (5~65) winsize 61
5493 12:21:02.365118 [CA 5] Center 34 (4~65) winsize 62
5494 12:21:02.365708
5495 12:21:02.368219 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5496 12:21:02.368688
5497 12:21:02.371239 [CATrainingPosCal] consider 1 rank data
5498 12:21:02.374801 u2DelayCellTimex100 = 270/100 ps
5499 12:21:02.377771 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5500 12:21:02.381321 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5501 12:21:02.387923 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5502 12:21:02.391077 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5503 12:21:02.394841 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5504 12:21:02.398220 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5505 12:21:02.398690
5506 12:21:02.401486 CA PerBit enable=1, Macro0, CA PI delay=34
5507 12:21:02.401954
5508 12:21:02.404465 [CBTSetCACLKResult] CA Dly = 34
5509 12:21:02.404962 CS Dly: 6 (0~37)
5510 12:21:02.407792 ==
5511 12:21:02.411111 Dram Type= 6, Freq= 0, CH_1, rank 1
5512 12:21:02.414578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 12:21:02.415053 ==
5514 12:21:02.417578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 12:21:02.424504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5516 12:21:02.428389 [CA 0] Center 38 (8~68) winsize 61
5517 12:21:02.431641 [CA 1] Center 38 (8~68) winsize 61
5518 12:21:02.434470 [CA 2] Center 36 (6~66) winsize 61
5519 12:21:02.437980 [CA 3] Center 35 (6~65) winsize 60
5520 12:21:02.441532 [CA 4] Center 35 (6~65) winsize 60
5521 12:21:02.445051 [CA 5] Center 35 (5~65) winsize 61
5522 12:21:02.445614
5523 12:21:02.448236 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5524 12:21:02.448798
5525 12:21:02.451182 [CATrainingPosCal] consider 2 rank data
5526 12:21:02.454542 u2DelayCellTimex100 = 270/100 ps
5527 12:21:02.458001 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5528 12:21:02.461107 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5529 12:21:02.468223 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5530 12:21:02.471570 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5531 12:21:02.474884 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
5532 12:21:02.477895 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5533 12:21:02.478358
5534 12:21:02.481586 CA PerBit enable=1, Macro0, CA PI delay=35
5535 12:21:02.482146
5536 12:21:02.484832 [CBTSetCACLKResult] CA Dly = 35
5537 12:21:02.485469 CS Dly: 7 (0~39)
5538 12:21:02.485854
5539 12:21:02.487598 ----->DramcWriteLeveling(PI) begin...
5540 12:21:02.490921 ==
5541 12:21:02.494714 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 12:21:02.497768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 12:21:02.498235 ==
5544 12:21:02.500919 Write leveling (Byte 0): 26 => 26
5545 12:21:02.504475 Write leveling (Byte 1): 32 => 32
5546 12:21:02.507784 DramcWriteLeveling(PI) end<-----
5547 12:21:02.508337
5548 12:21:02.508709 ==
5549 12:21:02.511285 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 12:21:02.514123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 12:21:02.514606 ==
5552 12:21:02.517525 [Gating] SW mode calibration
5553 12:21:02.524460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5554 12:21:02.530799 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5555 12:21:02.534232 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 12:21:02.537340 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 12:21:02.544064 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 12:21:02.547303 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 12:21:02.550861 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 12:21:02.557088 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 12:21:02.560726 0 14 24 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 0)
5562 12:21:02.563987 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5563 12:21:02.567639 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 12:21:02.573899 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 12:21:02.577216 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 12:21:02.580617 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 12:21:02.587318 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 12:21:02.591224 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 12:21:02.594160 0 15 24 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (0 0)
5570 12:21:02.600647 0 15 28 | B1->B0 | 3d3d 4040 | 0 0 | (0 0) (0 0)
5571 12:21:02.603930 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 12:21:02.607219 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 12:21:02.614463 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 12:21:02.617091 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 12:21:02.620730 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 12:21:02.627475 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5577 12:21:02.630704 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5578 12:21:02.633899 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:21:02.640654 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:21:02.644064 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:21:02.647700 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:21:02.653897 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:21:02.656891 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:21:02.660430 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:21:02.667117 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:21:02.670148 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:21:02.673813 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:21:02.680584 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:21:02.683552 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:21:02.687287 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:21:02.690416 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:21:02.696903 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:21:02.700322 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5594 12:21:02.704001 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 12:21:02.706919 Total UI for P1: 0, mck2ui 16
5596 12:21:02.710393 best dqsien dly found for B0: ( 1, 2, 24)
5597 12:21:02.713909 Total UI for P1: 0, mck2ui 16
5598 12:21:02.717355 best dqsien dly found for B1: ( 1, 2, 24)
5599 12:21:02.720488 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5600 12:21:02.726870 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5601 12:21:02.727457
5602 12:21:02.730020 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5603 12:21:02.733262 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5604 12:21:02.737150 [Gating] SW calibration Done
5605 12:21:02.737722 ==
5606 12:21:02.740783 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 12:21:02.743703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 12:21:02.744287 ==
5609 12:21:02.744664 RX Vref Scan: 0
5610 12:21:02.747127
5611 12:21:02.747700 RX Vref 0 -> 0, step: 1
5612 12:21:02.748080
5613 12:21:02.750406 RX Delay -80 -> 252, step: 8
5614 12:21:02.753632 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5615 12:21:02.756766 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5616 12:21:02.763289 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5617 12:21:02.766532 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5618 12:21:02.769978 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5619 12:21:02.773539 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5620 12:21:02.776637 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5621 12:21:02.783363 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5622 12:21:02.786717 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5623 12:21:02.790160 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5624 12:21:02.793270 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5625 12:21:02.796863 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5626 12:21:02.800161 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5627 12:21:02.806629 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5628 12:21:02.810327 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5629 12:21:02.813497 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5630 12:21:02.813971 ==
5631 12:21:02.816721 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 12:21:02.820009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 12:21:02.820485 ==
5634 12:21:02.823459 DQS Delay:
5635 12:21:02.824036 DQS0 = 0, DQS1 = 0
5636 12:21:02.824417 DQM Delay:
5637 12:21:02.827102 DQM0 = 103, DQM1 = 95
5638 12:21:02.827581 DQ Delay:
5639 12:21:02.830059 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =103
5640 12:21:02.833622 DQ4 =103, DQ5 =111, DQ6 =115, DQ7 =103
5641 12:21:02.836581 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5642 12:21:02.840078 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =99
5643 12:21:02.840656
5644 12:21:02.843332
5645 12:21:02.843799 ==
5646 12:21:02.846830 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 12:21:02.850161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 12:21:02.850749 ==
5649 12:21:02.851128
5650 12:21:02.851473
5651 12:21:02.853018 TX Vref Scan disable
5652 12:21:02.853493 == TX Byte 0 ==
5653 12:21:02.859477 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5654 12:21:02.862813 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5655 12:21:02.862897 == TX Byte 1 ==
5656 12:21:02.869681 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5657 12:21:02.872987 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5658 12:21:02.873126 ==
5659 12:21:02.876042 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 12:21:02.879417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 12:21:02.879515 ==
5662 12:21:02.879592
5663 12:21:02.879662
5664 12:21:02.883074 TX Vref Scan disable
5665 12:21:02.886382 == TX Byte 0 ==
5666 12:21:02.889439 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5667 12:21:02.893050 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5668 12:21:02.895953 == TX Byte 1 ==
5669 12:21:02.899718 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5670 12:21:02.902728 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5671 12:21:02.902869
5672 12:21:02.905974 [DATLAT]
5673 12:21:02.906144 Freq=933, CH1 RK0
5674 12:21:02.906270
5675 12:21:02.909247 DATLAT Default: 0xd
5676 12:21:02.909423 0, 0xFFFF, sum = 0
5677 12:21:02.912811 1, 0xFFFF, sum = 0
5678 12:21:02.913045 2, 0xFFFF, sum = 0
5679 12:21:02.915745 3, 0xFFFF, sum = 0
5680 12:21:02.916016 4, 0xFFFF, sum = 0
5681 12:21:02.919811 5, 0xFFFF, sum = 0
5682 12:21:02.920110 6, 0xFFFF, sum = 0
5683 12:21:02.922558 7, 0xFFFF, sum = 0
5684 12:21:02.922806 8, 0xFFFF, sum = 0
5685 12:21:02.926202 9, 0xFFFF, sum = 0
5686 12:21:02.926604 10, 0x0, sum = 1
5687 12:21:02.929482 11, 0x0, sum = 2
5688 12:21:02.929961 12, 0x0, sum = 3
5689 12:21:02.932703 13, 0x0, sum = 4
5690 12:21:02.933161 best_step = 11
5691 12:21:02.933457
5692 12:21:02.933778 ==
5693 12:21:02.936199 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 12:21:02.942783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 12:21:02.943215 ==
5696 12:21:02.943553 RX Vref Scan: 1
5697 12:21:02.943870
5698 12:21:02.946426 RX Vref 0 -> 0, step: 1
5699 12:21:02.946851
5700 12:21:02.949614 RX Delay -53 -> 252, step: 4
5701 12:21:02.950041
5702 12:21:02.952757 Set Vref, RX VrefLevel [Byte0]: 52
5703 12:21:02.955862 [Byte1]: 53
5704 12:21:02.956505
5705 12:21:02.959441 Final RX Vref Byte 0 = 52 to rank0
5706 12:21:02.963186 Final RX Vref Byte 1 = 53 to rank0
5707 12:21:02.966306 Final RX Vref Byte 0 = 52 to rank1
5708 12:21:02.969314 Final RX Vref Byte 1 = 53 to rank1==
5709 12:21:02.972886 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 12:21:02.976041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 12:21:02.976474 ==
5712 12:21:02.979680 DQS Delay:
5713 12:21:02.980104 DQS0 = 0, DQS1 = 0
5714 12:21:02.980442 DQM Delay:
5715 12:21:02.982869 DQM0 = 104, DQM1 = 97
5716 12:21:02.983296 DQ Delay:
5717 12:21:02.986013 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5718 12:21:02.989447 DQ4 =102, DQ5 =112, DQ6 =114, DQ7 =102
5719 12:21:02.992640 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92
5720 12:21:02.996407 DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =102
5721 12:21:02.999406
5722 12:21:02.999868
5723 12:21:03.005663 [DQSOSCAuto] RK0, (LSB)MR18= 0x1932, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5724 12:21:03.009237 CH1 RK0: MR19=505, MR18=1932
5725 12:21:03.015558 CH1_RK0: MR19=0x505, MR18=0x1932, DQSOSC=406, MR23=63, INC=65, DEC=43
5726 12:21:03.016116
5727 12:21:03.019261 ----->DramcWriteLeveling(PI) begin...
5728 12:21:03.019731 ==
5729 12:21:03.022532 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 12:21:03.025983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 12:21:03.026451 ==
5732 12:21:03.029407 Write leveling (Byte 0): 27 => 27
5733 12:21:03.033164 Write leveling (Byte 1): 27 => 27
5734 12:21:03.036103 DramcWriteLeveling(PI) end<-----
5735 12:21:03.036665
5736 12:21:03.037089 ==
5737 12:21:03.039561 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 12:21:03.042760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 12:21:03.043328 ==
5740 12:21:03.046166 [Gating] SW mode calibration
5741 12:21:03.052592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5742 12:21:03.059416 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5743 12:21:03.062455 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 12:21:03.065959 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 12:21:03.072568 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 12:21:03.076120 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 12:21:03.079153 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 12:21:03.085576 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 12:21:03.089238 0 14 24 | B1->B0 | 3030 3434 | 1 0 | (0 1) (0 1)
5750 12:21:03.092438 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
5751 12:21:03.099176 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
5752 12:21:03.102245 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 12:21:03.105824 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 12:21:03.113070 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 12:21:03.115534 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 12:21:03.119167 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 12:21:03.122445 0 15 24 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
5758 12:21:03.129394 0 15 28 | B1->B0 | 3f3f 3b3b | 0 1 | (0 0) (0 0)
5759 12:21:03.132891 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5760 12:21:03.136265 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 12:21:03.142565 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 12:21:03.146068 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 12:21:03.149536 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 12:21:03.155863 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 12:21:03.159084 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 12:21:03.162438 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5767 12:21:03.169033 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 12:21:03.172152 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 12:21:03.175804 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 12:21:03.182124 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:21:03.185826 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:21:03.188694 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:21:03.195198 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:21:03.198723 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:21:03.202335 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:21:03.208427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:21:03.212045 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:21:03.215263 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:21:03.221980 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:21:03.224991 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:21:03.228418 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5782 12:21:03.235314 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5783 12:21:03.238487 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 12:21:03.241969 Total UI for P1: 0, mck2ui 16
5785 12:21:03.245481 best dqsien dly found for B0: ( 1, 2, 26)
5786 12:21:03.248372 Total UI for P1: 0, mck2ui 16
5787 12:21:03.251651 best dqsien dly found for B1: ( 1, 2, 28)
5788 12:21:03.255105 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5789 12:21:03.258489 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5790 12:21:03.258584
5791 12:21:03.261568 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5792 12:21:03.265089 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5793 12:21:03.268329 [Gating] SW calibration Done
5794 12:21:03.268474 ==
5795 12:21:03.272071 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 12:21:03.275154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 12:21:03.275347 ==
5798 12:21:03.278668 RX Vref Scan: 0
5799 12:21:03.278854
5800 12:21:03.281690 RX Vref 0 -> 0, step: 1
5801 12:21:03.281894
5802 12:21:03.282037 RX Delay -80 -> 252, step: 8
5803 12:21:03.288545 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5804 12:21:03.291688 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5805 12:21:03.295146 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5806 12:21:03.298159 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5807 12:21:03.301622 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5808 12:21:03.304543 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5809 12:21:03.311479 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5810 12:21:03.314928 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5811 12:21:03.317981 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5812 12:21:03.321637 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5813 12:21:03.324849 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5814 12:21:03.331487 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5815 12:21:03.335013 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5816 12:21:03.338246 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5817 12:21:03.341292 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5818 12:21:03.344814 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5819 12:21:03.345099 ==
5820 12:21:03.348227 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 12:21:03.354817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 12:21:03.355161 ==
5823 12:21:03.355427 DQS Delay:
5824 12:21:03.358141 DQS0 = 0, DQS1 = 0
5825 12:21:03.358389 DQM Delay:
5826 12:21:03.358691 DQM0 = 101, DQM1 = 95
5827 12:21:03.361442 DQ Delay:
5828 12:21:03.365047 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5829 12:21:03.368623 DQ4 =99, DQ5 =111, DQ6 =107, DQ7 =99
5830 12:21:03.372078 DQ8 =79, DQ9 =83, DQ10 =99, DQ11 =87
5831 12:21:03.375629 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5832 12:21:03.376211
5833 12:21:03.376688
5834 12:21:03.377223 ==
5835 12:21:03.378035 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 12:21:03.381547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 12:21:03.382028 ==
5838 12:21:03.382498
5839 12:21:03.382938
5840 12:21:03.384875 TX Vref Scan disable
5841 12:21:03.387759 == TX Byte 0 ==
5842 12:21:03.391433 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5843 12:21:03.395069 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5844 12:21:03.398226 == TX Byte 1 ==
5845 12:21:03.401302 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5846 12:21:03.404587 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5847 12:21:03.405110 ==
5848 12:21:03.408320 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 12:21:03.411722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 12:21:03.414937 ==
5851 12:21:03.415511
5852 12:21:03.415986
5853 12:21:03.416428 TX Vref Scan disable
5854 12:21:03.418515 == TX Byte 0 ==
5855 12:21:03.421883 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5856 12:21:03.428525 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5857 12:21:03.429151 == TX Byte 1 ==
5858 12:21:03.431533 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5859 12:21:03.438211 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5860 12:21:03.438839
5861 12:21:03.439330 [DATLAT]
5862 12:21:03.439781 Freq=933, CH1 RK1
5863 12:21:03.440217
5864 12:21:03.441669 DATLAT Default: 0xb
5865 12:21:03.442144 0, 0xFFFF, sum = 0
5866 12:21:03.445175 1, 0xFFFF, sum = 0
5867 12:21:03.445773 2, 0xFFFF, sum = 0
5868 12:21:03.448237 3, 0xFFFF, sum = 0
5869 12:21:03.451985 4, 0xFFFF, sum = 0
5870 12:21:03.452568 5, 0xFFFF, sum = 0
5871 12:21:03.455241 6, 0xFFFF, sum = 0
5872 12:21:03.455840 7, 0xFFFF, sum = 0
5873 12:21:03.458060 8, 0xFFFF, sum = 0
5874 12:21:03.458548 9, 0xFFFF, sum = 0
5875 12:21:03.461546 10, 0x0, sum = 1
5876 12:21:03.462030 11, 0x0, sum = 2
5877 12:21:03.465317 12, 0x0, sum = 3
5878 12:21:03.465900 13, 0x0, sum = 4
5879 12:21:03.466388 best_step = 11
5880 12:21:03.466912
5881 12:21:03.468115 ==
5882 12:21:03.468594 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 12:21:03.475124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 12:21:03.475708 ==
5885 12:21:03.476188 RX Vref Scan: 0
5886 12:21:03.476634
5887 12:21:03.478166 RX Vref 0 -> 0, step: 1
5888 12:21:03.478641
5889 12:21:03.481536 RX Delay -61 -> 252, step: 4
5890 12:21:03.485117 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5891 12:21:03.491728 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5892 12:21:03.494754 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5893 12:21:03.498007 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5894 12:21:03.501392 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5895 12:21:03.504644 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5896 12:21:03.511540 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5897 12:21:03.515065 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5898 12:21:03.518291 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5899 12:21:03.521685 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5900 12:21:03.525098 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5901 12:21:03.528442 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5902 12:21:03.534823 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5903 12:21:03.537816 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5904 12:21:03.541175 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5905 12:21:03.544333 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5906 12:21:03.544791 ==
5907 12:21:03.547813 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 12:21:03.554688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 12:21:03.555157 ==
5910 12:21:03.555529 DQS Delay:
5911 12:21:03.557796 DQS0 = 0, DQS1 = 0
5912 12:21:03.558276 DQM Delay:
5913 12:21:03.558648 DQM0 = 104, DQM1 = 97
5914 12:21:03.561169 DQ Delay:
5915 12:21:03.564639 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5916 12:21:03.568067 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5917 12:21:03.571551 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =92
5918 12:21:03.574717 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5919 12:21:03.575284
5920 12:21:03.575653
5921 12:21:03.581137 [DQSOSCAuto] RK1, (LSB)MR18= 0x2401, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5922 12:21:03.585351 CH1 RK1: MR19=505, MR18=2401
5923 12:21:03.591740 CH1_RK1: MR19=0x505, MR18=0x2401, DQSOSC=410, MR23=63, INC=64, DEC=42
5924 12:21:03.594826 [RxdqsGatingPostProcess] freq 933
5925 12:21:03.601411 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5926 12:21:03.601888 best DQS0 dly(2T, 0.5T) = (0, 10)
5927 12:21:03.604630 best DQS1 dly(2T, 0.5T) = (0, 10)
5928 12:21:03.608008 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5929 12:21:03.611759 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5930 12:21:03.614861 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 12:21:03.618031 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 12:21:03.621718 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 12:21:03.624681 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 12:21:03.628253 Pre-setting of DQS Precalculation
5935 12:21:03.631560 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5936 12:21:03.641116 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5937 12:21:03.647877 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5938 12:21:03.648356
5939 12:21:03.648745
5940 12:21:03.651211 [Calibration Summary] 1866 Mbps
5941 12:21:03.651679 CH 0, Rank 0
5942 12:21:03.655141 SW Impedance : PASS
5943 12:21:03.655618 DUTY Scan : NO K
5944 12:21:03.657718 ZQ Calibration : PASS
5945 12:21:03.661191 Jitter Meter : NO K
5946 12:21:03.661619 CBT Training : PASS
5947 12:21:03.664587 Write leveling : PASS
5948 12:21:03.667990 RX DQS gating : PASS
5949 12:21:03.668462 RX DQ/DQS(RDDQC) : PASS
5950 12:21:03.671174 TX DQ/DQS : PASS
5951 12:21:03.674462 RX DATLAT : PASS
5952 12:21:03.675046 RX DQ/DQS(Engine): PASS
5953 12:21:03.678350 TX OE : NO K
5954 12:21:03.678912 All Pass.
5955 12:21:03.679277
5956 12:21:03.681319 CH 0, Rank 1
5957 12:21:03.681745 SW Impedance : PASS
5958 12:21:03.685392 DUTY Scan : NO K
5959 12:21:03.688434 ZQ Calibration : PASS
5960 12:21:03.689066 Jitter Meter : NO K
5961 12:21:03.691371 CBT Training : PASS
5962 12:21:03.691889 Write leveling : PASS
5963 12:21:03.694549 RX DQS gating : PASS
5964 12:21:03.697939 RX DQ/DQS(RDDQC) : PASS
5965 12:21:03.698412 TX DQ/DQS : PASS
5966 12:21:03.701532 RX DATLAT : PASS
5967 12:21:03.704586 RX DQ/DQS(Engine): PASS
5968 12:21:03.705110 TX OE : NO K
5969 12:21:03.707901 All Pass.
5970 12:21:03.708400
5971 12:21:03.708775 CH 1, Rank 0
5972 12:21:03.711870 SW Impedance : PASS
5973 12:21:03.712452 DUTY Scan : NO K
5974 12:21:03.714789 ZQ Calibration : PASS
5975 12:21:03.718196 Jitter Meter : NO K
5976 12:21:03.718711 CBT Training : PASS
5977 12:21:03.721187 Write leveling : PASS
5978 12:21:03.724688 RX DQS gating : PASS
5979 12:21:03.725207 RX DQ/DQS(RDDQC) : PASS
5980 12:21:03.728096 TX DQ/DQS : PASS
5981 12:21:03.731384 RX DATLAT : PASS
5982 12:21:03.731962 RX DQ/DQS(Engine): PASS
5983 12:21:03.734960 TX OE : NO K
5984 12:21:03.735544 All Pass.
5985 12:21:03.735916
5986 12:21:03.738025 CH 1, Rank 1
5987 12:21:03.738726 SW Impedance : PASS
5988 12:21:03.741072 DUTY Scan : NO K
5989 12:21:03.741634 ZQ Calibration : PASS
5990 12:21:03.744561 Jitter Meter : NO K
5991 12:21:03.748419 CBT Training : PASS
5992 12:21:03.749041 Write leveling : PASS
5993 12:21:03.751503 RX DQS gating : PASS
5994 12:21:03.754851 RX DQ/DQS(RDDQC) : PASS
5995 12:21:03.755422 TX DQ/DQS : PASS
5996 12:21:03.757824 RX DATLAT : PASS
5997 12:21:03.761354 RX DQ/DQS(Engine): PASS
5998 12:21:03.761832 TX OE : NO K
5999 12:21:03.764385 All Pass.
6000 12:21:03.764853
6001 12:21:03.765312 DramC Write-DBI off
6002 12:21:03.767714 PER_BANK_REFRESH: Hybrid Mode
6003 12:21:03.768186 TX_TRACKING: ON
6004 12:21:03.777934 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6005 12:21:03.781248 [FAST_K] Save calibration result to emmc
6006 12:21:03.784676 dramc_set_vcore_voltage set vcore to 650000
6007 12:21:03.787954 Read voltage for 400, 6
6008 12:21:03.788420 Vio18 = 0
6009 12:21:03.791759 Vcore = 650000
6010 12:21:03.792247 Vdram = 0
6011 12:21:03.792619 Vddq = 0
6012 12:21:03.794844 Vmddr = 0
6013 12:21:03.797736 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6014 12:21:03.804700 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6015 12:21:03.805398 MEM_TYPE=3, freq_sel=20
6016 12:21:03.808286 sv_algorithm_assistance_LP4_800
6017 12:21:03.811539 ============ PULL DRAM RESETB DOWN ============
6018 12:21:03.817786 ========== PULL DRAM RESETB DOWN end =========
6019 12:21:03.821196 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6020 12:21:03.824878 ===================================
6021 12:21:03.827963 LPDDR4 DRAM CONFIGURATION
6022 12:21:03.831272 ===================================
6023 12:21:03.831841 EX_ROW_EN[0] = 0x0
6024 12:21:03.834593 EX_ROW_EN[1] = 0x0
6025 12:21:03.835156 LP4Y_EN = 0x0
6026 12:21:03.837745 WORK_FSP = 0x0
6027 12:21:03.841255 WL = 0x2
6028 12:21:03.841868 RL = 0x2
6029 12:21:03.844353 BL = 0x2
6030 12:21:03.844817 RPST = 0x0
6031 12:21:03.848188 RD_PRE = 0x0
6032 12:21:03.848845 WR_PRE = 0x1
6033 12:21:03.851325 WR_PST = 0x0
6034 12:21:03.851790 DBI_WR = 0x0
6035 12:21:03.854589 DBI_RD = 0x0
6036 12:21:03.855150 OTF = 0x1
6037 12:21:03.858467 ===================================
6038 12:21:03.860806 ===================================
6039 12:21:03.864094 ANA top config
6040 12:21:03.867504 ===================================
6041 12:21:03.867969 DLL_ASYNC_EN = 0
6042 12:21:03.871300 ALL_SLAVE_EN = 1
6043 12:21:03.874078 NEW_RANK_MODE = 1
6044 12:21:03.877660 DLL_IDLE_MODE = 1
6045 12:21:03.878139 LP45_APHY_COMB_EN = 1
6046 12:21:03.880792 TX_ODT_DIS = 1
6047 12:21:03.884543 NEW_8X_MODE = 1
6048 12:21:03.887568 ===================================
6049 12:21:03.890646 ===================================
6050 12:21:03.894343 data_rate = 800
6051 12:21:03.897898 CKR = 1
6052 12:21:03.900920 DQ_P2S_RATIO = 4
6053 12:21:03.901404 ===================================
6054 12:21:03.904404 CA_P2S_RATIO = 4
6055 12:21:03.907688 DQ_CA_OPEN = 0
6056 12:21:03.910922 DQ_SEMI_OPEN = 1
6057 12:21:03.914385 CA_SEMI_OPEN = 1
6058 12:21:03.917378 CA_FULL_RATE = 0
6059 12:21:03.917843 DQ_CKDIV4_EN = 0
6060 12:21:03.921036 CA_CKDIV4_EN = 1
6061 12:21:03.924219 CA_PREDIV_EN = 0
6062 12:21:03.927686 PH8_DLY = 0
6063 12:21:03.931152 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6064 12:21:03.934261 DQ_AAMCK_DIV = 0
6065 12:21:03.934884 CA_AAMCK_DIV = 0
6066 12:21:03.937575 CA_ADMCK_DIV = 4
6067 12:21:03.940799 DQ_TRACK_CA_EN = 0
6068 12:21:03.944297 CA_PICK = 800
6069 12:21:03.947233 CA_MCKIO = 400
6070 12:21:03.950792 MCKIO_SEMI = 400
6071 12:21:03.953864 PLL_FREQ = 3016
6072 12:21:03.957743 DQ_UI_PI_RATIO = 32
6073 12:21:03.958307 CA_UI_PI_RATIO = 32
6074 12:21:03.960726 ===================================
6075 12:21:03.963997 ===================================
6076 12:21:03.967251 memory_type:LPDDR4
6077 12:21:03.970486 GP_NUM : 10
6078 12:21:03.971016 SRAM_EN : 1
6079 12:21:03.973649 MD32_EN : 0
6080 12:21:03.977509 ===================================
6081 12:21:03.980858 [ANA_INIT] >>>>>>>>>>>>>>
6082 12:21:03.983863 <<<<<< [CONFIGURE PHASE]: ANA_TX
6083 12:21:03.987628 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6084 12:21:03.990459 ===================================
6085 12:21:03.990932 data_rate = 800,PCW = 0X7400
6086 12:21:03.993898 ===================================
6087 12:21:03.997334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6088 12:21:04.003782 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6089 12:21:04.013681 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 12:21:04.020153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6091 12:21:04.024399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6092 12:21:04.027408 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6093 12:21:04.030883 [ANA_INIT] flow start
6094 12:21:04.031449 [ANA_INIT] PLL >>>>>>>>
6095 12:21:04.033916 [ANA_INIT] PLL <<<<<<<<
6096 12:21:04.036759 [ANA_INIT] MIDPI >>>>>>>>
6097 12:21:04.037267 [ANA_INIT] MIDPI <<<<<<<<
6098 12:21:04.040593 [ANA_INIT] DLL >>>>>>>>
6099 12:21:04.043472 [ANA_INIT] flow end
6100 12:21:04.046738 ============ LP4 DIFF to SE enter ============
6101 12:21:04.050367 ============ LP4 DIFF to SE exit ============
6102 12:21:04.053314 [ANA_INIT] <<<<<<<<<<<<<
6103 12:21:04.056862 [Flow] Enable top DCM control >>>>>
6104 12:21:04.059948 [Flow] Enable top DCM control <<<<<
6105 12:21:04.063591 Enable DLL master slave shuffle
6106 12:21:04.066749 ==============================================================
6107 12:21:04.070223 Gating Mode config
6108 12:21:04.076426 ==============================================================
6109 12:21:04.077030 Config description:
6110 12:21:04.086724 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6111 12:21:04.093055 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6112 12:21:04.096459 SELPH_MODE 0: By rank 1: By Phase
6113 12:21:04.103513 ==============================================================
6114 12:21:04.106257 GAT_TRACK_EN = 0
6115 12:21:04.109448 RX_GATING_MODE = 2
6116 12:21:04.112794 RX_GATING_TRACK_MODE = 2
6117 12:21:04.116055 SELPH_MODE = 1
6118 12:21:04.119368 PICG_EARLY_EN = 1
6119 12:21:04.122911 VALID_LAT_VALUE = 1
6120 12:21:04.126519 ==============================================================
6121 12:21:04.129598 Enter into Gating configuration >>>>
6122 12:21:04.132770 Exit from Gating configuration <<<<
6123 12:21:04.136048 Enter into DVFS_PRE_config >>>>>
6124 12:21:04.149741 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6125 12:21:04.152421 Exit from DVFS_PRE_config <<<<<
6126 12:21:04.155918 Enter into PICG configuration >>>>
6127 12:21:04.156387 Exit from PICG configuration <<<<
6128 12:21:04.159502 [RX_INPUT] configuration >>>>>
6129 12:21:04.162591 [RX_INPUT] configuration <<<<<
6130 12:21:04.169326 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6131 12:21:04.173160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6132 12:21:04.179550 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6133 12:21:04.185964 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6134 12:21:04.192454 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 12:21:04.199050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 12:21:04.202469 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6137 12:21:04.205595 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6138 12:21:04.208794 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6139 12:21:04.215938 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6140 12:21:04.218833 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6141 12:21:04.222604 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6142 12:21:04.225390 ===================================
6143 12:21:04.228780 LPDDR4 DRAM CONFIGURATION
6144 12:21:04.232595 ===================================
6145 12:21:04.235695 EX_ROW_EN[0] = 0x0
6146 12:21:04.236262 EX_ROW_EN[1] = 0x0
6147 12:21:04.238876 LP4Y_EN = 0x0
6148 12:21:04.239445 WORK_FSP = 0x0
6149 12:21:04.242544 WL = 0x2
6150 12:21:04.243106 RL = 0x2
6151 12:21:04.245645 BL = 0x2
6152 12:21:04.246113 RPST = 0x0
6153 12:21:04.249099 RD_PRE = 0x0
6154 12:21:04.249567 WR_PRE = 0x1
6155 12:21:04.252221 WR_PST = 0x0
6156 12:21:04.252684 DBI_WR = 0x0
6157 12:21:04.255477 DBI_RD = 0x0
6158 12:21:04.256046 OTF = 0x1
6159 12:21:04.259260 ===================================
6160 12:21:04.265424 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6161 12:21:04.268589 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6162 12:21:04.272207 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6163 12:21:04.275724 ===================================
6164 12:21:04.279044 LPDDR4 DRAM CONFIGURATION
6165 12:21:04.281630 ===================================
6166 12:21:04.285268 EX_ROW_EN[0] = 0x10
6167 12:21:04.285734 EX_ROW_EN[1] = 0x0
6168 12:21:04.288681 LP4Y_EN = 0x0
6169 12:21:04.289192 WORK_FSP = 0x0
6170 12:21:04.291805 WL = 0x2
6171 12:21:04.292268 RL = 0x2
6172 12:21:04.295446 BL = 0x2
6173 12:21:04.296039 RPST = 0x0
6174 12:21:04.298486 RD_PRE = 0x0
6175 12:21:04.298949 WR_PRE = 0x1
6176 12:21:04.301616 WR_PST = 0x0
6177 12:21:04.302197 DBI_WR = 0x0
6178 12:21:04.305217 DBI_RD = 0x0
6179 12:21:04.305676 OTF = 0x1
6180 12:21:04.308390 ===================================
6181 12:21:04.315259 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6182 12:21:04.320020 nWR fixed to 30
6183 12:21:04.323231 [ModeRegInit_LP4] CH0 RK0
6184 12:21:04.323800 [ModeRegInit_LP4] CH0 RK1
6185 12:21:04.326951 [ModeRegInit_LP4] CH1 RK0
6186 12:21:04.329592 [ModeRegInit_LP4] CH1 RK1
6187 12:21:04.330061 match AC timing 19
6188 12:21:04.337136 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6189 12:21:04.339615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6190 12:21:04.343653 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6191 12:21:04.349828 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6192 12:21:04.353250 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6193 12:21:04.353815 ==
6194 12:21:04.356452 Dram Type= 6, Freq= 0, CH_0, rank 0
6195 12:21:04.360028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6196 12:21:04.360642 ==
6197 12:21:04.366787 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6198 12:21:04.373191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6199 12:21:04.376689 [CA 0] Center 36 (8~64) winsize 57
6200 12:21:04.379932 [CA 1] Center 36 (8~64) winsize 57
6201 12:21:04.382852 [CA 2] Center 36 (8~64) winsize 57
6202 12:21:04.383327 [CA 3] Center 36 (8~64) winsize 57
6203 12:21:04.386765 [CA 4] Center 36 (8~64) winsize 57
6204 12:21:04.390085 [CA 5] Center 36 (8~64) winsize 57
6205 12:21:04.390660
6206 12:21:04.393139 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6207 12:21:04.396821
6208 12:21:04.399760 [CATrainingPosCal] consider 1 rank data
6209 12:21:04.400338 u2DelayCellTimex100 = 270/100 ps
6210 12:21:04.406122 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 12:21:04.409524 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 12:21:04.412991 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 12:21:04.416238 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 12:21:04.419549 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 12:21:04.423285 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 12:21:04.423757
6217 12:21:04.426392 CA PerBit enable=1, Macro0, CA PI delay=36
6218 12:21:04.426866
6219 12:21:04.429902 [CBTSetCACLKResult] CA Dly = 36
6220 12:21:04.430377 CS Dly: 1 (0~32)
6221 12:21:04.433094 ==
6222 12:21:04.436657 Dram Type= 6, Freq= 0, CH_0, rank 1
6223 12:21:04.440296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 12:21:04.440775 ==
6225 12:21:04.443320 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 12:21:04.450344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6227 12:21:04.453558 [CA 0] Center 36 (8~64) winsize 57
6228 12:21:04.456761 [CA 1] Center 36 (8~64) winsize 57
6229 12:21:04.460117 [CA 2] Center 36 (8~64) winsize 57
6230 12:21:04.463118 [CA 3] Center 36 (8~64) winsize 57
6231 12:21:04.466413 [CA 4] Center 36 (8~64) winsize 57
6232 12:21:04.469631 [CA 5] Center 36 (8~64) winsize 57
6233 12:21:04.470204
6234 12:21:04.473462 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6235 12:21:04.474039
6236 12:21:04.476454 [CATrainingPosCal] consider 2 rank data
6237 12:21:04.479786 u2DelayCellTimex100 = 270/100 ps
6238 12:21:04.483030 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 12:21:04.486286 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 12:21:04.489644 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 12:21:04.493129 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 12:21:04.499344 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 12:21:04.502660 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:21:04.503157
6245 12:21:04.506293 CA PerBit enable=1, Macro0, CA PI delay=36
6246 12:21:04.506762
6247 12:21:04.509252 [CBTSetCACLKResult] CA Dly = 36
6248 12:21:04.509727 CS Dly: 1 (0~32)
6249 12:21:04.510100
6250 12:21:04.512910 ----->DramcWriteLeveling(PI) begin...
6251 12:21:04.513440 ==
6252 12:21:04.516372 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 12:21:04.523024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 12:21:04.523528 ==
6255 12:21:04.525935 Write leveling (Byte 0): 40 => 8
6256 12:21:04.526402 Write leveling (Byte 1): 32 => 0
6257 12:21:04.529165 DramcWriteLeveling(PI) end<-----
6258 12:21:04.529632
6259 12:21:04.529998 ==
6260 12:21:04.532745 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 12:21:04.539326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 12:21:04.539802 ==
6263 12:21:04.542923 [Gating] SW mode calibration
6264 12:21:04.549280 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6265 12:21:04.553011 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6266 12:21:04.559469 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 12:21:04.562645 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 12:21:04.566359 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 12:21:04.569566 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6270 12:21:04.576358 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 12:21:04.579841 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 12:21:04.582968 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 12:21:04.589581 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 12:21:04.592681 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 12:21:04.596082 Total UI for P1: 0, mck2ui 16
6276 12:21:04.599390 best dqsien dly found for B0: ( 0, 14, 24)
6277 12:21:04.602611 Total UI for P1: 0, mck2ui 16
6278 12:21:04.606223 best dqsien dly found for B1: ( 0, 14, 24)
6279 12:21:04.609417 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6280 12:21:04.613353 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6281 12:21:04.613933
6282 12:21:04.615889 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6283 12:21:04.619554 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 12:21:04.622653 [Gating] SW calibration Done
6285 12:21:04.623128 ==
6286 12:21:04.626132 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 12:21:04.632704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 12:21:04.633231 ==
6289 12:21:04.633605 RX Vref Scan: 0
6290 12:21:04.633962
6291 12:21:04.636249 RX Vref 0 -> 0, step: 1
6292 12:21:04.636722
6293 12:21:04.639342 RX Delay -410 -> 252, step: 16
6294 12:21:04.642680 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6295 12:21:04.645841 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6296 12:21:04.652292 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6297 12:21:04.655973 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6298 12:21:04.659452 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6299 12:21:04.662486 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6300 12:21:04.669100 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6301 12:21:04.672091 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6302 12:21:04.675842 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6303 12:21:04.678973 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6304 12:21:04.682343 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6305 12:21:04.688749 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6306 12:21:04.692065 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6307 12:21:04.695633 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6308 12:21:04.702291 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6309 12:21:04.706319 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6310 12:21:04.706885 ==
6311 12:21:04.709224 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 12:21:04.712479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 12:21:04.712972 ==
6314 12:21:04.715945 DQS Delay:
6315 12:21:04.716403 DQS0 = 19, DQS1 = 43
6316 12:21:04.716761 DQM Delay:
6317 12:21:04.718731 DQM0 = 5, DQM1 = 14
6318 12:21:04.719191 DQ Delay:
6319 12:21:04.722570 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6320 12:21:04.725662 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6321 12:21:04.729066 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6322 12:21:04.732136 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6323 12:21:04.732699
6324 12:21:04.733130
6325 12:21:04.733476 ==
6326 12:21:04.735777 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 12:21:04.738913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 12:21:04.739475 ==
6329 12:21:04.742144
6330 12:21:04.742927
6331 12:21:04.743643 TX Vref Scan disable
6332 12:21:04.745113 == TX Byte 0 ==
6333 12:21:04.748604 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 12:21:04.752031 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 12:21:04.755436 == TX Byte 1 ==
6336 12:21:04.759037 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6337 12:21:04.762033 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6338 12:21:04.762497 ==
6339 12:21:04.765595 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 12:21:04.771965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 12:21:04.772666 ==
6342 12:21:04.773179
6343 12:21:04.773557
6344 12:21:04.773883 TX Vref Scan disable
6345 12:21:04.775576 == TX Byte 0 ==
6346 12:21:04.778990 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 12:21:04.781581 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 12:21:04.785300 == TX Byte 1 ==
6349 12:21:04.788406 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6350 12:21:04.791718 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6351 12:21:04.792178
6352 12:21:04.795193 [DATLAT]
6353 12:21:04.795647 Freq=400, CH0 RK0
6354 12:21:04.796010
6355 12:21:04.798853 DATLAT Default: 0xf
6356 12:21:04.799404 0, 0xFFFF, sum = 0
6357 12:21:04.801589 1, 0xFFFF, sum = 0
6358 12:21:04.802059 2, 0xFFFF, sum = 0
6359 12:21:04.805002 3, 0xFFFF, sum = 0
6360 12:21:04.805553 4, 0xFFFF, sum = 0
6361 12:21:04.808582 5, 0xFFFF, sum = 0
6362 12:21:04.809236 6, 0xFFFF, sum = 0
6363 12:21:04.811547 7, 0xFFFF, sum = 0
6364 12:21:04.812012 8, 0xFFFF, sum = 0
6365 12:21:04.815163 9, 0xFFFF, sum = 0
6366 12:21:04.815723 10, 0xFFFF, sum = 0
6367 12:21:04.818499 11, 0xFFFF, sum = 0
6368 12:21:04.821572 12, 0xFFFF, sum = 0
6369 12:21:04.822038 13, 0x0, sum = 1
6370 12:21:04.825132 14, 0x0, sum = 2
6371 12:21:04.825688 15, 0x0, sum = 3
6372 12:21:04.826060 16, 0x0, sum = 4
6373 12:21:04.828586 best_step = 14
6374 12:21:04.829187
6375 12:21:04.829557 ==
6376 12:21:04.831926 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 12:21:04.834776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 12:21:04.835255 ==
6379 12:21:04.838128 RX Vref Scan: 1
6380 12:21:04.838822
6381 12:21:04.839285 RX Vref 0 -> 0, step: 1
6382 12:21:04.841609
6383 12:21:04.842065 RX Delay -327 -> 252, step: 8
6384 12:21:04.842431
6385 12:21:04.845096 Set Vref, RX VrefLevel [Byte0]: 58
6386 12:21:04.848039 [Byte1]: 50
6387 12:21:04.853314
6388 12:21:04.853861 Final RX Vref Byte 0 = 58 to rank0
6389 12:21:04.856542 Final RX Vref Byte 1 = 50 to rank0
6390 12:21:04.859896 Final RX Vref Byte 0 = 58 to rank1
6391 12:21:04.863340 Final RX Vref Byte 1 = 50 to rank1==
6392 12:21:04.866356 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 12:21:04.873056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 12:21:04.873518 ==
6395 12:21:04.873879 DQS Delay:
6396 12:21:04.876404 DQS0 = 28, DQS1 = 48
6397 12:21:04.876863 DQM Delay:
6398 12:21:04.877302 DQM0 = 12, DQM1 = 15
6399 12:21:04.879599 DQ Delay:
6400 12:21:04.883320 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6401 12:21:04.883778 DQ4 =12, DQ5 =0, DQ6 =24, DQ7 =20
6402 12:21:04.886129 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6403 12:21:04.889444 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6404 12:21:04.893028
6405 12:21:04.893580
6406 12:21:04.899947 [DQSOSCAuto] RK0, (LSB)MR18= 0xaca5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6407 12:21:04.902938 CH0 RK0: MR19=C0C, MR18=ACA5
6408 12:21:04.909355 CH0_RK0: MR19=0xC0C, MR18=0xACA5, DQSOSC=388, MR23=63, INC=392, DEC=261
6409 12:21:04.909821 ==
6410 12:21:04.912670 Dram Type= 6, Freq= 0, CH_0, rank 1
6411 12:21:04.916471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 12:21:04.916975 ==
6413 12:21:04.919652 [Gating] SW mode calibration
6414 12:21:04.926595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6415 12:21:04.933117 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6416 12:21:04.936279 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6417 12:21:04.939787 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 12:21:04.945677 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 12:21:04.948774 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 12:21:04.952329 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 12:21:04.959176 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 12:21:04.962081 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 12:21:04.965475 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 12:21:04.972047 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 12:21:04.972523 Total UI for P1: 0, mck2ui 16
6426 12:21:04.978869 best dqsien dly found for B0: ( 0, 14, 24)
6427 12:21:04.979284 Total UI for P1: 0, mck2ui 16
6428 12:21:04.985178 best dqsien dly found for B1: ( 0, 14, 24)
6429 12:21:04.989050 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6430 12:21:04.992119 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6431 12:21:04.992585
6432 12:21:04.995581 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6433 12:21:04.999005 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 12:21:05.002426 [Gating] SW calibration Done
6435 12:21:05.003009 ==
6436 12:21:05.005642 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 12:21:05.009132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 12:21:05.009783 ==
6439 12:21:05.011825 RX Vref Scan: 0
6440 12:21:05.012478
6441 12:21:05.012850 RX Vref 0 -> 0, step: 1
6442 12:21:05.013224
6443 12:21:05.015533 RX Delay -410 -> 252, step: 16
6444 12:21:05.022253 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6445 12:21:05.025134 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6446 12:21:05.028539 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6447 12:21:05.032206 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6448 12:21:05.038701 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6449 12:21:05.041488 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6450 12:21:05.045013 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6451 12:21:05.048536 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6452 12:21:05.055113 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6453 12:21:05.058664 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6454 12:21:05.061568 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6455 12:21:05.065161 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6456 12:21:05.071781 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6457 12:21:05.074966 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6458 12:21:05.078240 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6459 12:21:05.084424 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6460 12:21:05.084891 ==
6461 12:21:05.088076 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 12:21:05.091370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 12:21:05.091841 ==
6464 12:21:05.092209 DQS Delay:
6465 12:21:05.094794 DQS0 = 27, DQS1 = 43
6466 12:21:05.095265 DQM Delay:
6467 12:21:05.097875 DQM0 = 10, DQM1 = 15
6468 12:21:05.098346 DQ Delay:
6469 12:21:05.101526 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6470 12:21:05.105071 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6471 12:21:05.107865 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6472 12:21:05.110986 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6473 12:21:05.111609
6474 12:21:05.112059
6475 12:21:05.112412 ==
6476 12:21:05.115043 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 12:21:05.118253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 12:21:05.118829 ==
6479 12:21:05.119205
6480 12:21:05.119542
6481 12:21:05.121092 TX Vref Scan disable
6482 12:21:05.121561 == TX Byte 0 ==
6483 12:21:05.128112 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6484 12:21:05.130933 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6485 12:21:05.131408 == TX Byte 1 ==
6486 12:21:05.137655 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6487 12:21:05.140903 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6488 12:21:05.141525 ==
6489 12:21:05.144447 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 12:21:05.147460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 12:21:05.147934 ==
6492 12:21:05.148304
6493 12:21:05.148642
6494 12:21:05.151114 TX Vref Scan disable
6495 12:21:05.154527 == TX Byte 0 ==
6496 12:21:05.157698 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6497 12:21:05.160897 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6498 12:21:05.161507 == TX Byte 1 ==
6499 12:21:05.167330 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6500 12:21:05.170578 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6501 12:21:05.171051
6502 12:21:05.171421 [DATLAT]
6503 12:21:05.173891 Freq=400, CH0 RK1
6504 12:21:05.174360
6505 12:21:05.174723 DATLAT Default: 0xe
6506 12:21:05.177484 0, 0xFFFF, sum = 0
6507 12:21:05.178076 1, 0xFFFF, sum = 0
6508 12:21:05.180533 2, 0xFFFF, sum = 0
6509 12:21:05.181056 3, 0xFFFF, sum = 0
6510 12:21:05.184190 4, 0xFFFF, sum = 0
6511 12:21:05.187471 5, 0xFFFF, sum = 0
6512 12:21:05.188053 6, 0xFFFF, sum = 0
6513 12:21:05.190283 7, 0xFFFF, sum = 0
6514 12:21:05.190737 8, 0xFFFF, sum = 0
6515 12:21:05.193710 9, 0xFFFF, sum = 0
6516 12:21:05.194183 10, 0xFFFF, sum = 0
6517 12:21:05.197147 11, 0xFFFF, sum = 0
6518 12:21:05.197623 12, 0xFFFF, sum = 0
6519 12:21:05.200327 13, 0x0, sum = 1
6520 12:21:05.200800 14, 0x0, sum = 2
6521 12:21:05.203734 15, 0x0, sum = 3
6522 12:21:05.204210 16, 0x0, sum = 4
6523 12:21:05.206736 best_step = 14
6524 12:21:05.207201
6525 12:21:05.207567 ==
6526 12:21:05.210752 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 12:21:05.213734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 12:21:05.214209 ==
6529 12:21:05.214582 RX Vref Scan: 0
6530 12:21:05.216749
6531 12:21:05.217259 RX Vref 0 -> 0, step: 1
6532 12:21:05.217635
6533 12:21:05.219979 RX Delay -327 -> 252, step: 8
6534 12:21:05.227952 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6535 12:21:05.230758 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6536 12:21:05.233954 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6537 12:21:05.237409 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6538 12:21:05.243990 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6539 12:21:05.247492 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6540 12:21:05.250700 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6541 12:21:05.254161 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6542 12:21:05.260625 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6543 12:21:05.264313 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6544 12:21:05.267971 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6545 12:21:05.270600 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6546 12:21:05.277492 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6547 12:21:05.281168 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6548 12:21:05.283890 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6549 12:21:05.290917 iDelay=217, Bit 15, Center -20 (-247 ~ 208) 456
6550 12:21:05.291478 ==
6551 12:21:05.294198 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 12:21:05.297313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 12:21:05.297787 ==
6554 12:21:05.298158 DQS Delay:
6555 12:21:05.300694 DQS0 = 28, DQS1 = 44
6556 12:21:05.301228 DQM Delay:
6557 12:21:05.303881 DQM0 = 9, DQM1 = 16
6558 12:21:05.304345 DQ Delay:
6559 12:21:05.307274 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6560 12:21:05.310590 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6561 12:21:05.314210 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6562 12:21:05.317560 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6563 12:21:05.318200
6564 12:21:05.318582
6565 12:21:05.323988 [DQSOSCAuto] RK1, (LSB)MR18= 0xb66b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6566 12:21:05.327635 CH0 RK1: MR19=C0C, MR18=B66B
6567 12:21:05.333990 CH0_RK1: MR19=0xC0C, MR18=0xB66B, DQSOSC=387, MR23=63, INC=394, DEC=262
6568 12:21:05.337611 [RxdqsGatingPostProcess] freq 400
6569 12:21:05.341027 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6570 12:21:05.343944 best DQS0 dly(2T, 0.5T) = (0, 10)
6571 12:21:05.346968 best DQS1 dly(2T, 0.5T) = (0, 10)
6572 12:21:05.350386 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6573 12:21:05.353891 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6574 12:21:05.357656 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 12:21:05.360673 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 12:21:05.363992 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 12:21:05.367035 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 12:21:05.370704 Pre-setting of DQS Precalculation
6579 12:21:05.374290 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6580 12:21:05.377818 ==
6581 12:21:05.378407 Dram Type= 6, Freq= 0, CH_1, rank 0
6582 12:21:05.384169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 12:21:05.384765 ==
6584 12:21:05.387208 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6585 12:21:05.393839 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6586 12:21:05.396877 [CA 0] Center 36 (8~64) winsize 57
6587 12:21:05.400219 [CA 1] Center 36 (8~64) winsize 57
6588 12:21:05.403910 [CA 2] Center 36 (8~64) winsize 57
6589 12:21:05.407005 [CA 3] Center 36 (8~64) winsize 57
6590 12:21:05.410386 [CA 4] Center 36 (8~64) winsize 57
6591 12:21:05.413718 [CA 5] Center 36 (8~64) winsize 57
6592 12:21:05.414252
6593 12:21:05.416874 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6594 12:21:05.417519
6595 12:21:05.420446 [CATrainingPosCal] consider 1 rank data
6596 12:21:05.423795 u2DelayCellTimex100 = 270/100 ps
6597 12:21:05.427242 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 12:21:05.430242 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 12:21:05.434025 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 12:21:05.437181 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 12:21:05.440681 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 12:21:05.447096 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 12:21:05.447683
6604 12:21:05.450448 CA PerBit enable=1, Macro0, CA PI delay=36
6605 12:21:05.450936
6606 12:21:05.453518 [CBTSetCACLKResult] CA Dly = 36
6607 12:21:05.454005 CS Dly: 1 (0~32)
6608 12:21:05.454489 ==
6609 12:21:05.457038 Dram Type= 6, Freq= 0, CH_1, rank 1
6610 12:21:05.460156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 12:21:05.463937 ==
6612 12:21:05.466710 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 12:21:05.473821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6614 12:21:05.477082 [CA 0] Center 36 (8~64) winsize 57
6615 12:21:05.480268 [CA 1] Center 36 (8~64) winsize 57
6616 12:21:05.483407 [CA 2] Center 36 (8~64) winsize 57
6617 12:21:05.486458 [CA 3] Center 36 (8~64) winsize 57
6618 12:21:05.490162 [CA 4] Center 36 (8~64) winsize 57
6619 12:21:05.493246 [CA 5] Center 36 (8~64) winsize 57
6620 12:21:05.493734
6621 12:21:05.496730 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6622 12:21:05.497265
6623 12:21:05.500076 [CATrainingPosCal] consider 2 rank data
6624 12:21:05.503505 u2DelayCellTimex100 = 270/100 ps
6625 12:21:05.506406 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 12:21:05.509867 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 12:21:05.513464 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 12:21:05.516632 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 12:21:05.520045 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 12:21:05.523181 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:21:05.523655
6632 12:21:05.529625 CA PerBit enable=1, Macro0, CA PI delay=36
6633 12:21:05.530101
6634 12:21:05.530498 [CBTSetCACLKResult] CA Dly = 36
6635 12:21:05.533241 CS Dly: 1 (0~32)
6636 12:21:05.533863
6637 12:21:05.536529 ----->DramcWriteLeveling(PI) begin...
6638 12:21:05.537158 ==
6639 12:21:05.540266 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 12:21:05.543376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 12:21:05.543961 ==
6642 12:21:05.546367 Write leveling (Byte 0): 40 => 8
6643 12:21:05.549587 Write leveling (Byte 1): 32 => 0
6644 12:21:05.553040 DramcWriteLeveling(PI) end<-----
6645 12:21:05.553545
6646 12:21:05.553923 ==
6647 12:21:05.556381 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 12:21:05.560358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 12:21:05.560969 ==
6650 12:21:05.563397 [Gating] SW mode calibration
6651 12:21:05.569745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6652 12:21:05.577081 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6653 12:21:05.580407 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6654 12:21:05.586992 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 12:21:05.589964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 12:21:05.593785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 12:21:05.596601 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 12:21:05.603151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 12:21:05.606619 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 12:21:05.610051 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 12:21:05.616557 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 12:21:05.620166 Total UI for P1: 0, mck2ui 16
6663 12:21:05.623228 best dqsien dly found for B0: ( 0, 14, 24)
6664 12:21:05.623705 Total UI for P1: 0, mck2ui 16
6665 12:21:05.629654 best dqsien dly found for B1: ( 0, 14, 24)
6666 12:21:05.633135 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6667 12:21:05.636285 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6668 12:21:05.636758
6669 12:21:05.640060 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6670 12:21:05.642989 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 12:21:05.646458 [Gating] SW calibration Done
6672 12:21:05.647034 ==
6673 12:21:05.649860 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 12:21:05.653380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 12:21:05.653866 ==
6676 12:21:05.656437 RX Vref Scan: 0
6677 12:21:05.657041
6678 12:21:05.659604 RX Vref 0 -> 0, step: 1
6679 12:21:05.660175
6680 12:21:05.660553 RX Delay -410 -> 252, step: 16
6681 12:21:05.666148 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6682 12:21:05.669600 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6683 12:21:05.673204 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6684 12:21:05.676372 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6685 12:21:05.682808 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6686 12:21:05.686194 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6687 12:21:05.689748 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6688 12:21:05.692870 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6689 12:21:05.699459 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6690 12:21:05.702918 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6691 12:21:05.706188 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6692 12:21:05.709530 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6693 12:21:05.716484 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6694 12:21:05.719594 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6695 12:21:05.722981 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6696 12:21:05.729514 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6697 12:21:05.730000 ==
6698 12:21:05.733208 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 12:21:05.736188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 12:21:05.736661 ==
6701 12:21:05.737077 DQS Delay:
6702 12:21:05.739780 DQS0 = 27, DQS1 = 43
6703 12:21:05.740538 DQM Delay:
6704 12:21:05.742939 DQM0 = 5, DQM1 = 15
6705 12:21:05.743359 DQ Delay:
6706 12:21:05.746036 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6707 12:21:05.749575 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6708 12:21:05.752727 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6709 12:21:05.756522 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6710 12:21:05.757132
6711 12:21:05.757512
6712 12:21:05.757854 ==
6713 12:21:05.759618 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 12:21:05.762818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 12:21:05.763306 ==
6716 12:21:05.763707
6717 12:21:05.764050
6718 12:21:05.766363 TX Vref Scan disable
6719 12:21:05.766826 == TX Byte 0 ==
6720 12:21:05.773104 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 12:21:05.776139 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 12:21:05.776563 == TX Byte 1 ==
6723 12:21:05.783157 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6724 12:21:05.786480 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6725 12:21:05.787251 ==
6726 12:21:05.789639 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 12:21:05.793281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 12:21:05.793908 ==
6729 12:21:05.794253
6730 12:21:05.794560
6731 12:21:05.796148 TX Vref Scan disable
6732 12:21:05.796570 == TX Byte 0 ==
6733 12:21:05.803397 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 12:21:05.806263 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 12:21:05.806882 == TX Byte 1 ==
6736 12:21:05.813292 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6737 12:21:05.816042 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6738 12:21:05.816484
6739 12:21:05.816925 [DATLAT]
6740 12:21:05.820342 Freq=400, CH1 RK0
6741 12:21:05.820890
6742 12:21:05.821383 DATLAT Default: 0xf
6743 12:21:05.823017 0, 0xFFFF, sum = 0
6744 12:21:05.823465 1, 0xFFFF, sum = 0
6745 12:21:05.826232 2, 0xFFFF, sum = 0
6746 12:21:05.826721 3, 0xFFFF, sum = 0
6747 12:21:05.829655 4, 0xFFFF, sum = 0
6748 12:21:05.830149 5, 0xFFFF, sum = 0
6749 12:21:05.832964 6, 0xFFFF, sum = 0
6750 12:21:05.833460 7, 0xFFFF, sum = 0
6751 12:21:05.836098 8, 0xFFFF, sum = 0
6752 12:21:05.836694 9, 0xFFFF, sum = 0
6753 12:21:05.839497 10, 0xFFFF, sum = 0
6754 12:21:05.842779 11, 0xFFFF, sum = 0
6755 12:21:05.843230 12, 0xFFFF, sum = 0
6756 12:21:05.846205 13, 0x0, sum = 1
6757 12:21:05.846699 14, 0x0, sum = 2
6758 12:21:05.847192 15, 0x0, sum = 3
6759 12:21:05.849319 16, 0x0, sum = 4
6760 12:21:05.849809 best_step = 14
6761 12:21:05.850296
6762 12:21:05.852644 ==
6763 12:21:05.856424 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 12:21:05.859376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 12:21:05.859828 ==
6766 12:21:05.860169 RX Vref Scan: 1
6767 12:21:05.860488
6768 12:21:05.862667 RX Vref 0 -> 0, step: 1
6769 12:21:05.863093
6770 12:21:05.865957 RX Delay -327 -> 252, step: 8
6771 12:21:05.866388
6772 12:21:05.869469 Set Vref, RX VrefLevel [Byte0]: 52
6773 12:21:05.872656 [Byte1]: 53
6774 12:21:05.876031
6775 12:21:05.876502 Final RX Vref Byte 0 = 52 to rank0
6776 12:21:05.879928 Final RX Vref Byte 1 = 53 to rank0
6777 12:21:05.882793 Final RX Vref Byte 0 = 52 to rank1
6778 12:21:05.885945 Final RX Vref Byte 1 = 53 to rank1==
6779 12:21:05.889514 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 12:21:05.896128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 12:21:05.896698 ==
6782 12:21:05.897209 DQS Delay:
6783 12:21:05.899862 DQS0 = 32, DQS1 = 40
6784 12:21:05.900431 DQM Delay:
6785 12:21:05.900805 DQM0 = 11, DQM1 = 12
6786 12:21:05.903044 DQ Delay:
6787 12:21:05.905995 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6788 12:21:05.906681 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6789 12:21:05.909147 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6790 12:21:05.912318 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =16
6791 12:21:05.912787
6792 12:21:05.915710
6793 12:21:05.922274 [DQSOSCAuto] RK0, (LSB)MR18= 0x8fca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6794 12:21:05.925692 CH1 RK0: MR19=C0C, MR18=8FCA
6795 12:21:05.932798 CH1_RK0: MR19=0xC0C, MR18=0x8FCA, DQSOSC=384, MR23=63, INC=400, DEC=267
6796 12:21:05.933420 ==
6797 12:21:05.935710 Dram Type= 6, Freq= 0, CH_1, rank 1
6798 12:21:05.939209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 12:21:05.939778 ==
6800 12:21:05.942087 [Gating] SW mode calibration
6801 12:21:05.949034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6802 12:21:05.955942 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6803 12:21:05.959370 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6804 12:21:05.962440 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 12:21:05.968905 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 12:21:05.972329 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 12:21:05.976031 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 12:21:05.978979 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 12:21:05.985862 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 12:21:05.988836 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 12:21:05.992793 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 12:21:05.995627 Total UI for P1: 0, mck2ui 16
6813 12:21:05.999641 best dqsien dly found for B0: ( 0, 14, 24)
6814 12:21:06.002376 Total UI for P1: 0, mck2ui 16
6815 12:21:06.005582 best dqsien dly found for B1: ( 0, 14, 24)
6816 12:21:06.008773 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6817 12:21:06.012516 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6818 12:21:06.015994
6819 12:21:06.019005 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6820 12:21:06.022649 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 12:21:06.025529 [Gating] SW calibration Done
6822 12:21:06.025996 ==
6823 12:21:06.029061 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 12:21:06.032527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 12:21:06.033147 ==
6826 12:21:06.033526 RX Vref Scan: 0
6827 12:21:06.036052
6828 12:21:06.036613 RX Vref 0 -> 0, step: 1
6829 12:21:06.037032
6830 12:21:06.038362 RX Delay -410 -> 252, step: 16
6831 12:21:06.042252 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6832 12:21:06.048482 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6833 12:21:06.051916 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6834 12:21:06.055435 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6835 12:21:06.058892 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6836 12:21:06.065496 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6837 12:21:06.068420 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6838 12:21:06.071854 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6839 12:21:06.075164 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6840 12:21:06.081886 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6841 12:21:06.086032 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6842 12:21:06.088434 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6843 12:21:06.092080 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6844 12:21:06.098427 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6845 12:21:06.101716 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6846 12:21:06.105535 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6847 12:21:06.106168 ==
6848 12:21:06.108721 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 12:21:06.111916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 12:21:06.115063 ==
6851 12:21:06.115545 DQS Delay:
6852 12:21:06.115929 DQS0 = 35, DQS1 = 43
6853 12:21:06.119140 DQM Delay:
6854 12:21:06.119706 DQM0 = 18, DQM1 = 18
6855 12:21:06.121620 DQ Delay:
6856 12:21:06.125194 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6857 12:21:06.125775 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6858 12:21:06.128640 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6859 12:21:06.131759 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6860 12:21:06.135341
6861 12:21:06.135906
6862 12:21:06.136277 ==
6863 12:21:06.138488 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 12:21:06.141757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 12:21:06.142327 ==
6866 12:21:06.142694
6867 12:21:06.143031
6868 12:21:06.145111 TX Vref Scan disable
6869 12:21:06.145573 == TX Byte 0 ==
6870 12:21:06.148434 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6871 12:21:06.155292 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6872 12:21:06.155862 == TX Byte 1 ==
6873 12:21:06.157970 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6874 12:21:06.165068 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6875 12:21:06.165613 ==
6876 12:21:06.168033 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 12:21:06.171288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 12:21:06.171772 ==
6879 12:21:06.172157
6880 12:21:06.172737
6881 12:21:06.174701 TX Vref Scan disable
6882 12:21:06.175260 == TX Byte 0 ==
6883 12:21:06.181299 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6884 12:21:06.184917 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6885 12:21:06.185529 == TX Byte 1 ==
6886 12:21:06.188007 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6887 12:21:06.194625 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6888 12:21:06.195193
6889 12:21:06.195562 [DATLAT]
6890 12:21:06.197788 Freq=400, CH1 RK1
6891 12:21:06.198378
6892 12:21:06.198752 DATLAT Default: 0xe
6893 12:21:06.200878 0, 0xFFFF, sum = 0
6894 12:21:06.201394 1, 0xFFFF, sum = 0
6895 12:21:06.204525 2, 0xFFFF, sum = 0
6896 12:21:06.205138 3, 0xFFFF, sum = 0
6897 12:21:06.208111 4, 0xFFFF, sum = 0
6898 12:21:06.208679 5, 0xFFFF, sum = 0
6899 12:21:06.210998 6, 0xFFFF, sum = 0
6900 12:21:06.211786 7, 0xFFFF, sum = 0
6901 12:21:06.214590 8, 0xFFFF, sum = 0
6902 12:21:06.215153 9, 0xFFFF, sum = 0
6903 12:21:06.217749 10, 0xFFFF, sum = 0
6904 12:21:06.218222 11, 0xFFFF, sum = 0
6905 12:21:06.220795 12, 0xFFFF, sum = 0
6906 12:21:06.221312 13, 0x0, sum = 1
6907 12:21:06.224036 14, 0x0, sum = 2
6908 12:21:06.224506 15, 0x0, sum = 3
6909 12:21:06.227953 16, 0x0, sum = 4
6910 12:21:06.228528 best_step = 14
6911 12:21:06.228900
6912 12:21:06.229300 ==
6913 12:21:06.231365 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 12:21:06.237677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 12:21:06.238244 ==
6916 12:21:06.238610 RX Vref Scan: 0
6917 12:21:06.238954
6918 12:21:06.240835 RX Vref 0 -> 0, step: 1
6919 12:21:06.241346
6920 12:21:06.244178 RX Delay -327 -> 252, step: 8
6921 12:21:06.251021 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6922 12:21:06.254027 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6923 12:21:06.257469 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6924 12:21:06.260684 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6925 12:21:06.267200 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6926 12:21:06.270664 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6927 12:21:06.273639 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6928 12:21:06.277218 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6929 12:21:06.283883 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6930 12:21:06.287393 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6931 12:21:06.290487 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6932 12:21:06.294282 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
6933 12:21:06.300325 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6934 12:21:06.304275 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6935 12:21:06.307119 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6936 12:21:06.313761 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
6937 12:21:06.314190 ==
6938 12:21:06.317183 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 12:21:06.320455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 12:21:06.320886 ==
6941 12:21:06.321257 DQS Delay:
6942 12:21:06.323499 DQS0 = 32, DQS1 = 36
6943 12:21:06.323926 DQM Delay:
6944 12:21:06.327113 DQM0 = 11, DQM1 = 10
6945 12:21:06.327540 DQ Delay:
6946 12:21:06.330453 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6947 12:21:06.333627 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
6948 12:21:06.337024 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6949 12:21:06.340841 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6950 12:21:06.341419
6951 12:21:06.341762
6952 12:21:06.347538 [DQSOSCAuto] RK1, (LSB)MR18= 0xab55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6953 12:21:06.351081 CH1 RK1: MR19=C0C, MR18=AB55
6954 12:21:06.357217 CH1_RK1: MR19=0xC0C, MR18=0xAB55, DQSOSC=388, MR23=63, INC=392, DEC=261
6955 12:21:06.360509 [RxdqsGatingPostProcess] freq 400
6956 12:21:06.363810 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6957 12:21:06.367696 best DQS0 dly(2T, 0.5T) = (0, 10)
6958 12:21:06.370475 best DQS1 dly(2T, 0.5T) = (0, 10)
6959 12:21:06.373747 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6960 12:21:06.377049 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6961 12:21:06.380453 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 12:21:06.383807 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 12:21:06.387405 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 12:21:06.390660 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 12:21:06.393845 Pre-setting of DQS Precalculation
6966 12:21:06.397591 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6967 12:21:06.407359 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6968 12:21:06.414772 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6969 12:21:06.415311
6970 12:21:06.415690
6971 12:21:06.417552 [Calibration Summary] 800 Mbps
6972 12:21:06.418025 CH 0, Rank 0
6973 12:21:06.420440 SW Impedance : PASS
6974 12:21:06.420914 DUTY Scan : NO K
6975 12:21:06.423529 ZQ Calibration : PASS
6976 12:21:06.427200 Jitter Meter : NO K
6977 12:21:06.427632 CBT Training : PASS
6978 12:21:06.430663 Write leveling : PASS
6979 12:21:06.433540 RX DQS gating : PASS
6980 12:21:06.433969 RX DQ/DQS(RDDQC) : PASS
6981 12:21:06.436746 TX DQ/DQS : PASS
6982 12:21:06.440575 RX DATLAT : PASS
6983 12:21:06.441038 RX DQ/DQS(Engine): PASS
6984 12:21:06.443733 TX OE : NO K
6985 12:21:06.444160 All Pass.
6986 12:21:06.444495
6987 12:21:06.447039 CH 0, Rank 1
6988 12:21:06.447467 SW Impedance : PASS
6989 12:21:06.450345 DUTY Scan : NO K
6990 12:21:06.450771 ZQ Calibration : PASS
6991 12:21:06.453276 Jitter Meter : NO K
6992 12:21:06.456748 CBT Training : PASS
6993 12:21:06.457210 Write leveling : NO K
6994 12:21:06.460170 RX DQS gating : PASS
6995 12:21:06.463478 RX DQ/DQS(RDDQC) : PASS
6996 12:21:06.463906 TX DQ/DQS : PASS
6997 12:21:06.467005 RX DATLAT : PASS
6998 12:21:06.470079 RX DQ/DQS(Engine): PASS
6999 12:21:06.470523 TX OE : NO K
7000 12:21:06.473409 All Pass.
7001 12:21:06.473853
7002 12:21:06.474191 CH 1, Rank 0
7003 12:21:06.476632 SW Impedance : PASS
7004 12:21:06.477097 DUTY Scan : NO K
7005 12:21:06.480517 ZQ Calibration : PASS
7006 12:21:06.483636 Jitter Meter : NO K
7007 12:21:06.484066 CBT Training : PASS
7008 12:21:06.486883 Write leveling : PASS
7009 12:21:06.490091 RX DQS gating : PASS
7010 12:21:06.490519 RX DQ/DQS(RDDQC) : PASS
7011 12:21:06.493351 TX DQ/DQS : PASS
7012 12:21:06.493782 RX DATLAT : PASS
7013 12:21:06.496883 RX DQ/DQS(Engine): PASS
7014 12:21:06.499995 TX OE : NO K
7015 12:21:06.500456 All Pass.
7016 12:21:06.500792
7017 12:21:06.501165 CH 1, Rank 1
7018 12:21:06.503500 SW Impedance : PASS
7019 12:21:06.506814 DUTY Scan : NO K
7020 12:21:06.507259 ZQ Calibration : PASS
7021 12:21:06.510350 Jitter Meter : NO K
7022 12:21:06.513449 CBT Training : PASS
7023 12:21:06.513925 Write leveling : NO K
7024 12:21:06.516796 RX DQS gating : PASS
7025 12:21:06.519963 RX DQ/DQS(RDDQC) : PASS
7026 12:21:06.520392 TX DQ/DQS : PASS
7027 12:21:06.523356 RX DATLAT : PASS
7028 12:21:06.526859 RX DQ/DQS(Engine): PASS
7029 12:21:06.527289 TX OE : NO K
7030 12:21:06.529823 All Pass.
7031 12:21:06.530253
7032 12:21:06.530593 DramC Write-DBI off
7033 12:21:06.533397 PER_BANK_REFRESH: Hybrid Mode
7034 12:21:06.533825 TX_TRACKING: ON
7035 12:21:06.543741 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7036 12:21:06.546834 [FAST_K] Save calibration result to emmc
7037 12:21:06.550185 dramc_set_vcore_voltage set vcore to 725000
7038 12:21:06.553199 Read voltage for 1600, 0
7039 12:21:06.553623 Vio18 = 0
7040 12:21:06.557218 Vcore = 725000
7041 12:21:06.557647 Vdram = 0
7042 12:21:06.557990 Vddq = 0
7043 12:21:06.558307 Vmddr = 0
7044 12:21:06.563487 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7045 12:21:06.570219 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7046 12:21:06.570745 MEM_TYPE=3, freq_sel=13
7047 12:21:06.573246 sv_algorithm_assistance_LP4_3733
7048 12:21:06.576836 ============ PULL DRAM RESETB DOWN ============
7049 12:21:06.583549 ========== PULL DRAM RESETB DOWN end =========
7050 12:21:06.586789 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7051 12:21:06.590477 ===================================
7052 12:21:06.593517 LPDDR4 DRAM CONFIGURATION
7053 12:21:06.596700 ===================================
7054 12:21:06.597232 EX_ROW_EN[0] = 0x0
7055 12:21:06.600187 EX_ROW_EN[1] = 0x0
7056 12:21:06.600654 LP4Y_EN = 0x0
7057 12:21:06.603104 WORK_FSP = 0x1
7058 12:21:06.606480 WL = 0x5
7059 12:21:06.607094 RL = 0x5
7060 12:21:06.609780 BL = 0x2
7061 12:21:06.610233 RPST = 0x0
7062 12:21:06.613042 RD_PRE = 0x0
7063 12:21:06.613528 WR_PRE = 0x1
7064 12:21:06.616480 WR_PST = 0x1
7065 12:21:06.616906 DBI_WR = 0x0
7066 12:21:06.620003 DBI_RD = 0x0
7067 12:21:06.620431 OTF = 0x1
7068 12:21:06.623403 ===================================
7069 12:21:06.626677 ===================================
7070 12:21:06.629753 ANA top config
7071 12:21:06.633079 ===================================
7072 12:21:06.633512 DLL_ASYNC_EN = 0
7073 12:21:06.636485 ALL_SLAVE_EN = 0
7074 12:21:06.639995 NEW_RANK_MODE = 1
7075 12:21:06.643520 DLL_IDLE_MODE = 1
7076 12:21:06.644055 LP45_APHY_COMB_EN = 1
7077 12:21:06.646420 TX_ODT_DIS = 0
7078 12:21:06.649723 NEW_8X_MODE = 1
7079 12:21:06.653374 ===================================
7080 12:21:06.656877 ===================================
7081 12:21:06.660164 data_rate = 3200
7082 12:21:06.663561 CKR = 1
7083 12:21:06.664094 DQ_P2S_RATIO = 8
7084 12:21:06.666582 ===================================
7085 12:21:06.669831 CA_P2S_RATIO = 8
7086 12:21:06.673293 DQ_CA_OPEN = 0
7087 12:21:06.676981 DQ_SEMI_OPEN = 0
7088 12:21:06.680143 CA_SEMI_OPEN = 0
7089 12:21:06.683303 CA_FULL_RATE = 0
7090 12:21:06.683733 DQ_CKDIV4_EN = 0
7091 12:21:06.686352 CA_CKDIV4_EN = 0
7092 12:21:06.689621 CA_PREDIV_EN = 0
7093 12:21:06.692823 PH8_DLY = 12
7094 12:21:06.696223 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7095 12:21:06.699458 DQ_AAMCK_DIV = 4
7096 12:21:06.699890 CA_AAMCK_DIV = 4
7097 12:21:06.703195 CA_ADMCK_DIV = 4
7098 12:21:06.706103 DQ_TRACK_CA_EN = 0
7099 12:21:06.709654 CA_PICK = 1600
7100 12:21:06.712660 CA_MCKIO = 1600
7101 12:21:06.716352 MCKIO_SEMI = 0
7102 12:21:06.719418 PLL_FREQ = 3068
7103 12:21:06.723080 DQ_UI_PI_RATIO = 32
7104 12:21:06.723510 CA_UI_PI_RATIO = 0
7105 12:21:06.725831 ===================================
7106 12:21:06.729497 ===================================
7107 12:21:06.732767 memory_type:LPDDR4
7108 12:21:06.735834 GP_NUM : 10
7109 12:21:06.736370 SRAM_EN : 1
7110 12:21:06.739278 MD32_EN : 0
7111 12:21:06.742643 ===================================
7112 12:21:06.746050 [ANA_INIT] >>>>>>>>>>>>>>
7113 12:21:06.749546 <<<<<< [CONFIGURE PHASE]: ANA_TX
7114 12:21:06.752277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7115 12:21:06.755795 ===================================
7116 12:21:06.756215 data_rate = 3200,PCW = 0X7600
7117 12:21:06.759392 ===================================
7118 12:21:06.762333 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7119 12:21:06.769196 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7120 12:21:06.775651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 12:21:06.779024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7122 12:21:06.782694 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7123 12:21:06.785456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7124 12:21:06.788750 [ANA_INIT] flow start
7125 12:21:06.792102 [ANA_INIT] PLL >>>>>>>>
7126 12:21:06.792519 [ANA_INIT] PLL <<<<<<<<
7127 12:21:06.795619 [ANA_INIT] MIDPI >>>>>>>>
7128 12:21:06.798812 [ANA_INIT] MIDPI <<<<<<<<
7129 12:21:06.799269 [ANA_INIT] DLL >>>>>>>>
7130 12:21:06.802192 [ANA_INIT] DLL <<<<<<<<
7131 12:21:06.805413 [ANA_INIT] flow end
7132 12:21:06.808869 ============ LP4 DIFF to SE enter ============
7133 12:21:06.811995 ============ LP4 DIFF to SE exit ============
7134 12:21:06.815219 [ANA_INIT] <<<<<<<<<<<<<
7135 12:21:06.818470 [Flow] Enable top DCM control >>>>>
7136 12:21:06.821854 [Flow] Enable top DCM control <<<<<
7137 12:21:06.825489 Enable DLL master slave shuffle
7138 12:21:06.828665 ==============================================================
7139 12:21:06.832110 Gating Mode config
7140 12:21:06.838687 ==============================================================
7141 12:21:06.839210 Config description:
7142 12:21:06.849009 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7143 12:21:06.855277 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7144 12:21:06.862271 SELPH_MODE 0: By rank 1: By Phase
7145 12:21:06.865011 ==============================================================
7146 12:21:06.868221 GAT_TRACK_EN = 1
7147 12:21:06.871297 RX_GATING_MODE = 2
7148 12:21:06.874755 RX_GATING_TRACK_MODE = 2
7149 12:21:06.878118 SELPH_MODE = 1
7150 12:21:06.881488 PICG_EARLY_EN = 1
7151 12:21:06.884675 VALID_LAT_VALUE = 1
7152 12:21:06.887853 ==============================================================
7153 12:21:06.891127 Enter into Gating configuration >>>>
7154 12:21:06.894591 Exit from Gating configuration <<<<
7155 12:21:06.897676 Enter into DVFS_PRE_config >>>>>
7156 12:21:06.911172 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7157 12:21:06.914630 Exit from DVFS_PRE_config <<<<<
7158 12:21:06.917697 Enter into PICG configuration >>>>
7159 12:21:06.918120 Exit from PICG configuration <<<<
7160 12:21:06.921429 [RX_INPUT] configuration >>>>>
7161 12:21:06.924268 [RX_INPUT] configuration <<<<<
7162 12:21:06.931180 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7163 12:21:06.934305 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7164 12:21:06.941008 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7165 12:21:06.947799 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7166 12:21:06.954119 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 12:21:06.961138 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 12:21:06.964134 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7169 12:21:06.967444 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7170 12:21:06.970938 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7171 12:21:06.977839 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7172 12:21:06.981319 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7173 12:21:06.984420 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7174 12:21:06.987767 ===================================
7175 12:21:06.991075 LPDDR4 DRAM CONFIGURATION
7176 12:21:06.994473 ===================================
7177 12:21:06.998012 EX_ROW_EN[0] = 0x0
7178 12:21:06.998580 EX_ROW_EN[1] = 0x0
7179 12:21:07.001080 LP4Y_EN = 0x0
7180 12:21:07.001633 WORK_FSP = 0x1
7181 12:21:07.004235 WL = 0x5
7182 12:21:07.004829 RL = 0x5
7183 12:21:07.007402 BL = 0x2
7184 12:21:07.007865 RPST = 0x0
7185 12:21:07.011396 RD_PRE = 0x0
7186 12:21:07.012040 WR_PRE = 0x1
7187 12:21:07.014191 WR_PST = 0x1
7188 12:21:07.014655 DBI_WR = 0x0
7189 12:21:07.017393 DBI_RD = 0x0
7190 12:21:07.017855 OTF = 0x1
7191 12:21:07.020574 ===================================
7192 12:21:07.027479 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7193 12:21:07.030815 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7194 12:21:07.033967 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7195 12:21:07.037263 ===================================
7196 12:21:07.040645 LPDDR4 DRAM CONFIGURATION
7197 12:21:07.044379 ===================================
7198 12:21:07.047396 EX_ROW_EN[0] = 0x10
7199 12:21:07.047967 EX_ROW_EN[1] = 0x0
7200 12:21:07.050835 LP4Y_EN = 0x0
7201 12:21:07.051399 WORK_FSP = 0x1
7202 12:21:07.053862 WL = 0x5
7203 12:21:07.054326 RL = 0x5
7204 12:21:07.057313 BL = 0x2
7205 12:21:07.057777 RPST = 0x0
7206 12:21:07.060832 RD_PRE = 0x0
7207 12:21:07.061339 WR_PRE = 0x1
7208 12:21:07.063995 WR_PST = 0x1
7209 12:21:07.064452 DBI_WR = 0x0
7210 12:21:07.067729 DBI_RD = 0x0
7211 12:21:07.068359 OTF = 0x1
7212 12:21:07.070521 ===================================
7213 12:21:07.077509 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7214 12:21:07.078076 ==
7215 12:21:07.080882 Dram Type= 6, Freq= 0, CH_0, rank 0
7216 12:21:07.087164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7217 12:21:07.087733 ==
7218 12:21:07.088105 [Duty_Offset_Calibration]
7219 12:21:07.090295 B0:2 B1:0 CA:1
7220 12:21:07.090854
7221 12:21:07.093813 [DutyScan_Calibration_Flow] k_type=0
7222 12:21:07.102980
7223 12:21:07.103540 ==CLK 0==
7224 12:21:07.106127 Final CLK duty delay cell = 0
7225 12:21:07.109457 [0] MAX Duty = 5187%(X100), DQS PI = 20
7226 12:21:07.113006 [0] MIN Duty = 5031%(X100), DQS PI = 0
7227 12:21:07.113604 [0] AVG Duty = 5109%(X100)
7228 12:21:07.116182
7229 12:21:07.116792 CH0 CLK Duty spec in!! Max-Min= 156%
7230 12:21:07.123086 [DutyScan_Calibration_Flow] ====Done====
7231 12:21:07.123575
7232 12:21:07.126004 [DutyScan_Calibration_Flow] k_type=1
7233 12:21:07.142222
7234 12:21:07.142783 ==DQS 0 ==
7235 12:21:07.145064 Final DQS duty delay cell = 0
7236 12:21:07.148345 [0] MAX Duty = 5249%(X100), DQS PI = 32
7237 12:21:07.151771 [0] MIN Duty = 4969%(X100), DQS PI = 0
7238 12:21:07.152288 [0] AVG Duty = 5109%(X100)
7239 12:21:07.155191
7240 12:21:07.155653 ==DQS 1 ==
7241 12:21:07.158520 Final DQS duty delay cell = -4
7242 12:21:07.162112 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7243 12:21:07.165651 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7244 12:21:07.168686 [-4] AVG Duty = 5000%(X100)
7245 12:21:07.169230
7246 12:21:07.172077 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7247 12:21:07.172647
7248 12:21:07.175211 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7249 12:21:07.178461 [DutyScan_Calibration_Flow] ====Done====
7250 12:21:07.178928
7251 12:21:07.181790 [DutyScan_Calibration_Flow] k_type=3
7252 12:21:07.199511
7253 12:21:07.200076 ==DQM 0 ==
7254 12:21:07.202804 Final DQM duty delay cell = 0
7255 12:21:07.205751 [0] MAX Duty = 5062%(X100), DQS PI = 12
7256 12:21:07.209530 [0] MIN Duty = 4813%(X100), DQS PI = 50
7257 12:21:07.213100 [0] AVG Duty = 4937%(X100)
7258 12:21:07.213575
7259 12:21:07.213960 ==DQM 1 ==
7260 12:21:07.215720 Final DQM duty delay cell = 0
7261 12:21:07.219247 [0] MAX Duty = 5249%(X100), DQS PI = 30
7262 12:21:07.222956 [0] MIN Duty = 5000%(X100), DQS PI = 20
7263 12:21:07.225812 [0] AVG Duty = 5124%(X100)
7264 12:21:07.226281
7265 12:21:07.229438 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7266 12:21:07.229906
7267 12:21:07.232405 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7268 12:21:07.235702 [DutyScan_Calibration_Flow] ====Done====
7269 12:21:07.236230
7270 12:21:07.239415 [DutyScan_Calibration_Flow] k_type=2
7271 12:21:07.256548
7272 12:21:07.257158 ==DQ 0 ==
7273 12:21:07.259822 Final DQ duty delay cell = 0
7274 12:21:07.263440 [0] MAX Duty = 5124%(X100), DQS PI = 34
7275 12:21:07.266727 [0] MIN Duty = 5000%(X100), DQS PI = 16
7276 12:21:07.267198 [0] AVG Duty = 5062%(X100)
7277 12:21:07.267567
7278 12:21:07.269792 ==DQ 1 ==
7279 12:21:07.273306 Final DQ duty delay cell = 0
7280 12:21:07.276832 [0] MAX Duty = 4969%(X100), DQS PI = 42
7281 12:21:07.280004 [0] MIN Duty = 4875%(X100), DQS PI = 10
7282 12:21:07.280583 [0] AVG Duty = 4922%(X100)
7283 12:21:07.280996
7284 12:21:07.283599 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7285 12:21:07.286369
7286 12:21:07.286859 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7287 12:21:07.293088 [DutyScan_Calibration_Flow] ====Done====
7288 12:21:07.293561 ==
7289 12:21:07.296614 Dram Type= 6, Freq= 0, CH_1, rank 0
7290 12:21:07.299863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7291 12:21:07.300353 ==
7292 12:21:07.303001 [Duty_Offset_Calibration]
7293 12:21:07.303458 B0:0 B1:-1 CA:2
7294 12:21:07.303819
7295 12:21:07.306264 [DutyScan_Calibration_Flow] k_type=0
7296 12:21:07.316764
7297 12:21:07.317239 ==CLK 0==
7298 12:21:07.320294 Final CLK duty delay cell = 0
7299 12:21:07.323457 [0] MAX Duty = 5156%(X100), DQS PI = 10
7300 12:21:07.326656 [0] MIN Duty = 4906%(X100), DQS PI = 44
7301 12:21:07.327089 [0] AVG Duty = 5031%(X100)
7302 12:21:07.329657
7303 12:21:07.333281 CH1 CLK Duty spec in!! Max-Min= 250%
7304 12:21:07.336458 [DutyScan_Calibration_Flow] ====Done====
7305 12:21:07.336876
7306 12:21:07.339696 [DutyScan_Calibration_Flow] k_type=1
7307 12:21:07.356208
7308 12:21:07.356623 ==DQS 0 ==
7309 12:21:07.359845 Final DQS duty delay cell = 0
7310 12:21:07.363186 [0] MAX Duty = 5124%(X100), DQS PI = 26
7311 12:21:07.366071 [0] MIN Duty = 4969%(X100), DQS PI = 0
7312 12:21:07.366516 [0] AVG Duty = 5046%(X100)
7313 12:21:07.369524
7314 12:21:07.369934 ==DQS 1 ==
7315 12:21:07.372894 Final DQS duty delay cell = 0
7316 12:21:07.376104 [0] MAX Duty = 5156%(X100), DQS PI = 0
7317 12:21:07.379758 [0] MIN Duty = 4876%(X100), DQS PI = 32
7318 12:21:07.380286 [0] AVG Duty = 5016%(X100)
7319 12:21:07.383058
7320 12:21:07.386411 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7321 12:21:07.386929
7322 12:21:07.389545 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7323 12:21:07.393127 [DutyScan_Calibration_Flow] ====Done====
7324 12:21:07.393646
7325 12:21:07.396146 [DutyScan_Calibration_Flow] k_type=3
7326 12:21:07.414320
7327 12:21:07.414872 ==DQM 0 ==
7328 12:21:07.417288 Final DQM duty delay cell = 4
7329 12:21:07.420641 [4] MAX Duty = 5125%(X100), DQS PI = 6
7330 12:21:07.424032 [4] MIN Duty = 5000%(X100), DQS PI = 30
7331 12:21:07.424490 [4] AVG Duty = 5062%(X100)
7332 12:21:07.427476
7333 12:21:07.427982 ==DQM 1 ==
7334 12:21:07.430684 Final DQM duty delay cell = 0
7335 12:21:07.433941 [0] MAX Duty = 5281%(X100), DQS PI = 58
7336 12:21:07.437613 [0] MIN Duty = 4876%(X100), DQS PI = 34
7337 12:21:07.440539 [0] AVG Duty = 5078%(X100)
7338 12:21:07.441070
7339 12:21:07.443773 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7340 12:21:07.444234
7341 12:21:07.447158 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7342 12:21:07.450635 [DutyScan_Calibration_Flow] ====Done====
7343 12:21:07.451095
7344 12:21:07.453618 [DutyScan_Calibration_Flow] k_type=2
7345 12:21:07.470962
7346 12:21:07.471518 ==DQ 0 ==
7347 12:21:07.474502 Final DQ duty delay cell = 0
7348 12:21:07.477312 [0] MAX Duty = 5093%(X100), DQS PI = 18
7349 12:21:07.481349 [0] MIN Duty = 4969%(X100), DQS PI = 46
7350 12:21:07.481922 [0] AVG Duty = 5031%(X100)
7351 12:21:07.482288
7352 12:21:07.484197 ==DQ 1 ==
7353 12:21:07.487657 Final DQ duty delay cell = 0
7354 12:21:07.491077 [0] MAX Duty = 5062%(X100), DQS PI = 2
7355 12:21:07.494194 [0] MIN Duty = 4844%(X100), DQS PI = 32
7356 12:21:07.494755 [0] AVG Duty = 4953%(X100)
7357 12:21:07.495122
7358 12:21:07.498066 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7359 12:21:07.498650
7360 12:21:07.501002 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7361 12:21:07.507344 [DutyScan_Calibration_Flow] ====Done====
7362 12:21:07.511051 nWR fixed to 30
7363 12:21:07.511511 [ModeRegInit_LP4] CH0 RK0
7364 12:21:07.514447 [ModeRegInit_LP4] CH0 RK1
7365 12:21:07.517371 [ModeRegInit_LP4] CH1 RK0
7366 12:21:07.517795 [ModeRegInit_LP4] CH1 RK1
7367 12:21:07.521256 match AC timing 5
7368 12:21:07.523894 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7369 12:21:07.527301 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7370 12:21:07.533984 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7371 12:21:07.537909 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7372 12:21:07.543799 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7373 12:21:07.544223 [MiockJmeterHQA]
7374 12:21:07.544583
7375 12:21:07.547494 [DramcMiockJmeter] u1RxGatingPI = 0
7376 12:21:07.550637 0 : 4363, 4138
7377 12:21:07.551070 4 : 4253, 4027
7378 12:21:07.551411 8 : 4253, 4027
7379 12:21:07.553763 12 : 4255, 4029
7380 12:21:07.554188 16 : 4252, 4027
7381 12:21:07.557033 20 : 4363, 4137
7382 12:21:07.557471 24 : 4363, 4137
7383 12:21:07.560436 28 : 4253, 4026
7384 12:21:07.560910 32 : 4254, 4029
7385 12:21:07.563759 36 : 4252, 4027
7386 12:21:07.564318 40 : 4253, 4027
7387 12:21:07.564832 44 : 4252, 4027
7388 12:21:07.567222 48 : 4363, 4138
7389 12:21:07.567661 52 : 4252, 4027
7390 12:21:07.570730 56 : 4255, 4029
7391 12:21:07.571152 60 : 4250, 4027
7392 12:21:07.573807 64 : 4250, 4026
7393 12:21:07.574228 68 : 4250, 4027
7394 12:21:07.577244 72 : 4361, 4137
7395 12:21:07.577667 76 : 4361, 4137
7396 12:21:07.578001 80 : 4250, 4026
7397 12:21:07.580369 84 : 4250, 4027
7398 12:21:07.580792 88 : 4250, 3482
7399 12:21:07.584245 92 : 4253, 0
7400 12:21:07.584771 96 : 4250, 0
7401 12:21:07.585171 100 : 4250, 0
7402 12:21:07.587377 104 : 4252, 0
7403 12:21:07.587906 108 : 4360, 0
7404 12:21:07.591109 112 : 4360, 0
7405 12:21:07.591631 116 : 4361, 0
7406 12:21:07.591968 120 : 4250, 0
7407 12:21:07.594314 124 : 4361, 0
7408 12:21:07.594849 128 : 4250, 0
7409 12:21:07.595186 132 : 4250, 0
7410 12:21:07.597476 136 : 4250, 0
7411 12:21:07.598004 140 : 4250, 0
7412 12:21:07.600652 144 : 4250, 0
7413 12:21:07.601136 148 : 4250, 0
7414 12:21:07.601474 152 : 4250, 0
7415 12:21:07.603882 156 : 4252, 0
7416 12:21:07.604397 160 : 4361, 0
7417 12:21:07.607390 164 : 4250, 0
7418 12:21:07.608143 168 : 4361, 0
7419 12:21:07.608634 172 : 4250, 0
7420 12:21:07.610326 176 : 4250, 0
7421 12:21:07.611013 180 : 4250, 0
7422 12:21:07.613852 184 : 4361, 0
7423 12:21:07.614435 188 : 4250, 0
7424 12:21:07.614992 192 : 4250, 0
7425 12:21:07.617050 196 : 4254, 0
7426 12:21:07.617638 200 : 4250, 3
7427 12:21:07.620467 204 : 4250, 2380
7428 12:21:07.621040 208 : 4250, 4027
7429 12:21:07.621545 212 : 4250, 4026
7430 12:21:07.624029 216 : 4253, 4029
7431 12:21:07.624453 220 : 4250, 4027
7432 12:21:07.627209 224 : 4250, 4026
7433 12:21:07.627802 228 : 4361, 4137
7434 12:21:07.630728 232 : 4250, 4026
7435 12:21:07.631151 236 : 4250, 4027
7436 12:21:07.633669 240 : 4360, 4138
7437 12:21:07.634130 244 : 4250, 4026
7438 12:21:07.636909 248 : 4250, 4027
7439 12:21:07.637423 252 : 4361, 4137
7440 12:21:07.640673 256 : 4250, 4027
7441 12:21:07.641242 260 : 4250, 4026
7442 12:21:07.643883 264 : 4250, 4027
7443 12:21:07.644396 268 : 4250, 4026
7444 12:21:07.644734 272 : 4250, 4027
7445 12:21:07.647404 276 : 4250, 4026
7446 12:21:07.647854 280 : 4361, 4137
7447 12:21:07.650686 284 : 4250, 4026
7448 12:21:07.651204 288 : 4250, 4027
7449 12:21:07.653688 292 : 4360, 4138
7450 12:21:07.654281 296 : 4250, 4026
7451 12:21:07.657128 300 : 4250, 4026
7452 12:21:07.657556 304 : 4361, 4137
7453 12:21:07.660326 308 : 4360, 4138
7454 12:21:07.660790 312 : 4250, 3898
7455 12:21:07.663646 316 : 4250, 2242
7456 12:21:07.664080 320 : 4250, 4
7457 12:21:07.664411
7458 12:21:07.666947 MIOCK jitter meter ch=0
7459 12:21:07.667361
7460 12:21:07.670134 1T = (320-92) = 228 dly cells
7461 12:21:07.673545 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7462 12:21:07.673991 ==
7463 12:21:07.676792 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 12:21:07.683899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7465 12:21:07.684325 ==
7466 12:21:07.686883 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7467 12:21:07.693645 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7468 12:21:07.697030 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7469 12:21:07.703286 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7470 12:21:07.710759 [CA 0] Center 43 (13~73) winsize 61
7471 12:21:07.714287 [CA 1] Center 42 (12~73) winsize 62
7472 12:21:07.717452 [CA 2] Center 37 (7~67) winsize 61
7473 12:21:07.720855 [CA 3] Center 37 (7~67) winsize 61
7474 12:21:07.724348 [CA 4] Center 36 (6~66) winsize 61
7475 12:21:07.727488 [CA 5] Center 35 (5~65) winsize 61
7476 12:21:07.727909
7477 12:21:07.731467 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7478 12:21:07.731890
7479 12:21:07.734203 [CATrainingPosCal] consider 1 rank data
7480 12:21:07.737895 u2DelayCellTimex100 = 285/100 ps
7481 12:21:07.741236 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7482 12:21:07.747510 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7483 12:21:07.750991 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7484 12:21:07.754625 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7485 12:21:07.757346 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7486 12:21:07.761140 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7487 12:21:07.761739
7488 12:21:07.764407 CA PerBit enable=1, Macro0, CA PI delay=35
7489 12:21:07.765152
7490 12:21:07.767524 [CBTSetCACLKResult] CA Dly = 35
7491 12:21:07.770916 CS Dly: 10 (0~41)
7492 12:21:07.774496 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7493 12:21:07.777462 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7494 12:21:07.777888 ==
7495 12:21:07.781095 Dram Type= 6, Freq= 0, CH_0, rank 1
7496 12:21:07.784504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 12:21:07.784992 ==
7498 12:21:07.791179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 12:21:07.794309 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 12:21:07.801109 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 12:21:07.804091 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 12:21:07.814548 [CA 0] Center 43 (13~73) winsize 61
7503 12:21:07.817603 [CA 1] Center 43 (13~73) winsize 61
7504 12:21:07.820865 [CA 2] Center 38 (8~68) winsize 61
7505 12:21:07.824207 [CA 3] Center 38 (8~68) winsize 61
7506 12:21:07.827828 [CA 4] Center 36 (6~66) winsize 61
7507 12:21:07.831068 [CA 5] Center 36 (6~66) winsize 61
7508 12:21:07.831587
7509 12:21:07.834235 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7510 12:21:07.834757
7511 12:21:07.837896 [CATrainingPosCal] consider 2 rank data
7512 12:21:07.840917 u2DelayCellTimex100 = 285/100 ps
7513 12:21:07.844460 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7514 12:21:07.850932 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7515 12:21:07.854322 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 12:21:07.857881 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7517 12:21:07.860820 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7518 12:21:07.864494 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7519 12:21:07.864912
7520 12:21:07.867249 CA PerBit enable=1, Macro0, CA PI delay=35
7521 12:21:07.867727
7522 12:21:07.870713 [CBTSetCACLKResult] CA Dly = 35
7523 12:21:07.874079 CS Dly: 11 (0~43)
7524 12:21:07.877389 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 12:21:07.880809 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 12:21:07.881402
7527 12:21:07.883888 ----->DramcWriteLeveling(PI) begin...
7528 12:21:07.884358 ==
7529 12:21:07.887114 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 12:21:07.893858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 12:21:07.894412 ==
7532 12:21:07.897482 Write leveling (Byte 0): 36 => 36
7533 12:21:07.897950 Write leveling (Byte 1): 31 => 31
7534 12:21:07.900524 DramcWriteLeveling(PI) end<-----
7535 12:21:07.901010
7536 12:21:07.901380 ==
7537 12:21:07.903864 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 12:21:07.910433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 12:21:07.911067 ==
7540 12:21:07.913857 [Gating] SW mode calibration
7541 12:21:07.920354 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7542 12:21:07.923744 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7543 12:21:07.930351 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 12:21:07.933834 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 12:21:07.937111 1 4 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
7546 12:21:07.944635 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7547 12:21:07.947332 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7548 12:21:07.950858 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7549 12:21:07.954180 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 12:21:07.960790 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7551 12:21:07.964184 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7552 12:21:07.967537 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 12:21:07.973930 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
7554 12:21:07.977342 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7555 12:21:07.980809 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7556 12:21:07.987204 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7557 12:21:07.990993 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 12:21:07.994358 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 12:21:08.000731 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7560 12:21:08.003985 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 12:21:08.007139 1 6 8 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7562 12:21:08.014055 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7563 12:21:08.017059 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7564 12:21:08.020572 1 6 20 | B1->B0 | 3d3c 4646 | 1 0 | (0 0) (0 0)
7565 12:21:08.026884 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 12:21:08.030270 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 12:21:08.033625 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 12:21:08.040322 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 12:21:08.043716 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7570 12:21:08.047136 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 12:21:08.054293 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7572 12:21:08.057387 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 12:21:08.060399 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 12:21:08.066885 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 12:21:08.070259 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 12:21:08.073482 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 12:21:08.080094 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 12:21:08.083108 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:21:08.086581 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:21:08.093294 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:21:08.097206 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:21:08.099752 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:21:08.103095 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:21:08.110302 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:21:08.113076 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 12:21:08.116490 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 12:21:08.123350 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7588 12:21:08.126869 Total UI for P1: 0, mck2ui 16
7589 12:21:08.129985 best dqsien dly found for B0: ( 1, 9, 10)
7590 12:21:08.133073 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7591 12:21:08.136507 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 12:21:08.140017 Total UI for P1: 0, mck2ui 16
7593 12:21:08.143370 best dqsien dly found for B1: ( 1, 9, 20)
7594 12:21:08.146607 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7595 12:21:08.149993 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7596 12:21:08.150550
7597 12:21:08.156446 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7598 12:21:08.160232 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7599 12:21:08.162979 [Gating] SW calibration Done
7600 12:21:08.163827 ==
7601 12:21:08.166367 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 12:21:08.169389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 12:21:08.169854 ==
7604 12:21:08.170217 RX Vref Scan: 0
7605 12:21:08.173359
7606 12:21:08.173918 RX Vref 0 -> 0, step: 1
7607 12:21:08.174288
7608 12:21:08.176113 RX Delay 0 -> 252, step: 8
7609 12:21:08.179751 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7610 12:21:08.183132 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7611 12:21:08.189759 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7612 12:21:08.193108 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7613 12:21:08.195963 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7614 12:21:08.199221 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7615 12:21:08.202467 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7616 12:21:08.209022 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7617 12:21:08.212474 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
7618 12:21:08.216340 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7619 12:21:08.219157 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
7620 12:21:08.222632 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7621 12:21:08.229149 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7622 12:21:08.232531 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7623 12:21:08.236389 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7624 12:21:08.239412 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7625 12:21:08.239974 ==
7626 12:21:08.242867 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 12:21:08.246162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 12:21:08.249429 ==
7629 12:21:08.249990 DQS Delay:
7630 12:21:08.250355 DQS0 = 0, DQS1 = 0
7631 12:21:08.252725 DQM Delay:
7632 12:21:08.253222 DQM0 = 138, DQM1 = 128
7633 12:21:08.256033 DQ Delay:
7634 12:21:08.259432 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7635 12:21:08.262505 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7636 12:21:08.265576 DQ8 =123, DQ9 =115, DQ10 =127, DQ11 =127
7637 12:21:08.269559 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7638 12:21:08.270131
7639 12:21:08.270495
7640 12:21:08.270829 ==
7641 12:21:08.272254 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 12:21:08.275985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 12:21:08.276555 ==
7644 12:21:08.276925
7645 12:21:08.278842
7646 12:21:08.279303 TX Vref Scan disable
7647 12:21:08.282199 == TX Byte 0 ==
7648 12:21:08.285544 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7649 12:21:08.289097 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7650 12:21:08.292444 == TX Byte 1 ==
7651 12:21:08.295631 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7652 12:21:08.299433 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7653 12:21:08.300003 ==
7654 12:21:08.302330 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 12:21:08.308993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 12:21:08.309459 ==
7657 12:21:08.320646
7658 12:21:08.324093 TX Vref early break, caculate TX vref
7659 12:21:08.327374 TX Vref=16, minBit 12, minWin=22, winSum=377
7660 12:21:08.330766 TX Vref=18, minBit 8, minWin=23, winSum=389
7661 12:21:08.334611 TX Vref=20, minBit 0, minWin=24, winSum=395
7662 12:21:08.337289 TX Vref=22, minBit 1, minWin=25, winSum=407
7663 12:21:08.340661 TX Vref=24, minBit 7, minWin=25, winSum=419
7664 12:21:08.347829 TX Vref=26, minBit 12, minWin=25, winSum=423
7665 12:21:08.350514 TX Vref=28, minBit 2, minWin=26, winSum=431
7666 12:21:08.354070 TX Vref=30, minBit 0, minWin=26, winSum=422
7667 12:21:08.357389 TX Vref=32, minBit 0, minWin=25, winSum=413
7668 12:21:08.360854 TX Vref=34, minBit 0, minWin=24, winSum=403
7669 12:21:08.367836 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
7670 12:21:08.368427
7671 12:21:08.370551 Final TX Range 0 Vref 28
7672 12:21:08.371024
7673 12:21:08.371393 ==
7674 12:21:08.373957 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 12:21:08.377149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 12:21:08.377734 ==
7677 12:21:08.378110
7678 12:21:08.378458
7679 12:21:08.380580 TX Vref Scan disable
7680 12:21:08.387573 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7681 12:21:08.388156 == TX Byte 0 ==
7682 12:21:08.390588 u2DelayCellOfst[0]=13 cells (4 PI)
7683 12:21:08.393611 u2DelayCellOfst[1]=17 cells (5 PI)
7684 12:21:08.397311 u2DelayCellOfst[2]=10 cells (3 PI)
7685 12:21:08.400348 u2DelayCellOfst[3]=10 cells (3 PI)
7686 12:21:08.403793 u2DelayCellOfst[4]=6 cells (2 PI)
7687 12:21:08.407158 u2DelayCellOfst[5]=0 cells (0 PI)
7688 12:21:08.410241 u2DelayCellOfst[6]=17 cells (5 PI)
7689 12:21:08.413659 u2DelayCellOfst[7]=13 cells (4 PI)
7690 12:21:08.417062 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7691 12:21:08.420435 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7692 12:21:08.423545 == TX Byte 1 ==
7693 12:21:08.424015 u2DelayCellOfst[8]=3 cells (1 PI)
7694 12:21:08.426758 u2DelayCellOfst[9]=0 cells (0 PI)
7695 12:21:08.430401 u2DelayCellOfst[10]=10 cells (3 PI)
7696 12:21:08.433482 u2DelayCellOfst[11]=3 cells (1 PI)
7697 12:21:08.437147 u2DelayCellOfst[12]=13 cells (4 PI)
7698 12:21:08.440153 u2DelayCellOfst[13]=13 cells (4 PI)
7699 12:21:08.443666 u2DelayCellOfst[14]=13 cells (4 PI)
7700 12:21:08.446923 u2DelayCellOfst[15]=10 cells (3 PI)
7701 12:21:08.450824 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7702 12:21:08.457443 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7703 12:21:08.458014 DramC Write-DBI on
7704 12:21:08.458387 ==
7705 12:21:08.460087 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 12:21:08.466796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 12:21:08.467444 ==
7708 12:21:08.467874
7709 12:21:08.468270
7710 12:21:08.468602 TX Vref Scan disable
7711 12:21:08.470643 == TX Byte 0 ==
7712 12:21:08.473837 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7713 12:21:08.477232 == TX Byte 1 ==
7714 12:21:08.480486 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7715 12:21:08.483982 DramC Write-DBI off
7716 12:21:08.484544
7717 12:21:08.484982 [DATLAT]
7718 12:21:08.485354 Freq=1600, CH0 RK0
7719 12:21:08.485689
7720 12:21:08.487375 DATLAT Default: 0xf
7721 12:21:08.487891 0, 0xFFFF, sum = 0
7722 12:21:08.490892 1, 0xFFFF, sum = 0
7723 12:21:08.494005 2, 0xFFFF, sum = 0
7724 12:21:08.494581 3, 0xFFFF, sum = 0
7725 12:21:08.497039 4, 0xFFFF, sum = 0
7726 12:21:08.497514 5, 0xFFFF, sum = 0
7727 12:21:08.500171 6, 0xFFFF, sum = 0
7728 12:21:08.500648 7, 0xFFFF, sum = 0
7729 12:21:08.503769 8, 0xFFFF, sum = 0
7730 12:21:08.504357 9, 0xFFFF, sum = 0
7731 12:21:08.507032 10, 0xFFFF, sum = 0
7732 12:21:08.507512 11, 0xFFFF, sum = 0
7733 12:21:08.510275 12, 0xFFFF, sum = 0
7734 12:21:08.510908 13, 0xFFFF, sum = 0
7735 12:21:08.513457 14, 0x0, sum = 1
7736 12:21:08.513955 15, 0x0, sum = 2
7737 12:21:08.516915 16, 0x0, sum = 3
7738 12:21:08.517638 17, 0x0, sum = 4
7739 12:21:08.520485 best_step = 15
7740 12:21:08.520988
7741 12:21:08.521369 ==
7742 12:21:08.523840 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 12:21:08.526872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 12:21:08.527573 ==
7745 12:21:08.528140 RX Vref Scan: 1
7746 12:21:08.530403
7747 12:21:08.530894 Set Vref Range= 24 -> 127
7748 12:21:08.531295
7749 12:21:08.533608 RX Vref 24 -> 127, step: 1
7750 12:21:08.534075
7751 12:21:08.537106 RX Delay 19 -> 252, step: 4
7752 12:21:08.537685
7753 12:21:08.540770 Set Vref, RX VrefLevel [Byte0]: 24
7754 12:21:08.543597 [Byte1]: 24
7755 12:21:08.544154
7756 12:21:08.546884 Set Vref, RX VrefLevel [Byte0]: 25
7757 12:21:08.550295 [Byte1]: 25
7758 12:21:08.550763
7759 12:21:08.553587 Set Vref, RX VrefLevel [Byte0]: 26
7760 12:21:08.556598 [Byte1]: 26
7761 12:21:08.560686
7762 12:21:08.561265 Set Vref, RX VrefLevel [Byte0]: 27
7763 12:21:08.564012 [Byte1]: 27
7764 12:21:08.568152
7765 12:21:08.568692 Set Vref, RX VrefLevel [Byte0]: 28
7766 12:21:08.571396 [Byte1]: 28
7767 12:21:08.576322
7768 12:21:08.576842 Set Vref, RX VrefLevel [Byte0]: 29
7769 12:21:08.579640 [Byte1]: 29
7770 12:21:08.583463
7771 12:21:08.583979 Set Vref, RX VrefLevel [Byte0]: 30
7772 12:21:08.586747 [Byte1]: 30
7773 12:21:08.591334
7774 12:21:08.591855 Set Vref, RX VrefLevel [Byte0]: 31
7775 12:21:08.594512 [Byte1]: 31
7776 12:21:08.598994
7777 12:21:08.599520 Set Vref, RX VrefLevel [Byte0]: 32
7778 12:21:08.601869 [Byte1]: 32
7779 12:21:08.606600
7780 12:21:08.607120 Set Vref, RX VrefLevel [Byte0]: 33
7781 12:21:08.609244 [Byte1]: 33
7782 12:21:08.613576
7783 12:21:08.613993 Set Vref, RX VrefLevel [Byte0]: 34
7784 12:21:08.616999 [Byte1]: 34
7785 12:21:08.621654
7786 12:21:08.622102 Set Vref, RX VrefLevel [Byte0]: 35
7787 12:21:08.624566 [Byte1]: 35
7788 12:21:08.628991
7789 12:21:08.629412 Set Vref, RX VrefLevel [Byte0]: 36
7790 12:21:08.632254 [Byte1]: 36
7791 12:21:08.636574
7792 12:21:08.637039 Set Vref, RX VrefLevel [Byte0]: 37
7793 12:21:08.639751 [Byte1]: 37
7794 12:21:08.643795
7795 12:21:08.644354 Set Vref, RX VrefLevel [Byte0]: 38
7796 12:21:08.647761 [Byte1]: 38
7797 12:21:08.651718
7798 12:21:08.652137 Set Vref, RX VrefLevel [Byte0]: 39
7799 12:21:08.654794 [Byte1]: 39
7800 12:21:08.659199
7801 12:21:08.659720 Set Vref, RX VrefLevel [Byte0]: 40
7802 12:21:08.662424 [Byte1]: 40
7803 12:21:08.667019
7804 12:21:08.667435 Set Vref, RX VrefLevel [Byte0]: 41
7805 12:21:08.669900 [Byte1]: 41
7806 12:21:08.674230
7807 12:21:08.674646 Set Vref, RX VrefLevel [Byte0]: 42
7808 12:21:08.677532 [Byte1]: 42
7809 12:21:08.681901
7810 12:21:08.682419 Set Vref, RX VrefLevel [Byte0]: 43
7811 12:21:08.685021 [Byte1]: 43
7812 12:21:08.689787
7813 12:21:08.690351 Set Vref, RX VrefLevel [Byte0]: 44
7814 12:21:08.692847 [Byte1]: 44
7815 12:21:08.697059
7816 12:21:08.697571 Set Vref, RX VrefLevel [Byte0]: 45
7817 12:21:08.700469 [Byte1]: 45
7818 12:21:08.704781
7819 12:21:08.705248 Set Vref, RX VrefLevel [Byte0]: 46
7820 12:21:08.707849 [Byte1]: 46
7821 12:21:08.711917
7822 12:21:08.712339 Set Vref, RX VrefLevel [Byte0]: 47
7823 12:21:08.715381 [Byte1]: 47
7824 12:21:08.719452
7825 12:21:08.719908 Set Vref, RX VrefLevel [Byte0]: 48
7826 12:21:08.723013 [Byte1]: 48
7827 12:21:08.727485
7828 12:21:08.727904 Set Vref, RX VrefLevel [Byte0]: 49
7829 12:21:08.730471 [Byte1]: 49
7830 12:21:08.734750
7831 12:21:08.735168 Set Vref, RX VrefLevel [Byte0]: 50
7832 12:21:08.738399 [Byte1]: 50
7833 12:21:08.742197
7834 12:21:08.742616 Set Vref, RX VrefLevel [Byte0]: 51
7835 12:21:08.745686 [Byte1]: 51
7836 12:21:08.749896
7837 12:21:08.750393 Set Vref, RX VrefLevel [Byte0]: 52
7838 12:21:08.753142 [Byte1]: 52
7839 12:21:08.757786
7840 12:21:08.758200 Set Vref, RX VrefLevel [Byte0]: 53
7841 12:21:08.760778 [Byte1]: 53
7842 12:21:08.764980
7843 12:21:08.765399 Set Vref, RX VrefLevel [Byte0]: 54
7844 12:21:08.768266 [Byte1]: 54
7845 12:21:08.772470
7846 12:21:08.772885 Set Vref, RX VrefLevel [Byte0]: 55
7847 12:21:08.776082 [Byte1]: 55
7848 12:21:08.780219
7849 12:21:08.780802 Set Vref, RX VrefLevel [Byte0]: 56
7850 12:21:08.783655 [Byte1]: 56
7851 12:21:08.787624
7852 12:21:08.788151 Set Vref, RX VrefLevel [Byte0]: 57
7853 12:21:08.791125 [Byte1]: 57
7854 12:21:08.795152
7855 12:21:08.795688 Set Vref, RX VrefLevel [Byte0]: 58
7856 12:21:08.798908 [Byte1]: 58
7857 12:21:08.802928
7858 12:21:08.803546 Set Vref, RX VrefLevel [Byte0]: 59
7859 12:21:08.806428 [Byte1]: 59
7860 12:21:08.810477
7861 12:21:08.810915 Set Vref, RX VrefLevel [Byte0]: 60
7862 12:21:08.813523 [Byte1]: 60
7863 12:21:08.818390
7864 12:21:08.818809 Set Vref, RX VrefLevel [Byte0]: 61
7865 12:21:08.821397 [Byte1]: 61
7866 12:21:08.825587
7867 12:21:08.826006 Set Vref, RX VrefLevel [Byte0]: 62
7868 12:21:08.828872 [Byte1]: 62
7869 12:21:08.833002
7870 12:21:08.833422 Set Vref, RX VrefLevel [Byte0]: 63
7871 12:21:08.836666 [Byte1]: 63
7872 12:21:08.841127
7873 12:21:08.841750 Set Vref, RX VrefLevel [Byte0]: 64
7874 12:21:08.844521 [Byte1]: 64
7875 12:21:08.848175
7876 12:21:08.848686 Set Vref, RX VrefLevel [Byte0]: 65
7877 12:21:08.851534 [Byte1]: 65
7878 12:21:08.856245
7879 12:21:08.856764 Set Vref, RX VrefLevel [Byte0]: 66
7880 12:21:08.859666 [Byte1]: 66
7881 12:21:08.863747
7882 12:21:08.864208 Set Vref, RX VrefLevel [Byte0]: 67
7883 12:21:08.867127 [Byte1]: 67
7884 12:21:08.871059
7885 12:21:08.871659 Set Vref, RX VrefLevel [Byte0]: 68
7886 12:21:08.874360 [Byte1]: 68
7887 12:21:08.878654
7888 12:21:08.879115 Set Vref, RX VrefLevel [Byte0]: 69
7889 12:21:08.881940 [Byte1]: 69
7890 12:21:08.886103
7891 12:21:08.886564 Set Vref, RX VrefLevel [Byte0]: 70
7892 12:21:08.889459 [Byte1]: 70
7893 12:21:08.894108
7894 12:21:08.894567 Set Vref, RX VrefLevel [Byte0]: 71
7895 12:21:08.897047 [Byte1]: 71
7896 12:21:08.901244
7897 12:21:08.901790 Set Vref, RX VrefLevel [Byte0]: 72
7898 12:21:08.904759 [Byte1]: 72
7899 12:21:08.909000
7900 12:21:08.909530 Set Vref, RX VrefLevel [Byte0]: 73
7901 12:21:08.912024 [Byte1]: 73
7902 12:21:08.916218
7903 12:21:08.916800 Set Vref, RX VrefLevel [Byte0]: 74
7904 12:21:08.920254 [Byte1]: 74
7905 12:21:08.924065
7906 12:21:08.924480 Set Vref, RX VrefLevel [Byte0]: 75
7907 12:21:08.927653 [Byte1]: 75
7908 12:21:08.931825
7909 12:21:08.932247 Set Vref, RX VrefLevel [Byte0]: 76
7910 12:21:08.935044 [Byte1]: 76
7911 12:21:08.939348
7912 12:21:08.939768 Set Vref, RX VrefLevel [Byte0]: 77
7913 12:21:08.942616 [Byte1]: 77
7914 12:21:08.946790
7915 12:21:08.947303 Set Vref, RX VrefLevel [Byte0]: 78
7916 12:21:08.950233 [Byte1]: 78
7917 12:21:08.954512
7918 12:21:08.955051 Set Vref, RX VrefLevel [Byte0]: 79
7919 12:21:08.957830 [Byte1]: 79
7920 12:21:08.962479
7921 12:21:08.963020 Set Vref, RX VrefLevel [Byte0]: 80
7922 12:21:08.965198 [Byte1]: 80
7923 12:21:08.970356
7924 12:21:08.970774 Final RX Vref Byte 0 = 66 to rank0
7925 12:21:08.972893 Final RX Vref Byte 1 = 62 to rank0
7926 12:21:08.976394 Final RX Vref Byte 0 = 66 to rank1
7927 12:21:08.979902 Final RX Vref Byte 1 = 62 to rank1==
7928 12:21:08.983199 Dram Type= 6, Freq= 0, CH_0, rank 0
7929 12:21:08.989493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7930 12:21:08.990141 ==
7931 12:21:08.990512 DQS Delay:
7932 12:21:08.990855 DQS0 = 0, DQS1 = 0
7933 12:21:08.993040 DQM Delay:
7934 12:21:08.993505 DQM0 = 134, DQM1 = 126
7935 12:21:08.996336 DQ Delay:
7936 12:21:08.999888 DQ0 =134, DQ1 =134, DQ2 =130, DQ3 =132
7937 12:21:09.003099 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =142
7938 12:21:09.006053 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =122
7939 12:21:09.009594 DQ12 =130, DQ13 =130, DQ14 =138, DQ15 =134
7940 12:21:09.010225
7941 12:21:09.010765
7942 12:21:09.011323
7943 12:21:09.012671 [DramC_TX_OE_Calibration] TA2
7944 12:21:09.016081 Original DQ_B0 (3 6) =30, OEN = 27
7945 12:21:09.019359 Original DQ_B1 (3 6) =30, OEN = 27
7946 12:21:09.023394 24, 0x0, End_B0=24 End_B1=24
7947 12:21:09.023970 25, 0x0, End_B0=25 End_B1=25
7948 12:21:09.026220 26, 0x0, End_B0=26 End_B1=26
7949 12:21:09.029492 27, 0x0, End_B0=27 End_B1=27
7950 12:21:09.033370 28, 0x0, End_B0=28 End_B1=28
7951 12:21:09.033927 29, 0x0, End_B0=29 End_B1=29
7952 12:21:09.035989 30, 0x0, End_B0=30 End_B1=30
7953 12:21:09.039196 31, 0x4141, End_B0=30 End_B1=30
7954 12:21:09.042653 Byte0 end_step=30 best_step=27
7955 12:21:09.045958 Byte1 end_step=30 best_step=27
7956 12:21:09.049103 Byte0 TX OE(2T, 0.5T) = (3, 3)
7957 12:21:09.049572 Byte1 TX OE(2T, 0.5T) = (3, 3)
7958 12:21:09.052897
7959 12:21:09.053547
7960 12:21:09.059275 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7961 12:21:09.062470 CH0 RK0: MR19=303, MR18=1C1A
7962 12:21:09.069158 CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15
7963 12:21:09.069635
7964 12:21:09.073085 ----->DramcWriteLeveling(PI) begin...
7965 12:21:09.073667 ==
7966 12:21:09.076371 Dram Type= 6, Freq= 0, CH_0, rank 1
7967 12:21:09.079543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 12:21:09.080159 ==
7969 12:21:09.083107 Write leveling (Byte 0): 37 => 37
7970 12:21:09.086242 Write leveling (Byte 1): 30 => 30
7971 12:21:09.089771 DramcWriteLeveling(PI) end<-----
7972 12:21:09.090340
7973 12:21:09.090710 ==
7974 12:21:09.092916 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 12:21:09.095873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 12:21:09.096499 ==
7977 12:21:09.099158 [Gating] SW mode calibration
7978 12:21:09.105880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7979 12:21:09.112199 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7980 12:21:09.115519 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 12:21:09.118981 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 12:21:09.125896 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 12:21:09.129080 1 4 12 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (1 1)
7984 12:21:09.132602 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 12:21:09.139230 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7986 12:21:09.142238 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 12:21:09.145762 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 12:21:09.152042 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7989 12:21:09.155517 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 12:21:09.159289 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7991 12:21:09.165463 1 5 12 | B1->B0 | 3333 2828 | 0 1 | (0 1) (1 0)
7992 12:21:09.168806 1 5 16 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7993 12:21:09.171978 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 12:21:09.178839 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7995 12:21:09.182248 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 12:21:09.185415 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 12:21:09.192381 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 12:21:09.195624 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7999 12:21:09.198974 1 6 12 | B1->B0 | 3534 4646 | 1 0 | (0 0) (0 0)
8000 12:21:09.205653 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8001 12:21:09.208960 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 12:21:09.212132 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 12:21:09.218803 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 12:21:09.222142 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 12:21:09.225470 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 12:21:09.228692 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 12:21:09.235987 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8008 12:21:09.239027 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8009 12:21:09.241888 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 12:21:09.248888 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 12:21:09.252180 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 12:21:09.255517 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 12:21:09.261801 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 12:21:09.265084 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 12:21:09.268753 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 12:21:09.275114 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 12:21:09.278576 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 12:21:09.281981 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 12:21:09.288595 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 12:21:09.291809 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 12:21:09.295083 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 12:21:09.301827 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8023 12:21:09.305066 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8024 12:21:09.308142 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8025 12:21:09.311355 Total UI for P1: 0, mck2ui 16
8026 12:21:09.315213 best dqsien dly found for B0: ( 1, 9, 10)
8027 12:21:09.321930 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 12:21:09.322399 Total UI for P1: 0, mck2ui 16
8029 12:21:09.328081 best dqsien dly found for B1: ( 1, 9, 14)
8030 12:21:09.331263 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8031 12:21:09.335041 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8032 12:21:09.335607
8033 12:21:09.338437 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8034 12:21:09.341537 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8035 12:21:09.345014 [Gating] SW calibration Done
8036 12:21:09.345489 ==
8037 12:21:09.348012 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 12:21:09.351338 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 12:21:09.351805 ==
8040 12:21:09.354706 RX Vref Scan: 0
8041 12:21:09.355172
8042 12:21:09.355538 RX Vref 0 -> 0, step: 1
8043 12:21:09.355882
8044 12:21:09.358157 RX Delay 0 -> 252, step: 8
8045 12:21:09.361197 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8046 12:21:09.367947 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8047 12:21:09.371544 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8048 12:21:09.374501 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8049 12:21:09.377801 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8050 12:21:09.381154 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8051 12:21:09.388047 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8052 12:21:09.391269 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8053 12:21:09.394266 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8054 12:21:09.397457 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8055 12:21:09.400859 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8056 12:21:09.407612 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8057 12:21:09.410832 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8058 12:21:09.414012 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8059 12:21:09.417885 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8060 12:21:09.424393 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8061 12:21:09.424813 ==
8062 12:21:09.427739 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 12:21:09.430994 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 12:21:09.431608 ==
8065 12:21:09.432137 DQS Delay:
8066 12:21:09.434243 DQS0 = 0, DQS1 = 0
8067 12:21:09.434704 DQM Delay:
8068 12:21:09.437734 DQM0 = 136, DQM1 = 127
8069 12:21:09.438196 DQ Delay:
8070 12:21:09.440674 DQ0 =135, DQ1 =135, DQ2 =135, DQ3 =131
8071 12:21:09.443778 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8072 12:21:09.447134 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8073 12:21:09.450672 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8074 12:21:09.451417
8075 12:21:09.451976
8076 12:21:09.453758 ==
8077 12:21:09.457039 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 12:21:09.460197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 12:21:09.460578 ==
8080 12:21:09.460892
8081 12:21:09.461231
8082 12:21:09.463518 TX Vref Scan disable
8083 12:21:09.464088 == TX Byte 0 ==
8084 12:21:09.467362 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8085 12:21:09.473458 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8086 12:21:09.473884 == TX Byte 1 ==
8087 12:21:09.477080 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8088 12:21:09.483508 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8089 12:21:09.483936 ==
8090 12:21:09.487290 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 12:21:09.490213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 12:21:09.490768 ==
8093 12:21:09.505382
8094 12:21:09.508684 TX Vref early break, caculate TX vref
8095 12:21:09.511890 TX Vref=16, minBit 2, minWin=23, winSum=391
8096 12:21:09.515252 TX Vref=18, minBit 1, minWin=24, winSum=398
8097 12:21:09.518802 TX Vref=20, minBit 0, minWin=24, winSum=407
8098 12:21:09.521838 TX Vref=22, minBit 8, minWin=24, winSum=413
8099 12:21:09.525724 TX Vref=24, minBit 0, minWin=25, winSum=423
8100 12:21:09.532064 TX Vref=26, minBit 0, minWin=26, winSum=429
8101 12:21:09.535514 TX Vref=28, minBit 0, minWin=26, winSum=428
8102 12:21:09.538726 TX Vref=30, minBit 0, minWin=26, winSum=427
8103 12:21:09.541686 TX Vref=32, minBit 1, minWin=25, winSum=416
8104 12:21:09.545088 TX Vref=34, minBit 4, minWin=24, winSum=408
8105 12:21:09.548711 TX Vref=36, minBit 2, minWin=23, winSum=400
8106 12:21:09.555563 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
8107 12:21:09.556086
8108 12:21:09.558590 Final TX Range 0 Vref 26
8109 12:21:09.559157
8110 12:21:09.559523 ==
8111 12:21:09.561915 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 12:21:09.565386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 12:21:09.565858 ==
8114 12:21:09.566245
8115 12:21:09.566585
8116 12:21:09.568577 TX Vref Scan disable
8117 12:21:09.574834 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8118 12:21:09.575305 == TX Byte 0 ==
8119 12:21:09.578453 u2DelayCellOfst[0]=17 cells (5 PI)
8120 12:21:09.581689 u2DelayCellOfst[1]=17 cells (5 PI)
8121 12:21:09.585145 u2DelayCellOfst[2]=13 cells (4 PI)
8122 12:21:09.588275 u2DelayCellOfst[3]=13 cells (4 PI)
8123 12:21:09.591736 u2DelayCellOfst[4]=10 cells (3 PI)
8124 12:21:09.595375 u2DelayCellOfst[5]=0 cells (0 PI)
8125 12:21:09.598464 u2DelayCellOfst[6]=20 cells (6 PI)
8126 12:21:09.601660 u2DelayCellOfst[7]=20 cells (6 PI)
8127 12:21:09.604856 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8128 12:21:09.608254 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8129 12:21:09.611811 == TX Byte 1 ==
8130 12:21:09.615405 u2DelayCellOfst[8]=0 cells (0 PI)
8131 12:21:09.618357 u2DelayCellOfst[9]=3 cells (1 PI)
8132 12:21:09.618833 u2DelayCellOfst[10]=6 cells (2 PI)
8133 12:21:09.621837 u2DelayCellOfst[11]=3 cells (1 PI)
8134 12:21:09.625047 u2DelayCellOfst[12]=13 cells (4 PI)
8135 12:21:09.628046 u2DelayCellOfst[13]=13 cells (4 PI)
8136 12:21:09.631808 u2DelayCellOfst[14]=17 cells (5 PI)
8137 12:21:09.635198 u2DelayCellOfst[15]=13 cells (4 PI)
8138 12:21:09.641336 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8139 12:21:09.644664 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8140 12:21:09.645167 DramC Write-DBI on
8141 12:21:09.645539 ==
8142 12:21:09.647944 Dram Type= 6, Freq= 0, CH_0, rank 1
8143 12:21:09.654550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8144 12:21:09.655128 ==
8145 12:21:09.655499
8146 12:21:09.655842
8147 12:21:09.656172 TX Vref Scan disable
8148 12:21:09.658883 == TX Byte 0 ==
8149 12:21:09.661917 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8150 12:21:09.665463 == TX Byte 1 ==
8151 12:21:09.669324 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8152 12:21:09.672588 DramC Write-DBI off
8153 12:21:09.673121
8154 12:21:09.673495 [DATLAT]
8155 12:21:09.673838 Freq=1600, CH0 RK1
8156 12:21:09.674173
8157 12:21:09.675835 DATLAT Default: 0xf
8158 12:21:09.676308 0, 0xFFFF, sum = 0
8159 12:21:09.679499 1, 0xFFFF, sum = 0
8160 12:21:09.679978 2, 0xFFFF, sum = 0
8161 12:21:09.682295 3, 0xFFFF, sum = 0
8162 12:21:09.685753 4, 0xFFFF, sum = 0
8163 12:21:09.686237 5, 0xFFFF, sum = 0
8164 12:21:09.688720 6, 0xFFFF, sum = 0
8165 12:21:09.689242 7, 0xFFFF, sum = 0
8166 12:21:09.692060 8, 0xFFFF, sum = 0
8167 12:21:09.692537 9, 0xFFFF, sum = 0
8168 12:21:09.695380 10, 0xFFFF, sum = 0
8169 12:21:09.695857 11, 0xFFFF, sum = 0
8170 12:21:09.698568 12, 0xFFFF, sum = 0
8171 12:21:09.699046 13, 0xFFFF, sum = 0
8172 12:21:09.701843 14, 0x0, sum = 1
8173 12:21:09.702323 15, 0x0, sum = 2
8174 12:21:09.705134 16, 0x0, sum = 3
8175 12:21:09.705625 17, 0x0, sum = 4
8176 12:21:09.708514 best_step = 15
8177 12:21:09.709032
8178 12:21:09.709422 ==
8179 12:21:09.711952 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 12:21:09.715244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 12:21:09.715789 ==
8182 12:21:09.716165 RX Vref Scan: 0
8183 12:21:09.718990
8184 12:21:09.719610 RX Vref 0 -> 0, step: 1
8185 12:21:09.720182
8186 12:21:09.721921 RX Delay 19 -> 252, step: 4
8187 12:21:09.725492 iDelay=191, Bit 0, Center 130 (79 ~ 182) 104
8188 12:21:09.731877 iDelay=191, Bit 1, Center 134 (83 ~ 186) 104
8189 12:21:09.735377 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8190 12:21:09.738757 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8191 12:21:09.741873 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8192 12:21:09.745551 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8193 12:21:09.751846 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8194 12:21:09.755269 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8195 12:21:09.758747 iDelay=191, Bit 8, Center 118 (71 ~ 166) 96
8196 12:21:09.761708 iDelay=191, Bit 9, Center 114 (63 ~ 166) 104
8197 12:21:09.765189 iDelay=191, Bit 10, Center 128 (83 ~ 174) 92
8198 12:21:09.768134 iDelay=191, Bit 11, Center 122 (75 ~ 170) 96
8199 12:21:09.774931 iDelay=191, Bit 12, Center 128 (79 ~ 178) 100
8200 12:21:09.778485 iDelay=191, Bit 13, Center 130 (83 ~ 178) 96
8201 12:21:09.781698 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8202 12:21:09.784868 iDelay=191, Bit 15, Center 132 (83 ~ 182) 100
8203 12:21:09.785373 ==
8204 12:21:09.788374 Dram Type= 6, Freq= 0, CH_0, rank 1
8205 12:21:09.795137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8206 12:21:09.795610 ==
8207 12:21:09.795983 DQS Delay:
8208 12:21:09.798430 DQS0 = 0, DQS1 = 0
8209 12:21:09.798897 DQM Delay:
8210 12:21:09.801453 DQM0 = 132, DQM1 = 125
8211 12:21:09.801947 DQ Delay:
8212 12:21:09.804809 DQ0 =130, DQ1 =134, DQ2 =130, DQ3 =130
8213 12:21:09.808160 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =138
8214 12:21:09.811632 DQ8 =118, DQ9 =114, DQ10 =128, DQ11 =122
8215 12:21:09.814947 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8216 12:21:09.815460
8217 12:21:09.815981
8218 12:21:09.816643
8219 12:21:09.818118 [DramC_TX_OE_Calibration] TA2
8220 12:21:09.822126 Original DQ_B0 (3 6) =30, OEN = 27
8221 12:21:09.824648 Original DQ_B1 (3 6) =30, OEN = 27
8222 12:21:09.828029 24, 0x0, End_B0=24 End_B1=24
8223 12:21:09.831516 25, 0x0, End_B0=25 End_B1=25
8224 12:21:09.832237 26, 0x0, End_B0=26 End_B1=26
8225 12:21:09.834853 27, 0x0, End_B0=27 End_B1=27
8226 12:21:09.838219 28, 0x0, End_B0=28 End_B1=28
8227 12:21:09.841488 29, 0x0, End_B0=29 End_B1=29
8228 12:21:09.842035 30, 0x0, End_B0=30 End_B1=30
8229 12:21:09.844502 31, 0x4545, End_B0=30 End_B1=30
8230 12:21:09.847835 Byte0 end_step=30 best_step=27
8231 12:21:09.851223 Byte1 end_step=30 best_step=27
8232 12:21:09.854465 Byte0 TX OE(2T, 0.5T) = (3, 3)
8233 12:21:09.857895 Byte1 TX OE(2T, 0.5T) = (3, 3)
8234 12:21:09.858309
8235 12:21:09.858632
8236 12:21:09.864556 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f0c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 394 ps
8237 12:21:09.867880 CH0 RK1: MR19=303, MR18=1F0C
8238 12:21:09.874627 CH0_RK1: MR19=0x303, MR18=0x1F0C, DQSOSC=394, MR23=63, INC=23, DEC=15
8239 12:21:09.878017 [RxdqsGatingPostProcess] freq 1600
8240 12:21:09.881568 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8241 12:21:09.884448 best DQS0 dly(2T, 0.5T) = (1, 1)
8242 12:21:09.888519 best DQS1 dly(2T, 0.5T) = (1, 1)
8243 12:21:09.891507 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8244 12:21:09.894915 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8245 12:21:09.897974 best DQS0 dly(2T, 0.5T) = (1, 1)
8246 12:21:09.901284 best DQS1 dly(2T, 0.5T) = (1, 1)
8247 12:21:09.904409 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8248 12:21:09.907847 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8249 12:21:09.911015 Pre-setting of DQS Precalculation
8250 12:21:09.914352 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8251 12:21:09.914784 ==
8252 12:21:09.917713 Dram Type= 6, Freq= 0, CH_1, rank 0
8253 12:21:09.920895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 12:21:09.924555 ==
8255 12:21:09.927533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8256 12:21:09.931432 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8257 12:21:09.937562 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8258 12:21:09.944185 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8259 12:21:09.951598 [CA 0] Center 40 (11~70) winsize 60
8260 12:21:09.955174 [CA 1] Center 41 (12~71) winsize 60
8261 12:21:09.958321 [CA 2] Center 37 (8~67) winsize 60
8262 12:21:09.961779 [CA 3] Center 36 (6~66) winsize 61
8263 12:21:09.965182 [CA 4] Center 36 (6~66) winsize 61
8264 12:21:09.968156 [CA 5] Center 35 (5~66) winsize 62
8265 12:21:09.968736
8266 12:21:09.971224 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8267 12:21:09.971836
8268 12:21:09.974618 [CATrainingPosCal] consider 1 rank data
8269 12:21:09.977953 u2DelayCellTimex100 = 285/100 ps
8270 12:21:09.981135 CA0 delay=40 (11~70),Diff = 5 PI (17 cell)
8271 12:21:09.987948 CA1 delay=41 (12~71),Diff = 6 PI (20 cell)
8272 12:21:09.991299 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
8273 12:21:09.994829 CA3 delay=36 (6~66),Diff = 1 PI (3 cell)
8274 12:21:09.998423 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
8275 12:21:10.001082 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
8276 12:21:10.001558
8277 12:21:10.004618 CA PerBit enable=1, Macro0, CA PI delay=35
8278 12:21:10.005175
8279 12:21:10.007619 [CBTSetCACLKResult] CA Dly = 35
8280 12:21:10.011009 CS Dly: 8 (0~39)
8281 12:21:10.014599 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8282 12:21:10.017597 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8283 12:21:10.018061 ==
8284 12:21:10.021257 Dram Type= 6, Freq= 0, CH_1, rank 1
8285 12:21:10.024371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 12:21:10.027737 ==
8287 12:21:10.031107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 12:21:10.034444 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 12:21:10.041228 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 12:21:10.044205 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 12:21:10.055411 [CA 0] Center 42 (12~72) winsize 61
8292 12:21:10.057826 [CA 1] Center 42 (12~72) winsize 61
8293 12:21:10.061254 [CA 2] Center 37 (8~67) winsize 60
8294 12:21:10.064490 [CA 3] Center 37 (8~66) winsize 59
8295 12:21:10.067825 [CA 4] Center 37 (8~67) winsize 60
8296 12:21:10.071014 [CA 5] Center 36 (7~66) winsize 60
8297 12:21:10.071615
8298 12:21:10.074269 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8299 12:21:10.074870
8300 12:21:10.077657 [CATrainingPosCal] consider 2 rank data
8301 12:21:10.081140 u2DelayCellTimex100 = 285/100 ps
8302 12:21:10.084429 CA0 delay=41 (12~70),Diff = 5 PI (17 cell)
8303 12:21:10.091291 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8304 12:21:10.094576 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
8305 12:21:10.097715 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8306 12:21:10.100976 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8307 12:21:10.104545 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 12:21:10.105030
8309 12:21:10.108086 CA PerBit enable=1, Macro0, CA PI delay=36
8310 12:21:10.108697
8311 12:21:10.111048 [CBTSetCACLKResult] CA Dly = 36
8312 12:21:10.114100 CS Dly: 9 (0~42)
8313 12:21:10.117534 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 12:21:10.120820 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 12:21:10.121451
8316 12:21:10.124307 ----->DramcWriteLeveling(PI) begin...
8317 12:21:10.124842 ==
8318 12:21:10.127570 Dram Type= 6, Freq= 0, CH_1, rank 0
8319 12:21:10.133869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 12:21:10.134496 ==
8321 12:21:10.137320 Write leveling (Byte 0): 23 => 23
8322 12:21:10.137773 Write leveling (Byte 1): 28 => 28
8323 12:21:10.140708 DramcWriteLeveling(PI) end<-----
8324 12:21:10.141212
8325 12:21:10.141569 ==
8326 12:21:10.144618 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 12:21:10.150677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 12:21:10.151140 ==
8329 12:21:10.154132 [Gating] SW mode calibration
8330 12:21:10.160583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8331 12:21:10.163965 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8332 12:21:10.170719 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 12:21:10.173776 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 12:21:10.177174 1 4 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8335 12:21:10.183888 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8336 12:21:10.186956 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 12:21:10.190282 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 12:21:10.196772 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 12:21:10.200200 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 12:21:10.203584 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 12:21:10.210243 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8342 12:21:10.214166 1 5 8 | B1->B0 | 3131 2c2c | 1 0 | (1 1) (0 1)
8343 12:21:10.217052 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8344 12:21:10.220622 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8345 12:21:10.227095 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 12:21:10.230145 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 12:21:10.233590 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 12:21:10.240026 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 12:21:10.243806 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 12:21:10.247017 1 6 8 | B1->B0 | 2d2d 4141 | 0 0 | (0 0) (0 0)
8351 12:21:10.253583 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 12:21:10.256764 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 12:21:10.260038 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 12:21:10.266947 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 12:21:10.270613 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 12:21:10.273626 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 12:21:10.280189 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8358 12:21:10.283309 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8359 12:21:10.286937 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8360 12:21:10.293707 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8361 12:21:10.297159 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 12:21:10.300336 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 12:21:10.306774 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 12:21:10.310151 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 12:21:10.313432 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 12:21:10.320254 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 12:21:10.323247 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 12:21:10.326949 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 12:21:10.333226 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 12:21:10.336550 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 12:21:10.340200 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 12:21:10.346836 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 12:21:10.350065 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 12:21:10.353248 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8375 12:21:10.357403 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8376 12:21:10.360114 Total UI for P1: 0, mck2ui 16
8377 12:21:10.363485 best dqsien dly found for B0: ( 1, 9, 8)
8378 12:21:10.371033 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8379 12:21:10.373256 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 12:21:10.376598 Total UI for P1: 0, mck2ui 16
8381 12:21:10.380234 best dqsien dly found for B1: ( 1, 9, 12)
8382 12:21:10.383232 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8383 12:21:10.386431 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8384 12:21:10.386903
8385 12:21:10.389927 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8386 12:21:10.396680 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8387 12:21:10.397197 [Gating] SW calibration Done
8388 12:21:10.397576 ==
8389 12:21:10.400410 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 12:21:10.406199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 12:21:10.406773 ==
8392 12:21:10.407148 RX Vref Scan: 0
8393 12:21:10.407494
8394 12:21:10.409559 RX Vref 0 -> 0, step: 1
8395 12:21:10.410031
8396 12:21:10.412822 RX Delay 0 -> 252, step: 8
8397 12:21:10.416317 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8398 12:21:10.419427 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8399 12:21:10.423076 iDelay=200, Bit 2, Center 127 (80 ~ 175) 96
8400 12:21:10.426162 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8401 12:21:10.432632 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8402 12:21:10.436191 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8403 12:21:10.439537 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8404 12:21:10.442636 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8405 12:21:10.445765 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8406 12:21:10.452725 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8407 12:21:10.455819 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8408 12:21:10.459227 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8409 12:21:10.462701 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8410 12:21:10.465866 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8411 12:21:10.472468 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8412 12:21:10.476094 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8413 12:21:10.476703 ==
8414 12:21:10.479135 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 12:21:10.482734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 12:21:10.483311 ==
8417 12:21:10.485576 DQS Delay:
8418 12:21:10.486055 DQS0 = 0, DQS1 = 0
8419 12:21:10.486535 DQM Delay:
8420 12:21:10.489171 DQM0 = 139, DQM1 = 131
8421 12:21:10.489748 DQ Delay:
8422 12:21:10.492236 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8423 12:21:10.495825 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8424 12:21:10.499336 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8425 12:21:10.505687 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8426 12:21:10.506166
8427 12:21:10.506638
8428 12:21:10.507085 ==
8429 12:21:10.508906 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 12:21:10.512489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 12:21:10.513155 ==
8432 12:21:10.513597
8433 12:21:10.513947
8434 12:21:10.515587 TX Vref Scan disable
8435 12:21:10.516054 == TX Byte 0 ==
8436 12:21:10.522410 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8437 12:21:10.525756 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8438 12:21:10.526226 == TX Byte 1 ==
8439 12:21:10.532202 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8440 12:21:10.535544 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8441 12:21:10.536031 ==
8442 12:21:10.538689 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 12:21:10.541849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 12:21:10.542314 ==
8445 12:21:10.556063
8446 12:21:10.559736 TX Vref early break, caculate TX vref
8447 12:21:10.562836 TX Vref=16, minBit 11, minWin=22, winSum=372
8448 12:21:10.565823 TX Vref=18, minBit 1, minWin=23, winSum=383
8449 12:21:10.569292 TX Vref=20, minBit 15, minWin=23, winSum=389
8450 12:21:10.572663 TX Vref=22, minBit 15, minWin=24, winSum=406
8451 12:21:10.576285 TX Vref=24, minBit 15, minWin=24, winSum=412
8452 12:21:10.582994 TX Vref=26, minBit 1, minWin=25, winSum=419
8453 12:21:10.585840 TX Vref=28, minBit 10, minWin=25, winSum=426
8454 12:21:10.589508 TX Vref=30, minBit 12, minWin=25, winSum=419
8455 12:21:10.592638 TX Vref=32, minBit 10, minWin=24, winSum=410
8456 12:21:10.596154 TX Vref=34, minBit 5, minWin=24, winSum=400
8457 12:21:10.602622 [TxChooseVref] Worse bit 10, Min win 25, Win sum 426, Final Vref 28
8458 12:21:10.603168
8459 12:21:10.605805 Final TX Range 0 Vref 28
8460 12:21:10.606267
8461 12:21:10.606626 ==
8462 12:21:10.608981 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 12:21:10.612448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 12:21:10.612912 ==
8465 12:21:10.613332
8466 12:21:10.613672
8467 12:21:10.616099 TX Vref Scan disable
8468 12:21:10.622668 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8469 12:21:10.623157 == TX Byte 0 ==
8470 12:21:10.626111 u2DelayCellOfst[0]=13 cells (4 PI)
8471 12:21:10.629191 u2DelayCellOfst[1]=6 cells (2 PI)
8472 12:21:10.632674 u2DelayCellOfst[2]=0 cells (0 PI)
8473 12:21:10.635946 u2DelayCellOfst[3]=3 cells (1 PI)
8474 12:21:10.639290 u2DelayCellOfst[4]=6 cells (2 PI)
8475 12:21:10.642154 u2DelayCellOfst[5]=17 cells (5 PI)
8476 12:21:10.645968 u2DelayCellOfst[6]=17 cells (5 PI)
8477 12:21:10.648902 u2DelayCellOfst[7]=6 cells (2 PI)
8478 12:21:10.652009 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8479 12:21:10.655492 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8480 12:21:10.658898 == TX Byte 1 ==
8481 12:21:10.662363 u2DelayCellOfst[8]=0 cells (0 PI)
8482 12:21:10.662827 u2DelayCellOfst[9]=0 cells (0 PI)
8483 12:21:10.665554 u2DelayCellOfst[10]=6 cells (2 PI)
8484 12:21:10.668819 u2DelayCellOfst[11]=3 cells (1 PI)
8485 12:21:10.672110 u2DelayCellOfst[12]=13 cells (4 PI)
8486 12:21:10.675768 u2DelayCellOfst[13]=10 cells (3 PI)
8487 12:21:10.679082 u2DelayCellOfst[14]=13 cells (4 PI)
8488 12:21:10.682252 u2DelayCellOfst[15]=10 cells (3 PI)
8489 12:21:10.685611 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8490 12:21:10.692278 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8491 12:21:10.692845 DramC Write-DBI on
8492 12:21:10.693294 ==
8493 12:21:10.695546 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 12:21:10.702476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 12:21:10.703044 ==
8496 12:21:10.703410
8497 12:21:10.703745
8498 12:21:10.704068 TX Vref Scan disable
8499 12:21:10.706007 == TX Byte 0 ==
8500 12:21:10.709063 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8501 12:21:10.713138 == TX Byte 1 ==
8502 12:21:10.716322 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8503 12:21:10.719291 DramC Write-DBI off
8504 12:21:10.719754
8505 12:21:10.720114 [DATLAT]
8506 12:21:10.720450 Freq=1600, CH1 RK0
8507 12:21:10.720777
8508 12:21:10.723322 DATLAT Default: 0xf
8509 12:21:10.723931 0, 0xFFFF, sum = 0
8510 12:21:10.725760 1, 0xFFFF, sum = 0
8511 12:21:10.726384 2, 0xFFFF, sum = 0
8512 12:21:10.729601 3, 0xFFFF, sum = 0
8513 12:21:10.732654 4, 0xFFFF, sum = 0
8514 12:21:10.733161 5, 0xFFFF, sum = 0
8515 12:21:10.735907 6, 0xFFFF, sum = 0
8516 12:21:10.736373 7, 0xFFFF, sum = 0
8517 12:21:10.739318 8, 0xFFFF, sum = 0
8518 12:21:10.739938 9, 0xFFFF, sum = 0
8519 12:21:10.742920 10, 0xFFFF, sum = 0
8520 12:21:10.743387 11, 0xFFFF, sum = 0
8521 12:21:10.745638 12, 0xFFFF, sum = 0
8522 12:21:10.746129 13, 0xFFFF, sum = 0
8523 12:21:10.749006 14, 0x0, sum = 1
8524 12:21:10.749476 15, 0x0, sum = 2
8525 12:21:10.752728 16, 0x0, sum = 3
8526 12:21:10.753343 17, 0x0, sum = 4
8527 12:21:10.755663 best_step = 15
8528 12:21:10.756176
8529 12:21:10.756683 ==
8530 12:21:10.759137 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 12:21:10.762414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 12:21:10.763043 ==
8533 12:21:10.765414 RX Vref Scan: 1
8534 12:21:10.765876
8535 12:21:10.766303 Set Vref Range= 24 -> 127
8536 12:21:10.766726
8537 12:21:10.768799 RX Vref 24 -> 127, step: 1
8538 12:21:10.769319
8539 12:21:10.772565 RX Delay 19 -> 252, step: 4
8540 12:21:10.773236
8541 12:21:10.775438 Set Vref, RX VrefLevel [Byte0]: 24
8542 12:21:10.778734 [Byte1]: 24
8543 12:21:10.779201
8544 12:21:10.782170 Set Vref, RX VrefLevel [Byte0]: 25
8545 12:21:10.785698 [Byte1]: 25
8546 12:21:10.786338
8547 12:21:10.789068 Set Vref, RX VrefLevel [Byte0]: 26
8548 12:21:10.791806 [Byte1]: 26
8549 12:21:10.795747
8550 12:21:10.796382 Set Vref, RX VrefLevel [Byte0]: 27
8551 12:21:10.799108 [Byte1]: 27
8552 12:21:10.803679
8553 12:21:10.804090 Set Vref, RX VrefLevel [Byte0]: 28
8554 12:21:10.807503 [Byte1]: 28
8555 12:21:10.811371
8556 12:21:10.811941 Set Vref, RX VrefLevel [Byte0]: 29
8557 12:21:10.814693 [Byte1]: 29
8558 12:21:10.818731
8559 12:21:10.819145 Set Vref, RX VrefLevel [Byte0]: 30
8560 12:21:10.822047 [Byte1]: 30
8561 12:21:10.826665
8562 12:21:10.827387 Set Vref, RX VrefLevel [Byte0]: 31
8563 12:21:10.830034 [Byte1]: 31
8564 12:21:10.833933
8565 12:21:10.834356 Set Vref, RX VrefLevel [Byte0]: 32
8566 12:21:10.837247 [Byte1]: 32
8567 12:21:10.841382
8568 12:21:10.841822 Set Vref, RX VrefLevel [Byte0]: 33
8569 12:21:10.844797 [Byte1]: 33
8570 12:21:10.849098
8571 12:21:10.849525 Set Vref, RX VrefLevel [Byte0]: 34
8572 12:21:10.852504 [Byte1]: 34
8573 12:21:10.856502
8574 12:21:10.857071 Set Vref, RX VrefLevel [Byte0]: 35
8575 12:21:10.859875 [Byte1]: 35
8576 12:21:10.864099
8577 12:21:10.864524 Set Vref, RX VrefLevel [Byte0]: 36
8578 12:21:10.867605 [Byte1]: 36
8579 12:21:10.871728
8580 12:21:10.872152 Set Vref, RX VrefLevel [Byte0]: 37
8581 12:21:10.874916 [Byte1]: 37
8582 12:21:10.879290
8583 12:21:10.879715 Set Vref, RX VrefLevel [Byte0]: 38
8584 12:21:10.882416 [Byte1]: 38
8585 12:21:10.886752
8586 12:21:10.887306 Set Vref, RX VrefLevel [Byte0]: 39
8587 12:21:10.890176 [Byte1]: 39
8588 12:21:10.894667
8589 12:21:10.895091 Set Vref, RX VrefLevel [Byte0]: 40
8590 12:21:10.897941 [Byte1]: 40
8591 12:21:10.901958
8592 12:21:10.902383 Set Vref, RX VrefLevel [Byte0]: 41
8593 12:21:10.905509 [Byte1]: 41
8594 12:21:10.909911
8595 12:21:10.910368 Set Vref, RX VrefLevel [Byte0]: 42
8596 12:21:10.916039 [Byte1]: 42
8597 12:21:10.916468
8598 12:21:10.919351 Set Vref, RX VrefLevel [Byte0]: 43
8599 12:21:10.922742 [Byte1]: 43
8600 12:21:10.923167
8601 12:21:10.925732 Set Vref, RX VrefLevel [Byte0]: 44
8602 12:21:10.929369 [Byte1]: 44
8603 12:21:10.929795
8604 12:21:10.932525 Set Vref, RX VrefLevel [Byte0]: 45
8605 12:21:10.936010 [Byte1]: 45
8606 12:21:10.939849
8607 12:21:10.940273 Set Vref, RX VrefLevel [Byte0]: 46
8608 12:21:10.943400 [Byte1]: 46
8609 12:21:10.947575
8610 12:21:10.947999 Set Vref, RX VrefLevel [Byte0]: 47
8611 12:21:10.950555 [Byte1]: 47
8612 12:21:10.955175
8613 12:21:10.955621 Set Vref, RX VrefLevel [Byte0]: 48
8614 12:21:10.958618 [Byte1]: 48
8615 12:21:10.962674
8616 12:21:10.963101 Set Vref, RX VrefLevel [Byte0]: 49
8617 12:21:10.966610 [Byte1]: 49
8618 12:21:10.970666
8619 12:21:10.971226 Set Vref, RX VrefLevel [Byte0]: 50
8620 12:21:10.973753 [Byte1]: 50
8621 12:21:10.978076
8622 12:21:10.978505 Set Vref, RX VrefLevel [Byte0]: 51
8623 12:21:10.981350 [Byte1]: 51
8624 12:21:10.985709
8625 12:21:10.986237 Set Vref, RX VrefLevel [Byte0]: 52
8626 12:21:10.988994 [Byte1]: 52
8627 12:21:10.993087
8628 12:21:10.993699 Set Vref, RX VrefLevel [Byte0]: 53
8629 12:21:10.996079 [Byte1]: 53
8630 12:21:11.000714
8631 12:21:11.001336 Set Vref, RX VrefLevel [Byte0]: 54
8632 12:21:11.003988 [Byte1]: 54
8633 12:21:11.008467
8634 12:21:11.009055 Set Vref, RX VrefLevel [Byte0]: 55
8635 12:21:11.011494 [Byte1]: 55
8636 12:21:11.015600
8637 12:21:11.016026 Set Vref, RX VrefLevel [Byte0]: 56
8638 12:21:11.019032 [Byte1]: 56
8639 12:21:11.023260
8640 12:21:11.023701 Set Vref, RX VrefLevel [Byte0]: 57
8641 12:21:11.026366 [Byte1]: 57
8642 12:21:11.030689
8643 12:21:11.031114 Set Vref, RX VrefLevel [Byte0]: 58
8644 12:21:11.034373 [Byte1]: 58
8645 12:21:11.038191
8646 12:21:11.038616 Set Vref, RX VrefLevel [Byte0]: 59
8647 12:21:11.041634 [Byte1]: 59
8648 12:21:11.045933
8649 12:21:11.046403 Set Vref, RX VrefLevel [Byte0]: 60
8650 12:21:11.049074 [Byte1]: 60
8651 12:21:11.053417
8652 12:21:11.053885 Set Vref, RX VrefLevel [Byte0]: 61
8653 12:21:11.057221 [Byte1]: 61
8654 12:21:11.061449
8655 12:21:11.061921 Set Vref, RX VrefLevel [Byte0]: 62
8656 12:21:11.064526 [Byte1]: 62
8657 12:21:11.068625
8658 12:21:11.069371 Set Vref, RX VrefLevel [Byte0]: 63
8659 12:21:11.071971 [Byte1]: 63
8660 12:21:11.076431
8661 12:21:11.077069 Set Vref, RX VrefLevel [Byte0]: 64
8662 12:21:11.079665 [Byte1]: 64
8663 12:21:11.084201
8664 12:21:11.084762 Set Vref, RX VrefLevel [Byte0]: 65
8665 12:21:11.087187 [Byte1]: 65
8666 12:21:11.091768
8667 12:21:11.092375 Set Vref, RX VrefLevel [Byte0]: 66
8668 12:21:11.094553 [Byte1]: 66
8669 12:21:11.099032
8670 12:21:11.099498 Set Vref, RX VrefLevel [Byte0]: 67
8671 12:21:11.102194 [Byte1]: 67
8672 12:21:11.106769
8673 12:21:11.107343 Set Vref, RX VrefLevel [Byte0]: 68
8674 12:21:11.110186 [Byte1]: 68
8675 12:21:11.114079
8676 12:21:11.114536 Set Vref, RX VrefLevel [Byte0]: 69
8677 12:21:11.117548 [Byte1]: 69
8678 12:21:11.121545
8679 12:21:11.122091 Set Vref, RX VrefLevel [Byte0]: 70
8680 12:21:11.125015 [Byte1]: 70
8681 12:21:11.129453
8682 12:21:11.129915 Set Vref, RX VrefLevel [Byte0]: 71
8683 12:21:11.132864 [Byte1]: 71
8684 12:21:11.136700
8685 12:21:11.137230 Set Vref, RX VrefLevel [Byte0]: 72
8686 12:21:11.140114 [Byte1]: 72
8687 12:21:11.144589
8688 12:21:11.145079 Set Vref, RX VrefLevel [Byte0]: 73
8689 12:21:11.147614 [Byte1]: 73
8690 12:21:11.151863
8691 12:21:11.152324 Final RX Vref Byte 0 = 63 to rank0
8692 12:21:11.155424 Final RX Vref Byte 1 = 64 to rank0
8693 12:21:11.158481 Final RX Vref Byte 0 = 63 to rank1
8694 12:21:11.162571 Final RX Vref Byte 1 = 64 to rank1==
8695 12:21:11.165464 Dram Type= 6, Freq= 0, CH_1, rank 0
8696 12:21:11.172007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8697 12:21:11.172482 ==
8698 12:21:11.172855 DQS Delay:
8699 12:21:11.173260 DQS0 = 0, DQS1 = 0
8700 12:21:11.175068 DQM Delay:
8701 12:21:11.175535 DQM0 = 135, DQM1 = 128
8702 12:21:11.178559 DQ Delay:
8703 12:21:11.181822 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =134
8704 12:21:11.185700 DQ4 =132, DQ5 =146, DQ6 =148, DQ7 =132
8705 12:21:11.188288 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =120
8706 12:21:11.191688 DQ12 =140, DQ13 =134, DQ14 =134, DQ15 =134
8707 12:21:11.192255
8708 12:21:11.192769
8709 12:21:11.193214
8710 12:21:11.195003 [DramC_TX_OE_Calibration] TA2
8711 12:21:11.198304 Original DQ_B0 (3 6) =30, OEN = 27
8712 12:21:11.201549 Original DQ_B1 (3 6) =30, OEN = 27
8713 12:21:11.204831 24, 0x0, End_B0=24 End_B1=24
8714 12:21:11.205360 25, 0x0, End_B0=25 End_B1=25
8715 12:21:11.208295 26, 0x0, End_B0=26 End_B1=26
8716 12:21:11.211668 27, 0x0, End_B0=27 End_B1=27
8717 12:21:11.215335 28, 0x0, End_B0=28 End_B1=28
8718 12:21:11.218479 29, 0x0, End_B0=29 End_B1=29
8719 12:21:11.218963 30, 0x0, End_B0=30 End_B1=30
8720 12:21:11.221374 31, 0x4141, End_B0=30 End_B1=30
8721 12:21:11.224816 Byte0 end_step=30 best_step=27
8722 12:21:11.228039 Byte1 end_step=30 best_step=27
8723 12:21:11.232371 Byte0 TX OE(2T, 0.5T) = (3, 3)
8724 12:21:11.234792 Byte1 TX OE(2T, 0.5T) = (3, 3)
8725 12:21:11.235281
8726 12:21:11.235697
8727 12:21:11.241600 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8728 12:21:11.245034 CH1 RK0: MR19=303, MR18=1523
8729 12:21:11.251722 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8730 12:21:11.252285
8731 12:21:11.255174 ----->DramcWriteLeveling(PI) begin...
8732 12:21:11.255915 ==
8733 12:21:11.258222 Dram Type= 6, Freq= 0, CH_1, rank 1
8734 12:21:11.261800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 12:21:11.262316 ==
8736 12:21:11.264895 Write leveling (Byte 0): 27 => 27
8737 12:21:11.268525 Write leveling (Byte 1): 31 => 31
8738 12:21:11.271434 DramcWriteLeveling(PI) end<-----
8739 12:21:11.271833
8740 12:21:11.272174 ==
8741 12:21:11.274915 Dram Type= 6, Freq= 0, CH_1, rank 1
8742 12:21:11.278070 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8743 12:21:11.278629 ==
8744 12:21:11.281499 [Gating] SW mode calibration
8745 12:21:11.288189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8746 12:21:11.294758 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8747 12:21:11.298212 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 12:21:11.301807 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 12:21:11.308156 1 4 8 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
8750 12:21:11.311358 1 4 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
8751 12:21:11.314888 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 12:21:11.321721 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 12:21:11.324739 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 12:21:11.328309 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 12:21:11.335074 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 12:21:11.338153 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8757 12:21:11.341950 1 5 8 | B1->B0 | 2d2d 3434 | 0 1 | (1 0) (1 0)
8758 12:21:11.347918 1 5 12 | B1->B0 | 2323 3030 | 0 1 | (1 0) (1 0)
8759 12:21:11.351510 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 12:21:11.354740 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 12:21:11.361099 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 12:21:11.364428 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 12:21:11.367700 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 12:21:11.374824 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 12:21:11.378057 1 6 8 | B1->B0 | 3d3d 2626 | 1 1 | (0 0) (0 0)
8766 12:21:11.381512 1 6 12 | B1->B0 | 4646 3636 | 0 0 | (0 0) (0 0)
8767 12:21:11.387805 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 12:21:11.391431 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 12:21:11.394304 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 12:21:11.398020 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 12:21:11.404267 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 12:21:11.407998 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 12:21:11.410986 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8774 12:21:11.418052 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8775 12:21:11.421033 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 12:21:11.424298 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 12:21:11.431117 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 12:21:11.434185 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 12:21:11.437886 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 12:21:11.444676 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 12:21:11.447678 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 12:21:11.450793 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 12:21:11.457591 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 12:21:11.460606 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 12:21:11.464111 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 12:21:11.470739 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 12:21:11.473801 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 12:21:11.476978 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 12:21:11.483673 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8790 12:21:11.487446 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8791 12:21:11.490666 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 12:21:11.493990 Total UI for P1: 0, mck2ui 16
8793 12:21:11.497264 best dqsien dly found for B0: ( 1, 9, 10)
8794 12:21:11.500349 Total UI for P1: 0, mck2ui 16
8795 12:21:11.503718 best dqsien dly found for B1: ( 1, 9, 10)
8796 12:21:11.506846 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8797 12:21:11.510257 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8798 12:21:11.510707
8799 12:21:11.516807 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8800 12:21:11.520166 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8801 12:21:11.523523 [Gating] SW calibration Done
8802 12:21:11.523944 ==
8803 12:21:11.526891 Dram Type= 6, Freq= 0, CH_1, rank 1
8804 12:21:11.530154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8805 12:21:11.530574 ==
8806 12:21:11.530906 RX Vref Scan: 0
8807 12:21:11.533526
8808 12:21:11.533943 RX Vref 0 -> 0, step: 1
8809 12:21:11.534269
8810 12:21:11.536786 RX Delay 0 -> 252, step: 8
8811 12:21:11.540132 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8812 12:21:11.543554 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8813 12:21:11.546926 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8814 12:21:11.553625 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8815 12:21:11.556646 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8816 12:21:11.560191 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8817 12:21:11.563409 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8818 12:21:11.566789 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8819 12:21:11.573267 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8820 12:21:11.576402 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8821 12:21:11.579651 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8822 12:21:11.583378 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8823 12:21:11.589879 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8824 12:21:11.593451 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8825 12:21:11.596391 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8826 12:21:11.599770 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8827 12:21:11.600306 ==
8828 12:21:11.603328 Dram Type= 6, Freq= 0, CH_1, rank 1
8829 12:21:11.606972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8830 12:21:11.609873 ==
8831 12:21:11.610299 DQS Delay:
8832 12:21:11.610631 DQS0 = 0, DQS1 = 0
8833 12:21:11.613287 DQM Delay:
8834 12:21:11.613735 DQM0 = 138, DQM1 = 130
8835 12:21:11.616647 DQ Delay:
8836 12:21:11.619750 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8837 12:21:11.623101 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =139
8838 12:21:11.626421 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8839 12:21:11.629622 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8840 12:21:11.630089
8841 12:21:11.630474
8842 12:21:11.630783 ==
8843 12:21:11.633116 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 12:21:11.636580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 12:21:11.637060 ==
8846 12:21:11.639576
8847 12:21:11.639997
8848 12:21:11.640330 TX Vref Scan disable
8849 12:21:11.643161 == TX Byte 0 ==
8850 12:21:11.646317 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8851 12:21:11.649672 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8852 12:21:11.652892 == TX Byte 1 ==
8853 12:21:11.656321 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8854 12:21:11.659516 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8855 12:21:11.659942 ==
8856 12:21:11.663274 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 12:21:11.669500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 12:21:11.669922 ==
8859 12:21:11.682650
8860 12:21:11.685645 TX Vref early break, caculate TX vref
8861 12:21:11.688726 TX Vref=16, minBit 9, minWin=22, winSum=384
8862 12:21:11.692418 TX Vref=18, minBit 8, minWin=23, winSum=388
8863 12:21:11.695861 TX Vref=20, minBit 9, minWin=23, winSum=397
8864 12:21:11.698849 TX Vref=22, minBit 9, minWin=23, winSum=403
8865 12:21:11.702357 TX Vref=24, minBit 9, minWin=24, winSum=414
8866 12:21:11.708873 TX Vref=26, minBit 9, minWin=25, winSum=420
8867 12:21:11.712488 TX Vref=28, minBit 9, minWin=25, winSum=418
8868 12:21:11.715647 TX Vref=30, minBit 9, minWin=24, winSum=409
8869 12:21:11.719304 TX Vref=32, minBit 9, minWin=24, winSum=405
8870 12:21:11.722250 TX Vref=34, minBit 0, minWin=24, winSum=399
8871 12:21:11.725569 TX Vref=36, minBit 10, minWin=22, winSum=390
8872 12:21:11.732060 [TxChooseVref] Worse bit 9, Min win 25, Win sum 420, Final Vref 26
8873 12:21:11.732529
8874 12:21:11.735996 Final TX Range 0 Vref 26
8875 12:21:11.736463
8876 12:21:11.736843 ==
8877 12:21:11.738929 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 12:21:11.742094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 12:21:11.742562 ==
8880 12:21:11.742925
8881 12:21:11.743263
8882 12:21:11.745635 TX Vref Scan disable
8883 12:21:11.752598 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8884 12:21:11.753169 == TX Byte 0 ==
8885 12:21:11.755686 u2DelayCellOfst[0]=17 cells (5 PI)
8886 12:21:11.758991 u2DelayCellOfst[1]=13 cells (4 PI)
8887 12:21:11.762273 u2DelayCellOfst[2]=0 cells (0 PI)
8888 12:21:11.765322 u2DelayCellOfst[3]=6 cells (2 PI)
8889 12:21:11.769276 u2DelayCellOfst[4]=6 cells (2 PI)
8890 12:21:11.772666 u2DelayCellOfst[5]=20 cells (6 PI)
8891 12:21:11.775495 u2DelayCellOfst[6]=17 cells (5 PI)
8892 12:21:11.779133 u2DelayCellOfst[7]=6 cells (2 PI)
8893 12:21:11.782217 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8894 12:21:11.785399 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8895 12:21:11.788730 == TX Byte 1 ==
8896 12:21:11.792355 u2DelayCellOfst[8]=0 cells (0 PI)
8897 12:21:11.792914 u2DelayCellOfst[9]=6 cells (2 PI)
8898 12:21:11.795704 u2DelayCellOfst[10]=10 cells (3 PI)
8899 12:21:11.798714 u2DelayCellOfst[11]=3 cells (1 PI)
8900 12:21:11.802545 u2DelayCellOfst[12]=13 cells (4 PI)
8901 12:21:11.806319 u2DelayCellOfst[13]=17 cells (5 PI)
8902 12:21:11.808988 u2DelayCellOfst[14]=17 cells (5 PI)
8903 12:21:11.812132 u2DelayCellOfst[15]=17 cells (5 PI)
8904 12:21:11.815449 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8905 12:21:11.822084 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8906 12:21:11.822553 DramC Write-DBI on
8907 12:21:11.822923 ==
8908 12:21:11.825329 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 12:21:11.831932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 12:21:11.832497 ==
8911 12:21:11.832870
8912 12:21:11.833270
8913 12:21:11.833603 TX Vref Scan disable
8914 12:21:11.835440 == TX Byte 0 ==
8915 12:21:11.838847 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8916 12:21:11.842236 == TX Byte 1 ==
8917 12:21:11.845490 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8918 12:21:11.848983 DramC Write-DBI off
8919 12:21:11.849555
8920 12:21:11.849924 [DATLAT]
8921 12:21:11.850264 Freq=1600, CH1 RK1
8922 12:21:11.850596
8923 12:21:11.852124 DATLAT Default: 0xf
8924 12:21:11.852589 0, 0xFFFF, sum = 0
8925 12:21:11.855787 1, 0xFFFF, sum = 0
8926 12:21:11.858661 2, 0xFFFF, sum = 0
8927 12:21:11.859134 3, 0xFFFF, sum = 0
8928 12:21:11.862223 4, 0xFFFF, sum = 0
8929 12:21:11.862832 5, 0xFFFF, sum = 0
8930 12:21:11.865611 6, 0xFFFF, sum = 0
8931 12:21:11.866099 7, 0xFFFF, sum = 0
8932 12:21:11.868750 8, 0xFFFF, sum = 0
8933 12:21:11.869270 9, 0xFFFF, sum = 0
8934 12:21:11.872209 10, 0xFFFF, sum = 0
8935 12:21:11.872680 11, 0xFFFF, sum = 0
8936 12:21:11.875392 12, 0xFFFF, sum = 0
8937 12:21:11.875988 13, 0xFFFF, sum = 0
8938 12:21:11.878869 14, 0x0, sum = 1
8939 12:21:11.879407 15, 0x0, sum = 2
8940 12:21:11.881834 16, 0x0, sum = 3
8941 12:21:11.882313 17, 0x0, sum = 4
8942 12:21:11.885626 best_step = 15
8943 12:21:11.886140
8944 12:21:11.886796 ==
8945 12:21:11.888755 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 12:21:11.892334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 12:21:11.892900 ==
8948 12:21:11.895632 RX Vref Scan: 0
8949 12:21:11.896094
8950 12:21:11.896455 RX Vref 0 -> 0, step: 1
8951 12:21:11.896795
8952 12:21:11.898723 RX Delay 19 -> 252, step: 4
8953 12:21:11.902040 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8954 12:21:11.909025 iDelay=195, Bit 1, Center 132 (87 ~ 178) 92
8955 12:21:11.912289 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8956 12:21:11.915724 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8957 12:21:11.918768 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8958 12:21:11.922085 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8959 12:21:11.925517 iDelay=195, Bit 6, Center 146 (99 ~ 194) 96
8960 12:21:11.931956 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8961 12:21:11.935479 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8962 12:21:11.938382 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8963 12:21:11.941818 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8964 12:21:11.945551 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8965 12:21:11.952081 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8966 12:21:11.954950 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8967 12:21:11.958445 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8968 12:21:11.961859 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8969 12:21:11.962294 ==
8970 12:21:11.965082 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 12:21:11.971553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 12:21:11.971991 ==
8973 12:21:11.972420 DQS Delay:
8974 12:21:11.975037 DQS0 = 0, DQS1 = 0
8975 12:21:11.975467 DQM Delay:
8976 12:21:11.978448 DQM0 = 134, DQM1 = 129
8977 12:21:11.979037 DQ Delay:
8978 12:21:11.981913 DQ0 =138, DQ1 =132, DQ2 =120, DQ3 =132
8979 12:21:11.985013 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =132
8980 12:21:11.988110 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
8981 12:21:11.991846 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =140
8982 12:21:11.992329
8983 12:21:11.992809
8984 12:21:11.993302
8985 12:21:11.995088 [DramC_TX_OE_Calibration] TA2
8986 12:21:11.998454 Original DQ_B0 (3 6) =30, OEN = 27
8987 12:21:12.002007 Original DQ_B1 (3 6) =30, OEN = 27
8988 12:21:12.005323 24, 0x0, End_B0=24 End_B1=24
8989 12:21:12.008326 25, 0x0, End_B0=25 End_B1=25
8990 12:21:12.008815 26, 0x0, End_B0=26 End_B1=26
8991 12:21:12.011484 27, 0x0, End_B0=27 End_B1=27
8992 12:21:12.015367 28, 0x0, End_B0=28 End_B1=28
8993 12:21:12.018005 29, 0x0, End_B0=29 End_B1=29
8994 12:21:12.018492 30, 0x0, End_B0=30 End_B1=30
8995 12:21:12.021879 31, 0x4141, End_B0=30 End_B1=30
8996 12:21:12.024879 Byte0 end_step=30 best_step=27
8997 12:21:12.028290 Byte1 end_step=30 best_step=27
8998 12:21:12.031467 Byte0 TX OE(2T, 0.5T) = (3, 3)
8999 12:21:12.034751 Byte1 TX OE(2T, 0.5T) = (3, 3)
9000 12:21:12.035221
9001 12:21:12.035590
9002 12:21:12.041405 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9003 12:21:12.044806 CH1 RK1: MR19=303, MR18=1B06
9004 12:21:12.051305 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
9005 12:21:12.054527 [RxdqsGatingPostProcess] freq 1600
9006 12:21:12.058186 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9007 12:21:12.061312 best DQS0 dly(2T, 0.5T) = (1, 1)
9008 12:21:12.065113 best DQS1 dly(2T, 0.5T) = (1, 1)
9009 12:21:12.068100 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9010 12:21:12.071730 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9011 12:21:12.074782 best DQS0 dly(2T, 0.5T) = (1, 1)
9012 12:21:12.078144 best DQS1 dly(2T, 0.5T) = (1, 1)
9013 12:21:12.081791 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9014 12:21:12.084885 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9015 12:21:12.088490 Pre-setting of DQS Precalculation
9016 12:21:12.091784 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9017 12:21:12.098438 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9018 12:21:12.108131 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9019 12:21:12.108698
9020 12:21:12.109152
9021 12:21:12.111454 [Calibration Summary] 3200 Mbps
9022 12:21:12.111926 CH 0, Rank 0
9023 12:21:12.114678 SW Impedance : PASS
9024 12:21:12.115097 DUTY Scan : NO K
9025 12:21:12.118610 ZQ Calibration : PASS
9026 12:21:12.119175 Jitter Meter : NO K
9027 12:21:12.121525 CBT Training : PASS
9028 12:21:12.124836 Write leveling : PASS
9029 12:21:12.125407 RX DQS gating : PASS
9030 12:21:12.128065 RX DQ/DQS(RDDQC) : PASS
9031 12:21:12.131012 TX DQ/DQS : PASS
9032 12:21:12.131487 RX DATLAT : PASS
9033 12:21:12.134639 RX DQ/DQS(Engine): PASS
9034 12:21:12.138026 TX OE : PASS
9035 12:21:12.138594 All Pass.
9036 12:21:12.138966
9037 12:21:12.139309 CH 0, Rank 1
9038 12:21:12.141091 SW Impedance : PASS
9039 12:21:12.144408 DUTY Scan : NO K
9040 12:21:12.144878 ZQ Calibration : PASS
9041 12:21:12.147758 Jitter Meter : NO K
9042 12:21:12.151232 CBT Training : PASS
9043 12:21:12.151646 Write leveling : PASS
9044 12:21:12.154444 RX DQS gating : PASS
9045 12:21:12.157702 RX DQ/DQS(RDDQC) : PASS
9046 12:21:12.158160 TX DQ/DQS : PASS
9047 12:21:12.161142 RX DATLAT : PASS
9048 12:21:12.161603 RX DQ/DQS(Engine): PASS
9049 12:21:12.164170 TX OE : PASS
9050 12:21:12.164633 All Pass.
9051 12:21:12.165024
9052 12:21:12.167908 CH 1, Rank 0
9053 12:21:12.168424 SW Impedance : PASS
9054 12:21:12.171468 DUTY Scan : NO K
9055 12:21:12.174768 ZQ Calibration : PASS
9056 12:21:12.175229 Jitter Meter : NO K
9057 12:21:12.177684 CBT Training : PASS
9058 12:21:12.181153 Write leveling : PASS
9059 12:21:12.181630 RX DQS gating : PASS
9060 12:21:12.184393 RX DQ/DQS(RDDQC) : PASS
9061 12:21:12.187694 TX DQ/DQS : PASS
9062 12:21:12.188106 RX DATLAT : PASS
9063 12:21:12.191380 RX DQ/DQS(Engine): PASS
9064 12:21:12.194440 TX OE : PASS
9065 12:21:12.194903 All Pass.
9066 12:21:12.195265
9067 12:21:12.195599 CH 1, Rank 1
9068 12:21:12.197626 SW Impedance : PASS
9069 12:21:12.200999 DUTY Scan : NO K
9070 12:21:12.201465 ZQ Calibration : PASS
9071 12:21:12.204554 Jitter Meter : NO K
9072 12:21:12.207489 CBT Training : PASS
9073 12:21:12.207954 Write leveling : PASS
9074 12:21:12.210989 RX DQS gating : PASS
9075 12:21:12.211455 RX DQ/DQS(RDDQC) : PASS
9076 12:21:12.214172 TX DQ/DQS : PASS
9077 12:21:12.218065 RX DATLAT : PASS
9078 12:21:12.218531 RX DQ/DQS(Engine): PASS
9079 12:21:12.220919 TX OE : PASS
9080 12:21:12.221426 All Pass.
9081 12:21:12.221789
9082 12:21:12.224395 DramC Write-DBI on
9083 12:21:12.227180 PER_BANK_REFRESH: Hybrid Mode
9084 12:21:12.227262 TX_TRACKING: ON
9085 12:21:12.237261 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9086 12:21:12.243836 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9087 12:21:12.251097 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9088 12:21:12.257830 [FAST_K] Save calibration result to emmc
9089 12:21:12.258292 sync common calibartion params.
9090 12:21:12.260997 sync cbt_mode0:1, 1:1
9091 12:21:12.264271 dram_init: ddr_geometry: 2
9092 12:21:12.264735 dram_init: ddr_geometry: 2
9093 12:21:12.267913 dram_init: ddr_geometry: 2
9094 12:21:12.271444 0:dram_rank_size:100000000
9095 12:21:12.274846 1:dram_rank_size:100000000
9096 12:21:12.277712 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9097 12:21:12.280977 DFS_SHUFFLE_HW_MODE: ON
9098 12:21:12.284123 dramc_set_vcore_voltage set vcore to 725000
9099 12:21:12.287905 Read voltage for 1600, 0
9100 12:21:12.288473 Vio18 = 0
9101 12:21:12.288843 Vcore = 725000
9102 12:21:12.290879 Vdram = 0
9103 12:21:12.291445 Vddq = 0
9104 12:21:12.291810 Vmddr = 0
9105 12:21:12.294511 switch to 3200 Mbps bootup
9106 12:21:12.297575 [DramcRunTimeConfig]
9107 12:21:12.298038 PHYPLL
9108 12:21:12.298405 DPM_CONTROL_AFTERK: ON
9109 12:21:12.301252 PER_BANK_REFRESH: ON
9110 12:21:12.305386 REFRESH_OVERHEAD_REDUCTION: ON
9111 12:21:12.305956 CMD_PICG_NEW_MODE: OFF
9112 12:21:12.307859 XRTWTW_NEW_MODE: ON
9113 12:21:12.308320 XRTRTR_NEW_MODE: ON
9114 12:21:12.311046 TX_TRACKING: ON
9115 12:21:12.311509 RDSEL_TRACKING: OFF
9116 12:21:12.314644 DQS Precalculation for DVFS: ON
9117 12:21:12.317751 RX_TRACKING: OFF
9118 12:21:12.318213 HW_GATING DBG: ON
9119 12:21:12.320966 ZQCS_ENABLE_LP4: ON
9120 12:21:12.321453 RX_PICG_NEW_MODE: ON
9121 12:21:12.324211 TX_PICG_NEW_MODE: ON
9122 12:21:12.327754 ENABLE_RX_DCM_DPHY: ON
9123 12:21:12.328214 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9124 12:21:12.330993 DUMMY_READ_FOR_TRACKING: OFF
9125 12:21:12.334490 !!! SPM_CONTROL_AFTERK: OFF
9126 12:21:12.337472 !!! SPM could not control APHY
9127 12:21:12.337937 IMPEDANCE_TRACKING: ON
9128 12:21:12.341287 TEMP_SENSOR: ON
9129 12:21:12.341751 HW_SAVE_FOR_SR: OFF
9130 12:21:12.344164 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9131 12:21:12.347526 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9132 12:21:12.350819 Read ODT Tracking: ON
9133 12:21:12.354099 Refresh Rate DeBounce: ON
9134 12:21:12.354584 DFS_NO_QUEUE_FLUSH: ON
9135 12:21:12.357447 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9136 12:21:12.360850 ENABLE_DFS_RUNTIME_MRW: OFF
9137 12:21:12.364118 DDR_RESERVE_NEW_MODE: ON
9138 12:21:12.364586 MR_CBT_SWITCH_FREQ: ON
9139 12:21:12.367430 =========================
9140 12:21:12.386893 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9141 12:21:12.390099 dram_init: ddr_geometry: 2
9142 12:21:12.408245 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9143 12:21:12.411701 dram_init: dram init end (result: 0)
9144 12:21:12.418448 DRAM-K: Full calibration passed in 24485 msecs
9145 12:21:12.421680 MRC: failed to locate region type 0.
9146 12:21:12.422321 DRAM rank0 size:0x100000000,
9147 12:21:12.425253 DRAM rank1 size=0x100000000
9148 12:21:12.434972 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9149 12:21:12.441954 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9150 12:21:12.448135 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9151 12:21:12.454356 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9152 12:21:12.458040 DRAM rank0 size:0x100000000,
9153 12:21:12.461225 DRAM rank1 size=0x100000000
9154 12:21:12.461691 CBMEM:
9155 12:21:12.464962 IMD: root @ 0xfffff000 254 entries.
9156 12:21:12.467753 IMD: root @ 0xffffec00 62 entries.
9157 12:21:12.471267 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9158 12:21:12.477689 WARNING: RO_VPD is uninitialized or empty.
9159 12:21:12.480662 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9160 12:21:12.488319 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9161 12:21:12.500779 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9162 12:21:12.512916 BS: romstage times (exec / console): total (unknown) / 23987 ms
9163 12:21:12.513609
9164 12:21:12.513988
9165 12:21:12.522415 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9166 12:21:12.525624 ARM64: Exception handlers installed.
9167 12:21:12.528925 ARM64: Testing exception
9168 12:21:12.532686 ARM64: Done test exception
9169 12:21:12.533310 Enumerating buses...
9170 12:21:12.535544 Show all devs... Before device enumeration.
9171 12:21:12.538948 Root Device: enabled 1
9172 12:21:12.542497 CPU_CLUSTER: 0: enabled 1
9173 12:21:12.542965 CPU: 00: enabled 1
9174 12:21:12.545486 Compare with tree...
9175 12:21:12.545955 Root Device: enabled 1
9176 12:21:12.548906 CPU_CLUSTER: 0: enabled 1
9177 12:21:12.552544 CPU: 00: enabled 1
9178 12:21:12.553148 Root Device scanning...
9179 12:21:12.556037 scan_static_bus for Root Device
9180 12:21:12.559015 CPU_CLUSTER: 0 enabled
9181 12:21:12.562428 scan_static_bus for Root Device done
9182 12:21:12.565515 scan_bus: bus Root Device finished in 8 msecs
9183 12:21:12.565981 done
9184 12:21:12.572341 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9185 12:21:12.575832 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9186 12:21:12.582057 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9187 12:21:12.585463 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9188 12:21:12.588688 Allocating resources...
9189 12:21:12.592075 Reading resources...
9190 12:21:12.595495 Root Device read_resources bus 0 link: 0
9191 12:21:12.595964 DRAM rank0 size:0x100000000,
9192 12:21:12.598587 DRAM rank1 size=0x100000000
9193 12:21:12.602036 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9194 12:21:12.606133 CPU: 00 missing read_resources
9195 12:21:12.609600 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9196 12:21:12.615392 Root Device read_resources bus 0 link: 0 done
9197 12:21:12.615861 Done reading resources.
9198 12:21:12.621961 Show resources in subtree (Root Device)...After reading.
9199 12:21:12.625461 Root Device child on link 0 CPU_CLUSTER: 0
9200 12:21:12.628701 CPU_CLUSTER: 0 child on link 0 CPU: 00
9201 12:21:12.638231 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9202 12:21:12.638383 CPU: 00
9203 12:21:12.641622 Root Device assign_resources, bus 0 link: 0
9204 12:21:12.644743 CPU_CLUSTER: 0 missing set_resources
9205 12:21:12.651546 Root Device assign_resources, bus 0 link: 0 done
9206 12:21:12.651635 Done setting resources.
9207 12:21:12.658305 Show resources in subtree (Root Device)...After assigning values.
9208 12:21:12.661893 Root Device child on link 0 CPU_CLUSTER: 0
9209 12:21:12.665503 CPU_CLUSTER: 0 child on link 0 CPU: 00
9210 12:21:12.675241 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9211 12:21:12.675460 CPU: 00
9212 12:21:12.678075 Done allocating resources.
9213 12:21:12.681448 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9214 12:21:12.684700 Enabling resources...
9215 12:21:12.684874 done.
9216 12:21:12.691219 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9217 12:21:12.691498 Initializing devices...
9218 12:21:12.694720 Root Device init
9219 12:21:12.694961 init hardware done!
9220 12:21:12.698082 0x00000018: ctrlr->caps
9221 12:21:12.702193 52.000 MHz: ctrlr->f_max
9222 12:21:12.702596 0.400 MHz: ctrlr->f_min
9223 12:21:12.705061 0x40ff8080: ctrlr->voltages
9224 12:21:12.705461 sclk: 390625
9225 12:21:12.708318 Bus Width = 1
9226 12:21:12.708775 sclk: 390625
9227 12:21:12.711398 Bus Width = 1
9228 12:21:12.711864 Early init status = 3
9229 12:21:12.718221 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9230 12:21:12.721448 in-header: 03 fc 00 00 01 00 00 00
9231 12:21:12.721915 in-data: 00
9232 12:21:12.728144 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9233 12:21:12.731461 in-header: 03 fd 00 00 00 00 00 00
9234 12:21:12.734890 in-data:
9235 12:21:12.738225 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9236 12:21:12.742285 in-header: 03 fc 00 00 01 00 00 00
9237 12:21:12.745672 in-data: 00
9238 12:21:12.748497 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9239 12:21:12.754553 in-header: 03 fd 00 00 00 00 00 00
9240 12:21:12.757790 in-data:
9241 12:21:12.761436 [SSUSB] Setting up USB HOST controller...
9242 12:21:12.764239 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9243 12:21:12.767270 [SSUSB] phy power-on done.
9244 12:21:12.770787 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9245 12:21:12.777510 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9246 12:21:12.780979 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9247 12:21:12.787145 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9248 12:21:12.793998 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9249 12:21:12.800725 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9250 12:21:12.807290 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9251 12:21:12.813779 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9252 12:21:12.817238 SPM: binary array size = 0x9dc
9253 12:21:12.820611 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9254 12:21:12.827505 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9255 12:21:12.833728 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9256 12:21:12.840266 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9257 12:21:12.843633 configure_display: Starting display init
9258 12:21:12.877574 anx7625_power_on_init: Init interface.
9259 12:21:12.881016 anx7625_disable_pd_protocol: Disabled PD feature.
9260 12:21:12.884291 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9261 12:21:12.911583 anx7625_start_dp_work: Secure OCM version=00
9262 12:21:12.915039 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9263 12:21:12.929852 sp_tx_get_edid_block: EDID Block = 1
9264 12:21:13.032683 Extracted contents:
9265 12:21:13.035773 header: 00 ff ff ff ff ff ff 00
9266 12:21:13.039043 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9267 12:21:13.042519 version: 01 04
9268 12:21:13.046133 basic params: 95 1f 11 78 0a
9269 12:21:13.049338 chroma info: 76 90 94 55 54 90 27 21 50 54
9270 12:21:13.052074 established: 00 00 00
9271 12:21:13.059380 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9272 12:21:13.062410 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9273 12:21:13.069534 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9274 12:21:13.075649 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9275 12:21:13.082537 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9276 12:21:13.085450 extensions: 00
9277 12:21:13.085969 checksum: fb
9278 12:21:13.086377
9279 12:21:13.088874 Manufacturer: IVO Model 57d Serial Number 0
9280 12:21:13.092029 Made week 0 of 2020
9281 12:21:13.092815 EDID version: 1.4
9282 12:21:13.095374 Digital display
9283 12:21:13.098678 6 bits per primary color channel
9284 12:21:13.099306 DisplayPort interface
9285 12:21:13.102139 Maximum image size: 31 cm x 17 cm
9286 12:21:13.105796 Gamma: 220%
9287 12:21:13.106510 Check DPMS levels
9288 12:21:13.109042 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9289 12:21:13.112259 First detailed timing is preferred timing
9290 12:21:13.115778 Established timings supported:
9291 12:21:13.118959 Standard timings supported:
9292 12:21:13.122136 Detailed timings
9293 12:21:13.125298 Hex of detail: 383680a07038204018303c0035ae10000019
9294 12:21:13.128734 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9295 12:21:13.135220 0780 0798 07c8 0820 hborder 0
9296 12:21:13.138496 0438 043b 0447 0458 vborder 0
9297 12:21:13.141987 -hsync -vsync
9298 12:21:13.142571 Did detailed timing
9299 12:21:13.148635 Hex of detail: 000000000000000000000000000000000000
9300 12:21:13.149063 Manufacturer-specified data, tag 0
9301 12:21:13.155398 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9302 12:21:13.158311 ASCII string: InfoVision
9303 12:21:13.161601 Hex of detail: 000000fe00523134304e574635205248200a
9304 12:21:13.164838 ASCII string: R140NWF5 RH
9305 12:21:13.164983 Checksum
9306 12:21:13.168151 Checksum: 0xfb (valid)
9307 12:21:13.171301 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9308 12:21:13.174607 DSI data_rate: 832800000 bps
9309 12:21:13.181317 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9310 12:21:13.184787 anx7625_parse_edid: pixelclock(138800).
9311 12:21:13.187694 hactive(1920), hsync(48), hfp(24), hbp(88)
9312 12:21:13.191162 vactive(1080), vsync(12), vfp(3), vbp(17)
9313 12:21:13.194735 anx7625_dsi_config: config dsi.
9314 12:21:13.201276 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9315 12:21:13.214491 anx7625_dsi_config: success to config DSI
9316 12:21:13.218367 anx7625_dp_start: MIPI phy setup OK.
9317 12:21:13.221290 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9318 12:21:13.225148 mtk_ddp_mode_set invalid vrefresh 60
9319 12:21:13.227770 main_disp_path_setup
9320 12:21:13.228389 ovl_layer_smi_id_en
9321 12:21:13.231126 ovl_layer_smi_id_en
9322 12:21:13.231577 ccorr_config
9323 12:21:13.231927 aal_config
9324 12:21:13.234239 gamma_config
9325 12:21:13.234685 postmask_config
9326 12:21:13.237635 dither_config
9327 12:21:13.240872 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9328 12:21:13.247952 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9329 12:21:13.251021 Root Device init finished in 553 msecs
9330 12:21:13.254290 CPU_CLUSTER: 0 init
9331 12:21:13.260908 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9332 12:21:13.264599 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9333 12:21:13.267576 APU_MBOX 0x190000b0 = 0x10001
9334 12:21:13.270849 APU_MBOX 0x190001b0 = 0x10001
9335 12:21:13.274028 APU_MBOX 0x190005b0 = 0x10001
9336 12:21:13.277496 APU_MBOX 0x190006b0 = 0x10001
9337 12:21:13.280821 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9338 12:21:13.293699 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9339 12:21:13.305826 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9340 12:21:13.312518 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9341 12:21:13.324057 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9342 12:21:13.333296 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9343 12:21:13.336755 CPU_CLUSTER: 0 init finished in 81 msecs
9344 12:21:13.340115 Devices initialized
9345 12:21:13.343349 Show all devs... After init.
9346 12:21:13.343836 Root Device: enabled 1
9347 12:21:13.346588 CPU_CLUSTER: 0: enabled 1
9348 12:21:13.349765 CPU: 00: enabled 1
9349 12:21:13.353047 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9350 12:21:13.356699 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9351 12:21:13.359819 ELOG: NV offset 0x57f000 size 0x1000
9352 12:21:13.366480 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9353 12:21:13.373276 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9354 12:21:13.376710 ELOG: Event(17) added with size 13 at 2023-10-27 12:20:51 UTC
9355 12:21:13.382921 out: cmd=0x121: 03 db 21 01 00 00 00 00
9356 12:21:13.386322 in-header: 03 44 00 00 2c 00 00 00
9357 12:21:13.396341 in-data: 1b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9358 12:21:13.403384 ELOG: Event(A1) added with size 10 at 2023-10-27 12:20:51 UTC
9359 12:21:13.409620 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9360 12:21:13.416554 ELOG: Event(A0) added with size 9 at 2023-10-27 12:20:51 UTC
9361 12:21:13.419231 elog_add_boot_reason: Logged dev mode boot
9362 12:21:13.426129 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9363 12:21:13.426738 Finalize devices...
9364 12:21:13.429317 Devices finalized
9365 12:21:13.432706 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9366 12:21:13.435832 Writing coreboot table at 0xffe64000
9367 12:21:13.439165 0. 000000000010a000-0000000000113fff: RAMSTAGE
9368 12:21:13.442426 1. 0000000040000000-00000000400fffff: RAM
9369 12:21:13.449134 2. 0000000040100000-000000004032afff: RAMSTAGE
9370 12:21:13.452464 3. 000000004032b000-00000000545fffff: RAM
9371 12:21:13.455983 4. 0000000054600000-000000005465ffff: BL31
9372 12:21:13.459390 5. 0000000054660000-00000000ffe63fff: RAM
9373 12:21:13.465692 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9374 12:21:13.469116 7. 0000000100000000-000000023fffffff: RAM
9375 12:21:13.472193 Passing 5 GPIOs to payload:
9376 12:21:13.475552 NAME | PORT | POLARITY | VALUE
9377 12:21:13.479156 EC in RW | 0x000000aa | low | undefined
9378 12:21:13.485486 EC interrupt | 0x00000005 | low | undefined
9379 12:21:13.488907 TPM interrupt | 0x000000ab | high | undefined
9380 12:21:13.495617 SD card detect | 0x00000011 | high | undefined
9381 12:21:13.499197 speaker enable | 0x00000093 | high | undefined
9382 12:21:13.502207 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9383 12:21:13.505493 in-header: 03 f9 00 00 02 00 00 00
9384 12:21:13.509204 in-data: 02 00
9385 12:21:13.512119 ADC[4]: Raw value=900663 ID=7
9386 12:21:13.512671 ADC[3]: Raw value=213179 ID=1
9387 12:21:13.515478 RAM Code: 0x71
9388 12:21:13.518666 ADC[6]: Raw value=74502 ID=0
9389 12:21:13.519124 ADC[5]: Raw value=212441 ID=1
9390 12:21:13.522201 SKU Code: 0x1
9391 12:21:13.525266 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7bf0
9392 12:21:13.528614 coreboot table: 964 bytes.
9393 12:21:13.532205 IMD ROOT 0. 0xfffff000 0x00001000
9394 12:21:13.535543 IMD SMALL 1. 0xffffe000 0x00001000
9395 12:21:13.538504 RO MCACHE 2. 0xffffc000 0x00001104
9396 12:21:13.542050 CONSOLE 3. 0xfff7c000 0x00080000
9397 12:21:13.545350 FMAP 4. 0xfff7b000 0x00000452
9398 12:21:13.548977 TIME STAMP 5. 0xfff7a000 0x00000910
9399 12:21:13.552127 VBOOT WORK 6. 0xfff66000 0x00014000
9400 12:21:13.555376 RAMOOPS 7. 0xffe66000 0x00100000
9401 12:21:13.558215 COREBOOT 8. 0xffe64000 0x00002000
9402 12:21:13.562096 IMD small region:
9403 12:21:13.565231 IMD ROOT 0. 0xffffec00 0x00000400
9404 12:21:13.568295 VPD 1. 0xffffeb80 0x0000006c
9405 12:21:13.572025 MMC STATUS 2. 0xffffeb60 0x00000004
9406 12:21:13.574982 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9407 12:21:13.578460 Probing TPM: done!
9408 12:21:13.582059 Connected to device vid:did:rid of 1ae0:0028:00
9409 12:21:13.592412 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9410 12:21:13.595885 Initialized TPM device CR50 revision 0
9411 12:21:13.599566 Checking cr50 for pending updates
9412 12:21:13.603238 Reading cr50 TPM mode
9413 12:21:13.611975 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9414 12:21:13.618565 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9415 12:21:13.658558 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9416 12:21:13.661797 Checking segment from ROM address 0x40100000
9417 12:21:13.665506 Checking segment from ROM address 0x4010001c
9418 12:21:13.671958 Loading segment from ROM address 0x40100000
9419 12:21:13.672669 code (compression=0)
9420 12:21:13.682178 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9421 12:21:13.688542 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9422 12:21:13.689499 it's not compressed!
9423 12:21:13.695186 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9424 12:21:13.698582 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9425 12:21:13.719265 Loading segment from ROM address 0x4010001c
9426 12:21:13.719909 Entry Point 0x80000000
9427 12:21:13.722506 Loaded segments
9428 12:21:13.725905 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9429 12:21:13.732289 Jumping to boot code at 0x80000000(0xffe64000)
9430 12:21:13.738947 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9431 12:21:13.745856 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9432 12:21:13.753314 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9433 12:21:13.756730 Checking segment from ROM address 0x40100000
9434 12:21:13.759865 Checking segment from ROM address 0x4010001c
9435 12:21:13.766867 Loading segment from ROM address 0x40100000
9436 12:21:13.767295 code (compression=1)
9437 12:21:13.773441 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9438 12:21:13.783267 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9439 12:21:13.783837 using LZMA
9440 12:21:13.791707 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9441 12:21:13.798194 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9442 12:21:13.801665 Loading segment from ROM address 0x4010001c
9443 12:21:13.802112 Entry Point 0x54601000
9444 12:21:13.804857 Loaded segments
9445 12:21:13.808160 NOTICE: MT8192 bl31_setup
9446 12:21:13.815093 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9447 12:21:13.818695 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9448 12:21:13.821990 WARNING: region 0:
9449 12:21:13.825687 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9450 12:21:13.826261 WARNING: region 1:
9451 12:21:13.832101 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9452 12:21:13.835820 WARNING: region 2:
9453 12:21:13.838943 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9454 12:21:13.842099 WARNING: region 3:
9455 12:21:13.845469 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9456 12:21:13.848643 WARNING: region 4:
9457 12:21:13.855242 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9458 12:21:13.855730 WARNING: region 5:
9459 12:21:13.858676 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9460 12:21:13.862130 WARNING: region 6:
9461 12:21:13.865873 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 12:21:13.866357 WARNING: region 7:
9463 12:21:13.872056 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 12:21:13.878633 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9465 12:21:13.882270 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9466 12:21:13.885743 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9467 12:21:13.892215 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9468 12:21:13.895406 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9469 12:21:13.899150 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9470 12:21:13.905432 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9471 12:21:13.909147 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9472 12:21:13.912384 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9473 12:21:13.918977 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9474 12:21:13.922206 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9475 12:21:13.929281 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9476 12:21:13.932030 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9477 12:21:13.936044 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9478 12:21:13.942346 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9479 12:21:13.945468 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9480 12:21:13.948717 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9481 12:21:13.955505 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9482 12:21:13.959208 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9483 12:21:13.962345 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9484 12:21:13.968909 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9485 12:21:13.972259 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9486 12:21:13.978992 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9487 12:21:13.982288 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9488 12:21:13.988983 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9489 12:21:13.992706 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9490 12:21:13.995822 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9491 12:21:14.002438 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9492 12:21:14.005838 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9493 12:21:14.009482 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9494 12:21:14.015703 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9495 12:21:14.019215 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9496 12:21:14.022552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9497 12:21:14.029214 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9498 12:21:14.032470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9499 12:21:14.035579 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9500 12:21:14.039589 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9501 12:21:14.045582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9502 12:21:14.049138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9503 12:21:14.052582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9504 12:21:14.056409 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9505 12:21:14.062897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9506 12:21:14.066012 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9507 12:21:14.069324 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9508 12:21:14.072510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9509 12:21:14.078964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9510 12:21:14.082277 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9511 12:21:14.085781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9512 12:21:14.092197 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9513 12:21:14.095586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9514 12:21:14.102137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9515 12:21:14.105410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9516 12:21:14.108833 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9517 12:21:14.115775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9518 12:21:14.118755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9519 12:21:14.125210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9520 12:21:14.128898 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9521 12:21:14.132347 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9522 12:21:14.139151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9523 12:21:14.142322 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9524 12:21:14.148840 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9525 12:21:14.152124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9526 12:21:14.158952 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9527 12:21:14.162328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9528 12:21:14.168964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9529 12:21:14.172248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9530 12:21:14.175860 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9531 12:21:14.182547 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9532 12:21:14.185734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9533 12:21:14.192163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9534 12:21:14.195993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9535 12:21:14.199326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9536 12:21:14.205597 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9537 12:21:14.208857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9538 12:21:14.215689 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9539 12:21:14.218943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9540 12:21:14.225709 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9541 12:21:14.229277 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9542 12:21:14.235605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9543 12:21:14.239182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9544 12:21:14.242283 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9545 12:21:14.249173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9546 12:21:14.252167 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9547 12:21:14.258960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9548 12:21:14.262348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9549 12:21:14.269118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9550 12:21:14.272530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9551 12:21:14.275815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9552 12:21:14.282082 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9553 12:21:14.285850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9554 12:21:14.292335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9555 12:21:14.295795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9556 12:21:14.302440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9557 12:21:14.305711 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9558 12:21:14.309099 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9559 12:21:14.315686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9560 12:21:14.319043 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9561 12:21:14.322715 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9562 12:21:14.329201 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9563 12:21:14.332792 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9564 12:21:14.335877 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9565 12:21:14.342522 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9566 12:21:14.346057 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9567 12:21:14.349026 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9568 12:21:14.355874 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9569 12:21:14.358935 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9570 12:21:14.362433 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9571 12:21:14.368886 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9572 12:21:14.372589 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9573 12:21:14.379379 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9574 12:21:14.382660 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9575 12:21:14.385742 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9576 12:21:14.392839 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9577 12:21:14.396026 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9578 12:21:14.403179 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9579 12:21:14.406322 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9580 12:21:14.409479 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9581 12:21:14.416227 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9582 12:21:14.419237 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9583 12:21:14.422690 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9584 12:21:14.426322 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9585 12:21:14.432541 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9586 12:21:14.436084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9587 12:21:14.439200 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9588 12:21:14.442461 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9589 12:21:14.449220 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9590 12:21:14.452972 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9591 12:21:14.459267 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9592 12:21:14.462937 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9593 12:21:14.466013 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9594 12:21:14.472616 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9595 12:21:14.476160 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9596 12:21:14.483013 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9597 12:21:14.486093 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9598 12:21:14.489061 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9599 12:21:14.495975 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9600 12:21:14.499675 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9601 12:21:14.503201 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9602 12:21:14.509845 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9603 12:21:14.512812 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9604 12:21:14.519171 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9605 12:21:14.522632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9606 12:21:14.526175 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9607 12:21:14.532632 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9608 12:21:14.536218 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9609 12:21:14.542811 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9610 12:21:14.546188 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9611 12:21:14.549328 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9612 12:21:14.555742 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9613 12:21:14.559739 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9614 12:21:14.562705 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9615 12:21:14.569682 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9616 12:21:14.573127 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9617 12:21:14.579775 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9618 12:21:14.582545 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9619 12:21:14.586588 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9620 12:21:14.593128 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9621 12:21:14.595943 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9622 12:21:14.599628 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9623 12:21:14.606651 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9624 12:21:14.609491 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9625 12:21:14.616240 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9626 12:21:14.619420 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9627 12:21:14.626034 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9628 12:21:14.629161 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9629 12:21:14.633077 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9630 12:21:14.639248 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9631 12:21:14.642758 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9632 12:21:14.645883 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9633 12:21:14.652537 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9634 12:21:14.655882 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9635 12:21:14.662387 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9636 12:21:14.665503 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9637 12:21:14.668855 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9638 12:21:14.675811 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9639 12:21:14.679113 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9640 12:21:14.685471 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9641 12:21:14.688839 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9642 12:21:14.692342 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9643 12:21:14.698942 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9644 12:21:14.702236 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9645 12:21:14.709374 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9646 12:21:14.712332 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9647 12:21:14.715726 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9648 12:21:14.722093 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9649 12:21:14.725921 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9650 12:21:14.729257 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9651 12:21:14.735608 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9652 12:21:14.739201 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9653 12:21:14.745676 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9654 12:21:14.749048 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9655 12:21:14.755548 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9656 12:21:14.758825 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9657 12:21:14.762457 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9658 12:21:14.769590 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9659 12:21:14.771976 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9660 12:21:14.779143 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9661 12:21:14.782126 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9662 12:21:14.785592 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9663 12:21:14.792214 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9664 12:21:14.795196 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9665 12:21:14.802665 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9666 12:21:14.805281 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9667 12:21:14.808580 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9668 12:21:14.815666 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9669 12:21:14.818610 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9670 12:21:14.825522 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9671 12:21:14.828456 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9672 12:21:14.835610 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9673 12:21:14.838672 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9674 12:21:14.841714 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9675 12:21:14.848660 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9676 12:21:14.851991 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9677 12:21:14.858527 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9678 12:21:14.861797 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9679 12:21:14.865215 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9680 12:21:14.871697 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9681 12:21:14.875330 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9682 12:21:14.881625 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9683 12:21:14.885210 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9684 12:21:14.891579 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9685 12:21:14.894995 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9686 12:21:14.898247 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9687 12:21:14.905159 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9688 12:21:14.908709 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9689 12:21:14.914879 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9690 12:21:14.918459 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9691 12:21:14.925114 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9692 12:21:14.928649 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9693 12:21:14.931840 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9694 12:21:14.935104 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9695 12:21:14.941501 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9696 12:21:14.945090 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9697 12:21:14.948333 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9698 12:21:14.951182 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9699 12:21:14.958236 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9700 12:21:14.961177 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9701 12:21:14.967995 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9702 12:21:14.971372 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9703 12:21:14.974533 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9704 12:21:14.981229 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9705 12:21:14.984591 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9706 12:21:14.988086 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9707 12:21:14.994569 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9708 12:21:14.998152 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9709 12:21:15.001285 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9710 12:21:15.007473 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9711 12:21:15.011627 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9712 12:21:15.014317 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9713 12:21:15.021300 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9714 12:21:15.024329 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9715 12:21:15.031536 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9716 12:21:15.034516 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9717 12:21:15.038279 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9718 12:21:15.044842 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9719 12:21:15.047831 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9720 12:21:15.051045 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9721 12:21:15.057895 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9722 12:21:15.061297 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9723 12:21:15.064555 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9724 12:21:15.071369 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9725 12:21:15.074484 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9726 12:21:15.081100 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9727 12:21:15.084519 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9728 12:21:15.087674 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9729 12:21:15.094195 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9730 12:21:15.097679 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9731 12:21:15.100721 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9732 12:21:15.107456 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9733 12:21:15.111261 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9734 12:21:15.114584 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9735 12:21:15.117643 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9736 12:21:15.124395 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9737 12:21:15.127655 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9738 12:21:15.130959 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9739 12:21:15.134200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9740 12:21:15.140882 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9741 12:21:15.144097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9742 12:21:15.147288 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9743 12:21:15.150729 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9744 12:21:15.157174 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9745 12:21:15.160410 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9746 12:21:15.163807 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9747 12:21:15.170747 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9748 12:21:15.174122 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9749 12:21:15.180619 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9750 12:21:15.183605 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9751 12:21:15.190504 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9752 12:21:15.193642 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9753 12:21:15.197235 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9754 12:21:15.203533 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9755 12:21:15.207336 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9756 12:21:15.213766 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9757 12:21:15.216874 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9758 12:21:15.220038 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9759 12:21:15.226773 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9760 12:21:15.229918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9761 12:21:15.236596 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9762 12:21:15.240174 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9763 12:21:15.243605 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9764 12:21:15.250084 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9765 12:21:15.253245 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9766 12:21:15.260013 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9767 12:21:15.263440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9768 12:21:15.270037 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9769 12:21:15.273219 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9770 12:21:15.276912 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9771 12:21:15.283124 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9772 12:21:15.286371 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9773 12:21:15.293390 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9774 12:21:15.296841 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9775 12:21:15.299786 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9776 12:21:15.306534 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9777 12:21:15.309990 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9778 12:21:15.313537 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9779 12:21:15.319773 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9780 12:21:15.323543 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9781 12:21:15.329885 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9782 12:21:15.333103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9783 12:21:15.340403 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9784 12:21:15.343704 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9785 12:21:15.346707 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9786 12:21:15.353169 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9787 12:21:15.356839 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9788 12:21:15.363446 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9789 12:21:15.366293 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9790 12:21:15.369991 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9791 12:21:15.376209 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9792 12:21:15.380039 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9793 12:21:15.386331 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9794 12:21:15.389626 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9795 12:21:15.392968 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9796 12:21:15.399652 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9797 12:21:15.402929 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9798 12:21:15.409465 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9799 12:21:15.412989 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9800 12:21:15.419480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9801 12:21:15.423010 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9802 12:21:15.426286 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9803 12:21:15.432824 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9804 12:21:15.436360 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9805 12:21:15.442861 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9806 12:21:15.446231 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9807 12:21:15.449571 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9808 12:21:15.456081 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9809 12:21:15.459527 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9810 12:21:15.462963 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9811 12:21:15.469424 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9812 12:21:15.472909 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9813 12:21:15.479647 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9814 12:21:15.482530 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9815 12:21:15.489201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9816 12:21:15.493163 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9817 12:21:15.496272 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9818 12:21:15.502769 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9819 12:21:15.506184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9820 12:21:15.513442 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9821 12:21:15.516125 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9822 12:21:15.522875 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9823 12:21:15.526188 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9824 12:21:15.529170 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9825 12:21:15.535807 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9826 12:21:15.539197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9827 12:21:15.545700 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9828 12:21:15.549299 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9829 12:21:15.555987 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9830 12:21:15.559065 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9831 12:21:15.562325 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9832 12:21:15.569407 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9833 12:21:15.572543 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9834 12:21:15.578880 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9835 12:21:15.582121 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9836 12:21:15.589014 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9837 12:21:15.591951 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9838 12:21:15.599168 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9839 12:21:15.602099 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9840 12:21:15.605777 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9841 12:21:15.612423 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9842 12:21:15.615807 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9843 12:21:15.621824 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9844 12:21:15.625727 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9845 12:21:15.632035 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9846 12:21:15.635313 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9847 12:21:15.641675 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9848 12:21:15.644882 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9849 12:21:15.648291 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9850 12:21:15.655045 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9851 12:21:15.658248 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9852 12:21:15.665105 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9853 12:21:15.668360 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9854 12:21:15.675164 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9855 12:21:15.678652 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9856 12:21:15.681520 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9857 12:21:15.688066 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9858 12:21:15.691612 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9859 12:21:15.697616 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9860 12:21:15.700967 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9861 12:21:15.707764 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9862 12:21:15.711375 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9863 12:21:15.714607 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9864 12:21:15.721318 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9865 12:21:15.724555 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9866 12:21:15.731532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9867 12:21:15.734924 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9868 12:21:15.741438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9869 12:21:15.744712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9870 12:21:15.748038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9871 12:21:15.754737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9872 12:21:15.757653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9873 12:21:15.764452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9874 12:21:15.767689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9875 12:21:15.774374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9876 12:21:15.777783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9877 12:21:15.784352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9878 12:21:15.787765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9879 12:21:15.794276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9880 12:21:15.797616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9881 12:21:15.803832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9882 12:21:15.807310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9883 12:21:15.814107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9884 12:21:15.817467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9885 12:21:15.824161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9886 12:21:15.827420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9887 12:21:15.833796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9888 12:21:15.837458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9889 12:21:15.844188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9890 12:21:15.847187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9891 12:21:15.854273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9892 12:21:15.857093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9893 12:21:15.863609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9894 12:21:15.866949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9895 12:21:15.873670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9896 12:21:15.876877 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9897 12:21:15.883526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9898 12:21:15.887091 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9899 12:21:15.890372 INFO: [APUAPC] vio 0
9900 12:21:15.893466 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9901 12:21:15.900478 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9902 12:21:15.903756 INFO: [APUAPC] D0_APC_0: 0x400510
9903 12:21:15.904317 INFO: [APUAPC] D0_APC_1: 0x0
9904 12:21:15.907007 INFO: [APUAPC] D0_APC_2: 0x1540
9905 12:21:15.910539 INFO: [APUAPC] D0_APC_3: 0x0
9906 12:21:15.913820 INFO: [APUAPC] D1_APC_0: 0xffffffff
9907 12:21:15.916637 INFO: [APUAPC] D1_APC_1: 0xffffffff
9908 12:21:15.920614 INFO: [APUAPC] D1_APC_2: 0x3fffff
9909 12:21:15.923442 INFO: [APUAPC] D1_APC_3: 0x0
9910 12:21:15.926887 INFO: [APUAPC] D2_APC_0: 0xffffffff
9911 12:21:15.930026 INFO: [APUAPC] D2_APC_1: 0xffffffff
9912 12:21:15.933447 INFO: [APUAPC] D2_APC_2: 0x3fffff
9913 12:21:15.936899 INFO: [APUAPC] D2_APC_3: 0x0
9914 12:21:15.940258 INFO: [APUAPC] D3_APC_0: 0xffffffff
9915 12:21:15.943822 INFO: [APUAPC] D3_APC_1: 0xffffffff
9916 12:21:15.946516 INFO: [APUAPC] D3_APC_2: 0x3fffff
9917 12:21:15.950206 INFO: [APUAPC] D3_APC_3: 0x0
9918 12:21:15.953674 INFO: [APUAPC] D4_APC_0: 0xffffffff
9919 12:21:15.957255 INFO: [APUAPC] D4_APC_1: 0xffffffff
9920 12:21:15.960186 INFO: [APUAPC] D4_APC_2: 0x3fffff
9921 12:21:15.963577 INFO: [APUAPC] D4_APC_3: 0x0
9922 12:21:15.966862 INFO: [APUAPC] D5_APC_0: 0xffffffff
9923 12:21:15.970001 INFO: [APUAPC] D5_APC_1: 0xffffffff
9924 12:21:15.973584 INFO: [APUAPC] D5_APC_2: 0x3fffff
9925 12:21:15.976897 INFO: [APUAPC] D5_APC_3: 0x0
9926 12:21:15.979853 INFO: [APUAPC] D6_APC_0: 0xffffffff
9927 12:21:15.983294 INFO: [APUAPC] D6_APC_1: 0xffffffff
9928 12:21:15.986612 INFO: [APUAPC] D6_APC_2: 0x3fffff
9929 12:21:15.989994 INFO: [APUAPC] D6_APC_3: 0x0
9930 12:21:15.993050 INFO: [APUAPC] D7_APC_0: 0xffffffff
9931 12:21:15.996458 INFO: [APUAPC] D7_APC_1: 0xffffffff
9932 12:21:15.999913 INFO: [APUAPC] D7_APC_2: 0x3fffff
9933 12:21:16.003542 INFO: [APUAPC] D7_APC_3: 0x0
9934 12:21:16.006924 INFO: [APUAPC] D8_APC_0: 0xffffffff
9935 12:21:16.010076 INFO: [APUAPC] D8_APC_1: 0xffffffff
9936 12:21:16.013002 INFO: [APUAPC] D8_APC_2: 0x3fffff
9937 12:21:16.016465 INFO: [APUAPC] D8_APC_3: 0x0
9938 12:21:16.020052 INFO: [APUAPC] D9_APC_0: 0xffffffff
9939 12:21:16.023066 INFO: [APUAPC] D9_APC_1: 0xffffffff
9940 12:21:16.026482 INFO: [APUAPC] D9_APC_2: 0x3fffff
9941 12:21:16.026960 INFO: [APUAPC] D9_APC_3: 0x0
9942 12:21:16.033128 INFO: [APUAPC] D10_APC_0: 0xffffffff
9943 12:21:16.036412 INFO: [APUAPC] D10_APC_1: 0xffffffff
9944 12:21:16.039636 INFO: [APUAPC] D10_APC_2: 0x3fffff
9945 12:21:16.043444 INFO: [APUAPC] D10_APC_3: 0x0
9946 12:21:16.046662 INFO: [APUAPC] D11_APC_0: 0xffffffff
9947 12:21:16.049703 INFO: [APUAPC] D11_APC_1: 0xffffffff
9948 12:21:16.053213 INFO: [APUAPC] D11_APC_2: 0x3fffff
9949 12:21:16.056967 INFO: [APUAPC] D11_APC_3: 0x0
9950 12:21:16.059466 INFO: [APUAPC] D12_APC_0: 0xffffffff
9951 12:21:16.063092 INFO: [APUAPC] D12_APC_1: 0xffffffff
9952 12:21:16.066369 INFO: [APUAPC] D12_APC_2: 0x3fffff
9953 12:21:16.069414 INFO: [APUAPC] D12_APC_3: 0x0
9954 12:21:16.072849 INFO: [APUAPC] D13_APC_0: 0xffffffff
9955 12:21:16.076024 INFO: [APUAPC] D13_APC_1: 0xffffffff
9956 12:21:16.079630 INFO: [APUAPC] D13_APC_2: 0x3fffff
9957 12:21:16.082742 INFO: [APUAPC] D13_APC_3: 0x0
9958 12:21:16.086306 INFO: [APUAPC] D14_APC_0: 0xffffffff
9959 12:21:16.089421 INFO: [APUAPC] D14_APC_1: 0xffffffff
9960 12:21:16.092703 INFO: [APUAPC] D14_APC_2: 0x3fffff
9961 12:21:16.095786 INFO: [APUAPC] D14_APC_3: 0x0
9962 12:21:16.099145 INFO: [APUAPC] D15_APC_0: 0xffffffff
9963 12:21:16.102576 INFO: [APUAPC] D15_APC_1: 0xffffffff
9964 12:21:16.105702 INFO: [APUAPC] D15_APC_2: 0x3fffff
9965 12:21:16.109398 INFO: [APUAPC] D15_APC_3: 0x0
9966 12:21:16.112708 INFO: [APUAPC] APC_CON: 0x4
9967 12:21:16.113323 INFO: [NOCDAPC] D0_APC_0: 0x0
9968 12:21:16.115851 INFO: [NOCDAPC] D0_APC_1: 0x0
9969 12:21:16.119500 INFO: [NOCDAPC] D1_APC_0: 0x0
9970 12:21:16.122523 INFO: [NOCDAPC] D1_APC_1: 0xfff
9971 12:21:16.126098 INFO: [NOCDAPC] D2_APC_0: 0x0
9972 12:21:16.129042 INFO: [NOCDAPC] D2_APC_1: 0xfff
9973 12:21:16.132315 INFO: [NOCDAPC] D3_APC_0: 0x0
9974 12:21:16.136063 INFO: [NOCDAPC] D3_APC_1: 0xfff
9975 12:21:16.139031 INFO: [NOCDAPC] D4_APC_0: 0x0
9976 12:21:16.142176 INFO: [NOCDAPC] D4_APC_1: 0xfff
9977 12:21:16.142673 INFO: [NOCDAPC] D5_APC_0: 0x0
9978 12:21:16.145442 INFO: [NOCDAPC] D5_APC_1: 0xfff
9979 12:21:16.148805 INFO: [NOCDAPC] D6_APC_0: 0x0
9980 12:21:16.152691 INFO: [NOCDAPC] D6_APC_1: 0xfff
9981 12:21:16.155942 INFO: [NOCDAPC] D7_APC_0: 0x0
9982 12:21:16.159097 INFO: [NOCDAPC] D7_APC_1: 0xfff
9983 12:21:16.162225 INFO: [NOCDAPC] D8_APC_0: 0x0
9984 12:21:16.165872 INFO: [NOCDAPC] D8_APC_1: 0xfff
9985 12:21:16.169157 INFO: [NOCDAPC] D9_APC_0: 0x0
9986 12:21:16.172170 INFO: [NOCDAPC] D9_APC_1: 0xfff
9987 12:21:16.175421 INFO: [NOCDAPC] D10_APC_0: 0x0
9988 12:21:16.178642 INFO: [NOCDAPC] D10_APC_1: 0xfff
9989 12:21:16.179113 INFO: [NOCDAPC] D11_APC_0: 0x0
9990 12:21:16.182221 INFO: [NOCDAPC] D11_APC_1: 0xfff
9991 12:21:16.185325 INFO: [NOCDAPC] D12_APC_0: 0x0
9992 12:21:16.188707 INFO: [NOCDAPC] D12_APC_1: 0xfff
9993 12:21:16.192752 INFO: [NOCDAPC] D13_APC_0: 0x0
9994 12:21:16.195972 INFO: [NOCDAPC] D13_APC_1: 0xfff
9995 12:21:16.198853 INFO: [NOCDAPC] D14_APC_0: 0x0
9996 12:21:16.201997 INFO: [NOCDAPC] D14_APC_1: 0xfff
9997 12:21:16.205429 INFO: [NOCDAPC] D15_APC_0: 0x0
9998 12:21:16.209151 INFO: [NOCDAPC] D15_APC_1: 0xfff
9999 12:21:16.212018 INFO: [NOCDAPC] APC_CON: 0x4
10000 12:21:16.215417 INFO: [APUAPC] set_apusys_apc done
10001 12:21:16.218505 INFO: [DEVAPC] devapc_init done
10002 12:21:16.222119 INFO: GICv3 without legacy support detected.
10003 12:21:16.225173 INFO: ARM GICv3 driver initialized in EL3
10004 12:21:16.228485 INFO: Maximum SPI INTID supported: 639
10005 12:21:16.231978 INFO: BL31: Initializing runtime services
10006 12:21:16.238683 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10007 12:21:16.242097 INFO: SPM: enable CPC mode
10008 12:21:16.248489 INFO: mcdi ready for mcusys-off-idle and system suspend
10009 12:21:16.251818 INFO: BL31: Preparing for EL3 exit to normal world
10010 12:21:16.255004 INFO: Entry point address = 0x80000000
10011 12:21:16.258613 INFO: SPSR = 0x8
10012 12:21:16.263255
10013 12:21:16.263900
10014 12:21:16.264514
10015 12:21:16.266834 Starting depthcharge on Spherion...
10016 12:21:16.267334
10017 12:21:16.267702 Wipe memory regions:
10018 12:21:16.268042
10019 12:21:16.270472 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10020 12:21:16.270999 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10021 12:21:16.271436 Setting prompt string to ['asurada:']
10022 12:21:16.271863 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10023 12:21:16.272571 [0x00000040000000, 0x00000054600000)
10024 12:21:16.392297
10025 12:21:16.392857 [0x00000054660000, 0x00000080000000)
10026 12:21:16.652785
10027 12:21:16.653403 [0x000000821a7280, 0x000000ffe64000)
10028 12:21:17.397997
10029 12:21:17.398685 [0x00000100000000, 0x00000240000000)
10030 12:21:19.288121
10031 12:21:19.291352 Initializing XHCI USB controller at 0x11200000.
10032 12:21:20.329629
10033 12:21:20.332410 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10034 12:21:20.332879
10035 12:21:20.333272
10036 12:21:20.333615
10037 12:21:20.334394 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10039 12:21:20.435751 asurada: tftpboot 192.168.201.1 11893133/tftp-deploy-znijld6f/kernel/image.itb 11893133/tftp-deploy-znijld6f/kernel/cmdline
10040 12:21:20.436455 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10041 12:21:20.436920 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10042 12:21:20.441501 tftpboot 192.168.201.1 11893133/tftp-deploy-znijld6f/kernel/image.ittp-deploy-znijld6f/kernel/cmdline
10043 12:21:20.441978
10044 12:21:20.442347 Waiting for link
10045 12:21:20.601769
10046 12:21:20.602326 R8152: Initializing
10047 12:21:20.602703
10048 12:21:20.605216 Version 9 (ocp_data = 6010)
10049 12:21:20.605686
10050 12:21:20.608166 R8152: Done initializing
10051 12:21:20.608720
10052 12:21:20.609141 Adding net device
10053 12:21:22.476756
10054 12:21:22.476962 done.
10055 12:21:22.477083
10056 12:21:22.477187 MAC: 00:e0:4c:72:2d:d6
10057 12:21:22.477286
10058 12:21:22.480063 Sending DHCP discover... done.
10059 12:21:22.480192
10060 12:21:22.483487 Waiting for reply... done.
10061 12:21:22.483612
10062 12:21:22.486448 Sending DHCP request... done.
10063 12:21:22.486564
10064 12:21:22.486669 Waiting for reply... done.
10065 12:21:22.486769
10066 12:21:22.490029 My ip is 192.168.201.21
10067 12:21:22.490186
10068 12:21:22.493337 The DHCP server ip is 192.168.201.1
10069 12:21:22.493456
10070 12:21:22.496692 TFTP server IP predefined by user: 192.168.201.1
10071 12:21:22.496818
10072 12:21:22.504064 Bootfile predefined by user: 11893133/tftp-deploy-znijld6f/kernel/image.itb
10073 12:21:22.504215
10074 12:21:22.506897 Sending tftp read request... done.
10075 12:21:22.507025
10076 12:21:22.510285 Waiting for the transfer...
10077 12:21:22.510420
10078 12:21:22.851711 00000000 ################################################################
10079 12:21:22.852338
10080 12:21:23.141053 00080000 ################################################################
10081 12:21:23.141189
10082 12:21:23.409665 00100000 ################################################################
10083 12:21:23.409816
10084 12:21:23.683878 00180000 ################################################################
10085 12:21:23.684028
10086 12:21:23.943596 00200000 ################################################################
10087 12:21:23.943747
10088 12:21:24.229922 00280000 ################################################################
10089 12:21:24.230076
10090 12:21:24.491453 00300000 ################################################################
10091 12:21:24.491607
10093 12:25:41.271218 end: 2.2.4 bootloader-commands (duration 00:04:25) [common]
10095 12:25:41.271430 depthcharge-retry failed: 1 of 1 attempts. 'bootloader-commands timed out after 265 seconds'
10097 12:25:41.271598 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10100 12:25:41.271876 end: 2 depthcharge-action (duration 00:05:00) [common]
10102 12:25:41.272104 Cleaning after the job
10103 12:25:41.272215 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/ramdisk
10104 12:25:41.276548 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/kernel
10105 12:25:41.288300 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/dtb
10106 12:25:41.288535 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893133/tftp-deploy-znijld6f/modules
10107 12:25:41.294222 start: 4.1 power-off (timeout 00:00:30) [common]
10108 12:25:41.294404 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
10109 12:25:41.370755 >> Command sent successfully.
10110 12:25:41.373497 Returned 0 in 0 seconds
10111 12:25:41.473920 end: 4.1 power-off (duration 00:00:00) [common]
10113 12:25:41.474283 start: 4.2 read-feedback (timeout 00:10:00) [common]
10114 12:25:41.474556 Listened to connection for namespace 'common' for up to 1s
10115 12:25:42.475492 Finalising connection for namespace 'common'
10116 12:25:42.475674 Disconnecting from shell: Finalise
10117 12:25:42.475751 00380000 #######################
10118 12:25:42.576089 end: 4.2 read-feedback (duration 00:00:01) [common]
10119 12:25:42.576251 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893133
10120 12:25:42.629896 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893133
10121 12:25:42.630077 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.