Boot log: mt8192-asurada-spherion-r0

    1 12:20:52.829457  lava-dispatcher, installed at version: 2023.08
    2 12:20:52.829652  start: 0 validate
    3 12:20:52.829786  Start time: 2023-10-27 12:20:52.829778+00:00 (UTC)
    4 12:20:52.829908  Using caching service: 'http://localhost/cache/?uri=%s'
    5 12:20:52.830044  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
    6 12:20:53.099338  Using caching service: 'http://localhost/cache/?uri=%s'
    7 12:20:53.099571  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 12:20:53.366742  Using caching service: 'http://localhost/cache/?uri=%s'
    9 12:20:53.367577  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 12:20:53.637782  Using caching service: 'http://localhost/cache/?uri=%s'
   11 12:20:53.637950  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.58-cip7-132-gb38ea1474c159%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 12:20:53.906084  validate duration: 1.08
   14 12:20:53.906368  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 12:20:53.906466  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 12:20:53.906559  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 12:20:53.906690  Not decompressing ramdisk as can be used compressed.
   18 12:20:53.906776  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
   19 12:20:53.906843  saving as /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/ramdisk/rootfs.cpio.gz
   20 12:20:53.906907  total size: 26246609 (25 MB)
   21 12:20:53.911161  progress   0 % (0 MB)
   22 12:20:53.919196  progress   5 % (1 MB)
   23 12:20:53.926467  progress  10 % (2 MB)
   24 12:20:53.933790  progress  15 % (3 MB)
   25 12:20:53.940868  progress  20 % (5 MB)
   26 12:20:53.947872  progress  25 % (6 MB)
   27 12:20:53.954954  progress  30 % (7 MB)
   28 12:20:53.962100  progress  35 % (8 MB)
   29 12:20:53.969158  progress  40 % (10 MB)
   30 12:20:53.976128  progress  45 % (11 MB)
   31 12:20:53.983135  progress  50 % (12 MB)
   32 12:20:53.990398  progress  55 % (13 MB)
   33 12:20:53.997551  progress  60 % (15 MB)
   34 12:20:54.004649  progress  65 % (16 MB)
   35 12:20:54.011649  progress  70 % (17 MB)
   36 12:20:54.018537  progress  75 % (18 MB)
   37 12:20:54.025561  progress  80 % (20 MB)
   38 12:20:54.032403  progress  85 % (21 MB)
   39 12:20:54.039190  progress  90 % (22 MB)
   40 12:20:54.046026  progress  95 % (23 MB)
   41 12:20:54.052758  progress 100 % (25 MB)
   42 12:20:54.053009  25 MB downloaded in 0.15 s (171.32 MB/s)
   43 12:20:54.053165  end: 1.1.1 http-download (duration 00:00:00) [common]
   45 12:20:54.053411  end: 1.1 download-retry (duration 00:00:00) [common]
   46 12:20:54.053498  start: 1.2 download-retry (timeout 00:10:00) [common]
   47 12:20:54.053591  start: 1.2.1 http-download (timeout 00:10:00) [common]
   48 12:20:54.053722  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 12:20:54.053794  saving as /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/kernel/Image
   50 12:20:54.053855  total size: 49236480 (46 MB)
   51 12:20:54.053916  No compression specified
   52 12:20:54.055146  progress   0 % (0 MB)
   53 12:20:54.068503  progress   5 % (2 MB)
   54 12:20:54.081396  progress  10 % (4 MB)
   55 12:20:54.094479  progress  15 % (7 MB)
   56 12:20:54.107435  progress  20 % (9 MB)
   57 12:20:54.120225  progress  25 % (11 MB)
   58 12:20:54.133451  progress  30 % (14 MB)
   59 12:20:54.146127  progress  35 % (16 MB)
   60 12:20:54.159597  progress  40 % (18 MB)
   61 12:20:54.172353  progress  45 % (21 MB)
   62 12:20:54.185620  progress  50 % (23 MB)
   63 12:20:54.198653  progress  55 % (25 MB)
   64 12:20:54.211652  progress  60 % (28 MB)
   65 12:20:54.224738  progress  65 % (30 MB)
   66 12:20:54.237687  progress  70 % (32 MB)
   67 12:20:54.250536  progress  75 % (35 MB)
   68 12:20:54.263951  progress  80 % (37 MB)
   69 12:20:54.276848  progress  85 % (39 MB)
   70 12:20:54.290531  progress  90 % (42 MB)
   71 12:20:54.303422  progress  95 % (44 MB)
   72 12:20:54.316546  progress 100 % (46 MB)
   73 12:20:54.316785  46 MB downloaded in 0.26 s (178.59 MB/s)
   74 12:20:54.316943  end: 1.2.1 http-download (duration 00:00:00) [common]
   76 12:20:54.317174  end: 1.2 download-retry (duration 00:00:00) [common]
   77 12:20:54.317261  start: 1.3 download-retry (timeout 00:10:00) [common]
   78 12:20:54.317354  start: 1.3.1 http-download (timeout 00:10:00) [common]
   79 12:20:54.317490  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 12:20:54.317559  saving as /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/dtb/mt8192-asurada-spherion-r0.dtb
   81 12:20:54.317620  total size: 47278 (0 MB)
   82 12:20:54.317682  No compression specified
   83 12:20:54.318868  progress  69 % (0 MB)
   84 12:20:54.319147  progress 100 % (0 MB)
   85 12:20:54.319301  0 MB downloaded in 0.00 s (26.86 MB/s)
   86 12:20:54.319469  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 12:20:54.319691  end: 1.3 download-retry (duration 00:00:00) [common]
   89 12:20:54.319775  start: 1.4 download-retry (timeout 00:10:00) [common]
   90 12:20:54.319858  start: 1.4.1 http-download (timeout 00:10:00) [common]
   91 12:20:54.319973  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.58-cip7-132-gb38ea1474c159/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 12:20:54.320041  saving as /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/modules/modules.tar
   93 12:20:54.320101  total size: 8625084 (8 MB)
   94 12:20:54.320162  Using unxz to decompress xz
   95 12:20:54.324603  progress   0 % (0 MB)
   96 12:20:54.346517  progress   5 % (0 MB)
   97 12:20:54.369105  progress  10 % (0 MB)
   98 12:20:54.396087  progress  15 % (1 MB)
   99 12:20:54.421906  progress  20 % (1 MB)
  100 12:20:54.448222  progress  25 % (2 MB)
  101 12:20:54.474241  progress  30 % (2 MB)
  102 12:20:54.501473  progress  35 % (2 MB)
  103 12:20:54.526756  progress  40 % (3 MB)
  104 12:20:54.551021  progress  45 % (3 MB)
  105 12:20:54.577237  progress  50 % (4 MB)
  106 12:20:54.602326  progress  55 % (4 MB)
  107 12:20:54.626968  progress  60 % (4 MB)
  108 12:20:54.651400  progress  65 % (5 MB)
  109 12:20:54.677499  progress  70 % (5 MB)
  110 12:20:54.703423  progress  75 % (6 MB)
  111 12:20:54.730888  progress  80 % (6 MB)
  112 12:20:54.761012  progress  85 % (7 MB)
  113 12:20:54.787926  progress  90 % (7 MB)
  114 12:20:54.813837  progress  95 % (7 MB)
  115 12:20:54.836990  progress 100 % (8 MB)
  116 12:20:54.841821  8 MB downloaded in 0.52 s (15.77 MB/s)
  117 12:20:54.842071  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 12:20:54.842333  end: 1.4 download-retry (duration 00:00:01) [common]
  120 12:20:54.842426  start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
  121 12:20:54.842525  start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
  122 12:20:54.842608  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 12:20:54.842693  start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
  124 12:20:54.842912  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh
  125 12:20:54.843048  makedir: /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin
  126 12:20:54.843154  makedir: /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/tests
  127 12:20:54.843255  makedir: /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/results
  128 12:20:54.843369  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-add-keys
  129 12:20:54.843565  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-add-sources
  130 12:20:54.843697  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-background-process-start
  131 12:20:54.843830  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-background-process-stop
  132 12:20:54.843956  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-common-functions
  133 12:20:54.844082  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-echo-ipv4
  134 12:20:54.844209  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-install-packages
  135 12:20:54.844334  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-installed-packages
  136 12:20:54.844460  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-os-build
  137 12:20:54.844586  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-probe-channel
  138 12:20:54.844711  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-probe-ip
  139 12:20:54.844840  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-target-ip
  140 12:20:54.844966  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-target-mac
  141 12:20:54.845091  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-target-storage
  142 12:20:54.845222  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-test-case
  143 12:20:54.845347  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-test-event
  144 12:20:54.845472  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-test-feedback
  145 12:20:54.845598  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-test-raise
  146 12:20:54.845724  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-test-reference
  147 12:20:54.845848  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-test-runner
  148 12:20:54.845974  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-test-set
  149 12:20:54.846102  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-test-shell
  150 12:20:54.846230  Updating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-install-packages (oe)
  151 12:20:54.846386  Updating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/bin/lava-installed-packages (oe)
  152 12:20:54.846509  Creating /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/environment
  153 12:20:54.846605  LAVA metadata
  154 12:20:54.846679  - LAVA_JOB_ID=11893139
  155 12:20:54.846743  - LAVA_DISPATCHER_IP=192.168.201.1
  156 12:20:54.846843  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
  157 12:20:54.846909  skipped lava-vland-overlay
  158 12:20:54.846982  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 12:20:54.847064  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
  160 12:20:54.847126  skipped lava-multinode-overlay
  161 12:20:54.847205  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 12:20:54.847289  start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
  163 12:20:54.847362  Loading test definitions
  164 12:20:54.847499  start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
  165 12:20:54.847582  Using /lava-11893139 at stage 0
  166 12:20:54.847893  uuid=11893139_1.5.2.3.1 testdef=None
  167 12:20:54.847981  end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
  168 12:20:54.848070  start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
  169 12:20:54.848590  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  171 12:20:54.848805  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
  172 12:20:54.849420  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  174 12:20:54.849655  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
  175 12:20:54.850245  runner path: /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/0/tests/0_v4l2-compliance-uvc test_uuid 11893139_1.5.2.3.1
  176 12:20:54.850406  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  178 12:20:54.850613  Creating lava-test-runner.conf files
  179 12:20:54.850694  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11893139/lava-overlay-6gv_z1uh/lava-11893139/0 for stage 0
  180 12:20:54.850789  - 0_v4l2-compliance-uvc
  181 12:20:54.850892  end: 1.5.2.3 test-definition (duration 00:00:00) [common]
  182 12:20:54.850977  start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
  183 12:20:54.857996  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  184 12:20:54.858120  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
  185 12:20:54.858220  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  186 12:20:54.858304  end: 1.5.2 lava-overlay (duration 00:00:00) [common]
  187 12:20:54.858390  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
  188 12:20:55.595935  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  189 12:20:55.596318  start: 1.5.4 extract-modules (timeout 00:09:58) [common]
  190 12:20:55.596439  extracting modules file /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11893139/extract-overlay-ramdisk-wh1upa_s/ramdisk
  191 12:20:55.826989  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  192 12:20:55.827144  start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
  193 12:20:55.827241  [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893139/compress-overlay-t5qg3aiv/overlay-1.5.2.4.tar.gz to ramdisk
  194 12:20:55.827313  [common] Applying overlay /var/lib/lava/dispatcher/tmp/11893139/compress-overlay-t5qg3aiv/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11893139/extract-overlay-ramdisk-wh1upa_s/ramdisk
  195 12:20:55.834193  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  196 12:20:55.834308  start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
  197 12:20:55.834399  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  198 12:20:55.834487  start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
  199 12:20:55.834567  Building ramdisk /var/lib/lava/dispatcher/tmp/11893139/extract-overlay-ramdisk-wh1upa_s/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11893139/extract-overlay-ramdisk-wh1upa_s/ramdisk
  200 12:20:56.460977  >> 228398 blocks

  201 12:21:00.431860  rename /var/lib/lava/dispatcher/tmp/11893139/extract-overlay-ramdisk-wh1upa_s/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/ramdisk/ramdisk.cpio.gz
  202 12:21:00.432290  end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
  203 12:21:00.432421  start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
  204 12:21:00.432523  start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
  205 12:21:00.432658  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/kernel/Image'
  206 12:21:12.360779  Returned 0 in 11 seconds
  207 12:21:12.461902  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/kernel/image.itb
  208 12:21:13.089324  output: FIT description: Kernel Image image with one or more FDT blobs
  209 12:21:13.089677  output: Created:         Fri Oct 27 13:21:12 2023
  210 12:21:13.089753  output:  Image 0 (kernel-1)
  211 12:21:13.089819  output:   Description:  
  212 12:21:13.089884  output:   Created:      Fri Oct 27 13:21:12 2023
  213 12:21:13.089945  output:   Type:         Kernel Image
  214 12:21:13.090007  output:   Compression:  lzma compressed
  215 12:21:13.090066  output:   Data Size:    11047994 Bytes = 10789.06 KiB = 10.54 MiB
  216 12:21:13.090127  output:   Architecture: AArch64
  217 12:21:13.090185  output:   OS:           Linux
  218 12:21:13.090246  output:   Load Address: 0x00000000
  219 12:21:13.090303  output:   Entry Point:  0x00000000
  220 12:21:13.090358  output:   Hash algo:    crc32
  221 12:21:13.090417  output:   Hash value:   d33b93ae
  222 12:21:13.090472  output:  Image 1 (fdt-1)
  223 12:21:13.090527  output:   Description:  mt8192-asurada-spherion-r0
  224 12:21:13.090580  output:   Created:      Fri Oct 27 13:21:12 2023
  225 12:21:13.090632  output:   Type:         Flat Device Tree
  226 12:21:13.090685  output:   Compression:  uncompressed
  227 12:21:13.090737  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  228 12:21:13.090791  output:   Architecture: AArch64
  229 12:21:13.090844  output:   Hash algo:    crc32
  230 12:21:13.090897  output:   Hash value:   cc4352de
  231 12:21:13.090950  output:  Image 2 (ramdisk-1)
  232 12:21:13.091003  output:   Description:  unavailable
  233 12:21:13.091056  output:   Created:      Fri Oct 27 13:21:12 2023
  234 12:21:13.091109  output:   Type:         RAMDisk Image
  235 12:21:13.091162  output:   Compression:  Unknown Compression
  236 12:21:13.091215  output:   Data Size:    39351308 Bytes = 38429.01 KiB = 37.53 MiB
  237 12:21:13.091268  output:   Architecture: AArch64
  238 12:21:13.091320  output:   OS:           Linux
  239 12:21:13.091373  output:   Load Address: unavailable
  240 12:21:13.091474  output:   Entry Point:  unavailable
  241 12:21:13.091529  output:   Hash algo:    crc32
  242 12:21:13.091581  output:   Hash value:   bd1d3253
  243 12:21:13.091634  output:  Default Configuration: 'conf-1'
  244 12:21:13.091687  output:  Configuration 0 (conf-1)
  245 12:21:13.091740  output:   Description:  mt8192-asurada-spherion-r0
  246 12:21:13.091792  output:   Kernel:       kernel-1
  247 12:21:13.091845  output:   Init Ramdisk: ramdisk-1
  248 12:21:13.091897  output:   FDT:          fdt-1
  249 12:21:13.091950  output:   Loadables:    kernel-1
  250 12:21:13.092003  output: 
  251 12:21:13.092203  end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
  252 12:21:13.092301  end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
  253 12:21:13.092405  end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
  254 12:21:13.092503  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
  255 12:21:13.092583  No LXC device requested
  256 12:21:13.092663  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  257 12:21:13.092748  start: 1.7 deploy-device-env (timeout 00:09:41) [common]
  258 12:21:13.092826  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  259 12:21:13.092894  Checking files for TFTP limit of 4294967296 bytes.
  260 12:21:13.093395  end: 1 tftp-deploy (duration 00:00:19) [common]
  261 12:21:13.093501  start: 2 depthcharge-action (timeout 00:05:00) [common]
  262 12:21:13.093589  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  263 12:21:13.093710  substitutions:
  264 12:21:13.093776  - {DTB}: 11893139/tftp-deploy-g3sfu_86/dtb/mt8192-asurada-spherion-r0.dtb
  265 12:21:13.093839  - {INITRD}: 11893139/tftp-deploy-g3sfu_86/ramdisk/ramdisk.cpio.gz
  266 12:21:13.093898  - {KERNEL}: 11893139/tftp-deploy-g3sfu_86/kernel/Image
  267 12:21:13.093955  - {LAVA_MAC}: None
  268 12:21:13.094011  - {PRESEED_CONFIG}: None
  269 12:21:13.094065  - {PRESEED_LOCAL}: None
  270 12:21:13.094120  - {RAMDISK}: 11893139/tftp-deploy-g3sfu_86/ramdisk/ramdisk.cpio.gz
  271 12:21:13.094175  - {ROOT_PART}: None
  272 12:21:13.094229  - {ROOT}: None
  273 12:21:13.094283  - {SERVER_IP}: 192.168.201.1
  274 12:21:13.094336  - {TEE}: None
  275 12:21:13.094389  Parsed boot commands:
  276 12:21:13.094443  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  277 12:21:13.094613  Parsed boot commands: tftpboot 192.168.201.1 11893139/tftp-deploy-g3sfu_86/kernel/image.itb 11893139/tftp-deploy-g3sfu_86/kernel/cmdline 
  278 12:21:13.094700  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  279 12:21:13.094784  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  280 12:21:13.094877  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  281 12:21:13.094965  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  282 12:21:13.095035  Not connected, no need to disconnect.
  283 12:21:13.095108  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  284 12:21:13.095188  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  285 12:21:13.095254  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
  286 12:21:13.099226  Setting prompt string to ['lava-test: # ']
  287 12:21:13.099631  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  288 12:21:13.099744  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  289 12:21:13.099843  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  290 12:21:13.099933  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  291 12:21:13.100131  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
  292 12:21:18.246323  >> Command sent successfully.

  293 12:21:18.256973  Returned 0 in 5 seconds
  294 12:21:18.358137  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  296 12:21:18.359572  end: 2.2.2 reset-device (duration 00:00:05) [common]
  297 12:21:18.360116  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  298 12:21:18.360712  Setting prompt string to 'Starting depthcharge on Spherion...'
  299 12:21:18.361070  Changing prompt to 'Starting depthcharge on Spherion...'
  300 12:21:18.361438  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  301 12:21:18.362624  [Enter `^Ec?' for help]

  302 12:21:18.521232  

  303 12:21:18.521783  

  304 12:21:18.522143  F0: 102B 0000

  305 12:21:18.522471  

  306 12:21:18.522789  F3: 1001 0000 [0200]

  307 12:21:18.524736  

  308 12:21:18.525293  F3: 1001 0000

  309 12:21:18.525642  

  310 12:21:18.525959  F7: 102D 0000

  311 12:21:18.526262  

  312 12:21:18.527830  F1: 0000 0000

  313 12:21:18.528264  

  314 12:21:18.528605  V0: 0000 0000 [0001]

  315 12:21:18.528937  

  316 12:21:18.530800  00: 0007 8000

  317 12:21:18.531243  

  318 12:21:18.531644  01: 0000 0000

  319 12:21:18.531970  

  320 12:21:18.534364  BP: 0C00 0209 [0000]

  321 12:21:18.534904  

  322 12:21:18.535246  G0: 1182 0000

  323 12:21:18.535650  

  324 12:21:18.538149  EC: 0000 0021 [4000]

  325 12:21:18.538587  

  326 12:21:18.538978  S7: 0000 0000 [0000]

  327 12:21:18.539487  

  328 12:21:18.541963  CC: 0000 0000 [0001]

  329 12:21:18.542537  

  330 12:21:18.542989  T0: 0000 0040 [010F]

  331 12:21:18.543535  

  332 12:21:18.543868  Jump to BL

  333 12:21:18.545077  

  334 12:21:18.568280  

  335 12:21:18.568780  

  336 12:21:18.569183  

  337 12:21:18.575589  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  338 12:21:18.579433  ARM64: Exception handlers installed.

  339 12:21:18.582789  ARM64: Testing exception

  340 12:21:18.585886  ARM64: Done test exception

  341 12:21:18.592571  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  342 12:21:18.603189  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  343 12:21:18.609952  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  344 12:21:18.619670  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  345 12:21:18.626836  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  346 12:21:18.633663  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  347 12:21:18.645130  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  348 12:21:18.651274  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  349 12:21:18.671101  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  350 12:21:18.674615  WDT: Last reset was cold boot

  351 12:21:18.677653  SPI1(PAD0) initialized at 2873684 Hz

  352 12:21:18.680785  SPI5(PAD0) initialized at 992727 Hz

  353 12:21:18.684341  VBOOT: Loading verstage.

  354 12:21:18.690693  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  355 12:21:18.694440  FMAP: Found "FLASH" version 1.1 at 0x20000.

  356 12:21:18.697427  FMAP: base = 0x0 size = 0x800000 #areas = 25

  357 12:21:18.700953  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  358 12:21:18.708279  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  359 12:21:18.715285  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  360 12:21:18.725639  read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps

  361 12:21:18.726150  

  362 12:21:18.726483  

  363 12:21:18.735744  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  364 12:21:18.739553  ARM64: Exception handlers installed.

  365 12:21:18.742627  ARM64: Testing exception

  366 12:21:18.743053  ARM64: Done test exception

  367 12:21:18.749861  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  368 12:21:18.753148  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  369 12:21:18.767269  Probing TPM: . done!

  370 12:21:18.767837  TPM ready after 0 ms

  371 12:21:18.773750  Connected to device vid:did:rid of 1ae0:0028:00

  372 12:21:18.780738  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  373 12:21:18.822361  Initialized TPM device CR50 revision 0

  374 12:21:18.833979  tlcl_send_startup: Startup return code is 0

  375 12:21:18.834541  TPM: setup succeeded

  376 12:21:18.845611  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  377 12:21:18.854140  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  378 12:21:18.865506  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  379 12:21:18.874707  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  380 12:21:18.878147  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  381 12:21:18.881789  in-header: 03 07 00 00 08 00 00 00 

  382 12:21:18.885109  in-data: aa e4 47 04 13 02 00 00 

  383 12:21:18.888674  Chrome EC: UHEPI supported

  384 12:21:18.896577  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  385 12:21:18.899870  in-header: 03 9d 00 00 08 00 00 00 

  386 12:21:18.903660  in-data: 10 20 20 08 00 00 00 00 

  387 12:21:18.904094  Phase 1

  388 12:21:18.907255  FMAP: area GBB found @ 3f5000 (12032 bytes)

  389 12:21:18.914635  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  390 12:21:18.918470  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  391 12:21:18.921685  Recovery requested (1009000e)

  392 12:21:18.929831  TPM: Extending digest for VBOOT: boot mode into PCR 0

  393 12:21:18.935492  tlcl_extend: response is 0

  394 12:21:18.943266  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  395 12:21:18.948717  tlcl_extend: response is 0

  396 12:21:18.955697  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  397 12:21:18.976217  read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps

  398 12:21:18.983463  BS: bootblock times (exec / console): total (unknown) / 149 ms

  399 12:21:18.983997  

  400 12:21:18.984339  

  401 12:21:18.994467  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  402 12:21:18.995080  ARM64: Exception handlers installed.

  403 12:21:18.998550  ARM64: Testing exception

  404 12:21:19.001380  ARM64: Done test exception

  405 12:21:19.021574  pmic_efuse_setting: Set efuses in 11 msecs

  406 12:21:19.025793  pmwrap_interface_init: Select PMIF_VLD_RDY

  407 12:21:19.029041  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  408 12:21:19.036466  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  409 12:21:19.040522  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  410 12:21:19.043927  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  411 12:21:19.051376  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  412 12:21:19.055110  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  413 12:21:19.059126  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  414 12:21:19.066229  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  415 12:21:19.068979  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  416 12:21:19.072361  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  417 12:21:19.079503  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  418 12:21:19.082983  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  419 12:21:19.086390  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  420 12:21:19.092768  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  421 12:21:19.099899  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  422 12:21:19.106305  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  423 12:21:19.109771  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  424 12:21:19.116344  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  425 12:21:19.123802  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  426 12:21:19.126999  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  427 12:21:19.134525  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  428 12:21:19.138275  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  429 12:21:19.144576  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  430 12:21:19.148122  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  431 12:21:19.155095  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  432 12:21:19.161711  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  433 12:21:19.165697  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  434 12:21:19.169882  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  435 12:21:19.175963  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  436 12:21:19.179543  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  437 12:21:19.186592  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  438 12:21:19.190228  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  439 12:21:19.194126  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  440 12:21:19.201498  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  441 12:21:19.205024  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  442 12:21:19.212328  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  443 12:21:19.215530  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  444 12:21:19.218665  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  445 12:21:19.225652  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  446 12:21:19.228801  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  447 12:21:19.231864  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  448 12:21:19.238549  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  449 12:21:19.242209  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  450 12:21:19.245053  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  451 12:21:19.252334  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  452 12:21:19.255089  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  453 12:21:19.258759  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  454 12:21:19.265632  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  455 12:21:19.268447  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  456 12:21:19.272279  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  457 12:21:19.275771  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  458 12:21:19.285106  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  459 12:21:19.292304  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  460 12:21:19.298472  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  461 12:21:19.304969  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  462 12:21:19.315979  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  463 12:21:19.318868  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  464 12:21:19.322241  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  465 12:21:19.328714  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  466 12:21:19.335748  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x5

  467 12:21:19.338607  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  468 12:21:19.346111  [RTC]rtc_osc_init,62: osc32con val = 0xde6f

  469 12:21:19.349255  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  470 12:21:19.358938  [RTC]rtc_get_frequency_meter,154: input=15, output=794

  471 12:21:19.362090  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f

  472 12:21:19.368746  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  473 12:21:19.372231  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  474 12:21:19.375473  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  475 12:21:19.378762  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  476 12:21:19.381737  ADC[4]: Raw value=899260 ID=7

  477 12:21:19.385116  ADC[3]: Raw value=213440 ID=1

  478 12:21:19.388943  RAM Code: 0x71

  479 12:21:19.392075  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  480 12:21:19.394941  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  481 12:21:19.405683  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  482 12:21:19.412403  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  483 12:21:19.416100  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  484 12:21:19.419477  in-header: 03 07 00 00 08 00 00 00 

  485 12:21:19.422523  in-data: aa e4 47 04 13 02 00 00 

  486 12:21:19.423055  Chrome EC: UHEPI supported

  487 12:21:19.429667  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  488 12:21:19.434010  in-header: 03 d5 00 00 08 00 00 00 

  489 12:21:19.437424  in-data: 98 20 60 08 00 00 00 00 

  490 12:21:19.440876  MRC: failed to locate region type 0.

  491 12:21:19.448047  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  492 12:21:19.452154  DRAM-K: Running full calibration

  493 12:21:19.458363  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  494 12:21:19.458793  header.status = 0x0

  495 12:21:19.461369  header.version = 0x6 (expected: 0x6)

  496 12:21:19.464996  header.size = 0xd00 (expected: 0xd00)

  497 12:21:19.468877  header.flags = 0x0

  498 12:21:19.472135  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  499 12:21:19.491175  read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps

  500 12:21:19.498545  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  501 12:21:19.502763  dram_init: ddr_geometry: 2

  502 12:21:19.503296  [EMI] MDL number = 2

  503 12:21:19.506241  [EMI] Get MDL freq = 0

  504 12:21:19.506768  dram_init: ddr_type: 0

  505 12:21:19.509913  is_discrete_lpddr4: 1

  506 12:21:19.513950  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  507 12:21:19.514385  

  508 12:21:19.514719  

  509 12:21:19.515029  [Bian_co] ETT version 0.0.0.1

  510 12:21:19.521245   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  511 12:21:19.521760  

  512 12:21:19.524703  dramc_set_vcore_voltage set vcore to 650000

  513 12:21:19.525129  Read voltage for 800, 4

  514 12:21:19.528387  Vio18 = 0

  515 12:21:19.528809  Vcore = 650000

  516 12:21:19.529147  Vdram = 0

  517 12:21:19.529456  Vddq = 0

  518 12:21:19.532082  Vmddr = 0

  519 12:21:19.532506  dram_init: config_dvfs: 1

  520 12:21:19.540527  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  521 12:21:19.543914  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  522 12:21:19.547551  [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9

  523 12:21:19.550974  freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9

  524 12:21:19.554932  [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9

  525 12:21:19.558896  freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9

  526 12:21:19.562414  MEM_TYPE=3, freq_sel=18

  527 12:21:19.565457  sv_algorithm_assistance_LP4_1600 

  528 12:21:19.569105  ============ PULL DRAM RESETB DOWN ============

  529 12:21:19.572693  ========== PULL DRAM RESETB DOWN end =========

  530 12:21:19.575530  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  531 12:21:19.579200  =================================== 

  532 12:21:19.582714  LPDDR4 DRAM CONFIGURATION

  533 12:21:19.586026  =================================== 

  534 12:21:19.589295  EX_ROW_EN[0]    = 0x0

  535 12:21:19.589727  EX_ROW_EN[1]    = 0x0

  536 12:21:19.592110  LP4Y_EN      = 0x0

  537 12:21:19.592556  WORK_FSP     = 0x0

  538 12:21:19.595323  WL           = 0x2

  539 12:21:19.595807  RL           = 0x2

  540 12:21:19.599006  BL           = 0x2

  541 12:21:19.599474  RPST         = 0x0

  542 12:21:19.602450  RD_PRE       = 0x0

  543 12:21:19.602973  WR_PRE       = 0x1

  544 12:21:19.605695  WR_PST       = 0x0

  545 12:21:19.606199  DBI_WR       = 0x0

  546 12:21:19.608967  DBI_RD       = 0x0

  547 12:21:19.609397  OTF          = 0x1

  548 12:21:19.612153  =================================== 

  549 12:21:19.615639  =================================== 

  550 12:21:19.619023  ANA top config

  551 12:21:19.622216  =================================== 

  552 12:21:19.625867  DLL_ASYNC_EN            =  0

  553 12:21:19.626297  ALL_SLAVE_EN            =  1

  554 12:21:19.628764  NEW_RANK_MODE           =  1

  555 12:21:19.632265  DLL_IDLE_MODE           =  1

  556 12:21:19.635368  LP45_APHY_COMB_EN       =  1

  557 12:21:19.635844  TX_ODT_DIS              =  1

  558 12:21:19.638757  NEW_8X_MODE             =  1

  559 12:21:19.642551  =================================== 

  560 12:21:19.645964  =================================== 

  561 12:21:19.648787  data_rate                  = 1600

  562 12:21:19.652081  CKR                        = 1

  563 12:21:19.655308  DQ_P2S_RATIO               = 8

  564 12:21:19.658897  =================================== 

  565 12:21:19.662474  CA_P2S_RATIO               = 8

  566 12:21:19.663003  DQ_CA_OPEN                 = 0

  567 12:21:19.665690  DQ_SEMI_OPEN               = 0

  568 12:21:19.668744  CA_SEMI_OPEN               = 0

  569 12:21:19.672180  CA_FULL_RATE               = 0

  570 12:21:19.676125  DQ_CKDIV4_EN               = 1

  571 12:21:19.676550  CA_CKDIV4_EN               = 1

  572 12:21:19.679424  CA_PREDIV_EN               = 0

  573 12:21:19.682462  PH8_DLY                    = 0

  574 12:21:19.685440  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  575 12:21:19.689384  DQ_AAMCK_DIV               = 4

  576 12:21:19.692431  CA_AAMCK_DIV               = 4

  577 12:21:19.692858  CA_ADMCK_DIV               = 4

  578 12:21:19.695635  DQ_TRACK_CA_EN             = 0

  579 12:21:19.699136  CA_PICK                    = 800

  580 12:21:19.702325  CA_MCKIO                   = 800

  581 12:21:19.705454  MCKIO_SEMI                 = 0

  582 12:21:19.709757  PLL_FREQ                   = 3068

  583 12:21:19.712267  DQ_UI_PI_RATIO             = 32

  584 12:21:19.712787  CA_UI_PI_RATIO             = 0

  585 12:21:19.715528  =================================== 

  586 12:21:19.718988  =================================== 

  587 12:21:19.722187  memory_type:LPDDR4         

  588 12:21:19.725650  GP_NUM     : 10       

  589 12:21:19.726075  SRAM_EN    : 1       

  590 12:21:19.729487  MD32_EN    : 0       

  591 12:21:19.732695  =================================== 

  592 12:21:19.735756  [ANA_INIT] >>>>>>>>>>>>>> 

  593 12:21:19.738886  <<<<<< [CONFIGURE PHASE]: ANA_TX

  594 12:21:19.742553  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  595 12:21:19.745548  =================================== 

  596 12:21:19.745979  data_rate = 1600,PCW = 0X7600

  597 12:21:19.749096  =================================== 

  598 12:21:19.752358  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  599 12:21:19.759249  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  600 12:21:19.765793  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  601 12:21:19.769169  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  602 12:21:19.772742  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  603 12:21:19.776555  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  604 12:21:19.779672  [ANA_INIT] flow start 

  605 12:21:19.780118  [ANA_INIT] PLL >>>>>>>> 

  606 12:21:19.783677  [ANA_INIT] PLL <<<<<<<< 

  607 12:21:19.784101  [ANA_INIT] MIDPI >>>>>>>> 

  608 12:21:19.787357  [ANA_INIT] MIDPI <<<<<<<< 

  609 12:21:19.790798  [ANA_INIT] DLL >>>>>>>> 

  610 12:21:19.791222  [ANA_INIT] flow end 

  611 12:21:19.794428  ============ LP4 DIFF to SE enter ============

  612 12:21:19.802056  ============ LP4 DIFF to SE exit  ============

  613 12:21:19.802604  [ANA_INIT] <<<<<<<<<<<<< 

  614 12:21:19.806126  [Flow] Enable top DCM control >>>>> 

  615 12:21:19.809345  [Flow] Enable top DCM control <<<<< 

  616 12:21:19.812927  Enable DLL master slave shuffle 

  617 12:21:19.816890  ============================================================== 

  618 12:21:19.820283  Gating Mode config

  619 12:21:19.823992  ============================================================== 

  620 12:21:19.826729  Config description: 

  621 12:21:19.837767  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  622 12:21:19.841555  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  623 12:21:19.849093  SELPH_MODE            0: By rank         1: By Phase 

  624 12:21:19.852230  ============================================================== 

  625 12:21:19.856452  GAT_TRACK_EN                 =  1

  626 12:21:19.859955  RX_GATING_MODE               =  2

  627 12:21:19.863818  RX_GATING_TRACK_MODE         =  2

  628 12:21:19.864471  SELPH_MODE                   =  1

  629 12:21:19.866725  PICG_EARLY_EN                =  1

  630 12:21:19.871280  VALID_LAT_VALUE              =  1

  631 12:21:19.878313  ============================================================== 

  632 12:21:19.881674  Enter into Gating configuration >>>> 

  633 12:21:19.882105  Exit from Gating configuration <<<< 

  634 12:21:19.885809  Enter into  DVFS_PRE_config >>>>> 

  635 12:21:19.896658  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  636 12:21:19.900206  Exit from  DVFS_PRE_config <<<<< 

  637 12:21:19.904153  Enter into PICG configuration >>>> 

  638 12:21:19.907822  Exit from PICG configuration <<<< 

  639 12:21:19.911880  [RX_INPUT] configuration >>>>> 

  640 12:21:19.912663  [RX_INPUT] configuration <<<<< 

  641 12:21:19.919268  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  642 12:21:19.923136  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  643 12:21:19.930602  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  644 12:21:19.934229  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  645 12:21:19.941412  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  646 12:21:19.948838  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  647 12:21:19.952337  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  648 12:21:19.956351  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  649 12:21:19.959880  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  650 12:21:19.963814  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  651 12:21:19.967727  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  652 12:21:19.971022  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  653 12:21:19.974848  =================================== 

  654 12:21:19.978920  LPDDR4 DRAM CONFIGURATION

  655 12:21:19.982646  =================================== 

  656 12:21:19.983184  EX_ROW_EN[0]    = 0x0

  657 12:21:19.986272  EX_ROW_EN[1]    = 0x0

  658 12:21:19.986696  LP4Y_EN      = 0x0

  659 12:21:19.989914  WORK_FSP     = 0x0

  660 12:21:19.990627  WL           = 0x2

  661 12:21:19.993234  RL           = 0x2

  662 12:21:19.993720  BL           = 0x2

  663 12:21:19.996854  RPST         = 0x0

  664 12:21:19.997274  RD_PRE       = 0x0

  665 12:21:20.000662  WR_PRE       = 0x1

  666 12:21:20.001087  WR_PST       = 0x0

  667 12:21:20.004351  DBI_WR       = 0x0

  668 12:21:20.004784  DBI_RD       = 0x0

  669 12:21:20.008289  OTF          = 0x1

  670 12:21:20.008730  =================================== 

  671 12:21:20.011459  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  672 12:21:20.018962  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  673 12:21:20.022860  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  674 12:21:20.026191  =================================== 

  675 12:21:20.026624  LPDDR4 DRAM CONFIGURATION

  676 12:21:20.030093  =================================== 

  677 12:21:20.033988  EX_ROW_EN[0]    = 0x10

  678 12:21:20.034424  EX_ROW_EN[1]    = 0x0

  679 12:21:20.037434  LP4Y_EN      = 0x0

  680 12:21:20.037892  WORK_FSP     = 0x0

  681 12:21:20.041295  WL           = 0x2

  682 12:21:20.041874  RL           = 0x2

  683 12:21:20.044607  BL           = 0x2

  684 12:21:20.045033  RPST         = 0x0

  685 12:21:20.048409  RD_PRE       = 0x0

  686 12:21:20.048853  WR_PRE       = 0x1

  687 12:21:20.052817  WR_PST       = 0x0

  688 12:21:20.053296  DBI_WR       = 0x0

  689 12:21:20.055760  DBI_RD       = 0x0

  690 12:21:20.056242  OTF          = 0x1

  691 12:21:20.059616  =================================== 

  692 12:21:20.067757  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  693 12:21:20.071031  nWR fixed to 40

  694 12:21:20.071520  [ModeRegInit_LP4] CH0 RK0

  695 12:21:20.074810  [ModeRegInit_LP4] CH0 RK1

  696 12:21:20.075239  [ModeRegInit_LP4] CH1 RK0

  697 12:21:20.078483  [ModeRegInit_LP4] CH1 RK1

  698 12:21:20.078907  match AC timing 13

  699 12:21:20.085655  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  700 12:21:20.088841  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  701 12:21:20.092903  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  702 12:21:20.096948  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  703 12:21:20.103961  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  704 12:21:20.104471  [EMI DOE] emi_dcm 0

  705 12:21:20.107674  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  706 12:21:20.108101  ==

  707 12:21:20.111164  Dram Type= 6, Freq= 0, CH_0, rank 0

  708 12:21:20.115035  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  709 12:21:20.115714  ==

  710 12:21:20.121958  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  711 12:21:20.129109  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  712 12:21:20.136804  [CA 0] Center 38 (7~69) winsize 63

  713 12:21:20.140481  [CA 1] Center 37 (7~68) winsize 62

  714 12:21:20.143992  [CA 2] Center 35 (5~66) winsize 62

  715 12:21:20.146820  [CA 3] Center 35 (5~66) winsize 62

  716 12:21:20.150144  [CA 4] Center 34 (4~65) winsize 62

  717 12:21:20.153472  [CA 5] Center 34 (4~64) winsize 61

  718 12:21:20.153901  

  719 12:21:20.157239  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  720 12:21:20.157771  

  721 12:21:20.160691  [CATrainingPosCal] consider 1 rank data

  722 12:21:20.163532  u2DelayCellTimex100 = 270/100 ps

  723 12:21:20.166657  CA0 delay=38 (7~69),Diff = 4 PI (28 cell)

  724 12:21:20.170471  CA1 delay=37 (7~68),Diff = 3 PI (21 cell)

  725 12:21:20.173623  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

  726 12:21:20.180484  CA3 delay=35 (5~66),Diff = 1 PI (7 cell)

  727 12:21:20.183435  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

  728 12:21:20.187285  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

  729 12:21:20.187868  

  730 12:21:20.190514  CA PerBit enable=1, Macro0, CA PI delay=34

  731 12:21:20.191045  

  732 12:21:20.193783  [CBTSetCACLKResult] CA Dly = 34

  733 12:21:20.194438  CS Dly: 6 (0~37)

  734 12:21:20.194889  ==

  735 12:21:20.196928  Dram Type= 6, Freq= 0, CH_0, rank 1

  736 12:21:20.203824  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  737 12:21:20.204354  ==

  738 12:21:20.206793  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  739 12:21:20.213804  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  740 12:21:20.222854  [CA 0] Center 38 (7~69) winsize 63

  741 12:21:20.226495  [CA 1] Center 38 (7~69) winsize 63

  742 12:21:20.229519  [CA 2] Center 35 (5~66) winsize 62

  743 12:21:20.232700  [CA 3] Center 35 (5~66) winsize 62

  744 12:21:20.236173  [CA 4] Center 34 (4~65) winsize 62

  745 12:21:20.239816  [CA 5] Center 34 (4~65) winsize 62

  746 12:21:20.240249  

  747 12:21:20.243119  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  748 12:21:20.243584  

  749 12:21:20.246364  [CATrainingPosCal] consider 2 rank data

  750 12:21:20.249613  u2DelayCellTimex100 = 270/100 ps

  751 12:21:20.253276  CA0 delay=38 (7~69),Diff = 4 PI (28 cell)

  752 12:21:20.256395  CA1 delay=37 (7~68),Diff = 3 PI (21 cell)

  753 12:21:20.262652  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

  754 12:21:20.265914  CA3 delay=35 (5~66),Diff = 1 PI (7 cell)

  755 12:21:20.269433  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

  756 12:21:20.273008  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

  757 12:21:20.273162  

  758 12:21:20.276197  CA PerBit enable=1, Macro0, CA PI delay=34

  759 12:21:20.276330  

  760 12:21:20.279382  [CBTSetCACLKResult] CA Dly = 34

  761 12:21:20.279530  CS Dly: 6 (0~38)

  762 12:21:20.279635  

  763 12:21:20.283031  ----->DramcWriteLeveling(PI) begin...

  764 12:21:20.283154  ==

  765 12:21:20.285742  Dram Type= 6, Freq= 0, CH_0, rank 0

  766 12:21:20.292616  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  767 12:21:20.292712  ==

  768 12:21:20.295676  Write leveling (Byte 0): 30 => 30

  769 12:21:20.299087  Write leveling (Byte 1): 28 => 28

  770 12:21:20.299172  DramcWriteLeveling(PI) end<-----

  771 12:21:20.302618  

  772 12:21:20.302701  ==

  773 12:21:20.306000  Dram Type= 6, Freq= 0, CH_0, rank 0

  774 12:21:20.309432  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  775 12:21:20.309517  ==

  776 12:21:20.312983  [Gating] SW mode calibration

  777 12:21:20.319462  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  778 12:21:20.323004  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  779 12:21:20.329341   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  780 12:21:20.332562   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  781 12:21:20.336079   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

  782 12:21:20.343029   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  783 12:21:20.346193   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  784 12:21:20.349197   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  785 12:21:20.355900   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  786 12:21:20.359347   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  787 12:21:20.363048   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  788 12:21:20.367018   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  789 12:21:20.370415   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  790 12:21:20.378269   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  791 12:21:20.381236   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  792 12:21:20.384855   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  793 12:21:20.388738   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  794 12:21:20.395333   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  795 12:21:20.398374   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  796 12:21:20.401966   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  797 12:21:20.408603   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

  798 12:21:20.411932   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

  799 12:21:20.415227   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 12:21:20.421926   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 12:21:20.424841   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 12:21:20.428206   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 12:21:20.434948   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  804 12:21:20.438545   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  805 12:21:20.441910   0  9  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  806 12:21:20.448532   0  9 12 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)

  807 12:21:20.451861   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  808 12:21:20.455291   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  809 12:21:20.458792   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  810 12:21:20.465257   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  811 12:21:20.468325   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  812 12:21:20.471902   0 10  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

  813 12:21:20.478383   0 10  8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)

  814 12:21:20.482079   0 10 12 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)

  815 12:21:20.485047   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  816 12:21:20.491950   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  817 12:21:20.495543   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  818 12:21:20.498763   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  819 12:21:20.505206   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  820 12:21:20.508649   0 11  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  821 12:21:20.512343   0 11  8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

  822 12:21:20.518376   0 11 12 | B1->B0 | 3434 3f3f | 0 1 | (0 0) (0 0)

  823 12:21:20.521906   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  824 12:21:20.524999   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  825 12:21:20.531642   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  826 12:21:20.535347   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  827 12:21:20.538349   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  828 12:21:20.541777   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  829 12:21:20.548726   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  830 12:21:20.551653   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  831 12:21:20.555256   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  832 12:21:20.562025   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  833 12:21:20.565231   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  834 12:21:20.568648   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  835 12:21:20.575080   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  836 12:21:20.578687   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  837 12:21:20.582059   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  838 12:21:20.588156   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  839 12:21:20.591736   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  840 12:21:20.594995   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  841 12:21:20.601643   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  842 12:21:20.605061   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  843 12:21:20.608451   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  844 12:21:20.615049   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  845 12:21:20.618291   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

  846 12:21:20.621978   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  847 12:21:20.624955  Total UI for P1: 0, mck2ui 16

  848 12:21:20.628603  best dqsien dly found for B0: ( 0, 14,  8)

  849 12:21:20.631695  Total UI for P1: 0, mck2ui 16

  850 12:21:20.634919  best dqsien dly found for B1: ( 0, 14,  8)

  851 12:21:20.638389  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

  852 12:21:20.641704  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

  853 12:21:20.641852  

  854 12:21:20.644948  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

  855 12:21:20.651800  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

  856 12:21:20.651980  [Gating] SW calibration Done

  857 12:21:20.652088  ==

  858 12:21:20.655413  Dram Type= 6, Freq= 0, CH_0, rank 0

  859 12:21:20.661855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  860 12:21:20.662033  ==

  861 12:21:20.662148  RX Vref Scan: 0

  862 12:21:20.662239  

  863 12:21:20.665188  RX Vref 0 -> 0, step: 1

  864 12:21:20.665425  

  865 12:21:20.668493  RX Delay -130 -> 252, step: 16

  866 12:21:20.671995  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

  867 12:21:20.675298  iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240

  868 12:21:20.678205  iDelay=206, Bit 2, Center 77 (-50 ~ 205) 256

  869 12:21:20.681596  iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256

  870 12:21:20.688330  iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240

  871 12:21:20.691515  iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240

  872 12:21:20.694918  iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240

  873 12:21:20.698418  iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240

  874 12:21:20.701683  iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256

  875 12:21:20.708208  iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240

  876 12:21:20.711836  iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240

  877 12:21:20.715072  iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256

  878 12:21:20.718487  iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256

  879 12:21:20.721758  iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256

  880 12:21:20.728407  iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256

  881 12:21:20.731958  iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256

  882 12:21:20.732112  ==

  883 12:21:20.735162  Dram Type= 6, Freq= 0, CH_0, rank 0

  884 12:21:20.738268  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  885 12:21:20.738384  ==

  886 12:21:20.741824  DQS Delay:

  887 12:21:20.741943  DQS0 = 0, DQS1 = 0

  888 12:21:20.742042  DQM Delay:

  889 12:21:20.745248  DQM0 = 81, DQM1 = 69

  890 12:21:20.745381  DQ Delay:

  891 12:21:20.748609  DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77

  892 12:21:20.751889  DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85

  893 12:21:20.755170  DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61

  894 12:21:20.758930  DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77

  895 12:21:20.759072  

  896 12:21:20.759180  

  897 12:21:20.759281  ==

  898 12:21:20.761703  Dram Type= 6, Freq= 0, CH_0, rank 0

  899 12:21:20.768255  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  900 12:21:20.768412  ==

  901 12:21:20.768520  

  902 12:21:20.768617  

  903 12:21:20.768713  	TX Vref Scan disable

  904 12:21:20.771999   == TX Byte 0 ==

  905 12:21:20.775267  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  906 12:21:20.778860  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  907 12:21:20.781846   == TX Byte 1 ==

  908 12:21:20.785170  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

  909 12:21:20.788616  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

  910 12:21:20.792114  ==

  911 12:21:20.795556  Dram Type= 6, Freq= 0, CH_0, rank 0

  912 12:21:20.798541  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  913 12:21:20.798651  ==

  914 12:21:20.811264  TX Vref=22, minBit 11, minWin=26, winSum=439

  915 12:21:20.814700  TX Vref=24, minBit 1, minWin=27, winSum=442

  916 12:21:20.817716  TX Vref=26, minBit 2, minWin=27, winSum=443

  917 12:21:20.820860  TX Vref=28, minBit 11, minWin=27, winSum=446

  918 12:21:20.824280  TX Vref=30, minBit 2, minWin=27, winSum=445

  919 12:21:20.831036  TX Vref=32, minBit 2, minWin=26, winSum=439

  920 12:21:20.834545  [TxChooseVref] Worse bit 11, Min win 27, Win sum 446, Final Vref 28

  921 12:21:20.834653  

  922 12:21:20.837741  Final TX Range 1 Vref 28

  923 12:21:20.837842  

  924 12:21:20.837911  ==

  925 12:21:20.841281  Dram Type= 6, Freq= 0, CH_0, rank 0

  926 12:21:20.844650  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  927 12:21:20.847526  ==

  928 12:21:20.847622  

  929 12:21:20.847690  

  930 12:21:20.847761  	TX Vref Scan disable

  931 12:21:20.851189   == TX Byte 0 ==

  932 12:21:20.854903  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  933 12:21:20.858206  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  934 12:21:20.861452   == TX Byte 1 ==

  935 12:21:20.864374  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

  936 12:21:20.868253  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

  937 12:21:20.871110  

  938 12:21:20.871225  [DATLAT]

  939 12:21:20.871299  Freq=800, CH0 RK0

  940 12:21:20.871367  

  941 12:21:20.874689  DATLAT Default: 0xa

  942 12:21:20.874823  0, 0xFFFF, sum = 0

  943 12:21:20.878098  1, 0xFFFF, sum = 0

  944 12:21:20.878199  2, 0xFFFF, sum = 0

  945 12:21:20.881342  3, 0xFFFF, sum = 0

  946 12:21:20.881435  4, 0xFFFF, sum = 0

  947 12:21:20.884563  5, 0xFFFF, sum = 0

  948 12:21:20.884657  6, 0xFFFF, sum = 0

  949 12:21:20.888008  7, 0xFFFF, sum = 0

  950 12:21:20.891418  8, 0xFFFF, sum = 0

  951 12:21:20.891516  9, 0x0, sum = 1

  952 12:21:20.891587  10, 0x0, sum = 2

  953 12:21:20.894845  11, 0x0, sum = 3

  954 12:21:20.894937  12, 0x0, sum = 4

  955 12:21:20.898375  best_step = 10

  956 12:21:20.898475  

  957 12:21:20.898546  ==

  958 12:21:20.901491  Dram Type= 6, Freq= 0, CH_0, rank 0

  959 12:21:20.904604  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  960 12:21:20.904726  ==

  961 12:21:20.908192  RX Vref Scan: 1

  962 12:21:20.908313  

  963 12:21:20.908410  Set Vref Range= 32 -> 127

  964 12:21:20.908504  

  965 12:21:20.911499  RX Vref 32 -> 127, step: 1

  966 12:21:20.911612  

  967 12:21:20.914867  RX Delay -111 -> 252, step: 8

  968 12:21:20.914980  

  969 12:21:20.918136  Set Vref, RX VrefLevel [Byte0]: 32

  970 12:21:20.921526                           [Byte1]: 32

  971 12:21:20.921647  

  972 12:21:20.924750  Set Vref, RX VrefLevel [Byte0]: 33

  973 12:21:20.928083                           [Byte1]: 33

  974 12:21:20.931621  

  975 12:21:20.931745  Set Vref, RX VrefLevel [Byte0]: 34

  976 12:21:20.934841                           [Byte1]: 34

  977 12:21:20.939477  

  978 12:21:20.939609  Set Vref, RX VrefLevel [Byte0]: 35

  979 12:21:20.942748                           [Byte1]: 35

  980 12:21:20.947088  

  981 12:21:20.947217  Set Vref, RX VrefLevel [Byte0]: 36

  982 12:21:20.950418                           [Byte1]: 36

  983 12:21:20.954470  

  984 12:21:20.954621  Set Vref, RX VrefLevel [Byte0]: 37

  985 12:21:20.957793                           [Byte1]: 37

  986 12:21:20.962637  

  987 12:21:20.962848  Set Vref, RX VrefLevel [Byte0]: 38

  988 12:21:20.965953                           [Byte1]: 38

  989 12:21:20.970266  

  990 12:21:20.970470  Set Vref, RX VrefLevel [Byte0]: 39

  991 12:21:20.973298                           [Byte1]: 39

  992 12:21:20.977698  

  993 12:21:20.977884  Set Vref, RX VrefLevel [Byte0]: 40

  994 12:21:20.980959                           [Byte1]: 40

  995 12:21:20.985946  

  996 12:21:20.986146  Set Vref, RX VrefLevel [Byte0]: 41

  997 12:21:20.988689                           [Byte1]: 41

  998 12:21:20.993383  

  999 12:21:20.993568  Set Vref, RX VrefLevel [Byte0]: 42

 1000 12:21:20.996414                           [Byte1]: 42

 1001 12:21:21.000939  

 1002 12:21:21.001116  Set Vref, RX VrefLevel [Byte0]: 43

 1003 12:21:21.003744                           [Byte1]: 43

 1004 12:21:21.008157  

 1005 12:21:21.008336  Set Vref, RX VrefLevel [Byte0]: 44

 1006 12:21:21.012058                           [Byte1]: 44

 1007 12:21:21.016073  

 1008 12:21:21.016297  Set Vref, RX VrefLevel [Byte0]: 45

 1009 12:21:21.019338                           [Byte1]: 45

 1010 12:21:21.023701  

 1011 12:21:21.023903  Set Vref, RX VrefLevel [Byte0]: 46

 1012 12:21:21.026980                           [Byte1]: 46

 1013 12:21:21.031531  

 1014 12:21:21.031738  Set Vref, RX VrefLevel [Byte0]: 47

 1015 12:21:21.034721                           [Byte1]: 47

 1016 12:21:21.039640  

 1017 12:21:21.039841  Set Vref, RX VrefLevel [Byte0]: 48

 1018 12:21:21.042658                           [Byte1]: 48

 1019 12:21:21.047316  

 1020 12:21:21.047567  Set Vref, RX VrefLevel [Byte0]: 49

 1021 12:21:21.050688                           [Byte1]: 49

 1022 12:21:21.054541  

 1023 12:21:21.054717  Set Vref, RX VrefLevel [Byte0]: 50

 1024 12:21:21.058037                           [Byte1]: 50

 1025 12:21:21.061799  

 1026 12:21:21.062005  Set Vref, RX VrefLevel [Byte0]: 51

 1027 12:21:21.064993                           [Byte1]: 51

 1028 12:21:21.069281  

 1029 12:21:21.069470  Set Vref, RX VrefLevel [Byte0]: 52

 1030 12:21:21.072625                           [Byte1]: 52

 1031 12:21:21.077131  

 1032 12:21:21.077302  Set Vref, RX VrefLevel [Byte0]: 53

 1033 12:21:21.080117                           [Byte1]: 53

 1034 12:21:21.084703  

 1035 12:21:21.084887  Set Vref, RX VrefLevel [Byte0]: 54

 1036 12:21:21.088163                           [Byte1]: 54

 1037 12:21:21.092183  

 1038 12:21:21.092402  Set Vref, RX VrefLevel [Byte0]: 55

 1039 12:21:21.095989                           [Byte1]: 55

 1040 12:21:21.100037  

 1041 12:21:21.100221  Set Vref, RX VrefLevel [Byte0]: 56

 1042 12:21:21.103233                           [Byte1]: 56

 1043 12:21:21.107515  

 1044 12:21:21.107699  Set Vref, RX VrefLevel [Byte0]: 57

 1045 12:21:21.110841                           [Byte1]: 57

 1046 12:21:21.115103  

 1047 12:21:21.115281  Set Vref, RX VrefLevel [Byte0]: 58

 1048 12:21:21.118736                           [Byte1]: 58

 1049 12:21:21.122779  

 1050 12:21:21.122949  Set Vref, RX VrefLevel [Byte0]: 59

 1051 12:21:21.126252                           [Byte1]: 59

 1052 12:21:21.130708  

 1053 12:21:21.130883  Set Vref, RX VrefLevel [Byte0]: 60

 1054 12:21:21.133867                           [Byte1]: 60

 1055 12:21:21.138069  

 1056 12:21:21.138265  Set Vref, RX VrefLevel [Byte0]: 61

 1057 12:21:21.141858                           [Byte1]: 61

 1058 12:21:21.145821  

 1059 12:21:21.146036  Set Vref, RX VrefLevel [Byte0]: 62

 1060 12:21:21.149070                           [Byte1]: 62

 1061 12:21:21.153238  

 1062 12:21:21.153424  Set Vref, RX VrefLevel [Byte0]: 63

 1063 12:21:21.156851                           [Byte1]: 63

 1064 12:21:21.160792  

 1065 12:21:21.160937  Set Vref, RX VrefLevel [Byte0]: 64

 1066 12:21:21.164849                           [Byte1]: 64

 1067 12:21:21.168822  

 1068 12:21:21.168952  Set Vref, RX VrefLevel [Byte0]: 65

 1069 12:21:21.172240                           [Byte1]: 65

 1070 12:21:21.176283  

 1071 12:21:21.176418  Set Vref, RX VrefLevel [Byte0]: 66

 1072 12:21:21.179438                           [Byte1]: 66

 1073 12:21:21.183847  

 1074 12:21:21.183995  Set Vref, RX VrefLevel [Byte0]: 67

 1075 12:21:21.187362                           [Byte1]: 67

 1076 12:21:21.191506  

 1077 12:21:21.191653  Set Vref, RX VrefLevel [Byte0]: 68

 1078 12:21:21.195204                           [Byte1]: 68

 1079 12:21:21.199586  

 1080 12:21:21.199755  Set Vref, RX VrefLevel [Byte0]: 69

 1081 12:21:21.202953                           [Byte1]: 69

 1082 12:21:21.207280  

 1083 12:21:21.207444  Set Vref, RX VrefLevel [Byte0]: 70

 1084 12:21:21.210367                           [Byte1]: 70

 1085 12:21:21.214432  

 1086 12:21:21.214559  Set Vref, RX VrefLevel [Byte0]: 71

 1087 12:21:21.217798                           [Byte1]: 71

 1088 12:21:21.222381  

 1089 12:21:21.222503  Set Vref, RX VrefLevel [Byte0]: 72

 1090 12:21:21.225654                           [Byte1]: 72

 1091 12:21:21.229668  

 1092 12:21:21.229783  Set Vref, RX VrefLevel [Byte0]: 73

 1093 12:21:21.233056                           [Byte1]: 73

 1094 12:21:21.237421  

 1095 12:21:21.237537  Set Vref, RX VrefLevel [Byte0]: 74

 1096 12:21:21.240638                           [Byte1]: 74

 1097 12:21:21.245079  

 1098 12:21:21.245198  Set Vref, RX VrefLevel [Byte0]: 75

 1099 12:21:21.248661                           [Byte1]: 75

 1100 12:21:21.253236  

 1101 12:21:21.253359  Set Vref, RX VrefLevel [Byte0]: 76

 1102 12:21:21.256112                           [Byte1]: 76

 1103 12:21:21.260447  

 1104 12:21:21.260560  Set Vref, RX VrefLevel [Byte0]: 77

 1105 12:21:21.263751                           [Byte1]: 77

 1106 12:21:21.268106  

 1107 12:21:21.268225  Set Vref, RX VrefLevel [Byte0]: 78

 1108 12:21:21.274467                           [Byte1]: 78

 1109 12:21:21.274587  

 1110 12:21:21.277865  Final RX Vref Byte 0 = 61 to rank0

 1111 12:21:21.281238  Final RX Vref Byte 1 = 61 to rank0

 1112 12:21:21.284679  Final RX Vref Byte 0 = 61 to rank1

 1113 12:21:21.288162  Final RX Vref Byte 1 = 61 to rank1==

 1114 12:21:21.291283  Dram Type= 6, Freq= 0, CH_0, rank 0

 1115 12:21:21.294572  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1116 12:21:21.294692  ==

 1117 12:21:21.294790  DQS Delay:

 1118 12:21:21.297637  DQS0 = 0, DQS1 = 0

 1119 12:21:21.297748  DQM Delay:

 1120 12:21:21.301252  DQM0 = 81, DQM1 = 68

 1121 12:21:21.301361  DQ Delay:

 1122 12:21:21.304375  DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80

 1123 12:21:21.307815  DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92

 1124 12:21:21.310870  DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60

 1125 12:21:21.314411  DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76

 1126 12:21:21.314526  

 1127 12:21:21.314622  

 1128 12:21:21.321422  [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps

 1129 12:21:21.324210  CH0 RK0: MR19=606, MR18=2626

 1130 12:21:21.331176  CH0_RK0: MR19=0x606, MR18=0x2626, DQSOSC=400, MR23=63, INC=92, DEC=61

 1131 12:21:21.331306  

 1132 12:21:21.334643  ----->DramcWriteLeveling(PI) begin...

 1133 12:21:21.334758  ==

 1134 12:21:21.337835  Dram Type= 6, Freq= 0, CH_0, rank 1

 1135 12:21:21.341194  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1136 12:21:21.341308  ==

 1137 12:21:21.344246  Write leveling (Byte 0): 33 => 33

 1138 12:21:21.347621  Write leveling (Byte 1): 29 => 29

 1139 12:21:21.350895  DramcWriteLeveling(PI) end<-----

 1140 12:21:21.351010  

 1141 12:21:21.351102  ==

 1142 12:21:21.354398  Dram Type= 6, Freq= 0, CH_0, rank 1

 1143 12:21:21.361104  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1144 12:21:21.361234  ==

 1145 12:21:21.361332  [Gating] SW mode calibration

 1146 12:21:21.370905  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1147 12:21:21.374293  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1148 12:21:21.377659   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1149 12:21:21.384639   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1150 12:21:21.387512   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1151 12:21:21.390825   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1152 12:21:21.397823   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1153 12:21:21.401012   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1154 12:21:21.404441   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1155 12:21:21.411053   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1156 12:21:21.414203   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1157 12:21:21.417642   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1158 12:21:21.424376   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1159 12:21:21.427848   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1160 12:21:21.430984   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1161 12:21:21.437621   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1162 12:21:21.440970   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1163 12:21:21.444128   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1164 12:21:21.488303   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1165 12:21:21.488806   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1166 12:21:21.489517   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1167 12:21:21.489627   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1168 12:21:21.489917   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1169 12:21:21.490018   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1170 12:21:21.490455   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1171 12:21:21.490755   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1172 12:21:21.490859   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1173 12:21:21.490968   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1174 12:21:21.532607   0  9  8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)

 1175 12:21:21.533015   0  9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 1176 12:21:21.533463   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1177 12:21:21.533572   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1178 12:21:21.534066   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1179 12:21:21.534662   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1180 12:21:21.535227   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1181 12:21:21.535837   0 10  4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 1182 12:21:21.535944   0 10  8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)

 1183 12:21:21.536555   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1184 12:21:21.576971   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1185 12:21:21.577370   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1186 12:21:21.577486   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1187 12:21:21.577580   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1188 12:21:21.577686   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1189 12:21:21.577780   0 11  4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 1190 12:21:21.578069   0 11  8 | B1->B0 | 3535 3b3b | 0 0 | (0 0) (0 0)

 1191 12:21:21.578169   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1192 12:21:21.578260   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1193 12:21:21.578365   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1194 12:21:21.581180   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1195 12:21:21.584769   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1196 12:21:21.591087   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1197 12:21:21.594392   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1198 12:21:21.597777   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1199 12:21:21.605140   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1200 12:21:21.608860   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1201 12:21:21.612598   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1202 12:21:21.616075   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1203 12:21:21.619438   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1204 12:21:21.626228   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1205 12:21:21.629989   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1206 12:21:21.633571   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1207 12:21:21.636911   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1208 12:21:21.643725   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1209 12:21:21.647160   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1210 12:21:21.649875   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1211 12:21:21.656520   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1212 12:21:21.660092   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1213 12:21:21.663439   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1214 12:21:21.670046   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1215 12:21:21.673327   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1216 12:21:21.676989  Total UI for P1: 0, mck2ui 16

 1217 12:21:21.680351  best dqsien dly found for B0: ( 0, 14,  6)

 1218 12:21:21.683368  Total UI for P1: 0, mck2ui 16

 1219 12:21:21.686725  best dqsien dly found for B1: ( 0, 14, 10)

 1220 12:21:21.690170  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1221 12:21:21.693043  best DQS1 dly(MCK, UI, PI) = (0, 14, 10)

 1222 12:21:21.693157  

 1223 12:21:21.696711  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1224 12:21:21.699997  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)

 1225 12:21:21.703351  [Gating] SW calibration Done

 1226 12:21:21.703474  ==

 1227 12:21:21.706451  Dram Type= 6, Freq= 0, CH_0, rank 1

 1228 12:21:21.709723  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1229 12:21:21.713262  ==

 1230 12:21:21.713379  RX Vref Scan: 0

 1231 12:21:21.713476  

 1232 12:21:21.716915  RX Vref 0 -> 0, step: 1

 1233 12:21:21.717026  

 1234 12:21:21.720014  RX Delay -130 -> 252, step: 16

 1235 12:21:21.723588  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1236 12:21:21.726794  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

 1237 12:21:21.729899  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1238 12:21:21.733319  iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256

 1239 12:21:21.736723  iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256

 1240 12:21:21.743678  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

 1241 12:21:21.747293  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

 1242 12:21:21.749961  iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256

 1243 12:21:21.753900  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

 1244 12:21:21.757183  iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240

 1245 12:21:21.763450  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

 1246 12:21:21.766898  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1247 12:21:21.770236  iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256

 1248 12:21:21.773714  iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256

 1249 12:21:21.776902  iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256

 1250 12:21:21.783829  iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256

 1251 12:21:21.783968  ==

 1252 12:21:21.787316  Dram Type= 6, Freq= 0, CH_0, rank 1

 1253 12:21:21.790617  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1254 12:21:21.790734  ==

 1255 12:21:21.790827  DQS Delay:

 1256 12:21:21.793962  DQS0 = 0, DQS1 = 0

 1257 12:21:21.794074  DQM Delay:

 1258 12:21:21.796922  DQM0 = 81, DQM1 = 71

 1259 12:21:21.797034  DQ Delay:

 1260 12:21:21.800273  DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77

 1261 12:21:21.803434  DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93

 1262 12:21:21.807004  DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69

 1263 12:21:21.810532  DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77

 1264 12:21:21.810651  

 1265 12:21:21.810747  

 1266 12:21:21.810838  ==

 1267 12:21:21.813319  Dram Type= 6, Freq= 0, CH_0, rank 1

 1268 12:21:21.816880  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1269 12:21:21.816995  ==

 1270 12:21:21.820153  

 1271 12:21:21.820264  

 1272 12:21:21.820358  	TX Vref Scan disable

 1273 12:21:21.823345   == TX Byte 0 ==

 1274 12:21:21.826870  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

 1275 12:21:21.830207  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

 1276 12:21:21.833451   == TX Byte 1 ==

 1277 12:21:21.836588  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1278 12:21:21.840274  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1279 12:21:21.840404  ==

 1280 12:21:21.843346  Dram Type= 6, Freq= 0, CH_0, rank 1

 1281 12:21:21.850304  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1282 12:21:21.850448  ==

 1283 12:21:21.862253  TX Vref=22, minBit 2, minWin=26, winSum=434

 1284 12:21:21.866019  TX Vref=24, minBit 1, minWin=27, winSum=439

 1285 12:21:21.869465  TX Vref=26, minBit 11, minWin=26, winSum=441

 1286 12:21:21.872434  TX Vref=28, minBit 1, minWin=27, winSum=444

 1287 12:21:21.875686  TX Vref=30, minBit 2, minWin=27, winSum=441

 1288 12:21:21.879374  TX Vref=32, minBit 9, minWin=27, winSum=442

 1289 12:21:21.885604  [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 28

 1290 12:21:21.885747  

 1291 12:21:21.888909  Final TX Range 1 Vref 28

 1292 12:21:21.889026  

 1293 12:21:21.889122  ==

 1294 12:21:21.892439  Dram Type= 6, Freq= 0, CH_0, rank 1

 1295 12:21:21.895850  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1296 12:21:21.895971  ==

 1297 12:21:21.896069  

 1298 12:21:21.899071  

 1299 12:21:21.899181  	TX Vref Scan disable

 1300 12:21:21.902396   == TX Byte 0 ==

 1301 12:21:21.905634  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

 1302 12:21:21.909202  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

 1303 12:21:21.912826   == TX Byte 1 ==

 1304 12:21:21.915672  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1305 12:21:21.919148  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1306 12:21:21.922777  

 1307 12:21:21.922917  [DATLAT]

 1308 12:21:21.923012  Freq=800, CH0 RK1

 1309 12:21:21.923115  

 1310 12:21:21.926031  DATLAT Default: 0xa

 1311 12:21:21.926137  0, 0xFFFF, sum = 0

 1312 12:21:21.929440  1, 0xFFFF, sum = 0

 1313 12:21:21.929554  2, 0xFFFF, sum = 0

 1314 12:21:21.932462  3, 0xFFFF, sum = 0

 1315 12:21:21.932586  4, 0xFFFF, sum = 0

 1316 12:21:21.936152  5, 0xFFFF, sum = 0

 1317 12:21:21.939447  6, 0xFFFF, sum = 0

 1318 12:21:21.939568  7, 0xFFFF, sum = 0

 1319 12:21:21.942441  8, 0xFFFF, sum = 0

 1320 12:21:21.942574  9, 0x0, sum = 1

 1321 12:21:21.942684  10, 0x0, sum = 2

 1322 12:21:21.945998  11, 0x0, sum = 3

 1323 12:21:21.946116  12, 0x0, sum = 4

 1324 12:21:21.949258  best_step = 10

 1325 12:21:21.949378  

 1326 12:21:21.949474  ==

 1327 12:21:21.952522  Dram Type= 6, Freq= 0, CH_0, rank 1

 1328 12:21:21.955857  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1329 12:21:21.955975  ==

 1330 12:21:21.959493  RX Vref Scan: 0

 1331 12:21:21.959609  

 1332 12:21:21.959703  RX Vref 0 -> 0, step: 1

 1333 12:21:21.959795  

 1334 12:21:21.962963  RX Delay -111 -> 252, step: 8

 1335 12:21:21.969673  iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232

 1336 12:21:21.972372  iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232

 1337 12:21:21.975759  iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232

 1338 12:21:21.979649  iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240

 1339 12:21:21.982645  iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240

 1340 12:21:21.988959  iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240

 1341 12:21:21.992206  iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232

 1342 12:21:21.995815  iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232

 1343 12:21:21.999496  iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240

 1344 12:21:22.002256  iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240

 1345 12:21:22.009029  iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240

 1346 12:21:22.012434  iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240

 1347 12:21:22.015605  iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240

 1348 12:21:22.019071  iDelay=209, Bit 13, Center 72 (-47 ~ 192) 240

 1349 12:21:22.025986  iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240

 1350 12:21:22.028874  iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240

 1351 12:21:22.028970  ==

 1352 12:21:22.032307  Dram Type= 6, Freq= 0, CH_0, rank 1

 1353 12:21:22.035972  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1354 12:21:22.036061  ==

 1355 12:21:22.036129  DQS Delay:

 1356 12:21:22.039146  DQS0 = 0, DQS1 = 0

 1357 12:21:22.039235  DQM Delay:

 1358 12:21:22.043077  DQM0 = 79, DQM1 = 70

 1359 12:21:22.043192  DQ Delay:

 1360 12:21:22.045706  DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72

 1361 12:21:22.048996  DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =92

 1362 12:21:22.052497  DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64

 1363 12:21:22.055889  DQ12 =72, DQ13 =72, DQ14 =80, DQ15 =80

 1364 12:21:22.056029  

 1365 12:21:22.056121  

 1366 12:21:22.065803  [DQSOSCAuto] RK1, (LSB)MR18= 0x4a26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps

 1367 12:21:22.065968  CH0 RK1: MR19=606, MR18=4A26

 1368 12:21:22.072449  CH0_RK1: MR19=0x606, MR18=0x4A26, DQSOSC=391, MR23=63, INC=96, DEC=64

 1369 12:21:22.075654  [RxdqsGatingPostProcess] freq 800

 1370 12:21:22.082355  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1371 12:21:22.085801  Pre-setting of DQS Precalculation

 1372 12:21:22.089044  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1373 12:21:22.089154  ==

 1374 12:21:22.092563  Dram Type= 6, Freq= 0, CH_1, rank 0

 1375 12:21:22.095864  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1376 12:21:22.099206  ==

 1377 12:21:22.102424  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1378 12:21:22.109554  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1379 12:21:22.117709  [CA 0] Center 36 (6~66) winsize 61

 1380 12:21:22.120816  [CA 1] Center 36 (6~67) winsize 62

 1381 12:21:22.124302  [CA 2] Center 34 (4~64) winsize 61

 1382 12:21:22.127759  [CA 3] Center 33 (3~64) winsize 62

 1383 12:21:22.131158  [CA 4] Center 34 (4~64) winsize 61

 1384 12:21:22.134246  [CA 5] Center 33 (3~64) winsize 62

 1385 12:21:22.134358  

 1386 12:21:22.137781  [CmdBusTrainingLP45] Vref(ca) range 1: 32

 1387 12:21:22.137890  

 1388 12:21:22.141412  [CATrainingPosCal] consider 1 rank data

 1389 12:21:22.144089  u2DelayCellTimex100 = 270/100 ps

 1390 12:21:22.147519  CA0 delay=36 (6~66),Diff = 3 PI (21 cell)

 1391 12:21:22.151235  CA1 delay=36 (6~67),Diff = 3 PI (21 cell)

 1392 12:21:22.157983  CA2 delay=34 (4~64),Diff = 1 PI (7 cell)

 1393 12:21:22.160835  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 1394 12:21:22.164398  CA4 delay=34 (4~64),Diff = 1 PI (7 cell)

 1395 12:21:22.167915  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1396 12:21:22.168041  

 1397 12:21:22.170906  CA PerBit enable=1, Macro0, CA PI delay=33

 1398 12:21:22.171028  

 1399 12:21:22.174324  [CBTSetCACLKResult] CA Dly = 33

 1400 12:21:22.174437  CS Dly: 5 (0~36)

 1401 12:21:22.174531  ==

 1402 12:21:22.177796  Dram Type= 6, Freq= 0, CH_1, rank 1

 1403 12:21:22.184434  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1404 12:21:22.184595  ==

 1405 12:21:22.187604  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1406 12:21:22.194509  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1407 12:21:22.203734  [CA 0] Center 37 (7~67) winsize 61

 1408 12:21:22.206950  [CA 1] Center 36 (6~67) winsize 62

 1409 12:21:22.210288  [CA 2] Center 34 (4~65) winsize 62

 1410 12:21:22.213769  [CA 3] Center 34 (4~64) winsize 61

 1411 12:21:22.217178  [CA 4] Center 34 (4~65) winsize 62

 1412 12:21:22.220185  [CA 5] Center 33 (3~64) winsize 62

 1413 12:21:22.220284  

 1414 12:21:22.223674  [CmdBusTrainingLP45] Vref(ca) range 1: 32

 1415 12:21:22.223760  

 1416 12:21:22.226785  [CATrainingPosCal] consider 2 rank data

 1417 12:21:22.230456  u2DelayCellTimex100 = 270/100 ps

 1418 12:21:22.233394  CA0 delay=36 (7~66),Diff = 3 PI (21 cell)

 1419 12:21:22.237097  CA1 delay=36 (6~67),Diff = 3 PI (21 cell)

 1420 12:21:22.244259  CA2 delay=34 (4~64),Diff = 1 PI (7 cell)

 1421 12:21:22.247288  CA3 delay=34 (4~64),Diff = 1 PI (7 cell)

 1422 12:21:22.250286  CA4 delay=34 (4~64),Diff = 1 PI (7 cell)

 1423 12:21:22.253803  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1424 12:21:22.253974  

 1425 12:21:22.257365  CA PerBit enable=1, Macro0, CA PI delay=33

 1426 12:21:22.257572  

 1427 12:21:22.260839  [CBTSetCACLKResult] CA Dly = 33

 1428 12:21:22.261027  CS Dly: 6 (0~38)

 1429 12:21:22.261178  

 1430 12:21:22.264387  ----->DramcWriteLeveling(PI) begin...

 1431 12:21:22.264519  ==

 1432 12:21:22.267880  Dram Type= 6, Freq= 0, CH_1, rank 0

 1433 12:21:22.271754  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1434 12:21:22.271874  ==

 1435 12:21:22.275321  Write leveling (Byte 0): 27 => 27

 1436 12:21:22.279044  Write leveling (Byte 1): 31 => 31

 1437 12:21:22.282595  DramcWriteLeveling(PI) end<-----

 1438 12:21:22.282774  

 1439 12:21:22.282923  ==

 1440 12:21:22.286341  Dram Type= 6, Freq= 0, CH_1, rank 0

 1441 12:21:22.289972  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1442 12:21:22.290141  ==

 1443 12:21:22.293376  [Gating] SW mode calibration

 1444 12:21:22.301804  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1445 12:21:22.303960  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1446 12:21:22.310528   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1447 12:21:22.313803   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1448 12:21:22.316838   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1449 12:21:22.323772   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1450 12:21:22.326718   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1451 12:21:22.330220   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1452 12:21:22.337341   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1453 12:21:22.340337   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1454 12:21:22.343314   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1455 12:21:22.350029   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1456 12:21:22.353653   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1457 12:21:22.356742   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1458 12:21:22.363635   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1459 12:21:22.366987   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1460 12:21:22.370056   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1461 12:21:22.376766   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1462 12:21:22.380366   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1463 12:21:22.383325   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1464 12:21:22.389966   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1465 12:21:22.393528   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1466 12:21:22.397096   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1467 12:21:22.399910   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1468 12:21:22.406704   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1469 12:21:22.410225   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1470 12:21:22.413245   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1471 12:21:22.420013   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1472 12:21:22.423252   0  9  8 | B1->B0 | 2a2a 2929 | 1 0 | (1 1) (0 0)

 1473 12:21:22.426678   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1474 12:21:22.433275   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1475 12:21:22.436611   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1476 12:21:22.439963   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1477 12:21:22.446574   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1478 12:21:22.450202   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1479 12:21:22.453362   0 10  4 | B1->B0 | 3333 3232 | 0 1 | (0 0) (0 0)

 1480 12:21:22.459940   0 10  8 | B1->B0 | 2323 2626 | 0 0 | (1 0) (1 1)

 1481 12:21:22.463410   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1482 12:21:22.466991   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1483 12:21:22.473618   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1484 12:21:22.476560   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1485 12:21:22.479964   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1486 12:21:22.486802   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1487 12:21:22.490326   0 11  4 | B1->B0 | 2a29 2929 | 1 0 | (0 0) (1 1)

 1488 12:21:22.493318   0 11  8 | B1->B0 | 3a3a 3736 | 0 1 | (0 0) (0 0)

 1489 12:21:22.499977   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1490 12:21:22.503305   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1491 12:21:22.506775   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1492 12:21:22.510382   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1493 12:21:22.516672   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1494 12:21:22.519840   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1495 12:21:22.523495   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1496 12:21:22.529712   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1497 12:21:22.533131   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1498 12:21:22.536431   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1499 12:21:22.543234   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1500 12:21:22.546697   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1501 12:21:22.550060   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1502 12:21:22.556453   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1503 12:21:22.560106   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1504 12:21:22.563052   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1505 12:21:22.569679   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1506 12:21:22.573395   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1507 12:21:22.576692   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1508 12:21:22.583076   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1509 12:21:22.586707   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1510 12:21:22.589949   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1511 12:21:22.596352   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1512 12:21:22.599878   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1513 12:21:22.603514   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1514 12:21:22.606477  Total UI for P1: 0, mck2ui 16

 1515 12:21:22.610100  best dqsien dly found for B0: ( 0, 14,  8)

 1516 12:21:22.613409  Total UI for P1: 0, mck2ui 16

 1517 12:21:22.616485  best dqsien dly found for B1: ( 0, 14,  8)

 1518 12:21:22.619969  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1519 12:21:22.623455  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1520 12:21:22.623570  

 1521 12:21:22.626450  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1522 12:21:22.630016  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1523 12:21:22.633037  [Gating] SW calibration Done

 1524 12:21:22.633119  ==

 1525 12:21:22.636446  Dram Type= 6, Freq= 0, CH_1, rank 0

 1526 12:21:22.643329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1527 12:21:22.643444  ==

 1528 12:21:22.643513  RX Vref Scan: 0

 1529 12:21:22.643591  

 1530 12:21:22.646571  RX Vref 0 -> 0, step: 1

 1531 12:21:22.646653  

 1532 12:21:22.650160  RX Delay -130 -> 252, step: 16

 1533 12:21:22.653057  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1534 12:21:22.656324  iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256

 1535 12:21:22.660089  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1536 12:21:22.662918  iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256

 1537 12:21:22.669925  iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256

 1538 12:21:22.673577  iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256

 1539 12:21:22.676550  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

 1540 12:21:22.680315  iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256

 1541 12:21:22.682992  iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240

 1542 12:21:22.690073  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1543 12:21:22.693071  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

 1544 12:21:22.696471  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1545 12:21:22.699651  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1546 12:21:22.706758  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1547 12:21:22.709861  iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256

 1548 12:21:22.713214  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1549 12:21:22.713298  ==

 1550 12:21:22.716745  Dram Type= 6, Freq= 0, CH_1, rank 0

 1551 12:21:22.719767  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1552 12:21:22.719851  ==

 1553 12:21:22.722958  DQS Delay:

 1554 12:21:22.723041  DQS0 = 0, DQS1 = 0

 1555 12:21:22.723106  DQM Delay:

 1556 12:21:22.726238  DQM0 = 81, DQM1 = 74

 1557 12:21:22.726337  DQ Delay:

 1558 12:21:22.729930  DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77

 1559 12:21:22.732884  DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77

 1560 12:21:22.736518  DQ8 =53, DQ9 =69, DQ10 =69, DQ11 =69

 1561 12:21:22.739653  DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85

 1562 12:21:22.739736  

 1563 12:21:22.739801  

 1564 12:21:22.739860  ==

 1565 12:21:22.743014  Dram Type= 6, Freq= 0, CH_1, rank 0

 1566 12:21:22.749548  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1567 12:21:22.749683  ==

 1568 12:21:22.749779  

 1569 12:21:22.749854  

 1570 12:21:22.749913  	TX Vref Scan disable

 1571 12:21:22.753534   == TX Byte 0 ==

 1572 12:21:22.756446  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1573 12:21:22.759982  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1574 12:21:22.763544   == TX Byte 1 ==

 1575 12:21:22.767034  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1576 12:21:22.769781  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1577 12:21:22.773167  ==

 1578 12:21:22.776739  Dram Type= 6, Freq= 0, CH_1, rank 0

 1579 12:21:22.780300  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1580 12:21:22.780386  ==

 1581 12:21:22.792708  TX Vref=22, minBit 8, minWin=27, winSum=448

 1582 12:21:22.795916  TX Vref=24, minBit 8, minWin=27, winSum=450

 1583 12:21:22.799522  TX Vref=26, minBit 9, minWin=27, winSum=453

 1584 12:21:22.802600  TX Vref=28, minBit 1, minWin=28, winSum=457

 1585 12:21:22.806052  TX Vref=30, minBit 1, minWin=28, winSum=457

 1586 12:21:22.809453  TX Vref=32, minBit 8, minWin=27, winSum=456

 1587 12:21:22.816227  [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 28

 1588 12:21:22.816323  

 1589 12:21:22.819592  Final TX Range 1 Vref 28

 1590 12:21:22.819675  

 1591 12:21:22.819739  ==

 1592 12:21:22.823236  Dram Type= 6, Freq= 0, CH_1, rank 0

 1593 12:21:22.826339  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1594 12:21:22.826449  ==

 1595 12:21:22.826591  

 1596 12:21:22.826709  

 1597 12:21:22.829932  	TX Vref Scan disable

 1598 12:21:22.832792   == TX Byte 0 ==

 1599 12:21:22.836430  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1600 12:21:22.840035  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1601 12:21:22.843594   == TX Byte 1 ==

 1602 12:21:22.847089  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1603 12:21:22.850595  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1604 12:21:22.850686  

 1605 12:21:22.850780  [DATLAT]

 1606 12:21:22.853691  Freq=800, CH1 RK0

 1607 12:21:22.853774  

 1608 12:21:22.857136  DATLAT Default: 0xa

 1609 12:21:22.857212  0, 0xFFFF, sum = 0

 1610 12:21:22.860575  1, 0xFFFF, sum = 0

 1611 12:21:22.860678  2, 0xFFFF, sum = 0

 1612 12:21:22.864034  3, 0xFFFF, sum = 0

 1613 12:21:22.864112  4, 0xFFFF, sum = 0

 1614 12:21:22.867079  5, 0xFFFF, sum = 0

 1615 12:21:22.867180  6, 0xFFFF, sum = 0

 1616 12:21:22.870574  7, 0xFFFF, sum = 0

 1617 12:21:22.870675  8, 0x0, sum = 1

 1618 12:21:22.873684  9, 0x0, sum = 2

 1619 12:21:22.873761  10, 0x0, sum = 3

 1620 12:21:22.873845  11, 0x0, sum = 4

 1621 12:21:22.877326  best_step = 9

 1622 12:21:22.877399  

 1623 12:21:22.877459  ==

 1624 12:21:22.880310  Dram Type= 6, Freq= 0, CH_1, rank 0

 1625 12:21:22.884059  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1626 12:21:22.884136  ==

 1627 12:21:22.887293  RX Vref Scan: 1

 1628 12:21:22.887364  

 1629 12:21:22.887449  Set Vref Range= 32 -> 127

 1630 12:21:22.890815  

 1631 12:21:22.890887  RX Vref 32 -> 127, step: 1

 1632 12:21:22.890947  

 1633 12:21:22.893648  RX Delay -111 -> 252, step: 8

 1634 12:21:22.893716  

 1635 12:21:22.897107  Set Vref, RX VrefLevel [Byte0]: 32

 1636 12:21:22.900662                           [Byte1]: 32

 1637 12:21:22.900743  

 1638 12:21:22.903791  Set Vref, RX VrefLevel [Byte0]: 33

 1639 12:21:22.907303                           [Byte1]: 33

 1640 12:21:22.911551  

 1641 12:21:22.911632  Set Vref, RX VrefLevel [Byte0]: 34

 1642 12:21:22.914460                           [Byte1]: 34

 1643 12:21:22.918786  

 1644 12:21:22.918867  Set Vref, RX VrefLevel [Byte0]: 35

 1645 12:21:22.922158                           [Byte1]: 35

 1646 12:21:22.926934  

 1647 12:21:22.927016  Set Vref, RX VrefLevel [Byte0]: 36

 1648 12:21:22.929908                           [Byte1]: 36

 1649 12:21:22.934620  

 1650 12:21:22.934706  Set Vref, RX VrefLevel [Byte0]: 37

 1651 12:21:22.937491                           [Byte1]: 37

 1652 12:21:22.941712  

 1653 12:21:22.941817  Set Vref, RX VrefLevel [Byte0]: 38

 1654 12:21:22.945426                           [Byte1]: 38

 1655 12:21:22.949474  

 1656 12:21:22.949610  Set Vref, RX VrefLevel [Byte0]: 39

 1657 12:21:22.953003                           [Byte1]: 39

 1658 12:21:22.957016  

 1659 12:21:22.957099  Set Vref, RX VrefLevel [Byte0]: 40

 1660 12:21:22.960506                           [Byte1]: 40

 1661 12:21:22.964700  

 1662 12:21:22.964784  Set Vref, RX VrefLevel [Byte0]: 41

 1663 12:21:22.968220                           [Byte1]: 41

 1664 12:21:22.972272  

 1665 12:21:22.972356  Set Vref, RX VrefLevel [Byte0]: 42

 1666 12:21:22.975767                           [Byte1]: 42

 1667 12:21:22.980040  

 1668 12:21:22.980153  Set Vref, RX VrefLevel [Byte0]: 43

 1669 12:21:22.983179                           [Byte1]: 43

 1670 12:21:22.987834  

 1671 12:21:22.987917  Set Vref, RX VrefLevel [Byte0]: 44

 1672 12:21:22.990908                           [Byte1]: 44

 1673 12:21:22.995178  

 1674 12:21:22.995265  Set Vref, RX VrefLevel [Byte0]: 45

 1675 12:21:22.998576                           [Byte1]: 45

 1676 12:21:23.002998  

 1677 12:21:23.003080  Set Vref, RX VrefLevel [Byte0]: 46

 1678 12:21:23.006469                           [Byte1]: 46

 1679 12:21:23.010763  

 1680 12:21:23.010845  Set Vref, RX VrefLevel [Byte0]: 47

 1681 12:21:23.014306                           [Byte1]: 47

 1682 12:21:23.018593  

 1683 12:21:23.018674  Set Vref, RX VrefLevel [Byte0]: 48

 1684 12:21:23.021572                           [Byte1]: 48

 1685 12:21:23.025908  

 1686 12:21:23.025990  Set Vref, RX VrefLevel [Byte0]: 49

 1687 12:21:23.029139                           [Byte1]: 49

 1688 12:21:23.033475  

 1689 12:21:23.033557  Set Vref, RX VrefLevel [Byte0]: 50

 1690 12:21:23.037003                           [Byte1]: 50

 1691 12:21:23.041668  

 1692 12:21:23.041750  Set Vref, RX VrefLevel [Byte0]: 51

 1693 12:21:23.044746                           [Byte1]: 51

 1694 12:21:23.049129  

 1695 12:21:23.049210  Set Vref, RX VrefLevel [Byte0]: 52

 1696 12:21:23.052192                           [Byte1]: 52

 1697 12:21:23.056546  

 1698 12:21:23.056628  Set Vref, RX VrefLevel [Byte0]: 53

 1699 12:21:23.060089                           [Byte1]: 53

 1700 12:21:23.064148  

 1701 12:21:23.064247  Set Vref, RX VrefLevel [Byte0]: 54

 1702 12:21:23.067752                           [Byte1]: 54

 1703 12:21:23.071979  

 1704 12:21:23.072060  Set Vref, RX VrefLevel [Byte0]: 55

 1705 12:21:23.074945                           [Byte1]: 55

 1706 12:21:23.079341  

 1707 12:21:23.079456  Set Vref, RX VrefLevel [Byte0]: 56

 1708 12:21:23.083123                           [Byte1]: 56

 1709 12:21:23.087335  

 1710 12:21:23.087439  Set Vref, RX VrefLevel [Byte0]: 57

 1711 12:21:23.090353                           [Byte1]: 57

 1712 12:21:23.094633  

 1713 12:21:23.094714  Set Vref, RX VrefLevel [Byte0]: 58

 1714 12:21:23.098114                           [Byte1]: 58

 1715 12:21:23.102850  

 1716 12:21:23.102930  Set Vref, RX VrefLevel [Byte0]: 59

 1717 12:21:23.105863                           [Byte1]: 59

 1718 12:21:23.110166  

 1719 12:21:23.110276  Set Vref, RX VrefLevel [Byte0]: 60

 1720 12:21:23.113270                           [Byte1]: 60

 1721 12:21:23.117843  

 1722 12:21:23.117925  Set Vref, RX VrefLevel [Byte0]: 61

 1723 12:21:23.121078                           [Byte1]: 61

 1724 12:21:23.125133  

 1725 12:21:23.125217  Set Vref, RX VrefLevel [Byte0]: 62

 1726 12:21:23.128712                           [Byte1]: 62

 1727 12:21:23.132850  

 1728 12:21:23.132934  Set Vref, RX VrefLevel [Byte0]: 63

 1729 12:21:23.136232                           [Byte1]: 63

 1730 12:21:23.140422  

 1731 12:21:23.140500  Set Vref, RX VrefLevel [Byte0]: 64

 1732 12:21:23.143932                           [Byte1]: 64

 1733 12:21:23.148363  

 1734 12:21:23.148443  Set Vref, RX VrefLevel [Byte0]: 65

 1735 12:21:23.151942                           [Byte1]: 65

 1736 12:21:23.156206  

 1737 12:21:23.156293  Set Vref, RX VrefLevel [Byte0]: 66

 1738 12:21:23.159101                           [Byte1]: 66

 1739 12:21:23.163839  

 1740 12:21:23.163934  Set Vref, RX VrefLevel [Byte0]: 67

 1741 12:21:23.166705                           [Byte1]: 67

 1742 12:21:23.171338  

 1743 12:21:23.171468  Set Vref, RX VrefLevel [Byte0]: 68

 1744 12:21:23.174277                           [Byte1]: 68

 1745 12:21:23.178895  

 1746 12:21:23.179004  Set Vref, RX VrefLevel [Byte0]: 69

 1747 12:21:23.181964                           [Byte1]: 69

 1748 12:21:23.186736  

 1749 12:21:23.186817  Set Vref, RX VrefLevel [Byte0]: 70

 1750 12:21:23.189889                           [Byte1]: 70

 1751 12:21:23.194145  

 1752 12:21:23.194226  Set Vref, RX VrefLevel [Byte0]: 71

 1753 12:21:23.197705                           [Byte1]: 71

 1754 12:21:23.201818  

 1755 12:21:23.201900  Set Vref, RX VrefLevel [Byte0]: 72

 1756 12:21:23.205394                           [Byte1]: 72

 1757 12:21:23.209626  

 1758 12:21:23.209711  Set Vref, RX VrefLevel [Byte0]: 73

 1759 12:21:23.212679                           [Byte1]: 73

 1760 12:21:23.217069  

 1761 12:21:23.217150  Set Vref, RX VrefLevel [Byte0]: 74

 1762 12:21:23.220745                           [Byte1]: 74

 1763 12:21:23.225012  

 1764 12:21:23.225094  Final RX Vref Byte 0 = 53 to rank0

 1765 12:21:23.228562  Final RX Vref Byte 1 = 56 to rank0

 1766 12:21:23.231530  Final RX Vref Byte 0 = 53 to rank1

 1767 12:21:23.234609  Final RX Vref Byte 1 = 56 to rank1==

 1768 12:21:23.238238  Dram Type= 6, Freq= 0, CH_1, rank 0

 1769 12:21:23.244967  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1770 12:21:23.245054  ==

 1771 12:21:23.245120  DQS Delay:

 1772 12:21:23.245180  DQS0 = 0, DQS1 = 0

 1773 12:21:23.248208  DQM Delay:

 1774 12:21:23.248290  DQM0 = 80, DQM1 = 71

 1775 12:21:23.251544  DQ Delay:

 1776 12:21:23.254814  DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76

 1777 12:21:23.254897  DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76

 1778 12:21:23.258120  DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64

 1779 12:21:23.261362  DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =80

 1780 12:21:23.264958  

 1781 12:21:23.265043  

 1782 12:21:23.271725  [DQSOSCAuto] RK0, (LSB)MR18= 0xd18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps

 1783 12:21:23.274587  CH1 RK0: MR19=606, MR18=D18

 1784 12:21:23.281296  CH1_RK0: MR19=0x606, MR18=0xD18, DQSOSC=403, MR23=63, INC=90, DEC=60

 1785 12:21:23.281406  

 1786 12:21:23.284998  ----->DramcWriteLeveling(PI) begin...

 1787 12:21:23.285081  ==

 1788 12:21:23.287852  Dram Type= 6, Freq= 0, CH_1, rank 1

 1789 12:21:23.291224  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1790 12:21:23.291345  ==

 1791 12:21:23.294898  Write leveling (Byte 0): 27 => 27

 1792 12:21:23.298085  Write leveling (Byte 1): 31 => 31

 1793 12:21:23.301210  DramcWriteLeveling(PI) end<-----

 1794 12:21:23.301292  

 1795 12:21:23.301356  ==

 1796 12:21:23.304825  Dram Type= 6, Freq= 0, CH_1, rank 1

 1797 12:21:23.308381  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1798 12:21:23.308520  ==

 1799 12:21:23.311477  [Gating] SW mode calibration

 1800 12:21:23.318036  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1801 12:21:23.325111  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1802 12:21:23.328007   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1803 12:21:23.331148   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1804 12:21:23.338241   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1805 12:21:23.341575   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1806 12:21:23.344500   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1807 12:21:23.351267   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1808 12:21:23.354910   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1809 12:21:23.357733   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1810 12:21:23.361678   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1811 12:21:23.367778   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1812 12:21:23.371408   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1813 12:21:23.374740   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1814 12:21:23.381065   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1815 12:21:23.384590   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1816 12:21:23.387893   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1817 12:21:23.394405   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1818 12:21:23.397908   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1819 12:21:23.401052   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1820 12:21:23.408238   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1821 12:21:23.411262   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1822 12:21:23.414891   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1823 12:21:23.421056   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1824 12:21:23.424711   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1825 12:21:23.427685   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1826 12:21:23.434843   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1827 12:21:23.437589   0  9  4 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)

 1828 12:21:23.441265   0  9  8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 1829 12:21:23.448448   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1830 12:21:23.451059   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1831 12:21:23.454963   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1832 12:21:23.461059   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1833 12:21:23.464657   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1834 12:21:23.468191   0 10  0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 1835 12:21:23.474643   0 10  4 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 1)

 1836 12:21:23.477900   0 10  8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)

 1837 12:21:23.481272   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1838 12:21:23.484973   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1839 12:21:23.491515   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1840 12:21:23.494689   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1841 12:21:23.498162   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1842 12:21:23.504416   0 11  0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 1843 12:21:23.507904   0 11  4 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (1 1)

 1844 12:21:23.511367   0 11  8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

 1845 12:21:23.517616   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1846 12:21:23.521202   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1847 12:21:23.524795   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1848 12:21:23.531301   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1849 12:21:23.534468   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1850 12:21:23.538201   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1851 12:21:23.544669   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1852 12:21:23.547711   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1853 12:21:23.551304   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1854 12:21:23.557953   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1855 12:21:23.561304   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1856 12:21:23.564396   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1857 12:21:23.571303   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1858 12:21:23.574194   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1859 12:21:23.578000   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1860 12:21:23.581111   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1861 12:21:23.587863   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1862 12:21:23.591300   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1863 12:21:23.594268   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1864 12:21:23.600989   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1865 12:21:23.604379   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1866 12:21:23.607564   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1867 12:21:23.614209   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1868 12:21:23.617792   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1869 12:21:23.621179  Total UI for P1: 0, mck2ui 16

 1870 12:21:23.624279  best dqsien dly found for B0: ( 0, 14,  6)

 1871 12:21:23.627875  Total UI for P1: 0, mck2ui 16

 1872 12:21:23.630835  best dqsien dly found for B1: ( 0, 14,  6)

 1873 12:21:23.634482  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1874 12:21:23.637573  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1875 12:21:23.637654  

 1876 12:21:23.641213  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1877 12:21:23.644082  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1878 12:21:23.647655  [Gating] SW calibration Done

 1879 12:21:23.647737  ==

 1880 12:21:23.650718  Dram Type= 6, Freq= 0, CH_1, rank 1

 1881 12:21:23.654349  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1882 12:21:23.657447  ==

 1883 12:21:23.657528  RX Vref Scan: 0

 1884 12:21:23.657591  

 1885 12:21:23.661028  RX Vref 0 -> 0, step: 1

 1886 12:21:23.661108  

 1887 12:21:23.664190  RX Delay -130 -> 252, step: 16

 1888 12:21:23.667398  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1889 12:21:23.670815  iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240

 1890 12:21:23.674271  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1891 12:21:23.677661  iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256

 1892 12:21:23.684526  iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256

 1893 12:21:23.687981  iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256

 1894 12:21:23.690901  iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240

 1895 12:21:23.694516  iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256

 1896 12:21:23.697990  iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256

 1897 12:21:23.701106  iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256

 1898 12:21:23.707739  iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256

 1899 12:21:23.711391  iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256

 1900 12:21:23.714272  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1901 12:21:23.717836  iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256

 1902 12:21:23.724393  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1903 12:21:23.727888  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1904 12:21:23.728001  ==

 1905 12:21:23.731018  Dram Type= 6, Freq= 0, CH_1, rank 1

 1906 12:21:23.734557  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1907 12:21:23.734644  ==

 1908 12:21:23.734747  DQS Delay:

 1909 12:21:23.737565  DQS0 = 0, DQS1 = 0

 1910 12:21:23.737670  DQM Delay:

 1911 12:21:23.741211  DQM0 = 79, DQM1 = 74

 1912 12:21:23.741320  DQ Delay:

 1913 12:21:23.744255  DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77

 1914 12:21:23.747823  DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77

 1915 12:21:23.750771  DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61

 1916 12:21:23.754431  DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85

 1917 12:21:23.754589  

 1918 12:21:23.754668  

 1919 12:21:23.754728  ==

 1920 12:21:23.757756  Dram Type= 6, Freq= 0, CH_1, rank 1

 1921 12:21:23.760913  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1922 12:21:23.764628  ==

 1923 12:21:23.764729  

 1924 12:21:23.764819  

 1925 12:21:23.764904  	TX Vref Scan disable

 1926 12:21:23.767673   == TX Byte 0 ==

 1927 12:21:23.770847  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1928 12:21:23.774665  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1929 12:21:23.777740   == TX Byte 1 ==

 1930 12:21:23.780814  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1931 12:21:23.784349  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1932 12:21:23.787451  ==

 1933 12:21:23.787526  Dram Type= 6, Freq= 0, CH_1, rank 1

 1934 12:21:23.794175  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1935 12:21:23.794291  ==

 1936 12:21:23.806387  TX Vref=22, minBit 9, minWin=27, winSum=449

 1937 12:21:23.809717  TX Vref=24, minBit 3, minWin=28, winSum=456

 1938 12:21:23.813274  TX Vref=26, minBit 3, minWin=28, winSum=456

 1939 12:21:23.817008  TX Vref=28, minBit 3, minWin=28, winSum=458

 1940 12:21:23.819919  TX Vref=30, minBit 8, minWin=28, winSum=462

 1941 12:21:23.823506  TX Vref=32, minBit 8, minWin=28, winSum=458

 1942 12:21:23.830239  [TxChooseVref] Worse bit 8, Min win 28, Win sum 462, Final Vref 30

 1943 12:21:23.830327  

 1944 12:21:23.832960  Final TX Range 1 Vref 30

 1945 12:21:23.833039  

 1946 12:21:23.833101  ==

 1947 12:21:23.836376  Dram Type= 6, Freq= 0, CH_1, rank 1

 1948 12:21:23.840087  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1949 12:21:23.840173  ==

 1950 12:21:23.840239  

 1951 12:21:23.840300  

 1952 12:21:23.843231  	TX Vref Scan disable

 1953 12:21:23.846631   == TX Byte 0 ==

 1954 12:21:23.850047  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1955 12:21:23.853485  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1956 12:21:23.856506   == TX Byte 1 ==

 1957 12:21:23.860016  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1958 12:21:23.863119  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1959 12:21:23.866727  

 1960 12:21:23.866817  [DATLAT]

 1961 12:21:23.866884  Freq=800, CH1 RK1

 1962 12:21:23.866945  

 1963 12:21:23.869737  DATLAT Default: 0x9

 1964 12:21:23.869842  0, 0xFFFF, sum = 0

 1965 12:21:23.873424  1, 0xFFFF, sum = 0

 1966 12:21:23.873509  2, 0xFFFF, sum = 0

 1967 12:21:23.876478  3, 0xFFFF, sum = 0

 1968 12:21:23.876567  4, 0xFFFF, sum = 0

 1969 12:21:23.880123  5, 0xFFFF, sum = 0

 1970 12:21:23.880242  6, 0xFFFF, sum = 0

 1971 12:21:23.883243  7, 0xFFFF, sum = 0

 1972 12:21:23.887035  8, 0xFFFF, sum = 0

 1973 12:21:23.887215  9, 0x0, sum = 1

 1974 12:21:23.887334  10, 0x0, sum = 2

 1975 12:21:23.889947  11, 0x0, sum = 3

 1976 12:21:23.890032  12, 0x0, sum = 4

 1977 12:21:23.893360  best_step = 10

 1978 12:21:23.893442  

 1979 12:21:23.893507  ==

 1980 12:21:23.896869  Dram Type= 6, Freq= 0, CH_1, rank 1

 1981 12:21:23.899749  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1982 12:21:23.899833  ==

 1983 12:21:23.903225  RX Vref Scan: 0

 1984 12:21:23.903347  

 1985 12:21:23.903458  RX Vref 0 -> 0, step: 1

 1986 12:21:23.903524  

 1987 12:21:23.906943  RX Delay -111 -> 252, step: 8

 1988 12:21:23.913614  iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240

 1989 12:21:23.916780  iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240

 1990 12:21:23.919739  iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240

 1991 12:21:23.923366  iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240

 1992 12:21:23.926596  iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248

 1993 12:21:23.933176  iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240

 1994 12:21:23.936401  iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240

 1995 12:21:23.940145  iDelay=209, Bit 7, Center 72 (-47 ~ 192) 240

 1996 12:21:23.943112  iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248

 1997 12:21:23.946726  iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240

 1998 12:21:23.953335  iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248

 1999 12:21:23.956443  iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240

 2000 12:21:23.959693  iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240

 2001 12:21:23.963634  iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240

 2002 12:21:23.966471  iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240

 2003 12:21:23.973423  iDelay=209, Bit 15, Center 76 (-47 ~ 200) 248

 2004 12:21:23.973511  ==

 2005 12:21:23.976462  Dram Type= 6, Freq= 0, CH_1, rank 1

 2006 12:21:23.980247  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2007 12:21:23.980391  ==

 2008 12:21:23.980496  DQS Delay:

 2009 12:21:23.983164  DQS0 = 0, DQS1 = 0

 2010 12:21:23.983284  DQM Delay:

 2011 12:21:23.986357  DQM0 = 76, DQM1 = 72

 2012 12:21:23.986466  DQ Delay:

 2013 12:21:23.990035  DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72

 2014 12:21:23.993562  DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =72

 2015 12:21:23.996543  DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64

 2016 12:21:24.000178  DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76

 2017 12:21:24.000262  

 2018 12:21:24.000328  

 2019 12:21:24.006501  [DQSOSCAuto] RK1, (LSB)MR18= 0x223a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps

 2020 12:21:24.009910  CH1 RK1: MR19=606, MR18=223A

 2021 12:21:24.016673  CH1_RK1: MR19=0x606, MR18=0x223A, DQSOSC=395, MR23=63, INC=94, DEC=63

 2022 12:21:24.019819  [RxdqsGatingPostProcess] freq 800

 2023 12:21:24.026814  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2024 12:21:24.029834  Pre-setting of DQS Precalculation

 2025 12:21:24.033192  [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10

 2026 12:21:24.040196  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2027 12:21:24.046699  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2028 12:21:24.046798  

 2029 12:21:24.046864  

 2030 12:21:24.050499  [Calibration Summary] 1600 Mbps

 2031 12:21:24.053346  CH 0, Rank 0

 2032 12:21:24.053456  SW Impedance     : PASS

 2033 12:21:24.057166  DUTY Scan        : NO K

 2034 12:21:24.059960  ZQ Calibration   : PASS

 2035 12:21:24.060043  Jitter Meter     : NO K

 2036 12:21:24.063300  CBT Training     : PASS

 2037 12:21:24.063415  Write leveling   : PASS

 2038 12:21:24.066862  RX DQS gating    : PASS

 2039 12:21:24.070371  RX DQ/DQS(RDDQC) : PASS

 2040 12:21:24.070461  TX DQ/DQS        : PASS

 2041 12:21:24.073660  RX DATLAT        : PASS

 2042 12:21:24.077121  RX DQ/DQS(Engine): PASS

 2043 12:21:24.077241  TX OE            : NO K

 2044 12:21:24.080249  All Pass.

 2045 12:21:24.080359  

 2046 12:21:24.080452  CH 0, Rank 1

 2047 12:21:24.083352  SW Impedance     : PASS

 2048 12:21:24.083470  DUTY Scan        : NO K

 2049 12:21:24.087130  ZQ Calibration   : PASS

 2050 12:21:24.090138  Jitter Meter     : NO K

 2051 12:21:24.090247  CBT Training     : PASS

 2052 12:21:24.093727  Write leveling   : PASS

 2053 12:21:24.096773  RX DQS gating    : PASS

 2054 12:21:24.096887  RX DQ/DQS(RDDQC) : PASS

 2055 12:21:24.099935  TX DQ/DQS        : PASS

 2056 12:21:24.103581  RX DATLAT        : PASS

 2057 12:21:24.103692  RX DQ/DQS(Engine): PASS

 2058 12:21:24.106912  TX OE            : NO K

 2059 12:21:24.107017  All Pass.

 2060 12:21:24.107111  

 2061 12:21:24.109915  CH 1, Rank 0

 2062 12:21:24.110021  SW Impedance     : PASS

 2063 12:21:24.113402  DUTY Scan        : NO K

 2064 12:21:24.113513  ZQ Calibration   : PASS

 2065 12:21:24.116862  Jitter Meter     : NO K

 2066 12:21:24.119801  CBT Training     : PASS

 2067 12:21:24.119912  Write leveling   : PASS

 2068 12:21:24.123072  RX DQS gating    : PASS

 2069 12:21:24.126560  RX DQ/DQS(RDDQC) : PASS

 2070 12:21:24.126668  TX DQ/DQS        : PASS

 2071 12:21:24.130198  RX DATLAT        : PASS

 2072 12:21:24.133259  RX DQ/DQS(Engine): PASS

 2073 12:21:24.133372  TX OE            : NO K

 2074 12:21:24.136959  All Pass.

 2075 12:21:24.137077  

 2076 12:21:24.137177  CH 1, Rank 1

 2077 12:21:24.139966  SW Impedance     : PASS

 2078 12:21:24.140080  DUTY Scan        : NO K

 2079 12:21:24.143668  ZQ Calibration   : PASS

 2080 12:21:24.146790  Jitter Meter     : NO K

 2081 12:21:24.146909  CBT Training     : PASS

 2082 12:21:24.150147  Write leveling   : PASS

 2083 12:21:24.150262  RX DQS gating    : PASS

 2084 12:21:24.153365  RX DQ/DQS(RDDQC) : PASS

 2085 12:21:24.156809  TX DQ/DQS        : PASS

 2086 12:21:24.156923  RX DATLAT        : PASS

 2087 12:21:24.160005  RX DQ/DQS(Engine): PASS

 2088 12:21:24.163733  TX OE            : NO K

 2089 12:21:24.163824  All Pass.

 2090 12:21:24.163898  

 2091 12:21:24.167041  DramC Write-DBI off

 2092 12:21:24.167138  	PER_BANK_REFRESH: Hybrid Mode

 2093 12:21:24.170203  TX_TRACKING: ON

 2094 12:21:24.173296  [GetDramInforAfterCalByMRR] Vendor 6.

 2095 12:21:24.176626  [GetDramInforAfterCalByMRR] Revision 606.

 2096 12:21:24.180131  [GetDramInforAfterCalByMRR] Revision 2 0.

 2097 12:21:24.180214  MR0 0x3b3b

 2098 12:21:24.183462  MR8 0x5151

 2099 12:21:24.187115  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2100 12:21:24.187247  

 2101 12:21:24.187344  MR0 0x3b3b

 2102 12:21:24.187439  MR8 0x5151

 2103 12:21:24.193695  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2104 12:21:24.193801  

 2105 12:21:24.200455  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2106 12:21:24.203442  [FAST_K] Save calibration result to emmc

 2107 12:21:24.206688  [FAST_K] Save calibration result to emmc

 2108 12:21:24.210404  dram_init: config_dvfs: 1

 2109 12:21:24.213381  dramc_set_vcore_voltage set vcore to 662500

 2110 12:21:24.217295  Read voltage for 1200, 2

 2111 12:21:24.217375  Vio18 = 0

 2112 12:21:24.220169  Vcore = 662500

 2113 12:21:24.220246  Vdram = 0

 2114 12:21:24.220309  Vddq = 0

 2115 12:21:24.220376  Vmddr = 0

 2116 12:21:24.227171  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2117 12:21:24.233617  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2118 12:21:24.233708  MEM_TYPE=3, freq_sel=15

 2119 12:21:24.237159  sv_algorithm_assistance_LP4_1600 

 2120 12:21:24.240300  ============ PULL DRAM RESETB DOWN ============

 2121 12:21:24.246964  ========== PULL DRAM RESETB DOWN end =========

 2122 12:21:24.250356  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2123 12:21:24.254058  =================================== 

 2124 12:21:24.257029  LPDDR4 DRAM CONFIGURATION

 2125 12:21:24.260132  =================================== 

 2126 12:21:24.260217  EX_ROW_EN[0]    = 0x0

 2127 12:21:24.263536  EX_ROW_EN[1]    = 0x0

 2128 12:21:24.263622  LP4Y_EN      = 0x0

 2129 12:21:24.267089  WORK_FSP     = 0x0

 2130 12:21:24.267197  WL           = 0x4

 2131 12:21:24.270358  RL           = 0x4

 2132 12:21:24.270472  BL           = 0x2

 2133 12:21:24.273912  RPST         = 0x0

 2134 12:21:24.276694  RD_PRE       = 0x0

 2135 12:21:24.276778  WR_PRE       = 0x1

 2136 12:21:24.280634  WR_PST       = 0x0

 2137 12:21:24.280730  DBI_WR       = 0x0

 2138 12:21:24.283813  DBI_RD       = 0x0

 2139 12:21:24.283919  OTF          = 0x1

 2140 12:21:24.286894  =================================== 

 2141 12:21:24.290160  =================================== 

 2142 12:21:24.290272  ANA top config

 2143 12:21:24.293423  =================================== 

 2144 12:21:24.296824  DLL_ASYNC_EN            =  0

 2145 12:21:24.300268  ALL_SLAVE_EN            =  0

 2146 12:21:24.303832  NEW_RANK_MODE           =  1

 2147 12:21:24.306909  DLL_IDLE_MODE           =  1

 2148 12:21:24.307015  LP45_APHY_COMB_EN       =  1

 2149 12:21:24.310642  TX_ODT_DIS              =  1

 2150 12:21:24.313688  NEW_8X_MODE             =  1

 2151 12:21:24.316924  =================================== 

 2152 12:21:24.320496  =================================== 

 2153 12:21:24.324118  data_rate                  = 2400

 2154 12:21:24.327206  CKR                        = 1

 2155 12:21:24.327315  DQ_P2S_RATIO               = 8

 2156 12:21:24.330688  =================================== 

 2157 12:21:24.333729  CA_P2S_RATIO               = 8

 2158 12:21:24.337280  DQ_CA_OPEN                 = 0

 2159 12:21:24.340309  DQ_SEMI_OPEN               = 0

 2160 12:21:24.343990  CA_SEMI_OPEN               = 0

 2161 12:21:24.344074  CA_FULL_RATE               = 0

 2162 12:21:24.347113  DQ_CKDIV4_EN               = 0

 2163 12:21:24.350746  CA_CKDIV4_EN               = 0

 2164 12:21:24.353631  CA_PREDIV_EN               = 0

 2165 12:21:24.357318  PH8_DLY                    = 17

 2166 12:21:24.360475  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2167 12:21:24.363605  DQ_AAMCK_DIV               = 4

 2168 12:21:24.363688  CA_AAMCK_DIV               = 4

 2169 12:21:24.367208  CA_ADMCK_DIV               = 4

 2170 12:21:24.370262  DQ_TRACK_CA_EN             = 0

 2171 12:21:24.373665  CA_PICK                    = 1200

 2172 12:21:24.377034  CA_MCKIO                   = 1200

 2173 12:21:24.380256  MCKIO_SEMI                 = 0

 2174 12:21:24.383912  PLL_FREQ                   = 2366

 2175 12:21:24.383997  DQ_UI_PI_RATIO             = 32

 2176 12:21:24.387344  CA_UI_PI_RATIO             = 0

 2177 12:21:24.390512  =================================== 

 2178 12:21:24.393385  =================================== 

 2179 12:21:24.397067  memory_type:LPDDR4         

 2180 12:21:24.400309  GP_NUM     : 10       

 2181 12:21:24.400394  SRAM_EN    : 1       

 2182 12:21:24.403395  MD32_EN    : 0       

 2183 12:21:24.407012  =================================== 

 2184 12:21:24.407116  [ANA_INIT] >>>>>>>>>>>>>> 

 2185 12:21:24.410317  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2186 12:21:24.413566  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2187 12:21:24.416869  =================================== 

 2188 12:21:24.420175  data_rate = 2400,PCW = 0X5b00

 2189 12:21:24.423766  =================================== 

 2190 12:21:24.426810  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2191 12:21:24.433501  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2192 12:21:24.440162  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2193 12:21:24.443293  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2194 12:21:24.447101  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2195 12:21:24.450180  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2196 12:21:24.453327  [ANA_INIT] flow start 

 2197 12:21:24.453407  [ANA_INIT] PLL >>>>>>>> 

 2198 12:21:24.456912  [ANA_INIT] PLL <<<<<<<< 

 2199 12:21:24.460034  [ANA_INIT] MIDPI >>>>>>>> 

 2200 12:21:24.460150  [ANA_INIT] MIDPI <<<<<<<< 

 2201 12:21:24.463718  [ANA_INIT] DLL >>>>>>>> 

 2202 12:21:24.466670  [ANA_INIT] DLL <<<<<<<< 

 2203 12:21:24.466786  [ANA_INIT] flow end 

 2204 12:21:24.473500  ============ LP4 DIFF to SE enter ============

 2205 12:21:24.476687  ============ LP4 DIFF to SE exit  ============

 2206 12:21:24.476779  [ANA_INIT] <<<<<<<<<<<<< 

 2207 12:21:24.480564  [Flow] Enable top DCM control >>>>> 

 2208 12:21:24.483668  [Flow] Enable top DCM control <<<<< 

 2209 12:21:24.487067  Enable DLL master slave shuffle 

 2210 12:21:24.493532  ============================================================== 

 2211 12:21:24.496965  Gating Mode config

 2212 12:21:24.499954  ============================================================== 

 2213 12:21:24.503590  Config description: 

 2214 12:21:24.513435  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2215 12:21:24.520076  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2216 12:21:24.523344  SELPH_MODE            0: By rank         1: By Phase 

 2217 12:21:24.530310  ============================================================== 

 2218 12:21:24.533839  GAT_TRACK_EN                 =  1

 2219 12:21:24.537567  RX_GATING_MODE               =  2

 2220 12:21:24.537658  RX_GATING_TRACK_MODE         =  2

 2221 12:21:24.540004  SELPH_MODE                   =  1

 2222 12:21:24.543343  PICG_EARLY_EN                =  1

 2223 12:21:24.546748  VALID_LAT_VALUE              =  1

 2224 12:21:24.553524  ============================================================== 

 2225 12:21:24.557057  Enter into Gating configuration >>>> 

 2226 12:21:24.560195  Exit from Gating configuration <<<< 

 2227 12:21:24.563209  Enter into  DVFS_PRE_config >>>>> 

 2228 12:21:24.573356  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2229 12:21:24.577032  Exit from  DVFS_PRE_config <<<<< 

 2230 12:21:24.579953  Enter into PICG configuration >>>> 

 2231 12:21:24.583679  Exit from PICG configuration <<<< 

 2232 12:21:24.586680  [RX_INPUT] configuration >>>>> 

 2233 12:21:24.589881  [RX_INPUT] configuration <<<<< 

 2234 12:21:24.593674  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2235 12:21:24.599919  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2236 12:21:24.606407  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2237 12:21:24.610249  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2238 12:21:24.616366  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2239 12:21:24.622898  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2240 12:21:24.626736  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2241 12:21:24.633023  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2242 12:21:24.636773  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2243 12:21:24.639699  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2244 12:21:24.643024  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2245 12:21:24.649449  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2246 12:21:24.653027  =================================== 

 2247 12:21:24.653116  LPDDR4 DRAM CONFIGURATION

 2248 12:21:24.656468  =================================== 

 2249 12:21:24.659731  EX_ROW_EN[0]    = 0x0

 2250 12:21:24.663473  EX_ROW_EN[1]    = 0x0

 2251 12:21:24.663583  LP4Y_EN      = 0x0

 2252 12:21:24.666528  WORK_FSP     = 0x0

 2253 12:21:24.666608  WL           = 0x4

 2254 12:21:24.669641  RL           = 0x4

 2255 12:21:24.669724  BL           = 0x2

 2256 12:21:24.673472  RPST         = 0x0

 2257 12:21:24.673580  RD_PRE       = 0x0

 2258 12:21:24.676657  WR_PRE       = 0x1

 2259 12:21:24.676732  WR_PST       = 0x0

 2260 12:21:24.679747  DBI_WR       = 0x0

 2261 12:21:24.679853  DBI_RD       = 0x0

 2262 12:21:24.682879  OTF          = 0x1

 2263 12:21:24.686447  =================================== 

 2264 12:21:24.689601  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2265 12:21:24.693305  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2266 12:21:24.699934  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2267 12:21:24.703022  =================================== 

 2268 12:21:24.703105  LPDDR4 DRAM CONFIGURATION

 2269 12:21:24.706542  =================================== 

 2270 12:21:24.709731  EX_ROW_EN[0]    = 0x10

 2271 12:21:24.709813  EX_ROW_EN[1]    = 0x0

 2272 12:21:24.712979  LP4Y_EN      = 0x0

 2273 12:21:24.713062  WORK_FSP     = 0x0

 2274 12:21:24.716902  WL           = 0x4

 2275 12:21:24.717019  RL           = 0x4

 2276 12:21:24.720049  BL           = 0x2

 2277 12:21:24.720163  RPST         = 0x0

 2278 12:21:24.723556  RD_PRE       = 0x0

 2279 12:21:24.726381  WR_PRE       = 0x1

 2280 12:21:24.726467  WR_PST       = 0x0

 2281 12:21:24.729869  DBI_WR       = 0x0

 2282 12:21:24.729957  DBI_RD       = 0x0

 2283 12:21:24.733079  OTF          = 0x1

 2284 12:21:24.736689  =================================== 

 2285 12:21:24.740101  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2286 12:21:24.740209  ==

 2287 12:21:24.743608  Dram Type= 6, Freq= 0, CH_0, rank 0

 2288 12:21:24.750066  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2289 12:21:24.750152  ==

 2290 12:21:24.750218  [Duty_Offset_Calibration]

 2291 12:21:24.753347  	B0:2	B1:0	CA:3

 2292 12:21:24.753457  

 2293 12:21:24.756598  [DutyScan_Calibration_Flow] k_type=0

 2294 12:21:24.766030  

 2295 12:21:24.766164  ==CLK 0==

 2296 12:21:24.769028  Final CLK duty delay cell = 0

 2297 12:21:24.772401  [0] MAX Duty = 5000%(X100), DQS PI = 12

 2298 12:21:24.775596  [0] MIN Duty = 4875%(X100), DQS PI = 58

 2299 12:21:24.775698  [0] AVG Duty = 4937%(X100)

 2300 12:21:24.779321  

 2301 12:21:24.782387  CH0 CLK Duty spec in!! Max-Min= 125%

 2302 12:21:24.786088  [DutyScan_Calibration_Flow] ====Done====

 2303 12:21:24.786184  

 2304 12:21:24.789166  [DutyScan_Calibration_Flow] k_type=1

 2305 12:21:24.804560  

 2306 12:21:24.804687  ==DQS 0 ==

 2307 12:21:24.807568  Final DQS duty delay cell = 0

 2308 12:21:24.811159  [0] MAX Duty = 5062%(X100), DQS PI = 12

 2309 12:21:24.814168  [0] MIN Duty = 4907%(X100), DQS PI = 0

 2310 12:21:24.814252  [0] AVG Duty = 4984%(X100)

 2311 12:21:24.817807  

 2312 12:21:24.817893  ==DQS 1 ==

 2313 12:21:24.820883  Final DQS duty delay cell = -4

 2314 12:21:24.824383  [-4] MAX Duty = 4969%(X100), DQS PI = 22

 2315 12:21:24.827989  [-4] MIN Duty = 4875%(X100), DQS PI = 0

 2316 12:21:24.830965  [-4] AVG Duty = 4922%(X100)

 2317 12:21:24.831048  

 2318 12:21:24.834051  CH0 DQS 0 Duty spec in!! Max-Min= 155%

 2319 12:21:24.834134  

 2320 12:21:24.837593  CH0 DQS 1 Duty spec in!! Max-Min= 94%

 2321 12:21:24.840882  [DutyScan_Calibration_Flow] ====Done====

 2322 12:21:24.840992  

 2323 12:21:24.844151  [DutyScan_Calibration_Flow] k_type=3

 2324 12:21:24.861836  

 2325 12:21:24.861958  ==DQM 0 ==

 2326 12:21:24.865076  Final DQM duty delay cell = 0

 2327 12:21:24.868751  [0] MAX Duty = 5124%(X100), DQS PI = 28

 2328 12:21:24.871873  [0] MIN Duty = 4876%(X100), DQS PI = 48

 2329 12:21:24.875145  [0] AVG Duty = 5000%(X100)

 2330 12:21:24.875252  

 2331 12:21:24.875344  ==DQM 1 ==

 2332 12:21:24.878406  Final DQM duty delay cell = 4

 2333 12:21:24.881869  [4] MAX Duty = 5124%(X100), DQS PI = 52

 2334 12:21:24.884910  [4] MIN Duty = 5031%(X100), DQS PI = 10

 2335 12:21:24.888490  [4] AVG Duty = 5077%(X100)

 2336 12:21:24.888577  

 2337 12:21:24.891467  CH0 DQM 0 Duty spec in!! Max-Min= 248%

 2338 12:21:24.891541  

 2339 12:21:24.895194  CH0 DQM 1 Duty spec in!! Max-Min= 93%

 2340 12:21:24.898112  [DutyScan_Calibration_Flow] ====Done====

 2341 12:21:24.898214  

 2342 12:21:24.901191  [DutyScan_Calibration_Flow] k_type=2

 2343 12:21:24.916882  

 2344 12:21:24.917029  ==DQ 0 ==

 2345 12:21:24.919879  Final DQ duty delay cell = -4

 2346 12:21:24.923550  [-4] MAX Duty = 5031%(X100), DQS PI = 20

 2347 12:21:24.926643  [-4] MIN Duty = 4907%(X100), DQS PI = 46

 2348 12:21:24.930256  [-4] AVG Duty = 4969%(X100)

 2349 12:21:24.930368  

 2350 12:21:24.930460  ==DQ 1 ==

 2351 12:21:24.933368  Final DQ duty delay cell = -4

 2352 12:21:24.936825  [-4] MAX Duty = 5000%(X100), DQS PI = 0

 2353 12:21:24.940337  [-4] MIN Duty = 4876%(X100), DQS PI = 18

 2354 12:21:24.943200  [-4] AVG Duty = 4938%(X100)

 2355 12:21:24.943308  

 2356 12:21:24.946999  CH0 DQ 0 Duty spec in!! Max-Min= 124%

 2357 12:21:24.947126  

 2358 12:21:24.950209  CH0 DQ 1 Duty spec in!! Max-Min= 124%

 2359 12:21:24.953828  [DutyScan_Calibration_Flow] ====Done====

 2360 12:21:24.953953  ==

 2361 12:21:24.957034  Dram Type= 6, Freq= 0, CH_1, rank 0

 2362 12:21:24.960091  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2363 12:21:24.960187  ==

 2364 12:21:24.963697  [Duty_Offset_Calibration]

 2365 12:21:24.963804  	B0:1	B1:-2	CA:0

 2366 12:21:24.963897  

 2367 12:21:24.966739  [DutyScan_Calibration_Flow] k_type=0

 2368 12:21:24.977238  

 2369 12:21:24.977360  ==CLK 0==

 2370 12:21:24.980787  Final CLK duty delay cell = 0

 2371 12:21:24.984168  [0] MAX Duty = 5062%(X100), DQS PI = 30

 2372 12:21:24.987268  [0] MIN Duty = 4876%(X100), DQS PI = 2

 2373 12:21:24.987375  [0] AVG Duty = 4969%(X100)

 2374 12:21:24.990775  

 2375 12:21:24.990878  CH1 CLK Duty spec in!! Max-Min= 186%

 2376 12:21:24.997141  [DutyScan_Calibration_Flow] ====Done====

 2377 12:21:24.997254  

 2378 12:21:25.000311  [DutyScan_Calibration_Flow] k_type=1

 2379 12:21:25.015690  

 2380 12:21:25.015805  ==DQS 0 ==

 2381 12:21:25.019189  Final DQS duty delay cell = -4

 2382 12:21:25.022144  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 2383 12:21:25.025799  [-4] MIN Duty = 4907%(X100), DQS PI = 4

 2384 12:21:25.028949  [-4] AVG Duty = 4969%(X100)

 2385 12:21:25.029032  

 2386 12:21:25.029097  ==DQS 1 ==

 2387 12:21:25.032521  Final DQS duty delay cell = 0

 2388 12:21:25.035573  [0] MAX Duty = 5093%(X100), DQS PI = 0

 2389 12:21:25.039128  [0] MIN Duty = 4875%(X100), DQS PI = 26

 2390 12:21:25.042673  [0] AVG Duty = 4984%(X100)

 2391 12:21:25.042756  

 2392 12:21:25.045634  CH1 DQS 0 Duty spec in!! Max-Min= 124%

 2393 12:21:25.045718  

 2394 12:21:25.049252  CH1 DQS 1 Duty spec in!! Max-Min= 218%

 2395 12:21:25.052272  [DutyScan_Calibration_Flow] ====Done====

 2396 12:21:25.052389  

 2397 12:21:25.055990  [DutyScan_Calibration_Flow] k_type=3

 2398 12:21:25.072296  

 2399 12:21:25.072415  ==DQM 0 ==

 2400 12:21:25.075855  Final DQM duty delay cell = 0

 2401 12:21:25.078887  [0] MAX Duty = 5000%(X100), DQS PI = 22

 2402 12:21:25.082490  [0] MIN Duty = 4844%(X100), DQS PI = 54

 2403 12:21:25.086009  [0] AVG Duty = 4922%(X100)

 2404 12:21:25.086093  

 2405 12:21:25.086158  ==DQM 1 ==

 2406 12:21:25.088870  Final DQM duty delay cell = 0

 2407 12:21:25.092105  [0] MAX Duty = 5031%(X100), DQS PI = 36

 2408 12:21:25.095849  [0] MIN Duty = 4907%(X100), DQS PI = 0

 2409 12:21:25.095930  [0] AVG Duty = 4969%(X100)

 2410 12:21:25.098862  

 2411 12:21:25.102327  CH1 DQM 0 Duty spec in!! Max-Min= 156%

 2412 12:21:25.102428  

 2413 12:21:25.105743  CH1 DQM 1 Duty spec in!! Max-Min= 124%

 2414 12:21:25.109089  [DutyScan_Calibration_Flow] ====Done====

 2415 12:21:25.109199  

 2416 12:21:25.112198  [DutyScan_Calibration_Flow] k_type=2

 2417 12:21:25.129037  

 2418 12:21:25.129183  ==DQ 0 ==

 2419 12:21:25.131989  Final DQ duty delay cell = 0

 2420 12:21:25.135105  [0] MAX Duty = 5062%(X100), DQS PI = 20

 2421 12:21:25.138673  [0] MIN Duty = 4938%(X100), DQS PI = 56

 2422 12:21:25.138764  [0] AVG Duty = 5000%(X100)

 2423 12:21:25.142403  

 2424 12:21:25.142487  ==DQ 1 ==

 2425 12:21:25.145389  Final DQ duty delay cell = 0

 2426 12:21:25.148814  [0] MAX Duty = 5125%(X100), DQS PI = 36

 2427 12:21:25.152567  [0] MIN Duty = 4969%(X100), DQS PI = 26

 2428 12:21:25.152650  [0] AVG Duty = 5047%(X100)

 2429 12:21:25.152714  

 2430 12:21:25.155803  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 2431 12:21:25.158686  

 2432 12:21:25.162169  CH1 DQ 1 Duty spec in!! Max-Min= 156%

 2433 12:21:25.165734  [DutyScan_Calibration_Flow] ====Done====

 2434 12:21:25.168640  nWR fixed to 30

 2435 12:21:25.168756  [ModeRegInit_LP4] CH0 RK0

 2436 12:21:25.172369  [ModeRegInit_LP4] CH0 RK1

 2437 12:21:25.175669  [ModeRegInit_LP4] CH1 RK0

 2438 12:21:25.175785  [ModeRegInit_LP4] CH1 RK1

 2439 12:21:25.178551  match AC timing 7

 2440 12:21:25.181630  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2441 12:21:25.188560  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2442 12:21:25.191673  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2443 12:21:25.198368  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2444 12:21:25.202044  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2445 12:21:25.202133  ==

 2446 12:21:25.205046  Dram Type= 6, Freq= 0, CH_0, rank 0

 2447 12:21:25.208727  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2448 12:21:25.208813  ==

 2449 12:21:25.215271  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2450 12:21:25.221757  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2451 12:21:25.228610  [CA 0] Center 40 (10~71) winsize 62

 2452 12:21:25.232019  [CA 1] Center 40 (10~70) winsize 61

 2453 12:21:25.235582  [CA 2] Center 36 (6~66) winsize 61

 2454 12:21:25.238954  [CA 3] Center 35 (5~66) winsize 62

 2455 12:21:25.242342  [CA 4] Center 34 (4~65) winsize 62

 2456 12:21:25.245758  [CA 5] Center 33 (3~64) winsize 62

 2457 12:21:25.245872  

 2458 12:21:25.248745  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2459 12:21:25.248828  

 2460 12:21:25.252250  [CATrainingPosCal] consider 1 rank data

 2461 12:21:25.255554  u2DelayCellTimex100 = 270/100 ps

 2462 12:21:25.259310  CA0 delay=40 (10~71),Diff = 7 PI (33 cell)

 2463 12:21:25.265414  CA1 delay=40 (10~70),Diff = 7 PI (33 cell)

 2464 12:21:25.268664  CA2 delay=36 (6~66),Diff = 3 PI (14 cell)

 2465 12:21:25.272279  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2466 12:21:25.275310  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2467 12:21:25.279228  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 2468 12:21:25.279342  

 2469 12:21:25.282416  CA PerBit enable=1, Macro0, CA PI delay=33

 2470 12:21:25.282507  

 2471 12:21:25.285391  [CBTSetCACLKResult] CA Dly = 33

 2472 12:21:25.285477  CS Dly: 7 (0~38)

 2473 12:21:25.289073  ==

 2474 12:21:25.292077  Dram Type= 6, Freq= 0, CH_0, rank 1

 2475 12:21:25.295247  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2476 12:21:25.295336  ==

 2477 12:21:25.298952  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2478 12:21:25.305691  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2479 12:21:25.315149  [CA 0] Center 40 (10~70) winsize 61

 2480 12:21:25.318198  [CA 1] Center 39 (9~70) winsize 62

 2481 12:21:25.321644  [CA 2] Center 35 (5~66) winsize 62

 2482 12:21:25.325175  [CA 3] Center 35 (5~66) winsize 62

 2483 12:21:25.328234  [CA 4] Center 34 (4~65) winsize 62

 2484 12:21:25.331350  [CA 5] Center 33 (3~64) winsize 62

 2485 12:21:25.331466  

 2486 12:21:25.334904  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2487 12:21:25.335027  

 2488 12:21:25.338394  [CATrainingPosCal] consider 2 rank data

 2489 12:21:25.342069  u2DelayCellTimex100 = 270/100 ps

 2490 12:21:25.345096  CA0 delay=40 (10~70),Diff = 7 PI (33 cell)

 2491 12:21:25.351395  CA1 delay=40 (10~70),Diff = 7 PI (33 cell)

 2492 12:21:25.354752  CA2 delay=36 (6~66),Diff = 3 PI (14 cell)

 2493 12:21:25.358367  CA3 delay=35 (5~66),Diff = 2 PI (9 cell)

 2494 12:21:25.361496  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 2495 12:21:25.364783  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 2496 12:21:25.364869  

 2497 12:21:25.368295  CA PerBit enable=1, Macro0, CA PI delay=33

 2498 12:21:25.368380  

 2499 12:21:25.371931  [CBTSetCACLKResult] CA Dly = 33

 2500 12:21:25.372016  CS Dly: 8 (0~40)

 2501 12:21:25.375256  

 2502 12:21:25.378619  ----->DramcWriteLeveling(PI) begin...

 2503 12:21:25.378705  ==

 2504 12:21:25.381575  Dram Type= 6, Freq= 0, CH_0, rank 0

 2505 12:21:25.385370  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2506 12:21:25.385465  ==

 2507 12:21:25.388521  Write leveling (Byte 0): 34 => 34

 2508 12:21:25.392108  Write leveling (Byte 1): 30 => 30

 2509 12:21:25.394980  DramcWriteLeveling(PI) end<-----

 2510 12:21:25.395062  

 2511 12:21:25.395128  ==

 2512 12:21:25.398819  Dram Type= 6, Freq= 0, CH_0, rank 0

 2513 12:21:25.401815  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2514 12:21:25.401901  ==

 2515 12:21:25.405409  [Gating] SW mode calibration

 2516 12:21:25.411722  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2517 12:21:25.418829  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2518 12:21:25.421881   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2519 12:21:25.424947   0 15  4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)

 2520 12:21:25.428401   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2521 12:21:25.435292   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2522 12:21:25.438471   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2523 12:21:25.441789   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2524 12:21:25.448507   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2525 12:21:25.451958   0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 2526 12:21:25.455157   1  0  0 | B1->B0 | 3333 2828 | 0 0 | (0 1) (0 0)

 2527 12:21:25.461787   1  0  4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)

 2528 12:21:25.464843   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2529 12:21:25.468251   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2530 12:21:25.475096   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2531 12:21:25.478535   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2532 12:21:25.481656   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2533 12:21:25.488359   1  0 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 2534 12:21:25.491913   1  1  0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)

 2535 12:21:25.495010   1  1  4 | B1->B0 | 4343 4646 | 0 0 | (1 1) (0 0)

 2536 12:21:25.501822   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2537 12:21:25.504897   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2538 12:21:25.508482   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2539 12:21:25.515201   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2540 12:21:25.518206   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2541 12:21:25.521562   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2542 12:21:25.524964   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2543 12:21:25.531733   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2544 12:21:25.535008   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2545 12:21:25.538624   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2546 12:21:25.545343   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2547 12:21:25.548158   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2548 12:21:25.551764   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2549 12:21:25.558343   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2550 12:21:25.562009   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2551 12:21:25.565133   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2552 12:21:25.571648   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2553 12:21:25.575230   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2554 12:21:25.578288   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2555 12:21:25.584917   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2556 12:21:25.589429   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2557 12:21:25.591671   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2558 12:21:25.598396   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2559 12:21:25.598525  Total UI for P1: 0, mck2ui 16

 2560 12:21:25.605469  best dqsien dly found for B0: ( 1,  3, 28)

 2561 12:21:25.608087   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2562 12:21:25.611436   1  4  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2563 12:21:25.615170  Total UI for P1: 0, mck2ui 16

 2564 12:21:25.618232  best dqsien dly found for B1: ( 1,  4,  2)

 2565 12:21:25.621430  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 2566 12:21:25.625082  best DQS1 dly(MCK, UI, PI) = (1, 4, 2)

 2567 12:21:25.625191  

 2568 12:21:25.628166  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2569 12:21:25.634885  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)

 2570 12:21:25.635004  [Gating] SW calibration Done

 2571 12:21:25.635105  ==

 2572 12:21:25.638259  Dram Type= 6, Freq= 0, CH_0, rank 0

 2573 12:21:25.644757  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2574 12:21:25.644872  ==

 2575 12:21:25.644966  RX Vref Scan: 0

 2576 12:21:25.645056  

 2577 12:21:25.648415  RX Vref 0 -> 0, step: 1

 2578 12:21:25.648522  

 2579 12:21:25.652030  RX Delay -40 -> 252, step: 8

 2580 12:21:25.654968  iDelay=200, Bit 0, Center 111 (32 ~ 191) 160

 2581 12:21:25.658419  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 2582 12:21:25.661673  iDelay=200, Bit 2, Center 115 (40 ~ 191) 152

 2583 12:21:25.665072  iDelay=200, Bit 3, Center 107 (32 ~ 183) 152

 2584 12:21:25.671799  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2585 12:21:25.674891  iDelay=200, Bit 5, Center 99 (24 ~ 175) 152

 2586 12:21:25.678589  iDelay=200, Bit 6, Center 119 (48 ~ 191) 144

 2587 12:21:25.682198  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2588 12:21:25.685228  iDelay=200, Bit 8, Center 91 (16 ~ 167) 152

 2589 12:21:25.688325  iDelay=200, Bit 9, Center 83 (8 ~ 159) 152

 2590 12:21:25.695361  iDelay=200, Bit 10, Center 103 (32 ~ 175) 144

 2591 12:21:25.698439  iDelay=200, Bit 11, Center 95 (24 ~ 167) 144

 2592 12:21:25.702034  iDelay=200, Bit 12, Center 107 (32 ~ 183) 152

 2593 12:21:25.705269  iDelay=200, Bit 13, Center 107 (32 ~ 183) 152

 2594 12:21:25.711497  iDelay=200, Bit 14, Center 115 (40 ~ 191) 152

 2595 12:21:25.715094  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 2596 12:21:25.715216  ==

 2597 12:21:25.718654  Dram Type= 6, Freq= 0, CH_0, rank 0

 2598 12:21:25.721525  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2599 12:21:25.721639  ==

 2600 12:21:25.721734  DQS Delay:

 2601 12:21:25.725406  DQS0 = 0, DQS1 = 0

 2602 12:21:25.725515  DQM Delay:

 2603 12:21:25.728391  DQM0 = 112, DQM1 = 101

 2604 12:21:25.728500  DQ Delay:

 2605 12:21:25.732076  DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107

 2606 12:21:25.735148  DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123

 2607 12:21:25.738341  DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95

 2608 12:21:25.741961  DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111

 2609 12:21:25.742045  

 2610 12:21:25.742110  

 2611 12:21:25.745349  ==

 2612 12:21:25.748834  Dram Type= 6, Freq= 0, CH_0, rank 0

 2613 12:21:25.751581  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2614 12:21:25.751667  ==

 2615 12:21:25.751734  

 2616 12:21:25.751794  

 2617 12:21:25.754806  	TX Vref Scan disable

 2618 12:21:25.754903   == TX Byte 0 ==

 2619 12:21:25.758310  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2620 12:21:25.764994  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2621 12:21:25.765115   == TX Byte 1 ==

 2622 12:21:25.768442  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 2623 12:21:25.774836  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 2624 12:21:25.774960  ==

 2625 12:21:25.778646  Dram Type= 6, Freq= 0, CH_0, rank 0

 2626 12:21:25.781665  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2627 12:21:25.781772  ==

 2628 12:21:25.794114  TX Vref=22, minBit 7, minWin=25, winSum=415

 2629 12:21:25.797168  TX Vref=24, minBit 0, minWin=26, winSum=421

 2630 12:21:25.800642  TX Vref=26, minBit 0, minWin=26, winSum=425

 2631 12:21:25.803722  TX Vref=28, minBit 1, minWin=26, winSum=428

 2632 12:21:25.807467  TX Vref=30, minBit 2, minWin=26, winSum=431

 2633 12:21:25.814082  TX Vref=32, minBit 10, minWin=26, winSum=430

 2634 12:21:25.817496  [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 30

 2635 12:21:25.817609  

 2636 12:21:25.820859  Final TX Range 1 Vref 30

 2637 12:21:25.820973  

 2638 12:21:25.821074  ==

 2639 12:21:25.824206  Dram Type= 6, Freq= 0, CH_0, rank 0

 2640 12:21:25.827118  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2641 12:21:25.827231  ==

 2642 12:21:25.827328  

 2643 12:21:25.830590  

 2644 12:21:25.830700  	TX Vref Scan disable

 2645 12:21:25.833910   == TX Byte 0 ==

 2646 12:21:25.837111  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2647 12:21:25.840669  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2648 12:21:25.843742   == TX Byte 1 ==

 2649 12:21:25.847455  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 2650 12:21:25.850437  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 2651 12:21:25.850545  

 2652 12:21:25.854022  [DATLAT]

 2653 12:21:25.854104  Freq=1200, CH0 RK0

 2654 12:21:25.854169  

 2655 12:21:25.857601  DATLAT Default: 0xd

 2656 12:21:25.857687  0, 0xFFFF, sum = 0

 2657 12:21:25.860554  1, 0xFFFF, sum = 0

 2658 12:21:25.860642  2, 0xFFFF, sum = 0

 2659 12:21:25.863955  3, 0xFFFF, sum = 0

 2660 12:21:25.864044  4, 0xFFFF, sum = 0

 2661 12:21:25.867243  5, 0xFFFF, sum = 0

 2662 12:21:25.867331  6, 0xFFFF, sum = 0

 2663 12:21:25.870606  7, 0xFFFF, sum = 0

 2664 12:21:25.873900  8, 0xFFFF, sum = 0

 2665 12:21:25.873989  9, 0xFFFF, sum = 0

 2666 12:21:25.877431  10, 0xFFFF, sum = 0

 2667 12:21:25.877519  11, 0xFFFF, sum = 0

 2668 12:21:25.880837  12, 0x0, sum = 1

 2669 12:21:25.880925  13, 0x0, sum = 2

 2670 12:21:25.884142  14, 0x0, sum = 3

 2671 12:21:25.884253  15, 0x0, sum = 4

 2672 12:21:25.884359  best_step = 13

 2673 12:21:25.884441  

 2674 12:21:25.887138  ==

 2675 12:21:25.887225  Dram Type= 6, Freq= 0, CH_0, rank 0

 2676 12:21:25.893999  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2677 12:21:25.894087  ==

 2678 12:21:25.894172  RX Vref Scan: 1

 2679 12:21:25.894254  

 2680 12:21:25.897127  Set Vref Range= 32 -> 127

 2681 12:21:25.897213  

 2682 12:21:25.900700  RX Vref 32 -> 127, step: 1

 2683 12:21:25.900789  

 2684 12:21:25.904222  RX Delay -37 -> 252, step: 4

 2685 12:21:25.904307  

 2686 12:21:25.907143  Set Vref, RX VrefLevel [Byte0]: 32

 2687 12:21:25.910754                           [Byte1]: 32

 2688 12:21:25.910840  

 2689 12:21:25.913758  Set Vref, RX VrefLevel [Byte0]: 33

 2690 12:21:25.917402                           [Byte1]: 33

 2691 12:21:25.920428  

 2692 12:21:25.920513  Set Vref, RX VrefLevel [Byte0]: 34

 2693 12:21:25.923877                           [Byte1]: 34

 2694 12:21:25.928385  

 2695 12:21:25.928472  Set Vref, RX VrefLevel [Byte0]: 35

 2696 12:21:25.931542                           [Byte1]: 35

 2697 12:21:25.936400  

 2698 12:21:25.936484  Set Vref, RX VrefLevel [Byte0]: 36

 2699 12:21:25.939589                           [Byte1]: 36

 2700 12:21:25.944260  

 2701 12:21:25.944371  Set Vref, RX VrefLevel [Byte0]: 37

 2702 12:21:25.947542                           [Byte1]: 37

 2703 12:21:25.952435  

 2704 12:21:25.952522  Set Vref, RX VrefLevel [Byte0]: 38

 2705 12:21:25.955928                           [Byte1]: 38

 2706 12:21:25.960679  

 2707 12:21:25.960759  Set Vref, RX VrefLevel [Byte0]: 39

 2708 12:21:25.963839                           [Byte1]: 39

 2709 12:21:25.968867  

 2710 12:21:25.968948  Set Vref, RX VrefLevel [Byte0]: 40

 2711 12:21:25.971785                           [Byte1]: 40

 2712 12:21:25.976619  

 2713 12:21:25.976698  Set Vref, RX VrefLevel [Byte0]: 41

 2714 12:21:25.979666                           [Byte1]: 41

 2715 12:21:25.984540  

 2716 12:21:25.984631  Set Vref, RX VrefLevel [Byte0]: 42

 2717 12:21:25.987540                           [Byte1]: 42

 2718 12:21:25.992528  

 2719 12:21:25.992619  Set Vref, RX VrefLevel [Byte0]: 43

 2720 12:21:25.995943                           [Byte1]: 43

 2721 12:21:26.000331  

 2722 12:21:26.000454  Set Vref, RX VrefLevel [Byte0]: 44

 2723 12:21:26.004028                           [Byte1]: 44

 2724 12:21:26.008240  

 2725 12:21:26.008326  Set Vref, RX VrefLevel [Byte0]: 45

 2726 12:21:26.011609                           [Byte1]: 45

 2727 12:21:26.016401  

 2728 12:21:26.016486  Set Vref, RX VrefLevel [Byte0]: 46

 2729 12:21:26.019603                           [Byte1]: 46

 2730 12:21:26.024584  

 2731 12:21:26.024668  Set Vref, RX VrefLevel [Byte0]: 47

 2732 12:21:26.027610                           [Byte1]: 47

 2733 12:21:26.032472  

 2734 12:21:26.032560  Set Vref, RX VrefLevel [Byte0]: 48

 2735 12:21:26.035811                           [Byte1]: 48

 2736 12:21:26.040404  

 2737 12:21:26.040488  Set Vref, RX VrefLevel [Byte0]: 49

 2738 12:21:26.043777                           [Byte1]: 49

 2739 12:21:26.048595  

 2740 12:21:26.048690  Set Vref, RX VrefLevel [Byte0]: 50

 2741 12:21:26.051725                           [Byte1]: 50

 2742 12:21:26.056379  

 2743 12:21:26.056468  Set Vref, RX VrefLevel [Byte0]: 51

 2744 12:21:26.059770                           [Byte1]: 51

 2745 12:21:26.064530  

 2746 12:21:26.064620  Set Vref, RX VrefLevel [Byte0]: 52

 2747 12:21:26.067672                           [Byte1]: 52

 2748 12:21:26.072628  

 2749 12:21:26.072718  Set Vref, RX VrefLevel [Byte0]: 53

 2750 12:21:26.076033                           [Byte1]: 53

 2751 12:21:26.080778  

 2752 12:21:26.080863  Set Vref, RX VrefLevel [Byte0]: 54

 2753 12:21:26.083793                           [Byte1]: 54

 2754 12:21:26.088463  

 2755 12:21:26.088547  Set Vref, RX VrefLevel [Byte0]: 55

 2756 12:21:26.091673                           [Byte1]: 55

 2757 12:21:26.096292  

 2758 12:21:26.096378  Set Vref, RX VrefLevel [Byte0]: 56

 2759 12:21:26.099642                           [Byte1]: 56

 2760 12:21:26.104244  

 2761 12:21:26.104330  Set Vref, RX VrefLevel [Byte0]: 57

 2762 12:21:26.107860                           [Byte1]: 57

 2763 12:21:26.112372  

 2764 12:21:26.112564  Set Vref, RX VrefLevel [Byte0]: 58

 2765 12:21:26.115658                           [Byte1]: 58

 2766 12:21:26.120203  

 2767 12:21:26.120296  Set Vref, RX VrefLevel [Byte0]: 59

 2768 12:21:26.123824                           [Byte1]: 59

 2769 12:21:26.128217  

 2770 12:21:26.128305  Set Vref, RX VrefLevel [Byte0]: 60

 2771 12:21:26.131847                           [Byte1]: 60

 2772 12:21:26.136160  

 2773 12:21:26.136248  Set Vref, RX VrefLevel [Byte0]: 61

 2774 12:21:26.139811                           [Byte1]: 61

 2775 12:21:26.144594  

 2776 12:21:26.144705  Set Vref, RX VrefLevel [Byte0]: 62

 2777 12:21:26.147689                           [Byte1]: 62

 2778 12:21:26.152654  

 2779 12:21:26.152741  Set Vref, RX VrefLevel [Byte0]: 63

 2780 12:21:26.156083                           [Byte1]: 63

 2781 12:21:26.160240  

 2782 12:21:26.160341  Set Vref, RX VrefLevel [Byte0]: 64

 2783 12:21:26.163990                           [Byte1]: 64

 2784 12:21:26.168195  

 2785 12:21:26.168386  Set Vref, RX VrefLevel [Byte0]: 65

 2786 12:21:26.171814                           [Byte1]: 65

 2787 12:21:26.176295  

 2788 12:21:26.176454  Set Vref, RX VrefLevel [Byte0]: 66

 2789 12:21:26.179934                           [Byte1]: 66

 2790 12:21:26.184267  

 2791 12:21:26.184402  Set Vref, RX VrefLevel [Byte0]: 67

 2792 12:21:26.187543                           [Byte1]: 67

 2793 12:21:26.192389  

 2794 12:21:26.192492  Set Vref, RX VrefLevel [Byte0]: 68

 2795 12:21:26.196052                           [Byte1]: 68

 2796 12:21:26.200459  

 2797 12:21:26.200544  Set Vref, RX VrefLevel [Byte0]: 69

 2798 12:21:26.204017                           [Byte1]: 69

 2799 12:21:26.208686  

 2800 12:21:26.208771  Set Vref, RX VrefLevel [Byte0]: 70

 2801 12:21:26.211702                           [Byte1]: 70

 2802 12:21:26.216599  

 2803 12:21:26.216691  Set Vref, RX VrefLevel [Byte0]: 71

 2804 12:21:26.219556                           [Byte1]: 71

 2805 12:21:26.224400  

 2806 12:21:26.224488  Set Vref, RX VrefLevel [Byte0]: 72

 2807 12:21:26.227770                           [Byte1]: 72

 2808 12:21:26.232290  

 2809 12:21:26.232377  Set Vref, RX VrefLevel [Byte0]: 73

 2810 12:21:26.235392                           [Byte1]: 73

 2811 12:21:26.240501  

 2812 12:21:26.240597  Set Vref, RX VrefLevel [Byte0]: 74

 2813 12:21:26.243688                           [Byte1]: 74

 2814 12:21:26.248404  

 2815 12:21:26.248494  Final RX Vref Byte 0 = 61 to rank0

 2816 12:21:26.251496  Final RX Vref Byte 1 = 53 to rank0

 2817 12:21:26.255212  Final RX Vref Byte 0 = 61 to rank1

 2818 12:21:26.258221  Final RX Vref Byte 1 = 53 to rank1==

 2819 12:21:26.261723  Dram Type= 6, Freq= 0, CH_0, rank 0

 2820 12:21:26.268607  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2821 12:21:26.268743  ==

 2822 12:21:26.268839  DQS Delay:

 2823 12:21:26.268935  DQS0 = 0, DQS1 = 0

 2824 12:21:26.271580  DQM Delay:

 2825 12:21:26.271693  DQM0 = 112, DQM1 = 101

 2826 12:21:26.275145  DQ Delay:

 2827 12:21:26.278593  DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =106

 2828 12:21:26.281745  DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120

 2829 12:21:26.285068  DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =92

 2830 12:21:26.288670  DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110

 2831 12:21:26.288787  

 2832 12:21:26.288885  

 2833 12:21:26.295038  [DQSOSCAuto] RK0, (LSB)MR18= 0xfafa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps

 2834 12:21:26.298195  CH0 RK0: MR19=303, MR18=FAFA

 2835 12:21:26.305113  CH0_RK0: MR19=0x303, MR18=0xFAFA, DQSOSC=412, MR23=63, INC=38, DEC=25

 2836 12:21:26.305267  

 2837 12:21:26.308227  ----->DramcWriteLeveling(PI) begin...

 2838 12:21:26.308338  ==

 2839 12:21:26.311812  Dram Type= 6, Freq= 0, CH_0, rank 1

 2840 12:21:26.315025  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2841 12:21:26.318248  ==

 2842 12:21:26.318362  Write leveling (Byte 0): 33 => 33

 2843 12:21:26.321698  Write leveling (Byte 1): 31 => 31

 2844 12:21:26.325095  DramcWriteLeveling(PI) end<-----

 2845 12:21:26.325205  

 2846 12:21:26.325300  ==

 2847 12:21:26.328029  Dram Type= 6, Freq= 0, CH_0, rank 1

 2848 12:21:26.334819  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2849 12:21:26.334936  ==

 2850 12:21:26.335036  [Gating] SW mode calibration

 2851 12:21:26.345151  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2852 12:21:26.348362  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2853 12:21:26.351528   0 15  0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)

 2854 12:21:26.358602   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2855 12:21:26.361718   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2856 12:21:26.365323   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2857 12:21:26.371527   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2858 12:21:26.375228   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2859 12:21:26.378274   0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)

 2860 12:21:26.385221   0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)

 2861 12:21:26.388664   1  0  0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 2862 12:21:26.391725   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2863 12:21:26.398569   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2864 12:21:26.401803   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2865 12:21:26.404950   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2866 12:21:26.411897   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2867 12:21:26.415327   1  0 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)

 2868 12:21:26.418454   1  0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)

 2869 12:21:26.425399   1  1  0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 2870 12:21:26.428351   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2871 12:21:26.431689   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2872 12:21:26.435050   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2873 12:21:26.441654   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2874 12:21:26.445276   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2875 12:21:26.448261   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2876 12:21:26.455053   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2877 12:21:26.458190   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2878 12:21:26.461904   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2879 12:21:26.468555   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2880 12:21:26.471694   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2881 12:21:26.475143   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2882 12:21:26.481931   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2883 12:21:26.485111   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2884 12:21:26.488763   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2885 12:21:26.494934   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2886 12:21:26.498660   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2887 12:21:26.501831   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2888 12:21:26.508759   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2889 12:21:26.511947   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2890 12:21:26.515188   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2891 12:21:26.521507   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2892 12:21:26.525327   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2893 12:21:26.528488   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2894 12:21:26.531600  Total UI for P1: 0, mck2ui 16

 2895 12:21:26.535319  best dqsien dly found for B0: ( 1,  3, 26)

 2896 12:21:26.538428   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2897 12:21:26.541862  Total UI for P1: 0, mck2ui 16

 2898 12:21:26.545071  best dqsien dly found for B1: ( 1,  4,  0)

 2899 12:21:26.548340  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2900 12:21:26.551703  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2901 12:21:26.551785  

 2902 12:21:26.558710  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2903 12:21:26.561648  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2904 12:21:26.561731  [Gating] SW calibration Done

 2905 12:21:26.565471  ==

 2906 12:21:26.568409  Dram Type= 6, Freq= 0, CH_0, rank 1

 2907 12:21:26.572006  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2908 12:21:26.572119  ==

 2909 12:21:26.572214  RX Vref Scan: 0

 2910 12:21:26.572304  

 2911 12:21:26.575046  RX Vref 0 -> 0, step: 1

 2912 12:21:26.575129  

 2913 12:21:26.578624  RX Delay -40 -> 252, step: 8

 2914 12:21:26.581654  iDelay=200, Bit 0, Center 111 (40 ~ 183) 144

 2915 12:21:26.584990  iDelay=200, Bit 1, Center 107 (32 ~ 183) 152

 2916 12:21:26.588899  iDelay=200, Bit 2, Center 111 (40 ~ 183) 144

 2917 12:21:26.595039  iDelay=200, Bit 3, Center 107 (32 ~ 183) 152

 2918 12:21:26.598505  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2919 12:21:26.601874  iDelay=200, Bit 5, Center 103 (32 ~ 175) 144

 2920 12:21:26.605191  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 2921 12:21:26.608085  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2922 12:21:26.615063  iDelay=200, Bit 8, Center 91 (16 ~ 167) 152

 2923 12:21:26.618214  iDelay=200, Bit 9, Center 83 (8 ~ 159) 152

 2924 12:21:26.621932  iDelay=200, Bit 10, Center 103 (32 ~ 175) 144

 2925 12:21:26.625130  iDelay=200, Bit 11, Center 95 (24 ~ 167) 144

 2926 12:21:26.628330  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2927 12:21:26.635030  iDelay=200, Bit 13, Center 111 (40 ~ 183) 144

 2928 12:21:26.638417  iDelay=200, Bit 14, Center 111 (40 ~ 183) 144

 2929 12:21:26.641649  iDelay=200, Bit 15, Center 107 (32 ~ 183) 152

 2930 12:21:26.641760  ==

 2931 12:21:26.644766  Dram Type= 6, Freq= 0, CH_0, rank 1

 2932 12:21:26.648656  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2933 12:21:26.648769  ==

 2934 12:21:26.651569  DQS Delay:

 2935 12:21:26.651664  DQS0 = 0, DQS1 = 0

 2936 12:21:26.655025  DQM Delay:

 2937 12:21:26.655137  DQM0 = 112, DQM1 = 101

 2938 12:21:26.655226  DQ Delay:

 2939 12:21:26.661891  DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107

 2940 12:21:26.664949  DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123

 2941 12:21:26.668380  DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95

 2942 12:21:26.671966  DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107

 2943 12:21:26.672086  

 2944 12:21:26.672189  

 2945 12:21:26.672254  ==

 2946 12:21:26.675027  Dram Type= 6, Freq= 0, CH_0, rank 1

 2947 12:21:26.678626  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2948 12:21:26.678742  ==

 2949 12:21:26.678841  

 2950 12:21:26.678939  

 2951 12:21:26.681816  	TX Vref Scan disable

 2952 12:21:26.685079   == TX Byte 0 ==

 2953 12:21:26.688543  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2954 12:21:26.691319  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2955 12:21:26.694665   == TX Byte 1 ==

 2956 12:21:26.698365  Update DQ  dly =848 (3 ,2, 16)  DQ  OEN =(2 ,7)

 2957 12:21:26.701487  Update DQM dly =848 (3 ,2, 16)  DQM OEN =(2 ,7)

 2958 12:21:26.701570  ==

 2959 12:21:26.704987  Dram Type= 6, Freq= 0, CH_0, rank 1

 2960 12:21:26.708507  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2961 12:21:26.708592  ==

 2962 12:21:26.721371  TX Vref=22, minBit 1, minWin=26, winSum=426

 2963 12:21:26.725032  TX Vref=24, minBit 2, minWin=26, winSum=429

 2964 12:21:26.728540  TX Vref=26, minBit 0, minWin=26, winSum=428

 2965 12:21:26.731589  TX Vref=28, minBit 1, minWin=26, winSum=440

 2966 12:21:26.734840  TX Vref=30, minBit 1, minWin=26, winSum=439

 2967 12:21:26.741732  TX Vref=32, minBit 10, minWin=26, winSum=439

 2968 12:21:26.744820  [TxChooseVref] Worse bit 1, Min win 26, Win sum 440, Final Vref 28

 2969 12:21:26.744908  

 2970 12:21:26.747859  Final TX Range 1 Vref 28

 2971 12:21:26.747949  

 2972 12:21:26.748046  ==

 2973 12:21:26.751729  Dram Type= 6, Freq= 0, CH_0, rank 1

 2974 12:21:26.754969  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2975 12:21:26.755053  ==

 2976 12:21:26.758037  

 2977 12:21:26.758119  

 2978 12:21:26.758184  	TX Vref Scan disable

 2979 12:21:26.761290   == TX Byte 0 ==

 2980 12:21:26.764691  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2981 12:21:26.768158  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2982 12:21:26.771217   == TX Byte 1 ==

 2983 12:21:26.774626  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 2984 12:21:26.778096  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 2985 12:21:26.781263  

 2986 12:21:26.781346  [DATLAT]

 2987 12:21:26.781410  Freq=1200, CH0 RK1

 2988 12:21:26.781471  

 2989 12:21:26.784906  DATLAT Default: 0xd

 2990 12:21:26.784989  0, 0xFFFF, sum = 0

 2991 12:21:26.787761  1, 0xFFFF, sum = 0

 2992 12:21:26.787846  2, 0xFFFF, sum = 0

 2993 12:21:26.791519  3, 0xFFFF, sum = 0

 2994 12:21:26.791606  4, 0xFFFF, sum = 0

 2995 12:21:26.794945  5, 0xFFFF, sum = 0

 2996 12:21:26.798276  6, 0xFFFF, sum = 0

 2997 12:21:26.798379  7, 0xFFFF, sum = 0

 2998 12:21:26.801182  8, 0xFFFF, sum = 0

 2999 12:21:26.801299  9, 0xFFFF, sum = 0

 3000 12:21:26.804817  10, 0xFFFF, sum = 0

 3001 12:21:26.804902  11, 0xFFFF, sum = 0

 3002 12:21:26.807796  12, 0x0, sum = 1

 3003 12:21:26.807897  13, 0x0, sum = 2

 3004 12:21:26.811348  14, 0x0, sum = 3

 3005 12:21:26.811458  15, 0x0, sum = 4

 3006 12:21:26.811545  best_step = 13

 3007 12:21:26.811609  

 3008 12:21:26.814324  ==

 3009 12:21:26.817967  Dram Type= 6, Freq= 0, CH_0, rank 1

 3010 12:21:26.821035  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3011 12:21:26.821144  ==

 3012 12:21:26.821242  RX Vref Scan: 0

 3013 12:21:26.821334  

 3014 12:21:26.824943  RX Vref 0 -> 0, step: 1

 3015 12:21:26.825071  

 3016 12:21:26.827963  RX Delay -37 -> 252, step: 4

 3017 12:21:26.831607  iDelay=195, Bit 0, Center 108 (39 ~ 178) 140

 3018 12:21:26.837895  iDelay=195, Bit 1, Center 112 (43 ~ 182) 140

 3019 12:21:26.841613  iDelay=195, Bit 2, Center 106 (39 ~ 174) 136

 3020 12:21:26.844915  iDelay=195, Bit 3, Center 108 (39 ~ 178) 140

 3021 12:21:26.848014  iDelay=195, Bit 4, Center 112 (43 ~ 182) 140

 3022 12:21:26.851202  iDelay=195, Bit 5, Center 100 (35 ~ 166) 132

 3023 12:21:26.854979  iDelay=195, Bit 6, Center 120 (47 ~ 194) 148

 3024 12:21:26.861185  iDelay=195, Bit 7, Center 118 (43 ~ 194) 152

 3025 12:21:26.864684  iDelay=195, Bit 8, Center 90 (19 ~ 162) 144

 3026 12:21:26.868301  iDelay=195, Bit 9, Center 82 (11 ~ 154) 144

 3027 12:21:26.871157  iDelay=195, Bit 10, Center 104 (35 ~ 174) 140

 3028 12:21:26.874563  iDelay=195, Bit 11, Center 94 (27 ~ 162) 136

 3029 12:21:26.881767  iDelay=195, Bit 12, Center 108 (39 ~ 178) 140

 3030 12:21:26.884683  iDelay=195, Bit 13, Center 108 (39 ~ 178) 140

 3031 12:21:26.888095  iDelay=195, Bit 14, Center 114 (47 ~ 182) 136

 3032 12:21:26.891598  iDelay=195, Bit 15, Center 110 (43 ~ 178) 136

 3033 12:21:26.891682  ==

 3034 12:21:26.894524  Dram Type= 6, Freq= 0, CH_0, rank 1

 3035 12:21:26.901499  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3036 12:21:26.901586  ==

 3037 12:21:26.901654  DQS Delay:

 3038 12:21:26.904491  DQS0 = 0, DQS1 = 0

 3039 12:21:26.904575  DQM Delay:

 3040 12:21:26.904641  DQM0 = 110, DQM1 = 101

 3041 12:21:26.907928  DQ Delay:

 3042 12:21:26.911355  DQ0 =108, DQ1 =112, DQ2 =106, DQ3 =108

 3043 12:21:26.914447  DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118

 3044 12:21:26.918063  DQ8 =90, DQ9 =82, DQ10 =104, DQ11 =94

 3045 12:21:26.921123  DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110

 3046 12:21:26.921207  

 3047 12:21:26.921273  

 3048 12:21:26.928291  [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps

 3049 12:21:26.931424  CH0 RK1: MR19=403, MR18=10F8

 3050 12:21:26.938047  CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26

 3051 12:21:26.941700  [RxdqsGatingPostProcess] freq 1200

 3052 12:21:26.947879  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3053 12:21:26.951630  best DQS0 dly(2T, 0.5T) = (0, 11)

 3054 12:21:26.951718  best DQS1 dly(2T, 0.5T) = (0, 12)

 3055 12:21:26.954889  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3056 12:21:26.958109  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3057 12:21:26.961290  best DQS0 dly(2T, 0.5T) = (0, 11)

 3058 12:21:26.964520  best DQS1 dly(2T, 0.5T) = (0, 12)

 3059 12:21:26.968140  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3060 12:21:26.971722  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3061 12:21:26.974988  Pre-setting of DQS Precalculation

 3062 12:21:26.981546  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3063 12:21:26.981656  ==

 3064 12:21:26.985054  Dram Type= 6, Freq= 0, CH_1, rank 0

 3065 12:21:26.988154  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3066 12:21:26.988274  ==

 3067 12:21:26.994757  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3068 12:21:26.997709  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 3069 12:21:27.007382  [CA 0] Center 37 (7~67) winsize 61

 3070 12:21:27.010624  [CA 1] Center 37 (7~68) winsize 62

 3071 12:21:27.014237  [CA 2] Center 34 (5~64) winsize 60

 3072 12:21:27.017657  [CA 3] Center 33 (3~64) winsize 62

 3073 12:21:27.020856  [CA 4] Center 34 (4~64) winsize 61

 3074 12:21:27.024257  [CA 5] Center 33 (3~63) winsize 61

 3075 12:21:27.024340  

 3076 12:21:27.027701  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 3077 12:21:27.027779  

 3078 12:21:27.030718  [CATrainingPosCal] consider 1 rank data

 3079 12:21:27.034423  u2DelayCellTimex100 = 270/100 ps

 3080 12:21:27.037510  CA0 delay=37 (7~67),Diff = 4 PI (19 cell)

 3081 12:21:27.041094  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3082 12:21:27.047297  CA2 delay=34 (5~64),Diff = 1 PI (4 cell)

 3083 12:21:27.051041  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 3084 12:21:27.054109  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3085 12:21:27.057722  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3086 12:21:27.057829  

 3087 12:21:27.060741  CA PerBit enable=1, Macro0, CA PI delay=33

 3088 12:21:27.060847  

 3089 12:21:27.063913  [CBTSetCACLKResult] CA Dly = 33

 3090 12:21:27.064081  CS Dly: 6 (0~37)

 3091 12:21:27.067618  ==

 3092 12:21:27.067726  Dram Type= 6, Freq= 0, CH_1, rank 1

 3093 12:21:27.073767  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3094 12:21:27.073881  ==

 3095 12:21:27.077280  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3096 12:21:27.083992  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 3097 12:21:27.092957  [CA 0] Center 37 (7~67) winsize 61

 3098 12:21:27.096625  [CA 1] Center 37 (7~68) winsize 62

 3099 12:21:27.099777  [CA 2] Center 34 (4~65) winsize 62

 3100 12:21:27.103343  [CA 3] Center 33 (3~64) winsize 62

 3101 12:21:27.106285  [CA 4] Center 34 (4~64) winsize 61

 3102 12:21:27.109631  [CA 5] Center 32 (2~63) winsize 62

 3103 12:21:27.109720  

 3104 12:21:27.113081  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 3105 12:21:27.113166  

 3106 12:21:27.116188  [CATrainingPosCal] consider 2 rank data

 3107 12:21:27.119990  u2DelayCellTimex100 = 270/100 ps

 3108 12:21:27.123064  CA0 delay=37 (7~67),Diff = 4 PI (19 cell)

 3109 12:21:27.126672  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3110 12:21:27.132954  CA2 delay=34 (5~64),Diff = 1 PI (4 cell)

 3111 12:21:27.136149  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 3112 12:21:27.139471  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3113 12:21:27.143016  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3114 12:21:27.143125  

 3115 12:21:27.146374  CA PerBit enable=1, Macro0, CA PI delay=33

 3116 12:21:27.146491  

 3117 12:21:27.149854  [CBTSetCACLKResult] CA Dly = 33

 3118 12:21:27.149968  CS Dly: 7 (0~39)

 3119 12:21:27.150066  

 3120 12:21:27.152932  ----->DramcWriteLeveling(PI) begin...

 3121 12:21:27.156178  ==

 3122 12:21:27.156268  Dram Type= 6, Freq= 0, CH_1, rank 0

 3123 12:21:27.162562  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3124 12:21:27.162677  ==

 3125 12:21:27.166381  Write leveling (Byte 0): 26 => 26

 3126 12:21:27.169570  Write leveling (Byte 1): 28 => 28

 3127 12:21:27.172703  DramcWriteLeveling(PI) end<-----

 3128 12:21:27.172793  

 3129 12:21:27.172860  ==

 3130 12:21:27.175941  Dram Type= 6, Freq= 0, CH_1, rank 0

 3131 12:21:27.179652  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3132 12:21:27.179769  ==

 3133 12:21:27.182686  [Gating] SW mode calibration

 3134 12:21:27.189515  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3135 12:21:27.196042  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3136 12:21:27.199355   0 15  0 | B1->B0 | 2d2d 2625 | 1 1 | (1 1) (0 0)

 3137 12:21:27.202304   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3138 12:21:27.209143   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3139 12:21:27.212159   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3140 12:21:27.215545   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3141 12:21:27.222674   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3142 12:21:27.225267   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3143 12:21:27.229020   0 15 28 | B1->B0 | 3030 3131 | 1 1 | (1 1) (1 0)

 3144 12:21:27.235772   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3145 12:21:27.238892   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3146 12:21:27.242413   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3147 12:21:27.249084   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3148 12:21:27.252417   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3149 12:21:27.256075   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3150 12:21:27.258776   1  0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 3151 12:21:27.265308   1  0 28 | B1->B0 | 3c3c 3f3f | 1 0 | (1 1) (0 0)

 3152 12:21:27.269135   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3153 12:21:27.272043   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3154 12:21:27.278888   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3155 12:21:27.282471   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3156 12:21:27.285509   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3157 12:21:27.291987   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3158 12:21:27.295136   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3159 12:21:27.298880   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3160 12:21:27.306047   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 3161 12:21:27.308740   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3162 12:21:27.312091   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3163 12:21:27.318688   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3164 12:21:27.322302   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3165 12:21:27.325214   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3166 12:21:27.331926   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3167 12:21:27.335483   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3168 12:21:27.338645   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3169 12:21:27.345073   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3170 12:21:27.348891   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3171 12:21:27.351896   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3172 12:21:27.358324   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3173 12:21:27.361907   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3174 12:21:27.365505   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 3175 12:21:27.372044   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3176 12:21:27.375169   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3177 12:21:27.378422  Total UI for P1: 0, mck2ui 16

 3178 12:21:27.381543  best dqsien dly found for B0: ( 1,  3, 28)

 3179 12:21:27.385227  Total UI for P1: 0, mck2ui 16

 3180 12:21:27.388311  best dqsien dly found for B1: ( 1,  3, 26)

 3181 12:21:27.391938  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 3182 12:21:27.395061  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3183 12:21:27.395178  

 3184 12:21:27.398199  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 3185 12:21:27.401877  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3186 12:21:27.405053  [Gating] SW calibration Done

 3187 12:21:27.405174  ==

 3188 12:21:27.408176  Dram Type= 6, Freq= 0, CH_1, rank 0

 3189 12:21:27.411859  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3190 12:21:27.411993  ==

 3191 12:21:27.414908  RX Vref Scan: 0

 3192 12:21:27.415021  

 3193 12:21:27.418549  RX Vref 0 -> 0, step: 1

 3194 12:21:27.418663  

 3195 12:21:27.418758  RX Delay -40 -> 252, step: 8

 3196 12:21:27.425228  iDelay=200, Bit 0, Center 123 (48 ~ 199) 152

 3197 12:21:27.428737  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 3198 12:21:27.431674  iDelay=200, Bit 2, Center 103 (32 ~ 175) 144

 3199 12:21:27.435082  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 3200 12:21:27.438658  iDelay=200, Bit 4, Center 111 (40 ~ 183) 144

 3201 12:21:27.444910  iDelay=200, Bit 5, Center 123 (48 ~ 199) 152

 3202 12:21:27.448603  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 3203 12:21:27.451614  iDelay=200, Bit 7, Center 111 (40 ~ 183) 144

 3204 12:21:27.455515  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 3205 12:21:27.458618  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 3206 12:21:27.461612  iDelay=200, Bit 10, Center 103 (32 ~ 175) 144

 3207 12:21:27.468579  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 3208 12:21:27.471970  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3209 12:21:27.474989  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 3210 12:21:27.478655  iDelay=200, Bit 14, Center 111 (40 ~ 183) 144

 3211 12:21:27.485529  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 3212 12:21:27.485623  ==

 3213 12:21:27.488535  Dram Type= 6, Freq= 0, CH_1, rank 0

 3214 12:21:27.491583  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3215 12:21:27.491670  ==

 3216 12:21:27.491737  DQS Delay:

 3217 12:21:27.495272  DQS0 = 0, DQS1 = 0

 3218 12:21:27.495382  DQM Delay:

 3219 12:21:27.498455  DQM0 = 115, DQM1 = 107

 3220 12:21:27.498563  DQ Delay:

 3221 12:21:27.502125  DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115

 3222 12:21:27.505296  DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111

 3223 12:21:27.508366  DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103

 3224 12:21:27.512121  DQ12 =119, DQ13 =119, DQ14 =111, DQ15 =111

 3225 12:21:27.512209  

 3226 12:21:27.512277  

 3227 12:21:27.512338  ==

 3228 12:21:27.515372  Dram Type= 6, Freq= 0, CH_1, rank 0

 3229 12:21:27.522148  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3230 12:21:27.522235  ==

 3231 12:21:27.522302  

 3232 12:21:27.522363  

 3233 12:21:27.522421  	TX Vref Scan disable

 3234 12:21:27.525177   == TX Byte 0 ==

 3235 12:21:27.528845  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3236 12:21:27.531779  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3237 12:21:27.535240   == TX Byte 1 ==

 3238 12:21:27.538896  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3239 12:21:27.541804  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3240 12:21:27.545331  ==

 3241 12:21:27.548668  Dram Type= 6, Freq= 0, CH_1, rank 0

 3242 12:21:27.551827  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3243 12:21:27.551916  ==

 3244 12:21:27.563565  TX Vref=22, minBit 11, minWin=24, winSum=407

 3245 12:21:27.566470  TX Vref=24, minBit 8, minWin=25, winSum=413

 3246 12:21:27.570038  TX Vref=26, minBit 8, minWin=24, winSum=418

 3247 12:21:27.573425  TX Vref=28, minBit 9, minWin=25, winSum=421

 3248 12:21:27.576381  TX Vref=30, minBit 9, minWin=25, winSum=423

 3249 12:21:27.583186  TX Vref=32, minBit 9, minWin=25, winSum=421

 3250 12:21:27.586606  [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 30

 3251 12:21:27.586693  

 3252 12:21:27.589776  Final TX Range 1 Vref 30

 3253 12:21:27.589861  

 3254 12:21:27.589927  ==

 3255 12:21:27.592750  Dram Type= 6, Freq= 0, CH_1, rank 0

 3256 12:21:27.596441  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3257 12:21:27.596526  ==

 3258 12:21:27.599529  

 3259 12:21:27.599639  

 3260 12:21:27.599733  	TX Vref Scan disable

 3261 12:21:27.603116   == TX Byte 0 ==

 3262 12:21:27.606327  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3263 12:21:27.610020  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3264 12:21:27.613131   == TX Byte 1 ==

 3265 12:21:27.616293  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3266 12:21:27.619468  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3267 12:21:27.619552  

 3268 12:21:27.623110  [DATLAT]

 3269 12:21:27.623187  Freq=1200, CH1 RK0

 3270 12:21:27.623251  

 3271 12:21:27.626696  DATLAT Default: 0xd

 3272 12:21:27.626794  0, 0xFFFF, sum = 0

 3273 12:21:27.629938  1, 0xFFFF, sum = 0

 3274 12:21:27.630023  2, 0xFFFF, sum = 0

 3275 12:21:27.633388  3, 0xFFFF, sum = 0

 3276 12:21:27.633473  4, 0xFFFF, sum = 0

 3277 12:21:27.636556  5, 0xFFFF, sum = 0

 3278 12:21:27.636642  6, 0xFFFF, sum = 0

 3279 12:21:27.640063  7, 0xFFFF, sum = 0

 3280 12:21:27.640181  8, 0xFFFF, sum = 0

 3281 12:21:27.642890  9, 0xFFFF, sum = 0

 3282 12:21:27.646830  10, 0xFFFF, sum = 0

 3283 12:21:27.646946  11, 0xFFFF, sum = 0

 3284 12:21:27.649929  12, 0x0, sum = 1

 3285 12:21:27.650033  13, 0x0, sum = 2

 3286 12:21:27.650108  14, 0x0, sum = 3

 3287 12:21:27.652934  15, 0x0, sum = 4

 3288 12:21:27.653013  best_step = 13

 3289 12:21:27.653077  

 3290 12:21:27.656376  ==

 3291 12:21:27.656456  Dram Type= 6, Freq= 0, CH_1, rank 0

 3292 12:21:27.663107  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3293 12:21:27.663224  ==

 3294 12:21:27.663318  RX Vref Scan: 1

 3295 12:21:27.663414  

 3296 12:21:27.666311  Set Vref Range= 32 -> 127

 3297 12:21:27.666394  

 3298 12:21:27.670067  RX Vref 32 -> 127, step: 1

 3299 12:21:27.670154  

 3300 12:21:27.673294  RX Delay -21 -> 252, step: 4

 3301 12:21:27.673413  

 3302 12:21:27.676446  Set Vref, RX VrefLevel [Byte0]: 32

 3303 12:21:27.679631                           [Byte1]: 32

 3304 12:21:27.679735  

 3305 12:21:27.683215  Set Vref, RX VrefLevel [Byte0]: 33

 3306 12:21:27.686123                           [Byte1]: 33

 3307 12:21:27.686231  

 3308 12:21:27.689864  Set Vref, RX VrefLevel [Byte0]: 34

 3309 12:21:27.692759                           [Byte1]: 34

 3310 12:21:27.697472  

 3311 12:21:27.697554  Set Vref, RX VrefLevel [Byte0]: 35

 3312 12:21:27.700979                           [Byte1]: 35

 3313 12:21:27.705450  

 3314 12:21:27.705563  Set Vref, RX VrefLevel [Byte0]: 36

 3315 12:21:27.708448                           [Byte1]: 36

 3316 12:21:27.712857  

 3317 12:21:27.712946  Set Vref, RX VrefLevel [Byte0]: 37

 3318 12:21:27.716579                           [Byte1]: 37

 3319 12:21:27.720942  

 3320 12:21:27.721040  Set Vref, RX VrefLevel [Byte0]: 38

 3321 12:21:27.724176                           [Byte1]: 38

 3322 12:21:27.729238  

 3323 12:21:27.729336  Set Vref, RX VrefLevel [Byte0]: 39

 3324 12:21:27.732224                           [Byte1]: 39

 3325 12:21:27.736552  

 3326 12:21:27.736634  Set Vref, RX VrefLevel [Byte0]: 40

 3327 12:21:27.740414                           [Byte1]: 40

 3328 12:21:27.744962  

 3329 12:21:27.745038  Set Vref, RX VrefLevel [Byte0]: 41

 3330 12:21:27.748368                           [Byte1]: 41

 3331 12:21:27.752495  

 3332 12:21:27.752609  Set Vref, RX VrefLevel [Byte0]: 42

 3333 12:21:27.756297                           [Byte1]: 42

 3334 12:21:27.760583  

 3335 12:21:27.760693  Set Vref, RX VrefLevel [Byte0]: 43

 3336 12:21:27.763615                           [Byte1]: 43

 3337 12:21:27.768696  

 3338 12:21:27.768777  Set Vref, RX VrefLevel [Byte0]: 44

 3339 12:21:27.771773                           [Byte1]: 44

 3340 12:21:27.776783  

 3341 12:21:27.776896  Set Vref, RX VrefLevel [Byte0]: 45

 3342 12:21:27.779624                           [Byte1]: 45

 3343 12:21:27.784513  

 3344 12:21:27.784627  Set Vref, RX VrefLevel [Byte0]: 46

 3345 12:21:27.787699                           [Byte1]: 46

 3346 12:21:27.792458  

 3347 12:21:27.792574  Set Vref, RX VrefLevel [Byte0]: 47

 3348 12:21:27.795448                           [Byte1]: 47

 3349 12:21:27.800269  

 3350 12:21:27.800380  Set Vref, RX VrefLevel [Byte0]: 48

 3351 12:21:27.803682                           [Byte1]: 48

 3352 12:21:27.807920  

 3353 12:21:27.808032  Set Vref, RX VrefLevel [Byte0]: 49

 3354 12:21:27.811512                           [Byte1]: 49

 3355 12:21:27.816288  

 3356 12:21:27.816392  Set Vref, RX VrefLevel [Byte0]: 50

 3357 12:21:27.819463                           [Byte1]: 50

 3358 12:21:27.824013  

 3359 12:21:27.824130  Set Vref, RX VrefLevel [Byte0]: 51

 3360 12:21:27.827214                           [Byte1]: 51

 3361 12:21:27.831669  

 3362 12:21:27.831785  Set Vref, RX VrefLevel [Byte0]: 52

 3363 12:21:27.835528                           [Byte1]: 52

 3364 12:21:27.839772  

 3365 12:21:27.839873  Set Vref, RX VrefLevel [Byte0]: 53

 3366 12:21:27.842992                           [Byte1]: 53

 3367 12:21:27.848110  

 3368 12:21:27.848229  Set Vref, RX VrefLevel [Byte0]: 54

 3369 12:21:27.851334                           [Byte1]: 54

 3370 12:21:27.855552  

 3371 12:21:27.855663  Set Vref, RX VrefLevel [Byte0]: 55

 3372 12:21:27.858911                           [Byte1]: 55

 3373 12:21:27.863339  

 3374 12:21:27.863454  Set Vref, RX VrefLevel [Byte0]: 56

 3375 12:21:27.866663                           [Byte1]: 56

 3376 12:21:27.871562  

 3377 12:21:27.871653  Set Vref, RX VrefLevel [Byte0]: 57

 3378 12:21:27.875090                           [Byte1]: 57

 3379 12:21:27.879089  

 3380 12:21:27.879207  Set Vref, RX VrefLevel [Byte0]: 58

 3381 12:21:27.882513                           [Byte1]: 58

 3382 12:21:27.887302  

 3383 12:21:27.887427  Set Vref, RX VrefLevel [Byte0]: 59

 3384 12:21:27.890510                           [Byte1]: 59

 3385 12:21:27.894963  

 3386 12:21:27.895052  Set Vref, RX VrefLevel [Byte0]: 60

 3387 12:21:27.898528                           [Byte1]: 60

 3388 12:21:27.903268  

 3389 12:21:27.903400  Set Vref, RX VrefLevel [Byte0]: 61

 3390 12:21:27.906494                           [Byte1]: 61

 3391 12:21:27.910944  

 3392 12:21:27.911059  Set Vref, RX VrefLevel [Byte0]: 62

 3393 12:21:27.914158                           [Byte1]: 62

 3394 12:21:27.919151  

 3395 12:21:27.921937  Set Vref, RX VrefLevel [Byte0]: 63

 3396 12:21:27.925149                           [Byte1]: 63

 3397 12:21:27.925246  

 3398 12:21:27.929108  Set Vref, RX VrefLevel [Byte0]: 64

 3399 12:21:27.932194                           [Byte1]: 64

 3400 12:21:27.932281  

 3401 12:21:27.935312  Set Vref, RX VrefLevel [Byte0]: 65

 3402 12:21:27.938484                           [Byte1]: 65

 3403 12:21:27.942818  

 3404 12:21:27.942935  Set Vref, RX VrefLevel [Byte0]: 66

 3405 12:21:27.945879                           [Byte1]: 66

 3406 12:21:27.950961  

 3407 12:21:27.951067  Final RX Vref Byte 0 = 54 to rank0

 3408 12:21:27.954123  Final RX Vref Byte 1 = 52 to rank0

 3409 12:21:27.957463  Final RX Vref Byte 0 = 54 to rank1

 3410 12:21:27.960863  Final RX Vref Byte 1 = 52 to rank1==

 3411 12:21:27.964233  Dram Type= 6, Freq= 0, CH_1, rank 0

 3412 12:21:27.970886  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3413 12:21:27.971007  ==

 3414 12:21:27.971102  DQS Delay:

 3415 12:21:27.971193  DQS0 = 0, DQS1 = 0

 3416 12:21:27.973982  DQM Delay:

 3417 12:21:27.974108  DQM0 = 114, DQM1 = 106

 3418 12:21:27.977203  DQ Delay:

 3419 12:21:27.980427  DQ0 =120, DQ1 =108, DQ2 =104, DQ3 =110

 3420 12:21:27.983889  DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =110

 3421 12:21:27.987265  DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =102

 3422 12:21:27.990764  DQ12 =114, DQ13 =114, DQ14 =114, DQ15 =114

 3423 12:21:27.990872  

 3424 12:21:27.990940  

 3425 12:21:27.997244  [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps

 3426 12:21:28.001097  CH1 RK0: MR19=303, MR18=ECF3

 3427 12:21:28.007437  CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25

 3428 12:21:28.007525  

 3429 12:21:28.010797  ----->DramcWriteLeveling(PI) begin...

 3430 12:21:28.010891  ==

 3431 12:21:28.014007  Dram Type= 6, Freq= 0, CH_1, rank 1

 3432 12:21:28.017091  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3433 12:21:28.020921  ==

 3434 12:21:28.021002  Write leveling (Byte 0): 24 => 24

 3435 12:21:28.024238  Write leveling (Byte 1): 28 => 28

 3436 12:21:28.027249  DramcWriteLeveling(PI) end<-----

 3437 12:21:28.027359  

 3438 12:21:28.027444  ==

 3439 12:21:28.030790  Dram Type= 6, Freq= 0, CH_1, rank 1

 3440 12:21:28.037423  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3441 12:21:28.037515  ==

 3442 12:21:28.037584  [Gating] SW mode calibration

 3443 12:21:28.047278  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3444 12:21:28.050739  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3445 12:21:28.053975   0 15  0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)

 3446 12:21:28.060889   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3447 12:21:28.063940   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3448 12:21:28.067241   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3449 12:21:28.074098   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3450 12:21:28.077518   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3451 12:21:28.080640   0 15 24 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)

 3452 12:21:28.087396   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 3453 12:21:28.090554   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3454 12:21:28.094143   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3455 12:21:28.100412   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3456 12:21:28.103888   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3457 12:21:28.107511   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3458 12:21:28.114128   1  0 20 | B1->B0 | 2424 2525 | 0 1 | (0 0) (0 0)

 3459 12:21:28.117239   1  0 24 | B1->B0 | 2f2f 4545 | 0 0 | (0 0) (0 0)

 3460 12:21:28.120402   1  0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 3461 12:21:28.127607   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3462 12:21:28.130824   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3463 12:21:28.133955   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3464 12:21:28.140401   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3465 12:21:28.144176   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3466 12:21:28.147367   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3467 12:21:28.153637   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3468 12:21:28.157373   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 3469 12:21:28.160496   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3470 12:21:28.163671   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3471 12:21:28.170640   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3472 12:21:28.173907   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3473 12:21:28.177160   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3474 12:21:28.183697   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3475 12:21:28.186751   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3476 12:21:28.190636   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3477 12:21:28.196903   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3478 12:21:28.200041   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3479 12:21:28.203410   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3480 12:21:28.210400   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3481 12:21:28.213194   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3482 12:21:28.216724   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3483 12:21:28.223348   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3484 12:21:28.226628   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 3485 12:21:28.229967  Total UI for P1: 0, mck2ui 16

 3486 12:21:28.232869  best dqsien dly found for B0: ( 1,  3, 24)

 3487 12:21:28.236624   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3488 12:21:28.239705  Total UI for P1: 0, mck2ui 16

 3489 12:21:28.243214  best dqsien dly found for B1: ( 1,  3, 26)

 3490 12:21:28.246281  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 3491 12:21:28.249810  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3492 12:21:28.253088  

 3493 12:21:28.256095  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3494 12:21:28.259792  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3495 12:21:28.262935  [Gating] SW calibration Done

 3496 12:21:28.263061  ==

 3497 12:21:28.266146  Dram Type= 6, Freq= 0, CH_1, rank 1

 3498 12:21:28.269228  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3499 12:21:28.269343  ==

 3500 12:21:28.269445  RX Vref Scan: 0

 3501 12:21:28.272967  

 3502 12:21:28.273083  RX Vref 0 -> 0, step: 1

 3503 12:21:28.273185  

 3504 12:21:28.276133  RX Delay -40 -> 252, step: 8

 3505 12:21:28.279330  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 3506 12:21:28.282559  iDelay=200, Bit 1, Center 107 (32 ~ 183) 152

 3507 12:21:28.289363  iDelay=200, Bit 2, Center 99 (24 ~ 175) 152

 3508 12:21:28.292653  iDelay=200, Bit 3, Center 107 (32 ~ 183) 152

 3509 12:21:28.296169  iDelay=200, Bit 4, Center 107 (32 ~ 183) 152

 3510 12:21:28.299318  iDelay=200, Bit 5, Center 119 (40 ~ 199) 160

 3511 12:21:28.302435  iDelay=200, Bit 6, Center 119 (40 ~ 199) 160

 3512 12:21:28.309197  iDelay=200, Bit 7, Center 107 (32 ~ 183) 152

 3513 12:21:28.312203  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 3514 12:21:28.315939  iDelay=200, Bit 9, Center 99 (24 ~ 175) 152

 3515 12:21:28.318819  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3516 12:21:28.322412  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 3517 12:21:28.329180  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3518 12:21:28.332269  iDelay=200, Bit 13, Center 115 (40 ~ 191) 152

 3519 12:21:28.335765  iDelay=200, Bit 14, Center 111 (40 ~ 183) 144

 3520 12:21:28.338657  iDelay=200, Bit 15, Center 115 (40 ~ 191) 152

 3521 12:21:28.338784  ==

 3522 12:21:28.342079  Dram Type= 6, Freq= 0, CH_1, rank 1

 3523 12:21:28.348828  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3524 12:21:28.348948  ==

 3525 12:21:28.349060  DQS Delay:

 3526 12:21:28.352464  DQS0 = 0, DQS1 = 0

 3527 12:21:28.352572  DQM Delay:

 3528 12:21:28.355742  DQM0 = 110, DQM1 = 108

 3529 12:21:28.355858  DQ Delay:

 3530 12:21:28.358583  DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107

 3531 12:21:28.362075  DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107

 3532 12:21:28.365135  DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103

 3533 12:21:28.368768  DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115

 3534 12:21:28.368898  

 3535 12:21:28.369011  

 3536 12:21:28.369111  ==

 3537 12:21:28.371925  Dram Type= 6, Freq= 0, CH_1, rank 1

 3538 12:21:28.375053  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3539 12:21:28.378794  ==

 3540 12:21:28.378922  

 3541 12:21:28.379028  

 3542 12:21:28.379126  	TX Vref Scan disable

 3543 12:21:28.382034   == TX Byte 0 ==

 3544 12:21:28.385137  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3545 12:21:28.389024  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3546 12:21:28.392209   == TX Byte 1 ==

 3547 12:21:28.395301  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3548 12:21:28.398369  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3549 12:21:28.401961  ==

 3550 12:21:28.402057  Dram Type= 6, Freq= 0, CH_1, rank 1

 3551 12:21:28.408567  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3552 12:21:28.408667  ==

 3553 12:21:28.419580  TX Vref=22, minBit 9, minWin=25, winSum=422

 3554 12:21:28.423155  TX Vref=24, minBit 9, minWin=25, winSum=425

 3555 12:21:28.426149  TX Vref=26, minBit 8, minWin=26, winSum=433

 3556 12:21:28.429833  TX Vref=28, minBit 8, minWin=26, winSum=435

 3557 12:21:28.433036  TX Vref=30, minBit 9, minWin=26, winSum=437

 3558 12:21:28.439829  TX Vref=32, minBit 8, minWin=25, winSum=430

 3559 12:21:28.443044  [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30

 3560 12:21:28.443164  

 3561 12:21:28.446033  Final TX Range 1 Vref 30

 3562 12:21:28.446143  

 3563 12:21:28.446237  ==

 3564 12:21:28.449781  Dram Type= 6, Freq= 0, CH_1, rank 1

 3565 12:21:28.452664  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3566 12:21:28.452753  ==

 3567 12:21:28.455943  

 3568 12:21:28.456026  

 3569 12:21:28.456090  	TX Vref Scan disable

 3570 12:21:28.459404   == TX Byte 0 ==

 3571 12:21:28.462485  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3572 12:21:28.469315  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3573 12:21:28.469407   == TX Byte 1 ==

 3574 12:21:28.472500  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3575 12:21:28.479524  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3576 12:21:28.479628  

 3577 12:21:28.479698  [DATLAT]

 3578 12:21:28.479760  Freq=1200, CH1 RK1

 3579 12:21:28.479840  

 3580 12:21:28.482711  DATLAT Default: 0xd

 3581 12:21:28.482793  0, 0xFFFF, sum = 0

 3582 12:21:28.485902  1, 0xFFFF, sum = 0

 3583 12:21:28.489121  2, 0xFFFF, sum = 0

 3584 12:21:28.489207  3, 0xFFFF, sum = 0

 3585 12:21:28.492965  4, 0xFFFF, sum = 0

 3586 12:21:28.493050  5, 0xFFFF, sum = 0

 3587 12:21:28.495921  6, 0xFFFF, sum = 0

 3588 12:21:28.496006  7, 0xFFFF, sum = 0

 3589 12:21:28.499147  8, 0xFFFF, sum = 0

 3590 12:21:28.499230  9, 0xFFFF, sum = 0

 3591 12:21:28.502705  10, 0xFFFF, sum = 0

 3592 12:21:28.502789  11, 0xFFFF, sum = 0

 3593 12:21:28.505874  12, 0x0, sum = 1

 3594 12:21:28.505957  13, 0x0, sum = 2

 3595 12:21:28.509377  14, 0x0, sum = 3

 3596 12:21:28.509460  15, 0x0, sum = 4

 3597 12:21:28.512360  best_step = 13

 3598 12:21:28.512441  

 3599 12:21:28.512506  ==

 3600 12:21:28.515608  Dram Type= 6, Freq= 0, CH_1, rank 1

 3601 12:21:28.519284  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3602 12:21:28.519367  ==

 3603 12:21:28.519439  RX Vref Scan: 0

 3604 12:21:28.519499  

 3605 12:21:28.522215  RX Vref 0 -> 0, step: 1

 3606 12:21:28.522297  

 3607 12:21:28.526122  RX Delay -21 -> 252, step: 4

 3608 12:21:28.528892  iDelay=195, Bit 0, Center 114 (43 ~ 186) 144

 3609 12:21:28.535820  iDelay=195, Bit 1, Center 110 (43 ~ 178) 136

 3610 12:21:28.538782  iDelay=195, Bit 2, Center 102 (35 ~ 170) 136

 3611 12:21:28.542439  iDelay=195, Bit 3, Center 108 (39 ~ 178) 140

 3612 12:21:28.545498  iDelay=195, Bit 4, Center 108 (39 ~ 178) 140

 3613 12:21:28.552502  iDelay=195, Bit 5, Center 120 (47 ~ 194) 148

 3614 12:21:28.555429  iDelay=195, Bit 6, Center 120 (47 ~ 194) 148

 3615 12:21:28.559039  iDelay=195, Bit 7, Center 108 (39 ~ 178) 140

 3616 12:21:28.562075  iDelay=195, Bit 8, Center 96 (31 ~ 162) 132

 3617 12:21:28.565294  iDelay=195, Bit 9, Center 100 (35 ~ 166) 132

 3618 12:21:28.568690  iDelay=195, Bit 10, Center 110 (43 ~ 178) 136

 3619 12:21:28.575579  iDelay=195, Bit 11, Center 104 (39 ~ 170) 132

 3620 12:21:28.578713  iDelay=195, Bit 12, Center 114 (47 ~ 182) 136

 3621 12:21:28.581844  iDelay=195, Bit 13, Center 114 (47 ~ 182) 136

 3622 12:21:28.585077  iDelay=195, Bit 14, Center 116 (51 ~ 182) 132

 3623 12:21:28.592023  iDelay=195, Bit 15, Center 116 (47 ~ 186) 140

 3624 12:21:28.592137  ==

 3625 12:21:28.595212  Dram Type= 6, Freq= 0, CH_1, rank 1

 3626 12:21:28.598571  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3627 12:21:28.598674  ==

 3628 12:21:28.598769  DQS Delay:

 3629 12:21:28.601689  DQS0 = 0, DQS1 = 0

 3630 12:21:28.601772  DQM Delay:

 3631 12:21:28.605452  DQM0 = 111, DQM1 = 108

 3632 12:21:28.605532  DQ Delay:

 3633 12:21:28.608585  DQ0 =114, DQ1 =110, DQ2 =102, DQ3 =108

 3634 12:21:28.611800  DQ4 =108, DQ5 =120, DQ6 =120, DQ7 =108

 3635 12:21:28.615039  DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =104

 3636 12:21:28.618267  DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =116

 3637 12:21:28.618363  

 3638 12:21:28.621647  

 3639 12:21:28.627994  [DQSOSCAuto] RK1, (LSB)MR18= 0xf606, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps

 3640 12:21:28.631629  CH1 RK1: MR19=304, MR18=F606

 3641 12:21:28.638237  CH1_RK1: MR19=0x304, MR18=0xF606, DQSOSC=407, MR23=63, INC=39, DEC=26

 3642 12:21:28.641618  [RxdqsGatingPostProcess] freq 1200

 3643 12:21:28.644716  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3644 12:21:28.648186  best DQS0 dly(2T, 0.5T) = (0, 11)

 3645 12:21:28.651203  best DQS1 dly(2T, 0.5T) = (0, 11)

 3646 12:21:28.654947  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3647 12:21:28.658082  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3648 12:21:28.661262  best DQS0 dly(2T, 0.5T) = (0, 11)

 3649 12:21:28.664211  best DQS1 dly(2T, 0.5T) = (0, 11)

 3650 12:21:28.667626  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3651 12:21:28.671011  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3652 12:21:28.674226  Pre-setting of DQS Precalculation

 3653 12:21:28.677787  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3654 12:21:28.687784  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3655 12:21:28.693959  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3656 12:21:28.694051  

 3657 12:21:28.694116  

 3658 12:21:28.697634  [Calibration Summary] 2400 Mbps

 3659 12:21:28.697717  CH 0, Rank 0

 3660 12:21:28.700624  SW Impedance     : PASS

 3661 12:21:28.700706  DUTY Scan        : NO K

 3662 12:21:28.704369  ZQ Calibration   : PASS

 3663 12:21:28.707578  Jitter Meter     : NO K

 3664 12:21:28.707664  CBT Training     : PASS

 3665 12:21:28.710609  Write leveling   : PASS

 3666 12:21:28.713791  RX DQS gating    : PASS

 3667 12:21:28.713872  RX DQ/DQS(RDDQC) : PASS

 3668 12:21:28.717433  TX DQ/DQS        : PASS

 3669 12:21:28.720541  RX DATLAT        : PASS

 3670 12:21:28.720630  RX DQ/DQS(Engine): PASS

 3671 12:21:28.723729  TX OE            : NO K

 3672 12:21:28.723831  All Pass.

 3673 12:21:28.723899  

 3674 12:21:28.727350  CH 0, Rank 1

 3675 12:21:28.727455  SW Impedance     : PASS

 3676 12:21:28.730637  DUTY Scan        : NO K

 3677 12:21:28.730722  ZQ Calibration   : PASS

 3678 12:21:28.734128  Jitter Meter     : NO K

 3679 12:21:28.737284  CBT Training     : PASS

 3680 12:21:28.737370  Write leveling   : PASS

 3681 12:21:28.740348  RX DQS gating    : PASS

 3682 12:21:28.743494  RX DQ/DQS(RDDQC) : PASS

 3683 12:21:28.743583  TX DQ/DQS        : PASS

 3684 12:21:28.746973  RX DATLAT        : PASS

 3685 12:21:28.750364  RX DQ/DQS(Engine): PASS

 3686 12:21:28.750472  TX OE            : NO K

 3687 12:21:28.753553  All Pass.

 3688 12:21:28.753638  

 3689 12:21:28.753705  CH 1, Rank 0

 3690 12:21:28.756800  SW Impedance     : PASS

 3691 12:21:28.756911  DUTY Scan        : NO K

 3692 12:21:28.760291  ZQ Calibration   : PASS

 3693 12:21:28.763835  Jitter Meter     : NO K

 3694 12:21:28.763949  CBT Training     : PASS

 3695 12:21:28.767002  Write leveling   : PASS

 3696 12:21:28.770140  RX DQS gating    : PASS

 3697 12:21:28.770223  RX DQ/DQS(RDDQC) : PASS

 3698 12:21:28.773713  TX DQ/DQS        : PASS

 3699 12:21:28.776633  RX DATLAT        : PASS

 3700 12:21:28.776747  RX DQ/DQS(Engine): PASS

 3701 12:21:28.780202  TX OE            : NO K

 3702 12:21:28.780334  All Pass.

 3703 12:21:28.780416  

 3704 12:21:28.783147  CH 1, Rank 1

 3705 12:21:28.783244  SW Impedance     : PASS

 3706 12:21:28.786747  DUTY Scan        : NO K

 3707 12:21:28.789745  ZQ Calibration   : PASS

 3708 12:21:28.789853  Jitter Meter     : NO K

 3709 12:21:28.793293  CBT Training     : PASS

 3710 12:21:28.796407  Write leveling   : PASS

 3711 12:21:28.796491  RX DQS gating    : PASS

 3712 12:21:28.800307  RX DQ/DQS(RDDQC) : PASS

 3713 12:21:28.800417  TX DQ/DQS        : PASS

 3714 12:21:28.802923  RX DATLAT        : PASS

 3715 12:21:28.806830  RX DQ/DQS(Engine): PASS

 3716 12:21:28.806937  TX OE            : NO K

 3717 12:21:28.809838  All Pass.

 3718 12:21:28.809921  

 3719 12:21:28.809986  DramC Write-DBI off

 3720 12:21:28.813418  	PER_BANK_REFRESH: Hybrid Mode

 3721 12:21:28.816617  TX_TRACKING: ON

 3722 12:21:28.822815  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3723 12:21:28.825935  [FAST_K] Save calibration result to emmc

 3724 12:21:28.833028  dramc_set_vcore_voltage set vcore to 650000

 3725 12:21:28.833153  Read voltage for 600, 5

 3726 12:21:28.833220  Vio18 = 0

 3727 12:21:28.836154  Vcore = 650000

 3728 12:21:28.836239  Vdram = 0

 3729 12:21:28.836305  Vddq = 0

 3730 12:21:28.839304  Vmddr = 0

 3731 12:21:28.842958  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3732 12:21:28.849289  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3733 12:21:28.852358  MEM_TYPE=3, freq_sel=19

 3734 12:21:28.852475  sv_algorithm_assistance_LP4_1600 

 3735 12:21:28.859214  ============ PULL DRAM RESETB DOWN ============

 3736 12:21:28.862708  ========== PULL DRAM RESETB DOWN end =========

 3737 12:21:28.865990  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3738 12:21:28.869143  =================================== 

 3739 12:21:28.872403  LPDDR4 DRAM CONFIGURATION

 3740 12:21:28.875817  =================================== 

 3741 12:21:28.879182  EX_ROW_EN[0]    = 0x0

 3742 12:21:28.879270  EX_ROW_EN[1]    = 0x0

 3743 12:21:28.882454  LP4Y_EN      = 0x0

 3744 12:21:28.882538  WORK_FSP     = 0x0

 3745 12:21:28.885465  WL           = 0x2

 3746 12:21:28.885548  RL           = 0x2

 3747 12:21:28.888676  BL           = 0x2

 3748 12:21:28.888762  RPST         = 0x0

 3749 12:21:28.892139  RD_PRE       = 0x0

 3750 12:21:28.892248  WR_PRE       = 0x1

 3751 12:21:28.895743  WR_PST       = 0x0

 3752 12:21:28.895826  DBI_WR       = 0x0

 3753 12:21:28.899316  DBI_RD       = 0x0

 3754 12:21:28.902280  OTF          = 0x1

 3755 12:21:28.905565  =================================== 

 3756 12:21:28.905684  =================================== 

 3757 12:21:28.908750  ANA top config

 3758 12:21:28.911961  =================================== 

 3759 12:21:28.915079  DLL_ASYNC_EN            =  0

 3760 12:21:28.918708  ALL_SLAVE_EN            =  1

 3761 12:21:28.918794  NEW_RANK_MODE           =  1

 3762 12:21:28.921857  DLL_IDLE_MODE           =  1

 3763 12:21:28.925673  LP45_APHY_COMB_EN       =  1

 3764 12:21:28.928867  TX_ODT_DIS              =  1

 3765 12:21:28.928953  NEW_8X_MODE             =  1

 3766 12:21:28.931923  =================================== 

 3767 12:21:28.935028  =================================== 

 3768 12:21:28.938737  data_rate                  = 1200

 3769 12:21:28.941848  CKR                        = 1

 3770 12:21:28.944848  DQ_P2S_RATIO               = 8

 3771 12:21:28.948423  =================================== 

 3772 12:21:28.951961  CA_P2S_RATIO               = 8

 3773 12:21:28.955218  DQ_CA_OPEN                 = 0

 3774 12:21:28.955320  DQ_SEMI_OPEN               = 0

 3775 12:21:28.958440  CA_SEMI_OPEN               = 0

 3776 12:21:28.961685  CA_FULL_RATE               = 0

 3777 12:21:28.964837  DQ_CKDIV4_EN               = 1

 3778 12:21:28.968070  CA_CKDIV4_EN               = 1

 3779 12:21:28.971779  CA_PREDIV_EN               = 0

 3780 12:21:28.971869  PH8_DLY                    = 0

 3781 12:21:28.974685  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3782 12:21:28.978249  DQ_AAMCK_DIV               = 4

 3783 12:21:28.981614  CA_AAMCK_DIV               = 4

 3784 12:21:28.984416  CA_ADMCK_DIV               = 4

 3785 12:21:28.987730  DQ_TRACK_CA_EN             = 0

 3786 12:21:28.991391  CA_PICK                    = 600

 3787 12:21:28.991477  CA_MCKIO                   = 600

 3788 12:21:28.994329  MCKIO_SEMI                 = 0

 3789 12:21:28.997855  PLL_FREQ                   = 2288

 3790 12:21:29.001361  DQ_UI_PI_RATIO             = 32

 3791 12:21:29.004328  CA_UI_PI_RATIO             = 0

 3792 12:21:29.007617  =================================== 

 3793 12:21:29.011267  =================================== 

 3794 12:21:29.014823  memory_type:LPDDR4         

 3795 12:21:29.014913  GP_NUM     : 10       

 3796 12:21:29.017608  SRAM_EN    : 1       

 3797 12:21:29.017711  MD32_EN    : 0       

 3798 12:21:29.020750  =================================== 

 3799 12:21:29.024620  [ANA_INIT] >>>>>>>>>>>>>> 

 3800 12:21:29.027683  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3801 12:21:29.030831  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3802 12:21:29.034010  =================================== 

 3803 12:21:29.037777  data_rate = 1200,PCW = 0X5800

 3804 12:21:29.040962  =================================== 

 3805 12:21:29.044050  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3806 12:21:29.050838  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3807 12:21:29.054316  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3808 12:21:29.060971  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3809 12:21:29.064190  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3810 12:21:29.067502  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3811 12:21:29.067594  [ANA_INIT] flow start 

 3812 12:21:29.070771  [ANA_INIT] PLL >>>>>>>> 

 3813 12:21:29.073887  [ANA_INIT] PLL <<<<<<<< 

 3814 12:21:29.074002  [ANA_INIT] MIDPI >>>>>>>> 

 3815 12:21:29.077078  [ANA_INIT] MIDPI <<<<<<<< 

 3816 12:21:29.080667  [ANA_INIT] DLL >>>>>>>> 

 3817 12:21:29.080783  [ANA_INIT] flow end 

 3818 12:21:29.087482  ============ LP4 DIFF to SE enter ============

 3819 12:21:29.090553  ============ LP4 DIFF to SE exit  ============

 3820 12:21:29.093849  [ANA_INIT] <<<<<<<<<<<<< 

 3821 12:21:29.096959  [Flow] Enable top DCM control >>>>> 

 3822 12:21:29.100645  [Flow] Enable top DCM control <<<<< 

 3823 12:21:29.100732  Enable DLL master slave shuffle 

 3824 12:21:29.107061  ============================================================== 

 3825 12:21:29.110086  Gating Mode config

 3826 12:21:29.113282  ============================================================== 

 3827 12:21:29.116883  Config description: 

 3828 12:21:29.126601  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3829 12:21:29.133193  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3830 12:21:29.136904  SELPH_MODE            0: By rank         1: By Phase 

 3831 12:21:29.143464  ============================================================== 

 3832 12:21:29.146510  GAT_TRACK_EN                 =  1

 3833 12:21:29.149795  RX_GATING_MODE               =  2

 3834 12:21:29.152958  RX_GATING_TRACK_MODE         =  2

 3835 12:21:29.156523  SELPH_MODE                   =  1

 3836 12:21:29.159950  PICG_EARLY_EN                =  1

 3837 12:21:29.162908  VALID_LAT_VALUE              =  1

 3838 12:21:29.166536  ============================================================== 

 3839 12:21:29.169581  Enter into Gating configuration >>>> 

 3840 12:21:29.172671  Exit from Gating configuration <<<< 

 3841 12:21:29.176336  Enter into  DVFS_PRE_config >>>>> 

 3842 12:21:29.189179  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3843 12:21:29.189302  Exit from  DVFS_PRE_config <<<<< 

 3844 12:21:29.192708  Enter into PICG configuration >>>> 

 3845 12:21:29.195905  Exit from PICG configuration <<<< 

 3846 12:21:29.199132  [RX_INPUT] configuration >>>>> 

 3847 12:21:29.202745  [RX_INPUT] configuration <<<<< 

 3848 12:21:29.209194  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3849 12:21:29.212599  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3850 12:21:29.219534  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3851 12:21:29.225707  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3852 12:21:29.232751  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3853 12:21:29.238912  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3854 12:21:29.242336  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3855 12:21:29.245611  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3856 12:21:29.249135  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3857 12:21:29.255415  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3858 12:21:29.259342  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3859 12:21:29.262593  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3860 12:21:29.265444  =================================== 

 3861 12:21:29.268818  LPDDR4 DRAM CONFIGURATION

 3862 12:21:29.272043  =================================== 

 3863 12:21:29.275392  EX_ROW_EN[0]    = 0x0

 3864 12:21:29.275487  EX_ROW_EN[1]    = 0x0

 3865 12:21:29.278699  LP4Y_EN      = 0x0

 3866 12:21:29.278785  WORK_FSP     = 0x0

 3867 12:21:29.282037  WL           = 0x2

 3868 12:21:29.282148  RL           = 0x2

 3869 12:21:29.285717  BL           = 0x2

 3870 12:21:29.285820  RPST         = 0x0

 3871 12:21:29.288876  RD_PRE       = 0x0

 3872 12:21:29.288962  WR_PRE       = 0x1

 3873 12:21:29.291908  WR_PST       = 0x0

 3874 12:21:29.291987  DBI_WR       = 0x0

 3875 12:21:29.295565  DBI_RD       = 0x0

 3876 12:21:29.295646  OTF          = 0x1

 3877 12:21:29.298679  =================================== 

 3878 12:21:29.301969  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3879 12:21:29.308473  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3880 12:21:29.312125  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3881 12:21:29.315039  =================================== 

 3882 12:21:29.318791  LPDDR4 DRAM CONFIGURATION

 3883 12:21:29.321759  =================================== 

 3884 12:21:29.321850  EX_ROW_EN[0]    = 0x10

 3885 12:21:29.325243  EX_ROW_EN[1]    = 0x0

 3886 12:21:29.328312  LP4Y_EN      = 0x0

 3887 12:21:29.328403  WORK_FSP     = 0x0

 3888 12:21:29.331552  WL           = 0x2

 3889 12:21:29.331640  RL           = 0x2

 3890 12:21:29.335263  BL           = 0x2

 3891 12:21:29.335370  RPST         = 0x0

 3892 12:21:29.338567  RD_PRE       = 0x0

 3893 12:21:29.338660  WR_PRE       = 0x1

 3894 12:21:29.341514  WR_PST       = 0x0

 3895 12:21:29.341599  DBI_WR       = 0x0

 3896 12:21:29.345116  DBI_RD       = 0x0

 3897 12:21:29.345201  OTF          = 0x1

 3898 12:21:29.348221  =================================== 

 3899 12:21:29.354814  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3900 12:21:29.359296  nWR fixed to 30

 3901 12:21:29.362751  [ModeRegInit_LP4] CH0 RK0

 3902 12:21:29.362848  [ModeRegInit_LP4] CH0 RK1

 3903 12:21:29.366079  [ModeRegInit_LP4] CH1 RK0

 3904 12:21:29.369434  [ModeRegInit_LP4] CH1 RK1

 3905 12:21:29.369551  match AC timing 17

 3906 12:21:29.375769  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3907 12:21:29.380022  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3908 12:21:29.382602  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3909 12:21:29.389221  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3910 12:21:29.392263  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3911 12:21:29.392369  ==

 3912 12:21:29.395968  Dram Type= 6, Freq= 0, CH_0, rank 0

 3913 12:21:29.399099  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3914 12:21:29.399203  ==

 3915 12:21:29.406048  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3916 12:21:29.412341  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3917 12:21:29.415995  [CA 0] Center 37 (7~67) winsize 61

 3918 12:21:29.418996  [CA 1] Center 37 (7~67) winsize 61

 3919 12:21:29.422707  [CA 2] Center 35 (5~65) winsize 61

 3920 12:21:29.425681  [CA 3] Center 35 (5~65) winsize 61

 3921 12:21:29.428853  [CA 4] Center 34 (4~64) winsize 61

 3922 12:21:29.432439  [CA 5] Center 34 (4~64) winsize 61

 3923 12:21:29.432538  

 3924 12:21:29.435346  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3925 12:21:29.435469  

 3926 12:21:29.439014  [CATrainingPosCal] consider 1 rank data

 3927 12:21:29.442339  u2DelayCellTimex100 = 270/100 ps

 3928 12:21:29.445322  CA0 delay=37 (7~67),Diff = 3 PI (28 cell)

 3929 12:21:29.449108  CA1 delay=37 (7~67),Diff = 3 PI (28 cell)

 3930 12:21:29.452379  CA2 delay=35 (5~65),Diff = 1 PI (9 cell)

 3931 12:21:29.455619  CA3 delay=35 (5~65),Diff = 1 PI (9 cell)

 3932 12:21:29.458696  CA4 delay=34 (4~64),Diff = 0 PI (0 cell)

 3933 12:21:29.465629  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3934 12:21:29.465768  

 3935 12:21:29.468575  CA PerBit enable=1, Macro0, CA PI delay=34

 3936 12:21:29.468692  

 3937 12:21:29.472483  [CBTSetCACLKResult] CA Dly = 34

 3938 12:21:29.472601  CS Dly: 7 (0~38)

 3939 12:21:29.472698  ==

 3940 12:21:29.475512  Dram Type= 6, Freq= 0, CH_0, rank 1

 3941 12:21:29.478986  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3942 12:21:29.481987  ==

 3943 12:21:29.485128  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3944 12:21:29.492098  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3945 12:21:29.494962  [CA 0] Center 37 (7~67) winsize 61

 3946 12:21:29.498470  [CA 1] Center 37 (7~67) winsize 61

 3947 12:21:29.502004  [CA 2] Center 35 (5~65) winsize 61

 3948 12:21:29.505449  [CA 3] Center 35 (5~65) winsize 61

 3949 12:21:29.508450  [CA 4] Center 34 (4~64) winsize 61

 3950 12:21:29.512224  [CA 5] Center 33 (3~64) winsize 62

 3951 12:21:29.512315  

 3952 12:21:29.515341  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3953 12:21:29.515442  

 3954 12:21:29.518511  [CATrainingPosCal] consider 2 rank data

 3955 12:21:29.521993  u2DelayCellTimex100 = 270/100 ps

 3956 12:21:29.525306  CA0 delay=37 (7~67),Diff = 3 PI (28 cell)

 3957 12:21:29.528391  CA1 delay=37 (7~67),Diff = 3 PI (28 cell)

 3958 12:21:29.531913  CA2 delay=35 (5~65),Diff = 1 PI (9 cell)

 3959 12:21:29.538672  CA3 delay=35 (5~65),Diff = 1 PI (9 cell)

 3960 12:21:29.541613  CA4 delay=34 (4~64),Diff = 0 PI (0 cell)

 3961 12:21:29.545177  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 3962 12:21:29.545273  

 3963 12:21:29.548253  CA PerBit enable=1, Macro0, CA PI delay=34

 3964 12:21:29.548341  

 3965 12:21:29.551488  [CBTSetCACLKResult] CA Dly = 34

 3966 12:21:29.551578  CS Dly: 6 (0~36)

 3967 12:21:29.551645  

 3968 12:21:29.555315  ----->DramcWriteLeveling(PI) begin...

 3969 12:21:29.555444  ==

 3970 12:21:29.558372  Dram Type= 6, Freq= 0, CH_0, rank 0

 3971 12:21:29.564992  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3972 12:21:29.565110  ==

 3973 12:21:29.568026  Write leveling (Byte 0): 32 => 32

 3974 12:21:29.571322  Write leveling (Byte 1): 32 => 32

 3975 12:21:29.571457  DramcWriteLeveling(PI) end<-----

 3976 12:21:29.574884  

 3977 12:21:29.574982  ==

 3978 12:21:29.578141  Dram Type= 6, Freq= 0, CH_0, rank 0

 3979 12:21:29.581201  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3980 12:21:29.581320  ==

 3981 12:21:29.584554  [Gating] SW mode calibration

 3982 12:21:29.591413  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 3983 12:21:29.594631  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 3984 12:21:29.601632   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3985 12:21:29.604755   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3986 12:21:29.607812   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3987 12:21:29.614763   0  9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)

 3988 12:21:29.618117   0  9 16 | B1->B0 | 3131 2b2b | 0 0 | (0 1) (0 0)

 3989 12:21:29.620946   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3990 12:21:29.627795   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3991 12:21:29.631031   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3992 12:21:29.634543   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3993 12:21:29.641032   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3994 12:21:29.644593   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3995 12:21:29.647695   0 10 12 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)

 3996 12:21:29.654235   0 10 16 | B1->B0 | 2e2e 3b3b | 0 0 | (0 0) (0 0)

 3997 12:21:29.657921   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3998 12:21:29.661129   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3999 12:21:29.667287   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4000 12:21:29.671130   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4001 12:21:29.674124   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4002 12:21:29.680654   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4003 12:21:29.683902   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4004 12:21:29.687594   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4005 12:21:29.694231   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4006 12:21:29.697425   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4007 12:21:29.700631   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4008 12:21:29.706981   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4009 12:21:29.710709   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4010 12:21:29.713911   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4011 12:21:29.720735   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4012 12:21:29.723705   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4013 12:21:29.726986   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4014 12:21:29.733608   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4015 12:21:29.737116   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4016 12:21:29.740165   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4017 12:21:29.747083   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4018 12:21:29.750279   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4019 12:21:29.753501   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4020 12:21:29.760129   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 4021 12:21:29.760320  Total UI for P1: 0, mck2ui 16

 4022 12:21:29.763787  best dqsien dly found for B0: ( 0, 13, 14)

 4023 12:21:29.770051   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4024 12:21:29.773402  Total UI for P1: 0, mck2ui 16

 4025 12:21:29.776669  best dqsien dly found for B1: ( 0, 13, 18)

 4026 12:21:29.780169  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4027 12:21:29.783225  best DQS1 dly(MCK, UI, PI) = (0, 13, 18)

 4028 12:21:29.783378  

 4029 12:21:29.787020  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4030 12:21:29.790191  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)

 4031 12:21:29.793226  [Gating] SW calibration Done

 4032 12:21:29.793382  ==

 4033 12:21:29.796281  Dram Type= 6, Freq= 0, CH_0, rank 0

 4034 12:21:29.800072  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4035 12:21:29.800231  ==

 4036 12:21:29.803330  RX Vref Scan: 0

 4037 12:21:29.803488  

 4038 12:21:29.806585  RX Vref 0 -> 0, step: 1

 4039 12:21:29.806737  

 4040 12:21:29.806866  RX Delay -230 -> 252, step: 16

 4041 12:21:29.813310  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4042 12:21:29.816557  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4043 12:21:29.820465  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4044 12:21:29.823410  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4045 12:21:29.829842  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4046 12:21:29.833661  iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320

 4047 12:21:29.836391  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4048 12:21:29.840045  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4049 12:21:29.846614  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4050 12:21:29.850434  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4051 12:21:29.853479  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4052 12:21:29.856664  iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336

 4053 12:21:29.859850  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4054 12:21:29.866682  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4055 12:21:29.869816  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4056 12:21:29.873118  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4057 12:21:29.873279  ==

 4058 12:21:29.876046  Dram Type= 6, Freq= 0, CH_0, rank 0

 4059 12:21:29.882922  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4060 12:21:29.883104  ==

 4061 12:21:29.883235  DQS Delay:

 4062 12:21:29.883367  DQS0 = 0, DQS1 = 0

 4063 12:21:29.886074  DQM Delay:

 4064 12:21:29.886221  DQM0 = 41, DQM1 = 30

 4065 12:21:29.889481  DQ Delay:

 4066 12:21:29.893111  DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41

 4067 12:21:29.896053  DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49

 4068 12:21:29.899412  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17

 4069 12:21:29.902787  DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41

 4070 12:21:29.902941  

 4071 12:21:29.903077  

 4072 12:21:29.903204  ==

 4073 12:21:29.905977  Dram Type= 6, Freq= 0, CH_0, rank 0

 4074 12:21:29.909202  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4075 12:21:29.909359  ==

 4076 12:21:29.909485  

 4077 12:21:29.909616  

 4078 12:21:29.913071  	TX Vref Scan disable

 4079 12:21:29.913232   == TX Byte 0 ==

 4080 12:21:29.919519  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4081 12:21:29.922658  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4082 12:21:29.922817   == TX Byte 1 ==

 4083 12:21:29.928941  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4084 12:21:29.932572  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4085 12:21:29.932733  ==

 4086 12:21:29.935657  Dram Type= 6, Freq= 0, CH_0, rank 0

 4087 12:21:29.939390  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4088 12:21:29.939557  ==

 4089 12:21:29.939684  

 4090 12:21:29.942290  

 4091 12:21:29.942436  	TX Vref Scan disable

 4092 12:21:29.946044   == TX Byte 0 ==

 4093 12:21:29.949172  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4094 12:21:29.955792  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4095 12:21:29.955980   == TX Byte 1 ==

 4096 12:21:29.958954  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4097 12:21:29.965586  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4098 12:21:29.965761  

 4099 12:21:29.965898  [DATLAT]

 4100 12:21:29.966020  Freq=600, CH0 RK0

 4101 12:21:29.966149  

 4102 12:21:29.969417  DATLAT Default: 0x9

 4103 12:21:29.969551  0, 0xFFFF, sum = 0

 4104 12:21:29.972449  1, 0xFFFF, sum = 0

 4105 12:21:29.975994  2, 0xFFFF, sum = 0

 4106 12:21:29.976099  3, 0xFFFF, sum = 0

 4107 12:21:29.978966  4, 0xFFFF, sum = 0

 4108 12:21:29.979064  5, 0xFFFF, sum = 0

 4109 12:21:29.982686  6, 0xFFFF, sum = 0

 4110 12:21:29.982781  7, 0xFFFF, sum = 0

 4111 12:21:29.985744  8, 0x0, sum = 1

 4112 12:21:29.985838  9, 0x0, sum = 2

 4113 12:21:29.985927  10, 0x0, sum = 3

 4114 12:21:29.989000  11, 0x0, sum = 4

 4115 12:21:29.989091  best_step = 9

 4116 12:21:29.989179  

 4117 12:21:29.989263  ==

 4118 12:21:29.992600  Dram Type= 6, Freq= 0, CH_0, rank 0

 4119 12:21:29.999164  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4120 12:21:29.999277  ==

 4121 12:21:29.999392  RX Vref Scan: 1

 4122 12:21:29.999477  

 4123 12:21:30.002145  RX Vref 0 -> 0, step: 1

 4124 12:21:30.002236  

 4125 12:21:30.005684  RX Delay -195 -> 252, step: 8

 4126 12:21:30.005835  

 4127 12:21:30.009132  Set Vref, RX VrefLevel [Byte0]: 61

 4128 12:21:30.011929                           [Byte1]: 53

 4129 12:21:30.012085  

 4130 12:21:30.015663  Final RX Vref Byte 0 = 61 to rank0

 4131 12:21:30.018781  Final RX Vref Byte 1 = 53 to rank0

 4132 12:21:30.022204  Final RX Vref Byte 0 = 61 to rank1

 4133 12:21:30.025424  Final RX Vref Byte 1 = 53 to rank1==

 4134 12:21:30.028999  Dram Type= 6, Freq= 0, CH_0, rank 0

 4135 12:21:30.032045  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4136 12:21:30.032201  ==

 4137 12:21:30.035530  DQS Delay:

 4138 12:21:30.035663  DQS0 = 0, DQS1 = 0

 4139 12:21:30.038562  DQM Delay:

 4140 12:21:30.038697  DQM0 = 36, DQM1 = 29

 4141 12:21:30.038818  DQ Delay:

 4142 12:21:30.042251  DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32

 4143 12:21:30.045409  DQ4 =36, DQ5 =24, DQ6 =40, DQ7 =48

 4144 12:21:30.048996  DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20

 4145 12:21:30.051850  DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36

 4146 12:21:30.051972  

 4147 12:21:30.052066  

 4148 12:21:30.062234  [DQSOSCAuto] RK0, (LSB)MR18= 0x4140, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps

 4149 12:21:30.065519  CH0 RK0: MR19=808, MR18=4140

 4150 12:21:30.071742  CH0_RK0: MR19=0x808, MR18=0x4140, DQSOSC=397, MR23=63, INC=166, DEC=110

 4151 12:21:30.071844  

 4152 12:21:30.074979  ----->DramcWriteLeveling(PI) begin...

 4153 12:21:30.075090  ==

 4154 12:21:30.078187  Dram Type= 6, Freq= 0, CH_0, rank 1

 4155 12:21:30.081807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4156 12:21:30.081896  ==

 4157 12:21:30.085065  Write leveling (Byte 0): 31 => 31

 4158 12:21:30.088229  Write leveling (Byte 1): 31 => 31

 4159 12:21:30.091954  DramcWriteLeveling(PI) end<-----

 4160 12:21:30.092038  

 4161 12:21:30.092124  ==

 4162 12:21:30.095202  Dram Type= 6, Freq= 0, CH_0, rank 1

 4163 12:21:30.098237  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4164 12:21:30.098321  ==

 4165 12:21:30.101876  [Gating] SW mode calibration

 4166 12:21:30.108164  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4167 12:21:30.114640  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4168 12:21:30.118283   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4169 12:21:30.121474   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4170 12:21:30.128549   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4171 12:21:30.131465   0  9 12 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)

 4172 12:21:30.134662   0  9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (0 0)

 4173 12:21:30.141417   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4174 12:21:30.144350   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4175 12:21:30.147891   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4176 12:21:30.154550   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4177 12:21:30.158036   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4178 12:21:30.161271   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4179 12:21:30.167797   0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)

 4180 12:21:30.170822   0 10 16 | B1->B0 | 3a3a 4545 | 1 1 | (0 0) (0 0)

 4181 12:21:30.174609   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4182 12:21:30.180906   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4183 12:21:30.184474   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4184 12:21:30.187537   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4185 12:21:30.194446   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4186 12:21:30.197700   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4187 12:21:30.201047   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4188 12:21:30.207687   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4189 12:21:30.210894   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4190 12:21:30.213965   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4191 12:21:30.220465   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4192 12:21:30.224221   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4193 12:21:30.227353   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4194 12:21:30.233822   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4195 12:21:30.236956   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4196 12:21:30.240793   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4197 12:21:30.247114   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4198 12:21:30.250611   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4199 12:21:30.253512   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4200 12:21:30.260384   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4201 12:21:30.263861   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4202 12:21:30.267149   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4203 12:21:30.274030   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4204 12:21:30.277275   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4205 12:21:30.280296  Total UI for P1: 0, mck2ui 16

 4206 12:21:30.284202  best dqsien dly found for B0: ( 0, 13, 12)

 4207 12:21:30.287093  Total UI for P1: 0, mck2ui 16

 4208 12:21:30.290574  best dqsien dly found for B1: ( 0, 13, 14)

 4209 12:21:30.293668  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4210 12:21:30.296688  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4211 12:21:30.296775  

 4212 12:21:30.300426  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4213 12:21:30.303546  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4214 12:21:30.306670  [Gating] SW calibration Done

 4215 12:21:30.306781  ==

 4216 12:21:30.310560  Dram Type= 6, Freq= 0, CH_0, rank 1

 4217 12:21:30.313598  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4218 12:21:30.313677  ==

 4219 12:21:30.316544  RX Vref Scan: 0

 4220 12:21:30.316635  

 4221 12:21:30.320314  RX Vref 0 -> 0, step: 1

 4222 12:21:30.320426  

 4223 12:21:30.323100  RX Delay -230 -> 252, step: 16

 4224 12:21:30.326804  iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336

 4225 12:21:30.330374  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4226 12:21:30.333461  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4227 12:21:30.336518  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4228 12:21:30.343222  iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336

 4229 12:21:30.346353  iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336

 4230 12:21:30.350058  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4231 12:21:30.353200  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4232 12:21:30.359572  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4233 12:21:30.363318  iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320

 4234 12:21:30.366265  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4235 12:21:30.369662  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4236 12:21:30.376318  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4237 12:21:30.379693  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4238 12:21:30.383176  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4239 12:21:30.386185  iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336

 4240 12:21:30.386303  ==

 4241 12:21:30.389852  Dram Type= 6, Freq= 0, CH_0, rank 1

 4242 12:21:30.396042  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4243 12:21:30.396138  ==

 4244 12:21:30.396206  DQS Delay:

 4245 12:21:30.399379  DQS0 = 0, DQS1 = 0

 4246 12:21:30.399498  DQM Delay:

 4247 12:21:30.399594  DQM0 = 36, DQM1 = 29

 4248 12:21:30.402967  DQ Delay:

 4249 12:21:30.406109  DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33

 4250 12:21:30.409322  DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49

 4251 12:21:30.412583  DQ8 =25, DQ9 =9, DQ10 =33, DQ11 =25

 4252 12:21:30.416265  DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33

 4253 12:21:30.416354  

 4254 12:21:30.416424  

 4255 12:21:30.416487  ==

 4256 12:21:30.419171  Dram Type= 6, Freq= 0, CH_0, rank 1

 4257 12:21:30.422800  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4258 12:21:30.422887  ==

 4259 12:21:30.422986  

 4260 12:21:30.423077  

 4261 12:21:30.425810  	TX Vref Scan disable

 4262 12:21:30.425894   == TX Byte 0 ==

 4263 12:21:30.432495  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4264 12:21:30.436050  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4265 12:21:30.439132   == TX Byte 1 ==

 4266 12:21:30.442255  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4267 12:21:30.445953  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4268 12:21:30.446039  ==

 4269 12:21:30.449076  Dram Type= 6, Freq= 0, CH_0, rank 1

 4270 12:21:30.452313  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4271 12:21:30.452407  ==

 4272 12:21:30.455658  

 4273 12:21:30.455744  

 4274 12:21:30.455809  	TX Vref Scan disable

 4275 12:21:30.459295   == TX Byte 0 ==

 4276 12:21:30.462421  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4277 12:21:30.466307  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4278 12:21:30.469442   == TX Byte 1 ==

 4279 12:21:30.472497  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4280 12:21:30.478939  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4281 12:21:30.479046  

 4282 12:21:30.479116  [DATLAT]

 4283 12:21:30.479177  Freq=600, CH0 RK1

 4284 12:21:30.479238  

 4285 12:21:30.482562  DATLAT Default: 0x9

 4286 12:21:30.482647  0, 0xFFFF, sum = 0

 4287 12:21:30.485948  1, 0xFFFF, sum = 0

 4288 12:21:30.486036  2, 0xFFFF, sum = 0

 4289 12:21:30.489157  3, 0xFFFF, sum = 0

 4290 12:21:30.492399  4, 0xFFFF, sum = 0

 4291 12:21:30.492493  5, 0xFFFF, sum = 0

 4292 12:21:30.495834  6, 0xFFFF, sum = 0

 4293 12:21:30.495948  7, 0xFFFF, sum = 0

 4294 12:21:30.498933  8, 0x0, sum = 1

 4295 12:21:30.499052  9, 0x0, sum = 2

 4296 12:21:30.499156  10, 0x0, sum = 3

 4297 12:21:30.502587  11, 0x0, sum = 4

 4298 12:21:30.502680  best_step = 9

 4299 12:21:30.502746  

 4300 12:21:30.502808  ==

 4301 12:21:30.505629  Dram Type= 6, Freq= 0, CH_0, rank 1

 4302 12:21:30.512057  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4303 12:21:30.512180  ==

 4304 12:21:30.512276  RX Vref Scan: 0

 4305 12:21:30.512366  

 4306 12:21:30.515647  RX Vref 0 -> 0, step: 1

 4307 12:21:30.515734  

 4308 12:21:30.518675  RX Delay -195 -> 252, step: 8

 4309 12:21:30.522313  iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312

 4310 12:21:30.529163  iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320

 4311 12:21:30.532240  iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312

 4312 12:21:30.535859  iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320

 4313 12:21:30.538811  iDelay=205, Bit 4, Center 28 (-131 ~ 188) 320

 4314 12:21:30.545517  iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312

 4315 12:21:30.548563  iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320

 4316 12:21:30.552414  iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320

 4317 12:21:30.555541  iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320

 4318 12:21:30.558643  iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320

 4319 12:21:30.565610  iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320

 4320 12:21:30.569087  iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320

 4321 12:21:30.571972  iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320

 4322 12:21:30.575016  iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320

 4323 12:21:30.581713  iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320

 4324 12:21:30.585074  iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320

 4325 12:21:30.585203  ==

 4326 12:21:30.588576  Dram Type= 6, Freq= 0, CH_0, rank 1

 4327 12:21:30.592138  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4328 12:21:30.592228  ==

 4329 12:21:30.595656  DQS Delay:

 4330 12:21:30.595743  DQS0 = 0, DQS1 = 0

 4331 12:21:30.595810  DQM Delay:

 4332 12:21:30.598967  DQM0 = 33, DQM1 = 28

 4333 12:21:30.599048  DQ Delay:

 4334 12:21:30.601636  DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28

 4335 12:21:30.605294  DQ4 =28, DQ5 =24, DQ6 =44, DQ7 =44

 4336 12:21:30.608277  DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20

 4337 12:21:30.611939  DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36

 4338 12:21:30.612036  

 4339 12:21:30.612101  

 4340 12:21:30.621889  [DQSOSCAuto] RK1, (LSB)MR18= 0x6c3b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 389 ps

 4341 12:21:30.625128  CH0 RK1: MR19=808, MR18=6C3B

 4342 12:21:30.628133  CH0_RK1: MR19=0x808, MR18=0x6C3B, DQSOSC=389, MR23=63, INC=173, DEC=115

 4343 12:21:30.631660  [RxdqsGatingPostProcess] freq 600

 4344 12:21:30.638198  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4345 12:21:30.641656  Pre-setting of DQS Precalculation

 4346 12:21:30.645622  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4347 12:21:30.645721  ==

 4348 12:21:30.648393  Dram Type= 6, Freq= 0, CH_1, rank 0

 4349 12:21:30.654977  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4350 12:21:30.655086  ==

 4351 12:21:30.658233  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4352 12:21:30.664455  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 4353 12:21:30.668272  [CA 0] Center 36 (6~66) winsize 61

 4354 12:21:30.671293  [CA 1] Center 36 (6~66) winsize 61

 4355 12:21:30.675073  [CA 2] Center 34 (4~65) winsize 62

 4356 12:21:30.678136  [CA 3] Center 34 (4~65) winsize 62

 4357 12:21:30.681693  [CA 4] Center 34 (4~65) winsize 62

 4358 12:21:30.684946  [CA 5] Center 34 (4~64) winsize 61

 4359 12:21:30.685026  

 4360 12:21:30.687965  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 4361 12:21:30.688069  

 4362 12:21:30.691592  [CATrainingPosCal] consider 1 rank data

 4363 12:21:30.694969  u2DelayCellTimex100 = 270/100 ps

 4364 12:21:30.697930  CA0 delay=36 (6~66),Diff = 2 PI (19 cell)

 4365 12:21:30.705213  CA1 delay=36 (6~66),Diff = 2 PI (19 cell)

 4366 12:21:30.708015  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4367 12:21:30.711584  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4368 12:21:30.714571  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4369 12:21:30.718259  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 4370 12:21:30.718416  

 4371 12:21:30.721092  CA PerBit enable=1, Macro0, CA PI delay=34

 4372 12:21:30.721182  

 4373 12:21:30.725014  [CBTSetCACLKResult] CA Dly = 34

 4374 12:21:30.725095  CS Dly: 4 (0~35)

 4375 12:21:30.728188  ==

 4376 12:21:30.731344  Dram Type= 6, Freq= 0, CH_1, rank 1

 4377 12:21:30.734430  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4378 12:21:30.734515  ==

 4379 12:21:30.738177  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4380 12:21:30.744171  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 4381 12:21:30.748387  [CA 0] Center 35 (5~66) winsize 62

 4382 12:21:30.751491  [CA 1] Center 35 (5~66) winsize 62

 4383 12:21:30.754730  [CA 2] Center 34 (4~65) winsize 62

 4384 12:21:30.758221  [CA 3] Center 34 (3~65) winsize 63

 4385 12:21:30.761740  [CA 4] Center 34 (4~65) winsize 62

 4386 12:21:30.764726  [CA 5] Center 33 (3~64) winsize 62

 4387 12:21:30.764814  

 4388 12:21:30.767950  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 4389 12:21:30.768033  

 4390 12:21:30.771631  [CATrainingPosCal] consider 2 rank data

 4391 12:21:30.774669  u2DelayCellTimex100 = 270/100 ps

 4392 12:21:30.777962  CA0 delay=36 (6~66),Diff = 2 PI (19 cell)

 4393 12:21:30.784607  CA1 delay=36 (6~66),Diff = 2 PI (19 cell)

 4394 12:21:30.788371  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4395 12:21:30.791341  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4396 12:21:30.794508  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4397 12:21:30.798111  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 4398 12:21:30.798222  

 4399 12:21:30.801135  CA PerBit enable=1, Macro0, CA PI delay=34

 4400 12:21:30.801225  

 4401 12:21:30.804414  [CBTSetCACLKResult] CA Dly = 34

 4402 12:21:30.807830  CS Dly: 5 (0~37)

 4403 12:21:30.807918  

 4404 12:21:30.810951  ----->DramcWriteLeveling(PI) begin...

 4405 12:21:30.811060  ==

 4406 12:21:30.814468  Dram Type= 6, Freq= 0, CH_1, rank 0

 4407 12:21:30.817977  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4408 12:21:30.818091  ==

 4409 12:21:30.821149  Write leveling (Byte 0): 29 => 29

 4410 12:21:30.824615  Write leveling (Byte 1): 29 => 29

 4411 12:21:30.827979  DramcWriteLeveling(PI) end<-----

 4412 12:21:30.828072  

 4413 12:21:30.828166  ==

 4414 12:21:30.830865  Dram Type= 6, Freq= 0, CH_1, rank 0

 4415 12:21:30.834567  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4416 12:21:30.834657  ==

 4417 12:21:30.837586  [Gating] SW mode calibration

 4418 12:21:30.844527  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4419 12:21:30.851157  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4420 12:21:30.854364   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4421 12:21:30.858044   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4422 12:21:30.864654   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4423 12:21:30.867393   0  9 12 | B1->B0 | 3030 3030 | 1 0 | (1 0) (0 1)

 4424 12:21:30.871115   0  9 16 | B1->B0 | 2b2b 2626 | 0 0 | (0 0) (0 0)

 4425 12:21:30.877440   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4426 12:21:30.880706   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4427 12:21:30.884103   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4428 12:21:30.891109   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4429 12:21:30.894262   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4430 12:21:30.897516   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4431 12:21:30.903891   0 10 12 | B1->B0 | 302f 3131 | 1 0 | (1 1) (0 0)

 4432 12:21:30.907363   0 10 16 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)

 4433 12:21:30.910715   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4434 12:21:30.917328   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4435 12:21:30.920772   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4436 12:21:30.924407   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4437 12:21:30.927490   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4438 12:21:30.933791   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4439 12:21:30.937506   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4440 12:21:30.940319   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4441 12:21:30.947490   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4442 12:21:30.950543   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4443 12:21:30.954050   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4444 12:21:30.960111   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4445 12:21:30.963725   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4446 12:21:30.966726   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4447 12:21:30.973901   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4448 12:21:30.977093   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4449 12:21:30.980393   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4450 12:21:30.987075   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4451 12:21:30.990145   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4452 12:21:30.993381   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4453 12:21:31.000103   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4454 12:21:31.003305   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4455 12:21:31.007039   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4456 12:21:31.013249   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 4457 12:21:31.013339  Total UI for P1: 0, mck2ui 16

 4458 12:21:31.020085  best dqsien dly found for B1: ( 0, 13, 12)

 4459 12:21:31.023355   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4460 12:21:31.026661  Total UI for P1: 0, mck2ui 16

 4461 12:21:31.029897  best dqsien dly found for B0: ( 0, 13, 14)

 4462 12:21:31.033343  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4463 12:21:31.036504  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4464 12:21:31.036590  

 4465 12:21:31.040129  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4466 12:21:31.043200  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4467 12:21:31.046762  [Gating] SW calibration Done

 4468 12:21:31.046852  ==

 4469 12:21:31.049712  Dram Type= 6, Freq= 0, CH_1, rank 0

 4470 12:21:31.053334  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4471 12:21:31.056834  ==

 4472 12:21:31.056921  RX Vref Scan: 0

 4473 12:21:31.056989  

 4474 12:21:31.060026  RX Vref 0 -> 0, step: 1

 4475 12:21:31.060116  

 4476 12:21:31.063669  RX Delay -230 -> 252, step: 16

 4477 12:21:31.066633  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4478 12:21:31.069784  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4479 12:21:31.073434  iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352

 4480 12:21:31.080065  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4481 12:21:31.083374  iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336

 4482 12:21:31.086451  iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336

 4483 12:21:31.090244  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4484 12:21:31.093320  iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336

 4485 12:21:31.099750  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4486 12:21:31.103286  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4487 12:21:31.106540  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4488 12:21:31.109622  iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352

 4489 12:21:31.116359  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4490 12:21:31.119527  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4491 12:21:31.123140  iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336

 4492 12:21:31.126238  iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336

 4493 12:21:31.126324  ==

 4494 12:21:31.129647  Dram Type= 6, Freq= 0, CH_1, rank 0

 4495 12:21:31.136021  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4496 12:21:31.136121  ==

 4497 12:21:31.136207  DQS Delay:

 4498 12:21:31.139476  DQS0 = 0, DQS1 = 0

 4499 12:21:31.139563  DQM Delay:

 4500 12:21:31.143033  DQM0 = 40, DQM1 = 28

 4501 12:21:31.143118  DQ Delay:

 4502 12:21:31.146112  DQ0 =57, DQ1 =33, DQ2 =25, DQ3 =33

 4503 12:21:31.149220  DQ4 =33, DQ5 =49, DQ6 =57, DQ7 =33

 4504 12:21:31.152438  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25

 4505 12:21:31.156090  DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33

 4506 12:21:31.156181  

 4507 12:21:31.156276  

 4508 12:21:31.156358  ==

 4509 12:21:31.159531  Dram Type= 6, Freq= 0, CH_1, rank 0

 4510 12:21:31.162805  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4511 12:21:31.162900  ==

 4512 12:21:31.162986  

 4513 12:21:31.163069  

 4514 12:21:31.165878  	TX Vref Scan disable

 4515 12:21:31.169140   == TX Byte 0 ==

 4516 12:21:31.172840  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4517 12:21:31.175955  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4518 12:21:31.179151   == TX Byte 1 ==

 4519 12:21:31.182317  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4520 12:21:31.186006  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4521 12:21:31.186090  ==

 4522 12:21:31.189043  Dram Type= 6, Freq= 0, CH_1, rank 0

 4523 12:21:31.192414  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4524 12:21:31.195871  ==

 4525 12:21:31.195985  

 4526 12:21:31.196091  

 4527 12:21:31.196191  	TX Vref Scan disable

 4528 12:21:31.199968   == TX Byte 0 ==

 4529 12:21:31.202876  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4530 12:21:31.209709  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4531 12:21:31.209858   == TX Byte 1 ==

 4532 12:21:31.212917  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4533 12:21:31.219489  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4534 12:21:31.219603  

 4535 12:21:31.219695  [DATLAT]

 4536 12:21:31.219790  Freq=600, CH1 RK0

 4537 12:21:31.219879  

 4538 12:21:31.222716  DATLAT Default: 0x9

 4539 12:21:31.222800  0, 0xFFFF, sum = 0

 4540 12:21:31.226448  1, 0xFFFF, sum = 0

 4541 12:21:31.226534  2, 0xFFFF, sum = 0

 4542 12:21:31.229493  3, 0xFFFF, sum = 0

 4543 12:21:31.232686  4, 0xFFFF, sum = 0

 4544 12:21:31.232772  5, 0xFFFF, sum = 0

 4545 12:21:31.236215  6, 0xFFFF, sum = 0

 4546 12:21:31.236300  7, 0xFFFF, sum = 0

 4547 12:21:31.239402  8, 0x0, sum = 1

 4548 12:21:31.239518  9, 0x0, sum = 2

 4549 12:21:31.239591  10, 0x0, sum = 3

 4550 12:21:31.242497  11, 0x0, sum = 4

 4551 12:21:31.242583  best_step = 9

 4552 12:21:31.242650  

 4553 12:21:31.242709  ==

 4554 12:21:31.245998  Dram Type= 6, Freq= 0, CH_1, rank 0

 4555 12:21:31.252549  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4556 12:21:31.252655  ==

 4557 12:21:31.252744  RX Vref Scan: 1

 4558 12:21:31.252847  

 4559 12:21:31.256067  RX Vref 0 -> 0, step: 1

 4560 12:21:31.256152  

 4561 12:21:31.259252  RX Delay -195 -> 252, step: 8

 4562 12:21:31.259365  

 4563 12:21:31.262897  Set Vref, RX VrefLevel [Byte0]: 54

 4564 12:21:31.265995                           [Byte1]: 52

 4565 12:21:31.266105  

 4566 12:21:31.269480  Final RX Vref Byte 0 = 54 to rank0

 4567 12:21:31.272353  Final RX Vref Byte 1 = 52 to rank0

 4568 12:21:31.275929  Final RX Vref Byte 0 = 54 to rank1

 4569 12:21:31.278946  Final RX Vref Byte 1 = 52 to rank1==

 4570 12:21:31.282565  Dram Type= 6, Freq= 0, CH_1, rank 0

 4571 12:21:31.285869  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4572 12:21:31.285961  ==

 4573 12:21:31.289122  DQS Delay:

 4574 12:21:31.289204  DQS0 = 0, DQS1 = 0

 4575 12:21:31.292226  DQM Delay:

 4576 12:21:31.292319  DQM0 = 38, DQM1 = 27

 4577 12:21:31.292391  DQ Delay:

 4578 12:21:31.295927  DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36

 4579 12:21:31.299070  DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36

 4580 12:21:31.302458  DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20

 4581 12:21:31.305602  DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36

 4582 12:21:31.305832  

 4583 12:21:31.305920  

 4584 12:21:31.315351  [DQSOSCAuto] RK0, (LSB)MR18= 0x2532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps

 4585 12:21:31.319084  CH1 RK0: MR19=808, MR18=2532

 4586 12:21:31.325919  CH1_RK0: MR19=0x808, MR18=0x2532, DQSOSC=400, MR23=63, INC=163, DEC=109

 4587 12:21:31.326021  

 4588 12:21:31.328700  ----->DramcWriteLeveling(PI) begin...

 4589 12:21:31.328785  ==

 4590 12:21:31.332427  Dram Type= 6, Freq= 0, CH_1, rank 1

 4591 12:21:31.335798  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4592 12:21:31.335888  ==

 4593 12:21:31.338730  Write leveling (Byte 0): 28 => 28

 4594 12:21:31.342375  Write leveling (Byte 1): 32 => 32

 4595 12:21:31.345554  DramcWriteLeveling(PI) end<-----

 4596 12:21:31.345639  

 4597 12:21:31.345704  ==

 4598 12:21:31.348643  Dram Type= 6, Freq= 0, CH_1, rank 1

 4599 12:21:31.352038  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4600 12:21:31.352132  ==

 4601 12:21:31.355611  [Gating] SW mode calibration

 4602 12:21:31.361764  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4603 12:21:31.368682  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4604 12:21:31.371632   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4605 12:21:31.375354   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4606 12:21:31.381905   0  9  8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)

 4607 12:21:31.385392   0  9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (0 0)

 4608 12:21:31.388271   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4609 12:21:31.395087   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4610 12:21:31.398316   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4611 12:21:31.401430   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4612 12:21:31.408344   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4613 12:21:31.411750   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4614 12:21:31.415055   0 10  8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 4615 12:21:31.421599   0 10 12 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)

 4616 12:21:31.424888   0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 4617 12:21:31.427923   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4618 12:21:31.434811   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4619 12:21:31.437939   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4620 12:21:31.441467   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4621 12:21:31.448039   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4622 12:21:31.451499   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4623 12:21:31.454631   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4624 12:21:31.461245   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4625 12:21:31.464919   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4626 12:21:31.467717   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4627 12:21:31.474908   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4628 12:21:31.477917   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4629 12:21:31.481057   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4630 12:21:31.487899   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4631 12:21:31.491306   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4632 12:21:31.494734   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4633 12:21:31.497626   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4634 12:21:31.504454   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4635 12:21:31.507655   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4636 12:21:31.511290   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4637 12:21:31.517961   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4638 12:21:31.520768   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4639 12:21:31.524159   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4640 12:21:31.530834   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4641 12:21:31.533970  Total UI for P1: 0, mck2ui 16

 4642 12:21:31.537717  best dqsien dly found for B0: ( 0, 13, 10)

 4643 12:21:31.540901  Total UI for P1: 0, mck2ui 16

 4644 12:21:31.544288  best dqsien dly found for B1: ( 0, 13, 14)

 4645 12:21:31.547294  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4646 12:21:31.550927  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4647 12:21:31.551009  

 4648 12:21:31.553863  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4649 12:21:31.557367  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4650 12:21:31.560562  [Gating] SW calibration Done

 4651 12:21:31.560646  ==

 4652 12:21:31.564140  Dram Type= 6, Freq= 0, CH_1, rank 1

 4653 12:21:31.567021  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4654 12:21:31.567114  ==

 4655 12:21:31.570689  RX Vref Scan: 0

 4656 12:21:31.570775  

 4657 12:21:31.574157  RX Vref 0 -> 0, step: 1

 4658 12:21:31.574241  

 4659 12:21:31.574307  RX Delay -230 -> 252, step: 16

 4660 12:21:31.580816  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4661 12:21:31.584005  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4662 12:21:31.587205  iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336

 4663 12:21:31.590416  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4664 12:21:31.597033  iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336

 4665 12:21:31.600416  iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336

 4666 12:21:31.603920  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4667 12:21:31.607362  iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336

 4668 12:21:31.610648  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4669 12:21:31.617437  iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352

 4670 12:21:31.620502  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4671 12:21:31.624213  iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352

 4672 12:21:31.627181  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4673 12:21:31.633815  iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352

 4674 12:21:31.637317  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4675 12:21:31.640430  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4676 12:21:31.640540  ==

 4677 12:21:31.643556  Dram Type= 6, Freq= 0, CH_1, rank 1

 4678 12:21:31.647250  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4679 12:21:31.650333  ==

 4680 12:21:31.650452  DQS Delay:

 4681 12:21:31.650535  DQS0 = 0, DQS1 = 0

 4682 12:21:31.653690  DQM Delay:

 4683 12:21:31.653801  DQM0 = 36, DQM1 = 32

 4684 12:21:31.656840  DQ Delay:

 4685 12:21:31.656946  DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33

 4686 12:21:31.660386  DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33

 4687 12:21:31.663376  DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25

 4688 12:21:31.667228  DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41

 4689 12:21:31.670654  

 4690 12:21:31.670746  

 4691 12:21:31.670810  ==

 4692 12:21:31.673517  Dram Type= 6, Freq= 0, CH_1, rank 1

 4693 12:21:31.676804  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4694 12:21:31.676922  ==

 4695 12:21:31.677049  

 4696 12:21:31.677139  

 4697 12:21:31.680175  	TX Vref Scan disable

 4698 12:21:31.680277   == TX Byte 0 ==

 4699 12:21:31.686489  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4700 12:21:31.690108  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4701 12:21:31.690208   == TX Byte 1 ==

 4702 12:21:31.696751  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4703 12:21:31.699873  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4704 12:21:31.699995  ==

 4705 12:21:31.703068  Dram Type= 6, Freq= 0, CH_1, rank 1

 4706 12:21:31.706711  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4707 12:21:31.706819  ==

 4708 12:21:31.706886  

 4709 12:21:31.706947  

 4710 12:21:31.709538  	TX Vref Scan disable

 4711 12:21:31.713220   == TX Byte 0 ==

 4712 12:21:31.716416  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4713 12:21:31.723364  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4714 12:21:31.723499   == TX Byte 1 ==

 4715 12:21:31.726405  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4716 12:21:31.730199  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4717 12:21:31.733567  

 4718 12:21:31.733695  [DATLAT]

 4719 12:21:31.733797  Freq=600, CH1 RK1

 4720 12:21:31.733888  

 4721 12:21:31.736479  DATLAT Default: 0x9

 4722 12:21:31.736586  0, 0xFFFF, sum = 0

 4723 12:21:31.740011  1, 0xFFFF, sum = 0

 4724 12:21:31.740117  2, 0xFFFF, sum = 0

 4725 12:21:31.742917  3, 0xFFFF, sum = 0

 4726 12:21:31.743029  4, 0xFFFF, sum = 0

 4727 12:21:31.746547  5, 0xFFFF, sum = 0

 4728 12:21:31.749553  6, 0xFFFF, sum = 0

 4729 12:21:31.749777  7, 0xFFFF, sum = 0

 4730 12:21:31.749940  8, 0x0, sum = 1

 4731 12:21:31.753340  9, 0x0, sum = 2

 4732 12:21:31.753461  10, 0x0, sum = 3

 4733 12:21:31.756533  11, 0x0, sum = 4

 4734 12:21:31.756646  best_step = 9

 4735 12:21:31.756761  

 4736 12:21:31.756868  ==

 4737 12:21:31.759760  Dram Type= 6, Freq= 0, CH_1, rank 1

 4738 12:21:31.766570  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4739 12:21:31.766660  ==

 4740 12:21:31.766725  RX Vref Scan: 0

 4741 12:21:31.766785  

 4742 12:21:31.769647  RX Vref 0 -> 0, step: 1

 4743 12:21:31.769751  

 4744 12:21:31.772770  RX Delay -195 -> 252, step: 8

 4745 12:21:31.776543  iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312

 4746 12:21:31.782560  iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312

 4747 12:21:31.786220  iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312

 4748 12:21:31.789270  iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312

 4749 12:21:31.792744  iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320

 4750 12:21:31.799169  iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312

 4751 12:21:31.802390  iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312

 4752 12:21:31.805901  iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312

 4753 12:21:31.809021  iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328

 4754 12:21:31.812598  iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320

 4755 12:21:31.819373  iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320

 4756 12:21:31.822359  iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320

 4757 12:21:31.825975  iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320

 4758 12:21:31.829116  iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320

 4759 12:21:31.835999  iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320

 4760 12:21:31.838840  iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320

 4761 12:21:31.838950  ==

 4762 12:21:31.842471  Dram Type= 6, Freq= 0, CH_1, rank 1

 4763 12:21:31.845942  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4764 12:21:31.846069  ==

 4765 12:21:31.848910  DQS Delay:

 4766 12:21:31.849046  DQS0 = 0, DQS1 = 0

 4767 12:21:31.852525  DQM Delay:

 4768 12:21:31.852643  DQM0 = 36, DQM1 = 29

 4769 12:21:31.852746  DQ Delay:

 4770 12:21:31.855827  DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32

 4771 12:21:31.858947  DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32

 4772 12:21:31.862079  DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20

 4773 12:21:31.865374  DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36

 4774 12:21:31.865490  

 4775 12:21:31.865585  

 4776 12:21:31.875277  [DQSOSCAuto] RK1, (LSB)MR18= 0x3453, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps

 4777 12:21:31.879054  CH1 RK1: MR19=808, MR18=3453

 4778 12:21:31.882129  CH1_RK1: MR19=0x808, MR18=0x3453, DQSOSC=394, MR23=63, INC=168, DEC=112

 4779 12:21:31.885641  [RxdqsGatingPostProcess] freq 600

 4780 12:21:31.892180  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4781 12:21:31.895253  Pre-setting of DQS Precalculation

 4782 12:21:31.898945  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4783 12:21:31.908801  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4784 12:21:31.915328  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4785 12:21:31.915455  

 4786 12:21:31.915529  

 4787 12:21:31.918892  [Calibration Summary] 1200 Mbps

 4788 12:21:31.918985  CH 0, Rank 0

 4789 12:21:31.921943  SW Impedance     : PASS

 4790 12:21:31.922030  DUTY Scan        : NO K

 4791 12:21:31.925360  ZQ Calibration   : PASS

 4792 12:21:31.929039  Jitter Meter     : NO K

 4793 12:21:31.929129  CBT Training     : PASS

 4794 12:21:31.932188  Write leveling   : PASS

 4795 12:21:31.935322  RX DQS gating    : PASS

 4796 12:21:31.935435  RX DQ/DQS(RDDQC) : PASS

 4797 12:21:31.938784  TX DQ/DQS        : PASS

 4798 12:21:31.941852  RX DATLAT        : PASS

 4799 12:21:31.941947  RX DQ/DQS(Engine): PASS

 4800 12:21:31.945196  TX OE            : NO K

 4801 12:21:31.945314  All Pass.

 4802 12:21:31.945410  

 4803 12:21:31.948499  CH 0, Rank 1

 4804 12:21:31.948589  SW Impedance     : PASS

 4805 12:21:31.952160  DUTY Scan        : NO K

 4806 12:21:31.952255  ZQ Calibration   : PASS

 4807 12:21:31.955529  Jitter Meter     : NO K

 4808 12:21:31.958860  CBT Training     : PASS

 4809 12:21:31.958956  Write leveling   : PASS

 4810 12:21:31.961781  RX DQS gating    : PASS

 4811 12:21:31.965503  RX DQ/DQS(RDDQC) : PASS

 4812 12:21:31.965602  TX DQ/DQS        : PASS

 4813 12:21:31.968551  RX DATLAT        : PASS

 4814 12:21:31.971720  RX DQ/DQS(Engine): PASS

 4815 12:21:31.971842  TX OE            : NO K

 4816 12:21:31.974965  All Pass.

 4817 12:21:31.975081  

 4818 12:21:31.975177  CH 1, Rank 0

 4819 12:21:31.978550  SW Impedance     : PASS

 4820 12:21:31.978631  DUTY Scan        : NO K

 4821 12:21:31.981627  ZQ Calibration   : PASS

 4822 12:21:31.984944  Jitter Meter     : NO K

 4823 12:21:31.985044  CBT Training     : PASS

 4824 12:21:31.988380  Write leveling   : PASS

 4825 12:21:31.991952  RX DQS gating    : PASS

 4826 12:21:31.992066  RX DQ/DQS(RDDQC) : PASS

 4827 12:21:31.994920  TX DQ/DQS        : PASS

 4828 12:21:31.998104  RX DATLAT        : PASS

 4829 12:21:31.998196  RX DQ/DQS(Engine): PASS

 4830 12:21:32.001810  TX OE            : NO K

 4831 12:21:32.001904  All Pass.

 4832 12:21:32.001995  

 4833 12:21:32.004925  CH 1, Rank 1

 4834 12:21:32.005032  SW Impedance     : PASS

 4835 12:21:32.007939  DUTY Scan        : NO K

 4836 12:21:32.008015  ZQ Calibration   : PASS

 4837 12:21:32.011632  Jitter Meter     : NO K

 4838 12:21:32.014638  CBT Training     : PASS

 4839 12:21:32.014744  Write leveling   : PASS

 4840 12:21:32.018296  RX DQS gating    : PASS

 4841 12:21:32.021650  RX DQ/DQS(RDDQC) : PASS

 4842 12:21:32.021762  TX DQ/DQS        : PASS

 4843 12:21:32.024877  RX DATLAT        : PASS

 4844 12:21:32.028111  RX DQ/DQS(Engine): PASS

 4845 12:21:32.028193  TX OE            : NO K

 4846 12:21:32.031155  All Pass.

 4847 12:21:32.031234  

 4848 12:21:32.031316  DramC Write-DBI off

 4849 12:21:32.034897  	PER_BANK_REFRESH: Hybrid Mode

 4850 12:21:32.037929  TX_TRACKING: ON

 4851 12:21:32.044585  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4852 12:21:32.048025  [FAST_K] Save calibration result to emmc

 4853 12:21:32.051282  dramc_set_vcore_voltage set vcore to 662500

 4854 12:21:32.054441  Read voltage for 933, 3

 4855 12:21:32.054533  Vio18 = 0

 4856 12:21:32.057720  Vcore = 662500

 4857 12:21:32.057803  Vdram = 0

 4858 12:21:32.057890  Vddq = 0

 4859 12:21:32.061422  Vmddr = 0

 4860 12:21:32.064571  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4861 12:21:32.071162  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4862 12:21:32.071274  MEM_TYPE=3, freq_sel=17

 4863 12:21:32.074721  sv_algorithm_assistance_LP4_1600 

 4864 12:21:32.081026  ============ PULL DRAM RESETB DOWN ============

 4865 12:21:32.084734  ========== PULL DRAM RESETB DOWN end =========

 4866 12:21:32.087892  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4867 12:21:32.091414  =================================== 

 4868 12:21:32.094355  LPDDR4 DRAM CONFIGURATION

 4869 12:21:32.097787  =================================== 

 4870 12:21:32.097911  EX_ROW_EN[0]    = 0x0

 4871 12:21:32.101190  EX_ROW_EN[1]    = 0x0

 4872 12:21:32.104371  LP4Y_EN      = 0x0

 4873 12:21:32.104459  WORK_FSP     = 0x0

 4874 12:21:32.107495  WL           = 0x3

 4875 12:21:32.107618  RL           = 0x3

 4876 12:21:32.110816  BL           = 0x2

 4877 12:21:32.110945  RPST         = 0x0

 4878 12:21:32.114404  RD_PRE       = 0x0

 4879 12:21:32.114513  WR_PRE       = 0x1

 4880 12:21:32.117542  WR_PST       = 0x0

 4881 12:21:32.117626  DBI_WR       = 0x0

 4882 12:21:32.121218  DBI_RD       = 0x0

 4883 12:21:32.121329  OTF          = 0x1

 4884 12:21:32.124295  =================================== 

 4885 12:21:32.127262  =================================== 

 4886 12:21:32.130958  ANA top config

 4887 12:21:32.134054  =================================== 

 4888 12:21:32.134164  DLL_ASYNC_EN            =  0

 4889 12:21:32.137717  ALL_SLAVE_EN            =  1

 4890 12:21:32.140849  NEW_RANK_MODE           =  1

 4891 12:21:32.144009  DLL_IDLE_MODE           =  1

 4892 12:21:32.147821  LP45_APHY_COMB_EN       =  1

 4893 12:21:32.147909  TX_ODT_DIS              =  1

 4894 12:21:32.150891  NEW_8X_MODE             =  1

 4895 12:21:32.153959  =================================== 

 4896 12:21:32.157686  =================================== 

 4897 12:21:32.160939  data_rate                  = 1866

 4898 12:21:32.164096  CKR                        = 1

 4899 12:21:32.167064  DQ_P2S_RATIO               = 8

 4900 12:21:32.170755  =================================== 

 4901 12:21:32.173874  CA_P2S_RATIO               = 8

 4902 12:21:32.174001  DQ_CA_OPEN                 = 0

 4903 12:21:32.176990  DQ_SEMI_OPEN               = 0

 4904 12:21:32.180483  CA_SEMI_OPEN               = 0

 4905 12:21:32.183801  CA_FULL_RATE               = 0

 4906 12:21:32.187077  DQ_CKDIV4_EN               = 1

 4907 12:21:32.190220  CA_CKDIV4_EN               = 1

 4908 12:21:32.190338  CA_PREDIV_EN               = 0

 4909 12:21:32.193483  PH8_DLY                    = 0

 4910 12:21:32.196979  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4911 12:21:32.200617  DQ_AAMCK_DIV               = 4

 4912 12:21:32.203555  CA_AAMCK_DIV               = 4

 4913 12:21:32.206987  CA_ADMCK_DIV               = 4

 4914 12:21:32.207076  DQ_TRACK_CA_EN             = 0

 4915 12:21:32.209973  CA_PICK                    = 933

 4916 12:21:32.213869  CA_MCKIO                   = 933

 4917 12:21:32.216857  MCKIO_SEMI                 = 0

 4918 12:21:32.219858  PLL_FREQ                   = 3732

 4919 12:21:32.223701  DQ_UI_PI_RATIO             = 32

 4920 12:21:32.226758  CA_UI_PI_RATIO             = 0

 4921 12:21:32.230371  =================================== 

 4922 12:21:32.233216  =================================== 

 4923 12:21:32.233313  memory_type:LPDDR4         

 4924 12:21:32.236899  GP_NUM     : 10       

 4925 12:21:32.240089  SRAM_EN    : 1       

 4926 12:21:32.240174  MD32_EN    : 0       

 4927 12:21:32.243187  =================================== 

 4928 12:21:32.246386  [ANA_INIT] >>>>>>>>>>>>>> 

 4929 12:21:32.250238  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4930 12:21:32.253036  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4931 12:21:32.256770  =================================== 

 4932 12:21:32.260043  data_rate = 1866,PCW = 0X8f00

 4933 12:21:32.263566  =================================== 

 4934 12:21:32.266339  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4935 12:21:32.269954  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4936 12:21:32.276667  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4937 12:21:32.279875  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4938 12:21:32.283025  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4939 12:21:32.286094  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4940 12:21:32.289805  [ANA_INIT] flow start 

 4941 12:21:32.292753  [ANA_INIT] PLL >>>>>>>> 

 4942 12:21:32.292852  [ANA_INIT] PLL <<<<<<<< 

 4943 12:21:32.296334  [ANA_INIT] MIDPI >>>>>>>> 

 4944 12:21:32.299663  [ANA_INIT] MIDPI <<<<<<<< 

 4945 12:21:32.302972  [ANA_INIT] DLL >>>>>>>> 

 4946 12:21:32.303096  [ANA_INIT] flow end 

 4947 12:21:32.307398  ============ LP4 DIFF to SE enter ============

 4948 12:21:32.312538  ============ LP4 DIFF to SE exit  ============

 4949 12:21:32.312656  [ANA_INIT] <<<<<<<<<<<<< 

 4950 12:21:32.316208  [Flow] Enable top DCM control >>>>> 

 4951 12:21:32.319214  [Flow] Enable top DCM control <<<<< 

 4952 12:21:32.322835  Enable DLL master slave shuffle 

 4953 12:21:32.329485  ============================================================== 

 4954 12:21:32.329592  Gating Mode config

 4955 12:21:32.336392  ============================================================== 

 4956 12:21:32.339220  Config description: 

 4957 12:21:32.349255  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4958 12:21:32.355903  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4959 12:21:32.358959  SELPH_MODE            0: By rank         1: By Phase 

 4960 12:21:32.365811  ============================================================== 

 4961 12:21:32.369330  GAT_TRACK_EN                 =  1

 4962 12:21:32.369460  RX_GATING_MODE               =  2

 4963 12:21:32.372394  RX_GATING_TRACK_MODE         =  2

 4964 12:21:32.375838  SELPH_MODE                   =  1

 4965 12:21:32.378905  PICG_EARLY_EN                =  1

 4966 12:21:32.382412  VALID_LAT_VALUE              =  1

 4967 12:21:32.388732  ============================================================== 

 4968 12:21:32.392159  Enter into Gating configuration >>>> 

 4969 12:21:32.395671  Exit from Gating configuration <<<< 

 4970 12:21:32.398937  Enter into  DVFS_PRE_config >>>>> 

 4971 12:21:32.408634  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 4972 12:21:32.412245  Exit from  DVFS_PRE_config <<<<< 

 4973 12:21:32.415745  Enter into PICG configuration >>>> 

 4974 12:21:32.418895  Exit from PICG configuration <<<< 

 4975 12:21:32.422011  [RX_INPUT] configuration >>>>> 

 4976 12:21:32.425581  [RX_INPUT] configuration <<<<< 

 4977 12:21:32.428850  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 4978 12:21:32.435671  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 4979 12:21:32.442473  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 4980 12:21:32.445460  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 4981 12:21:32.452424  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 4982 12:21:32.458454  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 4983 12:21:32.462158  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 4984 12:21:32.468821  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 4985 12:21:32.471756  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 4986 12:21:32.475324  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 4987 12:21:32.478333  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 4988 12:21:32.484918  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4989 12:21:32.488398  =================================== 

 4990 12:21:32.488498  LPDDR4 DRAM CONFIGURATION

 4991 12:21:32.491436  =================================== 

 4992 12:21:32.495214  EX_ROW_EN[0]    = 0x0

 4993 12:21:32.498246  EX_ROW_EN[1]    = 0x0

 4994 12:21:32.498358  LP4Y_EN      = 0x0

 4995 12:21:32.502083  WORK_FSP     = 0x0

 4996 12:21:32.502171  WL           = 0x3

 4997 12:21:32.505035  RL           = 0x3

 4998 12:21:32.505139  BL           = 0x2

 4999 12:21:32.508540  RPST         = 0x0

 5000 12:21:32.508658  RD_PRE       = 0x0

 5001 12:21:32.511704  WR_PRE       = 0x1

 5002 12:21:32.511821  WR_PST       = 0x0

 5003 12:21:32.514839  DBI_WR       = 0x0

 5004 12:21:32.514933  DBI_RD       = 0x0

 5005 12:21:32.518026  OTF          = 0x1

 5006 12:21:32.521633  =================================== 

 5007 12:21:32.524798  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5008 12:21:32.528411  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5009 12:21:32.534740  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5010 12:21:32.537865  =================================== 

 5011 12:21:32.537955  LPDDR4 DRAM CONFIGURATION

 5012 12:21:32.541476  =================================== 

 5013 12:21:32.544422  EX_ROW_EN[0]    = 0x10

 5014 12:21:32.547800  EX_ROW_EN[1]    = 0x0

 5015 12:21:32.547886  LP4Y_EN      = 0x0

 5016 12:21:32.551333  WORK_FSP     = 0x0

 5017 12:21:32.551439  WL           = 0x3

 5018 12:21:32.554444  RL           = 0x3

 5019 12:21:32.554526  BL           = 0x2

 5020 12:21:32.557917  RPST         = 0x0

 5021 12:21:32.558000  RD_PRE       = 0x0

 5022 12:21:32.561441  WR_PRE       = 0x1

 5023 12:21:32.561523  WR_PST       = 0x0

 5024 12:21:32.564295  DBI_WR       = 0x0

 5025 12:21:32.564378  DBI_RD       = 0x0

 5026 12:21:32.567937  OTF          = 0x1

 5027 12:21:32.571005  =================================== 

 5028 12:21:32.577815  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5029 12:21:32.581061  nWR fixed to 30

 5030 12:21:32.581207  [ModeRegInit_LP4] CH0 RK0

 5031 12:21:32.584563  [ModeRegInit_LP4] CH0 RK1

 5032 12:21:32.587687  [ModeRegInit_LP4] CH1 RK0

 5033 12:21:32.591311  [ModeRegInit_LP4] CH1 RK1

 5034 12:21:32.591409  match AC timing 9

 5035 12:21:32.594150  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5036 12:21:32.601431  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5037 12:21:32.604473  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5038 12:21:32.611124  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5039 12:21:32.614025  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5040 12:21:32.614119  ==

 5041 12:21:32.617735  Dram Type= 6, Freq= 0, CH_0, rank 0

 5042 12:21:32.621017  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5043 12:21:32.621103  ==

 5044 12:21:32.627308  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5045 12:21:32.634323  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5046 12:21:32.637479  [CA 0] Center 38 (7~69) winsize 63

 5047 12:21:32.640496  [CA 1] Center 38 (8~69) winsize 62

 5048 12:21:32.644191  [CA 2] Center 35 (5~65) winsize 61

 5049 12:21:32.647790  [CA 3] Center 35 (5~65) winsize 61

 5050 12:21:32.650790  [CA 4] Center 34 (4~64) winsize 61

 5051 12:21:32.653892  [CA 5] Center 33 (3~64) winsize 62

 5052 12:21:32.653984  

 5053 12:21:32.657490  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5054 12:21:32.657592  

 5055 12:21:32.660964  [CATrainingPosCal] consider 1 rank data

 5056 12:21:32.664205  u2DelayCellTimex100 = 270/100 ps

 5057 12:21:32.667095  CA0 delay=38 (7~69),Diff = 5 PI (31 cell)

 5058 12:21:32.670507  CA1 delay=38 (8~69),Diff = 5 PI (31 cell)

 5059 12:21:32.673611  CA2 delay=35 (5~65),Diff = 2 PI (12 cell)

 5060 12:21:32.677314  CA3 delay=35 (5~65),Diff = 2 PI (12 cell)

 5061 12:21:32.680449  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5062 12:21:32.683583  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5063 12:21:32.683707  

 5064 12:21:32.690635  CA PerBit enable=1, Macro0, CA PI delay=33

 5065 12:21:32.690756  

 5066 12:21:32.693812  [CBTSetCACLKResult] CA Dly = 33

 5067 12:21:32.693909  CS Dly: 7 (0~38)

 5068 12:21:32.693977  ==

 5069 12:21:32.696771  Dram Type= 6, Freq= 0, CH_0, rank 1

 5070 12:21:32.700267  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5071 12:21:32.700375  ==

 5072 12:21:32.706858  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5073 12:21:32.713917  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5074 12:21:32.716971  [CA 0] Center 38 (8~69) winsize 62

 5075 12:21:32.719951  [CA 1] Center 38 (8~69) winsize 62

 5076 12:21:32.723719  [CA 2] Center 35 (5~66) winsize 62

 5077 12:21:32.726627  [CA 3] Center 35 (5~66) winsize 62

 5078 12:21:32.730387  [CA 4] Center 34 (4~65) winsize 62

 5079 12:21:32.733444  [CA 5] Center 33 (3~64) winsize 62

 5080 12:21:32.733550  

 5081 12:21:32.736489  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5082 12:21:32.736584  

 5083 12:21:32.740204  [CATrainingPosCal] consider 2 rank data

 5084 12:21:32.743244  u2DelayCellTimex100 = 270/100 ps

 5085 12:21:32.746393  CA0 delay=38 (8~69),Diff = 5 PI (31 cell)

 5086 12:21:32.750048  CA1 delay=38 (8~69),Diff = 5 PI (31 cell)

 5087 12:21:32.753126  CA2 delay=35 (5~65),Diff = 2 PI (12 cell)

 5088 12:21:32.756881  CA3 delay=35 (5~65),Diff = 2 PI (12 cell)

 5089 12:21:32.763031  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5090 12:21:32.766470  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5091 12:21:32.766578  

 5092 12:21:32.769989  CA PerBit enable=1, Macro0, CA PI delay=33

 5093 12:21:32.770075  

 5094 12:21:32.773105  [CBTSetCACLKResult] CA Dly = 33

 5095 12:21:32.773193  CS Dly: 7 (0~39)

 5096 12:21:32.773260  

 5097 12:21:32.776763  ----->DramcWriteLeveling(PI) begin...

 5098 12:21:32.776849  ==

 5099 12:21:32.779971  Dram Type= 6, Freq= 0, CH_0, rank 0

 5100 12:21:32.786723  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5101 12:21:32.786840  ==

 5102 12:21:32.789786  Write leveling (Byte 0): 32 => 32

 5103 12:21:32.789880  Write leveling (Byte 1): 30 => 30

 5104 12:21:32.793521  DramcWriteLeveling(PI) end<-----

 5105 12:21:32.793619  

 5106 12:21:32.793691  ==

 5107 12:21:32.796739  Dram Type= 6, Freq= 0, CH_0, rank 0

 5108 12:21:32.803042  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5109 12:21:32.803161  ==

 5110 12:21:32.806429  [Gating] SW mode calibration

 5111 12:21:32.813197  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5112 12:21:32.816082  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5113 12:21:32.822894   0 14  0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)

 5114 12:21:32.826133   0 14  4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)

 5115 12:21:32.829785   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5116 12:21:32.835957   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5117 12:21:32.839682   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5118 12:21:32.842710   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5119 12:21:32.849510   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5120 12:21:32.852644   0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)

 5121 12:21:32.856228   0 15  0 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (1 1)

 5122 12:21:32.862822   0 15  4 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)

 5123 12:21:32.865793   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5124 12:21:32.869417   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5125 12:21:32.875797   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5126 12:21:32.879151   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5127 12:21:32.882313   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5128 12:21:32.889113   0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 5129 12:21:32.892222   1  0  0 | B1->B0 | 2d2d 3e3e | 1 0 | (0 0) (0 0)

 5130 12:21:32.895783   1  0  4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)

 5131 12:21:32.902262   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5132 12:21:32.905387   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5133 12:21:32.908894   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5134 12:21:32.915594   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5135 12:21:32.918716   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5136 12:21:32.922366   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5137 12:21:32.928863   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5138 12:21:32.932031   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5139 12:21:32.935146   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5140 12:21:32.941740   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5141 12:21:32.944884   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5142 12:21:32.948846   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5143 12:21:32.954911   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5144 12:21:32.958109   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5145 12:21:32.961675   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5146 12:21:32.968019   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5147 12:21:32.971710   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5148 12:21:32.974780   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5149 12:21:32.981198   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5150 12:21:32.984638   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5151 12:21:32.988287   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5152 12:21:32.994931   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5153 12:21:32.998045   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5154 12:21:33.001199   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5155 12:21:33.004813  Total UI for P1: 0, mck2ui 16

 5156 12:21:33.007893  best dqsien dly found for B0: ( 1,  2, 30)

 5157 12:21:33.014251   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5158 12:21:33.014362  Total UI for P1: 0, mck2ui 16

 5159 12:21:33.017894  best dqsien dly found for B1: ( 1,  3,  4)

 5160 12:21:33.024540  best DQS0 dly(MCK, UI, PI) = (1, 2, 30)

 5161 12:21:33.027532  best DQS1 dly(MCK, UI, PI) = (1, 3, 4)

 5162 12:21:33.027640  

 5163 12:21:33.031255  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5164 12:21:33.034419  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)

 5165 12:21:33.037745  [Gating] SW calibration Done

 5166 12:21:33.037855  ==

 5167 12:21:33.041128  Dram Type= 6, Freq= 0, CH_0, rank 0

 5168 12:21:33.044282  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5169 12:21:33.044388  ==

 5170 12:21:33.047611  RX Vref Scan: 0

 5171 12:21:33.047705  

 5172 12:21:33.047773  RX Vref 0 -> 0, step: 1

 5173 12:21:33.047852  

 5174 12:21:33.050724  RX Delay -80 -> 252, step: 8

 5175 12:21:33.053838  iDelay=208, Bit 0, Center 99 (8 ~ 191) 184

 5176 12:21:33.057494  iDelay=208, Bit 1, Center 99 (8 ~ 191) 184

 5177 12:21:33.064181  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5178 12:21:33.067193  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5179 12:21:33.070861  iDelay=208, Bit 4, Center 99 (8 ~ 191) 184

 5180 12:21:33.073862  iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192

 5181 12:21:33.077608  iDelay=208, Bit 6, Center 103 (8 ~ 199) 192

 5182 12:21:33.081021  iDelay=208, Bit 7, Center 107 (8 ~ 207) 200

 5183 12:21:33.087471  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5184 12:21:33.090495  iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192

 5185 12:21:33.093695  iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200

 5186 12:21:33.097428  iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200

 5187 12:21:33.103937  iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208

 5188 12:21:33.107542  iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200

 5189 12:21:33.110554  iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200

 5190 12:21:33.113623  iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200

 5191 12:21:33.113728  ==

 5192 12:21:33.116867  Dram Type= 6, Freq= 0, CH_0, rank 0

 5193 12:21:33.120579  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5194 12:21:33.123851  ==

 5195 12:21:33.123960  DQS Delay:

 5196 12:21:33.124031  DQS0 = 0, DQS1 = 0

 5197 12:21:33.127169  DQM Delay:

 5198 12:21:33.127288  DQM0 = 97, DQM1 = 83

 5199 12:21:33.130227  DQ Delay:

 5200 12:21:33.133465  DQ0 =99, DQ1 =99, DQ2 =99, DQ3 =91

 5201 12:21:33.136591  DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107

 5202 12:21:33.136692  DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75

 5203 12:21:33.143728  DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91

 5204 12:21:33.143839  

 5205 12:21:33.143943  

 5206 12:21:33.144035  ==

 5207 12:21:33.146647  Dram Type= 6, Freq= 0, CH_0, rank 0

 5208 12:21:33.150247  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5209 12:21:33.150334  ==

 5210 12:21:33.150400  

 5211 12:21:33.150461  

 5212 12:21:33.153359  	TX Vref Scan disable

 5213 12:21:33.153460   == TX Byte 0 ==

 5214 12:21:33.160280  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5215 12:21:33.163130  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5216 12:21:33.163223   == TX Byte 1 ==

 5217 12:21:33.169726  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5218 12:21:33.173145  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5219 12:21:33.173267  ==

 5220 12:21:33.176463  Dram Type= 6, Freq= 0, CH_0, rank 0

 5221 12:21:33.179960  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5222 12:21:33.180073  ==

 5223 12:21:33.180167  

 5224 12:21:33.182919  

 5225 12:21:33.182997  	TX Vref Scan disable

 5226 12:21:33.186141   == TX Byte 0 ==

 5227 12:21:33.189961  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5228 12:21:33.192939  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5229 12:21:33.196065   == TX Byte 1 ==

 5230 12:21:33.199457  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5231 12:21:33.202781  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5232 12:21:33.206483  

 5233 12:21:33.206577  [DATLAT]

 5234 12:21:33.206665  Freq=933, CH0 RK0

 5235 12:21:33.206749  

 5236 12:21:33.209525  DATLAT Default: 0xd

 5237 12:21:33.209612  0, 0xFFFF, sum = 0

 5238 12:21:33.213062  1, 0xFFFF, sum = 0

 5239 12:21:33.213152  2, 0xFFFF, sum = 0

 5240 12:21:33.216124  3, 0xFFFF, sum = 0

 5241 12:21:33.216213  4, 0xFFFF, sum = 0

 5242 12:21:33.219219  5, 0xFFFF, sum = 0

 5243 12:21:33.222950  6, 0xFFFF, sum = 0

 5244 12:21:33.223041  7, 0xFFFF, sum = 0

 5245 12:21:33.225988  8, 0xFFFF, sum = 0

 5246 12:21:33.226076  9, 0xFFFF, sum = 0

 5247 12:21:33.229662  10, 0x0, sum = 1

 5248 12:21:33.229771  11, 0x0, sum = 2

 5249 12:21:33.229866  12, 0x0, sum = 3

 5250 12:21:33.232924  13, 0x0, sum = 4

 5251 12:21:33.233020  best_step = 11

 5252 12:21:33.233107  

 5253 12:21:33.235994  ==

 5254 12:21:33.239228  Dram Type= 6, Freq= 0, CH_0, rank 0

 5255 12:21:33.242618  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5256 12:21:33.242720  ==

 5257 12:21:33.242787  RX Vref Scan: 1

 5258 12:21:33.242855  

 5259 12:21:33.246156  RX Vref 0 -> 0, step: 1

 5260 12:21:33.246272  

 5261 12:21:33.249059  RX Delay -69 -> 252, step: 4

 5262 12:21:33.249180  

 5263 12:21:33.252686  Set Vref, RX VrefLevel [Byte0]: 61

 5264 12:21:33.255865                           [Byte1]: 53

 5265 12:21:33.255967  

 5266 12:21:33.258946  Final RX Vref Byte 0 = 61 to rank0

 5267 12:21:33.262496  Final RX Vref Byte 1 = 53 to rank0

 5268 12:21:33.265512  Final RX Vref Byte 0 = 61 to rank1

 5269 12:21:33.269274  Final RX Vref Byte 1 = 53 to rank1==

 5270 12:21:33.272186  Dram Type= 6, Freq= 0, CH_0, rank 0

 5271 12:21:33.275574  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5272 12:21:33.278852  ==

 5273 12:21:33.278989  DQS Delay:

 5274 12:21:33.279092  DQS0 = 0, DQS1 = 0

 5275 12:21:33.282019  DQM Delay:

 5276 12:21:33.282139  DQM0 = 95, DQM1 = 84

 5277 12:21:33.285589  DQ Delay:

 5278 12:21:33.289071  DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92

 5279 12:21:33.289190  DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106

 5280 12:21:33.292483  DQ8 =76, DQ9 =70, DQ10 =84, DQ11 =78

 5281 12:21:33.298652  DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =90

 5282 12:21:33.298746  

 5283 12:21:33.298811  

 5284 12:21:33.305479  [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 417 ps

 5285 12:21:33.308703  CH0 RK0: MR19=505, MR18=F0F

 5286 12:21:33.315321  CH0_RK0: MR19=0x505, MR18=0xF0F, DQSOSC=417, MR23=63, INC=62, DEC=41

 5287 12:21:33.315441  

 5288 12:21:33.318789  ----->DramcWriteLeveling(PI) begin...

 5289 12:21:33.318901  ==

 5290 12:21:33.322331  Dram Type= 6, Freq= 0, CH_0, rank 1

 5291 12:21:33.325375  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5292 12:21:33.325487  ==

 5293 12:21:33.329109  Write leveling (Byte 0): 33 => 33

 5294 12:21:33.332220  Write leveling (Byte 1): 33 => 33

 5295 12:21:33.335281  DramcWriteLeveling(PI) end<-----

 5296 12:21:33.335366  

 5297 12:21:33.335444  ==

 5298 12:21:33.338955  Dram Type= 6, Freq= 0, CH_0, rank 1

 5299 12:21:33.342160  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5300 12:21:33.342267  ==

 5301 12:21:33.345163  [Gating] SW mode calibration

 5302 12:21:33.351866  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5303 12:21:33.358523  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5304 12:21:33.362069   0 14  0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)

 5305 12:21:33.365450   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5306 12:21:33.371658   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5307 12:21:33.374919   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5308 12:21:33.378554   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5309 12:21:33.385196   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5310 12:21:33.388264   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5311 12:21:33.391532   0 14 28 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 1)

 5312 12:21:33.398102   0 15  0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)

 5313 12:21:33.401551   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5314 12:21:33.405149   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5315 12:21:33.411352   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5316 12:21:33.414907   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5317 12:21:33.417897   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5318 12:21:33.424929   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5319 12:21:33.428231   0 15 28 | B1->B0 | 2323 3737 | 0 1 | (0 0) (0 0)

 5320 12:21:33.431360   1  0  0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)

 5321 12:21:33.438108   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5322 12:21:33.441304   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5323 12:21:33.444851   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5324 12:21:33.451039   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5325 12:21:33.454914   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5326 12:21:33.457750   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5327 12:21:33.464413   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5328 12:21:33.467760   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5329 12:21:33.471311   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5330 12:21:33.477612   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5331 12:21:33.481338   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5332 12:21:33.484269   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5333 12:21:33.490861   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5334 12:21:33.494569   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5335 12:21:33.497782   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5336 12:21:33.504525   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5337 12:21:33.507671   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5338 12:21:33.510779   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5339 12:21:33.517780   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5340 12:21:33.521156   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5341 12:21:33.524255   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5342 12:21:33.527451   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5343 12:21:33.534098   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5344 12:21:33.537533  Total UI for P1: 0, mck2ui 16

 5345 12:21:33.540692  best dqsien dly found for B0: ( 1,  2, 26)

 5346 12:21:33.543989   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5347 12:21:33.548137   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5348 12:21:33.550820  Total UI for P1: 0, mck2ui 16

 5349 12:21:33.554446  best dqsien dly found for B1: ( 1,  2, 30)

 5350 12:21:33.557643  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5351 12:21:33.560691  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5352 12:21:33.561042  

 5353 12:21:33.567290  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5354 12:21:33.571128  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5355 12:21:33.574218  [Gating] SW calibration Done

 5356 12:21:33.574486  ==

 5357 12:21:33.577751  Dram Type= 6, Freq= 0, CH_0, rank 1

 5358 12:21:33.580897  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5359 12:21:33.581272  ==

 5360 12:21:33.581624  RX Vref Scan: 0

 5361 12:21:33.581961  

 5362 12:21:33.583978  RX Vref 0 -> 0, step: 1

 5363 12:21:33.584088  

 5364 12:21:33.587478  RX Delay -80 -> 252, step: 8

 5365 12:21:33.590508  iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200

 5366 12:21:33.593989  iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208

 5367 12:21:33.600795  iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192

 5368 12:21:33.603978  iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208

 5369 12:21:33.606924  iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200

 5370 12:21:33.610654  iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200

 5371 12:21:33.613649  iDelay=208, Bit 6, Center 103 (0 ~ 207) 208

 5372 12:21:33.617250  iDelay=208, Bit 7, Center 103 (0 ~ 207) 208

 5373 12:21:33.623742  iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200

 5374 12:21:33.626646  iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200

 5375 12:21:33.630096  iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200

 5376 12:21:33.634020  iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200

 5377 12:21:33.640231  iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200

 5378 12:21:33.643311  iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200

 5379 12:21:33.647114  iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200

 5380 12:21:33.650180  iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192

 5381 12:21:33.650258  ==

 5382 12:21:33.653641  Dram Type= 6, Freq= 0, CH_0, rank 1

 5383 12:21:33.656845  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5384 12:21:33.659921  ==

 5385 12:21:33.660012  DQS Delay:

 5386 12:21:33.660077  DQS0 = 0, DQS1 = 0

 5387 12:21:33.663396  DQM Delay:

 5388 12:21:33.663477  DQM0 = 91, DQM1 = 82

 5389 12:21:33.663542  DQ Delay:

 5390 12:21:33.666942  DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87

 5391 12:21:33.670084  DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103

 5392 12:21:33.673299  DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75

 5393 12:21:33.677052  DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87

 5394 12:21:33.677161  

 5395 12:21:33.680234  

 5396 12:21:33.680309  ==

 5397 12:21:33.683269  Dram Type= 6, Freq= 0, CH_0, rank 1

 5398 12:21:33.686705  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5399 12:21:33.686785  ==

 5400 12:21:33.686859  

 5401 12:21:33.686921  

 5402 12:21:33.690226  	TX Vref Scan disable

 5403 12:21:33.690334   == TX Byte 0 ==

 5404 12:21:33.696422  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5405 12:21:33.700088  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5406 12:21:33.700172   == TX Byte 1 ==

 5407 12:21:33.706873  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5408 12:21:33.709895  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5409 12:21:33.709986  ==

 5410 12:21:33.713525  Dram Type= 6, Freq= 0, CH_0, rank 1

 5411 12:21:33.716502  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5412 12:21:33.716599  ==

 5413 12:21:33.716675  

 5414 12:21:33.716743  

 5415 12:21:33.719817  	TX Vref Scan disable

 5416 12:21:33.723371   == TX Byte 0 ==

 5417 12:21:33.726526  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5418 12:21:33.729533  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5419 12:21:33.733289   == TX Byte 1 ==

 5420 12:21:33.736542  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5421 12:21:33.740038  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5422 12:21:33.740191  

 5423 12:21:33.743089  [DATLAT]

 5424 12:21:33.743262  Freq=933, CH0 RK1

 5425 12:21:33.743416  

 5426 12:21:33.746043  DATLAT Default: 0xb

 5427 12:21:33.746216  0, 0xFFFF, sum = 0

 5428 12:21:33.749875  1, 0xFFFF, sum = 0

 5429 12:21:33.750081  2, 0xFFFF, sum = 0

 5430 12:21:33.753157  3, 0xFFFF, sum = 0

 5431 12:21:33.753404  4, 0xFFFF, sum = 0

 5432 12:21:33.756267  5, 0xFFFF, sum = 0

 5433 12:21:33.756514  6, 0xFFFF, sum = 0

 5434 12:21:33.759468  7, 0xFFFF, sum = 0

 5435 12:21:33.759773  8, 0xFFFF, sum = 0

 5436 12:21:33.762800  9, 0xFFFF, sum = 0

 5437 12:21:33.763325  10, 0x0, sum = 1

 5438 12:21:33.766548  11, 0x0, sum = 2

 5439 12:21:33.766958  12, 0x0, sum = 3

 5440 12:21:33.769860  13, 0x0, sum = 4

 5441 12:21:33.770304  best_step = 11

 5442 12:21:33.770621  

 5443 12:21:33.770909  ==

 5444 12:21:33.773096  Dram Type= 6, Freq= 0, CH_0, rank 1

 5445 12:21:33.779424  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5446 12:21:33.779991  ==

 5447 12:21:33.780459  RX Vref Scan: 0

 5448 12:21:33.780801  

 5449 12:21:33.783032  RX Vref 0 -> 0, step: 1

 5450 12:21:33.783633  

 5451 12:21:33.786287  RX Delay -77 -> 252, step: 4

 5452 12:21:33.789559  iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192

 5453 12:21:33.793144  iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188

 5454 12:21:33.799473  iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188

 5455 12:21:33.803016  iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196

 5456 12:21:33.806137  iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192

 5457 12:21:33.809748  iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188

 5458 12:21:33.812846  iDelay=199, Bit 6, Center 104 (11 ~ 198) 188

 5459 12:21:33.819806  iDelay=199, Bit 7, Center 104 (11 ~ 198) 188

 5460 12:21:33.823000  iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180

 5461 12:21:33.826278  iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180

 5462 12:21:33.829529  iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188

 5463 12:21:33.832675  iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180

 5464 12:21:33.839477  iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192

 5465 12:21:33.842509  iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188

 5466 12:21:33.846233  iDelay=199, Bit 14, Center 96 (7 ~ 186) 180

 5467 12:21:33.849411  iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184

 5468 12:21:33.849955  ==

 5469 12:21:33.852547  Dram Type= 6, Freq= 0, CH_0, rank 1

 5470 12:21:33.856439  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5471 12:21:33.859210  ==

 5472 12:21:33.859659  DQS Delay:

 5473 12:21:33.859985  DQS0 = 0, DQS1 = 0

 5474 12:21:33.862538  DQM Delay:

 5475 12:21:33.862942  DQM0 = 92, DQM1 = 84

 5476 12:21:33.865843  DQ Delay:

 5477 12:21:33.866260  DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88

 5478 12:21:33.869600  DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104

 5479 12:21:33.872560  DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76

 5480 12:21:33.879153  DQ12 =90, DQ13 =92, DQ14 =96, DQ15 =90

 5481 12:21:33.879648  

 5482 12:21:33.879972  

 5483 12:21:33.886021  [DQSOSCAuto] RK1, (LSB)MR18= 0x3112, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps

 5484 12:21:33.889158  CH0 RK1: MR19=505, MR18=3112

 5485 12:21:33.895725  CH0_RK1: MR19=0x505, MR18=0x3112, DQSOSC=406, MR23=63, INC=65, DEC=43

 5486 12:21:33.899174  [RxdqsGatingPostProcess] freq 933

 5487 12:21:33.902618  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5488 12:21:33.905616  best DQS0 dly(2T, 0.5T) = (0, 10)

 5489 12:21:33.909000  best DQS1 dly(2T, 0.5T) = (0, 11)

 5490 12:21:33.912403  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5491 12:21:33.915496  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5492 12:21:33.919209  best DQS0 dly(2T, 0.5T) = (0, 10)

 5493 12:21:33.922216  best DQS1 dly(2T, 0.5T) = (0, 10)

 5494 12:21:33.925264  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5495 12:21:33.928922  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5496 12:21:33.931944  Pre-setting of DQS Precalculation

 5497 12:21:33.935343  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5498 12:21:33.935680  ==

 5499 12:21:33.938660  Dram Type= 6, Freq= 0, CH_1, rank 0

 5500 12:21:33.945177  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5501 12:21:33.945446  ==

 5502 12:21:33.948398  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5503 12:21:33.955086  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 5504 12:21:33.958257  [CA 0] Center 37 (7~67) winsize 61

 5505 12:21:33.962008  [CA 1] Center 37 (7~68) winsize 62

 5506 12:21:33.965195  [CA 2] Center 34 (5~64) winsize 60

 5507 12:21:33.968850  [CA 3] Center 34 (4~64) winsize 61

 5508 12:21:33.971810  [CA 4] Center 35 (5~65) winsize 61

 5509 12:21:33.975203  [CA 5] Center 34 (4~64) winsize 61

 5510 12:21:33.975431  

 5511 12:21:33.978143  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 5512 12:21:33.978418  

 5513 12:21:33.981651  [CATrainingPosCal] consider 1 rank data

 5514 12:21:33.985040  u2DelayCellTimex100 = 270/100 ps

 5515 12:21:33.988071  CA0 delay=37 (7~67),Diff = 3 PI (18 cell)

 5516 12:21:33.991724  CA1 delay=37 (7~68),Diff = 3 PI (18 cell)

 5517 12:21:33.998153  CA2 delay=34 (5~64),Diff = 0 PI (0 cell)

 5518 12:21:34.001470  CA3 delay=34 (4~64),Diff = 0 PI (0 cell)

 5519 12:21:34.004824  CA4 delay=35 (5~65),Diff = 1 PI (6 cell)

 5520 12:21:34.008343  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5521 12:21:34.008562  

 5522 12:21:34.011298  CA PerBit enable=1, Macro0, CA PI delay=34

 5523 12:21:34.011633  

 5524 12:21:34.014843  [CBTSetCACLKResult] CA Dly = 34

 5525 12:21:34.015054  CS Dly: 6 (0~37)

 5526 12:21:34.018011  ==

 5527 12:21:34.018308  Dram Type= 6, Freq= 0, CH_1, rank 1

 5528 12:21:34.024335  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5529 12:21:34.024579  ==

 5530 12:21:34.027928  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5531 12:21:34.034639  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 5532 12:21:34.038292  [CA 0] Center 37 (7~67) winsize 61

 5533 12:21:34.041766  [CA 1] Center 37 (7~68) winsize 62

 5534 12:21:34.045076  [CA 2] Center 35 (5~65) winsize 61

 5535 12:21:34.048088  [CA 3] Center 34 (4~64) winsize 61

 5536 12:21:34.051782  [CA 4] Center 34 (4~65) winsize 62

 5537 12:21:34.054863  [CA 5] Center 33 (3~64) winsize 62

 5538 12:21:34.055095  

 5539 12:21:34.057848  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 5540 12:21:34.058123  

 5541 12:21:34.061507  [CATrainingPosCal] consider 2 rank data

 5542 12:21:34.064694  u2DelayCellTimex100 = 270/100 ps

 5543 12:21:34.067835  CA0 delay=37 (7~67),Diff = 3 PI (18 cell)

 5544 12:21:34.074578  CA1 delay=37 (7~68),Diff = 3 PI (18 cell)

 5545 12:21:34.077743  CA2 delay=34 (5~64),Diff = 0 PI (0 cell)

 5546 12:21:34.081324  CA3 delay=34 (4~64),Diff = 0 PI (0 cell)

 5547 12:21:34.084288  CA4 delay=35 (5~65),Diff = 1 PI (6 cell)

 5548 12:21:34.087455  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5549 12:21:34.087712  

 5550 12:21:34.090846  CA PerBit enable=1, Macro0, CA PI delay=34

 5551 12:21:34.091102  

 5552 12:21:34.094697  [CBTSetCACLKResult] CA Dly = 34

 5553 12:21:34.097794  CS Dly: 7 (0~39)

 5554 12:21:34.098116  

 5555 12:21:34.100646  ----->DramcWriteLeveling(PI) begin...

 5556 12:21:34.100906  ==

 5557 12:21:34.104569  Dram Type= 6, Freq= 0, CH_1, rank 0

 5558 12:21:34.107611  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5559 12:21:34.107886  ==

 5560 12:21:34.110594  Write leveling (Byte 0): 26 => 26

 5561 12:21:34.114314  Write leveling (Byte 1): 27 => 27

 5562 12:21:34.117186  DramcWriteLeveling(PI) end<-----

 5563 12:21:34.117506  

 5564 12:21:34.117771  ==

 5565 12:21:34.120484  Dram Type= 6, Freq= 0, CH_1, rank 0

 5566 12:21:34.124222  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5567 12:21:34.124478  ==

 5568 12:21:34.127685  [Gating] SW mode calibration

 5569 12:21:34.134197  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5570 12:21:34.140530  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5571 12:21:34.143375   0 14  0 | B1->B0 | 3131 3131 | 0 1 | (0 0) (1 1)

 5572 12:21:34.147293   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5573 12:21:34.153403   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5574 12:21:34.156803   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5575 12:21:34.159951   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5576 12:21:34.167035   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5577 12:21:34.170216   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 5578 12:21:34.173709   0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)

 5579 12:21:34.180481   0 15  0 | B1->B0 | 2626 2828 | 0 1 | (0 0) (1 0)

 5580 12:21:34.183507   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5581 12:21:34.187430   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5582 12:21:34.193344   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5583 12:21:34.196797   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5584 12:21:34.200130   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5585 12:21:34.206824   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5586 12:21:34.209775   0 15 28 | B1->B0 | 3434 3232 | 0 0 | (0 0) (1 1)

 5587 12:21:34.213575   1  0  0 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)

 5588 12:21:34.220344   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5589 12:21:34.223456   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5590 12:21:34.226559   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5591 12:21:34.233175   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5592 12:21:34.236735   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5593 12:21:34.240138   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5594 12:21:34.246401   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 5595 12:21:34.250201   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5596 12:21:34.253248   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5597 12:21:34.260277   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5598 12:21:34.263319   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5599 12:21:34.266907   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5600 12:21:34.269806   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5601 12:21:34.276358   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5602 12:21:34.279618   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5603 12:21:34.283298   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5604 12:21:34.289593   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5605 12:21:34.293329   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5606 12:21:34.296488   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5607 12:21:34.303236   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5608 12:21:34.306068   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5609 12:21:34.309500   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 5610 12:21:34.316268   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5611 12:21:34.319410  Total UI for P1: 0, mck2ui 16

 5612 12:21:34.322492  best dqsien dly found for B0: ( 1,  2, 26)

 5613 12:21:34.325874   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5614 12:21:34.329146  Total UI for P1: 0, mck2ui 16

 5615 12:21:34.332254  best dqsien dly found for B1: ( 1,  2, 26)

 5616 12:21:34.335732  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5617 12:21:34.339333  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5618 12:21:34.339441  

 5619 12:21:34.342525  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5620 12:21:34.349271  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5621 12:21:34.349359  [Gating] SW calibration Done

 5622 12:21:34.349443  ==

 5623 12:21:34.352117  Dram Type= 6, Freq= 0, CH_1, rank 0

 5624 12:21:34.359522  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5625 12:21:34.359608  ==

 5626 12:21:34.359675  RX Vref Scan: 0

 5627 12:21:34.359737  

 5628 12:21:34.362241  RX Vref 0 -> 0, step: 1

 5629 12:21:34.362324  

 5630 12:21:34.365614  RX Delay -80 -> 252, step: 8

 5631 12:21:34.369075  iDelay=208, Bit 0, Center 99 (0 ~ 199) 200

 5632 12:21:34.372063  iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200

 5633 12:21:34.375582  iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192

 5634 12:21:34.378828  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5635 12:21:34.385737  iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200

 5636 12:21:34.388977  iDelay=208, Bit 5, Center 107 (8 ~ 207) 200

 5637 12:21:34.392265  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5638 12:21:34.395203  iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200

 5639 12:21:34.398736  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5640 12:21:34.401862  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5641 12:21:34.408889  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5642 12:21:34.411910  iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200

 5643 12:21:34.414936  iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200

 5644 12:21:34.418534  iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200

 5645 12:21:34.425237  iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200

 5646 12:21:34.428436  iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200

 5647 12:21:34.428519  ==

 5648 12:21:34.431662  Dram Type= 6, Freq= 0, CH_1, rank 0

 5649 12:21:34.435240  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5650 12:21:34.435344  ==

 5651 12:21:34.435448  DQS Delay:

 5652 12:21:34.438083  DQS0 = 0, DQS1 = 0

 5653 12:21:34.438159  DQM Delay:

 5654 12:21:34.441729  DQM0 = 95, DQM1 = 86

 5655 12:21:34.441808  DQ Delay:

 5656 12:21:34.444938  DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91

 5657 12:21:34.448124  DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91

 5658 12:21:34.451949  DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83

 5659 12:21:34.455079  DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91

 5660 12:21:34.455157  

 5661 12:21:34.455222  

 5662 12:21:34.455290  ==

 5663 12:21:34.458780  Dram Type= 6, Freq= 0, CH_1, rank 0

 5664 12:21:34.464711  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5665 12:21:34.464821  ==

 5666 12:21:34.464914  

 5667 12:21:34.465004  

 5668 12:21:34.465091  	TX Vref Scan disable

 5669 12:21:34.468404   == TX Byte 0 ==

 5670 12:21:34.471327  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5671 12:21:34.474701  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5672 12:21:34.478342   == TX Byte 1 ==

 5673 12:21:34.481438  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5674 12:21:34.485308  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5675 12:21:34.488371  ==

 5676 12:21:34.491427  Dram Type= 6, Freq= 0, CH_1, rank 0

 5677 12:21:34.494565  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5678 12:21:34.494673  ==

 5679 12:21:34.494768  

 5680 12:21:34.494858  

 5681 12:21:34.498105  	TX Vref Scan disable

 5682 12:21:34.498210   == TX Byte 0 ==

 5683 12:21:34.504630  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5684 12:21:34.508110  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5685 12:21:34.508194   == TX Byte 1 ==

 5686 12:21:34.514379  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5687 12:21:34.518138  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5688 12:21:34.518248  

 5689 12:21:34.518345  [DATLAT]

 5690 12:21:34.521313  Freq=933, CH1 RK0

 5691 12:21:34.521423  

 5692 12:21:34.521517  DATLAT Default: 0xd

 5693 12:21:34.524572  0, 0xFFFF, sum = 0

 5694 12:21:34.524678  1, 0xFFFF, sum = 0

 5695 12:21:34.527600  2, 0xFFFF, sum = 0

 5696 12:21:34.527680  3, 0xFFFF, sum = 0

 5697 12:21:34.531111  4, 0xFFFF, sum = 0

 5698 12:21:34.531224  5, 0xFFFF, sum = 0

 5699 12:21:34.534501  6, 0xFFFF, sum = 0

 5700 12:21:34.537888  7, 0xFFFF, sum = 0

 5701 12:21:34.537997  8, 0xFFFF, sum = 0

 5702 12:21:34.540943  9, 0xFFFF, sum = 0

 5703 12:21:34.541023  10, 0x0, sum = 1

 5704 12:21:34.544479  11, 0x0, sum = 2

 5705 12:21:34.544589  12, 0x0, sum = 3

 5706 12:21:34.544687  13, 0x0, sum = 4

 5707 12:21:34.547419  best_step = 11

 5708 12:21:34.547507  

 5709 12:21:34.547607  ==

 5710 12:21:34.551133  Dram Type= 6, Freq= 0, CH_1, rank 0

 5711 12:21:34.554293  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5712 12:21:34.554396  ==

 5713 12:21:34.557519  RX Vref Scan: 1

 5714 12:21:34.557594  

 5715 12:21:34.557657  RX Vref 0 -> 0, step: 1

 5716 12:21:34.560715  

 5717 12:21:34.560789  RX Delay -61 -> 252, step: 4

 5718 12:21:34.560851  

 5719 12:21:34.564148  Set Vref, RX VrefLevel [Byte0]: 54

 5720 12:21:34.567546                           [Byte1]: 52

 5721 12:21:34.572237  

 5722 12:21:34.572331  Final RX Vref Byte 0 = 54 to rank0

 5723 12:21:34.575153  Final RX Vref Byte 1 = 52 to rank0

 5724 12:21:34.578816  Final RX Vref Byte 0 = 54 to rank1

 5725 12:21:34.581789  Final RX Vref Byte 1 = 52 to rank1==

 5726 12:21:34.585210  Dram Type= 6, Freq= 0, CH_1, rank 0

 5727 12:21:34.591805  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5728 12:21:34.591896  ==

 5729 12:21:34.591963  DQS Delay:

 5730 12:21:34.592024  DQS0 = 0, DQS1 = 0

 5731 12:21:34.595508  DQM Delay:

 5732 12:21:34.595598  DQM0 = 96, DQM1 = 88

 5733 12:21:34.598844  DQ Delay:

 5734 12:21:34.601908  DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92

 5735 12:21:34.605721  DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92

 5736 12:21:34.608779  DQ8 =76, DQ9 =82, DQ10 =86, DQ11 =82

 5737 12:21:34.612267  DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96

 5738 12:21:34.612370  

 5739 12:21:34.612473  

 5740 12:21:34.618885  [DQSOSCAuto] RK0, (LSB)MR18= 0xff07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps

 5741 12:21:34.621942  CH1 RK0: MR19=405, MR18=FF07

 5742 12:21:34.628936  CH1_RK0: MR19=0x405, MR18=0xFF07, DQSOSC=419, MR23=63, INC=61, DEC=41

 5743 12:21:34.629022  

 5744 12:21:34.631666  ----->DramcWriteLeveling(PI) begin...

 5745 12:21:34.631771  ==

 5746 12:21:34.635269  Dram Type= 6, Freq= 0, CH_1, rank 1

 5747 12:21:34.638329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5748 12:21:34.638437  ==

 5749 12:21:34.642006  Write leveling (Byte 0): 27 => 27

 5750 12:21:34.644976  Write leveling (Byte 1): 29 => 29

 5751 12:21:34.648221  DramcWriteLeveling(PI) end<-----

 5752 12:21:34.648307  

 5753 12:21:34.648385  ==

 5754 12:21:34.651655  Dram Type= 6, Freq= 0, CH_1, rank 1

 5755 12:21:34.655160  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5756 12:21:34.655245  ==

 5757 12:21:34.658363  [Gating] SW mode calibration

 5758 12:21:34.664774  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5759 12:21:34.671313  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5760 12:21:34.674711   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5761 12:21:34.681329   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5762 12:21:34.684426   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5763 12:21:34.688056   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5764 12:21:34.694901   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5765 12:21:34.697852   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5766 12:21:34.701586   0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)

 5767 12:21:34.707804   0 14 28 | B1->B0 | 2c2c 2424 | 1 0 | (1 0) (1 0)

 5768 12:21:34.710963   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5769 12:21:34.714624   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5770 12:21:34.720923   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5771 12:21:34.724562   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5772 12:21:34.727627   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5773 12:21:34.734383   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5774 12:21:34.737717   0 15 24 | B1->B0 | 2828 3434 | 0 1 | (0 0) (0 0)

 5775 12:21:34.740971   0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)

 5776 12:21:34.747102   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5777 12:21:34.750367   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5778 12:21:34.753982   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5779 12:21:34.760741   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5780 12:21:34.763980   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5781 12:21:34.767139   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5782 12:21:34.773747   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5783 12:21:34.776847   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5784 12:21:34.780299   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5785 12:21:34.787048   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5786 12:21:34.790151   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5787 12:21:34.793897   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5788 12:21:34.800283   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5789 12:21:34.803796   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5790 12:21:34.806867   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5791 12:21:34.813303   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5792 12:21:34.816493   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5793 12:21:34.820101   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5794 12:21:34.826737   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5795 12:21:34.829955   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5796 12:21:34.833080   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5797 12:21:34.839974   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5798 12:21:34.842909   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5799 12:21:34.846249   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5800 12:21:34.849406  Total UI for P1: 0, mck2ui 16

 5801 12:21:34.852809  best dqsien dly found for B0: ( 1,  2, 24)

 5802 12:21:34.856500   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5803 12:21:34.859668  Total UI for P1: 0, mck2ui 16

 5804 12:21:34.862658  best dqsien dly found for B1: ( 1,  2, 26)

 5805 12:21:34.869181  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5806 12:21:34.872714  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5807 12:21:34.872830  

 5808 12:21:34.876318  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5809 12:21:34.879480  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5810 12:21:34.882751  [Gating] SW calibration Done

 5811 12:21:34.882846  ==

 5812 12:21:34.886085  Dram Type= 6, Freq= 0, CH_1, rank 1

 5813 12:21:34.889031  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5814 12:21:34.889143  ==

 5815 12:21:34.892503  RX Vref Scan: 0

 5816 12:21:34.892608  

 5817 12:21:34.892704  RX Vref 0 -> 0, step: 1

 5818 12:21:34.892801  

 5819 12:21:34.896128  RX Delay -80 -> 252, step: 8

 5820 12:21:34.899196  iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208

 5821 12:21:34.906160  iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200

 5822 12:21:34.909560  iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200

 5823 12:21:34.912365  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5824 12:21:34.915903  iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200

 5825 12:21:34.918836  iDelay=208, Bit 5, Center 103 (0 ~ 207) 208

 5826 12:21:34.922474  iDelay=208, Bit 6, Center 99 (0 ~ 199) 200

 5827 12:21:34.929365  iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200

 5828 12:21:34.932402  iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200

 5829 12:21:34.935480  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5830 12:21:34.939150  iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200

 5831 12:21:34.942201  iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200

 5832 12:21:34.948997  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5833 12:21:34.952444  iDelay=208, Bit 13, Center 95 (0 ~ 191) 192

 5834 12:21:34.955473  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5835 12:21:34.958806  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5836 12:21:34.958917  ==

 5837 12:21:34.962345  Dram Type= 6, Freq= 0, CH_1, rank 1

 5838 12:21:34.965374  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5839 12:21:34.965478  ==

 5840 12:21:34.968602  DQS Delay:

 5841 12:21:34.968713  DQS0 = 0, DQS1 = 0

 5842 12:21:34.972168  DQM Delay:

 5843 12:21:34.972275  DQM0 = 93, DQM1 = 88

 5844 12:21:34.972343  DQ Delay:

 5845 12:21:34.975398  DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91

 5846 12:21:34.978698  DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =91

 5847 12:21:34.982295  DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83

 5848 12:21:34.985286  DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95

 5849 12:21:34.985391  

 5850 12:21:34.988898  

 5851 12:21:34.989019  ==

 5852 12:21:34.991789  Dram Type= 6, Freq= 0, CH_1, rank 1

 5853 12:21:34.995332  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5854 12:21:34.995435  ==

 5855 12:21:34.995503  

 5856 12:21:34.995582  

 5857 12:21:34.998541  	TX Vref Scan disable

 5858 12:21:34.998643   == TX Byte 0 ==

 5859 12:21:35.005178  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5860 12:21:35.008542  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5861 12:21:35.008652   == TX Byte 1 ==

 5862 12:21:35.015171  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5863 12:21:35.018196  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5864 12:21:35.018303  ==

 5865 12:21:35.021668  Dram Type= 6, Freq= 0, CH_1, rank 1

 5866 12:21:35.024929  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5867 12:21:35.025036  ==

 5868 12:21:35.025133  

 5869 12:21:35.025224  

 5870 12:21:35.028427  	TX Vref Scan disable

 5871 12:21:35.031576   == TX Byte 0 ==

 5872 12:21:35.034763  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5873 12:21:35.038413  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5874 12:21:35.041617   == TX Byte 1 ==

 5875 12:21:35.044710  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5876 12:21:35.048361  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5877 12:21:35.048439  

 5878 12:21:35.051489  [DATLAT]

 5879 12:21:35.051572  Freq=933, CH1 RK1

 5880 12:21:35.051671  

 5881 12:21:35.054540  DATLAT Default: 0xb

 5882 12:21:35.054648  0, 0xFFFF, sum = 0

 5883 12:21:35.058264  1, 0xFFFF, sum = 0

 5884 12:21:35.058369  2, 0xFFFF, sum = 0

 5885 12:21:35.061612  3, 0xFFFF, sum = 0

 5886 12:21:35.061717  4, 0xFFFF, sum = 0

 5887 12:21:35.064499  5, 0xFFFF, sum = 0

 5888 12:21:35.064614  6, 0xFFFF, sum = 0

 5889 12:21:35.067991  7, 0xFFFF, sum = 0

 5890 12:21:35.068076  8, 0xFFFF, sum = 0

 5891 12:21:35.071427  9, 0xFFFF, sum = 0

 5892 12:21:35.071526  10, 0x0, sum = 1

 5893 12:21:35.074466  11, 0x0, sum = 2

 5894 12:21:35.074581  12, 0x0, sum = 3

 5895 12:21:35.077903  13, 0x0, sum = 4

 5896 12:21:35.078012  best_step = 11

 5897 12:21:35.078103  

 5898 12:21:35.078201  ==

 5899 12:21:35.081088  Dram Type= 6, Freq= 0, CH_1, rank 1

 5900 12:21:35.087959  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5901 12:21:35.088070  ==

 5902 12:21:35.088164  RX Vref Scan: 0

 5903 12:21:35.088253  

 5904 12:21:35.091151  RX Vref 0 -> 0, step: 1

 5905 12:21:35.091257  

 5906 12:21:35.094296  RX Delay -69 -> 252, step: 4

 5907 12:21:35.097918  iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200

 5908 12:21:35.101072  iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192

 5909 12:21:35.108037  iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196

 5910 12:21:35.111285  iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196

 5911 12:21:35.114281  iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196

 5912 12:21:35.117957  iDelay=203, Bit 5, Center 102 (7 ~ 198) 192

 5913 12:21:35.121081  iDelay=203, Bit 6, Center 104 (7 ~ 202) 196

 5914 12:21:35.127373  iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196

 5915 12:21:35.130943  iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188

 5916 12:21:35.134120  iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188

 5917 12:21:35.137423  iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188

 5918 12:21:35.141044  iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188

 5919 12:21:35.147477  iDelay=203, Bit 12, Center 98 (7 ~ 190) 184

 5920 12:21:35.150638  iDelay=203, Bit 13, Center 98 (7 ~ 190) 184

 5921 12:21:35.153680  iDelay=203, Bit 14, Center 96 (3 ~ 190) 188

 5922 12:21:35.157539  iDelay=203, Bit 15, Center 96 (3 ~ 190) 188

 5923 12:21:35.157618  ==

 5924 12:21:35.160672  Dram Type= 6, Freq= 0, CH_1, rank 1

 5925 12:21:35.163917  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5926 12:21:35.164011  ==

 5927 12:21:35.167442  DQS Delay:

 5928 12:21:35.167526  DQS0 = 0, DQS1 = 0

 5929 12:21:35.170920  DQM Delay:

 5930 12:21:35.171007  DQM0 = 91, DQM1 = 90

 5931 12:21:35.171093  DQ Delay:

 5932 12:21:35.173811  DQ0 =94, DQ1 =86, DQ2 =80, DQ3 =88

 5933 12:21:35.177207  DQ4 =88, DQ5 =102, DQ6 =104, DQ7 =88

 5934 12:21:35.180940  DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =84

 5935 12:21:35.183713  DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =96

 5936 12:21:35.183798  

 5937 12:21:35.187402  

 5938 12:21:35.193543  [DQSOSCAuto] RK1, (LSB)MR18= 0x1124, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps

 5939 12:21:35.197315  CH1 RK1: MR19=505, MR18=1124

 5940 12:21:35.203491  CH1_RK1: MR19=0x505, MR18=0x1124, DQSOSC=410, MR23=63, INC=64, DEC=42

 5941 12:21:35.207280  [RxdqsGatingPostProcess] freq 933

 5942 12:21:35.210484  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5943 12:21:35.213565  best DQS0 dly(2T, 0.5T) = (0, 10)

 5944 12:21:35.217229  best DQS1 dly(2T, 0.5T) = (0, 10)

 5945 12:21:35.220232  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5946 12:21:35.223312  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5947 12:21:35.227128  best DQS0 dly(2T, 0.5T) = (0, 10)

 5948 12:21:35.230164  best DQS1 dly(2T, 0.5T) = (0, 10)

 5949 12:21:35.233238  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5950 12:21:35.236856  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5951 12:21:35.239764  Pre-setting of DQS Precalculation

 5952 12:21:35.243122  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5953 12:21:35.250207  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5954 12:21:35.259838  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5955 12:21:35.259926  

 5956 12:21:35.259992  

 5957 12:21:35.263015  [Calibration Summary] 1866 Mbps

 5958 12:21:35.263126  CH 0, Rank 0

 5959 12:21:35.266712  SW Impedance     : PASS

 5960 12:21:35.266798  DUTY Scan        : NO K

 5961 12:21:35.269496  ZQ Calibration   : PASS

 5962 12:21:35.272997  Jitter Meter     : NO K

 5963 12:21:35.273108  CBT Training     : PASS

 5964 12:21:35.276329  Write leveling   : PASS

 5965 12:21:35.276409  RX DQS gating    : PASS

 5966 12:21:35.279409  RX DQ/DQS(RDDQC) : PASS

 5967 12:21:35.283034  TX DQ/DQS        : PASS

 5968 12:21:35.283157  RX DATLAT        : PASS

 5969 12:21:35.286058  RX DQ/DQS(Engine): PASS

 5970 12:21:35.289499  TX OE            : NO K

 5971 12:21:35.289587  All Pass.

 5972 12:21:35.289655  

 5973 12:21:35.289740  CH 0, Rank 1

 5974 12:21:35.293169  SW Impedance     : PASS

 5975 12:21:35.296313  DUTY Scan        : NO K

 5976 12:21:35.296417  ZQ Calibration   : PASS

 5977 12:21:35.299483  Jitter Meter     : NO K

 5978 12:21:35.302611  CBT Training     : PASS

 5979 12:21:35.302738  Write leveling   : PASS

 5980 12:21:35.306320  RX DQS gating    : PASS

 5981 12:21:35.309442  RX DQ/DQS(RDDQC) : PASS

 5982 12:21:35.309552  TX DQ/DQS        : PASS

 5983 12:21:35.313206  RX DATLAT        : PASS

 5984 12:21:35.316218  RX DQ/DQS(Engine): PASS

 5985 12:21:35.316302  TX OE            : NO K

 5986 12:21:35.319345  All Pass.

 5987 12:21:35.319447  

 5988 12:21:35.319513  CH 1, Rank 0

 5989 12:21:35.322915  SW Impedance     : PASS

 5990 12:21:35.322999  DUTY Scan        : NO K

 5991 12:21:35.326089  ZQ Calibration   : PASS

 5992 12:21:35.329201  Jitter Meter     : NO K

 5993 12:21:35.329285  CBT Training     : PASS

 5994 12:21:35.333051  Write leveling   : PASS

 5995 12:21:35.333136  RX DQS gating    : PASS

 5996 12:21:35.335908  RX DQ/DQS(RDDQC) : PASS

 5997 12:21:35.339686  TX DQ/DQS        : PASS

 5998 12:21:35.339770  RX DATLAT        : PASS

 5999 12:21:35.342684  RX DQ/DQS(Engine): PASS

 6000 12:21:35.345800  TX OE            : NO K

 6001 12:21:35.345884  All Pass.

 6002 12:21:35.345967  

 6003 12:21:35.346031  CH 1, Rank 1

 6004 12:21:35.349306  SW Impedance     : PASS

 6005 12:21:35.352587  DUTY Scan        : NO K

 6006 12:21:35.352684  ZQ Calibration   : PASS

 6007 12:21:35.356150  Jitter Meter     : NO K

 6008 12:21:35.359357  CBT Training     : PASS

 6009 12:21:35.359451  Write leveling   : PASS

 6010 12:21:35.362274  RX DQS gating    : PASS

 6011 12:21:35.365894  RX DQ/DQS(RDDQC) : PASS

 6012 12:21:35.365978  TX DQ/DQS        : PASS

 6013 12:21:35.369293  RX DATLAT        : PASS

 6014 12:21:35.372264  RX DQ/DQS(Engine): PASS

 6015 12:21:35.372358  TX OE            : NO K

 6016 12:21:35.375721  All Pass.

 6017 12:21:35.375830  

 6018 12:21:35.375919  DramC Write-DBI off

 6019 12:21:35.378892  	PER_BANK_REFRESH: Hybrid Mode

 6020 12:21:35.378976  TX_TRACKING: ON

 6021 12:21:35.388839  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6022 12:21:35.392177  [FAST_K] Save calibration result to emmc

 6023 12:21:35.395353  dramc_set_vcore_voltage set vcore to 650000

 6024 12:21:35.398770  Read voltage for 400, 6

 6025 12:21:35.398878  Vio18 = 0

 6026 12:21:35.402201  Vcore = 650000

 6027 12:21:35.402310  Vdram = 0

 6028 12:21:35.402413  Vddq = 0

 6029 12:21:35.405446  Vmddr = 0

 6030 12:21:35.408783  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6031 12:21:35.415410  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6032 12:21:35.415503  MEM_TYPE=3, freq_sel=20

 6033 12:21:35.418778  sv_algorithm_assistance_LP4_800 

 6034 12:21:35.422490  ============ PULL DRAM RESETB DOWN ============

 6035 12:21:35.428799  ========== PULL DRAM RESETB DOWN end =========

 6036 12:21:35.432106  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6037 12:21:35.435855  =================================== 

 6038 12:21:35.438885  LPDDR4 DRAM CONFIGURATION

 6039 12:21:35.442035  =================================== 

 6040 12:21:35.442112  EX_ROW_EN[0]    = 0x0

 6041 12:21:35.445836  EX_ROW_EN[1]    = 0x0

 6042 12:21:35.445946  LP4Y_EN      = 0x0

 6043 12:21:35.448909  WORK_FSP     = 0x0

 6044 12:21:35.448995  WL           = 0x2

 6045 12:21:35.452422  RL           = 0x2

 6046 12:21:35.455591  BL           = 0x2

 6047 12:21:35.455674  RPST         = 0x0

 6048 12:21:35.458716  RD_PRE       = 0x0

 6049 12:21:35.458797  WR_PRE       = 0x1

 6050 12:21:35.462602  WR_PST       = 0x0

 6051 12:21:35.462686  DBI_WR       = 0x0

 6052 12:21:35.465497  DBI_RD       = 0x0

 6053 12:21:35.465581  OTF          = 0x1

 6054 12:21:35.468641  =================================== 

 6055 12:21:35.471829  =================================== 

 6056 12:21:35.475514  ANA top config

 6057 12:21:35.478635  =================================== 

 6058 12:21:35.478718  DLL_ASYNC_EN            =  0

 6059 12:21:35.482049  ALL_SLAVE_EN            =  1

 6060 12:21:35.485091  NEW_RANK_MODE           =  1

 6061 12:21:35.488721  DLL_IDLE_MODE           =  1

 6062 12:21:35.488808  LP45_APHY_COMB_EN       =  1

 6063 12:21:35.491809  TX_ODT_DIS              =  1

 6064 12:21:35.495478  NEW_8X_MODE             =  1

 6065 12:21:35.498272  =================================== 

 6066 12:21:35.501648  =================================== 

 6067 12:21:35.504924  data_rate                  =  800

 6068 12:21:35.508319  CKR                        = 1

 6069 12:21:35.511727  DQ_P2S_RATIO               = 4

 6070 12:21:35.514967  =================================== 

 6071 12:21:35.515066  CA_P2S_RATIO               = 4

 6072 12:21:35.518139  DQ_CA_OPEN                 = 0

 6073 12:21:35.521546  DQ_SEMI_OPEN               = 1

 6074 12:21:35.524986  CA_SEMI_OPEN               = 1

 6075 12:21:35.528223  CA_FULL_RATE               = 0

 6076 12:21:35.531548  DQ_CKDIV4_EN               = 0

 6077 12:21:35.531637  CA_CKDIV4_EN               = 1

 6078 12:21:35.534914  CA_PREDIV_EN               = 0

 6079 12:21:35.538330  PH8_DLY                    = 0

 6080 12:21:35.541429  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6081 12:21:35.545044  DQ_AAMCK_DIV               = 0

 6082 12:21:35.548173  CA_AAMCK_DIV               = 0

 6083 12:21:35.548251  CA_ADMCK_DIV               = 4

 6084 12:21:35.551908  DQ_TRACK_CA_EN             = 0

 6085 12:21:35.554966  CA_PICK                    = 800

 6086 12:21:35.558500  CA_MCKIO                   = 400

 6087 12:21:35.561654  MCKIO_SEMI                 = 400

 6088 12:21:35.564722  PLL_FREQ                   = 3016

 6089 12:21:35.568431  DQ_UI_PI_RATIO             = 32

 6090 12:21:35.568504  CA_UI_PI_RATIO             = 32

 6091 12:21:35.571744  =================================== 

 6092 12:21:35.574857  =================================== 

 6093 12:21:35.577855  memory_type:LPDDR4         

 6094 12:21:35.581561  GP_NUM     : 10       

 6095 12:21:35.581657  SRAM_EN    : 1       

 6096 12:21:35.584682  MD32_EN    : 0       

 6097 12:21:35.588328  =================================== 

 6098 12:21:35.591305  [ANA_INIT] >>>>>>>>>>>>>> 

 6099 12:21:35.594785  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6100 12:21:35.597917  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6101 12:21:35.601529  =================================== 

 6102 12:21:35.601648  data_rate = 800,PCW = 0X7400

 6103 12:21:35.604508  =================================== 

 6104 12:21:35.607897  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6105 12:21:35.614700  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6106 12:21:35.627564  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6107 12:21:35.631239  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6108 12:21:35.634324  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6109 12:21:35.637709  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6110 12:21:35.641210  [ANA_INIT] flow start 

 6111 12:21:35.641296  [ANA_INIT] PLL >>>>>>>> 

 6112 12:21:35.644405  [ANA_INIT] PLL <<<<<<<< 

 6113 12:21:35.647550  [ANA_INIT] MIDPI >>>>>>>> 

 6114 12:21:35.647662  [ANA_INIT] MIDPI <<<<<<<< 

 6115 12:21:35.651258  [ANA_INIT] DLL >>>>>>>> 

 6116 12:21:35.654447  [ANA_INIT] flow end 

 6117 12:21:35.657972  ============ LP4 DIFF to SE enter ============

 6118 12:21:35.661166  ============ LP4 DIFF to SE exit  ============

 6119 12:21:35.664215  [ANA_INIT] <<<<<<<<<<<<< 

 6120 12:21:35.667860  [Flow] Enable top DCM control >>>>> 

 6121 12:21:35.670976  [Flow] Enable top DCM control <<<<< 

 6122 12:21:35.673962  Enable DLL master slave shuffle 

 6123 12:21:35.677163  ============================================================== 

 6124 12:21:35.680462  Gating Mode config

 6125 12:21:35.687440  ============================================================== 

 6126 12:21:35.687530  Config description: 

 6127 12:21:35.697161  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6128 12:21:35.704113  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6129 12:21:35.710619  SELPH_MODE            0: By rank         1: By Phase 

 6130 12:21:35.714088  ============================================================== 

 6131 12:21:35.717151  GAT_TRACK_EN                 =  0

 6132 12:21:35.720182  RX_GATING_MODE               =  2

 6133 12:21:35.724020  RX_GATING_TRACK_MODE         =  2

 6134 12:21:35.727042  SELPH_MODE                   =  1

 6135 12:21:35.730683  PICG_EARLY_EN                =  1

 6136 12:21:35.733688  VALID_LAT_VALUE              =  1

 6137 12:21:35.736977  ============================================================== 

 6138 12:21:35.740721  Enter into Gating configuration >>>> 

 6139 12:21:35.743765  Exit from Gating configuration <<<< 

 6140 12:21:35.746694  Enter into  DVFS_PRE_config >>>>> 

 6141 12:21:35.760278  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6142 12:21:35.763855  Exit from  DVFS_PRE_config <<<<< 

 6143 12:21:35.766946  Enter into PICG configuration >>>> 

 6144 12:21:35.770257  Exit from PICG configuration <<<< 

 6145 12:21:35.770342  [RX_INPUT] configuration >>>>> 

 6146 12:21:35.774232  [RX_INPUT] configuration <<<<< 

 6147 12:21:35.780422  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6148 12:21:35.783610  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6149 12:21:35.790274  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6150 12:21:35.796363  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6151 12:21:35.803054  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6152 12:21:35.810124  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6153 12:21:35.813264  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6154 12:21:35.816288  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6155 12:21:35.823514  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6156 12:21:35.826601  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6157 12:21:35.829829  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6158 12:21:35.832890  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6159 12:21:35.836048  =================================== 

 6160 12:21:35.839680  LPDDR4 DRAM CONFIGURATION

 6161 12:21:35.842499  =================================== 

 6162 12:21:35.846207  EX_ROW_EN[0]    = 0x0

 6163 12:21:35.846287  EX_ROW_EN[1]    = 0x0

 6164 12:21:35.849145  LP4Y_EN      = 0x0

 6165 12:21:35.849224  WORK_FSP     = 0x0

 6166 12:21:35.852822  WL           = 0x2

 6167 12:21:35.852935  RL           = 0x2

 6168 12:21:35.855925  BL           = 0x2

 6169 12:21:35.856001  RPST         = 0x0

 6170 12:21:35.859365  RD_PRE       = 0x0

 6171 12:21:35.862475  WR_PRE       = 0x1

 6172 12:21:35.862554  WR_PST       = 0x0

 6173 12:21:35.865625  DBI_WR       = 0x0

 6174 12:21:35.865700  DBI_RD       = 0x0

 6175 12:21:35.869214  OTF          = 0x1

 6176 12:21:35.872438  =================================== 

 6177 12:21:35.875489  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6178 12:21:35.879104  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6179 12:21:35.882662  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6180 12:21:35.885604  =================================== 

 6181 12:21:35.889083  LPDDR4 DRAM CONFIGURATION

 6182 12:21:35.892452  =================================== 

 6183 12:21:35.895554  EX_ROW_EN[0]    = 0x10

 6184 12:21:35.895642  EX_ROW_EN[1]    = 0x0

 6185 12:21:35.898705  LP4Y_EN      = 0x0

 6186 12:21:35.898789  WORK_FSP     = 0x0

 6187 12:21:35.902243  WL           = 0x2

 6188 12:21:35.902365  RL           = 0x2

 6189 12:21:35.905290  BL           = 0x2

 6190 12:21:35.905406  RPST         = 0x0

 6191 12:21:35.908926  RD_PRE       = 0x0

 6192 12:21:35.912421  WR_PRE       = 0x1

 6193 12:21:35.912518  WR_PST       = 0x0

 6194 12:21:35.915262  DBI_WR       = 0x0

 6195 12:21:35.915345  DBI_RD       = 0x0

 6196 12:21:35.919125  OTF          = 0x1

 6197 12:21:35.922156  =================================== 

 6198 12:21:35.925616  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6199 12:21:35.931014  nWR fixed to 30

 6200 12:21:35.934098  [ModeRegInit_LP4] CH0 RK0

 6201 12:21:35.934206  [ModeRegInit_LP4] CH0 RK1

 6202 12:21:35.937557  [ModeRegInit_LP4] CH1 RK0

 6203 12:21:35.940633  [ModeRegInit_LP4] CH1 RK1

 6204 12:21:35.940711  match AC timing 19

 6205 12:21:35.947527  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6206 12:21:35.950552  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6207 12:21:35.953752  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6208 12:21:35.960552  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6209 12:21:35.963743  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6210 12:21:35.963851  ==

 6211 12:21:35.966864  Dram Type= 6, Freq= 0, CH_0, rank 0

 6212 12:21:35.970535  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6213 12:21:35.970616  ==

 6214 12:21:35.977238  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6215 12:21:35.983991  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6216 12:21:35.986969  [CA 0] Center 36 (8~64) winsize 57

 6217 12:21:35.990580  [CA 1] Center 36 (8~64) winsize 57

 6218 12:21:35.993440  [CA 2] Center 36 (8~64) winsize 57

 6219 12:21:35.997069  [CA 3] Center 36 (8~64) winsize 57

 6220 12:21:35.997153  [CA 4] Center 36 (8~64) winsize 57

 6221 12:21:36.000215  [CA 5] Center 36 (8~64) winsize 57

 6222 12:21:36.000295  

 6223 12:21:36.007142  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6224 12:21:36.007220  

 6225 12:21:36.010740  [CATrainingPosCal] consider 1 rank data

 6226 12:21:36.013760  u2DelayCellTimex100 = 270/100 ps

 6227 12:21:36.017303  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6228 12:21:36.020108  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6229 12:21:36.023413  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6230 12:21:36.027105  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6231 12:21:36.030215  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6232 12:21:36.033585  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6233 12:21:36.033707  

 6234 12:21:36.037405  CA PerBit enable=1, Macro0, CA PI delay=36

 6235 12:21:36.037488  

 6236 12:21:36.040592  [CBTSetCACLKResult] CA Dly = 36

 6237 12:21:36.043831  CS Dly: 1 (0~32)

 6238 12:21:36.043959  ==

 6239 12:21:36.047068  Dram Type= 6, Freq= 0, CH_0, rank 1

 6240 12:21:36.049986  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6241 12:21:36.050138  ==

 6242 12:21:36.056735  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6243 12:21:36.059956  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6244 12:21:36.063543  [CA 0] Center 36 (8~64) winsize 57

 6245 12:21:36.067141  [CA 1] Center 36 (8~64) winsize 57

 6246 12:21:36.070305  [CA 2] Center 36 (8~64) winsize 57

 6247 12:21:36.073345  [CA 3] Center 36 (8~64) winsize 57

 6248 12:21:36.077083  [CA 4] Center 36 (8~64) winsize 57

 6249 12:21:36.080288  [CA 5] Center 36 (8~64) winsize 57

 6250 12:21:36.080412  

 6251 12:21:36.083372  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6252 12:21:36.083500  

 6253 12:21:36.087125  [CATrainingPosCal] consider 2 rank data

 6254 12:21:36.090267  u2DelayCellTimex100 = 270/100 ps

 6255 12:21:36.093499  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6256 12:21:36.096561  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6257 12:21:36.103518  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6258 12:21:36.106636  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6259 12:21:36.109783  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6260 12:21:36.113361  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6261 12:21:36.113468  

 6262 12:21:36.116459  CA PerBit enable=1, Macro0, CA PI delay=36

 6263 12:21:36.116541  

 6264 12:21:36.120147  [CBTSetCACLKResult] CA Dly = 36

 6265 12:21:36.120237  CS Dly: 1 (0~32)

 6266 12:21:36.120303  

 6267 12:21:36.123228  ----->DramcWriteLeveling(PI) begin...

 6268 12:21:36.126312  ==

 6269 12:21:36.130022  Dram Type= 6, Freq= 0, CH_0, rank 0

 6270 12:21:36.133043  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6271 12:21:36.133127  ==

 6272 12:21:36.136568  Write leveling (Byte 0): 40 => 8

 6273 12:21:36.139570  Write leveling (Byte 1): 40 => 8

 6274 12:21:36.143096  DramcWriteLeveling(PI) end<-----

 6275 12:21:36.143179  

 6276 12:21:36.143243  ==

 6277 12:21:36.146516  Dram Type= 6, Freq= 0, CH_0, rank 0

 6278 12:21:36.149800  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6279 12:21:36.149887  ==

 6280 12:21:36.152877  [Gating] SW mode calibration

 6281 12:21:36.159712  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6282 12:21:36.166272  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6283 12:21:36.169602   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6284 12:21:36.172701   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6285 12:21:36.179248   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6286 12:21:36.182945   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6287 12:21:36.185982   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6288 12:21:36.192790   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6289 12:21:36.195963   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6290 12:21:36.199152   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6291 12:21:36.202327   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6292 12:21:36.205977  Total UI for P1: 0, mck2ui 16

 6293 12:21:36.209501  best dqsien dly found for B0: ( 0, 14, 24)

 6294 12:21:36.212269  Total UI for P1: 0, mck2ui 16

 6295 12:21:36.215696  best dqsien dly found for B1: ( 0, 14, 24)

 6296 12:21:36.219149  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6297 12:21:36.226081  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6298 12:21:36.226173  

 6299 12:21:36.229173  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6300 12:21:36.232250  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6301 12:21:36.235763  [Gating] SW calibration Done

 6302 12:21:36.235845  ==

 6303 12:21:36.239209  Dram Type= 6, Freq= 0, CH_0, rank 0

 6304 12:21:36.242498  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6305 12:21:36.242582  ==

 6306 12:21:36.245729  RX Vref Scan: 0

 6307 12:21:36.245811  

 6308 12:21:36.245922  RX Vref 0 -> 0, step: 1

 6309 12:21:36.246020  

 6310 12:21:36.248859  RX Delay -410 -> 252, step: 16

 6311 12:21:36.252504  iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512

 6312 12:21:36.259228  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6313 12:21:36.262279  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6314 12:21:36.265323  iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512

 6315 12:21:36.272115  iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512

 6316 12:21:36.275302  iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512

 6317 12:21:36.278495  iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496

 6318 12:21:36.281636  iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512

 6319 12:21:36.288162  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6320 12:21:36.291779  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6321 12:21:36.295199  iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528

 6322 12:21:36.298699  iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512

 6323 12:21:36.304852  iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512

 6324 12:21:36.308480  iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512

 6325 12:21:36.311679  iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528

 6326 12:21:36.314747  iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512

 6327 12:21:36.318354  ==

 6328 12:21:36.321580  Dram Type= 6, Freq= 0, CH_0, rank 0

 6329 12:21:36.324940  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6330 12:21:36.325025  ==

 6331 12:21:36.325090  DQS Delay:

 6332 12:21:36.328448  DQS0 = 59, DQS1 = 59

 6333 12:21:36.328530  DQM Delay:

 6334 12:21:36.331525  DQM0 = 17, DQM1 = 10

 6335 12:21:36.331608  DQ Delay:

 6336 12:21:36.334531  DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16

 6337 12:21:36.338171  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32

 6338 12:21:36.341097  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0

 6339 12:21:36.344668  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6340 12:21:36.344759  

 6341 12:21:36.344825  

 6342 12:21:36.344885  ==

 6343 12:21:36.348034  Dram Type= 6, Freq= 0, CH_0, rank 0

 6344 12:21:36.351165  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6345 12:21:36.351247  ==

 6346 12:21:36.351312  

 6347 12:21:36.351371  

 6348 12:21:36.354341  	TX Vref Scan disable

 6349 12:21:36.354455   == TX Byte 0 ==

 6350 12:21:36.361081  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6351 12:21:36.364662  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6352 12:21:36.364752   == TX Byte 1 ==

 6353 12:21:36.370942  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6354 12:21:36.374069  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6355 12:21:36.374177  ==

 6356 12:21:36.377697  Dram Type= 6, Freq= 0, CH_0, rank 0

 6357 12:21:36.380620  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6358 12:21:36.380709  ==

 6359 12:21:36.380774  

 6360 12:21:36.384022  

 6361 12:21:36.384108  	TX Vref Scan disable

 6362 12:21:36.387694   == TX Byte 0 ==

 6363 12:21:36.390899  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6364 12:21:36.393873  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6365 12:21:36.397462   == TX Byte 1 ==

 6366 12:21:36.400927  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6367 12:21:36.403616  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6368 12:21:36.403701  

 6369 12:21:36.403764  [DATLAT]

 6370 12:21:36.407067  Freq=400, CH0 RK0

 6371 12:21:36.407148  

 6372 12:21:36.407212  DATLAT Default: 0xf

 6373 12:21:36.410521  0, 0xFFFF, sum = 0

 6374 12:21:36.413943  1, 0xFFFF, sum = 0

 6375 12:21:36.414069  2, 0xFFFF, sum = 0

 6376 12:21:36.417192  3, 0xFFFF, sum = 0

 6377 12:21:36.417274  4, 0xFFFF, sum = 0

 6378 12:21:36.420760  5, 0xFFFF, sum = 0

 6379 12:21:36.420856  6, 0xFFFF, sum = 0

 6380 12:21:36.423789  7, 0xFFFF, sum = 0

 6381 12:21:36.423872  8, 0xFFFF, sum = 0

 6382 12:21:36.427272  9, 0xFFFF, sum = 0

 6383 12:21:36.427356  10, 0xFFFF, sum = 0

 6384 12:21:36.430362  11, 0xFFFF, sum = 0

 6385 12:21:36.430480  12, 0xFFFF, sum = 0

 6386 12:21:36.433656  13, 0x0, sum = 1

 6387 12:21:36.433739  14, 0x0, sum = 2

 6388 12:21:36.437020  15, 0x0, sum = 3

 6389 12:21:36.437103  16, 0x0, sum = 4

 6390 12:21:36.440099  best_step = 14

 6391 12:21:36.440181  

 6392 12:21:36.440245  ==

 6393 12:21:36.443585  Dram Type= 6, Freq= 0, CH_0, rank 0

 6394 12:21:36.446578  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6395 12:21:36.446661  ==

 6396 12:21:36.450192  RX Vref Scan: 1

 6397 12:21:36.450314  

 6398 12:21:36.450384  RX Vref 0 -> 0, step: 1

 6399 12:21:36.450446  

 6400 12:21:36.453576  RX Delay -359 -> 252, step: 8

 6401 12:21:36.453658  

 6402 12:21:36.457112  Set Vref, RX VrefLevel [Byte0]: 61

 6403 12:21:36.460261                           [Byte1]: 53

 6404 12:21:36.464538  

 6405 12:21:36.464619  Final RX Vref Byte 0 = 61 to rank0

 6406 12:21:36.468227  Final RX Vref Byte 1 = 53 to rank0

 6407 12:21:36.471247  Final RX Vref Byte 0 = 61 to rank1

 6408 12:21:36.474296  Final RX Vref Byte 1 = 53 to rank1==

 6409 12:21:36.478178  Dram Type= 6, Freq= 0, CH_0, rank 0

 6410 12:21:36.484297  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6411 12:21:36.484379  ==

 6412 12:21:36.484445  DQS Delay:

 6413 12:21:36.487798  DQS0 = 60, DQS1 = 68

 6414 12:21:36.487879  DQM Delay:

 6415 12:21:36.487944  DQM0 = 14, DQM1 = 14

 6416 12:21:36.491347  DQ Delay:

 6417 12:21:36.494491  DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12

 6418 12:21:36.497538  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24

 6419 12:21:36.497620  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6420 12:21:36.504339  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24

 6421 12:21:36.504421  

 6422 12:21:36.504485  

 6423 12:21:36.511103  [DQSOSCAuto] RK0, (LSB)MR18= 0x8281, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps

 6424 12:21:36.514202  CH0 RK0: MR19=C0C, MR18=8281

 6425 12:21:36.520935  CH0_RK0: MR19=0xC0C, MR18=0x8281, DQSOSC=393, MR23=63, INC=382, DEC=254

 6426 12:21:36.521017  ==

 6427 12:21:36.524318  Dram Type= 6, Freq= 0, CH_0, rank 1

 6428 12:21:36.527240  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6429 12:21:36.527323  ==

 6430 12:21:36.530999  [Gating] SW mode calibration

 6431 12:21:36.537366  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6432 12:21:36.543897  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6433 12:21:36.547474   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6434 12:21:36.550716   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6435 12:21:36.557157   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6436 12:21:36.560429   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6437 12:21:36.564130   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6438 12:21:36.570492   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6439 12:21:36.574110   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6440 12:21:36.577112   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6441 12:21:36.583882   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6442 12:21:36.583972  Total UI for P1: 0, mck2ui 16

 6443 12:21:36.590752  best dqsien dly found for B0: ( 0, 14, 24)

 6444 12:21:36.590836  Total UI for P1: 0, mck2ui 16

 6445 12:21:36.596692  best dqsien dly found for B1: ( 0, 14, 24)

 6446 12:21:36.600547  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6447 12:21:36.603534  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6448 12:21:36.603615  

 6449 12:21:36.607166  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6450 12:21:36.610207  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6451 12:21:36.613328  [Gating] SW calibration Done

 6452 12:21:36.613410  ==

 6453 12:21:36.617020  Dram Type= 6, Freq= 0, CH_0, rank 1

 6454 12:21:36.620167  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6455 12:21:36.620249  ==

 6456 12:21:36.623465  RX Vref Scan: 0

 6457 12:21:36.623546  

 6458 12:21:36.623610  RX Vref 0 -> 0, step: 1

 6459 12:21:36.623670  

 6460 12:21:36.627049  RX Delay -410 -> 252, step: 16

 6461 12:21:36.633294  iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512

 6462 12:21:36.636892  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6463 12:21:36.639948  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6464 12:21:36.643488  iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528

 6465 12:21:36.649919  iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512

 6466 12:21:36.653454  iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512

 6467 12:21:36.656688  iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528

 6468 12:21:36.660018  iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528

 6469 12:21:36.666546  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6470 12:21:36.669776  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6471 12:21:36.673234  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6472 12:21:36.676731  iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512

 6473 12:21:36.683328  iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512

 6474 12:21:36.686558  iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512

 6475 12:21:36.689832  iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512

 6476 12:21:36.692932  iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512

 6477 12:21:36.696489  ==

 6478 12:21:36.699451  Dram Type= 6, Freq= 0, CH_0, rank 1

 6479 12:21:36.703020  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6480 12:21:36.703128  ==

 6481 12:21:36.703237  DQS Delay:

 6482 12:21:36.706577  DQS0 = 59, DQS1 = 59

 6483 12:21:36.706657  DQM Delay:

 6484 12:21:36.709581  DQM0 = 15, DQM1 = 10

 6485 12:21:36.709661  DQ Delay:

 6486 12:21:36.713193  DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8

 6487 12:21:36.716237  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24

 6488 12:21:36.719273  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6489 12:21:36.723004  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6490 12:21:36.723079  

 6491 12:21:36.723142  

 6492 12:21:36.723200  ==

 6493 12:21:36.726069  Dram Type= 6, Freq= 0, CH_0, rank 1

 6494 12:21:36.729189  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6495 12:21:36.729278  ==

 6496 12:21:36.729342  

 6497 12:21:36.729400  

 6498 12:21:36.732806  	TX Vref Scan disable

 6499 12:21:36.732876   == TX Byte 0 ==

 6500 12:21:36.739696  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6501 12:21:36.742732  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6502 12:21:36.742813   == TX Byte 1 ==

 6503 12:21:36.749589  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6504 12:21:36.752773  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6505 12:21:36.752856  ==

 6506 12:21:36.756257  Dram Type= 6, Freq= 0, CH_0, rank 1

 6507 12:21:36.759029  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6508 12:21:36.759157  ==

 6509 12:21:36.759274  

 6510 12:21:36.759366  

 6511 12:21:36.762427  	TX Vref Scan disable

 6512 12:21:36.765988   == TX Byte 0 ==

 6513 12:21:36.768950  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6514 12:21:36.772399  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6515 12:21:36.772483   == TX Byte 1 ==

 6516 12:21:36.779114  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6517 12:21:36.782424  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6518 12:21:36.782508  

 6519 12:21:36.782592  [DATLAT]

 6520 12:21:36.786169  Freq=400, CH0 RK1

 6521 12:21:36.786254  

 6522 12:21:36.786338  DATLAT Default: 0xe

 6523 12:21:36.789230  0, 0xFFFF, sum = 0

 6524 12:21:36.789316  1, 0xFFFF, sum = 0

 6525 12:21:36.792604  2, 0xFFFF, sum = 0

 6526 12:21:36.792700  3, 0xFFFF, sum = 0

 6527 12:21:36.795517  4, 0xFFFF, sum = 0

 6528 12:21:36.795600  5, 0xFFFF, sum = 0

 6529 12:21:36.799043  6, 0xFFFF, sum = 0

 6530 12:21:36.802149  7, 0xFFFF, sum = 0

 6531 12:21:36.802249  8, 0xFFFF, sum = 0

 6532 12:21:36.805707  9, 0xFFFF, sum = 0

 6533 12:21:36.805790  10, 0xFFFF, sum = 0

 6534 12:21:36.808954  11, 0xFFFF, sum = 0

 6535 12:21:36.809037  12, 0xFFFF, sum = 0

 6536 12:21:36.812061  13, 0x0, sum = 1

 6537 12:21:36.812145  14, 0x0, sum = 2

 6538 12:21:36.815369  15, 0x0, sum = 3

 6539 12:21:36.815517  16, 0x0, sum = 4

 6540 12:21:36.815616  best_step = 14

 6541 12:21:36.818754  

 6542 12:21:36.818834  ==

 6543 12:21:36.822278  Dram Type= 6, Freq= 0, CH_0, rank 1

 6544 12:21:36.825358  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6545 12:21:36.825466  ==

 6546 12:21:36.825556  RX Vref Scan: 0

 6547 12:21:36.825650  

 6548 12:21:36.829040  RX Vref 0 -> 0, step: 1

 6549 12:21:36.829116  

 6550 12:21:36.832218  RX Delay -359 -> 252, step: 8

 6551 12:21:36.839584  iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504

 6552 12:21:36.842760  iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504

 6553 12:21:36.845975  iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504

 6554 12:21:36.849558  iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504

 6555 12:21:36.855881  iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504

 6556 12:21:36.859577  iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504

 6557 12:21:36.862591  iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512

 6558 12:21:36.865974  iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504

 6559 12:21:36.872913  iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504

 6560 12:21:36.875778  iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496

 6561 12:21:36.879001  iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504

 6562 12:21:36.885705  iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496

 6563 12:21:36.889096  iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512

 6564 12:21:36.892186  iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504

 6565 12:21:36.895887  iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504

 6566 12:21:36.902183  iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496

 6567 12:21:36.902261  ==

 6568 12:21:36.905810  Dram Type= 6, Freq= 0, CH_0, rank 1

 6569 12:21:36.908795  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6570 12:21:36.908893  ==

 6571 12:21:36.908982  DQS Delay:

 6572 12:21:36.912220  DQS0 = 60, DQS1 = 72

 6573 12:21:36.912316  DQM Delay:

 6574 12:21:36.915689  DQM0 = 11, DQM1 = 18

 6575 12:21:36.915786  DQ Delay:

 6576 12:21:36.918697  DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8

 6577 12:21:36.922245  DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24

 6578 12:21:36.925614  DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =8

 6579 12:21:36.928781  DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =24

 6580 12:21:36.928858  

 6581 12:21:36.928920  

 6582 12:21:36.935283  [DQSOSCAuto] RK1, (LSB)MR18= 0xce82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps

 6583 12:21:36.938762  CH0 RK1: MR19=C0C, MR18=CE82

 6584 12:21:36.945552  CH0_RK1: MR19=0xC0C, MR18=0xCE82, DQSOSC=384, MR23=63, INC=400, DEC=267

 6585 12:21:36.948616  [RxdqsGatingPostProcess] freq 400

 6586 12:21:36.955461  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6587 12:21:36.958550  best DQS0 dly(2T, 0.5T) = (0, 10)

 6588 12:21:36.958631  best DQS1 dly(2T, 0.5T) = (0, 10)

 6589 12:21:36.964891  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6590 12:21:36.968557  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6591 12:21:36.968638  best DQS0 dly(2T, 0.5T) = (0, 10)

 6592 12:21:36.971623  best DQS1 dly(2T, 0.5T) = (0, 10)

 6593 12:21:36.975172  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6594 12:21:36.978149  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6595 12:21:36.981617  Pre-setting of DQS Precalculation

 6596 12:21:36.988535  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6597 12:21:36.988618  ==

 6598 12:21:36.991844  Dram Type= 6, Freq= 0, CH_1, rank 0

 6599 12:21:36.994906  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6600 12:21:36.994988  ==

 6601 12:21:37.001448  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6602 12:21:37.008250  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 6603 12:21:37.011343  [CA 0] Center 36 (8~64) winsize 57

 6604 12:21:37.011464  [CA 1] Center 36 (8~64) winsize 57

 6605 12:21:37.014401  [CA 2] Center 36 (8~64) winsize 57

 6606 12:21:37.017974  [CA 3] Center 36 (8~64) winsize 57

 6607 12:21:37.021343  [CA 4] Center 36 (8~64) winsize 57

 6608 12:21:37.024251  [CA 5] Center 36 (8~64) winsize 57

 6609 12:21:37.024335  

 6610 12:21:37.027973  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 6611 12:21:37.028056  

 6612 12:21:37.031040  [CATrainingPosCal] consider 1 rank data

 6613 12:21:37.034170  u2DelayCellTimex100 = 270/100 ps

 6614 12:21:37.037902  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6615 12:21:37.044397  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6616 12:21:37.047728  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6617 12:21:37.050948  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6618 12:21:37.054085  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6619 12:21:37.057542  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6620 12:21:37.057625  

 6621 12:21:37.060843  CA PerBit enable=1, Macro0, CA PI delay=36

 6622 12:21:37.060926  

 6623 12:21:37.063978  [CBTSetCACLKResult] CA Dly = 36

 6624 12:21:37.067065  CS Dly: 1 (0~32)

 6625 12:21:37.067146  ==

 6626 12:21:37.070772  Dram Type= 6, Freq= 0, CH_1, rank 1

 6627 12:21:37.074233  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6628 12:21:37.074317  ==

 6629 12:21:37.080467  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6630 12:21:37.083984  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33

 6631 12:21:37.086966  [CA 0] Center 36 (8~64) winsize 57

 6632 12:21:37.090494  [CA 1] Center 36 (8~64) winsize 57

 6633 12:21:37.093830  [CA 2] Center 36 (8~64) winsize 57

 6634 12:21:37.097228  [CA 3] Center 36 (8~64) winsize 57

 6635 12:21:37.100546  [CA 4] Center 36 (8~64) winsize 57

 6636 12:21:37.104241  [CA 5] Center 36 (8~64) winsize 57

 6637 12:21:37.104323  

 6638 12:21:37.106900  [CmdBusTrainingLP45] Vref(ca) range 1: 33

 6639 12:21:37.106980  

 6640 12:21:37.110550  [CATrainingPosCal] consider 2 rank data

 6641 12:21:37.113570  u2DelayCellTimex100 = 270/100 ps

 6642 12:21:37.117326  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6643 12:21:37.120489  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6644 12:21:37.123976  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6645 12:21:37.130194  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6646 12:21:37.133345  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6647 12:21:37.136990  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6648 12:21:37.137072  

 6649 12:21:37.140192  CA PerBit enable=1, Macro0, CA PI delay=36

 6650 12:21:37.140273  

 6651 12:21:37.143826  [CBTSetCACLKResult] CA Dly = 36

 6652 12:21:37.143909  CS Dly: 1 (0~32)

 6653 12:21:37.143993  

 6654 12:21:37.146975  ----->DramcWriteLeveling(PI) begin...

 6655 12:21:37.150175  ==

 6656 12:21:37.150261  Dram Type= 6, Freq= 0, CH_1, rank 0

 6657 12:21:37.156645  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6658 12:21:37.156730  ==

 6659 12:21:37.160199  Write leveling (Byte 0): 40 => 8

 6660 12:21:37.163063  Write leveling (Byte 1): 40 => 8

 6661 12:21:37.166416  DramcWriteLeveling(PI) end<-----

 6662 12:21:37.166499  

 6663 12:21:37.166583  ==

 6664 12:21:37.169646  Dram Type= 6, Freq= 0, CH_1, rank 0

 6665 12:21:37.172936  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6666 12:21:37.173020  ==

 6667 12:21:37.176673  [Gating] SW mode calibration

 6668 12:21:37.183180  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6669 12:21:37.189451  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6670 12:21:37.193048   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6671 12:21:37.196012   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6672 12:21:37.202864   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6673 12:21:37.206301   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6674 12:21:37.209729   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6675 12:21:37.212600   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6676 12:21:37.219219   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6677 12:21:37.222748   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6678 12:21:37.228886   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6679 12:21:37.228972  Total UI for P1: 0, mck2ui 16

 6680 12:21:37.232444  best dqsien dly found for B0: ( 0, 14, 24)

 6681 12:21:37.235970  Total UI for P1: 0, mck2ui 16

 6682 12:21:37.239268  best dqsien dly found for B1: ( 0, 14, 24)

 6683 12:21:37.245996  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6684 12:21:37.249228  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6685 12:21:37.249342  

 6686 12:21:37.252359  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6687 12:21:37.255352  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6688 12:21:37.259052  [Gating] SW calibration Done

 6689 12:21:37.259136  ==

 6690 12:21:37.262513  Dram Type= 6, Freq= 0, CH_1, rank 0

 6691 12:21:37.265585  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6692 12:21:37.265670  ==

 6693 12:21:37.268648  RX Vref Scan: 0

 6694 12:21:37.268731  

 6695 12:21:37.268846  RX Vref 0 -> 0, step: 1

 6696 12:21:37.268954  

 6697 12:21:37.272356  RX Delay -410 -> 252, step: 16

 6698 12:21:37.278827  iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528

 6699 12:21:37.282339  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6700 12:21:37.285138  iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528

 6701 12:21:37.288514  iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512

 6702 12:21:37.295291  iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512

 6703 12:21:37.298751  iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512

 6704 12:21:37.301784  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6705 12:21:37.305439  iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512

 6706 12:21:37.311775  iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528

 6707 12:21:37.315070  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6708 12:21:37.318383  iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528

 6709 12:21:37.321859  iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528

 6710 12:21:37.328690  iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512

 6711 12:21:37.331742  iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528

 6712 12:21:37.334942  iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512

 6713 12:21:37.338452  iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528

 6714 12:21:37.341953  ==

 6715 12:21:37.342038  Dram Type= 6, Freq= 0, CH_1, rank 0

 6716 12:21:37.348662  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6717 12:21:37.348746  ==

 6718 12:21:37.348830  DQS Delay:

 6719 12:21:37.351842  DQS0 = 51, DQS1 = 67

 6720 12:21:37.351958  DQM Delay:

 6721 12:21:37.354974  DQM0 = 12, DQM1 = 19

 6722 12:21:37.355058  DQ Delay:

 6723 12:21:37.358035  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6724 12:21:37.361700  DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8

 6725 12:21:37.364667  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16

 6726 12:21:37.368227  DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32

 6727 12:21:37.368311  

 6728 12:21:37.368393  

 6729 12:21:37.368472  ==

 6730 12:21:37.371359  Dram Type= 6, Freq= 0, CH_1, rank 0

 6731 12:21:37.375110  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6732 12:21:37.375194  ==

 6733 12:21:37.375310  

 6734 12:21:37.375431  

 6735 12:21:37.378238  	TX Vref Scan disable

 6736 12:21:37.378321   == TX Byte 0 ==

 6737 12:21:37.384807  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6738 12:21:37.388294  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6739 12:21:37.388402   == TX Byte 1 ==

 6740 12:21:37.394720  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6741 12:21:37.397711  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6742 12:21:37.397848  ==

 6743 12:21:37.401139  Dram Type= 6, Freq= 0, CH_1, rank 0

 6744 12:21:37.404330  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6745 12:21:37.404411  ==

 6746 12:21:37.404476  

 6747 12:21:37.404535  

 6748 12:21:37.407991  	TX Vref Scan disable

 6749 12:21:37.408072   == TX Byte 0 ==

 6750 12:21:37.414600  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6751 12:21:37.417628  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6752 12:21:37.417710   == TX Byte 1 ==

 6753 12:21:37.424260  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6754 12:21:37.427586  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6755 12:21:37.427667  

 6756 12:21:37.427730  [DATLAT]

 6757 12:21:37.430889  Freq=400, CH1 RK0

 6758 12:21:37.430971  

 6759 12:21:37.431034  DATLAT Default: 0xf

 6760 12:21:37.434492  0, 0xFFFF, sum = 0

 6761 12:21:37.434575  1, 0xFFFF, sum = 0

 6762 12:21:37.437535  2, 0xFFFF, sum = 0

 6763 12:21:37.437617  3, 0xFFFF, sum = 0

 6764 12:21:37.441195  4, 0xFFFF, sum = 0

 6765 12:21:37.441277  5, 0xFFFF, sum = 0

 6766 12:21:37.444359  6, 0xFFFF, sum = 0

 6767 12:21:37.444440  7, 0xFFFF, sum = 0

 6768 12:21:37.447918  8, 0xFFFF, sum = 0

 6769 12:21:37.448001  9, 0xFFFF, sum = 0

 6770 12:21:37.450973  10, 0xFFFF, sum = 0

 6771 12:21:37.454216  11, 0xFFFF, sum = 0

 6772 12:21:37.454298  12, 0xFFFF, sum = 0

 6773 12:21:37.457605  13, 0x0, sum = 1

 6774 12:21:37.457686  14, 0x0, sum = 2

 6775 12:21:37.460723  15, 0x0, sum = 3

 6776 12:21:37.460804  16, 0x0, sum = 4

 6777 12:21:37.460869  best_step = 14

 6778 12:21:37.460928  

 6779 12:21:37.464505  ==

 6780 12:21:37.467679  Dram Type= 6, Freq= 0, CH_1, rank 0

 6781 12:21:37.470469  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6782 12:21:37.470551  ==

 6783 12:21:37.470631  RX Vref Scan: 1

 6784 12:21:37.470691  

 6785 12:21:37.474149  RX Vref 0 -> 0, step: 1

 6786 12:21:37.474229  

 6787 12:21:37.477241  RX Delay -375 -> 252, step: 8

 6788 12:21:37.477341  

 6789 12:21:37.480996  Set Vref, RX VrefLevel [Byte0]: 54

 6790 12:21:37.484011                           [Byte1]: 52

 6791 12:21:37.487680  

 6792 12:21:37.487766  Final RX Vref Byte 0 = 54 to rank0

 6793 12:21:37.491197  Final RX Vref Byte 1 = 52 to rank0

 6794 12:21:37.494853  Final RX Vref Byte 0 = 54 to rank1

 6795 12:21:37.497763  Final RX Vref Byte 1 = 52 to rank1==

 6796 12:21:37.500894  Dram Type= 6, Freq= 0, CH_1, rank 0

 6797 12:21:37.507676  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6798 12:21:37.507757  ==

 6799 12:21:37.507821  DQS Delay:

 6800 12:21:37.511221  DQS0 = 52, DQS1 = 64

 6801 12:21:37.511304  DQM Delay:

 6802 12:21:37.511368  DQM0 = 9, DQM1 = 10

 6803 12:21:37.514217  DQ Delay:

 6804 12:21:37.517578  DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4

 6805 12:21:37.517659  DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8

 6806 12:21:37.521021  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4

 6807 12:21:37.524494  DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16

 6808 12:21:37.524574  

 6809 12:21:37.524641  

 6810 12:21:37.534502  [DQSOSCAuto] RK0, (LSB)MR18= 0x5367, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps

 6811 12:21:37.537499  CH1 RK0: MR19=C0C, MR18=5367

 6812 12:21:37.544104  CH1_RK0: MR19=0xC0C, MR18=0x5367, DQSOSC=396, MR23=63, INC=376, DEC=251

 6813 12:21:37.544204  ==

 6814 12:21:37.547878  Dram Type= 6, Freq= 0, CH_1, rank 1

 6815 12:21:37.550842  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6816 12:21:37.550924  ==

 6817 12:21:37.553975  [Gating] SW mode calibration

 6818 12:21:37.560804  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6819 12:21:37.567334  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6820 12:21:37.570396   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6821 12:21:37.573865   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6822 12:21:37.580803   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6823 12:21:37.583908   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6824 12:21:37.587070   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6825 12:21:37.590952   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6826 12:21:37.597164   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6827 12:21:37.600526   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6828 12:21:37.604095   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6829 12:21:37.607170  Total UI for P1: 0, mck2ui 16

 6830 12:21:37.610828  best dqsien dly found for B0: ( 0, 14, 24)

 6831 12:21:37.613855  Total UI for P1: 0, mck2ui 16

 6832 12:21:37.616955  best dqsien dly found for B1: ( 0, 14, 24)

 6833 12:21:37.620200  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6834 12:21:37.626850  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6835 12:21:37.626941  

 6836 12:21:37.630469  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6837 12:21:37.633480  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6838 12:21:37.637115  [Gating] SW calibration Done

 6839 12:21:37.637189  ==

 6840 12:21:37.640257  Dram Type= 6, Freq= 0, CH_1, rank 1

 6841 12:21:37.643611  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6842 12:21:37.643699  ==

 6843 12:21:37.643761  RX Vref Scan: 0

 6844 12:21:37.647506  

 6845 12:21:37.647579  RX Vref 0 -> 0, step: 1

 6846 12:21:37.647640  

 6847 12:21:37.650085  RX Delay -410 -> 252, step: 16

 6848 12:21:37.653882  iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528

 6849 12:21:37.660159  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6850 12:21:37.663255  iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512

 6851 12:21:37.666607  iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512

 6852 12:21:37.670346  iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512

 6853 12:21:37.676771  iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512

 6854 12:21:37.680204  iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512

 6855 12:21:37.683290  iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512

 6856 12:21:37.686518  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6857 12:21:37.693478  iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528

 6858 12:21:37.696569  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6859 12:21:37.700231  iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528

 6860 12:21:37.703308  iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512

 6861 12:21:37.710243  iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528

 6862 12:21:37.713453  iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512

 6863 12:21:37.716536  iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528

 6864 12:21:37.716622  ==

 6865 12:21:37.719600  Dram Type= 6, Freq= 0, CH_1, rank 1

 6866 12:21:37.726273  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6867 12:21:37.726355  ==

 6868 12:21:37.726427  DQS Delay:

 6869 12:21:37.729999  DQS0 = 59, DQS1 = 59

 6870 12:21:37.730085  DQM Delay:

 6871 12:21:37.733392  DQM0 = 19, DQM1 = 14

 6872 12:21:37.733475  DQ Delay:

 6873 12:21:37.736381  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6874 12:21:37.739510  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6875 12:21:37.742707  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8

 6876 12:21:37.746451  DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24

 6877 12:21:37.746538  

 6878 12:21:37.746624  

 6879 12:21:37.746707  ==

 6880 12:21:37.749636  Dram Type= 6, Freq= 0, CH_1, rank 1

 6881 12:21:37.752615  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6882 12:21:37.752703  ==

 6883 12:21:37.752791  

 6884 12:21:37.752874  

 6885 12:21:37.756229  	TX Vref Scan disable

 6886 12:21:37.756315   == TX Byte 0 ==

 6887 12:21:37.762845  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6888 12:21:37.766284  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6889 12:21:37.766372   == TX Byte 1 ==

 6890 12:21:37.769879  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6891 12:21:37.776328  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6892 12:21:37.776413  ==

 6893 12:21:37.779746  Dram Type= 6, Freq= 0, CH_1, rank 1

 6894 12:21:37.782629  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6895 12:21:37.782714  ==

 6896 12:21:37.782798  

 6897 12:21:37.782878  

 6898 12:21:37.786043  	TX Vref Scan disable

 6899 12:21:37.786127   == TX Byte 0 ==

 6900 12:21:37.792423  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6901 12:21:37.796038  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6902 12:21:37.796117   == TX Byte 1 ==

 6903 12:21:37.803000  Update DQ  dly =583 (4 ,2, 7)  DQ  OEN =(3 ,3)

 6904 12:21:37.806130  Update DQM dly =583 (4 ,2, 7)  DQM OEN =(3 ,3)

 6905 12:21:37.806206  

 6906 12:21:37.806277  [DATLAT]

 6907 12:21:37.809250  Freq=400, CH1 RK1

 6908 12:21:37.809321  

 6909 12:21:37.809427  DATLAT Default: 0xe

 6910 12:21:37.812636  0, 0xFFFF, sum = 0

 6911 12:21:37.812709  1, 0xFFFF, sum = 0

 6912 12:21:37.816051  2, 0xFFFF, sum = 0

 6913 12:21:37.816126  3, 0xFFFF, sum = 0

 6914 12:21:37.819055  4, 0xFFFF, sum = 0

 6915 12:21:37.819125  5, 0xFFFF, sum = 0

 6916 12:21:37.822783  6, 0xFFFF, sum = 0

 6917 12:21:37.822854  7, 0xFFFF, sum = 0

 6918 12:21:37.825901  8, 0xFFFF, sum = 0

 6919 12:21:37.825972  9, 0xFFFF, sum = 0

 6920 12:21:37.828973  10, 0xFFFF, sum = 0

 6921 12:21:37.829051  11, 0xFFFF, sum = 0

 6922 12:21:37.832708  12, 0xFFFF, sum = 0

 6923 12:21:37.835835  13, 0x0, sum = 1

 6924 12:21:37.835906  14, 0x0, sum = 2

 6925 12:21:37.835967  15, 0x0, sum = 3

 6926 12:21:37.839303  16, 0x0, sum = 4

 6927 12:21:37.839430  best_step = 14

 6928 12:21:37.839512  

 6929 12:21:37.842190  ==

 6930 12:21:37.842270  Dram Type= 6, Freq= 0, CH_1, rank 1

 6931 12:21:37.849018  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6932 12:21:37.849093  ==

 6933 12:21:37.849161  RX Vref Scan: 0

 6934 12:21:37.849219  

 6935 12:21:37.852171  RX Vref 0 -> 0, step: 1

 6936 12:21:37.852281  

 6937 12:21:37.855213  RX Delay -359 -> 252, step: 8

 6938 12:21:37.862298  iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504

 6939 12:21:37.865519  iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504

 6940 12:21:37.869005  iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504

 6941 12:21:37.875329  iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504

 6942 12:21:37.878879  iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512

 6943 12:21:37.881976  iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504

 6944 12:21:37.885577  iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504

 6945 12:21:37.888611  iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504

 6946 12:21:37.895350  iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512

 6947 12:21:37.898555  iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512

 6948 12:21:37.902015  iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512

 6949 12:21:37.908349  iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504

 6950 12:21:37.911746  iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512

 6951 12:21:37.915130  iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512

 6952 12:21:37.918769  iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512

 6953 12:21:37.924966  iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512

 6954 12:21:37.925051  ==

 6955 12:21:37.928557  Dram Type= 6, Freq= 0, CH_1, rank 1

 6956 12:21:37.931633  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6957 12:21:37.931719  ==

 6958 12:21:37.931841  DQS Delay:

 6959 12:21:37.935335  DQS0 = 60, DQS1 = 64

 6960 12:21:37.935471  DQM Delay:

 6961 12:21:37.938443  DQM0 = 12, DQM1 = 10

 6962 12:21:37.938527  DQ Delay:

 6963 12:21:37.941413  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8

 6964 12:21:37.945007  DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8

 6965 12:21:37.948602  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4

 6966 12:21:37.951552  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6967 12:21:37.951633  

 6968 12:21:37.951713  

 6969 12:21:37.958500  [DQSOSCAuto] RK1, (LSB)MR18= 0x7bab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps

 6970 12:21:37.961621  CH1 RK1: MR19=C0C, MR18=7BAB

 6971 12:21:37.968249  CH1_RK1: MR19=0xC0C, MR18=0x7BAB, DQSOSC=388, MR23=63, INC=392, DEC=261

 6972 12:21:37.971499  [RxdqsGatingPostProcess] freq 400

 6973 12:21:37.978301  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6974 12:21:37.981287  best DQS0 dly(2T, 0.5T) = (0, 10)

 6975 12:21:37.981371  best DQS1 dly(2T, 0.5T) = (0, 10)

 6976 12:21:37.985175  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6977 12:21:37.988170  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6978 12:21:37.991720  best DQS0 dly(2T, 0.5T) = (0, 10)

 6979 12:21:37.994906  best DQS1 dly(2T, 0.5T) = (0, 10)

 6980 12:21:37.998036  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6981 12:21:38.001699  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6982 12:21:38.004719  Pre-setting of DQS Precalculation

 6983 12:21:38.011773  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6984 12:21:38.018415  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 6985 12:21:38.025028  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6986 12:21:38.025114  

 6987 12:21:38.025229  

 6988 12:21:38.028144  [Calibration Summary] 800 Mbps

 6989 12:21:38.028228  CH 0, Rank 0

 6990 12:21:38.031467  SW Impedance     : PASS

 6991 12:21:38.034940  DUTY Scan        : NO K

 6992 12:21:38.035025  ZQ Calibration   : PASS

 6993 12:21:38.037891  Jitter Meter     : NO K

 6994 12:21:38.041288  CBT Training     : PASS

 6995 12:21:38.041372  Write leveling   : PASS

 6996 12:21:38.044598  RX DQS gating    : PASS

 6997 12:21:38.044742  RX DQ/DQS(RDDQC) : PASS

 6998 12:21:38.048201  TX DQ/DQS        : PASS

 6999 12:21:38.051214  RX DATLAT        : PASS

 7000 12:21:38.051299  RX DQ/DQS(Engine): PASS

 7001 12:21:38.054221  TX OE            : NO K

 7002 12:21:38.054306  All Pass.

 7003 12:21:38.054390  

 7004 12:21:38.057952  CH 0, Rank 1

 7005 12:21:38.058036  SW Impedance     : PASS

 7006 12:21:38.061087  DUTY Scan        : NO K

 7007 12:21:38.064687  ZQ Calibration   : PASS

 7008 12:21:38.064770  Jitter Meter     : NO K

 7009 12:21:38.067728  CBT Training     : PASS

 7010 12:21:38.070766  Write leveling   : NO K

 7011 12:21:38.070852  RX DQS gating    : PASS

 7012 12:21:38.074385  RX DQ/DQS(RDDQC) : PASS

 7013 12:21:38.077486  TX DQ/DQS        : PASS

 7014 12:21:38.077573  RX DATLAT        : PASS

 7015 12:21:38.080665  RX DQ/DQS(Engine): PASS

 7016 12:21:38.084382  TX OE            : NO K

 7017 12:21:38.084468  All Pass.

 7018 12:21:38.084555  

 7019 12:21:38.084638  CH 1, Rank 0

 7020 12:21:38.087376  SW Impedance     : PASS

 7021 12:21:38.090998  DUTY Scan        : NO K

 7022 12:21:38.091084  ZQ Calibration   : PASS

 7023 12:21:38.093871  Jitter Meter     : NO K

 7024 12:21:38.097740  CBT Training     : PASS

 7025 12:21:38.097827  Write leveling   : PASS

 7026 12:21:38.100702  RX DQS gating    : PASS

 7027 12:21:38.103869  RX DQ/DQS(RDDQC) : PASS

 7028 12:21:38.103968  TX DQ/DQS        : PASS

 7029 12:21:38.107507  RX DATLAT        : PASS

 7030 12:21:38.110551  RX DQ/DQS(Engine): PASS

 7031 12:21:38.110637  TX OE            : NO K

 7032 12:21:38.110725  All Pass.

 7033 12:21:38.113599  

 7034 12:21:38.113684  CH 1, Rank 1

 7035 12:21:38.117470  SW Impedance     : PASS

 7036 12:21:38.117556  DUTY Scan        : NO K

 7037 12:21:38.120301  ZQ Calibration   : PASS

 7038 12:21:38.123997  Jitter Meter     : NO K

 7039 12:21:38.124107  CBT Training     : PASS

 7040 12:21:38.127059  Write leveling   : NO K

 7041 12:21:38.127146  RX DQS gating    : PASS

 7042 12:21:38.130143  RX DQ/DQS(RDDQC) : PASS

 7043 12:21:38.133792  TX DQ/DQS        : PASS

 7044 12:21:38.133878  RX DATLAT        : PASS

 7045 12:21:38.136668  RX DQ/DQS(Engine): PASS

 7046 12:21:38.140430  TX OE            : NO K

 7047 12:21:38.140516  All Pass.

 7048 12:21:38.140603  

 7049 12:21:38.143509  DramC Write-DBI off

 7050 12:21:38.143595  	PER_BANK_REFRESH: Hybrid Mode

 7051 12:21:38.146817  TX_TRACKING: ON

 7052 12:21:38.156695  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7053 12:21:38.160044  [FAST_K] Save calibration result to emmc

 7054 12:21:38.163391  dramc_set_vcore_voltage set vcore to 725000

 7055 12:21:38.166716  Read voltage for 1600, 0

 7056 12:21:38.166802  Vio18 = 0

 7057 12:21:38.166890  Vcore = 725000

 7058 12:21:38.166974  Vdram = 0

 7059 12:21:38.169745  Vddq = 0

 7060 12:21:38.169829  Vmddr = 0

 7061 12:21:38.176468  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7062 12:21:38.179948  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7063 12:21:38.183119  MEM_TYPE=3, freq_sel=13

 7064 12:21:38.186834  sv_algorithm_assistance_LP4_3733 

 7065 12:21:38.189913  ============ PULL DRAM RESETB DOWN ============

 7066 12:21:38.192958  ========== PULL DRAM RESETB DOWN end =========

 7067 12:21:38.199671  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7068 12:21:38.203108  =================================== 

 7069 12:21:38.203194  LPDDR4 DRAM CONFIGURATION

 7070 12:21:38.206512  =================================== 

 7071 12:21:38.209757  EX_ROW_EN[0]    = 0x0

 7072 12:21:38.212871  EX_ROW_EN[1]    = 0x0

 7073 12:21:38.213002  LP4Y_EN      = 0x0

 7074 12:21:38.216595  WORK_FSP     = 0x1

 7075 12:21:38.216681  WL           = 0x5

 7076 12:21:38.219626  RL           = 0x5

 7077 12:21:38.219710  BL           = 0x2

 7078 12:21:38.223043  RPST         = 0x0

 7079 12:21:38.223158  RD_PRE       = 0x0

 7080 12:21:38.226067  WR_PRE       = 0x1

 7081 12:21:38.226192  WR_PST       = 0x1

 7082 12:21:38.229816  DBI_WR       = 0x0

 7083 12:21:38.229900  DBI_RD       = 0x0

 7084 12:21:38.232893  OTF          = 0x1

 7085 12:21:38.235952  =================================== 

 7086 12:21:38.239760  =================================== 

 7087 12:21:38.239845  ANA top config

 7088 12:21:38.242870  =================================== 

 7089 12:21:38.245735  DLL_ASYNC_EN            =  0

 7090 12:21:38.249398  ALL_SLAVE_EN            =  0

 7091 12:21:38.252570  NEW_RANK_MODE           =  1

 7092 12:21:38.252655  DLL_IDLE_MODE           =  1

 7093 12:21:38.255731  LP45_APHY_COMB_EN       =  1

 7094 12:21:38.259300  TX_ODT_DIS              =  0

 7095 12:21:38.262657  NEW_8X_MODE             =  1

 7096 12:21:38.265474  =================================== 

 7097 12:21:38.269273  =================================== 

 7098 12:21:38.272371  data_rate                  = 3200

 7099 12:21:38.272456  CKR                        = 1

 7100 12:21:38.275337  DQ_P2S_RATIO               = 8

 7101 12:21:38.278722  =================================== 

 7102 12:21:38.281897  CA_P2S_RATIO               = 8

 7103 12:21:38.285821  DQ_CA_OPEN                 = 0

 7104 12:21:38.289099  DQ_SEMI_OPEN               = 0

 7105 12:21:38.291996  CA_SEMI_OPEN               = 0

 7106 12:21:38.292083  CA_FULL_RATE               = 0

 7107 12:21:38.295602  DQ_CKDIV4_EN               = 0

 7108 12:21:38.298630  CA_CKDIV4_EN               = 0

 7109 12:21:38.301890  CA_PREDIV_EN               = 0

 7110 12:21:38.305608  PH8_DLY                    = 12

 7111 12:21:38.308719  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7112 12:21:38.308795  DQ_AAMCK_DIV               = 4

 7113 12:21:38.312393  CA_AAMCK_DIV               = 4

 7114 12:21:38.315313  CA_ADMCK_DIV               = 4

 7115 12:21:38.318366  DQ_TRACK_CA_EN             = 0

 7116 12:21:38.321801  CA_PICK                    = 1600

 7117 12:21:38.325161  CA_MCKIO                   = 1600

 7118 12:21:38.328687  MCKIO_SEMI                 = 0

 7119 12:21:38.331884  PLL_FREQ                   = 3068

 7120 12:21:38.331964  DQ_UI_PI_RATIO             = 32

 7121 12:21:38.334981  CA_UI_PI_RATIO             = 0

 7122 12:21:38.338580  =================================== 

 7123 12:21:38.341632  =================================== 

 7124 12:21:38.345306  memory_type:LPDDR4         

 7125 12:21:38.348420  GP_NUM     : 10       

 7126 12:21:38.348530  SRAM_EN    : 1       

 7127 12:21:38.351267  MD32_EN    : 0       

 7128 12:21:38.355057  =================================== 

 7129 12:21:38.358043  [ANA_INIT] >>>>>>>>>>>>>> 

 7130 12:21:38.358121  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7131 12:21:38.364958  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7132 12:21:38.367959  =================================== 

 7133 12:21:38.368057  data_rate = 3200,PCW = 0X7600

 7134 12:21:38.371542  =================================== 

 7135 12:21:38.374727  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7136 12:21:38.381431  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7137 12:21:38.387963  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7138 12:21:38.390947  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7139 12:21:38.394524  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7140 12:21:38.397680  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7141 12:21:38.400947  [ANA_INIT] flow start 

 7142 12:21:38.401063  [ANA_INIT] PLL >>>>>>>> 

 7143 12:21:38.404310  [ANA_INIT] PLL <<<<<<<< 

 7144 12:21:38.407742  [ANA_INIT] MIDPI >>>>>>>> 

 7145 12:21:38.411018  [ANA_INIT] MIDPI <<<<<<<< 

 7146 12:21:38.411175  [ANA_INIT] DLL >>>>>>>> 

 7147 12:21:38.414597  [ANA_INIT] DLL <<<<<<<< 

 7148 12:21:38.417675  [ANA_INIT] flow end 

 7149 12:21:38.420707  ============ LP4 DIFF to SE enter ============

 7150 12:21:38.424452  ============ LP4 DIFF to SE exit  ============

 7151 12:21:38.427859  [ANA_INIT] <<<<<<<<<<<<< 

 7152 12:21:38.430749  [Flow] Enable top DCM control >>>>> 

 7153 12:21:38.434387  [Flow] Enable top DCM control <<<<< 

 7154 12:21:38.437250  Enable DLL master slave shuffle 

 7155 12:21:38.440999  ============================================================== 

 7156 12:21:38.444133  Gating Mode config

 7157 12:21:38.450767  ============================================================== 

 7158 12:21:38.450849  Config description: 

 7159 12:21:38.460485  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7160 12:21:38.467234  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7161 12:21:38.470268  SELPH_MODE            0: By rank         1: By Phase 

 7162 12:21:38.476885  ============================================================== 

 7163 12:21:38.480120  GAT_TRACK_EN                 =  1

 7164 12:21:38.483723  RX_GATING_MODE               =  2

 7165 12:21:38.486895  RX_GATING_TRACK_MODE         =  2

 7166 12:21:38.490013  SELPH_MODE                   =  1

 7167 12:21:38.493689  PICG_EARLY_EN                =  1

 7168 12:21:38.497042  VALID_LAT_VALUE              =  1

 7169 12:21:38.499960  ============================================================== 

 7170 12:21:38.503306  Enter into Gating configuration >>>> 

 7171 12:21:38.506898  Exit from Gating configuration <<<< 

 7172 12:21:38.510203  Enter into  DVFS_PRE_config >>>>> 

 7173 12:21:38.523322  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7174 12:21:38.523419  Exit from  DVFS_PRE_config <<<<< 

 7175 12:21:38.526414  Enter into PICG configuration >>>> 

 7176 12:21:38.530099  Exit from PICG configuration <<<< 

 7177 12:21:38.533355  [RX_INPUT] configuration >>>>> 

 7178 12:21:38.536631  [RX_INPUT] configuration <<<<< 

 7179 12:21:38.543211  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7180 12:21:38.546792  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7181 12:21:38.553577  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7182 12:21:38.560203  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7183 12:21:38.566607  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7184 12:21:38.572893  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7185 12:21:38.576596  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7186 12:21:38.579637  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7187 12:21:38.583178  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7188 12:21:38.589923  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7189 12:21:38.593122  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7190 12:21:38.596159  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7191 12:21:38.599794  =================================== 

 7192 12:21:38.603332  LPDDR4 DRAM CONFIGURATION

 7193 12:21:38.606414  =================================== 

 7194 12:21:38.609477  EX_ROW_EN[0]    = 0x0

 7195 12:21:38.609561  EX_ROW_EN[1]    = 0x0

 7196 12:21:38.612900  LP4Y_EN      = 0x0

 7197 12:21:38.612983  WORK_FSP     = 0x1

 7198 12:21:38.615946  WL           = 0x5

 7199 12:21:38.616030  RL           = 0x5

 7200 12:21:38.619638  BL           = 0x2

 7201 12:21:38.619722  RPST         = 0x0

 7202 12:21:38.622864  RD_PRE       = 0x0

 7203 12:21:38.622947  WR_PRE       = 0x1

 7204 12:21:38.626241  WR_PST       = 0x1

 7205 12:21:38.626325  DBI_WR       = 0x0

 7206 12:21:38.629346  DBI_RD       = 0x0

 7207 12:21:38.629429  OTF          = 0x1

 7208 12:21:38.632397  =================================== 

 7209 12:21:38.639301  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7210 12:21:38.642526  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7211 12:21:38.645478  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7212 12:21:38.649009  =================================== 

 7213 12:21:38.652561  LPDDR4 DRAM CONFIGURATION

 7214 12:21:38.655728  =================================== 

 7215 12:21:38.658952  EX_ROW_EN[0]    = 0x10

 7216 12:21:38.659048  EX_ROW_EN[1]    = 0x0

 7217 12:21:38.662489  LP4Y_EN      = 0x0

 7218 12:21:38.662581  WORK_FSP     = 0x1

 7219 12:21:38.665517  WL           = 0x5

 7220 12:21:38.665602  RL           = 0x5

 7221 12:21:38.668753  BL           = 0x2

 7222 12:21:38.668837  RPST         = 0x0

 7223 12:21:38.671832  RD_PRE       = 0x0

 7224 12:21:38.671916  WR_PRE       = 0x1

 7225 12:21:38.675555  WR_PST       = 0x1

 7226 12:21:38.675668  DBI_WR       = 0x0

 7227 12:21:38.678726  DBI_RD       = 0x0

 7228 12:21:38.678808  OTF          = 0x1

 7229 12:21:38.681736  =================================== 

 7230 12:21:38.688312  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7231 12:21:38.688397  ==

 7232 12:21:38.691483  Dram Type= 6, Freq= 0, CH_0, rank 0

 7233 12:21:38.698412  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7234 12:21:38.698499  ==

 7235 12:21:38.698565  [Duty_Offset_Calibration]

 7236 12:21:38.701512  	B0:2	B1:0	CA:4

 7237 12:21:38.701621  

 7238 12:21:38.705156  [DutyScan_Calibration_Flow] k_type=0

 7239 12:21:38.714728  

 7240 12:21:38.714825  ==CLK 0==

 7241 12:21:38.717645  Final CLK duty delay cell = 0

 7242 12:21:38.720849  [0] MAX Duty = 5062%(X100), DQS PI = 20

 7243 12:21:38.724628  [0] MIN Duty = 4876%(X100), DQS PI = 54

 7244 12:21:38.724711  [0] AVG Duty = 4969%(X100)

 7245 12:21:38.727779  

 7246 12:21:38.731146  CH0 CLK Duty spec in!! Max-Min= 186%

 7247 12:21:38.734047  [DutyScan_Calibration_Flow] ====Done====

 7248 12:21:38.734138  

 7249 12:21:38.737842  [DutyScan_Calibration_Flow] k_type=1

 7250 12:21:38.753297  

 7251 12:21:38.753382  ==DQS 0 ==

 7252 12:21:38.756789  Final DQS duty delay cell = 0

 7253 12:21:38.760298  [0] MAX Duty = 5125%(X100), DQS PI = 30

 7254 12:21:38.763297  [0] MIN Duty = 4906%(X100), DQS PI = 50

 7255 12:21:38.766720  [0] AVG Duty = 5015%(X100)

 7256 12:21:38.766803  

 7257 12:21:38.766869  ==DQS 1 ==

 7258 12:21:38.770381  Final DQS duty delay cell = -4

 7259 12:21:38.773534  [-4] MAX Duty = 4969%(X100), DQS PI = 4

 7260 12:21:38.776668  [-4] MIN Duty = 4844%(X100), DQS PI = 12

 7261 12:21:38.780284  [-4] AVG Duty = 4906%(X100)

 7262 12:21:38.780369  

 7263 12:21:38.783153  CH0 DQS 0 Duty spec in!! Max-Min= 219%

 7264 12:21:38.783238  

 7265 12:21:38.786406  CH0 DQS 1 Duty spec in!! Max-Min= 125%

 7266 12:21:38.790056  [DutyScan_Calibration_Flow] ====Done====

 7267 12:21:38.790172  

 7268 12:21:38.793162  [DutyScan_Calibration_Flow] k_type=3

 7269 12:21:38.811837  

 7270 12:21:38.811935  ==DQM 0 ==

 7271 12:21:38.814752  Final DQM duty delay cell = 0

 7272 12:21:38.818399  [0] MAX Duty = 5156%(X100), DQS PI = 30

 7273 12:21:38.821388  [0] MIN Duty = 4875%(X100), DQS PI = 48

 7274 12:21:38.825073  [0] AVG Duty = 5015%(X100)

 7275 12:21:38.825159  

 7276 12:21:38.825226  ==DQM 1 ==

 7277 12:21:38.828280  Final DQM duty delay cell = 4

 7278 12:21:38.831459  [4] MAX Duty = 5187%(X100), DQS PI = 60

 7279 12:21:38.834604  [4] MIN Duty = 5000%(X100), DQS PI = 12

 7280 12:21:38.838211  [4] AVG Duty = 5093%(X100)

 7281 12:21:38.838296  

 7282 12:21:38.841162  CH0 DQM 0 Duty spec in!! Max-Min= 281%

 7283 12:21:38.841271  

 7284 12:21:38.844921  CH0 DQM 1 Duty spec in!! Max-Min= 187%

 7285 12:21:38.848071  [DutyScan_Calibration_Flow] ====Done====

 7286 12:21:38.848156  

 7287 12:21:38.851215  [DutyScan_Calibration_Flow] k_type=2

 7288 12:21:38.868058  

 7289 12:21:38.868149  ==DQ 0 ==

 7290 12:21:38.871243  Final DQ duty delay cell = -4

 7291 12:21:38.874158  [-4] MAX Duty = 5000%(X100), DQS PI = 16

 7292 12:21:38.877553  [-4] MIN Duty = 4876%(X100), DQS PI = 0

 7293 12:21:38.881328  [-4] AVG Duty = 4938%(X100)

 7294 12:21:38.881417  

 7295 12:21:38.881498  ==DQ 1 ==

 7296 12:21:38.884267  Final DQ duty delay cell = 0

 7297 12:21:38.887795  [0] MAX Duty = 5156%(X100), DQS PI = 58

 7298 12:21:38.891157  [0] MIN Duty = 5000%(X100), DQS PI = 16

 7299 12:21:38.894346  [0] AVG Duty = 5078%(X100)

 7300 12:21:38.894429  

 7301 12:21:38.897325  CH0 DQ 0 Duty spec in!! Max-Min= 124%

 7302 12:21:38.897408  

 7303 12:21:38.900925  CH0 DQ 1 Duty spec in!! Max-Min= 156%

 7304 12:21:38.904114  [DutyScan_Calibration_Flow] ====Done====

 7305 12:21:38.904197  ==

 7306 12:21:38.907352  Dram Type= 6, Freq= 0, CH_1, rank 0

 7307 12:21:38.910432  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7308 12:21:38.910531  ==

 7309 12:21:38.914147  [Duty_Offset_Calibration]

 7310 12:21:38.914232  	B0:1	B1:-2	CA:1

 7311 12:21:38.914298  

 7312 12:21:38.917145  [DutyScan_Calibration_Flow] k_type=0

 7313 12:21:38.928227  

 7314 12:21:38.928313  ==CLK 0==

 7315 12:21:38.931379  Final CLK duty delay cell = 0

 7316 12:21:38.935160  [0] MAX Duty = 5062%(X100), DQS PI = 20

 7317 12:21:38.938304  [0] MIN Duty = 4813%(X100), DQS PI = 60

 7318 12:21:38.938388  [0] AVG Duty = 4937%(X100)

 7319 12:21:38.941499  

 7320 12:21:38.945110  CH1 CLK Duty spec in!! Max-Min= 249%

 7321 12:21:38.948457  [DutyScan_Calibration_Flow] ====Done====

 7322 12:21:38.948539  

 7323 12:21:38.951342  [DutyScan_Calibration_Flow] k_type=1

 7324 12:21:38.967403  

 7325 12:21:38.967492  ==DQS 0 ==

 7326 12:21:38.970640  Final DQS duty delay cell = -4

 7327 12:21:38.973821  [-4] MAX Duty = 4969%(X100), DQS PI = 24

 7328 12:21:38.976993  [-4] MIN Duty = 4844%(X100), DQS PI = 48

 7329 12:21:38.980739  [-4] AVG Duty = 4906%(X100)

 7330 12:21:38.980822  

 7331 12:21:38.980888  ==DQS 1 ==

 7332 12:21:38.983638  Final DQS duty delay cell = 0

 7333 12:21:38.986995  [0] MAX Duty = 5093%(X100), DQS PI = 60

 7334 12:21:38.990289  [0] MIN Duty = 4844%(X100), DQS PI = 24

 7335 12:21:38.993916  [0] AVG Duty = 4968%(X100)

 7336 12:21:38.994002  

 7337 12:21:38.997063  CH1 DQS 0 Duty spec in!! Max-Min= 125%

 7338 12:21:38.997148  

 7339 12:21:39.000175  CH1 DQS 1 Duty spec in!! Max-Min= 249%

 7340 12:21:39.003690  [DutyScan_Calibration_Flow] ====Done====

 7341 12:21:39.003773  

 7342 12:21:39.007079  [DutyScan_Calibration_Flow] k_type=3

 7343 12:21:39.024390  

 7344 12:21:39.024483  ==DQM 0 ==

 7345 12:21:39.027356  Final DQM duty delay cell = 0

 7346 12:21:39.031019  [0] MAX Duty = 5031%(X100), DQS PI = 26

 7347 12:21:39.034012  [0] MIN Duty = 4813%(X100), DQS PI = 54

 7348 12:21:39.037651  [0] AVG Duty = 4922%(X100)

 7349 12:21:39.037766  

 7350 12:21:39.037865  ==DQM 1 ==

 7351 12:21:39.040871  Final DQM duty delay cell = 0

 7352 12:21:39.044565  [0] MAX Duty = 5062%(X100), DQS PI = 34

 7353 12:21:39.047754  [0] MIN Duty = 4875%(X100), DQS PI = 24

 7354 12:21:39.050704  [0] AVG Duty = 4968%(X100)

 7355 12:21:39.050819  

 7356 12:21:39.054259  CH1 DQM 0 Duty spec in!! Max-Min= 218%

 7357 12:21:39.054343  

 7358 12:21:39.057515  CH1 DQM 1 Duty spec in!! Max-Min= 187%

 7359 12:21:39.060602  [DutyScan_Calibration_Flow] ====Done====

 7360 12:21:39.060686  

 7361 12:21:39.064215  [DutyScan_Calibration_Flow] k_type=2

 7362 12:21:39.081334  

 7363 12:21:39.081422  ==DQ 0 ==

 7364 12:21:39.084632  Final DQ duty delay cell = 0

 7365 12:21:39.088002  [0] MAX Duty = 5093%(X100), DQS PI = 22

 7366 12:21:39.091143  [0] MIN Duty = 4907%(X100), DQS PI = 62

 7367 12:21:39.091228  [0] AVG Duty = 5000%(X100)

 7368 12:21:39.094417  

 7369 12:21:39.094528  ==DQ 1 ==

 7370 12:21:39.097831  Final DQ duty delay cell = 0

 7371 12:21:39.101167  [0] MAX Duty = 5156%(X100), DQS PI = 36

 7372 12:21:39.104161  [0] MIN Duty = 4969%(X100), DQS PI = 24

 7373 12:21:39.104245  [0] AVG Duty = 5062%(X100)

 7374 12:21:39.107703  

 7375 12:21:39.111284  CH1 DQ 0 Duty spec in!! Max-Min= 186%

 7376 12:21:39.111412  

 7377 12:21:39.114152  CH1 DQ 1 Duty spec in!! Max-Min= 187%

 7378 12:21:39.117906  [DutyScan_Calibration_Flow] ====Done====

 7379 12:21:39.121088  nWR fixed to 30

 7380 12:21:39.121168  [ModeRegInit_LP4] CH0 RK0

 7381 12:21:39.124218  [ModeRegInit_LP4] CH0 RK1

 7382 12:21:39.127844  [ModeRegInit_LP4] CH1 RK0

 7383 12:21:39.130808  [ModeRegInit_LP4] CH1 RK1

 7384 12:21:39.130913  match AC timing 5

 7385 12:21:39.137696  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7386 12:21:39.141166  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7387 12:21:39.144348  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7388 12:21:39.150792  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7389 12:21:39.154043  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7390 12:21:39.154147  [MiockJmeterHQA]

 7391 12:21:39.154243  

 7392 12:21:39.157628  [DramcMiockJmeter] u1RxGatingPI = 0

 7393 12:21:39.160601  0 : 4257, 4032

 7394 12:21:39.160679  4 : 4257, 4032

 7395 12:21:39.164004  8 : 4365, 4140

 7396 12:21:39.164079  12 : 4257, 4029

 7397 12:21:39.164143  16 : 4255, 4029

 7398 12:21:39.167425  20 : 4257, 4031

 7399 12:21:39.167510  24 : 4257, 4029

 7400 12:21:39.170454  28 : 4365, 4140

 7401 12:21:39.170531  32 : 4255, 4029

 7402 12:21:39.174029  36 : 4252, 4029

 7403 12:21:39.174104  40 : 4257, 4030

 7404 12:21:39.177093  44 : 4255, 4029

 7405 12:21:39.177163  48 : 4252, 4029

 7406 12:21:39.177228  52 : 4252, 4029

 7407 12:21:39.180859  56 : 4365, 4139

 7408 12:21:39.180933  60 : 4253, 4029

 7409 12:21:39.183935  64 : 4253, 4029

 7410 12:21:39.184036  68 : 4363, 4140

 7411 12:21:39.187119  72 : 4255, 4029

 7412 12:21:39.187235  76 : 4250, 4027

 7413 12:21:39.187341  80 : 4252, 4029

 7414 12:21:39.190396  84 : 4257, 4031

 7415 12:21:39.190502  88 : 4252, 4029

 7416 12:21:39.193970  92 : 4252, 4030

 7417 12:21:39.194056  96 : 4255, 4029

 7418 12:21:39.197115  100 : 4252, 4029

 7419 12:21:39.197199  104 : 4252, 3558

 7420 12:21:39.200918  108 : 4368, 3

 7421 12:21:39.201002  112 : 4363, 0

 7422 12:21:39.201104  116 : 4254, 0

 7423 12:21:39.203910  120 : 4255, 0

 7424 12:21:39.204006  124 : 4252, 0

 7425 12:21:39.206929  128 : 4253, 0

 7426 12:21:39.207009  132 : 4252, 0

 7427 12:21:39.207073  136 : 4255, 0

 7428 12:21:39.210332  140 : 4252, 0

 7429 12:21:39.210407  144 : 4252, 0

 7430 12:21:39.210470  148 : 4255, 0

 7431 12:21:39.213693  152 : 4253, 0

 7432 12:21:39.213772  156 : 4252, 0

 7433 12:21:39.217018  160 : 4368, 0

 7434 12:21:39.217095  164 : 4363, 0

 7435 12:21:39.217167  168 : 4366, 0

 7436 12:21:39.220618  172 : 4368, 0

 7437 12:21:39.220693  176 : 4253, 0

 7438 12:21:39.223719  180 : 4363, 0

 7439 12:21:39.223826  184 : 4363, 0

 7440 12:21:39.223920  188 : 4250, 0

 7441 12:21:39.226839  192 : 4253, 0

 7442 12:21:39.226946  196 : 4255, 0

 7443 12:21:39.230083  200 : 4258, 0

 7444 12:21:39.230176  204 : 4252, 0

 7445 12:21:39.230250  208 : 4363, 0

 7446 12:21:39.233302  212 : 4254, 0

 7447 12:21:39.233401  216 : 4363, 0

 7448 12:21:39.237225  220 : 4366, 0

 7449 12:21:39.237338  224 : 4368, 0

 7450 12:21:39.237439  228 : 4253, 0

 7451 12:21:39.240375  232 : 4363, 0

 7452 12:21:39.240490  236 : 4363, 1305

 7453 12:21:39.243512  240 : 4363, 4139

 7454 12:21:39.243617  244 : 4252, 4029

 7455 12:21:39.247093  248 : 4253, 4029

 7456 12:21:39.247181  252 : 4255, 4029

 7457 12:21:39.247248  256 : 4255, 4029

 7458 12:21:39.250214  260 : 4253, 4029

 7459 12:21:39.250331  264 : 4253, 4029

 7460 12:21:39.253714  268 : 4258, 4032

 7461 12:21:39.253802  272 : 4255, 4029

 7462 12:21:39.256683  276 : 4363, 4140

 7463 12:21:39.256815  280 : 4363, 4140

 7464 12:21:39.260030  284 : 4252, 4026

 7465 12:21:39.260118  288 : 4252, 4027

 7466 12:21:39.263147  292 : 4250, 4026

 7467 12:21:39.263262  296 : 4253, 4029

 7468 12:21:39.266745  300 : 4257, 4031

 7469 12:21:39.266824  304 : 4365, 4139

 7470 12:21:39.270254  308 : 4254, 4029

 7471 12:21:39.270340  312 : 4365, 4140

 7472 12:21:39.273195  316 : 4250, 4027

 7473 12:21:39.273273  320 : 4253, 4029

 7474 12:21:39.273338  324 : 4255, 4029

 7475 12:21:39.276534  328 : 4253, 4029

 7476 12:21:39.276636  332 : 4253, 4029

 7477 12:21:39.280299  336 : 4257, 4031

 7478 12:21:39.280415  340 : 4255, 4029

 7479 12:21:39.283505  344 : 4366, 4140

 7480 12:21:39.283596  348 : 4252, 4029

 7481 12:21:39.286726  352 : 4253, 4028

 7482 12:21:39.286834  356 : 4257, 2801

 7483 12:21:39.289800  360 : 4365, 17

 7484 12:21:39.289906  

 7485 12:21:39.289998  	MIOCK jitter meter	ch=0

 7486 12:21:39.290096  

 7487 12:21:39.293003  1T = (360-108) = 252 dly cells

 7488 12:21:39.300093  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps

 7489 12:21:39.300184  ==

 7490 12:21:39.303125  Dram Type= 6, Freq= 0, CH_0, rank 0

 7491 12:21:39.306717  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7492 12:21:39.306806  ==

 7493 12:21:39.313424  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7494 12:21:39.316477  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7495 12:21:39.319918  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7496 12:21:39.326530  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7497 12:21:39.336295  [CA 0] Center 43 (13~74) winsize 62

 7498 12:21:39.339563  [CA 1] Center 43 (13~74) winsize 62

 7499 12:21:39.342605  [CA 2] Center 39 (10~68) winsize 59

 7500 12:21:39.346356  [CA 3] Center 39 (10~68) winsize 59

 7501 12:21:39.349447  [CA 4] Center 36 (7~66) winsize 60

 7502 12:21:39.352650  [CA 5] Center 36 (7~66) winsize 60

 7503 12:21:39.352727  

 7504 12:21:39.356268  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7505 12:21:39.356349  

 7506 12:21:39.359566  [CATrainingPosCal] consider 1 rank data

 7507 12:21:39.362584  u2DelayCellTimex100 = 258/100 ps

 7508 12:21:39.369370  CA0 delay=43 (13~74),Diff = 7 PI (26 cell)

 7509 12:21:39.372512  CA1 delay=43 (13~74),Diff = 7 PI (26 cell)

 7510 12:21:39.376006  CA2 delay=39 (10~68),Diff = 3 PI (11 cell)

 7511 12:21:39.379480  CA3 delay=39 (10~68),Diff = 3 PI (11 cell)

 7512 12:21:39.382798  CA4 delay=36 (7~66),Diff = 0 PI (0 cell)

 7513 12:21:39.385926  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 7514 12:21:39.386020  

 7515 12:21:39.389362  CA PerBit enable=1, Macro0, CA PI delay=36

 7516 12:21:39.389445  

 7517 12:21:39.392441  [CBTSetCACLKResult] CA Dly = 36

 7518 12:21:39.395601  CS Dly: 11 (0~42)

 7519 12:21:39.399350  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7520 12:21:39.402457  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7521 12:21:39.402568  ==

 7522 12:21:39.405603  Dram Type= 6, Freq= 0, CH_0, rank 1

 7523 12:21:39.412479  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7524 12:21:39.412594  ==

 7525 12:21:39.415589  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7526 12:21:39.422465  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7527 12:21:39.425553  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7528 12:21:39.432269  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7529 12:21:39.440301  [CA 0] Center 44 (14~75) winsize 62

 7530 12:21:39.443395  [CA 1] Center 43 (13~74) winsize 62

 7531 12:21:39.447157  [CA 2] Center 39 (10~69) winsize 60

 7532 12:21:39.450272  [CA 3] Center 39 (10~69) winsize 60

 7533 12:21:39.453395  [CA 4] Center 37 (8~67) winsize 60

 7534 12:21:39.457066  [CA 5] Center 37 (7~67) winsize 61

 7535 12:21:39.457169  

 7536 12:21:39.460196  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7537 12:21:39.460299  

 7538 12:21:39.463822  [CATrainingPosCal] consider 2 rank data

 7539 12:21:39.466889  u2DelayCellTimex100 = 258/100 ps

 7540 12:21:39.473437  CA0 delay=44 (14~74),Diff = 8 PI (30 cell)

 7541 12:21:39.476510  CA1 delay=43 (13~74),Diff = 7 PI (26 cell)

 7542 12:21:39.480090  CA2 delay=39 (10~68),Diff = 3 PI (11 cell)

 7543 12:21:39.483292  CA3 delay=39 (10~68),Diff = 3 PI (11 cell)

 7544 12:21:39.486553  CA4 delay=37 (8~66),Diff = 1 PI (3 cell)

 7545 12:21:39.490057  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 7546 12:21:39.490173  

 7547 12:21:39.493094  CA PerBit enable=1, Macro0, CA PI delay=36

 7548 12:21:39.493199  

 7549 12:21:39.496323  [CBTSetCACLKResult] CA Dly = 36

 7550 12:21:39.499720  CS Dly: 11 (0~43)

 7551 12:21:39.503216  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7552 12:21:39.506086  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7553 12:21:39.506161  

 7554 12:21:39.509774  ----->DramcWriteLeveling(PI) begin...

 7555 12:21:39.513046  ==

 7556 12:21:39.513131  Dram Type= 6, Freq= 0, CH_0, rank 0

 7557 12:21:39.519695  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7558 12:21:39.519779  ==

 7559 12:21:39.522742  Write leveling (Byte 0): 38 => 38

 7560 12:21:39.526320  Write leveling (Byte 1): 29 => 29

 7561 12:21:39.529365  DramcWriteLeveling(PI) end<-----

 7562 12:21:39.529449  

 7563 12:21:39.529515  ==

 7564 12:21:39.532428  Dram Type= 6, Freq= 0, CH_0, rank 0

 7565 12:21:39.536119  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7566 12:21:39.536203  ==

 7567 12:21:39.539597  [Gating] SW mode calibration

 7568 12:21:39.546240  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7569 12:21:39.552498  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7570 12:21:39.555746   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7571 12:21:39.559382   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7572 12:21:39.566092   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7573 12:21:39.568929   1  4 12 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)

 7574 12:21:39.572616   1  4 16 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)

 7575 12:21:39.578811   1  4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)

 7576 12:21:39.582629   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7577 12:21:39.585831   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7578 12:21:39.588806   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7579 12:21:39.595296   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7580 12:21:39.598643   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7581 12:21:39.605403   1  5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7582 12:21:39.608654   1  5 16 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)

 7583 12:21:39.611786   1  5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)

 7584 12:21:39.615212   1  5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)

 7585 12:21:39.622026   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7586 12:21:39.625172   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7587 12:21:39.628327   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7588 12:21:39.635309   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7589 12:21:39.638339   1  6 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)

 7590 12:21:39.645225   1  6 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)

 7591 12:21:39.648433   1  6 20 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)

 7592 12:21:39.652001   1  6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)

 7593 12:21:39.654922   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7594 12:21:39.661800   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7595 12:21:39.664911   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7596 12:21:39.668254   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7597 12:21:39.674857   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7598 12:21:39.677875   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7599 12:21:39.681334   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7600 12:21:39.688217   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7601 12:21:39.691541   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7602 12:21:39.694624   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7603 12:21:39.701419   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7604 12:21:39.704309   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7605 12:21:39.707700   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7606 12:21:39.714573   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7607 12:21:39.717981   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7608 12:21:39.721230   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7609 12:21:39.727772   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7610 12:21:39.730804   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7611 12:21:39.734271   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7612 12:21:39.740868   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7613 12:21:39.744538   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7614 12:21:39.747729   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7615 12:21:39.754117   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7616 12:21:39.757232   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7617 12:21:39.761076  Total UI for P1: 0, mck2ui 16

 7618 12:21:39.764056  best dqsien dly found for B0: ( 1,  9, 18)

 7619 12:21:39.767134   1  9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7620 12:21:39.774091   1 10  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7621 12:21:39.774178  Total UI for P1: 0, mck2ui 16

 7622 12:21:39.780787  best dqsien dly found for B1: ( 1,  9, 26)

 7623 12:21:39.783979  best DQS0 dly(MCK, UI, PI) = (1, 9, 18)

 7624 12:21:39.787088  best DQS1 dly(MCK, UI, PI) = (1, 9, 26)

 7625 12:21:39.787169  

 7626 12:21:39.790639  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)

 7627 12:21:39.793903  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 26)

 7628 12:21:39.797513  [Gating] SW calibration Done

 7629 12:21:39.797591  ==

 7630 12:21:39.800675  Dram Type= 6, Freq= 0, CH_0, rank 0

 7631 12:21:39.803714  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7632 12:21:39.803786  ==

 7633 12:21:39.806853  RX Vref Scan: 0

 7634 12:21:39.806928  

 7635 12:21:39.806990  RX Vref 0 -> 0, step: 1

 7636 12:21:39.810468  

 7637 12:21:39.810549  RX Delay 0 -> 252, step: 8

 7638 12:21:39.813589  iDelay=192, Bit 0, Center 127 (72 ~ 183) 112

 7639 12:21:39.820560  iDelay=192, Bit 1, Center 131 (80 ~ 183) 104

 7640 12:21:39.823767  iDelay=192, Bit 2, Center 127 (72 ~ 183) 112

 7641 12:21:39.826800  iDelay=192, Bit 3, Center 119 (64 ~ 175) 112

 7642 12:21:39.830359  iDelay=192, Bit 4, Center 127 (72 ~ 183) 112

 7643 12:21:39.836748  iDelay=192, Bit 5, Center 111 (56 ~ 167) 112

 7644 12:21:39.840216  iDelay=192, Bit 6, Center 139 (88 ~ 191) 104

 7645 12:21:39.843195  iDelay=192, Bit 7, Center 139 (88 ~ 191) 104

 7646 12:21:39.846444  iDelay=192, Bit 8, Center 115 (56 ~ 175) 120

 7647 12:21:39.850164  iDelay=192, Bit 9, Center 111 (56 ~ 167) 112

 7648 12:21:39.856395  iDelay=192, Bit 10, Center 123 (64 ~ 183) 120

 7649 12:21:39.860082  iDelay=192, Bit 11, Center 115 (56 ~ 175) 120

 7650 12:21:39.863220  iDelay=192, Bit 12, Center 127 (72 ~ 183) 112

 7651 12:21:39.866271  iDelay=192, Bit 13, Center 131 (72 ~ 191) 120

 7652 12:21:39.870009  iDelay=192, Bit 14, Center 135 (80 ~ 191) 112

 7653 12:21:39.876211  iDelay=192, Bit 15, Center 131 (72 ~ 191) 120

 7654 12:21:39.876295  ==

 7655 12:21:39.879923  Dram Type= 6, Freq= 0, CH_0, rank 0

 7656 12:21:39.882930  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7657 12:21:39.883010  ==

 7658 12:21:39.883075  DQS Delay:

 7659 12:21:39.886317  DQS0 = 0, DQS1 = 0

 7660 12:21:39.886395  DQM Delay:

 7661 12:21:39.889421  DQM0 = 127, DQM1 = 123

 7662 12:21:39.889497  DQ Delay:

 7663 12:21:39.893145  DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119

 7664 12:21:39.896495  DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139

 7665 12:21:39.899466  DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115

 7666 12:21:39.902626  DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131

 7667 12:21:39.906294  

 7668 12:21:39.906380  

 7669 12:21:39.906445  ==

 7670 12:21:39.909497  Dram Type= 6, Freq= 0, CH_0, rank 0

 7671 12:21:39.912640  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7672 12:21:39.912719  ==

 7673 12:21:39.912783  

 7674 12:21:39.912843  

 7675 12:21:39.916394  	TX Vref Scan disable

 7676 12:21:39.916466   == TX Byte 0 ==

 7677 12:21:39.922583  Update DQ  dly =995 (3 ,6, 35)  DQ  OEN =(3 ,3)

 7678 12:21:39.926269  Update DQM dly =995 (3 ,6, 35)  DQM OEN =(3 ,3)

 7679 12:21:39.926351   == TX Byte 1 ==

 7680 12:21:39.932802  Update DQ  dly =984 (3 ,6, 24)  DQ  OEN =(3 ,3)

 7681 12:21:39.935994  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 7682 12:21:39.936076  ==

 7683 12:21:39.939518  Dram Type= 6, Freq= 0, CH_0, rank 0

 7684 12:21:39.942826  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7685 12:21:39.942930  ==

 7686 12:21:39.957093  

 7687 12:21:39.960962  TX Vref early break, caculate TX vref

 7688 12:21:39.963770  TX Vref=16, minBit 8, minWin=20, winSum=360

 7689 12:21:39.967224  TX Vref=18, minBit 8, minWin=21, winSum=369

 7690 12:21:39.970242  TX Vref=20, minBit 8, minWin=22, winSum=382

 7691 12:21:39.973953  TX Vref=22, minBit 8, minWin=22, winSum=389

 7692 12:21:39.977136  TX Vref=24, minBit 9, minWin=23, winSum=398

 7693 12:21:39.983554  TX Vref=26, minBit 8, minWin=24, winSum=401

 7694 12:21:39.986665  TX Vref=28, minBit 8, minWin=24, winSum=405

 7695 12:21:39.990516  TX Vref=30, minBit 9, minWin=23, winSum=392

 7696 12:21:39.993579  TX Vref=32, minBit 8, minWin=23, winSum=389

 7697 12:21:39.997176  TX Vref=34, minBit 8, minWin=22, winSum=380

 7698 12:21:40.003478  [TxChooseVref] Worse bit 8, Min win 24, Win sum 405, Final Vref 28

 7699 12:21:40.003592  

 7700 12:21:40.006866  Final TX Range 0 Vref 28

 7701 12:21:40.006968  

 7702 12:21:40.007067  ==

 7703 12:21:40.009889  Dram Type= 6, Freq= 0, CH_0, rank 0

 7704 12:21:40.013926  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7705 12:21:40.014009  ==

 7706 12:21:40.014075  

 7707 12:21:40.014135  

 7708 12:21:40.016760  	TX Vref Scan disable

 7709 12:21:40.023215  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps

 7710 12:21:40.023351   == TX Byte 0 ==

 7711 12:21:40.026955  u2DelayCellOfst[0]=7 cells (2 PI)

 7712 12:21:40.030115  u2DelayCellOfst[1]=11 cells (3 PI)

 7713 12:21:40.033346  u2DelayCellOfst[2]=7 cells (2 PI)

 7714 12:21:40.037009  u2DelayCellOfst[3]=7 cells (2 PI)

 7715 12:21:40.040043  u2DelayCellOfst[4]=7 cells (2 PI)

 7716 12:21:40.043564  u2DelayCellOfst[5]=0 cells (0 PI)

 7717 12:21:40.046932  u2DelayCellOfst[6]=11 cells (3 PI)

 7718 12:21:40.047009  u2DelayCellOfst[7]=11 cells (3 PI)

 7719 12:21:40.053564  Update DQ  dly =993 (3 ,6, 33)  DQ  OEN =(3 ,3)

 7720 12:21:40.056694  Update DQM dly =994 (3 ,6, 34)  DQM OEN =(3 ,3)

 7721 12:21:40.056777   == TX Byte 1 ==

 7722 12:21:40.059831  u2DelayCellOfst[8]=0 cells (0 PI)

 7723 12:21:40.063050  u2DelayCellOfst[9]=3 cells (1 PI)

 7724 12:21:40.066503  u2DelayCellOfst[10]=7 cells (2 PI)

 7725 12:21:40.070248  u2DelayCellOfst[11]=7 cells (2 PI)

 7726 12:21:40.073376  u2DelayCellOfst[12]=15 cells (4 PI)

 7727 12:21:40.076751  u2DelayCellOfst[13]=15 cells (4 PI)

 7728 12:21:40.080073  u2DelayCellOfst[14]=18 cells (5 PI)

 7729 12:21:40.083429  u2DelayCellOfst[15]=15 cells (4 PI)

 7730 12:21:40.086561  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 7731 12:21:40.093466  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 7732 12:21:40.093556  DramC Write-DBI on

 7733 12:21:40.093623  ==

 7734 12:21:40.096569  Dram Type= 6, Freq= 0, CH_0, rank 0

 7735 12:21:40.099630  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7736 12:21:40.099705  ==

 7737 12:21:40.103234  

 7738 12:21:40.103353  

 7739 12:21:40.103441  	TX Vref Scan disable

 7740 12:21:40.106581   == TX Byte 0 ==

 7741 12:21:40.109532  Update DQM dly =739 (2 ,6, 35)  DQM OEN =(3 ,3)

 7742 12:21:40.112693   == TX Byte 1 ==

 7743 12:21:40.116122  Update DQM dly =726 (2 ,6, 22)  DQM OEN =(3 ,3)

 7744 12:21:40.119453  DramC Write-DBI off

 7745 12:21:40.119538  

 7746 12:21:40.119613  [DATLAT]

 7747 12:21:40.119673  Freq=1600, CH0 RK0

 7748 12:21:40.119734  

 7749 12:21:40.122965  DATLAT Default: 0xf

 7750 12:21:40.123035  0, 0xFFFF, sum = 0

 7751 12:21:40.126542  1, 0xFFFF, sum = 0

 7752 12:21:40.126648  2, 0xFFFF, sum = 0

 7753 12:21:40.129624  3, 0xFFFF, sum = 0

 7754 12:21:40.133271  4, 0xFFFF, sum = 0

 7755 12:21:40.133354  5, 0xFFFF, sum = 0

 7756 12:21:40.136417  6, 0xFFFF, sum = 0

 7757 12:21:40.136501  7, 0xFFFF, sum = 0

 7758 12:21:40.139497  8, 0xFFFF, sum = 0

 7759 12:21:40.139581  9, 0xFFFF, sum = 0

 7760 12:21:40.143186  10, 0xFFFF, sum = 0

 7761 12:21:40.143270  11, 0xFFFF, sum = 0

 7762 12:21:40.146309  12, 0xFFFF, sum = 0

 7763 12:21:40.146394  13, 0xCFFF, sum = 0

 7764 12:21:40.149460  14, 0x0, sum = 1

 7765 12:21:40.149544  15, 0x0, sum = 2

 7766 12:21:40.153325  16, 0x0, sum = 3

 7767 12:21:40.153409  17, 0x0, sum = 4

 7768 12:21:40.156239  best_step = 15

 7769 12:21:40.156347  

 7770 12:21:40.156444  ==

 7771 12:21:40.159677  Dram Type= 6, Freq= 0, CH_0, rank 0

 7772 12:21:40.163004  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7773 12:21:40.163088  ==

 7774 12:21:40.163153  RX Vref Scan: 1

 7775 12:21:40.166223  

 7776 12:21:40.166305  Set Vref Range= 24 -> 127

 7777 12:21:40.166370  

 7778 12:21:40.169732  RX Vref 24 -> 127, step: 1

 7779 12:21:40.169814  

 7780 12:21:40.173035  RX Delay 11 -> 252, step: 4

 7781 12:21:40.173118  

 7782 12:21:40.176478  Set Vref, RX VrefLevel [Byte0]: 24

 7783 12:21:40.179600                           [Byte1]: 24

 7784 12:21:40.179680  

 7785 12:21:40.182690  Set Vref, RX VrefLevel [Byte0]: 25

 7786 12:21:40.186462                           [Byte1]: 25

 7787 12:21:40.186540  

 7788 12:21:40.189479  Set Vref, RX VrefLevel [Byte0]: 26

 7789 12:21:40.193094                           [Byte1]: 26

 7790 12:21:40.196821  

 7791 12:21:40.196902  Set Vref, RX VrefLevel [Byte0]: 27

 7792 12:21:40.200161                           [Byte1]: 27

 7793 12:21:40.204301  

 7794 12:21:40.204394  Set Vref, RX VrefLevel [Byte0]: 28

 7795 12:21:40.207392                           [Byte1]: 28

 7796 12:21:40.212028  

 7797 12:21:40.212112  Set Vref, RX VrefLevel [Byte0]: 29

 7798 12:21:40.215583                           [Byte1]: 29

 7799 12:21:40.219931  

 7800 12:21:40.220048  Set Vref, RX VrefLevel [Byte0]: 30

 7801 12:21:40.222819                           [Byte1]: 30

 7802 12:21:40.227266  

 7803 12:21:40.227363  Set Vref, RX VrefLevel [Byte0]: 31

 7804 12:21:40.230669                           [Byte1]: 31

 7805 12:21:40.234735  

 7806 12:21:40.234817  Set Vref, RX VrefLevel [Byte0]: 32

 7807 12:21:40.238302                           [Byte1]: 32

 7808 12:21:40.242678  

 7809 12:21:40.242758  Set Vref, RX VrefLevel [Byte0]: 33

 7810 12:21:40.245828                           [Byte1]: 33

 7811 12:21:40.250089  

 7812 12:21:40.250164  Set Vref, RX VrefLevel [Byte0]: 34

 7813 12:21:40.253129                           [Byte1]: 34

 7814 12:21:40.257964  

 7815 12:21:40.258048  Set Vref, RX VrefLevel [Byte0]: 35

 7816 12:21:40.261025                           [Byte1]: 35

 7817 12:21:40.265270  

 7818 12:21:40.265382  Set Vref, RX VrefLevel [Byte0]: 36

 7819 12:21:40.268346                           [Byte1]: 36

 7820 12:21:40.272997  

 7821 12:21:40.273075  Set Vref, RX VrefLevel [Byte0]: 37

 7822 12:21:40.276040                           [Byte1]: 37

 7823 12:21:40.280814  

 7824 12:21:40.280899  Set Vref, RX VrefLevel [Byte0]: 38

 7825 12:21:40.283704                           [Byte1]: 38

 7826 12:21:40.287942  

 7827 12:21:40.288050  Set Vref, RX VrefLevel [Byte0]: 39

 7828 12:21:40.291092                           [Byte1]: 39

 7829 12:21:40.295628  

 7830 12:21:40.295712  Set Vref, RX VrefLevel [Byte0]: 40

 7831 12:21:40.298960                           [Byte1]: 40

 7832 12:21:40.303362  

 7833 12:21:40.303452  Set Vref, RX VrefLevel [Byte0]: 41

 7834 12:21:40.306887                           [Byte1]: 41

 7835 12:21:40.311026  

 7836 12:21:40.311113  Set Vref, RX VrefLevel [Byte0]: 42

 7837 12:21:40.314368                           [Byte1]: 42

 7838 12:21:40.318354  

 7839 12:21:40.318480  Set Vref, RX VrefLevel [Byte0]: 43

 7840 12:21:40.322075                           [Byte1]: 43

 7841 12:21:40.326519  

 7842 12:21:40.326602  Set Vref, RX VrefLevel [Byte0]: 44

 7843 12:21:40.329396                           [Byte1]: 44

 7844 12:21:40.333690  

 7845 12:21:40.333774  Set Vref, RX VrefLevel [Byte0]: 45

 7846 12:21:40.337259                           [Byte1]: 45

 7847 12:21:40.341264  

 7848 12:21:40.341340  Set Vref, RX VrefLevel [Byte0]: 46

 7849 12:21:40.344989                           [Byte1]: 46

 7850 12:21:40.348711  

 7851 12:21:40.348821  Set Vref, RX VrefLevel [Byte0]: 47

 7852 12:21:40.352483                           [Byte1]: 47

 7853 12:21:40.356753  

 7854 12:21:40.356856  Set Vref, RX VrefLevel [Byte0]: 48

 7855 12:21:40.359881                           [Byte1]: 48

 7856 12:21:40.364163  

 7857 12:21:40.364243  Set Vref, RX VrefLevel [Byte0]: 49

 7858 12:21:40.367795                           [Byte1]: 49

 7859 12:21:40.372152  

 7860 12:21:40.372257  Set Vref, RX VrefLevel [Byte0]: 50

 7861 12:21:40.375133                           [Byte1]: 50

 7862 12:21:40.379297  

 7863 12:21:40.379382  Set Vref, RX VrefLevel [Byte0]: 51

 7864 12:21:40.383000                           [Byte1]: 51

 7865 12:21:40.387156  

 7866 12:21:40.387274  Set Vref, RX VrefLevel [Byte0]: 52

 7867 12:21:40.390215                           [Byte1]: 52

 7868 12:21:40.394405  

 7869 12:21:40.394489  Set Vref, RX VrefLevel [Byte0]: 53

 7870 12:21:40.397845                           [Byte1]: 53

 7871 12:21:40.402432  

 7872 12:21:40.402513  Set Vref, RX VrefLevel [Byte0]: 54

 7873 12:21:40.405825                           [Byte1]: 54

 7874 12:21:40.409754  

 7875 12:21:40.409864  Set Vref, RX VrefLevel [Byte0]: 55

 7876 12:21:40.413092                           [Byte1]: 55

 7877 12:21:40.417609  

 7878 12:21:40.417694  Set Vref, RX VrefLevel [Byte0]: 56

 7879 12:21:40.421115                           [Byte1]: 56

 7880 12:21:40.424934  

 7881 12:21:40.425017  Set Vref, RX VrefLevel [Byte0]: 57

 7882 12:21:40.428393                           [Byte1]: 57

 7883 12:21:40.432976  

 7884 12:21:40.433055  Set Vref, RX VrefLevel [Byte0]: 58

 7885 12:21:40.435813                           [Byte1]: 58

 7886 12:21:40.440327  

 7887 12:21:40.440407  Set Vref, RX VrefLevel [Byte0]: 59

 7888 12:21:40.443658                           [Byte1]: 59

 7889 12:21:40.447833  

 7890 12:21:40.447914  Set Vref, RX VrefLevel [Byte0]: 60

 7891 12:21:40.451525                           [Byte1]: 60

 7892 12:21:40.455823  

 7893 12:21:40.455901  Set Vref, RX VrefLevel [Byte0]: 61

 7894 12:21:40.458951                           [Byte1]: 61

 7895 12:21:40.463318  

 7896 12:21:40.463411  Set Vref, RX VrefLevel [Byte0]: 62

 7897 12:21:40.466455                           [Byte1]: 62

 7898 12:21:40.470799  

 7899 12:21:40.470893  Set Vref, RX VrefLevel [Byte0]: 63

 7900 12:21:40.473791                           [Byte1]: 63

 7901 12:21:40.478166  

 7902 12:21:40.478242  Set Vref, RX VrefLevel [Byte0]: 64

 7903 12:21:40.481626                           [Byte1]: 64

 7904 12:21:40.485878  

 7905 12:21:40.485997  Set Vref, RX VrefLevel [Byte0]: 65

 7906 12:21:40.489585                           [Byte1]: 65

 7907 12:21:40.493855  

 7908 12:21:40.493942  Set Vref, RX VrefLevel [Byte0]: 66

 7909 12:21:40.496847                           [Byte1]: 66

 7910 12:21:40.501161  

 7911 12:21:40.501242  Set Vref, RX VrefLevel [Byte0]: 67

 7912 12:21:40.504862                           [Byte1]: 67

 7913 12:21:40.508897  

 7914 12:21:40.508974  Set Vref, RX VrefLevel [Byte0]: 68

 7915 12:21:40.512041                           [Byte1]: 68

 7916 12:21:40.516359  

 7917 12:21:40.516439  Set Vref, RX VrefLevel [Byte0]: 69

 7918 12:21:40.519989                           [Byte1]: 69

 7919 12:21:40.523940  

 7920 12:21:40.524016  Set Vref, RX VrefLevel [Byte0]: 70

 7921 12:21:40.527401                           [Byte1]: 70

 7922 12:21:40.531732  

 7923 12:21:40.531812  Set Vref, RX VrefLevel [Byte0]: 71

 7924 12:21:40.534765                           [Byte1]: 71

 7925 12:21:40.539214  

 7926 12:21:40.539331  Set Vref, RX VrefLevel [Byte0]: 72

 7927 12:21:40.542442                           [Byte1]: 72

 7928 12:21:40.546649  

 7929 12:21:40.546734  Set Vref, RX VrefLevel [Byte0]: 73

 7930 12:21:40.550167                           [Byte1]: 73

 7931 12:21:40.554662  

 7932 12:21:40.554746  Set Vref, RX VrefLevel [Byte0]: 74

 7933 12:21:40.557876                           [Byte1]: 74

 7934 12:21:40.562265  

 7935 12:21:40.562373  Set Vref, RX VrefLevel [Byte0]: 75

 7936 12:21:40.565201                           [Byte1]: 75

 7937 12:21:40.569586  

 7938 12:21:40.569667  Set Vref, RX VrefLevel [Byte0]: 76

 7939 12:21:40.573259                           [Byte1]: 76

 7940 12:21:40.577595  

 7941 12:21:40.577698  Set Vref, RX VrefLevel [Byte0]: 77

 7942 12:21:40.580691                           [Byte1]: 77

 7943 12:21:40.584993  

 7944 12:21:40.585080  Set Vref, RX VrefLevel [Byte0]: 78

 7945 12:21:40.588516                           [Byte1]: 78

 7946 12:21:40.592911  

 7947 12:21:40.593004  Set Vref, RX VrefLevel [Byte0]: 79

 7948 12:21:40.595758                           [Byte1]: 79

 7949 12:21:40.600133  

 7950 12:21:40.600225  Set Vref, RX VrefLevel [Byte0]: 80

 7951 12:21:40.603825                           [Byte1]: 80

 7952 12:21:40.608102  

 7953 12:21:40.608195  Final RX Vref Byte 0 = 64 to rank0

 7954 12:21:40.611090  Final RX Vref Byte 1 = 60 to rank0

 7955 12:21:40.614529  Final RX Vref Byte 0 = 64 to rank1

 7956 12:21:40.618175  Final RX Vref Byte 1 = 60 to rank1==

 7957 12:21:40.621192  Dram Type= 6, Freq= 0, CH_0, rank 0

 7958 12:21:40.627905  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7959 12:21:40.627997  ==

 7960 12:21:40.628082  DQS Delay:

 7961 12:21:40.628164  DQS0 = 0, DQS1 = 0

 7962 12:21:40.630906  DQM Delay:

 7963 12:21:40.630988  DQM0 = 126, DQM1 = 119

 7964 12:21:40.634249  DQ Delay:

 7965 12:21:40.637537  DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122

 7966 12:21:40.641301  DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138

 7967 12:21:40.644445  DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114

 7968 12:21:40.647468  DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128

 7969 12:21:40.647557  

 7970 12:21:40.647642  

 7971 12:21:40.647723  

 7972 12:21:40.651134  [DramC_TX_OE_Calibration] TA2

 7973 12:21:40.654013  Original DQ_B0 (3 6) =30, OEN = 27

 7974 12:21:40.657453  Original DQ_B1 (3 6) =30, OEN = 27

 7975 12:21:40.660947  24, 0x0, End_B0=24 End_B1=24

 7976 12:21:40.661025  25, 0x0, End_B0=25 End_B1=25

 7977 12:21:40.664152  26, 0x0, End_B0=26 End_B1=26

 7978 12:21:40.667345  27, 0x0, End_B0=27 End_B1=27

 7979 12:21:40.670602  28, 0x0, End_B0=28 End_B1=28

 7980 12:21:40.674273  29, 0x0, End_B0=29 End_B1=29

 7981 12:21:40.674361  30, 0x0, End_B0=30 End_B1=30

 7982 12:21:40.677160  31, 0x4101, End_B0=30 End_B1=30

 7983 12:21:40.680701  Byte0 end_step=30  best_step=27

 7984 12:21:40.684103  Byte1 end_step=30  best_step=27

 7985 12:21:40.687103  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7986 12:21:40.690522  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7987 12:21:40.690602  

 7988 12:21:40.690690  

 7989 12:21:40.697171  [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps

 7990 12:21:40.700331  CH0 RK0: MR19=303, MR18=1414

 7991 12:21:40.707022  CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15

 7992 12:21:40.707142  

 7993 12:21:40.710143  ----->DramcWriteLeveling(PI) begin...

 7994 12:21:40.710262  ==

 7995 12:21:40.713853  Dram Type= 6, Freq= 0, CH_0, rank 1

 7996 12:21:40.716804  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7997 12:21:40.716909  ==

 7998 12:21:40.720370  Write leveling (Byte 0): 34 => 34

 7999 12:21:40.723403  Write leveling (Byte 1): 27 => 27

 8000 12:21:40.727178  DramcWriteLeveling(PI) end<-----

 8001 12:21:40.727254  

 8002 12:21:40.727355  ==

 8003 12:21:40.730227  Dram Type= 6, Freq= 0, CH_0, rank 1

 8004 12:21:40.733287  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8005 12:21:40.733365  ==

 8006 12:21:40.736952  [Gating] SW mode calibration

 8007 12:21:40.743412  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8008 12:21:40.750290  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8009 12:21:40.753394   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8010 12:21:40.760278   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8011 12:21:40.763242   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8012 12:21:40.766563   1  4 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)

 8013 12:21:40.773102   1  4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 8014 12:21:40.776756   1  4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 8015 12:21:40.779676   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8016 12:21:40.786433   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8017 12:21:40.789617   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8018 12:21:40.793116   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8019 12:21:40.799595   1  5  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 8020 12:21:40.802976   1  5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)

 8021 12:21:40.806206   1  5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)

 8022 12:21:40.812800   1  5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)

 8023 12:21:40.816035   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8024 12:21:40.819627   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8025 12:21:40.826261   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8026 12:21:40.829436   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8027 12:21:40.832999   1  6  8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 8028 12:21:40.839202   1  6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)

 8029 12:21:40.842934   1  6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)

 8030 12:21:40.846097   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8031 12:21:40.852510   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8032 12:21:40.855867   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8033 12:21:40.858847   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8034 12:21:40.865438   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8035 12:21:40.868962   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8036 12:21:40.872387   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8037 12:21:40.878925   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8038 12:21:40.882592   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8039 12:21:40.885646   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8040 12:21:40.888765   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8041 12:21:40.895531   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8042 12:21:40.898913   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8043 12:21:40.902183   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8044 12:21:40.908662   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8045 12:21:40.912146   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8046 12:21:40.915206   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8047 12:21:40.921886   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8048 12:21:40.925311   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8049 12:21:40.928789   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8050 12:21:40.935224   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8051 12:21:40.938281   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8052 12:21:40.941893   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8053 12:21:40.948664   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8054 12:21:40.951672  Total UI for P1: 0, mck2ui 16

 8055 12:21:40.954781  best dqsien dly found for B0: ( 1,  9, 10)

 8056 12:21:40.958544   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8057 12:21:40.961565   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8058 12:21:40.965070  Total UI for P1: 0, mck2ui 16

 8059 12:21:40.968313  best dqsien dly found for B1: ( 1,  9, 18)

 8060 12:21:40.971335  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8061 12:21:40.978018  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 8062 12:21:40.978100  

 8063 12:21:40.981110  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8064 12:21:40.984502  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 8065 12:21:40.988104  [Gating] SW calibration Done

 8066 12:21:40.988181  ==

 8067 12:21:40.991173  Dram Type= 6, Freq= 0, CH_0, rank 1

 8068 12:21:40.994278  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8069 12:21:40.994383  ==

 8070 12:21:40.997854  RX Vref Scan: 0

 8071 12:21:40.997942  

 8072 12:21:40.998006  RX Vref 0 -> 0, step: 1

 8073 12:21:40.998066  

 8074 12:21:41.000921  RX Delay 0 -> 252, step: 8

 8075 12:21:41.004477  iDelay=200, Bit 0, Center 127 (72 ~ 183) 112

 8076 12:21:41.007914  iDelay=200, Bit 1, Center 131 (72 ~ 191) 120

 8077 12:21:41.014710  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8078 12:21:41.017912  iDelay=200, Bit 3, Center 123 (64 ~ 183) 120

 8079 12:21:41.020830  iDelay=200, Bit 4, Center 127 (72 ~ 183) 112

 8080 12:21:41.024163  iDelay=200, Bit 5, Center 115 (56 ~ 175) 120

 8081 12:21:41.027880  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8082 12:21:41.034193  iDelay=200, Bit 7, Center 139 (80 ~ 199) 120

 8083 12:21:41.037436  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 8084 12:21:41.040734  iDelay=200, Bit 9, Center 107 (48 ~ 167) 120

 8085 12:21:41.044296  iDelay=200, Bit 10, Center 123 (64 ~ 183) 120

 8086 12:21:41.050493  iDelay=200, Bit 11, Center 115 (56 ~ 175) 120

 8087 12:21:41.054261  iDelay=200, Bit 12, Center 127 (64 ~ 191) 128

 8088 12:21:41.057397  iDelay=200, Bit 13, Center 131 (72 ~ 191) 120

 8089 12:21:41.060580  iDelay=200, Bit 14, Center 131 (72 ~ 191) 120

 8090 12:21:41.063764  iDelay=200, Bit 15, Center 127 (64 ~ 191) 128

 8091 12:21:41.067410  ==

 8092 12:21:41.070480  Dram Type= 6, Freq= 0, CH_0, rank 1

 8093 12:21:41.073898  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8094 12:21:41.073984  ==

 8095 12:21:41.074071  DQS Delay:

 8096 12:21:41.077227  DQS0 = 0, DQS1 = 0

 8097 12:21:41.077310  DQM Delay:

 8098 12:21:41.080670  DQM0 = 128, DQM1 = 122

 8099 12:21:41.080754  DQ Delay:

 8100 12:21:41.084183  DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123

 8101 12:21:41.087008  DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139

 8102 12:21:41.090544  DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115

 8103 12:21:41.093507  DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127

 8104 12:21:41.093591  

 8105 12:21:41.093657  

 8106 12:21:41.096753  ==

 8107 12:21:41.096837  Dram Type= 6, Freq= 0, CH_0, rank 1

 8108 12:21:41.103511  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8109 12:21:41.103596  ==

 8110 12:21:41.103663  

 8111 12:21:41.103723  

 8112 12:21:41.107173  	TX Vref Scan disable

 8113 12:21:41.107256   == TX Byte 0 ==

 8114 12:21:41.110327  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 8115 12:21:41.116843  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 8116 12:21:41.116933   == TX Byte 1 ==

 8117 12:21:41.120184  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8118 12:21:41.126313  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8119 12:21:41.126446  ==

 8120 12:21:41.129963  Dram Type= 6, Freq= 0, CH_0, rank 1

 8121 12:21:41.133444  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8122 12:21:41.133532  ==

 8123 12:21:41.147850  

 8124 12:21:41.151249  TX Vref early break, caculate TX vref

 8125 12:21:41.154947  TX Vref=16, minBit 9, minWin=20, winSum=357

 8126 12:21:41.158069  TX Vref=18, minBit 11, minWin=21, winSum=366

 8127 12:21:41.161936  TX Vref=20, minBit 8, minWin=22, winSum=375

 8128 12:21:41.164983  TX Vref=22, minBit 8, minWin=22, winSum=383

 8129 12:21:41.168144  TX Vref=24, minBit 8, minWin=23, winSum=395

 8130 12:21:41.174996  TX Vref=26, minBit 8, minWin=23, winSum=400

 8131 12:21:41.178135  TX Vref=28, minBit 8, minWin=23, winSum=401

 8132 12:21:41.181778  TX Vref=30, minBit 8, minWin=23, winSum=400

 8133 12:21:41.184704  TX Vref=32, minBit 8, minWin=22, winSum=387

 8134 12:21:41.188505  TX Vref=34, minBit 8, minWin=22, winSum=383

 8135 12:21:41.191694  TX Vref=36, minBit 8, minWin=22, winSum=375

 8136 12:21:41.198137  [TxChooseVref] Worse bit 8, Min win 23, Win sum 401, Final Vref 28

 8137 12:21:41.198254  

 8138 12:21:41.201347  Final TX Range 0 Vref 28

 8139 12:21:41.201464  

 8140 12:21:41.201564  ==

 8141 12:21:41.204872  Dram Type= 6, Freq= 0, CH_0, rank 1

 8142 12:21:41.208026  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8143 12:21:41.208106  ==

 8144 12:21:41.208177  

 8145 12:21:41.211115  

 8146 12:21:41.211229  	TX Vref Scan disable

 8147 12:21:41.217942  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps

 8148 12:21:41.218057   == TX Byte 0 ==

 8149 12:21:41.220986  u2DelayCellOfst[0]=11 cells (3 PI)

 8150 12:21:41.224388  u2DelayCellOfst[1]=18 cells (5 PI)

 8151 12:21:41.227700  u2DelayCellOfst[2]=11 cells (3 PI)

 8152 12:21:41.231369  u2DelayCellOfst[3]=15 cells (4 PI)

 8153 12:21:41.234427  u2DelayCellOfst[4]=7 cells (2 PI)

 8154 12:21:41.237468  u2DelayCellOfst[5]=0 cells (0 PI)

 8155 12:21:41.240980  u2DelayCellOfst[6]=18 cells (5 PI)

 8156 12:21:41.244408  u2DelayCellOfst[7]=18 cells (5 PI)

 8157 12:21:41.247579  Update DQ  dly =988 (3 ,6, 28)  DQ  OEN =(3 ,3)

 8158 12:21:41.250577  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 8159 12:21:41.254099   == TX Byte 1 ==

 8160 12:21:41.257487  u2DelayCellOfst[8]=3 cells (1 PI)

 8161 12:21:41.261035  u2DelayCellOfst[9]=0 cells (0 PI)

 8162 12:21:41.264000  u2DelayCellOfst[10]=11 cells (3 PI)

 8163 12:21:41.267624  u2DelayCellOfst[11]=7 cells (2 PI)

 8164 12:21:41.267701  u2DelayCellOfst[12]=15 cells (4 PI)

 8165 12:21:41.270548  u2DelayCellOfst[13]=11 cells (3 PI)

 8166 12:21:41.274303  u2DelayCellOfst[14]=18 cells (5 PI)

 8167 12:21:41.277501  u2DelayCellOfst[15]=15 cells (4 PI)

 8168 12:21:41.284237  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8169 12:21:41.287431  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8170 12:21:41.287510  DramC Write-DBI on

 8171 12:21:41.290538  ==

 8172 12:21:41.293509  Dram Type= 6, Freq= 0, CH_0, rank 1

 8173 12:21:41.297109  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8174 12:21:41.297194  ==

 8175 12:21:41.297280  

 8176 12:21:41.297370  

 8177 12:21:41.300732  	TX Vref Scan disable

 8178 12:21:41.300841   == TX Byte 0 ==

 8179 12:21:41.307134  Update DQM dly =734 (2 ,6, 30)  DQM OEN =(3 ,3)

 8180 12:21:41.307244   == TX Byte 1 ==

 8181 12:21:41.310410  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8182 12:21:41.313650  DramC Write-DBI off

 8183 12:21:41.313754  

 8184 12:21:41.313855  [DATLAT]

 8185 12:21:41.316918  Freq=1600, CH0 RK1

 8186 12:21:41.317005  

 8187 12:21:41.317072  DATLAT Default: 0xf

 8188 12:21:41.320449  0, 0xFFFF, sum = 0

 8189 12:21:41.320530  1, 0xFFFF, sum = 0

 8190 12:21:41.323494  2, 0xFFFF, sum = 0

 8191 12:21:41.323615  3, 0xFFFF, sum = 0

 8192 12:21:41.327212  4, 0xFFFF, sum = 0

 8193 12:21:41.327317  5, 0xFFFF, sum = 0

 8194 12:21:41.330296  6, 0xFFFF, sum = 0

 8195 12:21:41.333554  7, 0xFFFF, sum = 0

 8196 12:21:41.333666  8, 0xFFFF, sum = 0

 8197 12:21:41.336885  9, 0xFFFF, sum = 0

 8198 12:21:41.336992  10, 0xFFFF, sum = 0

 8199 12:21:41.340453  11, 0xFFFF, sum = 0

 8200 12:21:41.340532  12, 0xFFFF, sum = 0

 8201 12:21:41.343616  13, 0xCFFF, sum = 0

 8202 12:21:41.343703  14, 0x0, sum = 1

 8203 12:21:41.346543  15, 0x0, sum = 2

 8204 12:21:41.346618  16, 0x0, sum = 3

 8205 12:21:41.350181  17, 0x0, sum = 4

 8206 12:21:41.350258  best_step = 15

 8207 12:21:41.350332  

 8208 12:21:41.350400  ==

 8209 12:21:41.353570  Dram Type= 6, Freq= 0, CH_0, rank 1

 8210 12:21:41.356967  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8211 12:21:41.357050  ==

 8212 12:21:41.359830  RX Vref Scan: 0

 8213 12:21:41.359915  

 8214 12:21:41.363315  RX Vref 0 -> 0, step: 1

 8215 12:21:41.363408  

 8216 12:21:41.363475  RX Delay 3 -> 252, step: 4

 8217 12:21:41.370447  iDelay=191, Bit 0, Center 124 (71 ~ 178) 108

 8218 12:21:41.373575  iDelay=191, Bit 1, Center 126 (71 ~ 182) 112

 8219 12:21:41.377368  iDelay=191, Bit 2, Center 122 (71 ~ 174) 104

 8220 12:21:41.380485  iDelay=191, Bit 3, Center 122 (67 ~ 178) 112

 8221 12:21:41.383590  iDelay=191, Bit 4, Center 124 (71 ~ 178) 108

 8222 12:21:41.390426  iDelay=191, Bit 5, Center 112 (59 ~ 166) 108

 8223 12:21:41.394024  iDelay=191, Bit 6, Center 134 (79 ~ 190) 112

 8224 12:21:41.397029  iDelay=191, Bit 7, Center 134 (79 ~ 190) 112

 8225 12:21:41.400087  iDelay=191, Bit 8, Center 110 (55 ~ 166) 112

 8226 12:21:41.403621  iDelay=191, Bit 9, Center 104 (47 ~ 162) 116

 8227 12:21:41.410129  iDelay=191, Bit 10, Center 120 (63 ~ 178) 116

 8228 12:21:41.413906  iDelay=191, Bit 11, Center 112 (55 ~ 170) 116

 8229 12:21:41.416794  iDelay=191, Bit 12, Center 124 (67 ~ 182) 116

 8230 12:21:41.420320  iDelay=191, Bit 13, Center 122 (67 ~ 178) 112

 8231 12:21:41.426746  iDelay=191, Bit 14, Center 128 (71 ~ 186) 116

 8232 12:21:41.429853  iDelay=191, Bit 15, Center 124 (67 ~ 182) 116

 8233 12:21:41.429968  ==

 8234 12:21:41.433604  Dram Type= 6, Freq= 0, CH_0, rank 1

 8235 12:21:41.436607  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8236 12:21:41.436717  ==

 8237 12:21:41.440211  DQS Delay:

 8238 12:21:41.440324  DQS0 = 0, DQS1 = 0

 8239 12:21:41.440418  DQM Delay:

 8240 12:21:41.443471  DQM0 = 124, DQM1 = 118

 8241 12:21:41.443555  DQ Delay:

 8242 12:21:41.446777  DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122

 8243 12:21:41.450173  DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134

 8244 12:21:41.453326  DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112

 8245 12:21:41.460009  DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124

 8246 12:21:41.460134  

 8247 12:21:41.460230  

 8248 12:21:41.460330  

 8249 12:21:41.463456  [DramC_TX_OE_Calibration] TA2

 8250 12:21:41.466614  Original DQ_B0 (3 6) =30, OEN = 27

 8251 12:21:41.466693  Original DQ_B1 (3 6) =30, OEN = 27

 8252 12:21:41.470160  24, 0x0, End_B0=24 End_B1=24

 8253 12:21:41.472947  25, 0x0, End_B0=25 End_B1=25

 8254 12:21:41.476313  26, 0x0, End_B0=26 End_B1=26

 8255 12:21:41.479952  27, 0x0, End_B0=27 End_B1=27

 8256 12:21:41.480059  28, 0x0, End_B0=28 End_B1=28

 8257 12:21:41.483144  29, 0x0, End_B0=29 End_B1=29

 8258 12:21:41.486244  30, 0x0, End_B0=30 End_B1=30

 8259 12:21:41.489402  31, 0x4141, End_B0=30 End_B1=30

 8260 12:21:41.493212  Byte0 end_step=30  best_step=27

 8261 12:21:41.496251  Byte1 end_step=30  best_step=27

 8262 12:21:41.496356  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8263 12:21:41.499338  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8264 12:21:41.499462  

 8265 12:21:41.499529  

 8266 12:21:41.509754  [DQSOSCAuto] RK1, (LSB)MR18= 0x2410, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps

 8267 12:21:41.512695  CH0 RK1: MR19=303, MR18=2410

 8268 12:21:41.516292  CH0_RK1: MR19=0x303, MR18=0x2410, DQSOSC=391, MR23=63, INC=24, DEC=16

 8269 12:21:41.519356  [RxdqsGatingPostProcess] freq 1600

 8270 12:21:41.525893  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8271 12:21:41.529400  best DQS0 dly(2T, 0.5T) = (1, 1)

 8272 12:21:41.532417  best DQS1 dly(2T, 0.5T) = (1, 1)

 8273 12:21:41.535916  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8274 12:21:41.539011  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8275 12:21:41.542750  best DQS0 dly(2T, 0.5T) = (1, 1)

 8276 12:21:41.542828  best DQS1 dly(2T, 0.5T) = (1, 1)

 8277 12:21:41.545804  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8278 12:21:41.548763  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8279 12:21:41.552244  Pre-setting of DQS Precalculation

 8280 12:21:41.558707  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8281 12:21:41.558822  ==

 8282 12:21:41.562398  Dram Type= 6, Freq= 0, CH_1, rank 0

 8283 12:21:41.565441  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8284 12:21:41.565542  ==

 8285 12:21:41.571875  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8286 12:21:41.575585  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8287 12:21:41.579046  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8288 12:21:41.585607  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8289 12:21:41.595100  [CA 0] Center 41 (12~70) winsize 59

 8290 12:21:41.598035  [CA 1] Center 42 (12~72) winsize 61

 8291 12:21:41.601764  [CA 2] Center 37 (8~66) winsize 59

 8292 12:21:41.604827  [CA 3] Center 36 (7~66) winsize 60

 8293 12:21:41.607953  [CA 4] Center 37 (8~67) winsize 60

 8294 12:21:41.611704  [CA 5] Center 36 (7~66) winsize 60

 8295 12:21:41.611791  

 8296 12:21:41.614795  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8297 12:21:41.614883  

 8298 12:21:41.617880  [CATrainingPosCal] consider 1 rank data

 8299 12:21:41.621613  u2DelayCellTimex100 = 258/100 ps

 8300 12:21:41.625153  CA0 delay=41 (12~70),Diff = 5 PI (18 cell)

 8301 12:21:41.631373  CA1 delay=42 (12~72),Diff = 6 PI (22 cell)

 8302 12:21:41.634775  CA2 delay=37 (8~66),Diff = 1 PI (3 cell)

 8303 12:21:41.638435  CA3 delay=36 (7~66),Diff = 0 PI (0 cell)

 8304 12:21:41.641367  CA4 delay=37 (8~67),Diff = 1 PI (3 cell)

 8305 12:21:41.644535  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8306 12:21:41.644618  

 8307 12:21:41.648222  CA PerBit enable=1, Macro0, CA PI delay=36

 8308 12:21:41.648312  

 8309 12:21:41.651302  [CBTSetCACLKResult] CA Dly = 36

 8310 12:21:41.654368  CS Dly: 9 (0~40)

 8311 12:21:41.658002  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8312 12:21:41.660947  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8313 12:21:41.661050  ==

 8314 12:21:41.664405  Dram Type= 6, Freq= 0, CH_1, rank 1

 8315 12:21:41.667760  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8316 12:21:41.671124  ==

 8317 12:21:41.674510  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8318 12:21:41.677405  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8319 12:21:41.684219  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8320 12:21:41.687832  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8321 12:21:41.697890  [CA 0] Center 42 (12~72) winsize 61

 8322 12:21:41.701532  [CA 1] Center 42 (13~72) winsize 60

 8323 12:21:41.704733  [CA 2] Center 37 (8~67) winsize 60

 8324 12:21:41.707788  [CA 3] Center 36 (7~66) winsize 60

 8325 12:21:41.711401  [CA 4] Center 37 (7~67) winsize 61

 8326 12:21:41.714573  [CA 5] Center 36 (6~66) winsize 61

 8327 12:21:41.714655  

 8328 12:21:41.717780  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8329 12:21:41.717858  

 8330 12:21:41.721356  [CATrainingPosCal] consider 2 rank data

 8331 12:21:41.724544  u2DelayCellTimex100 = 258/100 ps

 8332 12:21:41.727659  CA0 delay=41 (12~70),Diff = 5 PI (18 cell)

 8333 12:21:41.734486  CA1 delay=42 (13~72),Diff = 6 PI (22 cell)

 8334 12:21:41.737747  CA2 delay=37 (8~66),Diff = 1 PI (3 cell)

 8335 12:21:41.741104  CA3 delay=36 (7~66),Diff = 0 PI (0 cell)

 8336 12:21:41.744402  CA4 delay=37 (8~67),Diff = 1 PI (3 cell)

 8337 12:21:41.747679  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8338 12:21:41.747766  

 8339 12:21:41.751234  CA PerBit enable=1, Macro0, CA PI delay=36

 8340 12:21:41.751358  

 8341 12:21:41.754466  [CBTSetCACLKResult] CA Dly = 36

 8342 12:21:41.757472  CS Dly: 10 (0~43)

 8343 12:21:41.761131  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8344 12:21:41.764230  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8345 12:21:41.764313  

 8346 12:21:41.767286  ----->DramcWriteLeveling(PI) begin...

 8347 12:21:41.767407  ==

 8348 12:21:41.770780  Dram Type= 6, Freq= 0, CH_1, rank 0

 8349 12:21:41.777759  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8350 12:21:41.777844  ==

 8351 12:21:41.780932  Write leveling (Byte 0): 25 => 25

 8352 12:21:41.781038  Write leveling (Byte 1): 28 => 28

 8353 12:21:41.783920  DramcWriteLeveling(PI) end<-----

 8354 12:21:41.784029  

 8355 12:21:41.784123  ==

 8356 12:21:41.787335  Dram Type= 6, Freq= 0, CH_1, rank 0

 8357 12:21:41.794129  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8358 12:21:41.794213  ==

 8359 12:21:41.797122  [Gating] SW mode calibration

 8360 12:21:41.804310  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8361 12:21:41.807348  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8362 12:21:41.814091   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8363 12:21:41.817079   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8364 12:21:41.820876   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8365 12:21:41.827025   1  4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8366 12:21:41.830738   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8367 12:21:41.833826   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8368 12:21:41.840618   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8369 12:21:41.844122   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8370 12:21:41.847204   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8371 12:21:41.850840   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8372 12:21:41.857116   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8373 12:21:41.860366   1  5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8374 12:21:41.863916   1  5 16 | B1->B0 | 2626 2424 | 0 1 | (0 0) (1 0)

 8375 12:21:41.870641   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8376 12:21:41.874345   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8377 12:21:41.877229   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8378 12:21:41.883777   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8379 12:21:41.887207   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8380 12:21:41.890483   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8381 12:21:41.897014   1  6 12 | B1->B0 | 2e2e 2f2f | 1 1 | (0 0) (0 0)

 8382 12:21:41.900336   1  6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 8383 12:21:41.903846   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8384 12:21:41.910356   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8385 12:21:41.913430   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8386 12:21:41.917230   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8387 12:21:41.923575   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8388 12:21:41.926615   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8389 12:21:41.930345   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8390 12:21:41.936628   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8391 12:21:41.940310   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8392 12:21:41.943362   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8393 12:21:41.950033   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8394 12:21:41.953140   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8395 12:21:41.956764   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8396 12:21:41.963166   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8397 12:21:41.966618   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8398 12:21:41.970069   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8399 12:21:41.976588   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8400 12:21:41.979768   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8401 12:21:41.983264   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8402 12:21:41.990019   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8403 12:21:41.993023   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8404 12:21:41.996387   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8405 12:21:42.003142   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8406 12:21:42.006556   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8407 12:21:42.009544   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8408 12:21:42.013039  Total UI for P1: 0, mck2ui 16

 8409 12:21:42.016480  best dqsien dly found for B0: ( 1,  9, 14)

 8410 12:21:42.022758   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8411 12:21:42.022852  Total UI for P1: 0, mck2ui 16

 8412 12:21:42.026453  best dqsien dly found for B1: ( 1,  9, 16)

 8413 12:21:42.032525  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 8414 12:21:42.036240  best DQS1 dly(MCK, UI, PI) = (1, 9, 16)

 8415 12:21:42.036327  

 8416 12:21:42.039432  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8417 12:21:42.042572  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)

 8418 12:21:42.045674  [Gating] SW calibration Done

 8419 12:21:42.045766  ==

 8420 12:21:42.049244  Dram Type= 6, Freq= 0, CH_1, rank 0

 8421 12:21:42.052908  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8422 12:21:42.052997  ==

 8423 12:21:42.056082  RX Vref Scan: 0

 8424 12:21:42.056177  

 8425 12:21:42.056242  RX Vref 0 -> 0, step: 1

 8426 12:21:42.056306  

 8427 12:21:42.059107  RX Delay 0 -> 252, step: 8

 8428 12:21:42.062904  iDelay=208, Bit 0, Center 139 (80 ~ 199) 120

 8429 12:21:42.068997  iDelay=208, Bit 1, Center 131 (72 ~ 191) 120

 8430 12:21:42.072524  iDelay=208, Bit 2, Center 119 (64 ~ 175) 112

 8431 12:21:42.076114  iDelay=208, Bit 3, Center 131 (72 ~ 191) 120

 8432 12:21:42.078966  iDelay=208, Bit 4, Center 127 (72 ~ 183) 112

 8433 12:21:42.082435  iDelay=208, Bit 5, Center 147 (88 ~ 207) 120

 8434 12:21:42.089371  iDelay=208, Bit 6, Center 143 (88 ~ 199) 112

 8435 12:21:42.092367  iDelay=208, Bit 7, Center 131 (72 ~ 191) 120

 8436 12:21:42.095407  iDelay=208, Bit 8, Center 111 (56 ~ 167) 112

 8437 12:21:42.099084  iDelay=208, Bit 9, Center 115 (56 ~ 175) 120

 8438 12:21:42.102514  iDelay=208, Bit 10, Center 123 (72 ~ 175) 104

 8439 12:21:42.109025  iDelay=208, Bit 11, Center 119 (64 ~ 175) 112

 8440 12:21:42.112361  iDelay=208, Bit 12, Center 135 (80 ~ 191) 112

 8441 12:21:42.115610  iDelay=208, Bit 13, Center 135 (80 ~ 191) 112

 8442 12:21:42.118905  iDelay=208, Bit 14, Center 135 (80 ~ 191) 112

 8443 12:21:42.122386  iDelay=208, Bit 15, Center 135 (80 ~ 191) 112

 8444 12:21:42.125355  ==

 8445 12:21:42.128898  Dram Type= 6, Freq= 0, CH_1, rank 0

 8446 12:21:42.131813  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8447 12:21:42.131920  ==

 8448 12:21:42.132017  DQS Delay:

 8449 12:21:42.135457  DQS0 = 0, DQS1 = 0

 8450 12:21:42.135544  DQM Delay:

 8451 12:21:42.138640  DQM0 = 133, DQM1 = 126

 8452 12:21:42.138732  DQ Delay:

 8453 12:21:42.141852  DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =131

 8454 12:21:42.145565  DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131

 8455 12:21:42.148683  DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119

 8456 12:21:42.152210  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135

 8457 12:21:42.152288  

 8458 12:21:42.152360  

 8459 12:21:42.152421  ==

 8460 12:21:42.155085  Dram Type= 6, Freq= 0, CH_1, rank 0

 8461 12:21:42.161734  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8462 12:21:42.161829  ==

 8463 12:21:42.161896  

 8464 12:21:42.161962  

 8465 12:21:42.164927  	TX Vref Scan disable

 8466 12:21:42.165003   == TX Byte 0 ==

 8467 12:21:42.168577  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8468 12:21:42.175117  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8469 12:21:42.175198   == TX Byte 1 ==

 8470 12:21:42.178726  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8471 12:21:42.185220  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8472 12:21:42.185308  ==

 8473 12:21:42.188482  Dram Type= 6, Freq= 0, CH_1, rank 0

 8474 12:21:42.191356  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8475 12:21:42.191456  ==

 8476 12:21:42.204348  

 8477 12:21:42.207924  TX Vref early break, caculate TX vref

 8478 12:21:42.211337  TX Vref=16, minBit 11, minWin=20, winSum=358

 8479 12:21:42.214852  TX Vref=18, minBit 10, minWin=22, winSum=373

 8480 12:21:42.217654  TX Vref=20, minBit 11, minWin=22, winSum=379

 8481 12:21:42.221461  TX Vref=22, minBit 5, minWin=23, winSum=386

 8482 12:21:42.224261  TX Vref=24, minBit 5, minWin=24, winSum=400

 8483 12:21:42.231066  TX Vref=26, minBit 0, minWin=24, winSum=410

 8484 12:21:42.234339  TX Vref=28, minBit 5, minWin=24, winSum=419

 8485 12:21:42.237932  TX Vref=30, minBit 1, minWin=24, winSum=415

 8486 12:21:42.240963  TX Vref=32, minBit 0, minWin=24, winSum=406

 8487 12:21:42.244657  TX Vref=34, minBit 0, minWin=23, winSum=391

 8488 12:21:42.250792  [TxChooseVref] Worse bit 5, Min win 24, Win sum 419, Final Vref 28

 8489 12:21:42.250874  

 8490 12:21:42.254047  Final TX Range 0 Vref 28

 8491 12:21:42.254151  

 8492 12:21:42.254247  ==

 8493 12:21:42.257841  Dram Type= 6, Freq= 0, CH_1, rank 0

 8494 12:21:42.261062  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8495 12:21:42.261180  ==

 8496 12:21:42.261297  

 8497 12:21:42.261404  

 8498 12:21:42.264582  	TX Vref Scan disable

 8499 12:21:42.270947  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps

 8500 12:21:42.271062   == TX Byte 0 ==

 8501 12:21:42.274137  u2DelayCellOfst[0]=18 cells (5 PI)

 8502 12:21:42.277748  u2DelayCellOfst[1]=18 cells (5 PI)

 8503 12:21:42.280797  u2DelayCellOfst[2]=0 cells (0 PI)

 8504 12:21:42.283983  u2DelayCellOfst[3]=7 cells (2 PI)

 8505 12:21:42.287622  u2DelayCellOfst[4]=11 cells (3 PI)

 8506 12:21:42.291319  u2DelayCellOfst[5]=26 cells (7 PI)

 8507 12:21:42.293763  u2DelayCellOfst[6]=22 cells (6 PI)

 8508 12:21:42.297326  u2DelayCellOfst[7]=7 cells (2 PI)

 8509 12:21:42.300469  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8510 12:21:42.303933  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8511 12:21:42.307396   == TX Byte 1 ==

 8512 12:21:42.310497  u2DelayCellOfst[8]=0 cells (0 PI)

 8513 12:21:42.310611  u2DelayCellOfst[9]=7 cells (2 PI)

 8514 12:21:42.314100  u2DelayCellOfst[10]=15 cells (4 PI)

 8515 12:21:42.316963  u2DelayCellOfst[11]=11 cells (3 PI)

 8516 12:21:42.320478  u2DelayCellOfst[12]=18 cells (5 PI)

 8517 12:21:42.323534  u2DelayCellOfst[13]=22 cells (6 PI)

 8518 12:21:42.327279  u2DelayCellOfst[14]=22 cells (6 PI)

 8519 12:21:42.330314  u2DelayCellOfst[15]=22 cells (6 PI)

 8520 12:21:42.336932  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8521 12:21:42.340380  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8522 12:21:42.340506  DramC Write-DBI on

 8523 12:21:42.340585  ==

 8524 12:21:42.343298  Dram Type= 6, Freq= 0, CH_1, rank 0

 8525 12:21:42.350004  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8526 12:21:42.350122  ==

 8527 12:21:42.350220  

 8528 12:21:42.350309  

 8529 12:21:42.350396  	TX Vref Scan disable

 8530 12:21:42.354386   == TX Byte 0 ==

 8531 12:21:42.357610  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8532 12:21:42.360670   == TX Byte 1 ==

 8533 12:21:42.364629  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8534 12:21:42.367456  DramC Write-DBI off

 8535 12:21:42.367574  

 8536 12:21:42.367674  [DATLAT]

 8537 12:21:42.367764  Freq=1600, CH1 RK0

 8538 12:21:42.367852  

 8539 12:21:42.370625  DATLAT Default: 0xf

 8540 12:21:42.373726  0, 0xFFFF, sum = 0

 8541 12:21:42.373848  1, 0xFFFF, sum = 0

 8542 12:21:42.377414  2, 0xFFFF, sum = 0

 8543 12:21:42.377533  3, 0xFFFF, sum = 0

 8544 12:21:42.380414  4, 0xFFFF, sum = 0

 8545 12:21:42.380522  5, 0xFFFF, sum = 0

 8546 12:21:42.384196  6, 0xFFFF, sum = 0

 8547 12:21:42.384308  7, 0xFFFF, sum = 0

 8548 12:21:42.387198  8, 0xFFFF, sum = 0

 8549 12:21:42.387305  9, 0xFFFF, sum = 0

 8550 12:21:42.390304  10, 0xFFFF, sum = 0

 8551 12:21:42.390421  11, 0xFFFF, sum = 0

 8552 12:21:42.393955  12, 0xFFFF, sum = 0

 8553 12:21:42.394062  13, 0x8FFF, sum = 0

 8554 12:21:42.396996  14, 0x0, sum = 1

 8555 12:21:42.397073  15, 0x0, sum = 2

 8556 12:21:42.400126  16, 0x0, sum = 3

 8557 12:21:42.400231  17, 0x0, sum = 4

 8558 12:21:42.403785  best_step = 15

 8559 12:21:42.403866  

 8560 12:21:42.403931  ==

 8561 12:21:42.406820  Dram Type= 6, Freq= 0, CH_1, rank 0

 8562 12:21:42.410358  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8563 12:21:42.410442  ==

 8564 12:21:42.413856  RX Vref Scan: 1

 8565 12:21:42.413946  

 8566 12:21:42.414038  Set Vref Range= 24 -> 127

 8567 12:21:42.414127  

 8568 12:21:42.416873  RX Vref 24 -> 127, step: 1

 8569 12:21:42.416967  

 8570 12:21:42.420647  RX Delay 11 -> 252, step: 4

 8571 12:21:42.420753  

 8572 12:21:42.423755  Set Vref, RX VrefLevel [Byte0]: 24

 8573 12:21:42.426631                           [Byte1]: 24

 8574 12:21:42.426744  

 8575 12:21:42.430109  Set Vref, RX VrefLevel [Byte0]: 25

 8576 12:21:42.433599                           [Byte1]: 25

 8577 12:21:42.437376  

 8578 12:21:42.437455  Set Vref, RX VrefLevel [Byte0]: 26

 8579 12:21:42.440204                           [Byte1]: 26

 8580 12:21:42.444825  

 8581 12:21:42.444902  Set Vref, RX VrefLevel [Byte0]: 27

 8582 12:21:42.448294                           [Byte1]: 27

 8583 12:21:42.452261  

 8584 12:21:42.452374  Set Vref, RX VrefLevel [Byte0]: 28

 8585 12:21:42.455786                           [Byte1]: 28

 8586 12:21:42.459925  

 8587 12:21:42.460007  Set Vref, RX VrefLevel [Byte0]: 29

 8588 12:21:42.462980                           [Byte1]: 29

 8589 12:21:42.467394  

 8590 12:21:42.467506  Set Vref, RX VrefLevel [Byte0]: 30

 8591 12:21:42.470900                           [Byte1]: 30

 8592 12:21:42.475203  

 8593 12:21:42.475283  Set Vref, RX VrefLevel [Byte0]: 31

 8594 12:21:42.478293                           [Byte1]: 31

 8595 12:21:42.482475  

 8596 12:21:42.482551  Set Vref, RX VrefLevel [Byte0]: 32

 8597 12:21:42.486190                           [Byte1]: 32

 8598 12:21:42.490236  

 8599 12:21:42.490315  Set Vref, RX VrefLevel [Byte0]: 33

 8600 12:21:42.493352                           [Byte1]: 33

 8601 12:21:42.497647  

 8602 12:21:42.497744  Set Vref, RX VrefLevel [Byte0]: 34

 8603 12:21:42.501331                           [Byte1]: 34

 8604 12:21:42.505673  

 8605 12:21:42.505755  Set Vref, RX VrefLevel [Byte0]: 35

 8606 12:21:42.509154                           [Byte1]: 35

 8607 12:21:42.513273  

 8608 12:21:42.513359  Set Vref, RX VrefLevel [Byte0]: 36

 8609 12:21:42.516238                           [Byte1]: 36

 8610 12:21:42.521079  

 8611 12:21:42.521183  Set Vref, RX VrefLevel [Byte0]: 37

 8612 12:21:42.523950                           [Byte1]: 37

 8613 12:21:42.528488  

 8614 12:21:42.528593  Set Vref, RX VrefLevel [Byte0]: 38

 8615 12:21:42.531526                           [Byte1]: 38

 8616 12:21:42.536163  

 8617 12:21:42.536288  Set Vref, RX VrefLevel [Byte0]: 39

 8618 12:21:42.539005                           [Byte1]: 39

 8619 12:21:42.543429  

 8620 12:21:42.543542  Set Vref, RX VrefLevel [Byte0]: 40

 8621 12:21:42.547014                           [Byte1]: 40

 8622 12:21:42.550902  

 8623 12:21:42.551006  Set Vref, RX VrefLevel [Byte0]: 41

 8624 12:21:42.554521                           [Byte1]: 41

 8625 12:21:42.558682  

 8626 12:21:42.558766  Set Vref, RX VrefLevel [Byte0]: 42

 8627 12:21:42.562320                           [Byte1]: 42

 8628 12:21:42.566662  

 8629 12:21:42.566748  Set Vref, RX VrefLevel [Byte0]: 43

 8630 12:21:42.569801                           [Byte1]: 43

 8631 12:21:42.574038  

 8632 12:21:42.574124  Set Vref, RX VrefLevel [Byte0]: 44

 8633 12:21:42.577167                           [Byte1]: 44

 8634 12:21:42.581542  

 8635 12:21:42.581645  Set Vref, RX VrefLevel [Byte0]: 45

 8636 12:21:42.585194                           [Byte1]: 45

 8637 12:21:42.589611  

 8638 12:21:42.589694  Set Vref, RX VrefLevel [Byte0]: 46

 8639 12:21:42.592277                           [Byte1]: 46

 8640 12:21:42.597123  

 8641 12:21:42.597204  Set Vref, RX VrefLevel [Byte0]: 47

 8642 12:21:42.600296                           [Byte1]: 47

 8643 12:21:42.604486  

 8644 12:21:42.604561  Set Vref, RX VrefLevel [Byte0]: 48

 8645 12:21:42.608113                           [Byte1]: 48

 8646 12:21:42.612288  

 8647 12:21:42.612398  Set Vref, RX VrefLevel [Byte0]: 49

 8648 12:21:42.615297                           [Byte1]: 49

 8649 12:21:42.620017  

 8650 12:21:42.620100  Set Vref, RX VrefLevel [Byte0]: 50

 8651 12:21:42.623085                           [Byte1]: 50

 8652 12:21:42.627382  

 8653 12:21:42.627503  Set Vref, RX VrefLevel [Byte0]: 51

 8654 12:21:42.630355                           [Byte1]: 51

 8655 12:21:42.634821  

 8656 12:21:42.634923  Set Vref, RX VrefLevel [Byte0]: 52

 8657 12:21:42.638040                           [Byte1]: 52

 8658 12:21:42.642565  

 8659 12:21:42.642644  Set Vref, RX VrefLevel [Byte0]: 53

 8660 12:21:42.645590                           [Byte1]: 53

 8661 12:21:42.650353  

 8662 12:21:42.650460  Set Vref, RX VrefLevel [Byte0]: 54

 8663 12:21:42.653361                           [Byte1]: 54

 8664 12:21:42.657943  

 8665 12:21:42.658028  Set Vref, RX VrefLevel [Byte0]: 55

 8666 12:21:42.660904                           [Byte1]: 55

 8667 12:21:42.665578  

 8668 12:21:42.665659  Set Vref, RX VrefLevel [Byte0]: 56

 8669 12:21:42.668535                           [Byte1]: 56

 8670 12:21:42.672875  

 8671 12:21:42.672964  Set Vref, RX VrefLevel [Byte0]: 57

 8672 12:21:42.676526                           [Byte1]: 57

 8673 12:21:42.680750  

 8674 12:21:42.680830  Set Vref, RX VrefLevel [Byte0]: 58

 8675 12:21:42.683885                           [Byte1]: 58

 8676 12:21:42.688030  

 8677 12:21:42.688111  Set Vref, RX VrefLevel [Byte0]: 59

 8678 12:21:42.691814                           [Byte1]: 59

 8679 12:21:42.695994  

 8680 12:21:42.696076  Set Vref, RX VrefLevel [Byte0]: 60

 8681 12:21:42.699027                           [Byte1]: 60

 8682 12:21:42.703889  

 8683 12:21:42.703990  Set Vref, RX VrefLevel [Byte0]: 61

 8684 12:21:42.706894                           [Byte1]: 61

 8685 12:21:42.711259  

 8686 12:21:42.711365  Set Vref, RX VrefLevel [Byte0]: 62

 8687 12:21:42.714453                           [Byte1]: 62

 8688 12:21:42.718737  

 8689 12:21:42.718810  Set Vref, RX VrefLevel [Byte0]: 63

 8690 12:21:42.722127                           [Byte1]: 63

 8691 12:21:42.726078  

 8692 12:21:42.726168  Set Vref, RX VrefLevel [Byte0]: 64

 8693 12:21:42.729776                           [Byte1]: 64

 8694 12:21:42.734077  

 8695 12:21:42.734152  Set Vref, RX VrefLevel [Byte0]: 65

 8696 12:21:42.740067                           [Byte1]: 65

 8697 12:21:42.740173  

 8698 12:21:42.743422  Set Vref, RX VrefLevel [Byte0]: 66

 8699 12:21:42.746877                           [Byte1]: 66

 8700 12:21:42.746952  

 8701 12:21:42.750141  Set Vref, RX VrefLevel [Byte0]: 67

 8702 12:21:42.753791                           [Byte1]: 67

 8703 12:21:42.753870  

 8704 12:21:42.756897  Set Vref, RX VrefLevel [Byte0]: 68

 8705 12:21:42.760328                           [Byte1]: 68

 8706 12:21:42.764327  

 8707 12:21:42.764404  Set Vref, RX VrefLevel [Byte0]: 69

 8708 12:21:42.767833                           [Byte1]: 69

 8709 12:21:42.772078  

 8710 12:21:42.772155  Set Vref, RX VrefLevel [Byte0]: 70

 8711 12:21:42.775000                           [Byte1]: 70

 8712 12:21:42.779429  

 8713 12:21:42.779507  Set Vref, RX VrefLevel [Byte0]: 71

 8714 12:21:42.782814                           [Byte1]: 71

 8715 12:21:42.787176  

 8716 12:21:42.787284  Set Vref, RX VrefLevel [Byte0]: 72

 8717 12:21:42.790263                           [Byte1]: 72

 8718 12:21:42.794616  

 8719 12:21:42.794746  Final RX Vref Byte 0 = 55 to rank0

 8720 12:21:42.798314  Final RX Vref Byte 1 = 54 to rank0

 8721 12:21:42.801246  Final RX Vref Byte 0 = 55 to rank1

 8722 12:21:42.805012  Final RX Vref Byte 1 = 54 to rank1==

 8723 12:21:42.808042  Dram Type= 6, Freq= 0, CH_1, rank 0

 8724 12:21:42.814863  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8725 12:21:42.814992  ==

 8726 12:21:42.815093  DQS Delay:

 8727 12:21:42.815193  DQS0 = 0, DQS1 = 0

 8728 12:21:42.817993  DQM Delay:

 8729 12:21:42.818077  DQM0 = 131, DQM1 = 123

 8730 12:21:42.821800  DQ Delay:

 8731 12:21:42.824816  DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130

 8732 12:21:42.828359  DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128

 8733 12:21:42.831196  DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116

 8734 12:21:42.834906  DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132

 8735 12:21:42.835044  

 8736 12:21:42.835141  

 8737 12:21:42.835230  

 8738 12:21:42.837894  [DramC_TX_OE_Calibration] TA2

 8739 12:21:42.841526  Original DQ_B0 (3 6) =30, OEN = 27

 8740 12:21:42.844655  Original DQ_B1 (3 6) =30, OEN = 27

 8741 12:21:42.848225  24, 0x0, End_B0=24 End_B1=24

 8742 12:21:42.848362  25, 0x0, End_B0=25 End_B1=25

 8743 12:21:42.851252  26, 0x0, End_B0=26 End_B1=26

 8744 12:21:42.854884  27, 0x0, End_B0=27 End_B1=27

 8745 12:21:42.857898  28, 0x0, End_B0=28 End_B1=28

 8746 12:21:42.858017  29, 0x0, End_B0=29 End_B1=29

 8747 12:21:42.861466  30, 0x0, End_B0=30 End_B1=30

 8748 12:21:42.864777  31, 0x4545, End_B0=30 End_B1=30

 8749 12:21:42.867979  Byte0 end_step=30  best_step=27

 8750 12:21:42.871234  Byte1 end_step=30  best_step=27

 8751 12:21:42.874364  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8752 12:21:42.877568  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8753 12:21:42.877693  

 8754 12:21:42.877794  

 8755 12:21:42.884412  [DQSOSCAuto] RK0, (LSB)MR18= 0xb0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps

 8756 12:21:42.887872  CH1 RK0: MR19=303, MR18=B0F

 8757 12:21:42.894483  CH1_RK0: MR19=0x303, MR18=0xB0F, DQSOSC=402, MR23=63, INC=22, DEC=15

 8758 12:21:42.894574  

 8759 12:21:42.897690  ----->DramcWriteLeveling(PI) begin...

 8760 12:21:42.897810  ==

 8761 12:21:42.901014  Dram Type= 6, Freq= 0, CH_1, rank 1

 8762 12:21:42.904482  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8763 12:21:42.904593  ==

 8764 12:21:42.907514  Write leveling (Byte 0): 25 => 25

 8765 12:21:42.911183  Write leveling (Byte 1): 26 => 26

 8766 12:21:42.914209  DramcWriteLeveling(PI) end<-----

 8767 12:21:42.914320  

 8768 12:21:42.914416  ==

 8769 12:21:42.917435  Dram Type= 6, Freq= 0, CH_1, rank 1

 8770 12:21:42.920563  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8771 12:21:42.920670  ==

 8772 12:21:42.923933  [Gating] SW mode calibration

 8773 12:21:42.930697  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8774 12:21:42.937390  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8775 12:21:42.940742   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8776 12:21:42.944133   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8777 12:21:42.950773   1  4  8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)

 8778 12:21:42.953777   1  4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

 8779 12:21:42.957269   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8780 12:21:42.964144   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8781 12:21:42.967351   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8782 12:21:42.970337   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8783 12:21:42.977366   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8784 12:21:42.980281   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8785 12:21:42.983606   1  5  8 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)

 8786 12:21:42.990510   1  5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)

 8787 12:21:42.993781   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8788 12:21:42.997103   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8789 12:21:43.003957   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8790 12:21:43.006789   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8791 12:21:43.010350   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8792 12:21:43.016963   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8793 12:21:43.020054   1  6  8 | B1->B0 | 2525 3e3e | 0 0 | (0 0) (0 0)

 8794 12:21:43.023649   1  6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)

 8795 12:21:43.029906   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8796 12:21:43.033026   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8797 12:21:43.036668   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8798 12:21:43.043527   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8799 12:21:43.046466   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8800 12:21:43.049883   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8801 12:21:43.056223   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8802 12:21:43.059612   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8803 12:21:43.062813   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8804 12:21:43.069363   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8805 12:21:43.072977   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8806 12:21:43.076074   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8807 12:21:43.082558   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8808 12:21:43.086162   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8809 12:21:43.089249   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8810 12:21:43.096130   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8811 12:21:43.099625   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8812 12:21:43.102809   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8813 12:21:43.109138   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8814 12:21:43.112349   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8815 12:21:43.116339   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8816 12:21:43.122387   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8817 12:21:43.125828   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8818 12:21:43.128900   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8819 12:21:43.132038  Total UI for P1: 0, mck2ui 16

 8820 12:21:43.135790  best dqsien dly found for B0: ( 1,  9,  8)

 8821 12:21:43.142640   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8822 12:21:43.142753  Total UI for P1: 0, mck2ui 16

 8823 12:21:43.148773  best dqsien dly found for B1: ( 1,  9, 10)

 8824 12:21:43.152353  best DQS0 dly(MCK, UI, PI) = (1, 9, 8)

 8825 12:21:43.155493  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8826 12:21:43.155595  

 8827 12:21:43.159004  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)

 8828 12:21:43.161919  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8829 12:21:43.165157  [Gating] SW calibration Done

 8830 12:21:43.165243  ==

 8831 12:21:43.168513  Dram Type= 6, Freq= 0, CH_1, rank 1

 8832 12:21:43.172220  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8833 12:21:43.172308  ==

 8834 12:21:43.175341  RX Vref Scan: 0

 8835 12:21:43.175446  

 8836 12:21:43.175515  RX Vref 0 -> 0, step: 1

 8837 12:21:43.175577  

 8838 12:21:43.178448  RX Delay 0 -> 252, step: 8

 8839 12:21:43.181998  iDelay=200, Bit 0, Center 131 (72 ~ 191) 120

 8840 12:21:43.188579  iDelay=200, Bit 1, Center 127 (72 ~ 183) 112

 8841 12:21:43.191607  iDelay=200, Bit 2, Center 115 (56 ~ 175) 120

 8842 12:21:43.195336  iDelay=200, Bit 3, Center 127 (64 ~ 191) 128

 8843 12:21:43.198210  iDelay=200, Bit 4, Center 127 (64 ~ 191) 128

 8844 12:21:43.201827  iDelay=200, Bit 5, Center 139 (80 ~ 199) 120

 8845 12:21:43.208309  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8846 12:21:43.211673  iDelay=200, Bit 7, Center 127 (64 ~ 191) 128

 8847 12:21:43.215220  iDelay=200, Bit 8, Center 111 (48 ~ 175) 128

 8848 12:21:43.218146  iDelay=200, Bit 9, Center 115 (56 ~ 175) 120

 8849 12:21:43.221861  iDelay=200, Bit 10, Center 131 (72 ~ 191) 120

 8850 12:21:43.228125  iDelay=200, Bit 11, Center 123 (64 ~ 183) 120

 8851 12:21:43.231046  iDelay=200, Bit 12, Center 131 (72 ~ 191) 120

 8852 12:21:43.234502  iDelay=200, Bit 13, Center 139 (80 ~ 199) 120

 8853 12:21:43.238155  iDelay=200, Bit 14, Center 135 (72 ~ 199) 128

 8854 12:21:43.244325  iDelay=200, Bit 15, Center 139 (80 ~ 199) 120

 8855 12:21:43.244436  ==

 8856 12:21:43.247975  Dram Type= 6, Freq= 0, CH_1, rank 1

 8857 12:21:43.251056  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8858 12:21:43.251166  ==

 8859 12:21:43.251259  DQS Delay:

 8860 12:21:43.254781  DQS0 = 0, DQS1 = 0

 8861 12:21:43.254887  DQM Delay:

 8862 12:21:43.258259  DQM0 = 129, DQM1 = 128

 8863 12:21:43.258382  DQ Delay:

 8864 12:21:43.261363  DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127

 8865 12:21:43.264477  DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127

 8866 12:21:43.268079  DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123

 8867 12:21:43.271022  DQ12 =131, DQ13 =139, DQ14 =135, DQ15 =139

 8868 12:21:43.271135  

 8869 12:21:43.271230  

 8870 12:21:43.271320  ==

 8871 12:21:43.274529  Dram Type= 6, Freq= 0, CH_1, rank 1

 8872 12:21:43.281463  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8873 12:21:43.281555  ==

 8874 12:21:43.281621  

 8875 12:21:43.281681  

 8876 12:21:43.284546  	TX Vref Scan disable

 8877 12:21:43.284624   == TX Byte 0 ==

 8878 12:21:43.288175  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8879 12:21:43.294251  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8880 12:21:43.294358   == TX Byte 1 ==

 8881 12:21:43.298039  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8882 12:21:43.304461  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8883 12:21:43.304578  ==

 8884 12:21:43.307561  Dram Type= 6, Freq= 0, CH_1, rank 1

 8885 12:21:43.310791  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8886 12:21:43.310909  ==

 8887 12:21:43.323892  

 8888 12:21:43.327199  TX Vref early break, caculate TX vref

 8889 12:21:43.330257  TX Vref=16, minBit 0, minWin=23, winSum=383

 8890 12:21:43.333976  TX Vref=18, minBit 0, minWin=23, winSum=397

 8891 12:21:43.336948  TX Vref=20, minBit 0, minWin=23, winSum=406

 8892 12:21:43.340382  TX Vref=22, minBit 0, minWin=24, winSum=414

 8893 12:21:43.343348  TX Vref=24, minBit 0, minWin=25, winSum=422

 8894 12:21:43.350196  TX Vref=26, minBit 0, minWin=25, winSum=425

 8895 12:21:43.353286  TX Vref=28, minBit 0, minWin=25, winSum=431

 8896 12:21:43.357071  TX Vref=30, minBit 1, minWin=25, winSum=421

 8897 12:21:43.359950  TX Vref=32, minBit 1, minWin=24, winSum=417

 8898 12:21:43.363529  TX Vref=34, minBit 0, minWin=24, winSum=404

 8899 12:21:43.370256  [TxChooseVref] Worse bit 0, Min win 25, Win sum 431, Final Vref 28

 8900 12:21:43.370342  

 8901 12:21:43.373265  Final TX Range 0 Vref 28

 8902 12:21:43.373344  

 8903 12:21:43.373408  ==

 8904 12:21:43.376299  Dram Type= 6, Freq= 0, CH_1, rank 1

 8905 12:21:43.379890  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8906 12:21:43.379969  ==

 8907 12:21:43.380037  

 8908 12:21:43.380099  

 8909 12:21:43.382877  	TX Vref Scan disable

 8910 12:21:43.389795  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps

 8911 12:21:43.389919   == TX Byte 0 ==

 8912 12:21:43.392774  u2DelayCellOfst[0]=18 cells (5 PI)

 8913 12:21:43.396291  u2DelayCellOfst[1]=15 cells (4 PI)

 8914 12:21:43.399404  u2DelayCellOfst[2]=0 cells (0 PI)

 8915 12:21:43.403051  u2DelayCellOfst[3]=7 cells (2 PI)

 8916 12:21:43.405963  u2DelayCellOfst[4]=11 cells (3 PI)

 8917 12:21:43.409582  u2DelayCellOfst[5]=26 cells (7 PI)

 8918 12:21:43.412645  u2DelayCellOfst[6]=22 cells (6 PI)

 8919 12:21:43.416489  u2DelayCellOfst[7]=7 cells (2 PI)

 8920 12:21:43.419524  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8921 12:21:43.423173  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8922 12:21:43.426198   == TX Byte 1 ==

 8923 12:21:43.429561  u2DelayCellOfst[8]=0 cells (0 PI)

 8924 12:21:43.432525  u2DelayCellOfst[9]=7 cells (2 PI)

 8925 12:21:43.432610  u2DelayCellOfst[10]=15 cells (4 PI)

 8926 12:21:43.436020  u2DelayCellOfst[11]=7 cells (2 PI)

 8927 12:21:43.439356  u2DelayCellOfst[12]=15 cells (4 PI)

 8928 12:21:43.442721  u2DelayCellOfst[13]=18 cells (5 PI)

 8929 12:21:43.445997  u2DelayCellOfst[14]=22 cells (6 PI)

 8930 12:21:43.449473  u2DelayCellOfst[15]=22 cells (6 PI)

 8931 12:21:43.455867  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8932 12:21:43.459674  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8933 12:21:43.459769  DramC Write-DBI on

 8934 12:21:43.459837  ==

 8935 12:21:43.462638  Dram Type= 6, Freq= 0, CH_1, rank 1

 8936 12:21:43.469204  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8937 12:21:43.469284  ==

 8938 12:21:43.469349  

 8939 12:21:43.469408  

 8940 12:21:43.469477  	TX Vref Scan disable

 8941 12:21:43.473416   == TX Byte 0 ==

 8942 12:21:43.476382  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8943 12:21:43.480097   == TX Byte 1 ==

 8944 12:21:43.483082  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8945 12:21:43.486348  DramC Write-DBI off

 8946 12:21:43.486425  

 8947 12:21:43.486488  [DATLAT]

 8948 12:21:43.486548  Freq=1600, CH1 RK1

 8949 12:21:43.486608  

 8950 12:21:43.490032  DATLAT Default: 0xf

 8951 12:21:43.490115  0, 0xFFFF, sum = 0

 8952 12:21:43.492844  1, 0xFFFF, sum = 0

 8953 12:21:43.496454  2, 0xFFFF, sum = 0

 8954 12:21:43.496533  3, 0xFFFF, sum = 0

 8955 12:21:43.499762  4, 0xFFFF, sum = 0

 8956 12:21:43.499848  5, 0xFFFF, sum = 0

 8957 12:21:43.503170  6, 0xFFFF, sum = 0

 8958 12:21:43.503255  7, 0xFFFF, sum = 0

 8959 12:21:43.506293  8, 0xFFFF, sum = 0

 8960 12:21:43.506378  9, 0xFFFF, sum = 0

 8961 12:21:43.509799  10, 0xFFFF, sum = 0

 8962 12:21:43.509885  11, 0xFFFF, sum = 0

 8963 12:21:43.512804  12, 0xFFFF, sum = 0

 8964 12:21:43.512901  13, 0x8FFF, sum = 0

 8965 12:21:43.515995  14, 0x0, sum = 1

 8966 12:21:43.516077  15, 0x0, sum = 2

 8967 12:21:43.519760  16, 0x0, sum = 3

 8968 12:21:43.519850  17, 0x0, sum = 4

 8969 12:21:43.522770  best_step = 15

 8970 12:21:43.522853  

 8971 12:21:43.522923  ==

 8972 12:21:43.525865  Dram Type= 6, Freq= 0, CH_1, rank 1

 8973 12:21:43.529598  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8974 12:21:43.529684  ==

 8975 12:21:43.532564  RX Vref Scan: 0

 8976 12:21:43.532645  

 8977 12:21:43.532710  RX Vref 0 -> 0, step: 1

 8978 12:21:43.532770  

 8979 12:21:43.536052  RX Delay 3 -> 252, step: 4

 8980 12:21:43.542617  iDelay=195, Bit 0, Center 130 (75 ~ 186) 112

 8981 12:21:43.545999  iDelay=195, Bit 1, Center 126 (75 ~ 178) 104

 8982 12:21:43.549616  iDelay=195, Bit 2, Center 116 (63 ~ 170) 108

 8983 12:21:43.552881  iDelay=195, Bit 3, Center 124 (71 ~ 178) 108

 8984 12:21:43.555915  iDelay=195, Bit 4, Center 124 (67 ~ 182) 116

 8985 12:21:43.559417  iDelay=195, Bit 5, Center 138 (83 ~ 194) 112

 8986 12:21:43.566179  iDelay=195, Bit 6, Center 138 (83 ~ 194) 112

 8987 12:21:43.569652  iDelay=195, Bit 7, Center 122 (67 ~ 178) 112

 8988 12:21:43.572767  iDelay=195, Bit 8, Center 110 (51 ~ 170) 120

 8989 12:21:43.576364  iDelay=195, Bit 9, Center 112 (59 ~ 166) 108

 8990 12:21:43.579394  iDelay=195, Bit 10, Center 128 (75 ~ 182) 108

 8991 12:21:43.586075  iDelay=195, Bit 11, Center 118 (63 ~ 174) 112

 8992 12:21:43.589223  iDelay=195, Bit 12, Center 130 (75 ~ 186) 112

 8993 12:21:43.592300  iDelay=195, Bit 13, Center 134 (79 ~ 190) 112

 8994 12:21:43.595727  iDelay=195, Bit 14, Center 130 (75 ~ 186) 112

 8995 12:21:43.602350  iDelay=195, Bit 15, Center 136 (83 ~ 190) 108

 8996 12:21:43.602442  ==

 8997 12:21:43.605940  Dram Type= 6, Freq= 0, CH_1, rank 1

 8998 12:21:43.609275  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8999 12:21:43.609356  ==

 9000 12:21:43.609432  DQS Delay:

 9001 12:21:43.612622  DQS0 = 0, DQS1 = 0

 9002 12:21:43.612700  DQM Delay:

 9003 12:21:43.615999  DQM0 = 127, DQM1 = 124

 9004 12:21:43.616111  DQ Delay:

 9005 12:21:43.618947  DQ0 =130, DQ1 =126, DQ2 =116, DQ3 =124

 9006 12:21:43.622125  DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122

 9007 12:21:43.625742  DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =118

 9008 12:21:43.628823  DQ12 =130, DQ13 =134, DQ14 =130, DQ15 =136

 9009 12:21:43.628901  

 9010 12:21:43.628973  

 9011 12:21:43.629036  

 9012 12:21:43.632570  [DramC_TX_OE_Calibration] TA2

 9013 12:21:43.635744  Original DQ_B0 (3 6) =30, OEN = 27

 9014 12:21:43.638870  Original DQ_B1 (3 6) =30, OEN = 27

 9015 12:21:43.642343  24, 0x0, End_B0=24 End_B1=24

 9016 12:21:43.645401  25, 0x0, End_B0=25 End_B1=25

 9017 12:21:43.649090  26, 0x0, End_B0=26 End_B1=26

 9018 12:21:43.649203  27, 0x0, End_B0=27 End_B1=27

 9019 12:21:43.652084  28, 0x0, End_B0=28 End_B1=28

 9020 12:21:43.655192  29, 0x0, End_B0=29 End_B1=29

 9021 12:21:43.658907  30, 0x0, End_B0=30 End_B1=30

 9022 12:21:43.661869  31, 0x4141, End_B0=30 End_B1=30

 9023 12:21:43.661946  Byte0 end_step=30  best_step=27

 9024 12:21:43.665278  Byte1 end_step=30  best_step=27

 9025 12:21:43.668489  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9026 12:21:43.671779  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9027 12:21:43.671867  

 9028 12:21:43.671936  

 9029 12:21:43.678356  [DQSOSCAuto] RK1, (LSB)MR18= 0x121e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps

 9030 12:21:43.681640  CH1 RK1: MR19=303, MR18=121E

 9031 12:21:43.688646  CH1_RK1: MR19=0x303, MR18=0x121E, DQSOSC=394, MR23=63, INC=23, DEC=15

 9032 12:21:43.691759  [RxdqsGatingPostProcess] freq 1600

 9033 12:21:43.698644  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9034 12:21:43.701558  best DQS0 dly(2T, 0.5T) = (1, 1)

 9035 12:21:43.705005  best DQS1 dly(2T, 0.5T) = (1, 1)

 9036 12:21:43.705091  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9037 12:21:43.708245  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9038 12:21:43.711368  best DQS0 dly(2T, 0.5T) = (1, 1)

 9039 12:21:43.714913  best DQS1 dly(2T, 0.5T) = (1, 1)

 9040 12:21:43.718352  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9041 12:21:43.721775  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9042 12:21:43.724684  Pre-setting of DQS Precalculation

 9043 12:21:43.731298  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9044 12:21:43.738084  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9045 12:21:43.744971  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9046 12:21:43.745089  

 9047 12:21:43.745183  

 9048 12:21:43.747882  [Calibration Summary] 3200 Mbps

 9049 12:21:43.747987  CH 0, Rank 0

 9050 12:21:43.751382  SW Impedance     : PASS

 9051 12:21:43.754890  DUTY Scan        : NO K

 9052 12:21:43.754999  ZQ Calibration   : PASS

 9053 12:21:43.758027  Jitter Meter     : NO K

 9054 12:21:43.761147  CBT Training     : PASS

 9055 12:21:43.761251  Write leveling   : PASS

 9056 12:21:43.764886  RX DQS gating    : PASS

 9057 12:21:43.764972  RX DQ/DQS(RDDQC) : PASS

 9058 12:21:43.768012  TX DQ/DQS        : PASS

 9059 12:21:43.771157  RX DATLAT        : PASS

 9060 12:21:43.771272  RX DQ/DQS(Engine): PASS

 9061 12:21:43.774534  TX OE            : PASS

 9062 12:21:43.774613  All Pass.

 9063 12:21:43.774677  

 9064 12:21:43.777787  CH 0, Rank 1

 9065 12:21:43.777891  SW Impedance     : PASS

 9066 12:21:43.781236  DUTY Scan        : NO K

 9067 12:21:43.784767  ZQ Calibration   : PASS

 9068 12:21:43.784881  Jitter Meter     : NO K

 9069 12:21:43.787610  CBT Training     : PASS

 9070 12:21:43.791006  Write leveling   : PASS

 9071 12:21:43.791112  RX DQS gating    : PASS

 9072 12:21:43.794553  RX DQ/DQS(RDDQC) : PASS

 9073 12:21:43.797563  TX DQ/DQS        : PASS

 9074 12:21:43.797674  RX DATLAT        : PASS

 9075 12:21:43.800783  RX DQ/DQS(Engine): PASS

 9076 12:21:43.804466  TX OE            : PASS

 9077 12:21:43.804571  All Pass.

 9078 12:21:43.804663  

 9079 12:21:43.804756  CH 1, Rank 0

 9080 12:21:43.807352  SW Impedance     : PASS

 9081 12:21:43.811022  DUTY Scan        : NO K

 9082 12:21:43.811126  ZQ Calibration   : PASS

 9083 12:21:43.814156  Jitter Meter     : NO K

 9084 12:21:43.817808  CBT Training     : PASS

 9085 12:21:43.817889  Write leveling   : PASS

 9086 12:21:43.820842  RX DQS gating    : PASS

 9087 12:21:43.820942  RX DQ/DQS(RDDQC) : PASS

 9088 12:21:43.824226  TX DQ/DQS        : PASS

 9089 12:21:43.827267  RX DATLAT        : PASS

 9090 12:21:43.827367  RX DQ/DQS(Engine): PASS

 9091 12:21:43.830744  TX OE            : PASS

 9092 12:21:43.830818  All Pass.

 9093 12:21:43.830880  

 9094 12:21:43.834248  CH 1, Rank 1

 9095 12:21:43.834351  SW Impedance     : PASS

 9096 12:21:43.837117  DUTY Scan        : NO K

 9097 12:21:43.840890  ZQ Calibration   : PASS

 9098 12:21:43.840979  Jitter Meter     : NO K

 9099 12:21:43.843935  CBT Training     : PASS

 9100 12:21:43.847029  Write leveling   : PASS

 9101 12:21:43.847116  RX DQS gating    : PASS

 9102 12:21:43.850776  RX DQ/DQS(RDDQC) : PASS

 9103 12:21:43.854165  TX DQ/DQS        : PASS

 9104 12:21:43.854252  RX DATLAT        : PASS

 9105 12:21:43.857565  RX DQ/DQS(Engine): PASS

 9106 12:21:43.860526  TX OE            : PASS

 9107 12:21:43.860612  All Pass.

 9108 12:21:43.860699  

 9109 12:21:43.860782  DramC Write-DBI on

 9110 12:21:43.864245  	PER_BANK_REFRESH: Hybrid Mode

 9111 12:21:43.867226  TX_TRACKING: ON

 9112 12:21:43.873548  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9113 12:21:43.883586  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9114 12:21:43.890260  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9115 12:21:43.893675  [FAST_K] Save calibration result to emmc

 9116 12:21:43.897105  sync common calibartion params.

 9117 12:21:43.900533  sync cbt_mode0:1, 1:1

 9118 12:21:43.900652  dram_init: ddr_geometry: 2

 9119 12:21:43.903422  dram_init: ddr_geometry: 2

 9120 12:21:43.907116  dram_init: ddr_geometry: 2

 9121 12:21:43.907204  0:dram_rank_size:100000000

 9122 12:21:43.910265  1:dram_rank_size:100000000

 9123 12:21:43.916981  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9124 12:21:43.920003  DFS_SHUFFLE_HW_MODE: ON

 9125 12:21:43.923558  dramc_set_vcore_voltage set vcore to 725000

 9126 12:21:43.923646  Read voltage for 1600, 0

 9127 12:21:43.927088  Vio18 = 0

 9128 12:21:43.927167  Vcore = 725000

 9129 12:21:43.927268  Vdram = 0

 9130 12:21:43.930250  Vddq = 0

 9131 12:21:43.930337  Vmddr = 0

 9132 12:21:43.933454  switch to 3200 Mbps bootup

 9133 12:21:43.933541  [DramcRunTimeConfig]

 9134 12:21:43.933629  PHYPLL

 9135 12:21:43.937039  DPM_CONTROL_AFTERK: ON

 9136 12:21:43.940083  PER_BANK_REFRESH: ON

 9137 12:21:43.940170  REFRESH_OVERHEAD_REDUCTION: ON

 9138 12:21:43.943482  CMD_PICG_NEW_MODE: OFF

 9139 12:21:43.947140  XRTWTW_NEW_MODE: ON

 9140 12:21:43.947258  XRTRTR_NEW_MODE: ON

 9141 12:21:43.950029  TX_TRACKING: ON

 9142 12:21:43.950135  RDSEL_TRACKING: OFF

 9143 12:21:43.953159  DQS Precalculation for DVFS: ON

 9144 12:21:43.953270  RX_TRACKING: OFF

 9145 12:21:43.956808  HW_GATING DBG: ON

 9146 12:21:43.959864  ZQCS_ENABLE_LP4: ON

 9147 12:21:43.959976  RX_PICG_NEW_MODE: ON

 9148 12:21:43.963271  TX_PICG_NEW_MODE: ON

 9149 12:21:43.963382  ENABLE_RX_DCM_DPHY: ON

 9150 12:21:43.966820  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9151 12:21:43.969862  DUMMY_READ_FOR_TRACKING: OFF

 9152 12:21:43.972951  !!! SPM_CONTROL_AFTERK: OFF

 9153 12:21:43.976656  !!! SPM could not control APHY

 9154 12:21:43.976770  IMPEDANCE_TRACKING: ON

 9155 12:21:43.979879  TEMP_SENSOR: ON

 9156 12:21:43.979996  HW_SAVE_FOR_SR: OFF

 9157 12:21:43.982900  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9158 12:21:43.986576  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9159 12:21:43.989672  Read ODT Tracking: ON

 9160 12:21:43.993293  Refresh Rate DeBounce: ON

 9161 12:21:43.993406  DFS_NO_QUEUE_FLUSH: ON

 9162 12:21:43.996700  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9163 12:21:43.999683  ENABLE_DFS_RUNTIME_MRW: OFF

 9164 12:21:44.003117  DDR_RESERVE_NEW_MODE: ON

 9165 12:21:44.003233  MR_CBT_SWITCH_FREQ: ON

 9166 12:21:44.006041  =========================

 9167 12:21:44.024565  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9168 12:21:44.028261  dram_init: ddr_geometry: 2

 9169 12:21:44.046313  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9170 12:21:44.049936  dram_init: dram init end (result: 0)

 9171 12:21:44.056356  DRAM-K: Full calibration passed in 24594 msecs

 9172 12:21:44.059408  MRC: failed to locate region type 0.

 9173 12:21:44.059517  DRAM rank0 size:0x100000000,

 9174 12:21:44.062600  DRAM rank1 size=0x100000000

 9175 12:21:44.072885  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9176 12:21:44.079318  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9177 12:21:44.086115  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9178 12:21:44.092970  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9179 12:21:44.096190  DRAM rank0 size:0x100000000,

 9180 12:21:44.099183  DRAM rank1 size=0x100000000

 9181 12:21:44.099268  CBMEM:

 9182 12:21:44.102852  IMD: root @ 0xfffff000 254 entries.

 9183 12:21:44.106333  IMD: root @ 0xffffec00 62 entries.

 9184 12:21:44.109173  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9185 12:21:44.112549  WARNING: RO_VPD is uninitialized or empty.

 9186 12:21:44.119221  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9187 12:21:44.126506  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9188 12:21:44.138911  read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps

 9189 12:21:44.150894  BS: romstage times (exec / console): total (unknown) / 24057 ms

 9190 12:21:44.151029  

 9191 12:21:44.151123  

 9192 12:21:44.160732  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9193 12:21:44.163768  ARM64: Exception handlers installed.

 9194 12:21:44.166832  ARM64: Testing exception

 9195 12:21:44.170560  ARM64: Done test exception

 9196 12:21:44.170677  Enumerating buses...

 9197 12:21:44.173697  Show all devs... Before device enumeration.

 9198 12:21:44.177305  Root Device: enabled 1

 9199 12:21:44.180187  CPU_CLUSTER: 0: enabled 1

 9200 12:21:44.180302  CPU: 00: enabled 1

 9201 12:21:44.183677  Compare with tree...

 9202 12:21:44.183805  Root Device: enabled 1

 9203 12:21:44.186605   CPU_CLUSTER: 0: enabled 1

 9204 12:21:44.190315    CPU: 00: enabled 1

 9205 12:21:44.190430  Root Device scanning...

 9206 12:21:44.193379  scan_static_bus for Root Device

 9207 12:21:44.197155  CPU_CLUSTER: 0 enabled

 9208 12:21:44.200300  scan_static_bus for Root Device done

 9209 12:21:44.203425  scan_bus: bus Root Device finished in 8 msecs

 9210 12:21:44.203537  done

 9211 12:21:44.210137  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9212 12:21:44.213305  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9213 12:21:44.219659  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9214 12:21:44.223015  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9215 12:21:44.226555  Allocating resources...

 9216 12:21:44.230015  Reading resources...

 9217 12:21:44.233370  Root Device read_resources bus 0 link: 0

 9218 12:21:44.233484  DRAM rank0 size:0x100000000,

 9219 12:21:44.236255  DRAM rank1 size=0x100000000

 9220 12:21:44.240077  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9221 12:21:44.242915  CPU: 00 missing read_resources

 9222 12:21:44.249753  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9223 12:21:44.253369  Root Device read_resources bus 0 link: 0 done

 9224 12:21:44.253478  Done reading resources.

 9225 12:21:44.259869  Show resources in subtree (Root Device)...After reading.

 9226 12:21:44.262929   Root Device child on link 0 CPU_CLUSTER: 0

 9227 12:21:44.266348    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9228 12:21:44.276186    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9229 12:21:44.276334     CPU: 00

 9230 12:21:44.279887  Root Device assign_resources, bus 0 link: 0

 9231 12:21:44.282980  CPU_CLUSTER: 0 missing set_resources

 9232 12:21:44.289411  Root Device assign_resources, bus 0 link: 0 done

 9233 12:21:44.289535  Done setting resources.

 9234 12:21:44.296468  Show resources in subtree (Root Device)...After assigning values.

 9235 12:21:44.299562   Root Device child on link 0 CPU_CLUSTER: 0

 9236 12:21:44.302685    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9237 12:21:44.312475    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9238 12:21:44.312608     CPU: 00

 9239 12:21:44.316298  Done allocating resources.

 9240 12:21:44.322905  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9241 12:21:44.323033  Enabling resources...

 9242 12:21:44.323139  done.

 9243 12:21:44.329147  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9244 12:21:44.329270  Initializing devices...

 9245 12:21:44.332579  Root Device init

 9246 12:21:44.332703  init hardware done!

 9247 12:21:44.336065  0x00000018: ctrlr->caps

 9248 12:21:44.338934  52.000 MHz: ctrlr->f_max

 9249 12:21:44.339056  0.400 MHz: ctrlr->f_min

 9250 12:21:44.342622  0x40ff8080: ctrlr->voltages

 9251 12:21:44.345513  sclk: 390625

 9252 12:21:44.345632  Bus Width = 1

 9253 12:21:44.345732  sclk: 390625

 9254 12:21:44.349029  Bus Width = 1

 9255 12:21:44.349153  Early init status = 3

 9256 12:21:44.355352  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9257 12:21:44.358735  in-header: 03 fc 00 00 01 00 00 00 

 9258 12:21:44.362289  in-data: 00 

 9259 12:21:44.365824  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9260 12:21:44.371183  in-header: 03 fd 00 00 00 00 00 00 

 9261 12:21:44.374808  in-data: 

 9262 12:21:44.377888  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9263 12:21:44.382208  in-header: 03 fc 00 00 01 00 00 00 

 9264 12:21:44.385351  in-data: 00 

 9265 12:21:44.388956  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9266 12:21:44.394300  in-header: 03 fd 00 00 00 00 00 00 

 9267 12:21:44.397712  in-data: 

 9268 12:21:44.401213  [SSUSB] Setting up USB HOST controller...

 9269 12:21:44.404266  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9270 12:21:44.407346  [SSUSB] phy power-on done.

 9271 12:21:44.411091  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9272 12:21:44.417710  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9273 12:21:44.420779  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9274 12:21:44.427680  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9275 12:21:44.433851  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9276 12:21:44.440655  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9277 12:21:44.447410  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9278 12:21:44.453704  read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps

 9279 12:21:44.457424  SPM: binary array size = 0x9dc

 9280 12:21:44.460271  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9281 12:21:44.467187  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9282 12:21:44.473977  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9283 12:21:44.480384  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9284 12:21:44.483522  configure_display: Starting display init

 9285 12:21:44.517626  anx7625_power_on_init: Init interface.

 9286 12:21:44.521204  anx7625_disable_pd_protocol: Disabled PD feature.

 9287 12:21:44.524392  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9288 12:21:44.551832  anx7625_start_dp_work: Secure OCM version=00

 9289 12:21:44.555279  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9290 12:21:44.570003  sp_tx_get_edid_block: EDID Block = 1

 9291 12:21:44.672484  Extracted contents:

 9292 12:21:44.675835  header:          00 ff ff ff ff ff ff 00

 9293 12:21:44.679024  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9294 12:21:44.682690  version:         01 04

 9295 12:21:44.685767  basic params:    95 1f 11 78 0a

 9296 12:21:44.688867  chroma info:     76 90 94 55 54 90 27 21 50 54

 9297 12:21:44.692309  established:     00 00 00

 9298 12:21:44.699085  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9299 12:21:44.705433  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9300 12:21:44.708589  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9301 12:21:44.715554  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9302 12:21:44.721987  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9303 12:21:44.725206  extensions:      00

 9304 12:21:44.725289  checksum:        fb

 9305 12:21:44.725354  

 9306 12:21:44.731783  Manufacturer: IVO Model 57d Serial Number 0

 9307 12:21:44.731869  Made week 0 of 2020

 9308 12:21:44.735486  EDID version: 1.4

 9309 12:21:44.735597  Digital display

 9310 12:21:44.738566  6 bits per primary color channel

 9311 12:21:44.738651  DisplayPort interface

 9312 12:21:44.742237  Maximum image size: 31 cm x 17 cm

 9313 12:21:44.745451  Gamma: 220%

 9314 12:21:44.745534  Check DPMS levels

 9315 12:21:44.748380  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9316 12:21:44.755300  First detailed timing is preferred timing

 9317 12:21:44.755416  Established timings supported:

 9318 12:21:44.758399  Standard timings supported:

 9319 12:21:44.761995  Detailed timings

 9320 12:21:44.765407  Hex of detail: 383680a07038204018303c0035ae10000019

 9321 12:21:44.771515  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9322 12:21:44.775129                 0780 0798 07c8 0820 hborder 0

 9323 12:21:44.778593                 0438 043b 0447 0458 vborder 0

 9324 12:21:44.781516                 -hsync -vsync

 9325 12:21:44.781630  Did detailed timing

 9326 12:21:44.787971  Hex of detail: 000000000000000000000000000000000000

 9327 12:21:44.791628  Manufacturer-specified data, tag 0

 9328 12:21:44.794772  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9329 12:21:44.797925  ASCII string: InfoVision

 9330 12:21:44.801476  Hex of detail: 000000fe00523134304e574635205248200a

 9331 12:21:44.804945  ASCII string: R140NWF5 RH 

 9332 12:21:44.805027  Checksum

 9333 12:21:44.808490  Checksum: 0xfb (valid)

 9334 12:21:44.811426  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9335 12:21:44.814647  DSI data_rate: 832800000 bps

 9336 12:21:44.821323  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9337 12:21:44.825000  anx7625_parse_edid: pixelclock(138800).

 9338 12:21:44.827876   hactive(1920), hsync(48), hfp(24), hbp(88)

 9339 12:21:44.831517   vactive(1080), vsync(12), vfp(3), vbp(17)

 9340 12:21:44.834639  anx7625_dsi_config: config dsi.

 9341 12:21:44.841073  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9342 12:21:44.854775  anx7625_dsi_config: success to config DSI

 9343 12:21:44.857783  anx7625_dp_start: MIPI phy setup OK.

 9344 12:21:44.861510  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9345 12:21:44.864674  mtk_ddp_mode_set invalid vrefresh 60

 9346 12:21:44.867810  main_disp_path_setup

 9347 12:21:44.867916  ovl_layer_smi_id_en

 9348 12:21:44.871450  ovl_layer_smi_id_en

 9349 12:21:44.871532  ccorr_config

 9350 12:21:44.871604  aal_config

 9351 12:21:44.874326  gamma_config

 9352 12:21:44.874440  postmask_config

 9353 12:21:44.877684  dither_config

 9354 12:21:44.881460  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9355 12:21:44.887857                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9356 12:21:44.891306  Root Device init finished in 555 msecs

 9357 12:21:44.894196  CPU_CLUSTER: 0 init

 9358 12:21:44.900890  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9359 12:21:44.904091  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9360 12:21:44.907859  APU_MBOX 0x190000b0 = 0x10001

 9361 12:21:44.910980  APU_MBOX 0x190001b0 = 0x10001

 9362 12:21:44.914568  APU_MBOX 0x190005b0 = 0x10001

 9363 12:21:44.917477  APU_MBOX 0x190006b0 = 0x10001

 9364 12:21:44.921024  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9365 12:21:44.933520  read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps

 9366 12:21:44.946013  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9367 12:21:44.952752  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9368 12:21:44.964254  read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps

 9369 12:21:44.973484  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9370 12:21:44.976702  CPU_CLUSTER: 0 init finished in 81 msecs

 9371 12:21:44.980194  Devices initialized

 9372 12:21:44.983435  Show all devs... After init.

 9373 12:21:44.983524  Root Device: enabled 1

 9374 12:21:44.986844  CPU_CLUSTER: 0: enabled 1

 9375 12:21:44.990391  CPU: 00: enabled 1

 9376 12:21:44.993128  BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms

 9377 12:21:44.996641  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9378 12:21:44.999874  ELOG: NV offset 0x57f000 size 0x1000

 9379 12:21:45.006945  read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps

 9380 12:21:45.013133  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9381 12:21:45.016807  ELOG: Event(17) added with size 13 at 2023-10-27 12:21:45 UTC

 9382 12:21:45.023238  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9383 12:21:45.026604  in-header: 03 43 00 00 2c 00 00 00 

 9384 12:21:45.036631  in-data: 1b 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9385 12:21:45.043282  ELOG: Event(A1) added with size 10 at 2023-10-27 12:21:45 UTC

 9386 12:21:45.049531  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9387 12:21:45.056575  ELOG: Event(A0) added with size 9 at 2023-10-27 12:21:45 UTC

 9388 12:21:45.059604  elog_add_boot_reason: Logged dev mode boot

 9389 12:21:45.066187  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9390 12:21:45.066310  Finalize devices...

 9391 12:21:45.069309  Devices finalized

 9392 12:21:45.073077  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9393 12:21:45.075908  Writing coreboot table at 0xffe64000

 9394 12:21:45.079763   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9395 12:21:45.082764   1. 0000000040000000-00000000400fffff: RAM

 9396 12:21:45.089399   2. 0000000040100000-000000004032afff: RAMSTAGE

 9397 12:21:45.092893   3. 000000004032b000-00000000545fffff: RAM

 9398 12:21:45.096382   4. 0000000054600000-000000005465ffff: BL31

 9399 12:21:45.099256   5. 0000000054660000-00000000ffe63fff: RAM

 9400 12:21:45.105787   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9401 12:21:45.109458   7. 0000000100000000-000000023fffffff: RAM

 9402 12:21:45.112747  Passing 5 GPIOs to payload:

 9403 12:21:45.115863              NAME |       PORT | POLARITY |     VALUE

 9404 12:21:45.118992          EC in RW | 0x000000aa |      low | undefined

 9405 12:21:45.125891      EC interrupt | 0x00000005 |      low | undefined

 9406 12:21:45.129554     TPM interrupt | 0x000000ab |     high | undefined

 9407 12:21:45.136109    SD card detect | 0x00000011 |     high | undefined

 9408 12:21:45.139398    speaker enable | 0x00000093 |     high | undefined

 9409 12:21:45.142806  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9410 12:21:45.146122  in-header: 03 f9 00 00 02 00 00 00 

 9411 12:21:45.149124  in-data: 02 00 

 9412 12:21:45.152211  ADC[4]: Raw value=897410 ID=7

 9413 12:21:45.152292  ADC[3]: Raw value=212700 ID=1

 9414 12:21:45.155750  RAM Code: 0x71

 9415 12:21:45.159356  ADC[6]: Raw value=74722 ID=0

 9416 12:21:45.159455  ADC[5]: Raw value=211590 ID=1

 9417 12:21:45.162454  SKU Code: 0x1

 9418 12:21:45.165450  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 360f

 9419 12:21:45.169032  coreboot table: 964 bytes.

 9420 12:21:45.172096  IMD ROOT    0. 0xfffff000 0x00001000

 9421 12:21:45.175760  IMD SMALL   1. 0xffffe000 0x00001000

 9422 12:21:45.178870  RO MCACHE   2. 0xffffc000 0x00001104

 9423 12:21:45.181936  CONSOLE     3. 0xfff7c000 0x00080000

 9424 12:21:45.185637  FMAP        4. 0xfff7b000 0x00000452

 9425 12:21:45.188871  TIME STAMP  5. 0xfff7a000 0x00000910

 9426 12:21:45.191827  VBOOT WORK  6. 0xfff66000 0x00014000

 9427 12:21:45.195506  RAMOOPS     7. 0xffe66000 0x00100000

 9428 12:21:45.198974  COREBOOT    8. 0xffe64000 0x00002000

 9429 12:21:45.201916  IMD small region:

 9430 12:21:45.205385    IMD ROOT    0. 0xffffec00 0x00000400

 9431 12:21:45.208389    VPD         1. 0xffffeb80 0x0000006c

 9432 12:21:45.211642    MMC STATUS  2. 0xffffeb60 0x00000004

 9433 12:21:45.215103  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9434 12:21:45.218364  Probing TPM:  done!

 9435 12:21:45.221683  Connected to device vid:did:rid of 1ae0:0028:00

 9436 12:21:45.232832  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9437 12:21:45.235836  Initialized TPM device CR50 revision 0

 9438 12:21:45.239557  Checking cr50 for pending updates

 9439 12:21:45.243067  Reading cr50 TPM mode

 9440 12:21:45.251663  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9441 12:21:45.258651  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9442 12:21:45.298681  read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps

 9443 12:21:45.301676  Checking segment from ROM address 0x40100000

 9444 12:21:45.305410  Checking segment from ROM address 0x4010001c

 9445 12:21:45.311877  Loading segment from ROM address 0x40100000

 9446 12:21:45.311968    code (compression=0)

 9447 12:21:45.321906    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9448 12:21:45.328703  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9449 12:21:45.328799  it's not compressed!

 9450 12:21:45.335104  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9451 12:21:45.338804  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9452 12:21:45.359250  Loading segment from ROM address 0x4010001c

 9453 12:21:45.359395    Entry Point 0x80000000

 9454 12:21:45.362405  Loaded segments

 9455 12:21:45.365610  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9456 12:21:45.372044  Jumping to boot code at 0x80000000(0xffe64000)

 9457 12:21:45.378692  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9458 12:21:45.385774  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9459 12:21:45.393205  read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps

 9460 12:21:45.397018  Checking segment from ROM address 0x40100000

 9461 12:21:45.400032  Checking segment from ROM address 0x4010001c

 9462 12:21:45.407124  Loading segment from ROM address 0x40100000

 9463 12:21:45.407243    code (compression=1)

 9464 12:21:45.413260    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9465 12:21:45.423685  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9466 12:21:45.423804  using LZMA

 9467 12:21:45.432001  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9468 12:21:45.438320  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9469 12:21:45.441824  Loading segment from ROM address 0x4010001c

 9470 12:21:45.441917    Entry Point 0x54601000

 9471 12:21:45.445426  Loaded segments

 9472 12:21:45.448502  NOTICE:  MT8192 bl31_setup

 9473 12:21:45.455282  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9474 12:21:45.459033  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9475 12:21:45.461969  WARNING: region 0:

 9476 12:21:45.465422  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9477 12:21:45.465510  WARNING: region 1:

 9478 12:21:45.471915  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9479 12:21:45.475495  WARNING: region 2:

 9480 12:21:45.478615  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9481 12:21:45.482123  WARNING: region 3:

 9482 12:21:45.485546  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9483 12:21:45.488835  WARNING: region 4:

 9484 12:21:45.495324  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9485 12:21:45.495444  WARNING: region 5:

 9486 12:21:45.498472  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9487 12:21:45.502217  WARNING: region 6:

 9488 12:21:45.505234  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9489 12:21:45.508799  WARNING: region 7:

 9490 12:21:45.511755  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9491 12:21:45.518637  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9492 12:21:45.521816  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9493 12:21:45.525520  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9494 12:21:45.531841  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9495 12:21:45.535258  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9496 12:21:45.538292  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9497 12:21:45.545407  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9498 12:21:45.548734  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9499 12:21:45.555536  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9500 12:21:45.558702  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9501 12:21:45.561798  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9502 12:21:45.568467  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9503 12:21:45.572232  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9504 12:21:45.575126  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9505 12:21:45.582099  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9506 12:21:45.585488  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9507 12:21:45.591996  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9508 12:21:45.595544  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9509 12:21:45.598534  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9510 12:21:45.605471  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9511 12:21:45.608900  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9512 12:21:45.611968  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9513 12:21:45.618566  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9514 12:21:45.621747  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9515 12:21:45.628419  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9516 12:21:45.632096  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9517 12:21:45.635574  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9518 12:21:45.642210  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9519 12:21:45.645208  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9520 12:21:45.652232  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9521 12:21:45.655513  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9522 12:21:45.658752  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9523 12:21:45.665545  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9524 12:21:45.668644  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9525 12:21:45.671735  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9526 12:21:45.675377  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9527 12:21:45.682130  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9528 12:21:45.685128  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9529 12:21:45.688600  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9530 12:21:45.692231  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9531 12:21:45.698787  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9532 12:21:45.701963  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9533 12:21:45.705051  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9534 12:21:45.708752  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9535 12:21:45.715359  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9536 12:21:45.718712  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9537 12:21:45.721940  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9538 12:21:45.725417  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9539 12:21:45.731636  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9540 12:21:45.735258  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9541 12:21:45.742073  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9542 12:21:45.744991  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9543 12:21:45.748431  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9544 12:21:45.755264  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9545 12:21:45.758801  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9546 12:21:45.765511  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9547 12:21:45.768663  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9548 12:21:45.775300  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9549 12:21:45.778339  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9550 12:21:45.781998  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9551 12:21:45.788821  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9552 12:21:45.791840  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9553 12:21:45.798452  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9554 12:21:45.801996  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9555 12:21:45.808859  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9556 12:21:45.811781  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9557 12:21:45.818590  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9558 12:21:45.821792  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9559 12:21:45.825555  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9560 12:21:45.832026  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9561 12:21:45.835728  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9562 12:21:45.842310  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9563 12:21:45.845651  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9564 12:21:45.848766  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9565 12:21:45.855417  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9566 12:21:45.858774  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9567 12:21:45.865476  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9568 12:21:45.868950  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9569 12:21:45.875253  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9570 12:21:45.878906  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9571 12:21:45.885179  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9572 12:21:45.888785  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9573 12:21:45.891982  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9574 12:21:45.898516  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9575 12:21:45.902151  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9576 12:21:45.908810  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9577 12:21:45.912027  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9578 12:21:45.915767  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9579 12:21:45.921936  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9580 12:21:45.925686  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9581 12:21:45.931957  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9582 12:21:45.935330  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9583 12:21:45.942170  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9584 12:21:45.945235  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9585 12:21:45.952322  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9586 12:21:45.955213  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9587 12:21:45.958697  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9588 12:21:45.962130  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9589 12:21:45.968479  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9590 12:21:45.971726  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9591 12:21:45.975104  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9592 12:21:45.981713  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9593 12:21:45.985665  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9594 12:21:45.988687  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9595 12:21:45.995297  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9596 12:21:45.999057  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9597 12:21:46.005627  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9598 12:21:46.008750  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9599 12:21:46.012331  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9600 12:21:46.019065  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9601 12:21:46.022211  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9602 12:21:46.028935  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9603 12:21:46.031967  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9604 12:21:46.035203  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9605 12:21:46.041984  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9606 12:21:46.045511  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9607 12:21:46.048624  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9608 12:21:46.055238  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9609 12:21:46.058947  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9610 12:21:46.061993  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9611 12:21:46.068931  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9612 12:21:46.072244  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9613 12:21:46.075416  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9614 12:21:46.078998  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9615 12:21:46.085436  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9616 12:21:46.088775  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9617 12:21:46.092038  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9618 12:21:46.099040  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9619 12:21:46.102297  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9620 12:21:46.108814  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9621 12:21:46.111922  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9622 12:21:46.115606  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9623 12:21:46.122021  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9624 12:21:46.125136  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9625 12:21:46.131854  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9626 12:21:46.135454  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9627 12:21:46.138725  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9628 12:21:46.145299  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9629 12:21:46.148448  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9630 12:21:46.152007  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9631 12:21:46.158625  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9632 12:21:46.162292  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9633 12:21:46.168523  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9634 12:21:46.172224  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9635 12:21:46.175217  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9636 12:21:46.181936  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9637 12:21:46.185325  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9638 12:21:46.192085  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9639 12:21:46.195377  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9640 12:21:46.198814  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9641 12:21:46.205132  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9642 12:21:46.208893  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9643 12:21:46.212182  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9644 12:21:46.218791  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9645 12:21:46.221844  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9646 12:21:46.228598  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9647 12:21:46.232369  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9648 12:21:46.235410  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9649 12:21:46.242465  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9650 12:21:46.245449  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9651 12:21:46.252232  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9652 12:21:46.255362  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9653 12:21:46.259089  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9654 12:21:46.265237  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9655 12:21:46.269014  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9656 12:21:46.272126  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9657 12:21:46.278534  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9658 12:21:46.281651  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9659 12:21:46.288313  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9660 12:21:46.291974  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9661 12:21:46.294955  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9662 12:21:46.301418  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9663 12:21:46.305164  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9664 12:21:46.311800  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9665 12:21:46.314763  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9666 12:21:46.318116  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9667 12:21:46.325182  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9668 12:21:46.327892  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9669 12:21:46.334718  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9670 12:21:46.337760  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9671 12:21:46.341414  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9672 12:21:46.347759  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9673 12:21:46.351416  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9674 12:21:46.357825  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9675 12:21:46.360995  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9676 12:21:46.364574  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9677 12:21:46.371521  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9678 12:21:46.374496  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9679 12:21:46.381397  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9680 12:21:46.384594  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9681 12:21:46.390921  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9682 12:21:46.394507  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9683 12:21:46.397420  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9684 12:21:46.403820  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9685 12:21:46.407298  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9686 12:21:46.413983  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9687 12:21:46.417660  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9688 12:21:46.423812  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9689 12:21:46.427246  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9690 12:21:46.430739  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9691 12:21:46.437251  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9692 12:21:46.440100  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9693 12:21:46.447288  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9694 12:21:46.450431  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9695 12:21:46.457182  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9696 12:21:46.460426  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9697 12:21:46.463502  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9698 12:21:46.470319  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9699 12:21:46.473533  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9700 12:21:46.479943  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9701 12:21:46.483068  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9702 12:21:46.486952  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9703 12:21:46.493215  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9704 12:21:46.496294  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9705 12:21:46.503208  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9706 12:21:46.506673  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9707 12:21:46.512996  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9708 12:21:46.516559  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9709 12:21:46.519921  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9710 12:21:46.526167  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9711 12:21:46.529801  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9712 12:21:46.536203  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9713 12:21:46.539826  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9714 12:21:46.543090  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9715 12:21:46.549578  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9716 12:21:46.553010  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9717 12:21:46.559278  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9718 12:21:46.562775  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9719 12:21:46.569400  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9720 12:21:46.572384  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9721 12:21:46.575589  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9722 12:21:46.578833  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9723 12:21:46.585800  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9724 12:21:46.589051  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9725 12:21:46.592177  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9726 12:21:46.599255  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9727 12:21:46.602312  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9728 12:21:46.605429  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9729 12:21:46.612078  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9730 12:21:46.615728  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9731 12:21:46.618684  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9732 12:21:46.625297  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9733 12:21:46.629014  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9734 12:21:46.631956  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9735 12:21:46.638289  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9736 12:21:46.641746  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9737 12:21:46.648236  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9738 12:21:46.651875  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9739 12:21:46.655033  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9740 12:21:46.661475  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9741 12:21:46.664966  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9742 12:21:46.671588  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9743 12:21:46.674965  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9744 12:21:46.678325  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9745 12:21:46.684694  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9746 12:21:46.687937  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9747 12:21:46.691672  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9748 12:21:46.698166  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9749 12:21:46.701270  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9750 12:21:46.704445  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9751 12:21:46.710823  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9752 12:21:46.714558  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9753 12:21:46.721335  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9754 12:21:46.724497  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9755 12:21:46.727526  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9756 12:21:46.734386  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9757 12:21:46.737439  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9758 12:21:46.744057  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9759 12:21:46.747752  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9760 12:21:46.750823  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9761 12:21:46.754278  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9762 12:21:46.757567  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9763 12:21:46.764008  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9764 12:21:46.767292  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9765 12:21:46.770616  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9766 12:21:46.773637  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9767 12:21:46.780757  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9768 12:21:46.783587  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9769 12:21:46.787034  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9770 12:21:46.790237  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9771 12:21:46.796750  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9772 12:21:46.800514  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9773 12:21:46.806970  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9774 12:21:46.810125  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9775 12:21:46.813340  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9776 12:21:46.820312  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9777 12:21:46.823397  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9778 12:21:46.830271  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9779 12:21:46.833277  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9780 12:21:46.836751  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9781 12:21:46.843786  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9782 12:21:46.847028  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9783 12:21:46.853165  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9784 12:21:46.856848  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9785 12:21:46.863177  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9786 12:21:46.866621  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9787 12:21:46.870072  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9788 12:21:46.878729  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9789 12:21:46.879942  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9790 12:21:46.886239  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9791 12:21:46.889960  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9792 12:21:46.892778  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9793 12:21:46.899577  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9794 12:21:46.902687  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9795 12:21:46.909596  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9796 12:21:46.912682  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9797 12:21:46.915936  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9798 12:21:46.922839  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9799 12:21:46.925811  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9800 12:21:46.932661  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9801 12:21:46.935802  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9802 12:21:46.942371  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9803 12:21:46.945909  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9804 12:21:46.948786  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9805 12:21:46.955572  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9806 12:21:46.958843  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9807 12:21:46.965662  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9808 12:21:46.968892  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9809 12:21:46.975709  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9810 12:21:46.978686  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9811 12:21:46.981945  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9812 12:21:46.988707  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9813 12:21:46.991804  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9814 12:21:46.998560  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9815 12:21:47.002198  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9816 12:21:47.005121  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9817 12:21:47.012092  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9818 12:21:47.015403  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9819 12:21:47.021745  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9820 12:21:47.024975  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9821 12:21:47.028170  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9822 12:21:47.035014  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9823 12:21:47.038119  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9824 12:21:47.045205  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9825 12:21:47.048303  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9826 12:21:47.054872  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9827 12:21:47.057975  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9828 12:21:47.061782  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9829 12:21:47.068370  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9830 12:21:47.071363  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9831 12:21:47.077846  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9832 12:21:47.081620  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9833 12:21:47.084674  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9834 12:21:47.091132  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9835 12:21:47.094446  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9836 12:21:47.100984  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9837 12:21:47.104658  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9838 12:21:47.107868  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9839 12:21:47.114297  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9840 12:21:47.117878  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9841 12:21:47.124473  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9842 12:21:47.127679  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9843 12:21:47.134100  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9844 12:21:47.137813  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9845 12:21:47.141007  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9846 12:21:47.147531  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9847 12:21:47.150512  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9848 12:21:47.157493  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9849 12:21:47.160848  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9850 12:21:47.167596  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9851 12:21:47.170882  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9852 12:21:47.173990  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9853 12:21:47.180864  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9854 12:21:47.184046  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9855 12:21:47.190686  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9856 12:21:47.193842  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9857 12:21:47.200144  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9858 12:21:47.204096  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9859 12:21:47.210463  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9860 12:21:47.213723  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9861 12:21:47.216869  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9862 12:21:47.223536  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9863 12:21:47.226820  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9864 12:21:47.233768  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9865 12:21:47.237427  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9866 12:21:47.243754  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9867 12:21:47.246982  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9868 12:21:47.250524  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9869 12:21:47.256849  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9870 12:21:47.260259  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9871 12:21:47.266818  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9872 12:21:47.269966  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9873 12:21:47.277104  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9874 12:21:47.280064  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9875 12:21:47.286571  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9876 12:21:47.289770  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9877 12:21:47.293082  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9878 12:21:47.299923  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9879 12:21:47.303108  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9880 12:21:47.310130  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9881 12:21:47.313353  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9882 12:21:47.319644  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9883 12:21:47.323583  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9884 12:21:47.326679  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9885 12:21:47.333117  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9886 12:21:47.336317  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9887 12:21:47.343337  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9888 12:21:47.346499  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9889 12:21:47.352937  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9890 12:21:47.356649  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9891 12:21:47.363013  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9892 12:21:47.366164  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9893 12:21:47.369817  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9894 12:21:47.376073  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9895 12:21:47.379241  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9896 12:21:47.386122  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9897 12:21:47.389644  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9898 12:21:47.396090  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9899 12:21:47.399421  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9900 12:21:47.402962  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9901 12:21:47.409403  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9902 12:21:47.412678  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9903 12:21:47.419312  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9904 12:21:47.422579  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9905 12:21:47.429510  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9906 12:21:47.432494  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9907 12:21:47.439464  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9908 12:21:47.442603  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9909 12:21:47.448944  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9910 12:21:47.452602  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9911 12:21:47.458898  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9912 12:21:47.462143  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9913 12:21:47.469281  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9914 12:21:47.472081  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9915 12:21:47.478916  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9916 12:21:47.482569  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9917 12:21:47.489326  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9918 12:21:47.492194  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9919 12:21:47.499264  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9920 12:21:47.501993  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9921 12:21:47.508595  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9922 12:21:47.511940  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9923 12:21:47.518758  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9924 12:21:47.521834  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9925 12:21:47.528391  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9926 12:21:47.528509  INFO:    [APUAPC] vio 0

 9927 12:21:47.535279  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9928 12:21:47.539026  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9929 12:21:47.542174  INFO:    [APUAPC] D0_APC_0: 0x400510

 9930 12:21:47.545236  INFO:    [APUAPC] D0_APC_1: 0x0

 9931 12:21:47.548390  INFO:    [APUAPC] D0_APC_2: 0x1540

 9932 12:21:47.552236  INFO:    [APUAPC] D0_APC_3: 0x0

 9933 12:21:47.555366  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9934 12:21:47.558566  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9935 12:21:47.561736  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9936 12:21:47.565081  INFO:    [APUAPC] D1_APC_3: 0x0

 9937 12:21:47.568718  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9938 12:21:47.571834  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9939 12:21:47.575033  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9940 12:21:47.578337  INFO:    [APUAPC] D2_APC_3: 0x0

 9941 12:21:47.581731  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9942 12:21:47.584838  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9943 12:21:47.588606  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9944 12:21:47.591744  INFO:    [APUAPC] D3_APC_3: 0x0

 9945 12:21:47.594793  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9946 12:21:47.598572  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9947 12:21:47.601658  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9948 12:21:47.604663  INFO:    [APUAPC] D4_APC_3: 0x0

 9949 12:21:47.608379  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9950 12:21:47.611548  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9951 12:21:47.614904  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9952 12:21:47.615014  INFO:    [APUAPC] D5_APC_3: 0x0

 9953 12:21:47.618428  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9954 12:21:47.624582  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9955 12:21:47.627873  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9956 12:21:47.627984  INFO:    [APUAPC] D6_APC_3: 0x0

 9957 12:21:47.631221  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9958 12:21:47.634807  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9959 12:21:47.637968  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9960 12:21:47.641227  INFO:    [APUAPC] D7_APC_3: 0x0

 9961 12:21:47.644586  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9962 12:21:47.647943  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9963 12:21:47.651328  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9964 12:21:47.654501  INFO:    [APUAPC] D8_APC_3: 0x0

 9965 12:21:47.658319  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9966 12:21:47.661414  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9967 12:21:47.664574  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9968 12:21:47.667864  INFO:    [APUAPC] D9_APC_3: 0x0

 9969 12:21:47.671026  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9970 12:21:47.674228  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9971 12:21:47.677942  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9972 12:21:47.681194  INFO:    [APUAPC] D10_APC_3: 0x0

 9973 12:21:47.684696  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9974 12:21:47.688056  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9975 12:21:47.691509  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9976 12:21:47.694483  INFO:    [APUAPC] D11_APC_3: 0x0

 9977 12:21:47.697597  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9978 12:21:47.701090  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9979 12:21:47.704192  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9980 12:21:47.707810  INFO:    [APUAPC] D12_APC_3: 0x0

 9981 12:21:47.711022  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9982 12:21:47.714198  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9983 12:21:47.717492  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9984 12:21:47.721065  INFO:    [APUAPC] D13_APC_3: 0x0

 9985 12:21:47.724500  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9986 12:21:47.728015  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9987 12:21:47.731248  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9988 12:21:47.734632  INFO:    [APUAPC] D14_APC_3: 0x0

 9989 12:21:47.737593  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9990 12:21:47.741005  INFO:    [APUAPC] D15_APC_1: 0xffffffff

 9991 12:21:47.744469  INFO:    [APUAPC] D15_APC_2: 0x3fffff

 9992 12:21:47.747928  INFO:    [APUAPC] D15_APC_3: 0x0

 9993 12:21:47.750780  INFO:    [APUAPC] APC_CON: 0x4

 9994 12:21:47.754105  INFO:    [NOCDAPC] D0_APC_0: 0x0

 9995 12:21:47.757852  INFO:    [NOCDAPC] D0_APC_1: 0x0

 9996 12:21:47.761099  INFO:    [NOCDAPC] D1_APC_0: 0x0

 9997 12:21:47.764561  INFO:    [NOCDAPC] D1_APC_1: 0xfff

 9998 12:21:47.767763  INFO:    [NOCDAPC] D2_APC_0: 0x0

 9999 12:21:47.767871  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10000 12:21:47.770984  INFO:    [NOCDAPC] D3_APC_0: 0x0

10001 12:21:47.774116  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10002 12:21:47.777430  INFO:    [NOCDAPC] D4_APC_0: 0x0

10003 12:21:47.781094  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10004 12:21:47.784259  INFO:    [NOCDAPC] D5_APC_0: 0x0

10005 12:21:47.787218  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10006 12:21:47.790553  INFO:    [NOCDAPC] D6_APC_0: 0x0

10007 12:21:47.794000  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10008 12:21:47.797403  INFO:    [NOCDAPC] D7_APC_0: 0x0

10009 12:21:47.800821  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10010 12:21:47.800931  INFO:    [NOCDAPC] D8_APC_0: 0x0

10011 12:21:47.804167  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10012 12:21:47.807051  INFO:    [NOCDAPC] D9_APC_0: 0x0

10013 12:21:47.810653  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10014 12:21:47.813757  INFO:    [NOCDAPC] D10_APC_0: 0x0

10015 12:21:47.816856  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10016 12:21:47.820706  INFO:    [NOCDAPC] D11_APC_0: 0x0

10017 12:21:47.823861  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10018 12:21:47.827020  INFO:    [NOCDAPC] D12_APC_0: 0x0

10019 12:21:47.830185  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10020 12:21:47.833565  INFO:    [NOCDAPC] D13_APC_0: 0x0

10021 12:21:47.837117  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10022 12:21:47.840226  INFO:    [NOCDAPC] D14_APC_0: 0x0

10023 12:21:47.843332  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10024 12:21:47.847013  INFO:    [NOCDAPC] D15_APC_0: 0x0

10025 12:21:47.850544  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10026 12:21:47.850658  INFO:    [NOCDAPC] APC_CON: 0x4

10027 12:21:47.853528  INFO:    [APUAPC] set_apusys_apc done

10028 12:21:47.856714  INFO:    [DEVAPC] devapc_init done

10029 12:21:47.863338  INFO:    GICv3 without legacy support detected.

10030 12:21:47.866905  INFO:    ARM GICv3 driver initialized in EL3

10031 12:21:47.870139  INFO:    Maximum SPI INTID supported: 639

10032 12:21:47.873346  INFO:    BL31: Initializing runtime services

10033 12:21:47.879713  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10034 12:21:47.882929  INFO:    SPM: enable CPC mode

10035 12:21:47.886712  INFO:    mcdi ready for mcusys-off-idle and system suspend

10036 12:21:47.893072  INFO:    BL31: Preparing for EL3 exit to normal world

10037 12:21:47.896118  INFO:    Entry point address = 0x80000000

10038 12:21:47.896230  INFO:    SPSR = 0x8

10039 12:21:47.903475  

10040 12:21:47.903583  

10041 12:21:47.903678  

10042 12:21:47.906822  Starting depthcharge on Spherion...

10043 12:21:47.906929  

10044 12:21:47.907071  Wipe memory regions:

10045 12:21:47.907205  

10046 12:21:47.908098  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10047 12:21:47.908241  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10048 12:21:47.908357  Setting prompt string to ['asurada:']
10049 12:21:47.908470  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10050 12:21:47.910117  	[0x00000040000000, 0x00000054600000)

10051 12:21:48.032607  

10052 12:21:48.032782  	[0x00000054660000, 0x00000080000000)

10053 12:21:48.293163  

10054 12:21:48.293343  	[0x000000821a7280, 0x000000ffe64000)

10055 12:21:49.038301  

10056 12:21:49.038466  	[0x00000100000000, 0x00000240000000)

10057 12:21:50.928811  

10058 12:21:50.932160  Initializing XHCI USB controller at 0x11200000.

10059 12:21:51.970092  

10060 12:21:51.972795  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10061 12:21:51.972907  

10062 12:21:51.973000  

10063 12:21:51.973088  

10064 12:21:51.973434  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10066 12:21:52.073910  asurada: tftpboot 192.168.201.1 11893139/tftp-deploy-g3sfu_86/kernel/image.itb 11893139/tftp-deploy-g3sfu_86/kernel/cmdline 

10067 12:21:52.074083  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10068 12:21:52.074176  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10069 12:21:52.078826  tftpboot 192.168.201.1 11893139/tftp-deploy-g3sfu_86/kernel/image.itp-deploy-g3sfu_86/kernel/cmdline 

10070 12:21:52.078922  

10071 12:21:52.078989  Waiting for link

10072 12:21:52.239478  

10073 12:21:52.239618  R8152: Initializing

10074 12:21:52.239691  

10075 12:21:52.242115  Version 6 (ocp_data = 5c30)

10076 12:21:52.242200  

10077 12:21:52.245503  R8152: Done initializing

10078 12:21:52.245590  

10079 12:21:52.245658  Adding net device

10080 12:21:54.148802  

10081 12:21:54.148944  done.

10082 12:21:54.149014  

10083 12:21:54.149076  MAC: 00:24:32:30:78:ff

10084 12:21:54.149136  

10085 12:21:54.152498  Sending DHCP discover... done.

10086 12:21:54.152586  

10087 12:21:57.236378  Waiting for reply... done.

10088 12:21:57.236644  

10089 12:21:57.236801  Sending DHCP request... done.

10090 12:21:57.239933  

10091 12:21:57.247374  Waiting for reply... done.

10092 12:21:57.247549  

10093 12:21:57.247687  My ip is 192.168.201.21

10094 12:21:57.247827  

10095 12:21:57.250423  The DHCP server ip is 192.168.201.1

10096 12:21:57.250579  

10097 12:21:57.257072  TFTP server IP predefined by user: 192.168.201.1

10098 12:21:57.257236  

10099 12:21:57.263919  Bootfile predefined by user: 11893139/tftp-deploy-g3sfu_86/kernel/image.itb

10100 12:21:57.264082  

10101 12:21:57.264227  Sending tftp read request... done.

10102 12:21:57.266993  

10103 12:21:57.270629  Waiting for the transfer... 

10104 12:21:57.270788  

10105 12:21:57.803631  00000000 ################################################################

10106 12:21:57.803810  

10107 12:21:58.333006  00080000 ################################################################

10108 12:21:58.333142  

10109 12:21:58.862473  00100000 ################################################################

10110 12:21:58.862635  

10111 12:21:59.393070  00180000 ################################################################

10112 12:21:59.393229  

10113 12:21:59.923813  00200000 ################################################################

10114 12:21:59.923995  

10115 12:22:00.455862  00280000 ################################################################

10116 12:22:00.456036  

10117 12:22:00.978989  00300000 ################################################################

10118 12:22:00.979162  

10119 12:22:01.502274  00380000 ################################################################

10120 12:22:01.502446  

10121 12:22:02.031861  00400000 ################################################################

10122 12:22:02.032066  

10123 12:22:02.565545  00480000 ################################################################

10124 12:22:02.565721  

10125 12:22:03.092630  00500000 ################################################################

10126 12:22:03.092804  

10127 12:22:03.621067  00580000 ################################################################

10128 12:22:03.621237  

10129 12:22:04.151206  00600000 ################################################################

10130 12:22:04.151373  

10131 12:22:04.676905  00680000 ################################################################

10132 12:22:04.677099  

10133 12:22:05.193925  00700000 ################################################################

10134 12:22:05.194106  

10135 12:22:05.724343  00780000 ################################################################

10136 12:22:05.724487  

10137 12:22:06.286358  00800000 ################################################################

10138 12:22:06.286491  

10139 12:22:06.822215  00880000 ################################################################

10140 12:22:06.822391  

10141 12:22:07.357754  00900000 ################################################################

10142 12:22:07.357890  

10143 12:22:07.899000  00980000 ################################################################

10144 12:22:07.899174  

10145 12:22:08.440200  00a00000 ################################################################

10146 12:22:08.440370  

10147 12:22:08.973110  00a80000 ################################################################

10148 12:22:08.973286  

10149 12:22:09.520932  00b00000 ################################################################

10150 12:22:09.521069  

10151 12:22:10.058643  00b80000 ################################################################

10152 12:22:10.058789  

10153 12:22:10.598448  00c00000 ################################################################

10154 12:22:10.598587  

10155 12:22:11.140015  00c80000 ################################################################

10156 12:22:11.140193  

10157 12:22:11.684990  00d00000 ################################################################

10158 12:22:11.685178  

10159 12:22:12.240272  00d80000 ################################################################

10160 12:22:12.240427  

10161 12:22:12.797817  00e00000 ################################################################

10162 12:22:12.798004  

10163 12:22:13.361025  00e80000 ################################################################

10164 12:22:13.361168  

10165 12:22:13.897051  00f00000 ################################################################

10166 12:22:13.897191  

10167 12:22:14.436905  00f80000 ################################################################

10168 12:22:14.437047  

10169 12:22:14.967916  01000000 ################################################################

10170 12:22:14.968082  

10171 12:22:15.511854  01080000 ################################################################

10172 12:22:15.511988  

10173 12:22:16.048031  01100000 ################################################################

10174 12:22:16.048172  

10175 12:22:16.592389  01180000 ################################################################

10176 12:22:16.592531  

10177 12:22:17.119635  01200000 ################################################################

10178 12:22:17.119770  

10179 12:22:17.704867  01280000 ################################################################

10180 12:22:17.705343  

10181 12:22:18.400825  01300000 ################################################################

10182 12:22:18.401344  

10183 12:22:19.048332  01380000 ################################################################

10184 12:22:19.048469  

10185 12:22:19.641373  01400000 ################################################################

10186 12:22:19.641533  

10187 12:22:20.219191  01480000 ################################################################

10188 12:22:20.219328  

10189 12:22:20.820475  01500000 ################################################################

10190 12:22:20.820610  

10191 12:22:21.429257  01580000 ################################################################

10192 12:22:21.429391  

10193 12:22:22.029802  01600000 ################################################################

10194 12:22:22.029936  

10195 12:22:22.632252  01680000 ################################################################

10196 12:22:22.632387  

10197 12:22:23.212618  01700000 ################################################################

10198 12:22:23.212775  

10199 12:22:23.792538  01780000 ################################################################

10200 12:22:23.792668  

10201 12:22:24.349575  01800000 ################################################################

10202 12:22:24.349710  

10203 12:22:24.918573  01880000 ################################################################

10204 12:22:24.918710  

10205 12:22:25.541504  01900000 ################################################################

10206 12:22:25.542234  

10207 12:22:26.254505  01980000 ################################################################

10208 12:22:26.255165  

10209 12:22:26.811887  01a00000 ################################################################

10210 12:22:26.812045  

10211 12:22:27.347427  01a80000 ################################################################

10212 12:22:27.347562  

10213 12:22:27.882469  01b00000 ################################################################

10214 12:22:27.882616  

10215 12:22:28.451323  01b80000 ################################################################

10216 12:22:28.451519  

10217 12:22:29.015899  01c00000 ################################################################

10218 12:22:29.016054  

10219 12:22:29.549728  01c80000 ################################################################

10220 12:22:29.549879  

10221 12:22:30.077948  01d00000 ################################################################

10222 12:22:30.078079  

10223 12:22:30.622255  01d80000 ################################################################

10224 12:22:30.622391  

10225 12:22:31.168750  01e00000 ################################################################

10226 12:22:31.168923  

10227 12:22:31.705581  01e80000 ################################################################

10228 12:22:31.705714  

10229 12:22:32.241663  01f00000 ################################################################

10230 12:22:32.241824  

10231 12:22:32.791988  01f80000 ################################################################

10232 12:22:32.792163  

10233 12:22:33.341736  02000000 ################################################################

10234 12:22:33.341890  

10235 12:22:33.903083  02080000 ################################################################

10236 12:22:33.903254  

10237 12:22:34.452030  02100000 ################################################################

10238 12:22:34.452193  

10239 12:22:34.998170  02180000 ################################################################

10240 12:22:34.998340  

10241 12:22:35.550881  02200000 ################################################################

10242 12:22:35.551018  

10243 12:22:36.096048  02280000 ################################################################

10244 12:22:36.096224  

10245 12:22:36.633371  02300000 ################################################################

10246 12:22:36.633510  

10247 12:22:37.167409  02380000 ################################################################

10248 12:22:37.167543  

10249 12:22:37.699671  02400000 ################################################################

10250 12:22:37.699812  

10251 12:22:38.245354  02480000 ################################################################

10252 12:22:38.245492  

10253 12:22:38.784653  02500000 ################################################################

10254 12:22:38.784820  

10255 12:22:39.317006  02580000 ################################################################

10256 12:22:39.317166  

10257 12:22:39.854895  02600000 ################################################################

10258 12:22:39.855030  

10259 12:22:40.393112  02680000 ################################################################

10260 12:22:40.393277  

10261 12:22:40.919550  02700000 ################################################################

10262 12:22:40.919681  

10263 12:22:41.450912  02780000 ################################################################

10264 12:22:41.451042  

10265 12:22:41.984908  02800000 ################################################################

10266 12:22:41.985078  

10267 12:22:42.511956  02880000 ################################################################

10268 12:22:42.512121  

10269 12:22:43.041100  02900000 ################################################################

10270 12:22:43.041230  

10271 12:22:43.578391  02980000 ################################################################

10272 12:22:43.578549  

10273 12:22:44.129649  02a00000 ################################################################

10274 12:22:44.129815  

10275 12:22:44.649880  02a80000 ################################################################

10276 12:22:44.650030  

10277 12:22:45.173406  02b00000 ################################################################

10278 12:22:45.173596  

10279 12:22:45.691396  02b80000 ################################################################

10280 12:22:45.691557  

10281 12:22:46.211769  02c00000 ################################################################

10282 12:22:46.211909  

10283 12:22:46.748489  02c80000 ################################################################

10284 12:22:46.748655  

10285 12:22:47.277909  02d00000 ################################################################

10286 12:22:47.278076  

10287 12:22:47.821795  02d80000 ################################################################

10288 12:22:47.821953  

10289 12:22:48.362477  02e00000 ################################################################

10290 12:22:48.362609  

10291 12:22:48.892997  02e80000 ################################################################

10292 12:22:48.893135  

10293 12:22:49.427540  02f00000 ################################################################

10294 12:22:49.427694  

10295 12:22:49.972156  02f80000 ################################################################

10296 12:22:49.972319  

10297 12:22:50.090295  03000000 ############### done.

10298 12:22:50.090475  

10299 12:22:50.093227  The bootfile was 50448614 bytes long.

10300 12:22:50.093313  

10301 12:22:50.096547  Sending tftp read request... done.

10302 12:22:50.096655  

10303 12:22:50.100056  Waiting for the transfer... 

10304 12:22:50.100157  

10305 12:22:50.103317  00000000 # done.

10306 12:22:50.103416  

10307 12:22:50.110305  Command line loaded dynamically from TFTP file: 11893139/tftp-deploy-g3sfu_86/kernel/cmdline

10308 12:22:50.110393  

10309 12:22:50.123475  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10310 12:22:50.123564  

10311 12:22:50.123631  Loading FIT.

10312 12:22:50.123726  

10313 12:22:50.126698  Image ramdisk-1 has 39351308 bytes.

10314 12:22:50.126796  

10315 12:22:50.129888  Image fdt-1 has 47278 bytes.

10316 12:22:50.129966  

10317 12:22:50.132873  Image kernel-1 has 11047994 bytes.

10318 12:22:50.132950  

10319 12:22:50.142737  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10320 12:22:50.142841  

10321 12:22:50.159275  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10322 12:22:50.159391  

10323 12:22:50.166505  Choosing best match conf-1 for compat google,spherion-rev2.

10324 12:22:50.166607  

10325 12:22:50.173955  Connected to device vid:did:rid of 1ae0:0028:00

10326 12:22:50.180835  

10327 12:22:50.184157  tpm_get_response: command 0x17b, return code 0x0

10328 12:22:50.184260  

10329 12:22:50.187317  ec_init: CrosEC protocol v3 supported (256, 248)

10330 12:22:50.192153  

10331 12:22:50.195780  tpm_cleanup: add release locality here.

10332 12:22:50.195868  

10333 12:22:50.195931  Shutting down all USB controllers.

10334 12:22:50.198975  

10335 12:22:50.199072  Removing current net device

10336 12:22:50.199162  

10337 12:22:50.205702  Exiting depthcharge with code 4 at timestamp: 91634358

10338 12:22:50.205805  

10339 12:22:50.208625  LZMA decompressing kernel-1 to 0x821a6718

10340 12:22:50.208701  

10341 12:22:50.212163  LZMA decompressing kernel-1 to 0x40000000

10342 12:22:51.600963  

10343 12:22:51.601113  jumping to kernel

10344 12:22:51.601632  end: 2.2.4 bootloader-commands (duration 00:01:04) [common]
10345 12:22:51.601753  start: 2.2.5 auto-login-action (timeout 00:03:21) [common]
10346 12:22:51.601881  Setting prompt string to ['Linux version [0-9]']
10347 12:22:51.601982  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10348 12:22:51.602083  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10349 12:22:51.683284  

10350 12:22:51.686192  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10351 12:22:51.689495  start: 2.2.5.1 login-action (timeout 00:03:21) [common]
10352 12:22:51.689585  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10353 12:22:51.689656  Setting prompt string to []
10354 12:22:51.689752  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10355 12:22:51.689854  Using line separator: #'\n'#
10356 12:22:51.689953  No login prompt set.
10357 12:22:51.690085  Parsing kernel messages
10358 12:22:51.690145  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10359 12:22:51.690250  [login-action] Waiting for messages, (timeout 00:03:21)
10360 12:22:51.709299  [    0.000000] Linux version 6.1.59-cip7 (KernelCI@build-j83005-arm64-gcc-10-defconfig-arm64-chromebook-w8fsm) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023

10361 12:22:51.712618  [    0.000000] random: crng init done

10362 12:22:51.719532  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10363 12:22:51.722745  [    0.000000] efi: UEFI not found.

10364 12:22:51.728940  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10365 12:22:51.735905  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10366 12:22:51.745817  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10367 12:22:51.755633  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10368 12:22:51.761900  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10369 12:22:51.768686  [    0.000000] printk: bootconsole [mtk8250] enabled

10370 12:22:51.775619  [    0.000000] NUMA: No NUMA configuration found

10371 12:22:51.781881  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10372 12:22:51.785420  [    0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]

10373 12:22:51.788602  [    0.000000] Zone ranges:

10374 12:22:51.795502  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10375 12:22:51.798641  [    0.000000]   DMA32    empty

10376 12:22:51.805519  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10377 12:22:51.808490  [    0.000000] Movable zone start for each node

10378 12:22:51.811547  [    0.000000] Early memory node ranges

10379 12:22:51.818401  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10380 12:22:51.824848  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10381 12:22:51.831525  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10382 12:22:51.838381  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10383 12:22:51.841907  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10384 12:22:51.851630  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10385 12:22:51.907105  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10386 12:22:51.913692  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10387 12:22:51.920529  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10388 12:22:51.924147  [    0.000000] psci: probing for conduit method from DT.

10389 12:22:51.930639  [    0.000000] psci: PSCIv1.1 detected in firmware.

10390 12:22:51.933510  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10391 12:22:51.940694  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10392 12:22:51.943332  [    0.000000] psci: SMC Calling Convention v1.2

10393 12:22:51.949900  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10394 12:22:51.953368  [    0.000000] Detected VIPT I-cache on CPU0

10395 12:22:51.960103  [    0.000000] CPU features: detected: GIC system register CPU interface

10396 12:22:51.966762  [    0.000000] CPU features: detected: Virtualization Host Extensions

10397 12:22:51.973467  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10398 12:22:51.979697  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10399 12:22:51.986937  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10400 12:22:51.996527  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10401 12:22:51.999748  [    0.000000] alternatives: applying boot alternatives

10402 12:22:52.006611  [    0.000000] Fallback order for Node 0: 0 

10403 12:22:52.013428  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10404 12:22:52.016399  [    0.000000] Policy zone: Normal

10405 12:22:52.029561  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10406 12:22:52.039353  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10407 12:22:52.051440  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10408 12:22:52.061470  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10409 12:22:52.068611  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10410 12:22:52.071142  <6>[    0.000000] software IO TLB: area num 8.

10411 12:22:52.128394  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10412 12:22:52.276893  <6>[    0.000000] Memory: 7931060K/8385536K available (17984K kernel code, 4114K rwdata, 17472K rodata, 8384K init, 615K bss, 421708K reserved, 32768K cma-reserved)

10413 12:22:52.283912  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10414 12:22:52.290396  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10415 12:22:52.293459  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10416 12:22:52.299954  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10417 12:22:52.306680  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10418 12:22:52.310384  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10419 12:22:52.319769  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10420 12:22:52.326627  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10421 12:22:52.333252  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10422 12:22:52.339813  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10423 12:22:52.343165  <6>[    0.000000] GICv3: 608 SPIs implemented

10424 12:22:52.346558  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10425 12:22:52.352933  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10426 12:22:52.356685  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10427 12:22:52.363254  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10428 12:22:52.376380  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10429 12:22:52.389625  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10430 12:22:52.396123  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10431 12:22:52.404026  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10432 12:22:52.416910  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10433 12:22:52.423516  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10434 12:22:52.430308  <6>[    0.009182] Console: colour dummy device 80x25

10435 12:22:52.439890  <6>[    0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10436 12:22:52.446701  <6>[    0.024349] pid_max: default: 32768 minimum: 301

10437 12:22:52.450248  <6>[    0.029222] LSM: Security Framework initializing

10438 12:22:52.456776  <6>[    0.034190] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10439 12:22:52.466401  <6>[    0.042052] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10440 12:22:52.476588  <6>[    0.051522] cblist_init_generic: Setting adjustable number of callback queues.

10441 12:22:52.479869  <6>[    0.059009] cblist_init_generic: Setting shift to 3 and lim to 1.

10442 12:22:52.489794  <6>[    0.065349] cblist_init_generic: Setting adjustable number of callback queues.

10443 12:22:52.496002  <6>[    0.072775] cblist_init_generic: Setting shift to 3 and lim to 1.

10444 12:22:52.499592  <6>[    0.079178] rcu: Hierarchical SRCU implementation.

10445 12:22:52.506112  <6>[    0.084193] rcu: 	Max phase no-delay instances is 1000.

10446 12:22:52.512696  <6>[    0.091216] EFI services will not be available.

10447 12:22:52.516331  <6>[    0.096176] smp: Bringing up secondary CPUs ...

10448 12:22:52.524845  <6>[    0.101254] Detected VIPT I-cache on CPU1

10449 12:22:52.531414  <6>[    0.101325] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10450 12:22:52.538265  <6>[    0.101356] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10451 12:22:52.541151  <6>[    0.101689] Detected VIPT I-cache on CPU2

10452 12:22:52.547814  <6>[    0.101739] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10453 12:22:52.557704  <6>[    0.101755] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10454 12:22:52.560808  <6>[    0.102015] Detected VIPT I-cache on CPU3

10455 12:22:52.567382  <6>[    0.102061] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10456 12:22:52.574190  <6>[    0.102075] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10457 12:22:52.577511  <6>[    0.102382] CPU features: detected: Spectre-v4

10458 12:22:52.584002  <6>[    0.102389] CPU features: detected: Spectre-BHB

10459 12:22:52.587593  <6>[    0.102394] Detected PIPT I-cache on CPU4

10460 12:22:52.594291  <6>[    0.102450] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10461 12:22:52.600338  <6>[    0.102468] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10462 12:22:52.607054  <6>[    0.102757] Detected PIPT I-cache on CPU5

10463 12:22:52.613710  <6>[    0.102819] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10464 12:22:52.620613  <6>[    0.102836] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10465 12:22:52.623654  <6>[    0.103118] Detected PIPT I-cache on CPU6

10466 12:22:52.630358  <6>[    0.103181] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10467 12:22:52.637003  <6>[    0.103197] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10468 12:22:52.643197  <6>[    0.103493] Detected PIPT I-cache on CPU7

10469 12:22:52.650306  <6>[    0.103558] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10470 12:22:52.656728  <6>[    0.103574] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10471 12:22:52.660017  <6>[    0.103621] smp: Brought up 1 node, 8 CPUs

10472 12:22:52.666604  <6>[    0.244984] SMP: Total of 8 processors activated.

10473 12:22:52.669706  <6>[    0.249935] CPU features: detected: 32-bit EL0 Support

10474 12:22:52.679972  <6>[    0.255298] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10475 12:22:52.686457  <6>[    0.264099] CPU features: detected: Common not Private translations

10476 12:22:52.693166  <6>[    0.270575] CPU features: detected: CRC32 instructions

10477 12:22:52.696633  <6>[    0.275960] CPU features: detected: RCpc load-acquire (LDAPR)

10478 12:22:52.703290  <6>[    0.281920] CPU features: detected: LSE atomic instructions

10479 12:22:52.709489  <6>[    0.287702] CPU features: detected: Privileged Access Never

10480 12:22:52.716083  <6>[    0.293518] CPU features: detected: RAS Extension Support

10481 12:22:52.722864  <6>[    0.299127] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10482 12:22:52.726011  <6>[    0.306391] CPU: All CPU(s) started at EL2

10483 12:22:52.732853  <6>[    0.310708] alternatives: applying system-wide alternatives

10484 12:22:52.742677  <6>[    0.321460] devtmpfs: initialized

10485 12:22:52.757774  <6>[    0.330352] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10486 12:22:52.764547  <6>[    0.340315] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10487 12:22:52.770815  <6>[    0.348283] pinctrl core: initialized pinctrl subsystem

10488 12:22:52.774512  <6>[    0.354963] DMI not present or invalid.

10489 12:22:52.781170  <6>[    0.359369] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10490 12:22:52.790771  <6>[    0.366220] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10491 12:22:52.797478  <6>[    0.373805] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10492 12:22:52.807064  <6>[    0.382013] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10493 12:22:52.810894  <6>[    0.390256] audit: initializing netlink subsys (disabled)

10494 12:22:52.820500  <5>[    0.395949] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1

10495 12:22:52.827392  <6>[    0.396656] thermal_sys: Registered thermal governor 'step_wise'

10496 12:22:52.833819  <6>[    0.403918] thermal_sys: Registered thermal governor 'power_allocator'

10497 12:22:52.837013  <6>[    0.410176] cpuidle: using governor menu

10498 12:22:52.843685  <6>[    0.421139] NET: Registered PF_QIPCRTR protocol family

10499 12:22:52.850398  <6>[    0.426626] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10500 12:22:52.857158  <6>[    0.433730] ASID allocator initialised with 32768 entries

10501 12:22:52.860138  <6>[    0.440304] Serial: AMBA PL011 UART driver

10502 12:22:52.869940  <4>[    0.449094] Trying to register duplicate clock ID: 134

10503 12:22:52.925849  <6>[    0.508300] KASLR enabled

10504 12:22:52.940191  <6>[    0.515966] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10505 12:22:52.946900  <6>[    0.522981] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10506 12:22:52.953752  <6>[    0.529473] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10507 12:22:52.960204  <6>[    0.536480] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10508 12:22:52.966326  <6>[    0.542969] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10509 12:22:52.973072  <6>[    0.549976] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10510 12:22:52.979701  <6>[    0.556466] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10511 12:22:52.986586  <6>[    0.563472] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10512 12:22:52.989705  <6>[    0.570958] ACPI: Interpreter disabled.

10513 12:22:52.998371  <6>[    0.577388] iommu: Default domain type: Translated 

10514 12:22:53.004979  <6>[    0.582544] iommu: DMA domain TLB invalidation policy: strict mode 

10515 12:22:53.008042  <5>[    0.589215] SCSI subsystem initialized

10516 12:22:53.014734  <6>[    0.593479] usbcore: registered new interface driver usbfs

10517 12:22:53.021356  <6>[    0.599211] usbcore: registered new interface driver hub

10518 12:22:53.024873  <6>[    0.604767] usbcore: registered new device driver usb

10519 12:22:53.031448  <6>[    0.610896] pps_core: LinuxPPS API ver. 1 registered

10520 12:22:53.041434  <6>[    0.616092] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10521 12:22:53.045254  <6>[    0.625437] PTP clock support registered

10522 12:22:53.048232  <6>[    0.629678] EDAC MC: Ver: 3.0.0

10523 12:22:53.055647  <6>[    0.634826] FPGA manager framework

10524 12:22:53.062142  <6>[    0.638503] Advanced Linux Sound Architecture Driver Initialized.

10525 12:22:53.065847  <6>[    0.645282] vgaarb: loaded

10526 12:22:53.072411  <6>[    0.648460] clocksource: Switched to clocksource arch_sys_counter

10527 12:22:53.075555  <5>[    0.654919] VFS: Disk quotas dquot_6.6.0

10528 12:22:53.082293  <6>[    0.659106] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10529 12:22:53.085225  <6>[    0.666304] pnp: PnP ACPI: disabled

10530 12:22:53.094249  <6>[    0.673036] NET: Registered PF_INET protocol family

10531 12:22:53.103479  <6>[    0.678630] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10532 12:22:53.115580  <6>[    0.690965] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10533 12:22:53.125304  <6>[    0.699782] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10534 12:22:53.131855  <6>[    0.707752] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10535 12:22:53.138575  <6>[    0.716460] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10536 12:22:53.150894  <6>[    0.726199] TCP: Hash tables configured (established 65536 bind 65536)

10537 12:22:53.157103  <6>[    0.733062] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10538 12:22:53.163347  <6>[    0.740260] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10539 12:22:53.170224  <6>[    0.747960] NET: Registered PF_UNIX/PF_LOCAL protocol family

10540 12:22:53.176565  <6>[    0.754129] RPC: Registered named UNIX socket transport module.

10541 12:22:53.179870  <6>[    0.760285] RPC: Registered udp transport module.

10542 12:22:53.186817  <6>[    0.765221] RPC: Registered tcp transport module.

10543 12:22:53.193352  <6>[    0.770153] RPC: Registered tcp NFSv4.1 backchannel transport module.

10544 12:22:53.196336  <6>[    0.776823] PCI: CLS 0 bytes, default 64

10545 12:22:53.200100  <6>[    0.781249] Unpacking initramfs...

10546 12:22:53.209595  <6>[    0.785415] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10547 12:22:53.219790  <6>[    0.794055] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10548 12:22:53.223242  <6>[    0.802887] kvm [1]: IPA Size Limit: 40 bits

10549 12:22:53.229784  <6>[    0.807418] kvm [1]: GICv3: no GICV resource entry

10550 12:22:53.232684  <6>[    0.812442] kvm [1]: disabling GICv2 emulation

10551 12:22:53.239594  <6>[    0.817129] kvm [1]: GIC system register CPU interface enabled

10552 12:22:53.243210  <6>[    0.823298] kvm [1]: vgic interrupt IRQ18

10553 12:22:53.249455  <6>[    0.828530] kvm [1]: VHE mode initialized successfully

10554 12:22:53.256069  <5>[    0.834760] Initialise system trusted keyrings

10555 12:22:53.262519  <6>[    0.839562] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10556 12:22:53.270295  <6>[    0.849595] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10557 12:22:53.277048  <5>[    0.855985] NFS: Registering the id_resolver key type

10558 12:22:53.280607  <5>[    0.861287] Key type id_resolver registered

10559 12:22:53.286889  <5>[    0.865705] Key type id_legacy registered

10560 12:22:53.293432  <6>[    0.869992] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10561 12:22:53.300784  <6>[    0.876915] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10562 12:22:53.306799  <6>[    0.884625] 9p: Installing v9fs 9p2000 file system support

10563 12:22:53.342904  <5>[    0.921695] Key type asymmetric registered

10564 12:22:53.345948  <5>[    0.926027] Asymmetric key parser 'x509' registered

10565 12:22:53.355875  <6>[    0.931179] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10566 12:22:53.359085  <6>[    0.938796] io scheduler mq-deadline registered

10567 12:22:53.362846  <6>[    0.943557] io scheduler kyber registered

10568 12:22:53.382072  <6>[    0.960980] EINJ: ACPI disabled.

10569 12:22:53.414955  <4>[    0.987086] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10570 12:22:53.424510  <4>[    0.997712] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10571 12:22:53.439304  <6>[    1.018630] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10572 12:22:53.447609  <6>[    1.026623] printk: console [ttyS0] disabled

10573 12:22:53.475379  <6>[    1.051267] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10574 12:22:53.482046  <6>[    1.060767] printk: console [ttyS0] enabled

10575 12:22:53.485034  <6>[    1.060767] printk: console [ttyS0] enabled

10576 12:22:53.491959  <6>[    1.069663] printk: bootconsole [mtk8250] disabled

10577 12:22:53.495022  <6>[    1.069663] printk: bootconsole [mtk8250] disabled

10578 12:22:53.501898  <6>[    1.080978] SuperH (H)SCI(F) driver initialized

10579 12:22:53.505498  <6>[    1.086245] msm_serial: driver initialized

10580 12:22:53.519155  <6>[    1.095273] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10581 12:22:53.529196  <6>[    1.103824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10582 12:22:53.536218  <6>[    1.112365] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10583 12:22:53.545863  <6>[    1.120993] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10584 12:22:53.555949  <6>[    1.129699] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10585 12:22:53.562427  <6>[    1.138420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10586 12:22:53.572415  <6>[    1.146960] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10587 12:22:53.579120  <6>[    1.155777] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10588 12:22:53.588851  <6>[    1.164320] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10589 12:22:53.601406  <6>[    1.180216] loop: module loaded

10590 12:22:53.607671  <6>[    1.186285] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10591 12:22:53.630491  <4>[    1.209832] mtk-pmic-keys: Failed to locate of_node [id: -1]

10592 12:22:53.638021  <6>[    1.216882] megasas: 07.719.03.00-rc1

10593 12:22:53.647536  <6>[    1.226721] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10594 12:22:53.656763  <6>[    1.235937] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10595 12:22:53.673158  <6>[    1.252384] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10596 12:22:53.729562  <6>[    1.302167] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10597 12:22:54.802659  <6>[    2.381703] Freeing initrd memory: 38428K

10598 12:22:54.812577  <6>[    2.391985] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10599 12:22:54.823607  <6>[    2.402910] tun: Universal TUN/TAP device driver, 1.6

10600 12:22:54.827204  <6>[    2.408993] thunder_xcv, ver 1.0

10601 12:22:54.830377  <6>[    2.412498] thunder_bgx, ver 1.0

10602 12:22:54.833511  <6>[    2.415991] nicpf, ver 1.0

10603 12:22:54.844366  <6>[    2.420026] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10604 12:22:54.847651  <6>[    2.427502] hns3: Copyright (c) 2017 Huawei Corporation.

10605 12:22:54.854053  <6>[    2.433091] hclge is initializing

10606 12:22:54.857183  <6>[    2.436665] e1000: Intel(R) PRO/1000 Network Driver

10607 12:22:54.864041  <6>[    2.441795] e1000: Copyright (c) 1999-2006 Intel Corporation.

10608 12:22:54.870033  <6>[    2.447812] e1000e: Intel(R) PRO/1000 Network Driver

10609 12:22:54.873899  <6>[    2.453027] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10610 12:22:54.880491  <6>[    2.459214] igb: Intel(R) Gigabit Ethernet Network Driver

10611 12:22:54.886974  <6>[    2.464865] igb: Copyright (c) 2007-2014 Intel Corporation.

10612 12:22:54.893297  <6>[    2.470702] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10613 12:22:54.900291  <6>[    2.477220] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10614 12:22:54.903854  <6>[    2.483688] sky2: driver version 1.30

10615 12:22:54.909884  <6>[    2.488708] VFIO - User Level meta-driver version: 0.3

10616 12:22:54.917832  <6>[    2.496987] usbcore: registered new interface driver usb-storage

10617 12:22:54.924060  <6>[    2.503433] usbcore: registered new device driver onboard-usb-hub

10618 12:22:54.933146  <6>[    2.512593] mt6397-rtc mt6359-rtc: registered as rtc0

10619 12:22:54.943324  <6>[    2.518055] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-27T12:22:55 UTC (1698409375)

10620 12:22:54.946235  <6>[    2.527627] i2c_dev: i2c /dev entries driver

10621 12:22:54.963684  <6>[    2.539525] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10622 12:22:54.984359  <6>[    2.563521] cpu cpu0: EM: created perf domain

10623 12:22:54.987256  <6>[    2.568447] cpu cpu4: EM: created perf domain

10624 12:22:54.994964  <6>[    2.574081] sdhci: Secure Digital Host Controller Interface driver

10625 12:22:55.001686  <6>[    2.580515] sdhci: Copyright(c) Pierre Ossman

10626 12:22:55.008130  <6>[    2.585470] Synopsys Designware Multimedia Card Interface Driver

10627 12:22:55.014572  <6>[    2.592107] sdhci-pltfm: SDHCI platform and OF driver helper

10628 12:22:55.018141  <6>[    2.592109] mmc0: CQHCI version 5.10

10629 12:22:55.024988  <6>[    2.602233] ledtrig-cpu: registered to indicate activity on CPUs

10630 12:22:55.031511  <6>[    2.609338] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10631 12:22:55.038302  <6>[    2.616396] usbcore: registered new interface driver usbhid

10632 12:22:55.041523  <6>[    2.622221] usbhid: USB HID core driver

10633 12:22:55.048065  <6>[    2.626422] spi_master spi0: will run message pump with realtime priority

10634 12:22:55.096404  <6>[    2.669290] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10635 12:22:55.117048  <6>[    2.685965] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10636 12:22:55.119989  <6>[    2.700069] mmc0: Command Queue Engine enabled

10637 12:22:55.127305  <6>[    2.701655] cros-ec-spi spi0.0: Chrome EC device registered

10638 12:22:55.133845  <6>[    2.704813] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10639 12:22:55.136855  <6>[    2.717912] mmcblk0: mmc0:0001 DA4128 116 GiB 

10640 12:22:55.148685  <6>[    2.724852] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10641 12:22:55.155693  <6>[    2.729156]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10642 12:22:55.162282  <6>[    2.735399] NET: Registered PF_PACKET protocol family

10643 12:22:55.165449  <6>[    2.741456] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10644 12:22:55.171933  <6>[    2.745473] 9pnet: Installing 9P2000 support

10645 12:22:55.174982  <6>[    2.751298] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10646 12:22:55.181673  <5>[    2.755172] Key type dns_resolver registered

10647 12:22:55.188717  <6>[    2.761077] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10648 12:22:55.191747  <6>[    2.765411] registered taskstats version 1

10649 12:22:55.195271  <5>[    2.775780] Loading compiled-in X.509 certificates

10650 12:22:55.225349  <4>[    2.797711] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10651 12:22:55.234907  <4>[    2.808431] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10652 12:22:55.241537  <3>[    2.818959] debugfs: File 'uA_load' in directory '/' already present!

10653 12:22:55.248298  <3>[    2.825657] debugfs: File 'min_uV' in directory '/' already present!

10654 12:22:55.255070  <3>[    2.832264] debugfs: File 'max_uV' in directory '/' already present!

10655 12:22:55.261521  <3>[    2.838927] debugfs: File 'constraint_flags' in directory '/' already present!

10656 12:22:55.272629  <3>[    2.848823] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10657 12:22:55.284999  <6>[    2.864417] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10658 12:22:55.292238  <6>[    2.871322] xhci-mtk 11200000.usb: xHCI Host Controller

10659 12:22:55.298704  <6>[    2.876846] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10660 12:22:55.308484  <6>[    2.884691] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10661 12:22:55.315046  <6>[    2.894103] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10662 12:22:55.321867  <6>[    2.900174] xhci-mtk 11200000.usb: xHCI Host Controller

10663 12:22:55.328240  <6>[    2.905669] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10664 12:22:55.335494  <6>[    2.913320] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10665 12:22:55.342003  <6>[    2.920943] hub 1-0:1.0: USB hub found

10666 12:22:55.345309  <6>[    2.924955] hub 1-0:1.0: 1 port detected

10667 12:22:55.351755  <6>[    2.929206] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10668 12:22:55.358213  <6>[    2.937713] hub 2-0:1.0: USB hub found

10669 12:22:55.361908  <6>[    2.941721] hub 2-0:1.0: 1 port detected

10670 12:22:55.369384  <6>[    2.948562] mtk-msdc 11f70000.mmc: Got CD GPIO

10671 12:22:55.386662  <6>[    2.962568] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10672 12:22:55.393015  <6>[    2.970585] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10673 12:22:55.403328  <4>[    2.978488] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10674 12:22:55.412953  <6>[    2.988036] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10675 12:22:55.419671  <6>[    2.996114] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10676 12:22:55.426344  <6>[    3.004153] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10677 12:22:55.436143  <6>[    3.012075] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10678 12:22:55.442843  <6>[    3.019894] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10679 12:22:55.452464  <6>[    3.027711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10680 12:22:55.462506  <6>[    3.038099] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10681 12:22:55.468816  <6>[    3.046457] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10682 12:22:55.479366  <6>[    3.054801] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10683 12:22:55.485446  <6>[    3.063141] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10684 12:22:55.495223  <6>[    3.071479] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10685 12:22:55.505251  <6>[    3.079817] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10686 12:22:55.511991  <6>[    3.088156] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10687 12:22:55.522060  <6>[    3.096495] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10688 12:22:55.528299  <6>[    3.104833] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10689 12:22:55.538199  <6>[    3.113172] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10690 12:22:55.545257  <6>[    3.121510] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10691 12:22:55.555017  <6>[    3.129848] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10692 12:22:55.561377  <6>[    3.138187] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10693 12:22:55.571481  <6>[    3.146526] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10694 12:22:55.578289  <6>[    3.154865] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10695 12:22:55.584540  <6>[    3.163597] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10696 12:22:55.591133  <6>[    3.170765] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10697 12:22:55.598291  <6>[    3.177524] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10698 12:22:55.608127  <6>[    3.184281] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10699 12:22:55.614825  <6>[    3.191212] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10700 12:22:55.621833  <6>[    3.198069] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10701 12:22:55.631097  <6>[    3.207203] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10702 12:22:55.641091  <6>[    3.216323] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10703 12:22:55.651035  <6>[    3.225618] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10704 12:22:55.660847  <6>[    3.235086] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10705 12:22:55.667751  <6>[    3.244555] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10706 12:22:55.677812  <6>[    3.253698] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10707 12:22:55.687779  <6>[    3.263165] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10708 12:22:55.697537  <6>[    3.272285] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10709 12:22:55.707542  <6>[    3.281579] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10710 12:22:55.717307  <6>[    3.291739] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10711 12:22:55.727125  <6>[    3.303278] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10712 12:22:55.752782  <6>[    3.328763] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10713 12:22:55.780143  <6>[    3.359455] hub 2-1:1.0: USB hub found

10714 12:22:55.783362  <6>[    3.363887] hub 2-1:1.0: 3 ports detected

10715 12:22:55.904934  <6>[    3.480730] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10716 12:22:56.059271  <6>[    3.638744] hub 1-1:1.0: USB hub found

10717 12:22:56.062577  <6>[    3.643248] hub 1-1:1.0: 4 ports detected

10718 12:22:56.137247  <6>[    3.713063] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10719 12:22:56.384853  <6>[    3.960852] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10720 12:22:56.517171  <6>[    4.096606] hub 1-1.4:1.0: USB hub found

10721 12:22:56.520416  <6>[    4.101274] hub 1-1.4:1.0: 2 ports detected

10722 12:22:56.816383  <6>[    4.392784] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10723 12:22:57.008732  <6>[    4.584804] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10724 12:23:08.021538  <6>[   15.605754] ALSA device list:

10725 12:23:08.027829  <6>[   15.609049]   No soundcards found.

10726 12:23:08.036322  <6>[   15.617061] Freeing unused kernel memory: 8384K

10727 12:23:08.039321  <6>[   15.622049] Run /init as init process

10728 12:23:08.087181  <6>[   15.667988] NET: Registered PF_INET6 protocol family

10729 12:23:08.093804  <6>[   15.674434] Segment Routing with IPv6

10730 12:23:08.096925  <6>[   15.678384] In-situ OAM (IOAM) with IPv6

10731 12:23:08.131812  <30>[   15.692667] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10732 12:23:08.134739  <30>[   15.716587] systemd[1]: Detected architecture arm64.

10733 12:23:08.134823  

10734 12:23:08.141360  Welcome to Debian GNU/Linux 11 (bullseye)!

10735 12:23:08.141449  

10736 12:23:08.156438  <30>[   15.736811] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10737 12:23:08.293789  <30>[   15.871593] systemd[1]: Queued start job for default target Graphical Interface.

10738 12:23:08.328658  <30>[   15.909495] systemd[1]: Created slice system-getty.slice.

10739 12:23:08.335324  [  OK  ] Created slice system-getty.slice.

10740 12:23:08.352174  <30>[   15.933125] systemd[1]: Created slice system-modprobe.slice.

10741 12:23:08.358817  [  OK  ] Created slice system-modprobe.slice.

10742 12:23:08.379585  <30>[   15.957425] systemd[1]: Created slice system-serial\x2dgetty.slice.

10743 12:23:08.386355  [  OK  ] Created slice system-serial\x2dgetty.slice.

10744 12:23:08.400745  <30>[   15.981373] systemd[1]: Created slice User and Session Slice.

10745 12:23:08.407569  [  OK  ] Created slice User and Session Slice.

10746 12:23:08.428234  <30>[   16.005354] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10747 12:23:08.437539  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10748 12:23:08.455820  <30>[   16.033377] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10749 12:23:08.462478  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10750 12:23:08.486547  <30>[   16.060781] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10751 12:23:08.492999  <30>[   16.072925] systemd[1]: Reached target Local Encrypted Volumes.

10752 12:23:08.499674  [  OK  ] Reached target Local Encrypted Volumes.

10753 12:23:08.516648  <30>[   16.097273] systemd[1]: Reached target Paths.

10754 12:23:08.520191  [  OK  ] Reached target Paths.

10755 12:23:08.536009  <30>[   16.116723] systemd[1]: Reached target Remote File Systems.

10756 12:23:08.542621  [  OK  ] Reached target Remote File Systems.

10757 12:23:08.555979  <30>[   16.136693] systemd[1]: Reached target Slices.

10758 12:23:08.559166  [  OK  ] Reached target Slices.

10759 12:23:08.576087  <30>[   16.156717] systemd[1]: Reached target Swap.

10760 12:23:08.579113  [  OK  ] Reached target Swap.

10761 12:23:08.600021  <30>[   16.177175] systemd[1]: Listening on initctl Compatibility Named Pipe.

10762 12:23:08.606576  [  OK  ] Listening on initctl Compatibility Named Pipe.

10763 12:23:08.621487  <30>[   16.202156] systemd[1]: Listening on Journal Audit Socket.

10764 12:23:08.627850  [  OK  ] Listening on Journal Audit Socket.

10765 12:23:08.644909  <30>[   16.225826] systemd[1]: Listening on Journal Socket (/dev/log).

10766 12:23:08.651715  [  OK  ] Listening on Journal Socket (/dev/log).

10767 12:23:08.669181  <30>[   16.249884] systemd[1]: Listening on Journal Socket.

10768 12:23:08.675678  [  OK  ] Listening on Journal Socket.

10769 12:23:08.691963  <30>[   16.269393] systemd[1]: Listening on Network Service Netlink Socket.

10770 12:23:08.698236  [  OK  ] Listening on Network Service Netlink Socket.

10771 12:23:08.713310  <30>[   16.293944] systemd[1]: Listening on udev Control Socket.

10772 12:23:08.719361  [  OK  ] Listening on udev Control Socket.

10773 12:23:08.736699  <30>[   16.317741] systemd[1]: Listening on udev Kernel Socket.

10774 12:23:08.743349  [  OK  ] Listening on udev Kernel Socket.

10775 12:23:08.796162  <30>[   16.376926] systemd[1]: Mounting Huge Pages File System...

10776 12:23:08.802943           Mounting Huge Pages File System...

10777 12:23:08.819531  <30>[   16.400364] systemd[1]: Mounting POSIX Message Queue File System...

10778 12:23:08.826178           Mounting POSIX Message Queue File System...

10779 12:23:08.864070  <30>[   16.444805] systemd[1]: Mounting Kernel Debug File System...

10780 12:23:08.870636           Mounting Kernel Debug File System...

10781 12:23:08.887342  <30>[   16.465170] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10782 12:23:08.900325  <30>[   16.477972] systemd[1]: Starting Create list of static device nodes for the current kernel...

10783 12:23:08.907238           Starting Create list of st…odes for the current kernel...

10784 12:23:08.936991  <30>[   16.517014] systemd[1]: Starting Load Kernel Module configfs...

10785 12:23:08.943131           Starting Load Kernel Module configfs...

10786 12:23:08.959638  <30>[   16.540728] systemd[1]: Starting Load Kernel Module drm...

10787 12:23:08.966834           Starting Load Kernel Module drm...

10788 12:23:08.983309  <30>[   16.561017] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10789 12:23:09.032402  <30>[   16.613250] systemd[1]: Starting Journal Service...

10790 12:23:09.035997           Starting Journal Service...

10791 12:23:09.054990  <30>[   16.635778] systemd[1]: Starting Load Kernel Modules...

10792 12:23:09.061640           Starting Load Kernel Modules...

10793 12:23:09.081408  <30>[   16.659182] systemd[1]: Starting Remount Root and Kernel File Systems...

10794 12:23:09.088505           Starting Remount Root and Kernel File Systems...

10795 12:23:09.104013  <30>[   16.684429] systemd[1]: Starting Coldplug All udev Devices...

10796 12:23:09.110465           Starting Coldplug All udev Devices...

10797 12:23:09.127757  <30>[   16.708667] systemd[1]: Started Journal Service.

10798 12:23:09.134293  [  OK  ] Started Journal Service.

10799 12:23:09.152072  [  OK  ] Mounted Huge Pages File System.

10800 12:23:09.168837  [  OK  ] Mounted POSIX Message Queue File System.

10801 12:23:09.185647  [  OK  ] Mounted Kernel Debug File System.

10802 12:23:09.205118  [  OK  ] Finished Create list of st… nodes for the current kernel.

10803 12:23:09.222594  [  OK  ] Finished Load Kernel Module configfs.

10804 12:23:09.246321  [  OK  ] Finished Load Kernel Module drm.

10805 12:23:09.266014  [  OK  ] Finished Load Kernel Modules.

10806 12:23:09.285899  [FAILED] Failed to start Remount Root and Kernel File Systems.

10807 12:23:09.300628  See 'systemctl status systemd-remount-fs.service' for details.

10808 12:23:09.348497           Mounting Kernel Configuration File System...

10809 12:23:09.372131           Starting Flush Journal to Persistent Storage...

10810 12:23:09.394163  <46>[   16.971550] systemd-journald[190]: Received client request to flush runtime journal.

10811 12:23:09.400483           Starting Load/Save Random Seed...

10812 12:23:09.457198           Starting Apply Kernel Variables...

10813 12:23:09.479677           Starting Create System Users...

10814 12:23:09.499327  [  OK  ] Finished Coldplug All udev Devices.

10815 12:23:09.520726  [  OK  ] Mounted Kernel Configuration File System.

10816 12:23:09.540997  [  OK  ] Finished Flush Journal to Persistent Storage.

10817 12:23:09.557470  [  OK  ] Finished Load/Save Random Seed.

10818 12:23:09.573878  [  OK  ] Finished Apply Kernel Variables.

10819 12:23:09.589489  [  OK  ] Finished Create System Users.

10820 12:23:09.645259           Starting Create Static Device Nodes in /dev...

10821 12:23:09.672163  [  OK  ] Finished Create Static Device Nodes in /dev.

10822 12:23:09.684359  [  OK  ] Reached target Local File Systems (Pre).

10823 12:23:09.700160  [  OK  ] Reached target Local File Systems.

10824 12:23:09.740747           Starting Create Volatile Files and Directories...

10825 12:23:09.767721           Starting Rule-based Manage…for Device Events and Files...

10826 12:23:09.786247  [  OK  ] Finished Create Volatile Files and Directories.

10827 12:23:09.805805  [  OK  ] Started Rule-based Manager for Device Events and Files.

10828 12:23:09.863295           Starting Network Service...

10829 12:23:09.896164           Starting Network Time Synchronization...

10830 12:23:09.917862           Starting Update UTMP about System Boot/Shutdown...

10831 12:23:09.938973  [  OK  ] Started Network Service.

10832 12:23:09.951894  <6>[   17.529821] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10833 12:23:09.961917  <6>[   17.537924] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10834 12:23:09.969001  <6>[   17.546706] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10835 12:23:09.975252  <6>[   17.554220] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10836 12:23:09.988368  <3>[   17.566096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10837 12:23:09.994990  <6>[   17.569015] remoteproc remoteproc0: scp is available

10838 12:23:10.002026  <3>[   17.575014] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10839 12:23:10.008377  <6>[   17.579973] remoteproc remoteproc0: powering up scp

10840 12:23:10.015198  <3>[   17.588035] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10841 12:23:10.021710  <6>[   17.592844] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10842 12:23:10.031871  <4>[   17.594513] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10843 12:23:10.038807  <4>[   17.594922] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10844 12:23:10.045039  <6>[   17.623938] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10845 12:23:10.048356  <6>[   17.626649] mc: Linux media interface: v0.10

10846 12:23:10.058717  [  OK  [<3>[   17.632346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10847 12:23:10.068767  0m] Finished [0<3>[   17.643852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10848 12:23:10.074766  ;1;39mUpdate UTM<6>[   17.651975] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10849 12:23:10.084894  <3>[   17.653431] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10850 12:23:10.091672  P about System B<6>[   17.654896] videodev: Linux video capture interface: v2.00

10851 12:23:10.097941  <6>[   17.666347] usbcore: registered new interface driver r8152

10852 12:23:10.107963  oot/Shutdown<3>[   17.671058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10853 12:23:10.108210  .

10854 12:23:10.114188  <4>[   17.675908] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10855 12:23:10.121086  <4>[   17.675908] Fallback method does not support PEC.

10856 12:23:10.127718  <6>[   17.679235] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10857 12:23:10.134345  <3>[   17.683176] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10858 12:23:10.144077  <3>[   17.683529] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10859 12:23:10.151011  <6>[   17.693169] pci_bus 0000:00: root bus resource [bus 00-ff]

10860 12:23:10.157392  <3>[   17.707245] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10861 12:23:10.164023  <6>[   17.713519] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10862 12:23:10.173637  <6>[   17.713531] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10863 12:23:10.180366  <6>[   17.713653] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10864 12:23:10.190322  <6>[   17.716712] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10865 12:23:10.200507  <6>[   17.718770] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3

10866 12:23:10.207613  <3>[   17.721760] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10867 12:23:10.217106  <6>[   17.722173] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2

10868 12:23:10.224645  <6>[   17.729971] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10869 12:23:10.234187  <3>[   17.736494] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10870 12:23:10.237608  <6>[   17.743758] pci 0000:00:00.0: supports D1 D2

10871 12:23:10.244271  <3>[   17.751363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10872 12:23:10.254489  <6>[   17.755363] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10873 12:23:10.261455  <6>[   17.761650] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10874 12:23:10.268060  <6>[   17.761817] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10875 12:23:10.277307  <6>[   17.763293] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10876 12:23:10.284504  <6>[   17.763907] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10877 12:23:10.290807  <6>[   17.763941] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10878 12:23:10.297830  <6>[   17.763962] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10879 12:23:10.304299  <6>[   17.763980] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10880 12:23:10.308349  <6>[   17.764103] pci 0000:01:00.0: supports D1 D2

10881 12:23:10.317945  <6>[   17.764107] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10882 12:23:10.322243  <6>[   17.765035] Bluetooth: Core ver 2.22

10883 12:23:10.325328  <6>[   17.765109] NET: Registered PF_BLUETOOTH protocol family

10884 12:23:10.331951  <6>[   17.765111] Bluetooth: HCI device and connection manager initialized

10885 12:23:10.338574  <6>[   17.765129] Bluetooth: HCI socket layer initialized

10886 12:23:10.342183  <6>[   17.765137] Bluetooth: L2CAP socket layer initialized

10887 12:23:10.348849  <6>[   17.765145] Bluetooth: SCO socket layer initialized

10888 12:23:10.355420  <3>[   17.767019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10889 12:23:10.362229  <6>[   17.777095] remoteproc remoteproc0: remote processor scp is now up

10890 12:23:10.372041  <3>[   17.786384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10891 12:23:10.378418  <6>[   17.786524] usbcore: registered new interface driver cdc_ether

10892 12:23:10.385090  <6>[   17.786576] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10893 12:23:10.391708  <6>[   17.787194] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10894 12:23:10.398544  <6>[   17.787271] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10895 12:23:10.408267  <6>[   17.787278] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10896 12:23:10.414806  <6>[   17.787297] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10897 12:23:10.422008  <6>[   17.787315] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10898 12:23:10.431669  <6>[   17.787332] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10899 12:23:10.434631  <6>[   17.787348] pci 0000:00:00.0: PCI bridge to [bus 01]

10900 12:23:10.444643  <6>[   17.787357] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10901 12:23:10.451503  <6>[   17.789832] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10902 12:23:10.458091  <6>[   17.804036] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10903 12:23:10.468201  <4>[   17.808135] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2

10904 12:23:10.474868  <4>[   17.808146] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)

10905 12:23:10.484323  <3>[   17.810965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10906 12:23:10.491267  <3>[   17.810971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10907 12:23:10.501261  <3>[   17.811016] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10908 12:23:10.507832  <6>[   17.811361] usbcore: registered new interface driver r8153_ecm

10909 12:23:10.514278  <6>[   17.811786] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10910 12:23:10.520572  <3>[   17.813219] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10911 12:23:10.534165  <6>[   17.814284] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10912 12:23:10.540547  <6>[   17.814436] usbcore: registered new interface driver uvcvideo

10913 12:23:10.547053  <6>[   17.823613] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10914 12:23:10.553951  <6>[   17.825398] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

10915 12:23:10.560483  <6>[   17.825588] pcieport 0000:00:00.0: AER: enabled with IRQ 282

10916 12:23:10.567272  <6>[   17.833251] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10917 12:23:10.574235  <6>[   17.841058] usbcore: registered new interface driver btusb

10918 12:23:10.584063  <4>[   17.842049] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10919 12:23:10.590070  <3>[   17.842076] Bluetooth: hci0: Failed to load firmware file (-2)

10920 12:23:10.597000  <3>[   17.842081] Bluetooth: hci0: Failed to set up firmware (-2)

10921 12:23:10.606695  <4>[   17.842091] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10922 12:23:10.613334  <5>[   17.848991] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10923 12:23:10.616838  <6>[   17.860704] r8152 2-1.3:1.0 eth0: v1.12.13

10924 12:23:10.623294  <5>[   17.874205] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10925 12:23:10.630027  <6>[   17.882589] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0

10926 12:23:10.640052  <3>[   17.919092] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10927 12:23:10.649930  <3>[   17.919810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6

10928 12:23:10.656986  [  OK  ] Started Network Time Synchronization.

10929 12:23:10.668686  <4>[   18.245288] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10930 12:23:10.674991  <6>[   18.254301] cfg80211: failed to load regulatory.db

10931 12:23:10.686261  <3>[   18.263790] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10932 12:23:10.696252  <3>[   18.264720] power_supply sbs-5-000b: driver failed to report `capacity' property: -6

10933 12:23:10.699914  [  OK  ] Found device /dev/ttyS0.

10934 12:23:10.715193  <6>[   18.292119] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10935 12:23:10.718751  <6>[   18.299705] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10936 12:23:10.729303  <3>[   18.306672] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10937 12:23:10.745850  <6>[   18.326346] mt7921e 0000:01:00.0: ASIC revision: 79610010

10938 12:23:10.758750  <3>[   18.336055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10939 12:23:10.788457  <3>[   18.366295] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10940 12:23:10.819606  <3>[   18.397012] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10941 12:23:10.831654  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10942 12:23:10.838699  [  OK  ] Reached target Bluetooth.

10943 12:23:10.852997  <4>[   18.426262] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10944 12:23:10.862991  [  OK  ] Reached targ<3>[   18.440233] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10945 12:23:10.866326  et System Time Set.

10946 12:23:10.884336  [  OK  ] Reached target System Time Synchronized.

10947 12:23:10.903191  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10948 12:23:10.940707           Starting Load/Save Screen …of leds:white:kbd_backlight...

10949 12:23:10.974286  <4>[   18.548616] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10950 12:23:10.978121           Starting Network Name Resolution...

10951 12:23:11.002402  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10952 12:23:11.017745  [  OK  ] Reached target System Initialization.

10953 12:23:11.036905  [  OK  ] Started Discard unused blocks once a week.

10954 12:23:11.055617  [  OK  ] Started Daily Cleanup of Temporary Directories.

10955 12:23:11.067834  [  OK  ] Reached target Timers.

10956 12:23:11.092531  [  OK  [<4>[   18.667223] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10957 12:23:11.098981  0m] Listening on D-Bus System Message Bus Socket.

10958 12:23:11.113167  [  OK  ] Reached target Sockets.

10959 12:23:11.132364  [  OK  ] Reached target Basic System.

10960 12:23:11.168954  [  OK  ] Started D-Bus System Message Bus.

10961 12:23:11.213560  <4>[   18.787722] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10962 12:23:11.228238           Starting User Login Management...

10963 12:23:11.248818           Starting Load/Save RF Kill Switch Status...

10964 12:23:11.264754  [  OK  ] Started Network Name Resolution.

10965 12:23:11.280949  [  OK  ] Started Load/Save RF Kill Switch Status.

10966 12:23:11.296329  [  OK  ] Reached target Network.

10967 12:23:11.314904  [  OK  ] Reached target Host and Network Name Lookups.

10968 12:23:11.332817  <4>[   18.907112] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10969 12:23:11.369203           Starting Permit User Sessions...

10970 12:23:11.386776  [  OK  ] Finished Permit User Sessions.

10971 12:23:11.393464  [  OK  ] Started User Login Management.

10972 12:23:11.436508  [  OK  ] Started Getty on tty1.

10973 12:23:11.453269  <4>[   19.027450] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10974 12:23:11.498017  [  OK  ] Started Serial Getty on ttyS0.

10975 12:23:11.513532  [  OK  ] Reached target Login Prompts.

10976 12:23:11.528306  [  OK  ] Reached target Multi-User System.

10977 12:23:11.545085  [  OK  ] Reached target Graphical Interface.

10978 12:23:11.573358  <4>[   19.147548] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10979 12:23:11.598137           Starting Update UTMP about System Runlevel Changes...

10980 12:23:11.635802  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10981 12:23:11.678206  

10982 12:23:11.678815  

10983 12:23:11.681849  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10984 12:23:11.682315  

10985 12:23:11.694386  debian-bullseye-arm64 login: root (automat<4>[   19.269752] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10986 12:23:11.697449  ic login)

10987 12:23:11.697904  

10988 12:23:11.698234  

10989 12:23:11.719486  Linux debian-bullseye-arm64 6.1.59-cip7 #1 SMP PREEMPT Fri Oct 27 12:01:33 UTC 2023 aarch64

10990 12:23:11.720040  

10991 12:23:11.726434  The programs included with the Debian GNU/Linux system are free software;

10992 12:23:11.732825  the exact distribution terms for each program are described in the

10993 12:23:11.736109  individual files in /usr/share/doc/*/copyright.

10994 12:23:11.736574  

10995 12:23:11.742376  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

10996 12:23:11.745644  permitted by applicable law.

10997 12:23:11.747221  Matched prompt #10: / #
10999 12:23:11.748475  Setting prompt string to ['/ #']
11000 12:23:11.748953  end: 2.2.5.1 login-action (duration 00:00:20) [common]
11002 12:23:11.750015  end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11003 12:23:11.750487  start: 2.2.6 expect-shell-connection (timeout 00:03:01) [common]
11004 12:23:11.750862  Setting prompt string to ['/ #']
11005 12:23:11.751202  Forcing a shell prompt, looking for ['/ #']
11007 12:23:11.802137  / # 

11008 12:23:11.802798  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11009 12:23:11.803229  Waiting using forced prompt support (timeout 00:02:30)
11010 12:23:11.817596  <4>[   19.391509] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11011 12:23:11.818044  

11012 12:23:11.822616  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11013 12:23:11.823137  start: 2.2.7 export-device-env (timeout 00:03:01) [common]
11014 12:23:11.823683  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11015 12:23:11.824126  end: 2.2 depthcharge-retry (duration 00:01:59) [common]
11016 12:23:11.824556  end: 2 depthcharge-action (duration 00:01:59) [common]
11017 12:23:11.824997  start: 3 lava-test-retry (timeout 00:07:42) [common]
11018 12:23:11.825435  start: 3.1 lava-test-shell (timeout 00:07:42) [common]
11019 12:23:11.825804  Using namespace: common
11021 12:23:11.926874  / # #

11022 12:23:11.927533  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11023 12:23:11.971856  #<4>[   19.511490] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11024 12:23:11.972309  

11025 12:23:11.972703  / # <6>[   19.532871] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready

11026 12:23:11.973330  Using /lava-11893139
11028 12:23:12.074425  <6>[   19.541080] r8152 2-1.3:1.0 enx0024323078ff: carrierexport SHELL=/bin/sh

11029 12:23:12.075234   on

11030 12:23:12.075710  export SHELL=/bin/sh<3>[   19.628840] mt7921e 0000:01:00.0: hardware init failed

11031 12:23:12.081441  

11033 12:23:12.182928  / # . /lava-11893139/environment

11034 12:23:12.189430  . /lava-11893139/environment

11036 12:23:12.291192  / # /lava-11893139/bin/lava-test-runner /lava-11893139/0

11037 12:23:12.291894  Test shell timeout: 10s (minimum of the action and connection timeout)
11038 12:23:12.298252  /lava-11893139/bin/lava-test-runner /lava-11893139/0

11039 12:23:12.322925  + export TESTRUN_ID=0_v4l2-compliance-uvc

11040 12:23:12.325850  + cd /lava-11893139/0/tests/0_v4l2-compliance-uvc

11041 12:23:12.326277  + cat uuid

11042 12:23:12.329320  + UUID=11893139_1.5.2.3.1

11043 12:23:12.329747  + set +x

11044 12:23:12.335919  <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 11893139_1.5.2.3.1>

11045 12:23:12.336664  Received signal: <STARTRUN> 0_v4l2-compliance-uvc 11893139_1.5.2.3.1
11046 12:23:12.337060  Starting test lava.0_v4l2-compliance-uvc (11893139_1.5.2.3.1)
11047 12:23:12.337484  Skipping test definition patterns.
11048 12:23:12.339141  + /usr/bin/v4l2-parser.sh -d uvcvideo

11049 12:23:12.345616  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>

11050 12:23:12.346039  device: /dev/video0

11051 12:23:12.346620  Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11053 12:23:18.964219  v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t

11054 12:23:18.977475  v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27

11055 12:23:18.988425  

11056 12:23:19.006803  Compliance test for uvcvideo device /dev/video0:

11057 12:23:19.014308  

11058 12:23:19.029886  Driver Info:

11059 12:23:19.041215  	Driver name      : uvcvideo

11060 12:23:19.055251  	Card type        : HD User Facing: HD User Facing

11061 12:23:19.064483  	Bus info         : usb-11200000.usb-1.4.1

11062 12:23:19.073147  	Driver version   : 6.1.59

11063 12:23:19.085700  	Capabilities     : 0x84a00001

11064 12:23:19.101958  		Metadata Capture

11065 12:23:19.114986  		Streaming

11066 12:23:19.125549  		Extended Pix Format

11067 12:23:19.137201  		Device Capabilities

11068 12:23:19.149019  	Device Caps      : 0x04200001

11069 12:23:19.167994  		Streaming

11070 12:23:19.178234  		Extended Pix Format

11071 12:23:19.193293  Media Driver Info:

11072 12:23:19.204247  	Driver name      : uvcvideo

11073 12:23:19.216573  	Model            : HD User Facing: HD User Facing

11074 12:23:19.225074  	Serial           : 200901010001

11075 12:23:19.240960  	Bus info         : usb-11200000.usb-1.4.1

11076 12:23:19.249112  	Media version    : 6.1.59

11077 12:23:19.263567  	Hardware revision: 0x00009758 (38744)

11078 12:23:19.272973  	Driver version   : 6.1.59

11079 12:23:19.285025  Interface Info:

11080 12:23:19.304176  <LAVA_SIGNAL_TESTSET START Interface-Info>

11081 12:23:19.304267  	ID               : 0x03000002

11082 12:23:19.304510  Received signal: <TESTSET> START Interface-Info
11083 12:23:19.304585  Starting test_set Interface-Info
11084 12:23:19.315785  	Type             : V4L Video

11085 12:23:19.326669  Entity Info:

11086 12:23:19.333361  <LAVA_SIGNAL_TESTSET STOP>

11087 12:23:19.333651  Received signal: <TESTSET> STOP
11088 12:23:19.333737  Closing test_set Interface-Info
11089 12:23:19.342964  <LAVA_SIGNAL_TESTSET START Entity-Info>

11090 12:23:19.343222  Received signal: <TESTSET> START Entity-Info
11091 12:23:19.343296  Starting test_set Entity-Info
11092 12:23:19.346670  	ID               : 0x00000001 (1)

11093 12:23:19.359933  	Name             : HD User Facing: HD User Facing

11094 12:23:19.366509  	Function         : V4L2 I/O

11095 12:23:19.381119  	Flags            : default

11096 12:23:19.393865  	Pad 0x01000007   : 0: Sink

11097 12:23:19.417307  	  Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable

11098 12:23:19.417409  

11099 12:23:19.432292  Required ioctls:

11100 12:23:19.440520  <LAVA_SIGNAL_TESTSET STOP>

11101 12:23:19.440780  Received signal: <TESTSET> STOP
11102 12:23:19.440854  Closing test_set Entity-Info
11103 12:23:19.450258  <LAVA_SIGNAL_TESTSET START Required-ioctls>

11104 12:23:19.450515  Received signal: <TESTSET> START Required-ioctls
11105 12:23:19.450589  Starting test_set Required-ioctls
11106 12:23:19.453769  	test MC information (see 'Media Driver Info' above): OK

11107 12:23:19.480311  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>

11108 12:23:19.480578  Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11110 12:23:19.483275  	test VIDIOC_QUERYCAP: OK

11111 12:23:19.504321  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>

11112 12:23:19.504582  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11114 12:23:19.507611  	test invalid ioctls: OK

11115 12:23:19.535880  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>

11116 12:23:19.535987  

11117 12:23:19.536247  Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11119 12:23:19.545009  Allow for multiple opens:

11120 12:23:19.553042  <LAVA_SIGNAL_TESTSET STOP>

11121 12:23:19.553299  Received signal: <TESTSET> STOP
11122 12:23:19.553373  Closing test_set Required-ioctls
11123 12:23:19.563517  <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>

11124 12:23:19.563776  Received signal: <TESTSET> START Allow-for-multiple-opens
11125 12:23:19.563852  Starting test_set Allow-for-multiple-opens
11126 12:23:19.566198  	test second /dev/video0 open: OK

11127 12:23:19.587722  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>

11128 12:23:19.587985  Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11130 12:23:19.591314  	test VIDIOC_QUERYCAP: OK

11131 12:23:19.612158  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>

11132 12:23:19.612419  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11134 12:23:19.615596  	test VIDIOC_G/S_PRIORITY: OK

11135 12:23:19.637804  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>

11136 12:23:19.638094  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11138 12:23:19.641469  	test for unlimited opens: OK

11139 12:23:19.664172  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>

11140 12:23:19.664269  

11141 12:23:19.664527  Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11143 12:23:19.675744  Debug ioctls:

11144 12:23:19.682144  <LAVA_SIGNAL_TESTSET STOP>

11145 12:23:19.682404  Received signal: <TESTSET> STOP
11146 12:23:19.682505  Closing test_set Allow-for-multiple-opens
11147 12:23:19.692147  <LAVA_SIGNAL_TESTSET START Debug-ioctls>

11148 12:23:19.692405  Received signal: <TESTSET> START Debug-ioctls
11149 12:23:19.692481  Starting test_set Debug-ioctls
11150 12:23:19.694996  	test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)

11151 12:23:19.720320  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>

11152 12:23:19.720580  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11154 12:23:19.727034  	test VIDIOC_LOG_STATUS: OK (Not Supported)

11155 12:23:19.748463  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>

11156 12:23:19.748549  

11157 12:23:19.748784  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11159 12:23:19.757604  Input ioctls:

11160 12:23:19.765677  <LAVA_SIGNAL_TESTSET STOP>

11161 12:23:19.765932  Received signal: <TESTSET> STOP
11162 12:23:19.766001  Closing test_set Debug-ioctls
11163 12:23:19.774793  <LAVA_SIGNAL_TESTSET START Input-ioctls>

11164 12:23:19.775049  Received signal: <TESTSET> START Input-ioctls
11165 12:23:19.775118  Starting test_set Input-ioctls
11166 12:23:19.778220  	test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)

11167 12:23:19.804204  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>

11168 12:23:19.804475  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11170 12:23:19.807625  	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)

11171 12:23:19.828635  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>

11172 12:23:19.828896  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11174 12:23:19.835585  	test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)

11175 12:23:19.855536  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>

11176 12:23:19.855794  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11178 12:23:19.861887  	test VIDIOC_ENUMAUDIO: OK (Not Supported)

11179 12:23:19.881543  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>

11180 12:23:19.881806  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11182 12:23:19.884630  	test VIDIOC_G/S/ENUMINPUT: OK

11183 12:23:19.907507  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>

11184 12:23:19.907773  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11186 12:23:19.910992  	test VIDIOC_G/S_AUDIO: OK (Not Supported)

11187 12:23:19.933567  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>

11188 12:23:19.933832  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11190 12:23:19.936923  	Inputs: 1 Audio Inputs: 0 Tuners: 0

11191 12:23:19.944563  

11192 12:23:19.962264  	test VIDIOC_G/S_MODULATOR: OK (Not Supported)

11193 12:23:19.985556  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>

11194 12:23:19.985819  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11196 12:23:19.992068  	test VIDIOC_G/S_FREQUENCY: OK (Not Supported)

11197 12:23:20.012592  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>

11198 12:23:20.012856  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11200 12:23:20.015421  	test VIDIOC_ENUMAUDOUT: OK (Not Supported)

11201 12:23:20.035601  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>

11202 12:23:20.035891  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11204 12:23:20.042357  	test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)

11205 12:23:20.061884  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>

11206 12:23:20.062147  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11208 12:23:20.068261  	test VIDIOC_G/S_AUDOUT: OK (Not Supported)

11209 12:23:20.091488  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>

11210 12:23:20.091606  

11211 12:23:20.091873  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11213 12:23:20.110223  	test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)

11214 12:23:20.131926  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>

11215 12:23:20.132196  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11217 12:23:20.138300  	test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)

11218 12:23:20.164914  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>

11219 12:23:20.165185  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11221 12:23:20.167822  	test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)

11222 12:23:20.187885  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>

11223 12:23:20.188142  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11225 12:23:20.191692  	test VIDIOC_G/S_EDID: OK (Not Supported)

11226 12:23:20.212906  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>

11227 12:23:20.213001  

11228 12:23:20.213236  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11230 12:23:20.224010  Control ioctls (Input 0):

11231 12:23:20.231907  <LAVA_SIGNAL_TESTSET STOP>

11232 12:23:20.232160  Received signal: <TESTSET> STOP
11233 12:23:20.232228  Closing test_set Input-ioctls
11234 12:23:20.241709  <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>

11235 12:23:20.241964  Received signal: <TESTSET> START Control-ioctls-Input-0
11236 12:23:20.242032  Starting test_set Control-ioctls-Input-0
11237 12:23:20.244660  	test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK

11238 12:23:20.271295  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>

11239 12:23:20.271482  	test VIDIOC_QUERYCTRL: OK

11240 12:23:20.271734  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11242 12:23:20.292668  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>

11243 12:23:20.292937  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11245 12:23:20.296210  	test VIDIOC_G/S_CTRL: OK

11246 12:23:20.317457  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>

11247 12:23:20.317763  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11249 12:23:20.320799  	test VIDIOC_G/S/TRY_EXT_CTRLS: OK

11250 12:23:20.343762  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>

11251 12:23:20.344037  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11253 12:23:20.350406  	test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK

11254 12:23:20.377717  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>

11255 12:23:20.378007  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11257 12:23:20.380992  	test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)

11258 12:23:20.404982  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>

11259 12:23:20.405256  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11261 12:23:20.408023  	Standard Controls: 16 Private Controls: 0

11262 12:23:20.419668  

11263 12:23:20.430896  Format ioctls (Input 0):

11264 12:23:20.438406  <LAVA_SIGNAL_TESTSET STOP>

11265 12:23:20.438669  Received signal: <TESTSET> STOP
11266 12:23:20.438739  Closing test_set Control-ioctls-Input-0
11267 12:23:20.447903  <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>

11268 12:23:20.448162  Received signal: <TESTSET> START Format-ioctls-Input-0
11269 12:23:20.448231  Starting test_set Format-ioctls-Input-0
11270 12:23:20.451222  	test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK

11271 12:23:20.474841  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>

11272 12:23:20.475170  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11274 12:23:20.478315  	test VIDIOC_G/S_PARM: OK

11275 12:23:20.497680  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>

11276 12:23:20.497961  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11278 12:23:20.501013  	test VIDIOC_G_FBUF: OK (Not Supported)

11279 12:23:20.523426  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>

11280 12:23:20.523737  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11282 12:23:20.526436  	test VIDIOC_G_FMT: OK

11283 12:23:20.548985  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>

11284 12:23:20.549270  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11286 12:23:20.552229  	test VIDIOC_TRY_FMT: OK

11287 12:23:20.573891  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>

11288 12:23:20.574179  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11290 12:23:20.580385  		warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2

11291 12:23:20.589253  	test VIDIOC_S_FMT: OK

11292 12:23:20.618790  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>

11293 12:23:20.619095  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11295 12:23:20.622208  	test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)

11296 12:23:20.644319  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>

11297 12:23:20.644608  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11299 12:23:20.647173  	test Cropping: OK (Not Supported)

11300 12:23:20.669365  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>

11301 12:23:20.669652  Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11303 12:23:20.672349  	test Composing: OK (Not Supported)

11304 12:23:20.701405  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>

11305 12:23:20.701690  Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11307 12:23:20.704164  	test Scaling: OK (Not Supported)

11308 12:23:20.728810  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>

11309 12:23:20.728916  

11310 12:23:20.729154  Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11312 12:23:20.740817  Codec ioctls (Input 0):

11313 12:23:20.748024  <LAVA_SIGNAL_TESTSET STOP>

11314 12:23:20.748280  Received signal: <TESTSET> STOP
11315 12:23:20.748349  Closing test_set Format-ioctls-Input-0
11316 12:23:20.756913  <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>

11317 12:23:20.757169  Received signal: <TESTSET> START Codec-ioctls-Input-0
11318 12:23:20.757238  Starting test_set Codec-ioctls-Input-0
11319 12:23:20.760394  	test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)

11320 12:23:20.782945  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>

11321 12:23:20.783221  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11323 12:23:20.789777  	test VIDIOC_G_ENC_INDEX: OK (Not Supported)

11324 12:23:20.807557  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>

11325 12:23:20.807825  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11327 12:23:20.813935  	test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)

11328 12:23:20.832342  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>

11329 12:23:20.832434  

11330 12:23:20.832674  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11332 12:23:20.842526  Buffer ioctls (Input 0):

11333 12:23:20.850109  <LAVA_SIGNAL_TESTSET STOP>

11334 12:23:20.850365  Received signal: <TESTSET> STOP
11335 12:23:20.850436  Closing test_set Codec-ioctls-Input-0
11336 12:23:20.860081  <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>

11337 12:23:20.860336  Received signal: <TESTSET> START Buffer-ioctls-Input-0
11338 12:23:20.860405  Starting test_set Buffer-ioctls-Input-0
11339 12:23:20.862874  	test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK

11340 12:23:20.889128  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>

11341 12:23:20.889238  	test VIDIOC_EXPBUF: OK

11342 12:23:20.889478  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11344 12:23:20.911323  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>

11345 12:23:20.911631  Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11347 12:23:20.914273  	test Requests: OK (Not Supported)

11348 12:23:20.936862  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>

11349 12:23:20.936961  

11350 12:23:20.937199  Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11352 12:23:20.951664  Test input 0:

11353 12:23:20.961500  

11354 12:23:20.974082  Streaming ioctls:

11355 12:23:20.981717  <LAVA_SIGNAL_TESTSET STOP>

11356 12:23:20.981981  Received signal: <TESTSET> STOP
11357 12:23:20.982052  Closing test_set Buffer-ioctls-Input-0
11358 12:23:20.990931  <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>

11359 12:23:20.991204  Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11360 12:23:20.991277  Starting test_set Streaming-ioctls_Test-input-0
11361 12:23:20.994203  	test read/write: OK (Not Supported)

11362 12:23:21.021325  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>

11363 12:23:21.021616  Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11365 12:23:21.024722  	test blocking wait: OK

11366 12:23:21.046530  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>

11367 12:23:21.046796  Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11369 12:23:21.056805  		fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL

11370 12:23:21.059728  	test MMAP (no poll): FAIL

11371 12:23:21.084787  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>

11372 12:23:21.085070  Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11374 12:23:21.094728  		fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL

11375 12:23:21.098270  	test MMAP (select): FAIL

11376 12:23:21.127594  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>

11377 12:23:21.127895  Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11379 12:23:21.138045  		fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL

11380 12:23:21.140833  	test MMAP (epoll): FAIL

11381 12:23:21.169450  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>

11382 12:23:21.169574  

11383 12:23:21.169815  Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11385 12:23:21.182635  

11386 12:23:21.379270  	                                                  

11387 12:23:21.387750  	test USERPTR (no poll): OK

11388 12:23:21.417581  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>

11389 12:23:21.417688  

11390 12:23:21.417929  Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11392 12:23:21.436402  

11393 12:23:21.622364  	                                                  

11394 12:23:21.629970  	test USERPTR (select): OK

11395 12:23:21.657995  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>

11396 12:23:21.658256  Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11398 12:23:21.664674  	test DMABUF: Cannot test, specify --expbuf-device

11399 12:23:21.668965  

11400 12:23:21.686042  Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3

11401 12:23:21.689330  <LAVA_TEST_RUNNER EXIT>

11402 12:23:21.689583  ok: lava_test_shell seems to have completed
11403 12:23:21.689661  Marking unfinished test run as failed
11405 12:23:21.690578  Composing:
  result: pass
  set: Format-ioctls-Input-0
Cropping:
  result: pass
  set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
  result: pass
  set: Required-ioctls
MMAP-epoll:
  result: fail
  set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
  result: fail
  set: Streaming-ioctls_Test-input-0
MMAP-select:
  result: fail
  set: Streaming-ioctls_Test-input-0
Requests:
  result: pass
  set: Buffer-ioctls-Input-0
Scaling:
  result: pass
  set: Format-ioctls-Input-0
USERPTR-no-poll:
  result: pass
  set: Streaming-ioctls_Test-input-0
USERPTR-select:
  result: pass
  set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
  result: pass
  set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
  result: pass
  set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
  result: pass
  set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
  result: pass
  set: Input-ioctls
VIDIOC_ENUMAUDIO:
  result: pass
  set: Input-ioctls
VIDIOC_ENUMAUDOUT:
  result: pass
  set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
  result: pass
  set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
  result: pass
  set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
  result: pass
  set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
  result: pass
  set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
  result: pass
  set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_AUDOUT:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_CTRL:
  result: pass
  set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
  result: pass
  set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
  result: pass
  set: Input-ioctls
VIDIOC_G/S_PARM:
  result: pass
  set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
  result: pass
  set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
  result: pass
  set: Input-ioctls
VIDIOC_G_ENC_INDEX:
  result: pass
  set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
  result: pass
  set: Format-ioctls-Input-0
VIDIOC_G_FMT:
  result: pass
  set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
  result: pass
  set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
  result: pass
  set: Debug-ioctls
VIDIOC_QUERYCAP:
  result: pass
  set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
  result: pass
  set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
  result: pass
  set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
  result: pass
  set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
  result: pass
  set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
  result: pass
  set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
  result: pass
  set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
  result: pass
  set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
  result: pass
  set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
  result: pass
  set: Control-ioctls-Input-0
blocking-wait:
  result: pass
  set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
  result: pass
  set: Allow-for-multiple-opens
invalid-ioctls:
  result: pass
  set: Required-ioctls
read/write:
  result: pass
  set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
  result: pass
  set: Allow-for-multiple-opens

11406 12:23:21.690700  end: 3.1 lava-test-shell (duration 00:00:10) [common]
11407 12:23:21.690786  end: 3 lava-test-retry (duration 00:00:10) [common]
11408 12:23:21.690874  start: 4 finalize (timeout 00:07:32) [common]
11409 12:23:21.690963  start: 4.1 power-off (timeout 00:00:30) [common]
11410 12:23:21.691113  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11411 12:23:21.766723  >> Command sent successfully.

11412 12:23:21.769120  Returned 0 in 0 seconds
11413 12:23:21.869518  end: 4.1 power-off (duration 00:00:00) [common]
11415 12:23:21.869851  start: 4.2 read-feedback (timeout 00:07:32) [common]
11416 12:23:21.870123  Listened to connection for namespace 'common' for up to 1s
11417 12:23:22.871067  Finalising connection for namespace 'common'
11418 12:23:22.871231  Disconnecting from shell: Finalise
11419 12:23:22.871309  / # 
11420 12:23:22.971656  end: 4.2 read-feedback (duration 00:00:01) [common]
11421 12:23:22.971843  end: 4 finalize (duration 00:00:01) [common]
11422 12:23:22.971961  Cleaning after the job
11423 12:23:22.972056  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/ramdisk
11424 12:23:22.977670  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/kernel
11425 12:23:22.993487  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/dtb
11426 12:23:22.993723  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11893139/tftp-deploy-g3sfu_86/modules
11427 12:23:23.001085  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11893139
11428 12:23:23.068388  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11893139
11429 12:23:23.068559  Job finished correctly