Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Warnings: 20
- Kernel Errors: 32
- Errors: 0
- Boot result: PASS
1 19:53:02.639874 lava-dispatcher, installed at version: 2023.08
2 19:53:02.640073 start: 0 validate
3 19:53:02.640205 Start time: 2023-10-28 19:53:02.640196+00:00 (UTC)
4 19:53:02.640346 Using caching service: 'http://localhost/cache/?uri=%s'
5 19:53:02.640477 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 19:53:02.905222 Using caching service: 'http://localhost/cache/?uri=%s'
7 19:53:02.905397 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 19:53:17.904638 Using caching service: 'http://localhost/cache/?uri=%s'
9 19:53:17.904856 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 19:53:18.178591 Using caching service: 'http://localhost/cache/?uri=%s'
11 19:53:18.179257 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.59-cip8-106-g65bd536c294e%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 19:53:22.446040 validate duration: 19.81
14 19:53:22.446315 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:53:22.446412 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:53:22.446501 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:53:22.446636 Not decompressing ramdisk as can be used compressed.
18 19:53:22.446724 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 19:53:22.446791 saving as /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/ramdisk/rootfs.cpio.gz
20 19:53:22.446856 total size: 43284872 (41 MB)
21 19:53:22.447974 progress 0 % (0 MB)
22 19:53:22.459396 progress 5 % (2 MB)
23 19:53:22.470706 progress 10 % (4 MB)
24 19:53:22.481892 progress 15 % (6 MB)
25 19:53:22.493078 progress 20 % (8 MB)
26 19:53:22.504413 progress 25 % (10 MB)
27 19:53:22.516083 progress 30 % (12 MB)
28 19:53:22.527881 progress 35 % (14 MB)
29 19:53:22.539439 progress 40 % (16 MB)
30 19:53:22.550860 progress 45 % (18 MB)
31 19:53:22.562730 progress 50 % (20 MB)
32 19:53:22.574001 progress 55 % (22 MB)
33 19:53:22.585363 progress 60 % (24 MB)
34 19:53:22.596783 progress 65 % (26 MB)
35 19:53:22.608260 progress 70 % (28 MB)
36 19:53:22.620083 progress 75 % (30 MB)
37 19:53:22.631975 progress 80 % (33 MB)
38 19:53:22.643441 progress 85 % (35 MB)
39 19:53:22.654776 progress 90 % (37 MB)
40 19:53:22.665983 progress 95 % (39 MB)
41 19:53:22.677483 progress 100 % (41 MB)
42 19:53:22.677791 41 MB downloaded in 0.23 s (178.76 MB/s)
43 19:53:22.678042 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:53:22.678328 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:53:22.678416 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:53:22.678500 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:53:22.678644 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 19:53:22.678748 saving as /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/kernel/Image
50 19:53:22.678810 total size: 49304064 (47 MB)
51 19:53:22.678871 No compression specified
52 19:53:22.680054 progress 0 % (0 MB)
53 19:53:22.693355 progress 5 % (2 MB)
54 19:53:22.706523 progress 10 % (4 MB)
55 19:53:22.719648 progress 15 % (7 MB)
56 19:53:22.732930 progress 20 % (9 MB)
57 19:53:22.746254 progress 25 % (11 MB)
58 19:53:22.759397 progress 30 % (14 MB)
59 19:53:22.772393 progress 35 % (16 MB)
60 19:53:22.785440 progress 40 % (18 MB)
61 19:53:22.798613 progress 45 % (21 MB)
62 19:53:22.811690 progress 50 % (23 MB)
63 19:53:22.825079 progress 55 % (25 MB)
64 19:53:22.838177 progress 60 % (28 MB)
65 19:53:22.851373 progress 65 % (30 MB)
66 19:53:22.864228 progress 70 % (32 MB)
67 19:53:22.877870 progress 75 % (35 MB)
68 19:53:22.891281 progress 80 % (37 MB)
69 19:53:22.904795 progress 85 % (39 MB)
70 19:53:22.919277 progress 90 % (42 MB)
71 19:53:22.932533 progress 95 % (44 MB)
72 19:53:22.945765 progress 100 % (47 MB)
73 19:53:22.946034 47 MB downloaded in 0.27 s (175.96 MB/s)
74 19:53:22.946193 end: 1.2.1 http-download (duration 00:00:00) [common]
76 19:53:22.946426 end: 1.2 download-retry (duration 00:00:00) [common]
77 19:53:22.946512 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:53:22.946601 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:53:22.946745 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 19:53:22.946815 saving as /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/dtb/mt8192-asurada-spherion-r0.dtb
81 19:53:22.946881 total size: 47278 (0 MB)
82 19:53:22.946943 No compression specified
83 19:53:22.948166 progress 69 % (0 MB)
84 19:53:22.948438 progress 100 % (0 MB)
85 19:53:22.948594 0 MB downloaded in 0.00 s (26.34 MB/s)
86 19:53:22.948715 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:53:22.948935 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:53:22.949018 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:53:22.949099 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:53:22.949247 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.59-cip8-106-g65bd536c294e/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 19:53:22.949334 saving as /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/modules/modules.tar
93 19:53:22.949397 total size: 8635496 (8 MB)
94 19:53:22.949473 Using unxz to decompress xz
95 19:53:22.953844 progress 0 % (0 MB)
96 19:53:22.975719 progress 5 % (0 MB)
97 19:53:22.998238 progress 10 % (0 MB)
98 19:53:23.025066 progress 15 % (1 MB)
99 19:53:23.051051 progress 20 % (1 MB)
100 19:53:23.077247 progress 25 % (2 MB)
101 19:53:23.105878 progress 30 % (2 MB)
102 19:53:23.131489 progress 35 % (2 MB)
103 19:53:23.156987 progress 40 % (3 MB)
104 19:53:23.181631 progress 45 % (3 MB)
105 19:53:23.210001 progress 50 % (4 MB)
106 19:53:23.236229 progress 55 % (4 MB)
107 19:53:23.263310 progress 60 % (4 MB)
108 19:53:23.286634 progress 65 % (5 MB)
109 19:53:23.312134 progress 70 % (5 MB)
110 19:53:23.337106 progress 75 % (6 MB)
111 19:53:23.363990 progress 80 % (6 MB)
112 19:53:23.396799 progress 85 % (7 MB)
113 19:53:23.423186 progress 90 % (7 MB)
114 19:53:23.448092 progress 95 % (7 MB)
115 19:53:23.471750 progress 100 % (8 MB)
116 19:53:23.477425 8 MB downloaded in 0.53 s (15.60 MB/s)
117 19:53:23.477694 end: 1.4.1 http-download (duration 00:00:01) [common]
119 19:53:23.477962 end: 1.4 download-retry (duration 00:00:01) [common]
120 19:53:23.478056 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 19:53:23.478202 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 19:53:23.478342 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:53:23.478433 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 19:53:23.478648 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57
125 19:53:23.478787 makedir: /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin
126 19:53:23.478893 makedir: /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/tests
127 19:53:23.478995 makedir: /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/results
128 19:53:23.479113 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-add-keys
129 19:53:23.479262 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-add-sources
130 19:53:23.479396 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-background-process-start
131 19:53:23.479530 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-background-process-stop
132 19:53:23.479667 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-common-functions
133 19:53:23.479798 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-echo-ipv4
134 19:53:23.479927 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-install-packages
135 19:53:23.480056 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-installed-packages
136 19:53:23.480182 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-os-build
137 19:53:23.480329 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-probe-channel
138 19:53:23.480456 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-probe-ip
139 19:53:23.480582 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-target-ip
140 19:53:23.480707 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-target-mac
141 19:53:23.480833 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-target-storage
142 19:53:23.480963 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-test-case
143 19:53:23.481091 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-test-event
144 19:53:23.481216 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-test-feedback
145 19:53:23.481343 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-test-raise
146 19:53:23.481468 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-test-reference
147 19:53:23.481594 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-test-runner
148 19:53:23.481721 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-test-set
149 19:53:23.481850 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-test-shell
150 19:53:23.481981 Updating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-install-packages (oe)
151 19:53:23.482137 Updating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/bin/lava-installed-packages (oe)
152 19:53:23.482280 Creating /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/environment
153 19:53:23.482392 LAVA metadata
154 19:53:23.482469 - LAVA_JOB_ID=11899565
155 19:53:23.482536 - LAVA_DISPATCHER_IP=192.168.201.1
156 19:53:23.482639 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 19:53:23.482706 skipped lava-vland-overlay
158 19:53:23.482782 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 19:53:23.482866 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 19:53:23.482930 skipped lava-multinode-overlay
161 19:53:23.483007 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 19:53:23.483091 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 19:53:23.483165 Loading test definitions
164 19:53:23.483255 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 19:53:23.483333 Using /lava-11899565 at stage 0
166 19:53:23.483655 uuid=11899565_1.5.2.3.1 testdef=None
167 19:53:23.483745 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 19:53:23.483830 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 19:53:23.484407 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 19:53:23.484690 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 19:53:23.485324 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 19:53:23.485556 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 19:53:23.486156 runner path: /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/0/tests/0_igt-gpu-panfrost test_uuid 11899565_1.5.2.3.1
176 19:53:23.486314 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 19:53:23.486532 Creating lava-test-runner.conf files
179 19:53:23.486596 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11899565/lava-overlay-nymz1o57/lava-11899565/0 for stage 0
180 19:53:23.486687 - 0_igt-gpu-panfrost
181 19:53:23.486785 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 19:53:23.486873 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 19:53:23.493633 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 19:53:23.493752 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 19:53:23.493841 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 19:53:23.493931 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 19:53:23.494033 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 19:53:24.935035 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 19:53:24.935441 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 19:53:24.935553 extracting modules file /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11899565/extract-overlay-ramdisk-m4hnxxsv/ramdisk
191 19:53:25.174613 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 19:53:25.174776 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 19:53:25.174870 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899565/compress-overlay-92qduqk9/overlay-1.5.2.4.tar.gz to ramdisk
194 19:53:25.174939 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11899565/compress-overlay-92qduqk9/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11899565/extract-overlay-ramdisk-m4hnxxsv/ramdisk
195 19:53:25.182077 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 19:53:25.182253 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 19:53:25.182371 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 19:53:25.182482 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 19:53:25.182564 Building ramdisk /var/lib/lava/dispatcher/tmp/11899565/extract-overlay-ramdisk-m4hnxxsv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11899565/extract-overlay-ramdisk-m4hnxxsv/ramdisk
200 19:53:26.392721 >> 369954 blocks
201 19:53:32.335885 rename /var/lib/lava/dispatcher/tmp/11899565/extract-overlay-ramdisk-m4hnxxsv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/ramdisk/ramdisk.cpio.gz
202 19:53:32.336346 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 19:53:32.336474 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 19:53:32.336577 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 19:53:32.336688 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/kernel/Image'
206 19:53:45.812977 Returned 0 in 13 seconds
207 19:53:45.913646 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/kernel/image.itb
208 19:53:46.775493 output: FIT description: Kernel Image image with one or more FDT blobs
209 19:53:46.775924 output: Created: Sat Oct 28 20:53:46 2023
210 19:53:46.776005 output: Image 0 (kernel-1)
211 19:53:46.776071 output: Description:
212 19:53:46.776134 output: Created: Sat Oct 28 20:53:46 2023
213 19:53:46.776193 output: Type: Kernel Image
214 19:53:46.776251 output: Compression: lzma compressed
215 19:53:46.776313 output: Data Size: 11047522 Bytes = 10788.60 KiB = 10.54 MiB
216 19:53:46.776373 output: Architecture: AArch64
217 19:53:46.776431 output: OS: Linux
218 19:53:46.776488 output: Load Address: 0x00000000
219 19:53:46.776546 output: Entry Point: 0x00000000
220 19:53:46.776602 output: Hash algo: crc32
221 19:53:46.776657 output: Hash value: da40eda2
222 19:53:46.776713 output: Image 1 (fdt-1)
223 19:53:46.776768 output: Description: mt8192-asurada-spherion-r0
224 19:53:46.776821 output: Created: Sat Oct 28 20:53:46 2023
225 19:53:46.776874 output: Type: Flat Device Tree
226 19:53:46.776926 output: Compression: uncompressed
227 19:53:46.776979 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 19:53:46.777031 output: Architecture: AArch64
229 19:53:46.777083 output: Hash algo: crc32
230 19:53:46.777135 output: Hash value: cc4352de
231 19:53:46.777188 output: Image 2 (ramdisk-1)
232 19:53:46.777240 output: Description: unavailable
233 19:53:46.777292 output: Created: Sat Oct 28 20:53:46 2023
234 19:53:46.777345 output: Type: RAMDisk Image
235 19:53:46.777397 output: Compression: Unknown Compression
236 19:53:46.777449 output: Data Size: 56428181 Bytes = 55105.65 KiB = 53.81 MiB
237 19:53:46.777501 output: Architecture: AArch64
238 19:53:46.777552 output: OS: Linux
239 19:53:46.777604 output: Load Address: unavailable
240 19:53:46.777656 output: Entry Point: unavailable
241 19:53:46.777707 output: Hash algo: crc32
242 19:53:46.777758 output: Hash value: 7ff57192
243 19:53:46.777810 output: Default Configuration: 'conf-1'
244 19:53:46.777861 output: Configuration 0 (conf-1)
245 19:53:46.777913 output: Description: mt8192-asurada-spherion-r0
246 19:53:46.777964 output: Kernel: kernel-1
247 19:53:46.778016 output: Init Ramdisk: ramdisk-1
248 19:53:46.778068 output: FDT: fdt-1
249 19:53:46.778120 output: Loadables: kernel-1
250 19:53:46.778171 output:
251 19:53:46.778371 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 19:53:46.778474 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 19:53:46.778583 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 19:53:46.778675 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 19:53:46.778749 No LXC device requested
256 19:53:46.778829 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 19:53:46.778916 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 19:53:46.778990 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 19:53:46.779059 Checking files for TFTP limit of 4294967296 bytes.
260 19:53:46.779555 end: 1 tftp-deploy (duration 00:00:24) [common]
261 19:53:46.779699 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 19:53:46.779803 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 19:53:46.779922 substitutions:
264 19:53:46.779992 - {DTB}: 11899565/tftp-deploy-kk2tey4x/dtb/mt8192-asurada-spherion-r0.dtb
265 19:53:46.780058 - {INITRD}: 11899565/tftp-deploy-kk2tey4x/ramdisk/ramdisk.cpio.gz
266 19:53:46.780117 - {KERNEL}: 11899565/tftp-deploy-kk2tey4x/kernel/Image
267 19:53:46.780175 - {LAVA_MAC}: None
268 19:53:46.780232 - {PRESEED_CONFIG}: None
269 19:53:46.780288 - {PRESEED_LOCAL}: None
270 19:53:46.780342 - {RAMDISK}: 11899565/tftp-deploy-kk2tey4x/ramdisk/ramdisk.cpio.gz
271 19:53:46.780397 - {ROOT_PART}: None
272 19:53:46.780450 - {ROOT}: None
273 19:53:46.780503 - {SERVER_IP}: 192.168.201.1
274 19:53:46.780556 - {TEE}: None
275 19:53:46.780609 Parsed boot commands:
276 19:53:46.780662 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 19:53:46.780837 Parsed boot commands: tftpboot 192.168.201.1 11899565/tftp-deploy-kk2tey4x/kernel/image.itb 11899565/tftp-deploy-kk2tey4x/kernel/cmdline
278 19:53:46.780924 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 19:53:46.781009 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 19:53:46.781103 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 19:53:46.781189 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 19:53:46.781261 Not connected, no need to disconnect.
283 19:53:46.781334 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 19:53:46.781413 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 19:53:46.781477 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 19:53:46.785637 Setting prompt string to ['lava-test: # ']
287 19:53:46.786010 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 19:53:46.786128 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 19:53:46.786232 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 19:53:46.786345 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 19:53:46.786614 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 19:53:51.929072 >> Command sent successfully.
293 19:53:51.939563 Returned 0 in 5 seconds
294 19:53:52.040881 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 19:53:52.042387 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 19:53:52.042966 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 19:53:52.043465 Setting prompt string to 'Starting depthcharge on Spherion...'
299 19:53:52.043970 Changing prompt to 'Starting depthcharge on Spherion...'
300 19:53:52.044515 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 19:53:52.045742 [Enter `^Ec?' for help]
302 19:53:52.205936
303 19:53:52.206195
304 19:53:52.206338 F0: 102B 0000
305 19:53:52.206473
306 19:53:52.206600 F3: 1001 0000 [0200]
307 19:53:52.209353
308 19:53:52.209516 F3: 1001 0000
309 19:53:52.209643
310 19:53:52.209762 F7: 102D 0000
311 19:53:52.209874
312 19:53:52.212898 F1: 0000 0000
313 19:53:52.213167
314 19:53:52.213325 V0: 0000 0000 [0001]
315 19:53:52.213476
316 19:53:52.215965 00: 0007 8000
317 19:53:52.216191
318 19:53:52.216359 01: 0000 0000
319 19:53:52.216519
320 19:53:52.219010 BP: 0C00 0209 [0000]
321 19:53:52.219221
322 19:53:52.219390 G0: 1182 0000
323 19:53:52.219547
324 19:53:52.223181 EC: 0000 0021 [4000]
325 19:53:52.223544
326 19:53:52.223861 S7: 0000 0000 [0000]
327 19:53:52.224069
328 19:53:52.226101 CC: 0000 0000 [0001]
329 19:53:52.226359
330 19:53:52.226629 T0: 0000 0040 [010F]
331 19:53:52.226948
332 19:53:52.227197 Jump to BL
333 19:53:52.227432
334 19:53:52.253265
335 19:53:52.253755
336 19:53:52.254118
337 19:53:52.260726 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 19:53:52.264449 ARM64: Exception handlers installed.
339 19:53:52.268030 ARM64: Testing exception
340 19:53:52.271323 ARM64: Done test exception
341 19:53:52.278061 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 19:53:52.288380 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 19:53:52.295632 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 19:53:52.305747 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 19:53:52.311505 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 19:53:52.318329 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 19:53:52.329607 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 19:53:52.336656 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 19:53:52.355751 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 19:53:52.359304 WDT: Last reset was cold boot
351 19:53:52.362701 SPI1(PAD0) initialized at 2873684 Hz
352 19:53:52.366134 SPI5(PAD0) initialized at 992727 Hz
353 19:53:52.369347 VBOOT: Loading verstage.
354 19:53:52.376495 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 19:53:52.380103 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 19:53:52.383270 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 19:53:52.386043 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 19:53:52.393448 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 19:53:52.400090 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 19:53:52.411163 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 19:53:52.411805
362 19:53:52.412377
363 19:53:52.421639 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 19:53:52.425398 ARM64: Exception handlers installed.
365 19:53:52.425825 ARM64: Testing exception
366 19:53:52.428761 ARM64: Done test exception
367 19:53:52.431924 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 19:53:52.438720 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 19:53:52.452251 Probing TPM: . done!
370 19:53:52.452746 TPM ready after 0 ms
371 19:53:52.458984 Connected to device vid:did:rid of 1ae0:0028:00
372 19:53:52.465671 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 19:53:52.525745 Initialized TPM device CR50 revision 0
374 19:53:52.537455 tlcl_send_startup: Startup return code is 0
375 19:53:52.537894 TPM: setup succeeded
376 19:53:52.549327 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 19:53:52.558015 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 19:53:52.569808 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 19:53:52.580177 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 19:53:52.584217 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 19:53:52.587868 in-header: 03 07 00 00 08 00 00 00
382 19:53:52.592061 in-data: aa e4 47 04 13 02 00 00
383 19:53:52.592599 Chrome EC: UHEPI supported
384 19:53:52.598232 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 19:53:52.602439 in-header: 03 95 00 00 08 00 00 00
386 19:53:52.606237 in-data: 18 20 20 08 00 00 00 00
387 19:53:52.606669 Phase 1
388 19:53:52.609751 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 19:53:52.617807 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 19:53:52.625448 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 19:53:52.626029 Recovery requested (1009000e)
392 19:53:52.635319 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 19:53:52.640940 tlcl_extend: response is 0
394 19:53:52.652066 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 19:53:52.655946 tlcl_extend: response is 0
396 19:53:52.663172 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 19:53:52.682226 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 19:53:52.689229 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 19:53:52.689660
400 19:53:52.689998
401 19:53:52.699160 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 19:53:52.702709 ARM64: Exception handlers installed.
403 19:53:52.706093 ARM64: Testing exception
404 19:53:52.706521 ARM64: Done test exception
405 19:53:52.728181 pmic_efuse_setting: Set efuses in 11 msecs
406 19:53:52.731128 pmwrap_interface_init: Select PMIF_VLD_RDY
407 19:53:52.738127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 19:53:52.741640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 19:53:52.745172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 19:53:52.752497 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 19:53:52.756229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 19:53:52.760191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 19:53:52.767683 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 19:53:52.771737 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 19:53:52.775627 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 19:53:52.779325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 19:53:52.786864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 19:53:52.790686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 19:53:52.794123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 19:53:52.801547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 19:53:52.805314 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 19:53:52.812767 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 19:53:52.817005 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 19:53:52.824347 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 19:53:52.828486 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 19:53:52.835724 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 19:53:52.839777 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 19:53:52.847662 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 19:53:52.850921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 19:53:52.858372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 19:53:52.862202 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 19:53:52.869631 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 19:53:52.872921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 19:53:52.876778 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 19:53:52.880672 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 19:53:52.887700 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 19:53:52.891488 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 19:53:52.898519 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 19:53:52.902435 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 19:53:52.905718 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 19:53:52.913154 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 19:53:52.916349 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 19:53:52.920285 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 19:53:52.928774 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 19:53:52.932065 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 19:53:52.935889 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 19:53:52.939936 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 19:53:52.943583 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 19:53:52.947468 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 19:53:52.955264 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 19:53:52.958620 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 19:53:52.962393 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 19:53:52.966175 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 19:53:52.969409 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 19:53:52.973307 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 19:53:52.980364 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 19:53:52.984373 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 19:53:52.991602 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 19:53:52.999722 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 19:53:53.002763 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 19:53:53.010999 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 19:53:53.021944 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 19:53:53.024927 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 19:53:53.029277 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 19:53:53.032279 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 19:53:53.042301 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 19:53:53.045664 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 19:53:53.054159 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 19:53:53.056821 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 19:53:53.065947 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 19:53:53.075509 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 19:53:53.084495 [RTC]rtc_get_frequency_meter,154: input=19, output=849
473 19:53:53.094057 [RTC]rtc_get_frequency_meter,154: input=17, output=804
474 19:53:53.104319 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 19:53:53.113091 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 19:53:53.123782 [RTC]rtc_get_frequency_meter,154: input=17, output=805
477 19:53:53.127288 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 19:53:53.131144 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 19:53:53.135038 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 19:53:53.142527 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 19:53:53.146284 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 19:53:53.149769 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 19:53:53.150467 ADC[4]: Raw value=906203 ID=7
484 19:53:53.154008 ADC[3]: Raw value=213441 ID=1
485 19:53:53.154633 RAM Code: 0x71
486 19:53:53.161457 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 19:53:53.165412 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 19:53:53.172811 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 19:53:53.180189 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 19:53:53.184686 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 19:53:53.187766 in-header: 03 07 00 00 08 00 00 00
492 19:53:53.191436 in-data: aa e4 47 04 13 02 00 00
493 19:53:53.191924 Chrome EC: UHEPI supported
494 19:53:53.199714 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 19:53:53.203265 in-header: 03 95 00 00 08 00 00 00
496 19:53:53.206746 in-data: 18 20 20 08 00 00 00 00
497 19:53:53.210247 MRC: failed to locate region type 0.
498 19:53:53.218010 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 19:53:53.218451 DRAM-K: Running full calibration
500 19:53:53.225910 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 19:53:53.226344 header.status = 0x0
502 19:53:53.229419 header.version = 0x6 (expected: 0x6)
503 19:53:53.232957 header.size = 0xd00 (expected: 0xd00)
504 19:53:53.236634 header.flags = 0x0
505 19:53:53.240325 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 19:53:53.260189 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 19:53:53.267884 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 19:53:53.268313 dram_init: ddr_geometry: 2
509 19:53:53.271289 [EMI] MDL number = 2
510 19:53:53.275309 [EMI] Get MDL freq = 0
511 19:53:53.275838 dram_init: ddr_type: 0
512 19:53:53.278944 is_discrete_lpddr4: 1
513 19:53:53.279538 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 19:53:53.282771
515 19:53:53.283183
516 19:53:53.283514 [Bian_co] ETT version 0.0.0.1
517 19:53:53.290330 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 19:53:53.290782
519 19:53:53.293851 dramc_set_vcore_voltage set vcore to 650000
520 19:53:53.294378 Read voltage for 800, 4
521 19:53:53.294791 Vio18 = 0
522 19:53:53.297285 Vcore = 650000
523 19:53:53.297824 Vdram = 0
524 19:53:53.298305 Vddq = 0
525 19:53:53.301159 Vmddr = 0
526 19:53:53.301663 dram_init: config_dvfs: 1
527 19:53:53.305484 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 19:53:53.312733 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 19:53:53.316272 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 19:53:53.320532 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 19:53:53.324118 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 19:53:53.327726 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 19:53:53.330990 MEM_TYPE=3, freq_sel=18
534 19:53:53.334329 sv_algorithm_assistance_LP4_1600
535 19:53:53.337299 ============ PULL DRAM RESETB DOWN ============
536 19:53:53.341012 ========== PULL DRAM RESETB DOWN end =========
537 19:53:53.344113 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 19:53:53.347759 ===================================
539 19:53:53.352115 LPDDR4 DRAM CONFIGURATION
540 19:53:53.355367 ===================================
541 19:53:53.356031 EX_ROW_EN[0] = 0x0
542 19:53:53.359078 EX_ROW_EN[1] = 0x0
543 19:53:53.359692 LP4Y_EN = 0x0
544 19:53:53.363113 WORK_FSP = 0x0
545 19:53:53.363540 WL = 0x2
546 19:53:53.366554 RL = 0x2
547 19:53:53.367070 BL = 0x2
548 19:53:53.370502 RPST = 0x0
549 19:53:53.370928 RD_PRE = 0x0
550 19:53:53.373466 WR_PRE = 0x1
551 19:53:53.373888 WR_PST = 0x0
552 19:53:53.376699 DBI_WR = 0x0
553 19:53:53.377121 DBI_RD = 0x0
554 19:53:53.380633 OTF = 0x1
555 19:53:53.383672 ===================================
556 19:53:53.386800 ===================================
557 19:53:53.387025 ANA top config
558 19:53:53.389990 ===================================
559 19:53:53.393139 DLL_ASYNC_EN = 0
560 19:53:53.396503 ALL_SLAVE_EN = 1
561 19:53:53.396586 NEW_RANK_MODE = 1
562 19:53:53.400029 DLL_IDLE_MODE = 1
563 19:53:53.403100 LP45_APHY_COMB_EN = 1
564 19:53:53.406650 TX_ODT_DIS = 1
565 19:53:53.406734 NEW_8X_MODE = 1
566 19:53:53.410414 ===================================
567 19:53:53.414121 ===================================
568 19:53:53.417123 data_rate = 1600
569 19:53:53.420765 CKR = 1
570 19:53:53.424358 DQ_P2S_RATIO = 8
571 19:53:53.427310 ===================================
572 19:53:53.430896 CA_P2S_RATIO = 8
573 19:53:53.430980 DQ_CA_OPEN = 0
574 19:53:53.434040 DQ_SEMI_OPEN = 0
575 19:53:53.437471 CA_SEMI_OPEN = 0
576 19:53:53.440621 CA_FULL_RATE = 0
577 19:53:53.444395 DQ_CKDIV4_EN = 1
578 19:53:53.444478 CA_CKDIV4_EN = 1
579 19:53:53.447484 CA_PREDIV_EN = 0
580 19:53:53.450710 PH8_DLY = 0
581 19:53:53.453955 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 19:53:53.457440 DQ_AAMCK_DIV = 4
583 19:53:53.461434 CA_AAMCK_DIV = 4
584 19:53:53.461517 CA_ADMCK_DIV = 4
585 19:53:53.464603 DQ_TRACK_CA_EN = 0
586 19:53:53.467779 CA_PICK = 800
587 19:53:53.471406 CA_MCKIO = 800
588 19:53:53.475324 MCKIO_SEMI = 0
589 19:53:53.475408 PLL_FREQ = 3068
590 19:53:53.478770 DQ_UI_PI_RATIO = 32
591 19:53:53.482632 CA_UI_PI_RATIO = 0
592 19:53:53.486612 ===================================
593 19:53:53.490480 ===================================
594 19:53:53.490564 memory_type:LPDDR4
595 19:53:53.493860 GP_NUM : 10
596 19:53:53.493941 SRAM_EN : 1
597 19:53:53.497812 MD32_EN : 0
598 19:53:53.501366 ===================================
599 19:53:53.501446 [ANA_INIT] >>>>>>>>>>>>>>
600 19:53:53.505476 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 19:53:53.508633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 19:53:53.512622 ===================================
603 19:53:53.515662 data_rate = 1600,PCW = 0X7600
604 19:53:53.518574 ===================================
605 19:53:53.522299 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 19:53:53.529213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 19:53:53.532044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 19:53:53.539294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 19:53:53.542560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 19:53:53.545938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 19:53:53.546116 [ANA_INIT] flow start
612 19:53:53.549053 [ANA_INIT] PLL >>>>>>>>
613 19:53:53.552784 [ANA_INIT] PLL <<<<<<<<
614 19:53:53.552983 [ANA_INIT] MIDPI >>>>>>>>
615 19:53:53.555570 [ANA_INIT] MIDPI <<<<<<<<
616 19:53:53.559291 [ANA_INIT] DLL >>>>>>>>
617 19:53:53.559481 [ANA_INIT] flow end
618 19:53:53.566067 ============ LP4 DIFF to SE enter ============
619 19:53:53.569607 ============ LP4 DIFF to SE exit ============
620 19:53:53.572371 [ANA_INIT] <<<<<<<<<<<<<
621 19:53:53.576270 [Flow] Enable top DCM control >>>>>
622 19:53:53.576531 [Flow] Enable top DCM control <<<<<
623 19:53:53.579785 Enable DLL master slave shuffle
624 19:53:53.585757 ==============================================================
625 19:53:53.589248 Gating Mode config
626 19:53:53.592969 ==============================================================
627 19:53:53.596384 Config description:
628 19:53:53.606581 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 19:53:53.612833 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 19:53:53.616419 SELPH_MODE 0: By rank 1: By Phase
631 19:53:53.623003 ==============================================================
632 19:53:53.626493 GAT_TRACK_EN = 1
633 19:53:53.629283 RX_GATING_MODE = 2
634 19:53:53.629717 RX_GATING_TRACK_MODE = 2
635 19:53:53.632909 SELPH_MODE = 1
636 19:53:53.636231 PICG_EARLY_EN = 1
637 19:53:53.639740 VALID_LAT_VALUE = 1
638 19:53:53.646412 ==============================================================
639 19:53:53.649819 Enter into Gating configuration >>>>
640 19:53:53.653150 Exit from Gating configuration <<<<
641 19:53:53.656325 Enter into DVFS_PRE_config >>>>>
642 19:53:53.666410 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 19:53:53.669954 Exit from DVFS_PRE_config <<<<<
644 19:53:53.673052 Enter into PICG configuration >>>>
645 19:53:53.676459 Exit from PICG configuration <<<<
646 19:53:53.679937 [RX_INPUT] configuration >>>>>
647 19:53:53.683022 [RX_INPUT] configuration <<<<<
648 19:53:53.686193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 19:53:53.692932 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 19:53:53.699696 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 19:53:53.702887 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 19:53:53.709844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 19:53:53.716583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 19:53:53.719725 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 19:53:53.723082 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 19:53:53.729967 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 19:53:53.733132 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 19:53:53.736639 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 19:53:53.743121 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 19:53:53.743553 ===================================
661 19:53:53.746741 LPDDR4 DRAM CONFIGURATION
662 19:53:53.749723 ===================================
663 19:53:53.753313 EX_ROW_EN[0] = 0x0
664 19:53:53.753743 EX_ROW_EN[1] = 0x0
665 19:53:53.756758 LP4Y_EN = 0x0
666 19:53:53.757186 WORK_FSP = 0x0
667 19:53:53.759847 WL = 0x2
668 19:53:53.760274 RL = 0x2
669 19:53:53.763146 BL = 0x2
670 19:53:53.763573 RPST = 0x0
671 19:53:53.766662 RD_PRE = 0x0
672 19:53:53.766964 WR_PRE = 0x1
673 19:53:53.770141 WR_PST = 0x0
674 19:53:53.770445 DBI_WR = 0x0
675 19:53:53.773293 DBI_RD = 0x0
676 19:53:53.776277 OTF = 0x1
677 19:53:53.779828 ===================================
678 19:53:53.783333 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 19:53:53.786506 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 19:53:53.789853 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 19:53:53.793537 ===================================
682 19:53:53.796515 LPDDR4 DRAM CONFIGURATION
683 19:53:53.800159 ===================================
684 19:53:53.803096 EX_ROW_EN[0] = 0x10
685 19:53:53.803327 EX_ROW_EN[1] = 0x0
686 19:53:53.807100 LP4Y_EN = 0x0
687 19:53:53.807329 WORK_FSP = 0x0
688 19:53:53.810280 WL = 0x2
689 19:53:53.810509 RL = 0x2
690 19:53:53.813311 BL = 0x2
691 19:53:53.813539 RPST = 0x0
692 19:53:53.816983 RD_PRE = 0x0
693 19:53:53.817213 WR_PRE = 0x1
694 19:53:53.819974 WR_PST = 0x0
695 19:53:53.820206 DBI_WR = 0x0
696 19:53:53.823791 DBI_RD = 0x0
697 19:53:53.824019 OTF = 0x1
698 19:53:53.826845 ===================================
699 19:53:53.833311 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 19:53:53.837523 nWR fixed to 40
701 19:53:53.841152 [ModeRegInit_LP4] CH0 RK0
702 19:53:53.841383 [ModeRegInit_LP4] CH0 RK1
703 19:53:53.844200 [ModeRegInit_LP4] CH1 RK0
704 19:53:53.847793 [ModeRegInit_LP4] CH1 RK1
705 19:53:53.848022 match AC timing 13
706 19:53:53.854377 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 19:53:53.857859 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 19:53:53.860857 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 19:53:53.867485 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 19:53:53.870736 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 19:53:53.871106 [EMI DOE] emi_dcm 0
712 19:53:53.877669 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 19:53:53.877909 ==
714 19:53:53.880919 Dram Type= 6, Freq= 0, CH_0, rank 0
715 19:53:53.884192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 19:53:53.884472 ==
717 19:53:53.890811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 19:53:53.897256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 19:53:53.905064 [CA 0] Center 36 (6~67) winsize 62
720 19:53:53.908732 [CA 1] Center 36 (6~67) winsize 62
721 19:53:53.911918 [CA 2] Center 34 (4~65) winsize 62
722 19:53:53.915098 [CA 3] Center 33 (3~64) winsize 62
723 19:53:53.918297 [CA 4] Center 33 (3~64) winsize 62
724 19:53:53.921568 [CA 5] Center 32 (3~62) winsize 60
725 19:53:53.921723
726 19:53:53.925058 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 19:53:53.925212
728 19:53:53.928228 [CATrainingPosCal] consider 1 rank data
729 19:53:53.931888 u2DelayCellTimex100 = 270/100 ps
730 19:53:53.935030 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 19:53:53.938087 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 19:53:53.945661 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 19:53:53.948605 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 19:53:53.951704 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 19:53:53.954854 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 19:53:53.954987
737 19:53:53.958361 CA PerBit enable=1, Macro0, CA PI delay=32
738 19:53:53.958531
739 19:53:53.961871 [CBTSetCACLKResult] CA Dly = 32
740 19:53:53.962004 CS Dly: 4 (0~35)
741 19:53:53.962112 ==
742 19:53:53.964971 Dram Type= 6, Freq= 0, CH_0, rank 1
743 19:53:53.971587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 19:53:53.971747 ==
745 19:53:53.975502 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 19:53:53.981908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 19:53:53.990959 [CA 0] Center 36 (6~67) winsize 62
748 19:53:53.994380 [CA 1] Center 36 (6~67) winsize 62
749 19:53:53.997756 [CA 2] Center 34 (3~65) winsize 63
750 19:53:54.001055 [CA 3] Center 34 (3~65) winsize 63
751 19:53:54.004370 [CA 4] Center 33 (3~64) winsize 62
752 19:53:54.007515 [CA 5] Center 32 (2~63) winsize 62
753 19:53:54.007660
754 19:53:54.011251 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 19:53:54.011382
756 19:53:54.014123 [CATrainingPosCal] consider 2 rank data
757 19:53:54.017305 u2DelayCellTimex100 = 270/100 ps
758 19:53:54.021101 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 19:53:54.027382 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 19:53:54.031135 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 19:53:54.034131 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 19:53:54.037905 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
763 19:53:54.041033 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 19:53:54.041156
765 19:53:54.044087 CA PerBit enable=1, Macro0, CA PI delay=32
766 19:53:54.044205
767 19:53:54.047558 [CBTSetCACLKResult] CA Dly = 32
768 19:53:54.047695 CS Dly: 5 (0~37)
769 19:53:54.047810
770 19:53:54.051450 ----->DramcWriteLeveling(PI) begin...
771 19:53:54.055146 ==
772 19:53:54.055254 Dram Type= 6, Freq= 0, CH_0, rank 0
773 19:53:54.058993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 19:53:54.062708 ==
775 19:53:54.062864 Write leveling (Byte 0): 32 => 32
776 19:53:54.066540 Write leveling (Byte 1): 28 => 28
777 19:53:54.069833 DramcWriteLeveling(PI) end<-----
778 19:53:54.069968
779 19:53:54.070084 ==
780 19:53:54.073460 Dram Type= 6, Freq= 0, CH_0, rank 0
781 19:53:54.076294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 19:53:54.076457 ==
783 19:53:54.080087 [Gating] SW mode calibration
784 19:53:54.087191 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 19:53:54.094296 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 19:53:54.097418 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 19:53:54.101054 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 19:53:54.103990 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 19:53:54.110905 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 19:53:54.113946 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 19:53:54.117662 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 19:53:54.124278 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 19:53:54.127431 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 19:53:54.130562 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 19:53:54.137427 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 19:53:54.141178 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 19:53:54.144690 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 19:53:54.151075 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 19:53:54.154319 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 19:53:54.157336 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 19:53:54.164123 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 19:53:54.167569 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 19:53:54.171276 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 19:53:54.177514 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 19:53:54.181152 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 19:53:54.184027 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 19:53:54.187703 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 19:53:54.194287 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 19:53:54.197507 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 19:53:54.200762 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 19:53:54.207771 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 19:53:54.210746 0 9 8 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 1)
813 19:53:54.214396 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 19:53:54.220773 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 19:53:54.224523 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 19:53:54.228175 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 19:53:54.234317 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 19:53:54.237557 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 19:53:54.241127 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
820 19:53:54.247986 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
821 19:53:54.251058 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
822 19:53:54.254567 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 19:53:54.261391 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 19:53:54.264575 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 19:53:54.267515 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 19:53:54.271243 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 19:53:54.278081 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
828 19:53:54.281065 0 11 8 | B1->B0 | 2d2d 3c3c | 1 0 | (0 0) (0 0)
829 19:53:54.284662 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 19:53:54.291105 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 19:53:54.294483 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 19:53:54.298236 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 19:53:54.304895 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 19:53:54.307920 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 19:53:54.311004 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 19:53:54.318086 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 19:53:54.321091 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 19:53:54.324788 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 19:53:54.331249 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 19:53:54.334847 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 19:53:54.337697 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 19:53:54.344514 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 19:53:54.348111 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 19:53:54.351174 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 19:53:54.354398 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 19:53:54.361186 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 19:53:54.364591 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 19:53:54.367803 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 19:53:54.374478 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 19:53:54.377817 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 19:53:54.381449 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 19:53:54.388310 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 19:53:54.388423 Total UI for P1: 0, mck2ui 16
854 19:53:54.395122 best dqsien dly found for B0: ( 0, 14, 4)
855 19:53:54.398319 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 19:53:54.401319 Total UI for P1: 0, mck2ui 16
857 19:53:54.405522 best dqsien dly found for B1: ( 0, 14, 8)
858 19:53:54.409323 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 19:53:54.412293 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 19:53:54.412404
861 19:53:54.415941 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 19:53:54.418981 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 19:53:54.422894 [Gating] SW calibration Done
864 19:53:54.423007 ==
865 19:53:54.426026 Dram Type= 6, Freq= 0, CH_0, rank 0
866 19:53:54.429057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 19:53:54.429142 ==
868 19:53:54.429209 RX Vref Scan: 0
869 19:53:54.432512
870 19:53:54.432627 RX Vref 0 -> 0, step: 1
871 19:53:54.432723
872 19:53:54.436132 RX Delay -130 -> 252, step: 16
873 19:53:54.439103 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 19:53:54.442508 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 19:53:54.449625 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 19:53:54.453090 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 19:53:54.456261 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 19:53:54.459416 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 19:53:54.463176 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 19:53:54.469773 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 19:53:54.472923 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
882 19:53:54.476118 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 19:53:54.479555 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 19:53:54.482701 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
885 19:53:54.489324 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 19:53:54.493143 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 19:53:54.496107 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 19:53:54.499757 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 19:53:54.499831 ==
890 19:53:54.502812 Dram Type= 6, Freq= 0, CH_0, rank 0
891 19:53:54.509629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 19:53:54.509734 ==
893 19:53:54.509835 DQS Delay:
894 19:53:54.509934 DQS0 = 0, DQS1 = 0
895 19:53:54.513162 DQM Delay:
896 19:53:54.513243 DQM0 = 90, DQM1 = 84
897 19:53:54.516399 DQ Delay:
898 19:53:54.519307 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
899 19:53:54.519438 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 19:53:54.522784 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
901 19:53:54.529766 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 19:53:54.529853
903 19:53:54.529920
904 19:53:54.529982 ==
905 19:53:54.532815 Dram Type= 6, Freq= 0, CH_0, rank 0
906 19:53:54.535993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 19:53:54.536078 ==
908 19:53:54.536144
909 19:53:54.536205
910 19:53:54.539676 TX Vref Scan disable
911 19:53:54.539761 == TX Byte 0 ==
912 19:53:54.546465 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 19:53:54.549877 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 19:53:54.550014 == TX Byte 1 ==
915 19:53:54.556177 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
916 19:53:54.559423 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
917 19:53:54.559557 ==
918 19:53:54.562934 Dram Type= 6, Freq= 0, CH_0, rank 0
919 19:53:54.566116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 19:53:54.566225 ==
921 19:53:54.580775 TX Vref=22, minBit 3, minWin=27, winSum=446
922 19:53:54.583835 TX Vref=24, minBit 10, minWin=27, winSum=455
923 19:53:54.587116 TX Vref=26, minBit 0, minWin=28, winSum=453
924 19:53:54.590452 TX Vref=28, minBit 0, minWin=28, winSum=457
925 19:53:54.593650 TX Vref=30, minBit 0, minWin=28, winSum=458
926 19:53:54.597419 TX Vref=32, minBit 2, minWin=28, winSum=456
927 19:53:54.603984 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
928 19:53:54.604060
929 19:53:54.607432 Final TX Range 1 Vref 30
930 19:53:54.607541
931 19:53:54.607633 ==
932 19:53:54.610353 Dram Type= 6, Freq= 0, CH_0, rank 0
933 19:53:54.614196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 19:53:54.614296 ==
935 19:53:54.614387
936 19:53:54.614491
937 19:53:54.617245 TX Vref Scan disable
938 19:53:54.621088 == TX Byte 0 ==
939 19:53:54.624003 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 19:53:54.627390 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 19:53:54.630325 == TX Byte 1 ==
942 19:53:54.634139 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
943 19:53:54.637340 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
944 19:53:54.640477
945 19:53:54.640552 [DATLAT]
946 19:53:54.640616 Freq=800, CH0 RK0
947 19:53:54.640677
948 19:53:54.644240 DATLAT Default: 0xa
949 19:53:54.644313 0, 0xFFFF, sum = 0
950 19:53:54.647337 1, 0xFFFF, sum = 0
951 19:53:54.647450 2, 0xFFFF, sum = 0
952 19:53:54.650500 3, 0xFFFF, sum = 0
953 19:53:54.650601 4, 0xFFFF, sum = 0
954 19:53:54.654147 5, 0xFFFF, sum = 0
955 19:53:54.654261 6, 0xFFFF, sum = 0
956 19:53:54.657243 7, 0xFFFF, sum = 0
957 19:53:54.657317 8, 0xFFFF, sum = 0
958 19:53:54.660910 9, 0x0, sum = 1
959 19:53:54.661027 10, 0x0, sum = 2
960 19:53:54.664000 11, 0x0, sum = 3
961 19:53:54.664076 12, 0x0, sum = 4
962 19:53:54.667450 best_step = 10
963 19:53:54.667562
964 19:53:54.667699 ==
965 19:53:54.670870 Dram Type= 6, Freq= 0, CH_0, rank 0
966 19:53:54.673970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 19:53:54.674118 ==
968 19:53:54.677747 RX Vref Scan: 1
969 19:53:54.677818
970 19:53:54.677879 Set Vref Range= 32 -> 127
971 19:53:54.677942
972 19:53:54.680664 RX Vref 32 -> 127, step: 1
973 19:53:54.680738
974 19:53:54.684262 RX Delay -95 -> 252, step: 8
975 19:53:54.684336
976 19:53:54.687447 Set Vref, RX VrefLevel [Byte0]: 32
977 19:53:54.691002 [Byte1]: 32
978 19:53:54.691084
979 19:53:54.694093 Set Vref, RX VrefLevel [Byte0]: 33
980 19:53:54.697865 [Byte1]: 33
981 19:53:54.701064
982 19:53:54.701136 Set Vref, RX VrefLevel [Byte0]: 34
983 19:53:54.704315 [Byte1]: 34
984 19:53:54.708606
985 19:53:54.708687 Set Vref, RX VrefLevel [Byte0]: 35
986 19:53:54.711530 [Byte1]: 35
987 19:53:54.716211
988 19:53:54.716282 Set Vref, RX VrefLevel [Byte0]: 36
989 19:53:54.719891 [Byte1]: 36
990 19:53:54.724325
991 19:53:54.724428 Set Vref, RX VrefLevel [Byte0]: 37
992 19:53:54.728056 [Byte1]: 37
993 19:53:54.731909
994 19:53:54.731987 Set Vref, RX VrefLevel [Byte0]: 38
995 19:53:54.735350 [Byte1]: 38
996 19:53:54.739179
997 19:53:54.739258 Set Vref, RX VrefLevel [Byte0]: 39
998 19:53:54.742107 [Byte1]: 39
999 19:53:54.746409
1000 19:53:54.746524 Set Vref, RX VrefLevel [Byte0]: 40
1001 19:53:54.749667 [Byte1]: 40
1002 19:53:54.754108
1003 19:53:54.754194 Set Vref, RX VrefLevel [Byte0]: 41
1004 19:53:54.757234 [Byte1]: 41
1005 19:53:54.761466
1006 19:53:54.761579 Set Vref, RX VrefLevel [Byte0]: 42
1007 19:53:54.765206 [Byte1]: 42
1008 19:53:54.769081
1009 19:53:54.769156 Set Vref, RX VrefLevel [Byte0]: 43
1010 19:53:54.772313 [Byte1]: 43
1011 19:53:54.776631
1012 19:53:54.776705 Set Vref, RX VrefLevel [Byte0]: 44
1013 19:53:54.780095 [Byte1]: 44
1014 19:53:54.784636
1015 19:53:54.784708 Set Vref, RX VrefLevel [Byte0]: 45
1016 19:53:54.787867 [Byte1]: 45
1017 19:53:54.792087
1018 19:53:54.792165 Set Vref, RX VrefLevel [Byte0]: 46
1019 19:53:54.795347 [Byte1]: 46
1020 19:53:54.799527
1021 19:53:54.799633 Set Vref, RX VrefLevel [Byte0]: 47
1022 19:53:54.802594 [Byte1]: 47
1023 19:53:54.807431
1024 19:53:54.807534 Set Vref, RX VrefLevel [Byte0]: 48
1025 19:53:54.810604 [Byte1]: 48
1026 19:53:54.814986
1027 19:53:54.815097 Set Vref, RX VrefLevel [Byte0]: 49
1028 19:53:54.818090 [Byte1]: 49
1029 19:53:54.822181
1030 19:53:54.822283 Set Vref, RX VrefLevel [Byte0]: 50
1031 19:53:54.825562 [Byte1]: 50
1032 19:53:54.829827
1033 19:53:54.829925 Set Vref, RX VrefLevel [Byte0]: 51
1034 19:53:54.833421 [Byte1]: 51
1035 19:53:54.837629
1036 19:53:54.837729 Set Vref, RX VrefLevel [Byte0]: 52
1037 19:53:54.840695 [Byte1]: 52
1038 19:53:54.844993
1039 19:53:54.845079 Set Vref, RX VrefLevel [Byte0]: 53
1040 19:53:54.848198 [Byte1]: 53
1041 19:53:54.852574
1042 19:53:54.852646 Set Vref, RX VrefLevel [Byte0]: 54
1043 19:53:54.856337 [Byte1]: 54
1044 19:53:54.860000
1045 19:53:54.860109 Set Vref, RX VrefLevel [Byte0]: 55
1046 19:53:54.863767 [Byte1]: 55
1047 19:53:54.868028
1048 19:53:54.868104 Set Vref, RX VrefLevel [Byte0]: 56
1049 19:53:54.871124 [Byte1]: 56
1050 19:53:54.875541
1051 19:53:54.875656 Set Vref, RX VrefLevel [Byte0]: 57
1052 19:53:54.878807 [Byte1]: 57
1053 19:53:54.883030
1054 19:53:54.883139 Set Vref, RX VrefLevel [Byte0]: 58
1055 19:53:54.886180 [Byte1]: 58
1056 19:53:54.890518
1057 19:53:54.890628 Set Vref, RX VrefLevel [Byte0]: 59
1058 19:53:54.894099 [Byte1]: 59
1059 19:53:54.898136
1060 19:53:54.898233 Set Vref, RX VrefLevel [Byte0]: 60
1061 19:53:54.901466 [Byte1]: 60
1062 19:53:54.905933
1063 19:53:54.906033 Set Vref, RX VrefLevel [Byte0]: 61
1064 19:53:54.909063 [Byte1]: 61
1065 19:53:54.913743
1066 19:53:54.913823 Set Vref, RX VrefLevel [Byte0]: 62
1067 19:53:54.916915 [Byte1]: 62
1068 19:53:54.921221
1069 19:53:54.921296 Set Vref, RX VrefLevel [Byte0]: 63
1070 19:53:54.924386 [Byte1]: 63
1071 19:53:54.928679
1072 19:53:54.928749 Set Vref, RX VrefLevel [Byte0]: 64
1073 19:53:54.932129 [Byte1]: 64
1074 19:53:54.936129
1075 19:53:54.936222 Set Vref, RX VrefLevel [Byte0]: 65
1076 19:53:54.939565 [Byte1]: 65
1077 19:53:54.943729
1078 19:53:54.943801 Set Vref, RX VrefLevel [Byte0]: 66
1079 19:53:54.947166 [Byte1]: 66
1080 19:53:54.951224
1081 19:53:54.951333 Set Vref, RX VrefLevel [Byte0]: 67
1082 19:53:54.954850 [Byte1]: 67
1083 19:53:54.959194
1084 19:53:54.959290 Set Vref, RX VrefLevel [Byte0]: 68
1085 19:53:54.962532 [Byte1]: 68
1086 19:53:54.966890
1087 19:53:54.966988 Set Vref, RX VrefLevel [Byte0]: 69
1088 19:53:54.970033 [Byte1]: 69
1089 19:53:54.974130
1090 19:53:54.974227 Set Vref, RX VrefLevel [Byte0]: 70
1091 19:53:54.977828 [Byte1]: 70
1092 19:53:54.982196
1093 19:53:54.982291 Set Vref, RX VrefLevel [Byte0]: 71
1094 19:53:54.985380 [Byte1]: 71
1095 19:53:54.989654
1096 19:53:54.989750 Set Vref, RX VrefLevel [Byte0]: 72
1097 19:53:54.992778 [Byte1]: 72
1098 19:53:54.997203
1099 19:53:54.997304 Set Vref, RX VrefLevel [Byte0]: 73
1100 19:53:55.000206 [Byte1]: 73
1101 19:53:55.004549
1102 19:53:55.004635 Set Vref, RX VrefLevel [Byte0]: 74
1103 19:53:55.008153 [Byte1]: 74
1104 19:53:55.012458
1105 19:53:55.012565 Set Vref, RX VrefLevel [Byte0]: 75
1106 19:53:55.015369 [Byte1]: 75
1107 19:53:55.020392
1108 19:53:55.020477 Set Vref, RX VrefLevel [Byte0]: 76
1109 19:53:55.023573 [Byte1]: 76
1110 19:53:55.027462
1111 19:53:55.027566 Set Vref, RX VrefLevel [Byte0]: 77
1112 19:53:55.030657 [Byte1]: 77
1113 19:53:55.035083
1114 19:53:55.035154 Set Vref, RX VrefLevel [Byte0]: 78
1115 19:53:55.038578 [Byte1]: 78
1116 19:53:55.042601
1117 19:53:55.042680 Final RX Vref Byte 0 = 53 to rank0
1118 19:53:55.046418 Final RX Vref Byte 1 = 61 to rank0
1119 19:53:55.049673 Final RX Vref Byte 0 = 53 to rank1
1120 19:53:55.052495 Final RX Vref Byte 1 = 61 to rank1==
1121 19:53:55.056136 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 19:53:55.059402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 19:53:55.062603 ==
1124 19:53:55.062682 DQS Delay:
1125 19:53:55.062744 DQS0 = 0, DQS1 = 0
1126 19:53:55.066385 DQM Delay:
1127 19:53:55.066459 DQM0 = 91, DQM1 = 85
1128 19:53:55.069453 DQ Delay:
1129 19:53:55.069525 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1130 19:53:55.073284 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1131 19:53:55.076432 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1132 19:53:55.079442 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1133 19:53:55.083162
1134 19:53:55.083243
1135 19:53:55.089573 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1136 19:53:55.092641 CH0 RK0: MR19=606, MR18=4B41
1137 19:53:55.099599 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1138 19:53:55.099713
1139 19:53:55.102610 ----->DramcWriteLeveling(PI) begin...
1140 19:53:55.102688 ==
1141 19:53:55.106511 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 19:53:55.109594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 19:53:55.109667 ==
1144 19:53:55.113291 Write leveling (Byte 0): 34 => 34
1145 19:53:55.116283 Write leveling (Byte 1): 30 => 30
1146 19:53:55.119530 DramcWriteLeveling(PI) end<-----
1147 19:53:55.119602
1148 19:53:55.119708 ==
1149 19:53:55.122599 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 19:53:55.126355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 19:53:55.126443 ==
1152 19:53:55.170341 [Gating] SW mode calibration
1153 19:53:55.170618 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 19:53:55.170722 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 19:53:55.170839 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 19:53:55.170936 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 19:53:55.171032 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 19:53:55.171513 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 19:53:55.171817 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 19:53:55.171931 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 19:53:55.214488 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 19:53:55.214576 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 19:53:55.214847 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 19:53:55.214920 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 19:53:55.215016 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 19:53:55.215830 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 19:53:55.215914 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 19:53:55.216183 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 19:53:55.216256 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 19:53:55.216351 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 19:53:55.241995 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 19:53:55.242122 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1173 19:53:55.242413 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1174 19:53:55.242512 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 19:53:55.242611 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 19:53:55.242722 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 19:53:55.242817 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 19:53:55.246068 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 19:53:55.252874 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 19:53:55.256038 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1181 19:53:55.259055 0 9 8 | B1->B0 | 2b2b 2827 | 0 1 | (1 1) (0 0)
1182 19:53:55.266111 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 19:53:55.269089 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 19:53:55.272885 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 19:53:55.279195 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 19:53:55.282796 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 19:53:55.286079 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 19:53:55.292793 0 10 4 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
1189 19:53:55.296661 0 10 8 | B1->B0 | 2828 2a2a | 0 0 | (1 0) (1 0)
1190 19:53:55.300142 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 19:53:55.303922 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 19:53:55.307597 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 19:53:55.311958 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 19:53:55.318189 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 19:53:55.321953 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 19:53:55.325108 0 11 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1197 19:53:55.332551 0 11 8 | B1->B0 | 3d3d 3636 | 0 0 | (0 0) (0 0)
1198 19:53:55.335679 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 19:53:55.338826 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 19:53:55.342699 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 19:53:55.349012 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 19:53:55.352598 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 19:53:55.355584 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 19:53:55.362497 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 19:53:55.365866 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1206 19:53:55.369133 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1207 19:53:55.375858 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 19:53:55.379397 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 19:53:55.382520 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 19:53:55.388851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 19:53:55.392481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 19:53:55.395973 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 19:53:55.402523 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 19:53:55.405724 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 19:53:55.409180 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 19:53:55.412568 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 19:53:55.419427 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 19:53:55.422643 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 19:53:55.426395 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 19:53:55.432499 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 19:53:55.436108 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1222 19:53:55.439300 Total UI for P1: 0, mck2ui 16
1223 19:53:55.443015 best dqsien dly found for B0: ( 0, 14, 6)
1224 19:53:55.446265 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 19:53:55.449329 Total UI for P1: 0, mck2ui 16
1226 19:53:55.453013 best dqsien dly found for B1: ( 0, 14, 8)
1227 19:53:55.455951 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1228 19:53:55.459181 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 19:53:55.459264
1230 19:53:55.462803 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1231 19:53:55.469726 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 19:53:55.469809 [Gating] SW calibration Done
1233 19:53:55.469928 ==
1234 19:53:55.472625 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 19:53:55.479795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 19:53:55.479880 ==
1237 19:53:55.479966 RX Vref Scan: 0
1238 19:53:55.480046
1239 19:53:55.482618 RX Vref 0 -> 0, step: 1
1240 19:53:55.482721
1241 19:53:55.485926 RX Delay -130 -> 252, step: 16
1242 19:53:55.489384 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1243 19:53:55.492562 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1244 19:53:55.496412 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1245 19:53:55.503093 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1246 19:53:55.506390 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1247 19:53:55.509443 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1248 19:53:55.512556 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1249 19:53:55.516235 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1250 19:53:55.522872 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1251 19:53:55.526205 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1252 19:53:55.529469 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
1253 19:53:55.533000 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1254 19:53:55.536269 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1255 19:53:55.542902 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1256 19:53:55.546045 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1257 19:53:55.549268 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1258 19:53:55.549348 ==
1259 19:53:55.553003 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 19:53:55.556213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 19:53:55.556287 ==
1262 19:53:55.559189 DQS Delay:
1263 19:53:55.559258 DQS0 = 0, DQS1 = 0
1264 19:53:55.562992 DQM Delay:
1265 19:53:55.563072 DQM0 = 93, DQM1 = 85
1266 19:53:55.563136 DQ Delay:
1267 19:53:55.566057 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1268 19:53:55.569741 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =93
1269 19:53:55.572908 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77
1270 19:53:55.575978 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1271 19:53:55.576056
1272 19:53:55.576119
1273 19:53:55.576177 ==
1274 19:53:55.579576 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 19:53:55.586136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 19:53:55.586210 ==
1277 19:53:55.586271
1278 19:53:55.586337
1279 19:53:55.586393 TX Vref Scan disable
1280 19:53:55.590207 == TX Byte 0 ==
1281 19:53:55.593051 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1282 19:53:55.596787 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1283 19:53:55.599946 == TX Byte 1 ==
1284 19:53:55.603565 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1285 19:53:55.606516 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1286 19:53:55.610077 ==
1287 19:53:55.613174 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 19:53:55.616945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 19:53:55.617012 ==
1290 19:53:55.629441 TX Vref=22, minBit 0, minWin=28, winSum=449
1291 19:53:55.632880 TX Vref=24, minBit 1, minWin=28, winSum=452
1292 19:53:55.636318 TX Vref=26, minBit 1, minWin=28, winSum=454
1293 19:53:55.639480 TX Vref=28, minBit 7, minWin=28, winSum=458
1294 19:53:55.643062 TX Vref=30, minBit 1, minWin=28, winSum=457
1295 19:53:55.646169 TX Vref=32, minBit 2, minWin=28, winSum=454
1296 19:53:55.653096 [TxChooseVref] Worse bit 7, Min win 28, Win sum 458, Final Vref 28
1297 19:53:55.653180
1298 19:53:55.656317 Final TX Range 1 Vref 28
1299 19:53:55.656392
1300 19:53:55.656454 ==
1301 19:53:55.659403 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 19:53:55.662924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 19:53:55.662998 ==
1304 19:53:55.663066
1305 19:53:55.663125
1306 19:53:55.665997 TX Vref Scan disable
1307 19:53:55.669557 == TX Byte 0 ==
1308 19:53:55.672647 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1309 19:53:55.679071 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1310 19:53:55.679147 == TX Byte 1 ==
1311 19:53:55.682681 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1312 19:53:55.689603 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1313 19:53:55.689679
1314 19:53:55.689741 [DATLAT]
1315 19:53:55.689806 Freq=800, CH0 RK1
1316 19:53:55.689866
1317 19:53:55.692709 DATLAT Default: 0xa
1318 19:53:55.692774 0, 0xFFFF, sum = 0
1319 19:53:55.695793 1, 0xFFFF, sum = 0
1320 19:53:55.695860 2, 0xFFFF, sum = 0
1321 19:53:55.699578 3, 0xFFFF, sum = 0
1322 19:53:55.702629 4, 0xFFFF, sum = 0
1323 19:53:55.702709 5, 0xFFFF, sum = 0
1324 19:53:55.705999 6, 0xFFFF, sum = 0
1325 19:53:55.706075 7, 0xFFFF, sum = 0
1326 19:53:55.709309 8, 0xFFFF, sum = 0
1327 19:53:55.709376 9, 0x0, sum = 1
1328 19:53:55.712383 10, 0x0, sum = 2
1329 19:53:55.712451 11, 0x0, sum = 3
1330 19:53:55.712511 12, 0x0, sum = 4
1331 19:53:55.715816 best_step = 10
1332 19:53:55.715887
1333 19:53:55.715947 ==
1334 19:53:55.719039 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 19:53:55.722823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 19:53:55.722903 ==
1337 19:53:55.725967 RX Vref Scan: 0
1338 19:53:55.726035
1339 19:53:55.726101 RX Vref 0 -> 0, step: 1
1340 19:53:55.726159
1341 19:53:55.729183 RX Delay -95 -> 252, step: 8
1342 19:53:55.736065 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1343 19:53:55.739173 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 19:53:55.742961 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1345 19:53:55.745943 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1346 19:53:55.749373 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1347 19:53:55.756144 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1348 19:53:55.759580 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 19:53:55.762474 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 19:53:55.766145 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1351 19:53:55.769565 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 19:53:55.776089 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 19:53:55.779260 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 19:53:55.783029 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1355 19:53:55.786040 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1356 19:53:55.789136 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 19:53:55.796080 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1358 19:53:55.796152 ==
1359 19:53:55.799288 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 19:53:55.803126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 19:53:55.803200 ==
1362 19:53:55.803260 DQS Delay:
1363 19:53:55.806421 DQS0 = 0, DQS1 = 0
1364 19:53:55.806487 DQM Delay:
1365 19:53:55.809512 DQM0 = 92, DQM1 = 83
1366 19:53:55.809578 DQ Delay:
1367 19:53:55.812649 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1368 19:53:55.816268 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1369 19:53:55.819164 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1370 19:53:55.822576 DQ12 =92, DQ13 =84, DQ14 =92, DQ15 =92
1371 19:53:55.822654
1372 19:53:55.822725
1373 19:53:55.832474 [DQSOSCAuto] RK1, (LSB)MR18= 0x4617, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1374 19:53:55.832552 CH0 RK1: MR19=606, MR18=4617
1375 19:53:55.839586 CH0_RK1: MR19=0x606, MR18=0x4617, DQSOSC=392, MR23=63, INC=96, DEC=64
1376 19:53:55.842919 [RxdqsGatingPostProcess] freq 800
1377 19:53:55.849148 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 19:53:55.852953 Pre-setting of DQS Precalculation
1379 19:53:55.856134 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 19:53:55.856210 ==
1381 19:53:55.859179 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 19:53:55.862575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 19:53:55.862653 ==
1384 19:53:55.869325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 19:53:55.875605 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 19:53:55.884528 [CA 0] Center 36 (6~67) winsize 62
1387 19:53:55.887531 [CA 1] Center 36 (6~67) winsize 62
1388 19:53:55.891459 [CA 2] Center 35 (5~65) winsize 61
1389 19:53:55.894566 [CA 3] Center 34 (4~65) winsize 62
1390 19:53:55.897689 [CA 4] Center 34 (4~65) winsize 62
1391 19:53:55.901524 [CA 5] Center 34 (4~64) winsize 61
1392 19:53:55.901594
1393 19:53:55.904758 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1394 19:53:55.904825
1395 19:53:55.908011 [CATrainingPosCal] consider 1 rank data
1396 19:53:55.911229 u2DelayCellTimex100 = 270/100 ps
1397 19:53:55.914396 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 19:53:55.918257 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 19:53:55.921482 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1400 19:53:55.928291 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 19:53:55.931179 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 19:53:55.934900 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 19:53:55.934976
1404 19:53:55.937915 CA PerBit enable=1, Macro0, CA PI delay=34
1405 19:53:55.937984
1406 19:53:55.941557 [CBTSetCACLKResult] CA Dly = 34
1407 19:53:55.941626 CS Dly: 5 (0~36)
1408 19:53:55.941693 ==
1409 19:53:55.944681 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 19:53:55.951547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 19:53:55.951625 ==
1412 19:53:55.954849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 19:53:55.961406 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 19:53:55.971185 [CA 0] Center 36 (6~67) winsize 62
1415 19:53:55.974606 [CA 1] Center 37 (6~68) winsize 63
1416 19:53:55.978360 [CA 2] Center 35 (4~66) winsize 63
1417 19:53:55.982183 [CA 3] Center 34 (4~65) winsize 62
1418 19:53:55.986532 [CA 4] Center 35 (4~66) winsize 63
1419 19:53:55.986617 [CA 5] Center 34 (4~65) winsize 62
1420 19:53:55.986702
1421 19:53:55.990718 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 19:53:55.990825
1423 19:53:55.994664 [CATrainingPosCal] consider 2 rank data
1424 19:53:55.998155 u2DelayCellTimex100 = 270/100 ps
1425 19:53:56.001353 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 19:53:56.004347 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 19:53:56.007989 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 19:53:56.011349 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 19:53:56.017675 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 19:53:56.021150 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 19:53:56.021231
1432 19:53:56.024252 CA PerBit enable=1, Macro0, CA PI delay=34
1433 19:53:56.024330
1434 19:53:56.027831 [CBTSetCACLKResult] CA Dly = 34
1435 19:53:56.027911 CS Dly: 6 (0~38)
1436 19:53:56.027975
1437 19:53:56.031014 ----->DramcWriteLeveling(PI) begin...
1438 19:53:56.031083 ==
1439 19:53:56.034574 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 19:53:56.041046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 19:53:56.041119 ==
1442 19:53:56.044831 Write leveling (Byte 0): 28 => 28
1443 19:53:56.044899 Write leveling (Byte 1): 28 => 28
1444 19:53:56.047974 DramcWriteLeveling(PI) end<-----
1445 19:53:56.048049
1446 19:53:56.050931 ==
1447 19:53:56.050997 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 19:53:56.057817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 19:53:56.057892 ==
1450 19:53:56.061306 [Gating] SW mode calibration
1451 19:53:56.067645 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 19:53:56.071531 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 19:53:56.077716 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 19:53:56.081172 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1455 19:53:56.084719 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1456 19:53:56.087902 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 19:53:56.094800 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 19:53:56.097995 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 19:53:56.101108 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 19:53:56.107910 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 19:53:56.111522 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 19:53:56.115097 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 19:53:56.121663 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 19:53:56.124910 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 19:53:56.128620 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 19:53:56.135202 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 19:53:56.138243 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 19:53:56.141415 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 19:53:56.148404 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1470 19:53:56.151574 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1471 19:53:56.154755 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 19:53:56.158427 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 19:53:56.164928 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 19:53:56.168232 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 19:53:56.171831 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 19:53:56.178085 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 19:53:56.181854 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 19:53:56.184859 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1479 19:53:56.191469 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1480 19:53:56.194729 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 19:53:56.198561 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 19:53:56.204952 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 19:53:56.208125 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 19:53:56.211603 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 19:53:56.218349 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 19:53:56.222127 0 10 4 | B1->B0 | 3232 2e2e | 1 0 | (0 1) (0 0)
1487 19:53:56.225110 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1488 19:53:56.232096 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 19:53:56.235321 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 19:53:56.238447 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 19:53:56.241626 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 19:53:56.248604 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 19:53:56.251797 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 19:53:56.255026 0 11 4 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
1495 19:53:56.261828 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1496 19:53:56.265599 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 19:53:56.268534 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 19:53:56.275300 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 19:53:56.279513 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 19:53:56.282091 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 19:53:56.288884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 19:53:56.291880 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1503 19:53:56.295570 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 19:53:56.298599 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 19:53:56.305577 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 19:53:56.308864 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 19:53:56.312049 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 19:53:56.318685 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 19:53:56.321934 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 19:53:56.325701 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 19:53:56.332000 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 19:53:56.335622 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 19:53:56.338959 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 19:53:56.345321 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 19:53:56.348537 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 19:53:56.352356 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 19:53:56.358585 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 19:53:56.362107 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1519 19:53:56.365624 Total UI for P1: 0, mck2ui 16
1520 19:53:56.368862 best dqsien dly found for B1: ( 0, 14, 2)
1521 19:53:56.372052 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 19:53:56.375558 Total UI for P1: 0, mck2ui 16
1523 19:53:56.378678 best dqsien dly found for B0: ( 0, 14, 4)
1524 19:53:56.382457 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1525 19:53:56.385687 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1526 19:53:56.385771
1527 19:53:56.388649 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 19:53:56.395745 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1529 19:53:56.395830 [Gating] SW calibration Done
1530 19:53:56.395934 ==
1531 19:53:56.398793 Dram Type= 6, Freq= 0, CH_1, rank 0
1532 19:53:56.405512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1533 19:53:56.405620 ==
1534 19:53:56.405751 RX Vref Scan: 0
1535 19:53:56.405846
1536 19:53:56.408647 RX Vref 0 -> 0, step: 1
1537 19:53:56.408737
1538 19:53:56.411797 RX Delay -130 -> 252, step: 16
1539 19:53:56.415673 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1540 19:53:56.418893 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1541 19:53:56.421952 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1542 19:53:56.428812 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1543 19:53:56.431982 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1544 19:53:56.435622 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1545 19:53:56.438734 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1546 19:53:56.441940 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1547 19:53:56.448865 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1548 19:53:56.451875 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1549 19:53:56.455401 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1550 19:53:56.458976 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1551 19:53:56.462150 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1552 19:53:56.469034 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1553 19:53:56.472161 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1554 19:53:56.475550 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1555 19:53:56.475630 ==
1556 19:53:56.479001 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 19:53:56.482355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 19:53:56.482440 ==
1559 19:53:56.485720 DQS Delay:
1560 19:53:56.485792 DQS0 = 0, DQS1 = 0
1561 19:53:56.485854 DQM Delay:
1562 19:53:56.489299 DQM0 = 93, DQM1 = 87
1563 19:53:56.489369 DQ Delay:
1564 19:53:56.492388 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1565 19:53:56.495944 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1566 19:53:56.498810 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1567 19:53:56.502420 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1568 19:53:56.502491
1569 19:53:56.502552
1570 19:53:56.502611 ==
1571 19:53:56.505546 Dram Type= 6, Freq= 0, CH_1, rank 0
1572 19:53:56.512132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1573 19:53:56.512210 ==
1574 19:53:56.512281
1575 19:53:56.512342
1576 19:53:56.512399 TX Vref Scan disable
1577 19:53:56.516075 == TX Byte 0 ==
1578 19:53:56.519169 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1579 19:53:56.522988 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1580 19:53:56.526260 == TX Byte 1 ==
1581 19:53:56.529442 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1582 19:53:56.533030 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1583 19:53:56.536096 ==
1584 19:53:56.539844 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 19:53:56.542857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 19:53:56.543018 ==
1587 19:53:56.554521 TX Vref=22, minBit 1, minWin=26, winSum=436
1588 19:53:56.558300 TX Vref=24, minBit 2, minWin=27, winSum=445
1589 19:53:56.561393 TX Vref=26, minBit 1, minWin=27, winSum=448
1590 19:53:56.564754 TX Vref=28, minBit 1, minWin=27, winSum=447
1591 19:53:56.568477 TX Vref=30, minBit 1, minWin=27, winSum=449
1592 19:53:56.574694 TX Vref=32, minBit 1, minWin=27, winSum=448
1593 19:53:56.578126 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 30
1594 19:53:56.578210
1595 19:53:56.581544 Final TX Range 1 Vref 30
1596 19:53:56.581623
1597 19:53:56.581688 ==
1598 19:53:56.584755 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 19:53:56.588169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 19:53:56.588242 ==
1601 19:53:56.588314
1602 19:53:56.591557
1603 19:53:56.591627 TX Vref Scan disable
1604 19:53:56.594815 == TX Byte 0 ==
1605 19:53:56.597979 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1606 19:53:56.601219 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1607 19:53:56.604694 == TX Byte 1 ==
1608 19:53:56.608327 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1609 19:53:56.611739 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1610 19:53:56.614829
1611 19:53:56.614909 [DATLAT]
1612 19:53:56.614974 Freq=800, CH1 RK0
1613 19:53:56.615036
1614 19:53:56.618477 DATLAT Default: 0xa
1615 19:53:56.618558 0, 0xFFFF, sum = 0
1616 19:53:56.621742 1, 0xFFFF, sum = 0
1617 19:53:56.621824 2, 0xFFFF, sum = 0
1618 19:53:56.624953 3, 0xFFFF, sum = 0
1619 19:53:56.625031 4, 0xFFFF, sum = 0
1620 19:53:56.628203 5, 0xFFFF, sum = 0
1621 19:53:56.628277 6, 0xFFFF, sum = 0
1622 19:53:56.631928 7, 0xFFFF, sum = 0
1623 19:53:56.632001 8, 0xFFFF, sum = 0
1624 19:53:56.635086 9, 0x0, sum = 1
1625 19:53:56.635164 10, 0x0, sum = 2
1626 19:53:56.638754 11, 0x0, sum = 3
1627 19:53:56.638832 12, 0x0, sum = 4
1628 19:53:56.641732 best_step = 10
1629 19:53:56.641805
1630 19:53:56.641866 ==
1631 19:53:56.644799 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 19:53:56.648727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 19:53:56.648804 ==
1634 19:53:56.651712 RX Vref Scan: 1
1635 19:53:56.651789
1636 19:53:56.651852 Set Vref Range= 32 -> 127
1637 19:53:56.651911
1638 19:53:56.655010 RX Vref 32 -> 127, step: 1
1639 19:53:56.655084
1640 19:53:56.658710 RX Delay -79 -> 252, step: 8
1641 19:53:56.658781
1642 19:53:56.661852 Set Vref, RX VrefLevel [Byte0]: 32
1643 19:53:56.665004 [Byte1]: 32
1644 19:53:56.665082
1645 19:53:56.668717 Set Vref, RX VrefLevel [Byte0]: 33
1646 19:53:56.671540 [Byte1]: 33
1647 19:53:56.675032
1648 19:53:56.675105 Set Vref, RX VrefLevel [Byte0]: 34
1649 19:53:56.678271 [Byte1]: 34
1650 19:53:56.682567
1651 19:53:56.682638 Set Vref, RX VrefLevel [Byte0]: 35
1652 19:53:56.685510 [Byte1]: 35
1653 19:53:56.690275
1654 19:53:56.690352 Set Vref, RX VrefLevel [Byte0]: 36
1655 19:53:56.693427 [Byte1]: 36
1656 19:53:56.697927
1657 19:53:56.697999 Set Vref, RX VrefLevel [Byte0]: 37
1658 19:53:56.701031 [Byte1]: 37
1659 19:53:56.705132
1660 19:53:56.705204 Set Vref, RX VrefLevel [Byte0]: 38
1661 19:53:56.708328 [Byte1]: 38
1662 19:53:56.712924
1663 19:53:56.712996 Set Vref, RX VrefLevel [Byte0]: 39
1664 19:53:56.715898 [Byte1]: 39
1665 19:53:56.720223
1666 19:53:56.720296 Set Vref, RX VrefLevel [Byte0]: 40
1667 19:53:56.723911 [Byte1]: 40
1668 19:53:56.727553
1669 19:53:56.727632 Set Vref, RX VrefLevel [Byte0]: 41
1670 19:53:56.731207 [Byte1]: 41
1671 19:53:56.735231
1672 19:53:56.735310 Set Vref, RX VrefLevel [Byte0]: 42
1673 19:53:56.738503 [Byte1]: 42
1674 19:53:56.742947
1675 19:53:56.743025 Set Vref, RX VrefLevel [Byte0]: 43
1676 19:53:56.746053 [Byte1]: 43
1677 19:53:56.750107
1678 19:53:56.750185 Set Vref, RX VrefLevel [Byte0]: 44
1679 19:53:56.753770 [Byte1]: 44
1680 19:53:56.758084
1681 19:53:56.758162 Set Vref, RX VrefLevel [Byte0]: 45
1682 19:53:56.761261 [Byte1]: 45
1683 19:53:56.765708
1684 19:53:56.765790 Set Vref, RX VrefLevel [Byte0]: 46
1685 19:53:56.768929 [Byte1]: 46
1686 19:53:56.773314
1687 19:53:56.773422 Set Vref, RX VrefLevel [Byte0]: 47
1688 19:53:56.776272 [Byte1]: 47
1689 19:53:56.780822
1690 19:53:56.780923 Set Vref, RX VrefLevel [Byte0]: 48
1691 19:53:56.783710 [Byte1]: 48
1692 19:53:56.788105
1693 19:53:56.788203 Set Vref, RX VrefLevel [Byte0]: 49
1694 19:53:56.791750 [Byte1]: 49
1695 19:53:56.795843
1696 19:53:56.795928 Set Vref, RX VrefLevel [Byte0]: 50
1697 19:53:56.798891 [Byte1]: 50
1698 19:53:56.803411
1699 19:53:56.803527 Set Vref, RX VrefLevel [Byte0]: 51
1700 19:53:56.806501 [Byte1]: 51
1701 19:53:56.810847
1702 19:53:56.810928 Set Vref, RX VrefLevel [Byte0]: 52
1703 19:53:56.813960 [Byte1]: 52
1704 19:53:56.818452
1705 19:53:56.818554 Set Vref, RX VrefLevel [Byte0]: 53
1706 19:53:56.821458 [Byte1]: 53
1707 19:53:56.826261
1708 19:53:56.826347 Set Vref, RX VrefLevel [Byte0]: 54
1709 19:53:56.829520 [Byte1]: 54
1710 19:53:56.833442
1711 19:53:56.833516 Set Vref, RX VrefLevel [Byte0]: 55
1712 19:53:56.836602 [Byte1]: 55
1713 19:53:56.840953
1714 19:53:56.841035 Set Vref, RX VrefLevel [Byte0]: 56
1715 19:53:56.844257 [Byte1]: 56
1716 19:53:56.848510
1717 19:53:56.848592 Set Vref, RX VrefLevel [Byte0]: 57
1718 19:53:56.851880 [Byte1]: 57
1719 19:53:56.856198
1720 19:53:56.856281 Set Vref, RX VrefLevel [Byte0]: 58
1721 19:53:56.859216 [Byte1]: 58
1722 19:53:56.863861
1723 19:53:56.863944 Set Vref, RX VrefLevel [Byte0]: 59
1724 19:53:56.866939 [Byte1]: 59
1725 19:53:56.871375
1726 19:53:56.871457 Set Vref, RX VrefLevel [Byte0]: 60
1727 19:53:56.874613 [Byte1]: 60
1728 19:53:56.879094
1729 19:53:56.879208 Set Vref, RX VrefLevel [Byte0]: 61
1730 19:53:56.882321 [Byte1]: 61
1731 19:53:56.886492
1732 19:53:56.886604 Set Vref, RX VrefLevel [Byte0]: 62
1733 19:53:56.889837 [Byte1]: 62
1734 19:53:56.893946
1735 19:53:56.894056 Set Vref, RX VrefLevel [Byte0]: 63
1736 19:53:56.896973 [Byte1]: 63
1737 19:53:56.901560
1738 19:53:56.901686 Set Vref, RX VrefLevel [Byte0]: 64
1739 19:53:56.904655 [Byte1]: 64
1740 19:53:56.909066
1741 19:53:56.909144 Set Vref, RX VrefLevel [Byte0]: 65
1742 19:53:56.912243 [Byte1]: 65
1743 19:53:56.916717
1744 19:53:56.916825 Set Vref, RX VrefLevel [Byte0]: 66
1745 19:53:56.919890 [Byte1]: 66
1746 19:53:56.924349
1747 19:53:56.924444 Set Vref, RX VrefLevel [Byte0]: 67
1748 19:53:56.927288 [Byte1]: 67
1749 19:53:56.931802
1750 19:53:56.931898 Set Vref, RX VrefLevel [Byte0]: 68
1751 19:53:56.934779 [Byte1]: 68
1752 19:53:56.939134
1753 19:53:56.939268 Set Vref, RX VrefLevel [Byte0]: 69
1754 19:53:56.942720 [Byte1]: 69
1755 19:53:56.946790
1756 19:53:56.946896 Set Vref, RX VrefLevel [Byte0]: 70
1757 19:53:56.950356 [Byte1]: 70
1758 19:53:56.954561
1759 19:53:56.954644 Set Vref, RX VrefLevel [Byte0]: 71
1760 19:53:56.957776 [Byte1]: 71
1761 19:53:56.961976
1762 19:53:56.962059 Set Vref, RX VrefLevel [Byte0]: 72
1763 19:53:56.964870 [Byte1]: 72
1764 19:53:56.969399
1765 19:53:56.969482 Set Vref, RX VrefLevel [Byte0]: 73
1766 19:53:56.972672 [Byte1]: 73
1767 19:53:56.976944
1768 19:53:56.977029 Set Vref, RX VrefLevel [Byte0]: 74
1769 19:53:56.980139 [Byte1]: 74
1770 19:53:56.984352
1771 19:53:56.984429 Final RX Vref Byte 0 = 53 to rank0
1772 19:53:56.987632 Final RX Vref Byte 1 = 55 to rank0
1773 19:53:56.990769 Final RX Vref Byte 0 = 53 to rank1
1774 19:53:56.994413 Final RX Vref Byte 1 = 55 to rank1==
1775 19:53:56.997301 Dram Type= 6, Freq= 0, CH_1, rank 0
1776 19:53:57.004459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1777 19:53:57.004543 ==
1778 19:53:57.004608 DQS Delay:
1779 19:53:57.004677 DQS0 = 0, DQS1 = 0
1780 19:53:57.007564 DQM Delay:
1781 19:53:57.007648 DQM0 = 95, DQM1 = 89
1782 19:53:57.011164 DQ Delay:
1783 19:53:57.014026 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1784 19:53:57.017837 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1785 19:53:57.020935 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1786 19:53:57.024090 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1787 19:53:57.024181
1788 19:53:57.024250
1789 19:53:57.030947 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1790 19:53:57.034026 CH1 RK0: MR19=606, MR18=2B48
1791 19:53:57.041025 CH1_RK0: MR19=0x606, MR18=0x2B48, DQSOSC=391, MR23=63, INC=96, DEC=64
1792 19:53:57.041104
1793 19:53:57.044077 ----->DramcWriteLeveling(PI) begin...
1794 19:53:57.044156 ==
1795 19:53:57.047736 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 19:53:57.050958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 19:53:57.051040 ==
1798 19:53:57.053898 Write leveling (Byte 0): 27 => 27
1799 19:53:57.057464 Write leveling (Byte 1): 29 => 29
1800 19:53:57.061085 DramcWriteLeveling(PI) end<-----
1801 19:53:57.061164
1802 19:53:57.061231 ==
1803 19:53:57.064169 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 19:53:57.067491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 19:53:57.067570 ==
1806 19:53:57.070689 [Gating] SW mode calibration
1807 19:53:57.077721 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1808 19:53:57.084087 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1809 19:53:57.087565 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1810 19:53:57.090866 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1811 19:53:57.097499 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1812 19:53:57.100728 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 19:53:57.104472 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 19:53:57.110963 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 19:53:57.114473 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 19:53:57.117819 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 19:53:57.124165 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 19:53:57.127660 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 19:53:57.130878 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 19:53:57.137625 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 19:53:57.141332 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 19:53:57.144455 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 19:53:57.150771 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 19:53:57.154580 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 19:53:57.157659 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1826 19:53:57.160700 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 19:53:57.167395 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 19:53:57.171206 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 19:53:57.174344 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 19:53:57.180771 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 19:53:57.183955 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 19:53:57.187867 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 19:53:57.193997 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 19:53:57.197429 0 9 4 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
1835 19:53:57.200824 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1836 19:53:57.207541 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 19:53:57.211083 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 19:53:57.214669 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 19:53:57.220743 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 19:53:57.224393 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 19:53:57.227438 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
1842 19:53:57.234179 0 10 4 | B1->B0 | 2b2b 3131 | 1 1 | (1 0) (1 0)
1843 19:53:57.237513 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 19:53:57.241038 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 19:53:57.244392 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 19:53:57.251246 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 19:53:57.254411 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 19:53:57.258234 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 19:53:57.264215 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 19:53:57.267442 0 11 4 | B1->B0 | 3c3c 2727 | 0 0 | (0 0) (0 0)
1851 19:53:57.270995 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
1852 19:53:57.277773 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 19:53:57.281509 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 19:53:57.284803 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 19:53:57.291099 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 19:53:57.294314 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 19:53:57.298147 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 19:53:57.304784 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1859 19:53:57.307617 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 19:53:57.311307 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 19:53:57.317843 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 19:53:57.321150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 19:53:57.324377 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 19:53:57.328039 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 19:53:57.334656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 19:53:57.337685 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 19:53:57.341337 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 19:53:57.347955 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 19:53:57.351246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 19:53:57.354427 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 19:53:57.361261 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 19:53:57.364477 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 19:53:57.367945 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1874 19:53:57.374844 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1875 19:53:57.377959 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1876 19:53:57.381622 Total UI for P1: 0, mck2ui 16
1877 19:53:57.384866 best dqsien dly found for B0: ( 0, 14, 6)
1878 19:53:57.387935 Total UI for P1: 0, mck2ui 16
1879 19:53:57.391748 best dqsien dly found for B1: ( 0, 14, 2)
1880 19:53:57.394838 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1881 19:53:57.398044 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1882 19:53:57.398155
1883 19:53:57.401179 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1884 19:53:57.404916 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1885 19:53:57.408055 [Gating] SW calibration Done
1886 19:53:57.408130 ==
1887 19:53:57.411220 Dram Type= 6, Freq= 0, CH_1, rank 1
1888 19:53:57.414782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1889 19:53:57.414883 ==
1890 19:53:57.417919 RX Vref Scan: 0
1891 19:53:57.418025
1892 19:53:57.421730 RX Vref 0 -> 0, step: 1
1893 19:53:57.421835
1894 19:53:57.421926 RX Delay -130 -> 252, step: 16
1895 19:53:57.427952 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1896 19:53:57.431554 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1897 19:53:57.434982 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1898 19:53:57.438249 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1899 19:53:57.441429 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1900 19:53:57.448410 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1901 19:53:57.451400 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1902 19:53:57.454957 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1903 19:53:57.458359 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1904 19:53:57.461470 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1905 19:53:57.467976 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1906 19:53:57.471908 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1907 19:53:57.475002 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1908 19:53:57.478422 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1909 19:53:57.481822 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1910 19:53:57.488264 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1911 19:53:57.488374 ==
1912 19:53:57.491355 Dram Type= 6, Freq= 0, CH_1, rank 1
1913 19:53:57.495068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1914 19:53:57.495172 ==
1915 19:53:57.495282 DQS Delay:
1916 19:53:57.498252 DQS0 = 0, DQS1 = 0
1917 19:53:57.498359 DQM Delay:
1918 19:53:57.501311 DQM0 = 93, DQM1 = 90
1919 19:53:57.501418 DQ Delay:
1920 19:53:57.505110 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1921 19:53:57.508288 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1922 19:53:57.511416 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1923 19:53:57.515210 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1924 19:53:57.515320
1925 19:53:57.515411
1926 19:53:57.515517 ==
1927 19:53:57.518529 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 19:53:57.521943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 19:53:57.522054 ==
1930 19:53:57.522145
1931 19:53:57.522251
1932 19:53:57.524912 TX Vref Scan disable
1933 19:53:57.528207 == TX Byte 0 ==
1934 19:53:57.532053 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1935 19:53:57.535238 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1936 19:53:57.538464 == TX Byte 1 ==
1937 19:53:57.541622 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1938 19:53:57.545426 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1939 19:53:57.545542 ==
1940 19:53:57.548428 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 19:53:57.554989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 19:53:57.555106 ==
1943 19:53:57.566425 TX Vref=22, minBit 1, minWin=26, winSum=442
1944 19:53:57.569993 TX Vref=24, minBit 1, minWin=26, winSum=445
1945 19:53:57.573409 TX Vref=26, minBit 2, minWin=27, winSum=451
1946 19:53:57.576600 TX Vref=28, minBit 2, minWin=27, winSum=449
1947 19:53:57.580219 TX Vref=30, minBit 1, minWin=27, winSum=452
1948 19:53:57.583060 TX Vref=32, minBit 2, minWin=27, winSum=450
1949 19:53:57.589869 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1950 19:53:57.589953
1951 19:53:57.593357 Final TX Range 1 Vref 30
1952 19:53:57.593434
1953 19:53:57.593498 ==
1954 19:53:57.596805 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 19:53:57.599885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 19:53:57.599966 ==
1957 19:53:57.600029
1958 19:53:57.603289
1959 19:53:57.603365 TX Vref Scan disable
1960 19:53:57.606301 == TX Byte 0 ==
1961 19:53:57.610062 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1962 19:53:57.613311 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1963 19:53:57.616476 == TX Byte 1 ==
1964 19:53:57.619694 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1965 19:53:57.623491 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1966 19:53:57.623572
1967 19:53:57.626736 [DATLAT]
1968 19:53:57.626818 Freq=800, CH1 RK1
1969 19:53:57.626884
1970 19:53:57.629878 DATLAT Default: 0xa
1971 19:53:57.629956 0, 0xFFFF, sum = 0
1972 19:53:57.633315 1, 0xFFFF, sum = 0
1973 19:53:57.633396 2, 0xFFFF, sum = 0
1974 19:53:57.636508 3, 0xFFFF, sum = 0
1975 19:53:57.636601 4, 0xFFFF, sum = 0
1976 19:53:57.639659 5, 0xFFFF, sum = 0
1977 19:53:57.639745 6, 0xFFFF, sum = 0
1978 19:53:57.643339 7, 0xFFFF, sum = 0
1979 19:53:57.646596 8, 0xFFFF, sum = 0
1980 19:53:57.646676 9, 0x0, sum = 1
1981 19:53:57.646739 10, 0x0, sum = 2
1982 19:53:57.649793 11, 0x0, sum = 3
1983 19:53:57.649868 12, 0x0, sum = 4
1984 19:53:57.653010 best_step = 10
1985 19:53:57.653088
1986 19:53:57.653151 ==
1987 19:53:57.656589 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 19:53:57.659600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 19:53:57.659688 ==
1990 19:53:57.663280 RX Vref Scan: 0
1991 19:53:57.663355
1992 19:53:57.663433 RX Vref 0 -> 0, step: 1
1993 19:53:57.663538
1994 19:53:57.666953 RX Delay -63 -> 252, step: 8
1995 19:53:57.673731 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1996 19:53:57.676649 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1997 19:53:57.679936 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1998 19:53:57.683215 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1999 19:53:57.687014 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2000 19:53:57.690296 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2001 19:53:57.696549 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2002 19:53:57.699981 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2003 19:53:57.703663 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2004 19:53:57.706594 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2005 19:53:57.709923 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2006 19:53:57.713517 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2007 19:53:57.719835 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2008 19:53:57.723661 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2009 19:53:57.726802 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2010 19:53:57.730070 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2011 19:53:57.730151 ==
2012 19:53:57.733884 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 19:53:57.740819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 19:53:57.740900 ==
2015 19:53:57.740987 DQS Delay:
2016 19:53:57.741068 DQS0 = 0, DQS1 = 0
2017 19:53:57.743246 DQM Delay:
2018 19:53:57.743327 DQM0 = 97, DQM1 = 91
2019 19:53:57.747058 DQ Delay:
2020 19:53:57.750200 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2021 19:53:57.753360 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2022 19:53:57.757249 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2023 19:53:57.760167 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2024 19:53:57.760244
2025 19:53:57.760326
2026 19:53:57.767074 [DQSOSCAuto] RK1, (LSB)MR18= 0x4913, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2027 19:53:57.770289 CH1 RK1: MR19=606, MR18=4913
2028 19:53:57.777119 CH1_RK1: MR19=0x606, MR18=0x4913, DQSOSC=391, MR23=63, INC=96, DEC=64
2029 19:53:57.780063 [RxdqsGatingPostProcess] freq 800
2030 19:53:57.783792 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2031 19:53:57.786741 Pre-setting of DQS Precalculation
2032 19:53:57.793696 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2033 19:53:57.800346 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2034 19:53:57.806677 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2035 19:53:57.806760
2036 19:53:57.806845
2037 19:53:57.810008 [Calibration Summary] 1600 Mbps
2038 19:53:57.810085 CH 0, Rank 0
2039 19:53:57.813430 SW Impedance : PASS
2040 19:53:57.817088 DUTY Scan : NO K
2041 19:53:57.817169 ZQ Calibration : PASS
2042 19:53:57.819947 Jitter Meter : NO K
2043 19:53:57.823255 CBT Training : PASS
2044 19:53:57.823338 Write leveling : PASS
2045 19:53:57.826967 RX DQS gating : PASS
2046 19:53:57.830117 RX DQ/DQS(RDDQC) : PASS
2047 19:53:57.830203 TX DQ/DQS : PASS
2048 19:53:57.833707 RX DATLAT : PASS
2049 19:53:57.833827 RX DQ/DQS(Engine): PASS
2050 19:53:57.836870 TX OE : NO K
2051 19:53:57.836980 All Pass.
2052 19:53:57.837077
2053 19:53:57.839969 CH 0, Rank 1
2054 19:53:57.840066 SW Impedance : PASS
2055 19:53:57.843766 DUTY Scan : NO K
2056 19:53:57.846903 ZQ Calibration : PASS
2057 19:53:57.847012 Jitter Meter : NO K
2058 19:53:57.850291 CBT Training : PASS
2059 19:53:57.854194 Write leveling : PASS
2060 19:53:57.854314 RX DQS gating : PASS
2061 19:53:57.857375 RX DQ/DQS(RDDQC) : PASS
2062 19:53:57.860483 TX DQ/DQS : PASS
2063 19:53:57.860588 RX DATLAT : PASS
2064 19:53:57.863468 RX DQ/DQS(Engine): PASS
2065 19:53:57.867258 TX OE : NO K
2066 19:53:57.867364 All Pass.
2067 19:53:57.867467
2068 19:53:57.867560 CH 1, Rank 0
2069 19:53:57.870424 SW Impedance : PASS
2070 19:53:57.874213 DUTY Scan : NO K
2071 19:53:57.874322 ZQ Calibration : PASS
2072 19:53:57.878180 Jitter Meter : NO K
2073 19:53:57.878280 CBT Training : PASS
2074 19:53:57.881953 Write leveling : PASS
2075 19:53:57.882056 RX DQS gating : PASS
2076 19:53:57.885701 RX DQ/DQS(RDDQC) : PASS
2077 19:53:57.885812 TX DQ/DQS : PASS
2078 19:53:57.888908 RX DATLAT : PASS
2079 19:53:57.892724 RX DQ/DQS(Engine): PASS
2080 19:53:57.892837 TX OE : NO K
2081 19:53:57.895819 All Pass.
2082 19:53:57.895919
2083 19:53:57.896031 CH 1, Rank 1
2084 19:53:57.898898 SW Impedance : PASS
2085 19:53:57.899000 DUTY Scan : NO K
2086 19:53:57.902586 ZQ Calibration : PASS
2087 19:53:57.905819 Jitter Meter : NO K
2088 19:53:57.905926 CBT Training : PASS
2089 19:53:57.908941 Write leveling : PASS
2090 19:53:57.912454 RX DQS gating : PASS
2091 19:53:57.912553 RX DQ/DQS(RDDQC) : PASS
2092 19:53:57.915997 TX DQ/DQS : PASS
2093 19:53:57.916098 RX DATLAT : PASS
2094 19:53:57.919421 RX DQ/DQS(Engine): PASS
2095 19:53:57.922690 TX OE : NO K
2096 19:53:57.922798 All Pass.
2097 19:53:57.922902
2098 19:53:57.925657 DramC Write-DBI off
2099 19:53:57.925757 PER_BANK_REFRESH: Hybrid Mode
2100 19:53:57.929423 TX_TRACKING: ON
2101 19:53:57.932352 [GetDramInforAfterCalByMRR] Vendor 6.
2102 19:53:57.935770 [GetDramInforAfterCalByMRR] Revision 606.
2103 19:53:57.939073 [GetDramInforAfterCalByMRR] Revision 2 0.
2104 19:53:57.939178 MR0 0x3b3b
2105 19:53:57.942702 MR8 0x5151
2106 19:53:57.946045 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 19:53:57.946152
2108 19:53:57.946254 MR0 0x3b3b
2109 19:53:57.949555 MR8 0x5151
2110 19:53:57.952622 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 19:53:57.952724
2112 19:53:57.959102 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2113 19:53:57.962719 [FAST_K] Save calibration result to emmc
2114 19:53:57.965827 [FAST_K] Save calibration result to emmc
2115 19:53:57.969555 dram_init: config_dvfs: 1
2116 19:53:57.972657 dramc_set_vcore_voltage set vcore to 662500
2117 19:53:57.975891 Read voltage for 1200, 2
2118 19:53:57.975995 Vio18 = 0
2119 19:53:57.979049 Vcore = 662500
2120 19:53:57.979154 Vdram = 0
2121 19:53:57.979250 Vddq = 0
2122 19:53:57.982939 Vmddr = 0
2123 19:53:57.986068 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2124 19:53:57.992900 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2125 19:53:57.993026 MEM_TYPE=3, freq_sel=15
2126 19:53:57.996419 sv_algorithm_assistance_LP4_1600
2127 19:53:57.999327 ============ PULL DRAM RESETB DOWN ============
2128 19:53:58.006176 ========== PULL DRAM RESETB DOWN end =========
2129 19:53:58.009225 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 19:53:58.013019 ===================================
2131 19:53:58.016062 LPDDR4 DRAM CONFIGURATION
2132 19:53:58.019202 ===================================
2133 19:53:58.019309 EX_ROW_EN[0] = 0x0
2134 19:53:58.023018 EX_ROW_EN[1] = 0x0
2135 19:53:58.023124 LP4Y_EN = 0x0
2136 19:53:58.026014 WORK_FSP = 0x0
2137 19:53:58.026134 WL = 0x4
2138 19:53:58.029435 RL = 0x4
2139 19:53:58.032843 BL = 0x2
2140 19:53:58.032960 RPST = 0x0
2141 19:53:58.036206 RD_PRE = 0x0
2142 19:53:58.036289 WR_PRE = 0x1
2143 19:53:58.039331 WR_PST = 0x0
2144 19:53:58.039440 DBI_WR = 0x0
2145 19:53:58.042500 DBI_RD = 0x0
2146 19:53:58.042581 OTF = 0x1
2147 19:53:58.046264 ===================================
2148 19:53:58.049691 ===================================
2149 19:53:58.053114 ANA top config
2150 19:53:58.053212 ===================================
2151 19:53:58.056311 DLL_ASYNC_EN = 0
2152 19:53:58.059434 ALL_SLAVE_EN = 0
2153 19:53:58.062835 NEW_RANK_MODE = 1
2154 19:53:58.066277 DLL_IDLE_MODE = 1
2155 19:53:58.066376 LP45_APHY_COMB_EN = 1
2156 19:53:58.069941 TX_ODT_DIS = 1
2157 19:53:58.073232 NEW_8X_MODE = 1
2158 19:53:58.076113 ===================================
2159 19:53:58.079792 ===================================
2160 19:53:58.082889 data_rate = 2400
2161 19:53:58.086002 CKR = 1
2162 19:53:58.086084 DQ_P2S_RATIO = 8
2163 19:53:58.089818 ===================================
2164 19:53:58.092905 CA_P2S_RATIO = 8
2165 19:53:58.096214 DQ_CA_OPEN = 0
2166 19:53:58.099780 DQ_SEMI_OPEN = 0
2167 19:53:58.102760 CA_SEMI_OPEN = 0
2168 19:53:58.106288 CA_FULL_RATE = 0
2169 19:53:58.106386 DQ_CKDIV4_EN = 0
2170 19:53:58.109617 CA_CKDIV4_EN = 0
2171 19:53:58.113185 CA_PREDIV_EN = 0
2172 19:53:58.116392 PH8_DLY = 17
2173 19:53:58.119510 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2174 19:53:58.123043 DQ_AAMCK_DIV = 4
2175 19:53:58.123122 CA_AAMCK_DIV = 4
2176 19:53:58.126266 CA_ADMCK_DIV = 4
2177 19:53:58.129495 DQ_TRACK_CA_EN = 0
2178 19:53:58.132675 CA_PICK = 1200
2179 19:53:58.136323 CA_MCKIO = 1200
2180 19:53:58.139707 MCKIO_SEMI = 0
2181 19:53:58.143082 PLL_FREQ = 2366
2182 19:53:58.143164 DQ_UI_PI_RATIO = 32
2183 19:53:58.146560 CA_UI_PI_RATIO = 0
2184 19:53:58.149624 ===================================
2185 19:53:58.152739 ===================================
2186 19:53:58.156498 memory_type:LPDDR4
2187 19:53:58.159617 GP_NUM : 10
2188 19:53:58.159695 SRAM_EN : 1
2189 19:53:58.163246 MD32_EN : 0
2190 19:53:58.166571 ===================================
2191 19:53:58.166686 [ANA_INIT] >>>>>>>>>>>>>>
2192 19:53:58.169851 <<<<<< [CONFIGURE PHASE]: ANA_TX
2193 19:53:58.173369 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2194 19:53:58.176238 ===================================
2195 19:53:58.179778 data_rate = 2400,PCW = 0X5b00
2196 19:53:58.182906 ===================================
2197 19:53:58.186349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2198 19:53:58.193062 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2199 19:53:58.196197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2200 19:53:58.203100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2201 19:53:58.206393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2202 19:53:58.210031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2203 19:53:58.210109 [ANA_INIT] flow start
2204 19:53:58.213071 [ANA_INIT] PLL >>>>>>>>
2205 19:53:58.216547 [ANA_INIT] PLL <<<<<<<<
2206 19:53:58.219537 [ANA_INIT] MIDPI >>>>>>>>
2207 19:53:58.219614 [ANA_INIT] MIDPI <<<<<<<<
2208 19:53:58.223074 [ANA_INIT] DLL >>>>>>>>
2209 19:53:58.226711 [ANA_INIT] DLL <<<<<<<<
2210 19:53:58.226797 [ANA_INIT] flow end
2211 19:53:58.229837 ============ LP4 DIFF to SE enter ============
2212 19:53:58.236774 ============ LP4 DIFF to SE exit ============
2213 19:53:58.236858 [ANA_INIT] <<<<<<<<<<<<<
2214 19:53:58.239860 [Flow] Enable top DCM control >>>>>
2215 19:53:58.242989 [Flow] Enable top DCM control <<<<<
2216 19:53:58.246591 Enable DLL master slave shuffle
2217 19:53:58.253266 ==============================================================
2218 19:53:58.253350 Gating Mode config
2219 19:53:58.260101 ==============================================================
2220 19:53:58.263308 Config description:
2221 19:53:58.273390 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2222 19:53:58.276349 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2223 19:53:58.283299 SELPH_MODE 0: By rank 1: By Phase
2224 19:53:58.290091 ==============================================================
2225 19:53:58.290173 GAT_TRACK_EN = 1
2226 19:53:58.293193 RX_GATING_MODE = 2
2227 19:53:58.296721 RX_GATING_TRACK_MODE = 2
2228 19:53:58.299897 SELPH_MODE = 1
2229 19:53:58.303398 PICG_EARLY_EN = 1
2230 19:53:58.306393 VALID_LAT_VALUE = 1
2231 19:53:58.313301 ==============================================================
2232 19:53:58.316578 Enter into Gating configuration >>>>
2233 19:53:58.320257 Exit from Gating configuration <<<<
2234 19:53:58.323278 Enter into DVFS_PRE_config >>>>>
2235 19:53:58.333300 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2236 19:53:58.336291 Exit from DVFS_PRE_config <<<<<
2237 19:53:58.340083 Enter into PICG configuration >>>>
2238 19:53:58.343267 Exit from PICG configuration <<<<
2239 19:53:58.346401 [RX_INPUT] configuration >>>>>
2240 19:53:58.346503 [RX_INPUT] configuration <<<<<
2241 19:53:58.353152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2242 19:53:58.360366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2243 19:53:58.363467 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2244 19:53:58.369634 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2245 19:53:58.376681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2246 19:53:58.383014 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2247 19:53:58.386689 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2248 19:53:58.389620 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2249 19:53:58.396333 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2250 19:53:58.399580 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2251 19:53:58.403355 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2252 19:53:58.406407 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2253 19:53:58.410317 ===================================
2254 19:53:58.413417 LPDDR4 DRAM CONFIGURATION
2255 19:53:58.416706 ===================================
2256 19:53:58.419897 EX_ROW_EN[0] = 0x0
2257 19:53:58.419983 EX_ROW_EN[1] = 0x0
2258 19:53:58.423216 LP4Y_EN = 0x0
2259 19:53:58.423326 WORK_FSP = 0x0
2260 19:53:58.426784 WL = 0x4
2261 19:53:58.426891 RL = 0x4
2262 19:53:58.429890 BL = 0x2
2263 19:53:58.429996 RPST = 0x0
2264 19:53:58.433036 RD_PRE = 0x0
2265 19:53:58.433143 WR_PRE = 0x1
2266 19:53:58.436823 WR_PST = 0x0
2267 19:53:58.439801 DBI_WR = 0x0
2268 19:53:58.439903 DBI_RD = 0x0
2269 19:53:58.443158 OTF = 0x1
2270 19:53:58.446255 ===================================
2271 19:53:58.450009 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2272 19:53:58.453040 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2273 19:53:58.456708 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2274 19:53:58.459820 ===================================
2275 19:53:58.463394 LPDDR4 DRAM CONFIGURATION
2276 19:53:58.466461 ===================================
2277 19:53:58.469959 EX_ROW_EN[0] = 0x10
2278 19:53:58.470045 EX_ROW_EN[1] = 0x0
2279 19:53:58.473081 LP4Y_EN = 0x0
2280 19:53:58.473175 WORK_FSP = 0x0
2281 19:53:58.476869 WL = 0x4
2282 19:53:58.476956 RL = 0x4
2283 19:53:58.479975 BL = 0x2
2284 19:53:58.480055 RPST = 0x0
2285 19:53:58.483143 RD_PRE = 0x0
2286 19:53:58.483256 WR_PRE = 0x1
2287 19:53:58.486972 WR_PST = 0x0
2288 19:53:58.487085 DBI_WR = 0x0
2289 19:53:58.490081 DBI_RD = 0x0
2290 19:53:58.490164 OTF = 0x1
2291 19:53:58.493401 ===================================
2292 19:53:58.500260 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2293 19:53:58.500339 ==
2294 19:53:58.503138 Dram Type= 6, Freq= 0, CH_0, rank 0
2295 19:53:58.507023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2296 19:53:58.510097 ==
2297 19:53:58.510197 [Duty_Offset_Calibration]
2298 19:53:58.513606 B0:2 B1:1 CA:1
2299 19:53:58.513707
2300 19:53:58.516792 [DutyScan_Calibration_Flow] k_type=0
2301 19:53:58.525384
2302 19:53:58.525484 ==CLK 0==
2303 19:53:58.528564 Final CLK duty delay cell = 0
2304 19:53:58.532097 [0] MAX Duty = 5218%(X100), DQS PI = 24
2305 19:53:58.535187 [0] MIN Duty = 4875%(X100), DQS PI = 0
2306 19:53:58.535284 [0] AVG Duty = 5046%(X100)
2307 19:53:58.535383
2308 19:53:58.538324 CH0 CLK Duty spec in!! Max-Min= 343%
2309 19:53:58.545210 [DutyScan_Calibration_Flow] ====Done====
2310 19:53:58.545288
2311 19:53:58.548736 [DutyScan_Calibration_Flow] k_type=1
2312 19:53:58.563809
2313 19:53:58.563895 ==DQS 0 ==
2314 19:53:58.566952 Final DQS duty delay cell = -4
2315 19:53:58.570560 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2316 19:53:58.573728 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2317 19:53:58.577418 [-4] AVG Duty = 4937%(X100)
2318 19:53:58.577525
2319 19:53:58.577625 ==DQS 1 ==
2320 19:53:58.580589 Final DQS duty delay cell = 0
2321 19:53:58.583806 [0] MAX Duty = 5187%(X100), DQS PI = 62
2322 19:53:58.587083 [0] MIN Duty = 5000%(X100), DQS PI = 36
2323 19:53:58.587182 [0] AVG Duty = 5093%(X100)
2324 19:53:58.590965
2325 19:53:58.594101 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2326 19:53:58.594173
2327 19:53:58.597332 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2328 19:53:58.601018 [DutyScan_Calibration_Flow] ====Done====
2329 19:53:58.601116
2330 19:53:58.604167 [DutyScan_Calibration_Flow] k_type=3
2331 19:53:58.620721
2332 19:53:58.620809 ==DQM 0 ==
2333 19:53:58.624055 Final DQM duty delay cell = 0
2334 19:53:58.627226 [0] MAX Duty = 5156%(X100), DQS PI = 26
2335 19:53:58.630293 [0] MIN Duty = 4906%(X100), DQS PI = 52
2336 19:53:58.633615 [0] AVG Duty = 5031%(X100)
2337 19:53:58.633696
2338 19:53:58.633762 ==DQM 1 ==
2339 19:53:58.637323 Final DQM duty delay cell = 0
2340 19:53:58.640825 [0] MAX Duty = 5093%(X100), DQS PI = 0
2341 19:53:58.643889 [0] MIN Duty = 5031%(X100), DQS PI = 34
2342 19:53:58.643965 [0] AVG Duty = 5062%(X100)
2343 19:53:58.647444
2344 19:53:58.650725 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2345 19:53:58.650832
2346 19:53:58.654268 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2347 19:53:58.657434 [DutyScan_Calibration_Flow] ====Done====
2348 19:53:58.657535
2349 19:53:58.660602 [DutyScan_Calibration_Flow] k_type=2
2350 19:53:58.676902
2351 19:53:58.677003 ==DQ 0 ==
2352 19:53:58.680428 Final DQ duty delay cell = 0
2353 19:53:58.683997 [0] MAX Duty = 5031%(X100), DQS PI = 24
2354 19:53:58.687128 [0] MIN Duty = 4875%(X100), DQS PI = 62
2355 19:53:58.687203 [0] AVG Duty = 4953%(X100)
2356 19:53:58.687287
2357 19:53:58.690358 ==DQ 1 ==
2358 19:53:58.694120 Final DQ duty delay cell = 0
2359 19:53:58.697310 [0] MAX Duty = 5062%(X100), DQS PI = 8
2360 19:53:58.700425 [0] MIN Duty = 4938%(X100), DQS PI = 36
2361 19:53:58.700522 [0] AVG Duty = 5000%(X100)
2362 19:53:58.700636
2363 19:53:58.703653 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2364 19:53:58.703727
2365 19:53:58.706859 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2366 19:53:58.713697 [DutyScan_Calibration_Flow] ====Done====
2367 19:53:58.713829 ==
2368 19:53:58.716960 Dram Type= 6, Freq= 0, CH_1, rank 0
2369 19:53:58.720167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2370 19:53:58.720259 ==
2371 19:53:58.724037 [Duty_Offset_Calibration]
2372 19:53:58.724145 B0:1 B1:0 CA:0
2373 19:53:58.724243
2374 19:53:58.727187 [DutyScan_Calibration_Flow] k_type=0
2375 19:53:58.736300
2376 19:53:58.736393 ==CLK 0==
2377 19:53:58.739213 Final CLK duty delay cell = -4
2378 19:53:58.742710 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2379 19:53:58.745866 [-4] MIN Duty = 4907%(X100), DQS PI = 10
2380 19:53:58.749399 [-4] AVG Duty = 4953%(X100)
2381 19:53:58.749495
2382 19:53:58.752449 CH1 CLK Duty spec in!! Max-Min= 93%
2383 19:53:58.756010 [DutyScan_Calibration_Flow] ====Done====
2384 19:53:58.756091
2385 19:53:58.759509 [DutyScan_Calibration_Flow] k_type=1
2386 19:53:58.775552
2387 19:53:58.775648 ==DQS 0 ==
2388 19:53:58.779165 Final DQS duty delay cell = 0
2389 19:53:58.782385 [0] MAX Duty = 5094%(X100), DQS PI = 26
2390 19:53:58.785952 [0] MIN Duty = 4875%(X100), DQS PI = 0
2391 19:53:58.786062 [0] AVG Duty = 4984%(X100)
2392 19:53:58.786157
2393 19:53:58.788998 ==DQS 1 ==
2394 19:53:58.792458 Final DQS duty delay cell = 0
2395 19:53:58.795645 [0] MAX Duty = 5187%(X100), DQS PI = 20
2396 19:53:58.799547 [0] MIN Duty = 4969%(X100), DQS PI = 8
2397 19:53:58.799630 [0] AVG Duty = 5078%(X100)
2398 19:53:58.799703
2399 19:53:58.806213 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2400 19:53:58.806296
2401 19:53:58.809361 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2402 19:53:58.812552 [DutyScan_Calibration_Flow] ====Done====
2403 19:53:58.812636
2404 19:53:58.816242 [DutyScan_Calibration_Flow] k_type=3
2405 19:53:58.832173
2406 19:53:58.832257 ==DQM 0 ==
2407 19:53:58.835935 Final DQM duty delay cell = 0
2408 19:53:58.839086 [0] MAX Duty = 5156%(X100), DQS PI = 4
2409 19:53:58.842351 [0] MIN Duty = 5031%(X100), DQS PI = 0
2410 19:53:58.842434 [0] AVG Duty = 5093%(X100)
2411 19:53:58.845574
2412 19:53:58.845656 ==DQM 1 ==
2413 19:53:58.849322 Final DQM duty delay cell = 0
2414 19:53:58.852426 [0] MAX Duty = 5031%(X100), DQS PI = 16
2415 19:53:58.856011 [0] MIN Duty = 4907%(X100), DQS PI = 36
2416 19:53:58.856092 [0] AVG Duty = 4969%(X100)
2417 19:53:58.856157
2418 19:53:58.862594 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2419 19:53:58.862676
2420 19:53:58.865872 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2421 19:53:58.868929 [DutyScan_Calibration_Flow] ====Done====
2422 19:53:58.869028
2423 19:53:58.872452 [DutyScan_Calibration_Flow] k_type=2
2424 19:53:58.888324
2425 19:53:58.888422 ==DQ 0 ==
2426 19:53:58.891315 Final DQ duty delay cell = -4
2427 19:53:58.894983 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2428 19:53:58.898382 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2429 19:53:58.898477 [-4] AVG Duty = 5000%(X100)
2430 19:53:58.898542
2431 19:53:58.901837 ==DQ 1 ==
2432 19:53:58.905026 Final DQ duty delay cell = 0
2433 19:53:58.908477 [0] MAX Duty = 5125%(X100), DQS PI = 20
2434 19:53:58.911577 [0] MIN Duty = 4938%(X100), DQS PI = 34
2435 19:53:58.911677 [0] AVG Duty = 5031%(X100)
2436 19:53:58.911742
2437 19:53:58.914708 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2438 19:53:58.918320
2439 19:53:58.921456 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2440 19:53:58.925205 [DutyScan_Calibration_Flow] ====Done====
2441 19:53:58.928454 nWR fixed to 30
2442 19:53:58.928537 [ModeRegInit_LP4] CH0 RK0
2443 19:53:58.931697 [ModeRegInit_LP4] CH0 RK1
2444 19:53:58.934816 [ModeRegInit_LP4] CH1 RK0
2445 19:53:58.934893 [ModeRegInit_LP4] CH1 RK1
2446 19:53:58.938594 match AC timing 7
2447 19:53:58.941752 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2448 19:53:58.944924 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2449 19:53:58.952077 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2450 19:53:58.955172 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2451 19:53:58.961968 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2452 19:53:58.962078 ==
2453 19:53:58.965172 Dram Type= 6, Freq= 0, CH_0, rank 0
2454 19:53:58.968270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2455 19:53:58.968350 ==
2456 19:53:58.975075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2457 19:53:58.978705 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2458 19:53:58.988648 [CA 0] Center 39 (8~70) winsize 63
2459 19:53:58.991791 [CA 1] Center 39 (8~70) winsize 63
2460 19:53:58.994842 [CA 2] Center 35 (5~66) winsize 62
2461 19:53:58.997997 [CA 3] Center 34 (4~65) winsize 62
2462 19:53:59.001345 [CA 4] Center 33 (3~64) winsize 62
2463 19:53:59.004751 [CA 5] Center 32 (3~62) winsize 60
2464 19:53:59.004829
2465 19:53:59.008247 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2466 19:53:59.008351
2467 19:53:59.011725 [CATrainingPosCal] consider 1 rank data
2468 19:53:59.014726 u2DelayCellTimex100 = 270/100 ps
2469 19:53:59.018430 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2470 19:53:59.021961 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2471 19:53:59.028515 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2472 19:53:59.031735 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2473 19:53:59.035490 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2474 19:53:59.038713 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2475 19:53:59.038789
2476 19:53:59.041973 CA PerBit enable=1, Macro0, CA PI delay=32
2477 19:53:59.042058
2478 19:53:59.044942 [CBTSetCACLKResult] CA Dly = 32
2479 19:53:59.045027 CS Dly: 6 (0~37)
2480 19:53:59.045094 ==
2481 19:53:59.048704 Dram Type= 6, Freq= 0, CH_0, rank 1
2482 19:53:59.055041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2483 19:53:59.055126 ==
2484 19:53:59.058772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2485 19:53:59.065102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2486 19:53:59.073827 [CA 0] Center 38 (8~69) winsize 62
2487 19:53:59.077305 [CA 1] Center 38 (8~69) winsize 62
2488 19:53:59.080474 [CA 2] Center 35 (4~66) winsize 63
2489 19:53:59.084250 [CA 3] Center 34 (4~65) winsize 62
2490 19:53:59.087280 [CA 4] Center 33 (3~64) winsize 62
2491 19:53:59.090964 [CA 5] Center 32 (3~62) winsize 60
2492 19:53:59.091043
2493 19:53:59.094100 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2494 19:53:59.094184
2495 19:53:59.097154 [CATrainingPosCal] consider 2 rank data
2496 19:53:59.100606 u2DelayCellTimex100 = 270/100 ps
2497 19:53:59.103971 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2498 19:53:59.107207 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2499 19:53:59.113755 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2500 19:53:59.117189 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2501 19:53:59.120369 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2502 19:53:59.123954 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2503 19:53:59.124034
2504 19:53:59.127790 CA PerBit enable=1, Macro0, CA PI delay=32
2505 19:53:59.127872
2506 19:53:59.130914 [CBTSetCACLKResult] CA Dly = 32
2507 19:53:59.130985 CS Dly: 6 (0~38)
2508 19:53:59.131087
2509 19:53:59.134125 ----->DramcWriteLeveling(PI) begin...
2510 19:53:59.137683 ==
2511 19:53:59.137790 Dram Type= 6, Freq= 0, CH_0, rank 0
2512 19:53:59.143901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2513 19:53:59.143984 ==
2514 19:53:59.147613 Write leveling (Byte 0): 32 => 32
2515 19:53:59.150767 Write leveling (Byte 1): 30 => 30
2516 19:53:59.150843 DramcWriteLeveling(PI) end<-----
2517 19:53:59.153892
2518 19:53:59.153993 ==
2519 19:53:59.157756 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 19:53:59.160850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 19:53:59.160929 ==
2522 19:53:59.164015 [Gating] SW mode calibration
2523 19:53:59.170387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2524 19:53:59.174324 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2525 19:53:59.180898 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2526 19:53:59.183925 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2527 19:53:59.187132 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 19:53:59.193886 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2529 19:53:59.197092 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2530 19:53:59.200984 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 19:53:59.207441 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2532 19:53:59.210610 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 1)
2533 19:53:59.214737 1 0 0 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
2534 19:53:59.221131 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 19:53:59.224277 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 19:53:59.227199 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2537 19:53:59.234107 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 19:53:59.237813 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 19:53:59.240893 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2540 19:53:59.247412 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2541 19:53:59.250919 1 1 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
2542 19:53:59.253826 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 19:53:59.257282 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 19:53:59.264063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 19:53:59.267679 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 19:53:59.270741 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 19:53:59.277655 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 19:53:59.281327 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2549 19:53:59.284357 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2550 19:53:59.291121 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 19:53:59.294281 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 19:53:59.297332 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 19:53:59.304328 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 19:53:59.307459 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 19:53:59.310690 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 19:53:59.317574 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 19:53:59.320737 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 19:53:59.324565 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 19:53:59.331252 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 19:53:59.334456 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 19:53:59.337532 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 19:53:59.340824 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 19:53:59.347971 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 19:53:59.351077 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2565 19:53:59.354285 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2566 19:53:59.357478 Total UI for P1: 0, mck2ui 16
2567 19:53:59.360937 best dqsien dly found for B0: ( 1, 3, 28)
2568 19:53:59.367819 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2569 19:53:59.367915 Total UI for P1: 0, mck2ui 16
2570 19:53:59.374066 best dqsien dly found for B1: ( 1, 4, 0)
2571 19:53:59.377828 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2572 19:53:59.381204 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2573 19:53:59.381283
2574 19:53:59.384533 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2575 19:53:59.387663 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2576 19:53:59.391328 [Gating] SW calibration Done
2577 19:53:59.391420 ==
2578 19:53:59.394455 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 19:53:59.398045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 19:53:59.398135 ==
2581 19:53:59.401086 RX Vref Scan: 0
2582 19:53:59.401208
2583 19:53:59.401304 RX Vref 0 -> 0, step: 1
2584 19:53:59.401401
2585 19:53:59.404211 RX Delay -40 -> 252, step: 8
2586 19:53:59.407517 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
2587 19:53:59.414343 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2588 19:53:59.418146 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2589 19:53:59.421294 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2590 19:53:59.424452 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2591 19:53:59.427604 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2592 19:53:59.431446 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2593 19:53:59.437836 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2594 19:53:59.441459 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2595 19:53:59.444347 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2596 19:53:59.448037 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2597 19:53:59.451334 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2598 19:53:59.457818 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2599 19:53:59.461453 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2600 19:53:59.464483 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2601 19:53:59.468059 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2602 19:53:59.468137 ==
2603 19:53:59.471200 Dram Type= 6, Freq= 0, CH_0, rank 0
2604 19:53:59.477981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2605 19:53:59.478064 ==
2606 19:53:59.478139 DQS Delay:
2607 19:53:59.478202 DQS0 = 0, DQS1 = 0
2608 19:53:59.481595 DQM Delay:
2609 19:53:59.481693 DQM0 = 121, DQM1 = 113
2610 19:53:59.484559 DQ Delay:
2611 19:53:59.487884 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2612 19:53:59.491426 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2613 19:53:59.494721 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2614 19:53:59.497872 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2615 19:53:59.497965
2616 19:53:59.498038
2617 19:53:59.498100 ==
2618 19:53:59.501535 Dram Type= 6, Freq= 0, CH_0, rank 0
2619 19:53:59.504860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2620 19:53:59.504935 ==
2621 19:53:59.504999
2622 19:53:59.508296
2623 19:53:59.508381 TX Vref Scan disable
2624 19:53:59.511418 == TX Byte 0 ==
2625 19:53:59.514620 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2626 19:53:59.518415 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2627 19:53:59.521613 == TX Byte 1 ==
2628 19:53:59.524866 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2629 19:53:59.528462 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2630 19:53:59.528544 ==
2631 19:53:59.531748 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 19:53:59.538047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 19:53:59.538125 ==
2634 19:53:59.548805 TX Vref=22, minBit 7, minWin=24, winSum=405
2635 19:53:59.551881 TX Vref=24, minBit 0, minWin=25, winSum=412
2636 19:53:59.555506 TX Vref=26, minBit 2, minWin=25, winSum=414
2637 19:53:59.558575 TX Vref=28, minBit 1, minWin=26, winSum=427
2638 19:53:59.562073 TX Vref=30, minBit 10, minWin=25, winSum=424
2639 19:53:59.568595 TX Vref=32, minBit 10, minWin=25, winSum=419
2640 19:53:59.571785 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
2641 19:53:59.571872
2642 19:53:59.575657 Final TX Range 1 Vref 28
2643 19:53:59.575741
2644 19:53:59.575807 ==
2645 19:53:59.578793 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 19:53:59.581857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 19:53:59.581930 ==
2648 19:53:59.581993
2649 19:53:59.585546
2650 19:53:59.585624 TX Vref Scan disable
2651 19:53:59.588534 == TX Byte 0 ==
2652 19:53:59.592236 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2653 19:53:59.595184 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2654 19:53:59.598328 == TX Byte 1 ==
2655 19:53:59.602038 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2656 19:53:59.605327 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2657 19:53:59.605411
2658 19:53:59.608745 [DATLAT]
2659 19:53:59.608834 Freq=1200, CH0 RK0
2660 19:53:59.608900
2661 19:53:59.612180 DATLAT Default: 0xd
2662 19:53:59.612263 0, 0xFFFF, sum = 0
2663 19:53:59.615266 1, 0xFFFF, sum = 0
2664 19:53:59.615346 2, 0xFFFF, sum = 0
2665 19:53:59.618688 3, 0xFFFF, sum = 0
2666 19:53:59.618764 4, 0xFFFF, sum = 0
2667 19:53:59.622353 5, 0xFFFF, sum = 0
2668 19:53:59.622429 6, 0xFFFF, sum = 0
2669 19:53:59.625545 7, 0xFFFF, sum = 0
2670 19:53:59.625627 8, 0xFFFF, sum = 0
2671 19:53:59.628469 9, 0xFFFF, sum = 0
2672 19:53:59.632379 10, 0xFFFF, sum = 0
2673 19:53:59.632460 11, 0xFFFF, sum = 0
2674 19:53:59.635519 12, 0x0, sum = 1
2675 19:53:59.635624 13, 0x0, sum = 2
2676 19:53:59.635723 14, 0x0, sum = 3
2677 19:53:59.638663 15, 0x0, sum = 4
2678 19:53:59.638737 best_step = 13
2679 19:53:59.638800
2680 19:53:59.642414 ==
2681 19:53:59.642492 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 19:53:59.648878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 19:53:59.648958 ==
2684 19:53:59.649030 RX Vref Scan: 1
2685 19:53:59.649092
2686 19:53:59.652052 Set Vref Range= 32 -> 127
2687 19:53:59.652137
2688 19:53:59.655665 RX Vref 32 -> 127, step: 1
2689 19:53:59.655742
2690 19:53:59.658556 RX Delay -13 -> 252, step: 4
2691 19:53:59.658631
2692 19:53:59.662330 Set Vref, RX VrefLevel [Byte0]: 32
2693 19:53:59.665373 [Byte1]: 32
2694 19:53:59.665479
2695 19:53:59.668509 Set Vref, RX VrefLevel [Byte0]: 33
2696 19:53:59.671968 [Byte1]: 33
2697 19:53:59.672047
2698 19:53:59.675251 Set Vref, RX VrefLevel [Byte0]: 34
2699 19:53:59.678517 [Byte1]: 34
2700 19:53:59.682845
2701 19:53:59.682925 Set Vref, RX VrefLevel [Byte0]: 35
2702 19:53:59.685960 [Byte1]: 35
2703 19:53:59.690830
2704 19:53:59.690908 Set Vref, RX VrefLevel [Byte0]: 36
2705 19:53:59.694216 [Byte1]: 36
2706 19:53:59.698587
2707 19:53:59.698668 Set Vref, RX VrefLevel [Byte0]: 37
2708 19:53:59.702112 [Byte1]: 37
2709 19:53:59.706545
2710 19:53:59.706630 Set Vref, RX VrefLevel [Byte0]: 38
2711 19:53:59.709698 [Byte1]: 38
2712 19:53:59.714108
2713 19:53:59.714185 Set Vref, RX VrefLevel [Byte0]: 39
2714 19:53:59.717768 [Byte1]: 39
2715 19:53:59.722145
2716 19:53:59.722223 Set Vref, RX VrefLevel [Byte0]: 40
2717 19:53:59.725270 [Byte1]: 40
2718 19:53:59.729967
2719 19:53:59.730054 Set Vref, RX VrefLevel [Byte0]: 41
2720 19:53:59.733491 [Byte1]: 41
2721 19:53:59.737659
2722 19:53:59.737737 Set Vref, RX VrefLevel [Byte0]: 42
2723 19:53:59.741302 [Byte1]: 42
2724 19:53:59.746052
2725 19:53:59.746144 Set Vref, RX VrefLevel [Byte0]: 43
2726 19:53:59.749301 [Byte1]: 43
2727 19:53:59.753786
2728 19:53:59.753871 Set Vref, RX VrefLevel [Byte0]: 44
2729 19:53:59.757054 [Byte1]: 44
2730 19:53:59.761349
2731 19:53:59.761426 Set Vref, RX VrefLevel [Byte0]: 45
2732 19:53:59.764727 [Byte1]: 45
2733 19:53:59.769707
2734 19:53:59.769789 Set Vref, RX VrefLevel [Byte0]: 46
2735 19:53:59.772780 [Byte1]: 46
2736 19:53:59.777238
2737 19:53:59.777319 Set Vref, RX VrefLevel [Byte0]: 47
2738 19:53:59.780930 [Byte1]: 47
2739 19:53:59.785350
2740 19:53:59.785427 Set Vref, RX VrefLevel [Byte0]: 48
2741 19:53:59.788487 [Byte1]: 48
2742 19:53:59.793393
2743 19:53:59.793473 Set Vref, RX VrefLevel [Byte0]: 49
2744 19:53:59.796411 [Byte1]: 49
2745 19:53:59.801240
2746 19:53:59.801361 Set Vref, RX VrefLevel [Byte0]: 50
2747 19:53:59.804733 [Byte1]: 50
2748 19:53:59.809002
2749 19:53:59.809119 Set Vref, RX VrefLevel [Byte0]: 51
2750 19:53:59.812054 [Byte1]: 51
2751 19:53:59.816593
2752 19:53:59.816682 Set Vref, RX VrefLevel [Byte0]: 52
2753 19:53:59.820208 [Byte1]: 52
2754 19:53:59.824565
2755 19:53:59.824669 Set Vref, RX VrefLevel [Byte0]: 53
2756 19:53:59.827760 [Byte1]: 53
2757 19:53:59.832799
2758 19:53:59.832915 Set Vref, RX VrefLevel [Byte0]: 54
2759 19:53:59.835922 [Byte1]: 54
2760 19:53:59.840240
2761 19:53:59.840346 Set Vref, RX VrefLevel [Byte0]: 55
2762 19:53:59.843963 [Byte1]: 55
2763 19:53:59.848468
2764 19:53:59.848572 Set Vref, RX VrefLevel [Byte0]: 56
2765 19:53:59.851671 [Byte1]: 56
2766 19:53:59.855801
2767 19:53:59.859477 Set Vref, RX VrefLevel [Byte0]: 57
2768 19:53:59.862601 [Byte1]: 57
2769 19:53:59.862720
2770 19:53:59.866329 Set Vref, RX VrefLevel [Byte0]: 58
2771 19:53:59.869412 [Byte1]: 58
2772 19:53:59.869522
2773 19:53:59.872890 Set Vref, RX VrefLevel [Byte0]: 59
2774 19:53:59.876106 [Byte1]: 59
2775 19:53:59.879919
2776 19:53:59.880021 Set Vref, RX VrefLevel [Byte0]: 60
2777 19:53:59.883046 [Byte1]: 60
2778 19:53:59.888108
2779 19:53:59.888191 Set Vref, RX VrefLevel [Byte0]: 61
2780 19:53:59.891235 [Byte1]: 61
2781 19:53:59.895865
2782 19:53:59.895971 Set Vref, RX VrefLevel [Byte0]: 62
2783 19:53:59.899173 [Byte1]: 62
2784 19:53:59.903362
2785 19:53:59.903471 Set Vref, RX VrefLevel [Byte0]: 63
2786 19:53:59.906673 [Byte1]: 63
2787 19:53:59.911714
2788 19:53:59.911807 Set Vref, RX VrefLevel [Byte0]: 64
2789 19:53:59.914545 [Byte1]: 64
2790 19:53:59.919239
2791 19:53:59.919343 Set Vref, RX VrefLevel [Byte0]: 65
2792 19:53:59.922926 [Byte1]: 65
2793 19:53:59.927324
2794 19:53:59.927431 Set Vref, RX VrefLevel [Byte0]: 66
2795 19:53:59.930420 [Byte1]: 66
2796 19:53:59.934900
2797 19:53:59.935011 Set Vref, RX VrefLevel [Byte0]: 67
2798 19:53:59.938583 [Byte1]: 67
2799 19:53:59.943010
2800 19:53:59.943086 Set Vref, RX VrefLevel [Byte0]: 68
2801 19:53:59.946247 [Byte1]: 68
2802 19:53:59.951356
2803 19:53:59.951459 Set Vref, RX VrefLevel [Byte0]: 69
2804 19:53:59.954464 [Byte1]: 69
2805 19:53:59.958722
2806 19:53:59.958796 Final RX Vref Byte 0 = 56 to rank0
2807 19:53:59.962236 Final RX Vref Byte 1 = 50 to rank0
2808 19:53:59.965491 Final RX Vref Byte 0 = 56 to rank1
2809 19:53:59.968907 Final RX Vref Byte 1 = 50 to rank1==
2810 19:53:59.972273 Dram Type= 6, Freq= 0, CH_0, rank 0
2811 19:53:59.978661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2812 19:53:59.978758 ==
2813 19:53:59.978825 DQS Delay:
2814 19:53:59.978887 DQS0 = 0, DQS1 = 0
2815 19:53:59.982196 DQM Delay:
2816 19:53:59.982274 DQM0 = 121, DQM1 = 112
2817 19:53:59.985623 DQ Delay:
2818 19:53:59.989213 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =120
2819 19:53:59.992359 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2820 19:53:59.995544 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2821 19:53:59.998672 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2822 19:53:59.998791
2823 19:53:59.998886
2824 19:54:00.005709 [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2825 19:54:00.009188 CH0 RK0: MR19=404, MR18=140D
2826 19:54:00.015542 CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27
2827 19:54:00.015660
2828 19:54:00.019055 ----->DramcWriteLeveling(PI) begin...
2829 19:54:00.019165 ==
2830 19:54:00.022502 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 19:54:00.025709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 19:54:00.028983 ==
2833 19:54:00.029097 Write leveling (Byte 0): 35 => 35
2834 19:54:00.032507 Write leveling (Byte 1): 31 => 31
2835 19:54:00.035427 DramcWriteLeveling(PI) end<-----
2836 19:54:00.035534
2837 19:54:00.035635 ==
2838 19:54:00.039111 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 19:54:00.045957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 19:54:00.046066 ==
2841 19:54:00.046160 [Gating] SW mode calibration
2842 19:54:00.055507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2843 19:54:00.059349 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2844 19:54:00.062566 0 15 0 | B1->B0 | 3333 3130 | 1 1 | (1 1) (0 0)
2845 19:54:00.069388 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 19:54:00.072496 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 19:54:00.076256 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 19:54:00.082420 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 19:54:00.086108 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 19:54:00.089129 0 15 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
2851 19:54:00.095750 0 15 28 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (0 0)
2852 19:54:00.099431 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2853 19:54:00.102380 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 19:54:00.109320 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 19:54:00.112426 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 19:54:00.115814 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 19:54:00.119309 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 19:54:00.125994 1 0 24 | B1->B0 | 2424 2424 | 0 0 | (1 1) (0 0)
2859 19:54:00.129395 1 0 28 | B1->B0 | 3a3a 3a3a | 0 1 | (0 0) (0 0)
2860 19:54:00.132916 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 19:54:00.139394 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 19:54:00.142675 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 19:54:00.146394 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 19:54:00.152946 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 19:54:00.156045 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 19:54:00.159264 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 19:54:00.166313 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2868 19:54:00.169495 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2869 19:54:00.172544 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 19:54:00.179275 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 19:54:00.182858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 19:54:00.186030 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 19:54:00.193028 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 19:54:00.196312 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 19:54:00.199420 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 19:54:00.206143 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 19:54:00.209530 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 19:54:00.212955 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 19:54:00.215926 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 19:54:00.222797 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 19:54:00.225874 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 19:54:00.229407 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 19:54:00.235970 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2884 19:54:00.239228 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2885 19:54:00.242703 Total UI for P1: 0, mck2ui 16
2886 19:54:00.246252 best dqsien dly found for B1: ( 1, 3, 28)
2887 19:54:00.249299 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 19:54:00.253002 Total UI for P1: 0, mck2ui 16
2889 19:54:00.255851 best dqsien dly found for B0: ( 1, 3, 30)
2890 19:54:00.259433 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2891 19:54:00.262511 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2892 19:54:00.262622
2893 19:54:00.269418 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2894 19:54:00.272545 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2895 19:54:00.272661 [Gating] SW calibration Done
2896 19:54:00.276335 ==
2897 19:54:00.279278 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 19:54:00.283123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 19:54:00.283241 ==
2900 19:54:00.283344 RX Vref Scan: 0
2901 19:54:00.283443
2902 19:54:00.286238 RX Vref 0 -> 0, step: 1
2903 19:54:00.286347
2904 19:54:00.289384 RX Delay -40 -> 252, step: 8
2905 19:54:00.293193 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2906 19:54:00.296386 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2907 19:54:00.299505 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2908 19:54:00.306458 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2909 19:54:00.309693 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2910 19:54:00.312894 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2911 19:54:00.315996 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2912 19:54:00.319563 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2913 19:54:00.326056 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2914 19:54:00.329402 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2915 19:54:00.332944 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2916 19:54:00.336264 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2917 19:54:00.339430 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2918 19:54:00.346422 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2919 19:54:00.349416 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2920 19:54:00.352854 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2921 19:54:00.352965 ==
2922 19:54:00.356402 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 19:54:00.359797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 19:54:00.359881 ==
2925 19:54:00.363091 DQS Delay:
2926 19:54:00.363203 DQS0 = 0, DQS1 = 0
2927 19:54:00.366122 DQM Delay:
2928 19:54:00.366232 DQM0 = 122, DQM1 = 112
2929 19:54:00.366347 DQ Delay:
2930 19:54:00.369452 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2931 19:54:00.372841 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2932 19:54:00.379760 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2933 19:54:00.383372 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2934 19:54:00.383493
2935 19:54:00.383564
2936 19:54:00.383627 ==
2937 19:54:00.386513 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 19:54:00.389561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 19:54:00.389645 ==
2940 19:54:00.389719
2941 19:54:00.389782
2942 19:54:00.393315 TX Vref Scan disable
2943 19:54:00.393404 == TX Byte 0 ==
2944 19:54:00.399609 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2945 19:54:00.403444 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2946 19:54:00.403525 == TX Byte 1 ==
2947 19:54:00.409761 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2948 19:54:00.412914 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2949 19:54:00.412994 ==
2950 19:54:00.416765 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 19:54:00.419977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 19:54:00.420068 ==
2953 19:54:00.433291 TX Vref=22, minBit 1, minWin=25, winSum=413
2954 19:54:00.436234 TX Vref=24, minBit 3, minWin=25, winSum=420
2955 19:54:00.440113 TX Vref=26, minBit 3, minWin=25, winSum=425
2956 19:54:00.443279 TX Vref=28, minBit 1, minWin=26, winSum=428
2957 19:54:00.446224 TX Vref=30, minBit 1, minWin=26, winSum=426
2958 19:54:00.449594 TX Vref=32, minBit 5, minWin=25, winSum=423
2959 19:54:00.456578 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
2960 19:54:00.456724
2961 19:54:00.459590 Final TX Range 1 Vref 28
2962 19:54:00.459711
2963 19:54:00.459805 ==
2964 19:54:00.462929 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 19:54:00.466055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 19:54:00.466160 ==
2967 19:54:00.466253
2968 19:54:00.469607
2969 19:54:00.469685 TX Vref Scan disable
2970 19:54:00.472722 == TX Byte 0 ==
2971 19:54:00.476265 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2972 19:54:00.479931 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2973 19:54:00.482729 == TX Byte 1 ==
2974 19:54:00.486222 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2975 19:54:00.489631 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2976 19:54:00.489716
2977 19:54:00.493020 [DATLAT]
2978 19:54:00.493104 Freq=1200, CH0 RK1
2979 19:54:00.493170
2980 19:54:00.496360 DATLAT Default: 0xd
2981 19:54:00.496470 0, 0xFFFF, sum = 0
2982 19:54:00.499872 1, 0xFFFF, sum = 0
2983 19:54:00.499954 2, 0xFFFF, sum = 0
2984 19:54:00.502955 3, 0xFFFF, sum = 0
2985 19:54:00.503060 4, 0xFFFF, sum = 0
2986 19:54:00.506123 5, 0xFFFF, sum = 0
2987 19:54:00.506226 6, 0xFFFF, sum = 0
2988 19:54:00.509325 7, 0xFFFF, sum = 0
2989 19:54:00.513186 8, 0xFFFF, sum = 0
2990 19:54:00.513288 9, 0xFFFF, sum = 0
2991 19:54:00.516412 10, 0xFFFF, sum = 0
2992 19:54:00.516513 11, 0xFFFF, sum = 0
2993 19:54:00.519507 12, 0x0, sum = 1
2994 19:54:00.519612 13, 0x0, sum = 2
2995 19:54:00.523292 14, 0x0, sum = 3
2996 19:54:00.523401 15, 0x0, sum = 4
2997 19:54:00.523494 best_step = 13
2998 19:54:00.523587
2999 19:54:00.526368 ==
3000 19:54:00.526466 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 19:54:00.533369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 19:54:00.533475 ==
3003 19:54:00.533567 RX Vref Scan: 0
3004 19:54:00.533665
3005 19:54:00.536378 RX Vref 0 -> 0, step: 1
3006 19:54:00.536475
3007 19:54:00.539925 RX Delay -13 -> 252, step: 4
3008 19:54:00.542940 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3009 19:54:00.546104 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3010 19:54:00.553124 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3011 19:54:00.556201 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3012 19:54:00.559754 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3013 19:54:00.563134 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3014 19:54:00.566538 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3015 19:54:00.572931 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3016 19:54:00.576349 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3017 19:54:00.579749 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3018 19:54:00.582992 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3019 19:54:00.586161 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3020 19:54:00.593068 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3021 19:54:00.596529 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3022 19:54:00.599906 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3023 19:54:00.603312 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3024 19:54:00.603419 ==
3025 19:54:00.606468 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 19:54:00.613325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 19:54:00.613439 ==
3028 19:54:00.613533 DQS Delay:
3029 19:54:00.613627 DQS0 = 0, DQS1 = 0
3030 19:54:00.616794 DQM Delay:
3031 19:54:00.616898 DQM0 = 120, DQM1 = 110
3032 19:54:00.619972 DQ Delay:
3033 19:54:00.623180 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3034 19:54:00.626375 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3035 19:54:00.630074 DQ8 =100, DQ9 =100, DQ10 =110, DQ11 =102
3036 19:54:00.633286 DQ12 =114, DQ13 =118, DQ14 =122, DQ15 =120
3037 19:54:00.633397
3038 19:54:00.633489
3039 19:54:00.639547 [DQSOSCAuto] RK1, (LSB)MR18= 0xdef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3040 19:54:00.643106 CH0 RK1: MR19=403, MR18=DEF
3041 19:54:00.650242 CH0_RK1: MR19=0x403, MR18=0xDEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3042 19:54:00.653443 [RxdqsGatingPostProcess] freq 1200
3043 19:54:00.659757 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3044 19:54:00.659836 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 19:54:00.663581 best DQS1 dly(2T, 0.5T) = (0, 12)
3046 19:54:00.666695 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 19:54:00.669810 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3048 19:54:00.673078 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 19:54:00.676455 best DQS1 dly(2T, 0.5T) = (0, 11)
3050 19:54:00.680268 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 19:54:00.683312 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3052 19:54:00.686997 Pre-setting of DQS Precalculation
3053 19:54:00.689880 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3054 19:54:00.693271 ==
3055 19:54:00.696697 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 19:54:00.700088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 19:54:00.700181 ==
3058 19:54:00.703599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3059 19:54:00.709812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3060 19:54:00.719106 [CA 0] Center 37 (7~68) winsize 62
3061 19:54:00.722530 [CA 1] Center 37 (7~68) winsize 62
3062 19:54:00.725761 [CA 2] Center 35 (5~65) winsize 61
3063 19:54:00.729165 [CA 3] Center 34 (4~64) winsize 61
3064 19:54:00.732784 [CA 4] Center 34 (4~64) winsize 61
3065 19:54:00.735999 [CA 5] Center 33 (3~63) winsize 61
3066 19:54:00.736098
3067 19:54:00.739023 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3068 19:54:00.739124
3069 19:54:00.742791 [CATrainingPosCal] consider 1 rank data
3070 19:54:00.745843 u2DelayCellTimex100 = 270/100 ps
3071 19:54:00.749438 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3072 19:54:00.753025 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3073 19:54:00.756261 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3074 19:54:00.762482 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3075 19:54:00.766290 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3076 19:54:00.769483 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3077 19:54:00.769585
3078 19:54:00.772744 CA PerBit enable=1, Macro0, CA PI delay=33
3079 19:54:00.772859
3080 19:54:00.776474 [CBTSetCACLKResult] CA Dly = 33
3081 19:54:00.776581 CS Dly: 7 (0~38)
3082 19:54:00.776683 ==
3083 19:54:00.779465 Dram Type= 6, Freq= 0, CH_1, rank 1
3084 19:54:00.786291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 19:54:00.786403 ==
3086 19:54:00.789825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3087 19:54:00.796065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3088 19:54:00.804890 [CA 0] Center 37 (7~68) winsize 62
3089 19:54:00.808231 [CA 1] Center 37 (7~68) winsize 62
3090 19:54:00.811202 [CA 2] Center 35 (5~65) winsize 61
3091 19:54:00.814585 [CA 3] Center 34 (4~65) winsize 62
3092 19:54:00.818259 [CA 4] Center 35 (5~65) winsize 61
3093 19:54:00.821232 [CA 5] Center 34 (4~64) winsize 61
3094 19:54:00.821333
3095 19:54:00.824902 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3096 19:54:00.824978
3097 19:54:00.828036 [CATrainingPosCal] consider 2 rank data
3098 19:54:00.831599 u2DelayCellTimex100 = 270/100 ps
3099 19:54:00.835103 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3100 19:54:00.838102 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3101 19:54:00.844481 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3102 19:54:00.848343 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3103 19:54:00.851451 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3104 19:54:00.854630 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3105 19:54:00.854733
3106 19:54:00.858207 CA PerBit enable=1, Macro0, CA PI delay=33
3107 19:54:00.858307
3108 19:54:00.861384 [CBTSetCACLKResult] CA Dly = 33
3109 19:54:00.861492 CS Dly: 8 (0~40)
3110 19:54:00.861591
3111 19:54:00.865091 ----->DramcWriteLeveling(PI) begin...
3112 19:54:00.868334 ==
3113 19:54:00.868439 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 19:54:00.874766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 19:54:00.874876 ==
3116 19:54:00.877967 Write leveling (Byte 0): 26 => 26
3117 19:54:00.881151 Write leveling (Byte 1): 29 => 29
3118 19:54:00.884937 DramcWriteLeveling(PI) end<-----
3119 19:54:00.885039
3120 19:54:00.885138 ==
3121 19:54:00.888201 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 19:54:00.891309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 19:54:00.891409 ==
3124 19:54:00.894901 [Gating] SW mode calibration
3125 19:54:00.901193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3126 19:54:00.904741 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3127 19:54:00.911616 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3128 19:54:00.915024 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 19:54:00.918100 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 19:54:00.924894 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 19:54:00.928478 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 19:54:00.931442 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 19:54:00.938054 0 15 24 | B1->B0 | 3434 2d2d | 1 1 | (1 0) (0 0)
3134 19:54:00.941297 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3135 19:54:00.945080 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 19:54:00.951531 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 19:54:00.954879 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 19:54:00.958049 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 19:54:00.961772 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 19:54:00.968446 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3141 19:54:00.971655 1 0 24 | B1->B0 | 3030 3b3b | 1 1 | (0 0) (0 0)
3142 19:54:00.975425 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 19:54:00.981768 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 19:54:00.984964 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 19:54:00.988570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 19:54:00.994964 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 19:54:00.998760 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 19:54:01.001802 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 19:54:01.008237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3150 19:54:01.011531 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3151 19:54:01.015474 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 19:54:01.022166 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 19:54:01.024927 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 19:54:01.028392 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 19:54:01.035345 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 19:54:01.038450 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 19:54:01.041872 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 19:54:01.048396 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 19:54:01.051597 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 19:54:01.055375 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 19:54:01.058368 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 19:54:01.065030 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 19:54:01.068845 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 19:54:01.071694 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 19:54:01.078746 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3166 19:54:01.081858 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 19:54:01.085093 Total UI for P1: 0, mck2ui 16
3168 19:54:01.088296 best dqsien dly found for B0: ( 1, 3, 24)
3169 19:54:01.092066 Total UI for P1: 0, mck2ui 16
3170 19:54:01.095235 best dqsien dly found for B1: ( 1, 3, 24)
3171 19:54:01.098363 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3172 19:54:01.102206 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3173 19:54:01.102307
3174 19:54:01.105404 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3175 19:54:01.108514 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3176 19:54:01.111759 [Gating] SW calibration Done
3177 19:54:01.111833 ==
3178 19:54:01.115483 Dram Type= 6, Freq= 0, CH_1, rank 0
3179 19:54:01.118691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3180 19:54:01.121786 ==
3181 19:54:01.121885 RX Vref Scan: 0
3182 19:54:01.121982
3183 19:54:01.125367 RX Vref 0 -> 0, step: 1
3184 19:54:01.125439
3185 19:54:01.128233 RX Delay -40 -> 252, step: 8
3186 19:54:01.131963 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3187 19:54:01.134924 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3188 19:54:01.138318 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3189 19:54:01.141401 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3190 19:54:01.148414 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3191 19:54:01.151973 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3192 19:54:01.155081 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3193 19:54:01.158125 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3194 19:54:01.161504 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3195 19:54:01.168542 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3196 19:54:01.171460 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3197 19:54:01.174999 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3198 19:54:01.178175 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3199 19:54:01.181634 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3200 19:54:01.188461 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3201 19:54:01.191832 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3202 19:54:01.191913 ==
3203 19:54:01.195009 Dram Type= 6, Freq= 0, CH_1, rank 0
3204 19:54:01.198170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3205 19:54:01.198246 ==
3206 19:54:01.201393 DQS Delay:
3207 19:54:01.201502 DQS0 = 0, DQS1 = 0
3208 19:54:01.201594 DQM Delay:
3209 19:54:01.204622 DQM0 = 120, DQM1 = 116
3210 19:54:01.204702 DQ Delay:
3211 19:54:01.208445 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3212 19:54:01.211497 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3213 19:54:01.214629 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3214 19:54:01.221702 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3215 19:54:01.221802
3216 19:54:01.221897
3217 19:54:01.221991 ==
3218 19:54:01.224931 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 19:54:01.228043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 19:54:01.228147 ==
3221 19:54:01.228247
3222 19:54:01.228343
3223 19:54:01.231903 TX Vref Scan disable
3224 19:54:01.231993 == TX Byte 0 ==
3225 19:54:01.238402 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3226 19:54:01.241765 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3227 19:54:01.241852 == TX Byte 1 ==
3228 19:54:01.248013 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3229 19:54:01.251605 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3230 19:54:01.251696 ==
3231 19:54:01.254813 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 19:54:01.258022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 19:54:01.258109 ==
3234 19:54:01.270668 TX Vref=22, minBit 1, minWin=25, winSum=414
3235 19:54:01.274023 TX Vref=24, minBit 9, minWin=25, winSum=419
3236 19:54:01.278470 TX Vref=26, minBit 1, minWin=26, winSum=425
3237 19:54:01.280991 TX Vref=28, minBit 9, minWin=25, winSum=430
3238 19:54:01.284175 TX Vref=30, minBit 9, minWin=26, winSum=434
3239 19:54:01.287377 TX Vref=32, minBit 9, minWin=26, winSum=429
3240 19:54:01.294015 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3241 19:54:01.294116
3242 19:54:01.297885 Final TX Range 1 Vref 30
3243 19:54:01.297996
3244 19:54:01.298095 ==
3245 19:54:01.300809 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 19:54:01.303939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 19:54:01.304044 ==
3248 19:54:01.304153
3249 19:54:01.304243
3250 19:54:01.307459 TX Vref Scan disable
3251 19:54:01.310543 == TX Byte 0 ==
3252 19:54:01.314354 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3253 19:54:01.317436 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3254 19:54:01.321277 == TX Byte 1 ==
3255 19:54:01.324382 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3256 19:54:01.327695 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3257 19:54:01.327780
3258 19:54:01.330849 [DATLAT]
3259 19:54:01.330932 Freq=1200, CH1 RK0
3260 19:54:01.330997
3261 19:54:01.334606 DATLAT Default: 0xd
3262 19:54:01.334715 0, 0xFFFF, sum = 0
3263 19:54:01.337782 1, 0xFFFF, sum = 0
3264 19:54:01.337884 2, 0xFFFF, sum = 0
3265 19:54:01.340785 3, 0xFFFF, sum = 0
3266 19:54:01.340879 4, 0xFFFF, sum = 0
3267 19:54:01.343988 5, 0xFFFF, sum = 0
3268 19:54:01.344071 6, 0xFFFF, sum = 0
3269 19:54:01.347782 7, 0xFFFF, sum = 0
3270 19:54:01.347865 8, 0xFFFF, sum = 0
3271 19:54:01.350718 9, 0xFFFF, sum = 0
3272 19:54:01.350824 10, 0xFFFF, sum = 0
3273 19:54:01.354167 11, 0xFFFF, sum = 0
3274 19:54:01.354272 12, 0x0, sum = 1
3275 19:54:01.358065 13, 0x0, sum = 2
3276 19:54:01.358153 14, 0x0, sum = 3
3277 19:54:01.361460 15, 0x0, sum = 4
3278 19:54:01.361566 best_step = 13
3279 19:54:01.361655
3280 19:54:01.361756 ==
3281 19:54:01.364572 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 19:54:01.370913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 19:54:01.370989 ==
3284 19:54:01.371125 RX Vref Scan: 1
3285 19:54:01.371213
3286 19:54:01.374677 Set Vref Range= 32 -> 127
3287 19:54:01.374782
3288 19:54:01.377993 RX Vref 32 -> 127, step: 1
3289 19:54:01.378098
3290 19:54:01.378191 RX Delay -5 -> 252, step: 4
3291 19:54:01.378258
3292 19:54:01.381173 Set Vref, RX VrefLevel [Byte0]: 32
3293 19:54:01.384178 [Byte1]: 32
3294 19:54:01.388838
3295 19:54:01.388909 Set Vref, RX VrefLevel [Byte0]: 33
3296 19:54:01.392231 [Byte1]: 33
3297 19:54:01.396552
3298 19:54:01.396626 Set Vref, RX VrefLevel [Byte0]: 34
3299 19:54:01.399771 [Byte1]: 34
3300 19:54:01.404414
3301 19:54:01.404502 Set Vref, RX VrefLevel [Byte0]: 35
3302 19:54:01.407569 [Byte1]: 35
3303 19:54:01.412455
3304 19:54:01.412540 Set Vref, RX VrefLevel [Byte0]: 36
3305 19:54:01.415856 [Byte1]: 36
3306 19:54:01.420401
3307 19:54:01.420486 Set Vref, RX VrefLevel [Byte0]: 37
3308 19:54:01.423691 [Byte1]: 37
3309 19:54:01.427892
3310 19:54:01.427969 Set Vref, RX VrefLevel [Byte0]: 38
3311 19:54:01.431765 [Byte1]: 38
3312 19:54:01.436170
3313 19:54:01.436252 Set Vref, RX VrefLevel [Byte0]: 39
3314 19:54:01.439325 [Byte1]: 39
3315 19:54:01.443628
3316 19:54:01.443757 Set Vref, RX VrefLevel [Byte0]: 40
3317 19:54:01.446757 [Byte1]: 40
3318 19:54:01.451820
3319 19:54:01.451896 Set Vref, RX VrefLevel [Byte0]: 41
3320 19:54:01.455003 [Byte1]: 41
3321 19:54:01.459315
3322 19:54:01.459388 Set Vref, RX VrefLevel [Byte0]: 42
3323 19:54:01.462917 [Byte1]: 42
3324 19:54:01.467594
3325 19:54:01.467714 Set Vref, RX VrefLevel [Byte0]: 43
3326 19:54:01.470448 [Byte1]: 43
3327 19:54:01.475408
3328 19:54:01.475484 Set Vref, RX VrefLevel [Byte0]: 44
3329 19:54:01.478454 [Byte1]: 44
3330 19:54:01.482911
3331 19:54:01.482992 Set Vref, RX VrefLevel [Byte0]: 45
3332 19:54:01.486059 [Byte1]: 45
3333 19:54:01.491015
3334 19:54:01.491091 Set Vref, RX VrefLevel [Byte0]: 46
3335 19:54:01.494165 [Byte1]: 46
3336 19:54:01.498482
3337 19:54:01.498561 Set Vref, RX VrefLevel [Byte0]: 47
3338 19:54:01.502223 [Byte1]: 47
3339 19:54:01.506377
3340 19:54:01.506451 Set Vref, RX VrefLevel [Byte0]: 48
3341 19:54:01.509919 [Byte1]: 48
3342 19:54:01.514213
3343 19:54:01.514294 Set Vref, RX VrefLevel [Byte0]: 49
3344 19:54:01.517647 [Byte1]: 49
3345 19:54:01.522469
3346 19:54:01.522582 Set Vref, RX VrefLevel [Byte0]: 50
3347 19:54:01.525500 [Byte1]: 50
3348 19:54:01.530357
3349 19:54:01.530441 Set Vref, RX VrefLevel [Byte0]: 51
3350 19:54:01.533175 [Byte1]: 51
3351 19:54:01.538234
3352 19:54:01.538312 Set Vref, RX VrefLevel [Byte0]: 52
3353 19:54:01.541234 [Byte1]: 52
3354 19:54:01.546067
3355 19:54:01.546145 Set Vref, RX VrefLevel [Byte0]: 53
3356 19:54:01.548902 [Byte1]: 53
3357 19:54:01.553406
3358 19:54:01.553505 Set Vref, RX VrefLevel [Byte0]: 54
3359 19:54:01.557247 [Byte1]: 54
3360 19:54:01.561769
3361 19:54:01.561847 Set Vref, RX VrefLevel [Byte0]: 55
3362 19:54:01.564861 [Byte1]: 55
3363 19:54:01.569294
3364 19:54:01.569368 Set Vref, RX VrefLevel [Byte0]: 56
3365 19:54:01.573004 [Byte1]: 56
3366 19:54:01.577423
3367 19:54:01.577523 Set Vref, RX VrefLevel [Byte0]: 57
3368 19:54:01.580908 [Byte1]: 57
3369 19:54:01.585167
3370 19:54:01.585246 Set Vref, RX VrefLevel [Byte0]: 58
3371 19:54:01.588285 [Byte1]: 58
3372 19:54:01.592653
3373 19:54:01.592763 Set Vref, RX VrefLevel [Byte0]: 59
3374 19:54:01.596499 [Byte1]: 59
3375 19:54:01.600905
3376 19:54:01.600981 Set Vref, RX VrefLevel [Byte0]: 60
3377 19:54:01.603833 [Byte1]: 60
3378 19:54:01.608791
3379 19:54:01.608862 Set Vref, RX VrefLevel [Byte0]: 61
3380 19:54:01.611955 [Byte1]: 61
3381 19:54:01.616223
3382 19:54:01.616328 Set Vref, RX VrefLevel [Byte0]: 62
3383 19:54:01.619987 [Byte1]: 62
3384 19:54:01.624283
3385 19:54:01.624364 Set Vref, RX VrefLevel [Byte0]: 63
3386 19:54:01.627889 [Byte1]: 63
3387 19:54:01.632285
3388 19:54:01.632363 Set Vref, RX VrefLevel [Byte0]: 64
3389 19:54:01.635531 [Byte1]: 64
3390 19:54:01.639772
3391 19:54:01.639879 Set Vref, RX VrefLevel [Byte0]: 65
3392 19:54:01.643468 [Byte1]: 65
3393 19:54:01.648125
3394 19:54:01.648206 Set Vref, RX VrefLevel [Byte0]: 66
3395 19:54:01.651381 [Byte1]: 66
3396 19:54:01.655579
3397 19:54:01.655688 Set Vref, RX VrefLevel [Byte0]: 67
3398 19:54:01.659203 [Byte1]: 67
3399 19:54:01.663597
3400 19:54:01.663694 Set Vref, RX VrefLevel [Byte0]: 68
3401 19:54:01.666913 [Byte1]: 68
3402 19:54:01.671368
3403 19:54:01.671454 Final RX Vref Byte 0 = 55 to rank0
3404 19:54:01.675002 Final RX Vref Byte 1 = 52 to rank0
3405 19:54:01.678095 Final RX Vref Byte 0 = 55 to rank1
3406 19:54:01.681292 Final RX Vref Byte 1 = 52 to rank1==
3407 19:54:01.684464 Dram Type= 6, Freq= 0, CH_1, rank 0
3408 19:54:01.691170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3409 19:54:01.691254 ==
3410 19:54:01.691319 DQS Delay:
3411 19:54:01.691380 DQS0 = 0, DQS1 = 0
3412 19:54:01.694607 DQM Delay:
3413 19:54:01.694683 DQM0 = 120, DQM1 = 117
3414 19:54:01.697991 DQ Delay:
3415 19:54:01.701314 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3416 19:54:01.704859 DQ4 =120, DQ5 =130, DQ6 =128, DQ7 =120
3417 19:54:01.707867 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3418 19:54:01.711610 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3419 19:54:01.711699
3420 19:54:01.711775
3421 19:54:01.717785 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3422 19:54:01.721575 CH1 RK0: MR19=404, MR18=13
3423 19:54:01.728109 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3424 19:54:01.728194
3425 19:54:01.731682 ----->DramcWriteLeveling(PI) begin...
3426 19:54:01.731767 ==
3427 19:54:01.734889 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 19:54:01.738009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 19:54:01.738086 ==
3430 19:54:01.741296 Write leveling (Byte 0): 26 => 26
3431 19:54:01.744460 Write leveling (Byte 1): 29 => 29
3432 19:54:01.748246 DramcWriteLeveling(PI) end<-----
3433 19:54:01.748317
3434 19:54:01.748379 ==
3435 19:54:01.751452 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 19:54:01.754674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 19:54:01.758364 ==
3438 19:54:01.758440 [Gating] SW mode calibration
3439 19:54:01.768096 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3440 19:54:01.771247 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3441 19:54:01.774410 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 19:54:01.781227 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 19:54:01.784731 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 19:54:01.787646 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 19:54:01.794649 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 19:54:01.797847 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3447 19:54:01.801014 0 15 24 | B1->B0 | 2828 3333 | 0 0 | (0 1) (0 1)
3448 19:54:01.807750 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 19:54:01.811023 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 19:54:01.814411 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 19:54:01.821063 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 19:54:01.824493 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 19:54:01.827976 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 19:54:01.834682 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3455 19:54:01.837922 1 0 24 | B1->B0 | 4545 3130 | 0 1 | (0 0) (0 0)
3456 19:54:01.841476 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 19:54:01.844573 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 19:54:01.851527 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 19:54:01.854652 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 19:54:01.857814 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 19:54:01.864732 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 19:54:01.867583 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 19:54:01.871378 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3464 19:54:01.877825 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3465 19:54:01.881451 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 19:54:01.884642 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 19:54:01.891267 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 19:54:01.894929 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 19:54:01.897891 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 19:54:01.904757 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 19:54:01.907919 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 19:54:01.911058 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 19:54:01.917423 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 19:54:01.921294 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 19:54:01.924212 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 19:54:01.930742 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 19:54:01.934477 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 19:54:01.937622 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3479 19:54:01.944195 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3480 19:54:01.947569 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3481 19:54:01.951136 Total UI for P1: 0, mck2ui 16
3482 19:54:01.954179 best dqsien dly found for B1: ( 1, 3, 22)
3483 19:54:01.957364 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 19:54:01.960838 Total UI for P1: 0, mck2ui 16
3485 19:54:01.964009 best dqsien dly found for B0: ( 1, 3, 26)
3486 19:54:01.967784 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3487 19:54:01.970721 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3488 19:54:01.970834
3489 19:54:01.974355 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3490 19:54:01.981194 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3491 19:54:01.981276 [Gating] SW calibration Done
3492 19:54:01.981342 ==
3493 19:54:01.984134 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 19:54:01.991106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 19:54:01.991195 ==
3496 19:54:01.991262 RX Vref Scan: 0
3497 19:54:01.991325
3498 19:54:01.994190 RX Vref 0 -> 0, step: 1
3499 19:54:01.994262
3500 19:54:01.997919 RX Delay -40 -> 252, step: 8
3501 19:54:02.001070 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3502 19:54:02.004166 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3503 19:54:02.007409 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3504 19:54:02.010724 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3505 19:54:02.017545 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3506 19:54:02.020732 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3507 19:54:02.024049 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3508 19:54:02.027830 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3509 19:54:02.030777 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3510 19:54:02.037619 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3511 19:54:02.040636 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3512 19:54:02.044415 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3513 19:54:02.047562 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3514 19:54:02.054414 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3515 19:54:02.057194 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3516 19:54:02.060854 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3517 19:54:02.060935 ==
3518 19:54:02.064147 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 19:54:02.067126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 19:54:02.067215 ==
3521 19:54:02.070506 DQS Delay:
3522 19:54:02.070620 DQS0 = 0, DQS1 = 0
3523 19:54:02.073995 DQM Delay:
3524 19:54:02.074071 DQM0 = 120, DQM1 = 117
3525 19:54:02.074135 DQ Delay:
3526 19:54:02.080329 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3527 19:54:02.083829 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3528 19:54:02.087171 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3529 19:54:02.090307 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3530 19:54:02.090384
3531 19:54:02.090456
3532 19:54:02.090517 ==
3533 19:54:02.093846 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 19:54:02.097596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 19:54:02.097677 ==
3536 19:54:02.097742
3537 19:54:02.097803
3538 19:54:02.100801 TX Vref Scan disable
3539 19:54:02.103956 == TX Byte 0 ==
3540 19:54:02.107194 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3541 19:54:02.110938 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3542 19:54:02.114040 == TX Byte 1 ==
3543 19:54:02.117442 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3544 19:54:02.120853 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3545 19:54:02.120932 ==
3546 19:54:02.124011 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 19:54:02.127179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 19:54:02.127261 ==
3549 19:54:02.140241 TX Vref=22, minBit 10, minWin=25, winSum=421
3550 19:54:02.143818 TX Vref=24, minBit 1, minWin=26, winSum=425
3551 19:54:02.147079 TX Vref=26, minBit 9, minWin=26, winSum=430
3552 19:54:02.150183 TX Vref=28, minBit 9, minWin=26, winSum=436
3553 19:54:02.154001 TX Vref=30, minBit 9, minWin=26, winSum=434
3554 19:54:02.157262 TX Vref=32, minBit 0, minWin=27, winSum=437
3555 19:54:02.163517 [TxChooseVref] Worse bit 0, Min win 27, Win sum 437, Final Vref 32
3556 19:54:02.163625
3557 19:54:02.166667 Final TX Range 1 Vref 32
3558 19:54:02.166742
3559 19:54:02.166804 ==
3560 19:54:02.170479 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 19:54:02.173581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 19:54:02.173658 ==
3563 19:54:02.176541
3564 19:54:02.176611
3565 19:54:02.176672 TX Vref Scan disable
3566 19:54:02.179877 == TX Byte 0 ==
3567 19:54:02.183347 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3568 19:54:02.186869 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3569 19:54:02.190288 == TX Byte 1 ==
3570 19:54:02.193586 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3571 19:54:02.199995 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3572 19:54:02.200073
3573 19:54:02.200139 [DATLAT]
3574 19:54:02.200206 Freq=1200, CH1 RK1
3575 19:54:02.200274
3576 19:54:02.203253 DATLAT Default: 0xd
3577 19:54:02.203355 0, 0xFFFF, sum = 0
3578 19:54:02.206799 1, 0xFFFF, sum = 0
3579 19:54:02.206898 2, 0xFFFF, sum = 0
3580 19:54:02.209838 3, 0xFFFF, sum = 0
3581 19:54:02.213536 4, 0xFFFF, sum = 0
3582 19:54:02.213616 5, 0xFFFF, sum = 0
3583 19:54:02.216663 6, 0xFFFF, sum = 0
3584 19:54:02.216734 7, 0xFFFF, sum = 0
3585 19:54:02.219926 8, 0xFFFF, sum = 0
3586 19:54:02.219997 9, 0xFFFF, sum = 0
3587 19:54:02.223453 10, 0xFFFF, sum = 0
3588 19:54:02.223527 11, 0xFFFF, sum = 0
3589 19:54:02.226486 12, 0x0, sum = 1
3590 19:54:02.226560 13, 0x0, sum = 2
3591 19:54:02.230324 14, 0x0, sum = 3
3592 19:54:02.230401 15, 0x0, sum = 4
3593 19:54:02.230480 best_step = 13
3594 19:54:02.233627
3595 19:54:02.233715 ==
3596 19:54:02.236836 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 19:54:02.239903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 19:54:02.239978 ==
3599 19:54:02.240052 RX Vref Scan: 0
3600 19:54:02.240114
3601 19:54:02.243730 RX Vref 0 -> 0, step: 1
3602 19:54:02.243800
3603 19:54:02.246639 RX Delay -5 -> 252, step: 4
3604 19:54:02.250260 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3605 19:54:02.256523 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3606 19:54:02.260301 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3607 19:54:02.263471 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3608 19:54:02.266669 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3609 19:54:02.269903 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3610 19:54:02.273635 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3611 19:54:02.280009 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3612 19:54:02.283050 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3613 19:54:02.286659 iDelay=195, Bit 9, Center 110 (51 ~ 170) 120
3614 19:54:02.290089 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3615 19:54:02.296348 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3616 19:54:02.300186 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3617 19:54:02.303216 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3618 19:54:02.306835 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3619 19:54:02.309868 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3620 19:54:02.309961 ==
3621 19:54:02.313443 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 19:54:02.320031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 19:54:02.320112 ==
3624 19:54:02.320177 DQS Delay:
3625 19:54:02.323519 DQS0 = 0, DQS1 = 0
3626 19:54:02.323602 DQM Delay:
3627 19:54:02.326348 DQM0 = 120, DQM1 = 118
3628 19:54:02.326459 DQ Delay:
3629 19:54:02.329942 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3630 19:54:02.333458 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3631 19:54:02.336728 DQ8 =106, DQ9 =110, DQ10 =116, DQ11 =112
3632 19:54:02.339903 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3633 19:54:02.339983
3634 19:54:02.340071
3635 19:54:02.349981 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3636 19:54:02.350063 CH1 RK1: MR19=403, MR18=10EE
3637 19:54:02.356479 CH1_RK1: MR19=0x403, MR18=0x10EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3638 19:54:02.360043 [RxdqsGatingPostProcess] freq 1200
3639 19:54:02.366864 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3640 19:54:02.370184 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 19:54:02.373318 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 19:54:02.376403 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 19:54:02.380256 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 19:54:02.383342 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 19:54:02.383420 best DQS1 dly(2T, 0.5T) = (0, 11)
3646 19:54:02.386581 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 19:54:02.390346 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3648 19:54:02.393367 Pre-setting of DQS Precalculation
3649 19:54:02.399893 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3650 19:54:02.406268 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3651 19:54:02.413041 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3652 19:54:02.413120
3653 19:54:02.413191
3654 19:54:02.416830 [Calibration Summary] 2400 Mbps
3655 19:54:02.419931 CH 0, Rank 0
3656 19:54:02.420003 SW Impedance : PASS
3657 19:54:02.423129 DUTY Scan : NO K
3658 19:54:02.423214 ZQ Calibration : PASS
3659 19:54:02.426254 Jitter Meter : NO K
3660 19:54:02.430008 CBT Training : PASS
3661 19:54:02.430100 Write leveling : PASS
3662 19:54:02.432965 RX DQS gating : PASS
3663 19:54:02.436445 RX DQ/DQS(RDDQC) : PASS
3664 19:54:02.436534 TX DQ/DQS : PASS
3665 19:54:02.439932 RX DATLAT : PASS
3666 19:54:02.443319 RX DQ/DQS(Engine): PASS
3667 19:54:02.443433 TX OE : NO K
3668 19:54:02.446512 All Pass.
3669 19:54:02.446595
3670 19:54:02.446659 CH 0, Rank 1
3671 19:54:02.449627 SW Impedance : PASS
3672 19:54:02.449705 DUTY Scan : NO K
3673 19:54:02.453067 ZQ Calibration : PASS
3674 19:54:02.456275 Jitter Meter : NO K
3675 19:54:02.456351 CBT Training : PASS
3676 19:54:02.459569 Write leveling : PASS
3677 19:54:02.459685 RX DQS gating : PASS
3678 19:54:02.463147 RX DQ/DQS(RDDQC) : PASS
3679 19:54:02.466573 TX DQ/DQS : PASS
3680 19:54:02.466656 RX DATLAT : PASS
3681 19:54:02.469989 RX DQ/DQS(Engine): PASS
3682 19:54:02.473238 TX OE : NO K
3683 19:54:02.473317 All Pass.
3684 19:54:02.473381
3685 19:54:02.473442 CH 1, Rank 0
3686 19:54:02.476534 SW Impedance : PASS
3687 19:54:02.479956 DUTY Scan : NO K
3688 19:54:02.480037 ZQ Calibration : PASS
3689 19:54:02.483072 Jitter Meter : NO K
3690 19:54:02.486455 CBT Training : PASS
3691 19:54:02.486558 Write leveling : PASS
3692 19:54:02.490214 RX DQS gating : PASS
3693 19:54:02.493381 RX DQ/DQS(RDDQC) : PASS
3694 19:54:02.493453 TX DQ/DQS : PASS
3695 19:54:02.496453 RX DATLAT : PASS
3696 19:54:02.500082 RX DQ/DQS(Engine): PASS
3697 19:54:02.500161 TX OE : NO K
3698 19:54:02.500226 All Pass.
3699 19:54:02.503122
3700 19:54:02.503221 CH 1, Rank 1
3701 19:54:02.506734 SW Impedance : PASS
3702 19:54:02.506810 DUTY Scan : NO K
3703 19:54:02.509916 ZQ Calibration : PASS
3704 19:54:02.509987 Jitter Meter : NO K
3705 19:54:02.513402 CBT Training : PASS
3706 19:54:02.516608 Write leveling : PASS
3707 19:54:02.516680 RX DQS gating : PASS
3708 19:54:02.519781 RX DQ/DQS(RDDQC) : PASS
3709 19:54:02.522991 TX DQ/DQS : PASS
3710 19:54:02.523062 RX DATLAT : PASS
3711 19:54:02.526925 RX DQ/DQS(Engine): PASS
3712 19:54:02.529862 TX OE : NO K
3713 19:54:02.529955 All Pass.
3714 19:54:02.530021
3715 19:54:02.533009 DramC Write-DBI off
3716 19:54:02.533096 PER_BANK_REFRESH: Hybrid Mode
3717 19:54:02.536208 TX_TRACKING: ON
3718 19:54:02.542839 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3719 19:54:02.549532 [FAST_K] Save calibration result to emmc
3720 19:54:02.553048 dramc_set_vcore_voltage set vcore to 650000
3721 19:54:02.553130 Read voltage for 600, 5
3722 19:54:02.556421 Vio18 = 0
3723 19:54:02.556496 Vcore = 650000
3724 19:54:02.556566 Vdram = 0
3725 19:54:02.559931 Vddq = 0
3726 19:54:02.560005 Vmddr = 0
3727 19:54:02.562713 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3728 19:54:02.569588 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3729 19:54:02.572998 MEM_TYPE=3, freq_sel=19
3730 19:54:02.576192 sv_algorithm_assistance_LP4_1600
3731 19:54:02.579716 ============ PULL DRAM RESETB DOWN ============
3732 19:54:02.583197 ========== PULL DRAM RESETB DOWN end =========
3733 19:54:02.586546 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3734 19:54:02.589357 ===================================
3735 19:54:02.592599 LPDDR4 DRAM CONFIGURATION
3736 19:54:02.596377 ===================================
3737 19:54:02.599504 EX_ROW_EN[0] = 0x0
3738 19:54:02.599587 EX_ROW_EN[1] = 0x0
3739 19:54:02.602654 LP4Y_EN = 0x0
3740 19:54:02.602733 WORK_FSP = 0x0
3741 19:54:02.606343 WL = 0x2
3742 19:54:02.606417 RL = 0x2
3743 19:54:02.609451 BL = 0x2
3744 19:54:02.609526 RPST = 0x0
3745 19:54:02.613114 RD_PRE = 0x0
3746 19:54:02.613215 WR_PRE = 0x1
3747 19:54:02.616211 WR_PST = 0x0
3748 19:54:02.619282 DBI_WR = 0x0
3749 19:54:02.619366 DBI_RD = 0x0
3750 19:54:02.623074 OTF = 0x1
3751 19:54:02.626226 ===================================
3752 19:54:02.629469 ===================================
3753 19:54:02.629585 ANA top config
3754 19:54:02.632651 ===================================
3755 19:54:02.635834 DLL_ASYNC_EN = 0
3756 19:54:02.639653 ALL_SLAVE_EN = 1
3757 19:54:02.639730 NEW_RANK_MODE = 1
3758 19:54:02.642802 DLL_IDLE_MODE = 1
3759 19:54:02.645989 LP45_APHY_COMB_EN = 1
3760 19:54:02.649538 TX_ODT_DIS = 1
3761 19:54:02.649626 NEW_8X_MODE = 1
3762 19:54:02.652538 ===================================
3763 19:54:02.655626 ===================================
3764 19:54:02.659296 data_rate = 1200
3765 19:54:02.662661 CKR = 1
3766 19:54:02.665964 DQ_P2S_RATIO = 8
3767 19:54:02.668989 ===================================
3768 19:54:02.672784 CA_P2S_RATIO = 8
3769 19:54:02.675745 DQ_CA_OPEN = 0
3770 19:54:02.675873 DQ_SEMI_OPEN = 0
3771 19:54:02.679248 CA_SEMI_OPEN = 0
3772 19:54:02.682755 CA_FULL_RATE = 0
3773 19:54:02.685668 DQ_CKDIV4_EN = 1
3774 19:54:02.689340 CA_CKDIV4_EN = 1
3775 19:54:02.692377 CA_PREDIV_EN = 0
3776 19:54:02.692454 PH8_DLY = 0
3777 19:54:02.696062 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3778 19:54:02.699000 DQ_AAMCK_DIV = 4
3779 19:54:02.702385 CA_AAMCK_DIV = 4
3780 19:54:02.706012 CA_ADMCK_DIV = 4
3781 19:54:02.709167 DQ_TRACK_CA_EN = 0
3782 19:54:02.709243 CA_PICK = 600
3783 19:54:02.712363 CA_MCKIO = 600
3784 19:54:02.715910 MCKIO_SEMI = 0
3785 19:54:02.718851 PLL_FREQ = 2288
3786 19:54:02.722479 DQ_UI_PI_RATIO = 32
3787 19:54:02.725629 CA_UI_PI_RATIO = 0
3788 19:54:02.729357 ===================================
3789 19:54:02.732675 ===================================
3790 19:54:02.732798 memory_type:LPDDR4
3791 19:54:02.735820 GP_NUM : 10
3792 19:54:02.738883 SRAM_EN : 1
3793 19:54:02.738976 MD32_EN : 0
3794 19:54:02.742612 ===================================
3795 19:54:02.745856 [ANA_INIT] >>>>>>>>>>>>>>
3796 19:54:02.749007 <<<<<< [CONFIGURE PHASE]: ANA_TX
3797 19:54:02.752142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3798 19:54:02.755827 ===================================
3799 19:54:02.759253 data_rate = 1200,PCW = 0X5800
3800 19:54:02.762348 ===================================
3801 19:54:02.765442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3802 19:54:02.768832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 19:54:02.775292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 19:54:02.778788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3805 19:54:02.782458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3806 19:54:02.785546 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3807 19:54:02.788833 [ANA_INIT] flow start
3808 19:54:02.792504 [ANA_INIT] PLL >>>>>>>>
3809 19:54:02.792588 [ANA_INIT] PLL <<<<<<<<
3810 19:54:02.795297 [ANA_INIT] MIDPI >>>>>>>>
3811 19:54:02.799255 [ANA_INIT] MIDPI <<<<<<<<
3812 19:54:02.802505 [ANA_INIT] DLL >>>>>>>>
3813 19:54:02.802620 [ANA_INIT] flow end
3814 19:54:02.805620 ============ LP4 DIFF to SE enter ============
3815 19:54:02.811885 ============ LP4 DIFF to SE exit ============
3816 19:54:02.811996 [ANA_INIT] <<<<<<<<<<<<<
3817 19:54:02.815323 [Flow] Enable top DCM control >>>>>
3818 19:54:02.818482 [Flow] Enable top DCM control <<<<<
3819 19:54:02.822091 Enable DLL master slave shuffle
3820 19:54:02.828695 ==============================================================
3821 19:54:02.828774 Gating Mode config
3822 19:54:02.835551 ==============================================================
3823 19:54:02.838648 Config description:
3824 19:54:02.848727 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3825 19:54:02.854981 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3826 19:54:02.858784 SELPH_MODE 0: By rank 1: By Phase
3827 19:54:02.864995 ==============================================================
3828 19:54:02.868455 GAT_TRACK_EN = 1
3829 19:54:02.868564 RX_GATING_MODE = 2
3830 19:54:02.872131 RX_GATING_TRACK_MODE = 2
3831 19:54:02.875261 SELPH_MODE = 1
3832 19:54:02.878824 PICG_EARLY_EN = 1
3833 19:54:02.881804 VALID_LAT_VALUE = 1
3834 19:54:02.888521 ==============================================================
3835 19:54:02.892119 Enter into Gating configuration >>>>
3836 19:54:02.895313 Exit from Gating configuration <<<<
3837 19:54:02.898448 Enter into DVFS_PRE_config >>>>>
3838 19:54:02.908652 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3839 19:54:02.911823 Exit from DVFS_PRE_config <<<<<
3840 19:54:02.915046 Enter into PICG configuration >>>>
3841 19:54:02.918191 Exit from PICG configuration <<<<
3842 19:54:02.921453 [RX_INPUT] configuration >>>>>
3843 19:54:02.924898 [RX_INPUT] configuration <<<<<
3844 19:54:02.928190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3845 19:54:02.934930 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3846 19:54:02.941396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3847 19:54:02.944742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3848 19:54:02.951226 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 19:54:02.958033 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 19:54:02.961318 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3851 19:54:02.968380 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3852 19:54:02.971385 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3853 19:54:02.974939 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3854 19:54:02.977840 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3855 19:54:02.984556 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3856 19:54:02.988268 ===================================
3857 19:54:02.988353 LPDDR4 DRAM CONFIGURATION
3858 19:54:02.991269 ===================================
3859 19:54:02.994677 EX_ROW_EN[0] = 0x0
3860 19:54:02.997871 EX_ROW_EN[1] = 0x0
3861 19:54:02.997948 LP4Y_EN = 0x0
3862 19:54:03.001245 WORK_FSP = 0x0
3863 19:54:03.001324 WL = 0x2
3864 19:54:03.005056 RL = 0x2
3865 19:54:03.005127 BL = 0x2
3866 19:54:03.008163 RPST = 0x0
3867 19:54:03.008237 RD_PRE = 0x0
3868 19:54:03.011268 WR_PRE = 0x1
3869 19:54:03.011343 WR_PST = 0x0
3870 19:54:03.014795 DBI_WR = 0x0
3871 19:54:03.014868 DBI_RD = 0x0
3872 19:54:03.018145 OTF = 0x1
3873 19:54:03.021623 ===================================
3874 19:54:03.024519 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3875 19:54:03.028212 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3876 19:54:03.034548 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 19:54:03.038208 ===================================
3878 19:54:03.038286 LPDDR4 DRAM CONFIGURATION
3879 19:54:03.041283 ===================================
3880 19:54:03.045105 EX_ROW_EN[0] = 0x10
3881 19:54:03.045185 EX_ROW_EN[1] = 0x0
3882 19:54:03.048094 LP4Y_EN = 0x0
3883 19:54:03.048167 WORK_FSP = 0x0
3884 19:54:03.051536 WL = 0x2
3885 19:54:03.051610 RL = 0x2
3886 19:54:03.054830 BL = 0x2
3887 19:54:03.054906 RPST = 0x0
3888 19:54:03.058207 RD_PRE = 0x0
3889 19:54:03.061812 WR_PRE = 0x1
3890 19:54:03.061890 WR_PST = 0x0
3891 19:54:03.065152 DBI_WR = 0x0
3892 19:54:03.065229 DBI_RD = 0x0
3893 19:54:03.068330 OTF = 0x1
3894 19:54:03.071542 ===================================
3895 19:54:03.074741 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3896 19:54:03.080298 nWR fixed to 30
3897 19:54:03.083653 [ModeRegInit_LP4] CH0 RK0
3898 19:54:03.083738 [ModeRegInit_LP4] CH0 RK1
3899 19:54:03.086564 [ModeRegInit_LP4] CH1 RK0
3900 19:54:03.090355 [ModeRegInit_LP4] CH1 RK1
3901 19:54:03.090439 match AC timing 17
3902 19:54:03.096559 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3903 19:54:03.100345 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3904 19:54:03.103331 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3905 19:54:03.109891 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3906 19:54:03.113753 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3907 19:54:03.113833 ==
3908 19:54:03.116937 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 19:54:03.120108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3910 19:54:03.120183 ==
3911 19:54:03.126520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3912 19:54:03.133497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3913 19:54:03.136726 [CA 0] Center 35 (4~66) winsize 63
3914 19:54:03.139893 [CA 1] Center 35 (5~66) winsize 62
3915 19:54:03.143633 [CA 2] Center 33 (3~64) winsize 62
3916 19:54:03.146392 [CA 3] Center 33 (2~64) winsize 63
3917 19:54:03.150193 [CA 4] Center 33 (2~64) winsize 63
3918 19:54:03.153381 [CA 5] Center 32 (2~63) winsize 62
3919 19:54:03.153455
3920 19:54:03.156500 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3921 19:54:03.156576
3922 19:54:03.160188 [CATrainingPosCal] consider 1 rank data
3923 19:54:03.162980 u2DelayCellTimex100 = 270/100 ps
3924 19:54:03.166390 CA0 delay=35 (4~66),Diff = 3 PI (28 cell)
3925 19:54:03.169811 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3926 19:54:03.173104 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3927 19:54:03.176333 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3928 19:54:03.179557 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3929 19:54:03.183385 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3930 19:54:03.186465
3931 19:54:03.189406 CA PerBit enable=1, Macro0, CA PI delay=32
3932 19:54:03.189494
3933 19:54:03.193145 [CBTSetCACLKResult] CA Dly = 32
3934 19:54:03.193231 CS Dly: 4 (0~35)
3935 19:54:03.193316 ==
3936 19:54:03.196605 Dram Type= 6, Freq= 0, CH_0, rank 1
3937 19:54:03.199709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 19:54:03.199793 ==
3939 19:54:03.205989 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 19:54:03.212601 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3941 19:54:03.216028 [CA 0] Center 35 (5~66) winsize 62
3942 19:54:03.219297 [CA 1] Center 35 (5~66) winsize 62
3943 19:54:03.222991 [CA 2] Center 33 (3~64) winsize 62
3944 19:54:03.226072 [CA 3] Center 33 (3~64) winsize 62
3945 19:54:03.229289 [CA 4] Center 32 (2~63) winsize 62
3946 19:54:03.233020 [CA 5] Center 32 (2~63) winsize 62
3947 19:54:03.233106
3948 19:54:03.235983 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3949 19:54:03.236063
3950 19:54:03.239493 [CATrainingPosCal] consider 2 rank data
3951 19:54:03.242839 u2DelayCellTimex100 = 270/100 ps
3952 19:54:03.246052 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3953 19:54:03.249194 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3954 19:54:03.253024 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3955 19:54:03.255795 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3956 19:54:03.262891 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3957 19:54:03.266033 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3958 19:54:03.266119
3959 19:54:03.269105 CA PerBit enable=1, Macro0, CA PI delay=32
3960 19:54:03.269185
3961 19:54:03.272907 [CBTSetCACLKResult] CA Dly = 32
3962 19:54:03.272990 CS Dly: 4 (0~36)
3963 19:54:03.273080
3964 19:54:03.275940 ----->DramcWriteLeveling(PI) begin...
3965 19:54:03.276020 ==
3966 19:54:03.279333 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 19:54:03.285965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 19:54:03.286051 ==
3969 19:54:03.289219 Write leveling (Byte 0): 34 => 34
3970 19:54:03.289301 Write leveling (Byte 1): 33 => 33
3971 19:54:03.292920 DramcWriteLeveling(PI) end<-----
3972 19:54:03.293002
3973 19:54:03.293090 ==
3974 19:54:03.295748 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 19:54:03.302752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 19:54:03.302837 ==
3977 19:54:03.305848 [Gating] SW mode calibration
3978 19:54:03.312851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3979 19:54:03.316023 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3980 19:54:03.322244 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 19:54:03.326068 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 19:54:03.329344 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 19:54:03.336187 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 1)
3984 19:54:03.339297 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
3985 19:54:03.342477 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 19:54:03.349015 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 19:54:03.352532 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 19:54:03.355535 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 19:54:03.362226 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 19:54:03.365863 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 19:54:03.368736 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
3992 19:54:03.372344 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3993 19:54:03.379289 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 19:54:03.382357 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 19:54:03.385312 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 19:54:03.392047 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 19:54:03.395247 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 19:54:03.399048 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 19:54:03.405260 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4000 19:54:03.408602 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 19:54:03.412228 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 19:54:03.418441 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 19:54:03.422204 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 19:54:03.425398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 19:54:03.432283 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 19:54:03.435019 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 19:54:03.438924 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 19:54:03.445662 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 19:54:03.448782 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 19:54:03.451839 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 19:54:03.458850 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 19:54:03.462029 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 19:54:03.465151 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 19:54:03.471906 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 19:54:03.475243 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4016 19:54:03.478612 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4017 19:54:03.481904 Total UI for P1: 0, mck2ui 16
4018 19:54:03.485045 best dqsien dly found for B0: ( 0, 13, 12)
4019 19:54:03.491914 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 19:54:03.491999 Total UI for P1: 0, mck2ui 16
4021 19:54:03.495406 best dqsien dly found for B1: ( 0, 13, 16)
4022 19:54:03.501712 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4023 19:54:03.504820 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4024 19:54:03.504903
4025 19:54:03.508571 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4026 19:54:03.511679 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4027 19:54:03.515284 [Gating] SW calibration Done
4028 19:54:03.515364 ==
4029 19:54:03.518155 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 19:54:03.521722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 19:54:03.521802 ==
4032 19:54:03.524914 RX Vref Scan: 0
4033 19:54:03.524993
4034 19:54:03.525077 RX Vref 0 -> 0, step: 1
4035 19:54:03.525177
4036 19:54:03.528050 RX Delay -230 -> 252, step: 16
4037 19:54:03.531906 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4038 19:54:03.538381 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4039 19:54:03.541413 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4040 19:54:03.544784 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4041 19:54:03.548034 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4042 19:54:03.554895 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4043 19:54:03.557966 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4044 19:54:03.561596 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4045 19:54:03.564560 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4046 19:54:03.567986 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4047 19:54:03.574892 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4048 19:54:03.578020 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4049 19:54:03.581213 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4050 19:54:03.584799 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4051 19:54:03.591448 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4052 19:54:03.594970 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4053 19:54:03.595062 ==
4054 19:54:03.598081 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 19:54:03.601220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 19:54:03.601299 ==
4057 19:54:03.604852 DQS Delay:
4058 19:54:03.604931 DQS0 = 0, DQS1 = 0
4059 19:54:03.605015 DQM Delay:
4060 19:54:03.608205 DQM0 = 52, DQM1 = 46
4061 19:54:03.608283 DQ Delay:
4062 19:54:03.611109 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4063 19:54:03.614433 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4064 19:54:03.618181 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4065 19:54:03.621207 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4066 19:54:03.621286
4067 19:54:03.621371
4068 19:54:03.621454 ==
4069 19:54:03.624458 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 19:54:03.631078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 19:54:03.631161 ==
4072 19:54:03.631250
4073 19:54:03.631330
4074 19:54:03.631409 TX Vref Scan disable
4075 19:54:03.634877 == TX Byte 0 ==
4076 19:54:03.638092 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4077 19:54:03.641977 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4078 19:54:03.645246 == TX Byte 1 ==
4079 19:54:03.648288 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4080 19:54:03.655037 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4081 19:54:03.655117 ==
4082 19:54:03.658513 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 19:54:03.661794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 19:54:03.661871 ==
4085 19:54:03.661959
4086 19:54:03.662036
4087 19:54:03.665190 TX Vref Scan disable
4088 19:54:03.665267 == TX Byte 0 ==
4089 19:54:03.671367 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4090 19:54:03.674822 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4091 19:54:03.674902 == TX Byte 1 ==
4092 19:54:03.681348 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4093 19:54:03.685198 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4094 19:54:03.685278
4095 19:54:03.685367 [DATLAT]
4096 19:54:03.688219 Freq=600, CH0 RK0
4097 19:54:03.688300
4098 19:54:03.688382 DATLAT Default: 0x9
4099 19:54:03.691332 0, 0xFFFF, sum = 0
4100 19:54:03.691413 1, 0xFFFF, sum = 0
4101 19:54:03.694929 2, 0xFFFF, sum = 0
4102 19:54:03.695006 3, 0xFFFF, sum = 0
4103 19:54:03.698499 4, 0xFFFF, sum = 0
4104 19:54:03.701320 5, 0xFFFF, sum = 0
4105 19:54:03.701413 6, 0xFFFF, sum = 0
4106 19:54:03.704707 7, 0xFFFF, sum = 0
4107 19:54:03.704793 8, 0x0, sum = 1
4108 19:54:03.704871 9, 0x0, sum = 2
4109 19:54:03.708509 10, 0x0, sum = 3
4110 19:54:03.708580 11, 0x0, sum = 4
4111 19:54:03.711702 best_step = 9
4112 19:54:03.711780
4113 19:54:03.711846 ==
4114 19:54:03.714892 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 19:54:03.718024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 19:54:03.718099 ==
4117 19:54:03.721389 RX Vref Scan: 1
4118 19:54:03.721462
4119 19:54:03.721530 RX Vref 0 -> 0, step: 1
4120 19:54:03.721596
4121 19:54:03.724731 RX Delay -163 -> 252, step: 8
4122 19:54:03.724817
4123 19:54:03.728174 Set Vref, RX VrefLevel [Byte0]: 56
4124 19:54:03.731621 [Byte1]: 50
4125 19:54:03.735599
4126 19:54:03.735691 Final RX Vref Byte 0 = 56 to rank0
4127 19:54:03.739012 Final RX Vref Byte 1 = 50 to rank0
4128 19:54:03.742172 Final RX Vref Byte 0 = 56 to rank1
4129 19:54:03.745512 Final RX Vref Byte 1 = 50 to rank1==
4130 19:54:03.748663 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 19:54:03.751893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 19:54:03.755716 ==
4133 19:54:03.755796 DQS Delay:
4134 19:54:03.755859 DQS0 = 0, DQS1 = 0
4135 19:54:03.758805 DQM Delay:
4136 19:54:03.758878 DQM0 = 53, DQM1 = 46
4137 19:54:03.761839 DQ Delay:
4138 19:54:03.765514 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4139 19:54:03.765591 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4140 19:54:03.768648 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4141 19:54:03.771944 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4142 19:54:03.775406
4143 19:54:03.775490
4144 19:54:03.781825 [DQSOSCAuto] RK0, (LSB)MR18= 0x7366, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4145 19:54:03.785259 CH0 RK0: MR19=808, MR18=7366
4146 19:54:03.791849 CH0_RK0: MR19=0x808, MR18=0x7366, DQSOSC=388, MR23=63, INC=174, DEC=116
4147 19:54:03.791945
4148 19:54:03.795077 ----->DramcWriteLeveling(PI) begin...
4149 19:54:03.795155 ==
4150 19:54:03.798782 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 19:54:03.801834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 19:54:03.801914 ==
4153 19:54:03.805425 Write leveling (Byte 0): 33 => 33
4154 19:54:03.808566 Write leveling (Byte 1): 31 => 31
4155 19:54:03.811816 DramcWriteLeveling(PI) end<-----
4156 19:54:03.811896
4157 19:54:03.811980 ==
4158 19:54:03.814805 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 19:54:03.818657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 19:54:03.818736 ==
4161 19:54:03.821787 [Gating] SW mode calibration
4162 19:54:03.828093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 19:54:03.834813 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 19:54:03.838166 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 19:54:03.844458 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 19:54:03.847806 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 19:54:03.851316 0 9 12 | B1->B0 | 3333 3333 | 1 0 | (1 0) (0 1)
4168 19:54:03.857689 0 9 16 | B1->B0 | 2d2d 2b2b | 1 0 | (0 0) (0 0)
4169 19:54:03.861519 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 19:54:03.864590 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 19:54:03.871047 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 19:54:03.874710 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 19:54:03.878067 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 19:54:03.881043 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 19:54:03.887535 0 10 12 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4176 19:54:03.891041 0 10 16 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
4177 19:54:03.894604 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 19:54:03.901295 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 19:54:03.904454 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 19:54:03.907701 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 19:54:03.914419 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 19:54:03.917312 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 19:54:03.920695 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4184 19:54:03.927819 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4185 19:54:03.930992 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 19:54:03.934267 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 19:54:03.940711 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 19:54:03.944339 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 19:54:03.947498 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 19:54:03.954067 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 19:54:03.957302 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 19:54:03.961077 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 19:54:03.967442 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 19:54:03.971231 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 19:54:03.974399 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 19:54:03.980553 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 19:54:03.984243 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 19:54:03.987338 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 19:54:03.994287 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4200 19:54:03.997546 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 19:54:04.000832 Total UI for P1: 0, mck2ui 16
4202 19:54:04.004416 best dqsien dly found for B0: ( 0, 13, 12)
4203 19:54:04.007267 Total UI for P1: 0, mck2ui 16
4204 19:54:04.010952 best dqsien dly found for B1: ( 0, 13, 14)
4205 19:54:04.014153 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4206 19:54:04.017291 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4207 19:54:04.017371
4208 19:54:04.020498 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 19:54:04.024224 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4210 19:54:04.027560 [Gating] SW calibration Done
4211 19:54:04.027647 ==
4212 19:54:04.030414 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 19:54:04.034022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 19:54:04.034108 ==
4215 19:54:04.037603 RX Vref Scan: 0
4216 19:54:04.037709
4217 19:54:04.040698 RX Vref 0 -> 0, step: 1
4218 19:54:04.040793
4219 19:54:04.043704 RX Delay -230 -> 252, step: 16
4220 19:54:04.047439 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4221 19:54:04.050370 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4222 19:54:04.054087 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4223 19:54:04.057206 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4224 19:54:04.063399 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4225 19:54:04.067003 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4226 19:54:04.070362 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4227 19:54:04.073712 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4228 19:54:04.076845 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4229 19:54:04.083776 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4230 19:54:04.087347 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4231 19:54:04.090551 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4232 19:54:04.093669 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4233 19:54:04.100324 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4234 19:54:04.103453 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4235 19:54:04.106936 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4236 19:54:04.107022 ==
4237 19:54:04.110253 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 19:54:04.113598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 19:54:04.117191 ==
4240 19:54:04.117269 DQS Delay:
4241 19:54:04.117334 DQS0 = 0, DQS1 = 0
4242 19:54:04.120316 DQM Delay:
4243 19:54:04.120387 DQM0 = 54, DQM1 = 46
4244 19:54:04.123448 DQ Delay:
4245 19:54:04.127197 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4246 19:54:04.127275 DQ4 =57, DQ5 =49, DQ6 =65, DQ7 =65
4247 19:54:04.130378 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =41
4248 19:54:04.133556 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4249 19:54:04.137027
4250 19:54:04.137112
4251 19:54:04.137215 ==
4252 19:54:04.140162 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 19:54:04.143720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 19:54:04.143819 ==
4255 19:54:04.143915
4256 19:54:04.143990
4257 19:54:04.146673 TX Vref Scan disable
4258 19:54:04.146768 == TX Byte 0 ==
4259 19:54:04.153473 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4260 19:54:04.157052 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4261 19:54:04.157130 == TX Byte 1 ==
4262 19:54:04.163362 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4263 19:54:04.167028 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4264 19:54:04.167108 ==
4265 19:54:04.170193 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 19:54:04.173400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 19:54:04.173481 ==
4268 19:54:04.173550
4269 19:54:04.173614
4270 19:54:04.177006 TX Vref Scan disable
4271 19:54:04.179874 == TX Byte 0 ==
4272 19:54:04.183573 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4273 19:54:04.186475 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4274 19:54:04.190036 == TX Byte 1 ==
4275 19:54:04.193235 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4276 19:54:04.196506 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4277 19:54:04.196587
4278 19:54:04.200220 [DATLAT]
4279 19:54:04.200298 Freq=600, CH0 RK1
4280 19:54:04.200363
4281 19:54:04.203291 DATLAT Default: 0x9
4282 19:54:04.203367 0, 0xFFFF, sum = 0
4283 19:54:04.206998 1, 0xFFFF, sum = 0
4284 19:54:04.207078 2, 0xFFFF, sum = 0
4285 19:54:04.210124 3, 0xFFFF, sum = 0
4286 19:54:04.210203 4, 0xFFFF, sum = 0
4287 19:54:04.213290 5, 0xFFFF, sum = 0
4288 19:54:04.213368 6, 0xFFFF, sum = 0
4289 19:54:04.216934 7, 0xFFFF, sum = 0
4290 19:54:04.217013 8, 0x0, sum = 1
4291 19:54:04.220245 9, 0x0, sum = 2
4292 19:54:04.220323 10, 0x0, sum = 3
4293 19:54:04.223510 11, 0x0, sum = 4
4294 19:54:04.223587 best_step = 9
4295 19:54:04.223663
4296 19:54:04.223726 ==
4297 19:54:04.227215 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 19:54:04.230128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 19:54:04.233986 ==
4300 19:54:04.234105 RX Vref Scan: 0
4301 19:54:04.234184
4302 19:54:04.237067 RX Vref 0 -> 0, step: 1
4303 19:54:04.237142
4304 19:54:04.240119 RX Delay -179 -> 252, step: 8
4305 19:54:04.243631 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4306 19:54:04.247068 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4307 19:54:04.254003 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4308 19:54:04.256989 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4309 19:54:04.259995 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4310 19:54:04.263569 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4311 19:54:04.266545 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4312 19:54:04.273486 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4313 19:54:04.276594 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4314 19:54:04.280399 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4315 19:54:04.283711 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4316 19:54:04.286870 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4317 19:54:04.293354 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4318 19:54:04.296722 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4319 19:54:04.299833 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4320 19:54:04.303590 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4321 19:54:04.303697 ==
4322 19:54:04.306604 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 19:54:04.313450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 19:54:04.313538 ==
4325 19:54:04.313600 DQS Delay:
4326 19:54:04.316610 DQS0 = 0, DQS1 = 0
4327 19:54:04.316698 DQM Delay:
4328 19:54:04.316759 DQM0 = 54, DQM1 = 46
4329 19:54:04.319816 DQ Delay:
4330 19:54:04.323656 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4331 19:54:04.326649 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4332 19:54:04.329927 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4333 19:54:04.333260 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4334 19:54:04.333368
4335 19:54:04.333465
4336 19:54:04.340211 [DQSOSCAuto] RK1, (LSB)MR18= 0x6727, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4337 19:54:04.343367 CH0 RK1: MR19=808, MR18=6727
4338 19:54:04.350259 CH0_RK1: MR19=0x808, MR18=0x6727, DQSOSC=390, MR23=63, INC=172, DEC=114
4339 19:54:04.353056 [RxdqsGatingPostProcess] freq 600
4340 19:54:04.356589 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 19:54:04.359740 Pre-setting of DQS Precalculation
4342 19:54:04.366776 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 19:54:04.366857 ==
4344 19:54:04.369611 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 19:54:04.373052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 19:54:04.373140 ==
4347 19:54:04.379986 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 19:54:04.383230 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4349 19:54:04.387707 [CA 0] Center 36 (5~67) winsize 63
4350 19:54:04.390932 [CA 1] Center 36 (6~67) winsize 62
4351 19:54:04.394172 [CA 2] Center 35 (4~66) winsize 63
4352 19:54:04.397370 [CA 3] Center 34 (4~65) winsize 62
4353 19:54:04.401093 [CA 4] Center 34 (4~65) winsize 62
4354 19:54:04.404316 [CA 5] Center 34 (3~65) winsize 63
4355 19:54:04.404392
4356 19:54:04.407807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4357 19:54:04.407909
4358 19:54:04.411341 [CATrainingPosCal] consider 1 rank data
4359 19:54:04.414490 u2DelayCellTimex100 = 270/100 ps
4360 19:54:04.417572 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4361 19:54:04.420996 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4362 19:54:04.427874 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4363 19:54:04.430991 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4364 19:54:04.434684 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4365 19:54:04.437605 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4366 19:54:04.437712
4367 19:54:04.441103 CA PerBit enable=1, Macro0, CA PI delay=34
4368 19:54:04.441177
4369 19:54:04.444477 [CBTSetCACLKResult] CA Dly = 34
4370 19:54:04.444574 CS Dly: 6 (0~37)
4371 19:54:04.444664 ==
4372 19:54:04.447397 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 19:54:04.454448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 19:54:04.454531 ==
4375 19:54:04.457498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 19:54:04.463869 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4377 19:54:04.467498 [CA 0] Center 36 (5~67) winsize 63
4378 19:54:04.471033 [CA 1] Center 36 (5~67) winsize 63
4379 19:54:04.474094 [CA 2] Center 35 (4~66) winsize 63
4380 19:54:04.477498 [CA 3] Center 34 (4~65) winsize 62
4381 19:54:04.480953 [CA 4] Center 34 (4~65) winsize 62
4382 19:54:04.484075 [CA 5] Center 34 (3~65) winsize 63
4383 19:54:04.484155
4384 19:54:04.487913 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4385 19:54:04.487989
4386 19:54:04.491065 [CATrainingPosCal] consider 2 rank data
4387 19:54:04.494183 u2DelayCellTimex100 = 270/100 ps
4388 19:54:04.497321 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4389 19:54:04.501232 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4390 19:54:04.507736 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4391 19:54:04.510802 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 19:54:04.514526 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 19:54:04.517835 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4394 19:54:04.517914
4395 19:54:04.520808 CA PerBit enable=1, Macro0, CA PI delay=34
4396 19:54:04.520892
4397 19:54:04.524448 [CBTSetCACLKResult] CA Dly = 34
4398 19:54:04.524532 CS Dly: 6 (0~37)
4399 19:54:04.524599
4400 19:54:04.527390 ----->DramcWriteLeveling(PI) begin...
4401 19:54:04.530667 ==
4402 19:54:04.534221 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 19:54:04.537654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 19:54:04.537766 ==
4405 19:54:04.540844 Write leveling (Byte 0): 31 => 31
4406 19:54:04.544458 Write leveling (Byte 1): 31 => 31
4407 19:54:04.547659 DramcWriteLeveling(PI) end<-----
4408 19:54:04.547744
4409 19:54:04.547811 ==
4410 19:54:04.550673 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 19:54:04.554227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 19:54:04.554344 ==
4413 19:54:04.557248 [Gating] SW mode calibration
4414 19:54:04.563978 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 19:54:04.570886 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 19:54:04.574013 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 19:54:04.577549 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 19:54:04.580708 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4419 19:54:04.587304 0 9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (0 0) (0 0)
4420 19:54:04.590778 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 19:54:04.593830 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 19:54:04.601060 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 19:54:04.604112 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 19:54:04.607226 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 19:54:04.614240 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 19:54:04.617426 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 19:54:04.620671 0 10 12 | B1->B0 | 3737 3a3a | 0 0 | (0 0) (0 0)
4428 19:54:04.627624 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 19:54:04.630751 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 19:54:04.633910 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 19:54:04.640495 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 19:54:04.643991 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 19:54:04.647324 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 19:54:04.653903 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 19:54:04.657432 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 19:54:04.660454 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 19:54:04.667055 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 19:54:04.670411 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 19:54:04.674045 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 19:54:04.680580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 19:54:04.683802 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 19:54:04.687440 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 19:54:04.693656 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 19:54:04.697247 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 19:54:04.700523 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 19:54:04.706650 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 19:54:04.710465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 19:54:04.713681 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 19:54:04.716942 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 19:54:04.723306 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 19:54:04.727056 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4452 19:54:04.730297 Total UI for P1: 0, mck2ui 16
4453 19:54:04.733420 best dqsien dly found for B0: ( 0, 13, 10)
4454 19:54:04.736645 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4455 19:54:04.743517 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 19:54:04.747281 Total UI for P1: 0, mck2ui 16
4457 19:54:04.750368 best dqsien dly found for B1: ( 0, 13, 14)
4458 19:54:04.753672 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4459 19:54:04.756666 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4460 19:54:04.756753
4461 19:54:04.760079 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4462 19:54:04.763610 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4463 19:54:04.767184 [Gating] SW calibration Done
4464 19:54:04.767267 ==
4465 19:54:04.769949 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 19:54:04.773629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 19:54:04.773714 ==
4468 19:54:04.776650 RX Vref Scan: 0
4469 19:54:04.776733
4470 19:54:04.776800 RX Vref 0 -> 0, step: 1
4471 19:54:04.779974
4472 19:54:04.780057 RX Delay -230 -> 252, step: 16
4473 19:54:04.786982 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4474 19:54:04.790362 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4475 19:54:04.793805 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4476 19:54:04.796663 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4477 19:54:04.800131 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4478 19:54:04.807374 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4479 19:54:04.810454 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4480 19:54:04.813663 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4481 19:54:04.816817 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4482 19:54:04.820535 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4483 19:54:04.826916 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4484 19:54:04.830951 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4485 19:54:04.833969 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4486 19:54:04.837101 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4487 19:54:04.843538 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4488 19:54:04.847271 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4489 19:54:04.847369 ==
4490 19:54:04.850247 Dram Type= 6, Freq= 0, CH_1, rank 0
4491 19:54:04.853418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4492 19:54:04.853595 ==
4493 19:54:04.857269 DQS Delay:
4494 19:54:04.857353 DQS0 = 0, DQS1 = 0
4495 19:54:04.860406 DQM Delay:
4496 19:54:04.860489 DQM0 = 50, DQM1 = 46
4497 19:54:04.860556 DQ Delay:
4498 19:54:04.863399 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4499 19:54:04.866842 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4500 19:54:04.870150 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4501 19:54:04.873845 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4502 19:54:04.873929
4503 19:54:04.873996
4504 19:54:04.874058 ==
4505 19:54:04.877105 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 19:54:04.883360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 19:54:04.883445 ==
4508 19:54:04.883513
4509 19:54:04.883575
4510 19:54:04.883641 TX Vref Scan disable
4511 19:54:04.887482 == TX Byte 0 ==
4512 19:54:04.890629 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4513 19:54:04.897390 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4514 19:54:04.897509 == TX Byte 1 ==
4515 19:54:04.900857 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4516 19:54:04.907038 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4517 19:54:04.907145 ==
4518 19:54:04.910771 Dram Type= 6, Freq= 0, CH_1, rank 0
4519 19:54:04.914152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4520 19:54:04.914229 ==
4521 19:54:04.914312
4522 19:54:04.914375
4523 19:54:04.916964 TX Vref Scan disable
4524 19:54:04.920517 == TX Byte 0 ==
4525 19:54:04.924084 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4526 19:54:04.927274 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4527 19:54:04.930837 == TX Byte 1 ==
4528 19:54:04.934012 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4529 19:54:04.937154 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4530 19:54:04.937256
4531 19:54:04.937348 [DATLAT]
4532 19:54:04.940363 Freq=600, CH1 RK0
4533 19:54:04.940438
4534 19:54:04.940500 DATLAT Default: 0x9
4535 19:54:04.944094 0, 0xFFFF, sum = 0
4536 19:54:04.944169 1, 0xFFFF, sum = 0
4537 19:54:04.947299 2, 0xFFFF, sum = 0
4538 19:54:04.950343 3, 0xFFFF, sum = 0
4539 19:54:04.950419 4, 0xFFFF, sum = 0
4540 19:54:04.953971 5, 0xFFFF, sum = 0
4541 19:54:04.954077 6, 0xFFFF, sum = 0
4542 19:54:04.957345 7, 0xFFFF, sum = 0
4543 19:54:04.957437 8, 0x0, sum = 1
4544 19:54:04.960431 9, 0x0, sum = 2
4545 19:54:04.960540 10, 0x0, sum = 3
4546 19:54:04.960635 11, 0x0, sum = 4
4547 19:54:04.963555 best_step = 9
4548 19:54:04.963663
4549 19:54:04.963755 ==
4550 19:54:04.966664 Dram Type= 6, Freq= 0, CH_1, rank 0
4551 19:54:04.970328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4552 19:54:04.970434 ==
4553 19:54:04.973869 RX Vref Scan: 1
4554 19:54:04.973969
4555 19:54:04.974060 RX Vref 0 -> 0, step: 1
4556 19:54:04.974159
4557 19:54:04.976888 RX Delay -163 -> 252, step: 8
4558 19:54:04.976988
4559 19:54:04.979945 Set Vref, RX VrefLevel [Byte0]: 55
4560 19:54:04.983926 [Byte1]: 52
4561 19:54:04.987701
4562 19:54:04.987775 Final RX Vref Byte 0 = 55 to rank0
4563 19:54:04.990815 Final RX Vref Byte 1 = 52 to rank0
4564 19:54:04.994589 Final RX Vref Byte 0 = 55 to rank1
4565 19:54:04.998007 Final RX Vref Byte 1 = 52 to rank1==
4566 19:54:05.001308 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 19:54:05.007551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 19:54:05.007671 ==
4569 19:54:05.007741 DQS Delay:
4570 19:54:05.007802 DQS0 = 0, DQS1 = 0
4571 19:54:05.011044 DQM Delay:
4572 19:54:05.011149 DQM0 = 48, DQM1 = 45
4573 19:54:05.014410 DQ Delay:
4574 19:54:05.017398 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4575 19:54:05.017485 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4576 19:54:05.021070 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4577 19:54:05.027465 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4578 19:54:05.027577
4579 19:54:05.027680
4580 19:54:05.033862 [DQSOSCAuto] RK0, (LSB)MR18= 0x476c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4581 19:54:05.037895 CH1 RK0: MR19=808, MR18=476C
4582 19:54:05.044326 CH1_RK0: MR19=0x808, MR18=0x476C, DQSOSC=389, MR23=63, INC=173, DEC=115
4583 19:54:05.044414
4584 19:54:05.047735 ----->DramcWriteLeveling(PI) begin...
4585 19:54:05.047821 ==
4586 19:54:05.050900 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 19:54:05.053989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 19:54:05.054074 ==
4589 19:54:05.057678 Write leveling (Byte 0): 29 => 29
4590 19:54:05.060811 Write leveling (Byte 1): 31 => 31
4591 19:54:05.064018 DramcWriteLeveling(PI) end<-----
4592 19:54:05.064102
4593 19:54:05.064168 ==
4594 19:54:05.067250 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 19:54:05.070485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 19:54:05.070570 ==
4597 19:54:05.074118 [Gating] SW mode calibration
4598 19:54:05.080680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4599 19:54:05.087538 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4600 19:54:05.090737 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 19:54:05.097096 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 19:54:05.100862 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4603 19:54:05.104062 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
4604 19:54:05.110245 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 19:54:05.113480 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 19:54:05.117207 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 19:54:05.120253 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 19:54:05.127188 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 19:54:05.130315 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 19:54:05.133395 0 10 8 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4611 19:54:05.140372 0 10 12 | B1->B0 | 3f3f 3838 | 1 0 | (0 0) (1 1)
4612 19:54:05.143356 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 19:54:05.146888 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 19:54:05.153624 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 19:54:05.156677 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 19:54:05.160307 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 19:54:05.166825 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 19:54:05.169849 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4619 19:54:05.173616 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 19:54:05.179782 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 19:54:05.183491 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 19:54:05.186585 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 19:54:05.193516 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 19:54:05.196585 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 19:54:05.199800 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 19:54:05.206778 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 19:54:05.209810 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 19:54:05.213533 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 19:54:05.219908 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 19:54:05.223108 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 19:54:05.226846 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 19:54:05.232926 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 19:54:05.236620 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 19:54:05.239942 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4635 19:54:05.246996 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 19:54:05.247098 Total UI for P1: 0, mck2ui 16
4637 19:54:05.249814 best dqsien dly found for B0: ( 0, 13, 10)
4638 19:54:05.253187 Total UI for P1: 0, mck2ui 16
4639 19:54:05.256530 best dqsien dly found for B1: ( 0, 13, 8)
4640 19:54:05.262950 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4641 19:54:05.266550 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4642 19:54:05.266635
4643 19:54:05.269922 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4644 19:54:05.273197 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4645 19:54:05.276435 [Gating] SW calibration Done
4646 19:54:05.276519 ==
4647 19:54:05.279624 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 19:54:05.282992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 19:54:05.283077 ==
4650 19:54:05.286393 RX Vref Scan: 0
4651 19:54:05.286477
4652 19:54:05.286544 RX Vref 0 -> 0, step: 1
4653 19:54:05.286606
4654 19:54:05.289782 RX Delay -230 -> 252, step: 16
4655 19:54:05.292643 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4656 19:54:05.299564 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4657 19:54:05.302756 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4658 19:54:05.306535 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4659 19:54:05.309627 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4660 19:54:05.315858 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4661 19:54:05.319446 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4662 19:54:05.322590 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4663 19:54:05.325790 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4664 19:54:05.329497 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4665 19:54:05.335829 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4666 19:54:05.339523 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4667 19:54:05.342790 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4668 19:54:05.345766 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4669 19:54:05.352505 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4670 19:54:05.355873 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4671 19:54:05.355991 ==
4672 19:54:05.359470 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 19:54:05.362458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 19:54:05.362548 ==
4675 19:54:05.366098 DQS Delay:
4676 19:54:05.366192 DQS0 = 0, DQS1 = 0
4677 19:54:05.366257 DQM Delay:
4678 19:54:05.369594 DQM0 = 50, DQM1 = 48
4679 19:54:05.369711 DQ Delay:
4680 19:54:05.372676 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4681 19:54:05.375684 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4682 19:54:05.379323 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4683 19:54:05.382429 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4684 19:54:05.382510
4685 19:54:05.382617
4686 19:54:05.382707 ==
4687 19:54:05.385797 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 19:54:05.392804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 19:54:05.392898 ==
4690 19:54:05.392962
4691 19:54:05.393027
4692 19:54:05.393084 TX Vref Scan disable
4693 19:54:05.396186 == TX Byte 0 ==
4694 19:54:05.399313 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4695 19:54:05.406304 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4696 19:54:05.406394 == TX Byte 1 ==
4697 19:54:05.409440 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4698 19:54:05.412642 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4699 19:54:05.416354 ==
4700 19:54:05.419486 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 19:54:05.422535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 19:54:05.422635 ==
4703 19:54:05.422732
4704 19:54:05.422807
4705 19:54:05.425695 TX Vref Scan disable
4706 19:54:05.429533 == TX Byte 0 ==
4707 19:54:05.432686 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4708 19:54:05.435835 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4709 19:54:05.435932 == TX Byte 1 ==
4710 19:54:05.442648 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4711 19:54:05.445748 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4712 19:54:05.445861
4713 19:54:05.445956 [DATLAT]
4714 19:54:05.449568 Freq=600, CH1 RK1
4715 19:54:05.449667
4716 19:54:05.449765 DATLAT Default: 0x9
4717 19:54:05.452740 0, 0xFFFF, sum = 0
4718 19:54:05.452869 1, 0xFFFF, sum = 0
4719 19:54:05.455799 2, 0xFFFF, sum = 0
4720 19:54:05.459349 3, 0xFFFF, sum = 0
4721 19:54:05.459435 4, 0xFFFF, sum = 0
4722 19:54:05.462368 5, 0xFFFF, sum = 0
4723 19:54:05.462453 6, 0xFFFF, sum = 0
4724 19:54:05.465672 7, 0xFFFF, sum = 0
4725 19:54:05.465759 8, 0x0, sum = 1
4726 19:54:05.465828 9, 0x0, sum = 2
4727 19:54:05.469425 10, 0x0, sum = 3
4728 19:54:05.469511 11, 0x0, sum = 4
4729 19:54:05.472735 best_step = 9
4730 19:54:05.472822
4731 19:54:05.472889 ==
4732 19:54:05.475971 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 19:54:05.479474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 19:54:05.479585 ==
4735 19:54:05.482410 RX Vref Scan: 0
4736 19:54:05.482529
4737 19:54:05.482651 RX Vref 0 -> 0, step: 1
4738 19:54:05.482749
4739 19:54:05.485941 RX Delay -163 -> 252, step: 8
4740 19:54:05.492834 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4741 19:54:05.496505 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4742 19:54:05.499599 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4743 19:54:05.502718 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4744 19:54:05.506115 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4745 19:54:05.512958 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4746 19:54:05.516351 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4747 19:54:05.519372 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4748 19:54:05.523211 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4749 19:54:05.526239 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4750 19:54:05.533244 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4751 19:54:05.536373 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4752 19:54:05.539540 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4753 19:54:05.542712 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4754 19:54:05.549454 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4755 19:54:05.553120 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4756 19:54:05.553205 ==
4757 19:54:05.556274 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 19:54:05.559438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 19:54:05.559549 ==
4760 19:54:05.563118 DQS Delay:
4761 19:54:05.563201 DQS0 = 0, DQS1 = 0
4762 19:54:05.563269 DQM Delay:
4763 19:54:05.565992 DQM0 = 49, DQM1 = 46
4764 19:54:05.566077 DQ Delay:
4765 19:54:05.569845 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4766 19:54:05.572928 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4767 19:54:05.576348 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4768 19:54:05.579708 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4769 19:54:05.579793
4770 19:54:05.579860
4771 19:54:05.589613 [DQSOSCAuto] RK1, (LSB)MR18= 0x6920, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4772 19:54:05.589712 CH1 RK1: MR19=808, MR18=6920
4773 19:54:05.596132 CH1_RK1: MR19=0x808, MR18=0x6920, DQSOSC=390, MR23=63, INC=172, DEC=114
4774 19:54:05.599259 [RxdqsGatingPostProcess] freq 600
4775 19:54:05.606339 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4776 19:54:05.609504 Pre-setting of DQS Precalculation
4777 19:54:05.612535 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4778 19:54:05.619437 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4779 19:54:05.629155 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4780 19:54:05.629245
4781 19:54:05.629316
4782 19:54:05.632431 [Calibration Summary] 1200 Mbps
4783 19:54:05.632509 CH 0, Rank 0
4784 19:54:05.636189 SW Impedance : PASS
4785 19:54:05.636277 DUTY Scan : NO K
4786 19:54:05.639399 ZQ Calibration : PASS
4787 19:54:05.639476 Jitter Meter : NO K
4788 19:54:05.642634 CBT Training : PASS
4789 19:54:05.645716 Write leveling : PASS
4790 19:54:05.645820 RX DQS gating : PASS
4791 19:54:05.649286 RX DQ/DQS(RDDQC) : PASS
4792 19:54:05.652567 TX DQ/DQS : PASS
4793 19:54:05.652650 RX DATLAT : PASS
4794 19:54:05.655831 RX DQ/DQS(Engine): PASS
4795 19:54:05.659015 TX OE : NO K
4796 19:54:05.659088 All Pass.
4797 19:54:05.659150
4798 19:54:05.659208 CH 0, Rank 1
4799 19:54:05.662281 SW Impedance : PASS
4800 19:54:05.665955 DUTY Scan : NO K
4801 19:54:05.666028 ZQ Calibration : PASS
4802 19:54:05.668907 Jitter Meter : NO K
4803 19:54:05.672564 CBT Training : PASS
4804 19:54:05.672645 Write leveling : PASS
4805 19:54:05.675759 RX DQS gating : PASS
4806 19:54:05.678773 RX DQ/DQS(RDDQC) : PASS
4807 19:54:05.678846 TX DQ/DQS : PASS
4808 19:54:05.682245 RX DATLAT : PASS
4809 19:54:05.685475 RX DQ/DQS(Engine): PASS
4810 19:54:05.685579 TX OE : NO K
4811 19:54:05.685676 All Pass.
4812 19:54:05.685765
4813 19:54:05.689238 CH 1, Rank 0
4814 19:54:05.689314 SW Impedance : PASS
4815 19:54:05.692208 DUTY Scan : NO K
4816 19:54:05.695629 ZQ Calibration : PASS
4817 19:54:05.695740 Jitter Meter : NO K
4818 19:54:05.699307 CBT Training : PASS
4819 19:54:05.702367 Write leveling : PASS
4820 19:54:05.702466 RX DQS gating : PASS
4821 19:54:05.706052 RX DQ/DQS(RDDQC) : PASS
4822 19:54:05.709132 TX DQ/DQS : PASS
4823 19:54:05.709226 RX DATLAT : PASS
4824 19:54:05.712357 RX DQ/DQS(Engine): PASS
4825 19:54:05.715979 TX OE : NO K
4826 19:54:05.716070 All Pass.
4827 19:54:05.716153
4828 19:54:05.716227 CH 1, Rank 1
4829 19:54:05.719220 SW Impedance : PASS
4830 19:54:05.722285 DUTY Scan : NO K
4831 19:54:05.722384 ZQ Calibration : PASS
4832 19:54:05.725840 Jitter Meter : NO K
4833 19:54:05.728784 CBT Training : PASS
4834 19:54:05.728885 Write leveling : PASS
4835 19:54:05.732573 RX DQS gating : PASS
4836 19:54:05.732673 RX DQ/DQS(RDDQC) : PASS
4837 19:54:05.735936 TX DQ/DQS : PASS
4838 19:54:05.739251 RX DATLAT : PASS
4839 19:54:05.739358 RX DQ/DQS(Engine): PASS
4840 19:54:05.742290 TX OE : NO K
4841 19:54:05.742394 All Pass.
4842 19:54:05.742487
4843 19:54:05.745757 DramC Write-DBI off
4844 19:54:05.749342 PER_BANK_REFRESH: Hybrid Mode
4845 19:54:05.749419 TX_TRACKING: ON
4846 19:54:05.759317 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4847 19:54:05.762564 [FAST_K] Save calibration result to emmc
4848 19:54:05.765783 dramc_set_vcore_voltage set vcore to 662500
4849 19:54:05.768896 Read voltage for 933, 3
4850 19:54:05.768969 Vio18 = 0
4851 19:54:05.769032 Vcore = 662500
4852 19:54:05.772585 Vdram = 0
4853 19:54:05.772661 Vddq = 0
4854 19:54:05.772725 Vmddr = 0
4855 19:54:05.778754 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4856 19:54:05.782542 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4857 19:54:05.785749 MEM_TYPE=3, freq_sel=17
4858 19:54:05.789246 sv_algorithm_assistance_LP4_1600
4859 19:54:05.792713 ============ PULL DRAM RESETB DOWN ============
4860 19:54:05.795687 ========== PULL DRAM RESETB DOWN end =========
4861 19:54:05.802143 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 19:54:05.805663 ===================================
4863 19:54:05.805745 LPDDR4 DRAM CONFIGURATION
4864 19:54:05.808841 ===================================
4865 19:54:05.812513 EX_ROW_EN[0] = 0x0
4866 19:54:05.815541 EX_ROW_EN[1] = 0x0
4867 19:54:05.815646 LP4Y_EN = 0x0
4868 19:54:05.819078 WORK_FSP = 0x0
4869 19:54:05.819182 WL = 0x3
4870 19:54:05.822320 RL = 0x3
4871 19:54:05.822394 BL = 0x2
4872 19:54:05.825912 RPST = 0x0
4873 19:54:05.825993 RD_PRE = 0x0
4874 19:54:05.829109 WR_PRE = 0x1
4875 19:54:05.829184 WR_PST = 0x0
4876 19:54:05.832268 DBI_WR = 0x0
4877 19:54:05.832339 DBI_RD = 0x0
4878 19:54:05.835802 OTF = 0x1
4879 19:54:05.838934 ===================================
4880 19:54:05.842430 ===================================
4881 19:54:05.842506 ANA top config
4882 19:54:05.845361 ===================================
4883 19:54:05.848681 DLL_ASYNC_EN = 0
4884 19:54:05.852041 ALL_SLAVE_EN = 1
4885 19:54:05.855488 NEW_RANK_MODE = 1
4886 19:54:05.855597 DLL_IDLE_MODE = 1
4887 19:54:05.858896 LP45_APHY_COMB_EN = 1
4888 19:54:05.862400 TX_ODT_DIS = 1
4889 19:54:05.865485 NEW_8X_MODE = 1
4890 19:54:05.868706 ===================================
4891 19:54:05.871894 ===================================
4892 19:54:05.875673 data_rate = 1866
4893 19:54:05.875761 CKR = 1
4894 19:54:05.878612 DQ_P2S_RATIO = 8
4895 19:54:05.881653 ===================================
4896 19:54:05.885432 CA_P2S_RATIO = 8
4897 19:54:05.888599 DQ_CA_OPEN = 0
4898 19:54:05.891733 DQ_SEMI_OPEN = 0
4899 19:54:05.894970 CA_SEMI_OPEN = 0
4900 19:54:05.895048 CA_FULL_RATE = 0
4901 19:54:05.898456 DQ_CKDIV4_EN = 1
4902 19:54:05.901706 CA_CKDIV4_EN = 1
4903 19:54:05.904869 CA_PREDIV_EN = 0
4904 19:54:05.908374 PH8_DLY = 0
4905 19:54:05.911761 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4906 19:54:05.911833 DQ_AAMCK_DIV = 4
4907 19:54:05.915335 CA_AAMCK_DIV = 4
4908 19:54:05.918482 CA_ADMCK_DIV = 4
4909 19:54:05.921594 DQ_TRACK_CA_EN = 0
4910 19:54:05.925190 CA_PICK = 933
4911 19:54:05.928074 CA_MCKIO = 933
4912 19:54:05.931734 MCKIO_SEMI = 0
4913 19:54:05.931808 PLL_FREQ = 3732
4914 19:54:05.934852 DQ_UI_PI_RATIO = 32
4915 19:54:05.938508 CA_UI_PI_RATIO = 0
4916 19:54:05.941565 ===================================
4917 19:54:05.944769 ===================================
4918 19:54:05.948597 memory_type:LPDDR4
4919 19:54:05.948706 GP_NUM : 10
4920 19:54:05.951557 SRAM_EN : 1
4921 19:54:05.955092 MD32_EN : 0
4922 19:54:05.958469 ===================================
4923 19:54:05.958574 [ANA_INIT] >>>>>>>>>>>>>>
4924 19:54:05.961875 <<<<<< [CONFIGURE PHASE]: ANA_TX
4925 19:54:05.965049 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4926 19:54:05.968440 ===================================
4927 19:54:05.971920 data_rate = 1866,PCW = 0X8f00
4928 19:54:05.975056 ===================================
4929 19:54:05.978247 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4930 19:54:05.985002 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 19:54:05.988326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 19:54:05.994680 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4933 19:54:05.998512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4934 19:54:06.001764 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4935 19:54:06.001839 [ANA_INIT] flow start
4936 19:54:06.004787 [ANA_INIT] PLL >>>>>>>>
4937 19:54:06.008224 [ANA_INIT] PLL <<<<<<<<
4938 19:54:06.011235 [ANA_INIT] MIDPI >>>>>>>>
4939 19:54:06.011339 [ANA_INIT] MIDPI <<<<<<<<
4940 19:54:06.015152 [ANA_INIT] DLL >>>>>>>>
4941 19:54:06.018064 [ANA_INIT] flow end
4942 19:54:06.021516 ============ LP4 DIFF to SE enter ============
4943 19:54:06.024458 ============ LP4 DIFF to SE exit ============
4944 19:54:06.028287 [ANA_INIT] <<<<<<<<<<<<<
4945 19:54:06.031309 [Flow] Enable top DCM control >>>>>
4946 19:54:06.034911 [Flow] Enable top DCM control <<<<<
4947 19:54:06.037918 Enable DLL master slave shuffle
4948 19:54:06.041583 ==============================================================
4949 19:54:06.044580 Gating Mode config
4950 19:54:06.048394 ==============================================================
4951 19:54:06.051560 Config description:
4952 19:54:06.061477 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4953 19:54:06.068109 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4954 19:54:06.071377 SELPH_MODE 0: By rank 1: By Phase
4955 19:54:06.077953 ==============================================================
4956 19:54:06.081332 GAT_TRACK_EN = 1
4957 19:54:06.084397 RX_GATING_MODE = 2
4958 19:54:06.087916 RX_GATING_TRACK_MODE = 2
4959 19:54:06.091018 SELPH_MODE = 1
4960 19:54:06.094870 PICG_EARLY_EN = 1
4961 19:54:06.094955 VALID_LAT_VALUE = 1
4962 19:54:06.101098 ==============================================================
4963 19:54:06.104268 Enter into Gating configuration >>>>
4964 19:54:06.108025 Exit from Gating configuration <<<<
4965 19:54:06.111246 Enter into DVFS_PRE_config >>>>>
4966 19:54:06.121437 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4967 19:54:06.124394 Exit from DVFS_PRE_config <<<<<
4968 19:54:06.127432 Enter into PICG configuration >>>>
4969 19:54:06.130768 Exit from PICG configuration <<<<
4970 19:54:06.134238 [RX_INPUT] configuration >>>>>
4971 19:54:06.137860 [RX_INPUT] configuration <<<<<
4972 19:54:06.144049 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4973 19:54:06.147618 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4974 19:54:06.154525 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 19:54:06.161194 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 19:54:06.167508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 19:54:06.174372 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 19:54:06.177463 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4979 19:54:06.180829 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4980 19:54:06.184371 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4981 19:54:06.187475 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4982 19:54:06.194203 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4983 19:54:06.197544 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 19:54:06.200715 ===================================
4985 19:54:06.204474 LPDDR4 DRAM CONFIGURATION
4986 19:54:06.207733 ===================================
4987 19:54:06.207815 EX_ROW_EN[0] = 0x0
4988 19:54:06.210839 EX_ROW_EN[1] = 0x0
4989 19:54:06.210924 LP4Y_EN = 0x0
4990 19:54:06.213964 WORK_FSP = 0x0
4991 19:54:06.214067 WL = 0x3
4992 19:54:06.217748 RL = 0x3
4993 19:54:06.217829 BL = 0x2
4994 19:54:06.220757 RPST = 0x0
4995 19:54:06.224194 RD_PRE = 0x0
4996 19:54:06.224271 WR_PRE = 0x1
4997 19:54:06.227558 WR_PST = 0x0
4998 19:54:06.227689 DBI_WR = 0x0
4999 19:54:06.230593 DBI_RD = 0x0
5000 19:54:06.230698 OTF = 0x1
5001 19:54:06.234190 ===================================
5002 19:54:06.237681 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5003 19:54:06.243923 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5004 19:54:06.247422 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 19:54:06.250994 ===================================
5006 19:54:06.254434 LPDDR4 DRAM CONFIGURATION
5007 19:54:06.257325 ===================================
5008 19:54:06.257429 EX_ROW_EN[0] = 0x10
5009 19:54:06.260805 EX_ROW_EN[1] = 0x0
5010 19:54:06.260907 LP4Y_EN = 0x0
5011 19:54:06.264506 WORK_FSP = 0x0
5012 19:54:06.264589 WL = 0x3
5013 19:54:06.267496 RL = 0x3
5014 19:54:06.267597 BL = 0x2
5015 19:54:06.271221 RPST = 0x0
5016 19:54:06.271322 RD_PRE = 0x0
5017 19:54:06.274437 WR_PRE = 0x1
5018 19:54:06.274539 WR_PST = 0x0
5019 19:54:06.277621 DBI_WR = 0x0
5020 19:54:06.277717 DBI_RD = 0x0
5021 19:54:06.280807 OTF = 0x1
5022 19:54:06.284407 ===================================
5023 19:54:06.290978 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5024 19:54:06.294038 nWR fixed to 30
5025 19:54:06.297624 [ModeRegInit_LP4] CH0 RK0
5026 19:54:06.297732 [ModeRegInit_LP4] CH0 RK1
5027 19:54:06.301004 [ModeRegInit_LP4] CH1 RK0
5028 19:54:06.304574 [ModeRegInit_LP4] CH1 RK1
5029 19:54:06.304647 match AC timing 9
5030 19:54:06.311109 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5031 19:54:06.314255 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5032 19:54:06.317364 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5033 19:54:06.323549 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5034 19:54:06.327363 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5035 19:54:06.327438 ==
5036 19:54:06.330632 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 19:54:06.334002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5038 19:54:06.334078 ==
5039 19:54:06.340530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5040 19:54:06.347047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5041 19:54:06.350643 [CA 0] Center 37 (6~68) winsize 63
5042 19:54:06.353747 [CA 1] Center 37 (6~68) winsize 63
5043 19:54:06.356899 [CA 2] Center 34 (4~65) winsize 62
5044 19:54:06.360508 [CA 3] Center 34 (3~65) winsize 63
5045 19:54:06.363536 [CA 4] Center 33 (3~63) winsize 61
5046 19:54:06.367024 [CA 5] Center 32 (2~62) winsize 61
5047 19:54:06.367102
5048 19:54:06.370419 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5049 19:54:06.370501
5050 19:54:06.373832 [CATrainingPosCal] consider 1 rank data
5051 19:54:06.376956 u2DelayCellTimex100 = 270/100 ps
5052 19:54:06.380066 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5053 19:54:06.383866 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5054 19:54:06.387003 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5055 19:54:06.390251 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5056 19:54:06.393958 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5057 19:54:06.400116 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5058 19:54:06.400208
5059 19:54:06.403555 CA PerBit enable=1, Macro0, CA PI delay=32
5060 19:54:06.403667
5061 19:54:06.406993 [CBTSetCACLKResult] CA Dly = 32
5062 19:54:06.407108 CS Dly: 5 (0~36)
5063 19:54:06.407202 ==
5064 19:54:06.410035 Dram Type= 6, Freq= 0, CH_0, rank 1
5065 19:54:06.413506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 19:54:06.417218 ==
5067 19:54:06.420398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 19:54:06.426646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 19:54:06.430425 [CA 0] Center 37 (6~68) winsize 63
5070 19:54:06.433543 [CA 1] Center 37 (6~68) winsize 63
5071 19:54:06.436805 [CA 2] Center 34 (4~65) winsize 62
5072 19:54:06.439958 [CA 3] Center 34 (3~65) winsize 63
5073 19:54:06.443193 [CA 4] Center 32 (2~63) winsize 62
5074 19:54:06.446688 [CA 5] Center 32 (2~62) winsize 61
5075 19:54:06.446770
5076 19:54:06.450325 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 19:54:06.450401
5078 19:54:06.453226 [CATrainingPosCal] consider 2 rank data
5079 19:54:06.456610 u2DelayCellTimex100 = 270/100 ps
5080 19:54:06.460379 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5081 19:54:06.463331 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5082 19:54:06.466493 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5083 19:54:06.470283 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5084 19:54:06.476510 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5085 19:54:06.479904 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5086 19:54:06.479980
5087 19:54:06.483366 CA PerBit enable=1, Macro0, CA PI delay=32
5088 19:54:06.483467
5089 19:54:06.486509 [CBTSetCACLKResult] CA Dly = 32
5090 19:54:06.486627 CS Dly: 5 (0~37)
5091 19:54:06.486717
5092 19:54:06.490090 ----->DramcWriteLeveling(PI) begin...
5093 19:54:06.490166 ==
5094 19:54:06.493177 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 19:54:06.499945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 19:54:06.500055 ==
5097 19:54:06.503193 Write leveling (Byte 0): 33 => 33
5098 19:54:06.503325 Write leveling (Byte 1): 30 => 30
5099 19:54:06.506981 DramcWriteLeveling(PI) end<-----
5100 19:54:06.507063
5101 19:54:06.507126 ==
5102 19:54:06.509967 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 19:54:06.516563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 19:54:06.516639 ==
5105 19:54:06.519927 [Gating] SW mode calibration
5106 19:54:06.526483 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 19:54:06.529756 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5108 19:54:06.536625 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5109 19:54:06.539806 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 19:54:06.543054 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 19:54:06.549869 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 19:54:06.553238 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 19:54:06.556562 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 19:54:06.562811 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5115 19:54:06.566344 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
5116 19:54:06.569987 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5117 19:54:06.576755 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 19:54:06.579846 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 19:54:06.582903 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 19:54:06.589861 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 19:54:06.592844 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 19:54:06.595966 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5123 19:54:06.602756 0 15 28 | B1->B0 | 2525 4141 | 0 1 | (0 0) (0 0)
5124 19:54:06.605879 1 0 0 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5125 19:54:06.609147 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 19:54:06.616322 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 19:54:06.619341 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 19:54:06.622818 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 19:54:06.625746 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 19:54:06.633054 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5131 19:54:06.636017 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5132 19:54:06.639200 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 19:54:06.646240 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 19:54:06.649417 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 19:54:06.652487 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 19:54:06.659184 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 19:54:06.662383 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 19:54:06.665817 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 19:54:06.672738 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 19:54:06.676320 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 19:54:06.679310 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 19:54:06.686393 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 19:54:06.689487 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 19:54:06.692573 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 19:54:06.699538 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 19:54:06.702577 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5147 19:54:06.706253 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5148 19:54:06.709452 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 19:54:06.712617 Total UI for P1: 0, mck2ui 16
5150 19:54:06.715845 best dqsien dly found for B0: ( 1, 2, 26)
5151 19:54:06.719546 Total UI for P1: 0, mck2ui 16
5152 19:54:06.722710 best dqsien dly found for B1: ( 1, 2, 30)
5153 19:54:06.726263 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5154 19:54:06.729579 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5155 19:54:06.732648
5156 19:54:06.735716 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5157 19:54:06.739159 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5158 19:54:06.742410 [Gating] SW calibration Done
5159 19:54:06.742518 ==
5160 19:54:06.745843 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 19:54:06.749249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 19:54:06.749330 ==
5163 19:54:06.749395 RX Vref Scan: 0
5164 19:54:06.752965
5165 19:54:06.753041 RX Vref 0 -> 0, step: 1
5166 19:54:06.753105
5167 19:54:06.756163 RX Delay -80 -> 252, step: 8
5168 19:54:06.759291 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5169 19:54:06.762437 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5170 19:54:06.768995 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5171 19:54:06.772296 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5172 19:54:06.775623 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5173 19:54:06.779189 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5174 19:54:06.782211 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5175 19:54:06.785671 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5176 19:54:06.792213 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5177 19:54:06.795873 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5178 19:54:06.799002 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5179 19:54:06.802671 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5180 19:54:06.805879 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5181 19:54:06.808803 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5182 19:54:06.815804 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5183 19:54:06.819028 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5184 19:54:06.819113 ==
5185 19:54:06.822288 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 19:54:06.825455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 19:54:06.825543 ==
5188 19:54:06.829107 DQS Delay:
5189 19:54:06.829192 DQS0 = 0, DQS1 = 0
5190 19:54:06.829260 DQM Delay:
5191 19:54:06.832266 DQM0 = 104, DQM1 = 95
5192 19:54:06.832357 DQ Delay:
5193 19:54:06.836082 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5194 19:54:06.839105 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5195 19:54:06.842317 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5196 19:54:06.845924 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5197 19:54:06.846007
5198 19:54:06.846072
5199 19:54:06.848800 ==
5200 19:54:06.848880 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 19:54:06.855517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 19:54:06.855594 ==
5203 19:54:06.855686
5204 19:54:06.855819
5205 19:54:06.858760 TX Vref Scan disable
5206 19:54:06.858853 == TX Byte 0 ==
5207 19:54:06.862417 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5208 19:54:06.868670 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5209 19:54:06.868746 == TX Byte 1 ==
5210 19:54:06.872378 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5211 19:54:06.878701 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5212 19:54:06.878780 ==
5213 19:54:06.882197 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 19:54:06.885543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 19:54:06.885655 ==
5216 19:54:06.885719
5217 19:54:06.885780
5218 19:54:06.888955 TX Vref Scan disable
5219 19:54:06.892162 == TX Byte 0 ==
5220 19:54:06.895283 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5221 19:54:06.898872 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5222 19:54:06.901887 == TX Byte 1 ==
5223 19:54:06.905460 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5224 19:54:06.908625 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5225 19:54:06.908717
5226 19:54:06.908780 [DATLAT]
5227 19:54:06.911784 Freq=933, CH0 RK0
5228 19:54:06.911878
5229 19:54:06.915485 DATLAT Default: 0xd
5230 19:54:06.915559 0, 0xFFFF, sum = 0
5231 19:54:06.918631 1, 0xFFFF, sum = 0
5232 19:54:06.918710 2, 0xFFFF, sum = 0
5233 19:54:06.922011 3, 0xFFFF, sum = 0
5234 19:54:06.922107 4, 0xFFFF, sum = 0
5235 19:54:06.925682 5, 0xFFFF, sum = 0
5236 19:54:06.925757 6, 0xFFFF, sum = 0
5237 19:54:06.928775 7, 0xFFFF, sum = 0
5238 19:54:06.928871 8, 0xFFFF, sum = 0
5239 19:54:06.931878 9, 0xFFFF, sum = 0
5240 19:54:06.931968 10, 0x0, sum = 1
5241 19:54:06.935562 11, 0x0, sum = 2
5242 19:54:06.935682 12, 0x0, sum = 3
5243 19:54:06.938795 13, 0x0, sum = 4
5244 19:54:06.938908 best_step = 11
5245 19:54:06.939002
5246 19:54:06.939117 ==
5247 19:54:06.941966 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 19:54:06.945063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 19:54:06.945173 ==
5250 19:54:06.948378 RX Vref Scan: 1
5251 19:54:06.948465
5252 19:54:06.952103 RX Vref 0 -> 0, step: 1
5253 19:54:06.952193
5254 19:54:06.952256 RX Delay -45 -> 252, step: 4
5255 19:54:06.955157
5256 19:54:06.955238 Set Vref, RX VrefLevel [Byte0]: 56
5257 19:54:06.958371 [Byte1]: 50
5258 19:54:06.963201
5259 19:54:06.963279 Final RX Vref Byte 0 = 56 to rank0
5260 19:54:06.966648 Final RX Vref Byte 1 = 50 to rank0
5261 19:54:06.970074 Final RX Vref Byte 0 = 56 to rank1
5262 19:54:06.973767 Final RX Vref Byte 1 = 50 to rank1==
5263 19:54:06.976970 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 19:54:06.983618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 19:54:06.983706 ==
5266 19:54:06.983772 DQS Delay:
5267 19:54:06.983839 DQS0 = 0, DQS1 = 0
5268 19:54:06.987039 DQM Delay:
5269 19:54:06.987124 DQM0 = 105, DQM1 = 96
5270 19:54:06.990035 DQ Delay:
5271 19:54:06.993400 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5272 19:54:06.996805 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5273 19:54:06.999862 DQ8 =86, DQ9 =90, DQ10 =98, DQ11 =92
5274 19:54:07.003587 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =102
5275 19:54:07.003671
5276 19:54:07.003767
5277 19:54:07.010124 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5278 19:54:07.013579 CH0 RK0: MR19=505, MR18=332B
5279 19:54:07.020284 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5280 19:54:07.020367
5281 19:54:07.023518 ----->DramcWriteLeveling(PI) begin...
5282 19:54:07.023596 ==
5283 19:54:07.026642 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 19:54:07.030148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 19:54:07.030256 ==
5286 19:54:07.033211 Write leveling (Byte 0): 34 => 34
5287 19:54:07.036902 Write leveling (Byte 1): 28 => 28
5288 19:54:07.040017 DramcWriteLeveling(PI) end<-----
5289 19:54:07.040104
5290 19:54:07.040171 ==
5291 19:54:07.043086 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 19:54:07.050002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 19:54:07.050090 ==
5294 19:54:07.050156 [Gating] SW mode calibration
5295 19:54:07.059916 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5296 19:54:07.063089 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5297 19:54:07.066270 0 14 0 | B1->B0 | 3131 2f2f | 0 1 | (0 0) (1 1)
5298 19:54:07.073178 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 19:54:07.076628 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 19:54:07.079974 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 19:54:07.086270 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 19:54:07.089768 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 19:54:07.093260 0 14 24 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
5304 19:54:07.099438 0 14 28 | B1->B0 | 2a2a 2a2a | 0 0 | (0 0) (0 0)
5305 19:54:07.102858 0 15 0 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
5306 19:54:07.106436 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 19:54:07.113009 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 19:54:07.116165 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 19:54:07.119905 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 19:54:07.126408 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 19:54:07.130076 0 15 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
5312 19:54:07.132972 0 15 28 | B1->B0 | 3a3a 3838 | 0 1 | (1 1) (0 0)
5313 19:54:07.136691 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5314 19:54:07.143156 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 19:54:07.146849 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 19:54:07.150067 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 19:54:07.156618 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 19:54:07.159747 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 19:54:07.163337 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 19:54:07.169579 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5321 19:54:07.173365 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5322 19:54:07.176522 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 19:54:07.183349 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 19:54:07.186286 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 19:54:07.189563 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 19:54:07.196342 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 19:54:07.199910 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 19:54:07.203013 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 19:54:07.210092 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 19:54:07.213015 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 19:54:07.216536 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 19:54:07.223266 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 19:54:07.226407 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 19:54:07.229961 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 19:54:07.236651 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 19:54:07.239839 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5337 19:54:07.242951 Total UI for P1: 0, mck2ui 16
5338 19:54:07.246489 best dqsien dly found for B1: ( 1, 2, 26)
5339 19:54:07.249256 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 19:54:07.252865 Total UI for P1: 0, mck2ui 16
5341 19:54:07.255964 best dqsien dly found for B0: ( 1, 2, 28)
5342 19:54:07.259744 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5343 19:54:07.262907 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5344 19:54:07.262985
5345 19:54:07.266039 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5346 19:54:07.273018 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5347 19:54:07.273102 [Gating] SW calibration Done
5348 19:54:07.273168 ==
5349 19:54:07.276226 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 19:54:07.282579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 19:54:07.282656 ==
5352 19:54:07.282720 RX Vref Scan: 0
5353 19:54:07.282782
5354 19:54:07.286072 RX Vref 0 -> 0, step: 1
5355 19:54:07.286146
5356 19:54:07.289279 RX Delay -80 -> 252, step: 8
5357 19:54:07.292944 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5358 19:54:07.296416 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5359 19:54:07.299747 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5360 19:54:07.302659 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5361 19:54:07.309658 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5362 19:54:07.312780 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5363 19:54:07.315739 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5364 19:54:07.319176 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5365 19:54:07.322659 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5366 19:54:07.328997 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5367 19:54:07.332744 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5368 19:54:07.335784 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5369 19:54:07.339513 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5370 19:54:07.342339 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5371 19:54:07.346012 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5372 19:54:07.352381 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5373 19:54:07.352460 ==
5374 19:54:07.355921 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 19:54:07.359339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 19:54:07.359414 ==
5377 19:54:07.359478 DQS Delay:
5378 19:54:07.362936 DQS0 = 0, DQS1 = 0
5379 19:54:07.363012 DQM Delay:
5380 19:54:07.365679 DQM0 = 104, DQM1 = 94
5381 19:54:07.365749 DQ Delay:
5382 19:54:07.369382 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5383 19:54:07.372440 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5384 19:54:07.375620 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5385 19:54:07.379481 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5386 19:54:07.379554
5387 19:54:07.379623
5388 19:54:07.379694 ==
5389 19:54:07.382581 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 19:54:07.385845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 19:54:07.389151 ==
5392 19:54:07.389221
5393 19:54:07.389284
5394 19:54:07.389350 TX Vref Scan disable
5395 19:54:07.392293 == TX Byte 0 ==
5396 19:54:07.395448 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5397 19:54:07.399163 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5398 19:54:07.402247 == TX Byte 1 ==
5399 19:54:07.405969 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5400 19:54:07.409117 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5401 19:54:07.412061 ==
5402 19:54:07.415383 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 19:54:07.418577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 19:54:07.418650 ==
5405 19:54:07.418713
5406 19:54:07.418772
5407 19:54:07.422244 TX Vref Scan disable
5408 19:54:07.422328 == TX Byte 0 ==
5409 19:54:07.428952 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5410 19:54:07.431812 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5411 19:54:07.431894 == TX Byte 1 ==
5412 19:54:07.438386 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5413 19:54:07.442335 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5414 19:54:07.442417
5415 19:54:07.442483 [DATLAT]
5416 19:54:07.445275 Freq=933, CH0 RK1
5417 19:54:07.445350
5418 19:54:07.445413 DATLAT Default: 0xb
5419 19:54:07.448859 0, 0xFFFF, sum = 0
5420 19:54:07.448973 1, 0xFFFF, sum = 0
5421 19:54:07.452069 2, 0xFFFF, sum = 0
5422 19:54:07.452147 3, 0xFFFF, sum = 0
5423 19:54:07.455249 4, 0xFFFF, sum = 0
5424 19:54:07.455329 5, 0xFFFF, sum = 0
5425 19:54:07.458495 6, 0xFFFF, sum = 0
5426 19:54:07.462181 7, 0xFFFF, sum = 0
5427 19:54:07.462257 8, 0xFFFF, sum = 0
5428 19:54:07.465172 9, 0xFFFF, sum = 0
5429 19:54:07.465248 10, 0x0, sum = 1
5430 19:54:07.465320 11, 0x0, sum = 2
5431 19:54:07.468944 12, 0x0, sum = 3
5432 19:54:07.469037 13, 0x0, sum = 4
5433 19:54:07.472335 best_step = 11
5434 19:54:07.472410
5435 19:54:07.472481 ==
5436 19:54:07.475280 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 19:54:07.478852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 19:54:07.478948 ==
5439 19:54:07.482030 RX Vref Scan: 0
5440 19:54:07.482111
5441 19:54:07.482181 RX Vref 0 -> 0, step: 1
5442 19:54:07.482246
5443 19:54:07.485196 RX Delay -45 -> 252, step: 4
5444 19:54:07.492875 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5445 19:54:07.496062 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5446 19:54:07.499266 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5447 19:54:07.502434 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5448 19:54:07.505621 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5449 19:54:07.512371 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5450 19:54:07.516162 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5451 19:54:07.519315 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5452 19:54:07.522441 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5453 19:54:07.525877 iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172
5454 19:54:07.532424 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5455 19:54:07.535775 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5456 19:54:07.539131 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5457 19:54:07.542563 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5458 19:54:07.545970 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5459 19:54:07.552259 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5460 19:54:07.552382 ==
5461 19:54:07.555429 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 19:54:07.558773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 19:54:07.558875 ==
5464 19:54:07.558960 DQS Delay:
5465 19:54:07.562233 DQS0 = 0, DQS1 = 0
5466 19:54:07.562348 DQM Delay:
5467 19:54:07.565521 DQM0 = 105, DQM1 = 94
5468 19:54:07.565604 DQ Delay:
5469 19:54:07.569037 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5470 19:54:07.571989 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5471 19:54:07.575750 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5472 19:54:07.578780 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5473 19:54:07.578859
5474 19:54:07.578931
5475 19:54:07.589010 [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5476 19:54:07.589105 CH0 RK1: MR19=505, MR18=2801
5477 19:54:07.595355 CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43
5478 19:54:07.598979 [RxdqsGatingPostProcess] freq 933
5479 19:54:07.605396 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 19:54:07.608558 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 19:54:07.611770 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 19:54:07.615385 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 19:54:07.618438 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 19:54:07.622312 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 19:54:07.625553 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 19:54:07.628637 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 19:54:07.631860 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 19:54:07.631943 Pre-setting of DQS Precalculation
5489 19:54:07.638460 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 19:54:07.638582 ==
5491 19:54:07.641895 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 19:54:07.645617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 19:54:07.645698 ==
5494 19:54:07.651746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 19:54:07.658338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5496 19:54:07.661619 [CA 0] Center 36 (6~67) winsize 62
5497 19:54:07.665038 [CA 1] Center 37 (6~68) winsize 63
5498 19:54:07.668284 [CA 2] Center 35 (5~65) winsize 61
5499 19:54:07.671995 [CA 3] Center 34 (4~65) winsize 62
5500 19:54:07.675265 [CA 4] Center 34 (4~65) winsize 62
5501 19:54:07.678466 [CA 5] Center 33 (3~64) winsize 62
5502 19:54:07.678557
5503 19:54:07.681801 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5504 19:54:07.681878
5505 19:54:07.685011 [CATrainingPosCal] consider 1 rank data
5506 19:54:07.688523 u2DelayCellTimex100 = 270/100 ps
5507 19:54:07.691946 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5508 19:54:07.695063 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5509 19:54:07.698563 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5510 19:54:07.701741 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5511 19:54:07.704980 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5512 19:54:07.708234 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5513 19:54:07.708322
5514 19:54:07.715304 CA PerBit enable=1, Macro0, CA PI delay=33
5515 19:54:07.715384
5516 19:54:07.718384 [CBTSetCACLKResult] CA Dly = 33
5517 19:54:07.718458 CS Dly: 6 (0~37)
5518 19:54:07.718531 ==
5519 19:54:07.721530 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 19:54:07.725268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 19:54:07.725348 ==
5522 19:54:07.731655 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 19:54:07.738039 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5524 19:54:07.741891 [CA 0] Center 36 (6~67) winsize 62
5525 19:54:07.745004 [CA 1] Center 37 (6~68) winsize 63
5526 19:54:07.748460 [CA 2] Center 35 (5~65) winsize 61
5527 19:54:07.751872 [CA 3] Center 34 (4~65) winsize 62
5528 19:54:07.755014 [CA 4] Center 34 (4~65) winsize 62
5529 19:54:07.758191 [CA 5] Center 34 (4~64) winsize 61
5530 19:54:07.758275
5531 19:54:07.761834 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5532 19:54:07.761914
5533 19:54:07.764986 [CATrainingPosCal] consider 2 rank data
5534 19:54:07.768072 u2DelayCellTimex100 = 270/100 ps
5535 19:54:07.771743 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5536 19:54:07.774695 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5537 19:54:07.778190 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5538 19:54:07.781392 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5539 19:54:07.784930 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5540 19:54:07.788320 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5541 19:54:07.788403
5542 19:54:07.794948 CA PerBit enable=1, Macro0, CA PI delay=34
5543 19:54:07.795037
5544 19:54:07.798343 [CBTSetCACLKResult] CA Dly = 34
5545 19:54:07.798418 CS Dly: 7 (0~40)
5546 19:54:07.798489
5547 19:54:07.801185 ----->DramcWriteLeveling(PI) begin...
5548 19:54:07.801295 ==
5549 19:54:07.804669 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 19:54:07.808336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 19:54:07.811492 ==
5552 19:54:07.811575 Write leveling (Byte 0): 25 => 25
5553 19:54:07.814793 Write leveling (Byte 1): 27 => 27
5554 19:54:07.817984 DramcWriteLeveling(PI) end<-----
5555 19:54:07.818063
5556 19:54:07.818127 ==
5557 19:54:07.821139 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 19:54:07.827907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 19:54:07.827998 ==
5560 19:54:07.828101 [Gating] SW mode calibration
5561 19:54:07.838166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 19:54:07.841251 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 19:54:07.847703 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 19:54:07.850896 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 19:54:07.854520 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 19:54:07.857940 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 19:54:07.864439 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 19:54:07.868067 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 19:54:07.871213 0 14 24 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 0)
5570 19:54:07.877996 0 14 28 | B1->B0 | 2424 2323 | 1 0 | (1 0) (1 0)
5571 19:54:07.881168 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 19:54:07.884262 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 19:54:07.891147 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 19:54:07.894447 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 19:54:07.897866 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 19:54:07.904209 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 19:54:07.907450 0 15 24 | B1->B0 | 2424 2c2c | 0 1 | (0 0) (1 1)
5578 19:54:07.910946 0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5579 19:54:07.917834 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 19:54:07.920825 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 19:54:07.924439 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 19:54:07.930708 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 19:54:07.934359 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 19:54:07.937466 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 19:54:07.944236 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5586 19:54:07.947386 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 19:54:07.950579 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 19:54:07.957526 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 19:54:07.960662 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 19:54:07.964251 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 19:54:07.970588 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 19:54:07.974298 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 19:54:07.977266 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 19:54:07.984229 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 19:54:07.987518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 19:54:07.990644 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 19:54:07.993835 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 19:54:08.000657 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 19:54:08.004426 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 19:54:08.007515 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5601 19:54:08.014043 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5602 19:54:08.017125 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 19:54:08.020701 Total UI for P1: 0, mck2ui 16
5604 19:54:08.024040 best dqsien dly found for B0: ( 1, 2, 22)
5605 19:54:08.027447 Total UI for P1: 0, mck2ui 16
5606 19:54:08.030483 best dqsien dly found for B1: ( 1, 2, 22)
5607 19:54:08.033860 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5608 19:54:08.037173 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5609 19:54:08.037251
5610 19:54:08.040413 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5611 19:54:08.043783 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5612 19:54:08.047486 [Gating] SW calibration Done
5613 19:54:08.047571 ==
5614 19:54:08.050694 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 19:54:08.057457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 19:54:08.057570 ==
5617 19:54:08.057635 RX Vref Scan: 0
5618 19:54:08.057696
5619 19:54:08.060585 RX Vref 0 -> 0, step: 1
5620 19:54:08.060654
5621 19:54:08.063814 RX Delay -80 -> 252, step: 8
5622 19:54:08.066935 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5623 19:54:08.070546 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5624 19:54:08.073979 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5625 19:54:08.077331 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5626 19:54:08.080751 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5627 19:54:08.086964 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5628 19:54:08.090748 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5629 19:54:08.093880 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5630 19:54:08.097086 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5631 19:54:08.100718 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5632 19:54:08.103873 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5633 19:54:08.110205 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5634 19:54:08.114043 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5635 19:54:08.117177 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5636 19:54:08.120305 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5637 19:54:08.123851 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5638 19:54:08.126978 ==
5639 19:54:08.127053 Dram Type= 6, Freq= 0, CH_1, rank 0
5640 19:54:08.133598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5641 19:54:08.133683 ==
5642 19:54:08.133792 DQS Delay:
5643 19:54:08.137022 DQS0 = 0, DQS1 = 0
5644 19:54:08.137099 DQM Delay:
5645 19:54:08.140390 DQM0 = 102, DQM1 = 98
5646 19:54:08.140467 DQ Delay:
5647 19:54:08.143834 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5648 19:54:08.146770 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5649 19:54:08.150328 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5650 19:54:08.153817 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5651 19:54:08.153900
5652 19:54:08.153967
5653 19:54:08.154027 ==
5654 19:54:08.157491 Dram Type= 6, Freq= 0, CH_1, rank 0
5655 19:54:08.160091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5656 19:54:08.160171 ==
5657 19:54:08.163540
5658 19:54:08.163618
5659 19:54:08.163715 TX Vref Scan disable
5660 19:54:08.166703 == TX Byte 0 ==
5661 19:54:08.170324 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5662 19:54:08.173505 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5663 19:54:08.176720 == TX Byte 1 ==
5664 19:54:08.179852 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5665 19:54:08.183429 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5666 19:54:08.183502 ==
5667 19:54:08.186666 Dram Type= 6, Freq= 0, CH_1, rank 0
5668 19:54:08.193306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5669 19:54:08.193397 ==
5670 19:54:08.193461
5671 19:54:08.193520
5672 19:54:08.193584 TX Vref Scan disable
5673 19:54:08.198035 == TX Byte 0 ==
5674 19:54:08.201093 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5675 19:54:08.207877 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5676 19:54:08.207951 == TX Byte 1 ==
5677 19:54:08.211030 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5678 19:54:08.217346 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5679 19:54:08.217436
5680 19:54:08.217498 [DATLAT]
5681 19:54:08.217563 Freq=933, CH1 RK0
5682 19:54:08.217638
5683 19:54:08.221162 DATLAT Default: 0xd
5684 19:54:08.221266 0, 0xFFFF, sum = 0
5685 19:54:08.224205 1, 0xFFFF, sum = 0
5686 19:54:08.224293 2, 0xFFFF, sum = 0
5687 19:54:08.227285 3, 0xFFFF, sum = 0
5688 19:54:08.231013 4, 0xFFFF, sum = 0
5689 19:54:08.231144 5, 0xFFFF, sum = 0
5690 19:54:08.234220 6, 0xFFFF, sum = 0
5691 19:54:08.234319 7, 0xFFFF, sum = 0
5692 19:54:08.237342 8, 0xFFFF, sum = 0
5693 19:54:08.237413 9, 0xFFFF, sum = 0
5694 19:54:08.241183 10, 0x0, sum = 1
5695 19:54:08.241280 11, 0x0, sum = 2
5696 19:54:08.241354 12, 0x0, sum = 3
5697 19:54:08.244432 13, 0x0, sum = 4
5698 19:54:08.244535 best_step = 11
5699 19:54:08.244596
5700 19:54:08.247598 ==
5701 19:54:08.251062 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 19:54:08.253971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 19:54:08.254047 ==
5704 19:54:08.254110 RX Vref Scan: 1
5705 19:54:08.254169
5706 19:54:08.257322 RX Vref 0 -> 0, step: 1
5707 19:54:08.257397
5708 19:54:08.260915 RX Delay -45 -> 252, step: 4
5709 19:54:08.260989
5710 19:54:08.264662 Set Vref, RX VrefLevel [Byte0]: 55
5711 19:54:08.268006 [Byte1]: 52
5712 19:54:08.268085
5713 19:54:08.270907 Final RX Vref Byte 0 = 55 to rank0
5714 19:54:08.274268 Final RX Vref Byte 1 = 52 to rank0
5715 19:54:08.277679 Final RX Vref Byte 0 = 55 to rank1
5716 19:54:08.281223 Final RX Vref Byte 1 = 52 to rank1==
5717 19:54:08.284365 Dram Type= 6, Freq= 0, CH_1, rank 0
5718 19:54:08.287512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5719 19:54:08.287590 ==
5720 19:54:08.291115 DQS Delay:
5721 19:54:08.291191 DQS0 = 0, DQS1 = 0
5722 19:54:08.294468 DQM Delay:
5723 19:54:08.294544 DQM0 = 103, DQM1 = 100
5724 19:54:08.294614 DQ Delay:
5725 19:54:08.297428 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5726 19:54:08.300740 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5727 19:54:08.304115 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5728 19:54:08.310708 DQ12 =106, DQ13 =106, DQ14 =108, DQ15 =110
5729 19:54:08.310789
5730 19:54:08.310855
5731 19:54:08.317613 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5732 19:54:08.320675 CH1 RK0: MR19=505, MR18=1B32
5733 19:54:08.327583 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5734 19:54:08.327670
5735 19:54:08.330562 ----->DramcWriteLeveling(PI) begin...
5736 19:54:08.330641 ==
5737 19:54:08.333754 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 19:54:08.337496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 19:54:08.337575 ==
5740 19:54:08.340662 Write leveling (Byte 0): 28 => 28
5741 19:54:08.343875 Write leveling (Byte 1): 28 => 28
5742 19:54:08.347675 DramcWriteLeveling(PI) end<-----
5743 19:54:08.347749
5744 19:54:08.347819 ==
5745 19:54:08.350782 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 19:54:08.353946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 19:54:08.354020 ==
5748 19:54:08.357648 [Gating] SW mode calibration
5749 19:54:08.364019 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5750 19:54:08.370805 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5751 19:54:08.373953 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 19:54:08.380845 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 19:54:08.383849 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 19:54:08.387182 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 19:54:08.394271 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 19:54:08.397321 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 19:54:08.400305 0 14 24 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 0)
5758 19:54:08.403803 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
5759 19:54:08.410258 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 19:54:08.413707 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 19:54:08.417039 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 19:54:08.423551 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 19:54:08.427362 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 19:54:08.430392 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 19:54:08.437341 0 15 24 | B1->B0 | 3f3f 2e2e | 0 0 | (0 0) (0 0)
5766 19:54:08.440531 0 15 28 | B1->B0 | 4646 3f3e | 0 1 | (0 0) (0 0)
5767 19:54:08.443707 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 19:54:08.450644 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 19:54:08.453684 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 19:54:08.456828 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 19:54:08.463659 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 19:54:08.466667 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 19:54:08.470201 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 19:54:08.476939 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5775 19:54:08.480232 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 19:54:08.483312 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 19:54:08.490265 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 19:54:08.493236 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 19:54:08.497038 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 19:54:08.503685 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 19:54:08.506766 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 19:54:08.509963 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 19:54:08.516698 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 19:54:08.519994 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 19:54:08.523301 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 19:54:08.529682 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 19:54:08.533336 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 19:54:08.536178 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 19:54:08.542987 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5790 19:54:08.546374 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5791 19:54:08.549401 Total UI for P1: 0, mck2ui 16
5792 19:54:08.553113 best dqsien dly found for B1: ( 1, 2, 24)
5793 19:54:08.556376 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 19:54:08.559478 Total UI for P1: 0, mck2ui 16
5795 19:54:08.563280 best dqsien dly found for B0: ( 1, 2, 28)
5796 19:54:08.566464 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5797 19:54:08.569478 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5798 19:54:08.569598
5799 19:54:08.573206 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5800 19:54:08.579789 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 19:54:08.579873 [Gating] SW calibration Done
5802 19:54:08.579939 ==
5803 19:54:08.582828 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 19:54:08.589909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 19:54:08.589992 ==
5806 19:54:08.590065 RX Vref Scan: 0
5807 19:54:08.590134
5808 19:54:08.593077 RX Vref 0 -> 0, step: 1
5809 19:54:08.593166
5810 19:54:08.596554 RX Delay -80 -> 252, step: 8
5811 19:54:08.599707 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5812 19:54:08.602807 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5813 19:54:08.606463 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5814 19:54:08.612716 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5815 19:54:08.615941 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5816 19:54:08.619766 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5817 19:54:08.622894 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5818 19:54:08.625978 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5819 19:54:08.629710 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5820 19:54:08.636063 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5821 19:54:08.639224 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5822 19:54:08.643000 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5823 19:54:08.646053 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5824 19:54:08.649502 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5825 19:54:08.656276 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5826 19:54:08.659093 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5827 19:54:08.659171 ==
5828 19:54:08.662542 Dram Type= 6, Freq= 0, CH_1, rank 1
5829 19:54:08.666123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 19:54:08.666198 ==
5831 19:54:08.666267 DQS Delay:
5832 19:54:08.669213 DQS0 = 0, DQS1 = 0
5833 19:54:08.669291 DQM Delay:
5834 19:54:08.672378 DQM0 = 103, DQM1 = 99
5835 19:54:08.672452 DQ Delay:
5836 19:54:08.676255 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =99
5837 19:54:08.679272 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =103
5838 19:54:08.682339 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5839 19:54:08.685761 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5840 19:54:08.685847
5841 19:54:08.685915
5842 19:54:08.689190 ==
5843 19:54:08.689274 Dram Type= 6, Freq= 0, CH_1, rank 1
5844 19:54:08.695776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 19:54:08.695859 ==
5846 19:54:08.695936
5847 19:54:08.696001
5848 19:54:08.699446 TX Vref Scan disable
5849 19:54:08.699533 == TX Byte 0 ==
5850 19:54:08.702519 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5851 19:54:08.708963 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5852 19:54:08.709042 == TX Byte 1 ==
5853 19:54:08.712599 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5854 19:54:08.718786 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5855 19:54:08.718866 ==
5856 19:54:08.722643 Dram Type= 6, Freq= 0, CH_1, rank 1
5857 19:54:08.725894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5858 19:54:08.725974 ==
5859 19:54:08.726037
5860 19:54:08.726104
5861 19:54:08.729013 TX Vref Scan disable
5862 19:54:08.732326 == TX Byte 0 ==
5863 19:54:08.735718 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5864 19:54:08.738931 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5865 19:54:08.742063 == TX Byte 1 ==
5866 19:54:08.745956 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5867 19:54:08.749074 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5868 19:54:08.749171
5869 19:54:08.749243 [DATLAT]
5870 19:54:08.752093 Freq=933, CH1 RK1
5871 19:54:08.752169
5872 19:54:08.755523 DATLAT Default: 0xb
5873 19:54:08.755608 0, 0xFFFF, sum = 0
5874 19:54:08.758704 1, 0xFFFF, sum = 0
5875 19:54:08.758785 2, 0xFFFF, sum = 0
5876 19:54:08.762509 3, 0xFFFF, sum = 0
5877 19:54:08.762586 4, 0xFFFF, sum = 0
5878 19:54:08.765626 5, 0xFFFF, sum = 0
5879 19:54:08.765709 6, 0xFFFF, sum = 0
5880 19:54:08.768792 7, 0xFFFF, sum = 0
5881 19:54:08.768904 8, 0xFFFF, sum = 0
5882 19:54:08.771858 9, 0xFFFF, sum = 0
5883 19:54:08.771930 10, 0x0, sum = 1
5884 19:54:08.775459 11, 0x0, sum = 2
5885 19:54:08.775575 12, 0x0, sum = 3
5886 19:54:08.778557 13, 0x0, sum = 4
5887 19:54:08.778641 best_step = 11
5888 19:54:08.778703
5889 19:54:08.778768 ==
5890 19:54:08.781671 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 19:54:08.785169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 19:54:08.788362 ==
5893 19:54:08.788474 RX Vref Scan: 0
5894 19:54:08.788549
5895 19:54:08.792093 RX Vref 0 -> 0, step: 1
5896 19:54:08.792210
5897 19:54:08.795091 RX Delay -45 -> 252, step: 4
5898 19:54:08.798587 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5899 19:54:08.802062 iDelay=203, Bit 1, Center 98 (15 ~ 182) 168
5900 19:54:08.804892 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5901 19:54:08.811457 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5902 19:54:08.815128 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5903 19:54:08.818190 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5904 19:54:08.821451 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5905 19:54:08.825213 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5906 19:54:08.831456 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5907 19:54:08.835240 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5908 19:54:08.838276 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5909 19:54:08.841873 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5910 19:54:08.844991 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5911 19:54:08.851430 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5912 19:54:08.854563 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5913 19:54:08.858152 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5914 19:54:08.858228 ==
5915 19:54:08.861660 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 19:54:08.864783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 19:54:08.864867 ==
5918 19:54:08.868018 DQS Delay:
5919 19:54:08.868097 DQS0 = 0, DQS1 = 0
5920 19:54:08.871277 DQM Delay:
5921 19:54:08.871359 DQM0 = 104, DQM1 = 100
5922 19:54:08.875048 DQ Delay:
5923 19:54:08.875127 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =100
5924 19:54:08.881242 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5925 19:54:08.884876 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92
5926 19:54:08.888078 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5927 19:54:08.888158
5928 19:54:08.888231
5929 19:54:08.894486 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5930 19:54:08.898361 CH1 RK1: MR19=505, MR18=2E01
5931 19:54:08.904680 CH1_RK1: MR19=0x505, MR18=0x2E01, DQSOSC=407, MR23=63, INC=65, DEC=43
5932 19:54:08.907831 [RxdqsGatingPostProcess] freq 933
5933 19:54:08.911687 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5934 19:54:08.914893 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 19:54:08.917973 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 19:54:08.921522 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 19:54:08.924741 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 19:54:08.928068 best DQS0 dly(2T, 0.5T) = (0, 10)
5939 19:54:08.931403 best DQS1 dly(2T, 0.5T) = (0, 10)
5940 19:54:08.934581 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5941 19:54:08.937982 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5942 19:54:08.941313 Pre-setting of DQS Precalculation
5943 19:54:08.945112 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5944 19:54:08.954780 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5945 19:54:08.961165 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5946 19:54:08.961244
5947 19:54:08.961322
5948 19:54:08.964840 [Calibration Summary] 1866 Mbps
5949 19:54:08.964919 CH 0, Rank 0
5950 19:54:08.968333 SW Impedance : PASS
5951 19:54:08.968419 DUTY Scan : NO K
5952 19:54:08.971443 ZQ Calibration : PASS
5953 19:54:08.974560 Jitter Meter : NO K
5954 19:54:08.974637 CBT Training : PASS
5955 19:54:08.977737 Write leveling : PASS
5956 19:54:08.981391 RX DQS gating : PASS
5957 19:54:08.981469 RX DQ/DQS(RDDQC) : PASS
5958 19:54:08.984938 TX DQ/DQS : PASS
5959 19:54:08.985013 RX DATLAT : PASS
5960 19:54:08.987955 RX DQ/DQS(Engine): PASS
5961 19:54:08.991161 TX OE : NO K
5962 19:54:08.991232 All Pass.
5963 19:54:08.991306
5964 19:54:08.991368 CH 0, Rank 1
5965 19:54:08.994955 SW Impedance : PASS
5966 19:54:08.997947 DUTY Scan : NO K
5967 19:54:08.998019 ZQ Calibration : PASS
5968 19:54:09.001472 Jitter Meter : NO K
5969 19:54:09.004512 CBT Training : PASS
5970 19:54:09.004590 Write leveling : PASS
5971 19:54:09.007865 RX DQS gating : PASS
5972 19:54:09.011543 RX DQ/DQS(RDDQC) : PASS
5973 19:54:09.011659 TX DQ/DQS : PASS
5974 19:54:09.014667 RX DATLAT : PASS
5975 19:54:09.017813 RX DQ/DQS(Engine): PASS
5976 19:54:09.017887 TX OE : NO K
5977 19:54:09.020957 All Pass.
5978 19:54:09.021037
5979 19:54:09.021100 CH 1, Rank 0
5980 19:54:09.024179 SW Impedance : PASS
5981 19:54:09.024287 DUTY Scan : NO K
5982 19:54:09.027824 ZQ Calibration : PASS
5983 19:54:09.031243 Jitter Meter : NO K
5984 19:54:09.031328 CBT Training : PASS
5985 19:54:09.034269 Write leveling : PASS
5986 19:54:09.037486 RX DQS gating : PASS
5987 19:54:09.037567 RX DQ/DQS(RDDQC) : PASS
5988 19:54:09.041260 TX DQ/DQS : PASS
5989 19:54:09.041347 RX DATLAT : PASS
5990 19:54:09.044364 RX DQ/DQS(Engine): PASS
5991 19:54:09.047814 TX OE : NO K
5992 19:54:09.047895 All Pass.
5993 19:54:09.047966
5994 19:54:09.048026 CH 1, Rank 1
5995 19:54:09.051301 SW Impedance : PASS
5996 19:54:09.054487 DUTY Scan : NO K
5997 19:54:09.054573 ZQ Calibration : PASS
5998 19:54:09.057332 Jitter Meter : NO K
5999 19:54:09.061050 CBT Training : PASS
6000 19:54:09.061130 Write leveling : PASS
6001 19:54:09.064057 RX DQS gating : PASS
6002 19:54:09.067381 RX DQ/DQS(RDDQC) : PASS
6003 19:54:09.067465 TX DQ/DQS : PASS
6004 19:54:09.070758 RX DATLAT : PASS
6005 19:54:09.074208 RX DQ/DQS(Engine): PASS
6006 19:54:09.074312 TX OE : NO K
6007 19:54:09.077417 All Pass.
6008 19:54:09.077496
6009 19:54:09.077600 DramC Write-DBI off
6010 19:54:09.080658 PER_BANK_REFRESH: Hybrid Mode
6011 19:54:09.080736 TX_TRACKING: ON
6012 19:54:09.090608 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6013 19:54:09.094462 [FAST_K] Save calibration result to emmc
6014 19:54:09.097660 dramc_set_vcore_voltage set vcore to 650000
6015 19:54:09.100856 Read voltage for 400, 6
6016 19:54:09.100951 Vio18 = 0
6017 19:54:09.103968 Vcore = 650000
6018 19:54:09.104051 Vdram = 0
6019 19:54:09.104124 Vddq = 0
6020 19:54:09.104185 Vmddr = 0
6021 19:54:09.110962 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6022 19:54:09.117273 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6023 19:54:09.117359 MEM_TYPE=3, freq_sel=20
6024 19:54:09.120975 sv_algorithm_assistance_LP4_800
6025 19:54:09.124083 ============ PULL DRAM RESETB DOWN ============
6026 19:54:09.130422 ========== PULL DRAM RESETB DOWN end =========
6027 19:54:09.134141 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6028 19:54:09.137511 ===================================
6029 19:54:09.140618 LPDDR4 DRAM CONFIGURATION
6030 19:54:09.143832 ===================================
6031 19:54:09.143918 EX_ROW_EN[0] = 0x0
6032 19:54:09.147625 EX_ROW_EN[1] = 0x0
6033 19:54:09.147745 LP4Y_EN = 0x0
6034 19:54:09.150745 WORK_FSP = 0x0
6035 19:54:09.150828 WL = 0x2
6036 19:54:09.153833 RL = 0x2
6037 19:54:09.157081 BL = 0x2
6038 19:54:09.157162 RPST = 0x0
6039 19:54:09.160701 RD_PRE = 0x0
6040 19:54:09.160781 WR_PRE = 0x1
6041 19:54:09.163966 WR_PST = 0x0
6042 19:54:09.164052 DBI_WR = 0x0
6043 19:54:09.167177 DBI_RD = 0x0
6044 19:54:09.167261 OTF = 0x1
6045 19:54:09.170955 ===================================
6046 19:54:09.174038 ===================================
6047 19:54:09.174118 ANA top config
6048 19:54:09.177207 ===================================
6049 19:54:09.180910 DLL_ASYNC_EN = 0
6050 19:54:09.184352 ALL_SLAVE_EN = 1
6051 19:54:09.187207 NEW_RANK_MODE = 1
6052 19:54:09.190466 DLL_IDLE_MODE = 1
6053 19:54:09.190546 LP45_APHY_COMB_EN = 1
6054 19:54:09.193758 TX_ODT_DIS = 1
6055 19:54:09.197237 NEW_8X_MODE = 1
6056 19:54:09.200368 ===================================
6057 19:54:09.203722 ===================================
6058 19:54:09.207089 data_rate = 800
6059 19:54:09.210374 CKR = 1
6060 19:54:09.210462 DQ_P2S_RATIO = 4
6061 19:54:09.213980 ===================================
6062 19:54:09.216926 CA_P2S_RATIO = 4
6063 19:54:09.220421 DQ_CA_OPEN = 0
6064 19:54:09.223530 DQ_SEMI_OPEN = 1
6065 19:54:09.226783 CA_SEMI_OPEN = 1
6066 19:54:09.230576 CA_FULL_RATE = 0
6067 19:54:09.230655 DQ_CKDIV4_EN = 0
6068 19:54:09.233780 CA_CKDIV4_EN = 1
6069 19:54:09.237071 CA_PREDIV_EN = 0
6070 19:54:09.240246 PH8_DLY = 0
6071 19:54:09.243470 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6072 19:54:09.246588 DQ_AAMCK_DIV = 0
6073 19:54:09.246669 CA_AAMCK_DIV = 0
6074 19:54:09.250353 CA_ADMCK_DIV = 4
6075 19:54:09.253581 DQ_TRACK_CA_EN = 0
6076 19:54:09.256749 CA_PICK = 800
6077 19:54:09.259858 CA_MCKIO = 400
6078 19:54:09.263413 MCKIO_SEMI = 400
6079 19:54:09.266832 PLL_FREQ = 3016
6080 19:54:09.269722 DQ_UI_PI_RATIO = 32
6081 19:54:09.269805 CA_UI_PI_RATIO = 32
6082 19:54:09.273499 ===================================
6083 19:54:09.276701 ===================================
6084 19:54:09.279862 memory_type:LPDDR4
6085 19:54:09.283087 GP_NUM : 10
6086 19:54:09.283163 SRAM_EN : 1
6087 19:54:09.286213 MD32_EN : 0
6088 19:54:09.289960 ===================================
6089 19:54:09.293096 [ANA_INIT] >>>>>>>>>>>>>>
6090 19:54:09.296338 <<<<<< [CONFIGURE PHASE]: ANA_TX
6091 19:54:09.299449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6092 19:54:09.303360 ===================================
6093 19:54:09.303464 data_rate = 800,PCW = 0X7400
6094 19:54:09.306556 ===================================
6095 19:54:09.309482 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6096 19:54:09.316168 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 19:54:09.329608 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 19:54:09.333316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6099 19:54:09.336324 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6100 19:54:09.339686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6101 19:54:09.342649 [ANA_INIT] flow start
6102 19:54:09.342725 [ANA_INIT] PLL >>>>>>>>
6103 19:54:09.346023 [ANA_INIT] PLL <<<<<<<<
6104 19:54:09.349654 [ANA_INIT] MIDPI >>>>>>>>
6105 19:54:09.349736 [ANA_INIT] MIDPI <<<<<<<<
6106 19:54:09.352733 [ANA_INIT] DLL >>>>>>>>
6107 19:54:09.356218 [ANA_INIT] flow end
6108 19:54:09.359778 ============ LP4 DIFF to SE enter ============
6109 19:54:09.362994 ============ LP4 DIFF to SE exit ============
6110 19:54:09.366239 [ANA_INIT] <<<<<<<<<<<<<
6111 19:54:09.369308 [Flow] Enable top DCM control >>>>>
6112 19:54:09.372876 [Flow] Enable top DCM control <<<<<
6113 19:54:09.375861 Enable DLL master slave shuffle
6114 19:54:09.379167 ==============================================================
6115 19:54:09.382875 Gating Mode config
6116 19:54:09.389253 ==============================================================
6117 19:54:09.389332 Config description:
6118 19:54:09.399354 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6119 19:54:09.405736 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6120 19:54:09.412816 SELPH_MODE 0: By rank 1: By Phase
6121 19:54:09.416043 ==============================================================
6122 19:54:09.419203 GAT_TRACK_EN = 0
6123 19:54:09.422399 RX_GATING_MODE = 2
6124 19:54:09.426053 RX_GATING_TRACK_MODE = 2
6125 19:54:09.429209 SELPH_MODE = 1
6126 19:54:09.432302 PICG_EARLY_EN = 1
6127 19:54:09.436111 VALID_LAT_VALUE = 1
6128 19:54:09.439303 ==============================================================
6129 19:54:09.442234 Enter into Gating configuration >>>>
6130 19:54:09.445655 Exit from Gating configuration <<<<
6131 19:54:09.448923 Enter into DVFS_PRE_config >>>>>
6132 19:54:09.462362 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6133 19:54:09.462449 Exit from DVFS_PRE_config <<<<<
6134 19:54:09.465747 Enter into PICG configuration >>>>
6135 19:54:09.469149 Exit from PICG configuration <<<<
6136 19:54:09.472289 [RX_INPUT] configuration >>>>>
6137 19:54:09.475955 [RX_INPUT] configuration <<<<<
6138 19:54:09.482218 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6139 19:54:09.486016 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6140 19:54:09.492590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6141 19:54:09.499159 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6142 19:54:09.505952 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 19:54:09.512262 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 19:54:09.515497 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6145 19:54:09.519291 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6146 19:54:09.522425 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6147 19:54:09.529297 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6148 19:54:09.532433 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6149 19:54:09.535707 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6150 19:54:09.538892 ===================================
6151 19:54:09.541984 LPDDR4 DRAM CONFIGURATION
6152 19:54:09.545708 ===================================
6153 19:54:09.545789 EX_ROW_EN[0] = 0x0
6154 19:54:09.548996 EX_ROW_EN[1] = 0x0
6155 19:54:09.552157 LP4Y_EN = 0x0
6156 19:54:09.552261 WORK_FSP = 0x0
6157 19:54:09.555739 WL = 0x2
6158 19:54:09.555846 RL = 0x2
6159 19:54:09.559168 BL = 0x2
6160 19:54:09.559269 RPST = 0x0
6161 19:54:09.561998 RD_PRE = 0x0
6162 19:54:09.562073 WR_PRE = 0x1
6163 19:54:09.565752 WR_PST = 0x0
6164 19:54:09.565832 DBI_WR = 0x0
6165 19:54:09.568820 DBI_RD = 0x0
6166 19:54:09.568905 OTF = 0x1
6167 19:54:09.571997 ===================================
6168 19:54:09.575904 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6169 19:54:09.582040 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6170 19:54:09.585561 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6171 19:54:09.588741 ===================================
6172 19:54:09.592272 LPDDR4 DRAM CONFIGURATION
6173 19:54:09.595233 ===================================
6174 19:54:09.595317 EX_ROW_EN[0] = 0x10
6175 19:54:09.599198 EX_ROW_EN[1] = 0x0
6176 19:54:09.599281 LP4Y_EN = 0x0
6177 19:54:09.601971 WORK_FSP = 0x0
6178 19:54:09.602057 WL = 0x2
6179 19:54:09.605634 RL = 0x2
6180 19:54:09.608770 BL = 0x2
6181 19:54:09.608869 RPST = 0x0
6182 19:54:09.612127 RD_PRE = 0x0
6183 19:54:09.612205 WR_PRE = 0x1
6184 19:54:09.615232 WR_PST = 0x0
6185 19:54:09.615334 DBI_WR = 0x0
6186 19:54:09.618559 DBI_RD = 0x0
6187 19:54:09.618658 OTF = 0x1
6188 19:54:09.621901 ===================================
6189 19:54:09.628911 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6190 19:54:09.632769 nWR fixed to 30
6191 19:54:09.635744 [ModeRegInit_LP4] CH0 RK0
6192 19:54:09.635848 [ModeRegInit_LP4] CH0 RK1
6193 19:54:09.639582 [ModeRegInit_LP4] CH1 RK0
6194 19:54:09.642800 [ModeRegInit_LP4] CH1 RK1
6195 19:54:09.642920 match AC timing 19
6196 19:54:09.649057 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6197 19:54:09.652286 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6198 19:54:09.655969 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6199 19:54:09.662249 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6200 19:54:09.665726 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6201 19:54:09.665814 ==
6202 19:54:09.669035 Dram Type= 6, Freq= 0, CH_0, rank 0
6203 19:54:09.672502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6204 19:54:09.672589 ==
6205 19:54:09.678851 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6206 19:54:09.685870 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6207 19:54:09.688835 [CA 0] Center 36 (8~64) winsize 57
6208 19:54:09.692486 [CA 1] Center 36 (8~64) winsize 57
6209 19:54:09.695746 [CA 2] Center 36 (8~64) winsize 57
6210 19:54:09.698924 [CA 3] Center 36 (8~64) winsize 57
6211 19:54:09.699015 [CA 4] Center 36 (8~64) winsize 57
6212 19:54:09.702103 [CA 5] Center 36 (8~64) winsize 57
6213 19:54:09.702181
6214 19:54:09.709011 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6215 19:54:09.709092
6216 19:54:09.712218 [CATrainingPosCal] consider 1 rank data
6217 19:54:09.715732 u2DelayCellTimex100 = 270/100 ps
6218 19:54:09.718533 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 19:54:09.722249 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 19:54:09.725273 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 19:54:09.728858 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 19:54:09.732014 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 19:54:09.735078 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 19:54:09.735157
6225 19:54:09.738405 CA PerBit enable=1, Macro0, CA PI delay=36
6226 19:54:09.738491
6227 19:54:09.742031 [CBTSetCACLKResult] CA Dly = 36
6228 19:54:09.745529 CS Dly: 1 (0~32)
6229 19:54:09.745637 ==
6230 19:54:09.748365 Dram Type= 6, Freq= 0, CH_0, rank 1
6231 19:54:09.751710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6232 19:54:09.751813 ==
6233 19:54:09.758277 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6234 19:54:09.765327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6235 19:54:09.765440 [CA 0] Center 36 (8~64) winsize 57
6236 19:54:09.768514 [CA 1] Center 36 (8~64) winsize 57
6237 19:54:09.771592 [CA 2] Center 36 (8~64) winsize 57
6238 19:54:09.775069 [CA 3] Center 36 (8~64) winsize 57
6239 19:54:09.778395 [CA 4] Center 36 (8~64) winsize 57
6240 19:54:09.782070 [CA 5] Center 36 (8~64) winsize 57
6241 19:54:09.782154
6242 19:54:09.785071 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6243 19:54:09.785174
6244 19:54:09.788287 [CATrainingPosCal] consider 2 rank data
6245 19:54:09.791884 u2DelayCellTimex100 = 270/100 ps
6246 19:54:09.794945 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 19:54:09.798699 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 19:54:09.805053 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 19:54:09.808326 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 19:54:09.811446 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 19:54:09.815279 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 19:54:09.815357
6253 19:54:09.818406 CA PerBit enable=1, Macro0, CA PI delay=36
6254 19:54:09.818495
6255 19:54:09.821502 [CBTSetCACLKResult] CA Dly = 36
6256 19:54:09.821613 CS Dly: 1 (0~32)
6257 19:54:09.821715
6258 19:54:09.824715 ----->DramcWriteLeveling(PI) begin...
6259 19:54:09.828078 ==
6260 19:54:09.831431 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 19:54:09.834807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 19:54:09.834910 ==
6263 19:54:09.837961 Write leveling (Byte 0): 40 => 8
6264 19:54:09.841500 Write leveling (Byte 1): 40 => 8
6265 19:54:09.844716 DramcWriteLeveling(PI) end<-----
6266 19:54:09.844821
6267 19:54:09.844916 ==
6268 19:54:09.848402 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 19:54:09.851569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 19:54:09.851680 ==
6271 19:54:09.854726 [Gating] SW mode calibration
6272 19:54:09.861450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6273 19:54:09.864468 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6274 19:54:09.871455 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 19:54:09.875182 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 19:54:09.877893 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 19:54:09.884617 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 19:54:09.888148 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 19:54:09.891431 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 19:54:09.898159 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 19:54:09.901151 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 19:54:09.904864 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 19:54:09.907987 Total UI for P1: 0, mck2ui 16
6284 19:54:09.911073 best dqsien dly found for B0: ( 0, 14, 24)
6285 19:54:09.914380 Total UI for P1: 0, mck2ui 16
6286 19:54:09.917551 best dqsien dly found for B1: ( 0, 14, 24)
6287 19:54:09.921434 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6288 19:54:09.924526 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6289 19:54:09.927789
6290 19:54:09.930881 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 19:54:09.934640 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 19:54:09.937543 [Gating] SW calibration Done
6293 19:54:09.937618 ==
6294 19:54:09.940900 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 19:54:09.944356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 19:54:09.944441 ==
6297 19:54:09.944510 RX Vref Scan: 0
6298 19:54:09.947882
6299 19:54:09.947957 RX Vref 0 -> 0, step: 1
6300 19:54:09.948021
6301 19:54:09.951194 RX Delay -410 -> 252, step: 16
6302 19:54:09.954141 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6303 19:54:09.961007 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6304 19:54:09.964246 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6305 19:54:09.967457 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6306 19:54:09.970592 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6307 19:54:09.977309 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6308 19:54:09.981120 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6309 19:54:09.984025 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6310 19:54:09.987211 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6311 19:54:09.993978 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6312 19:54:09.997373 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6313 19:54:10.000578 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6314 19:54:10.003909 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6315 19:54:10.010738 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6316 19:54:10.013791 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6317 19:54:10.017259 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6318 19:54:10.017460 ==
6319 19:54:10.020913 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 19:54:10.027286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 19:54:10.027421 ==
6322 19:54:10.027525 DQS Delay:
6323 19:54:10.030532 DQS0 = 27, DQS1 = 35
6324 19:54:10.030632 DQM Delay:
6325 19:54:10.030734 DQM0 = 10, DQM1 = 11
6326 19:54:10.033840 DQ Delay:
6327 19:54:10.037184 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6328 19:54:10.037285 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6329 19:54:10.040377 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6330 19:54:10.044098 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6331 19:54:10.044228
6332 19:54:10.044333
6333 19:54:10.047214 ==
6334 19:54:10.050664 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 19:54:10.053743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 19:54:10.053831 ==
6337 19:54:10.053896
6338 19:54:10.053966
6339 19:54:10.057239 TX Vref Scan disable
6340 19:54:10.057356 == TX Byte 0 ==
6341 19:54:10.060689 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6342 19:54:10.067614 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6343 19:54:10.067733 == TX Byte 1 ==
6344 19:54:10.070688 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6345 19:54:10.074031 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6346 19:54:10.077334 ==
6347 19:54:10.080456 Dram Type= 6, Freq= 0, CH_0, rank 0
6348 19:54:10.083688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6349 19:54:10.083789 ==
6350 19:54:10.083895
6351 19:54:10.083997
6352 19:54:10.087601 TX Vref Scan disable
6353 19:54:10.087714 == TX Byte 0 ==
6354 19:54:10.090891 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6355 19:54:10.097190 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6356 19:54:10.097289 == TX Byte 1 ==
6357 19:54:10.100716 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6358 19:54:10.104194 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6359 19:54:10.107186
6360 19:54:10.107289 [DATLAT]
6361 19:54:10.107382 Freq=400, CH0 RK0
6362 19:54:10.107475
6363 19:54:10.110433 DATLAT Default: 0xf
6364 19:54:10.110536 0, 0xFFFF, sum = 0
6365 19:54:10.114165 1, 0xFFFF, sum = 0
6366 19:54:10.114245 2, 0xFFFF, sum = 0
6367 19:54:10.117208 3, 0xFFFF, sum = 0
6368 19:54:10.117291 4, 0xFFFF, sum = 0
6369 19:54:10.120465 5, 0xFFFF, sum = 0
6370 19:54:10.123826 6, 0xFFFF, sum = 0
6371 19:54:10.123936 7, 0xFFFF, sum = 0
6372 19:54:10.126926 8, 0xFFFF, sum = 0
6373 19:54:10.127003 9, 0xFFFF, sum = 0
6374 19:54:10.130378 10, 0xFFFF, sum = 0
6375 19:54:10.130486 11, 0xFFFF, sum = 0
6376 19:54:10.134034 12, 0xFFFF, sum = 0
6377 19:54:10.134115 13, 0x0, sum = 1
6378 19:54:10.136870 14, 0x0, sum = 2
6379 19:54:10.136971 15, 0x0, sum = 3
6380 19:54:10.140652 16, 0x0, sum = 4
6381 19:54:10.140756 best_step = 14
6382 19:54:10.140851
6383 19:54:10.140939 ==
6384 19:54:10.143837 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 19:54:10.146885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 19:54:10.146990 ==
6387 19:54:10.150665 RX Vref Scan: 1
6388 19:54:10.150766
6389 19:54:10.153653 RX Vref 0 -> 0, step: 1
6390 19:54:10.153740
6391 19:54:10.153819 RX Delay -311 -> 252, step: 8
6392 19:54:10.157266
6393 19:54:10.157374 Set Vref, RX VrefLevel [Byte0]: 56
6394 19:54:10.160394 [Byte1]: 50
6395 19:54:10.165789
6396 19:54:10.165895 Final RX Vref Byte 0 = 56 to rank0
6397 19:54:10.169230 Final RX Vref Byte 1 = 50 to rank0
6398 19:54:10.172855 Final RX Vref Byte 0 = 56 to rank1
6399 19:54:10.175754 Final RX Vref Byte 1 = 50 to rank1==
6400 19:54:10.178930 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 19:54:10.185655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 19:54:10.185766 ==
6403 19:54:10.185858 DQS Delay:
6404 19:54:10.188790 DQS0 = 28, DQS1 = 36
6405 19:54:10.188866 DQM Delay:
6406 19:54:10.188937 DQM0 = 11, DQM1 = 13
6407 19:54:10.192680 DQ Delay:
6408 19:54:10.195834 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6409 19:54:10.195910 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6410 19:54:10.198913 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6411 19:54:10.202663 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6412 19:54:10.202738
6413 19:54:10.205815
6414 19:54:10.212840 [DQSOSCAuto] RK0, (LSB)MR18= 0xd4c1, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 383 ps
6415 19:54:10.215811 CH0 RK0: MR19=C0C, MR18=D4C1
6416 19:54:10.222648 CH0_RK0: MR19=0xC0C, MR18=0xD4C1, DQSOSC=383, MR23=63, INC=402, DEC=268
6417 19:54:10.222726 ==
6418 19:54:10.225739 Dram Type= 6, Freq= 0, CH_0, rank 1
6419 19:54:10.228908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 19:54:10.228982 ==
6421 19:54:10.232075 [Gating] SW mode calibration
6422 19:54:10.238607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6423 19:54:10.245619 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6424 19:54:10.248830 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 19:54:10.252270 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 19:54:10.255510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 19:54:10.261970 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 19:54:10.265624 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 19:54:10.268699 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 19:54:10.275232 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 19:54:10.278747 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 19:54:10.282153 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 19:54:10.285248 Total UI for P1: 0, mck2ui 16
6434 19:54:10.288921 best dqsien dly found for B0: ( 0, 14, 24)
6435 19:54:10.292048 Total UI for P1: 0, mck2ui 16
6436 19:54:10.295277 best dqsien dly found for B1: ( 0, 14, 24)
6437 19:54:10.298999 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6438 19:54:10.302045 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6439 19:54:10.304987
6440 19:54:10.308826 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 19:54:10.311998 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 19:54:10.315062 [Gating] SW calibration Done
6443 19:54:10.315166 ==
6444 19:54:10.318331 Dram Type= 6, Freq= 0, CH_0, rank 1
6445 19:54:10.322117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 19:54:10.322198 ==
6447 19:54:10.322261 RX Vref Scan: 0
6448 19:54:10.325250
6449 19:54:10.325330 RX Vref 0 -> 0, step: 1
6450 19:54:10.325394
6451 19:54:10.328784 RX Delay -410 -> 252, step: 16
6452 19:54:10.331772 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6453 19:54:10.338355 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6454 19:54:10.342188 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6455 19:54:10.345366 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6456 19:54:10.348384 iDelay=230, Bit 4, Center -3 (-234 ~ 229) 464
6457 19:54:10.355300 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6458 19:54:10.358509 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6459 19:54:10.361936 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6460 19:54:10.365192 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6461 19:54:10.368503 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6462 19:54:10.375131 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6463 19:54:10.378635 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6464 19:54:10.381616 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6465 19:54:10.388162 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6466 19:54:10.391688 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6467 19:54:10.394971 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6468 19:54:10.395070 ==
6469 19:54:10.398544 Dram Type= 6, Freq= 0, CH_0, rank 1
6470 19:54:10.401753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6471 19:54:10.404867 ==
6472 19:54:10.404945 DQS Delay:
6473 19:54:10.405008 DQS0 = 27, DQS1 = 35
6474 19:54:10.408569 DQM Delay:
6475 19:54:10.408645 DQM0 = 14, DQM1 = 12
6476 19:54:10.411733 DQ Delay:
6477 19:54:10.411812 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6478 19:54:10.414919 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6479 19:54:10.418331 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6480 19:54:10.421904 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6481 19:54:10.422004
6482 19:54:10.422097
6483 19:54:10.425048 ==
6484 19:54:10.425122 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 19:54:10.431377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 19:54:10.431456 ==
6487 19:54:10.431520
6488 19:54:10.431579
6489 19:54:10.435165 TX Vref Scan disable
6490 19:54:10.435239 == TX Byte 0 ==
6491 19:54:10.438115 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6492 19:54:10.441428 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6493 19:54:10.445096 == TX Byte 1 ==
6494 19:54:10.448215 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6495 19:54:10.451321 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6496 19:54:10.455103 ==
6497 19:54:10.455192 Dram Type= 6, Freq= 0, CH_0, rank 1
6498 19:54:10.461750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6499 19:54:10.461898 ==
6500 19:54:10.461989
6501 19:54:10.462076
6502 19:54:10.464732 TX Vref Scan disable
6503 19:54:10.464824 == TX Byte 0 ==
6504 19:54:10.467885 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6505 19:54:10.474895 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6506 19:54:10.475011 == TX Byte 1 ==
6507 19:54:10.477793 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6508 19:54:10.481238 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6509 19:54:10.484455
6510 19:54:10.484544 [DATLAT]
6511 19:54:10.484607 Freq=400, CH0 RK1
6512 19:54:10.484675
6513 19:54:10.487653 DATLAT Default: 0xe
6514 19:54:10.487788 0, 0xFFFF, sum = 0
6515 19:54:10.491095 1, 0xFFFF, sum = 0
6516 19:54:10.491211 2, 0xFFFF, sum = 0
6517 19:54:10.494549 3, 0xFFFF, sum = 0
6518 19:54:10.494663 4, 0xFFFF, sum = 0
6519 19:54:10.497924 5, 0xFFFF, sum = 0
6520 19:54:10.501450 6, 0xFFFF, sum = 0
6521 19:54:10.501540 7, 0xFFFF, sum = 0
6522 19:54:10.504200 8, 0xFFFF, sum = 0
6523 19:54:10.504314 9, 0xFFFF, sum = 0
6524 19:54:10.507717 10, 0xFFFF, sum = 0
6525 19:54:10.507841 11, 0xFFFF, sum = 0
6526 19:54:10.510904 12, 0xFFFF, sum = 0
6527 19:54:10.511004 13, 0x0, sum = 1
6528 19:54:10.514550 14, 0x0, sum = 2
6529 19:54:10.514622 15, 0x0, sum = 3
6530 19:54:10.517761 16, 0x0, sum = 4
6531 19:54:10.517831 best_step = 14
6532 19:54:10.517894
6533 19:54:10.517955 ==
6534 19:54:10.521106 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 19:54:10.524149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 19:54:10.524234 ==
6537 19:54:10.527915 RX Vref Scan: 0
6538 19:54:10.527984
6539 19:54:10.531162 RX Vref 0 -> 0, step: 1
6540 19:54:10.531248
6541 19:54:10.531329 RX Delay -311 -> 252, step: 8
6542 19:54:10.539546 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6543 19:54:10.543327 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6544 19:54:10.546868 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6545 19:54:10.549787 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6546 19:54:10.556268 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6547 19:54:10.560084 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6548 19:54:10.563012 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6549 19:54:10.566156 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6550 19:54:10.572899 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6551 19:54:10.576675 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6552 19:54:10.579672 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6553 19:54:10.583237 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6554 19:54:10.589488 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6555 19:54:10.593111 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6556 19:54:10.596631 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6557 19:54:10.602919 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6558 19:54:10.603034 ==
6559 19:54:10.606328 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 19:54:10.609656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 19:54:10.609744 ==
6562 19:54:10.609814 DQS Delay:
6563 19:54:10.612599 DQS0 = 24, DQS1 = 32
6564 19:54:10.612683 DQM Delay:
6565 19:54:10.615984 DQM0 = 8, DQM1 = 10
6566 19:54:10.616057 DQ Delay:
6567 19:54:10.619364 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6568 19:54:10.622876 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6569 19:54:10.626311 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6570 19:54:10.629553 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6571 19:54:10.629637
6572 19:54:10.629697
6573 19:54:10.635985 [DQSOSCAuto] RK1, (LSB)MR18= 0xbf5f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6574 19:54:10.639763 CH0 RK1: MR19=C0C, MR18=BF5F
6575 19:54:10.646081 CH0_RK1: MR19=0xC0C, MR18=0xBF5F, DQSOSC=386, MR23=63, INC=396, DEC=264
6576 19:54:10.649314 [RxdqsGatingPostProcess] freq 400
6577 19:54:10.656180 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6578 19:54:10.656265 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 19:54:10.658961 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 19:54:10.662336 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 19:54:10.665737 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 19:54:10.669246 best DQS0 dly(2T, 0.5T) = (0, 10)
6583 19:54:10.672210 best DQS1 dly(2T, 0.5T) = (0, 10)
6584 19:54:10.675918 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6585 19:54:10.679017 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6586 19:54:10.682168 Pre-setting of DQS Precalculation
6587 19:54:10.685603 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6588 19:54:10.689354 ==
6589 19:54:10.692483 Dram Type= 6, Freq= 0, CH_1, rank 0
6590 19:54:10.695580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 19:54:10.695700 ==
6592 19:54:10.699251 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6593 19:54:10.705653 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6594 19:54:10.708756 [CA 0] Center 36 (8~64) winsize 57
6595 19:54:10.712307 [CA 1] Center 36 (8~64) winsize 57
6596 19:54:10.715600 [CA 2] Center 36 (8~64) winsize 57
6597 19:54:10.718937 [CA 3] Center 36 (8~64) winsize 57
6598 19:54:10.722573 [CA 4] Center 36 (8~64) winsize 57
6599 19:54:10.725427 [CA 5] Center 36 (8~64) winsize 57
6600 19:54:10.725546
6601 19:54:10.728807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6602 19:54:10.728932
6603 19:54:10.732384 [CATrainingPosCal] consider 1 rank data
6604 19:54:10.735398 u2DelayCellTimex100 = 270/100 ps
6605 19:54:10.739296 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 19:54:10.742401 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 19:54:10.745560 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 19:54:10.748722 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 19:54:10.754992 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 19:54:10.758810 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 19:54:10.758887
6612 19:54:10.762033 CA PerBit enable=1, Macro0, CA PI delay=36
6613 19:54:10.762138
6614 19:54:10.765071 [CBTSetCACLKResult] CA Dly = 36
6615 19:54:10.765171 CS Dly: 1 (0~32)
6616 19:54:10.765265 ==
6617 19:54:10.768668 Dram Type= 6, Freq= 0, CH_1, rank 1
6618 19:54:10.774975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 19:54:10.775058 ==
6620 19:54:10.778271 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6621 19:54:10.785189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6622 19:54:10.788754 [CA 0] Center 36 (8~64) winsize 57
6623 19:54:10.791805 [CA 1] Center 36 (8~64) winsize 57
6624 19:54:10.794929 [CA 2] Center 36 (8~64) winsize 57
6625 19:54:10.798769 [CA 3] Center 36 (8~64) winsize 57
6626 19:54:10.801943 [CA 4] Center 36 (8~64) winsize 57
6627 19:54:10.805049 [CA 5] Center 36 (8~64) winsize 57
6628 19:54:10.805145
6629 19:54:10.808183 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6630 19:54:10.808251
6631 19:54:10.811691 [CATrainingPosCal] consider 2 rank data
6632 19:54:10.815483 u2DelayCellTimex100 = 270/100 ps
6633 19:54:10.818660 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 19:54:10.821643 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 19:54:10.825171 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 19:54:10.828415 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 19:54:10.832155 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 19:54:10.835259 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 19:54:10.835335
6640 19:54:10.842295 CA PerBit enable=1, Macro0, CA PI delay=36
6641 19:54:10.842400
6642 19:54:10.842494 [CBTSetCACLKResult] CA Dly = 36
6643 19:54:10.845043 CS Dly: 1 (0~32)
6644 19:54:10.845132
6645 19:54:10.848705 ----->DramcWriteLeveling(PI) begin...
6646 19:54:10.848780 ==
6647 19:54:10.851871 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 19:54:10.854953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 19:54:10.855025 ==
6650 19:54:10.858186 Write leveling (Byte 0): 40 => 8
6651 19:54:10.861896 Write leveling (Byte 1): 40 => 8
6652 19:54:10.865165 DramcWriteLeveling(PI) end<-----
6653 19:54:10.865260
6654 19:54:10.865349 ==
6655 19:54:10.868840 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 19:54:10.872093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 19:54:10.872169 ==
6658 19:54:10.874970 [Gating] SW mode calibration
6659 19:54:10.881752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6660 19:54:10.888365 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6661 19:54:10.891672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 19:54:10.898812 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 19:54:10.902272 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 19:54:10.905436 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 19:54:10.908652 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 19:54:10.915414 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 19:54:10.918925 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 19:54:10.922188 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 19:54:10.929162 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 19:54:10.929265 Total UI for P1: 0, mck2ui 16
6671 19:54:10.935152 best dqsien dly found for B0: ( 0, 14, 24)
6672 19:54:10.935230 Total UI for P1: 0, mck2ui 16
6673 19:54:10.942079 best dqsien dly found for B1: ( 0, 14, 24)
6674 19:54:10.945381 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6675 19:54:10.948697 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6676 19:54:10.948806
6677 19:54:10.952196 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 19:54:10.955713 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 19:54:10.958403 [Gating] SW calibration Done
6680 19:54:10.958505 ==
6681 19:54:10.962230 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 19:54:10.965354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 19:54:10.965456 ==
6684 19:54:10.968452 RX Vref Scan: 0
6685 19:54:10.968549
6686 19:54:10.968642 RX Vref 0 -> 0, step: 1
6687 19:54:10.971682
6688 19:54:10.971757 RX Delay -410 -> 252, step: 16
6689 19:54:10.978556 iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464
6690 19:54:10.981566 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6691 19:54:10.985153 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6692 19:54:10.988143 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6693 19:54:10.994909 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6694 19:54:10.998643 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6695 19:54:11.001558 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6696 19:54:11.005203 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6697 19:54:11.011453 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6698 19:54:11.015180 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6699 19:54:11.018238 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6700 19:54:11.021879 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6701 19:54:11.028405 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6702 19:54:11.031572 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6703 19:54:11.034657 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6704 19:54:11.037852 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6705 19:54:11.041647 ==
6706 19:54:11.041750 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 19:54:11.048157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 19:54:11.048240 ==
6709 19:54:11.048314 DQS Delay:
6710 19:54:11.051550 DQS0 = 35, DQS1 = 35
6711 19:54:11.051657 DQM Delay:
6712 19:54:11.054434 DQM0 = 17, DQM1 = 17
6713 19:54:11.054535 DQ Delay:
6714 19:54:11.057727 DQ0 =32, DQ1 =8, DQ2 =0, DQ3 =8
6715 19:54:11.061752 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =8
6716 19:54:11.064579 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6717 19:54:11.067997 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6718 19:54:11.068074
6719 19:54:11.068143
6720 19:54:11.068205 ==
6721 19:54:11.071380 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 19:54:11.074460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 19:54:11.074563 ==
6724 19:54:11.074654
6725 19:54:11.074745
6726 19:54:11.077647 TX Vref Scan disable
6727 19:54:11.077746 == TX Byte 0 ==
6728 19:54:11.084633 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6729 19:54:11.087680 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6730 19:54:11.087784 == TX Byte 1 ==
6731 19:54:11.091048 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6732 19:54:11.097901 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6733 19:54:11.097979 ==
6734 19:54:11.101534 Dram Type= 6, Freq= 0, CH_1, rank 0
6735 19:54:11.104712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6736 19:54:11.104785 ==
6737 19:54:11.104849
6738 19:54:11.104913
6739 19:54:11.107817 TX Vref Scan disable
6740 19:54:11.107889 == TX Byte 0 ==
6741 19:54:11.114514 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6742 19:54:11.117964 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6743 19:54:11.118048 == TX Byte 1 ==
6744 19:54:11.124874 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6745 19:54:11.127995 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6746 19:54:11.128071
6747 19:54:11.128134 [DATLAT]
6748 19:54:11.130957 Freq=400, CH1 RK0
6749 19:54:11.131052
6750 19:54:11.131143 DATLAT Default: 0xf
6751 19:54:11.134559 0, 0xFFFF, sum = 0
6752 19:54:11.134645 1, 0xFFFF, sum = 0
6753 19:54:11.137646 2, 0xFFFF, sum = 0
6754 19:54:11.137717 3, 0xFFFF, sum = 0
6755 19:54:11.140754 4, 0xFFFF, sum = 0
6756 19:54:11.140854 5, 0xFFFF, sum = 0
6757 19:54:11.144580 6, 0xFFFF, sum = 0
6758 19:54:11.144673 7, 0xFFFF, sum = 0
6759 19:54:11.147782 8, 0xFFFF, sum = 0
6760 19:54:11.147862 9, 0xFFFF, sum = 0
6761 19:54:11.150964 10, 0xFFFF, sum = 0
6762 19:54:11.151058 11, 0xFFFF, sum = 0
6763 19:54:11.154677 12, 0xFFFF, sum = 0
6764 19:54:11.154791 13, 0x0, sum = 1
6765 19:54:11.157686 14, 0x0, sum = 2
6766 19:54:11.157761 15, 0x0, sum = 3
6767 19:54:11.161405 16, 0x0, sum = 4
6768 19:54:11.161509 best_step = 14
6769 19:54:11.161637
6770 19:54:11.161724 ==
6771 19:54:11.164349 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 19:54:11.171135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 19:54:11.171216 ==
6774 19:54:11.171301 RX Vref Scan: 1
6775 19:54:11.171373
6776 19:54:11.174117 RX Vref 0 -> 0, step: 1
6777 19:54:11.174187
6778 19:54:11.177980 RX Delay -311 -> 252, step: 8
6779 19:54:11.178099
6780 19:54:11.180985 Set Vref, RX VrefLevel [Byte0]: 55
6781 19:54:11.184127 [Byte1]: 52
6782 19:54:11.184214
6783 19:54:11.187856 Final RX Vref Byte 0 = 55 to rank0
6784 19:54:11.191016 Final RX Vref Byte 1 = 52 to rank0
6785 19:54:11.194123 Final RX Vref Byte 0 = 55 to rank1
6786 19:54:11.197698 Final RX Vref Byte 1 = 52 to rank1==
6787 19:54:11.200965 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 19:54:11.204003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 19:54:11.207870 ==
6790 19:54:11.207945 DQS Delay:
6791 19:54:11.208007 DQS0 = 32, DQS1 = 32
6792 19:54:11.211030 DQM Delay:
6793 19:54:11.211100 DQM0 = 13, DQM1 = 11
6794 19:54:11.214018 DQ Delay:
6795 19:54:11.214088 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6796 19:54:11.217725 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6797 19:54:11.220744 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6798 19:54:11.223822 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6799 19:54:11.223896
6800 19:54:11.223994
6801 19:54:11.234147 [DQSOSCAuto] RK0, (LSB)MR18= 0x95cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6802 19:54:11.237721 CH1 RK0: MR19=C0C, MR18=95CC
6803 19:54:11.243841 CH1_RK0: MR19=0xC0C, MR18=0x95CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6804 19:54:11.243971 ==
6805 19:54:11.247739 Dram Type= 6, Freq= 0, CH_1, rank 1
6806 19:54:11.250887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 19:54:11.250962 ==
6808 19:54:11.254051 [Gating] SW mode calibration
6809 19:54:11.260434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6810 19:54:11.264167 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6811 19:54:11.270873 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 19:54:11.273666 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 19:54:11.277312 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 19:54:11.283763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 19:54:11.287174 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 19:54:11.290411 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 19:54:11.297220 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 19:54:11.300418 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 19:54:11.304063 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 19:54:11.306958 Total UI for P1: 0, mck2ui 16
6821 19:54:11.310371 best dqsien dly found for B0: ( 0, 14, 24)
6822 19:54:11.313755 Total UI for P1: 0, mck2ui 16
6823 19:54:11.316779 best dqsien dly found for B1: ( 0, 14, 24)
6824 19:54:11.320481 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6825 19:54:11.323551 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6826 19:54:11.327137
6827 19:54:11.330348 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 19:54:11.333422 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 19:54:11.337013 [Gating] SW calibration Done
6830 19:54:11.337087 ==
6831 19:54:11.340246 Dram Type= 6, Freq= 0, CH_1, rank 1
6832 19:54:11.343812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 19:54:11.343912 ==
6834 19:54:11.344006 RX Vref Scan: 0
6835 19:54:11.344095
6836 19:54:11.346814 RX Vref 0 -> 0, step: 1
6837 19:54:11.346896
6838 19:54:11.350582 RX Delay -410 -> 252, step: 16
6839 19:54:11.353738 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6840 19:54:11.360160 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6841 19:54:11.363404 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6842 19:54:11.366932 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6843 19:54:11.370015 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6844 19:54:11.376438 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6845 19:54:11.379940 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6846 19:54:11.383320 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6847 19:54:11.386450 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6848 19:54:11.390199 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6849 19:54:11.396874 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6850 19:54:11.400259 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6851 19:54:11.403162 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6852 19:54:11.410254 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6853 19:54:11.413315 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6854 19:54:11.416806 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6855 19:54:11.416894 ==
6856 19:54:11.419759 Dram Type= 6, Freq= 0, CH_1, rank 1
6857 19:54:11.423249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6858 19:54:11.426553 ==
6859 19:54:11.426626 DQS Delay:
6860 19:54:11.426689 DQS0 = 35, DQS1 = 35
6861 19:54:11.429909 DQM Delay:
6862 19:54:11.429980 DQM0 = 18, DQM1 = 14
6863 19:54:11.433228 DQ Delay:
6864 19:54:11.433309 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6865 19:54:11.436412 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6866 19:54:11.440053 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6867 19:54:11.443057 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6868 19:54:11.443154
6869 19:54:11.443248
6870 19:54:11.446319 ==
6871 19:54:11.450023 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 19:54:11.452957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 19:54:11.453070 ==
6874 19:54:11.453155
6875 19:54:11.453235
6876 19:54:11.456681 TX Vref Scan disable
6877 19:54:11.456758 == TX Byte 0 ==
6878 19:54:11.459827 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6879 19:54:11.466188 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6880 19:54:11.466273 == TX Byte 1 ==
6881 19:54:11.469832 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6882 19:54:11.476022 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6883 19:54:11.476141 ==
6884 19:54:11.479837 Dram Type= 6, Freq= 0, CH_1, rank 1
6885 19:54:11.483085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6886 19:54:11.483196 ==
6887 19:54:11.483300
6888 19:54:11.483400
6889 19:54:11.486060 TX Vref Scan disable
6890 19:54:11.486161 == TX Byte 0 ==
6891 19:54:11.489618 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6892 19:54:11.496164 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6893 19:54:11.496251 == TX Byte 1 ==
6894 19:54:11.499892 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6895 19:54:11.506053 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6896 19:54:11.506139
6897 19:54:11.506227 [DATLAT]
6898 19:54:11.506311 Freq=400, CH1 RK1
6899 19:54:11.506393
6900 19:54:11.509569 DATLAT Default: 0xe
6901 19:54:11.509657 0, 0xFFFF, sum = 0
6902 19:54:11.512649 1, 0xFFFF, sum = 0
6903 19:54:11.516524 2, 0xFFFF, sum = 0
6904 19:54:11.516613 3, 0xFFFF, sum = 0
6905 19:54:11.519606 4, 0xFFFF, sum = 0
6906 19:54:11.519727 5, 0xFFFF, sum = 0
6907 19:54:11.522668 6, 0xFFFF, sum = 0
6908 19:54:11.522756 7, 0xFFFF, sum = 0
6909 19:54:11.526514 8, 0xFFFF, sum = 0
6910 19:54:11.526601 9, 0xFFFF, sum = 0
6911 19:54:11.529462 10, 0xFFFF, sum = 0
6912 19:54:11.529549 11, 0xFFFF, sum = 0
6913 19:54:11.532656 12, 0xFFFF, sum = 0
6914 19:54:11.532769 13, 0x0, sum = 1
6915 19:54:11.536169 14, 0x0, sum = 2
6916 19:54:11.536283 15, 0x0, sum = 3
6917 19:54:11.539632 16, 0x0, sum = 4
6918 19:54:11.539727 best_step = 14
6919 19:54:11.539814
6920 19:54:11.539896 ==
6921 19:54:11.542798 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 19:54:11.546186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 19:54:11.546298 ==
6924 19:54:11.549447 RX Vref Scan: 0
6925 19:54:11.549555
6926 19:54:11.552960 RX Vref 0 -> 0, step: 1
6927 19:54:11.553060
6928 19:54:11.553156 RX Delay -311 -> 252, step: 8
6929 19:54:11.561518 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6930 19:54:11.564684 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6931 19:54:11.568450 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6932 19:54:11.571557 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6933 19:54:11.578442 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6934 19:54:11.581715 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6935 19:54:11.584966 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6936 19:54:11.588087 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6937 19:54:11.594906 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6938 19:54:11.598266 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6939 19:54:11.601518 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6940 19:54:11.605112 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6941 19:54:11.611549 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6942 19:54:11.615188 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6943 19:54:11.617956 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6944 19:54:11.625051 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6945 19:54:11.625135 ==
6946 19:54:11.627931 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 19:54:11.631648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 19:54:11.631726 ==
6949 19:54:11.631809 DQS Delay:
6950 19:54:11.634736 DQS0 = 28, DQS1 = 36
6951 19:54:11.634821 DQM Delay:
6952 19:54:11.637917 DQM0 = 11, DQM1 = 15
6953 19:54:11.638003 DQ Delay:
6954 19:54:11.641715 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6955 19:54:11.644864 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6956 19:54:11.647850 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6957 19:54:11.651306 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6958 19:54:11.651416
6959 19:54:11.651520
6960 19:54:11.658310 [DQSOSCAuto] RK1, (LSB)MR18= 0xcc5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
6961 19:54:11.661778 CH1 RK1: MR19=C0C, MR18=CC5C
6962 19:54:11.667861 CH1_RK1: MR19=0xC0C, MR18=0xCC5C, DQSOSC=384, MR23=63, INC=400, DEC=267
6963 19:54:11.671230 [RxdqsGatingPostProcess] freq 400
6964 19:54:11.678090 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6965 19:54:11.678168 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 19:54:11.681205 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 19:54:11.684861 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 19:54:11.688038 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 19:54:11.691229 best DQS0 dly(2T, 0.5T) = (0, 10)
6970 19:54:11.694453 best DQS1 dly(2T, 0.5T) = (0, 10)
6971 19:54:11.698204 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6972 19:54:11.701400 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6973 19:54:11.704340 Pre-setting of DQS Precalculation
6974 19:54:11.707741 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6975 19:54:11.718070 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6976 19:54:11.724596 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6977 19:54:11.724696
6978 19:54:11.724818
6979 19:54:11.727963 [Calibration Summary] 800 Mbps
6980 19:54:11.728039 CH 0, Rank 0
6981 19:54:11.731423 SW Impedance : PASS
6982 19:54:11.731540 DUTY Scan : NO K
6983 19:54:11.734666 ZQ Calibration : PASS
6984 19:54:11.738280 Jitter Meter : NO K
6985 19:54:11.738356 CBT Training : PASS
6986 19:54:11.740819 Write leveling : PASS
6987 19:54:11.744535 RX DQS gating : PASS
6988 19:54:11.744638 RX DQ/DQS(RDDQC) : PASS
6989 19:54:11.747792 TX DQ/DQS : PASS
6990 19:54:11.750947 RX DATLAT : PASS
6991 19:54:11.751025 RX DQ/DQS(Engine): PASS
6992 19:54:11.754667 TX OE : NO K
6993 19:54:11.754760 All Pass.
6994 19:54:11.754877
6995 19:54:11.757620 CH 0, Rank 1
6996 19:54:11.757719 SW Impedance : PASS
6997 19:54:11.761185 DUTY Scan : NO K
6998 19:54:11.764366 ZQ Calibration : PASS
6999 19:54:11.764467 Jitter Meter : NO K
7000 19:54:11.768061 CBT Training : PASS
7001 19:54:11.768173 Write leveling : NO K
7002 19:54:11.771166 RX DQS gating : PASS
7003 19:54:11.774305 RX DQ/DQS(RDDQC) : PASS
7004 19:54:11.774431 TX DQ/DQS : PASS
7005 19:54:11.777957 RX DATLAT : PASS
7006 19:54:11.780905 RX DQ/DQS(Engine): PASS
7007 19:54:11.781008 TX OE : NO K
7008 19:54:11.784256 All Pass.
7009 19:54:11.784357
7010 19:54:11.784458 CH 1, Rank 0
7011 19:54:11.787964 SW Impedance : PASS
7012 19:54:11.788075 DUTY Scan : NO K
7013 19:54:11.791301 ZQ Calibration : PASS
7014 19:54:11.794363 Jitter Meter : NO K
7015 19:54:11.794461 CBT Training : PASS
7016 19:54:11.798016 Write leveling : PASS
7017 19:54:11.801130 RX DQS gating : PASS
7018 19:54:11.801231 RX DQ/DQS(RDDQC) : PASS
7019 19:54:11.804331 TX DQ/DQS : PASS
7020 19:54:11.808058 RX DATLAT : PASS
7021 19:54:11.808164 RX DQ/DQS(Engine): PASS
7022 19:54:11.811253 TX OE : NO K
7023 19:54:11.811354 All Pass.
7024 19:54:11.811482
7025 19:54:11.811580 CH 1, Rank 1
7026 19:54:11.814270 SW Impedance : PASS
7027 19:54:11.817832 DUTY Scan : NO K
7028 19:54:11.817918 ZQ Calibration : PASS
7029 19:54:11.821001 Jitter Meter : NO K
7030 19:54:11.824408 CBT Training : PASS
7031 19:54:11.824512 Write leveling : NO K
7032 19:54:11.828203 RX DQS gating : PASS
7033 19:54:11.831476 RX DQ/DQS(RDDQC) : PASS
7034 19:54:11.831561 TX DQ/DQS : PASS
7035 19:54:11.834661 RX DATLAT : PASS
7036 19:54:11.837779 RX DQ/DQS(Engine): PASS
7037 19:54:11.837926 TX OE : NO K
7038 19:54:11.841445 All Pass.
7039 19:54:11.841521
7040 19:54:11.841582 DramC Write-DBI off
7041 19:54:11.844604 PER_BANK_REFRESH: Hybrid Mode
7042 19:54:11.844715 TX_TRACKING: ON
7043 19:54:11.854190 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7044 19:54:11.857919 [FAST_K] Save calibration result to emmc
7045 19:54:11.860831 dramc_set_vcore_voltage set vcore to 725000
7046 19:54:11.863907 Read voltage for 1600, 0
7047 19:54:11.863987 Vio18 = 0
7048 19:54:11.867582 Vcore = 725000
7049 19:54:11.867684 Vdram = 0
7050 19:54:11.867749 Vddq = 0
7051 19:54:11.870673 Vmddr = 0
7052 19:54:11.874320 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7053 19:54:11.880482 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7054 19:54:11.880562 MEM_TYPE=3, freq_sel=13
7055 19:54:11.884302 sv_algorithm_assistance_LP4_3733
7056 19:54:11.891140 ============ PULL DRAM RESETB DOWN ============
7057 19:54:11.894187 ========== PULL DRAM RESETB DOWN end =========
7058 19:54:11.897180 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7059 19:54:11.900536 ===================================
7060 19:54:11.904288 LPDDR4 DRAM CONFIGURATION
7061 19:54:11.907058 ===================================
7062 19:54:11.907130 EX_ROW_EN[0] = 0x0
7063 19:54:11.910554 EX_ROW_EN[1] = 0x0
7064 19:54:11.913744 LP4Y_EN = 0x0
7065 19:54:11.913851 WORK_FSP = 0x1
7066 19:54:11.917653 WL = 0x5
7067 19:54:11.917759 RL = 0x5
7068 19:54:11.920838 BL = 0x2
7069 19:54:11.920935 RPST = 0x0
7070 19:54:11.923827 RD_PRE = 0x0
7071 19:54:11.923918 WR_PRE = 0x1
7072 19:54:11.927399 WR_PST = 0x1
7073 19:54:11.927487 DBI_WR = 0x0
7074 19:54:11.930278 DBI_RD = 0x0
7075 19:54:11.930381 OTF = 0x1
7076 19:54:11.933574 ===================================
7077 19:54:11.937468 ===================================
7078 19:54:11.940529 ANA top config
7079 19:54:11.943689 ===================================
7080 19:54:11.943773 DLL_ASYNC_EN = 0
7081 19:54:11.947358 ALL_SLAVE_EN = 0
7082 19:54:11.950479 NEW_RANK_MODE = 1
7083 19:54:11.954057 DLL_IDLE_MODE = 1
7084 19:54:11.957206 LP45_APHY_COMB_EN = 1
7085 19:54:11.957290 TX_ODT_DIS = 0
7086 19:54:11.960634 NEW_8X_MODE = 1
7087 19:54:11.963631 ===================================
7088 19:54:11.967081 ===================================
7089 19:54:11.970552 data_rate = 3200
7090 19:54:11.973931 CKR = 1
7091 19:54:11.977046 DQ_P2S_RATIO = 8
7092 19:54:11.979978 ===================================
7093 19:54:11.980063 CA_P2S_RATIO = 8
7094 19:54:11.983575 DQ_CA_OPEN = 0
7095 19:54:11.986699 DQ_SEMI_OPEN = 0
7096 19:54:11.990484 CA_SEMI_OPEN = 0
7097 19:54:11.993710 CA_FULL_RATE = 0
7098 19:54:11.996885 DQ_CKDIV4_EN = 0
7099 19:54:11.996969 CA_CKDIV4_EN = 0
7100 19:54:11.999926 CA_PREDIV_EN = 0
7101 19:54:12.003682 PH8_DLY = 12
7102 19:54:12.006672 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7103 19:54:12.010275 DQ_AAMCK_DIV = 4
7104 19:54:12.013485 CA_AAMCK_DIV = 4
7105 19:54:12.013573 CA_ADMCK_DIV = 4
7106 19:54:12.016654 DQ_TRACK_CA_EN = 0
7107 19:54:12.020192 CA_PICK = 1600
7108 19:54:12.023181 CA_MCKIO = 1600
7109 19:54:12.027181 MCKIO_SEMI = 0
7110 19:54:12.030225 PLL_FREQ = 3068
7111 19:54:12.033284 DQ_UI_PI_RATIO = 32
7112 19:54:12.036852 CA_UI_PI_RATIO = 0
7113 19:54:12.039720 ===================================
7114 19:54:12.043195 ===================================
7115 19:54:12.043276 memory_type:LPDDR4
7116 19:54:12.046364 GP_NUM : 10
7117 19:54:12.050080 SRAM_EN : 1
7118 19:54:12.050156 MD32_EN : 0
7119 19:54:12.053163 ===================================
7120 19:54:12.056809 [ANA_INIT] >>>>>>>>>>>>>>
7121 19:54:12.059913 <<<<<< [CONFIGURE PHASE]: ANA_TX
7122 19:54:12.062976 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7123 19:54:12.066616 ===================================
7124 19:54:12.069738 data_rate = 3200,PCW = 0X7600
7125 19:54:12.073433 ===================================
7126 19:54:12.076486 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7127 19:54:12.079827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 19:54:12.086663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 19:54:12.089716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7130 19:54:12.093269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7131 19:54:12.096442 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7132 19:54:12.099768 [ANA_INIT] flow start
7133 19:54:12.103438 [ANA_INIT] PLL >>>>>>>>
7134 19:54:12.103531 [ANA_INIT] PLL <<<<<<<<
7135 19:54:12.106729 [ANA_INIT] MIDPI >>>>>>>>
7136 19:54:12.109930 [ANA_INIT] MIDPI <<<<<<<<
7137 19:54:12.110041 [ANA_INIT] DLL >>>>>>>>
7138 19:54:12.113105 [ANA_INIT] DLL <<<<<<<<
7139 19:54:12.116494 [ANA_INIT] flow end
7140 19:54:12.119499 ============ LP4 DIFF to SE enter ============
7141 19:54:12.123092 ============ LP4 DIFF to SE exit ============
7142 19:54:12.126428 [ANA_INIT] <<<<<<<<<<<<<
7143 19:54:12.129816 [Flow] Enable top DCM control >>>>>
7144 19:54:12.133188 [Flow] Enable top DCM control <<<<<
7145 19:54:12.136177 Enable DLL master slave shuffle
7146 19:54:12.139529 ==============================================================
7147 19:54:12.143258 Gating Mode config
7148 19:54:12.149906 ==============================================================
7149 19:54:12.149992 Config description:
7150 19:54:12.160117 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7151 19:54:12.166136 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7152 19:54:12.169940 SELPH_MODE 0: By rank 1: By Phase
7153 19:54:12.176636 ==============================================================
7154 19:54:12.179925 GAT_TRACK_EN = 1
7155 19:54:12.183027 RX_GATING_MODE = 2
7156 19:54:12.186123 RX_GATING_TRACK_MODE = 2
7157 19:54:12.189601 SELPH_MODE = 1
7158 19:54:12.193307 PICG_EARLY_EN = 1
7159 19:54:12.196270 VALID_LAT_VALUE = 1
7160 19:54:12.199797 ==============================================================
7161 19:54:12.202672 Enter into Gating configuration >>>>
7162 19:54:12.206431 Exit from Gating configuration <<<<
7163 19:54:12.209709 Enter into DVFS_PRE_config >>>>>
7164 19:54:12.219450 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7165 19:54:12.222766 Exit from DVFS_PRE_config <<<<<
7166 19:54:12.226152 Enter into PICG configuration >>>>
7167 19:54:12.229761 Exit from PICG configuration <<<<
7168 19:54:12.232880 [RX_INPUT] configuration >>>>>
7169 19:54:12.235835 [RX_INPUT] configuration <<<<<
7170 19:54:12.242906 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7171 19:54:12.245946 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7172 19:54:12.252898 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7173 19:54:12.259680 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7174 19:54:12.266551 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 19:54:12.273216 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 19:54:12.276151 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7177 19:54:12.279990 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7178 19:54:12.282710 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7179 19:54:12.286471 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7180 19:54:12.292885 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7181 19:54:12.296060 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7182 19:54:12.299907 ===================================
7183 19:54:12.302983 LPDDR4 DRAM CONFIGURATION
7184 19:54:12.306247 ===================================
7185 19:54:12.306330 EX_ROW_EN[0] = 0x0
7186 19:54:12.309659 EX_ROW_EN[1] = 0x0
7187 19:54:12.309737 LP4Y_EN = 0x0
7188 19:54:12.313120 WORK_FSP = 0x1
7189 19:54:12.313226 WL = 0x5
7190 19:54:12.316266 RL = 0x5
7191 19:54:12.316370 BL = 0x2
7192 19:54:12.319486 RPST = 0x0
7193 19:54:12.319588 RD_PRE = 0x0
7194 19:54:12.322830 WR_PRE = 0x1
7195 19:54:12.326561 WR_PST = 0x1
7196 19:54:12.326663 DBI_WR = 0x0
7197 19:54:12.329697 DBI_RD = 0x0
7198 19:54:12.329810 OTF = 0x1
7199 19:54:12.332965 ===================================
7200 19:54:12.336313 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7201 19:54:12.339517 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7202 19:54:12.346037 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7203 19:54:12.349515 ===================================
7204 19:54:12.353067 LPDDR4 DRAM CONFIGURATION
7205 19:54:12.355954 ===================================
7206 19:54:12.356059 EX_ROW_EN[0] = 0x10
7207 19:54:12.359471 EX_ROW_EN[1] = 0x0
7208 19:54:12.359577 LP4Y_EN = 0x0
7209 19:54:12.362891 WORK_FSP = 0x1
7210 19:54:12.362990 WL = 0x5
7211 19:54:12.366192 RL = 0x5
7212 19:54:12.366291 BL = 0x2
7213 19:54:12.369828 RPST = 0x0
7214 19:54:12.369943 RD_PRE = 0x0
7215 19:54:12.372809 WR_PRE = 0x1
7216 19:54:12.372888 WR_PST = 0x1
7217 19:54:12.375937 DBI_WR = 0x0
7218 19:54:12.376044 DBI_RD = 0x0
7219 19:54:12.379562 OTF = 0x1
7220 19:54:12.383036 ===================================
7221 19:54:12.389409 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7222 19:54:12.389518 ==
7223 19:54:12.392694 Dram Type= 6, Freq= 0, CH_0, rank 0
7224 19:54:12.396455 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7225 19:54:12.396565 ==
7226 19:54:12.399667 [Duty_Offset_Calibration]
7227 19:54:12.399770 B0:2 B1:1 CA:1
7228 19:54:12.399863
7229 19:54:12.402609 [DutyScan_Calibration_Flow] k_type=0
7230 19:54:12.413714
7231 19:54:12.413820 ==CLK 0==
7232 19:54:12.417252 Final CLK duty delay cell = 0
7233 19:54:12.420827 [0] MAX Duty = 5156%(X100), DQS PI = 22
7234 19:54:12.423693 [0] MIN Duty = 4907%(X100), DQS PI = 0
7235 19:54:12.423791 [0] AVG Duty = 5031%(X100)
7236 19:54:12.426841
7237 19:54:12.430070 CH0 CLK Duty spec in!! Max-Min= 249%
7238 19:54:12.433828 [DutyScan_Calibration_Flow] ====Done====
7239 19:54:12.433936
7240 19:54:12.436952 [DutyScan_Calibration_Flow] k_type=1
7241 19:54:12.452632
7242 19:54:12.452714 ==DQS 0 ==
7243 19:54:12.456037 Final DQS duty delay cell = -4
7244 19:54:12.459325 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7245 19:54:12.462686 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7246 19:54:12.466293 [-4] AVG Duty = 4891%(X100)
7247 19:54:12.466409
7248 19:54:12.466501 ==DQS 1 ==
7249 19:54:12.469361 Final DQS duty delay cell = 0
7250 19:54:12.472850 [0] MAX Duty = 5187%(X100), DQS PI = 10
7251 19:54:12.475837 [0] MIN Duty = 5031%(X100), DQS PI = 54
7252 19:54:12.479539 [0] AVG Duty = 5109%(X100)
7253 19:54:12.479656
7254 19:54:12.482487 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7255 19:54:12.482569
7256 19:54:12.485833 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7257 19:54:12.489318 [DutyScan_Calibration_Flow] ====Done====
7258 19:54:12.489427
7259 19:54:12.492808 [DutyScan_Calibration_Flow] k_type=3
7260 19:54:12.509314
7261 19:54:12.509425 ==DQM 0 ==
7262 19:54:12.513308 Final DQM duty delay cell = 0
7263 19:54:12.516507 [0] MAX Duty = 5218%(X100), DQS PI = 32
7264 19:54:12.519819 [0] MIN Duty = 4876%(X100), DQS PI = 60
7265 19:54:12.523024 [0] AVG Duty = 5047%(X100)
7266 19:54:12.523138
7267 19:54:12.523230 ==DQM 1 ==
7268 19:54:12.526107 Final DQM duty delay cell = -4
7269 19:54:12.529804 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7270 19:54:12.532611 [-4] MIN Duty = 4813%(X100), DQS PI = 12
7271 19:54:12.536314 [-4] AVG Duty = 4906%(X100)
7272 19:54:12.536395
7273 19:54:12.539677 CH0 DQM 0 Duty spec in!! Max-Min= 342%
7274 19:54:12.539759
7275 19:54:12.542868 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7276 19:54:12.546101 [DutyScan_Calibration_Flow] ====Done====
7277 19:54:12.546208
7278 19:54:12.549293 [DutyScan_Calibration_Flow] k_type=2
7279 19:54:12.567414
7280 19:54:12.567520 ==DQ 0 ==
7281 19:54:12.570720 Final DQ duty delay cell = 0
7282 19:54:12.573876 [0] MAX Duty = 5062%(X100), DQS PI = 26
7283 19:54:12.577260 [0] MIN Duty = 4907%(X100), DQS PI = 0
7284 19:54:12.577343 [0] AVG Duty = 4984%(X100)
7285 19:54:12.577412
7286 19:54:12.580323 ==DQ 1 ==
7287 19:54:12.583560 Final DQ duty delay cell = 0
7288 19:54:12.587301 [0] MAX Duty = 5156%(X100), DQS PI = 22
7289 19:54:12.590531 [0] MIN Duty = 4907%(X100), DQS PI = 34
7290 19:54:12.590640 [0] AVG Duty = 5031%(X100)
7291 19:54:12.590732
7292 19:54:12.593870 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7293 19:54:12.596814
7294 19:54:12.600312 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7295 19:54:12.603593 [DutyScan_Calibration_Flow] ====Done====
7296 19:54:12.603695 ==
7297 19:54:12.606663 Dram Type= 6, Freq= 0, CH_1, rank 0
7298 19:54:12.610067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 19:54:12.610176 ==
7300 19:54:12.613301 [Duty_Offset_Calibration]
7301 19:54:12.613390 B0:1 B1:0 CA:0
7302 19:54:12.613454
7303 19:54:12.616460 [DutyScan_Calibration_Flow] k_type=0
7304 19:54:12.626913
7305 19:54:12.627026 ==CLK 0==
7306 19:54:12.630040 Final CLK duty delay cell = -4
7307 19:54:12.633564 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7308 19:54:12.636390 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7309 19:54:12.639899 [-4] AVG Duty = 4922%(X100)
7310 19:54:12.639977
7311 19:54:12.643416 CH1 CLK Duty spec in!! Max-Min= 156%
7312 19:54:12.646462 [DutyScan_Calibration_Flow] ====Done====
7313 19:54:12.646537
7314 19:54:12.649694 [DutyScan_Calibration_Flow] k_type=1
7315 19:54:12.665463
7316 19:54:12.665575 ==DQS 0 ==
7317 19:54:12.668716 Final DQS duty delay cell = 0
7318 19:54:12.672558 [0] MAX Duty = 5094%(X100), DQS PI = 14
7319 19:54:12.675702 [0] MIN Duty = 4875%(X100), DQS PI = 0
7320 19:54:12.678615 [0] AVG Duty = 4984%(X100)
7321 19:54:12.678722
7322 19:54:12.678813 ==DQS 1 ==
7323 19:54:12.682063 Final DQS duty delay cell = -4
7324 19:54:12.685437 [-4] MAX Duty = 4969%(X100), DQS PI = 16
7325 19:54:12.688763 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7326 19:54:12.692010 [-4] AVG Duty = 4859%(X100)
7327 19:54:12.692089
7328 19:54:12.695206 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7329 19:54:12.695301
7330 19:54:12.698917 CH1 DQS 1 Duty spec in!! Max-Min= 219%
7331 19:54:12.702373 [DutyScan_Calibration_Flow] ====Done====
7332 19:54:12.702458
7333 19:54:12.705488 [DutyScan_Calibration_Flow] k_type=3
7334 19:54:12.723188
7335 19:54:12.723270 ==DQM 0 ==
7336 19:54:12.726320 Final DQM duty delay cell = 0
7337 19:54:12.729228 [0] MAX Duty = 5218%(X100), DQS PI = 18
7338 19:54:12.732821 [0] MIN Duty = 4969%(X100), DQS PI = 48
7339 19:54:12.736058 [0] AVG Duty = 5093%(X100)
7340 19:54:12.736140
7341 19:54:12.736206 ==DQM 1 ==
7342 19:54:12.739694 Final DQM duty delay cell = 0
7343 19:54:12.742687 [0] MAX Duty = 5093%(X100), DQS PI = 16
7344 19:54:12.745856 [0] MIN Duty = 4938%(X100), DQS PI = 6
7345 19:54:12.749331 [0] AVG Duty = 5015%(X100)
7346 19:54:12.749414
7347 19:54:12.752797 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7348 19:54:12.752889
7349 19:54:12.755831 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7350 19:54:12.759654 [DutyScan_Calibration_Flow] ====Done====
7351 19:54:12.759758
7352 19:54:12.762824 [DutyScan_Calibration_Flow] k_type=2
7353 19:54:12.779126
7354 19:54:12.779212 ==DQ 0 ==
7355 19:54:12.782423 Final DQ duty delay cell = -4
7356 19:54:12.785569 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7357 19:54:12.788665 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7358 19:54:12.792136 [-4] AVG Duty = 4953%(X100)
7359 19:54:12.792245
7360 19:54:12.792348 ==DQ 1 ==
7361 19:54:12.795567 Final DQ duty delay cell = 0
7362 19:54:12.798776 [0] MAX Duty = 5124%(X100), DQS PI = 18
7363 19:54:12.802475 [0] MIN Duty = 4938%(X100), DQS PI = 8
7364 19:54:12.802578 [0] AVG Duty = 5031%(X100)
7365 19:54:12.805333
7366 19:54:12.808776 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7367 19:54:12.808883
7368 19:54:12.812472 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7369 19:54:12.815755 [DutyScan_Calibration_Flow] ====Done====
7370 19:54:12.819049 nWR fixed to 30
7371 19:54:12.819131 [ModeRegInit_LP4] CH0 RK0
7372 19:54:12.822305 [ModeRegInit_LP4] CH0 RK1
7373 19:54:12.825620 [ModeRegInit_LP4] CH1 RK0
7374 19:54:12.828757 [ModeRegInit_LP4] CH1 RK1
7375 19:54:12.828864 match AC timing 5
7376 19:54:12.835621 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7377 19:54:12.838560 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7378 19:54:12.841913 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7379 19:54:12.848461 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7380 19:54:12.851836 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7381 19:54:12.851917 [MiockJmeterHQA]
7382 19:54:12.851991
7383 19:54:12.855421 [DramcMiockJmeter] u1RxGatingPI = 0
7384 19:54:12.858935 0 : 4252, 4027
7385 19:54:12.859049 4 : 4252, 4027
7386 19:54:12.861759 8 : 4252, 4027
7387 19:54:12.861864 12 : 4255, 4029
7388 19:54:12.861968 16 : 4252, 4027
7389 19:54:12.865567 20 : 4363, 4137
7390 19:54:12.865677 24 : 4252, 4027
7391 19:54:12.868819 28 : 4361, 4137
7392 19:54:12.868930 32 : 4253, 4027
7393 19:54:12.871964 36 : 4250, 4027
7394 19:54:12.872076 40 : 4250, 4027
7395 19:54:12.875262 44 : 4252, 4029
7396 19:54:12.875366 48 : 4250, 4026
7397 19:54:12.875459 52 : 4360, 4138
7398 19:54:12.878557 56 : 4360, 4137
7399 19:54:12.878670 60 : 4250, 4027
7400 19:54:12.881790 64 : 4252, 4027
7401 19:54:12.881905 68 : 4250, 4026
7402 19:54:12.885052 72 : 4250, 4027
7403 19:54:12.885164 76 : 4252, 4029
7404 19:54:12.885261 80 : 4361, 4137
7405 19:54:12.888923 84 : 4249, 4027
7406 19:54:12.889038 88 : 4250, 151
7407 19:54:12.892212 92 : 4360, 0
7408 19:54:12.892300 96 : 4250, 0
7409 19:54:12.892388 100 : 4250, 0
7410 19:54:12.895383 104 : 4363, 0
7411 19:54:12.895469 108 : 4249, 0
7412 19:54:12.898639 112 : 4250, 0
7413 19:54:12.898727 116 : 4250, 0
7414 19:54:12.898815 120 : 4250, 0
7415 19:54:12.901639 124 : 4250, 0
7416 19:54:12.901725 128 : 4250, 0
7417 19:54:12.905310 132 : 4252, 0
7418 19:54:12.905397 136 : 4250, 0
7419 19:54:12.905485 140 : 4250, 0
7420 19:54:12.908948 144 : 4252, 0
7421 19:54:12.909063 148 : 4360, 0
7422 19:54:12.909162 152 : 4361, 0
7423 19:54:12.911955 156 : 4363, 0
7424 19:54:12.912070 160 : 4250, 0
7425 19:54:12.915205 164 : 4250, 0
7426 19:54:12.915322 168 : 4250, 0
7427 19:54:12.915423 172 : 4249, 0
7428 19:54:12.918463 176 : 4250, 0
7429 19:54:12.918542 180 : 4250, 0
7430 19:54:12.921863 184 : 4252, 0
7431 19:54:12.921935 188 : 4250, 0
7432 19:54:12.922005 192 : 4250, 0
7433 19:54:12.924921 196 : 4252, 0
7434 19:54:12.925012 200 : 4360, 0
7435 19:54:12.928792 204 : 4361, 1525
7436 19:54:12.928868 208 : 4250, 4022
7437 19:54:12.932070 212 : 4250, 4027
7438 19:54:12.932153 216 : 4360, 4137
7439 19:54:12.932258 220 : 4250, 4026
7440 19:54:12.935410 224 : 4250, 4027
7441 19:54:12.935516 228 : 4249, 4027
7442 19:54:12.938722 232 : 4252, 4029
7443 19:54:12.938820 236 : 4250, 4026
7444 19:54:12.941816 240 : 4250, 4027
7445 19:54:12.941918 244 : 4360, 4138
7446 19:54:12.945160 248 : 4249, 4027
7447 19:54:12.945235 252 : 4250, 4026
7448 19:54:12.948276 256 : 4360, 4138
7449 19:54:12.948354 260 : 4250, 4027
7450 19:54:12.951414 264 : 4249, 4027
7451 19:54:12.951515 268 : 4363, 4140
7452 19:54:12.954662 272 : 4250, 4027
7453 19:54:12.954767 276 : 4250, 4027
7454 19:54:12.958069 280 : 4250, 4027
7455 19:54:12.958179 284 : 4249, 4027
7456 19:54:12.958271 288 : 4250, 4026
7457 19:54:12.961413 292 : 4250, 4027
7458 19:54:12.961520 296 : 4360, 4138
7459 19:54:12.965012 300 : 4250, 4027
7460 19:54:12.965114 304 : 4250, 4027
7461 19:54:12.968065 308 : 4361, 4044
7462 19:54:12.968173 312 : 4250, 2067
7463 19:54:12.968271
7464 19:54:12.971217 MIOCK jitter meter ch=0
7465 19:54:12.971317
7466 19:54:12.975019 1T = (312-88) = 224 dly cells
7467 19:54:12.981633 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7468 19:54:12.981751 ==
7469 19:54:12.984818 Dram Type= 6, Freq= 0, CH_0, rank 0
7470 19:54:12.988279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7471 19:54:12.988356 ==
7472 19:54:12.994624 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7473 19:54:12.998527 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7474 19:54:13.001684 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7475 19:54:13.008515 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7476 19:54:13.016540 [CA 0] Center 43 (13~74) winsize 62
7477 19:54:13.019656 [CA 1] Center 43 (13~74) winsize 62
7478 19:54:13.023422 [CA 2] Center 38 (9~68) winsize 60
7479 19:54:13.026690 [CA 3] Center 38 (8~68) winsize 61
7480 19:54:13.030070 [CA 4] Center 36 (7~66) winsize 60
7481 19:54:13.033411 [CA 5] Center 36 (7~65) winsize 59
7482 19:54:13.033498
7483 19:54:13.036585 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7484 19:54:13.036671
7485 19:54:13.040028 [CATrainingPosCal] consider 1 rank data
7486 19:54:13.043267 u2DelayCellTimex100 = 290/100 ps
7487 19:54:13.046472 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7488 19:54:13.052969 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7489 19:54:13.056849 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7490 19:54:13.060124 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7491 19:54:13.063336 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7492 19:54:13.066512 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7493 19:54:13.066611
7494 19:54:13.069576 CA PerBit enable=1, Macro0, CA PI delay=36
7495 19:54:13.069674
7496 19:54:13.073158 [CBTSetCACLKResult] CA Dly = 36
7497 19:54:13.076494 CS Dly: 9 (0~40)
7498 19:54:13.079475 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7499 19:54:13.083148 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7500 19:54:13.083232 ==
7501 19:54:13.086006 Dram Type= 6, Freq= 0, CH_0, rank 1
7502 19:54:13.089513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 19:54:13.089596 ==
7504 19:54:13.096264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 19:54:13.099297 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 19:54:13.106067 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 19:54:13.109253 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 19:54:13.119982 [CA 0] Center 42 (12~73) winsize 62
7509 19:54:13.122976 [CA 1] Center 42 (12~73) winsize 62
7510 19:54:13.126148 [CA 2] Center 38 (8~68) winsize 61
7511 19:54:13.129762 [CA 3] Center 38 (8~68) winsize 61
7512 19:54:13.132928 [CA 4] Center 36 (6~66) winsize 61
7513 19:54:13.136065 [CA 5] Center 35 (5~65) winsize 61
7514 19:54:13.136177
7515 19:54:13.139702 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7516 19:54:13.139787
7517 19:54:13.143268 [CATrainingPosCal] consider 2 rank data
7518 19:54:13.146101 u2DelayCellTimex100 = 290/100 ps
7519 19:54:13.149404 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7520 19:54:13.156131 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7521 19:54:13.159943 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7522 19:54:13.163100 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7523 19:54:13.166301 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7524 19:54:13.169419 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7525 19:54:13.169500
7526 19:54:13.172922 CA PerBit enable=1, Macro0, CA PI delay=36
7527 19:54:13.172994
7528 19:54:13.176184 [CBTSetCACLKResult] CA Dly = 36
7529 19:54:13.179849 CS Dly: 10 (0~42)
7530 19:54:13.182824 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 19:54:13.186085 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 19:54:13.186193
7533 19:54:13.189804 ----->DramcWriteLeveling(PI) begin...
7534 19:54:13.189881 ==
7535 19:54:13.193224 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 19:54:13.196339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 19:54:13.199611 ==
7538 19:54:13.199697 Write leveling (Byte 0): 34 => 34
7539 19:54:13.203199 Write leveling (Byte 1): 27 => 27
7540 19:54:13.206091 DramcWriteLeveling(PI) end<-----
7541 19:54:13.206178
7542 19:54:13.206245 ==
7543 19:54:13.209519 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 19:54:13.216347 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 19:54:13.216424 ==
7546 19:54:13.216488 [Gating] SW mode calibration
7547 19:54:13.226206 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7548 19:54:13.229496 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7549 19:54:13.236192 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7550 19:54:13.239266 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 19:54:13.243073 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7552 19:54:13.246314 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7553 19:54:13.252612 1 4 16 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
7554 19:54:13.256234 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7555 19:54:13.259123 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 19:54:13.266128 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 19:54:13.269301 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7558 19:54:13.272652 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7559 19:54:13.279558 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7560 19:54:13.282797 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7561 19:54:13.286014 1 5 16 | B1->B0 | 3333 2423 | 1 1 | (1 0) (0 0)
7562 19:54:13.292692 1 5 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
7563 19:54:13.296292 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7564 19:54:13.299555 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7565 19:54:13.306332 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 19:54:13.309393 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7567 19:54:13.312565 1 6 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
7568 19:54:13.319487 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7569 19:54:13.322926 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7570 19:54:13.325841 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 19:54:13.332636 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 19:54:13.335942 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 19:54:13.339329 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 19:54:13.345710 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 19:54:13.348883 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 19:54:13.352484 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 19:54:13.359303 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7578 19:54:13.362457 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7579 19:54:13.365572 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 19:54:13.372242 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 19:54:13.375390 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 19:54:13.378712 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 19:54:13.382463 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 19:54:13.388819 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 19:54:13.392627 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 19:54:13.395824 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 19:54:13.402123 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 19:54:13.405667 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 19:54:13.409150 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 19:54:13.415695 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 19:54:13.419088 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7592 19:54:13.422326 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 19:54:13.429103 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7594 19:54:13.429178 Total UI for P1: 0, mck2ui 16
7595 19:54:13.435720 best dqsien dly found for B0: ( 1, 9, 10)
7596 19:54:13.438910 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7597 19:54:13.442013 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 19:54:13.445189 Total UI for P1: 0, mck2ui 16
7599 19:54:13.448914 best dqsien dly found for B1: ( 1, 9, 18)
7600 19:54:13.451872 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7601 19:54:13.455336 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7602 19:54:13.455412
7603 19:54:13.462092 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7604 19:54:13.465353 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7605 19:54:13.468525 [Gating] SW calibration Done
7606 19:54:13.468601 ==
7607 19:54:13.471871 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 19:54:13.475085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 19:54:13.475154 ==
7610 19:54:13.475214 RX Vref Scan: 0
7611 19:54:13.475300
7612 19:54:13.478725 RX Vref 0 -> 0, step: 1
7613 19:54:13.478821
7614 19:54:13.481729 RX Delay 0 -> 252, step: 8
7615 19:54:13.485125 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7616 19:54:13.488335 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7617 19:54:13.495836 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7618 19:54:13.498741 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7619 19:54:13.501835 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7620 19:54:13.505062 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7621 19:54:13.508344 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7622 19:54:13.511594 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7623 19:54:13.518415 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7624 19:54:13.521363 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7625 19:54:13.524852 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7626 19:54:13.528533 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7627 19:54:13.531794 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7628 19:54:13.538085 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7629 19:54:13.541928 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7630 19:54:13.545071 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7631 19:54:13.545174 ==
7632 19:54:13.548338 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 19:54:13.551623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 19:54:13.555215 ==
7635 19:54:13.555327 DQS Delay:
7636 19:54:13.555421 DQS0 = 0, DQS1 = 0
7637 19:54:13.558267 DQM Delay:
7638 19:54:13.558369 DQM0 = 137, DQM1 = 130
7639 19:54:13.561592 DQ Delay:
7640 19:54:13.564696 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7641 19:54:13.568432 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7642 19:54:13.571430 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7643 19:54:13.574886 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135
7644 19:54:13.574990
7645 19:54:13.575095
7646 19:54:13.575187 ==
7647 19:54:13.577919 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 19:54:13.581313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 19:54:13.581432 ==
7650 19:54:13.581521
7651 19:54:13.584828
7652 19:54:13.584906 TX Vref Scan disable
7653 19:54:13.588079 == TX Byte 0 ==
7654 19:54:13.591360 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7655 19:54:13.594895 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7656 19:54:13.597834 == TX Byte 1 ==
7657 19:54:13.601205 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7658 19:54:13.604975 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7659 19:54:13.605087 ==
7660 19:54:13.607932 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 19:54:13.614445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 19:54:13.614538 ==
7663 19:54:13.627049
7664 19:54:13.630234 TX Vref early break, caculate TX vref
7665 19:54:13.633251 TX Vref=16, minBit 7, minWin=22, winSum=378
7666 19:54:13.636780 TX Vref=18, minBit 0, minWin=24, winSum=391
7667 19:54:13.640412 TX Vref=20, minBit 7, minWin=23, winSum=398
7668 19:54:13.643488 TX Vref=22, minBit 3, minWin=25, winSum=410
7669 19:54:13.647095 TX Vref=24, minBit 2, minWin=25, winSum=414
7670 19:54:13.653415 TX Vref=26, minBit 0, minWin=26, winSum=427
7671 19:54:13.657188 TX Vref=28, minBit 2, minWin=25, winSum=427
7672 19:54:13.660183 TX Vref=30, minBit 1, minWin=24, winSum=413
7673 19:54:13.663315 TX Vref=32, minBit 1, minWin=24, winSum=406
7674 19:54:13.667186 TX Vref=34, minBit 1, minWin=23, winSum=399
7675 19:54:13.673351 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
7676 19:54:13.673431
7677 19:54:13.676818 Final TX Range 0 Vref 26
7678 19:54:13.676928
7679 19:54:13.677026 ==
7680 19:54:13.679903 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 19:54:13.683560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 19:54:13.683648 ==
7683 19:54:13.683714
7684 19:54:13.683774
7685 19:54:13.686751 TX Vref Scan disable
7686 19:54:13.693843 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7687 19:54:13.693928 == TX Byte 0 ==
7688 19:54:13.696792 u2DelayCellOfst[0]=10 cells (3 PI)
7689 19:54:13.700533 u2DelayCellOfst[1]=13 cells (4 PI)
7690 19:54:13.703658 u2DelayCellOfst[2]=10 cells (3 PI)
7691 19:54:13.706719 u2DelayCellOfst[3]=10 cells (3 PI)
7692 19:54:13.710047 u2DelayCellOfst[4]=6 cells (2 PI)
7693 19:54:13.713426 u2DelayCellOfst[5]=0 cells (0 PI)
7694 19:54:13.713534 u2DelayCellOfst[6]=20 cells (6 PI)
7695 19:54:13.716625 u2DelayCellOfst[7]=16 cells (5 PI)
7696 19:54:13.723739 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7697 19:54:13.726868 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7698 19:54:13.726948 == TX Byte 1 ==
7699 19:54:13.730153 u2DelayCellOfst[8]=0 cells (0 PI)
7700 19:54:13.733365 u2DelayCellOfst[9]=0 cells (0 PI)
7701 19:54:13.736515 u2DelayCellOfst[10]=10 cells (3 PI)
7702 19:54:13.739760 u2DelayCellOfst[11]=3 cells (1 PI)
7703 19:54:13.743451 u2DelayCellOfst[12]=10 cells (3 PI)
7704 19:54:13.746626 u2DelayCellOfst[13]=13 cells (4 PI)
7705 19:54:13.750009 u2DelayCellOfst[14]=13 cells (4 PI)
7706 19:54:13.753541 u2DelayCellOfst[15]=10 cells (3 PI)
7707 19:54:13.756787 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7708 19:54:13.763323 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7709 19:54:13.763403 DramC Write-DBI on
7710 19:54:13.763469 ==
7711 19:54:13.766672 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 19:54:13.769850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 19:54:13.769931 ==
7714 19:54:13.773021
7715 19:54:13.773112
7716 19:54:13.773183 TX Vref Scan disable
7717 19:54:13.776931 == TX Byte 0 ==
7718 19:54:13.780097 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7719 19:54:13.783039 == TX Byte 1 ==
7720 19:54:13.786276 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7721 19:54:13.786357 DramC Write-DBI off
7722 19:54:13.790250
7723 19:54:13.790331 [DATLAT]
7724 19:54:13.790394 Freq=1600, CH0 RK0
7725 19:54:13.790454
7726 19:54:13.793480 DATLAT Default: 0xf
7727 19:54:13.793555 0, 0xFFFF, sum = 0
7728 19:54:13.796652 1, 0xFFFF, sum = 0
7729 19:54:13.796727 2, 0xFFFF, sum = 0
7730 19:54:13.799814 3, 0xFFFF, sum = 0
7731 19:54:13.799923 4, 0xFFFF, sum = 0
7732 19:54:13.803241 5, 0xFFFF, sum = 0
7733 19:54:13.803311 6, 0xFFFF, sum = 0
7734 19:54:13.806957 7, 0xFFFF, sum = 0
7735 19:54:13.809774 8, 0xFFFF, sum = 0
7736 19:54:13.809854 9, 0xFFFF, sum = 0
7737 19:54:13.813077 10, 0xFFFF, sum = 0
7738 19:54:13.813200 11, 0xFFFF, sum = 0
7739 19:54:13.816991 12, 0xFFFF, sum = 0
7740 19:54:13.817105 13, 0xFFFF, sum = 0
7741 19:54:13.820185 14, 0x0, sum = 1
7742 19:54:13.820268 15, 0x0, sum = 2
7743 19:54:13.823079 16, 0x0, sum = 3
7744 19:54:13.823195 17, 0x0, sum = 4
7745 19:54:13.823266 best_step = 15
7746 19:54:13.826371
7747 19:54:13.826503 ==
7748 19:54:13.830033 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 19:54:13.833145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 19:54:13.833237 ==
7751 19:54:13.833322 RX Vref Scan: 1
7752 19:54:13.833403
7753 19:54:13.836793 Set Vref Range= 24 -> 127
7754 19:54:13.836878
7755 19:54:13.840105 RX Vref 24 -> 127, step: 1
7756 19:54:13.840251
7757 19:54:13.843251 RX Delay 27 -> 252, step: 4
7758 19:54:13.843360
7759 19:54:13.846964 Set Vref, RX VrefLevel [Byte0]: 24
7760 19:54:13.850148 [Byte1]: 24
7761 19:54:13.850227
7762 19:54:13.853624 Set Vref, RX VrefLevel [Byte0]: 25
7763 19:54:13.856680 [Byte1]: 25
7764 19:54:13.856764
7765 19:54:13.860213 Set Vref, RX VrefLevel [Byte0]: 26
7766 19:54:13.863174 [Byte1]: 26
7767 19:54:13.866414
7768 19:54:13.866497 Set Vref, RX VrefLevel [Byte0]: 27
7769 19:54:13.870203 [Byte1]: 27
7770 19:54:13.873955
7771 19:54:13.874069 Set Vref, RX VrefLevel [Byte0]: 28
7772 19:54:13.877175 [Byte1]: 28
7773 19:54:13.881636
7774 19:54:13.881723 Set Vref, RX VrefLevel [Byte0]: 29
7775 19:54:13.884707 [Byte1]: 29
7776 19:54:13.888899
7777 19:54:13.888975 Set Vref, RX VrefLevel [Byte0]: 30
7778 19:54:13.892424 [Byte1]: 30
7779 19:54:13.896933
7780 19:54:13.897016 Set Vref, RX VrefLevel [Byte0]: 31
7781 19:54:13.900199 [Byte1]: 31
7782 19:54:13.903978
7783 19:54:13.904073 Set Vref, RX VrefLevel [Byte0]: 32
7784 19:54:13.907744 [Byte1]: 32
7785 19:54:13.911995
7786 19:54:13.912110 Set Vref, RX VrefLevel [Byte0]: 33
7787 19:54:13.914933 [Byte1]: 33
7788 19:54:13.919364
7789 19:54:13.919502 Set Vref, RX VrefLevel [Byte0]: 34
7790 19:54:13.922466 [Byte1]: 34
7791 19:54:13.926927
7792 19:54:13.927039 Set Vref, RX VrefLevel [Byte0]: 35
7793 19:54:13.930263 [Byte1]: 35
7794 19:54:13.934535
7795 19:54:13.934636 Set Vref, RX VrefLevel [Byte0]: 36
7796 19:54:13.937593 [Byte1]: 36
7797 19:54:13.941794
7798 19:54:13.941889 Set Vref, RX VrefLevel [Byte0]: 37
7799 19:54:13.945168 [Byte1]: 37
7800 19:54:13.949298
7801 19:54:13.949398 Set Vref, RX VrefLevel [Byte0]: 38
7802 19:54:13.952967 [Byte1]: 38
7803 19:54:13.957136
7804 19:54:13.957215 Set Vref, RX VrefLevel [Byte0]: 39
7805 19:54:13.960399 [Byte1]: 39
7806 19:54:13.964790
7807 19:54:13.964868 Set Vref, RX VrefLevel [Byte0]: 40
7808 19:54:13.967708 [Byte1]: 40
7809 19:54:13.972306
7810 19:54:13.972383 Set Vref, RX VrefLevel [Byte0]: 41
7811 19:54:13.975053 [Byte1]: 41
7812 19:54:13.979664
7813 19:54:13.979748 Set Vref, RX VrefLevel [Byte0]: 42
7814 19:54:13.982804 [Byte1]: 42
7815 19:54:13.987157
7816 19:54:13.987264 Set Vref, RX VrefLevel [Byte0]: 43
7817 19:54:13.990245 [Byte1]: 43
7818 19:54:13.994798
7819 19:54:13.994882 Set Vref, RX VrefLevel [Byte0]: 44
7820 19:54:13.997886 [Byte1]: 44
7821 19:54:14.002367
7822 19:54:14.002444 Set Vref, RX VrefLevel [Byte0]: 45
7823 19:54:14.005556 [Byte1]: 45
7824 19:54:14.009418
7825 19:54:14.009495 Set Vref, RX VrefLevel [Byte0]: 46
7826 19:54:14.013269 [Byte1]: 46
7827 19:54:14.017149
7828 19:54:14.017225 Set Vref, RX VrefLevel [Byte0]: 47
7829 19:54:14.020243 [Byte1]: 47
7830 19:54:14.024553
7831 19:54:14.024627 Set Vref, RX VrefLevel [Byte0]: 48
7832 19:54:14.028024 [Byte1]: 48
7833 19:54:14.032018
7834 19:54:14.032109 Set Vref, RX VrefLevel [Byte0]: 49
7835 19:54:14.035710 [Byte1]: 49
7836 19:54:14.039671
7837 19:54:14.039748 Set Vref, RX VrefLevel [Byte0]: 50
7838 19:54:14.042985 [Byte1]: 50
7839 19:54:14.047235
7840 19:54:14.047319 Set Vref, RX VrefLevel [Byte0]: 51
7841 19:54:14.050431 [Byte1]: 51
7842 19:54:14.054590
7843 19:54:14.054667 Set Vref, RX VrefLevel [Byte0]: 52
7844 19:54:14.057948 [Byte1]: 52
7845 19:54:14.062176
7846 19:54:14.062261 Set Vref, RX VrefLevel [Byte0]: 53
7847 19:54:14.065649 [Byte1]: 53
7848 19:54:14.069866
7849 19:54:14.069942 Set Vref, RX VrefLevel [Byte0]: 54
7850 19:54:14.073394 [Byte1]: 54
7851 19:54:14.077643
7852 19:54:14.077737 Set Vref, RX VrefLevel [Byte0]: 55
7853 19:54:14.080823 [Byte1]: 55
7854 19:54:14.084977
7855 19:54:14.085053 Set Vref, RX VrefLevel [Byte0]: 56
7856 19:54:14.088217 [Byte1]: 56
7857 19:54:14.092360
7858 19:54:14.092435 Set Vref, RX VrefLevel [Byte0]: 57
7859 19:54:14.096017 [Byte1]: 57
7860 19:54:14.100240
7861 19:54:14.100358 Set Vref, RX VrefLevel [Byte0]: 58
7862 19:54:14.103098 [Byte1]: 58
7863 19:54:14.107517
7864 19:54:14.107605 Set Vref, RX VrefLevel [Byte0]: 59
7865 19:54:14.110710 [Byte1]: 59
7866 19:54:14.115163
7867 19:54:14.115266 Set Vref, RX VrefLevel [Byte0]: 60
7868 19:54:14.118311 [Byte1]: 60
7869 19:54:14.122737
7870 19:54:14.122847 Set Vref, RX VrefLevel [Byte0]: 61
7871 19:54:14.125923 [Byte1]: 61
7872 19:54:14.130496
7873 19:54:14.130581 Set Vref, RX VrefLevel [Byte0]: 62
7874 19:54:14.133590 [Byte1]: 62
7875 19:54:14.137787
7876 19:54:14.137893 Set Vref, RX VrefLevel [Byte0]: 63
7877 19:54:14.141316 [Byte1]: 63
7878 19:54:14.145064
7879 19:54:14.145166 Set Vref, RX VrefLevel [Byte0]: 64
7880 19:54:14.148439 [Byte1]: 64
7881 19:54:14.152822
7882 19:54:14.152903 Set Vref, RX VrefLevel [Byte0]: 65
7883 19:54:14.155914 [Byte1]: 65
7884 19:54:14.160434
7885 19:54:14.160540 Set Vref, RX VrefLevel [Byte0]: 66
7886 19:54:14.163806 [Byte1]: 66
7887 19:54:14.167857
7888 19:54:14.167932 Set Vref, RX VrefLevel [Byte0]: 67
7889 19:54:14.171275 [Byte1]: 67
7890 19:54:14.175509
7891 19:54:14.175611 Set Vref, RX VrefLevel [Byte0]: 68
7892 19:54:14.178609 [Byte1]: 68
7893 19:54:14.182811
7894 19:54:14.182887 Set Vref, RX VrefLevel [Byte0]: 69
7895 19:54:14.186028 [Byte1]: 69
7896 19:54:14.190335
7897 19:54:14.190409 Set Vref, RX VrefLevel [Byte0]: 70
7898 19:54:14.197331 [Byte1]: 70
7899 19:54:14.197454
7900 19:54:14.200136 Set Vref, RX VrefLevel [Byte0]: 71
7901 19:54:14.203506 [Byte1]: 71
7902 19:54:14.203589
7903 19:54:14.207052 Set Vref, RX VrefLevel [Byte0]: 72
7904 19:54:14.210321 [Byte1]: 72
7905 19:54:14.210405
7906 19:54:14.213502 Set Vref, RX VrefLevel [Byte0]: 73
7907 19:54:14.216706 [Byte1]: 73
7908 19:54:14.220420
7909 19:54:14.220494 Final RX Vref Byte 0 = 57 to rank0
7910 19:54:14.223657 Final RX Vref Byte 1 = 64 to rank0
7911 19:54:14.226894 Final RX Vref Byte 0 = 57 to rank1
7912 19:54:14.230710 Final RX Vref Byte 1 = 64 to rank1==
7913 19:54:14.233902 Dram Type= 6, Freq= 0, CH_0, rank 0
7914 19:54:14.240254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7915 19:54:14.240329 ==
7916 19:54:14.240393 DQS Delay:
7917 19:54:14.244026 DQS0 = 0, DQS1 = 0
7918 19:54:14.244102 DQM Delay:
7919 19:54:14.244164 DQM0 = 134, DQM1 = 128
7920 19:54:14.247107 DQ Delay:
7921 19:54:14.250769 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7922 19:54:14.253621 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =140
7923 19:54:14.257011 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7924 19:54:14.260303 DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136
7925 19:54:14.260380
7926 19:54:14.260481
7927 19:54:14.260573
7928 19:54:14.263803 [DramC_TX_OE_Calibration] TA2
7929 19:54:14.267009 Original DQ_B0 (3 6) =30, OEN = 27
7930 19:54:14.270349 Original DQ_B1 (3 6) =30, OEN = 27
7931 19:54:14.273488 24, 0x0, End_B0=24 End_B1=24
7932 19:54:14.273602 25, 0x0, End_B0=25 End_B1=25
7933 19:54:14.277024 26, 0x0, End_B0=26 End_B1=26
7934 19:54:14.280440 27, 0x0, End_B0=27 End_B1=27
7935 19:54:14.283543 28, 0x0, End_B0=28 End_B1=28
7936 19:54:14.286788 29, 0x0, End_B0=29 End_B1=29
7937 19:54:14.286863 30, 0x0, End_B0=30 End_B1=30
7938 19:54:14.290581 31, 0x4141, End_B0=30 End_B1=30
7939 19:54:14.293646 Byte0 end_step=30 best_step=27
7940 19:54:14.297245 Byte1 end_step=30 best_step=27
7941 19:54:14.300190 Byte0 TX OE(2T, 0.5T) = (3, 3)
7942 19:54:14.303482 Byte1 TX OE(2T, 0.5T) = (3, 3)
7943 19:54:14.303592
7944 19:54:14.303692
7945 19:54:14.310166 [DQSOSCAuto] RK0, (LSB)MR18= 0x2622, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7946 19:54:14.313752 CH0 RK0: MR19=303, MR18=2622
7947 19:54:14.319927 CH0_RK0: MR19=0x303, MR18=0x2622, DQSOSC=390, MR23=63, INC=24, DEC=16
7948 19:54:14.320051
7949 19:54:14.323479 ----->DramcWriteLeveling(PI) begin...
7950 19:54:14.323587 ==
7951 19:54:14.326634 Dram Type= 6, Freq= 0, CH_0, rank 1
7952 19:54:14.329984 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7953 19:54:14.330093 ==
7954 19:54:14.333215 Write leveling (Byte 0): 36 => 36
7955 19:54:14.336399 Write leveling (Byte 1): 28 => 28
7956 19:54:14.339804 DramcWriteLeveling(PI) end<-----
7957 19:54:14.339900
7958 19:54:14.339971 ==
7959 19:54:14.343186 Dram Type= 6, Freq= 0, CH_0, rank 1
7960 19:54:14.346358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 19:54:14.346469 ==
7962 19:54:14.350206 [Gating] SW mode calibration
7963 19:54:14.356597 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7964 19:54:14.363044 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7965 19:54:14.366600 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 19:54:14.370034 1 4 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7967 19:54:14.376581 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 19:54:14.379604 1 4 12 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7969 19:54:14.383229 1 4 16 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7970 19:54:14.389743 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7971 19:54:14.392942 1 4 24 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7972 19:54:14.396334 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7973 19:54:14.403015 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7974 19:54:14.406735 1 5 4 | B1->B0 | 3434 3b3b | 1 0 | (1 1) (0 0)
7975 19:54:14.409831 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7976 19:54:14.416342 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
7977 19:54:14.419573 1 5 16 | B1->B0 | 2f2f 2828 | 0 0 | (1 0) (0 0)
7978 19:54:14.423131 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7979 19:54:14.429787 1 5 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7980 19:54:14.433301 1 5 28 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7981 19:54:14.436301 1 6 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7982 19:54:14.442670 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7983 19:54:14.446539 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7984 19:54:14.449596 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7985 19:54:14.456485 1 6 16 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
7986 19:54:14.459256 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 19:54:14.463029 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 19:54:14.469481 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 19:54:14.472752 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 19:54:14.475961 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 19:54:14.482611 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 19:54:14.486192 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7993 19:54:14.489038 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7994 19:54:14.496183 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 19:54:14.499079 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 19:54:14.502896 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 19:54:14.509417 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 19:54:14.512479 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 19:54:14.515728 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 19:54:14.522652 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 19:54:14.525711 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 19:54:14.529060 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 19:54:14.532387 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 19:54:14.539040 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 19:54:14.542518 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 19:54:14.545701 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 19:54:14.552177 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 19:54:14.555667 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8009 19:54:14.559057 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8010 19:54:14.562131 Total UI for P1: 0, mck2ui 16
8011 19:54:14.565395 best dqsien dly found for B1: ( 1, 9, 14)
8012 19:54:14.571926 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 19:54:14.575862 Total UI for P1: 0, mck2ui 16
8014 19:54:14.579065 best dqsien dly found for B0: ( 1, 9, 14)
8015 19:54:14.582314 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8016 19:54:14.585269 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8017 19:54:14.585363
8018 19:54:14.589135 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8019 19:54:14.592435 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8020 19:54:14.595517 [Gating] SW calibration Done
8021 19:54:14.595641 ==
8022 19:54:14.598634 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 19:54:14.602126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 19:54:14.602221 ==
8025 19:54:14.605628 RX Vref Scan: 0
8026 19:54:14.605703
8027 19:54:14.608749 RX Vref 0 -> 0, step: 1
8028 19:54:14.608829
8029 19:54:14.608906 RX Delay 0 -> 252, step: 8
8030 19:54:14.615648 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8031 19:54:14.618547 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8032 19:54:14.621886 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8033 19:54:14.624979 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8034 19:54:14.628265 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8035 19:54:14.635291 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8036 19:54:14.638504 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8037 19:54:14.641998 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8038 19:54:14.645338 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8039 19:54:14.648604 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8040 19:54:14.654932 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8041 19:54:14.658354 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8042 19:54:14.661925 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8043 19:54:14.665228 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8044 19:54:14.668405 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8045 19:54:14.675188 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8046 19:54:14.675279 ==
8047 19:54:14.678460 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 19:54:14.681676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 19:54:14.681768 ==
8050 19:54:14.681870 DQS Delay:
8051 19:54:14.685077 DQS0 = 0, DQS1 = 0
8052 19:54:14.685185 DQM Delay:
8053 19:54:14.688066 DQM0 = 136, DQM1 = 128
8054 19:54:14.688142 DQ Delay:
8055 19:54:14.691973 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8056 19:54:14.695220 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8057 19:54:14.698421 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8058 19:54:14.701810 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8059 19:54:14.701895
8060 19:54:14.701967
8061 19:54:14.705075 ==
8062 19:54:14.708872 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 19:54:14.711513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 19:54:14.711620 ==
8065 19:54:14.711697
8066 19:54:14.711759
8067 19:54:14.714833 TX Vref Scan disable
8068 19:54:14.714906 == TX Byte 0 ==
8069 19:54:14.718529 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8070 19:54:14.725022 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8071 19:54:14.725101 == TX Byte 1 ==
8072 19:54:14.728192 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8073 19:54:14.734982 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8074 19:54:14.735066 ==
8075 19:54:14.738441 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 19:54:14.741619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 19:54:14.741703 ==
8078 19:54:14.756874
8079 19:54:14.760335 TX Vref early break, caculate TX vref
8080 19:54:14.763409 TX Vref=16, minBit 0, minWin=22, winSum=386
8081 19:54:14.766862 TX Vref=18, minBit 1, minWin=23, winSum=393
8082 19:54:14.770024 TX Vref=20, minBit 1, minWin=24, winSum=407
8083 19:54:14.773698 TX Vref=22, minBit 3, minWin=24, winSum=409
8084 19:54:14.776536 TX Vref=24, minBit 1, minWin=25, winSum=421
8085 19:54:14.783440 TX Vref=26, minBit 4, minWin=24, winSum=423
8086 19:54:14.786423 TX Vref=28, minBit 0, minWin=25, winSum=424
8087 19:54:14.790018 TX Vref=30, minBit 11, minWin=25, winSum=420
8088 19:54:14.792962 TX Vref=32, minBit 1, minWin=24, winSum=405
8089 19:54:14.796688 TX Vref=34, minBit 1, minWin=24, winSum=403
8090 19:54:14.799979 TX Vref=36, minBit 0, minWin=24, winSum=391
8091 19:54:14.806274 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8092 19:54:14.806382
8093 19:54:14.809996 Final TX Range 0 Vref 28
8094 19:54:14.810082
8095 19:54:14.810147 ==
8096 19:54:14.813069 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 19:54:14.816285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 19:54:14.816371 ==
8099 19:54:14.816435
8100 19:54:14.819445
8101 19:54:14.819544 TX Vref Scan disable
8102 19:54:14.826432 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8103 19:54:14.826507 == TX Byte 0 ==
8104 19:54:14.829686 u2DelayCellOfst[0]=13 cells (4 PI)
8105 19:54:14.832823 u2DelayCellOfst[1]=16 cells (5 PI)
8106 19:54:14.836070 u2DelayCellOfst[2]=13 cells (4 PI)
8107 19:54:14.839833 u2DelayCellOfst[3]=13 cells (4 PI)
8108 19:54:14.843336 u2DelayCellOfst[4]=10 cells (3 PI)
8109 19:54:14.846373 u2DelayCellOfst[5]=0 cells (0 PI)
8110 19:54:14.849578 u2DelayCellOfst[6]=20 cells (6 PI)
8111 19:54:14.853202 u2DelayCellOfst[7]=16 cells (5 PI)
8112 19:54:14.856460 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8113 19:54:14.859642 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8114 19:54:14.862601 == TX Byte 1 ==
8115 19:54:14.865897 u2DelayCellOfst[8]=0 cells (0 PI)
8116 19:54:14.869230 u2DelayCellOfst[9]=0 cells (0 PI)
8117 19:54:14.873050 u2DelayCellOfst[10]=6 cells (2 PI)
8118 19:54:14.873141 u2DelayCellOfst[11]=3 cells (1 PI)
8119 19:54:14.875829 u2DelayCellOfst[12]=10 cells (3 PI)
8120 19:54:14.879506 u2DelayCellOfst[13]=10 cells (3 PI)
8121 19:54:14.882681 u2DelayCellOfst[14]=13 cells (4 PI)
8122 19:54:14.885853 u2DelayCellOfst[15]=10 cells (3 PI)
8123 19:54:14.893058 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8124 19:54:14.896262 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8125 19:54:14.896352 DramC Write-DBI on
8126 19:54:14.896435 ==
8127 19:54:14.899153 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 19:54:14.905927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 19:54:14.906012 ==
8130 19:54:14.906095
8131 19:54:14.906176
8132 19:54:14.906253 TX Vref Scan disable
8133 19:54:14.910299 == TX Byte 0 ==
8134 19:54:14.913480 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8135 19:54:14.917293 == TX Byte 1 ==
8136 19:54:14.920489 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8137 19:54:14.923633 DramC Write-DBI off
8138 19:54:14.923717
8139 19:54:14.923781 [DATLAT]
8140 19:54:14.923859 Freq=1600, CH0 RK1
8141 19:54:14.923920
8142 19:54:14.926764 DATLAT Default: 0xf
8143 19:54:14.926868 0, 0xFFFF, sum = 0
8144 19:54:14.930083 1, 0xFFFF, sum = 0
8145 19:54:14.933337 2, 0xFFFF, sum = 0
8146 19:54:14.933456 3, 0xFFFF, sum = 0
8147 19:54:14.937149 4, 0xFFFF, sum = 0
8148 19:54:14.937245 5, 0xFFFF, sum = 0
8149 19:54:14.940293 6, 0xFFFF, sum = 0
8150 19:54:14.940392 7, 0xFFFF, sum = 0
8151 19:54:14.943455 8, 0xFFFF, sum = 0
8152 19:54:14.943583 9, 0xFFFF, sum = 0
8153 19:54:14.946643 10, 0xFFFF, sum = 0
8154 19:54:14.946749 11, 0xFFFF, sum = 0
8155 19:54:14.949956 12, 0xFFFF, sum = 0
8156 19:54:14.950045 13, 0xFFFF, sum = 0
8157 19:54:14.953095 14, 0x0, sum = 1
8158 19:54:14.953218 15, 0x0, sum = 2
8159 19:54:14.956450 16, 0x0, sum = 3
8160 19:54:14.956543 17, 0x0, sum = 4
8161 19:54:14.959708 best_step = 15
8162 19:54:14.959788
8163 19:54:14.959876 ==
8164 19:54:14.963253 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 19:54:14.966590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 19:54:14.966671 ==
8167 19:54:14.969884 RX Vref Scan: 0
8168 19:54:14.969965
8169 19:54:14.970049 RX Vref 0 -> 0, step: 1
8170 19:54:14.970133
8171 19:54:14.973128 RX Delay 19 -> 252, step: 4
8172 19:54:14.976646 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8173 19:54:14.982891 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8174 19:54:14.986736 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8175 19:54:14.989613 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8176 19:54:14.993439 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8177 19:54:14.996664 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8178 19:54:15.003054 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8179 19:54:15.006593 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8180 19:54:15.010116 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8181 19:54:15.013303 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8182 19:54:15.016394 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8183 19:54:15.022775 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8184 19:54:15.026451 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8185 19:54:15.029554 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8186 19:54:15.033360 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8187 19:54:15.036417 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8188 19:54:15.039730 ==
8189 19:54:15.042918 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 19:54:15.046186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 19:54:15.046267 ==
8192 19:54:15.046355 DQS Delay:
8193 19:54:15.049883 DQS0 = 0, DQS1 = 0
8194 19:54:15.049962 DQM Delay:
8195 19:54:15.053095 DQM0 = 134, DQM1 = 127
8196 19:54:15.053177 DQ Delay:
8197 19:54:15.056236 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8198 19:54:15.060047 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8199 19:54:15.063059 DQ8 =120, DQ9 =116, DQ10 =130, DQ11 =118
8200 19:54:15.066473 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
8201 19:54:15.066553
8202 19:54:15.066637
8203 19:54:15.066717
8204 19:54:15.069635 [DramC_TX_OE_Calibration] TA2
8205 19:54:15.073296 Original DQ_B0 (3 6) =30, OEN = 27
8206 19:54:15.076355 Original DQ_B1 (3 6) =30, OEN = 27
8207 19:54:15.079887 24, 0x0, End_B0=24 End_B1=24
8208 19:54:15.083082 25, 0x0, End_B0=25 End_B1=25
8209 19:54:15.083165 26, 0x0, End_B0=26 End_B1=26
8210 19:54:15.086350 27, 0x0, End_B0=27 End_B1=27
8211 19:54:15.089829 28, 0x0, End_B0=28 End_B1=28
8212 19:54:15.093144 29, 0x0, End_B0=29 End_B1=29
8213 19:54:15.093226 30, 0x0, End_B0=30 End_B1=30
8214 19:54:15.096226 31, 0x4141, End_B0=30 End_B1=30
8215 19:54:15.099809 Byte0 end_step=30 best_step=27
8216 19:54:15.103178 Byte1 end_step=30 best_step=27
8217 19:54:15.105999 Byte0 TX OE(2T, 0.5T) = (3, 3)
8218 19:54:15.109761 Byte1 TX OE(2T, 0.5T) = (3, 3)
8219 19:54:15.109840
8220 19:54:15.109924
8221 19:54:15.116538 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8222 19:54:15.119544 CH0 RK1: MR19=303, MR18=220A
8223 19:54:15.126049 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8224 19:54:15.129849 [RxdqsGatingPostProcess] freq 1600
8225 19:54:15.133023 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8226 19:54:15.136483 best DQS0 dly(2T, 0.5T) = (1, 1)
8227 19:54:15.139490 best DQS1 dly(2T, 0.5T) = (1, 1)
8228 19:54:15.143346 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8229 19:54:15.146442 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8230 19:54:15.149549 best DQS0 dly(2T, 0.5T) = (1, 1)
8231 19:54:15.152750 best DQS1 dly(2T, 0.5T) = (1, 1)
8232 19:54:15.156516 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8233 19:54:15.159720 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8234 19:54:15.162860 Pre-setting of DQS Precalculation
8235 19:54:15.165992 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8236 19:54:15.166069 ==
8237 19:54:15.169773 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 19:54:15.172691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8239 19:54:15.176490 ==
8240 19:54:15.179657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8241 19:54:15.182834 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8242 19:54:15.189531 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8243 19:54:15.195785 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8244 19:54:15.203471 [CA 0] Center 42 (13~72) winsize 60
8245 19:54:15.206347 [CA 1] Center 42 (13~72) winsize 60
8246 19:54:15.209729 [CA 2] Center 38 (9~68) winsize 60
8247 19:54:15.213599 [CA 3] Center 38 (9~68) winsize 60
8248 19:54:15.216737 [CA 4] Center 39 (10~68) winsize 59
8249 19:54:15.219865 [CA 5] Center 37 (8~67) winsize 60
8250 19:54:15.219949
8251 19:54:15.222875 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8252 19:54:15.222954
8253 19:54:15.226612 [CATrainingPosCal] consider 1 rank data
8254 19:54:15.229784 u2DelayCellTimex100 = 290/100 ps
8255 19:54:15.233356 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8256 19:54:15.239596 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8257 19:54:15.243132 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8258 19:54:15.246787 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8259 19:54:15.249636 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8260 19:54:15.253339 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8261 19:54:15.253423
8262 19:54:15.256561 CA PerBit enable=1, Macro0, CA PI delay=37
8263 19:54:15.256644
8264 19:54:15.259790 [CBTSetCACLKResult] CA Dly = 37
8265 19:54:15.262966 CS Dly: 10 (0~41)
8266 19:54:15.266690 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8267 19:54:15.269850 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8268 19:54:15.269933 ==
8269 19:54:15.273120 Dram Type= 6, Freq= 0, CH_1, rank 1
8270 19:54:15.276599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8271 19:54:15.279520 ==
8272 19:54:15.283231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8273 19:54:15.286383 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8274 19:54:15.292651 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8275 19:54:15.299384 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8276 19:54:15.306725 [CA 0] Center 42 (12~72) winsize 61
8277 19:54:15.310150 [CA 1] Center 42 (13~71) winsize 59
8278 19:54:15.313249 [CA 2] Center 38 (9~68) winsize 60
8279 19:54:15.316368 [CA 3] Center 37 (8~67) winsize 60
8280 19:54:15.320051 [CA 4] Center 39 (9~69) winsize 61
8281 19:54:15.323105 [CA 5] Center 37 (7~67) winsize 61
8282 19:54:15.323186
8283 19:54:15.326562 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8284 19:54:15.326648
8285 19:54:15.329890 [CATrainingPosCal] consider 2 rank data
8286 19:54:15.333502 u2DelayCellTimex100 = 290/100 ps
8287 19:54:15.336708 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8288 19:54:15.343053 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8289 19:54:15.346842 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8290 19:54:15.349992 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8291 19:54:15.352913 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8292 19:54:15.356381 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8293 19:54:15.356494
8294 19:54:15.359576 CA PerBit enable=1, Macro0, CA PI delay=37
8295 19:54:15.359701
8296 19:54:15.362982 [CBTSetCACLKResult] CA Dly = 37
8297 19:54:15.366165 CS Dly: 12 (0~45)
8298 19:54:15.369935 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8299 19:54:15.373136 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8300 19:54:15.373210
8301 19:54:15.376349 ----->DramcWriteLeveling(PI) begin...
8302 19:54:15.376418 ==
8303 19:54:15.379421 Dram Type= 6, Freq= 0, CH_1, rank 0
8304 19:54:15.385852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8305 19:54:15.385928 ==
8306 19:54:15.389727 Write leveling (Byte 0): 23 => 23
8307 19:54:15.389800 Write leveling (Byte 1): 28 => 28
8308 19:54:15.392937 DramcWriteLeveling(PI) end<-----
8309 19:54:15.393008
8310 19:54:15.393068 ==
8311 19:54:15.396168 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 19:54:15.403162 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 19:54:15.403240 ==
8314 19:54:15.406304 [Gating] SW mode calibration
8315 19:54:15.412959 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8316 19:54:15.415929 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8317 19:54:15.422671 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 19:54:15.425903 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 19:54:15.429395 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 19:54:15.435649 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8321 19:54:15.439274 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 19:54:15.442580 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 19:54:15.449003 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 19:54:15.452753 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 19:54:15.455978 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 19:54:15.462593 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 19:54:15.465956 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8328 19:54:15.469081 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8329 19:54:15.475811 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8330 19:54:15.478825 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 19:54:15.482535 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 19:54:15.488584 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 19:54:15.492186 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 19:54:15.495357 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 19:54:15.502410 1 6 8 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
8336 19:54:15.505536 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 19:54:15.508736 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 19:54:15.511861 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 19:54:15.518877 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 19:54:15.521999 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 19:54:15.525665 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 19:54:15.531984 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 19:54:15.535466 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8344 19:54:15.538987 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8345 19:54:15.545581 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 19:54:15.548714 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 19:54:15.552292 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 19:54:15.558787 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 19:54:15.562106 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 19:54:15.565415 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 19:54:15.571773 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 19:54:15.575300 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 19:54:15.578695 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 19:54:15.585078 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 19:54:15.588780 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 19:54:15.591941 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 19:54:15.598680 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 19:54:15.601880 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 19:54:15.605095 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8360 19:54:15.611415 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8361 19:54:15.615227 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 19:54:15.618366 Total UI for P1: 0, mck2ui 16
8363 19:54:15.621515 best dqsien dly found for B0: ( 1, 9, 10)
8364 19:54:15.625309 Total UI for P1: 0, mck2ui 16
8365 19:54:15.628497 best dqsien dly found for B1: ( 1, 9, 10)
8366 19:54:15.631567 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8367 19:54:15.635230 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8368 19:54:15.635342
8369 19:54:15.638371 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 19:54:15.641511 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8371 19:54:15.644973 [Gating] SW calibration Done
8372 19:54:15.645085 ==
8373 19:54:15.648666 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 19:54:15.651542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 19:54:15.651664 ==
8376 19:54:15.655270 RX Vref Scan: 0
8377 19:54:15.655350
8378 19:54:15.658451 RX Vref 0 -> 0, step: 1
8379 19:54:15.658530
8380 19:54:15.658614 RX Delay 0 -> 252, step: 8
8381 19:54:15.665332 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8382 19:54:15.668502 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8383 19:54:15.671514 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8384 19:54:15.674951 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8385 19:54:15.678189 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8386 19:54:15.685298 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8387 19:54:15.688022 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8388 19:54:15.691379 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8389 19:54:15.695241 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8390 19:54:15.698084 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8391 19:54:15.704978 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8392 19:54:15.708327 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8393 19:54:15.711526 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8394 19:54:15.714733 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8395 19:54:15.717953 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8396 19:54:15.724895 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8397 19:54:15.724972 ==
8398 19:54:15.728066 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 19:54:15.731235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 19:54:15.731316 ==
8401 19:54:15.731379 DQS Delay:
8402 19:54:15.735046 DQS0 = 0, DQS1 = 0
8403 19:54:15.735120 DQM Delay:
8404 19:54:15.738142 DQM0 = 136, DQM1 = 133
8405 19:54:15.738216 DQ Delay:
8406 19:54:15.741112 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8407 19:54:15.744549 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8408 19:54:15.748058 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8409 19:54:15.751575 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8410 19:54:15.751675
8411 19:54:15.751752
8412 19:54:15.754676 ==
8413 19:54:15.758042 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 19:54:15.761555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 19:54:15.761632 ==
8416 19:54:15.761704
8417 19:54:15.761764
8418 19:54:15.764604 TX Vref Scan disable
8419 19:54:15.764676 == TX Byte 0 ==
8420 19:54:15.767817 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8421 19:54:15.774899 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8422 19:54:15.774978 == TX Byte 1 ==
8423 19:54:15.778071 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8424 19:54:15.785144 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8425 19:54:15.785225 ==
8426 19:54:15.788008 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 19:54:15.791420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 19:54:15.791496 ==
8429 19:54:15.804807
8430 19:54:15.808001 TX Vref early break, caculate TX vref
8431 19:54:15.811440 TX Vref=16, minBit 8, minWin=22, winSum=372
8432 19:54:15.814649 TX Vref=18, minBit 0, minWin=23, winSum=379
8433 19:54:15.817884 TX Vref=20, minBit 1, minWin=23, winSum=389
8434 19:54:15.821025 TX Vref=22, minBit 11, minWin=24, winSum=403
8435 19:54:15.824641 TX Vref=24, minBit 0, minWin=25, winSum=413
8436 19:54:15.831057 TX Vref=26, minBit 0, minWin=25, winSum=423
8437 19:54:15.834187 TX Vref=28, minBit 0, minWin=26, winSum=427
8438 19:54:15.837399 TX Vref=30, minBit 0, minWin=25, winSum=420
8439 19:54:15.841227 TX Vref=32, minBit 0, minWin=25, winSum=414
8440 19:54:15.844268 TX Vref=34, minBit 0, minWin=24, winSum=396
8441 19:54:15.850862 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8442 19:54:15.850948
8443 19:54:15.854282 Final TX Range 0 Vref 28
8444 19:54:15.854365
8445 19:54:15.854429 ==
8446 19:54:15.857519 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 19:54:15.860689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 19:54:15.860766 ==
8449 19:54:15.860830
8450 19:54:15.860889
8451 19:54:15.863923 TX Vref Scan disable
8452 19:54:15.870924 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8453 19:54:15.871003 == TX Byte 0 ==
8454 19:54:15.873883 u2DelayCellOfst[0]=13 cells (4 PI)
8455 19:54:15.876990 u2DelayCellOfst[1]=10 cells (3 PI)
8456 19:54:15.880813 u2DelayCellOfst[2]=0 cells (0 PI)
8457 19:54:15.884001 u2DelayCellOfst[3]=6 cells (2 PI)
8458 19:54:15.887243 u2DelayCellOfst[4]=10 cells (3 PI)
8459 19:54:15.890372 u2DelayCellOfst[5]=16 cells (5 PI)
8460 19:54:15.894138 u2DelayCellOfst[6]=16 cells (5 PI)
8461 19:54:15.897039 u2DelayCellOfst[7]=6 cells (2 PI)
8462 19:54:15.900567 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8463 19:54:15.903989 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8464 19:54:15.907109 == TX Byte 1 ==
8465 19:54:15.910843 u2DelayCellOfst[8]=0 cells (0 PI)
8466 19:54:15.910938 u2DelayCellOfst[9]=3 cells (1 PI)
8467 19:54:15.914238 u2DelayCellOfst[10]=13 cells (4 PI)
8468 19:54:15.917398 u2DelayCellOfst[11]=6 cells (2 PI)
8469 19:54:15.920472 u2DelayCellOfst[12]=16 cells (5 PI)
8470 19:54:15.923904 u2DelayCellOfst[13]=16 cells (5 PI)
8471 19:54:15.927402 u2DelayCellOfst[14]=20 cells (6 PI)
8472 19:54:15.930293 u2DelayCellOfst[15]=20 cells (6 PI)
8473 19:54:15.933581 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8474 19:54:15.940774 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8475 19:54:15.940869 DramC Write-DBI on
8476 19:54:15.940955 ==
8477 19:54:15.944056 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 19:54:15.950610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 19:54:15.950705 ==
8480 19:54:15.950805
8481 19:54:15.950896
8482 19:54:15.950981 TX Vref Scan disable
8483 19:54:15.953787 == TX Byte 0 ==
8484 19:54:15.957529 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8485 19:54:15.960608 == TX Byte 1 ==
8486 19:54:15.964052 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8487 19:54:15.967439 DramC Write-DBI off
8488 19:54:15.967515
8489 19:54:15.967587 [DATLAT]
8490 19:54:15.967659 Freq=1600, CH1 RK0
8491 19:54:15.967721
8492 19:54:15.970752 DATLAT Default: 0xf
8493 19:54:15.970838 0, 0xFFFF, sum = 0
8494 19:54:15.973825 1, 0xFFFF, sum = 0
8495 19:54:15.973904 2, 0xFFFF, sum = 0
8496 19:54:15.977303 3, 0xFFFF, sum = 0
8497 19:54:15.980914 4, 0xFFFF, sum = 0
8498 19:54:15.980992 5, 0xFFFF, sum = 0
8499 19:54:15.983979 6, 0xFFFF, sum = 0
8500 19:54:15.984091 7, 0xFFFF, sum = 0
8501 19:54:15.987222 8, 0xFFFF, sum = 0
8502 19:54:15.987302 9, 0xFFFF, sum = 0
8503 19:54:15.990944 10, 0xFFFF, sum = 0
8504 19:54:15.991028 11, 0xFFFF, sum = 0
8505 19:54:15.994060 12, 0xFFFF, sum = 0
8506 19:54:15.994138 13, 0xFFFF, sum = 0
8507 19:54:15.997222 14, 0x0, sum = 1
8508 19:54:15.997307 15, 0x0, sum = 2
8509 19:54:16.000372 16, 0x0, sum = 3
8510 19:54:16.000450 17, 0x0, sum = 4
8511 19:54:16.003958 best_step = 15
8512 19:54:16.004042
8513 19:54:16.004107 ==
8514 19:54:16.007073 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 19:54:16.010479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 19:54:16.010557 ==
8517 19:54:16.010620 RX Vref Scan: 1
8518 19:54:16.014058
8519 19:54:16.014138 Set Vref Range= 24 -> 127
8520 19:54:16.014209
8521 19:54:16.017089 RX Vref 24 -> 127, step: 1
8522 19:54:16.017172
8523 19:54:16.020835 RX Delay 27 -> 252, step: 4
8524 19:54:16.020918
8525 19:54:16.023814 Set Vref, RX VrefLevel [Byte0]: 24
8526 19:54:16.027550 [Byte1]: 24
8527 19:54:16.027657
8528 19:54:16.030564 Set Vref, RX VrefLevel [Byte0]: 25
8529 19:54:16.033814 [Byte1]: 25
8530 19:54:16.033888
8531 19:54:16.036839 Set Vref, RX VrefLevel [Byte0]: 26
8532 19:54:16.040344 [Byte1]: 26
8533 19:54:16.044271
8534 19:54:16.044348 Set Vref, RX VrefLevel [Byte0]: 27
8535 19:54:16.047598 [Byte1]: 27
8536 19:54:16.051686
8537 19:54:16.051790 Set Vref, RX VrefLevel [Byte0]: 28
8538 19:54:16.054768 [Byte1]: 28
8539 19:54:16.059263
8540 19:54:16.059348 Set Vref, RX VrefLevel [Byte0]: 29
8541 19:54:16.062513 [Byte1]: 29
8542 19:54:16.066933
8543 19:54:16.067010 Set Vref, RX VrefLevel [Byte0]: 30
8544 19:54:16.069982 [Byte1]: 30
8545 19:54:16.074220
8546 19:54:16.074297 Set Vref, RX VrefLevel [Byte0]: 31
8547 19:54:16.077369 [Byte1]: 31
8548 19:54:16.081963
8549 19:54:16.082042 Set Vref, RX VrefLevel [Byte0]: 32
8550 19:54:16.085326 [Byte1]: 32
8551 19:54:16.089470
8552 19:54:16.089545 Set Vref, RX VrefLevel [Byte0]: 33
8553 19:54:16.092890 [Byte1]: 33
8554 19:54:16.097197
8555 19:54:16.097275 Set Vref, RX VrefLevel [Byte0]: 34
8556 19:54:16.100445 [Byte1]: 34
8557 19:54:16.104808
8558 19:54:16.104884 Set Vref, RX VrefLevel [Byte0]: 35
8559 19:54:16.107776 [Byte1]: 35
8560 19:54:16.112256
8561 19:54:16.112337 Set Vref, RX VrefLevel [Byte0]: 36
8562 19:54:16.115306 [Byte1]: 36
8563 19:54:16.119288
8564 19:54:16.119362 Set Vref, RX VrefLevel [Byte0]: 37
8565 19:54:16.122918 [Byte1]: 37
8566 19:54:16.127221
8567 19:54:16.127303 Set Vref, RX VrefLevel [Byte0]: 38
8568 19:54:16.130138 [Byte1]: 38
8569 19:54:16.134475
8570 19:54:16.134579 Set Vref, RX VrefLevel [Byte0]: 39
8571 19:54:16.138203 [Byte1]: 39
8572 19:54:16.141895
8573 19:54:16.141996 Set Vref, RX VrefLevel [Byte0]: 40
8574 19:54:16.145675 [Byte1]: 40
8575 19:54:16.149459
8576 19:54:16.149561 Set Vref, RX VrefLevel [Byte0]: 41
8577 19:54:16.152973 [Byte1]: 41
8578 19:54:16.157467
8579 19:54:16.157553 Set Vref, RX VrefLevel [Byte0]: 42
8580 19:54:16.160339 [Byte1]: 42
8581 19:54:16.165070
8582 19:54:16.165153 Set Vref, RX VrefLevel [Byte0]: 43
8583 19:54:16.168272 [Byte1]: 43
8584 19:54:16.172117
8585 19:54:16.172202 Set Vref, RX VrefLevel [Byte0]: 44
8586 19:54:16.175918 [Byte1]: 44
8587 19:54:16.179742
8588 19:54:16.179833 Set Vref, RX VrefLevel [Byte0]: 45
8589 19:54:16.183240 [Byte1]: 45
8590 19:54:16.187511
8591 19:54:16.187593 Set Vref, RX VrefLevel [Byte0]: 46
8592 19:54:16.190557 [Byte1]: 46
8593 19:54:16.194804
8594 19:54:16.194880 Set Vref, RX VrefLevel [Byte0]: 47
8595 19:54:16.198448 [Byte1]: 47
8596 19:54:16.202237
8597 19:54:16.202314 Set Vref, RX VrefLevel [Byte0]: 48
8598 19:54:16.205493 [Byte1]: 48
8599 19:54:16.210215
8600 19:54:16.210293 Set Vref, RX VrefLevel [Byte0]: 49
8601 19:54:16.213340 [Byte1]: 49
8602 19:54:16.217755
8603 19:54:16.217869 Set Vref, RX VrefLevel [Byte0]: 50
8604 19:54:16.220888 [Byte1]: 50
8605 19:54:16.225062
8606 19:54:16.225138 Set Vref, RX VrefLevel [Byte0]: 51
8607 19:54:16.228475 [Byte1]: 51
8608 19:54:16.232726
8609 19:54:16.232802 Set Vref, RX VrefLevel [Byte0]: 52
8610 19:54:16.235714 [Byte1]: 52
8611 19:54:16.239947
8612 19:54:16.240021 Set Vref, RX VrefLevel [Byte0]: 53
8613 19:54:16.243233 [Byte1]: 53
8614 19:54:16.247655
8615 19:54:16.247747 Set Vref, RX VrefLevel [Byte0]: 54
8616 19:54:16.250786 [Byte1]: 54
8617 19:54:16.255309
8618 19:54:16.255393 Set Vref, RX VrefLevel [Byte0]: 55
8619 19:54:16.258668 [Byte1]: 55
8620 19:54:16.262904
8621 19:54:16.263011 Set Vref, RX VrefLevel [Byte0]: 56
8622 19:54:16.265836 [Byte1]: 56
8623 19:54:16.270209
8624 19:54:16.270341 Set Vref, RX VrefLevel [Byte0]: 57
8625 19:54:16.273329 [Byte1]: 57
8626 19:54:16.284585
8627 19:54:16.284728 Set Vref, RX VrefLevel [Byte0]: 58
8628 19:54:16.285039 [Byte1]: 58
8629 19:54:16.285370
8630 19:54:16.285480 Set Vref, RX VrefLevel [Byte0]: 59
8631 19:54:16.288272 [Byte1]: 59
8632 19:54:16.292590
8633 19:54:16.292687 Set Vref, RX VrefLevel [Byte0]: 60
8634 19:54:16.296314 [Byte1]: 60
8635 19:54:16.300120
8636 19:54:16.300220 Set Vref, RX VrefLevel [Byte0]: 61
8637 19:54:16.303944 [Byte1]: 61
8638 19:54:16.307969
8639 19:54:16.308079 Set Vref, RX VrefLevel [Byte0]: 62
8640 19:54:16.311157 [Byte1]: 62
8641 19:54:16.315297
8642 19:54:16.315386 Set Vref, RX VrefLevel [Byte0]: 63
8643 19:54:16.318609 [Byte1]: 63
8644 19:54:16.322792
8645 19:54:16.322891 Set Vref, RX VrefLevel [Byte0]: 64
8646 19:54:16.325984 [Byte1]: 64
8647 19:54:16.330291
8648 19:54:16.330394 Set Vref, RX VrefLevel [Byte0]: 65
8649 19:54:16.333800 [Byte1]: 65
8650 19:54:16.337799
8651 19:54:16.337913 Set Vref, RX VrefLevel [Byte0]: 66
8652 19:54:16.341523 [Byte1]: 66
8653 19:54:16.345769
8654 19:54:16.345840 Set Vref, RX VrefLevel [Byte0]: 67
8655 19:54:16.349226 [Byte1]: 67
8656 19:54:16.353231
8657 19:54:16.353348 Set Vref, RX VrefLevel [Byte0]: 68
8658 19:54:16.356437 [Byte1]: 68
8659 19:54:16.360726
8660 19:54:16.360814 Set Vref, RX VrefLevel [Byte0]: 69
8661 19:54:16.364042 [Byte1]: 69
8662 19:54:16.368282
8663 19:54:16.368354 Set Vref, RX VrefLevel [Byte0]: 70
8664 19:54:16.371559 [Byte1]: 70
8665 19:54:16.375720
8666 19:54:16.375812 Set Vref, RX VrefLevel [Byte0]: 71
8667 19:54:16.379206 [Byte1]: 71
8668 19:54:16.383275
8669 19:54:16.383384 Set Vref, RX VrefLevel [Byte0]: 72
8670 19:54:16.386420 [Byte1]: 72
8671 19:54:16.390689
8672 19:54:16.390794 Set Vref, RX VrefLevel [Byte0]: 73
8673 19:54:16.393764 [Byte1]: 73
8674 19:54:16.398449
8675 19:54:16.398527 Set Vref, RX VrefLevel [Byte0]: 74
8676 19:54:16.401553 [Byte1]: 74
8677 19:54:16.406071
8678 19:54:16.406144 Set Vref, RX VrefLevel [Byte0]: 75
8679 19:54:16.409174 [Byte1]: 75
8680 19:54:16.413602
8681 19:54:16.413673 Set Vref, RX VrefLevel [Byte0]: 76
8682 19:54:16.416678 [Byte1]: 76
8683 19:54:16.421182
8684 19:54:16.421255 Final RX Vref Byte 0 = 57 to rank0
8685 19:54:16.424179 Final RX Vref Byte 1 = 56 to rank0
8686 19:54:16.427691 Final RX Vref Byte 0 = 57 to rank1
8687 19:54:16.431024 Final RX Vref Byte 1 = 56 to rank1==
8688 19:54:16.434313 Dram Type= 6, Freq= 0, CH_1, rank 0
8689 19:54:16.440590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8690 19:54:16.440667 ==
8691 19:54:16.440732 DQS Delay:
8692 19:54:16.440809 DQS0 = 0, DQS1 = 0
8693 19:54:16.444014 DQM Delay:
8694 19:54:16.444089 DQM0 = 134, DQM1 = 131
8695 19:54:16.447684 DQ Delay:
8696 19:54:16.450877 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8697 19:54:16.454064 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =134
8698 19:54:16.457620 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8699 19:54:16.461051 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8700 19:54:16.461161
8701 19:54:16.461258
8702 19:54:16.461347
8703 19:54:16.464032 [DramC_TX_OE_Calibration] TA2
8704 19:54:16.467761 Original DQ_B0 (3 6) =30, OEN = 27
8705 19:54:16.470991 Original DQ_B1 (3 6) =30, OEN = 27
8706 19:54:16.474161 24, 0x0, End_B0=24 End_B1=24
8707 19:54:16.474249 25, 0x0, End_B0=25 End_B1=25
8708 19:54:16.477256 26, 0x0, End_B0=26 End_B1=26
8709 19:54:16.480467 27, 0x0, End_B0=27 End_B1=27
8710 19:54:16.484186 28, 0x0, End_B0=28 End_B1=28
8711 19:54:16.484264 29, 0x0, End_B0=29 End_B1=29
8712 19:54:16.487628 30, 0x0, End_B0=30 End_B1=30
8713 19:54:16.490929 31, 0x4141, End_B0=30 End_B1=30
8714 19:54:16.494139 Byte0 end_step=30 best_step=27
8715 19:54:16.497309 Byte1 end_step=30 best_step=27
8716 19:54:16.501039 Byte0 TX OE(2T, 0.5T) = (3, 3)
8717 19:54:16.501120 Byte1 TX OE(2T, 0.5T) = (3, 3)
8718 19:54:16.501185
8719 19:54:16.503871
8720 19:54:16.510523 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8721 19:54:16.514315 CH1 RK0: MR19=303, MR18=1523
8722 19:54:16.520510 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8723 19:54:16.520615
8724 19:54:16.524263 ----->DramcWriteLeveling(PI) begin...
8725 19:54:16.524339 ==
8726 19:54:16.527477 Dram Type= 6, Freq= 0, CH_1, rank 1
8727 19:54:16.530588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 19:54:16.530683 ==
8729 19:54:16.534305 Write leveling (Byte 0): 27 => 27
8730 19:54:16.537266 Write leveling (Byte 1): 29 => 29
8731 19:54:16.540606 DramcWriteLeveling(PI) end<-----
8732 19:54:16.540680
8733 19:54:16.540759 ==
8734 19:54:16.543987 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 19:54:16.547450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 19:54:16.547525 ==
8737 19:54:16.550808 [Gating] SW mode calibration
8738 19:54:16.557348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8739 19:54:16.564080 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8740 19:54:16.567525 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 19:54:16.570520 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 19:54:16.577310 1 4 8 | B1->B0 | 2d2d 2323 | 1 0 | (1 1) (0 0)
8743 19:54:16.580538 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 1)
8744 19:54:16.583660 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8745 19:54:16.590635 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8746 19:54:16.593780 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8747 19:54:16.597316 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 19:54:16.603680 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 19:54:16.607107 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8750 19:54:16.610448 1 5 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
8751 19:54:16.616734 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 0)
8752 19:54:16.620402 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 19:54:16.623452 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 19:54:16.630409 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 19:54:16.633577 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 19:54:16.636795 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 19:54:16.643716 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 19:54:16.646684 1 6 8 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
8759 19:54:16.649930 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8760 19:54:16.656654 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8761 19:54:16.660005 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8762 19:54:16.663175 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8763 19:54:16.666596 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 19:54:16.673468 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 19:54:16.676500 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 19:54:16.680055 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8767 19:54:16.686398 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8768 19:54:16.690253 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 19:54:16.693520 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 19:54:16.699736 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 19:54:16.703431 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 19:54:16.706423 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 19:54:16.713502 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 19:54:16.716578 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 19:54:16.720148 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 19:54:16.727184 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 19:54:16.730003 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 19:54:16.732946 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 19:54:16.739927 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 19:54:16.743056 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 19:54:16.746827 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8782 19:54:16.753053 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8783 19:54:16.756894 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8784 19:54:16.759946 Total UI for P1: 0, mck2ui 16
8785 19:54:16.763096 best dqsien dly found for B1: ( 1, 9, 6)
8786 19:54:16.766770 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8787 19:54:16.772849 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 19:54:16.772925 Total UI for P1: 0, mck2ui 16
8789 19:54:16.776449 best dqsien dly found for B0: ( 1, 9, 14)
8790 19:54:16.783108 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8791 19:54:16.786455 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8792 19:54:16.786554
8793 19:54:16.789726 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8794 19:54:16.793302 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8795 19:54:16.796398 [Gating] SW calibration Done
8796 19:54:16.796504 ==
8797 19:54:16.799364 Dram Type= 6, Freq= 0, CH_1, rank 1
8798 19:54:16.802637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 19:54:16.802716 ==
8800 19:54:16.806555 RX Vref Scan: 0
8801 19:54:16.806653
8802 19:54:16.806742 RX Vref 0 -> 0, step: 1
8803 19:54:16.806832
8804 19:54:16.809784 RX Delay 0 -> 252, step: 8
8805 19:54:16.813257 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8806 19:54:16.816244 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8807 19:54:16.822781 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8808 19:54:16.826002 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8809 19:54:16.829582 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8810 19:54:16.832495 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8811 19:54:16.839093 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8812 19:54:16.842484 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8813 19:54:16.846079 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8814 19:54:16.849243 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8815 19:54:16.852751 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8816 19:54:16.859159 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8817 19:54:16.862865 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8818 19:54:16.866000 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8819 19:54:16.869198 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8820 19:54:16.872903 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8821 19:54:16.876091 ==
8822 19:54:16.876197 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 19:54:16.882171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 19:54:16.882272 ==
8825 19:54:16.882362 DQS Delay:
8826 19:54:16.885985 DQS0 = 0, DQS1 = 0
8827 19:54:16.886085 DQM Delay:
8828 19:54:16.889016 DQM0 = 136, DQM1 = 133
8829 19:54:16.889115 DQ Delay:
8830 19:54:16.892634 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8831 19:54:16.895661 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8832 19:54:16.899460 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8833 19:54:16.902726 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8834 19:54:16.902833
8835 19:54:16.902925
8836 19:54:16.903011 ==
8837 19:54:16.905699 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 19:54:16.912542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 19:54:16.912646 ==
8840 19:54:16.912737
8841 19:54:16.912864
8842 19:54:16.912951 TX Vref Scan disable
8843 19:54:16.915785 == TX Byte 0 ==
8844 19:54:16.919274 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8845 19:54:16.925579 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8846 19:54:16.925687 == TX Byte 1 ==
8847 19:54:16.929004 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8848 19:54:16.935571 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8849 19:54:16.935711 ==
8850 19:54:16.939400 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 19:54:16.942319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 19:54:16.942422 ==
8853 19:54:16.954305
8854 19:54:16.958020 TX Vref early break, caculate TX vref
8855 19:54:16.961181 TX Vref=16, minBit 1, minWin=23, winSum=381
8856 19:54:16.964341 TX Vref=18, minBit 1, minWin=23, winSum=390
8857 19:54:16.967550 TX Vref=20, minBit 0, minWin=23, winSum=397
8858 19:54:16.970817 TX Vref=22, minBit 2, minWin=24, winSum=408
8859 19:54:16.974536 TX Vref=24, minBit 2, minWin=24, winSum=414
8860 19:54:16.981360 TX Vref=26, minBit 0, minWin=25, winSum=425
8861 19:54:16.984541 TX Vref=28, minBit 15, minWin=25, winSum=425
8862 19:54:16.987525 TX Vref=30, minBit 0, minWin=25, winSum=416
8863 19:54:16.991469 TX Vref=32, minBit 0, minWin=24, winSum=409
8864 19:54:16.994578 TX Vref=34, minBit 0, minWin=24, winSum=402
8865 19:54:17.001313 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
8866 19:54:17.001412
8867 19:54:17.004404 Final TX Range 0 Vref 26
8868 19:54:17.004480
8869 19:54:17.004575 ==
8870 19:54:17.007536 Dram Type= 6, Freq= 0, CH_1, rank 1
8871 19:54:17.011332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8872 19:54:17.011432 ==
8873 19:54:17.011526
8874 19:54:17.011615
8875 19:54:17.014351 TX Vref Scan disable
8876 19:54:17.021251 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8877 19:54:17.021370 == TX Byte 0 ==
8878 19:54:17.024216 u2DelayCellOfst[0]=13 cells (4 PI)
8879 19:54:17.027596 u2DelayCellOfst[1]=10 cells (3 PI)
8880 19:54:17.031040 u2DelayCellOfst[2]=0 cells (0 PI)
8881 19:54:17.034460 u2DelayCellOfst[3]=6 cells (2 PI)
8882 19:54:17.037692 u2DelayCellOfst[4]=6 cells (2 PI)
8883 19:54:17.041043 u2DelayCellOfst[5]=16 cells (5 PI)
8884 19:54:17.041158 u2DelayCellOfst[6]=16 cells (5 PI)
8885 19:54:17.044269 u2DelayCellOfst[7]=6 cells (2 PI)
8886 19:54:17.051269 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8887 19:54:17.054670 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8888 19:54:17.054783 == TX Byte 1 ==
8889 19:54:17.057581 u2DelayCellOfst[8]=0 cells (0 PI)
8890 19:54:17.060762 u2DelayCellOfst[9]=3 cells (1 PI)
8891 19:54:17.064399 u2DelayCellOfst[10]=10 cells (3 PI)
8892 19:54:17.067793 u2DelayCellOfst[11]=6 cells (2 PI)
8893 19:54:17.071260 u2DelayCellOfst[12]=13 cells (4 PI)
8894 19:54:17.074430 u2DelayCellOfst[13]=16 cells (5 PI)
8895 19:54:17.077582 u2DelayCellOfst[14]=16 cells (5 PI)
8896 19:54:17.080726 u2DelayCellOfst[15]=16 cells (5 PI)
8897 19:54:17.084538 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8898 19:54:17.087527 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8899 19:54:17.091096 DramC Write-DBI on
8900 19:54:17.091178 ==
8901 19:54:17.094310 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 19:54:17.097414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 19:54:17.097524 ==
8904 19:54:17.097618
8905 19:54:17.100628
8906 19:54:17.100737 TX Vref Scan disable
8907 19:54:17.104126 == TX Byte 0 ==
8908 19:54:17.107267 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8909 19:54:17.111054 == TX Byte 1 ==
8910 19:54:17.114247 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8911 19:54:17.114331 DramC Write-DBI off
8912 19:54:17.114397
8913 19:54:17.117350 [DATLAT]
8914 19:54:17.117433 Freq=1600, CH1 RK1
8915 19:54:17.117499
8916 19:54:17.120507 DATLAT Default: 0xf
8917 19:54:17.120589 0, 0xFFFF, sum = 0
8918 19:54:17.124292 1, 0xFFFF, sum = 0
8919 19:54:17.124376 2, 0xFFFF, sum = 0
8920 19:54:17.127496 3, 0xFFFF, sum = 0
8921 19:54:17.127580 4, 0xFFFF, sum = 0
8922 19:54:17.130789 5, 0xFFFF, sum = 0
8923 19:54:17.130874 6, 0xFFFF, sum = 0
8924 19:54:17.133921 7, 0xFFFF, sum = 0
8925 19:54:17.136981 8, 0xFFFF, sum = 0
8926 19:54:17.137065 9, 0xFFFF, sum = 0
8927 19:54:17.140550 10, 0xFFFF, sum = 0
8928 19:54:17.140634 11, 0xFFFF, sum = 0
8929 19:54:17.143905 12, 0xFFFF, sum = 0
8930 19:54:17.143989 13, 0xFFFF, sum = 0
8931 19:54:17.147399 14, 0x0, sum = 1
8932 19:54:17.147482 15, 0x0, sum = 2
8933 19:54:17.150566 16, 0x0, sum = 3
8934 19:54:17.150649 17, 0x0, sum = 4
8935 19:54:17.154175 best_step = 15
8936 19:54:17.154256
8937 19:54:17.154320 ==
8938 19:54:17.157080 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 19:54:17.160355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 19:54:17.160436 ==
8941 19:54:17.160500 RX Vref Scan: 0
8942 19:54:17.160559
8943 19:54:17.164123 RX Vref 0 -> 0, step: 1
8944 19:54:17.164203
8945 19:54:17.166935 RX Delay 19 -> 252, step: 4
8946 19:54:17.170338 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8947 19:54:17.173917 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8948 19:54:17.180371 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8949 19:54:17.183988 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8950 19:54:17.187129 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8951 19:54:17.190298 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8952 19:54:17.193850 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8953 19:54:17.200151 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8954 19:54:17.203807 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8955 19:54:17.206924 iDelay=195, Bit 9, Center 120 (67 ~ 174) 108
8956 19:54:17.210656 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8957 19:54:17.213675 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8958 19:54:17.220099 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8959 19:54:17.223926 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8960 19:54:17.227092 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8961 19:54:17.230263 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
8962 19:54:17.230370 ==
8963 19:54:17.234128 Dram Type= 6, Freq= 0, CH_1, rank 1
8964 19:54:17.240515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8965 19:54:17.240597 ==
8966 19:54:17.240662 DQS Delay:
8967 19:54:17.240722 DQS0 = 0, DQS1 = 0
8968 19:54:17.243603 DQM Delay:
8969 19:54:17.243732 DQM0 = 134, DQM1 = 131
8970 19:54:17.247276 DQ Delay:
8971 19:54:17.250319 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8972 19:54:17.253550 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8973 19:54:17.256997 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =126
8974 19:54:17.260254 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
8975 19:54:17.260337
8976 19:54:17.260412
8977 19:54:17.260480
8978 19:54:17.263979 [DramC_TX_OE_Calibration] TA2
8979 19:54:17.267084 Original DQ_B0 (3 6) =30, OEN = 27
8980 19:54:17.270050 Original DQ_B1 (3 6) =30, OEN = 27
8981 19:54:17.273861 24, 0x0, End_B0=24 End_B1=24
8982 19:54:17.273973 25, 0x0, End_B0=25 End_B1=25
8983 19:54:17.276876 26, 0x0, End_B0=26 End_B1=26
8984 19:54:17.280256 27, 0x0, End_B0=27 End_B1=27
8985 19:54:17.283681 28, 0x0, End_B0=28 End_B1=28
8986 19:54:17.283783 29, 0x0, End_B0=29 End_B1=29
8987 19:54:17.286801 30, 0x0, End_B0=30 End_B1=30
8988 19:54:17.290458 31, 0x4141, End_B0=30 End_B1=30
8989 19:54:17.293774 Byte0 end_step=30 best_step=27
8990 19:54:17.296901 Byte1 end_step=30 best_step=27
8991 19:54:17.300421 Byte0 TX OE(2T, 0.5T) = (3, 3)
8992 19:54:17.300504 Byte1 TX OE(2T, 0.5T) = (3, 3)
8993 19:54:17.303699
8994 19:54:17.303782
8995 19:54:17.310001 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
8996 19:54:17.313369 CH1 RK1: MR19=303, MR18=2308
8997 19:54:17.319882 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
8998 19:54:17.323227 [RxdqsGatingPostProcess] freq 1600
8999 19:54:17.326976 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9000 19:54:17.330209 best DQS0 dly(2T, 0.5T) = (1, 1)
9001 19:54:17.333384 best DQS1 dly(2T, 0.5T) = (1, 1)
9002 19:54:17.336497 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9003 19:54:17.339662 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9004 19:54:17.343489 best DQS0 dly(2T, 0.5T) = (1, 1)
9005 19:54:17.346697 best DQS1 dly(2T, 0.5T) = (1, 1)
9006 19:54:17.349891 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9007 19:54:17.353083 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9008 19:54:17.356828 Pre-setting of DQS Precalculation
9009 19:54:17.359913 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9010 19:54:17.366726 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9011 19:54:17.373279 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9012 19:54:17.373378
9013 19:54:17.376329
9014 19:54:17.376418 [Calibration Summary] 3200 Mbps
9015 19:54:17.380175 CH 0, Rank 0
9016 19:54:17.380258 SW Impedance : PASS
9017 19:54:17.383186 DUTY Scan : NO K
9018 19:54:17.386723 ZQ Calibration : PASS
9019 19:54:17.386807 Jitter Meter : NO K
9020 19:54:17.389675 CBT Training : PASS
9021 19:54:17.393106 Write leveling : PASS
9022 19:54:17.393204 RX DQS gating : PASS
9023 19:54:17.396233 RX DQ/DQS(RDDQC) : PASS
9024 19:54:17.399400 TX DQ/DQS : PASS
9025 19:54:17.399483 RX DATLAT : PASS
9026 19:54:17.403012 RX DQ/DQS(Engine): PASS
9027 19:54:17.406545 TX OE : PASS
9028 19:54:17.406644 All Pass.
9029 19:54:17.406742
9030 19:54:17.406818 CH 0, Rank 1
9031 19:54:17.409853 SW Impedance : PASS
9032 19:54:17.409956 DUTY Scan : NO K
9033 19:54:17.413348 ZQ Calibration : PASS
9034 19:54:17.416404 Jitter Meter : NO K
9035 19:54:17.416480 CBT Training : PASS
9036 19:54:17.419469 Write leveling : PASS
9037 19:54:17.423149 RX DQS gating : PASS
9038 19:54:17.423223 RX DQ/DQS(RDDQC) : PASS
9039 19:54:17.426444 TX DQ/DQS : PASS
9040 19:54:17.429548 RX DATLAT : PASS
9041 19:54:17.429621 RX DQ/DQS(Engine): PASS
9042 19:54:17.432695 TX OE : PASS
9043 19:54:17.432772 All Pass.
9044 19:54:17.432835
9045 19:54:17.436472 CH 1, Rank 0
9046 19:54:17.436559 SW Impedance : PASS
9047 19:54:17.439425 DUTY Scan : NO K
9048 19:54:17.443199 ZQ Calibration : PASS
9049 19:54:17.443275 Jitter Meter : NO K
9050 19:54:17.446316 CBT Training : PASS
9051 19:54:17.449469 Write leveling : PASS
9052 19:54:17.449542 RX DQS gating : PASS
9053 19:54:17.452644 RX DQ/DQS(RDDQC) : PASS
9054 19:54:17.456451 TX DQ/DQS : PASS
9055 19:54:17.456528 RX DATLAT : PASS
9056 19:54:17.459681 RX DQ/DQS(Engine): PASS
9057 19:54:17.459769 TX OE : PASS
9058 19:54:17.462816 All Pass.
9059 19:54:17.462929
9060 19:54:17.463032 CH 1, Rank 1
9061 19:54:17.466023 SW Impedance : PASS
9062 19:54:17.469645 DUTY Scan : NO K
9063 19:54:17.469742 ZQ Calibration : PASS
9064 19:54:17.472430 Jitter Meter : NO K
9065 19:54:17.472527 CBT Training : PASS
9066 19:54:17.476306 Write leveling : PASS
9067 19:54:17.479431 RX DQS gating : PASS
9068 19:54:17.479527 RX DQ/DQS(RDDQC) : PASS
9069 19:54:17.482982 TX DQ/DQS : PASS
9070 19:54:17.486025 RX DATLAT : PASS
9071 19:54:17.486153 RX DQ/DQS(Engine): PASS
9072 19:54:17.489649 TX OE : PASS
9073 19:54:17.489722 All Pass.
9074 19:54:17.489783
9075 19:54:17.492744 DramC Write-DBI on
9076 19:54:17.495883 PER_BANK_REFRESH: Hybrid Mode
9077 19:54:17.495985 TX_TRACKING: ON
9078 19:54:17.506069 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9079 19:54:17.512941 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9080 19:54:17.519347 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9081 19:54:17.522924 [FAST_K] Save calibration result to emmc
9082 19:54:17.526117 sync common calibartion params.
9083 19:54:17.529770 sync cbt_mode0:1, 1:1
9084 19:54:17.532765 dram_init: ddr_geometry: 2
9085 19:54:17.532840 dram_init: ddr_geometry: 2
9086 19:54:17.536336 dram_init: ddr_geometry: 2
9087 19:54:17.539453 0:dram_rank_size:100000000
9088 19:54:17.542455 1:dram_rank_size:100000000
9089 19:54:17.546244 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9090 19:54:17.549308 DFS_SHUFFLE_HW_MODE: ON
9091 19:54:17.552858 dramc_set_vcore_voltage set vcore to 725000
9092 19:54:17.556010 Read voltage for 1600, 0
9093 19:54:17.556094 Vio18 = 0
9094 19:54:17.556159 Vcore = 725000
9095 19:54:17.559167 Vdram = 0
9096 19:54:17.559245 Vddq = 0
9097 19:54:17.559338 Vmddr = 0
9098 19:54:17.562929 switch to 3200 Mbps bootup
9099 19:54:17.563033 [DramcRunTimeConfig]
9100 19:54:17.566071 PHYPLL
9101 19:54:17.566173 DPM_CONTROL_AFTERK: ON
9102 19:54:17.569236 PER_BANK_REFRESH: ON
9103 19:54:17.573021 REFRESH_OVERHEAD_REDUCTION: ON
9104 19:54:17.573096 CMD_PICG_NEW_MODE: OFF
9105 19:54:17.576187 XRTWTW_NEW_MODE: ON
9106 19:54:17.576258 XRTRTR_NEW_MODE: ON
9107 19:54:17.579279 TX_TRACKING: ON
9108 19:54:17.579380 RDSEL_TRACKING: OFF
9109 19:54:17.582355 DQS Precalculation for DVFS: ON
9110 19:54:17.586276 RX_TRACKING: OFF
9111 19:54:17.586379 HW_GATING DBG: ON
9112 19:54:17.589487 ZQCS_ENABLE_LP4: ON
9113 19:54:17.589568 RX_PICG_NEW_MODE: ON
9114 19:54:17.592998 TX_PICG_NEW_MODE: ON
9115 19:54:17.596198 ENABLE_RX_DCM_DPHY: ON
9116 19:54:17.596301 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9117 19:54:17.599071 DUMMY_READ_FOR_TRACKING: OFF
9118 19:54:17.602603 !!! SPM_CONTROL_AFTERK: OFF
9119 19:54:17.606191 !!! SPM could not control APHY
9120 19:54:17.606270 IMPEDANCE_TRACKING: ON
9121 19:54:17.609266 TEMP_SENSOR: ON
9122 19:54:17.609368 HW_SAVE_FOR_SR: OFF
9123 19:54:17.612409 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9124 19:54:17.616206 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9125 19:54:17.619268 Read ODT Tracking: ON
9126 19:54:17.622336 Refresh Rate DeBounce: ON
9127 19:54:17.622441 DFS_NO_QUEUE_FLUSH: ON
9128 19:54:17.625905 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9129 19:54:17.628884 ENABLE_DFS_RUNTIME_MRW: OFF
9130 19:54:17.632510 DDR_RESERVE_NEW_MODE: ON
9131 19:54:17.632584 MR_CBT_SWITCH_FREQ: ON
9132 19:54:17.635756 =========================
9133 19:54:17.655093 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9134 19:54:17.658328 dram_init: ddr_geometry: 2
9135 19:54:17.676505 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9136 19:54:17.679743 dram_init: dram init end (result: 0)
9137 19:54:17.686195 DRAM-K: Full calibration passed in 24455 msecs
9138 19:54:17.689848 MRC: failed to locate region type 0.
9139 19:54:17.689928 DRAM rank0 size:0x100000000,
9140 19:54:17.692919 DRAM rank1 size=0x100000000
9141 19:54:17.702940 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9142 19:54:17.709480 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9143 19:54:17.716170 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9144 19:54:17.722764 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9145 19:54:17.725924 DRAM rank0 size:0x100000000,
9146 19:54:17.729620 DRAM rank1 size=0x100000000
9147 19:54:17.729711 CBMEM:
9148 19:54:17.732772 IMD: root @ 0xfffff000 254 entries.
9149 19:54:17.735881 IMD: root @ 0xffffec00 62 entries.
9150 19:54:17.739452 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9151 19:54:17.742972 WARNING: RO_VPD is uninitialized or empty.
9152 19:54:17.749048 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9153 19:54:17.756625 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9154 19:54:17.769299 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9155 19:54:17.780864 BS: romstage times (exec / console): total (unknown) / 23987 ms
9156 19:54:17.780969
9157 19:54:17.781066
9158 19:54:17.791012 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9159 19:54:17.794097 ARM64: Exception handlers installed.
9160 19:54:17.797108 ARM64: Testing exception
9161 19:54:17.800244 ARM64: Done test exception
9162 19:54:17.800349 Enumerating buses...
9163 19:54:17.804069 Show all devs... Before device enumeration.
9164 19:54:17.807233 Root Device: enabled 1
9165 19:54:17.810663 CPU_CLUSTER: 0: enabled 1
9166 19:54:17.810737 CPU: 00: enabled 1
9167 19:54:17.813569 Compare with tree...
9168 19:54:17.813641 Root Device: enabled 1
9169 19:54:17.817092 CPU_CLUSTER: 0: enabled 1
9170 19:54:17.820292 CPU: 00: enabled 1
9171 19:54:17.820383 Root Device scanning...
9172 19:54:17.823922 scan_static_bus for Root Device
9173 19:54:17.827281 CPU_CLUSTER: 0 enabled
9174 19:54:17.830186 scan_static_bus for Root Device done
9175 19:54:17.833742 scan_bus: bus Root Device finished in 8 msecs
9176 19:54:17.833837 done
9177 19:54:17.840285 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9178 19:54:17.843441 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9179 19:54:17.850233 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9180 19:54:17.853620 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9181 19:54:17.856805 Allocating resources...
9182 19:54:17.860219 Reading resources...
9183 19:54:17.863861 Root Device read_resources bus 0 link: 0
9184 19:54:17.863938 DRAM rank0 size:0x100000000,
9185 19:54:17.866890 DRAM rank1 size=0x100000000
9186 19:54:17.870028 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9187 19:54:17.873826 CPU: 00 missing read_resources
9188 19:54:17.877009 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9189 19:54:17.883307 Root Device read_resources bus 0 link: 0 done
9190 19:54:17.883413 Done reading resources.
9191 19:54:17.890445 Show resources in subtree (Root Device)...After reading.
9192 19:54:17.893615 Root Device child on link 0 CPU_CLUSTER: 0
9193 19:54:17.896770 CPU_CLUSTER: 0 child on link 0 CPU: 00
9194 19:54:17.906865 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9195 19:54:17.906973 CPU: 00
9196 19:54:17.910060 Root Device assign_resources, bus 0 link: 0
9197 19:54:17.913273 CPU_CLUSTER: 0 missing set_resources
9198 19:54:17.920029 Root Device assign_resources, bus 0 link: 0 done
9199 19:54:17.920133 Done setting resources.
9200 19:54:17.926846 Show resources in subtree (Root Device)...After assigning values.
9201 19:54:17.929686 Root Device child on link 0 CPU_CLUSTER: 0
9202 19:54:17.933141 CPU_CLUSTER: 0 child on link 0 CPU: 00
9203 19:54:17.943497 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9204 19:54:17.943603 CPU: 00
9205 19:54:17.946602 Done allocating resources.
9206 19:54:17.950187 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9207 19:54:17.952994 Enabling resources...
9208 19:54:17.953093 done.
9209 19:54:17.959947 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9210 19:54:17.960040 Initializing devices...
9211 19:54:17.963374 Root Device init
9212 19:54:17.963478 init hardware done!
9213 19:54:17.966250 0x00000018: ctrlr->caps
9214 19:54:17.969641 52.000 MHz: ctrlr->f_max
9215 19:54:17.969762 0.400 MHz: ctrlr->f_min
9216 19:54:17.973034 0x40ff8080: ctrlr->voltages
9217 19:54:17.973219 sclk: 390625
9218 19:54:17.976244 Bus Width = 1
9219 19:54:17.976323 sclk: 390625
9220 19:54:17.979426 Bus Width = 1
9221 19:54:17.979529 Early init status = 3
9222 19:54:17.986375 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9223 19:54:17.990052 in-header: 03 fc 00 00 01 00 00 00
9224 19:54:17.992908 in-data: 00
9225 19:54:17.996331 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9226 19:54:18.001576 in-header: 03 fd 00 00 00 00 00 00
9227 19:54:18.004602 in-data:
9228 19:54:18.008300 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9229 19:54:18.012184 in-header: 03 fc 00 00 01 00 00 00
9230 19:54:18.015982 in-data: 00
9231 19:54:18.019223 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9232 19:54:18.024564 in-header: 03 fd 00 00 00 00 00 00
9233 19:54:18.027717 in-data:
9234 19:54:18.031675 [SSUSB] Setting up USB HOST controller...
9235 19:54:18.034678 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9236 19:54:18.037752 [SSUSB] phy power-on done.
9237 19:54:18.041256 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9238 19:54:18.048025 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9239 19:54:18.051074 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9240 19:54:18.057870 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9241 19:54:18.064792 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9242 19:54:18.071540 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9243 19:54:18.078037 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9244 19:54:18.084554 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9245 19:54:18.088246 SPM: binary array size = 0x9dc
9246 19:54:18.091516 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9247 19:54:18.097796 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9248 19:54:18.104524 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9249 19:54:18.107885 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9250 19:54:18.114052 configure_display: Starting display init
9251 19:54:18.147939 anx7625_power_on_init: Init interface.
9252 19:54:18.151240 anx7625_disable_pd_protocol: Disabled PD feature.
9253 19:54:18.154254 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9254 19:54:18.182532 anx7625_start_dp_work: Secure OCM version=00
9255 19:54:18.185570 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9256 19:54:18.200350 sp_tx_get_edid_block: EDID Block = 1
9257 19:54:18.303021 Extracted contents:
9258 19:54:18.306247 header: 00 ff ff ff ff ff ff 00
9259 19:54:18.309449 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9260 19:54:18.313018 version: 01 04
9261 19:54:18.316222 basic params: 95 1f 11 78 0a
9262 19:54:18.319408 chroma info: 76 90 94 55 54 90 27 21 50 54
9263 19:54:18.322552 established: 00 00 00
9264 19:54:18.329450 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9265 19:54:18.333074 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9266 19:54:18.339516 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9267 19:54:18.346014 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9268 19:54:18.352433 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9269 19:54:18.356199 extensions: 00
9270 19:54:18.356306 checksum: fb
9271 19:54:18.356412
9272 19:54:18.359425 Manufacturer: IVO Model 57d Serial Number 0
9273 19:54:18.362552 Made week 0 of 2020
9274 19:54:18.362672 EDID version: 1.4
9275 19:54:18.365704 Digital display
9276 19:54:18.368965 6 bits per primary color channel
9277 19:54:18.369043 DisplayPort interface
9278 19:54:18.372351 Maximum image size: 31 cm x 17 cm
9279 19:54:18.375773 Gamma: 220%
9280 19:54:18.375860 Check DPMS levels
9281 19:54:18.378923 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9282 19:54:18.385773 First detailed timing is preferred timing
9283 19:54:18.385876 Established timings supported:
9284 19:54:18.388880 Standard timings supported:
9285 19:54:18.392534 Detailed timings
9286 19:54:18.395438 Hex of detail: 383680a07038204018303c0035ae10000019
9287 19:54:18.399161 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9288 19:54:18.405569 0780 0798 07c8 0820 hborder 0
9289 19:54:18.408833 0438 043b 0447 0458 vborder 0
9290 19:54:18.412450 -hsync -vsync
9291 19:54:18.412528 Did detailed timing
9292 19:54:18.419194 Hex of detail: 000000000000000000000000000000000000
9293 19:54:18.419272 Manufacturer-specified data, tag 0
9294 19:54:18.425772 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9295 19:54:18.428867 ASCII string: InfoVision
9296 19:54:18.432003 Hex of detail: 000000fe00523134304e574635205248200a
9297 19:54:18.435858 ASCII string: R140NWF5 RH
9298 19:54:18.435940 Checksum
9299 19:54:18.439025 Checksum: 0xfb (valid)
9300 19:54:18.442067 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9301 19:54:18.445688 DSI data_rate: 832800000 bps
9302 19:54:18.452000 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9303 19:54:18.455303 anx7625_parse_edid: pixelclock(138800).
9304 19:54:18.458750 hactive(1920), hsync(48), hfp(24), hbp(88)
9305 19:54:18.462231 vactive(1080), vsync(12), vfp(3), vbp(17)
9306 19:54:18.465412 anx7625_dsi_config: config dsi.
9307 19:54:18.472252 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9308 19:54:18.485170 anx7625_dsi_config: success to config DSI
9309 19:54:18.488188 anx7625_dp_start: MIPI phy setup OK.
9310 19:54:18.491801 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9311 19:54:18.495049 mtk_ddp_mode_set invalid vrefresh 60
9312 19:54:18.498009 main_disp_path_setup
9313 19:54:18.498086 ovl_layer_smi_id_en
9314 19:54:18.501661 ovl_layer_smi_id_en
9315 19:54:18.501738 ccorr_config
9316 19:54:18.501802 aal_config
9317 19:54:18.504619 gamma_config
9318 19:54:18.504698 postmask_config
9319 19:54:18.507752 dither_config
9320 19:54:18.511528 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9321 19:54:18.517976 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9322 19:54:18.521102 Root Device init finished in 555 msecs
9323 19:54:18.524927 CPU_CLUSTER: 0 init
9324 19:54:18.531203 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9325 19:54:18.534344 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9326 19:54:18.537984 APU_MBOX 0x190000b0 = 0x10001
9327 19:54:18.541167 APU_MBOX 0x190001b0 = 0x10001
9328 19:54:18.544310 APU_MBOX 0x190005b0 = 0x10001
9329 19:54:18.547897 APU_MBOX 0x190006b0 = 0x10001
9330 19:54:18.551027 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9331 19:54:18.564199 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9332 19:54:18.576637 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9333 19:54:18.583209 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9334 19:54:18.594438 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9335 19:54:18.603885 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9336 19:54:18.607026 CPU_CLUSTER: 0 init finished in 81 msecs
9337 19:54:18.610631 Devices initialized
9338 19:54:18.613720 Show all devs... After init.
9339 19:54:18.613826 Root Device: enabled 1
9340 19:54:18.616870 CPU_CLUSTER: 0: enabled 1
9341 19:54:18.620715 CPU: 00: enabled 1
9342 19:54:18.623842 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9343 19:54:18.626965 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9344 19:54:18.630197 ELOG: NV offset 0x57f000 size 0x1000
9345 19:54:18.637201 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9346 19:54:18.643519 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9347 19:54:18.646668 ELOG: Event(17) added with size 13 at 2023-10-28 19:52:43 UTC
9348 19:54:18.650237 out: cmd=0x121: 03 db 21 01 00 00 00 00
9349 19:54:18.653929 in-header: 03 df 00 00 2c 00 00 00
9350 19:54:18.667609 in-data: 80 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9351 19:54:18.674198 ELOG: Event(A1) added with size 10 at 2023-10-28 19:52:43 UTC
9352 19:54:18.680737 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9353 19:54:18.687315 ELOG: Event(A0) added with size 9 at 2023-10-28 19:52:43 UTC
9354 19:54:18.690384 elog_add_boot_reason: Logged dev mode boot
9355 19:54:18.694262 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9356 19:54:18.697363 Finalize devices...
9357 19:54:18.697465 Devices finalized
9358 19:54:18.703825 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9359 19:54:18.707252 Writing coreboot table at 0xffe64000
9360 19:54:18.710394 0. 000000000010a000-0000000000113fff: RAMSTAGE
9361 19:54:18.713685 1. 0000000040000000-00000000400fffff: RAM
9362 19:54:18.720530 2. 0000000040100000-000000004032afff: RAMSTAGE
9363 19:54:18.723663 3. 000000004032b000-00000000545fffff: RAM
9364 19:54:18.726743 4. 0000000054600000-000000005465ffff: BL31
9365 19:54:18.729946 5. 0000000054660000-00000000ffe63fff: RAM
9366 19:54:18.736858 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9367 19:54:18.740006 7. 0000000100000000-000000023fffffff: RAM
9368 19:54:18.740080 Passing 5 GPIOs to payload:
9369 19:54:18.747046 NAME | PORT | POLARITY | VALUE
9370 19:54:18.750228 EC in RW | 0x000000aa | low | undefined
9371 19:54:18.756810 EC interrupt | 0x00000005 | low | undefined
9372 19:54:18.760468 TPM interrupt | 0x000000ab | high | undefined
9373 19:54:18.763572 SD card detect | 0x00000011 | high | undefined
9374 19:54:18.770388 speaker enable | 0x00000093 | high | undefined
9375 19:54:18.773409 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9376 19:54:18.777132 in-header: 03 f9 00 00 02 00 00 00
9377 19:54:18.777232 in-data: 02 00
9378 19:54:18.780131 ADC[4]: Raw value=905096 ID=7
9379 19:54:18.783605 ADC[3]: Raw value=213441 ID=1
9380 19:54:18.783731 RAM Code: 0x71
9381 19:54:18.787082 ADC[6]: Raw value=75701 ID=0
9382 19:54:18.790544 ADC[5]: Raw value=212333 ID=1
9383 19:54:18.790642 SKU Code: 0x1
9384 19:54:18.797044 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7
9385 19:54:18.800392 coreboot table: 964 bytes.
9386 19:54:18.803477 IMD ROOT 0. 0xfffff000 0x00001000
9387 19:54:18.806644 IMD SMALL 1. 0xffffe000 0x00001000
9388 19:54:18.809822 RO MCACHE 2. 0xffffc000 0x00001104
9389 19:54:18.813542 CONSOLE 3. 0xfff7c000 0x00080000
9390 19:54:18.816644 FMAP 4. 0xfff7b000 0x00000452
9391 19:54:18.820115 TIME STAMP 5. 0xfff7a000 0x00000910
9392 19:54:18.823390 VBOOT WORK 6. 0xfff66000 0x00014000
9393 19:54:18.826526 RAMOOPS 7. 0xffe66000 0x00100000
9394 19:54:18.829699 COREBOOT 8. 0xffe64000 0x00002000
9395 19:54:18.829821 IMD small region:
9396 19:54:18.833003 IMD ROOT 0. 0xffffec00 0x00000400
9397 19:54:18.836345 VPD 1. 0xffffeb80 0x0000006c
9398 19:54:18.840038 MMC STATUS 2. 0xffffeb60 0x00000004
9399 19:54:18.846248 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9400 19:54:18.850135 Probing TPM: done!
9401 19:54:18.853286 Connected to device vid:did:rid of 1ae0:0028:00
9402 19:54:18.863562 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9403 19:54:18.866414 Initialized TPM device CR50 revision 0
9404 19:54:18.870727 Checking cr50 for pending updates
9405 19:54:18.874338 Reading cr50 TPM mode
9406 19:54:18.882432 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9407 19:54:18.889227 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9408 19:54:18.929066 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9409 19:54:18.932848 Checking segment from ROM address 0x40100000
9410 19:54:18.935932 Checking segment from ROM address 0x4010001c
9411 19:54:18.942735 Loading segment from ROM address 0x40100000
9412 19:54:18.942840 code (compression=0)
9413 19:54:18.949482 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9414 19:54:18.959467 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9415 19:54:18.959579 it's not compressed!
9416 19:54:18.965829 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9417 19:54:18.969628 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9418 19:54:18.989694 Loading segment from ROM address 0x4010001c
9419 19:54:18.989786 Entry Point 0x80000000
9420 19:54:18.992736 Loaded segments
9421 19:54:18.996347 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9422 19:54:19.003129 Jumping to boot code at 0x80000000(0xffe64000)
9423 19:54:19.009155 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9424 19:54:19.015856 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9425 19:54:19.024071 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9426 19:54:19.027215 Checking segment from ROM address 0x40100000
9427 19:54:19.031006 Checking segment from ROM address 0x4010001c
9428 19:54:19.037770 Loading segment from ROM address 0x40100000
9429 19:54:19.037883 code (compression=1)
9430 19:54:19.044148 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9431 19:54:19.054264 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9432 19:54:19.054372 using LZMA
9433 19:54:19.062673 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9434 19:54:19.069082 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9435 19:54:19.072816 Loading segment from ROM address 0x4010001c
9436 19:54:19.072890 Entry Point 0x54601000
9437 19:54:19.075999 Loaded segments
9438 19:54:19.079190 NOTICE: MT8192 bl31_setup
9439 19:54:19.086223 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9440 19:54:19.089367 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9441 19:54:19.092472 WARNING: region 0:
9442 19:54:19.095974 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9443 19:54:19.096074 WARNING: region 1:
9444 19:54:19.102396 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9445 19:54:19.105699 WARNING: region 2:
9446 19:54:19.109438 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9447 19:54:19.112665 WARNING: region 3:
9448 19:54:19.116298 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9449 19:54:19.119591 WARNING: region 4:
9450 19:54:19.122544 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9451 19:54:19.126309 WARNING: region 5:
9452 19:54:19.129446 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 19:54:19.132807 WARNING: region 6:
9454 19:54:19.135943 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 19:54:19.136025 WARNING: region 7:
9456 19:54:19.142697 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 19:54:19.149684 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9458 19:54:19.152631 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9459 19:54:19.155870 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9460 19:54:19.162573 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9461 19:54:19.166170 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9462 19:54:19.169800 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9463 19:54:19.176257 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9464 19:54:19.179461 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9465 19:54:19.182600 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9466 19:54:19.189617 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9467 19:54:19.192735 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9468 19:54:19.196458 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9469 19:54:19.203215 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9470 19:54:19.206388 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9471 19:54:19.213371 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9472 19:54:19.216392 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9473 19:54:19.219701 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9474 19:54:19.226269 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9475 19:54:19.230041 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9476 19:54:19.233161 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9477 19:54:19.240128 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9478 19:54:19.243398 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9479 19:54:19.249916 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9480 19:54:19.253139 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9481 19:54:19.256757 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9482 19:54:19.263133 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9483 19:54:19.266743 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9484 19:54:19.273312 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9485 19:54:19.276809 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9486 19:54:19.279916 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9487 19:54:19.286250 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9488 19:54:19.290054 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9489 19:54:19.293146 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9490 19:54:19.299947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9491 19:54:19.303516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9492 19:54:19.306701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9493 19:54:19.309937 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9494 19:54:19.316405 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9495 19:54:19.319765 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9496 19:54:19.323407 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9497 19:54:19.326518 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9498 19:54:19.330003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9499 19:54:19.336629 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9500 19:54:19.340052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9501 19:54:19.343139 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9502 19:54:19.350068 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9503 19:54:19.353157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9504 19:54:19.356772 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9505 19:54:19.363684 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9506 19:54:19.366209 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9507 19:54:19.370034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9508 19:54:19.376321 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9509 19:54:19.379923 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9510 19:54:19.386523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9511 19:54:19.390313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9512 19:54:19.393521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9513 19:54:19.399897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9514 19:54:19.403038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9515 19:54:19.409763 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9516 19:54:19.413032 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9517 19:54:19.419881 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9518 19:54:19.423519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9519 19:54:19.429828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9520 19:54:19.433068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9521 19:54:19.436837 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9522 19:54:19.443542 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9523 19:54:19.446636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9524 19:54:19.453501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9525 19:54:19.456778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9526 19:54:19.463471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9527 19:54:19.466675 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9528 19:54:19.469831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9529 19:54:19.477030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9530 19:54:19.479938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9531 19:54:19.486841 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9532 19:54:19.490048 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9533 19:54:19.497066 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9534 19:54:19.500141 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9535 19:54:19.503648 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9536 19:54:19.510094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9537 19:54:19.513748 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9538 19:54:19.519879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9539 19:54:19.523530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9540 19:54:19.530364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9541 19:54:19.533525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9542 19:54:19.536654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9543 19:54:19.543427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9544 19:54:19.547200 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9545 19:54:19.553353 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9546 19:54:19.557180 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9547 19:54:19.563789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9548 19:54:19.567115 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9549 19:54:19.570024 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9550 19:54:19.576856 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9551 19:54:19.579920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9552 19:54:19.586785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9553 19:54:19.590505 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9554 19:54:19.593774 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9555 19:54:19.596821 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9556 19:54:19.603465 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9557 19:54:19.606847 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9558 19:54:19.610509 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9559 19:54:19.617092 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9560 19:54:19.620860 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9561 19:54:19.627203 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9562 19:54:19.630802 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9563 19:54:19.633857 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9564 19:54:19.640774 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9565 19:54:19.644040 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9566 19:54:19.650751 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9567 19:54:19.653945 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9568 19:54:19.657087 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9569 19:54:19.664027 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9570 19:54:19.667063 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9571 19:54:19.674109 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9572 19:54:19.677064 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9573 19:54:19.680417 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9574 19:54:19.683702 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9575 19:54:19.690416 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9576 19:54:19.693811 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9577 19:54:19.697229 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9578 19:54:19.700390 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9579 19:54:19.707246 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9580 19:54:19.710402 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9581 19:54:19.713645 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9582 19:54:19.720419 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9583 19:54:19.723936 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9584 19:54:19.726994 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9585 19:54:19.734034 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9586 19:54:19.737628 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9587 19:54:19.743786 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9588 19:54:19.747030 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9589 19:54:19.750766 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9590 19:54:19.757511 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9591 19:54:19.760509 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9592 19:54:19.767521 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9593 19:54:19.770791 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9594 19:54:19.774016 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9595 19:54:19.780896 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9596 19:54:19.784011 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9597 19:54:19.787247 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9598 19:54:19.793906 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9599 19:54:19.797442 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9600 19:54:19.804042 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9601 19:54:19.807205 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9602 19:54:19.810651 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9603 19:54:19.817687 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9604 19:54:19.820998 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9605 19:54:19.824043 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9606 19:54:19.830611 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9607 19:54:19.833841 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9608 19:54:19.840880 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9609 19:54:19.843934 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9610 19:54:19.847597 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9611 19:54:19.854017 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9612 19:54:19.857824 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9613 19:54:19.864183 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9614 19:54:19.867446 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9615 19:54:19.870858 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9616 19:54:19.877701 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9617 19:54:19.880876 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9618 19:54:19.884041 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9619 19:54:19.890972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9620 19:54:19.893925 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9621 19:54:19.900249 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9622 19:54:19.904051 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9623 19:54:19.907229 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9624 19:54:19.914057 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9625 19:54:19.917026 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9626 19:54:19.923477 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9627 19:54:19.927124 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9628 19:54:19.933289 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9629 19:54:19.936674 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9630 19:54:19.939857 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9631 19:54:19.946702 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9632 19:54:19.949897 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9633 19:54:19.953606 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9634 19:54:19.960052 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9635 19:54:19.963263 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9636 19:54:19.969694 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9637 19:54:19.973251 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9638 19:54:19.976193 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9639 19:54:19.982788 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9640 19:54:19.986349 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9641 19:54:19.992775 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9642 19:54:19.996271 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9643 19:54:19.999731 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9644 19:54:20.005982 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9645 19:54:20.009662 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9646 19:54:20.016092 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9647 19:54:20.019360 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9648 19:54:20.025602 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9649 19:54:20.029350 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9650 19:54:20.032340 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9651 19:54:20.039402 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9652 19:54:20.042358 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9653 19:54:20.049321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9654 19:54:20.052391 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9655 19:54:20.059383 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9656 19:54:20.062567 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9657 19:54:20.065763 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9658 19:54:20.072512 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9659 19:54:20.075668 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9660 19:54:20.082129 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9661 19:54:20.085717 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9662 19:54:20.088756 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9663 19:54:20.095520 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9664 19:54:20.098668 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9665 19:54:20.105625 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9666 19:54:20.109099 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9667 19:54:20.112604 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9668 19:54:20.118838 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9669 19:54:20.122048 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9670 19:54:20.128968 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9671 19:54:20.132284 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9672 19:54:20.138907 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9673 19:54:20.141919 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9674 19:54:20.145612 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9675 19:54:20.152011 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9676 19:54:20.154968 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9677 19:54:20.161626 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9678 19:54:20.165166 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9679 19:54:20.171804 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9680 19:54:20.174881 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9681 19:54:20.178661 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9682 19:54:20.185019 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9683 19:54:20.188061 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9684 19:54:20.194954 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9685 19:54:20.198559 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9686 19:54:20.201492 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9687 19:54:20.205305 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9688 19:54:20.211579 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9689 19:54:20.214856 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9690 19:54:20.218080 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9691 19:54:20.221978 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9692 19:54:20.228002 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9693 19:54:20.231572 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9694 19:54:20.238280 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9695 19:54:20.241548 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9696 19:54:20.245171 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9697 19:54:20.251459 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9698 19:54:20.255119 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9699 19:54:20.258510 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9700 19:54:20.264791 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9701 19:54:20.268437 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9702 19:54:20.274797 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9703 19:54:20.278473 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9704 19:54:20.281831 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9705 19:54:20.288199 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9706 19:54:20.291317 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9707 19:54:20.294558 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9708 19:54:20.301455 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9709 19:54:20.304601 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9710 19:54:20.308197 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9711 19:54:20.314782 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9712 19:54:20.317887 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9713 19:54:20.324852 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9714 19:54:20.327918 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9715 19:54:20.331031 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9716 19:54:20.337730 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9717 19:54:20.340967 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9718 19:54:20.344746 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9719 19:54:20.350979 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9720 19:54:20.354609 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9721 19:54:20.357842 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9722 19:54:20.364983 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9723 19:54:20.367535 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9724 19:54:20.374509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9725 19:54:20.377470 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9726 19:54:20.381198 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9727 19:54:20.384613 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9728 19:54:20.390868 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9729 19:54:20.394095 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9730 19:54:20.397201 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9731 19:54:20.401205 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9732 19:54:20.407546 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9733 19:54:20.410798 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9734 19:54:20.413909 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9735 19:54:20.417517 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9736 19:54:20.424191 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9737 19:54:20.427351 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9738 19:54:20.430556 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9739 19:54:20.437407 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9740 19:54:20.440496 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9741 19:54:20.443664 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9742 19:54:20.450569 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9743 19:54:20.453761 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9744 19:54:20.460143 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9745 19:54:20.463893 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9746 19:54:20.467076 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9747 19:54:20.473891 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9748 19:54:20.476868 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9749 19:54:20.483607 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9750 19:54:20.486846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9751 19:54:20.490728 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9752 19:54:20.497191 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9753 19:54:20.500401 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9754 19:54:20.507098 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9755 19:54:20.510227 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9756 19:54:20.516946 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9757 19:54:20.519953 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9758 19:54:20.523714 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9759 19:54:20.530423 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9760 19:54:20.533542 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9761 19:54:20.539999 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9762 19:54:20.543517 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9763 19:54:20.546669 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9764 19:54:20.553038 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9765 19:54:20.556233 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9766 19:54:20.563147 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9767 19:54:20.566288 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9768 19:54:20.573379 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9769 19:54:20.576533 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9770 19:54:20.579659 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9771 19:54:20.586658 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9772 19:54:20.589855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9773 19:54:20.596687 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9774 19:54:20.599937 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9775 19:54:20.602861 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9776 19:54:20.609579 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9777 19:54:20.612813 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9778 19:54:20.619439 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9779 19:54:20.622705 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9780 19:54:20.626145 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9781 19:54:20.632569 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9782 19:54:20.636274 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9783 19:54:20.642941 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9784 19:54:20.646408 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9785 19:54:20.652890 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9786 19:54:20.655963 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9787 19:54:20.659231 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9788 19:54:20.666109 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9789 19:54:20.669260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9790 19:54:20.676083 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9791 19:54:20.679199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9792 19:54:20.682308 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9793 19:54:20.689252 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9794 19:54:20.692322 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9795 19:54:20.699185 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9796 19:54:20.702421 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9797 19:54:20.705754 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9798 19:54:20.712527 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9799 19:54:20.715521 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9800 19:54:20.722519 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9801 19:54:20.726011 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9802 19:54:20.729037 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9803 19:54:20.735925 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9804 19:54:20.739007 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9805 19:54:20.745552 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9806 19:54:20.749122 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9807 19:54:20.755602 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9808 19:54:20.758531 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9809 19:54:20.762176 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9810 19:54:20.768704 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9811 19:54:20.772324 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9812 19:54:20.778727 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9813 19:54:20.782303 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9814 19:54:20.785474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9815 19:54:20.791765 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9816 19:54:20.795568 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9817 19:54:20.801733 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9818 19:54:20.805397 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9819 19:54:20.811678 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9820 19:54:20.815478 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9821 19:54:20.818594 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9822 19:54:20.825260 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9823 19:54:20.828304 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9824 19:54:20.835028 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9825 19:54:20.838524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9826 19:54:20.845409 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9827 19:54:20.848590 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9828 19:54:20.851763 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9829 19:54:20.858644 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9830 19:54:20.861627 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9831 19:54:20.868329 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9832 19:54:20.871718 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9833 19:54:20.878504 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9834 19:54:20.881580 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9835 19:54:20.888074 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9836 19:54:20.891486 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9837 19:54:20.895007 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9838 19:54:20.901435 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9839 19:54:20.904802 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9840 19:54:20.911428 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9841 19:54:20.915167 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9842 19:54:20.921458 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9843 19:54:20.924694 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9844 19:54:20.928479 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9845 19:54:20.934762 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9846 19:54:20.937802 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9847 19:54:20.944520 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9848 19:54:20.948010 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9849 19:54:20.954658 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9850 19:54:20.957783 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9851 19:54:20.961592 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9852 19:54:20.967910 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9853 19:54:20.971187 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9854 19:54:20.978033 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9855 19:54:20.981278 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9856 19:54:20.988097 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9857 19:54:20.991312 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9858 19:54:20.994470 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9859 19:54:21.001279 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9860 19:54:21.004322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9861 19:54:21.011175 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9862 19:54:21.014864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9863 19:54:21.020980 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9864 19:54:21.024361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9865 19:54:21.031003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9866 19:54:21.034908 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9867 19:54:21.041283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9868 19:54:21.044406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9869 19:54:21.050959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9870 19:54:21.054558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9871 19:54:21.057811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9872 19:54:21.064746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9873 19:54:21.067909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9874 19:54:21.074300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9875 19:54:21.077521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9876 19:54:21.084266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9877 19:54:21.087713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9878 19:54:21.094343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9879 19:54:21.097663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9880 19:54:21.104307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9881 19:54:21.107395 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9882 19:54:21.114310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9883 19:54:21.117551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9884 19:54:21.124093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9885 19:54:21.127424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9886 19:54:21.134201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9887 19:54:21.137477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9888 19:54:21.144172 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9889 19:54:21.147307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9890 19:54:21.154067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9891 19:54:21.157190 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9892 19:54:21.160835 INFO: [APUAPC] vio 0
9893 19:54:21.163845 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9894 19:54:21.170535 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9895 19:54:21.174321 INFO: [APUAPC] D0_APC_0: 0x400510
9896 19:54:21.174404 INFO: [APUAPC] D0_APC_1: 0x0
9897 19:54:21.177417 INFO: [APUAPC] D0_APC_2: 0x1540
9898 19:54:21.180590 INFO: [APUAPC] D0_APC_3: 0x0
9899 19:54:21.183763 INFO: [APUAPC] D1_APC_0: 0xffffffff
9900 19:54:21.187566 INFO: [APUAPC] D1_APC_1: 0xffffffff
9901 19:54:21.190838 INFO: [APUAPC] D1_APC_2: 0x3fffff
9902 19:54:21.194111 INFO: [APUAPC] D1_APC_3: 0x0
9903 19:54:21.197610 INFO: [APUAPC] D2_APC_0: 0xffffffff
9904 19:54:21.200443 INFO: [APUAPC] D2_APC_1: 0xffffffff
9905 19:54:21.203847 INFO: [APUAPC] D2_APC_2: 0x3fffff
9906 19:54:21.207043 INFO: [APUAPC] D2_APC_3: 0x0
9907 19:54:21.210793 INFO: [APUAPC] D3_APC_0: 0xffffffff
9908 19:54:21.213975 INFO: [APUAPC] D3_APC_1: 0xffffffff
9909 19:54:21.216958 INFO: [APUAPC] D3_APC_2: 0x3fffff
9910 19:54:21.220216 INFO: [APUAPC] D3_APC_3: 0x0
9911 19:54:21.223785 INFO: [APUAPC] D4_APC_0: 0xffffffff
9912 19:54:21.227002 INFO: [APUAPC] D4_APC_1: 0xffffffff
9913 19:54:21.230189 INFO: [APUAPC] D4_APC_2: 0x3fffff
9914 19:54:21.233746 INFO: [APUAPC] D4_APC_3: 0x0
9915 19:54:21.236849 INFO: [APUAPC] D5_APC_0: 0xffffffff
9916 19:54:21.240623 INFO: [APUAPC] D5_APC_1: 0xffffffff
9917 19:54:21.243592 INFO: [APUAPC] D5_APC_2: 0x3fffff
9918 19:54:21.247047 INFO: [APUAPC] D5_APC_3: 0x0
9919 19:54:21.250366 INFO: [APUAPC] D6_APC_0: 0xffffffff
9920 19:54:21.253614 INFO: [APUAPC] D6_APC_1: 0xffffffff
9921 19:54:21.257166 INFO: [APUAPC] D6_APC_2: 0x3fffff
9922 19:54:21.260337 INFO: [APUAPC] D6_APC_3: 0x0
9923 19:54:21.263331 INFO: [APUAPC] D7_APC_0: 0xffffffff
9924 19:54:21.266803 INFO: [APUAPC] D7_APC_1: 0xffffffff
9925 19:54:21.269934 INFO: [APUAPC] D7_APC_2: 0x3fffff
9926 19:54:21.273480 INFO: [APUAPC] D7_APC_3: 0x0
9927 19:54:21.276744 INFO: [APUAPC] D8_APC_0: 0xffffffff
9928 19:54:21.280614 INFO: [APUAPC] D8_APC_1: 0xffffffff
9929 19:54:21.283480 INFO: [APUAPC] D8_APC_2: 0x3fffff
9930 19:54:21.286792 INFO: [APUAPC] D8_APC_3: 0x0
9931 19:54:21.290030 INFO: [APUAPC] D9_APC_0: 0xffffffff
9932 19:54:21.293290 INFO: [APUAPC] D9_APC_1: 0xffffffff
9933 19:54:21.297030 INFO: [APUAPC] D9_APC_2: 0x3fffff
9934 19:54:21.300260 INFO: [APUAPC] D9_APC_3: 0x0
9935 19:54:21.303307 INFO: [APUAPC] D10_APC_0: 0xffffffff
9936 19:54:21.306404 INFO: [APUAPC] D10_APC_1: 0xffffffff
9937 19:54:21.310204 INFO: [APUAPC] D10_APC_2: 0x3fffff
9938 19:54:21.313563 INFO: [APUAPC] D10_APC_3: 0x0
9939 19:54:21.316406 INFO: [APUAPC] D11_APC_0: 0xffffffff
9940 19:54:21.320085 INFO: [APUAPC] D11_APC_1: 0xffffffff
9941 19:54:21.323437 INFO: [APUAPC] D11_APC_2: 0x3fffff
9942 19:54:21.326507 INFO: [APUAPC] D11_APC_3: 0x0
9943 19:54:21.330199 INFO: [APUAPC] D12_APC_0: 0xffffffff
9944 19:54:21.333248 INFO: [APUAPC] D12_APC_1: 0xffffffff
9945 19:54:21.336349 INFO: [APUAPC] D12_APC_2: 0x3fffff
9946 19:54:21.339959 INFO: [APUAPC] D12_APC_3: 0x0
9947 19:54:21.343162 INFO: [APUAPC] D13_APC_0: 0xffffffff
9948 19:54:21.346375 INFO: [APUAPC] D13_APC_1: 0xffffffff
9949 19:54:21.350078 INFO: [APUAPC] D13_APC_2: 0x3fffff
9950 19:54:21.353197 INFO: [APUAPC] D13_APC_3: 0x0
9951 19:54:21.356800 INFO: [APUAPC] D14_APC_0: 0xffffffff
9952 19:54:21.359902 INFO: [APUAPC] D14_APC_1: 0xffffffff
9953 19:54:21.363003 INFO: [APUAPC] D14_APC_2: 0x3fffff
9954 19:54:21.366656 INFO: [APUAPC] D14_APC_3: 0x0
9955 19:54:21.369576 INFO: [APUAPC] D15_APC_0: 0xffffffff
9956 19:54:21.373022 INFO: [APUAPC] D15_APC_1: 0xffffffff
9957 19:54:21.376248 INFO: [APUAPC] D15_APC_2: 0x3fffff
9958 19:54:21.379505 INFO: [APUAPC] D15_APC_3: 0x0
9959 19:54:21.383061 INFO: [APUAPC] APC_CON: 0x4
9960 19:54:21.383147 INFO: [NOCDAPC] D0_APC_0: 0x0
9961 19:54:21.386510 INFO: [NOCDAPC] D0_APC_1: 0x0
9962 19:54:21.389951 INFO: [NOCDAPC] D1_APC_0: 0x0
9963 19:54:21.393305 INFO: [NOCDAPC] D1_APC_1: 0xfff
9964 19:54:21.396391 INFO: [NOCDAPC] D2_APC_0: 0x0
9965 19:54:21.399548 INFO: [NOCDAPC] D2_APC_1: 0xfff
9966 19:54:21.402737 INFO: [NOCDAPC] D3_APC_0: 0x0
9967 19:54:21.406511 INFO: [NOCDAPC] D3_APC_1: 0xfff
9968 19:54:21.409700 INFO: [NOCDAPC] D4_APC_0: 0x0
9969 19:54:21.412780 INFO: [NOCDAPC] D4_APC_1: 0xfff
9970 19:54:21.412852 INFO: [NOCDAPC] D5_APC_0: 0x0
9971 19:54:21.416491 INFO: [NOCDAPC] D5_APC_1: 0xfff
9972 19:54:21.419597 INFO: [NOCDAPC] D6_APC_0: 0x0
9973 19:54:21.422795 INFO: [NOCDAPC] D6_APC_1: 0xfff
9974 19:54:21.425838 INFO: [NOCDAPC] D7_APC_0: 0x0
9975 19:54:21.429566 INFO: [NOCDAPC] D7_APC_1: 0xfff
9976 19:54:21.433145 INFO: [NOCDAPC] D8_APC_0: 0x0
9977 19:54:21.436052 INFO: [NOCDAPC] D8_APC_1: 0xfff
9978 19:54:21.439851 INFO: [NOCDAPC] D9_APC_0: 0x0
9979 19:54:21.442973 INFO: [NOCDAPC] D9_APC_1: 0xfff
9980 19:54:21.446000 INFO: [NOCDAPC] D10_APC_0: 0x0
9981 19:54:21.449432 INFO: [NOCDAPC] D10_APC_1: 0xfff
9982 19:54:21.449506 INFO: [NOCDAPC] D11_APC_0: 0x0
9983 19:54:21.452501 INFO: [NOCDAPC] D11_APC_1: 0xfff
9984 19:54:21.456204 INFO: [NOCDAPC] D12_APC_0: 0x0
9985 19:54:21.459732 INFO: [NOCDAPC] D12_APC_1: 0xfff
9986 19:54:21.462905 INFO: [NOCDAPC] D13_APC_0: 0x0
9987 19:54:21.465983 INFO: [NOCDAPC] D13_APC_1: 0xfff
9988 19:54:21.469209 INFO: [NOCDAPC] D14_APC_0: 0x0
9989 19:54:21.473039 INFO: [NOCDAPC] D14_APC_1: 0xfff
9990 19:54:21.476110 INFO: [NOCDAPC] D15_APC_0: 0x0
9991 19:54:21.479216 INFO: [NOCDAPC] D15_APC_1: 0xfff
9992 19:54:21.482637 INFO: [NOCDAPC] APC_CON: 0x4
9993 19:54:21.486130 INFO: [APUAPC] set_apusys_apc done
9994 19:54:21.489669 INFO: [DEVAPC] devapc_init done
9995 19:54:21.492625 INFO: GICv3 without legacy support detected.
9996 19:54:21.496165 INFO: ARM GICv3 driver initialized in EL3
9997 19:54:21.499837 INFO: Maximum SPI INTID supported: 639
9998 19:54:21.502538 INFO: BL31: Initializing runtime services
9999 19:54:21.509300 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10000 19:54:21.512333 INFO: SPM: enable CPC mode
10001 19:54:21.519299 INFO: mcdi ready for mcusys-off-idle and system suspend
10002 19:54:21.522330 INFO: BL31: Preparing for EL3 exit to normal world
10003 19:54:21.525965 INFO: Entry point address = 0x80000000
10004 19:54:21.529032 INFO: SPSR = 0x8
10005 19:54:21.534046
10006 19:54:21.534119
10007 19:54:21.534189
10008 19:54:21.537246 Starting depthcharge on Spherion...
10009 19:54:21.537319
10010 19:54:21.537379 Wipe memory regions:
10011 19:54:21.537437
10012 19:54:21.538107 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10013 19:54:21.538209 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10014 19:54:21.538297 Setting prompt string to ['asurada:']
10015 19:54:21.538379 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10016 19:54:21.540443 [0x00000040000000, 0x00000054600000)
10017 19:54:21.662898
10018 19:54:21.663032 [0x00000054660000, 0x00000080000000)
10019 19:54:21.923512
10020 19:54:21.923709 [0x000000821a7280, 0x000000ffe64000)
10021 19:54:22.668221
10022 19:54:22.668369 [0x00000100000000, 0x00000240000000)
10023 19:54:24.558083
10024 19:54:24.561154 Initializing XHCI USB controller at 0x11200000.
10025 19:54:25.599322
10026 19:54:25.602445 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10027 19:54:25.602541
10028 19:54:25.602606
10029 19:54:25.602665
10030 19:54:25.602943 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 19:54:25.703245 asurada: tftpboot 192.168.201.1 11899565/tftp-deploy-kk2tey4x/kernel/image.itb 11899565/tftp-deploy-kk2tey4x/kernel/cmdline
10033 19:54:25.703404 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10034 19:54:25.703522 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10035 19:54:25.707843 tftpboot 192.168.201.1 11899565/tftp-deploy-kk2tey4x/kernel/image.ittp-deploy-kk2tey4x/kernel/cmdline
10036 19:54:25.707961
10037 19:54:25.708031 Waiting for link
10038 19:54:25.868404
10039 19:54:25.868540 R8152: Initializing
10040 19:54:25.868610
10041 19:54:25.871471 Version 9 (ocp_data = 6010)
10042 19:54:25.871555
10043 19:54:25.874691 R8152: Done initializing
10044 19:54:25.874773
10045 19:54:25.874838 Adding net device
10046 19:54:27.747815
10047 19:54:27.747999 done.
10048 19:54:27.748075
10049 19:54:27.748138 MAC: 00:e0:4c:78:7a:aa
10050 19:54:27.748212
10051 19:54:27.751099 Sending DHCP discover... done.
10052 19:54:27.751208
10053 19:54:27.754419 Waiting for reply... done.
10054 19:54:27.754531
10055 19:54:27.757602 Sending DHCP request... done.
10056 19:54:27.757709
10057 19:54:27.760859 Waiting for reply... done.
10058 19:54:27.761009
10059 19:54:27.761090 My ip is 192.168.201.12
10060 19:54:27.761160
10061 19:54:27.764161 The DHCP server ip is 192.168.201.1
10062 19:54:27.764239
10063 19:54:27.767594 TFTP server IP predefined by user: 192.168.201.1
10064 19:54:27.767744
10065 19:54:27.774456 Bootfile predefined by user: 11899565/tftp-deploy-kk2tey4x/kernel/image.itb
10066 19:54:27.774570
10067 19:54:27.777171 Sending tftp read request... done.
10068 19:54:27.777282
10069 19:54:27.780863 Waiting for the transfer...
10070 19:54:27.783910
10071 19:54:28.038426 00000000 ################################################################
10072 19:54:28.038565
10073 19:54:28.286333 00080000 ################################################################
10074 19:54:28.286469
10075 19:54:28.534453 00100000 ################################################################
10076 19:54:28.534622
10077 19:54:28.782440 00180000 ################################################################
10078 19:54:28.782619
10079 19:54:29.033132 00200000 ################################################################
10080 19:54:29.033278
10081 19:54:29.285602 00280000 ################################################################
10082 19:54:29.285778
10083 19:54:29.537410 00300000 ################################################################
10084 19:54:29.537558
10085 19:54:29.792388 00380000 ################################################################
10086 19:54:29.792528
10087 19:54:30.067840 00400000 ################################################################
10088 19:54:30.067983
10089 19:54:30.320717 00480000 ################################################################
10090 19:54:30.320916
10091 19:54:30.577062 00500000 ################################################################
10092 19:54:30.577212
10093 19:54:30.832692 00580000 ################################################################
10094 19:54:30.832840
10095 19:54:31.093318 00600000 ################################################################
10096 19:54:31.093466
10097 19:54:31.351889 00680000 ################################################################
10098 19:54:31.352033
10099 19:54:31.604251 00700000 ################################################################
10100 19:54:31.604413
10101 19:54:31.869021 00780000 ################################################################
10102 19:54:31.869156
10103 19:54:32.122439 00800000 ################################################################
10104 19:54:32.122577
10105 19:54:32.374198 00880000 ################################################################
10106 19:54:32.374333
10107 19:54:32.652424 00900000 ################################################################
10108 19:54:32.652561
10109 19:54:32.915393 00980000 ################################################################
10110 19:54:32.915542
10111 19:54:33.178326 00a00000 ################################################################
10112 19:54:33.178467
10113 19:54:33.446740 00a80000 ################################################################
10114 19:54:33.446887
10115 19:54:33.708882 00b00000 ################################################################
10116 19:54:33.709031
10117 19:54:33.959335 00b80000 ################################################################
10118 19:54:33.959482
10119 19:54:34.213595 00c00000 ################################################################
10120 19:54:34.213747
10121 19:54:34.473038 00c80000 ################################################################
10122 19:54:34.473171
10123 19:54:34.724244 00d00000 ################################################################
10124 19:54:34.724387
10125 19:54:34.986630 00d80000 ################################################################
10126 19:54:34.986774
10127 19:54:35.244340 00e00000 ################################################################
10128 19:54:35.244525
10129 19:54:35.507701 00e80000 ################################################################
10130 19:54:35.507835
10131 19:54:35.770921 00f00000 ################################################################
10132 19:54:35.771080
10133 19:54:36.051094 00f80000 ################################################################
10134 19:54:36.051239
10135 19:54:36.339289 01000000 ################################################################
10136 19:54:36.339436
10137 19:54:36.604519 01080000 ################################################################
10138 19:54:36.604666
10139 19:54:36.896840 01100000 ################################################################
10140 19:54:36.896986
10141 19:54:37.183493 01180000 ################################################################
10142 19:54:37.183647
10143 19:54:37.456624 01200000 ################################################################
10144 19:54:37.456767
10145 19:54:37.741287 01280000 ################################################################
10146 19:54:37.741436
10147 19:54:38.031917 01300000 ################################################################
10148 19:54:38.032068
10149 19:54:38.314515 01380000 ################################################################
10150 19:54:38.314682
10151 19:54:38.593561 01400000 ################################################################
10152 19:54:38.593708
10153 19:54:38.874578 01480000 ################################################################
10154 19:54:38.874720
10155 19:54:39.153945 01500000 ################################################################
10156 19:54:39.154110
10157 19:54:39.433540 01580000 ################################################################
10158 19:54:39.433680
10159 19:54:39.757256 01600000 ################################################################
10160 19:54:39.757402
10161 19:54:40.037989 01680000 ################################################################
10162 19:54:40.038166
10163 19:54:40.316925 01700000 ################################################################
10164 19:54:40.317070
10165 19:54:40.596188 01780000 ################################################################
10166 19:54:40.596375
10167 19:54:40.846667 01800000 ################################################################
10168 19:54:40.846808
10169 19:54:41.105484 01880000 ################################################################
10170 19:54:41.105622
10171 19:54:41.357181 01900000 ################################################################
10172 19:54:41.357331
10173 19:54:41.607826 01980000 ################################################################
10174 19:54:41.607996
10175 19:54:41.873340 01a00000 ################################################################
10176 19:54:41.873493
10177 19:54:42.126074 01a80000 ################################################################
10178 19:54:42.126244
10179 19:54:42.384003 01b00000 ################################################################
10180 19:54:42.384163
10181 19:54:42.636531 01b80000 ################################################################
10182 19:54:42.636663
10183 19:54:42.893954 01c00000 ################################################################
10184 19:54:42.894132
10185 19:54:43.142917 01c80000 ################################################################
10186 19:54:43.143069
10187 19:54:43.396993 01d00000 ################################################################
10188 19:54:43.397141
10189 19:54:43.649477 01d80000 ################################################################
10190 19:54:43.649611
10191 19:54:43.903464 01e00000 ################################################################
10192 19:54:43.903629
10193 19:54:44.159798 01e80000 ################################################################
10194 19:54:44.159931
10195 19:54:44.442521 01f00000 ################################################################
10196 19:54:44.442715
10197 19:54:44.704713 01f80000 ################################################################
10198 19:54:44.704846
10199 19:54:44.956522 02000000 ################################################################
10200 19:54:44.956661
10201 19:54:45.202439 02080000 ################################################################
10202 19:54:45.202591
10203 19:54:45.451768 02100000 ################################################################
10204 19:54:45.451920
10205 19:54:45.702371 02180000 ################################################################
10206 19:54:45.702514
10207 19:54:45.954381 02200000 ################################################################
10208 19:54:45.954530
10209 19:54:46.200792 02280000 ################################################################
10210 19:54:46.200938
10211 19:54:46.448788 02300000 ################################################################
10212 19:54:46.448919
10213 19:54:46.713200 02380000 ################################################################
10214 19:54:46.713342
10215 19:54:46.964880 02400000 ################################################################
10216 19:54:46.965011
10217 19:54:47.216037 02480000 ################################################################
10218 19:54:47.216219
10219 19:54:47.470783 02500000 ################################################################
10220 19:54:47.470920
10221 19:54:47.721834 02580000 ################################################################
10222 19:54:47.721969
10223 19:54:47.974546 02600000 ################################################################
10224 19:54:47.974680
10225 19:54:48.226196 02680000 ################################################################
10226 19:54:48.226328
10227 19:54:48.479316 02700000 ################################################################
10228 19:54:48.479452
10229 19:54:48.728554 02780000 ################################################################
10230 19:54:48.728686
10231 19:54:48.977201 02800000 ################################################################
10232 19:54:48.977332
10233 19:54:49.227873 02880000 ################################################################
10234 19:54:49.228012
10235 19:54:49.480904 02900000 ################################################################
10236 19:54:49.481037
10237 19:54:49.750336 02980000 ################################################################
10238 19:54:49.750468
10239 19:54:50.042458 02a00000 ################################################################
10240 19:54:50.042595
10241 19:54:50.299412 02a80000 ################################################################
10242 19:54:50.299549
10243 19:54:50.551796 02b00000 ################################################################
10244 19:54:50.551929
10245 19:54:50.803401 02b80000 ################################################################
10246 19:54:50.803547
10247 19:54:51.056300 02c00000 ################################################################
10248 19:54:51.056441
10249 19:54:51.309827 02c80000 ################################################################
10250 19:54:51.309961
10251 19:54:51.569306 02d00000 ################################################################
10252 19:54:51.569435
10253 19:54:51.824058 02d80000 ################################################################
10254 19:54:51.824194
10255 19:54:52.072177 02e00000 ################################################################
10256 19:54:52.072338
10257 19:54:52.324433 02e80000 ################################################################
10258 19:54:52.324564
10259 19:54:52.599470 02f00000 ################################################################
10260 19:54:52.599631
10261 19:54:52.847924 02f80000 ################################################################
10262 19:54:52.848055
10263 19:54:53.117181 03000000 ################################################################
10264 19:54:53.117352
10265 19:54:53.391236 03080000 ################################################################
10266 19:54:53.391400
10267 19:54:53.682823 03100000 ################################################################
10268 19:54:53.682991
10269 19:54:53.971192 03180000 ################################################################
10270 19:54:53.971330
10271 19:54:54.227205 03200000 ################################################################
10272 19:54:54.227369
10273 19:54:54.477424 03280000 ################################################################
10274 19:54:54.477560
10275 19:54:54.730404 03300000 ################################################################
10276 19:54:54.730538
10277 19:54:54.980263 03380000 ################################################################
10278 19:54:54.980401
10279 19:54:55.317876 03400000 ################################################################
10280 19:54:55.318014
10281 19:54:55.600415 03480000 ################################################################
10282 19:54:55.600552
10283 19:54:55.849895 03500000 ################################################################
10284 19:54:55.850057
10285 19:54:56.099558 03580000 ################################################################
10286 19:54:56.099729
10287 19:54:56.351986 03600000 ################################################################
10288 19:54:56.352122
10289 19:54:56.606193 03680000 ################################################################
10290 19:54:56.606329
10291 19:54:56.855751 03700000 ################################################################
10292 19:54:56.855891
10293 19:54:57.105370 03780000 ################################################################
10294 19:54:57.105510
10295 19:54:57.354572 03800000 ################################################################
10296 19:54:57.354713
10297 19:54:57.605024 03880000 ################################################################
10298 19:54:57.605160
10299 19:54:57.857727 03900000 ################################################################
10300 19:54:57.857864
10301 19:54:58.110358 03980000 ################################################################
10302 19:54:58.110502
10303 19:54:58.381921 03a00000 ################################################################
10304 19:54:58.382061
10305 19:54:58.663767 03a80000 ################################################################
10306 19:54:58.663916
10307 19:54:58.947000 03b00000 ################################################################
10308 19:54:58.947147
10309 19:54:59.230853 03b80000 ################################################################
10310 19:54:59.231004
10311 19:54:59.527265 03c00000 ################################################################
10312 19:54:59.527418
10313 19:54:59.824539 03c80000 ################################################################
10314 19:54:59.824687
10315 19:55:00.104212 03d00000 ################################################################
10316 19:55:00.104355
10317 19:55:00.373399 03d80000 ################################################################
10318 19:55:00.373550
10319 19:55:00.652927 03e00000 ################################################################
10320 19:55:00.653073
10321 19:55:00.933157 03e80000 ################################################################
10322 19:55:00.933348
10323 19:55:01.209029 03f00000 ################################################################
10324 19:55:01.209166
10325 19:55:01.484713 03f80000 ################################################################
10326 19:55:01.484863
10327 19:55:01.708029 04000000 ################################################### done.
10328 19:55:01.708170
10329 19:55:01.711037 The bootfile was 67525018 bytes long.
10330 19:55:01.711126
10331 19:55:01.714619 Sending tftp read request... done.
10332 19:55:01.714719
10333 19:55:01.714795 Waiting for the transfer...
10334 19:55:01.714867
10335 19:55:01.718287 00000000 # done.
10336 19:55:01.718384
10337 19:55:01.724438 Command line loaded dynamically from TFTP file: 11899565/tftp-deploy-kk2tey4x/kernel/cmdline
10338 19:55:01.724633
10339 19:55:01.738205 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10340 19:55:01.738442
10341 19:55:01.741055 Loading FIT.
10342 19:55:01.741222
10343 19:55:01.743986 Image ramdisk-1 has 56428181 bytes.
10344 19:55:01.744140
10345 19:55:01.747721 Image fdt-1 has 47278 bytes.
10346 19:55:01.747897
10347 19:55:01.748034 Image kernel-1 has 11047522 bytes.
10348 19:55:01.751251
10349 19:55:01.757576 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10350 19:55:01.757905
10351 19:55:01.777855 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10352 19:55:01.778469
10353 19:55:01.780579 Choosing best match conf-1 for compat google,spherion-rev2.
10354 19:55:01.785551
10355 19:55:01.790482 Connected to device vid:did:rid of 1ae0:0028:00
10356 19:55:01.798224
10357 19:55:01.801794 tpm_get_response: command 0x17b, return code 0x0
10358 19:55:01.802280
10359 19:55:01.804647 ec_init: CrosEC protocol v3 supported (256, 248)
10360 19:55:01.809085
10361 19:55:01.812518 tpm_cleanup: add release locality here.
10362 19:55:01.813005
10363 19:55:01.813494 Shutting down all USB controllers.
10364 19:55:01.815459
10365 19:55:01.815954 Removing current net device
10366 19:55:01.816401
10367 19:55:01.823051 Exiting depthcharge with code 4 at timestamp: 69565370
10368 19:55:01.823586
10369 19:55:01.825619 LZMA decompressing kernel-1 to 0x821a6718
10370 19:55:01.826059
10371 19:55:01.829017 LZMA decompressing kernel-1 to 0x40000000
10372 19:55:03.217330
10373 19:55:03.217912 jumping to kernel
10374 19:55:03.220203 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10375 19:55:03.220754 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10376 19:55:03.221193 Setting prompt string to ['Linux version [0-9]']
10377 19:55:03.221631 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10378 19:55:03.222069 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10379 19:55:03.299439
10380 19:55:03.302975 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10381 19:55:03.306613 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10382 19:55:03.307194 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10383 19:55:03.307686 Setting prompt string to []
10384 19:55:03.308227 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10385 19:55:03.308664 Using line separator: #'\n'#
10386 19:55:03.309054 No login prompt set.
10387 19:55:03.309481 Parsing kernel messages
10388 19:55:03.309868 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10389 19:55:03.310481 [login-action] Waiting for messages, (timeout 00:03:43)
10390 19:55:03.325173 [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023
10391 19:55:03.328634 [ 0.000000] random: crng init done
10392 19:55:03.335178 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10393 19:55:03.338227 [ 0.000000] efi: UEFI not found.
10394 19:55:03.344878 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10395 19:55:03.354861 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10396 19:55:03.361502 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10397 19:55:03.371747 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10398 19:55:03.378656 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10399 19:55:03.384563 [ 0.000000] printk: bootconsole [mtk8250] enabled
10400 19:55:03.391729 [ 0.000000] NUMA: No NUMA configuration found
10401 19:55:03.398174 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10402 19:55:03.405089 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10403 19:55:03.405616 [ 0.000000] Zone ranges:
10404 19:55:03.411484 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10405 19:55:03.414823 [ 0.000000] DMA32 empty
10406 19:55:03.421352 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10407 19:55:03.424871 [ 0.000000] Movable zone start for each node
10408 19:55:03.428221 [ 0.000000] Early memory node ranges
10409 19:55:03.434324 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10410 19:55:03.441031 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10411 19:55:03.447756 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10412 19:55:03.454533 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10413 19:55:03.461220 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10414 19:55:03.467631 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10415 19:55:03.523678 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10416 19:55:03.530401 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10417 19:55:03.537028 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10418 19:55:03.540222 [ 0.000000] psci: probing for conduit method from DT.
10419 19:55:03.547135 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10420 19:55:03.550362 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10421 19:55:03.556458 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10422 19:55:03.560266 [ 0.000000] psci: SMC Calling Convention v1.2
10423 19:55:03.567170 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10424 19:55:03.570345 [ 0.000000] Detected VIPT I-cache on CPU0
10425 19:55:03.576565 [ 0.000000] CPU features: detected: GIC system register CPU interface
10426 19:55:03.583021 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10427 19:55:03.590142 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10428 19:55:03.596520 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10429 19:55:03.603525 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10430 19:55:03.613021 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10431 19:55:03.616345 [ 0.000000] alternatives: applying boot alternatives
10432 19:55:03.623051 [ 0.000000] Fallback order for Node 0: 0
10433 19:55:03.629419 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10434 19:55:03.632912 [ 0.000000] Policy zone: Normal
10435 19:55:03.645996 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10436 19:55:03.656216 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10437 19:55:03.668315 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10438 19:55:03.678072 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10439 19:55:03.684259 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10440 19:55:03.687346 <6>[ 0.000000] software IO TLB: area num 8.
10441 19:55:03.744403 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10442 19:55:03.894235 <6>[ 0.000000] Memory: 7914320K/8385536K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 438448K reserved, 32768K cma-reserved)
10443 19:55:03.900700 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10444 19:55:03.907421 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10445 19:55:03.910830 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10446 19:55:03.917033 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10447 19:55:03.923952 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10448 19:55:03.927525 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10449 19:55:03.937158 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10450 19:55:03.943862 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10451 19:55:03.947127 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10452 19:55:03.955288 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10453 19:55:03.958292 <6>[ 0.000000] GICv3: 608 SPIs implemented
10454 19:55:03.965050 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10455 19:55:03.968407 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10456 19:55:03.971579 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10457 19:55:03.981472 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10458 19:55:03.991565 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10459 19:55:04.005005 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10460 19:55:04.011533 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10461 19:55:04.020391 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10462 19:55:04.034134 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10463 19:55:04.039873 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10464 19:55:04.047038 <6>[ 0.009143] Console: colour dummy device 80x25
10465 19:55:04.056801 <6>[ 0.013868] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10466 19:55:04.063573 <6>[ 0.024311] pid_max: default: 32768 minimum: 301
10467 19:55:04.066720 <6>[ 0.029183] LSM: Security Framework initializing
10468 19:55:04.073565 <6>[ 0.034121] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10469 19:55:04.084004 <6>[ 0.041984] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10470 19:55:04.090547 <6>[ 0.051397] cblist_init_generic: Setting adjustable number of callback queues.
10471 19:55:04.096905 <6>[ 0.058840] cblist_init_generic: Setting shift to 3 and lim to 1.
10472 19:55:04.107208 <6>[ 0.065217] cblist_init_generic: Setting adjustable number of callback queues.
10473 19:55:04.110177 <6>[ 0.072644] cblist_init_generic: Setting shift to 3 and lim to 1.
10474 19:55:04.117120 <6>[ 0.079123] rcu: Hierarchical SRCU implementation.
10475 19:55:04.123419 <6>[ 0.079125] rcu: Max phase no-delay instances is 1000.
10476 19:55:04.130282 <6>[ 0.079150] printk: bootconsole [mtk8250] printing thread started
10477 19:55:04.136669 <6>[ 0.097516] EFI services will not be available.
10478 19:55:04.139910 <6>[ 0.097717] smp: Bringing up secondary CPUs ...
10479 19:55:04.143486 <6>[ 0.098027] Detected VIPT I-cache on CPU1
10480 19:55:04.149655 <6>[ 0.098094] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10481 19:55:04.156960 <6>[ 0.098127] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10482 19:55:04.168810 <6>[ 0.125956] Detected VIPT I-cache on CPU2
10483 19:55:04.175249 <6>[ 0.126003] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10484 19:55:04.185031 <6>[ 0.126017] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10485 19:55:04.188708 <6>[ 0.126266] Detected VIPT I-cache on CPU3
10486 19:55:04.195160 <6>[ 0.126307] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10487 19:55:04.202007 <6>[ 0.126320] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10488 19:55:04.205610 <6>[ 0.126615] CPU features: detected: Spectre-v4
10489 19:55:04.211995 <6>[ 0.126622] CPU features: detected: Spectre-BHB
10490 19:55:04.215377 <6>[ 0.126627] Detected PIPT I-cache on CPU4
10491 19:55:04.221876 <6>[ 0.126684] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10492 19:55:04.227853 <6>[ 0.126701] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10493 19:55:04.234853 <6>[ 0.126993] Detected PIPT I-cache on CPU5
10494 19:55:04.241803 <6>[ 0.127054] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10495 19:55:04.248103 <6>[ 0.127070] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10496 19:55:04.251365 <6>[ 0.127346] Detected PIPT I-cache on CPU6
10497 19:55:04.258074 <6>[ 0.127409] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10498 19:55:04.264585 <6>[ 0.127426] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10499 19:55:04.271254 <6>[ 0.127720] Detected PIPT I-cache on CPU7
10500 19:55:04.277902 <6>[ 0.127784] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10501 19:55:04.284262 <6>[ 0.127800] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10502 19:55:04.287938 <6>[ 0.127846] smp: Brought up 1 node, 8 CPUs
10503 19:55:04.294848 <6>[ 0.127851] SMP: Total of 8 processors activated.
10504 19:55:04.298086 <6>[ 0.127854] CPU features: detected: 32-bit EL0 Support
10505 19:55:04.308215 <6>[ 0.127856] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10506 19:55:04.314358 <6>[ 0.127858] CPU features: detected: Common not Private translations
10507 19:55:04.321252 <6>[ 0.127860] CPU features: detected: CRC32 instructions
10508 19:55:04.324684 <6>[ 0.127863] CPU features: detected: RCpc load-acquire (LDAPR)
10509 19:55:04.331179 <6>[ 0.127864] CPU features: detected: LSE atomic instructions
10510 19:55:04.338115 <6>[ 0.127866] CPU features: detected: Privileged Access Never
10511 19:55:04.344289 <6>[ 0.127867] CPU features: detected: RAS Extension Support
10512 19:55:04.350843 <6>[ 0.127870] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10513 19:55:04.354172 <6>[ 0.127936] CPU: All CPU(s) started at EL2
10514 19:55:04.361044 <6>[ 0.127938] alternatives: applying system-wide alternatives
10515 19:55:04.363981 <6>[ 0.141020] devtmpfs: initialized
10516 19:55:04.373802 <6>[ 0.147190] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10517 19:55:04.408685 �����r�������2�ѕ�B�͡�������*��ɥ�������Bzɑ����b�������ѕͱb����ɥjR�<6>[ 0.3<68479] printk: console [ttyS0] printing thread started
10518 19:55:04.412337 6<6>[ 0.368509] printk: console [ttyS0] enabled
10519 19:55:04.415446 >[ 0.148047] pinctrl core: initialized pinctrl subsystem
10520 19:55:04.423219 <6>[ 0.368513] printk: bootconsole [mtk8250] disabled
10521 19:55:04.430015 <6>[ 0.384234] printk: bootconsole [mtk8250] printing thread stopped
10522 19:55:04.433242 <6>[ 0.385492] SuperH (H)SCI(F) driver initialized
10523 19:55:04.439449 <6>[ 0.385982] msm_serial: driver initialized
10524 19:55:04.445825 <6>[ 0.390584] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10525 19:55:04.456560 <6>[ 0.390612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10526 19:55:04.462968 <6>[ 0.390641] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10527 19:55:04.482979 <6>[ 0.390670] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10528 19:55:04.491416 <6>[ 0.390691] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10529 19:55:04.491994 <6>[ 0.390718] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10530 19:55:04.508234 <6>[ 0.390746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10531 19:55:04.509509 <6>[ 0.390883] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10532 19:55:04.519449 <6>[ 0.390913] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10533 19:55:04.520022 <6>[ 0.400552] loop: module loaded
10534 19:55:04.530409 <6>[ 0.403124] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10535 19:55:04.534028 <4>[ 0.420025] mtk-pmic-keys: Failed to locate of_node [id: -1]
10536 19:55:04.534551 <6>[ 0.420925] megasas: 07.719.03.00-rc1
10537 19:55:04.540677 <6>[ 0.432729] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10538 19:55:04.547374 <6>[ 0.432851] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10539 19:55:04.554207 <6>[ 0.444941] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10540 19:55:04.563624 <6>[ 0.499675] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10541 19:55:06.694845 <6>[ 2.655237] Freeing initrd memory: 55104K
10542 19:55:06.701219 <6>[ 2.661229] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10543 19:55:06.703999 <6>[ 2.665950] tun: Universal TUN/TAP device driver, 1.6
10544 19:55:06.707460 <6>[ 2.666697] thunder_xcv, ver 1.0
10545 19:55:06.710916 <6>[ 2.666716] thunder_bgx, ver 1.0
10546 19:55:06.714240 <6>[ 2.666734] nicpf, ver 1.0
10547 19:55:06.723927 <6>[ 2.667779] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10548 19:55:06.727342 <6>[ 2.667782] hns3: Copyright (c) 2017 Huawei Corporation.
10549 19:55:06.730845 <6>[ 2.667806] hclge is initializing
10550 19:55:06.737796 <6>[ 2.667825] e1000: Intel(R) PRO/1000 Network Driver
10551 19:55:06.744067 <6>[ 2.667827] e1000: Copyright (c) 1999-2006 Intel Corporation.
10552 19:55:06.747596 <6>[ 2.667846] e1000e: Intel(R) PRO/1000 Network Driver
10553 19:55:06.755170 <6>[ 2.667848] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10554 19:55:06.761922 <6>[ 2.667865] igb: Intel(R) Gigabit Ethernet Network Driver
10555 19:55:06.765473 <6>[ 2.667867] igb: Copyright (c) 2007-2014 Intel Corporation.
10556 19:55:06.772608 <6>[ 2.667880] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10557 19:55:06.779555 <6>[ 2.667882] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10558 19:55:06.782528 <6>[ 2.668178] sky2: driver version 1.30
10559 19:55:06.789179 <6>[ 2.669256] VFIO - User Level meta-driver version: 0.3
10560 19:55:06.792665 <6>[ 2.672116] usbcore: registered new interface driver usb-storage
10561 19:55:06.799701 <6>[ 2.672293] usbcore: registered new device driver onboard-usb-hub
10562 19:55:06.806067 <6>[ 2.675032] mt6397-rtc mt6359-rtc: registered as rtc0
10563 19:55:06.816183 <6>[ 2.675184] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T19:53:32 UTC (1698522812)
10564 19:55:06.819633 <6>[ 2.675807] i2c_dev: i2c /dev entries driver
10565 19:55:06.825965 <6>[ 2.682986] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10566 19:55:06.832206 <6>[ 2.698976] cpu cpu0: EM: created perf domain
10567 19:55:06.835791 <6>[ 2.699293] cpu cpu4: EM: created perf domain
10568 19:55:06.842595 <6>[ 2.704902] sdhci: Secure Digital Host Controller Interface driver
10569 19:55:06.849192 <6>[ 2.704903] sdhci: Copyright(c) Pierre Ossman
10570 19:55:06.851959 <6>[ 2.705251] Synopsys Designware Multimedia Card Interface Driver
10571 19:55:06.859300 <6>[ 2.705623] sdhci-pltfm: SDHCI platform and OF driver helper
10572 19:55:06.865478 <6>[ 2.710791] ledtrig-cpu: registered to indicate activity on CPUs
10573 19:55:06.872567 <6>[ 2.711497] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10574 19:55:06.875575 <6>[ 2.711511] mmc0: CQHCI version 5.10
10575 19:55:06.882289 <6>[ 2.711774] usbcore: registered new interface driver usbhid
10576 19:55:06.885702 <6>[ 2.711775] usbhid: USB HID core driver
10577 19:55:06.892368 <6>[ 2.711903] spi_master spi0: will run message pump with realtime priority
10578 19:55:06.905471 <6>[ 2.741113] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10579 19:55:06.918779 <6>[ 2.743209] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10580 19:55:06.925639 <6>[ 2.744935] cros-ec-spi spi0.0: Chrome EC device registered
10581 19:55:06.935429 <6>[ 2.757631] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10582 19:55:06.938419 <6>[ 2.758648] NET: Registered PF_PACKET protocol family
10583 19:55:06.945313 <6>[ 2.758723] 9pnet: Installing 9P2000 support
10584 19:55:06.948561 <5>[ 2.758752] Key type dns_resolver registered
10585 19:55:06.952262 <6>[ 2.759242] registered taskstats version 1
10586 19:55:06.958347 <5>[ 2.759268] Loading compiled-in X.509 certificates
10587 19:55:06.968016 <4>[ 2.776452] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 19:55:06.977804 <4>[ 2.776748] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10589 19:55:06.984444 <3>[ 2.776770] debugfs: File 'uA_load' in directory '/' already present!
10590 19:55:06.991728 <3>[ 2.776781] debugfs: File 'min_uV' in directory '/' already present!
10591 19:55:06.997836 <3>[ 2.776788] debugfs: File 'max_uV' in directory '/' already present!
10592 19:55:07.008040 <3>[ 2.776794] debugfs: File 'constraint_flags' in directory '/' already present!
10593 19:55:07.014643 <3>[ 2.780574] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10594 19:55:07.020837 <6>[ 2.790485] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10595 19:55:07.028003 <6>[ 2.791112] xhci-mtk 11200000.usb: xHCI Host Controller
10596 19:55:07.034419 <6>[ 2.791132] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10597 19:55:07.044283 <6>[ 2.791358] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10598 19:55:07.050830 <6>[ 2.791412] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10599 19:55:07.054438 <6>[ 2.791519] xhci-mtk 11200000.usb: xHCI Host Controller
10600 19:55:07.064264 <6>[ 2.791527] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10601 19:55:07.071254 <6>[ 2.791534] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10602 19:55:07.074706 <6>[ 2.791999] hub 1-0:1.0: USB hub found
10603 19:55:07.077879 <6>[ 2.792034] hub 1-0:1.0: 1 port detected
10604 19:55:07.087681 <6>[ 2.792317] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10605 19:55:07.090790 <6>[ 2.792569] hub 2-0:1.0: USB hub found
10606 19:55:07.094334 <6>[ 2.792579] hub 2-0:1.0: 1 port detected
10607 19:55:07.100503 <6>[ 2.795672] mtk-msdc 11f70000.mmc: Got CD GPIO
10608 19:55:07.107398 <6>[ 2.804257] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10609 19:55:07.117213 <6>[ 2.804265] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10610 19:55:07.123893 <4>[ 2.804360] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10611 19:55:07.133932 <6>[ 2.804851] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10612 19:55:07.140579 <6>[ 2.804853] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10613 19:55:07.146985 <6>[ 2.805093] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10614 19:55:07.156688 <6>[ 2.805116] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10615 19:55:07.163704 <6>[ 2.805119] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10616 19:55:07.173243 <6>[ 2.805123] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10617 19:55:07.179966 <6>[ 2.806674] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10618 19:55:07.190221 <6>[ 2.806689] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10619 19:55:07.200048 <6>[ 2.806692] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10620 19:55:07.206466 <6>[ 2.806696] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10621 19:55:07.216681 <6>[ 2.806699] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10622 19:55:07.223104 <6>[ 2.806702] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10623 19:55:07.232802 <6>[ 2.806706] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10624 19:55:07.239500 <6>[ 2.806709] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10625 19:55:07.249133 <6>[ 2.806712] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10626 19:55:07.258690 <6>[ 2.806716] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10627 19:55:07.265822 <6>[ 2.806719] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10628 19:55:07.272350 <6>[ 2.806723] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10629 19:55:07.282639 <6>[ 2.806727] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10630 19:55:07.289124 <6>[ 2.806731] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10631 19:55:07.299112 <6>[ 2.806734] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10632 19:55:07.305760 <6>[ 2.807108] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10633 19:55:07.312363 <6>[ 2.807652] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10634 19:55:07.318874 <6>[ 2.807857] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10635 19:55:07.325875 <6>[ 2.808090] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10636 19:55:07.332047 <6>[ 2.808324] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10637 19:55:07.339434 <6>[ 2.808486] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10638 19:55:07.348624 <6>[ 2.808494] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10639 19:55:07.358985 <6>[ 2.808496] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10640 19:55:07.368905 <6>[ 2.808498] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10641 19:55:07.378515 <6>[ 2.808501] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10642 19:55:07.385988 <6>[ 2.808510] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10643 19:55:07.395379 <6>[ 2.808514] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10644 19:55:07.405401 <6>[ 2.808516] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10645 19:55:07.414932 <6>[ 2.808518] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10646 19:55:07.424759 <6>[ 2.808522] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10647 19:55:07.435334 <6>[ 2.808525] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10648 19:55:07.441916 <6>[ 2.809042] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10649 19:55:07.448449 <6>[ 2.810772] mmc0: Command Queue Engine enabled
10650 19:55:07.454869 <6>[ 2.810784] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10651 19:55:07.457905 <6>[ 2.811252] mmcblk0: mmc0:0001 DA4128 116 GiB
10652 19:55:07.464567 <6>[ 2.814414] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10653 19:55:07.471707 <6>[ 2.815479] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10654 19:55:07.474418 <6>[ 2.816083] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10655 19:55:07.481585 <6>[ 2.816595] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10656 19:55:07.488025 <6>[ 3.213475] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10657 19:55:07.491436 <6>[ 3.366128] hub 1-1:1.0: USB hub found
10658 19:55:07.497893 <6>[ 3.366515] hub 1-1:1.0: 4 ports detected
10659 19:55:07.538182 <6>[ 3.493791] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10660 19:55:07.558978 <6>[ 3.520359] hub 2-1:1.0: USB hub found
10661 19:55:07.562035 <6>[ 3.520733] hub 2-1:1.0: 3 ports detected
10662 19:55:07.721997 <6>[ 3.677629] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10663 19:55:07.843047 <6>[ 3.804458] hub 1-1.4:1.0: USB hub found
10664 19:55:07.846170 <6>[ 3.804768] hub 1-1.4:1.0: 2 ports detected
10665 19:55:07.926025 <6>[ 3.881780] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10666 19:55:08.138369 <6>[ 4.093598] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10667 19:55:08.321900 <6>[ 4.277610] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10668 19:55:19.142507 <6>[ 15.106415] ALSA device list:
10669 19:55:19.148997 <6>[ 15.106436] No soundcards found.
10670 19:55:19.152278 <6>[ 15.110796] Freeing unused kernel memory: 8448K
10671 19:55:19.155357 <6>[ 15.110895] Run /init as init process
10672 19:55:19.177867 <6>[ 15.140639] NET: Registered PF_INET6 protocol family
10673 19:55:19.180813 <6>[ 15.141722] Segment Routing with IPv6
10674 19:55:19.187532 <6>[ 15.141733] In-situ OAM (IOAM) with IPv6
10675 19:55:19.191064
10676 19:55:19.217729 Welcome to [1mDebian GNU/Linux 11 (bullseye)<30>[ 15.157595] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10677 19:55:19.218263 [0m!
10678 19:55:19.218593
10679 19:55:19.224198 <30>[ 15.158015] systemd[1]: Detected architecture arm64.
10680 19:55:19.230266 <30>[ 15.191981] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10681 19:55:19.352853 <30>[ 15.311188] systemd[1]: Queued start job for default target Graphical Interface.
10682 19:55:19.385861 [[0;32m OK [0m] Created slic<30>[ 15.346528] systemd[1]: Created slice system-getty.slice.
10683 19:55:19.389455 e [0;1;39msystem-getty.slice[0m.
10684 19:55:19.410203 [[0;32m OK [0m] Created slic<30>[ 15.371094] systemd[1]: Created slice system-modprobe.slice.
10685 19:55:19.413770 e [0;1;39msystem-modprobe.slice[0m.
10686 19:55:19.437188 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.394471] systemd[1]: Created slice system-serial\x2dgetty.slice.
10687 19:55:19.441025 m-serial\x2dgetty.slice[0m.
10688 19:55:19.461652 [[0;32m OK [0m] Created slice [0;1;39mUser <30>[ 15.418569] systemd[1]: Created slice User and Session Slice.
10689 19:55:19.462232 and Session Slice[0m.
10690 19:55:19.485422 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 15.442411] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10691 19:55:19.488900 ssword …ts to Console Directory Watch[0m.
10692 19:55:19.513396 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 15.470364] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10693 19:55:19.516332 sword R…uests to Wall Directory Watch[0m.
10694 19:55:19.544334 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 15.498092] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10695 19:55:19.550997 <30>[ 15.498345] systemd[1]: Reached target Local Encrypted Volumes.
10696 19:55:19.554476 l Encrypted Volumes[0m.
10697 19:55:19.574162 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 15.534067] systemd[1]: Reached target Paths.
10698 19:55:19.574687 s[0m.
10699 19:55:19.596450 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 15.553608] systemd[1]: Reached target Remote File Systems.
10700 19:55:19.596972 te File Systems[0m.
10701 19:55:19.612996 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 15.573576] systemd[1]: Reached target Slices.
10702 19:55:19.613569 es[0m.
10703 19:55:19.633306 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 15.593596] systemd[1]: Reached target Swap.
10704 19:55:19.633835 [0m.
10705 19:55:19.657113 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 15.614036] systemd[1]: Listening on initctl Compatibility Named Pipe.
10706 19:55:19.660175 l Compatibility Named Pipe[0m.
10707 19:55:19.678798 [[0;32m OK [0m] Listening on<30>[ 15.639106] systemd[1]: Listening on Journal Audit Socket.
10708 19:55:19.681625 [0;1;39mJournal Audit Socket[0m.
10709 19:55:19.705245 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 15.662104] systemd[1]: Listening on Journal Socket (/dev/log).
10710 19:55:19.705768 l Socket (/dev/log)[0m.
10711 19:55:19.726563 [[0;32m OK [0m] Listening on<30>[ 15.686798] systemd[1]: Listening on Journal Socket.
10712 19:55:19.729532 [0;1;39mJournal Socket[0m.
10713 19:55:19.745486 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 15.706170] systemd[1]: Listening on udev Control Socket.
10714 19:55:19.748883 ontrol Socket[0m.
10715 19:55:19.770317 [[0;32m OK [0m] Listening on<30>[ 15.730609] systemd[1]: Listening on udev Kernel Socket.
10716 19:55:19.773284 [0;1;39mudev Kernel Socket[0m.
10717 19:55:19.829525 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.789856] systemd[1]: Mounting Huge Pages File System...
10718 19:55:19.832517 m[0m...
10719 19:55:19.852571 Mountin<30>[ 15.813078] systemd[1]: Mounting POSIX Message Queue File System...
10720 19:55:19.855741 g [0;1;39mPOSIX Message Queue File System[0m...
10721 19:55:19.884518 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.841628] systemd[1]: Mounting Kernel Debug File System...
10722 19:55:19.885034 tem[0m...
10723 19:55:19.904414 <30>[ 15.862060] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10724 19:55:19.917854 Starting [0;1;39mCreate list of st…o<30>[ 15.866355] systemd[1]: Starting Create list of static device nodes for the current kernel...
10725 19:55:19.921187 des for the current kernel[0m...
10726 19:55:19.949508 Starting [0;1;39mLoad Kernel Module co<30>[ 15.906110] systemd[1]: Starting Load Kernel Module configfs...
10727 19:55:19.950040 nfigfs[0m...
10728 19:55:19.968034 Startin<30>[ 15.928080] systemd[1]: Starting Load Kernel Module drm...
10729 19:55:19.970851 g [0;1;39mLoad Kernel Module drm[0m...
10730 19:55:19.992920 <30>[ 15.949971] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10731 19:55:20.005669 Starting [0;1;39mJournal Service[0m..<30>[ 15.966426] systemd[1]: Starting Journal Service...
10732 19:55:20.006133 .
10733 19:55:20.027407 Startin<30>[ 15.988311] systemd[1]: Starting Load Kernel Modules...
10734 19:55:20.030900 g [0;1;39mLoad Kernel Modules[0m...
10735 19:55:20.052716 Startin<30>[ 16.012595] systemd[1]: Starting Remount Root and Kernel File Systems...
10736 19:55:20.058983 g [0;1;39mRemount Root and Kernel File Systems[0m...
10737 19:55:20.080559 Startin<30>[ 16.040564] systemd[1]: Starting Coldplug All udev Devices...
10738 19:55:20.083752 g [0;1;39mColdplug All udev Devices[0m...
10739 19:55:20.105164 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 16.065375] systemd[1]: Started Journal Service.
10740 19:55:20.108369 vice[0m.
10741 19:55:20.124338 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10742 19:55:20.143105 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10743 19:55:20.159162 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10744 19:55:20.179462 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10745 19:55:20.196997 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10746 19:55:20.216240 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10747 19:55:20.235245 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10748 19:55:20.255526 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10749 19:55:20.269903 See 'systemctl status systemd-remount-fs.service' for details.
10750 19:55:20.321363 Mounting [0;1;39mKernel Configuration File System[0m...
10751 19:55:20.342345 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10752 19:55:20.364722 <46>[ 16.325177] systemd-journald[191]: Received client request to flush runtime journal.
10753 19:55:20.367681 Starting [0;1;39mLoad/Save Random Seed[0m...
10754 19:55:20.388292 Starting [0;1;39mApply Kernel Variables[0m...
10755 19:55:20.407298 Starting [0;1;39mCreate System Users[0m...
10756 19:55:20.424878 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10757 19:55:20.443061 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10758 19:55:20.462501 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10759 19:55:20.475462 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10760 19:55:20.491519 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10761 19:55:20.507778 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10762 19:55:20.546399 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10763 19:55:20.577449 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10764 19:55:20.590930 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10765 19:55:20.606129 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10766 19:55:20.646029 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10767 19:55:20.670641 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10768 19:55:20.690856 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10769 19:55:20.712014 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10770 19:55:20.775874 Starting [0;1;39mNetwork Time Synchronization[0m...
10771 19:55:20.799196 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10772 19:55:20.848351 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10773 19:55:20.863377 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10774 19:55:20.888542 <6>[ 16.848192] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10775 19:55:20.891565 <6>[ 16.853743] remoteproc remoteproc0: scp is available
10776 19:55:20.898808 <6>[ 16.853823] remoteproc remoteproc0: powering up scp
10777 19:55:20.908227 [[0;32m OK [<6>[ 16.853828] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10778 19:55:20.915046 0m] Found device<6>[ 16.853847] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10779 19:55:20.925109 [0;1;39m/dev/t<6>[ 16.879727] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10780 19:55:20.934477 <6>[ 16.879815] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10781 19:55:20.935009 tyS0[0m.
10782 19:55:20.944518 <6>[ 16.879826] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10783 19:55:20.960249 <3>[ 16.919695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10784 19:55:20.967107 <3>[ 16.919711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10785 19:55:20.976993 <3>[ 16.919714] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10786 19:55:20.983472 <3>[ 16.923455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10787 19:55:20.997148 [[0;32m OK [0m] Created slice [0;1;39msyste<3>[ 16.923491] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10788 19:55:21.003552 <3>[ 16.923496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10789 19:55:21.013524 <3>[ 16.923502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 19:55:21.023203 m-systemd\x2dbac<3>[ 16.923505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 19:55:21.030310 <3>[ 16.931551] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10792 19:55:21.039851 <3>[ 16.958421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10793 19:55:21.046464 <3>[ 16.958441] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10794 19:55:21.056624 <3>[ 16.958449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10795 19:55:21.062946 <3>[ 16.960888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 19:55:21.069933 <3>[ 16.960911] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 19:55:21.079438 <3>[ 16.960914] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 19:55:21.089744 klight.slice[0m<3>[ 16.960920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10799 19:55:21.096323 <3>[ 16.960924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10800 19:55:21.103473 <3>[ 16.968012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10801 19:55:21.113788 <6>[ 16.982631] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10802 19:55:21.114223 .
10803 19:55:21.119906 <6>[ 16.982693] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10804 19:55:21.126815 <6>[ 16.982700] remoteproc remoteproc0: remote processor scp is now up
10805 19:55:21.136688 [[0;32m OK [<4>[ 16.992336] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10806 19:55:21.143752 0m] Reached targ<6>[ 16.992526] mc: Linux media interface: v0.10
10807 19:55:21.150385 <4>[ 17.001804] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10808 19:55:21.157205 <6>[ 17.017914] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10809 19:55:21.160210 <6>[ 17.017982] pci_bus 0000:00: root bus resource [bus 00-ff]
10810 19:55:21.170923 <6>[ 17.018005] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10811 19:55:21.177996 <6>[ 17.018013] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10812 19:55:21.184695 <6>[ 17.018190] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10813 19:55:21.194120 et [0;1;39mSyst<6>[ 17.018236] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10814 19:55:21.197554 <6>[ 17.018376] pci 0000:00:00.0: supports D1 D2
10815 19:55:21.204304 <6>[ 17.018381] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10816 19:55:21.214285 em Time Set[0m.<6>[ 17.030052] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10817 19:55:21.224281 <6>[ 17.031067] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10818 19:55:21.224708
10819 19:55:21.230648 <6>[ 17.036108] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10820 19:55:21.237084 <6>[ 17.036141] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10821 19:55:21.244123 <6>[ 17.036159] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10822 19:55:21.250470 <6>[ 17.036173] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10823 19:55:21.257407 [[0;32m OK [<6>[ 17.036280] pci 0000:01:00.0: supports D1 D2
10824 19:55:21.267927 0m] Reached targ<6>[ 17.036282] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10825 19:55:21.274379 et [0;1;39mSyst<6>[ 17.052127] videodev: Linux video capture interface: v2.00
10826 19:55:21.281555 em Time Synchron<6>[ 17.055339] usbcore: registered new interface driver r8152
10827 19:55:21.281981 ized[0m.
10828 19:55:21.291756 <4>[ 17.060936] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10829 19:55:21.294790 <4>[ 17.060936] Fallback method does not support PEC.
10830 19:55:21.301521 <6>[ 17.065600] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10831 19:55:21.311946 <6>[ 17.065757] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10832 19:55:21.318591 <6>[ 17.065770] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10833 19:55:21.325509 <6>[ 17.065792] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10834 19:55:21.335412 <6>[ 17.065807] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10835 19:55:21.342503 <6>[ 17.065824] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10836 19:55:21.345771 <6>[ 17.065841] pci 0000:00:00.0: PCI bridge to [bus 01]
10837 19:55:21.355979 <6>[ 17.065849] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10838 19:55:21.364127 <6>[ 17.066253] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10839 19:55:21.367509 <6>[ 17.073396] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10840 19:55:21.374103 <6>[ 17.074084] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10841 19:55:21.384555 <6>[ 17.074651] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10842 19:55:21.391806 <6>[ 17.075209] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10843 19:55:21.402277 <3>[ 17.076380] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 19:55:21.412352 <3>[ 17.122176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10845 19:55:21.419181 <3>[ 17.122759] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10846 19:55:21.430087 <6>[ 17.132365] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10847 19:55:21.436603 <6>[ 17.139393] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10848 19:55:21.443811 <3>[ 17.146922] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 19:55:21.453851 <4>[ 17.162444] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10850 19:55:21.460280 <4>[ 17.162463] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10851 19:55:21.466793 <6>[ 17.168686] usbcore: registered new interface driver cdc_ether
10852 19:55:21.477373 <6>[ 17.176155] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10853 19:55:21.483682 <6>[ 17.186927] usbcore: registered new interface driver r8153_ecm
10854 19:55:21.490950 <5>[ 17.189892] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10855 19:55:21.496760 <6>[ 17.192228] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10856 19:55:21.504070 <6>[ 17.199829] Bluetooth: Core ver 2.22
10857 19:55:21.506614 <6>[ 17.200036] NET: Registered PF_BLUETOOTH protocol family
10858 19:55:21.513527 <6>[ 17.200043] Bluetooth: HCI device and connection manager initialized
10859 19:55:21.520211 <6>[ 17.200094] Bluetooth: HCI socket layer initialized
10860 19:55:21.523674 <6>[ 17.200110] Bluetooth: L2CAP socket layer initialized
10861 19:55:21.529749 <6>[ 17.200162] Bluetooth: SCO socket layer initialized
10862 19:55:21.536568 <5>[ 17.205850] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10863 19:55:21.546320 <4>[ 17.205964] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10864 19:55:21.549677 <6>[ 17.205975] cfg80211: failed to load regulatory.db
10865 19:55:21.556151 <6>[ 17.215767] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10866 19:55:21.569359 <6>[ 17.217167] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10867 19:55:21.576332 <6>[ 17.217414] usbcore: registered new interface driver uvcvideo
10868 19:55:21.579381 <6>[ 17.217436] r8152 2-1.3:1.0 eth0: v1.12.13
10869 19:55:21.585829 <6>[ 17.237298] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10870 19:55:21.592390 <6>[ 17.245196] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10871 19:55:21.602126 <3>[ 17.258847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10872 19:55:21.608960 <3>[ 17.259583] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 19:55:21.619072 <3>[ 17.262173] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 19:55:21.625622 <6>[ 17.265567] usbcore: registered new interface driver btusb
10875 19:55:21.635410 <4>[ 17.266654] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10876 19:55:21.642149 <3>[ 17.266680] Bluetooth: hci0: Failed to load firmware file (-2)
10877 19:55:21.648638 <3>[ 17.266686] Bluetooth: hci0: Failed to set up firmware (-2)
10878 19:55:21.658098 <4>[ 17.266693] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10879 19:55:21.664801 <3>[ 17.282875] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 19:55:21.674827 <6>[ 17.309217] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10881 19:55:21.677911 <6>[ 17.309434] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10882 19:55:21.687865 <3>[ 17.312700] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 19:55:21.694582 <6>[ 17.329440] mt7921e 0000:01:00.0: ASIC revision: 79610010
10884 19:55:21.701344 <3>[ 17.334197] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 19:55:21.714881 <4>[ 17.424022] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10886 19:55:21.724887 <4>[ 17.533719] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10887 19:55:21.737970 <4>[ 17.643197] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10888 19:55:21.744672 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10889 19:55:21.765377 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10890 19:55:21.791576 <4>[ 17.747301] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10891 19:55:21.899423 <4>[ 17.855358] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10892 19:55:21.925605 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10893 19:55:21.941372 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10894 19:55:21.964831 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10895 19:55:21.980781 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10896 19:55:21.995289 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10897 19:55:22.008593 <4>[ 17.964063] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10898 19:55:22.018913 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10899 19:55:22.033170 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10900 19:55:22.049279 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10901 19:55:22.068897 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10902 19:55:22.117092 [[0;32m OK [0m] Started [0;<4>[ 18.071840] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10903 19:55:22.119984 1;39mD-Bus System Message Bus[0m.
10904 19:55:22.146812 Starting [0;1;39mUser Login Management[0m...
10905 19:55:22.165993 Starting [0;1;39mPermit User Sessions[0m...
10906 19:55:22.184983 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10907 19:55:22.227389 <4>[ 18.184226] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10908 19:55:22.242296 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10909 19:55:22.261920 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10910 19:55:22.277612 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10911 19:55:22.314882 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10912 19:55:22.343054 [[0;32m OK [0m] Started [0;1;39mUser Login <4>[ 18.294054] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10913 19:55:22.346782 Management[0m.
10914 19:55:22.361762 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10915 19:55:22.383209 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10916 19:55:22.401339 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10917 19:55:22.447184 <4>[ 18.403579] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10918 19:55:22.454207 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10919 19:55:22.481824 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10920 19:55:22.538711
10921 19:55:22.538870
10922 19:55:22.541976 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10923 19:55:22.542065
10924 19:55:22.551349 debian-bullseye-arm64 login: root (automat<3>[ 18.512142] mt7921e 0000:01:00.0: hardware init failed
10925 19:55:22.551483 ic login)
10926 19:55:22.551551
10927 19:55:22.551611
10928 19:55:22.566683 Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64
10929 19:55:22.566803
10930 19:55:22.573466 The programs included with the Debian GNU/Linux system are free software;
10931 19:55:22.579868 the exact distribution terms for each program are described in the
10932 19:55:22.583246 individual files in /usr/share/doc/*/copyright.
10933 19:55:22.583328
10934 19:55:22.589738 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10935 19:55:22.592653 permitted by applicable law.
10936 19:55:22.593022 Matched prompt #10: / #
10938 19:55:22.593222 Setting prompt string to ['/ #']
10939 19:55:22.593314 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10941 19:55:22.593506 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10942 19:55:22.593595 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
10943 19:55:22.593666 Setting prompt string to ['/ #']
10944 19:55:22.593726 Forcing a shell prompt, looking for ['/ #']
10946 19:55:22.643960 / #
10947 19:55:22.644160 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10948 19:55:22.644311 Waiting using forced prompt support (timeout 00:02:30)
10949 19:55:22.649893
10950 19:55:22.650295 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10951 19:55:22.650459 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
10952 19:55:22.650597 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10953 19:55:22.650718 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
10954 19:55:22.650828 end: 2 depthcharge-action (duration 00:01:36) [common]
10955 19:55:22.650955 start: 3 lava-test-retry (timeout 00:08:00) [common]
10956 19:55:22.651070 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
10957 19:55:22.651171 Using namespace: common
10959 19:55:22.751571 / # #
10960 19:55:22.751788 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10961 19:55:22.757250 #
10962 19:55:22.757530 Using /lava-11899565
10964 19:55:22.857855 / # export SHELL=/bin/sh
10965 19:55:22.863504 export SHELL=/bin/sh
10967 19:55:22.964385 / # . /lava-11899565/environment
10968 19:55:22.971255 . /lava-11899565/environment
10970 19:55:23.073047 / # /lava-11899565/bin/lava-test-runner /lava-11899565/0
10971 19:55:23.073630 Test shell timeout: 10s (minimum of the action and connection timeout)
10972 19:55:23.079892 /lava-11899565/bin/lava-test-runner /lava-11899565/0
10973 19:55:23.103448 + export TESTRUN_ID=0_igt-gpu-panfrost
10974 19:55:23.113339 + cd /lava-11899565/0/tests/0_igt-gpu-pa<8>[ 19.069715] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 11899565_1.5.2.3.1>
10975 19:55:23.113776 nfrost
10976 19:55:23.114111 + cat uuid
10977 19:55:23.114795 Received signal: <STARTRUN> 0_igt-gpu-panfrost 11899565_1.5.2.3.1
10978 19:55:23.115215 Starting test lava.0_igt-gpu-panfrost (11899565_1.5.2.3.1)
10979 19:55:23.115882 Skipping test definition patterns.
10980 19:55:23.116680 + UUID=11899565_1.5.2.3.1
10981 19:55:23.117063 + set +x
10982 19:55:23.126131 + IGT_FORCE_DRIVER=panfrost /usr/bin/ig<8>[ 19.086262] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10983 19:55:23.126851 Received signal: <TESTSET> START panfrost_gem_new
10984 19:55:23.127252 Starting test_set panfrost_gem_new
10985 19:55:23.132808 t-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
10986 19:55:23.136210 <14>[ 19.098608] [IGT] panfrost_gem_new: executing
10987 19:55:23.143399 IGT-Version: 1.2<14>[ 19.100807] [IGT] panfrost_gem_new: exiting, ret=77
10988 19:55:23.152951 7.1-g621c2d3 (aa<8>[ 19.107454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10989 19:55:23.153687 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10991 19:55:23.156370 rch64) (Linux: 6.1.59-cip8-rt4 aarch64)
10992 19:55:23.163345 Test re<14>[ 19.122459] [IGT] panfrost_gem_new: executing
10993 19:55:23.170345 quirement not me<14>[ 19.124488] [IGT] panfrost_gem_new: exiting, ret=77
10994 19:55:23.176093 t in function dr<8>[ 19.131084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10995 19:55:23.176900 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10997 19:55:23.180114 m_open_driver, file ../lib/drmtest.c:621:
10998 19:55:23.183060 Test requirement: !(fd<0)
10999 19:55:23.189956 No known gpu found for chi<14>[ 19.152876] [IGT] panfrost_gem_new: executing
11000 19:55:23.192710 pset flags 0x32 (panfrost)
11001 19:55:23.196022 Last<14>[ 19.159087] [IGT] panfrost_gem_new: exiting, ret=77
11002 19:55:23.206692 errno: 2, No su<8>[ 19.164262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11003 19:55:23.207490 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11005 19:55:23.209734 Received signal: <TESTSET> STOP
11006 19:55:23.210164 Closing test_set panfrost_gem_new
11007 19:55:23.212896 ch file or direc<8>[ 19.165581] <LAVA_SIGNAL_TESTSET STOP>
11008 19:55:23.213418 tory
11009 19:55:23.219704 [1mSubtes<8>[ 19.181049] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11010 19:55:23.220506 Received signal: <TESTSET> START panfrost_get_param
11011 19:55:23.220872 Starting test_set panfrost_get_param
11012 19:55:23.222720 t gem-new-4096: SKIP (0.000s)[0m
11013 19:55:23.229779 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11014 19:55:23.233277 Test<14>[ 19.193642] [IGT] panfrost_get_param: executing
11015 19:55:23.239498 requirement not<14>[ 19.195662] [IGT] panfrost_get_param: exiting, ret=77
11016 19:55:23.249318 met in function<8>[ 19.201781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11017 19:55:23.250111 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11019 19:55:23.252994 drm_open_driver, file ../lib/drmtest.c:621:
11020 19:55:23.256016 Te<14>[ 19.217738] [IGT] panfrost_get_param: executing
11021 19:55:23.262926 st requirement: <14>[ 19.219749] [IGT] panfrost_get_param: exiting, ret=77
11022 19:55:23.266250 !(fd<0)
11023 19:55:23.272829 No know<8>[ 19.224819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11024 19:55:23.273679 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11026 19:55:23.275601 n gpu found for chipset flags 0x32 (panfrost)
11027 19:55:23.282470 L<14>[ 19.241987] [IGT] panfrost_get_param: executing
11028 19:55:23.288955 ast errno: 2, No<14>[ 19.244021] [IGT] panfrost_get_param: exiting, ret=77
11029 19:55:23.296390 such file or di<8>[ 19.248842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11030 19:55:23.297241 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11032 19:55:23.299011 rectory
11033 19:55:23.302654 [1mSub<8>[ 19.250706] <LAVA_SIGNAL_TESTSET STOP>
11034 19:55:23.303487 Received signal: <TESTSET> STOP
11035 19:55:23.303933 Closing test_set panfrost_get_param
11036 19:55:23.309512 test gem-new-0: <8>[ 19.264389] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11037 19:55:23.310037 SKIP (0.000s)[0m
11038 19:55:23.310686 Received signal: <TESTSET> START panfrost_prime
11039 19:55:23.311053 Starting test_set panfrost_prime
11040 19:55:23.319181 IGT-Version: 1.27.1-g621c2d3 <14>[ 19.278887] [IGT] panfrost_prime: executing
11041 19:55:23.325335 (aarch64) (Linux<14>[ 19.281025] [IGT] panfrost_prime: exiting, ret=77
11042 19:55:23.332434 : 6.1.59-cip8-rt<8>[ 19.285871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11043 19:55:23.333237 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11045 19:55:23.335511 <8>[ 19.288552] <LAVA_SIGNAL_TESTSET STOP>
11046 19:55:23.336228 Received signal: <TESTSET> STOP
11047 19:55:23.336696 Closing test_set panfrost_prime
11048 19:55:23.339101 4 aarch64)
11049 19:55:23.345425 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11050 19:55:23.348853 Test requirement: !(fd<0)
11051 19:55:23.351816 No known gpu found for chipset flags 0x32 (panfrost)
11052 19:55:23.359284 Last errno: 2, No<8>[ 19.318691] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11053 19:55:23.360140 Received signal: <TESTSET> START panfrost_submit
11054 19:55:23.360512 Starting test_set panfrost_submit
11055 19:55:23.362287 such file or directory
11056 19:55:23.365632 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11057 19:55:23.371868 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11058 19:55:23.378519 Test requiremen<14>[ 19.339178] [IGT] panfrost_submit: executing
11059 19:55:23.385375 t not met in function drm_open_d<14>[ 19.347163] [IGT] panfrost_submit: exiting, ret=77
11060 19:55:23.391628 <8>[ 19.353796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11061 19:55:23.392354 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11063 19:55:23.395543 river, file ../lib/drmtest.c:621:
11064 19:55:23.399087 Test requirement: !(fd<0)
11065 19:55:23.405429 No known gpu found for chipset fla<14>[ 19.366344] [IGT] panfrost_submit: executing
11066 19:55:23.412233 <14>[ 19.368237] [IGT] panfrost_submit: exiting, ret=77
11067 19:55:23.418301 <8>[ 19.373103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11068 19:55:23.418837 gs 0x32 (panfrost)
11069 19:55:23.419559 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11071 19:55:23.424764 Last errno: 2, No such file or directory
11072 19:55:23.428168 [1mSubtest base-params: SKIP (0.000s)[0m
11073 19:55:23.434841 IGT-Version: 1.27.1-g6<14>[ 19.396097] [IGT] panfrost_submit: executing
11074 19:55:23.441301 21c2d3 (aarch64) (Linux: 6.1.59-<14>[ 19.403592] [IGT] panfrost_submit: exiting, ret=77
11075 19:55:23.451745 cip8-rt4 aarch64<8>[ 19.408868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11076 19:55:23.452249 )
11077 19:55:23.452852 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11079 19:55:23.457793 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11080 19:55:23.461731 Test requirement: !(fd<0)
11081 19:55:23.464420 No known gpu found for chipset flags 0x32 (panfrost)
11082 19:55:23.474727 Last errno: 2, No such fil<14>[ 19.436216] [IGT] panfrost_submit: executing
11083 19:55:23.475247 e or directory
11084 19:55:23.481846 [1mSubtest get-bad-param: SKIP <14>[ 19.442617] [IGT] panfrost_submit: exiting, ret=77
11085 19:55:23.491481 <8>[ 19.447900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11086 19:55:23.492052 (0.000s)[0m
11087 19:55:23.492668 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11089 19:55:23.497986 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11090 19:55:23.505012 Test requirement not met <14>[ 19.467337] [IGT] panfrost_submit: executing
11091 19:55:23.514841 in function drm_open_driver, fil<14>[ 19.475070] [IGT] panfrost_submit: exiting, ret=77
11092 19:55:23.521511 <8>[ 19.479446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11093 19:55:23.522308 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11095 19:55:23.524532 e ../lib/drmtest.c:621:
11096 19:55:23.528288 Test requirement: !(fd<0)
11097 19:55:23.531479 No known gpu found for chipset flags 0x32 (panfrost)
11098 19:55:23.534730 Last errno: 2, No such file or directory
11099 19:55:23.538425 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11100 19:55:23.547739 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-r<14>[ 19.512037] [IGT] panfrost_submit: executing
11101 19:55:23.551377 t4 aarch64)
11102 19:55:23.557869 Test requirement not met in functio<14>[ 19.518674] [IGT] panfrost_submit: exiting, ret=77
11103 19:55:23.568032 <8>[ 19.523853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11104 19:55:23.568890 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11106 19:55:23.574284 n drm_open_drive<14>[ 19.536179] [IGT] panfrost_submit: executing
11107 19:55:23.574818 r, file ../lib/drmtest.c:621:
11108 19:55:23.581159 Test requirement:<14>[ 19.542250] [IGT] panfrost_submit: exiting, ret=77
11109 19:55:23.584698 !(fd<0)
11110 19:55:23.590589 No kno<8>[ 19.547626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11111 19:55:23.591407 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11113 19:55:23.593848 wn gpu found for chipset flags 0x32 (panfrost)
11114 19:55:23.597434 Last errno: 2, No such file or directory
11115 19:55:23.600504 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11116 19:55:23.610564 IGT-Version: 1.27.1-g621c2d3 (aarch64<14>[ 19.570487] [IGT] panfrost_submit: executing
11117 19:55:23.617498 ) (Linux: 6.1.59-cip8-rt4 aarch6<14>[ 19.579715] [IGT] panfrost_submit: exiting, ret=77
11118 19:55:23.618015 4)
11119 19:55:23.627278 Test require<8>[ 19.584919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11120 19:55:23.628138 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11122 19:55:23.634288 ment not met in function drm_open_driver, file ../lib/drmtest.c:621:
11123 19:55:23.634821 Test requirement: !(fd<0)
11124 19:55:23.640488 No known gpu fo<14>[ 19.604927] [IGT] panfrost_submit: executing
11125 19:55:23.650828 und for chipset flags 0x32 (panf<14>[ 19.610881] [IGT] panfrost_submit: exiting, ret=77
11126 19:55:23.656811 <8>[ 19.616267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11127 19:55:23.657585 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11129 19:55:23.660488 <8>[ 19.617779] <LAVA_SIGNAL_TESTSET STOP>
11130 19:55:23.660922 rost)
11131 19:55:23.661620 Received signal: <TESTSET> STOP
11132 19:55:23.661987 Closing test_set panfrost_submit
11133 19:55:23.664395 Last errno: 2, No such file or directory
11134 19:55:23.670784 <8>[ 19.630666] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 11899565_1.5.2.3.1>
11135 19:55:23.671617 Received signal: <ENDRUN> 0_igt-gpu-panfrost 11899565_1.5.2.3.1
11136 19:55:23.672126 Ending use of test pattern.
11137 19:55:23.672516 Ending test lava.0_igt-gpu-panfrost (11899565_1.5.2.3.1), duration 0.56
11139 19:55:23.674233
11140 19:55:23.677498 [1mSubtest pan-submit: SKIP (0.000s)[0m
11141 19:55:23.684220 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11142 19:55:23.690692 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11143 19:55:23.691132 Test requirement: !(fd<0)
11144 19:55:23.697480 No known gpu found for chipset flags 0x32 (panfrost)
11145 19:55:23.700218 Last errno: 2, No such file or directory
11146 19:55:23.704058 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11147 19:55:23.710154 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11148 19:55:23.717082 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11149 19:55:23.720286 Test requirement: !(fd<0)
11150 19:55:23.726987 No known gpu found for chipset flags 0x32 (panfrost)
11151 19:55:23.730095 Last errno: 2, No such file or directory
11152 19:55:23.733443 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11153 19:55:23.740487 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11154 19:55:23.747060 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11155 19:55:23.749862 Test requirement: !(fd<0)
11156 19:55:23.753447 No known gpu found for chipset flags 0x32 (panfrost)
11157 19:55:23.759779 Last errno: 2, No such file or directory
11158 19:55:23.763124 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11159 19:55:23.770299 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11160 19:55:23.777071 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11161 19:55:23.779864 Test requirement: !(fd<0)
11162 19:55:23.783552 No known gpu found for chipset flags 0x32 (panfrost)
11163 19:55:23.789936 Last errno: 2, No such file or directory
11164 19:55:23.793221 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11165 19:55:23.800213 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11166 19:55:23.806461 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11167 19:55:23.810006 Test requirement: !(fd<0)
11168 19:55:23.813053 No known gpu found for chipset flags 0x32 (panfrost)
11169 19:55:23.819756 Last errno: 2, No such file or directory
11170 19:55:23.823290 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11171 19:55:23.829657 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11172 19:55:23.836445 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11173 19:55:23.839869 Test requirement: !(fd<0)
11174 19:55:23.842717 No known gpu found for chipset flags 0x32 (panfrost)
11175 19:55:23.845869 Last errno: 2, No such file or directory
11176 19:55:23.852869 [1mSubtest pan-reset: SKIP (0.000s)[0m
11177 19:55:23.855737 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11178 19:55:23.865808 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11179 19:55:23.866335 Test requirement: !(fd<0)
11180 19:55:23.872649 No known gpu found for chipset flags 0x32 (panfrost)
11181 19:55:23.876105 Last errno: 2, No such file or directory
11182 19:55:23.879583 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11183 19:55:23.885714 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)
11184 19:55:23.892117 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
11185 19:55:23.895341 Test requirement: !(fd<0)
11186 19:55:23.898974 No known gpu found for chipset flags 0x32 (panfrost)
11187 19:55:23.902494 Last errno: 2, No such file or directory
11188 19:55:23.908681 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11189 19:55:23.909185 + set +x
11190 19:55:23.912196 <LAVA_TEST_RUNNER EXIT>
11191 19:55:23.912893 ok: lava_test_shell seems to have completed
11192 19:55:23.914558 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11193 19:55:23.915046 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11194 19:55:23.915463 end: 3 lava-test-retry (duration 00:00:01) [common]
11195 19:55:23.915951 start: 4 finalize (timeout 00:07:59) [common]
11196 19:55:23.916396 start: 4.1 power-off (timeout 00:00:30) [common]
11197 19:55:23.917139 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11198 19:55:24.036203 >> Command sent successfully.
11199 19:55:24.038979 Returned 0 in 0 seconds
11200 19:55:24.139423 end: 4.1 power-off (duration 00:00:00) [common]
11202 19:55:24.139794 start: 4.2 read-feedback (timeout 00:07:58) [common]
11203 19:55:24.140094 Listened to connection for namespace 'common' for up to 1s
11204 19:55:25.141009 Finalising connection for namespace 'common'
11205 19:55:25.141218 Disconnecting from shell: Finalise
11206 19:55:25.141353 / #
11207 19:55:25.241778 end: 4.2 read-feedback (duration 00:00:01) [common]
11208 19:55:25.241972 end: 4 finalize (duration 00:00:01) [common]
11209 19:55:25.242100 Cleaning after the job
11210 19:55:25.242206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/ramdisk
11211 19:55:25.250327 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/kernel
11212 19:55:25.259084 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/dtb
11213 19:55:25.259302 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11899565/tftp-deploy-kk2tey4x/modules
11214 19:55:25.267225 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11899565
11215 19:55:25.388434 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11899565
11216 19:55:25.388618 Job finished correctly