[Enter `^Ec?' for help] F0: 102B 0000 F3: 1001 0000 [0200] F3: 1001 0000 F7: 102D 0000 F1: 0000 0000 V0: 0000 0000 [0001] 00: 0007 8000 01: 0000 0000 BP: 0C00 0209 [0000] G0: 1182 0000 EC: 0000 0021 [4000] S7: 0000 0000 [0000] CC: 0000 0000 [0001] T0: 0000 0040 [010F] Jump to BL coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal Backing address range [0x00000000:0x40000000) with new page table @0x0010f000 Backing address range [0x00000000:0x00200000) with new page table @0x00110000 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal Backing address range [0x00200000:0x00400000) with new page table @0x00111000 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal WDT: Last reset was cold boot SPI1(PAD0) initialized at 2873684 Hz SPI5(PAD0) initialized at 992727 Hz VBOOT: Loading verstage. SF: Detected 00 0000 with sector size 0x1000, total 0x800000 FMAP: Found "FLASH" version 1.1 at 0x20000. FMAP: base = 0x0 size = 0x800000 #areas = 25 FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception FMAP: area RW_NVRAM found @ 57b000 (8192 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 07 00 00 08 00 00 00 in-data: aa e4 47 04 13 02 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 in-header: 03 95 00 00 08 00 00 00 in-data: 18 20 20 08 00 00 00 00 Phase 1 FMAP: area GBB found @ 3f5000 (12032 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7 Recovery requested (1009000e) TPM: Extending digest for VBOOT: boot mode into PCR 0 tlcl_extend: response is 0 TPM: Extending digest for VBOOT: GBB HWID into PCR 1 tlcl_extend: response is 0 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps BS: bootblock times (exec / console): total (unknown) / 148 ms coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception pmic_efuse_setting: Set efuses in 11 msecs pmwrap_interface_init: Select PMIF_VLD_RDY [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2 [RTC]rtc_osc_init,62: osc32con val = 0xde70 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a [RTC]rtc_get_frequency_meter,154: input=15, output=759 [RTC]rtc_get_frequency_meter,154: input=23, output=943 [RTC]rtc_get_frequency_meter,154: input=19, output=850 [RTC]rtc_get_frequency_meter,154: input=17, output=804 [RTC]rtc_get_frequency_meter,154: input=16, output=782 [RTC]rtc_get_frequency_meter,154: input=16, output=780 [RTC]rtc_get_frequency_meter,154: input=17, output=803 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81 ADC[4]: Raw value=905465 ID=7 ADC[3]: Raw value=213441 ID=1 RAM Code: 0x71 FMAP: area COREBOOT found @ 21000 (4014080 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 07 00 00 08 00 00 00 in-data: aa e4 47 04 13 02 00 00 Chrome EC: UHEPI supported out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 in-header: 03 95 00 00 08 00 00 00 in-data: 18 20 20 08 00 00 00 00 MRC: failed to locate region type 0. DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0) DRAM-K: Running full calibration DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE header.status = 0x0 header.version = 0x6 (expected: 0x6) header.size = 0xd00 (expected: 0xd00) header.flags = 0x0 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6 dram_init: ddr_geometry: 2 [EMI] MDL number = 2 [EMI] Get MDL freq = 0 dram_init: ddr_type: 0 is_discrete_lpddr4: 1 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0 [Bian_co] ETT version 0.0.0.1 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6 dramc_set_vcore_voltage set vcore to 650000 Read voltage for 800, 4 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 dram_init: config_dvfs: 1 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9 MEM_TYPE=3, freq_sel=18 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1600 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 800 CA_MCKIO = 800 MCKIO_SEMI = 0 PLL_FREQ = 3068 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1600,PCW = 0X7600 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 40 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 13 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6) [EMI DOE] emi_dcm 0 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 36 (6~67) winsize 62 [CA 1] Center 36 (6~67) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~64) winsize 61 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 32 (2~62) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 34 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (6~67),Diff = 4 PI (28 cell) CA1 delay=36 (6~67),Diff = 4 PI (28 cell) CA2 delay=34 (4~65),Diff = 2 PI (14 cell) CA3 delay=34 (4~64),Diff = 2 PI (14 cell) CA4 delay=33 (3~64),Diff = 1 PI (7 cell) CA5 delay=32 (2~62),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 36 (6~67) winsize 62 [CA 1] Center 36 (6~67) winsize 62 [CA 2] Center 34 (3~65) winsize 63 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 33 (3~63) winsize 61 [CA 5] Center 33 (3~63) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (6~67),Diff = 4 PI (28 cell) CA1 delay=36 (6~67),Diff = 4 PI (28 cell) CA2 delay=34 (4~65),Diff = 2 PI (14 cell) CA3 delay=34 (4~64),Diff = 2 PI (14 cell) CA4 delay=33 (3~63),Diff = 1 PI (7 cell) CA5 delay=32 (3~62),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~36) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 32 => 32 Write leveling (Byte 1): 30 => 30 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1) 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0) 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0) 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1) 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0) 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0) 0 10 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0) 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 2e2e 3e3d | 0 1 | (0 0) (0 0) 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 6) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 10) best DQS0 dly(MCK, UI, PI) = (0, 14, 6) best DQS1 dly(MCK, UI, PI) = (0, 14, 10) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 89, DQM1 = 82 DQ Delay: DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6) Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6) Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref=22, minBit 9, minWin=27, winSum=450 TX Vref=24, minBit 10, minWin=27, winSum=453 TX Vref=26, minBit 10, minWin=27, winSum=452 TX Vref=28, minBit 8, minWin=28, winSum=457 TX Vref=30, minBit 0, minWin=28, winSum=459 TX Vref=32, minBit 6, minWin=28, winSum=457 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6) Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6) Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH0 RK0 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0x0, sum = 1 10, 0x0, sum = 2 11, 0x0, sum = 3 12, 0x0, sum = 4 best_step = 10 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -95 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Set Vref, RX VrefLevel [Byte0]: 75 [Byte1]: 75 Set Vref, RX VrefLevel [Byte0]: 76 [Byte1]: 76 Set Vref, RX VrefLevel [Byte0]: 77 [Byte1]: 77 Final RX Vref Byte 0 = 56 to rank0 Final RX Vref Byte 1 = 61 to rank0 Final RX Vref Byte 0 = 56 to rank1 Final RX Vref Byte 1 = 61 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 92, DQM1 = 85 DQ Delay: DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps CH0 RK0: MR19=606, MR18=4D43 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 35 => 35 Write leveling (Byte 1): 30 => 30 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1) 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0) 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 8 | B1->B0 | 2b2b 2a2a | 0 0 | (1 1) (0 0) 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1) 0 10 8 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0) 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2424 2a2a | 1 1 | (0 0) (0 0) 0 11 8 | B1->B0 | 3939 3a3a | 1 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 8) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 8) best DQS0 dly(MCK, UI, PI) = (0, 14, 8) best DQS1 dly(MCK, UI, PI) = (0, 14, 8) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 92, DQM1 = 82 DQ Delay: DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7) Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7) == TX Byte 1 == Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6) Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref=22, minBit 5, minWin=27, winSum=447 TX Vref=24, minBit 1, minWin=28, winSum=452 TX Vref=26, minBit 1, minWin=28, winSum=455 TX Vref=28, minBit 1, minWin=28, winSum=458 TX Vref=30, minBit 2, minWin=28, winSum=452 TX Vref=32, minBit 10, minWin=27, winSum=452 [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 28 Final TX Range 1 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7) Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7) == TX Byte 1 == Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6) Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH0 RK1 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0x0, sum = 1 10, 0x0, sum = 2 11, 0x0, sum = 3 12, 0x0, sum = 4 best_step = 10 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -95 -> 252, step: 8 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 93, DQM1 = 83 DQ Delay: DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92 [DQSOSCAuto] RK1, (LSB)MR18= 0x4112, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps CH0 RK1: MR19=606, MR18=4112 CH0_RK1: MR19=0x606, MR18=0x4112, DQSOSC=393, MR23=63, INC=95, DEC=63 [RxdqsGatingPostProcess] freq 800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 36 (6~67) winsize 62 [CA 1] Center 36 (6~67) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~64) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (6~67),Diff = 2 PI (14 cell) CA1 delay=36 (6~67),Diff = 2 PI (14 cell) CA2 delay=34 (4~65),Diff = 0 PI (0 cell) CA3 delay=34 (4~65),Diff = 0 PI (0 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (4~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 6 (0~37) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34 [CA 0] Center 36 (6~67) winsize 62 [CA 1] Center 36 (6~67) winsize 62 [CA 2] Center 35 (4~66) winsize 63 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~65) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 32 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (6~67),Diff = 2 PI (14 cell) CA1 delay=36 (6~67),Diff = 2 PI (14 cell) CA2 delay=34 (4~65),Diff = 0 PI (0 cell) CA3 delay=34 (4~65),Diff = 0 PI (0 cell) CA4 delay=34 (4~65),Diff = 0 PI (0 cell) CA5 delay=34 (4~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 6 (0~38) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 27 => 27 Write leveling (Byte 1): 30 => 30 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1) 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0) 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1) 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1) 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1) 0 10 4 | B1->B0 | 3131 2e2e | 1 1 | (1 0) (1 0) 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0) 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 2a2a 3333 | 0 1 | (0 0) (0 0) 0 11 8 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 4) 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 6) best DQS0 dly(MCK, UI, PI) = (0, 14, 6) best DQS1 dly(MCK, UI, PI) = (0, 14, 4) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 92, DQM1 = 87 DQ Delay: DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6) Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref=22, minBit 0, minWin=26, winSum=434 TX Vref=24, minBit 1, minWin=27, winSum=440 TX Vref=26, minBit 1, minWin=27, winSum=444 TX Vref=28, minBit 0, minWin=27, winSum=445 TX Vref=30, minBit 1, minWin=27, winSum=446 TX Vref=32, minBit 2, minWin=26, winSum=444 [TxChooseVref] Worse bit 1, Min win 27, Win sum 446, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6) Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH1 RK0 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0x0, sum = 1 10, 0x0, sum = 2 11, 0x0, sum = 3 12, 0x0, sum = 4 best_step = 10 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -79 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Final RX Vref Byte 0 = 57 to rank0 Final RX Vref Byte 1 = 58 to rank0 Final RX Vref Byte 0 = 57 to rank1 Final RX Vref Byte 1 = 58 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 95, DQM1 = 89 DQ Delay: DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps CH1 RK0: MR19=606, MR18=2E49 CH1_RK0: MR19=0x606, MR18=0x2E49, DQSOSC=391, MR23=63, INC=96, DEC=64 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 26 => 26 Write leveling (Byte 1): 31 => 31 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6) 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1) 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0) 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0) 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0) 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1) 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 4 | B1->B0 | 2c2c 2322 | 0 1 | (0 0) (0 0) 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0) 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1) 0 10 4 | B1->B0 | 2b2b 3232 | 0 0 | (1 0) (0 1) 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 3c3c 2b2b | 0 1 | (0 0) (0 0) 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 4) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 4) best DQS0 dly(MCK, UI, PI) = (0, 14, 4) best DQS1 dly(MCK, UI, PI) = (0, 14, 4) best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4) best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -130 -> 252, step: 16 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 10, Center 93 (-2 ~ 189) 192 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 96, DQM1 = 91 DQ Delay: DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =93 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6) Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref=22, minBit 1, minWin=26, winSum=439 TX Vref=24, minBit 1, minWin=26, winSum=444 TX Vref=26, minBit 0, minWin=27, winSum=445 TX Vref=28, minBit 1, minWin=27, winSum=446 TX Vref=30, minBit 2, minWin=27, winSum=450 TX Vref=32, minBit 0, minWin=27, winSum=447 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6) Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6) Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6) [DATLAT] Freq=800, CH1 RK1 DATLAT Default: 0xa 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0x0, sum = 1 10, 0x0, sum = 2 11, 0x0, sum = 3 12, 0x0, sum = 4 best_step = 10 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -79 -> 252, step: 8 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 97, DQM1 = 91 DQ Delay: DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96 [DQSOSCAuto] RK1, (LSB)MR18= 0x430d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps CH1 RK1: MR19=606, MR18=430D CH1_RK1: MR19=0x606, MR18=0x430D, DQSOSC=393, MR23=63, INC=95, DEC=63 [RxdqsGatingPostProcess] freq 800 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1600 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [GetDramInforAfterCalByMRR] Vendor 6. [GetDramInforAfterCalByMRR] Revision 606. [GetDramInforAfterCalByMRR] Revision 2 0. MR0 0x3b3b MR8 0x5151 RK0, DieNum 2, Density 16Gb, RKsize 32Gb. MR0 0x3b3b MR8 0x5151 RK1, DieNum 2, Density 16Gb, RKsize 32Gb. [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc [FAST_K] Save calibration result to emmc dram_init: config_dvfs: 1 dramc_set_vcore_voltage set vcore to 662500 Read voltage for 1200, 2 Vio18 = 0 Vcore = 662500 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=15 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 0 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 2400 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 0 CA_PREDIV_EN = 0 PH8_DLY = 17 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 1200 CA_MCKIO = 1200 MCKIO_SEMI = 0 PLL_FREQ = 2366 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 2400,PCW = 0X5b00 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] DLL <<<<<<<< [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x4 RL = 0x4 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Duty_Offset_Calibration] B0:2 B1:1 CA:1 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 22 [0] MIN Duty = 4875%(X100), DQS PI = 0 [0] AVG Duty = 5015%(X100) CH0 CLK Duty spec in!! Max-Min= 281% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = -4 [-4] MAX Duty = 5124%(X100), DQS PI = 22 [-4] MIN Duty = 4751%(X100), DQS PI = 0 [-4] AVG Duty = 4937%(X100) ==DQS 1 == Final DQS duty delay cell = -4 [-4] MAX Duty = 5000%(X100), DQS PI = 62 [-4] MIN Duty = 4844%(X100), DQS PI = 32 [-4] AVG Duty = 4922%(X100) CH0 DQS 0 Duty spec in!! Max-Min= 373% CH0 DQS 1 Duty spec in!! Max-Min= 156% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 30 [0] MIN Duty = 4906%(X100), DQS PI = 50 [0] AVG Duty = 5031%(X100) ==DQM 1 == Final DQM duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 58 [0] MIN Duty = 5031%(X100), DQS PI = 18 [0] AVG Duty = 5093%(X100) CH0 DQM 0 Duty spec in!! Max-Min= 250% CH0 DQM 1 Duty spec in!! Max-Min= 125% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 24 [0] MIN Duty = 4906%(X100), DQS PI = 0 [0] AVG Duty = 4968%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5093%(X100), DQS PI = 10 [0] MIN Duty = 4907%(X100), DQS PI = 36 [0] AVG Duty = 5000%(X100) CH0 DQ 0 Duty spec in!! Max-Min= 125% CH0 DQ 1 Duty spec in!! Max-Min= 186% [DutyScan_Calibration_Flow] ====Done==== == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Duty_Offset_Calibration] B0:1 B1:0 CA:0 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = -4 [-4] MAX Duty = 5031%(X100), DQS PI = 20 [-4] MIN Duty = 4907%(X100), DQS PI = 2 [-4] AVG Duty = 4969%(X100) CH1 CLK Duty spec in!! Max-Min= 124% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5094%(X100), DQS PI = 24 [0] MIN Duty = 4875%(X100), DQS PI = 0 [0] AVG Duty = 4984%(X100) ==DQS 1 == Final DQS duty delay cell = 0 [0] MAX Duty = 5187%(X100), DQS PI = 18 [0] MIN Duty = 4969%(X100), DQS PI = 10 [0] AVG Duty = 5078%(X100) CH1 DQS 0 Duty spec in!! Max-Min= 219% CH1 DQS 1 Duty spec in!! Max-Min= 218% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 6 [0] MIN Duty = 5031%(X100), DQS PI = 0 [0] AVG Duty = 5093%(X100) ==DQM 1 == Final DQM duty delay cell = 0 [0] MAX Duty = 5031%(X100), DQS PI = 16 [0] MIN Duty = 4907%(X100), DQS PI = 36 [0] AVG Duty = 4969%(X100) CH1 DQM 0 Duty spec in!! Max-Min= 125% CH1 DQM 1 Duty spec in!! Max-Min= 124% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 8 [-4] MIN Duty = 4938%(X100), DQS PI = 0 [-4] AVG Duty = 5000%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5125%(X100), DQS PI = 20 [0] MIN Duty = 4969%(X100), DQS PI = 12 [0] AVG Duty = 5047%(X100) CH1 DQ 0 Duty spec in!! Max-Min= 124% CH1 DQ 1 Duty spec in!! Max-Min= 156% [DutyScan_Calibration_Flow] ====Done==== nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 7 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39 [CA 0] Center 39 (8~70) winsize 63 [CA 1] Center 39 (8~70) winsize 63 [CA 2] Center 35 (5~66) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 32 (3~62) winsize 60 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=39 (8~70),Diff = 7 PI (33 cell) CA1 delay=39 (8~70),Diff = 7 PI (33 cell) CA2 delay=35 (5~66),Diff = 3 PI (14 cell) CA3 delay=34 (4~65),Diff = 2 PI (9 cell) CA4 delay=33 (3~64),Diff = 1 PI (4 cell) CA5 delay=32 (3~62),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 6 (0~37) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37 [CA 0] Center 38 (8~69) winsize 62 [CA 1] Center 38 (8~69) winsize 62 [CA 2] Center 35 (4~66) winsize 63 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 32 (3~62) winsize 60 [CmdBusTrainingLP45] Vref(ca) range 1: 35 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=38 (8~69),Diff = 6 PI (28 cell) CA1 delay=38 (8~69),Diff = 6 PI (28 cell) CA2 delay=35 (5~66),Diff = 3 PI (14 cell) CA3 delay=34 (4~65),Diff = 2 PI (9 cell) CA4 delay=33 (3~64),Diff = 1 PI (4 cell) CA5 delay=32 (3~62),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 6 (0~38) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 33 => 33 Write leveling (Byte 1): 29 => 29 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15) 0 15 0 | B1->B0 | 2323 3333 | 1 1 | (0 0) (1 1) 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1) 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0) 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0) 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0) 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0) 1 0 28 | B1->B0 | 2727 4444 | 0 0 | (0 0) (1 1) 1 1 0 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 3, 28) 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 4, 0) best DQS0 dly(MCK, UI, PI) = (1, 3, 28) best DQS1 dly(MCK, UI, PI) = (1, 4, 0) best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28) best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 121, DQM1 = 113 DQ Delay: DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7) Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7) Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref=22, minBit 0, minWin=25, winSum=412 TX Vref=24, minBit 0, minWin=25, winSum=418 TX Vref=26, minBit 0, minWin=26, winSum=423 TX Vref=28, minBit 4, minWin=26, winSum=427 TX Vref=30, minBit 0, minWin=26, winSum=427 TX Vref=32, minBit 0, minWin=26, winSum=429 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 32 Final TX Range 1 Vref 32 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7) Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7) Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7) [DATLAT] Freq=1200, CH0 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -13 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Final RX Vref Byte 0 = 54 to rank0 Final RX Vref Byte 1 = 45 to rank0 Final RX Vref Byte 0 = 54 to rank1 Final RX Vref Byte 1 = 45 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 120, DQM1 = 110 DQ Delay: DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =102 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps CH0 RK0: MR19=404, MR18=160F CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 35 => 35 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15) 0 15 0 | B1->B0 | 3434 2f2e | 0 1 | (0 0) (0 0) 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 28 | B1->B0 | 3232 2d2d | 0 1 | (0 1) (1 0) 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0) 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 24 | B1->B0 | 2727 2726 | 0 1 | (0 0) (0 0) 1 0 28 | B1->B0 | 3636 3c3c | 0 1 | (0 0) (0 0) 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 3, 28) 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 3, 30) best DQS0 dly(MCK, UI, PI) = (1, 3, 30) best DQS1 dly(MCK, UI, PI) = (1, 3, 28) best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30) best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 122, DQM1 = 112 DQ Delay: DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7) Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7) Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref=22, minBit 5, minWin=24, winSum=417 TX Vref=24, minBit 1, minWin=25, winSum=419 TX Vref=26, minBit 1, minWin=26, winSum=424 TX Vref=28, minBit 5, minWin=25, winSum=425 TX Vref=30, minBit 5, minWin=25, winSum=426 TX Vref=32, minBit 5, minWin=25, winSum=426 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 26 Final TX Range 1 Vref 26 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7) Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7) Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7) [DATLAT] Freq=1200, CH0 RK1 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -13 -> 252, step: 4 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 121, DQM1 = 109 DQ Delay: DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100 DQ12 =114, DQ13 =116, DQ14 =120, DQ15 =118 [DQSOSCAuto] RK1, (LSB)MR18= 0xff1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps CH0 RK1: MR19=403, MR18=FF1 CH0_RK1: MR19=0x403, MR18=0xFF1, DQSOSC=404, MR23=63, INC=40, DEC=26 [RxdqsGatingPostProcess] freq 1200 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2 best DQS0 dly(2T, 0.5T) = (0, 11) best DQS1 dly(2T, 0.5T) = (0, 12) best DQS0 P1 dly(2T, 0.5T) = (0, 15) best DQS1 P1 dly(2T, 0.5T) = (1, 0) best DQS0 dly(2T, 0.5T) = (0, 11) best DQS1 dly(2T, 0.5T) = (0, 11) best DQS0 P1 dly(2T, 0.5T) = (0, 15) best DQS1 P1 dly(2T, 0.5T) = (0, 15) Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 37 (7~68) winsize 62 [CA 2] Center 35 (5~65) winsize 61 [CA 3] Center 34 (5~64) winsize 60 [CA 4] Center 34 (4~64) winsize 61 [CA 5] Center 33 (3~63) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 4 PI (19 cell) CA1 delay=37 (7~68),Diff = 4 PI (19 cell) CA2 delay=35 (5~65),Diff = 2 PI (9 cell) CA3 delay=34 (5~64),Diff = 1 PI (4 cell) CA4 delay=34 (4~64),Diff = 1 PI (4 cell) CA5 delay=33 (3~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 7 (0~38) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37 [CA 0] Center 37 (7~68) winsize 62 [CA 1] Center 38 (8~68) winsize 61 [CA 2] Center 35 (5~65) winsize 61 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~64) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 35 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (7~68),Diff = 4 PI (19 cell) CA1 delay=38 (8~68),Diff = 5 PI (24 cell) CA2 delay=35 (5~65),Diff = 2 PI (9 cell) CA3 delay=34 (5~64),Diff = 1 PI (4 cell) CA4 delay=34 (4~64),Diff = 1 PI (4 cell) CA5 delay=33 (4~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 8 (0~40) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 25 => 25 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15) 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 24 | B1->B0 | 3333 2d2d | 1 0 | (1 1) (0 0) 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0) 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 24 | B1->B0 | 3030 4040 | 0 1 | (0 0) (0 0) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 3, 24) 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 3, 26) best DQS0 dly(MCK, UI, PI) = (1, 3, 26) best DQS1 dly(MCK, UI, PI) = (1, 3, 24) best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26) best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 119, DQM1 = 116 DQ Delay: DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119 DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7) Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7) Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref=22, minBit 10, minWin=24, winSum=412 TX Vref=24, minBit 9, minWin=25, winSum=417 TX Vref=26, minBit 1, minWin=26, winSum=425 TX Vref=28, minBit 9, minWin=25, winSum=428 TX Vref=30, minBit 2, minWin=26, winSum=428 TX Vref=32, minBit 2, minWin=26, winSum=428 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 30 Final TX Range 1 Vref 30 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7) Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7) Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7) [DATLAT] Freq=1200, CH1 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 32 -> 127 RX Vref 32 -> 127, step: 1 RX Delay -5 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Final RX Vref Byte 0 = 55 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 55 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 119, DQM1 = 116 DQ Delay: DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =120 DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126 [DQSOSCAuto] RK0, (LSB)MR18= 0x315, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps CH1 RK0: MR19=404, MR18=315 CH1_RK0: MR19=0x404, MR18=0x315, DQSOSC=401, MR23=63, INC=40, DEC=27 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 26 => 26 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15) 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 15 24 | B1->B0 | 2d2d 3434 | 0 0 | (1 0) (0 1) 0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0) 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 0 20 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0) 1 0 24 | B1->B0 | 4343 2727 | 0 0 | (0 0) (0 0) 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0) 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1) 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1) 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 3, 24) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 3, 22) best DQS0 dly(MCK, UI, PI) = (1, 3, 24) best DQS1 dly(MCK, UI, PI) = (1, 3, 22) best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24) best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -40 -> 252, step: 8 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 120, DQM1 = 118 DQ Delay: DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7) Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7) Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref=22, minBit 0, minWin=26, winSum=420 TX Vref=24, minBit 9, minWin=25, winSum=426 TX Vref=26, minBit 2, minWin=26, winSum=426 TX Vref=28, minBit 2, minWin=26, winSum=433 TX Vref=30, minBit 10, minWin=25, winSum=429 TX Vref=32, minBit 9, minWin=26, winSum=434 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 32 Final TX Range 1 Vref 32 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7) Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7) == TX Byte 1 == Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7) Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7) [DATLAT] Freq=1200, CH1 RK1 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0x0, sum = 1 13, 0x0, sum = 2 14, 0x0, sum = 3 15, 0x0, sum = 4 best_step = 13 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -5 -> 252, step: 4 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116 iDelay=195, Bit 4, Center 118 (59 ~ 178) 120 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 120, DQM1 = 117 DQ Delay: DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =126 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps CH1 RK1: MR19=403, MR18=10ED CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26 [RxdqsGatingPostProcess] freq 1200 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2 best DQS0 dly(2T, 0.5T) = (0, 11) best DQS1 dly(2T, 0.5T) = (0, 11) best DQS0 P1 dly(2T, 0.5T) = (0, 15) best DQS1 P1 dly(2T, 0.5T) = (0, 15) best DQS0 dly(2T, 0.5T) = (0, 11) best DQS1 dly(2T, 0.5T) = (0, 11) best DQS0 P1 dly(2T, 0.5T) = (0, 15) best DQS1 P1 dly(2T, 0.5T) = (0, 15) Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 2400 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 650000 Read voltage for 600, 5 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=19 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1200 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 600 CA_MCKIO = 600 MCKIO_SEMI = 0 PLL_FREQ = 2288 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1200,PCW = 0X5800 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 17 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 33 (3~64) winsize 62 [CA 3] Center 33 (2~64) winsize 63 [CA 4] Center 33 (2~64) winsize 63 [CA 5] Center 32 (2~63) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 3 PI (28 cell) CA1 delay=35 (5~66),Diff = 3 PI (28 cell) CA2 delay=33 (3~64),Diff = 1 PI (9 cell) CA3 delay=33 (2~64),Diff = 1 PI (9 cell) CA4 delay=33 (2~64),Diff = 1 PI (9 cell) CA5 delay=32 (2~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 34 (3~65) winsize 63 [CA 3] Center 33 (3~64) winsize 62 [CA 4] Center 32 (2~63) winsize 62 [CA 5] Center 32 (2~63) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 35 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 3 PI (28 cell) CA1 delay=35 (5~66),Diff = 3 PI (28 cell) CA2 delay=33 (3~64),Diff = 1 PI (9 cell) CA3 delay=33 (3~64),Diff = 1 PI (9 cell) CA4 delay=32 (2~63),Diff = 0 PI (0 cell) CA5 delay=32 (2~63),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~36) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 36 => 36 Write leveling (Byte 1): 29 => 29 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9) 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0) 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0) 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 12 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0) 0 10 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0) 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 13, 12) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 13, 18) best DQS0 dly(MCK, UI, PI) = (0, 13, 12) best DQS1 dly(MCK, UI, PI) = (0, 13, 18) best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12) best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 52, DQM1 = 46 DQ Delay: DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6) Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6) Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6) Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH0 RK0 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -163 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 45 Final RX Vref Byte 0 = 54 to rank0 Final RX Vref Byte 1 = 45 to rank0 Final RX Vref Byte 0 = 54 to rank1 Final RX Vref Byte 1 = 45 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 53, DQM1 = 46 DQ Delay: DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52 [DQSOSCAuto] RK0, (LSB)MR18= 0x7467, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps CH0 RK0: MR19=808, MR18=7467 CH0_RK0: MR19=0x808, MR18=0x7467, DQSOSC=388, MR23=63, INC=174, DEC=116 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 36 => 36 Write leveling (Byte 1): 31 => 31 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9) 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1) 0 9 16 | B1->B0 | 2d2d 2424 | 1 0 | (0 0) (0 0) 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 12 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0) 0 10 16 | B1->B0 | 3c3c 4040 | 0 1 | (0 0) (0 0) 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 13, 12) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 13, 14) best DQS0 dly(MCK, UI, PI) = (0, 13, 12) best DQS1 dly(MCK, UI, PI) = (0, 13, 14) best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12) best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 49, DQM1 = 43 DQ Delay: DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6) Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6) Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6) Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH0 RK1 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -163 -> 252, step: 8 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288 iDelay=205, Bit 4, Center 60 (-83 ~ 204) 288 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280 iDelay=205, Bit 7, Center 56 (-83 ~ 196) 280 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280 iDelay=205, Bit 15, Center 56 (-83 ~ 196) 280 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 53, DQM1 = 46 DQ Delay: DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52 DQ4 =60, DQ5 =44, DQ6 =56, DQ7 =56 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40 DQ12 =48, DQ13 =48, DQ14 =56, DQ15 =56 [DQSOSCAuto] RK1, (LSB)MR18= 0x6021, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps CH0 RK1: MR19=808, MR18=6021 CH0_RK1: MR19=0x808, MR18=0x6021, DQSOSC=391, MR23=63, INC=171, DEC=114 [RxdqsGatingPostProcess] freq 600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 35 (5~66) winsize 62 [CA 1] Center 35 (5~66) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=34 (4~65),Diff = 1 PI (9 cell) CA3 delay=34 (4~65),Diff = 1 PI (9 cell) CA4 delay=34 (4~65),Diff = 1 PI (9 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35 [CA 0] Center 36 (5~67) winsize 63 [CA 1] Center 36 (5~67) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (3~65) winsize 63 [CA 4] Center 35 (4~66) winsize 63 [CA 5] Center 34 (3~65) winsize 63 [CmdBusTrainingLP45] Vref(ca) range 1: 35 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=35 (5~66),Diff = 2 PI (19 cell) CA1 delay=35 (5~66),Diff = 2 PI (19 cell) CA2 delay=34 (4~65),Diff = 1 PI (9 cell) CA3 delay=34 (4~65),Diff = 1 PI (9 cell) CA4 delay=34 (4~65),Diff = 1 PI (9 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 6 (0~38) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 31 => 31 Write leveling (Byte 1): 30 => 30 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9) 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 12 | B1->B0 | 2e2e 3030 | 1 1 | (1 1) (1 1) 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 12 | B1->B0 | 3737 3b3b | 0 0 | (1 1) (0 0) 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 13, 10) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 13, 14) best DQS0 dly(MCK, UI, PI) = (0, 13, 10) best DQS1 dly(MCK, UI, PI) = (0, 13, 14) best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10) best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 47, DQM1 = 46 DQ Delay: DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =41 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6) Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH1 RK0 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -163 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 48 Final RX Vref Byte 0 = 55 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 55 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 49, DQM1 = 46 DQ Delay: DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =60 [DQSOSCAuto] RK0, (LSB)MR18= 0x486d, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps CH1 RK0: MR19=808, MR18=486D CH1_RK0: MR19=0x808, MR18=0x486D, DQSOSC=389, MR23=63, INC=173, DEC=115 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 29 => 29 Write leveling (Byte 1): 30 => 30 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9) 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 9 12 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0) 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 10 12 | B1->B0 | 3939 3838 | 0 0 | (0 0) (0 0) 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0) 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1) 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 13, 10) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 13, 10) best DQS0 dly(MCK, UI, PI) = (0, 13, 10) best DQS1 dly(MCK, UI, PI) = (0, 13, 10) best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10) best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -230 -> 252, step: 16 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 50, DQM1 = 46 DQ Delay: DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) == TX Byte 1 == Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6) Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6) [DATLAT] Freq=600, CH1 RK1 DATLAT Default: 0x9 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0x0, sum = 1 9, 0x0, sum = 2 10, 0x0, sum = 3 11, 0x0, sum = 4 best_step = 9 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -163 -> 252, step: 8 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 48, DQM1 = 45 DQ Delay: DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52 [DQSOSCAuto] RK1, (LSB)MR18= 0x6e25, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 389 ps CH1 RK1: MR19=808, MR18=6E25 CH1_RK1: MR19=0x808, MR18=0x6E25, DQSOSC=389, MR23=63, INC=173, DEC=115 [RxdqsGatingPostProcess] freq 600 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1 Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1200 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 662500 Read voltage for 933, 3 Vio18 = 0 Vcore = 662500 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=17 sv_algorithm_assistance_LP4_1600 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 1866 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 1 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 933 CA_MCKIO = 933 MCKIO_SEMI = 0 PLL_FREQ = 3732 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 1866,PCW = 0X8f00 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x3 RL = 0x3 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 9 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (3~65) winsize 63 [CA 4] Center 33 (3~64) winsize 62 [CA 5] Center 32 (2~62) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 5 PI (31 cell) CA1 delay=37 (6~68),Diff = 5 PI (31 cell) CA2 delay=34 (4~65),Diff = 2 PI (12 cell) CA3 delay=34 (3~65),Diff = 2 PI (12 cell) CA4 delay=33 (3~64),Diff = 1 PI (6 cell) CA5 delay=32 (2~62),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~36) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (6~68) winsize 63 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (3~65) winsize 63 [CA 4] Center 32 (2~63) winsize 62 [CA 5] Center 32 (2~62) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 35 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=37 (6~68),Diff = 5 PI (31 cell) CA1 delay=37 (6~68),Diff = 5 PI (31 cell) CA2 delay=34 (4~65),Diff = 2 PI (12 cell) CA3 delay=34 (3~65),Diff = 2 PI (12 cell) CA4 delay=33 (3~63),Diff = 1 PI (6 cell) CA5 delay=32 (2~62),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=32 [CBTSetCACLKResult] CA Dly = 32 CS Dly: 5 (0~37) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 33 => 33 Write leveling (Byte 1): 29 => 29 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14) 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1) 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0) 0 14 28 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0) 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0) 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0) 0 15 28 | B1->B0 | 2424 4242 | 0 1 | (0 0) (1 1) 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 2, 28) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 3, 0) best DQS0 dly(MCK, UI, PI) = (1, 2, 28) best DQS1 dly(MCK, UI, PI) = (1, 3, 0) best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28) best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 105, DQM1 = 94 DQ Delay: DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =115 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3) Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3) == TX Byte 1 == Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2) Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3) Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3) == TX Byte 1 == Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2) Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH0 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -45 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 45 Final RX Vref Byte 0 = 54 to rank0 Final RX Vref Byte 1 = 45 to rank0 Final RX Vref Byte 0 = 54 to rank1 Final RX Vref Byte 1 = 45 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 104, DQM1 = 95 DQ Delay: DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110 DQ8 =84, DQ9 =84, DQ10 =98, DQ11 =88 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps CH0 RK0: MR19=505, MR18=2E26 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 34 => 34 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14) 0 14 0 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0) 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1) 0 14 28 | B1->B0 | 2a2a 2a2a | 0 0 | (0 0) (0 0) 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0) 0 15 28 | B1->B0 | 3535 3433 | 0 1 | (0 0) (0 0) 1 0 0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (1 1) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 2, 28) 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 2, 30) best DQS0 dly(MCK, UI, PI) = (1, 2, 28) best DQS1 dly(MCK, UI, PI) = (1, 2, 30) best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28) best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 104, DQM1 = 93 DQ Delay: DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3) Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3) Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH0 RK1 DATLAT Default: 0xb 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -53 -> 252, step: 4 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172 iDelay=199, Bit 8, Center 84 (3 ~ 166) 164 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 104, DQM1 = 93 DQ Delay: DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102 DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =112 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e06, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps CH0 RK1: MR19=505, MR18=2E06 CH0_RK1: MR19=0x505, MR18=0x2E06, DQSOSC=407, MR23=63, INC=65, DEC=43 [RxdqsGatingPostProcess] freq 933 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2 best DQS0 dly(2T, 0.5T) = (0, 10) best DQS1 dly(2T, 0.5T) = (0, 11) best DQS0 P1 dly(2T, 0.5T) = (0, 14) best DQS1 P1 dly(2T, 0.5T) = (0, 15) best DQS0 dly(2T, 0.5T) = (0, 10) best DQS1 dly(2T, 0.5T) = (0, 10) best DQS0 P1 dly(2T, 0.5T) = (0, 14) best DQS1 P1 dly(2T, 0.5T) = (0, 14) Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (6~67) winsize 62 [CA 1] Center 36 (6~67) winsize 62 [CA 2] Center 34 (4~65) winsize 62 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 34 (4~64) winsize 61 [CA 5] Center 33 (3~64) winsize 62 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (6~67),Diff = 3 PI (18 cell) CA1 delay=36 (6~67),Diff = 3 PI (18 cell) CA2 delay=34 (4~65),Diff = 1 PI (6 cell) CA3 delay=34 (4~65),Diff = 1 PI (6 cell) CA4 delay=34 (4~64),Diff = 1 PI (6 cell) CA5 delay=33 (3~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=33 [CBTSetCACLKResult] CA Dly = 33 CS Dly: 7 (0~38) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35 [CA 0] Center 37 (6~68) winsize 63 [CA 1] Center 37 (7~68) winsize 62 [CA 2] Center 35 (4~66) winsize 63 [CA 3] Center 34 (4~65) winsize 62 [CA 4] Center 34 (4~65) winsize 62 [CA 5] Center 34 (4~64) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 1: 35 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (6~67),Diff = 2 PI (12 cell) CA1 delay=37 (7~67),Diff = 3 PI (18 cell) CA2 delay=34 (4~65),Diff = 0 PI (0 cell) CA3 delay=34 (4~65),Diff = 0 PI (0 cell) CA4 delay=34 (4~64),Diff = 0 PI (0 cell) CA5 delay=34 (4~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=34 [CBTSetCACLKResult] CA Dly = 34 CS Dly: 8 (0~40) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 23 => 23 Write leveling (Byte 1): 26 => 26 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14) 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1) 0 14 28 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0) 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0) 0 15 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0) 0 15 28 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 2, 26) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 2, 26) best DQS0 dly(MCK, UI, PI) = (1, 2, 26) best DQS1 dly(MCK, UI, PI) = (1, 2, 26) best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26) best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 102, DQM1 = 98 DQ Delay: DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2) Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2) Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2) Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2) Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH1 RK0 DATLAT Default: 0xd 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -45 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 48 Final RX Vref Byte 0 = 55 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 55 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 103, DQM1 = 99 DQ Delay: DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =98 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =106 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =96 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108 [DQSOSCAuto] RK0, (LSB)MR18= 0x162d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps CH1 RK0: MR19=505, MR18=162D CH1_RK0: MR19=0x505, MR18=0x162D, DQSOSC=407, MR23=63, INC=65, DEC=43 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 28 => 28 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14) 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0) 0 14 24 | B1->B0 | 2d2d 3030 | 0 1 | (0 1) (1 0) 0 14 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0) 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 15 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0) 0 15 24 | B1->B0 | 3737 2d2d | 0 0 | (0 0) (0 0) 0 15 28 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0) 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 2, 26) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 2, 26) best DQS0 dly(MCK, UI, PI) = (1, 2, 26) best DQS1 dly(MCK, UI, PI) = (1, 2, 26) best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26) best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -80 -> 252, step: 8 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 102, DQM1 = 98 DQ Delay: DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2) Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2) Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2) == TX Byte 1 == Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2) Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2) [DATLAT] Freq=933, CH1 RK1 DATLAT Default: 0xb 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0x0, sum = 1 11, 0x0, sum = 2 12, 0x0, sum = 3 13, 0x0, sum = 4 best_step = 11 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -45 -> 252, step: 4 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172 iDelay=203, Bit 8, Center 86 (-1 ~ 174) 176 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 105, DQM1 = 99 DQ Delay: DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104 DQ8 =86, DQ9 =88, DQ10 =100, DQ11 =92 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =110 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps CH1 RK1: MR19=504, MR18=2AFE CH1_RK1: MR19=0x504, MR18=0x2AFE, DQSOSC=408, MR23=63, INC=65, DEC=43 [RxdqsGatingPostProcess] freq 933 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2 best DQS0 dly(2T, 0.5T) = (0, 10) best DQS1 dly(2T, 0.5T) = (0, 10) best DQS0 P1 dly(2T, 0.5T) = (0, 14) best DQS1 P1 dly(2T, 0.5T) = (0, 14) best DQS0 dly(2T, 0.5T) = (0, 10) best DQS1 dly(2T, 0.5T) = (0, 10) best DQS0 P1 dly(2T, 0.5T) = (0, 14) best DQS1 P1 dly(2T, 0.5T) = (0, 14) Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 1866 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 650000 Read voltage for 400, 6 Vio18 = 0 Vcore = 650000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=20 sv_algorithm_assistance_LP4_800 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 1 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 1 NEW_8X_MODE = 1 =================================== =================================== data_rate = 800 CKR = 1 DQ_P2S_RATIO = 4 =================================== CA_P2S_RATIO = 4 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 1 CA_SEMI_OPEN = 1 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 1 CA_PREDIV_EN = 0 PH8_DLY = 0 SEMI_OPEN_CA_PICK_MCK_RATIO= 4 DQ_AAMCK_DIV = 0 CA_AAMCK_DIV = 0 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 800 CA_MCKIO = 400 MCKIO_SEMI = 400 PLL_FREQ = 3016 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 32 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 800,PCW = 0X7400 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 0 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x0 WL = 0x2 RL = 0x2 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x0 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 19 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 35 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == Write leveling (Byte 0): 40 => 8 Write leveling (Byte 1): 40 => 8 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 24) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 24) best DQS0 dly(MCK, UI, PI) = (0, 14, 24) best DQS1 dly(MCK, UI, PI) = (0, 14, 24) best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24) best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == DQS Delay: DQS0 = 27, DQS1 = 35 DQM Delay: DQM0 = 12, DQM1 = 12 DQ Delay: DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3) Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3) Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3) Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3) Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH0 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -311 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 45 Final RX Vref Byte 0 = 54 to rank0 Final RX Vref Byte 1 = 45 to rank0 Final RX Vref Byte 0 = 54 to rank1 Final RX Vref Byte 1 = 45 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == DQS Delay: DQS0 = 28, DQS1 = 36 DQM Delay: DQM0 = 11, DQM1 = 12 DQ Delay: DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps CH0 RK0: MR19=C0C, MR18=C8B5 CH0_RK0: MR19=0xC0C, MR18=0xC8B5, DQSOSC=385, MR23=63, INC=398, DEC=265 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 24) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 24) best DQS0 dly(MCK, UI, PI) = (0, 14, 24) best DQS1 dly(MCK, UI, PI) = (0, 14, 24) best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24) best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == DQS Delay: DQS0 = 27, DQS1 = 35 DQM Delay: DQM0 = 12, DQM1 = 12 DQ Delay: DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3) Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3) Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3) Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3) Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH0 RK1 DATLAT Default: 0xe 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -311 -> 252, step: 8 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == DQS Delay: DQS0 = 24, DQS1 = 36 DQM Delay: DQM0 = 8, DQM1 = 12 DQ Delay: DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20 [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5c, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps CH0 RK1: MR19=C0C, MR18=BD5C CH0_RK1: MR19=0xC0C, MR18=0xBD5C, DQSOSC=386, MR23=63, INC=396, DEC=264 [RxdqsGatingPostProcess] freq 400 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 best DQS0 dly(2T, 0.5T) = (0, 10) best DQS1 dly(2T, 0.5T) = (0, 10) best DQS0 P1 dly(2T, 0.5T) = (0, 12) best DQS1 P1 dly(2T, 0.5T) = (0, 12) best DQS0 dly(2T, 0.5T) = (0, 10) best DQS1 dly(2T, 0.5T) = (0, 10) best DQS0 P1 dly(2T, 0.5T) = (0, 12) best DQS1 P1 dly(2T, 0.5T) = (0, 12) Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 37 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35 [CA 0] Center 36 (8~64) winsize 57 [CA 1] Center 36 (8~64) winsize 57 [CA 2] Center 36 (8~64) winsize 57 [CA 3] Center 36 (8~64) winsize 57 [CA 4] Center 36 (8~64) winsize 57 [CA 5] Center 36 (8~64) winsize 57 [CmdBusTrainingLP45] Vref(ca) range 1: 35 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 270/100 ps CA0 delay=36 (8~64),Diff = 0 PI (0 cell) CA1 delay=36 (8~64),Diff = 0 PI (0 cell) CA2 delay=36 (8~64),Diff = 0 PI (0 cell) CA3 delay=36 (8~64),Diff = 0 PI (0 cell) CA4 delay=36 (8~64),Diff = 0 PI (0 cell) CA5 delay=36 (8~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=36 [CBTSetCACLKResult] CA Dly = 36 CS Dly: 1 (0~32) ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == Write leveling (Byte 0): 40 => 8 Write leveling (Byte 1): 40 => 8 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 24) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 24) best DQS0 dly(MCK, UI, PI) = (0, 14, 24) best DQS1 dly(MCK, UI, PI) = (0, 14, 24) best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24) best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == DQS Delay: DQS0 = 35, DQS1 = 35 DQM Delay: DQM0 = 18, DQM1 = 13 DQ Delay: DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3) Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3) Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3) Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3) Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH1 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == RX Vref Scan: 1 RX Vref 0 -> 0, step: 1 RX Delay -311 -> 252, step: 8 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 48 Final RX Vref Byte 0 = 55 to rank0 Final RX Vref Byte 1 = 48 to rank0 Final RX Vref Byte 0 = 55 to rank1 Final RX Vref Byte 1 = 48 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == DQS Delay: DQS0 = 32, DQS1 = 32 DQM Delay: DQM0 = 14, DQM1 = 11 DQ Delay: DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps CH1 RK0: MR19=C0C, MR18=90C7 CH1_RK0: MR19=0xC0C, MR18=0x90C7, DQSOSC=385, MR23=63, INC=398, DEC=265 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11) 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 0, 14, 24) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 0, 14, 24) best DQS0 dly(MCK, UI, PI) = (0, 14, 24) best DQS1 dly(MCK, UI, PI) = (0, 14, 24) best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24) best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -410 -> 252, step: 16 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == DQS Delay: DQS0 = 35, DQS1 = 35 DQM Delay: DQM0 = 18, DQM1 = 13 DQ Delay: DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3) Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3) Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3) Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3) Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3) [DATLAT] Freq=400, CH1 RK1 DATLAT Default: 0xe 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFFF, sum = 0 13, 0x0, sum = 1 14, 0x0, sum = 2 15, 0x0, sum = 3 16, 0x0, sum = 4 best_step = 14 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay -311 -> 252, step: 8 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2 == DQS Delay: DQS0 = 28, DQS1 = 32 DQM Delay: DQM0 = 11, DQM1 = 11 DQ Delay: DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =4 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20 [DQSOSCAuto] RK1, (LSB)MR18= 0xc152, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps CH1 RK1: MR19=C0C, MR18=C152 CH1_RK1: MR19=0xC0C, MR18=0xC152, DQSOSC=385, MR23=63, INC=398, DEC=265 [RxdqsGatingPostProcess] freq 400 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 best DQS0 dly(2T, 0.5T) = (0, 10) best DQS1 dly(2T, 0.5T) = (0, 10) best DQS0 P1 dly(2T, 0.5T) = (0, 12) best DQS1 P1 dly(2T, 0.5T) = (0, 12) best DQS0 dly(2T, 0.5T) = (0, 10) best DQS1 dly(2T, 0.5T) = (0, 10) best DQS0 P1 dly(2T, 0.5T) = (0, 12) best DQS1 P1 dly(2T, 0.5T) = (0, 12) Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 800 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : NO K RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : NO K RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : NO K All Pass. DramC Write-DBI off PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0 [FAST_K] Save calibration result to emmc dramc_set_vcore_voltage set vcore to 725000 Read voltage for 1600, 0 Vio18 = 0 Vcore = 725000 Vdram = 0 Vddq = 0 Vmddr = 0 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0 MEM_TYPE=3, freq_sel=13 sv_algorithm_assistance_LP4_3733 ============ PULL DRAM RESETB DOWN ============ ========== PULL DRAM RESETB DOWN end ========= [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== =================================== ANA top config =================================== DLL_ASYNC_EN = 0 ALL_SLAVE_EN = 0 NEW_RANK_MODE = 1 DLL_IDLE_MODE = 1 LP45_APHY_COMB_EN = 1 TX_ODT_DIS = 0 NEW_8X_MODE = 1 =================================== =================================== data_rate = 3200 CKR = 1 DQ_P2S_RATIO = 8 =================================== CA_P2S_RATIO = 8 DQ_CA_OPEN = 0 DQ_SEMI_OPEN = 0 CA_SEMI_OPEN = 0 CA_FULL_RATE = 0 DQ_CKDIV4_EN = 0 CA_CKDIV4_EN = 0 CA_PREDIV_EN = 0 PH8_DLY = 12 SEMI_OPEN_CA_PICK_MCK_RATIO= 0 DQ_AAMCK_DIV = 4 CA_AAMCK_DIV = 4 CA_ADMCK_DIV = 4 DQ_TRACK_CA_EN = 0 CA_PICK = 1600 CA_MCKIO = 1600 MCKIO_SEMI = 0 PLL_FREQ = 3068 DQ_UI_PI_RATIO = 32 CA_UI_PI_RATIO = 0 =================================== =================================== memory_type:LPDDR4 GP_NUM : 10 SRAM_EN : 1 MD32_EN : 0 =================================== [ANA_INIT] >>>>>>>>>>>>>> <<<<<< [CONFIGURE PHASE]: ANA_TX >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL =================================== data_rate = 3200,PCW = 0X7600 =================================== <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL [ANA_INIT] flow start [ANA_INIT] PLL >>>>>>>> [ANA_INIT] PLL <<<<<<<< [ANA_INIT] MIDPI >>>>>>>> [ANA_INIT] MIDPI <<<<<<<< [ANA_INIT] DLL >>>>>>>> [ANA_INIT] DLL <<<<<<<< [ANA_INIT] flow end ============ LP4 DIFF to SE enter ============ ============ LP4 DIFF to SE exit ============ [ANA_INIT] <<<<<<<<<<<<< [Flow] Enable top DCM control >>>>> [Flow] Enable top DCM control <<<<< Enable DLL master slave shuffle ============================================================== Gating Mode config ============================================================== Config description: RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode SELPH_MODE 0: By rank 1: By Phase ============================================================== GAT_TRACK_EN = 1 RX_GATING_MODE = 2 RX_GATING_TRACK_MODE = 2 SELPH_MODE = 1 PICG_EARLY_EN = 1 VALID_LAT_VALUE = 1 ============================================================== Enter into Gating configuration >>>> Exit from Gating configuration <<<< Enter into DVFS_PRE_config >>>>> Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. Exit from DVFS_PRE_config <<<<< Enter into PICG configuration >>>> Exit from PICG configuration <<<< [RX_INPUT] configuration >>>>> [RX_INPUT] configuration <<<<< [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>> [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<< [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x0 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5 =================================== LPDDR4 DRAM CONFIGURATION =================================== EX_ROW_EN[0] = 0x10 EX_ROW_EN[1] = 0x0 LP4Y_EN = 0x0 WORK_FSP = 0x1 WL = 0x5 RL = 0x5 BL = 0x2 RPST = 0x0 RD_PRE = 0x0 WR_PRE = 0x1 WR_PST = 0x1 DBI_WR = 0x0 DBI_RD = 0x0 OTF = 0x1 =================================== [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == [Duty_Offset_Calibration] B0:2 B1:1 CA:1 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = 0 [0] MAX Duty = 5156%(X100), DQS PI = 22 [0] MIN Duty = 4907%(X100), DQS PI = 0 [0] AVG Duty = 5031%(X100) CH0 CLK Duty spec in!! Max-Min= 249% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = -4 [-4] MAX Duty = 5125%(X100), DQS PI = 24 [-4] MIN Duty = 4657%(X100), DQS PI = 0 [-4] AVG Duty = 4891%(X100) ==DQS 1 == Final DQS duty delay cell = 0 [0] MAX Duty = 5187%(X100), DQS PI = 4 [0] MIN Duty = 5031%(X100), DQS PI = 52 [0] AVG Duty = 5109%(X100) CH0 DQS 0 Duty spec in!! Max-Min= 468% CH0 DQS 1 Duty spec in!! Max-Min= 156% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5218%(X100), DQS PI = 32 [0] MIN Duty = 4876%(X100), DQS PI = 58 [0] AVG Duty = 5047%(X100) ==DQM 1 == Final DQM duty delay cell = -4 [-4] MAX Duty = 4969%(X100), DQS PI = 20 [-4] MIN Duty = 4844%(X100), DQS PI = 14 [-4] AVG Duty = 4906%(X100) CH0 DQM 0 Duty spec in!! Max-Min= 342% CH0 DQM 1 Duty spec in!! Max-Min= 125% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = 0 [0] MAX Duty = 5062%(X100), DQS PI = 26 [0] MIN Duty = 4907%(X100), DQS PI = 0 [0] AVG Duty = 4984%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5125%(X100), DQS PI = 6 [0] MIN Duty = 4907%(X100), DQS PI = 34 [0] AVG Duty = 5016%(X100) CH0 DQ 0 Duty spec in!! Max-Min= 155% CH0 DQ 1 Duty spec in!! Max-Min= 218% [DutyScan_Calibration_Flow] ====Done==== == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == [Duty_Offset_Calibration] B0:1 B1:0 CA:0 [DutyScan_Calibration_Flow] k_type=0 ==CLK 0== Final CLK duty delay cell = -4 [-4] MAX Duty = 5000%(X100), DQS PI = 24 [-4] MIN Duty = 4875%(X100), DQS PI = 0 [-4] AVG Duty = 4937%(X100) CH1 CLK Duty spec in!! Max-Min= 125% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=1 ==DQS 0 == Final DQS duty delay cell = 0 [0] MAX Duty = 5094%(X100), DQS PI = 14 [0] MIN Duty = 4875%(X100), DQS PI = 0 [0] AVG Duty = 4984%(X100) ==DQS 1 == Final DQS duty delay cell = 0 [0] MAX Duty = 5249%(X100), DQS PI = 16 [0] MIN Duty = 4969%(X100), DQS PI = 6 [0] AVG Duty = 5109%(X100) CH1 DQS 0 Duty spec in!! Max-Min= 219% CH1 DQS 1 Duty spec in!! Max-Min= 280% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=3 ==DQM 0 == Final DQM duty delay cell = 0 [0] MAX Duty = 5218%(X100), DQS PI = 20 [0] MIN Duty = 5000%(X100), DQS PI = 48 [0] AVG Duty = 5109%(X100) ==DQM 1 == Final DQM duty delay cell = 0 [0] MAX Duty = 5093%(X100), DQS PI = 16 [0] MIN Duty = 4907%(X100), DQS PI = 32 [0] AVG Duty = 5000%(X100) CH1 DQM 0 Duty spec in!! Max-Min= 218% CH1 DQM 1 Duty spec in!! Max-Min= 186% [DutyScan_Calibration_Flow] ====Done==== [DutyScan_Calibration_Flow] k_type=2 ==DQ 0 == Final DQ duty delay cell = -4 [-4] MAX Duty = 5062%(X100), DQS PI = 12 [-4] MIN Duty = 4875%(X100), DQS PI = 46 [-4] AVG Duty = 4968%(X100) ==DQ 1 == Final DQ duty delay cell = 0 [0] MAX Duty = 5124%(X100), DQS PI = 18 [0] MIN Duty = 4938%(X100), DQS PI = 8 [0] AVG Duty = 5031%(X100) CH1 DQ 0 Duty spec in!! Max-Min= 187% CH1 DQ 1 Duty spec in!! Max-Min= 186% [DutyScan_Calibration_Flow] ====Done==== nWR fixed to 30 [ModeRegInit_LP4] CH0 RK0 [ModeRegInit_LP4] CH0 RK1 [ModeRegInit_LP4] CH1 RK0 [ModeRegInit_LP4] CH1 RK1 match AC timing 5 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2) [MiockJmeterHQA] [DramcMiockJmeter] u1RxGatingPI = 0 0 : 4255, 4029 4 : 4363, 4138 8 : 4252, 4027 12 : 4253, 4026 16 : 4253, 4027 20 : 4253, 4026 24 : 4255, 4030 28 : 4252, 4027 32 : 4253, 4027 36 : 4366, 4140 40 : 4253, 4026 44 : 4254, 4029 48 : 4253, 4026 52 : 4361, 4138 56 : 4250, 4027 60 : 4361, 4137 64 : 4250, 4027 68 : 4250, 4026 72 : 4252, 4029 76 : 4252, 4030 80 : 4361, 4137 84 : 4250, 4027 88 : 4360, 215 92 : 4361, 0 96 : 4361, 0 100 : 4252, 0 104 : 4249, 0 108 : 4250, 0 112 : 4361, 0 116 : 4361, 0 120 : 4250, 0 124 : 4250, 0 128 : 4250, 0 132 : 4252, 0 136 : 4253, 0 140 : 4250, 0 144 : 4252, 0 148 : 4361, 0 152 : 4251, 0 156 : 4250, 0 160 : 4250, 0 164 : 4360, 0 168 : 4360, 0 172 : 4250, 0 176 : 4250, 0 180 : 4250, 0 184 : 4252, 0 188 : 4250, 0 192 : 4250, 0 196 : 4253, 0 200 : 4363, 0 204 : 4250, 1126 208 : 4250, 4000 212 : 4250, 4027 216 : 4250, 4027 220 : 4249, 4027 224 : 4250, 4026 228 : 4250, 4027 232 : 4252, 4030 236 : 4250, 4027 240 : 4361, 4137 244 : 4361, 4137 248 : 4250, 4027 252 : 4363, 4140 256 : 4361, 4137 260 : 4250, 4026 264 : 4250, 4027 268 : 4252, 4030 272 : 4250, 4026 276 : 4250, 4026 280 : 4250, 4027 284 : 4252, 4030 288 : 4250, 4027 292 : 4361, 4137 296 : 4361, 4137 300 : 4250, 4027 304 : 4364, 4140 308 : 4252, 3978 312 : 4250, 1762 MIOCK jitter meter ch=0 1T = (312-88) = 224 dly cells Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 42 (12~73) winsize 62 [CA 1] Center 42 (12~73) winsize 62 [CA 2] Center 37 (8~67) winsize 60 [CA 3] Center 37 (7~67) winsize 61 [CA 4] Center 36 (6~66) winsize 61 [CA 5] Center 35 (6~64) winsize 59 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 290/100 ps CA0 delay=42 (12~73),Diff = 7 PI (23 cell) CA1 delay=42 (12~73),Diff = 7 PI (23 cell) CA2 delay=37 (8~67),Diff = 2 PI (6 cell) CA3 delay=37 (7~67),Diff = 2 PI (6 cell) CA4 delay=36 (6~66),Diff = 1 PI (3 cell) CA5 delay=35 (6~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=35 [CBTSetCACLKResult] CA Dly = 35 CS Dly: 9 (0~40) [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 42 (12~72) winsize 61 [CA 1] Center 42 (12~73) winsize 62 [CA 2] Center 37 (8~67) winsize 60 [CA 3] Center 37 (8~67) winsize 60 [CA 4] Center 35 (5~65) winsize 61 [CA 5] Center 35 (5~65) winsize 61 [CmdBusTrainingLP45] Vref(ca) range 0: 30 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 290/100 ps CA0 delay=42 (12~72),Diff = 7 PI (23 cell) CA1 delay=42 (12~73),Diff = 7 PI (23 cell) CA2 delay=37 (8~67),Diff = 2 PI (6 cell) CA3 delay=37 (8~67),Diff = 2 PI (6 cell) CA4 delay=35 (6~65),Diff = 0 PI (0 cell) CA5 delay=35 (6~64),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=35 [CBTSetCACLKResult] CA Dly = 35 CS Dly: 10 (0~42) [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 35 => 35 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20) 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0) 1 4 8 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0) 1 4 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0) 1 4 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1) 1 4 20 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1) 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 4 28 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1) 1 5 0 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1) 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1) 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0) 1 5 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1) 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0) 1 5 20 | B1->B0 | 2525 2424 | 0 0 | (0 1) (0 0) 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0) 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0) 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0) 1 6 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0) 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0) 1 6 16 | B1->B0 | 2f2f 4645 | 1 1 | (0 0) (0 0) 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0) 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1) 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1) 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 9, 10) 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0) 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 9, 18) best DQS0 dly(MCK, UI, PI) = (1, 9, 10) best DQS1 dly(MCK, UI, PI) = (1, 9, 18) best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10) best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 136, DQM1 = 130 DQ Delay: DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123 DQ12 =131, DQ13 =139, DQ14 =139, DQ15 =135 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3) Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3) Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 1, minWin=22, winSum=374 TX Vref=18, minBit 3, minWin=23, winSum=385 TX Vref=20, minBit 0, minWin=24, winSum=399 TX Vref=22, minBit 0, minWin=24, winSum=406 TX Vref=24, minBit 0, minWin=24, winSum=409 TX Vref=26, minBit 2, minWin=24, winSum=422 TX Vref=28, minBit 6, minWin=24, winSum=424 TX Vref=30, minBit 6, minWin=24, winSum=414 TX Vref=32, minBit 1, minWin=24, winSum=406 TX Vref=34, minBit 6, minWin=23, winSum=394 [TxChooseVref] Worse bit 6, Min win 24, Win sum 424, Final Vref 28 Final TX Range 0 Vref 28 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps == TX Byte 0 == u2DelayCellOfst[0]=10 cells (3 PI) u2DelayCellOfst[1]=16 cells (5 PI) u2DelayCellOfst[2]=13 cells (4 PI) u2DelayCellOfst[3]=10 cells (3 PI) u2DelayCellOfst[4]=10 cells (3 PI) u2DelayCellOfst[5]=0 cells (0 PI) u2DelayCellOfst[6]=16 cells (5 PI) u2DelayCellOfst[7]=16 cells (5 PI) Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3) Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=3 cells (1 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=6 cells (2 PI) u2DelayCellOfst[12]=10 cells (3 PI) u2DelayCellOfst[13]=13 cells (4 PI) u2DelayCellOfst[14]=13 cells (4 PI) u2DelayCellOfst[15]=10 cells (3 PI) Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3) Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFFF, sum = 0 13, 0xFFFF, sum = 0 14, 0x0, sum = 1 15, 0x0, sum = 2 16, 0x0, sum = 3 17, 0x0, sum = 4 best_step = 15 == Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 24 -> 127 RX Vref 24 -> 127, step: 1 RX Delay 27 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 24 [Byte1]: 24 Set Vref, RX VrefLevel [Byte0]: 25 [Byte1]: 25 Set Vref, RX VrefLevel [Byte0]: 26 [Byte1]: 26 Set Vref, RX VrefLevel [Byte0]: 27 [Byte1]: 27 Set Vref, RX VrefLevel [Byte0]: 28 [Byte1]: 28 Set Vref, RX VrefLevel [Byte0]: 29 [Byte1]: 29 Set Vref, RX VrefLevel [Byte0]: 30 [Byte1]: 30 Set Vref, RX VrefLevel [Byte0]: 31 [Byte1]: 31 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Final RX Vref Byte 0 = 57 to rank0 Final RX Vref Byte 1 = 62 to rank0 Final RX Vref Byte 0 = 57 to rank1 Final RX Vref Byte 1 = 62 to rank1== Dram Type= 6, Freq= 0, CH_0, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 134, DQM1 = 127 DQ Delay: DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130 DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =140 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4545, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps CH0 RK0: MR19=303, MR18=2521 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 37 => 37 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20) 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 4 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0) 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0) 1 4 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0) 1 4 16 | B1->B0 | 2e2e 3636 | 0 0 | (0 0) (1 1) 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1) 1 4 24 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1) 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1) 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0) 1 5 4 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0) 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1) 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0) 1 5 16 | B1->B0 | 2b2b 2525 | 1 1 | (1 0) (1 0) 1 5 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0) 1 5 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1) 1 5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1) 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0) 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0) 1 6 12 | B1->B0 | 2424 3736 | 0 1 | (0 0) (0 0) 1 6 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0) 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 9, 14) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 9, 14) best DQS0 dly(MCK, UI, PI) = (1, 9, 14) best DQS1 dly(MCK, UI, PI) = (1, 9, 14) best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14) best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 137, DQM1 = 129 DQ Delay: DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3) Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3) Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 3, minWin=23, winSum=386 TX Vref=18, minBit 1, minWin=24, winSum=397 TX Vref=20, minBit 1, minWin=23, winSum=402 TX Vref=22, minBit 3, minWin=24, winSum=412 TX Vref=24, minBit 1, minWin=25, winSum=418 TX Vref=26, minBit 1, minWin=25, winSum=429 TX Vref=28, minBit 3, minWin=25, winSum=425 TX Vref=30, minBit 3, minWin=25, winSum=416 TX Vref=32, minBit 4, minWin=24, winSum=409 TX Vref=34, minBit 1, minWin=24, winSum=406 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 26 Final TX Range 0 Vref 26 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps == TX Byte 0 == u2DelayCellOfst[0]=13 cells (4 PI) u2DelayCellOfst[1]=16 cells (5 PI) u2DelayCellOfst[2]=13 cells (4 PI) u2DelayCellOfst[3]=10 cells (3 PI) u2DelayCellOfst[4]=10 cells (3 PI) u2DelayCellOfst[5]=0 cells (0 PI) u2DelayCellOfst[6]=16 cells (5 PI) u2DelayCellOfst[7]=16 cells (5 PI) Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3) Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=3 cells (1 PI) u2DelayCellOfst[9]=0 cells (0 PI) u2DelayCellOfst[10]=6 cells (2 PI) u2DelayCellOfst[11]=3 cells (1 PI) u2DelayCellOfst[12]=10 cells (3 PI) u2DelayCellOfst[13]=13 cells (4 PI) u2DelayCellOfst[14]=16 cells (5 PI) u2DelayCellOfst[15]=10 cells (3 PI) Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3) Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH0 RK1 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFFF, sum = 0 13, 0xFFFF, sum = 0 14, 0x0, sum = 1 15, 0x0, sum = 2 16, 0x0, sum = 3 17, 0x0, sum = 4 best_step = 15 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 19 -> 252, step: 4 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100 == Dram Type= 6, Freq= 0, CH_0, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 134, DQM1 = 127 DQ Delay: DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK1, (LSB)MR18= 0x2109, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps CH0 RK1: MR19=303, MR18=2109 CH0_RK1: MR19=0x303, MR18=0x2109, DQSOSC=393, MR23=63, INC=23, DEC=15 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 best DQS0 dly(2T, 0.5T) = (1, 1) best DQS1 dly(2T, 0.5T) = (1, 1) best DQS0 P1 dly(2T, 0.5T) = (1, 5) best DQS1 P1 dly(2T, 0.5T) = (1, 5) best DQS0 dly(2T, 0.5T) = (1, 1) best DQS1 dly(2T, 0.5T) = (1, 1) best DQS0 P1 dly(2T, 0.5T) = (1, 5) best DQS1 P1 dly(2T, 0.5T) = (1, 5) Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 42 (12~72) winsize 61 [CA 1] Center 42 (12~72) winsize 61 [CA 2] Center 39 (10~68) winsize 59 [CA 3] Center 38 (10~67) winsize 58 [CA 4] Center 38 (9~68) winsize 60 [CA 5] Center 37 (8~67) winsize 60 [CmdBusTrainingLP45] Vref(ca) range 0: 32 [CATrainingPosCal] consider 1 rank data u2DelayCellTimex100 = 290/100 ps CA0 delay=42 (12~72),Diff = 5 PI (16 cell) CA1 delay=42 (12~72),Diff = 5 PI (16 cell) CA2 delay=39 (10~68),Diff = 2 PI (6 cell) CA3 delay=38 (10~67),Diff = 1 PI (3 cell) CA4 delay=38 (9~68),Diff = 1 PI (3 cell) CA5 delay=37 (8~67),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=37 [CBTSetCACLKResult] CA Dly = 37 CS Dly: 10 (0~41) [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32 [CA 0] Center 42 (12~72) winsize 61 [CA 1] Center 42 (13~72) winsize 60 [CA 2] Center 39 (10~68) winsize 59 [CA 3] Center 38 (8~68) winsize 61 [CA 4] Center 38 (8~68) winsize 61 [CA 5] Center 37 (8~67) winsize 60 [CmdBusTrainingLP45] Vref(ca) range 0: 30 [CATrainingPosCal] consider 2 rank data u2DelayCellTimex100 = 290/100 ps CA0 delay=42 (12~72),Diff = 5 PI (16 cell) CA1 delay=42 (13~72),Diff = 5 PI (16 cell) CA2 delay=39 (10~68),Diff = 2 PI (6 cell) CA3 delay=38 (10~67),Diff = 1 PI (3 cell) CA4 delay=38 (9~68),Diff = 1 PI (3 cell) CA5 delay=37 (8~67),Diff = 0 PI (0 cell) CA PerBit enable=1, Macro0, CA PI delay=37 [CBTSetCACLKResult] CA Dly = 37 CS Dly: 11 (0~44) [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 25 => 25 Write leveling (Byte 1): 27 => 27 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20) 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0) 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1) 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 5 8 | B1->B0 | 3434 2f2f | 0 0 | (1 0) (0 1) 1 5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0) 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 6 8 | B1->B0 | 2a2a 4242 | 0 0 | (0 0) (0 0) 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1) 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1) 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0) 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 9, 10) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 9, 12) best DQS0 dly(MCK, UI, PI) = (1, 9, 10) best DQS1 dly(MCK, UI, PI) = (1, 9, 12) best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10) best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112 iDelay=200, Bit 4, Center 135 (88 ~ 183) 96 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 137, DQM1 = 132 DQ Delay: DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135 DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =127 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3) Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3) Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 1, minWin=22, winSum=374 TX Vref=18, minBit 1, minWin=23, winSum=386 TX Vref=20, minBit 6, minWin=23, winSum=398 TX Vref=22, minBit 0, minWin=24, winSum=405 TX Vref=24, minBit 0, minWin=25, winSum=416 TX Vref=26, minBit 0, minWin=25, winSum=427 TX Vref=28, minBit 0, minWin=25, winSum=426 TX Vref=30, minBit 2, minWin=25, winSum=420 TX Vref=32, minBit 0, minWin=24, winSum=413 TX Vref=34, minBit 0, minWin=24, winSum=406 TX Vref=36, minBit 2, minWin=23, winSum=391 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26 Final TX Range 0 Vref 26 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps == TX Byte 0 == u2DelayCellOfst[0]=13 cells (4 PI) u2DelayCellOfst[1]=6 cells (2 PI) u2DelayCellOfst[2]=0 cells (0 PI) u2DelayCellOfst[3]=6 cells (2 PI) u2DelayCellOfst[4]=6 cells (2 PI) u2DelayCellOfst[5]=16 cells (5 PI) u2DelayCellOfst[6]=16 cells (5 PI) u2DelayCellOfst[7]=6 cells (2 PI) Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3) Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=3 cells (1 PI) u2DelayCellOfst[10]=13 cells (4 PI) u2DelayCellOfst[11]=3 cells (1 PI) u2DelayCellOfst[12]=13 cells (4 PI) u2DelayCellOfst[13]=16 cells (5 PI) u2DelayCellOfst[14]=16 cells (5 PI) u2DelayCellOfst[15]=16 cells (5 PI) Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3) Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK0 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFFF, sum = 0 13, 0xFFFF, sum = 0 14, 0x0, sum = 1 15, 0x0, sum = 2 16, 0x0, sum = 3 17, 0x0, sum = 4 best_step = 15 == Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == RX Vref Scan: 1 Set Vref Range= 24 -> 127 RX Vref 24 -> 127, step: 1 RX Delay 27 -> 252, step: 4 Set Vref, RX VrefLevel [Byte0]: 24 [Byte1]: 24 Set Vref, RX VrefLevel [Byte0]: 25 [Byte1]: 25 Set Vref, RX VrefLevel [Byte0]: 26 [Byte1]: 26 Set Vref, RX VrefLevel [Byte0]: 27 [Byte1]: 27 Set Vref, RX VrefLevel [Byte0]: 28 [Byte1]: 28 Set Vref, RX VrefLevel [Byte0]: 29 [Byte1]: 29 Set Vref, RX VrefLevel [Byte0]: 30 [Byte1]: 30 Set Vref, RX VrefLevel [Byte0]: 31 [Byte1]: 31 Set Vref, RX VrefLevel [Byte0]: 32 [Byte1]: 32 Set Vref, RX VrefLevel [Byte0]: 33 [Byte1]: 33 Set Vref, RX VrefLevel [Byte0]: 34 [Byte1]: 34 Set Vref, RX VrefLevel [Byte0]: 35 [Byte1]: 35 Set Vref, RX VrefLevel [Byte0]: 36 [Byte1]: 36 Set Vref, RX VrefLevel [Byte0]: 37 [Byte1]: 37 Set Vref, RX VrefLevel [Byte0]: 38 [Byte1]: 38 Set Vref, RX VrefLevel [Byte0]: 39 [Byte1]: 39 Set Vref, RX VrefLevel [Byte0]: 40 [Byte1]: 40 Set Vref, RX VrefLevel [Byte0]: 41 [Byte1]: 41 Set Vref, RX VrefLevel [Byte0]: 42 [Byte1]: 42 Set Vref, RX VrefLevel [Byte0]: 43 [Byte1]: 43 Set Vref, RX VrefLevel [Byte0]: 44 [Byte1]: 44 Set Vref, RX VrefLevel [Byte0]: 45 [Byte1]: 45 Set Vref, RX VrefLevel [Byte0]: 46 [Byte1]: 46 Set Vref, RX VrefLevel [Byte0]: 47 [Byte1]: 47 Set Vref, RX VrefLevel [Byte0]: 48 [Byte1]: 48 Set Vref, RX VrefLevel [Byte0]: 49 [Byte1]: 49 Set Vref, RX VrefLevel [Byte0]: 50 [Byte1]: 50 Set Vref, RX VrefLevel [Byte0]: 51 [Byte1]: 51 Set Vref, RX VrefLevel [Byte0]: 52 [Byte1]: 52 Set Vref, RX VrefLevel [Byte0]: 53 [Byte1]: 53 Set Vref, RX VrefLevel [Byte0]: 54 [Byte1]: 54 Set Vref, RX VrefLevel [Byte0]: 55 [Byte1]: 55 Set Vref, RX VrefLevel [Byte0]: 56 [Byte1]: 56 Set Vref, RX VrefLevel [Byte0]: 57 [Byte1]: 57 Set Vref, RX VrefLevel [Byte0]: 58 [Byte1]: 58 Set Vref, RX VrefLevel [Byte0]: 59 [Byte1]: 59 Set Vref, RX VrefLevel [Byte0]: 60 [Byte1]: 60 Set Vref, RX VrefLevel [Byte0]: 61 [Byte1]: 61 Set Vref, RX VrefLevel [Byte0]: 62 [Byte1]: 62 Set Vref, RX VrefLevel [Byte0]: 63 [Byte1]: 63 Set Vref, RX VrefLevel [Byte0]: 64 [Byte1]: 64 Set Vref, RX VrefLevel [Byte0]: 65 [Byte1]: 65 Set Vref, RX VrefLevel [Byte0]: 66 [Byte1]: 66 Set Vref, RX VrefLevel [Byte0]: 67 [Byte1]: 67 Set Vref, RX VrefLevel [Byte0]: 68 [Byte1]: 68 Set Vref, RX VrefLevel [Byte0]: 69 [Byte1]: 69 Set Vref, RX VrefLevel [Byte0]: 70 [Byte1]: 70 Set Vref, RX VrefLevel [Byte0]: 71 [Byte1]: 71 Set Vref, RX VrefLevel [Byte0]: 72 [Byte1]: 72 Set Vref, RX VrefLevel [Byte0]: 73 [Byte1]: 73 Set Vref, RX VrefLevel [Byte0]: 74 [Byte1]: 74 Set Vref, RX VrefLevel [Byte0]: 75 [Byte1]: 75 Final RX Vref Byte 0 = 57 to rank0 Final RX Vref Byte 1 = 57 to rank0 Final RX Vref Byte 0 = 57 to rank1 Final RX Vref Byte 1 = 57 to rank1== Dram Type= 6, Freq= 0, CH_1, rank 0 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 134, DQM1 = 131 DQ Delay: DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x5151, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK0, (LSB)MR18= 0x1522, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps CH1 RK0: MR19=303, MR18=1522 CH1_RK0: MR19=0x303, MR18=0x1522, DQSOSC=392, MR23=63, INC=24, DEC=16 ----->DramcWriteLeveling(PI) begin... == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == Write leveling (Byte 0): 25 => 25 Write leveling (Byte 1): 28 => 28 DramcWriteLeveling(PI) end<----- == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == [Gating] SW mode calibration [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20) 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 4 8 | B1->B0 | 2828 2323 | 1 0 | (1 1) (0 0) 1 4 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1) 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1) 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1) 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0) 1 5 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 1) 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0) 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0) 1 6 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0) 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0) 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0) 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1) 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1) 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1) 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1) 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0) 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B1: ( 1, 9, 6) 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0) Total UI for P1: 0, mck2ui 16 best dqsien dly found for B0: ( 1, 9, 10) best DQS0 dly(MCK, UI, PI) = (1, 9, 10) best DQS1 dly(MCK, UI, PI) = (1, 9, 6) best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10) best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6) [Gating] SW calibration Done == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 0 -> 252, step: 8 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 136, DQM1 = 133 DQ Delay: DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3) Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3) == TX Byte 1 == Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3) Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3) == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref early break, caculate TX vref TX Vref=16, minBit 0, minWin=23, winSum=384 TX Vref=18, minBit 0, minWin=23, winSum=393 TX Vref=20, minBit 0, minWin=23, winSum=400 TX Vref=22, minBit 1, minWin=24, winSum=409 TX Vref=24, minBit 6, minWin=24, winSum=417 TX Vref=26, minBit 6, minWin=25, winSum=424 TX Vref=28, minBit 0, minWin=25, winSum=426 TX Vref=30, minBit 1, minWin=25, winSum=418 TX Vref=32, minBit 0, minWin=24, winSum=409 TX Vref=34, minBit 0, minWin=24, winSum=404 TX Vref=36, minBit 0, minWin=24, winSum=400 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28 Final TX Range 0 Vref 28 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps == TX Byte 0 == u2DelayCellOfst[0]=16 cells (5 PI) u2DelayCellOfst[1]=10 cells (3 PI) u2DelayCellOfst[2]=0 cells (0 PI) u2DelayCellOfst[3]=6 cells (2 PI) u2DelayCellOfst[4]=10 cells (3 PI) u2DelayCellOfst[5]=16 cells (5 PI) u2DelayCellOfst[6]=16 cells (5 PI) u2DelayCellOfst[7]=6 cells (2 PI) Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3) Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3) == TX Byte 1 == u2DelayCellOfst[8]=0 cells (0 PI) u2DelayCellOfst[9]=3 cells (1 PI) u2DelayCellOfst[10]=10 cells (3 PI) u2DelayCellOfst[11]=3 cells (1 PI) u2DelayCellOfst[12]=13 cells (4 PI) u2DelayCellOfst[13]=16 cells (5 PI) u2DelayCellOfst[14]=16 cells (5 PI) u2DelayCellOfst[15]=16 cells (5 PI) Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3) Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3) DramC Write-DBI on == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == TX Vref Scan disable == TX Byte 0 == Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3) == TX Byte 1 == Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3) DramC Write-DBI off [DATLAT] Freq=1600, CH1 RK1 DATLAT Default: 0xf 0, 0xFFFF, sum = 0 1, 0xFFFF, sum = 0 2, 0xFFFF, sum = 0 3, 0xFFFF, sum = 0 4, 0xFFFF, sum = 0 5, 0xFFFF, sum = 0 6, 0xFFFF, sum = 0 7, 0xFFFF, sum = 0 8, 0xFFFF, sum = 0 9, 0xFFFF, sum = 0 10, 0xFFFF, sum = 0 11, 0xFFFF, sum = 0 12, 0xFFFF, sum = 0 13, 0xFFFF, sum = 0 14, 0x0, sum = 1 15, 0x0, sum = 2 16, 0x0, sum = 3 17, 0x0, sum = 4 best_step = 15 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == RX Vref Scan: 0 RX Vref 0 -> 0, step: 1 RX Delay 19 -> 252, step: 4 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104 == Dram Type= 6, Freq= 0, CH_1, rank 1 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1 == DQS Delay: DQS0 = 0, DQS1 = 0 DQM Delay: DQM0 = 134, DQM1 = 130 DQ Delay: DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138 [DramC_TX_OE_Calibration] TA2 Original DQ_B0 (3 6) =30, OEN = 27 Original DQ_B1 (3 6) =30, OEN = 27 24, 0x0, End_B0=24 End_B1=24 25, 0x0, End_B0=25 End_B1=25 26, 0x0, End_B0=26 End_B1=26 27, 0x0, End_B0=27 End_B1=27 28, 0x0, End_B0=28 End_B1=28 29, 0x0, End_B0=29 End_B1=29 30, 0x0, End_B0=30 End_B1=30 31, 0x4141, End_B0=30 End_B1=30 Byte0 end_step=30 best_step=27 Byte1 end_step=30 best_step=27 Byte0 TX OE(2T, 0.5T) = (3, 3) Byte1 TX OE(2T, 0.5T) = (3, 3) [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps CH1 RK1: MR19=303, MR18=2207 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16 [RxdqsGatingPostProcess] freq 1600 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3 best DQS0 dly(2T, 0.5T) = (1, 1) best DQS1 dly(2T, 0.5T) = (1, 1) best DQS0 P1 dly(2T, 0.5T) = (1, 5) best DQS1 P1 dly(2T, 0.5T) = (1, 5) best DQS0 dly(2T, 0.5T) = (1, 1) best DQS1 dly(2T, 0.5T) = (1, 1) best DQS0 P1 dly(2T, 0.5T) = (1, 5) best DQS1 P1 dly(2T, 0.5T) = (1, 5) Pre-setting of DQS Precalculation [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [Calibration Summary] 3200 Mbps CH 0, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 0, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 1, Rank 0 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. CH 1, Rank 1 SW Impedance : PASS DUTY Scan : NO K ZQ Calibration : PASS Jitter Meter : NO K CBT Training : PASS Write leveling : PASS RX DQS gating : PASS RX DQ/DQS(RDDQC) : PASS TX DQ/DQS : PASS RX DATLAT : PASS RX DQ/DQS(Engine): PASS TX OE : PASS All Pass. DramC Write-DBI on PER_BANK_REFRESH: Hybrid Mode TX_TRACKING: ON [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464 [FAST_K] Save calibration result to emmc sync common calibartion params. sync cbt_mode0:1, 1:1 dram_init: ddr_geometry: 2 dram_init: ddr_geometry: 2 dram_init: ddr_geometry: 2 0:dram_rank_size:100000000 1:dram_rank_size:100000000 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000 DFS_SHUFFLE_HW_MODE: ON dramc_set_vcore_voltage set vcore to 725000 Read voltage for 1600, 0 Vio18 = 0 Vcore = 725000 Vdram = 0 Vddq = 0 Vmddr = 0 switch to 3200 Mbps bootup [DramcRunTimeConfig] PHYPLL DPM_CONTROL_AFTERK: ON PER_BANK_REFRESH: ON REFRESH_OVERHEAD_REDUCTION: ON CMD_PICG_NEW_MODE: OFF XRTWTW_NEW_MODE: ON XRTRTR_NEW_MODE: ON TX_TRACKING: ON RDSEL_TRACKING: OFF DQS Precalculation for DVFS: ON RX_TRACKING: OFF HW_GATING DBG: ON ZQCS_ENABLE_LP4: ON RX_PICG_NEW_MODE: ON TX_PICG_NEW_MODE: ON ENABLE_RX_DCM_DPHY: ON LOWPOWER_GOLDEN_SETTINGS(DCM): ON DUMMY_READ_FOR_TRACKING: OFF !!! SPM_CONTROL_AFTERK: OFF !!! SPM could not control APHY IMPEDANCE_TRACKING: ON TEMP_SENSOR: ON HW_SAVE_FOR_SR: OFF CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF Read ODT Tracking: ON Refresh Rate DeBounce: ON DFS_NO_QUEUE_FLUSH: ON DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF ENABLE_DFS_RUNTIME_MRW: OFF DDR_RESERVE_NEW_MODE: ON MR_CBT_SWITCH_FREQ: ON ========================= [MEM] 1st complex R/W mem test pass (start addr:0x4c400000) dram_init: ddr_geometry: 2 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1) dram_init: dram init end (result: 0) DRAM-K: Full calibration passed in 24444 msecs MRC: failed to locate region type 0. DRAM rank0 size:0x100000000, DRAM rank1 size=0x100000000 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal Backing address range [0x40000000:0x80000000) with new page table @0x00112000 Backing address range [0x40000000:0x40200000) with new page table @0x00113000 DRAM rank0 size:0x100000000, DRAM rank1 size=0x100000000 CBMEM: IMD: root @ 0xfffff000 254 entries. IMD: root @ 0xffffec00 62 entries. FMAP: area RO_VPD found @ 3f8000 (32768 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 577000 (16384 bytes) CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps BS: romstage times (exec / console): total (unknown) / 23978 ms coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)... ARM64: Exception handlers installed. ARM64: Testing exception ARM64: Done test exception Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 Root Device scanning... scan_static_bus for Root Device CPU_CLUSTER: 0 enabled scan_static_bus for Root Device done scan_bus: bus Root Device finished in 8 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x800000 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 DRAM rank0 size:0x100000000, DRAM rank1 size=0x100000000 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU: 00 missing read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Root Device assign_resources, bus 0 link: 0 CPU_CLUSTER: 0 missing set_resources Root Device assign_resources, bus 0 link: 0 done Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 CPU: 00 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0 CPU: 00 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms Enabling resources... done. BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms Initializing devices... Root Device init init hardware done! 0x00000018: ctrlr->caps 52.000 MHz: ctrlr->f_max 0.400 MHz: ctrlr->f_min 0x40ff8080: ctrlr->voltages sclk: 390625 Bus Width = 1 sclk: 390625 Bus Width = 1 Early init status = 3 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 in-header: 03 fc 00 00 01 00 00 00 in-data: 00 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 in-header: 03 fd 00 00 00 00 00 00 in-data: out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 in-header: 03 fc 00 00 01 00 00 00 in-data: 00 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 in-header: 03 fd 00 00 00 00 00 00 in-data: [SSUSB] Setting up USB HOST controller... [SSUSB] u3phy_ports_enable u2p:1, u3p:1 [SSUSB] phy power-on done. FMAP: area COREBOOT found @ 21000 (4014080 bytes) CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes) CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes) CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps SPM: binary array size = 0x9dc SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16) spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes) SPM: spm_init done in 34 msecs, spm pc = 0x3f4 configure_display: Starting display init anx7625_power_on_init: Init interface. anx7625_disable_pd_protocol: Disabled PD feature. anx7625_power_on_init: Firmware: ver 0x13, rev 0x0. anx7625_start_dp_work: Secure OCM version=00 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91 sp_tx_get_edid_block: EDID Block = 1 Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 26 cf 7d 05 00 00 00 00 00 1e version: 01 04 basic params: 95 1f 11 78 0a chroma info: 76 90 94 55 54 90 27 21 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a extensions: 00 checksum: fb Manufacturer: IVO Model 57d Serial Number 0 Made week 0 of 2020 EDID version: 1.4 Digital display 6 bits per primary color channel DisplayPort interface Maximum image size: 31 cm x 17 cm Gamma: 220% Check DPMS levels Supported color formats: RGB 4:4:4, YCrCb 4:2:2 First detailed timing is preferred timing Established timings supported: Standard timings supported: Detailed timings Hex of detail: 383680a07038204018303c0035ae10000019 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm 0780 0798 07c8 0820 hborder 0 0438 043b 0447 0458 vborder 0 -hsync -vsync Did detailed timing Hex of detail: 000000000000000000000000000000000000 Manufacturer-specified data, tag 0 Hex of detail: 000000fe00496e666f566973696f6e0a2020 ASCII string: InfoVision Hex of detail: 000000fe00523134304e574635205248200a ASCII string: R140NWF5 RH Checksum Checksum: 0xfb (valid) configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz DSI data_rate: 832800000 bps anx7625_parse_edid: detected IVO panel, use k value 0x3b anx7625_parse_edid: pixelclock(138800). hactive(1920), hsync(48), hfp(24), hbp(88) vactive(1080), vsync(12), vfp(3), vbp(17) anx7625_dsi_config: config dsi. anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4). anx7625_dsi_config: success to config DSI anx7625_dp_start: MIPI phy setup OK. mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4 mtk_ddp_mode_set invalid vrefresh 60 main_disp_path_setup ovl_layer_smi_id_en ovl_layer_smi_id_en ccorr_config aal_config gamma_config postmask_config dither_config framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0 Root Device init finished in 551 msecs CPU_CLUSTER: 0 init Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff APU_MBOX 0x190000b0 = 0x10001 APU_MBOX 0x190001b0 = 0x10001 APU_MBOX 0x190005b0 = 0x10001 APU_MBOX 0x190006b0 = 0x10001 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes) CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes) CPU_CLUSTER: 0 init finished in 81 msecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 CPU: 00: enabled 1 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms FMAP: area RW_ELOG found @ 57f000 (4096 bytes) ELOG: NV offset 0x57f000 size 0x1000 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2023-10-28 19:58:23 UTC ELOG: Event(16) added with size 11 at 2023-10-28 19:58:23 UTC read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps out: cmd=0x121: 03 db 21 01 00 00 00 00 in-header: 03 91 00 00 2c 00 00 00 in-data: ce 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ELOG: Event(A1) added with size 10 at 2023-10-28 19:58:23 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b ELOG: Event(A0) added with size 9 at 2023-10-28 19:58:23 UTC elog_add_boot_reason: Logged dev mode boot BS: BS_POST_DEVICE entry times (exec / console): 81 / 74 ms Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms Writing coreboot table at 0xffe64000 0. 000000000010a000-0000000000113fff: RAMSTAGE 1. 0000000040000000-00000000400fffff: RAM 2. 0000000040100000-000000004032afff: RAMSTAGE 3. 000000004032b000-00000000545fffff: RAM 4. 0000000054600000-000000005465ffff: BL31 5. 0000000054660000-00000000ffe63fff: RAM 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES 7. 0000000100000000-000000023fffffff: RAM Passing 5 GPIOs to payload: NAME | PORT | POLARITY | VALUE EC in RW | 0x000000aa | low | undefined EC interrupt | 0x00000005 | low | undefined TPM interrupt | 0x000000ab | high | undefined SD card detect | 0x00000011 | high | undefined speaker enable | 0x00000093 | high | undefined out: cmd=0x6: 03 f7 06 00 00 00 00 00 in-header: 03 f9 00 00 02 00 00 00 in-data: 02 00 ADC[4]: Raw value=904357 ID=7 ADC[3]: Raw value=213441 ID=1 RAM Code: 0x71 ADC[6]: Raw value=75701 ID=0 ADC[5]: Raw value=213072 ID=1 SKU Code: 0x1 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b7d7 coreboot table: 964 bytes. IMD ROOT 0. 0xfffff000 0x00001000 IMD SMALL 1. 0xffffe000 0x00001000 RO MCACHE 2. 0xffffc000 0x00001104 CONSOLE 3. 0xfff7c000 0x00080000 FMAP 4. 0xfff7b000 0x00000452 TIME STAMP 5. 0xfff7a000 0x00000910 VBOOT WORK 6. 0xfff66000 0x00014000 RAMOOPS 7. 0xffe66000 0x00100000 COREBOOT 8. 0xffe64000 0x00002000 IMD small region: IMD ROOT 0. 0xffffec00 0x00000400 VPD 1. 0xffffeb80 0x0000006c MMC STATUS 2. 0xffffeb60 0x00000004 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c Initialized TPM device CR50 revision 0 Checking cr50 for pending updates Reading cr50 TPM mode BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps Checking segment from ROM address 0x40100000 Checking segment from ROM address 0x4010001c Loading segment from ROM address 0x40100000 code (compression=0) New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178 it's not compressed! [ 0x80000000, 8004f178, 0x821a7280) <- 40100038 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108 Loading segment from ROM address 0x4010001c Entry Point 0x80000000 Loaded segments BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms Jumping to boot code at 0x80000000(0xffe64000) CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps Checking segment from ROM address 0x40100000 Checking segment from ROM address 0x4010001c Loading segment from ROM address 0x40100000 code (compression=1) New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470 using LZMA [ 0x54600000, 54614abc, 0x5462e000) <- 40100038 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544 Loading segment from ROM address 0x4010001c Entry Point 0x54601000 Loaded segments NOTICE: MT8192 bl31_setup NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021 WARNING: region 0: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 1: WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d WARNING: region 2: WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d WARNING: region 3: WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d WARNING: region 4: WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d WARNING: region 5: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 6: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 WARNING: region 7: WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0 INFO: [APUAPC] vio 0 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS! INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS! INFO: [APUAPC] D0_APC_0: 0x400510 INFO: [APUAPC] D0_APC_1: 0x0 INFO: [APUAPC] D0_APC_2: 0x1540 INFO: [APUAPC] D0_APC_3: 0x0 INFO: [APUAPC] D1_APC_0: 0xffffffff INFO: [APUAPC] D1_APC_1: 0xffffffff INFO: [APUAPC] D1_APC_2: 0x3fffff INFO: [APUAPC] D1_APC_3: 0x0 INFO: [APUAPC] D2_APC_0: 0xffffffff INFO: [APUAPC] D2_APC_1: 0xffffffff INFO: [APUAPC] D2_APC_2: 0x3fffff INFO: [APUAPC] D2_APC_3: 0x0 INFO: [APUAPC] D3_APC_0: 0xffffffff INFO: [APUAPC] D3_APC_1: 0xffffffff INFO: [APUAPC] D3_APC_2: 0x3fffff INFO: [APUAPC] D3_APC_3: 0x0 INFO: [APUAPC] D4_APC_0: 0xffffffff INFO: [APUAPC] D4_APC_1: 0xffffffff INFO: [APUAPC] D4_APC_2: 0x3fffff INFO: [APUAPC] D4_APC_3: 0x0 INFO: [APUAPC] D5_APC_0: 0xffffffff INFO: [APUAPC] D5_APC_1: 0xffffffff INFO: [APUAPC] D5_APC_2: 0x3fffff INFO: [APUAPC] D5_APC_3: 0x0 INFO: [APUAPC] D6_APC_0: 0xffffffff INFO: [APUAPC] D6_APC_1: 0xffffffff INFO: [APUAPC] D6_APC_2: 0x3fffff INFO: [APUAPC] D6_APC_3: 0x0 INFO: [APUAPC] D7_APC_0: 0xffffffff INFO: [APUAPC] D7_APC_1: 0xffffffff INFO: [APUAPC] D7_APC_2: 0x3fffff INFO: [APUAPC] D7_APC_3: 0x0 INFO: [APUAPC] D8_APC_0: 0xffffffff INFO: [APUAPC] D8_APC_1: 0xffffffff INFO: [APUAPC] D8_APC_2: 0x3fffff INFO: [APUAPC] D8_APC_3: 0x0 INFO: [APUAPC] D9_APC_0: 0xffffffff INFO: [APUAPC] D9_APC_1: 0xffffffff INFO: [APUAPC] D9_APC_2: 0x3fffff INFO: [APUAPC] D9_APC_3: 0x0 INFO: [APUAPC] D10_APC_0: 0xffffffff INFO: [APUAPC] D10_APC_1: 0xffffffff INFO: [APUAPC] D10_APC_2: 0x3fffff INFO: [APUAPC] D10_APC_3: 0x0 INFO: [APUAPC] D11_APC_0: 0xffffffff INFO: [APUAPC] D11_APC_1: 0xffffffff INFO: [APUAPC] D11_APC_2: 0x3fffff INFO: [APUAPC] D11_APC_3: 0x0 INFO: [APUAPC] D12_APC_0: 0xffffffff INFO: [APUAPC] D12_APC_1: 0xffffffff INFO: [APUAPC] D12_APC_2: 0x3fffff INFO: [APUAPC] D12_APC_3: 0x0 INFO: [APUAPC] D13_APC_0: 0xffffffff INFO: [APUAPC] D13_APC_1: 0xffffffff INFO: [APUAPC] D13_APC_2: 0x3fffff INFO: [APUAPC] D13_APC_3: 0x0 INFO: [APUAPC] D14_APC_0: 0xffffffff INFO: [APUAPC] D14_APC_1: 0xffffffff INFO: [APUAPC] D14_APC_2: 0x3fffff INFO: [APUAPC] D14_APC_3: 0x0 INFO: [APUAPC] D15_APC_0: 0xffffffff INFO: [APUAPC] D15_APC_1: 0xffffffff INFO: [APUAPC] D15_APC_2: 0x3fffff INFO: [APUAPC] D15_APC_3: 0x0 INFO: [APUAPC] APC_CON: 0x4 INFO: [NOCDAPC] D0_APC_0: 0x0 INFO: [NOCDAPC] D0_APC_1: 0x0 INFO: [NOCDAPC] D1_APC_0: 0x0 INFO: [NOCDAPC] D1_APC_1: 0xfff INFO: [NOCDAPC] D2_APC_0: 0x0 INFO: [NOCDAPC] D2_APC_1: 0xfff INFO: [NOCDAPC] D3_APC_0: 0x0 INFO: [NOCDAPC] D3_APC_1: 0xfff INFO: [NOCDAPC] D4_APC_0: 0x0 INFO: [NOCDAPC] D4_APC_1: 0xfff INFO: [NOCDAPC] D5_APC_0: 0x0 INFO: [NOCDAPC] D5_APC_1: 0xfff INFO: [NOCDAPC] D6_APC_0: 0x0 INFO: [NOCDAPC] D6_APC_1: 0xfff INFO: [NOCDAPC] D7_APC_0: 0x0 INFO: [NOCDAPC] D7_APC_1: 0xfff INFO: [NOCDAPC] D8_APC_0: 0x0 INFO: [NOCDAPC] D8_APC_1: 0xfff INFO: [NOCDAPC] D9_APC_0: 0x0 INFO: [NOCDAPC] D9_APC_1: 0xfff INFO: [NOCDAPC] D10_APC_0: 0x0 INFO: [NOCDAPC] D10_APC_1: 0xfff INFO: [NOCDAPC] D11_APC_0: 0x0 INFO: [NOCDAPC] D11_APC_1: 0xfff INFO: [NOCDAPC] D12_APC_0: 0x0 INFO: [NOCDAPC] D12_APC_1: 0xfff INFO: [NOCDAPC] D13_APC_0: 0x0 INFO: [NOCDAPC] D13_APC_1: 0xfff INFO: [NOCDAPC] D14_APC_0: 0x0 INFO: [NOCDAPC] D14_APC_1: 0xfff INFO: [NOCDAPC] D15_APC_0: 0x0 INFO: [NOCDAPC] D15_APC_1: 0xfff INFO: [NOCDAPC] APC_CON: 0x4 INFO: [APUAPC] set_apusys_apc done INFO: [DEVAPC] devapc_init done INFO: GICv3 without legacy support detected. INFO: ARM GICv3 driver initialized in EL3 INFO: Maximum SPI INTID supported: 639 INFO: BL31: Initializing runtime services WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing! INFO: SPM: enable CPC mode INFO: mcdi ready for mcusys-off-idle and system suspend INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x80000000 INFO: SPSR = 0x8 Starting depthcharge on Spherion... Wipe memory regions: [0x00000040000000, 0x00000054600000) [0x00000054660000, 0x00000080000000) [0x000000821a7280, 0x000000ffe64000) [0x00000100000000, 0x00000240000000) Initializing XHCI USB controller at 0x11200000. [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38 asurada: tftpboot 192.168.201.1 11899592/tftp-deploy-pu673ckw/kernel/image.itb 11899592/tftp-deploy-pu673ckw/kernel/cmdline tftpboot 192.168.201.1 11899592/tftp-deploy-pu673ckw/kernel/image.ittp-deploy-pu673ckw/kernel/cmdline Waiting for link R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device done. MAC: 00:e0:4c:78:7a:aa Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.12 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 11899592/tftp-deploy-pu673ckw/kernel/image.itb Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ################################################################ 00b80000 ################################################################ 00c00000 ################################################################ 00c80000 ################################################################ 00d00000 ################################################################ 00d80000 ################################################################ 00e00000 ################################################################ 00e80000 ################################################################ 00f00000 ################################################################ 00f80000 ################################################################ 01000000 ################################################################ 01080000 ################################################################ 01100000 ################################################################ 01180000 ################################################################ 01200000 ################################################################ 01280000 ################################################################ 01300000 ################################################################ 01380000 ################################################################ 01400000 ################################################################ 01480000 ################################################################ 01500000 ################################################################ 01580000 ################################################################ 01600000 ################################################################ 01680000 ################################################################ 01700000 ################################################################ 01780000 ################################################################ 01800000 ################################################################ 01880000 ################################################################ 01900000 ################################################################ 01980000 ################################################################ 01a00000 ################################################################ 01a80000 ################################################################ 01b00000 ################################################################ 01b80000 ################################################################ 01c00000 ################################################################ 01c80000 ################################################################ 01d00000 ################################################################ 01d80000 ################################################################ 01e00000 ################################################################ 01e80000 ################################################################ 01f00000 ################################################################ 01f80000 ################################################################ 02000000 ################################################################ 02080000 ################################################################ 02100000 ################################################################ 02180000 ################################################################ 02200000 ################################################################ 02280000 ################################################################ 02300000 ################################################################ 02380000 ################################################################ 02400000 ################################################################ 02480000 ################################################################ 02500000 ################################################################ 02580000 ################################################################ 02600000 ################################################################ 02680000 ################################################################ 02700000 ################################################################ 02780000 ################################################################ 02800000 ################################################################ 02880000 ################################################################ 02900000 ################################################################ 02980000 ################################################################ 02a00000 ################################################################ 02a80000 ################################################################ 02b00000 ################################################################ 02b80000 ################################################################ 02c00000 ################################################################ 02c80000 ################################################################ 02d00000 ################################################################ 02d80000 ################################################################ 02e00000 ################################################################ 02e80000 ################################################################ 02f00000 ################################################################ 02f80000 ################################################################ 03000000 ################################################################ 03080000 ################################################################ 03100000 ################################################################ 03180000 ################################################################ 03200000 ################################################################ 03280000 ################################################################ 03300000 ################################################################ 03380000 ################################################################ 03400000 ################################################################ 03480000 ################################################################ 03500000 ################################################################ 03580000 ################################################################ 03600000 ################################################################ 03680000 ################################################################ 03700000 ################################################################ 03780000 ################################################################ 03800000 ################################################################ 03880000 ################################################################ 03900000 ################################################################ 03980000 ################################################################ 03a00000 ################################################################ 03a80000 ################################################################ 03b00000 ################################################################ 03b80000 ################################################################ 03c00000 ################################################################ 03c80000 ################################################################ 03d00000 ################################################################ 03d80000 ################################################################ 03e00000 ################################################################ 03e80000 ################################################################ 03f00000 ################################################################ 03f80000 ################################################################ 04000000 ################################################### done. The bootfile was 67520190 bytes long. Sending tftp read request... done. Waiting for the transfer... 00000000 # done. Command line loaded dynamically from TFTP file: 11899592/tftp-deploy-pu673ckw/kernel/cmdline The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 Loading FIT. Image ramdisk-1 has 56423353 bytes. Image fdt-1 has 47278 bytes. Image kernel-1 has 11047522 bytes. Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192 Choosing best match conf-1 for compat google,spherion-rev2. Connected to device vid:did:rid of 1ae0:0028:00 tpm_get_response: command 0x17b, return code 0x0 ec_init: CrosEC protocol v3 supported (256, 248) tpm_cleanup: add release locality here. Shutting down all USB controllers. Removing current net device Exiting depthcharge with code 4 at timestamp: 69593709 LZMA decompressing kernel-1 to 0x821a6718 LZMA decompressing kernel-1 to 0x40000000 jumping to kernel [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050] [ 0.000000] Linux version 6.1.59-cip8-rt4 (KernelCI@build-j84202-arm64-gcc-10-defconfig-arm64-chromebook-st8dj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 [ 0.000000] random: crng init done [ 0.000000] Machine model: Google Spherion (rev0 - 3) [ 0.000000] efi: UEFI not found. [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8') [ 0.000000] printk: bootconsole [mtk8250] enabled [ 0.000000] NUMA: No NUMA configuration found [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff] [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff] [ 0.000000] Zone ranges: [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff] [ 0.000000] DMA32 empty [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff] [ 0.000000] Movable zone start for each node [ 0.000000] Early memory node ranges [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff] [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff] [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff] [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff] [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff] [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff] [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000 [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: PSCIv1.1 detected in firmware. [ 0.000000] psci: Using standard PSCI v0.2 function IDs [ 0.000000] psci: MIGRATE_INFO_TYPE not supported. [ 0.000000] psci: SMC Calling Convention v1.2 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016 [ 0.000000] Detected VIPT I-cache on CPU0 [ 0.000000] CPU features: detected: GIC system register CPU interface [ 0.000000] CPU features: detected: Virtualization Host Extensions [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI) [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923 [ 0.000000] alternatives: applying boot alternatives [ 0.000000] Fallback order for Node 0: 0 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616 [ 0.000000] Policy zone: Normal [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space. <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear) <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off <6>[ 0.000000] software IO TLB: area num 8. <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB) <6>[ 0.000000] Memory: 7914324K/8385536K available (17984K kernel code, 4116K rwdata, 17476K rodata, 8448K init, 615K bss, 438444K reserved, 32768K cma-reserved) <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation. <6>[ 0.000000] rcu: RCU event tracing is enabled. <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8. <6>[ 0.000000] Trampoline variant of Tasks RCU enabled. <6>[ 0.000000] Tracing variant of Tasks RCU enabled. <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies. <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode <6>[ 0.000000] GICv3: 608 SPIs implemented <6>[ 0.000000] GICv3: 0 Extended SPIs implemented <6>[ 0.000000] Root IRQ handler: gic_handle_irq <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] } <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] } <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention. <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys). <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns <6>[ 0.009178] Console: colour dummy device 80x25 <6>[ 0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000) <6>[ 0.024346] pid_max: default: 32768 minimum: 301 <6>[ 0.029248] LSM: Security Framework initializing <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) <6>[ 0.042002] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear) <6>[ 0.051384] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.058827] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.065164] cblist_init_generic: Setting adjustable number of callback queues. <6>[ 0.072637] cblist_init_generic: Setting shift to 3 and lim to 1. <6>[ 0.079077] rcu: Hierarchical SRCU implementation. <6>[ 0.079079] rcu: Max phase no-delay instances is 1000. <6>[ 0.079104] printk: bootconsole [mtk8250] printing thread started <6>[ 0.097419] EFI services will not be available. <6>[ 0.097617] smp: Bringing up secondary CPUs ... <6>[ 0.097928] Detected VIPT I-cache on CPU1 <6>[ 0.097998] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000 <6>[ 0.098031] CPU1: Booted secondary processor 0x0000000100 [0x412fd050] <6>[ 0.125955] Detected VIPT I-cache on CPU2 <6>[ 0.126001] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000 <6>[ 0.126015] CPU2: Booted secondary processor 0x0000000200 [0x412fd050] <6>[ 0.126271] Detected VIPT I-cache on CPU3 <6>[ 0.126317] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000 <6>[ 0.126330] CPU3: Booted secondary processor 0x0000000300 [0x412fd050] <6>[ 0.126642] CPU features: detected: Spectre-v4 <6>[ 0.126648] CPU features: detected: Spectre-BHB <6>[ 0.126653] Detected PIPT I-cache on CPU4 <6>[ 0.126712] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000 <6>[ 0.126728] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0] <6>[ 0.127025] Detected PIPT I-cache on CPU5 <6>[ 0.127088] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000 <6>[ 0.127105] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0] <6>[ 0.127379] Detected PIPT I-cache on CPU6 <6>[ 0.127445] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000 <6>[ 0.127461] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0] <6>[ 0.127755] Detected PIPT I-cache on CPU7 <6>[ 0.127821] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000 <6>[ 0.127838] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0] <6>[ 0.127884] smp: Brought up 1 node, 8 CPUs <6>[ 0.127889] SMP: Total of 8 processors activated. <6>[ 0.127892] CPU features: detected: 32-bit EL0 Support <6>[ 0.127894] CPU features: detected: Data cache clean to the PoU not required for I/D coherence <6>[ 0.127897] CPU features: detected: Common not Private translations <6>[ 0.127899] CPU features: detected: CRC32 instructions <6>[ 0.127901] CPU features: detected: RCpc load-acquire (LDAPR) <6>[ 0.127903] CPU features: detected: LSE atomic instructions <6>[ 0.127904] CPU features: detected: Privileged Access Never <6>[ 0.127906] CPU features: detected: RAS Extension Support <6>[ 0.127909] CPU features: detected: Speculative Store Bypassing Safe (SSBS) <6>[ 0.127979] CPU: All CPU(s) started at EL2 <6>[ 0.127981] alternatives: applying system-wide alternatives <6>[ 0.140975] devtmpfs: initialized �B�͡�������*��ɥ������Bzɑ�Ɂ�b��ʲ�ѕͥjR�<6>[ 0.359051] printk: consol[ 0.359082] printk: console [ttyS0] enabled >[ 0.225910] pnp: PnP ACPI: disabled <6>[ 0.359087] printk: bootconsole [mtk8250] disabled <6>[ 0.373063] printk: bootconsole [mtk8250] printing thread stopped <6>[ 0.374526] SuperH (H)SCI(F) driver initialized <6>[ 0.375037] msm_serial: driver initialized <6>[ 0.379867] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000 <6>[ 0.379896] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000 <6>[ 0.379926] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000 <6>[ 0.379956] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000 <6>[ 0.379978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000 <6>[ 0.380006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000 <6>[ 0.380033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000 <6>[ 0.380152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000 <6>[ 0.380184] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000 <6>[ 0.388740] loop: module loaded <6>[ 0.391260] vgpu11_sshub: Bringing 400000uV into 575000-575000uV <4>[ 0.408270] mtk-pmic-keys: Failed to locate of_node [id: -1] <6>[ 0.409222] megasas: 07.719.03.00-rc1 <6>[ 0.421078] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2 <6>[ 0.421135] spi-nor spi2.0: w25q64jwm (8192 Kbytes) <6>[ 0.433219] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0) <6>[ 0.486699] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b <6>[ 2.624436] Freeing initrd memory: 55100K <6>[ 2.630522] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz <6>[ 2.635229] tun: Universal TUN/TAP device driver, 1.6 <6>[ 2.636009] thunder_xcv, ver 1.0 <6>[ 2.636028] thunder_bgx, ver 1.0 <6>[ 2.636043] nicpf, ver 1.0 <6>[ 2.637131] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version <6>[ 2.637134] hns3: Copyright (c) 2017 Huawei Corporation. <6>[ 2.637162] hclge is initializing <6>[ 2.637176] e1000: Intel(R) PRO/1000 Network Driver <6>[ 2.637177] e1000: Copyright (c) 1999-2006 Intel Corporation. <6>[ 2.637193] e1000e: Intel(R) PRO/1000 Network Driver <6>[ 2.637195] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. <6>[ 2.637210] igb: Intel(R) Gigabit Ethernet Network Driver <6>[ 2.637212] igb: Copyright (c) 2007-2014 Intel Corporation. <6>[ 2.637228] igbvf: Intel(R) Gigabit Virtual Function Network Driver <6>[ 2.637230] igbvf: Copyright (c) 2009 - 2012 Intel Corporation. <6>[ 2.637527] sky2: driver version 1.30 <6>[ 2.638655] VFIO - User Level meta-driver version: 0.3 <6>[ 2.641601] usbcore: registered new interface driver usb-storage <6>[ 2.641817] usbcore: registered new device driver onboard-usb-hub <6>[ 2.644597] mt6397-rtc mt6359-rtc: registered as rtc0 <6>[ 2.644747] mt6397-rtc mt6359-rtc: setting system clock to 2023-10-28T19:59:11 UTC (1698523151) <6>[ 2.645386] i2c_dev: i2c /dev entries driver <6>[ 2.652657] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0) <6>[ 2.667673] cpu cpu0: EM: created perf domain <6>[ 2.667982] cpu cpu4: EM: created perf domain <6>[ 2.671942] sdhci: Secure Digital Host Controller Interface driver <6>[ 2.671944] sdhci: Copyright(c) Pierre Ossman <6>[ 2.672309] Synopsys Designware Multimedia Card Interface Driver <6>[ 2.672682] sdhci-pltfm: SDHCI platform and OF driver helper <6>[ 2.677288] mmc0: CQHCI version 5.10 <6>[ 2.683291] ledtrig-cpu: registered to indicate activity on CPUs <6>[ 2.684115] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000 <6>[ 2.684412] usbcore: registered new interface driver usbhid <6>[ 2.684414] usbhid: USB HID core driver <6>[ 2.684537] spi_master spi0: will run message pump with realtime priority <6>[ 2.715332] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0 <6>[ 2.717167] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1 <6>[ 2.719266] cros-ec-spi spi0.0: Chrome EC device registered <6>[ 2.739060] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0) <6>[ 2.742058] NET: Registered PF_PACKET protocol family <6>[ 2.742177] 9pnet: Installing 9P2000 support <5>[ 2.742219] Key type dns_resolver registered <6>[ 2.742675] registered taskstats version 1 <5>[ 2.742694] Loading compiled-in X.509 certificates <4>[ 2.758466] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <4>[ 2.758635] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator <3>[ 2.758648] debugfs: File 'uA_load' in directory '/' already present! <3>[ 2.758657] debugfs: File 'min_uV' in directory '/' already present! <3>[ 2.758661] debugfs: File 'max_uV' in directory '/' already present! <3>[ 2.758665] debugfs: File 'constraint_flags' in directory '/' already present! <3>[ 2.760878] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0) <6>[ 2.772391] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102 <6>[ 2.773187] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 2.773214] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1 <6>[ 2.773506] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010 <6>[ 2.773584] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000 <6>[ 2.773816] xhci-mtk 11200000.usb: xHCI Host Controller <6>[ 2.773831] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2 <6>[ 2.773844] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed <6>[ 2.774591] hub 1-0:1.0: USB hub found <6>[ 2.774623] hub 1-0:1.0: 1 port detected <6>[ 2.775030] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM. <6>[ 2.775575] hub 2-0:1.0: USB hub found <6>[ 2.775603] hub 2-0:1.0: 1 port detected <6>[ 2.776387] mmc0: Command Queue Engine enabled <6>[ 2.776401] mmc0: new HS400 Enhanced strobe MMC card at address 0001 <6>[ 2.776988] mmcblk0: mmc0:0001 DA4128 116 GiB <6>[ 2.780051] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 <6>[ 2.781111] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB <6>[ 2.781238] mtk-msdc 11f70000.mmc: Got CD GPIO <6>[ 2.781915] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB <6>[ 2.782537] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0) <6>[ 2.797004] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume() <6>[ 2.797013] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock() <4>[ 2.797166] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW <6>[ 2.797830] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend() <6>[ 2.797835] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock() <6>[ 2.797957] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register() <6>[ 2.797968] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register() <6>[ 2.797972] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register() <6>[ 2.797980] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39 <6>[ 2.799404] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799421] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799428] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799434] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799440] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799447] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799453] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799459] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799465] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799471] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799477] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799483] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799489] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799495] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799500] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops) <6>[ 2.799980] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0 <6>[ 2.800809] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0 <6>[ 2.801352] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0 <6>[ 2.801995] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0 <6>[ 2.802650] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0 <6>[ 2.802856] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.802867] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.802872] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 2.802878] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops) <6>[ 2.802883] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops) <6>[ 2.802894] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops) <6>[ 2.802901] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops) <6>[ 2.802905] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops) <6>[ 2.802909] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops) <6>[ 2.802916] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing <6>[ 2.802921] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing <6>[ 2.804043] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0 <6>[ 3.158039] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk <6>[ 3.188742] hub 2-1:1.0: USB hub found <6>[ 3.189088] hub 2-1:1.0: 3 ports detected <6>[ 3.309814] usb 1-1: new high-speed USB device number 2 using xhci-mtk <6>[ 3.462476] hub 1-1:1.0: USB hub found <6>[ 3.462874] hub 1-1:1.0: 4 ports detected <6>[ 3.538170] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk <6>[ 3.773992] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk <6>[ 3.901816] hub 1-1.4:1.0: USB hub found <6>[ 3.902284] hub 1-1.4:1.0: 2 ports detected <6>[ 4.189960] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk <6>[ 4.373966] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk <6>[ 15.106788] ALSA device list: <6>[ 15.106809] No soundcards found. <6>[ 15.111239] Freeing unused kernel memory: 8448K <6>[ 15.111403] Run /init as init process <6>[ 15.153456] NET: Registered PF_INET6 protocol family <6>[ 15.154802] Segment Routing with IPv6 <6>[ 15.154817] In-situ OAM (IOAM) with IPv6 Welcome to Debian GNU/Linu<30>[ 15.170590] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified) x 11 (bullseye)<30>[ 15.171153] systemd[1]: Detected architecture arm64. [0m! <30>[ 15.214141] systemd[1]: Set hostname to . <30>[ 15.327476] systemd[1]: Queued start job for default target Graphical Interface. [ OK ] Created slice syste<30>[ 15.358869] systemd[1]: Created slice system-getty.slice. m-getty.slice. [ OK ] Created slice syste<30>[ 15.382588] systemd[1]: Created slice system-modprobe.slice. m-modprobe.slice. [ OK ] Created slic<30>[ 15.406976] systemd[1]: Created slice system-serial\x2dgetty.slice. e system-serial\x2dgetty.slice. [ OK ] Created slic<30>[ 15.431628] systemd[1]: Created slice User and Session Slice. e User and Session Slice. [ OK ] Started Dispatch Pa<30>[ 15.454771] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. ssword …ts to Console Directory Watch. [ OK ] Started Forward Pas<30>[ 15.482690] systemd[1]: Started Forward Password Requests to Wall Directory Watch. sword R…uests to Wall Directory Watch. [ OK ] Reached target Loca<30>[ 15.510481] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped. l Encrypted Volu<30>[ 15.510770] systemd[1]: Reached target Local Encrypted Volumes. mes. [ OK ] Reached target Path<30>[ 15.546096] systemd[1]: Reached target Paths. s. [ OK ] Reached target Remo<30>[ 15.566355] systemd[1]: Reached target Remote File Systems. te File Systems. [ OK ] Reached target Slic<30>[ 15.589949] systemd[1]: Reached target Slices. es. [ OK ] Reached target Swap<30>[ 15.610003] systemd[1]: Reached target Swap. . [ OK ] Listening on<30>[ 15.630865] systemd[1]: Listening on initctl Compatibility Named Pipe. initctl Compatibility Named Pipe. [ OK ] Listening on Journa<30>[ 15.646273] systemd[1]: Listening on Journal Audit Socket. l Audit Socket. [ OK ] Listening on Journa<30>[ 15.670608] systemd[1]: Listening on Journal Socket (/dev/log). l Socket (/dev/log). [ OK ] Listening on<30>[ 15.695154] systemd[1]: Listening on Journal Socket. Journal Socket. [ OK ] Listening on udev C<30>[ 15.714549] systemd[1]: Listening on udev Control Socket. ontrol Socket. [ OK ] Listening on<30>[ 15.739000] systemd[1]: Listening on udev Kernel Socket. udev Kernel Socket. Mounting Huge Pages File Syste<30>[ 15.798292] systemd[1]: Mounting Huge Pages File System... m... Mounting POSIX Message Queue F<30>[ 15.822066] systemd[1]: Mounting POSIX Message Queue File System... ile System... Mounting Kernel Debug File Sys<30>[ 15.850071] systemd[1]: Mounting Kernel Debug File System... tem... Startin<30>[ 15.870157] systemd[1]: Condition check resulted in Kernel Trace File System being skipped. g Creat<30>[ 15.872624] systemd[1]: Starting Create list of static device nodes for the current kernel... e list of st…odes for the current kernel... Starting Load Kernel Module co<30>[ 15.910484] systemd[1]: Starting Load Kernel Module configfs... nfigfs... Starting Load Kernel Module dr<30>[ 15.933935] systemd[1]: Starting Load Kernel Module drm... m... <30>[ 15.954133] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped. Starting Journ<30>[ 15.970942] systemd[1]: Starting Journal Service... al Service... Startin<30>[ 15.992806] systemd[1]: Starting Load Kernel Modules... g Load Kernel Modules... Starting Remou<30>[ 16.019103] systemd[1]: Starting Remount Root and Kernel File Systems... nt Root and Kernel File Systems... Starting Coldplug All udev Dev<30>[ 16.046276] systemd[1]: Starting Coldplug All udev Devices... ices... [ OK ] Started Journal Ser<30>[ 16.070998] systemd[1]: Started Journal Service. vice. [ OK ] Mounted Huge Pages File System. [ OK ] Mounted POSIX Message Queue File System. [ OK ] Mounted Kernel Debug File System. [ OK ] Finished Create list of st… nodes for the current kernel. [ OK ] Finished Load Kernel Module configfs. [ OK ] Finished Load Kernel Module drm. [ OK ] Finished Load Kernel Modules. [FAILED] Failed to start Remount Root and Kernel File Systems. See 'systemctl status systemd-remount-fs.service' for details. Mounting Kernel Configuration File System... Starting Flush Journal to Persistent Storage... <46>[ 16.343344] systemd-journald[194]: Received client request to flush runtime journal. Starting Load/Save Random Seed... Starting Apply Kernel Variables... Starting Create System Users... [ OK ] Finished Coldplug All udev Devices. [ OK ] Mounted Kernel Configuration File System. [ OK ] Finished Flush Journal to Persistent Storage. [ OK ] Finished Load/Save Random Seed. [ OK ] Finished Apply Kernel Variables. [ OK ] Finished Create System Users. Starting Create Static Device Nodes in /dev... [ OK ] Finished Create Static Device Nodes in /dev. [ OK ] Reached target Local File Systems (Pre). [ OK ] Reached target Local File Systems. Starting Create Volatile Files and Directories... Starting Rule-based Manage…for Device Events and Files... [ OK ] Started Rule-based Manager for Device Events and Files. [ OK ] Finished Create Volatile Files and Directories. Starting Network Time Synchronization... Starting Update UTMP about System Boot/Shutdown... [ OK ] Started Network Time Synchronization. <6>[ 16.949227] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges: <6>[ 16.949272] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000 [ OK ] Created slice syste<6>[ 16.949282] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000 m-systemd\x2dbac<6>[ 16.978477] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000 klight.slice. <6>[ 16.989605] remoteproc remoteproc0: scp is available <3>[ 16.991257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 16.991343] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 16.991358] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <6>[ 16.991777] remoteproc remoteproc0: powering up scp [ OK [<6>[ 16.991799] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164 0m] Reached targ<6>[ 16.991829] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0 et Syst<3>[ 16.993203] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 em Time Set.<3>[ 16.993217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 16.993225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 16.993235] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 16.993242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 16.993289] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0 <3>[ 16.993352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 16.993360] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 16.993366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 16.993421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 16.993429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 16.993435] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 16.993442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 16.993449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <3>[ 16.993486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1 <4>[ 17.007292] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator <4>[ 17.007372] elants_i2c 4-0010: supply vccio not found, using dummy regulator [ OK [<6>[ 17.010911] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered 0m] Reached targ<6>[ 17.072141] usbcore: registered new interface driver r8152 <6>[ 17.081277] mc: Linux media interface: v0.10 et Syst<4>[ 17.081625] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA. <4>[ 17.081625] Fallback method does not support PEC. <6>[ 17.106343] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00 <6>[ 17.106355] pci_bus 0000:00: root bus resource [bus 00-ff] <6>[ 17.106361] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff] <6>[ 17.106363] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff]) em Time Synchron<6>[ 17.106398] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400 <6>[ 17.106411] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref] <6>[ 17.106478] pci 0000:00:00.0: supports D1 D2 <6>[ 17.106479] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold ized. <6>[ 17.107465] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring <6>[ 17.107543] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000 <6>[ 17.107567] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref] <6>[ 17.107582] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref] <6>[ 17.107597] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref] <6>[ 17.107698] pci 0000:01:00.0: supports D1 D2 <6>[ 17.107699] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold <6>[ 17.117051] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd <6>[ 17.117111] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e <6>[ 17.117120] remoteproc remoteproc0: remote processor scp is now up <6>[ 17.117769] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 <6>[ 17.117806] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref] <6>[ 17.117812] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref] <6>[ 17.117826] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref] <6>[ 17.117842] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref] <6>[ 17.117858] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref] <6>[ 17.117874] pci 0000:00:00.0: PCI bridge to [bus 01] <6>[ 17.117883] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref] <6>[ 17.118066] pcieport 0000:00:00.0: enabling device (0000 -> 0002) <6>[ 17.119381] pcieport 0000:00:00.0: PME: Signaling with IRQ 282 <6>[ 17.119660] pcieport 0000:00:00.0: AER: enabled with IRQ 282 <6>[ 17.125026] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2 <3>[ 17.151101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <6>[ 17.178364] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003 <3>[ 17.180030] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <6>[ 17.180551] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3 <6>[ 17.196635] videodev: Linux video capture interface: v2.00 <3>[ 17.199730] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <3>[ 17.221432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <6>[ 17.250979] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk <6>[ 17.261500] Bluetooth: Core ver 2.22 <6>[ 17.262127] usbcore: registered new interface driver cdc_ether <6>[ 17.262595] NET: Registered PF_BLUETOOTH protocol family <6>[ 17.262602] Bluetooth: HCI device and connection manager initialized <6>[ 17.262650] Bluetooth: HCI socket layer initialized <6>[ 17.262656] Bluetooth: L2CAP socket layer initialized <6>[ 17.262680] Bluetooth: SCO socket layer initialized <3>[ 17.264957] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <4>[ 17.280236] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2 <4>[ 17.280247] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2) <6>[ 17.293282] usbcore: registered new interface driver r8153_ecm <6>[ 17.308692] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741) <6>[ 17.311391] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4 <6>[ 17.311602] usbcore: registered new interface driver uvcvideo <3>[ 17.326313] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <6>[ 17.328621] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected <6>[ 17.330479] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered <6>[ 17.334737] usbcore: registered new interface driver btusb <5>[ 17.335746] cfg80211: Loading compiled-in X.509 certificates for regulatory database <4>[ 17.335980] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2 <3>[ 17.335992] Bluetooth: hci0: Failed to load firmware file (-2) <3>[ 17.335995] Bluetooth: hci0: Failed to set up firmware (-2) <4>[ 17.336002] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported. <6>[ 17.337804] r8152 2-1.3:1.0 eth0: v1.12.13 <6>[ 17.345580] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0 <5>[ 17.349770] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' <3>[ 17.356191] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <3>[ 17.357041] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6 <6>[ 17.357435] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0 <3>[ 17.371008] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <3>[ 17.393176] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5 <4>[ 17.698532] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 <6>[ 17.698552] cfg80211: failed to load regulatory.db Starting Load/Save Screen …of leds:white:kbd_backlight... [ OK ] Finished Update UTMP about System Boot/Shutdown. <6>[ 17.771558] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000 <6>[ 17.771667] mt7921e 0000:01:00.0: enabling device (0000 -> 0002) [ OK ] Finished Load/Save <6>[ 17.792088] mt7921e 0000:01:00.0: ASIC revision: 79610010 Screen …s of leds:white:kbd_backlight. [ OK ] Found device /dev/ttyS0. <4>[ 17.884963] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 [ OK ] Reached target Bluetooth. [ OK ] Reached target System Initialization. [ OK ] Started Discard unu<4>[ 17.992277] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 sed blocks once a week. [ OK ] Started Daily Cleanup of Temporary Directories. [ OK ] Reached target Timers. [ OK ] Listening on D-Bus System Message Bus Socket. [ OK ] Reached target Sockets. [ OK ] Reached target Basic System. <4>[ 18.099972] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 [ OK ] Listening on Load/Save RF …itch Status /dev/rfkill Watch. [ OK ] Started D-Bus System Message Bus. Starting User Login Management... <4>[ 18.209146] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 Starting Permit User Sessions... [ OK ] Finished Permit User Sessions. [ OK ] Started Getty on tty1. [ OK ] Started Serial Getty on ttyS0. [ OK ] Reached target Login Prompts. <4>[ 18.320440] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 Starting Load/Save RF Kill Switch Status... [ OK ] Started Load/Save RF Kill Switch Status. [ OK ] Started User Login Management. [ OK ] Reached target Multi-User System. [ OK ] Reached target Graphical Interface. <4>[ 18.428448] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 Starting Update UTMP about System Runlevel Changes... [ OK ] Finished Update UTMP about System Runlevel Changes. <4>[ 18.536797] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0 debian-bullseye-arm64 login: root (automatic login) Linux debian-bullseye-arm64 6.1.59-cip8-rt4 #1 SMP PREEMPT Sat Oct 28 19:29:28 UTC 2023 aarch64 The programs included with the Debian GNU/Linux system are free software; the exact distribution terms for each program are described in the individual files in /usr/share/doc/*/copyright. Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent permitted by applicable law. / # <4>[ 18.644655] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 / # # #<4>[ 18.752276] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 / # export SHELL=/bin/sh export SHELL=/bin/sh<4>[ 18.860055] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2 / # . /lava-11899592/environment . /lava-11899592/environment<3>[ 18.965933] mt7921e 0000:01:00.0: hardware init failed / # /lava-11899592/bin/lava-test-runner /lava-11899592/0 /lava-11899592/bin/lava-test-runner /lava-11899592/0 + export TESTRUN_ID=0_igt-kms-mediatek + cd /lava-11899592/0/tests/0_igt-kms-mediatek + cat uuid + UUID=1189959<8>[ 19.147570] 2_1.5.2.3.1 + set +x + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank <8>[ 19.182107] IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 19.202058] [IGT] core_auth: executing .1.59-cip8-rt4 a<14>[ 19.202344] [IGT] core_auth: starting subtest getclient-simple arch64) Startin<14>[ 19.202527] [IGT] core_auth: finished subtest getclient-simple, SUCCESS <14>[ 19.202647] [IGT] core_auth: exiting, ret=0 <8>[ 19.208261] <14>[ 19.231054] [IGT] core_auth: executing g subtest: getclient-simple Opened device: /dev<14>[ 19.242692] [IGT] core_auth: starting subtest getclient-master-drop <14>[ 19.242888] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS <14>[ 19.242973] [IGT] core_auth: exiting, ret=0 <8>[ 19.248071] /dri/card0 <14>[ 19.272940] [IGT] core_auth: executing <14>[ 19.273352] [IGT] core_auth: starting subtest basic-auth <14>[ 19.273496] [IGT] core_auth: finished subtest basic-auth, SUCCESS <14>[ 19.273549] [IGT] core_auth: exiting, ret=0 <8>[ 19.279292] Subtest getclien<14>[ 19.295024] [IGT] core_auth: executing t-simple: SUCCESS (0.000s) <14>[ 19.307350] [IGT] core_auth: starting subtest many-magics IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Startin<14>[ 19.317909] [IGT] core_auth: finished subtest many-magics, SUCCESS <14>[ 19.317963] [IGT] core_auth: exiting, ret=0 <8>[ 19.324712] <8>[ 19.325828] g subtest: getclient-master-drop Opened device: /dev/dri/card0 Subtest getclient-master-drop: SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: basic-auth <14>[ 19.363253] [IGT] core_getclient: executing <14>[ 19.363540] [IGT] core_getclient: exiting, ret=0 <8>[ 19.369774] Subtest basic-auth: SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: many-mag<14>[ 19.394077] [IGT] core_getstats: executing ics Reopening d<14>[ 19.394357] [IGT] core_getstats: exiting, ret=0 evice failed aft<8>[ 19.401884] er 1020 opens Subtest many-magics: SUCCESS (0.010s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 <14>[ 19.440278] [IGT] core_getversion: executing <14>[ 19.440587] [IGT] core_getversion: exiting, ret=0 <8>[ 19.447776] SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 19.487192] [IGT] core_setmaster_vs_auth: executing <14>[ 19.487562] [IGT] core_setmaster_vs_auth: exiting, ret=0 <8>[ 19.494637] rch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 SUCCESS (0.000s) <8>[ 19.520442] IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 19.534012] [IGT] drm_read: executing <14>[ 19.534467] [IGT] drm_read: exiting, ret=77 <8>[ 19.541489] .1.59-cip8-rt4 aarch64) Opened device: /dev/dri<14>[ 19.554066] [IGT] drm_read: executing <14>[ 19.554509] [IGT] drm_read: exiting, ret=77 <8>[ 19.561302] /card0 No KMS driver or no outputs, pipes: 8, outputs: 0 S<14>[ 19.573827] [IGT] drm_read: executing <14>[ 19.574318] [IGT] drm_read: exiting, ret=77 <8>[ 19.580334] ubtest invalid-buffer: SKIP (0.000s) IGT-Ve<14>[ 19.594814] [IGT] drm_read: executing <14>[ 19.595251] [IGT] drm_read: exiting, ret=77 <8>[ 19.602520] rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-<14>[ 19.614680] [IGT] drm_read: executing <14>[ 19.615123] [IGT] drm_read: exiting, ret=77 <8>[ 19.620869] cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest fault-buffer: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (<14>[ 19.648130] [IGT] drm_read: executing <14>[ 19.648719] [IGT] drm_read: exiting, ret=77 <8>[ 19.654034] aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opene<14>[ 19.666503] [IGT] drm_read: executing <14>[ 19.666928] [IGT] drm_read: exiting, ret=77 <8>[ 19.673304] <8>[ 19.674712] <8>[ 19.688685] d device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest empty-block: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pi<14>[ 19.714391] [IGT] kms_addfb_basic: executing <14>[ 19.719100] [IGT] kms_addfb_basic: starting subtest unused-handle pes: 8, outputs:<14>[ 19.729645] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS 0 Subtest empty-nonblock: SKIP (0.000s)[0<14>[ 19.738489] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 19.743758] m IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux<14>[ 19.756125] [IGT] kms_addfb_basic: executing <14>[ 19.760462] [IGT] kms_addfb_basic: starting subtest unused-pitches : 6.1.59-cip8-rt4 aarch64) Opened device: /dev/<14>[ 19.770078] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 [<14>[ 19.781808] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 19.786534] 1mSubtest short-buffer-block: SK<14>[ 19.799399] [IGT] kms_addfb_basic: executing <14>[ 19.803796] [IGT] kms_addfb_basic: starting subtest unused-offsets IP (0.000s) <14>[ 19.813538] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: <14>[ 19.822294] [IGT] kms_addfb_basic: exiting, ret=0 6.1.59-cip8-rt4 <8>[ 19.826628] aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest short-buffer-nonblock: S<14>[ 19.849510] [IGT] kms_addfb_basic: executing KIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4<14>[ 19.859865] [IGT] kms_addfb_basic: starting subtest unused-modifier <14>[ 19.859971] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS aarch64) Opene<14>[ 19.876617] [IGT] kms_addfb_basic: exiting, ret=0 d device: /dev/dri/card0 No KMS driver or no ou<8>[ 19.883378] tputs, pipes: 8, outputs: 0 Subtest short-buffer-wakeup: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Startin<14>[ 19.906285] [IGT] kms_addfb_basic: executing <14>[ 19.910757] [IGT] kms_addfb_basic: starting subtest clobberred-modifier g subtest: unused-handle Subtest unused-han<14>[ 19.922905] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP dle: SUCCESS (0.000s) Test requirement not <14>[ 19.934614] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 19.939231] met in function igt_require_i915<14>[ 19.951352] [IGT] kms_addfb_basic: executing <14>[ 19.955714] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete , file ../lib/drmtest.c:720: Test requirement: <14>[ 19.966447] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP is_i915_device(fd) Test requirement not met in <14>[ 19.978990] [IGT] kms_addfb_basic: exiting, ret=77 function igt_req<8>[ 19.983501] uire_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.2<14>[ 20.006134] [IGT] kms_addfb_basic: executing <14>[ 20.010711] [IGT] kms_addfb_basic: starting subtest legacy-format 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: unused<14>[ 20.027936] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS -pitches Subtest unused-pitches: SUCCESS (0<14>[ 20.038458] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 20.042943] .000s) Test requirement not met in function<14>[ 20.054624] [IGT] kms_addfb_basic: executing <14>[ 20.061043] [IGT] kms_addfb_basic: starting subtest no-handle igt_require_i91<14>[ 20.069532] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS 5, file ../lib/drmtest.c:720: Test requirement: is_i915_device(<14>[ 20.077963] [IGT] kms_addfb_basic: exiting, ret=0 fd) Test requir<8>[ 20.082551] ement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No<14>[ 20.104878] [IGT] kms_addfb_basic: executing KMS driver or no outputs, pipes: 8, outputs: 0 <14>[ 20.111862] [IGT] kms_addfb_basic: starting subtest basic <14>[ 20.112022] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS IGT-Version: 1.27.1-g621c2d3 (a<14>[ 20.127470] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 20.134571] arch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dr<14>[ 20.145405] [IGT] kms_addfb_basic: executing i/card0 Starting subtest: unuse<14>[ 20.152015] [IGT] kms_addfb_basic: starting subtest bad-pitch-0 <14>[ 20.152105] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS d-offsets Subtest unused-of<14>[ 20.168172] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 20.172435] fsets: SUCCESS (0.000s) Test requirement no<14>[ 20.182852] [IGT] kms_addfb_basic: executing <14>[ 20.189180] [IGT] kms_addfb_basic: starting subtest bad-pitch-32 t met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: unused-modifier Subtest unused-modifier: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: clobberred-modifier Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Subtest clobberred-modifier: SKIP (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: invalid-smem-bo-on-discrete Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:715: Test requirement: is_intel_device(fd) Subtest invalid-smem-bo-on-discrete: SKIP (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: legacy-format Successfully fuzzed 10000 {bpp, depth} variations Subtest legacy-format: SUCCESS (0.006s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: no-handle Subtest no-handle: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: basic Subtest basic: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: bad-pitch-0 Subtest bad-pitch-0: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_dev<14>[ 20.530082] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS ice(fd) No KMS <14>[ 20.541371] [IGT] kms_addfb_basic: exiting, ret=0 driver or no out<8>[ 20.546067] puts, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: bad-pitch-32 Subtest <14>[ 20.568821] [IGT] kms_addfb_basic: executing bad-pitch-32: SUCCESS (0.000s)[<14>[ 20.576044] [IGT] kms_addfb_basic: starting subtest bad-pitch-63 <14>[ 20.576223] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS 0m Test requirement not met in <14>[ 20.592300] [IGT] kms_addfb_basic: exiting, ret=0 function igt_req<8>[ 20.597741] uire_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: <14>[ 20.621295] [IGT] kms_addfb_basic: executing Test requirement: is_i915_device(fd) No KMS dri<14>[ 20.628346] [IGT] kms_addfb_basic: starting subtest bad-pitch-128 <14>[ 20.628478] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS ver or no output<14>[ 20.644921] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 20.650349] s, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64)<14>[ 20.663355] [IGT] kms_addfb_basic: executing <14>[ 20.669993] [IGT] kms_addfb_basic: starting subtest bad-pitch-256 Opened device: /dev/dri/card0 Starting subtes<14>[ 20.677838] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS t: bad-pitch-63 <14>[ 20.689466] [IGT] kms_addfb_basic: exiting, ret=0 Subtest bad<8>[ 20.694071] -pitch-63: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test r<14>[ 20.717144] [IGT] kms_addfb_basic: executing equirement not met in function igt_require_i915,<14>[ 20.724460] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024 <14>[ 20.724543] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS file ../lib/drm<14>[ 20.740804] [IGT] kms_addfb_basic: exiting, ret=0 test.c:720: Tes<8>[ 20.745558] t requirement: is_i915_device(fd<14>[ 20.757725] [IGT] kms_addfb_basic: executing ) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2<14>[ 20.769386] [IGT] kms_addfb_basic: starting subtest bad-pitch-999 <14>[ 20.769483] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS d3 (aarch64) (Linux: 6.1.59-cip8<14>[ 20.783997] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 20.788556] -rt4 aarch64) Opened device: /dev/dri/card0 St<14>[ 20.800352] [IGT] kms_addfb_basic: executing <14>[ 20.806902] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536 arting subtest: bad-pitch-128 Subtest bad-p<14>[ 20.814426] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS itch-128: SUCCESS (0.000s) Test requirement<14>[ 20.826288] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 20.832002] not met in function igt_require_i915, file ../l<14>[ 20.842963] [IGT] kms_addfb_basic: executing <14>[ 20.851354] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any ib/drmtest.c:720: Test requirement: is_i915_dev<14>[ 20.858548] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS ice(fd) Test requirement not met in function ig<14>[ 20.870703] [IGT] kms_addfb_basic: exiting, ret=0 t_require_i915, <8>[ 20.874932] file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs<14>[ 20.897654] [IGT] kms_addfb_basic: executing : 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: b<14>[ 20.911556] [IGT] kms_addfb_basic: starting subtest invalid-get-prop <14>[ 20.911653] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS ad-pitch-256 [<14>[ 20.928561] [IGT] kms_addfb_basic: exiting, ret=0 1mSubtest bad-pi<8>[ 20.933249] tch-256: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met<14>[ 20.955785] [IGT] kms_addfb_basic: executing in function igt_require_i915, f<14>[ 20.964952] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any <14>[ 20.965026] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS ile ../lib/drmte<14>[ 20.981404] [IGT] kms_addfb_basic: exiting, ret=0 st.c:720: Test <8>[ 20.986204] requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Ope<14>[ 21.009459] [IGT] kms_addfb_basic: executing ned device: /dev/dri/card0 Starting subtest: bad-pitch-1024 Subtest bad-pitch-1024: SUCCESS (0.000s) Test requirement<14>[ 21.023899] [IGT] kms_addfb_basic: starting subtest invalid-set-prop <14>[ 21.024026] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS not met in func<14>[ 21.040673] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 21.045548] tion igt_require_i915, file ../lib/drmtest.c:720<14>[ 21.057024] [IGT] kms_addfb_basic: executing : Test requirement: is_i915_device(fd) Test requirement not met in function ig<14>[ 21.067516] [IGT] kms_addfb_basic: starting subtest master-rmfb <14>[ 21.067665] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS t_require_i915, file ../lib/drmt<14>[ 21.083567] [IGT] kms_addfb_basic: exiting, ret=0 est.c:720: Test<8>[ 21.088308] requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /de<14>[ 21.111082] [IGT] kms_addfb_basic: executing v/dri/card0 Starting subtest: bad-pitch-999 Subtest bad-pitch-999: SUCCESS<14>[ 21.124195] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag <14>[ 21.124314] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS <14>[ 21.124534] [IGT] kms_addfb_basic: exiting, ret=0 <8>[ 21.129512] <14>[ 21.142219] [IGT] kms_addfb_basic: executing (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt<14>[ 21.171516] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier _require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: bad-pitch-65536 Subtest bad-pitch-65536: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: invalid-get-prop-any Subtest invalid-get-prop-any: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: invalid-get-prop Subtest invalid-get-prop: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: invalid-set-prop-any Subtest invalid-set-prop-any: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: invalid-set-prop Subtest invalid-set-prop: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: master-rmfb Subtest master-rmfb: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: addfb25-modifier-no-flag Subtest addfb25-modifier-no-flag: SUCCESS (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: addfb25-bad-modifier (kms_addfb_basic:442) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662: (kms_addfb_basic:442) CRITICAL: Failed assertion: igt_ioctl((fd)<14>[ 21.516179] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL <14>[ 21.516397] [IGT] kms_addfb_basic: exiting, ret=98 <8>[ 21.521006] , ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0<14>[ 21.538794] [IGT] kms_addfb_basic: executing +8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))),<14>[ 21.551328] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 21.555880] (&f)) == -1 (kms_addfb_basic:4<14>[ 21.568442] [IGT] kms_addfb_basic: executing 42) CRITICAL: error: 0 != -1 Stack trace: #0 ../lib/igt_core.c:1971 __igt_fa<14>[ 21.581023] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 21.585534] il_assert() #1 [+0xbd0547e0] #2 [+0xbd056278] #3 [[ 21.598067] [IGT] kms_addfb_basic: executing known>+0xbd05167c] #4 [__libc_start_main+0xe8] #5 [+0xbd0516b4] <14>[ 21.610919] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 21.615457] #6 [+0xbd0516b4] Sub<14>[ 21.628499] [IGT] kms_addfb_basic: executing test addfb25-bad-modifier failed. **** DEBUG **** (kms_addfb_basic:442) ioctl_<14>[ 21.641358] [IGT] kms_addfb_basic: exiting, ret=77 wrappers-DEBUG: <8>[ 21.646208] Test requirement passed: igt_has_fb_modifiers(fd) (kms_addfb_basic:442) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.<14>[ 21.668831] [IGT] kms_addfb_basic: executing c:662: (kms_addfb_basic:442) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (<14>[ 21.682155] [IGT] kms_addfb_basic: exiting, ret=77 ((0xB8)) << 0) |<8>[ 21.686529] ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1 (kms_addfb_basic:442) CRITICAL: error: 0 != -1 (kms_addfb_basic:442) igt_core-INFO: Stack<14>[ 21.712350] [IGT] kms_addfb_basic: executing trace: (kms_addfb_basic:442) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert() (kms_addfb_basic:442) igt_core-IN<14>[ 21.726117] [IGT] kms_addfb_basic: exiting, ret=77 FO: #1 [[ 21.730469] wn>+0xbd0547e0] (kms_addfb_basic:442) igt_core-INFO: #2 [+0xbd056278] (kms_addfb_basic:442) igt_core-INFO: #3 [+0xbd05167c] (kms_addfb_basic:442) igt_core-INFO: #4 [__libc_start_mai<14>[ 21.758292] [IGT] kms_addfb_basic: executing n+0xe8] (kms_addfb_basic:442) igt_core-INFO: #5 [+0xbd0516b4] (kms_<14>[ 21.771789] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 21.777273] addfb_basic:442) igt_core-INFO: #6 [+0xbd0516b4] **** END **** [<14>[ 21.790826] [IGT] kms_addfb_basic: executing 1mSubtest addfb25-bad-modifier: FAIL (0.345s) Test requirement not met in f<14>[ 21.803677] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 21.808541] unction igt_require_i915, file ../lib/drmtest.c:<14>[ 21.820987] [IGT] kms_addfb_basic: executing 720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Subtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Subtest addfb25-x-tiled-legacy: SKIP (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Subtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Subtest basic-x-tiled-legacy: SKIP (0.000s) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Subtest framebuffer-vs-set-tiling: SKIP (0.000s) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Subtest tile-pitch-mismatch: SKIP (0.000s) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Subtest basic-y-tiled-legacy: SKIP (0.000s) No KMS driver or no outputs, pipes: 8, outputs: 0 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest size-max: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requireme<14>[ 22.166452] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 22.171076] nt not met in function igt_require_i915, file ..<14>[ 22.182755] [IGT] kms_addfb_basic: executing /lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function <14>[ 22.195363] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 22.200085] igt_require_i915, file ../lib/dr<14>[ 22.212478] [IGT] kms_addfb_basic: executing mtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outpu<14>[ 22.225234] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 22.229987] ts: 0 Subtest too-wide: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 22.242276] [IGT] kms_addfb_basic: executing rch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met<14>[ 22.255111] [IGT] kms_addfb_basic: exiting, ret=77 in function igt<8>[ 22.259642] _require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 22.282682] [IGT] kms_addfb_basic: executing 0: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 [1<14>[ 22.296537] [IGT] kms_addfb_basic: exiting, ret=77 mSubtest too-high: SKIP (0.000s)<8>[ 22.304316]  IGT-Version: 1.27.1-g621c2<14>[ 22.316929] [IGT] kms_addfb_basic: executing d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib<14>[ 22.329679] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 22.335962] /drmtest.c:720: Test requiremen<14>[ 22.348305] [IGT] kms_addfb_basic: executing t: is_i915_device(fd) Test requirement not met in function igt_require_i915, fi<14>[ 22.361080] [IGT] kms_addfb_basic: exiting, ret=77 <8>[ 22.365866] le ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or<14>[ 22.378138] [IGT] kms_addfb_basic: executing no outputs, pipes: 8, outputs: 0 Subtest bo-too-small: SKIP (0.000s) <14>[ 22.390993] [IGT] kms_addfb_basic: exiting, ret=77 IGT-Version: 1.2<8>[ 22.395672] 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmte<14>[ 22.418737] [IGT] kms_addfb_basic: executing st.c:720: Test requirement: is_i915_device(fd) Test requirement not met in fun<14>[ 22.432352] [IGT] kms_addfb_basic: exiting, ret=77 ction igt_require_i915, file ../<8>[ 22.440001] <8>[ 22.442887] lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8,<8>[ 22.458070] outputs: 0 Subtest small-bo: SKIP (0.000s) IGT-Version: 1.27.1-g621c2<14>[ 22.470596] [IGT] kms_atomic: executing <14>[ 22.471024] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.476891] d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) O<14>[ 22.491115] [IGT] kms_atomic: executing pened device: /d<14>[ 22.491549] [IGT] kms_atomic: exiting, ret=77 ev/dri/card0 Te<8>[ 22.496141] st requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requiremen<14>[ 22.519407] [IGT] kms_atomic: executing <14>[ 22.519995] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.525278] t: is_i915_devic<14>[ 22.540698] [IGT] kms_atomic: executing e(fd) Test requ<14>[ 22.541112] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.547760] irement not met in function igt_<14>[ 22.560054] [IGT] kms_atomic: executing require_i915, fi<14>[ 22.560435] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.567647] le ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest bo-too-small-due-to-tiling: SKIP (0.000s) IG<14>[ 22.590456] [IGT] kms_atomic: executing <14>[ 22.591083] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.596605] T-Version: 1.27.1-g621c2d3 (aarc<14>[ 22.611618] [IGT] kms_atomic: executing <14>[ 22.612010] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.620396] h64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened de<14>[ 22.631336] [IGT] kms_atomic: executing vice: /dev/dri/c<14>[ 22.631718] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.636364] ard0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement <14>[ 22.662967] [IGT] kms_atomic: executing <14>[ 22.663529] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.668565] not met in function igt_require_i915, file ../li<14>[ 22.682560] [IGT] kms_atomic: executing <14>[ 22.682955] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.689292] b/drmtest.c:720: Test requireme<14>[ 22.703758] [IGT] kms_atomic: executing nt: is_i915_devi<14>[ 22.704148] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.708275] ce(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest addfb25-y-tiled-legacy: SKIP (0.000s)<14>[ 22.731403] [IGT] kms_atomic: executing <14>[ 22.731966] [IGT] kms_atomic: exiting, ret=77 <8>[ 22.737259] <8>[ 22.738442] IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/d<8>[ 22.760979] ri/card0 Test requirement not met in function igt_require_i915,<14>[ 22.771324] [IGT] kms_flip_event_leak: executing <14>[ 22.771688] [IGT] kms_flip_event_leak: exiting, ret=77 <8>[ 22.776044] <8>[ 22.778919] file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file .<8>[ 22.805373] ./lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no <14>[ 22.815829] [IGT] kms_prop_blob: executing <14>[ 22.816132] [IGT] kms_prop_blob: starting subtest basic <14>[ 22.816182] [IGT] kms_prop_blob: finished subtest basic, SUCCESS <14>[ 22.816224] [IGT] kms_prop_blob: exiting, ret=0 outputs, pipes: 8, outputs: 0 <8>[ 22.823108] <14>[ 22.839935] [IGT] kms_prop_blob: executing <14>[ 22.840227] [IGT] kms_prop_blob: starting subtest blob-prop-core <14>[ 22.840277] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS <14>[ 22.840323] [IGT] kms_prop_blob: exiting, ret=0 <8>[ 22.845230] <14>[ 22.859890] [IGT] kms_prop_blob: executing [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest addfb25-y-tiled-small-legacy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720: Test requirement: is_i915_device(fd) No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest addfb25-4-tiled: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest plane-overlay-legacy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest plane-primary-legacy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest plane-primary-overlay-mutable-zpos: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest plane-immutable-zpos: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest test-only: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest plane-cursor-legacy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest plane-invalid-params: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest plane-invalid-params-fence: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest crtc-invalid-params: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest crtc-invalid-params-fence: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest atomic-invalid-params: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest atomic_plane_damage: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest basic: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: basic Subtest basic: SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d<14>[ 23.217090] [IGT] kms_prop_blob: starting subtest blob-prop-validate <14>[ 23.217254] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS <14>[ 23.217340] [IGT] kms_prop_blob: exiting, ret=0 <8>[ 23.221612] <14>[ 23.237254] [IGT] kms_prop_blob: executing 3 (aarch64) (Lin<14>[ 23.249341] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime <14>[ 23.249418] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS <14>[ 23.249459] [IGT] kms_prop_blob: exiting, ret=0 <8>[ 23.253541] ux: 6.1.59-cip8-<14>[ 23.277168] [IGT] kms_prop_blob: executing <14>[ 23.277454] [IGT] kms_prop_blob: starting subtest blob-multiple <14>[ 23.277574] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS <14>[ 23.277611] [IGT] kms_prop_blob: exiting, ret=0 <8>[ 23.281611] <14>[ 23.296342] [IGT] kms_prop_blob: executing rt4 aarch64) Op<14>[ 23.312858] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any <14>[ 23.312903] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS <14>[ 23.312940] [IGT] kms_prop_blob: exiting, ret=0 <8>[ 23.319200] <14>[ 23.333516] [IGT] kms_prop_blob: executing ened device: /dev/dri/card0 Starting subtest: blob-prop-core <14>[ 23.345858] [IGT] kms_prop_blob: starting subtest invalid-get-prop <14>[ 23.345921] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS <14>[ 23.345958] [IGT] kms_prop_blob: exiting, ret=0 <8>[ 23.349986] [1mSubtest blob-<14>[ 23.377242] [IGT] kms_prop_blob: executing <14>[ 23.377544] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any <14>[ 23.377592] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS <14>[ 23.377629] [IGT] kms_prop_blob: exiting, ret=0 <8>[ 23.383994] <14>[ 23.402483] [IGT] kms_prop_blob: executing prop-core: SUCCESS (0.000s) IGT-Version: 1.<14>[ 23.414756] [IGT] kms_prop_blob: starting subtest invalid-set-prop <14>[ 23.414805] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS <14>[ 23.414840] [IGT] kms_prop_blob: exiting, ret=0 <8>[ 23.418973] <8>[ 23.421150] <8>[ 23.433640] 27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened<14>[ 23.453924] [IGT] kms_setmode: executing <14>[ 23.454258] [IGT] kms_setmode: starting subtest basic <14>[ 23.454306] [IGT] kms_setmode: finished subtest basic, SKIP <14>[ 23.454347] [IGT] kms_setmode: exiting, ret=77 <8>[ 23.458568] device: /dev/dri/card0 Starting subtest: blob-<14>[ 23.486382] [IGT] kms_setmode: executing <14>[ 23.486735] [IGT] kms_setmode: starting subtest basic-clone-single-crtc <14>[ 23.486782] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP <14>[ 23.486830] [IGT] kms_setmode: exiting, ret=77 <8>[ 23.491003] prop-validate Subtest blob-prop-validate: S<14>[ 23.522044] [IGT] kms_setmode: executing <14>[ 23.522379] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc UCCESS (0.000s)<14>[ 23.522425] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP <14>[ 23.522466] [IGT] kms_setmode: exiting, ret=77 <8>[ 23.526805] [0m IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Op<14>[ 23.562773] [IGT] kms_setmode: executing ened device: /de<14>[ 23.563186] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc <14>[ 23.563261] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP v/dri/card0 Sta<14>[ 23.563340] [IGT] kms_setmode: exiting, ret=77 <8>[ 23.568694] rting subtest: blob-prop-lifetime Subtest blob-prop-lifetim<14>[ 23.601732] [IGT] kms_setmode: executing <14>[ 23.602331] [IGT] kms_setmode: starting subtest clone-exclusive-crtc <14>[ 23.602377] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP <14>[ 23.602416] [IGT] kms_setmode: exiting, ret=77 <8>[ 23.608355] e: SUCCESS (0.000s) IGT-Version: 1.27.1-g62<14>[ 23.638061] [IGT] kms_setmode: executing <14>[ 23.638393] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing <14>[ 23.638443] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP <14>[ 23.638485] [IGT] kms_setmode: exiting, ret=77 <8>[ 23.645066] <8>[ 23.647770] <8>[ 23.675702] 1c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device:<14>[ 23.686369] [IGT] kms_vblank: executing /dev/dri/card0 <14>[ 23.686842] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.695011] Starting subtest: blob-multiple<14>[ 23.707759] [IGT] kms_vblank: executing <14>[ 23.708181] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.713929] Subtest blob-multiple: SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/<14>[ 23.736870] [IGT] kms_vblank: executing <14>[ 23.737748] [IGT] kms_vblank: exiting, ret=77 dri/card0 Starting subtest: invalid-get-prop-any Subtest invalid-get-prop-<8>[ 23.752413] any: SUCCESS (0.000s) IGT-Version: 1.27.1-g<14>[ 23.762704] [IGT] kms_vblank: executing <14>[ 23.763170] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.769711] 621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch6<14>[ 23.782559] [IGT] kms_vblank: executing <14>[ 23.783043] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.788745] 4) Opened device: /dev/dri/card<14>[ 23.803494] [IGT] kms_vblank: executing 0 Starting subt<14>[ 23.803959] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.808004] est: invalid-get-prop Subtest invalid-get-prop: SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59<14>[ 23.831020] [IGT] kms_vblank: executing <14>[ 23.831884] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.837595] -cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: invalid-set<14>[ 23.856951] [IGT] kms_vblank: executing <14>[ 23.857880] [IGT] kms_vblank: exiting, ret=77 -prop-any Subtest invalid-set-prop-any: SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt<8>[ 23.874479] 4 aarch64) Opened device: /dev/dri/card0 Starting subtest: invalid-set-prop Subtest invalid-set-prop: SUCCESS (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt<14>[ 23.900041] [IGT] kms_vblank: executing <14>[ 23.900939] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.906082] 4 aarch64) Opened device: /dev/<14>[ 23.919947] [IGT] kms_vblank: executing dri/card0 Start<14>[ 23.920432] [IGT] kms_vblank: exiting, ret=77 ing subtest: bas<8>[ 23.924756] ic No dynamic tests executed. Subtest basic: SKIP (0.000s) IGT-Version: 1.27.1-g621c2<14>[ 23.949133] [IGT] kms_vblank: executing d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) O<14>[ 23.950056] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.959915] pened device: /dev/dri/card0 St<14>[ 23.972245] [IGT] kms_vblank: executing arting subtest: <14>[ 23.972753] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.979676] basic-clone-sing<14>[ 23.992635] [IGT] kms_vblank: executing le-crtc No dyna<14>[ 23.993108] [IGT] kms_vblank: exiting, ret=77 <8>[ 23.997240] mic tests executed. Subtest basic-clone-single-crtc: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<14>[ 24.021467] [IGT] kms_vblank: executing 59-cip8-rt4 aarch64) Opened dev<14>[ 24.027747] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.031978] ice: /dev/dri/card0 Starting subtest: invalid-c<14>[ 24.042652] [IGT] kms_vblank: executing lone-single-crtc<14>[ 24.043138] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.049808] No dynamic tes<14>[ 24.064765] [IGT] kms_vblank: executing ts executed. Subtest invalid-clone-single-crtc: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: invalid-clone-exclusive-crtc No dynamic tests executed. Subtest invalid-clone-exclusive-crtc: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: clone-exclusive-crtc No dynamic tests executed. Subtest clone-exclusive-crtc: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 Starting subtest: invalid-clone-single-crtc-stealing No dynamic tests executed. Subtest invalid-clone-single-crtc-stealing: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest invalid: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest crtc-id: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-accuracy-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-query-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-query-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-query-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-query-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-query-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-query-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-query-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-query-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-wait-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-wait-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-wait-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-wait-forked-<14>[ 24.402561] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.407179] hang: SKIP (0.000s) IGT-Version: 1.27.1-g62<14>[ 24.418468] [IGT] kms_vblank: executing <14>[ 24.418951] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.424982] 1c2d3 (aarch64) (Linux: 6.1.59-c<14>[ 24.439333] [IGT] kms_vblank: executing ip8-rt4 aarch64)<14>[ 24.439857] [IGT] kms_vblank: exiting, ret=77 Opened device:<8>[ 24.444943] /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-wait-busy<14>[ 24.467918] [IGT] kms_vblank: executing <14>[ 24.468827] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.474114] : SKIP (0.000s) IGT-Version<14>[ 24.487292] [IGT] kms_vblank: executing <14>[ 24.487839] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.495184] : 1.27.1-g621c2d3 (aarch64) (Lin<14>[ 24.507256] [IGT] kms_vblank: executing ux: 6.1.59-cip8-<14>[ 24.507799] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.512341] rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-wait-busy-hang: SKIP (0.000s) IGT-Versio<14>[ 24.537940] [IGT] kms_vblank: executing <14>[ 24.538799] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.544148] n: 1.27.1-g621c2d3 (aarch64) (Li<14>[ 24.560421] [IGT] kms_vblank: executing <14>[ 24.560935] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.567517] nux: 6.1.59-cip8<14>[ 24.581080] [IGT] kms_vblank: executing <14>[ 24.581603] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.586190] -rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-wait-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g62<14>[ 24.610486] [IGT] kms_vblank: executing <14>[ 24.611335] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.616654] 1c2d3 (aarch64) <14>[ 24.632610] [IGT] kms_vblank: executing <14>[ 24.633093] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.640037] (Linux: 6.1.59-cip8-rt4 aarch64)<14>[ 24.651888] [IGT] kms_vblank: executing Opened device:<14>[ 24.652379] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.656593] /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-wait-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS <14>[ 24.690343] [IGT] kms_vblank: executing <14>[ 24.691130] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.696083] driver or no outputs, pipes: 8, outputs: 0 <14>[ 24.711204] [IGT] kms_vblank: executing <14>[ 24.711681] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.719067] Subtest pipe-A-ts-continuation-i<14>[ 24.731717] [IGT] kms_vblank: executing <14>[ 24.732207] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.736430] dle: SKIP (0.000s) IGT-Version: 1.27.1-g621<14>[ 24.751255] [IGT] kms_vblank: executing <14>[ 24.751739] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.758710] c2d3 (aarch64) (Linux: 6.1.59-ci<14>[ 24.771964] [IGT] kms_vblank: executing <14>[ 24.772431] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.776680] p8-rt4 aarch64) Opened device: <14>[ 24.791623] [IGT] kms_vblank: executing /dev/dri/card0 <14>[ 24.792110] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.798922] No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s) IGT-Version:<14>[ 24.821122] [IGT] kms_vblank: executing 1.27.1-g621c2d3 (aarch64) (Linu<14>[ 24.822116] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.832596] x: 6.1.59-cip8-rt4 aarch64) Opened device: /dev<14>[ 24.843219] [IGT] kms_vblank: executing /dri/card0 No K<14>[ 24.843692] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.848935] MS driver or no <14>[ 24.865317] [IGT] kms_vblank: executing outputs, pipes: 8, outputs: 0 Subtest pipe-<14>[ 24.865870] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.877684] A-ts-continuation-dpms-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS dr<14>[ 24.899720] [IGT] kms_vblank: executing iver or no outpu<14>[ 24.900571] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.905616] ts, pipes: 8, outputs: 0 Subtest pipe-A-ts-continuation-dpms-suspend: SKIP <14>[ 24.924902] [IGT] kms_vblank: executing <14>[ 24.926103] [IGT] kms_vblank: exiting, ret=77 (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS dri<8>[ 24.942433] ver or no outputs, pipes: 8, outputs: 0 Sub<14>[ 24.954526] [IGT] kms_vblank: executing <14>[ 24.955005] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.960589] test pipe-A-ts-continuation-suspend: SKIP (0.000<14>[ 24.975118] [IGT] kms_vblank: executing s) IGT-Vers<14>[ 24.975605] [IGT] kms_vblank: exiting, ret=77 <8>[ 24.979947] ion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or<14>[ 25.002681] [IGT] kms_vblank: executing no outputs, pip<14>[ 25.003553] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.008827] es: 8, outputs: 0 Subtest pipe-A-ts-continuation-modeset: S<14>[ 25.027916] [IGT] kms_vblank: executing <14>[ 25.028802] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.034055] KIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opene<14>[ 25.053421] [IGT] kms_vblank: executing d device: /dev/dri/card0 No KMS<14>[ 25.059938] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.064813] driver or no outputs, pipes: 8, outputs: 0 [1<14>[ 25.075281] [IGT] kms_vblank: executing mSubtest pipe-A-<14>[ 25.075760] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.079783] ts-continuation-modeset-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: <14>[ 25.102618] [IGT] kms_vblank: executing <14>[ 25.103495] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.108714] 6.1.59-cip8-rt4 aarch64) Opened<14>[ 25.123275] [IGT] kms_vblank: executing device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-accuracy-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-query-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-query-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-query-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-query-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-query-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-query-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-query-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-query-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-wait-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-wait-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-wait-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-wait-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-wait-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-wait-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-wait-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-wait-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no o<14>[ 25.461377] [IGT] kms_vblank: exiting, ret=77 utputs, pipes: 8<8>[ 25.466233] , outputs: 0 Subtest pipe-B-ts-continuation-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device<14>[ 25.488923] [IGT] kms_vblank: executing <14>[ 25.490098] [IGT] kms_vblank: exiting, ret=77 : /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest<8>[ 25.504916] pipe-B-ts-continuation-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pip<14>[ 25.531942] [IGT] kms_vblank: executing <14>[ 25.532799] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.538440] e-B-ts-continuat<14>[ 25.552819] [IGT] kms_vblank: executing <14>[ 25.553391] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.558087] ion-dpms-rpm: SKIP (0.000s) <14>[ 25.571661] [IGT] kms_vblank: executing IGT-Version: 1.<14>[ 25.572214] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.578852] 27.1-g621c2d3 (a<14>[ 25.593297] [IGT] kms_vblank: executing arch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened<14>[ 25.593954] [IGT] kms_vblank: exiting, ret=77 device: /dev/dr<8>[ 25.603434] i/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s) IGT-Version: 1.2<14>[ 25.626686] [IGT] kms_vblank: executing 7.1-g621c2d3 (aa<14>[ 25.627562] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.632824] rch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri<14>[ 25.652328] [IGT] kms_vblank: executing <14>[ 25.653223] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.658610] /card0 No KMS driver or no outp<14>[ 25.671882] [IGT] kms_vblank: executing uts, pipes: 8, o<14>[ 25.672416] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.680030] utputs: 0 Subtest pipe-B-ts-continuation-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device<14>[ 25.702960] [IGT] kms_vblank: executing : /dev/dri/card0<14>[ 25.703771] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.708848] No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-ts-conti<14>[ 25.729372] [IGT] kms_vblank: executing nuation-modeset: SKIP (0.000s)[<14>[ 25.735812] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.740841] 0m IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<14>[ 25.751707] [IGT] kms_vblank: executing <14>[ 25.752234] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.756676] x: 6.1.59-cip8-rt4 aarch64) Ope<14>[ 25.771720] [IGT] kms_vblank: executing ned device: /dev<14>[ 25.772205] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.776460] /dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Open<14>[ 25.806067] [IGT] kms_vblank: executing <14>[ 25.806900] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.812301] ed device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 [<14>[ 25.832637] [IGT] kms_vblank: executing <14>[ 25.833432] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.838525] 1mSubtest pipe-B-ts-continuation-modeset-rpm: SK<14>[ 25.850819] [IGT] kms_vblank: executing <14>[ 25.851314] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.856828] IP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dr<14>[ 25.879460] [IGT] kms_vblank: executing <14>[ 25.880231] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.885016] i/card0 No KMS driver or no outputs, pipes: 8, <14>[ 25.898279] [IGT] kms_vblank: executing <14>[ 25.898759] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.904476] outputs: 0 Subtest pipe-C-accuracy-idle: SK<14>[ 25.919123] [IGT] kms_vblank: executing IP (0.000s) <14>[ 25.919601] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.923797] IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS <14>[ 25.946880] [IGT] kms_vblank: executing <14>[ 25.947713] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.952855] driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-query-idle: SKIP <14>[ 25.972009] [IGT] kms_vblank: executing <14>[ 25.972864] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.978122] (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarc<14>[ 25.990758] [IGT] kms_vblank: executing <14>[ 25.991259] [IGT] kms_vblank: exiting, ret=77 <8>[ 25.999549] h64) (Linux: 6.1.59-cip8-rt4 aar<14>[ 26.011580] [IGT] kms_vblank: executing ch64) Opened de<14>[ 26.012062] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.016154] vice: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-query-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 26.041859] [IGT] kms_vblank: executing <14>[ 26.042645] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.047757] rch64) (Linux: 6.1.59-cip8-rt4 a<14>[ 26.063687] [IGT] kms_vblank: executing arch64) Opened <14>[ 26.064165] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.068393] device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-query-forked: SKIP<14>[ 26.091061] [IGT] kms_vblank: executing <14>[ 26.091948] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.097121] (0.000s) IGT-Version: 1.27<14>[ 26.112326] [IGT] kms_vblank: executing <14>[ 26.112825] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.117108] .1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outpu<14>[ 26.141101] [IGT] kms_vblank: executing ts, pipes: 8, outputs: 0 Subtest pipe-C-que<14>[ 26.142042] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.151019] ry-forked-hang: SKIP (0.000s)[0<14>[ 26.164413] [IGT] kms_vblank: executing <14>[ 26.164890] [IGT] kms_vblank: exiting, ret=77 m IGT-Version: <8>[ 26.173318] 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt<14>[ 26.186081] [IGT] kms_vblank: executing <14>[ 26.186567] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.193100] 4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-query-busy: SKI<14>[ 26.216661] [IGT] kms_vblank: executing <14>[ 26.217465] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.222764] P (0.000s) <14>[ 26.236657] [IGT] kms_vblank: executing <14>[ 26.237119] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.241265] IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outp<14>[ 26.263512] [IGT] kms_vblank: executing uts, pipes: 8, outputs: 0 Subtest pipe-C-query-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-query-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-query-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-wait-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-wait-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-wait-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-wait-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-wait-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-wait-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-wait-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-wait-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-ts-continuation-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-ts-continuation-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-ts-continuation-modeset: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No <14>[ 26.601066] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.606050] KMS driver or no outputs, pipes:<14>[ 26.616330] [IGT] kms_vblank: executing <14>[ 26.616854] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.623856] 8, outputs: 0 Subtest pipe-C-ts-continuati<14>[ 26.634921] [IGT] kms_vblank: executing <14>[ 26.635408] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.639858] on-modeset-rpm: SKIP (0.000s)[0<14>[ 26.655472] [IGT] kms_vblank: executing <14>[ 26.655985] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.663054] m IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-accuracy-idle: <14>[ 26.685934] [IGT] kms_vblank: executing <14>[ 26.686695] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.692433] SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt<14>[ 26.712708] [IGT] kms_vblank: executing <14>[ 26.713493] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.719385] 4 aarch64) Opened device: /dev/<14>[ 26.731580] [IGT] kms_vblank: executing <14>[ 26.732136] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.740707] dri/card0 No KMS driver or no o<14>[ 26.752432] [IGT] kms_vblank: executing <14>[ 26.752972] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.758919] utputs, pipes: 8, outputs: 0 Subtest pipe-D<14>[ 26.770850] [IGT] kms_vblank: executing <14>[ 26.771380] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.775795] -query-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened <14>[ 26.798706] [IGT] kms_vblank: executing <14>[ 26.799561] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.804790] device: /dev/dri/card0 No KMS driver or no outp<14>[ 26.818514] [IGT] kms_vblank: executing <14>[ 26.819006] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.826026] uts, pipes: 8, outputs: 0 Subtest pipe-D-query-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<14>[ 26.847774] [IGT] kms_vblank: executing <14>[ 26.848623] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.853837] 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-query-forked: SK<14>[ 26.874210] [IGT] kms_vblank: executing <14>[ 26.874988] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.879908] IP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 <14>[ 26.900835] [IGT] kms_vblank: executing <14>[ 26.901647] [IGT] kms_vblank: exiting, ret=77 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, <8>[ 26.916653] outputs: 0 Subtest pipe-D-query-forked-hang<14>[ 26.927928] [IGT] kms_vblank: executing <14>[ 26.928415] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.933966] : SKIP (0.000s) IGT-Version: 1.27.1-g621c2d<14>[ 26.947034] [IGT] kms_vblank: executing <14>[ 26.947512] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.954365] 3 (aarch64) (Linux: 6.1.59-cip8-<14>[ 26.968066] [IGT] kms_vblank: executing <14>[ 26.968557] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.975380] rt4 aarch64) Opened device: /de<14>[ 26.988107] [IGT] kms_vblank: executing <14>[ 26.988591] [IGT] kms_vblank: exiting, ret=77 <8>[ 26.994864] v/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-query-busy: SKIP (0.000s) IGT-Version: 1<14>[ 27.017568] [IGT] kms_vblank: executing .27.1-g621c2d3 (aarch64) (Linux:<14>[ 27.023948] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.028712] 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-query-busy-hang: SKIP (0.000s) IGT-Version:<14>[ 27.050685] [IGT] kms_vblank: executing <14>[ 27.051582] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.056571] 1.27.1-g621c2d3 (aarch64) (Linu<14>[ 27.072440] [IGT] kms_vblank: executing <14>[ 27.072920] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.080244] x: 6.1.59-cip8-r<14>[ 27.093084] [IGT] kms_vblank: executing <14>[ 27.093553] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.097716] t4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-query-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621<14>[ 27.121898] [IGT] kms_vblank: executing <14>[ 27.122783] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.127719] c2d3 (aarch64) (<14>[ 27.144648] [IGT] kms_vblank: executing <14>[ 27.145146] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.152275] Linux: 6.1.59-cip8-rt4 aarch64) <14>[ 27.163919] [IGT] kms_vblank: executing <14>[ 27.164370] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.172982] Opened device: /dev/dri/card0 <14>[ 27.184498] [IGT] kms_vblank: executing <14>[ 27.184971] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.191639] No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-query-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 <14>[ 27.216192] [IGT] kms_vblank: executing <14>[ 27.217045] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.222101] aarch64) Opened device: /dev/dr<14>[ 27.235436] [IGT] kms_vblank: executing <14>[ 27.235924] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.239995] i/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-wait-idle: SKIP (0.000s) IGT-Version: 1.27.1<14>[ 27.264466] [IGT] kms_vblank: executing <14>[ 27.265327] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.270585] -g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subt<14>[ 27.290573] [IGT] kms_vblank: executing est pipe-D-wait-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-wait-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-wait-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-wait-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-wait-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-wait-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-wait-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-ts-continuation-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-ts-continuation-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-ts-continuation-modeset: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-accuracy-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-query-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-query-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: <14>[ 27.628987] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.634146] 8, outputs: 0 Subtest pipe-<14>[ 27.644541] [IGT] kms_vblank: executing <14>[ 27.645001] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.649313] E-query-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/<14>[ 27.673329] [IGT] kms_vblank: executing dri/card0 No KMS driver or no outputs, pipes: 8<14>[ 27.678785] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.683353] , outputs: 0 Subtest pipe-E-query-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip<14>[ 27.704245] [IGT] kms_vblank: executing <14>[ 27.705044] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.710472] 8-rt4 aarch64) Opened device: /<14>[ 27.723216] [IGT] kms_vblank: executing <14>[ 27.723793] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.728256] dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-query-busy: SKIP (0.000s) IGT-Version:<14>[ 27.751217] [IGT] kms_vblank: executing <14>[ 27.752103] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.757506] 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-r<14>[ 27.770728] [IGT] kms_vblank: executing <14>[ 27.771279] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.775918] t4 aarch64) Opened device: /dev<14>[ 27.791622] [IGT] kms_vblank: executing <14>[ 27.792173] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.798910] /dri/card0 No KMS driver or no outputs, pipes: <14>[ 27.810819] [IGT] kms_vblank: executing <14>[ 27.811359] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.818390] 8, outputs: 0 Subtest pipe-<14>[ 27.831890] [IGT] kms_vblank: executing <14>[ 27.832393] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.839460] E-query-busy-hang: SKIP (0.000s) IGT-Versio<14>[ 27.850874] [IGT] kms_vblank: executing <14>[ 27.851375] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.855846] n: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes<14>[ 27.878416] [IGT] kms_vblank: executing <14>[ 27.879282] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.884617] : 8, outputs: 0 Subtest pip<14>[ 27.899855] [IGT] kms_vblank: executing <14>[ 27.900345] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.904503] e-E-query-forked-busy: SKIP (0.0<14>[ 27.919721] [IGT] kms_vblank: executing <14>[ 27.920196] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.926862] 00s) IGT-Version: 1.27.1-g6<14>[ 27.939685] [IGT] kms_vblank: executing <14>[ 27.940174] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.944406] 21c2d3 (aarch64) (Linux: 6.1.59-<14>[ 27.960086] [IGT] kms_vblank: executing <14>[ 27.960559] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.967328] cip8-rt4 aarch64) Opened device<14>[ 27.980409] [IGT] kms_vblank: executing <14>[ 27.980910] [IGT] kms_vblank: exiting, ret=77 <8>[ 27.989447] : /dev/dri/card0<14>[ 28.001061] [IGT] kms_vblank: executing <14>[ 28.001532] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.010178] No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-query-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt<14>[ 28.033726] [IGT] kms_vblank: executing 4 aarch64) Opened device: /dev/<14>[ 28.040004] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.045056] dri/card0 No KMS driver or no o<14>[ 28.055573] [IGT] kms_vblank: executing utputs, pipes: 8<14>[ 28.056044] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.062531] , outputs: 0 [<14>[ 28.077511] [IGT] kms_vblank: executing 1mSubtest pipe-E-wait-idle: SKIP (0.000s) I<14>[ 28.083424] [IGT] kms_vblank: exiting, ret=77 GT-Version: 1.27<8>[ 28.087635] .1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Su<14>[ 28.110066] [IGT] kms_vblank: executing btest pipe-E-wai<14>[ 28.110906] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.116271] t-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 28.135310] [IGT] kms_vblank: executing <14>[ 28.136126] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.141432] rch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened <14>[ 28.154534] [IGT] kms_vblank: executing <14>[ 28.155004] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.161016] device: /dev/dri/card0 No KMS d<14>[ 28.175465] [IGT] kms_vblank: executing river or no outp<14>[ 28.175950] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.179940] uts, pipes: 8, outputs: 0 S<14>[ 28.196123] [IGT] kms_vblank: executing ubtest pipe-E-wa<14>[ 28.196604] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.200832] it-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened de<14>[ 28.223257] [IGT] kms_vblank: executing <14>[ 28.224124] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.229497] vice: /dev/dri/card0 No KMS driver or no output<14>[ 28.243183] [IGT] kms_vblank: executing s, pipes: 8, outputs: 0 Subtest pipe-E-wait-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-wait-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-wait-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-wait-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-wait-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-ts-continuation-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-ts-continuation-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-ts-continuation-modeset: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-accuracy-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-query-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-query-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-query-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-query-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device:<14>[ 28.581277] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.585798] /dev/dri/card0 No KMS driver or no outputs, pi<14>[ 28.596751] [IGT] kms_vblank: executing pes: 8, outputs:<14>[ 28.597236] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.601286] 0 Subtest pipe-F-query-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8<14>[ 28.623759] [IGT] kms_vblank: executing <14>[ 28.624643] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.630054] -rt4 aarch64) Opened device: /d<14>[ 28.644293] [IGT] kms_vblank: executing <14>[ 28.644805] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.651422] ev/dri/card0 No KMS driver or n<14>[ 28.663299] [IGT] kms_vblank: executing o outputs, pipes<14>[ 28.663813] [IGT] kms_vblank: exiting, ret=77 : 8, outputs: 0 <8>[ 28.668140] Subtest pipe-F-query-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-ci<14>[ 28.693127] [IGT] kms_vblank: executing p8-rt4 aarch64) Opened device: <14>[ 28.699495] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.704559] /dev/dri/card0 No KMS driver or no outputs, pip<14>[ 28.715884] [IGT] kms_vblank: executing <14>[ 28.716398] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.722925] es: 8, outputs: 0 Subtest p<14>[ 28.735331] [IGT] kms_vblank: executing <14>[ 28.735839] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.742670] ipe-F-query-forked-busy: SKIP (0.000s) IGT-<14>[ 28.754366] [IGT] kms_vblank: executing <14>[ 28.754892] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.761878] Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.5<14>[ 28.775185] [IGT] kms_vblank: executing <14>[ 28.775671] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.782470] 9-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subte<14>[ 28.804541] [IGT] kms_vblank: executing <14>[ 28.805430] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.810681] st pipe-F-query-forked-busy-hang<14>[ 28.823185] [IGT] kms_vblank: executing : SKIP (0.000s)<14>[ 28.823666] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.827946] [0m IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No <14>[ 28.850769] [IGT] kms_vblank: executing <14>[ 28.851682] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.856908] KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-wait-idle: SK<14>[ 28.876252] [IGT] kms_vblank: executing <14>[ 28.877112] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.882423] IP (0.000s) IGT-Version: 1.<14>[ 28.896335] [IGT] kms_vblank: executing <14>[ 28.896814] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.903397] 27.1-g621c2d3 (a<14>[ 28.916989] [IGT] kms_vblank: executing <14>[ 28.917478] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.921717] arch64) (Linux: 6.1.59-cip8-rt4 <14>[ 28.935844] [IGT] kms_vblank: executing <14>[ 28.936328] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.940750] aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-wait-idle-hang: S<14>[ 28.963248] [IGT] kms_vblank: executing <14>[ 28.964113] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.969290] KIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<14>[ 28.988325] [IGT] kms_vblank: executing <14>[ 28.989165] [IGT] kms_vblank: exiting, ret=77 <8>[ 28.994451] 6.1.59-cip8-rt4 aarch64) Opene<14>[ 29.008386] [IGT] kms_vblank: executing <14>[ 29.008841] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.015979] d device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-wait-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 29.038544] [IGT] kms_vblank: executing <14>[ 29.039279] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.045036] .1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outp<14>[ 29.065416] [IGT] kms_vblank: executing uts, pipes: 8, outputs: 0 Subtest pipe-F-wa<14>[ 29.070779] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.077542] it-forked-hang: SKIP (0.000s)[0<14>[ 29.087991] [IGT] kms_vblank: executing <14>[ 29.088441] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.093282] m IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8<14>[ 29.115166] [IGT] kms_vblank: executing <14>[ 29.115909] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.121173] , outputs: 0 Subtest pipe-F<14>[ 29.135912] [IGT] kms_vblank: executing <14>[ 29.136392] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.140443] -wait-busy: SKIP (0.000s) IGT-Version: 1.27<14>[ 29.155043] [IGT] kms_vblank: executing <14>[ 29.155511] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.161653] .1-g621c2d3 (aarch64) (Linux: 6.<14>[ 29.176039] [IGT] kms_vblank: executing <14>[ 29.176530] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.180588] 1.59-cip8-rt4 aarch64) Opened d<14>[ 29.195751] [IGT] kms_vblank: executing evice: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-wait-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-wait-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-wait-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-ts-continuation-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-ts-continuation-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-ts-continuation-modeset: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-accuracy-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-query-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-query-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-query-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-query-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-query-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-query-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0<14>[ 29.533959] [IGT] kms_vblank: exiting, ret=77 No KMS driver <8>[ 29.538694] or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-query-forked-busy: SKIP (0.000s) IGT-Version: 1.27.<14>[ 29.561176] [IGT] kms_vblank: executing 1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aar<14>[ 29.567401] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.572400] ch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-query-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) <14>[ 29.599734] [IGT] kms_vblank: executing <14>[ 29.600589] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.606604] Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-wait-idle: SKIP (0.000s)[0<14>[ 29.629271] [IGT] kms_vblank: executing m IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux<14>[ 29.635116] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.640477] : 6.1.59-cip8-rt4 aarch64) Open<14>[ 29.653372] [IGT] kms_vblank: executing ed device: /dev/dri/card0 No KMS driver or no o<14>[ 29.658288] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.662832] utputs, pipes: 8, outputs: 0 Subtest pipe-G<14>[ 29.675130] [IGT] kms_vblank: executing <14>[ 29.675689] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.682834] -wait-idle-hang: SKIP (0.000s)[<14>[ 29.695605] [IGT] kms_vblank: executing <14>[ 29.696159] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.703361] 0m IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-<14>[ 29.726601] [IGT] kms_vblank: executing <14>[ 29.727440] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.733039] G-wait-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<14>[ 29.752768] [IGT] kms_vblank: executing <14>[ 29.753628] [IGT] kms_vblank: exiting, ret=77 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-<8>[ 29.770212] wait-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 <14>[ 29.796171] [IGT] kms_vblank: executing Subtest pipe<14>[ 29.796984] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.803253] -G-wait-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (a<14>[ 29.817883] [IGT] kms_vblank: executing <14>[ 29.818469] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.823056] arch64) (Linux: <14>[ 29.841056] [IGT] kms_vblank: executing <14>[ 29.841606] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.847795] 6.1.59-cip8-rt4 aarch64) Opened<14>[ 29.859966] [IGT] kms_vblank: executing <14>[ 29.860551] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.865283] device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-wait-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (<14>[ 29.889855] [IGT] kms_vblank: executing <14>[ 29.890723] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.896097] aarch64) (Linux: 6.1.59-cip8-rt4<14>[ 29.911983] [IGT] kms_vblank: executing <14>[ 29.912544] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.917179] aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-wait-forked-busy<14>[ 29.939779] [IGT] kms_vblank: executing <14>[ 29.940658] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.946079] : SKIP (0.000s)<14>[ 29.961173] [IGT] kms_vblank: executing <14>[ 29.961719] [IGT] kms_vblank: exiting, ret=77 [0m IGT-Version: 1.27.1-g621c2d<8>[ 29.972389] 3 (aarch64) (Linux: 6.1.59-cip8-<14>[ 29.983636] [IGT] kms_vblank: executing <14>[ 29.984177] [IGT] kms_vblank: exiting, ret=77 <8>[ 29.989065] rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-wait-forked-busy-hang: SKIP (<14>[ 30.013210] [IGT] kms_vblank: executing 0.000s) IGT-Version: 1.27.1<14>[ 30.019533] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.024727] -g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarc<14>[ 30.036390] [IGT] kms_vblank: executing <14>[ 30.036883] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.043834] h64) Opened device: /dev/dri/card0 No KMS driv<14>[ 30.055090] [IGT] kms_vblank: executing <14>[ 30.055594] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.059978] er or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-ts-continuation-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Ope<14>[ 30.087625] [IGT] kms_vblank: executing <14>[ 30.088438] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.093411] ned device: /dev/dri/card0 No K<14>[ 30.107984] [IGT] kms_vblank: executing <14>[ 30.108459] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.112844] MS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s) IGT-Version: 1.2<14>[ 30.135725] [IGT] kms_vblank: executing <14>[ 30.136616] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.141551] 7.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS d<14>[ 30.160932] [IGT] kms_vblank: executing <14>[ 30.161972] [IGT] kms_vblank: exiting, ret=77 river or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g<8>[ 30.178717] 621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch6<14>[ 30.191395] [IGT] kms_vblank: executing <14>[ 30.191902] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.197479] 4) Opened devic<14>[ 30.212952] [IGT] kms_vblank: executing <14>[ 30.213461] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.218328] e: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s) IGT-Ve<14>[ 30.240282] [IGT] kms_vblank: executing <14>[ 30.241095] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.246299] rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, p<14>[ 30.266278] [IGT] kms_vblank: executing <14>[ 30.267017] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.272047] ipes: 8, outputs: 0 Subtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[<14>[ 30.292299] [IGT] kms_vblank: executing <14>[ 30.293103] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.298926] 0m IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<14>[ 30.310980] [IGT] kms_vblank: executing <14>[ 30.311451] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.318260] x: 6.1.59-cip8-rt4 aarch64) Ope<14>[ 30.331403] [IGT] kms_vblank: executing <14>[ 30.331877] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.338590] ned device: /dev/dri/card0 No KMS driver or no <14>[ 30.350841] [IGT] kms_vblank: executing <14>[ 30.351329] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.357760] outputs, pipes: 8, outputs: 0 <14>[ 30.371848] [IGT] kms_vblank: executing <14>[ 30.372316] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.378879] [1mSubtest pipe-G-ts-continuatio<14>[ 30.391927] [IGT] kms_vblank: executing n-modeset: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-accuracy-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-query-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-query-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-query-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-query-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-query-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-query-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-query-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-query-forked-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-wait-idle: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-wait-idle-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-wait-forked: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-wait-forked-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-wait-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-wait-busy-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-wait-forked-busy: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip<14>[ 30.730165] [IGT] kms_vblank: exiting, ret=77 8-rt4 aarch64) <8>[ 30.734742] Opened device: /<14>[ 30.749353] [IGT] kms_vblank: executing dev/dri/card0 No KMS driver or no outputs, pipe<14>[ 30.754928] [IGT] kms_vblank: exiting, ret=77 s: 8, outputs: 0<8>[ 30.761288] Subtest pipe-H-wait-forked-busy-hang: SKIP<14>[ 30.774011] [IGT] kms_vblank: executing <14>[ 30.774492] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.783266] (0.000s) IGT-Version: 1.27<14>[ 30.795696] [IGT] kms_vblank: executing <14>[ 30.796239] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.802073] .1-g621c2d3 (aarch64) (Linux: 6.<14>[ 30.816393] [IGT] kms_vblank: executing <14>[ 30.816933] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.823292] 1.59-cip8-rt4 aa<14>[ 30.836623] [IGT] kms_vblank: executing <14>[ 30.837158] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.843222] rch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-ts-continuation-idl<14>[ 30.865360] [IGT] kms_vblank: executing e: SKIP (0.000s) IGT-Version: 1.27.1-g621c2<14>[ 30.871246] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.876177] d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-ts-continuat<14>[ 30.898999] [IGT] kms_vblank: executing <14>[ 30.899861] [IGT] kms_vblank: exiting, ret=77 <8>[ 30.905591] <8>[ 30.907087] ion-idle-hang: SKIP (0.000s)<8>[ 30.924361] IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-ts-continuation-suspend: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-ts-continuation-modeset: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s) IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.59-cip8-rt4 aarch64) Opened device: /dev/dri/card0 No KMS driver or no outputs, pipes: 8, outputs: 0 Subtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s) + set +x / #